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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
123 #ifndef CHECK_STACK_LIMIT
124 #define CHECK_STACK_LIMIT (-1)
125 #endif
127 /* Return index of given mode in mult and division cost tables. */
128 #define MODE_INDEX(mode) \
129 ((mode) == QImode ? 0 \
130 : (mode) == HImode ? 1 \
131 : (mode) == SImode ? 2 \
132 : (mode) == DImode ? 3 \
133 : 4)
135 /* Processor costs (relative to an add) */
136 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
137 #define COSTS_N_BYTES(N) ((N) * 2)
139 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
148 const
171 in QImode, HImode and SImode.
172 Relative to reg-reg move (2). */
176 in SFmode, DFmode and XFmode */
178 in SFmode, DFmode and XFmode */
181 in SImode and DImode */
183 in SImode and DImode */
186 in SImode, DImode and TImode */
188 in SImode, DImode and TImode */
201 ix86_size_memcpy,
202 ix86_size_memset,
214 };
216 /* Processor costs (relative to an add) */
219 DUMMY_STRINGOP_ALGS};
222 DUMMY_STRINGOP_ALGS};
224 static const
247 in QImode, HImode and SImode.
248 Relative to reg-reg move (2). */
252 in SFmode, DFmode and XFmode */
254 in SFmode, DFmode and XFmode */
257 in SImode and DImode */
259 in SImode and DImode */
262 in SImode, DImode and TImode */
264 in SImode, DImode and TImode */
277 i386_memcpy,
278 i386_memset,
290 };
294 DUMMY_STRINGOP_ALGS};
297 DUMMY_STRINGOP_ALGS};
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
342 shared for code and data, so 4kB is
343 not really precise. */
354 i486_memcpy,
355 i486_memset,
367 };
371 DUMMY_STRINGOP_ALGS};
374 DUMMY_STRINGOP_ALGS};
376 static const
399 in QImode, HImode and SImode.
400 Relative to reg-reg move (2). */
404 in SFmode, DFmode and XFmode */
406 in SFmode, DFmode and XFmode */
409 in SImode and DImode */
411 in SImode and DImode */
414 in SImode, DImode and TImode */
416 in SImode, DImode and TImode */
429 pentium_memcpy,
430 pentium_memset,
442 };
444 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
445 (we ensure the alignment). For small blocks inline loop is still a
446 noticeable win, for bigger blocks either rep movsl or rep movsb is
447 way to go. Rep movsb has apparently more expensive startup time in CPU,
448 but after 4K the difference is down in the noise. */
453 DUMMY_STRINGOP_ALGS};
458 DUMMY_STRINGOP_ALGS};
459 static const
482 in QImode, HImode and SImode.
483 Relative to reg-reg move (2). */
487 in SFmode, DFmode and XFmode */
489 in SFmode, DFmode and XFmode */
492 in SImode and DImode */
494 in SImode and DImode */
497 in SImode, DImode and TImode */
499 in SImode, DImode and TImode */
512 pentiumpro_memcpy,
513 pentiumpro_memset,
525 };
529 DUMMY_STRINGOP_ALGS};
532 DUMMY_STRINGOP_ALGS};
533 static const
556 in QImode, HImode and SImode.
557 Relative to reg-reg move (2). */
561 in SFmode, DFmode and XFmode */
563 in SFmode, DFmode and XFmode */
567 in SImode and DImode */
569 in SImode and DImode */
572 in SImode, DImode and TImode */
574 in SImode, DImode and TImode */
587 geode_memcpy,
588 geode_memset,
600 };
604 DUMMY_STRINGOP_ALGS};
607 DUMMY_STRINGOP_ALGS};
608 static const
631 in QImode, HImode and SImode.
632 Relative to reg-reg move (2). */
636 in SFmode, DFmode and XFmode */
638 in SFmode, DFmode and XFmode */
641 in SImode and DImode */
643 in SImode and DImode */
646 in SImode, DImode and TImode */
648 in SImode, DImode and TImode */
652 have integrated l2 cache, but
653 optimizing for k6 is not important
654 enough to worry about that. */
664 k6_memcpy,
665 k6_memset,
677 };
679 /* For some reason, Athlon deals better with REP prefix (relative to loops)
680 compared to K8. Alignment becomes important after 8 bytes for memcpy and
681 128 bytes for memset. */
684 DUMMY_STRINGOP_ALGS};
687 DUMMY_STRINGOP_ALGS};
688 static const
711 in QImode, HImode and SImode.
712 Relative to reg-reg move (2). */
716 in SFmode, DFmode and XFmode */
718 in SFmode, DFmode and XFmode */
721 in SImode and DImode */
723 in SImode and DImode */
726 in SImode, DImode and TImode */
728 in SImode, DImode and TImode */
741 athlon_memcpy,
742 athlon_memset,
754 };
756 /* K8 has optimized REP instruction for medium sized blocks, but for very
757 small blocks it is better to use loop. For large blocks, libcall can
758 do nontemporary accesses and beat inline considerably. */
769 static const
792 in QImode, HImode and SImode.
793 Relative to reg-reg move (2). */
797 in SFmode, DFmode and XFmode */
799 in SFmode, DFmode and XFmode */
802 in SImode and DImode */
804 in SImode and DImode */
807 in SImode, DImode and TImode */
809 in SImode, DImode and TImode */
814 /* New AMD processors never drop prefetches; if they cannot be performed
815 immediately, they are queued. We set number of simultaneous prefetches
816 to a large constant to reflect this (it probably is not a good idea not
817 to limit number of prefetches at all, as their execution also takes some
818 time). */
828 k8_memcpy,
829 k8_memset,
841 };
843 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
844 very small blocks it is better to use loop. For large blocks, libcall can
845 do nontemporary accesses and beat inline considerably. */
878 in QImode, HImode and SImode.
879 Relative to reg-reg move (2). */
883 in SFmode, DFmode and XFmode */
885 in SFmode, DFmode and XFmode */
888 in SImode and DImode */
890 in SImode and DImode */
893 in SImode, DImode and TImode */
895 in SImode, DImode and TImode */
897 /* On K8:
898 MOVD reg64, xmmreg Double FSTORE 4
899 MOVD reg32, xmmreg Double FSTORE 4
900 On AMDFAM10:
901 MOVD reg64, xmmreg Double FADD 3
902 1/1 1/1
903 MOVD reg32, xmmreg Double FADD 3
904 1/1 1/1 */
908 /* New AMD processors never drop prefetches; if they cannot be performed
909 immediately, they are queued. We set number of simultaneous prefetches
910 to a large constant to reflect this (it probably is not a good idea not
911 to limit number of prefetches at all, as their execution also takes some
912 time). */
922 amdfam10_memcpy,
923 amdfam10_memset,
935 };
937 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
938 very small blocks it is better to use loop. For large blocks, libcall
939 can do nontemporary accesses and beat inline considerably. */
973 in QImode, HImode and SImode.
974 Relative to reg-reg move (2). */
978 in SFmode, DFmode and XFmode */
980 in SFmode, DFmode and XFmode */
983 in SImode and DImode */
985 in SImode and DImode */
988 in SImode, DImode and TImode */
990 in SImode, DImode and TImode */
992 /* On K8:
993 MOVD reg64, xmmreg Double FSTORE 4
994 MOVD reg32, xmmreg Double FSTORE 4
995 On AMDFAM10:
996 MOVD reg64, xmmreg Double FADD 3
997 1/1 1/1
998 MOVD reg32, xmmreg Double FADD 3
999 1/1 1/1 */
1003 /* New AMD processors never drop prefetches; if they cannot be performed
1004 immediately, they are queued. We set number of simultaneous prefetches
1005 to a large constant to reflect this (it probably is not a good idea not
1006 to limit number of prefetches at all, as their execution also takes some
1007 time). */
1017 bdver1_memcpy,
1018 bdver1_memset,
1030 };
1032 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1033 very small blocks it is better to use loop. For large blocks, libcall
1034 can do nontemporary accesses and beat inline considerably. */
1069 in QImode, HImode and SImode.
1070 Relative to reg-reg move (2). */
1074 in SFmode, DFmode and XFmode */
1076 in SFmode, DFmode and XFmode */
1079 in SImode and DImode */
1081 in SImode and DImode */
1084 in SImode, DImode and TImode */
1086 in SImode, DImode and TImode */
1088 /* On K8:
1089 MOVD reg64, xmmreg Double FSTORE 4
1090 MOVD reg32, xmmreg Double FSTORE 4
1091 On AMDFAM10:
1092 MOVD reg64, xmmreg Double FADD 3
1093 1/1 1/1
1094 MOVD reg32, xmmreg Double FADD 3
1095 1/1 1/1 */
1099 /* New AMD processors never drop prefetches; if they cannot be performed
1100 immediately, they are queued. We set number of simultaneous prefetches
1101 to a large constant to reflect this (it probably is not a good idea not
1102 to limit number of prefetches at all, as their execution also takes some
1103 time). */
1113 bdver2_memcpy,
1114 bdver2_memset,
1126 };
1129 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1130 very small blocks it is better to use loop. For large blocks, libcall
1131 can do nontemporary accesses and beat inline considerably. */
1164 in QImode, HImode and SImode.
1165 Relative to reg-reg move (2). */
1169 in SFmode, DFmode and XFmode */
1171 in SFmode, DFmode and XFmode */
1174 in SImode and DImode */
1176 in SImode and DImode */
1179 in SImode, DImode and TImode */
1181 in SImode, DImode and TImode */
1186 /* New AMD processors never drop prefetches; if they cannot be performed
1187 immediately, they are queued. We set number of simultaneous prefetches
1188 to a large constant to reflect this (it probably is not a good idea not
1189 to limit number of prefetches at all, as their execution also takes some
1190 time). */
1200 bdver3_memcpy,
1201 bdver3_memset,
1213 };
1215 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1216 very small blocks it is better to use loop. For large blocks, libcall
1217 can do nontemporary accesses and beat inline considerably. */
1250 in QImode, HImode and SImode.
1251 Relative to reg-reg move (2). */
1255 in SFmode, DFmode and XFmode */
1257 in SFmode, DFmode and XFmode */
1260 in SImode and DImode */
1262 in SImode and DImode */
1265 in SImode, DImode and TImode */
1267 in SImode, DImode and TImode */
1272 /* New AMD processors never drop prefetches; if they cannot be performed
1273 immediately, they are queued. We set number of simultaneous prefetches
1274 to a large constant to reflect this (it probably is not a good idea not
1275 to limit number of prefetches at all, as their execution also takes some
1276 time). */
1286 bdver4_memcpy,
1287 bdver4_memset,
1299 };
1301 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1302 very small blocks it is better to use loop. For large blocks, libcall can
1303 do nontemporary accesses and beat inline considerably. */
1336 in QImode, HImode and SImode.
1337 Relative to reg-reg move (2). */
1341 in SFmode, DFmode and XFmode */
1343 in SFmode, DFmode and XFmode */
1346 in SImode and DImode */
1348 in SImode and DImode */
1351 in SImode, DImode and TImode */
1353 in SImode, DImode and TImode */
1355 /* On K8:
1356 MOVD reg64, xmmreg Double FSTORE 4
1357 MOVD reg32, xmmreg Double FSTORE 4
1358 On AMDFAM10:
1359 MOVD reg64, xmmreg Double FADD 3
1360 1/1 1/1
1361 MOVD reg32, xmmreg Double FADD 3
1362 1/1 1/1 */
1375 btver1_memcpy,
1376 btver1_memset,
1388 };
1422 in QImode, HImode and SImode.
1423 Relative to reg-reg move (2). */
1427 in SFmode, DFmode and XFmode */
1429 in SFmode, DFmode and XFmode */
1432 in SImode and DImode */
1434 in SImode and DImode */
1437 in SImode, DImode and TImode */
1439 in SImode, DImode and TImode */
1441 /* On K8:
1442 MOVD reg64, xmmreg Double FSTORE 4
1443 MOVD reg32, xmmreg Double FSTORE 4
1444 On AMDFAM10:
1445 MOVD reg64, xmmreg Double FADD 3
1446 1/1 1/1
1447 MOVD reg32, xmmreg Double FADD 3
1448 1/1 1/1 */
1460 btver2_memcpy,
1461 btver2_memset,
1473 };
1477 DUMMY_STRINGOP_ALGS};
1481 DUMMY_STRINGOP_ALGS};
1483 static const
1506 in QImode, HImode and SImode.
1507 Relative to reg-reg move (2). */
1511 in SFmode, DFmode and XFmode */
1513 in SFmode, DFmode and XFmode */
1516 in SImode and DImode */
1518 in SImode and DImode */
1521 in SImode, DImode and TImode */
1523 in SImode, DImode and TImode */
1536 pentium4_memcpy,
1537 pentium4_memset,
1549 };
1562 static const
1585 in QImode, HImode and SImode.
1586 Relative to reg-reg move (2). */
1590 in SFmode, DFmode and XFmode */
1592 in SFmode, DFmode and XFmode */
1595 in SImode and DImode */
1597 in SImode and DImode */
1600 in SImode, DImode and TImode */
1602 in SImode, DImode and TImode */
1615 nocona_memcpy,
1616 nocona_memset,
1628 };
1639 static const
1662 in QImode, HImode and SImode.
1663 Relative to reg-reg move (2). */
1667 in SFmode, DFmode and XFmode */
1669 in SFmode, DFmode and XFmode */
1672 in SImode and DImode */
1674 in SImode and DImode */
1677 in SImode, DImode and TImode */
1679 in SImode, DImode and TImode */
1692 atom_memcpy,
1693 atom_memset,
1705 };
1716 static const
1739 in QImode, HImode and SImode.
1740 Relative to reg-reg move (2). */
1744 in SFmode, DFmode and XFmode */
1746 in SFmode, DFmode and XFmode */
1749 in SImode and DImode */
1751 in SImode and DImode */
1754 in SImode, DImode and TImode */
1756 in SImode, DImode and TImode */
1769 slm_memcpy,
1770 slm_memset,
1782 };
1793 static const
1816 in QImode, HImode and SImode.
1817 Relative to reg-reg move (2). */
1821 in SFmode, DFmode and XFmode */
1823 in SFmode, DFmode and XFmode */
1826 in SImode and DImode */
1828 in SImode and DImode */
1831 in SImode, DImode and TImode */
1833 in SImode, DImode and TImode */
1846 intel_memcpy,
1847 intel_memset,
1859 };
1861 /* Generic should produce code tuned for Core-i7 (and newer chips)
1862 and btver1 (and newer chips). */
1874 static const
1877 /* On all chips taken into consideration lea is 2 cycles and more. With
1878 this cost however our current implementation of synth_mult results in
1879 use of unnecessary temporary registers causing regression on several
1880 SPECfp benchmarks. */
1901 in QImode, HImode and SImode.
1902 Relative to reg-reg move (2). */
1906 in SFmode, DFmode and XFmode */
1908 in SFmode, DFmode and XFmode */
1911 in SImode and DImode */
1913 in SImode and DImode */
1916 in SImode, DImode and TImode */
1918 in SImode, DImode and TImode */
1924 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1925 value is increased to perhaps more appropriate value of 5. */
1933 generic_memcpy,
1934 generic_memset,
1946 };
1948 /* core_cost should produce code tuned for Core familly of CPUs. */
1961 static const
1964 /* On all chips taken into consideration lea is 2 cycles and more. With
1965 this cost however our current implementation of synth_mult results in
1966 use of unnecessary temporary registers causing regression on several
1967 SPECfp benchmarks. */
1988 in QImode, HImode and SImode.
1989 Relative to reg-reg move (2). */
1993 in SFmode, DFmode and XFmode */
1995 in SFmode, DFmode and XFmode */
1998 in SImode and DImode */
2000 in SImode and DImode */
2003 in SImode, DImode and TImode */
2005 in SImode, DImode and TImode */
2011 /* FIXME perhaps more appropriate value is 5. */
2019 core_memcpy,
2020 core_memset,
2032 };
2035 /* Set by -mtune. */
2038 /* Set by -mtune or -Os. */
2041 /* Processor feature/optimization bitmasks. */
2042 #define m_386 (1<<PROCESSOR_I386)
2043 #define m_486 (1<<PROCESSOR_I486)
2044 #define m_PENT (1<<PROCESSOR_PENTIUM)
2045 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2046 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2047 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2048 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2049 #define m_CORE2 (1<<PROCESSOR_CORE2)
2050 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2051 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2052 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2053 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2054 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2055 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2056 #define m_KNL (1<<PROCESSOR_KNL)
2057 #define m_INTEL (1<<PROCESSOR_INTEL)
2059 #define m_GEODE (1<<PROCESSOR_GEODE)
2060 #define m_K6 (1<<PROCESSOR_K6)
2061 #define m_K6_GEODE (m_K6 | m_GEODE)
2062 #define m_K8 (1<<PROCESSOR_K8)
2063 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2064 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2065 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2066 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2067 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2068 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2069 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2070 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2071 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2072 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2073 #define m_BTVER (m_BTVER1 | m_BTVER2)
2074 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2076 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2079 #undef DEF_TUNE
2080 #define DEF_TUNE(tune, name, selector) name,
2082 #undef DEF_TUNE
2083 };
2085 /* Feature tests against the various tunings. */
2088 /* Feature tests against the various tunings used to create ix86_tune_features
2089 based on the processor mask. */
2091 #undef DEF_TUNE
2092 #define DEF_TUNE(tune, name, selector) selector,
2094 #undef DEF_TUNE
2095 };
2097 /* Feature tests against the various architecture variations. */
2100 /* Feature tests against the various architecture variations, used to create
2101 ix86_arch_features based on the processor mask. */
2103 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2106 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2109 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2112 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2115 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2117 };
2119 /* In case the average insn count for single function invocation is
2120 lower than this constant, emit fast (but longer) prologue and
2121 epilogue code. */
2122 #define FAST_PROLOGUE_INSN_COUNT 20
2124 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2129 /* Array of the smallest class containing reg number REGNO, indexed by
2130 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2133 {
2134 /* ax, dx, cx, bx */
2136 /* si, di, bp, sp */
2138 /* FP registers */
2141 /* arg pointer */
2142 NON_Q_REGS,
2143 /* flags, fpsr, fpcr, frame */
2145 /* SSE registers */
2148 /* MMX registers */
2151 /* REX registers */
2154 /* SSE REX registers */
2157 /* AVX-512 SSE registers */
2162 /* Mask registers. */
2165 /* MPX bound registers */
2167 };
2169 /* The "default" register map used in 32bit mode. */
2172 {
2184 };
2186 /* The "default" register map used in 64bit mode. */
2189 {
2201 };
2203 /* Define the register numbers to be used in Dwarf debugging information.
2204 The SVR4 reference port C compiler uses the following register numbers
2205 in its Dwarf output code:
2206 0 for %eax (gcc regno = 0)
2207 1 for %ecx (gcc regno = 2)
2208 2 for %edx (gcc regno = 1)
2209 3 for %ebx (gcc regno = 3)
2210 4 for %esp (gcc regno = 7)
2211 5 for %ebp (gcc regno = 6)
2212 6 for %esi (gcc regno = 4)
2213 7 for %edi (gcc regno = 5)
2214 The following three DWARF register numbers are never generated by
2215 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2216 believes these numbers have these meanings.
2217 8 for %eip (no gcc equivalent)
2218 9 for %eflags (gcc regno = 17)
2219 10 for %trapno (no gcc equivalent)
2220 It is not at all clear how we should number the FP stack registers
2221 for the x86 architecture. If the version of SDB on x86/svr4 were
2222 a bit less brain dead with respect to floating-point then we would
2223 have a precedent to follow with respect to DWARF register numbers
2224 for x86 FP registers, but the SDB on x86/svr4 is so completely
2225 broken with respect to FP registers that it is hardly worth thinking
2226 of it as something to strive for compatibility with.
2227 The version of x86/svr4 SDB I have at the moment does (partially)
2228 seem to believe that DWARF register number 11 is associated with
2229 the x86 register %st(0), but that's about all. Higher DWARF
2230 register numbers don't seem to be associated with anything in
2231 particular, and even for DWARF regno 11, SDB only seems to under-
2232 stand that it should say that a variable lives in %st(0) (when
2233 asked via an `=' command) if we said it was in DWARF regno 11,
2234 but SDB still prints garbage when asked for the value of the
2235 variable in question (via a `/' command).
2236 (Also note that the labels SDB prints for various FP stack regs
2237 when doing an `x' command are all wrong.)
2238 Note that these problems generally don't affect the native SVR4
2239 C compiler because it doesn't allow the use of -O with -g and
2240 because when it is *not* optimizing, it allocates a memory
2241 location for each floating-point variable, and the memory
2242 location is what gets described in the DWARF AT_location
2243 attribute for the variable in question.
2244 Regardless of the severe mental illness of the x86/svr4 SDB, we
2245 do something sensible here and we use the following DWARF
2246 register numbers. Note that these are all stack-top-relative
2247 numbers.
2248 11 for %st(0) (gcc regno = 8)
2249 12 for %st(1) (gcc regno = 9)
2250 13 for %st(2) (gcc regno = 10)
2251 14 for %st(3) (gcc regno = 11)
2252 15 for %st(4) (gcc regno = 12)
2253 16 for %st(5) (gcc regno = 13)
2254 17 for %st(6) (gcc regno = 14)
2255 18 for %st(7) (gcc regno = 15)
2256 */
2258 {
2270 };
2272 /* Define parameter passing and return registers. */
2275 {
2277 };
2280 {
2282 };
2285 {
2287 };
2289 /* Additional registers that are clobbered by SYSV calls. */
2292 {
2297 };
2299 /* Define the structure for the machine field in struct function. */
2304 rtx rtl;
2306 };
2308 /* Structure describing stack frame layout.
2309 Stack grows downward:
2311 [arguments]
2312 <- ARG_POINTER
2313 saved pc
2315 saved static chain if ix86_static_chain_on_stack
2317 saved frame pointer if frame_pointer_needed
2318 <- HARD_FRAME_POINTER
2319 [saved regs]
2320 <- regs_save_offset
2321 [padding0]
2323 [saved SSE regs]
2324 <- sse_regs_save_offset
2325 [padding1] |
2326 | <- FRAME_POINTER
2327 [va_arg registers] |
2328 |
2329 [frame] |
2330 |
2331 [padding2] | = to_allocate
2332 <- STACK_POINTER
2333 */
2334 struct ix86_frame
2335 {
2342 /* The offsets relative to ARG_POINTER. */
2343 HOST_WIDE_INT frame_pointer_offset;
2344 HOST_WIDE_INT hard_frame_pointer_offset;
2345 HOST_WIDE_INT stack_pointer_offset;
2346 HOST_WIDE_INT hfp_save_offset;
2347 HOST_WIDE_INT reg_save_offset;
2348 HOST_WIDE_INT sse_reg_save_offset;
2350 /* When save_regs_using_mov is set, emit prologue using
2351 move instead of push instructions. */
2353 };
2355 /* Which cpu are we scheduling for. */
2358 /* Which cpu are we optimizing for. */
2361 /* Which instruction set architecture to use. */
2364 /* True if processor has SSE prefetch instruction. */
2367 /* -mstackrealign option */
2384 /* Preferred alignment for stack boundary in bits. */
2387 /* Alignment for incoming stack boundary in bits specified at
2388 command line. */
2391 /* Default alignment for incoming stack boundary in bits. */
2394 /* Alignment for incoming stack boundary in bits. */
2397 /* Calling abi specific va_list type nodes. */
2401 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2405 /* Fence to use after loop using movnt. */
2406 tree x86_mfence;
2408 /* Register class used for passing given 64bit part of the argument.
2409 These represent classes as documented by the PS ABI, with the exception
2410 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2411 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2413 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2414 whenever possible (upper half does contain padding). */
2415 enum x86_64_reg_class
2416 {
2417 X86_64_NO_CLASS,
2418 X86_64_INTEGER_CLASS,
2419 X86_64_INTEGERSI_CLASS,
2420 X86_64_SSE_CLASS,
2421 X86_64_SSESF_CLASS,
2422 X86_64_SSEDF_CLASS,
2423 X86_64_SSEUP_CLASS,
2424 X86_64_X87_CLASS,
2425 X86_64_X87UP_CLASS,
2426 X86_64_COMPLEX_X87_CLASS,
2427 X86_64_MEMORY_CLASS
2428 };
2430 #define MAX_CLASSES 8
2432 /* Table of constants used by fldpi, fldln2, etc.... */
2436 \f
2441 const_tree);
2453 enum ix86_function_specific_strings
2454 {
2455 IX86_FUNCTION_SPECIFIC_ARCH,
2456 IX86_FUNCTION_SPECIFIC_TUNE,
2457 IX86_FUNCTION_SPECIFIC_MAX
2458 };
2480 \f
2481 #ifndef SUBTARGET32_DEFAULT_CPU
2483 #endif
2485 /* Whether -mtune= or -march= were specified */
2489 /* Vectorization library interface and handlers. */
2495 /* Processor target table, indexed by processor number */
2496 struct ptt
2497 {
2505 };
2507 /* This table must be in sync with enum processor_type in i386.h. */
2509 {
2536 };
2537 \f
2538 static unsigned int
2540 {
2543 /* vzeroupper instructions are inserted immediately after reload to
2544 account for possible spills from 256bit registers. The pass
2545 reuses mode switching infrastructure by re-running mode insertion
2546 pass, so disable entities that have already been processed. */
2552 /* Call optimize_mode_switching. */
2555 }
2560 {
2570 };
2573 {
2577 {}
2579 /* opt_pass methods: */
2581 {
2585 }
2588 {
2590 }
2596 rtl_opt_pass *
2598 {
2600 }
2602 /* Return true if a red-zone is in use. */
2606 {
2608 }
2609 \f
2610 /* Return a string that documents the current -m options. The caller is
2611 responsible for freeing the string. */
2617 {
2618 struct ix86_target_opts
2619 {
2622 };
2624 /* This table is ordered so that options like -msse4.2 that imply
2625 preceding options while match those first. */
2627 {
2680 };
2682 /* Flag options. */
2684 {
2713 };
2730 /* Add -march= option. */
2732 {
2735 }
2737 /* Add -mtune= option. */
2739 {
2742 }
2744 /* Add -m32/-m64/-mx32. */
2746 {
2749 else
2751 isa &= ~ (OPTION_MASK_ISA_64BIT
2752 | OPTION_MASK_ABI_64
2754 }
2755 else
2759 /* Pick out the options in isa options. */
2761 {
2763 {
2766 }
2767 }
2770 {
2773 isa);
2774 }
2776 /* Add flag options. */
2778 {
2780 {
2783 }
2784 }
2787 {
2790 }
2792 /* Add -fpmath= option. */
2794 {
2797 {
2812 }
2813 }
2815 /* Any options? */
2821 /* Size the string. */
2825 {
2830 }
2832 /* Build the string. */
2837 {
2844 {
2846 line_len++;
2849 {
2853 }
2854 }
2858 {
2862 }
2863 }
2869 }
2871 /* Return true, if profiling code should be emitted before
2872 prologue. Otherwise it returns false.
2873 Note: For x86 with "hotfix" it is sorried. */
2874 static bool
2876 {
2878 }
2880 /* Function that is callable from the debugger to print the current
2881 options. */
2882 void ATTRIBUTE_UNUSED
2884 {
2890 {
2893 }
2894 else
2898 }
2901 #define DEF_ENUM
2902 #define DEF_ALG(alg, name) #name,
2904 #undef DEF_ENUM
2905 #undef DEF_ALG
2906 };
2908 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2909 The string is of the following form (or comma separated list of it):
2911 strategy_alg:max_size:[align|noalign]
2913 where the full size range for the strategy is either [0, max_size] or
2914 [min_size, max_size], in which min_size is the max_size + 1 of the
2915 preceding range. The last size range must have max_size == -1.
2917 Examples:
2919 1.
2920 -mmemcpy-strategy=libcall:-1:noalign
2922 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2925 2.
2926 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2928 This is to tell the compiler to use the following strategy for memset
2929 1) when the expected size is between [1, 16], use rep_8byte strategy;
2930 2) when the size is between [17, 2048], use vector_loop;
2931 3) when the size is > 2048, use libcall. */
2933 struct stringop_size_range
2934 {
2936 stringop_alg alg;
2938 };
2940 static void
2942 {
2950 else
2955 do
2956 {
2966 {
2970 }
2973 {
2977 }
2984 {
2986 alg_name,
2989 }
2997 else
2998 {
3002 }
3003 n++;
3005 }
3009 {
3014 }
3017 {
3021 }
3023 /* Now override the default algs array. */
3025 {
3031 }
3032 }
3034 \f
3035 /* parse -mtune-ctrl= option. When DUMP is true,
3036 print the features that are explicitly set. */
3038 static void
3040 {
3048 do
3049 {
3056 {
3057 curr_feature_string++;
3059 }
3061 {
3063 {
3069 }
3070 }
3075 }
3078 }
3080 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3081 processor type. */
3083 static void
3085 {
3090 {
3093 else
3095 }
3098 {
3103 }
3106 }
3109 /* Override various settings based on options. If MAIN_ARGS_P, the
3110 options are from the command line, otherwise they are from
3111 attributes. */
3113 static void
3117 {
3125 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3126 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3127 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3128 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3129 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3130 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3131 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3132 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3133 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3134 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3135 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3136 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3137 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3138 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3139 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3140 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3141 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3142 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3143 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3144 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3145 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3146 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3147 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3148 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3149 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3150 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3151 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3152 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3153 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3154 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3155 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3156 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3157 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3158 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3159 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3160 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3161 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3162 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3163 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3164 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3165 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3166 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3167 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3168 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3169 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3170 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3171 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3172 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3173 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3174 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3175 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3176 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3177 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3178 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3179 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3180 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3181 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3183 #define PTA_CORE2 \
3184 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3185 | PTA_CX16 | PTA_FXSR)
3186 #define PTA_NEHALEM \
3187 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3188 #define PTA_WESTMERE \
3189 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3190 #define PTA_SANDYBRIDGE \
3191 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3192 #define PTA_IVYBRIDGE \
3193 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3194 #define PTA_HASWELL \
3195 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3196 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3197 #define PTA_BROADWELL \
3198 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3199 #define PTA_KNL \
3200 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3201 #define PTA_BONNELL \
3202 (PTA_CORE2 | PTA_MOVBE)
3203 #define PTA_SILVERMONT \
3204 (PTA_WESTMERE | PTA_MOVBE)
3206 /* if this reaches 64, need to widen struct pta flags below */
3208 static struct pta
3209 {
3214 }
3216 {
3250 PTA_SANDYBRIDGE},
3252 PTA_SANDYBRIDGE},
3254 PTA_IVYBRIDGE},
3256 PTA_IVYBRIDGE},
3348 PTA_64BIT
3350 };
3352 /* -mrecip options. */
3353 static struct
3354 {
3357 }
3359 {
3366 };
3370 /* Set up prefix/suffix so the error messages refer to either the command
3371 line argument, or the attribute(target). */
3373 {
3377 }
3378 else
3379 {
3383 }
3385 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3386 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3389 #ifdef TARGET_BI_ARCH
3390 else
3391 {
3392 #if TARGET_BI_ARCH == 1
3393 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3394 is on and OPTION_MASK_ABI_X32 is off. We turn off
3395 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3396 -mx32. */
3399 #else
3400 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3401 on and OPTION_MASK_ABI_64 is off. We turn off
3402 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3403 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3407 #endif
3408 }
3409 #endif
3412 {
3413 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3414 OPTION_MASK_ABI_64 for TARGET_X32. */
3417 }
3420 | OPTION_MASK_ABI_X32
3423 {
3424 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3425 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3428 }
3430 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3431 SUBTARGET_OVERRIDE_OPTIONS;
3432 #endif
3434 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3435 SUBSUBTARGET_OVERRIDE_OPTIONS;
3436 #endif
3438 /* -fPIC is the default for x86_64. */
3442 /* Need to check -mtune=generic first. */
3444 {
3445 /* As special support for cross compilers we read -mtune=native
3446 as -mtune=generic. With native compilers we won't see the
3447 -mtune=native, as it was changed by the driver. */
3449 {
3451 }
3456 }
3457 else
3458 {
3462 {
3463 opts->x_ix86_tune_string
3466 }
3468 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3469 or defaulted. We need to use a sensible tune option. */
3471 {
3473 }
3474 }
3478 {
3479 /* rep; movq isn't available in 32-bit code. */
3482 }
3485 opts->x_ix86_arch_string
3488 else
3492 {
3500 }
3501 else
3508 /* For targets using ms ABI enable ms-extensions, if not
3509 explicit turned off. For non-ms ABI we turn off this
3510 option. */
3515 {
3517 {
3561 {
3564 }
3572 }
3573 }
3574 else
3575 {
3576 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3577 use of rip-relative addressing. This eliminates fixups that
3578 would otherwise be needed if this object is to be placed in a
3579 DLL, and is essentially just as efficient as direct addressing. */
3585 else
3587 }
3589 {
3592 }
3600 {
3603 /* Default cpu tuning to the architecture. */
3781 }
3805 {
3809 {
3811 {
3813 {
3821 }
3822 else
3825 }
3826 }
3827 /* Intel CPUs have always interpreted SSE prefetch instructions as
3828 NOPs; so, we can enable SSE prefetch instructions even when
3829 -mtune (rather than -march) points us to a processor that has them.
3830 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3831 higher processors. */
3836 }
3844 #ifndef USE_IX86_FRAME_POINTER
3845 #define USE_IX86_FRAME_POINTER 0
3846 #endif
3848 #ifndef USE_X86_64_FRAME_POINTER
3849 #define USE_X86_64_FRAME_POINTER 0
3850 #endif
3852 /* Set the default values for switches whose default depends on TARGET_64BIT
3853 in case they weren't overwritten by command line options. */
3855 {
3863 opts->x_flag_unwind_tables
3867 }
3868 else
3869 {
3871 opts->x_flag_omit_frame_pointer
3877 }
3880 /* TODO: ix86_cost should be chosen at instruction or function granuality
3881 so for cold code we use size_cost even in !optimize_size compilation. */
3884 else
3887 /* Arrange to set up i386_stack_locals for all functions. */
3890 /* Validate -mregparm= value. */
3892 {
3896 {
3900 }
3901 }
3905 /* Default align_* from the processor table. */
3907 {
3910 }
3912 {
3915 }
3917 {
3919 }
3921 /* Provide default for -mbranch-cost= value. */
3926 {
3927 opts->x_target_flags
3930 /* Enable by default the SSE and MMX builtins. Do allow the user to
3931 explicitly disable any of these. In particular, disabling SSE and
3932 MMX for kernel code is extremely useful. */
3934 opts->x_ix86_isa_flags
3941 }
3942 else
3943 {
3944 opts->x_target_flags
3948 opts->x_ix86_isa_flags
3951 /* i386 ABI does not specify red zone. It still makes sense to use it
3952 when programmer takes care to stack from being destroyed. */
3955 }
3957 /* Keep nonleaf frame pointers. */
3963 /* If we're doing fast math, we don't care about comparison order
3964 wrt NaNs. This lets us use a shorter comparison sequence. */
3968 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3969 since the insns won't need emulation. */
3973 /* Likewise, if the target doesn't have a 387, or we've specified
3974 software floating point, don't use 387 inline intrinsics. */
3978 /* Turn on MMX builtins for -msse. */
3980 opts->x_ix86_isa_flags
3983 /* Enable SSE prefetch. */
3988 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3991 opts->x_ix86_isa_flags
3994 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3997 opts->x_ix86_isa_flags
4000 /* Enable lzcnt instruction for -mabm. */
4002 opts->x_ix86_isa_flags
4005 /* Validate -mpreferred-stack-boundary= value or default it to
4006 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4009 {
4016 {
4020 else
4023 }
4024 else
4025 ix86_preferred_stack_boundary
4027 }
4029 /* Set the default value for -mstackrealign. */
4035 /* Validate -mincoming-stack-boundary= value or default it to
4036 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4039 {
4046 else
4047 {
4048 ix86_user_incoming_stack_boundary
4050 ix86_incoming_stack_boundary
4052 }
4053 }
4055 #ifndef NO_PROFILE_COUNTERS
4058 #endif
4062 /* Accept -msseregparm only if at least SSE support is enabled. */
4068 {
4070 {
4072 {
4075 }
4078 {
4081 }
4082 }
4083 }
4084 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4085 fpmath=387. The second is however default at many targets since the
4086 extra 80bit precision of temporaries is considered to be part of ABI.
4087 Overwrite the default at least for -ffast-math.
4088 TODO: -mfpmath=both seems to produce same performing code with bit
4089 smaller binaries. It is however not clear if register allocation is
4090 ready for this setting.
4091 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4092 codegen. We may switch to 387 with -ffast-math for size optimized
4093 functions. */
4097 else
4100 /* If the i387 is disabled, then do not return values in it. */
4104 /* Use external vectorized library in vectorizing intrinsics. */
4107 {
4118 }
4124 /* If stack probes are required, the space used for large function
4125 arguments on the stack must also be probed, so enable
4126 -maccumulate-outgoing-args so this happens in the prologue. */
4129 {
4134 }
4136 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4137 {
4143 }
4145 /* When scheduling description is not available, disable scheduler pass
4146 so it won't slow down the compilation and make x87 code slower. */
4167 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4169 && HAVE_prefetch
4175 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4176 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4181 {
4184 {
4186 ix86_gen_tls_local_dynamic_base_64
4188 }
4189 else
4190 {
4192 ix86_gen_tls_local_dynamic_base_64
4194 }
4195 }
4196 else
4200 {
4210 }
4211 else
4212 {
4222 }
4224 #ifdef USE_IX86_CLD
4225 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4228 #endif
4231 {
4236 }
4238 {
4242 }
4244 {
4245 #if defined(PROFILE_BEFORE_PROLOGUE)
4247 #else
4249 #endif
4250 }
4260 /* Enable 128-bit AVX instruction generation
4261 for the auto-vectorizer. */
4267 {
4274 {
4277 {
4279 q++;
4280 }
4281 else
4286 else
4287 {
4290 {
4293 }
4296 {
4300 }
4301 }
4306 else
4308 }
4309 }
4316 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4317 for 64-bit Bionic. */
4322 ? MASK_LONG_DOUBLE_128
4325 /* Only one of them can be active. */
4329 /* Save the initial options in case the user does function specific
4330 options. */
4332 target_option_default_node = target_option_current_node
4335 /* Handle stack protector */
4337 opts->x_ix86_stack_protector_guard
4340 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4342 {
4346 }
4349 {
4353 }
4354 }
4356 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4358 static void
4360 {
4362 struct register_pass_info insert_vzeroupper_info
4365 };
4370 /* This needs to be done at start up. It's convenient to do it here. */
4372 }
4374 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4377 {
4381 }
4383 /* Update register usage after having seen the compiler flags. */
4385 static void
4387 {
4390 /* For 32-bit targets, squash the REX registers. */
4392 {
4399 }
4401 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4409 {
4410 /* Set/reset conditionally defined registers from
4411 CALL_USED_REGISTERS initializer. */
4415 /* Calculate registers of CLOBBERED_REGS register set
4416 as call used registers from GENERAL_REGS register set. */
4420 }
4422 /* If MMX is disabled, squash the registers. */
4428 /* If SSE is disabled, squash the registers. */
4434 /* If the FPU is disabled, squash the registers. */
4440 /* If AVX512F is disabled, squash the registers. */
4442 {
4448 }
4450 /* If MPX is disabled, squash the registers. */
4454 }
4456 \f
4457 /* Save the current options */
4459 static void
4462 {
4498 /* The fields are char but the variables are not; make sure the
4499 values fit in the fields. */
4504 }
4506 /* Restore the current options */
4508 static void
4511 {
4517 /* We don't change -fPIC. */
4555 /* TODO: ix86_cost should be chosen at instruction or function granuality
4556 so for cold code we use size_cost even in !optimize_size compilation. */
4559 else
4562 /* Recreate the arch feature tests if the arch changed */
4564 {
4569 }
4571 /* Recreate the tune optimization tests */
4574 }
4576 /* Adjust target options after streaming them in. This is mainly about
4577 reconciling them with global options. */
4579 static void
4581 {
4582 /* flag_pic is a global option, but ix86_cmodel is target saved option
4583 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4584 for PIC, or error out. */
4587 {
4606 }
4607 else
4609 {
4624 }
4625 }
4627 /* Print the current options */
4629 static void
4632 {
4650 {
4653 }
4654 }
4656 \f
4657 /* Inner function to process the attribute((target(...))), take an argument and
4658 set the current options from the argument. If we have a list, recursively go
4659 over the list. */
4661 static bool
4666 {
4670 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4671 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4672 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4673 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4674 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4676 enum ix86_opt_type
4677 {
4678 ix86_opt_unknown,
4679 ix86_opt_yes,
4680 ix86_opt_no,
4681 ix86_opt_str,
4682 ix86_opt_enum,
4683 ix86_opt_isa
4684 };
4686 static const struct
4687 {
4694 /* isa options */
4747 /* enum options */
4750 /* string options */
4754 /* flag options */
4756 OPT_mcld,
4757 MASK_CLD),
4760 OPT_mfancy_math_387,
4761 MASK_NO_FANCY_MATH_387),
4764 OPT_mieee_fp,
4765 MASK_IEEE_FP),
4768 OPT_minline_all_stringops,
4769 MASK_INLINE_ALL_STRINGOPS),
4772 OPT_minline_stringops_dynamically,
4773 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4776 OPT_mno_align_stringops,
4777 MASK_NO_ALIGN_STRINGOPS),
4780 OPT_mrecip,
4781 MASK_RECIP),
4783 };
4785 /* If this is a list, recurse to get the options. */
4787 {
4794 enum_opts_set))
4798 }
4801 {
4804 }
4806 /* Handle multiple arguments separated by commas. */
4810 {
4824 {
4828 }
4829 else
4830 {
4833 }
4835 /* Recognize no-xxx. */
4837 {
4841 }
4842 else
4845 /* Find the option. */
4849 {
4857 {
4862 }
4863 }
4865 /* Process the option. */
4867 {
4870 }
4873 {
4879 }
4882 {
4888 else
4890 }
4893 {
4895 {
4898 }
4899 else
4901 }
4904 {
4912 global_dc);
4913 else
4914 {
4917 }
4918 }
4920 else
4922 }
4925 }
4927 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4929 tree
4933 {
4948 /* Process each of the options on the chain. */
4953 /* If the changed options are different from the default, rerun
4954 ix86_option_override_internal, and then save the options away.
4955 The string options are are attribute options, and will be undone
4956 when we copy the save structure. */
4962 {
4963 /* If we are using the default tune= or arch=, undo the string assigned,
4964 and use the default. */
4975 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4980 {
4983 }
4985 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4988 /* Add any builtin functions with the new isa if any. */
4991 /* Save the current options unless we are validating options for
4992 #pragma. */
4999 /* Free up memory allocated to hold the strings */
5002 }
5005 }
5007 /* Hook to validate attribute((target("string"))). */
5009 static bool
5012 tree args,
5014 {
5019 /* attribute((target("default"))) does nothing, beyond
5020 affecting multi-versioning. */
5029 /* Get the optimization options of the current function. */
5035 /* Init func_options. */
5043 /* Initialize func_options to the default before its target options can
5044 be set. */
5057 {
5062 }
5065 }
5067 \f
5068 /* Hook to determine if one function can safely inline another. */
5070 static bool
5072 {
5077 /* If callee has no option attributes, then it is ok to inline. */
5081 /* If caller has no option attributes, but callee does then it is not ok to
5082 inline. */
5086 else
5087 {
5091 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5092 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5093 function. */
5098 /* See if we have the same non-isa options. */
5102 /* See if arch, tune, etc. are the same. */
5115 else
5117 }
5120 }
5122 \f
5123 /* Remember the last target of ix86_set_current_function. */
5126 /* Set targets globals to the default (or current #pragma GCC target
5127 if active). Invalidate ix86_previous_fndecl cache. */
5129 void
5131 {
5138 else
5141 }
5143 /* Establish appropriate back-end context for processing the function
5144 FNDECL. The argument might be NULL to indicate processing at top
5145 level, outside of any function scope. */
5146 static void
5148 {
5149 /* Only change the context if the function changes. This hook is called
5150 several times in the course of compiling a function, and we don't want to
5151 slow things down too much or call target_reinit when it isn't safe. */
5155 tree old_tree;
5160 else
5164 {
5168 }
5175 {
5181 else
5183 }
5185 }
5187 \f
5188 /* Return true if this goes in large data/bss. */
5190 static bool
5192 {
5196 /* Functions are never large data. */
5200 /* Automatic variables are never large data. */
5205 {
5211 }
5212 else
5213 {
5216 /* If this is an incomplete type with size 0, then we can't put it
5217 in data because it might be too big when completed. Also,
5218 int_size_in_bytes returns -1 if size can vary or is larger than
5219 an integer in which case also it is safer to assume that it goes in
5220 large data. */
5223 }
5226 }
5228 /* Switch to the appropriate section for output of DECL.
5229 DECL is either a `VAR_DECL' node or a constant of some sort.
5230 RELOC indicates whether forming the initial value of DECL requires
5231 link-time relocations. */
5236 {
5238 {
5242 {
5276 /* We don't split these for medium model. Place them into
5277 default sections and hope for best. */
5279 }
5281 {
5282 /* We might get called with string constants, but get_named_section
5283 doesn't like them as they are not DECLs. Also, we need to set
5284 flags in that case. */
5288 }
5289 }
5291 }
5293 /* Select a set of attributes for section NAME based on the properties
5294 of DECL and whether or not RELOC indicates that DECL's initializer
5295 might contain runtime relocations. */
5297 static unsigned int ATTRIBUTE_UNUSED
5299 {
5313 }
5315 /* Build up a unique section name, expressed as a
5316 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5317 RELOC indicates whether the initial value of EXP requires
5318 link-time relocations. */
5320 static void ATTRIBUTE_UNUSED
5322 {
5324 {
5326 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5330 {
5354 /* We don't split these for medium model. Place them into
5355 default sections and hope for best. */
5357 }
5359 {
5366 /* If we're using one_only, then there needs to be a .gnu.linkonce
5367 prefix to the section name. */
5374 }
5375 }
5377 }
5379 #ifdef COMMON_ASM_OP
5380 /* This says how to output assembler code to declare an
5381 uninitialized external linkage data object.
5383 For medium model x86-64 we need to use .largecomm opcode for
5384 large objects. */
5385 void
5389 {
5393 else
5398 }
5399 #endif
5401 /* Utility function for targets to use in implementing
5402 ASM_OUTPUT_ALIGNED_BSS. */
5404 void
5407 {
5411 else
5414 #ifdef ASM_DECLARE_OBJECT_NAME
5417 #else
5418 /* Standard thing is just output label for the object. */
5422 }
5423 \f
5424 /* Decide whether we must probe the stack before any space allocation
5425 on this target. It's essentially TARGET_STACK_PROBE except when
5426 -fstack-check causes the stack to be already probed differently. */
5428 bool
5430 {
5431 /* Do not probe the stack twice if static stack checking is enabled. */
5436 }
5437 \f
5438 /* Decide whether we can make a sibling call to a function. DECL is the
5439 declaration of the function being targeted by the call and EXP is the
5440 CALL_EXPR representing the call. */
5442 static bool
5444 {
5448 /* If we are generating position-independent code, we cannot sibcall
5449 optimize any indirect call, or a direct call to a global function,
5450 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5452 && !TARGET_64BIT
5453 && flag_pic
5457 /* If we need to align the outgoing stack, then sibcalling would
5458 unalign the stack, which may break the called function. */
5464 {
5467 }
5468 else
5469 {
5470 /* We're looking at the CALL_EXPR, we need the type of the function. */
5475 }
5477 /* Check that the return value locations are the same. Like
5478 if we are returning floats on the 80387 register stack, we cannot
5479 make a sibcall from a function that doesn't return a float to a
5480 function that does or, conversely, from a function that does return
5481 a float to a function that doesn't; the necessary stack adjustment
5482 would not be executed. This is also the place we notice
5483 differences in the return value ABI. Note that it is ok for one
5484 of the functions to have void return type as long as the return
5485 value of the other is passed in a register. */
5490 {
5493 }
5495 ;
5500 {
5501 /* The SYSV ABI has more call-clobbered registers;
5502 disallow sibcalls from MS to SYSV. */
5506 }
5507 else
5508 {
5509 /* If this call is indirect, we'll need to be able to use a
5510 call-clobbered register for the address of the target function.
5511 Make sure that all such registers are not used for passing
5512 parameters. Note that DLLIMPORT functions are indirect. */
5515 {
5517 {
5518 /* ??? Need to count the actual number of registers to be used,
5519 not the possible number of registers. Fix later. */
5521 }
5522 }
5523 }
5525 /* Otherwise okay. That also includes certain types of indirect calls. */
5527 }
5529 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5530 and "sseregparm" calling convention attributes;
5531 arguments as in struct attribute_spec.handler. */
5533 static tree
5535 tree args,
5538 {
5543 {
5545 name);
5548 }
5550 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5552 {
5553 tree cst;
5556 {
5558 }
5561 {
5563 }
5567 {
5570 name);
5572 }
5574 {
5578 }
5581 }
5584 {
5585 /* Do not warn when emulating the MS ABI. */
5590 name);
5593 }
5595 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5597 {
5599 {
5601 }
5603 {
5605 }
5607 {
5609 }
5611 {
5613 }
5614 }
5616 /* Can combine stdcall with fastcall (redundant), regparm and
5617 sseregparm. */
5619 {
5621 {
5623 }
5625 {
5627 }
5629 {
5631 }
5632 }
5634 /* Can combine cdecl with regparm and sseregparm. */
5636 {
5638 {
5640 }
5642 {
5644 }
5646 {
5648 }
5649 }
5651 {
5654 name);
5656 {
5658 }
5660 {
5662 }
5664 {
5666 }
5667 }
5669 /* Can combine sseregparm with all attributes. */
5672 }
5674 /* The transactional memory builtins are implicitly regparm or fastcall
5675 depending on the ABI. Override the generic do-nothing attribute that
5676 these builtins were declared with, and replace it with one of the two
5677 attributes that we expect elsewhere. */
5679 static tree
5682 {
5683 tree alt;
5685 /* In no case do we want to add the placeholder attribute. */
5688 /* The 64-bit ABI is unchanged for transactional memory. */
5692 /* ??? Is there a better way to validate 32-bit windows? We have
5693 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5696 else
5697 {
5700 }
5704 }
5706 /* This function determines from TYPE the calling-convention. */
5708 unsigned int
5710 {
5713 tree attrs;
5720 {
5730 /* Regparam isn't allowed for thiscall and fastcall. */
5732 {
5737 }
5741 }
5748 || is_stdarg
5754 }
5756 /* Return 0 if the attributes for two types are incompatible, 1 if they
5757 are compatible, and 2 if they are nearly compatible (which causes a
5758 warning to be generated). */
5760 static int
5762 {
5778 }
5779 \f
5780 /* Return the regparm value for a function with the indicated TYPE and DECL.
5781 DECL may be NULL when calling function indirectly
5782 or considering a libcall. */
5784 static int
5786 {
5787 tree attr;
5798 {
5801 {
5804 }
5805 }
5811 /* Use register calling convention for local functions when possible. */
5814 {
5819 /* Caller and callee must agree on the calling convention, so
5820 checking here just optimize means that with
5821 __attribute__((optimize (...))) caller could use regparm convention
5822 and callee not, or vice versa. Instead look at whether the callee
5823 is optimized or not. */
5826 {
5829 {
5832 /* Make sure no regparm register is taken by a
5833 fixed register variable. */
5835 local_regparm++)
5839 /* We don't want to use regparm(3) for nested functions as
5840 these use a static chain pointer in the third argument. */
5844 /* Save a register for the split stack. */
5848 /* Each fixed register usage increases register pressure,
5849 so less registers should be used for argument passing.
5850 This functionality can be overriden by an explicit
5851 regparm value. */
5854 globals++;
5856 local_regparm
5861 }
5862 }
5863 }
5866 }
5868 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5869 DFmode (2) arguments in SSE registers for a function with the
5870 indicated TYPE and DECL. DECL may be NULL when calling function
5871 indirectly or considering a libcall. Otherwise return 0. */
5873 static int
5875 {
5878 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5879 by the sseregparm attribute. */
5882 {
5884 {
5886 {
5890 else
5893 }
5895 }
5898 }
5907 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5908 (and DFmode for SSE2) arguments in SSE registers. */
5910 /* TARGET_SSE_MATH */
5914 {
5917 {
5918 /* Refuse to produce wrong code when local function with SSE enabled
5919 is called from SSE disabled function.
5920 We may work hard to work out these scenarios but hopefully
5921 it doesnot matter in practice. */
5923 {
5927 }
5930 }
5931 }
5934 }
5936 /* Return true if EAX is live at the start of the function. Used by
5937 ix86_expand_prologue to determine if we need special help before
5938 calling allocate_stack_worker. */
5940 static bool
5942 {
5943 /* Cheat. Don't bother working forward from ix86_function_regparm
5944 to the function type to whether an actual argument is located in
5945 eax. Instead just look at cfg info, which is still close enough
5946 to correct at this point. This gives false positives for broken
5947 functions that might use uninitialized data that happens to be
5948 allocated in eax, but who cares? */
5950 }
5952 static bool
5954 {
5955 tree attr;
5958 {
5964 /* For 32-bit MS-ABI the default is to keep aggregate
5965 return pointer. */
5968 }
5970 }
5972 /* Value is the number of bytes of arguments automatically
5973 popped when returning from a subroutine call.
5974 FUNDECL is the declaration node of the function (as a tree),
5975 FUNTYPE is the data type of the function (as a tree),
5976 or for a library call it is an identifier node for the subroutine name.
5977 SIZE is the number of bytes of arguments passed on the stack.
5979 On the 80386, the RTD insn may be used to pop them if the number
5980 of args is fixed, but if the number is variable then the caller
5981 must pop them all. RTD can't be used for library calls now
5982 because the library is compiled with the Unix compiler.
5983 Use of RTD is a selectable option, since it is incompatible with
5984 standard Unix calling sequences. If the option is not selected,
5985 the caller must always pop the args.
5987 The attribute stdcall is equivalent to RTD on a per module basis. */
5989 static int
5991 {
5994 /* None of the 64-bit ABIs pop arguments. */
6005 /* Lose any fake structure return argument if it is passed on the stack. */
6008 {
6012 }
6015 }
6017 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6019 static bool
6021 {
6022 /* Check operand constraints in case hard registers were propagated
6023 into insn pattern. This check prevents combine pass from
6024 generating insn patterns with invalid hard register operands.
6025 These invalid insns can eventually confuse reload to error out
6026 with a spill failure. See also PRs 46829 and 46843. */
6028 {
6037 {
6045 /* For pre-AVX disallow unaligned loads/stores where the
6046 instructions don't support it. */
6050 {
6054 }
6056 /* A unary operator may be accepted by the predicate, but it
6057 is irrelevant for matching constraints. */
6062 {
6070 }
6077 /* Operand has no constraints, anything is OK. */
6082 {
6087 && operands_match_p
6091 {
6094 }
6095 }
6099 }
6100 }
6103 }
6104 \f
6105 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6107 static unsigned HOST_WIDE_INT
6109 {
6113 }
6114 \f
6115 /* Argument support functions. */
6117 /* Return true when register may be used to pass function parameters. */
6118 bool
6120 {
6128 {
6132 else
6138 }
6144 /* TODO: The function should depend on current function ABI but
6145 builtins.c would need updating then. Therefore we use the
6146 default ABI. */
6148 /* RAX is used as hidden argument to va_arg functions. */
6154 else
6161 }
6163 /* Return if we do not know how to pass TYPE solely in registers. */
6165 static bool
6167 {
6171 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6172 The layout_type routine is crafty and tries to trick us into passing
6173 currently unsupported vector types on the stack by using TImode. */
6176 }
6178 /* It returns the size, in bytes, of the area reserved for arguments passed
6179 in registers for the function represented by fndecl dependent to the used
6180 abi format. */
6181 int
6183 {
6187 else
6192 }
6194 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6195 call abi used. */
6196 enum calling_abi
6198 {
6200 {
6203 {
6205 {
6207 {
6210 {
6213 }
6214 }
6216 }
6217 }
6221 }
6223 }
6225 /* We add this as a workaround in order to use libc_has_function
6226 hook in i386.md. */
6227 bool
6229 {
6231 }
6233 static bool
6235 {
6237 {
6241 else
6243 }
6245 }
6247 static enum calling_abi
6249 {
6253 }
6255 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6256 call abi used. */
6257 enum calling_abi
6259 {
6263 }
6265 /* Write the extra assembler code needed to declare a function properly. */
6267 void
6269 tree decl)
6270 {
6274 {
6280 }
6282 #ifdef SUBTARGET_ASM_UNWIND_INIT
6284 #endif
6288 /* Output magic byte marker, if hot-patch attribute is set. */
6290 {
6292 {
6293 /* leaq [%rsp + 0], %rsp */
6296 }
6297 else
6298 {
6299 /* movl.s %edi, %edi
6300 push %ebp
6301 movl.s %esp, %ebp */
6304 }
6305 }
6306 }
6308 /* regclass.c */
6311 /* Implementation of call abi switching target hook. Specific to FNDECL
6312 the specific call register sets are set. See also
6313 ix86_conditional_register_usage for more details. */
6314 void
6316 {
6319 else
6321 }
6323 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6324 expensive re-initialization of init_regs each time we switch function context
6325 since this is needed only during RTL expansion. */
6326 static void
6328 {
6332 }
6334 /* Return 1 if pseudo register should be created and used to hold
6335 GOT address for PIC code. */
6336 bool
6338 {
6345 }
6347 /* Initialize large model PIC register. */
6349 static void
6351 {
6353 rtx tmp_reg;
6362 label));
6366 }
6368 /* Create and initialize PIC register if required. */
6369 static void
6371 {
6372 edge entry_edge;
6381 {
6384 else
6386 }
6387 else
6388 {
6389 /* If there is future mcount call in the function it is more profitable
6390 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6399 }
6407 }
6409 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6410 for a call to a function whose data type is FNTYPE.
6411 For a library call, FNTYPE is 0. */
6413 void
6417 tree fndecl,
6419 {
6426 {
6429 {
6433 }
6434 else
6436 }
6437 else
6442 /* Set up the number of registers to use for passing arguments. */
6445 {
6447 ? X86_64_REGPARM_MAX
6449 }
6451 {
6454 {
6456 ? X86_64_SSE_REGPARM_MAX
6458 }
6459 }
6467 /* Because type might mismatch in between caller and callee, we need to
6468 use actual type of function for local calls.
6469 FIXME: cgraph_analyze can be told to actually record if function uses
6470 va_start so for local functions maybe_vaarg can be made aggressive
6471 helping K&R code.
6472 FIXME: once typesytem is fixed, we won't need this code anymore. */
6485 {
6486 /* If there are variable arguments, then we won't pass anything
6487 in registers in 32-bit mode. */
6489 {
6498 }
6500 /* Use ecx and edx registers if function has fastcall attribute,
6501 else look for regparm information. */
6503 {
6506 {
6509 }
6511 {
6514 }
6515 else
6517 }
6519 /* Set up the number of SSE registers used for passing SFmode
6520 and DFmode arguments. Warn for mismatching ABI. */
6522 }
6523 }
6525 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6526 But in the case of vector types, it is some vector mode.
6528 When we have only some of our vector isa extensions enabled, then there
6529 are some modes for which vector_mode_supported_p is false. For these
6530 modes, the generic vector support in gcc will choose some non-vector mode
6531 in order to implement the type. By computing the natural mode, we'll
6532 select the proper ABI location for the operand and not depend on whatever
6533 the middle-end decides to do with these vector types.
6535 The midde-end can't deal with the vector types > 16 bytes. In this
6536 case, we return the original mode and warn ABI change if CUM isn't
6537 NULL.
6539 If INT_RETURN is true, warn ABI change if the vector mode isn't
6540 available for function return value. */
6542 static machine_mode
6545 {
6549 {
6552 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6554 {
6559 else
6562 /* Get the mode which has this inner mode and number of units. */
6566 {
6568 {
6573 {
6577 }
6579 {
6583 }
6586 }
6588 {
6593 {
6597 }
6599 {
6603 }
6606 }
6609 {
6614 {
6618 }
6620 {
6624 }
6625 }
6627 {
6632 {
6636 }
6638 {
6642 }
6643 }
6645 }
6648 }
6649 }
6652 }
6654 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6655 this may not agree with the mode that the type system has chosen for the
6656 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6657 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6659 static rtx
6662 {
6663 rtx tmp;
6667 else
6668 {
6672 }
6675 }
6677 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6678 of this code is to classify each 8bytes of incoming argument by the register
6679 class and assign registers accordingly. */
6681 /* Return the union class of CLASS1 and CLASS2.
6682 See the x86-64 PS ABI for details. */
6684 static enum x86_64_reg_class
6686 {
6687 /* Rule #1: If both classes are equal, this is the resulting class. */
6691 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6692 the other class. */
6698 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6702 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6710 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6711 MEMORY is used. */
6720 /* Rule #6: Otherwise class SSE is used. */
6722 }
6724 /* Classify the argument of type TYPE and mode MODE.
6725 CLASSES will be filled by the register class used to pass each word
6726 of the operand. The number of words is returned. In case the parameter
6727 should be passed in memory, 0 is returned. As a special case for zero
6728 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6730 BIT_OFFSET is used internally for handling records and specifies offset
6731 of the offset in bits modulo 512 to avoid overflow cases.
6733 See the x86-64 PS ABI for details.
6734 */
6736 static int
6739 {
6740 HOST_WIDE_INT bytes =
6742 int words
6745 /* Variable sized entities are always passed/returned in memory. */
6754 {
6756 tree field;
6759 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6766 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6767 signalize memory class, so handle it as special case. */
6769 {
6772 }
6774 /* Classify each field of record and merge classes. */
6776 {
6778 /* And now merge the fields of structure. */
6780 {
6782 {
6788 /* Bitfields are always classified as integer. Handle them
6789 early, since later code would consider them to be
6790 misaligned integers. */
6792 {
6801 }
6802 else
6803 {
6808 /* Flexible array member is ignored. */
6815 {
6819 {
6822 "the ABI of passing struct with"
6823 " a flexible array member has"
6825 }
6827 }
6829 subclasses,
6839 }
6840 }
6841 }
6845 /* Arrays are handled as small records. */
6846 {
6853 /* The partial classes are now full classes. */
6864 }
6867 /* Unions are similar to RECORD_TYPE but offset is always 0.
6868 */
6870 {
6872 {
6880 bit_offset);
6885 }
6886 }
6891 }
6894 {
6895 /* When size > 16 bytes, if the first one isn't
6896 X86_64_SSE_CLASS or any other ones aren't
6897 X86_64_SSEUP_CLASS, everything should be passed in
6898 memory. */
6905 }
6907 /* Final merger cleanup. */
6909 {
6910 /* If one class is MEMORY, everything should be passed in
6911 memory. */
6915 /* The X86_64_SSEUP_CLASS should be always preceded by
6916 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6920 {
6921 /* The first one should never be X86_64_SSEUP_CLASS. */
6924 }
6926 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6927 everything should be passed in memory. */
6930 {
6933 /* The first one should never be X86_64_X87UP_CLASS. */
6936 {
6939 "the ABI of passing union with long double"
6941 }
6943 }
6944 }
6946 }
6948 /* Compute alignment needed. We align all types to natural boundaries with
6949 exception of XFmode that is aligned to 64bits. */
6951 {
6960 /* Misaligned fields are always returned in memory. */
6963 }
6965 /* for V1xx modes, just use the base mode */
6970 /* Classification of atomic types. */
6972 {
6988 {
6991 /* Analyze last 128 bits only. */
6995 {
6998 }
7000 {
7003 }
7005 {
7009 }
7011 {
7014 }
7015 else
7017 }
7024 /* OImode shouldn't be used directly. */
7031 else
7049 else
7050 {
7054 {
7057 "the ABI of passing structure with complex float"
7059 }
7062 }
7071 /* This modes is larger than 16 bytes. */
7129 else
7133 }
7134 }
7136 /* Examine the argument and return set number of register required in each
7137 class. Return true iff parameter should be passed in memory. */
7139 static bool
7142 {
7153 {
7174 }
7177 }
7179 /* Construct container for the argument used by GCC interface. See
7180 FUNCTION_ARG for the detailed description. */
7182 static rtx
7186 {
7187 /* The following variables hold the static issued_error state. */
7192 machine_mode tmpmode;
7201 rtx ret;
7212 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7213 some less clueful developer tries to use floating-point anyway. */
7215 {
7217 {
7219 {
7222 }
7223 }
7225 {
7228 }
7230 }
7232 /* Likewise, error if the ABI requires us to return values in the
7233 x87 registers and the user specified -mno-80387. */
7239 {
7241 {
7244 }
7246 }
7248 /* First construct simple cases. Avoid SCmode, since we want to use
7249 single register to pass this type. */
7252 {
7267 /* Zero sized array, struct or class. */
7271 }
7310 /* Otherwise figure out the entries of the PARALLEL. */
7312 {
7316 {
7321 /* Merge TImodes on aligned occasions here too. */
7323 tmpmode
7327 else
7329 /* We've requested 24 bytes we
7330 don't have mode for. Use DImode. */
7337 intreg++;
7345 sse_regno++;
7353 sse_regno++;
7358 {
7364 {
7366 i++;
7367 }
7368 else
7393 }
7399 sse_regno++;
7403 }
7404 }
7406 /* Empty aligned struct, union or class. */
7414 }
7416 /* Update the data in CUM to advance over an argument of mode MODE
7417 and data type TYPE. (TYPE is null for libcalls where that information
7418 may not be available.)
7420 Return a number of integer regsiters advanced over. */
7422 static int
7425 HOST_WIDE_INT words)
7426 {
7430 {
7437 /* FALLTHRU */
7449 {
7452 }
7456 /* OImode shouldn't be used directly. */
7465 /* FALLTHRU */
7487 {
7492 {
7495 }
7496 }
7506 {
7511 {
7514 }
7515 }
7517 }
7520 }
7522 static int
7525 {
7528 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7535 {
7541 }
7542 else
7543 {
7548 }
7549 }
7551 static int
7553 HOST_WIDE_INT words)
7554 {
7555 /* Otherwise, this should be passed indirect. */
7560 {
7564 }
7566 }
7568 /* Update the data in CUM to advance over an argument of mode MODE and
7569 data type TYPE. (TYPE is null for libcalls where that information
7570 may not be available.) */
7572 static void
7575 {
7582 else
7591 {
7592 /* If we pass bounds in BT then just update remained bounds count. */
7594 {
7597 }
7599 /* Update remained number of bounds to force. */
7606 }
7608 /* The first arg not going to Bounds Tables resets this counter. */
7610 /* For unnamed args we always pass bounds to avoid bounds mess when
7611 passed and received types do not match. If bounds do not follow
7612 unnamed arg, still pretend required number of bounds were passed. */
7614 {
7617 }
7623 else
7626 /* For stdarg we expect bounds to be passed for each value passed
7627 in register. */
7630 /* For pointers passed in memory we expect bounds passed in Bounds
7631 Table. */
7634 }
7636 /* Define where to put the arguments to a function.
7637 Value is zero to push the argument on the stack,
7638 or a hard register in which to store the argument.
7640 MODE is the argument's machine mode.
7641 TYPE is the data type of the argument (as a tree).
7642 This is null for libcalls where that information may
7643 not be available.
7644 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7645 the preceding args and about the function being called.
7646 NAMED is nonzero if this argument is a named parameter
7647 (otherwise it is an extra parameter matching an ellipsis). */
7649 static rtx
7653 {
7654 /* Avoid the AL settings for the Unix64 ABI. */
7659 {
7666 /* FALLTHRU */
7672 {
7675 /* Fastcall allocates the first two DWORD (SImode) or
7676 smaller arguments to ECX and EDX if it isn't an
7677 aggregate type . */
7679 {
7685 /* ECX not EAX is the first allocated register. */
7688 }
7690 }
7699 /* FALLTHRU */
7701 /* In 32bit, we pass TImode in xmm registers. */
7709 {
7713 }
7718 /* OImode and XImode shouldn't be used directly. */
7734 {
7738 }
7748 {
7752 }
7754 }
7757 }
7759 static rtx
7762 {
7763 /* Handle a hidden AL argument containing number of registers
7764 for varargs x86-64 functions. */
7768 ? X86_64_SSE_REGPARM_MAX
7773 {
7789 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7793 }
7799 }
7801 static rtx
7804 HOST_WIDE_INT bytes)
7805 {
7808 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7809 We use value of -2 to specify that current function call is MSABI. */
7813 /* If we've run out of registers, it goes on the stack. */
7819 /* Only floating point modes are passed in anything but integer regs. */
7821 {
7824 else
7825 {
7828 /* Unnamed floating parameters are passed in both the
7829 SSE and integer registers. */
7835 }
7836 }
7837 /* Handle aggregated types passed in register. */
7839 {
7844 }
7847 }
7849 /* Return where to put the arguments to a function.
7850 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7852 MODE is the argument's machine mode. TYPE is the data type of the
7853 argument. It is null for libcalls where that information may not be
7854 available. CUM gives information about the preceding args and about
7855 the function being called. NAMED is nonzero if this argument is a
7856 named parameter (otherwise it is an extra parameter matching an
7857 ellipsis). */
7859 static rtx
7862 {
7866 rtx arg;
7868 /* All pointer bounds argumntas are handled separately here. */
7871 {
7872 /* Return NULL if bounds are forced to go in Bounds Table. */
7875 /* Return the next available bound reg if any. */
7878 /* Return the next special slot number otherwise. */
7879 else
7883 }
7887 else
7891 /* To simplify the code below, represent vector types with a vector mode
7892 even if MMX/SSE are not active. */
7900 else
7904 }
7906 /* A C expression that indicates when an argument must be passed by
7907 reference. If nonzero for an argument, a copy of that argument is
7908 made in memory and a pointer to the argument is passed instead of
7909 the argument itself. The pointer is passed in whatever way is
7910 appropriate for passing a pointer to that type. */
7912 static bool
7915 {
7918 /* Bounds are never passed by reference. */
7923 /* See Windows x64 Software Convention. */
7925 {
7928 {
7929 /* Arrays are passed by reference. */
7934 {
7935 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7936 are passed by reference. */
7938 }
7939 }
7941 /* __m128 is passed by reference. */
7947 }
7948 }
7953 }
7955 /* Return true when TYPE should be 128bit aligned for 32bit argument
7956 passing ABI. XXX: This function is obsolete and is only used for
7957 checking psABI compatibility with previous versions of GCC. */
7959 static bool
7961 {
7973 {
7974 /* Walk the aggregates recursively. */
7976 {
7980 {
7981 tree field;
7983 /* Walk all the structure fields. */
7985 {
7989 }
7991 }
7994 /* Just for use if some languages passes arrays by value. */
8001 }
8002 }
8004 }
8006 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8007 XXX: This function is obsolete and is only used for checking psABI
8008 compatibility with previous versions of GCC. */
8010 static unsigned int
8013 {
8014 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8015 natural boundaries. */
8017 {
8018 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8019 make an exception for SSE modes since these require 128bit
8020 alignment.
8022 The handling here differs from field_alignment. ICC aligns MMX
8023 arguments to 4 byte boundaries, while structure fields are aligned
8024 to 8 byte boundaries. */
8026 {
8029 }
8030 else
8031 {
8034 }
8035 }
8039 }
8041 /* Return true when TYPE should be 128bit aligned for 32bit argument
8042 passing ABI. */
8044 static bool
8046 {
8056 {
8057 /* Walk the aggregates recursively. */
8059 {
8063 {
8064 tree field;
8066 /* Walk all the structure fields. */
8068 field;
8070 {
8074 }
8076 }
8079 /* Just for use if some languages passes arrays by value. */
8086 }
8087 }
8088 else
8092 }
8094 /* Gives the alignment boundary, in bits, of an argument with the
8095 specified mode and type. */
8097 static unsigned int
8099 {
8102 {
8103 /* Since the main variant type is used for call, we convert it to
8104 the main variant type. */
8107 }
8108 else
8112 else
8113 {
8118 {
8119 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8121 {
8124 }
8130 }
8133 && !warned
8135 saved_align))
8136 {
8139 "The ABI for passing parameters with %d-byte"
8142 }
8143 }
8146 }
8148 /* Return true if N is a possible register number of function value. */
8150 static bool
8152 {
8154 {
8166 /* Complex values are returned in %st(0)/%st(1) pair. */
8169 /* TODO: The function should depend on current function ABI but
8170 builtins.c would need updating then. Therefore we use the
8171 default ABI. */
8176 /* Complex values are returned in %xmm0/%xmm1 pair. */
8185 }
8188 }
8190 /* Define how to find the value returned by a function.
8191 VALTYPE is the data type of the value (as a tree).
8192 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8193 otherwise, FUNC is 0. */
8195 static rtx
8198 {
8201 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8202 we normally prevent this case when mmx is not available. However
8203 some ABIs may require the result to be returned like DImode. */
8207 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8208 we prevent this case when sse is not available. However some ABIs
8209 may require the result to be returned like integer TImode. */
8214 /* 32-byte vector modes in %ymm0. */
8218 /* 64-byte vector modes in %zmm0. */
8222 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8225 else
8226 /* Most things go in %eax. */
8229 /* Override FP return register with %xmm0 for local functions when
8230 SSE math is enabled or for functions with sseregparm attribute. */
8232 {
8237 }
8239 /* OImode shouldn't be used directly. */
8243 }
8245 static rtx
8247 const_tree valtype)
8248 {
8249 rtx ret;
8251 /* Handle libcalls, which don't provide a type node. */
8253 {
8257 {
8276 }
8279 }
8281 {
8282 /* Pointers are always returned in word_mode. */
8284 }
8290 /* For zero sized structures, construct_container returns NULL, but we
8291 need to keep rest of compiler happy by returning meaningful value. */
8296 }
8298 static rtx
8300 const_tree valtype)
8301 {
8305 {
8307 {
8326 }
8327 }
8329 }
8331 static rtx
8334 {
8349 else
8351 }
8353 static rtx
8355 {
8361 }
8363 /* Return an RTX representing a place where a function returns
8364 or recieves pointer bounds or NULL if no bounds are returned.
8366 VALTYPE is a data type of a value returned by the function.
8368 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8369 or FUNCTION_TYPE of the function.
8371 If OUTGOING is false, return a place in which the caller will
8372 see the return value. Otherwise, return a place where a
8373 function returns a value. */
8375 static rtx
8377 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8379 {
8385 {
8386 bitmap slots;
8388 bitmap_iterator bi;
8396 {
8401 }
8407 }
8408 else
8412 }
8414 /* Pointer function arguments and return values are promoted to
8415 word_mode. */
8417 static machine_mode
8421 {
8423 {
8426 }
8428 for_return);
8429 }
8431 /* Return true if a structure, union or array with MODE containing FIELD
8432 should be accessed using BLKmode. */
8434 static bool
8436 {
8437 /* Union with XFmode must be in BLKmode. */
8441 }
8443 rtx
8445 {
8447 }
8449 /* Return true iff type is returned in memory. */
8451 static bool
8453 {
8454 #ifdef SUBTARGET_RETURN_IN_MEMORY
8456 #else
8458 HOST_WIDE_INT size;
8464 {
8466 {
8469 /* __m128 is returned in xmm0. */
8478 /* Otherwise, the size must be exactly in [1248]. */
8480 }
8481 else
8482 {
8487 }
8488 }
8489 else
8490 {
8500 {
8501 /* User-created vectors small enough to fit in EAX. */
8505 /* Unless ABI prescibes otherwise,
8506 MMX/3dNow values are returned in MM0 if available. */
8511 /* SSE values are returned in XMM0 if available. */
8515 /* AVX values are returned in YMM0 if available. */
8519 /* AVX512F values are returned in ZMM0 if available. */
8522 }
8530 /* OImode shouldn't be used directly. */
8534 }
8535 #endif
8536 }
8538 \f
8539 /* Create the va_list data type. */
8541 /* Returns the calling convention specific va_list date type.
8542 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8544 static tree
8546 {
8549 /* For i386 we use plain pointer to argument area. */
8559 unsigned_type_node);
8562 unsigned_type_node);
8565 ptr_type_node);
8568 ptr_type_node);
8587 /* The correct type is an array type of one element. */
8589 }
8591 /* Setup the builtin va_list data type and for 64-bit the additional
8592 calling convention specific va_list data types. */
8594 static tree
8596 {
8599 /* Initialize abi specific va_list builtin types. */
8601 {
8602 tree t;
8604 {
8609 }
8610 else
8611 {
8616 }
8618 {
8623 }
8624 else
8625 {
8630 }
8631 }
8634 }
8636 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8638 static void
8640 {
8642 alias_set_type set;
8645 /* GPR size of varargs save area. */
8648 else
8651 /* FPR size of varargs save area. We don't need it if we don't pass
8652 anything in SSE registers. */
8655 else
8669 {
8677 }
8680 {
8681 machine_mode smode;
8683 rtx test;
8685 /* Now emit code to save SSE registers. The AX parameter contains number
8686 of SSE parameter registers used to call this function, though all we
8687 actually check here is the zero/non-zero status. */
8692 label));
8694 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8695 we used movdqa (i.e. TImode) instead? Perhaps even better would
8696 be if we could determine the real mode of the data, via a hook
8697 into pass_stdarg. Ignore all that for now. */
8707 {
8716 }
8719 }
8720 }
8722 static void
8724 {
8728 /* Reset to zero, as there might be a sysv vaarg used
8729 before. */
8734 {
8745 }
8746 }
8748 static void
8751 {
8753 CUMULATIVE_ARGS next_cum;
8754 tree fntype;
8756 /* This argument doesn't appear to be used anymore. Which is good,
8757 because the old code here didn't suppress rtl generation. */
8765 /* For varargs, we do not want to skip the dummy va_dcl argument.
8766 For stdargs, we do want to skip the last named argument. */
8774 else
8776 }
8778 static void
8781 tree type,
8784 {
8786 CUMULATIVE_ARGS next_cum;
8787 tree fntype;
8788 rtx save_area;
8793 /* Do nothing if we use plain pointer to argument area. */
8799 /* For varargs, we do not want to skip the dummy va_dcl argument.
8800 For stdargs, we do want to skip the last named argument. */
8814 {
8819 rtx bounds;
8823 else
8824 {
8825 rtx ldx_addr =
8832 }
8838 bnd_reg++;
8839 }
8840 }
8843 /* Checks if TYPE is of kind va_list char *. */
8845 static bool
8847 {
8848 tree canonic;
8850 /* For 32-bit it is always true. */
8856 }
8858 /* Implement va_start. */
8860 static void
8862 {
8866 tree type;
8867 rtx ovf_rtx;
8871 {
8874 /* When we are splitting the stack, we can't refer to the stack
8875 arguments using internal_arg_pointer, because they may be on
8876 the old stack. The split stack prologue will arrange to
8877 leave a pointer to the old stack arguments in a scratch
8878 register, which we here copy to a pseudo-register. The split
8879 stack prologue can't set the pseudo-register directly because
8880 it (the prologue) runs before any registers have been saved. */
8884 {
8885 rtx reg;
8899 }
8900 }
8902 /* Only 64bit target needs something special. */
8904 {
8907 else
8908 {
8918 /* Store zero bounds for va_list. */
8922 next));
8924 }
8926 }
8935 /* The following should be folded into the MEM_REF offset. */
8945 /* Count number of gp and fp argument registers used. */
8951 {
8957 }
8960 {
8966 }
8968 /* Find the overflow area. */
8972 else
8978 /* Store zero bounds for overflow area pointer. */
8987 {
8988 /* Find the register save area.
8989 Prologue of the function save it right above stack frame. */
8995 /* Store zero bounds for save area pointer. */
9002 }
9003 }
9005 /* Implement va_arg. */
9007 static tree
9010 {
9017 rtx container;
9019 tree ptrtype;
9020 machine_mode nat_mode;
9023 /* Only 64bit target needs something special. */
9047 {
9060 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9062 {
9065 }
9073 }
9075 /* Pull the value out of the saved registers. */
9080 {
9094 /* In case we are passing structure, verify that it is consecutive block
9095 on the register save area. If not we need to do moves. */
9097 {
9098 /* Verify that all registers are strictly consecutive */
9100 {
9104 {
9109 }
9110 }
9111 else
9112 {
9116 {
9121 }
9122 }
9123 }
9125 {
9128 }
9129 else
9130 {
9133 }
9135 /* First ensure that we fit completely in registers. */
9137 {
9144 }
9146 {
9154 }
9156 /* Compute index to start of area used for integer regs. */
9158 {
9159 /* int_addr = gpr + sav; */
9162 }
9164 {
9165 /* sse_addr = fpr + sav; */
9168 }
9170 {
9174 /* addr = &temp; */
9179 {
9183 tree piece_type;
9184 tree addr_type;
9185 tree daddr_type;
9194 {
9199 }
9203 else
9210 {
9213 }
9214 else
9215 {
9218 }
9225 {
9230 }
9231 else
9232 {
9233 tree copy
9238 }
9240 }
9241 }
9244 {
9248 }
9251 {
9255 }
9260 }
9262 /* ... otherwise out of the overflow area. */
9264 /* When we align parameter on stack for caller, if the parameter
9265 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9266 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9267 here with caller. */
9272 /* Care for on-stack alignment if needed. */
9275 else
9276 {
9281 }
9298 }
9299 \f
9300 /* Return true if OPNUM's MEM should be matched
9301 in movabs* patterns. */
9303 bool
9305 {
9317 }
9318 \f
9319 /* Initialize the table of extra 80387 mathematical constants. */
9321 static void
9323 {
9325 {
9331 };
9335 {
9337 /* Ensure each constant is rounded to XFmode precision. */
9340 }
9343 }
9345 /* Return non-zero if the constant is something that
9346 can be loaded with a special instruction. */
9348 int
9350 {
9353 REAL_VALUE_TYPE r;
9365 /* For XFmode constants, try to find a special 80387 instruction when
9366 optimizing for size or on those CPUs that benefit from them. */
9369 {
9378 }
9380 /* Load of the constant -0.0 or -1.0 will be split as
9381 fldz;fchs or fld1;fchs sequence. */
9388 }
9390 /* Return the opcode of the special instruction to be used to load
9391 the constant X. */
9395 {
9397 {
9417 }
9418 }
9420 /* Return the CONST_DOUBLE representing the 80387 constant that is
9421 loaded by the specified special instruction. The argument IDX
9422 matches the return value from standard_80387_constant_p. */
9424 rtx
9426 {
9433 {
9444 }
9447 XFmode);
9448 }
9450 /* Return 1 if X is all 0s and 2 if x is all 1s
9451 in supported SSE/AVX vector mode. */
9453 int
9455 {
9462 {
9483 }
9486 }
9488 /* Return the opcode of the special instruction to be used to load
9489 the constant X. */
9493 {
9495 {
9498 {
9525 }
9535 else
9540 }
9542 }
9544 /* Returns true if OP contains a symbol reference */
9546 bool
9548 {
9557 {
9559 {
9565 }
9569 }
9572 }
9574 /* Return true if it is appropriate to emit `ret' instructions in the
9575 body of a function. Do this only if the epilogue is simple, needing a
9576 couple of insns. Prior to reloading, we can't tell how many registers
9577 must be saved, so return false then. Return false if there is no frame
9578 marker to de-allocate. */
9580 bool
9582 {
9588 /* Don't allow more than 32k pop, since that's all we can do
9589 with one instruction. */
9596 }
9597 \f
9598 /* Value should be nonzero if functions must have frame pointers.
9599 Zero means the frame pointer need not be set up (and parms may
9600 be accessed via the stack pointer) in functions that seem suitable. */
9602 static bool
9604 {
9605 /* If we accessed previous frames, then the generated code expects
9606 to be able to access the saved ebp value in our frame. */
9610 /* Several x86 os'es need a frame pointer for other reasons,
9611 usually pertaining to setjmp. */
9615 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9619 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9620 allocation is 4GB. */
9624 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9625 turns off the frame pointer by default. Turn it back on now if
9626 we've not got a leaf function. */
9636 }
9638 /* Record that the current function accesses previous call frames. */
9640 void
9642 {
9644 }
9645 \f
9646 #ifndef USE_HIDDEN_LINKONCE
9647 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9648 # define USE_HIDDEN_LINKONCE 1
9649 # else
9650 # define USE_HIDDEN_LINKONCE 0
9651 # endif
9652 #endif
9656 /* Fills in the label name that should be used for a pc thunk for
9657 the given register. */
9659 static void
9661 {
9666 else
9668 }
9671 /* This function generates code for -fpic that loads %ebx with
9672 the return address of the caller and then returns. */
9674 static void
9676 {
9681 {
9683 tree decl;
9699 #if TARGET_MACHO
9701 {
9710 }
9711 else
9712 #endif
9714 {
9725 }
9726 else
9727 {
9730 }
9736 /* Make sure unwind info is emitted for the thunk if needed. */
9739 /* Pad stack IP move with 4 instructions (two NOPs count
9740 as one instruction). */
9742 {
9747 }
9758 }
9762 }
9764 /* Emit code for the SET_GOT patterns. */
9768 {
9774 {
9775 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9780 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9781 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9782 an unadorned address. */
9787 }
9792 {
9794 /* We don't need a pic base, we're not producing pic. */
9801 }
9802 else
9803 {
9812 #if TARGET_MACHO
9813 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9814 This is what will be referenced by the Mach-O PIC subsystem. */
9818 /* When we are restoring the pic base at the site of a nonlocal label,
9819 and we decided to emit the pic base above, we will still output a
9820 local label used for calculating the correction offset (even though
9821 the offset will be 0 in that case). */
9825 #endif
9826 }
9832 }
9834 /* Generate an "push" pattern for input ARG. */
9836 static rtx
9838 {
9851 stack_pointer_rtx)),
9852 arg);
9853 }
9855 /* Generate an "pop" pattern for input ARG. */
9857 static rtx
9859 {
9864 arg,
9867 stack_pointer_rtx)));
9868 }
9870 /* Return >= 0 if there is an unused call-clobbered register available
9871 for the entire function. */
9873 static unsigned int
9875 {
9882 {
9884 /* Can't use the same register for both PIC and DRAP. */
9887 else
9892 }
9895 }
9897 /* Return TRUE if we need to save REGNO. */
9899 static bool
9901 {
9904 {
9906 {
9907 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9908 _mcount in prologue. */
9911 }
9918 }
9921 {
9924 {
9930 }
9931 }
9942 }
9944 /* Return number of saved general prupose registers. */
9946 static int
9948 {
9954 nregs ++;
9956 }
9958 /* Return number of saved SSE registrers. */
9960 static int
9962 {
9970 nregs ++;
9972 }
9974 /* Given FROM and TO register numbers, say whether this elimination is
9975 allowed. If stack alignment is needed, we can only replace argument
9976 pointer with hard frame pointer, or replace frame pointer with stack
9977 pointer. Otherwise, frame pointer elimination is automatically
9978 handled and all other eliminations are valid. */
9980 static bool
9982 {
9988 else
9990 }
9992 /* Return the offset between two registers, one to be eliminated, and the other
9993 its replacement, at the start of a routine. */
9995 HOST_WIDE_INT
9997 {
10006 else
10007 {
10015 }
10016 }
10018 /* In a dynamically-aligned function, we can't know the offset from
10019 stack pointer to frame pointer, so we must ensure that setjmp
10020 eliminates fp against the hard fp (%ebp) rather than trying to
10021 index from %esp up to the top of the frame across a gap that is
10022 of unknown (at compile-time) size. */
10023 static rtx
10025 {
10027 }
10029 /* When using -fsplit-stack, the allocation routines set a field in
10030 the TCB to the bottom of the stack plus this much space, measured
10031 in bytes. */
10033 #define SPLIT_STACK_AVAILABLE 256
10035 /* Fill structure ix86_frame about frame of currently computed function. */
10037 static void
10039 {
10041 HOST_WIDE_INT offset;
10044 HOST_WIDE_INT to_allocate;
10049 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10050 function prologues and leaf. */
10054 {
10057 }
10058 /* preferred_stack_boundary is never updated for call
10059 expanded from tls descriptor. Update it here. We don't update it in
10060 expand stage because according to the comments before
10061 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10062 away. */
10065 {
10069 }
10078 /* For SEH we have to limit the amount of code movement into the prologue.
10079 At present we do this via a BLOCKAGE, at which point there's very little
10080 scheduling that can be done, which means that there's very little point
10081 in doing anything except PUSHs. */
10085 /* During reload iteration the amount of registers saved can change.
10086 Recompute the value as needed. Do not recompute when amount of registers
10087 didn't change as reload does multiple calls to the function and does not
10088 expect the decision to change within single iteration. */
10091 {
10097 /* The fast prologue uses move instead of push to save registers. This
10098 is significantly longer, but also executes faster as modern hardware
10099 can execute the moves in parallel, but can't do that for push/pop.
10101 Be careful about choosing what prologue to emit: When function takes
10102 many instructions to execute we may use slow version as well as in
10103 case function is known to be outside hot spot (this is known with
10104 feedback only). Weight the size of function by number of registers
10105 to save as it is cheap to use one or two push instructions but very
10106 slow to use many of them. */
10110 || (flag_branch_probabilities
10113 else
10116 }
10118 frame->save_regs_using_mov
10120 /* If static stack checking is enabled and done with probes,
10121 the registers need to be saved before allocating the frame. */
10124 /* Skip return address. */
10127 /* Skip pushed static chain. */
10131 /* Skip saved base pointer. */
10136 /* The traditional frame pointer location is at the top of the frame. */
10139 /* Register save area */
10143 /* On SEH target, registers are pushed just before the frame pointer
10144 location. */
10148 /* Align and set SSE register save area. */
10150 {
10151 /* The only ABI that has saved SSE registers (Win64) also has a
10152 16-byte aligned default stack, and thus we don't need to be
10153 within the re-aligned local stack frame to save them. */
10157 }
10160 /* The re-aligned stack starts here. Values before this point are not
10161 directly comparable with values below this point. In order to make
10162 sure that no value happens to be the same before and after, force
10163 the alignment computation below to add a non-zero value. */
10167 /* Va-arg area */
10171 /* Align start of frame for local function. */
10180 /* Frame pointer points here. */
10185 /* Add outgoing arguments area. Can be skipped if we eliminated
10186 all the function calls as dead code.
10187 Skipping is however impossible when function calls alloca. Alloca
10188 expander assumes that last crtl->outgoing_args_size
10189 of stack frame are unused. */
10193 {
10196 }
10197 else
10200 /* Align stack boundary. Only needed if we're calling another function
10201 or using alloca. */
10206 /* We've reached end of stack frame. */
10209 /* Size prologue needs to allocate. */
10220 {
10226 }
10227 else
10231 /* The SEH frame pointer location is near the bottom of the frame.
10232 This is enforced by the fact that the difference between the
10233 stack pointer and the frame pointer is limited to 240 bytes in
10234 the unwind data structure. */
10236 {
10237 HOST_WIDE_INT diff;
10239 /* If we can leave the frame pointer where it is, do so. Also, returns
10240 the establisher frame for __builtin_frame_address (0). */
10245 {
10246 /* Ideally we'd determine what portion of the local stack frame
10247 (within the constraint of the lowest 240) is most heavily used.
10248 But without that complication, simply bias the frame pointer
10249 by 128 bytes so as to maximize the amount of the local stack
10250 frame that is addressable with 8-bit offsets. */
10252 }
10253 }
10254 }
10256 /* This is semi-inlined memory_address_length, but simplified
10257 since we know that we're always dealing with reg+offset, and
10258 to avoid having to create and discard all that rtl. */
10262 {
10266 {
10267 /* EBP and R13 cannot be encoded without an offset. */
10269 }
10273 /* ESP and R12 must be encoded with a SIB byte. */
10275 len++;
10278 }
10280 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10281 The valid base registers are taken from CFUN->MACHINE->FS. */
10283 static rtx
10285 {
10291 {
10292 /* Choose the base register most likely to allow the most scheduling
10293 opportunities. Generally FP is valid throughout the function,
10294 while DRAP must be reloaded within the epilogue. But choose either
10295 over the SP due to increased encoding size. */
10298 {
10301 }
10303 {
10306 }
10308 {
10311 }
10312 }
10313 else
10314 {
10315 HOST_WIDE_INT toffset;
10318 /* Choose the base register with the smallest address encoding.
10319 With a tie, choose FP > DRAP > SP. */
10321 {
10325 }
10327 {
10331 {
10335 }
10336 }
10338 {
10342 {
10346 }
10347 }
10348 }
10352 }
10354 /* Emit code to save registers in the prologue. */
10356 static void
10358 {
10360 rtx insn;
10364 {
10367 }
10368 }
10370 /* Emit a single register save at CFA - CFA_OFFSET. */
10372 static void
10374 HOST_WIDE_INT cfa_offset)
10375 {
10383 /* For SSE saves, we need to indicate the 128-bit alignment. */
10394 /* When saving registers into a re-aligned local stack frame, avoid
10395 any tricky guessing by dwarf2out. */
10397 {
10401 {
10402 /* A bit of a hack. We force the DRAP register to be saved in
10403 the re-aligned stack frame, which provides us with a copy
10404 of the CFA that will last past the prologue. Install it. */
10410 }
10411 else
10412 {
10413 /* The frame pointer is a stable reference within the
10414 aligned frame. Use it. */
10421 }
10422 }
10424 /* The memory may not be relative to the current CFA register,
10425 which means that we may need to generate a new pattern for
10426 use by the unwind info. */
10428 {
10433 }
10434 }
10436 /* Emit code to save registers using MOV insns.
10437 First register is stored at CFA - CFA_OFFSET. */
10438 static void
10440 {
10445 {
10448 }
10449 }
10451 /* Emit code to save SSE registers using MOV insns.
10452 First register is stored at CFA - CFA_OFFSET. */
10453 static void
10455 {
10460 {
10463 }
10464 }
10468 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10469 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10470 Don't add the note if the previously saved value will be left untouched
10471 within stack red-zone till return, as unwinders can find the same value
10472 in the register and on the stack. */
10474 static void
10476 {
10482 {
10485 }
10486 else
10487 queued_cfa_restores
10489 }
10491 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10493 static void
10495 {
10496 rtx last;
10500 ;
10505 }
10507 /* Expand prologue or epilogue stack adjustment.
10508 The pattern exist to put a dependency on all ebp-based memory accesses.
10509 STYLE should be negative if instructions should be marked as frame related,
10510 zero if %r11 register is live and cannot be freely used and positive
10511 otherwise. */
10513 static void
10516 {
10518 rtx insn;
10525 else
10526 {
10527 rtx tmp;
10528 /* r11 is used by indirect sibcall return as well, set before the
10529 epilogue and used after the epilogue. */
10532 else
10533 {
10537 }
10543 }
10550 {
10551 rtx r;
10561 }
10563 {
10566 {
10570 }
10571 }
10574 {
10579 {
10582 }
10584 {
10587 }
10588 else
10589 {
10590 /* Else there are two possibilities: SP itself, which we set
10591 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10592 taken care of this by hand along the eh_return path. */
10595 }
10599 }
10600 }
10602 /* Find an available register to be used as dynamic realign argument
10603 pointer regsiter. Such a register will be written in prologue and
10604 used in begin of body, so it must not be
10605 1. parameter passing register.
10606 2. GOT pointer.
10607 We reuse static-chain register if it is available. Otherwise, we
10608 use DI for i386 and R13 for x86-64. We chose R13 since it has
10609 shorter encoding.
10611 Return: the regno of chosen register. */
10613 static unsigned int
10615 {
10619 {
10620 /* Use R13 for nested function or function need static chain.
10621 Since function with tail call may use any caller-saved
10622 registers in epilogue, DRAP must not use caller-saved
10623 register in such case. */
10628 }
10629 else
10630 {
10631 /* Use DI for nested function or function need static chain.
10632 Since function with tail call may use any caller-saved
10633 registers in epilogue, DRAP must not use caller-saved
10634 register in such case. */
10638 /* Reuse static chain register if it isn't used for parameter
10639 passing. */
10641 {
10645 }
10647 }
10648 }
10650 /* Return minimum incoming stack alignment. */
10652 static unsigned int
10654 {
10657 /* Prefer the one specified at command line. */
10660 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10661 if -mstackrealign is used, it isn't used for sibcall check and
10662 estimated stack alignment is 128bit. */
10664 && !TARGET_64BIT
10665 && ix86_force_align_arg_pointer
10668 else
10671 /* Incoming stack alignment can be changed on individual functions
10672 via force_align_arg_pointer attribute. We use the smallest
10673 incoming stack boundary. */
10679 /* The incoming stack frame has to be aligned at least at
10680 parm_stack_boundary. */
10684 /* Stack at entrance of main is aligned by runtime. We use the
10685 smallest incoming stack boundary. */
10693 }
10695 /* Update incoming stack boundary and estimated stack alignment. */
10697 static void
10699 {
10700 ix86_incoming_stack_boundary
10703 /* x86_64 vararg needs 16byte stack alignment for register save
10704 area. */
10709 }
10711 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10712 needed or an rtx for DRAP otherwise. */
10714 static rtx
10716 {
10721 {
10722 /* Assign DRAP to vDRAP and returns vDRAP */
10724 rtx drap_vreg;
10725 rtx arg_ptr;
10738 {
10741 }
10743 }
10744 else
10746 }
10748 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10750 static rtx
10752 {
10754 }
10757 rtx reg;
10759 };
10761 /* Return a short-lived scratch register for use on function entry.
10762 In 32-bit mode, it is valid only after the registers are saved
10763 in the prologue. This register must be released by means of
10764 release_scratch_register_on_entry once it is dead. */
10766 static void
10768 {
10774 {
10775 /* We always use R11 in 64-bit mode. */
10777 }
10778 else
10779 {
10781 bool fastcall_p
10783 bool thiscall_p
10787 int drap_regno
10790 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10791 for the static chain register. */
10795 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10796 for the static chain register. */
10801 /* ecx is the static chain register. */
10803 && !static_chain_p
10808 /* esi is the static chain register. */
10814 else
10815 {
10818 }
10819 }
10823 {
10826 }
10827 }
10829 /* Release a scratch register obtained from the preceding function. */
10831 static void
10833 {
10835 {
10839 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10845 }
10846 }
10848 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10850 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10852 static void
10854 {
10855 /* We skip the probe for the first interval + a small dope of 4 words and
10856 probe that many bytes past the specified size to maintain a protection
10857 area at the botton of the stack. */
10861 /* See if we have a constant small number of probes to generate. If so,
10862 that's the easy case. The run-time loop is made up of 11 insns in the
10863 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10864 for n # of intervals. */
10866 {
10870 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10871 values of N from 1 until it exceeds SIZE. If only one probe is
10872 needed, this will not generate any code. Then adjust and probe
10873 to PROBE_INTERVAL + SIZE. */
10875 {
10877 {
10880 }
10881 else
10888 }
10892 else
10900 /* Adjust back to account for the additional first interval. */
10904 }
10906 /* Otherwise, do the same as above, but in a loop. Note that we must be
10907 extra careful with variables wrapping around because we might be at
10908 the very top (or the very bottom) of the address space and we have
10909 to be able to handle this case properly; in particular, we use an
10910 equality test for the loop condition. */
10911 else
10912 {
10913 HOST_WIDE_INT rounded_size;
10919 /* Step 1: round SIZE to the previous multiple of the interval. */
10924 /* Step 2: compute initial and final value of the loop counter. */
10926 /* SP = SP_0 + PROBE_INTERVAL. */
10931 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10935 stack_pointer_rtx)));
10938 /* Step 3: the loop
10940 while (SP != LAST_ADDR)
10941 {
10942 SP = SP + PROBE_INTERVAL
10943 probe at SP
10944 }
10946 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10947 values of N from 1 until it is equal to ROUNDED_SIZE. */
10952 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10953 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10956 {
10961 }
10963 /* Adjust back to account for the additional first interval. */
10969 }
10973 /* Even if the stack pointer isn't the CFA register, we need to correctly
10974 describe the adjustments made to it, in particular differentiate the
10975 frame-related ones from the frame-unrelated ones. */
10977 {
10990 }
10992 /* Make sure nothing is scheduled before we are done. */
10994 }
10996 /* Adjust the stack pointer up to REG while probing it. */
11000 {
11010 /* Jump to END_LAB if SP == LAST_ADDR. */
11018 /* SP = SP + PROBE_INTERVAL. */
11022 /* Probe at SP. */
11033 }
11035 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11036 inclusive. These are offsets from the current stack pointer. */
11038 static void
11040 {
11041 /* See if we have a constant small number of probes to generate. If so,
11042 that's the easy case. The run-time loop is made up of 7 insns in the
11043 generic case while the compile-time loop is made up of n insns for n #
11044 of intervals. */
11046 {
11047 HOST_WIDE_INT i;
11049 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11050 it exceeds SIZE. If only one probe is needed, this will not
11051 generate any code. Then probe at FIRST + SIZE. */
11058 }
11060 /* Otherwise, do the same as above, but in a loop. Note that we must be
11061 extra careful with variables wrapping around because we might be at
11062 the very top (or the very bottom) of the address space and we have
11063 to be able to handle this case properly; in particular, we use an
11064 equality test for the loop condition. */
11065 else
11066 {
11073 /* Step 1: round SIZE to the previous multiple of the interval. */
11078 /* Step 2: compute initial and final value of the loop counter. */
11080 /* TEST_OFFSET = FIRST. */
11083 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11087 /* Step 3: the loop
11089 while (TEST_ADDR != LAST_ADDR)
11090 {
11091 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11092 probe at TEST_ADDR
11093 }
11095 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11096 until it is equal to ROUNDED_SIZE. */
11101 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11102 that SIZE is equal to ROUNDED_SIZE. */
11107 stack_pointer_rtx,
11112 }
11114 /* Make sure nothing is scheduled before we are done. */
11116 }
11118 /* Probe a range of stack addresses from REG to END, inclusive. These are
11119 offsets from the current stack pointer. */
11123 {
11133 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11141 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11145 /* Probe at TEST_ADDR. */
11158 }
11160 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11161 to be generated in correct form. */
11162 static void
11164 {
11165 /* Check if stack realign is really needed after reload, and
11166 stores result in cfun */
11167 unsigned int incoming_stack_boundary
11176 {
11177 /* After stack_realign_needed is finalized, we can't no longer
11178 change it. */
11181 }
11183 /* If the only reason for frame_pointer_needed is that we conservatively
11184 assumed stack realignment might be needed, but in the end nothing that
11185 needed the stack alignment had been spilled, clear frame_pointer_needed
11186 and say we don't need stack realignment. */
11188 && frame_pointer_needed
11190 && flag_omit_frame_pointer
11192 && !ix86_current_function_calls_tls_descriptor
11201 {
11203 basic_block bb;
11210 HARD_FRAME_POINTER_REGNUM);
11212 {
11217 set_up_by_prologue))
11218 {
11222 }
11223 }
11225 /* If drap has been set, but it actually isn't live at the start
11226 of the function, there is no reason to set it up. */
11228 {
11231 {
11234 }
11235 }
11236 else
11251 }
11255 }
11257 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11259 static void
11261 {
11267 {
11270 {
11276 }
11277 }
11278 }
11280 /* Expand the prologue into a bunch of separate insns. */
11282 void
11284 {
11288 HOST_WIDE_INT allocate;
11294 /* DRAP should not coexist with stack_realign_fp */
11299 /* Initialize CFA state for before the prologue. */
11303 /* Track SP offset to the CFA. We continue tracking this after we've
11304 swapped the CFA register away from SP. In the case of re-alignment
11305 this is fudged; we're interested to offsets within the local frame. */
11312 {
11313 /* We should have already generated an error for any use of
11314 ms_hook on a nested function. */
11317 /* Check if profiling is active and we shall use profiling before
11318 prologue variant. If so sorry. */
11323 /* In ix86_asm_output_function_label we emitted:
11324 8b ff movl.s %edi,%edi
11325 55 push %ebp
11326 8b ec movl.s %esp,%ebp
11328 This matches the hookable function prologue in Win32 API
11329 functions in Microsoft Windows XP Service Pack 2 and newer.
11330 Wine uses this to enable Windows apps to hook the Win32 API
11331 functions provided by Wine.
11333 What that means is that we've already set up the frame pointer. */
11337 {
11340 /* We've decided to use the frame pointer already set up.
11341 Describe this to the unwinder by pretending that both
11342 push and mov insns happen right here.
11344 Putting the unwind info here at the end of the ms_hook
11345 is done so that we can make absolutely certain we get
11346 the required byte sequence at the start of the function,
11347 rather than relying on an assembler that can produce
11348 the exact encoding required.
11350 However it does mean (in the unpatched case) that we have
11351 a 1 insn window where the asynchronous unwind info is
11352 incorrect. However, if we placed the unwind info at
11353 its correct location we would have incorrect unwind info
11354 in the patched case. Which is probably all moot since
11355 I don't expect Wine generates dwarf2 unwind info for the
11356 system libraries that use this feature. */
11362 stack_pointer_rtx);
11370 /* Note that gen_push incremented m->fs.cfa_offset, even
11371 though we didn't emit the push insn here. */
11375 }
11376 else
11377 {
11378 /* The frame pointer is not needed so pop %ebp again.
11379 This leaves us with a pristine state. */
11381 }
11382 }
11384 /* The first insn of a function that accepts its static chain on the
11385 stack is to push the register that would be filled in by a direct
11386 call. This insn will be skipped by the trampoline. */
11388 {
11392 /* We don't want to interpret this push insn as a register save,
11393 only as a stack adjustment. The real copy of the register as
11394 a save will be done later, if needed. */
11399 }
11401 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11402 of DRAP is needed and stack realignment is really needed after reload */
11404 {
11407 /* Only need to push parameter pointer reg if it is caller saved. */
11409 {
11410 /* Push arg pointer reg */
11413 }
11415 /* Grab the argument pointer. */
11422 /* Align the stack. */
11424 stack_pointer_rtx,
11428 /* Replicate the return address on the stack so that return
11429 address can be reached via (argp - 1) slot. This is needed
11430 to implement macro RETURN_ADDR_RTX and intrinsic function
11431 expand_builtin_return_addr etc. */
11437 /* For the purposes of frame and register save area addressing,
11438 we've started over with a new frame. */
11441 }
11447 {
11448 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11449 slower on all targets. Also sdb doesn't like it. */
11453 /* Push registers now, before setting the frame pointer
11454 on SEH target. */
11456 && TARGET_SEH
11458 {
11462 }
11465 {
11473 }
11474 }
11477 {
11478 /* If saving registers via PUSH, do so now. */
11480 {
11484 }
11486 /* When using red zone we may start register saving before allocating
11487 the stack frame saving one cycle of the prologue. However, avoid
11488 doing this if we have to probe the stack; at least on x86_64 the
11489 stack probe can turn into a call that clobbers a red zone location. */
11491 && (! TARGET_STACK_PROBE
11493 {
11496 }
11497 }
11500 {
11504 /* The computation of the size of the re-aligned stack frame means
11505 that we must allocate the size of the register save area before
11506 performing the actual alignment. Otherwise we cannot guarantee
11507 that there's enough storage above the realignment point. */
11514 /* Align the stack. */
11516 stack_pointer_rtx,
11519 /* For the purposes of register save area addressing, the stack
11520 pointer is no longer valid. As for the value of sp_offset,
11521 see ix86_compute_frame_layout, which we need to match in order
11522 to pass verification of stack_pointer_offset at the end. */
11525 }
11530 {
11531 /* We start to count from ARG_POINTER. */
11534 /* If it was realigned, take into account the fake frame. */
11536 {
11543 /* This over-estimates by 1 minimal-stack-alignment-unit but
11544 mitigates that by counting in the new return address slot. */
11545 current_function_dynamic_stack_size
11547 }
11550 }
11552 /* On SEH target with very large frame size, allocate an area to save
11553 SSE registers (as the very large allocation won't be described). */
11557 {
11558 HOST_WIDE_INT sse_size =
11563 /* No need to do stack checking as the area will be immediately
11564 written. */
11571 }
11573 /* The stack has already been decremented by the instruction calling us
11574 so probe if the size is non-negative to preserve the protection area. */
11576 {
11577 /* We expect the registers to be saved when probes are used. */
11581 {
11584 {
11587 }
11588 }
11589 else
11590 {
11597 {
11599 {
11602 }
11603 else
11605 }
11606 else
11607 {
11609 {
11613 }
11614 else
11616 }
11617 }
11618 }
11621 ;
11624 {
11628 }
11629 else
11630 {
11642 {
11645 /* Note that SEH directives need to continue tracking the stack
11646 pointer even after the frame pointer has been set up. */
11648 {
11656 }
11657 }
11660 {
11665 {
11673 }
11674 }
11679 /* Use the fact that AX still contains ALLOCATE. */
11681 ? gen_pro_epilogue_adjust_stack_di_sub
11688 {
11696 }
11699 /* Use stack_pointer_rtx for relative addressing so that code
11700 works for realigned stack, too. */
11702 {
11709 }
11711 {
11716 }
11717 }
11720 /* If we havn't already set up the frame pointer, do so now. */
11722 {
11734 }
11741 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11742 in PROLOGUE. */
11744 {
11750 /* Deleting already emmitted SET_GOT if exist and allocated to
11751 REAL_PIC_OFFSET_TABLE_REGNUM. */
11753 }
11756 {
11757 /* vDRAP is setup but after reload it turns out stack realign
11758 isn't necessary, here we will emit prologue to setup DRAP
11759 without stack realign adjustment */
11762 }
11764 /* Prevent instructions from being scheduled into register save push
11765 sequence when access to the redzone area is done through frame pointer.
11766 The offset between the frame pointer and the stack pointer is calculated
11767 relative to the value of the stack pointer at the end of the function
11768 prologue, and moving instructions that access redzone area via frame
11769 pointer inside push sequence violates this assumption. */
11773 /* Emit cld instruction if stringops are used in the function. */
11777 /* SEH requires that the prologue end within 256 bytes of the start of
11778 the function. Prevent instruction schedules that would extend that.
11779 Further, prevent alloca modifications to the stack pointer from being
11780 combined with prologue modifications. */
11783 }
11785 /* Emit code to restore REG using a POP insn. */
11787 static void
11789 {
11798 {
11799 /* Previously we'd represented the CFA as an expression
11800 like *(%ebp - 8). We've just popped that value from
11801 the stack, which means we need to reset the CFA to
11802 the drap register. This will remain until we restore
11803 the stack pointer. */
11807 /* This means that the DRAP register is valid for addressing too. */
11810 }
11813 {
11820 }
11822 /* When the frame pointer is the CFA, and we pop it, we are
11823 swapping back to the stack pointer as the CFA. This happens
11824 for stack frames that don't allocate other data, so we assume
11825 the stack pointer is now pointing at the return address, i.e.
11826 the function entry state, which makes the offset be 1 word. */
11828 {
11831 {
11839 }
11840 }
11841 }
11843 /* Emit code to restore saved registers using POP insns. */
11845 static void
11847 {
11853 }
11855 /* Emit code and notes for the LEAVE instruction. */
11857 static void
11859 {
11871 {
11879 }
11882 }
11884 /* Emit code to restore saved registers using MOV insns.
11885 First register is restored from CFA - CFA_OFFSET. */
11886 static void
11889 {
11895 {
11904 {
11905 /* Previously we'd represented the CFA as an expression
11906 like *(%ebp - 8). We've just popped that value from
11907 the stack, which means we need to reset the CFA to
11908 the drap register. This will remain until we restore
11909 the stack pointer. */
11913 /* This means that the DRAP register is valid for addressing. */
11915 }
11916 else
11920 }
11921 }
11923 /* Emit code to restore saved registers using MOV insns.
11924 First register is restored from CFA - CFA_OFFSET. */
11925 static void
11928 {
11933 {
11935 rtx mem;
11945 }
11946 }
11948 /* Restore function stack, frame, and registers. */
11950 void
11952 {
11968 /* The FP must be valid if the frame pointer is present. */
11973 /* We must have *some* valid pointer to the stack frame. */
11976 /* The DRAP is never valid at this point. */
11979 /* See the comment about red zone and frame
11980 pointer usage in ix86_expand_prologue. */
11987 /* Determine the CFA offset of the end of the red-zone. */
11990 {
11991 /* The red-zone begins below the return address. */
11994 /* When the register save area is in the aligned portion of
11995 the stack, determine the maximum runtime displacement that
11996 matches up with the aligned frame. */
12000 }
12002 /* Special care must be taken for the normal return case of a function
12003 using eh_return: the eax and edx registers are marked as saved, but
12004 not restored along this path. Adjust the save location to match. */
12008 /* EH_RETURN requires the use of moves to function properly. */
12011 /* SEH requires the use of pops to identify the epilogue. */
12014 /* If we're only restoring one register and sp is not valid then
12015 using a move instruction to restore the register since it's
12016 less work than reloading sp and popping the register. */
12029 && TARGET_USE_LEAVE
12033 else
12037 {
12038 /* Ensure that the entire register save area is addressable via
12039 the stack pointer, if we will restore via sp. */
12044 {
12048 style,
12050 }
12051 }
12053 /* If there are any SSE registers to restore, then we have to do it
12054 via moves, since there's obviously no pop for SSE regs. */
12060 {
12061 rtx t;
12066 /* eh_return epilogues need %ecx added to the stack pointer. */
12068 {
12071 /* Stack align doesn't work with eh_return. */
12073 /* Neither does regparm nested functions. */
12077 {
12085 /* Note that we use SA as a temporary CFA, as the return
12086 address is at the proper place relative to it. We
12087 pretend this happens at the FP restore insn because
12088 prior to this insn the FP would be stored at the wrong
12089 offset relative to SA, and after this insn we have no
12090 other reasonable register to use for the CFA. We don't
12091 bother resetting the CFA to the SP for the duration of
12092 the return insn. */
12105 }
12106 else
12107 {
12115 {
12119 UNITS_PER_WORD));
12121 }
12122 }
12125 }
12126 }
12127 else
12128 {
12129 /* SEH requires that the function end with (1) a stack adjustment
12130 if necessary, (2) a sequence of pops, and (3) a return or
12131 jump instruction. Prevent insns from the function body from
12132 being scheduled into this sequence. */
12134 {
12135 /* Prevent a catch region from being adjacent to the standard
12136 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12137 several other flags that would be interesting to test are
12138 not yet set up. */
12141 else
12143 }
12145 /* First step is to deallocate the stack frame so that we can
12146 pop the registers. Also do it on SEH target for very large
12147 frame as the emitted instructions aren't allowed by the ABI in
12148 epilogues. */
12150 || (TARGET_SEH
12153 {
12158 }
12160 {
12164 style,
12166 }
12169 }
12171 /* If we used a stack pointer and haven't already got rid of it,
12172 then do so now. */
12174 {
12175 /* If the stack pointer is valid and pointing at the frame
12176 pointer store address, then we only need a pop. */
12179 /* Leave results in shorter dependency chains on CPUs that are
12180 able to grok it fast. */
12185 else
12186 {
12188 hard_frame_pointer_rtx,
12191 }
12192 }
12195 {
12197 rtx insn;
12223 }
12225 /* At this point the stack pointer must be valid, and we must have
12226 restored all of the registers. We may not have deallocated the
12227 entire stack frame. We've delayed this until now because it may
12228 be possible to merge the local stack deallocation with the
12229 deallocation forced by ix86_static_chain_on_stack. */
12234 {
12238 }
12239 else
12242 /* Sibcall epilogues don't want a return instruction. */
12244 {
12247 }
12250 {
12253 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12254 address, do explicit add, and jump indirectly to the caller. */
12257 {
12259 rtx insn;
12261 /* There is no "pascal" calling convention in any 64bit ABI. */
12278 }
12279 else
12281 }
12282 else
12285 /* Restore the state back to the state from the prologue,
12286 so that it's correct for the next epilogue. */
12288 }
12290 /* Reset from the function's potential modifications. */
12292 static void
12294 {
12298 #if TARGET_MACHO
12299 /* Mach-O doesn't support labels at the end of objects, so if
12300 it looks like we might want one, insert a NOP. */
12301 {
12307 {
12308 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12309 notes only, instead set their CODE_LABEL_NUMBER to -1,
12310 otherwise there would be code generation differences
12311 in between -g and -g0. */
12315 }
12325 }
12326 #endif
12328 }
12330 /* Return a scratch register to use in the split stack prologue. The
12331 split stack prologue is used for -fsplit-stack. It is the first
12332 instructions in the function, even before the regular prologue.
12333 The scratch register can be any caller-saved register which is not
12334 used for parameters or for the static chain. */
12336 static unsigned int
12338 {
12341 else
12342 {
12355 {
12357 {
12361 }
12363 }
12365 {
12369 }
12371 {
12374 else
12375 {
12377 {
12381 }
12383 }
12384 }
12385 else
12386 {
12387 /* FIXME: We could make this work by pushing a register
12388 around the addition and comparison. */
12391 }
12392 }
12393 }
12395 /* A SYMBOL_REF for the function which allocates new stackspace for
12396 -fsplit-stack. */
12400 /* A SYMBOL_REF for the more stack function when using the large
12401 model. */
12405 /* Handle -fsplit-stack. These are the first instructions in the
12406 function, even before the regular prologue. */
12408 void
12410 {
12412 HOST_WIDE_INT allocate;
12418 rtx fn;
12426 /* This is the label we will branch to if we have enough stack
12427 space. We expect the basic block reordering pass to reverse this
12428 branch if optimizing, so that we branch in the unlikely case. */
12431 /* We need to compare the stack pointer minus the frame size with
12432 the stack boundary in the TCB. The stack boundary always gives
12433 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12434 can compare directly. Otherwise we need to do an addition. */
12437 UNSPEC_STACK_CHECK);
12442 else
12443 {
12445 rtx offset;
12447 /* We need a scratch register to hold the stack pointer minus
12448 the required frame size. Since this is the very start of the
12449 function, the scratch register can be any caller-saved
12450 register which is not used for parameters. */
12457 {
12458 /* We don't use ix86_gen_add3 in this case because it will
12459 want to split to lea, but when not optimizing the insn
12460 will not be split after this point. */
12463 offset)));
12464 }
12465 else
12466 {
12469 stack_pointer_rtx));
12470 }
12472 }
12478 /* Mark the jump as very likely to be taken. */
12483 {
12486 }
12489 /* Get more stack space. We pass in the desired stack space and the
12490 size of the arguments to copy to the new stack. In 32-bit mode
12491 we push the parameters; __morestack will return on a new stack
12492 anyhow. In 64-bit mode we pass the parameters in r10 and
12493 r11. */
12498 {
12504 /* If this function uses a static chain, it will be in %r10.
12505 Preserve it across the call to __morestack. */
12507 {
12508 rtx rax;
12513 }
12517 {
12518 HOST_WIDE_INT argval;
12521 /* When using the large model we need to load the address
12522 into a register, and we've run out of registers. So we
12523 switch to a different calling convention, and we call a
12524 different function: __morestack_large. We pass the
12525 argument size in the upper 32 bits of r10 and pass the
12526 frame size in the lower 32 bits. */
12531 {
12532 split_stack_fn_large =
12535 }
12537 {
12539 rtx x;
12548 UNSPEC_GOT);
12554 }
12555 else
12562 }
12563 else
12564 {
12568 }
12571 }
12572 else
12573 {
12576 }
12582 /* In order to make call/return prediction work right, we now need
12583 to execute a return instruction. See
12584 libgcc/config/i386/morestack.S for the details on how this works.
12586 For flow purposes gcc must not see this as a return
12587 instruction--we need control flow to continue at the subsequent
12588 label. Therefore, we use an unspec. */
12592 /* If we are in 64-bit mode and this function uses a static chain,
12593 we saved %r10 in %rax before calling _morestack. */
12598 /* If this function calls va_start, we need to store a pointer to
12599 the arguments on the old stack, because they may not have been
12600 all copied to the new stack. At this point the old stack can be
12601 found at the frame pointer value used by __morestack, because
12602 __morestack has set that up before calling back to us. Here we
12603 store that pointer in a scratch register, and in
12604 ix86_expand_prologue we store the scratch register in a stack
12605 slot. */
12607 {
12609 rtx frame_reg;
12616 /* 64-bit:
12617 fp -> old fp value
12618 return address within this function
12619 return address of caller of this function
12620 stack arguments
12621 So we add three words to get to the stack arguments.
12623 32-bit:
12624 fp -> old fp value
12625 return address within this function
12626 first argument to __morestack
12627 second argument to __morestack
12628 return address of caller of this function
12629 stack arguments
12630 So we add five words to get to the stack arguments.
12631 */
12642 }
12647 /* If this function calls va_start, we now have to set the scratch
12648 register for the case where we do not call __morestack. In this
12649 case we need to set it based on the stack pointer. */
12651 {
12658 }
12659 }
12661 /* We may have to tell the dataflow pass that the split stack prologue
12662 is initializing a scratch register. */
12664 static void
12666 {
12668 {
12671 }
12672 }
12673 \f
12674 /* Extract the parts of an RTL expression that is a valid memory address
12675 for an instruction. Return 0 if the structure of the address is
12676 grossly off. Return -1 if the address contains ASHIFT, so it is not
12677 strictly valid, but still used for computing length of lea instruction. */
12679 int
12681 {
12686 rtx tmp;
12690 /* Allow zero-extended SImode addresses,
12691 they will be emitted with addr32 prefix. */
12693 {
12696 {
12700 }
12703 {
12710 }
12711 }
12713 /* Allow SImode subregs of DImode addresses,
12714 they will be emitted with addr32 prefix. */
12716 {
12719 {
12723 }
12724 }
12729 {
12732 else
12734 }
12736 {
12741 do
12742 {
12747 }
12754 {
12757 {
12782 /* FALLTHRU */
12786 && TARGET_TLS_DIRECT_SEG_REFS
12789 else
12796 /* FALLTHRU */
12803 else
12818 }
12819 }
12820 }
12822 {
12825 }
12827 {
12828 /* We're called for lea too, which implements ashift on occasion. */
12838 }
12839 else
12843 {
12845 ;
12848 ;
12849 else
12851 }
12853 /* Extract the integral value of scale. */
12855 {
12859 }
12864 /* Avoid useless 0 displacement. */
12868 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12873 {
12876 }
12878 /* Special case: %ebp cannot be encoded as a base without a displacement.
12879 Similarly %r13. */
12881 && base_reg
12890 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12891 Avoid this by transforming to [%esi+0].
12892 Reload calls address legitimization without cfun defined, so we need
12893 to test cfun for being non-NULL. */
12899 /* Special case: encode reg+reg instead of reg*2. */
12903 /* Special case: scaling cannot be encoded without base or displacement. */
12914 }
12915 \f
12916 /* Return cost of the memory address x.
12917 For i386, it is better to use a complex address than let gcc copy
12918 the address into a reg and make a new pseudo. But not if the address
12919 requires to two regs - that would mean more pseudos with longer
12920 lifetimes. */
12921 static int
12923 {
12935 /* Attempt to minimize number of registers in the address by increasing
12936 address cost for each used register. We don't increase address cost
12937 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
12938 is not invariant itself it most likely means that base or index is not
12939 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
12940 which is not profitable for x86. */
12944 || !pic_offset_table_rtx
12947 cost++;
12952 || !pic_offset_table_rtx
12955 cost++;
12957 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12958 since it's predecode logic can't detect the length of instructions
12959 and it degenerates to vector decoded. Increase cost of such
12960 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12961 to split such addresses or even refuse such addresses at all.
12963 Following addressing modes are affected:
12964 [base+scale*index]
12965 [scale*index+disp]
12966 [base+index]
12968 The first and last case may be avoidable by explicitly coding the zero in
12969 memory address, but I don't have AMD-K6 machine handy to check this
12970 theory. */
12979 }
12980 \f
12981 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12982 this is used for to form addresses to local data when -fPIC is in
12983 use. */
12985 static bool
12987 {
12990 }
12992 /* Determine if a given RTX is a valid constant. We already know this
12993 satisfies CONSTANT_P. */
12995 static bool
12997 {
12998 /* Pointer bounds constants are not valid. */
13003 {
13008 {
13012 }
13017 /* Only some unspecs are valid as "constants". */
13020 {
13036 }
13038 /* We must have drilled down to a symbol. */
13043 /* FALLTHRU */
13046 /* TLS symbols are never valid. */
13050 /* DLLIMPORT symbols are never valid. */
13055 #if TARGET_MACHO
13056 /* mdynamic-no-pic */
13059 #endif
13075 }
13077 /* Otherwise we handle everything else in the move patterns. */
13079 }
13081 /* Determine if it's legal to put X into the constant pool. This
13082 is not possible for the address of thread-local symbols, which
13083 is checked above. */
13085 static bool
13087 {
13088 /* We can always put integral constants and vectors in memory. */
13090 {
13098 }
13100 }
13102 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13103 otherwise zero. */
13105 static bool
13107 {
13113 }
13116 /* Nonzero if the constant value X is a legitimate general operand
13117 when generating PIC code. It is given that flag_pic is on and
13118 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
13120 bool
13122 {
13123 rtx inner;
13126 {
13133 /* Only some unspecs are valid as "constants". */
13136 {
13149 }
13150 /* FALLTHRU */
13158 }
13159 }
13161 /* Determine if a given CONST RTX is a valid memory displacement
13162 in PIC mode. */
13164 bool
13166 {
13169 /* In 64bit mode we can allow direct addresses of symbols and labels
13170 when they are not dynamic symbols. */
13172 {
13176 {
13200 /* FALLTHRU */
13203 /* TLS references should always be enclosed in UNSPEC.
13204 The dllimported symbol needs always to be resolved. */
13210 {
13218 /* Function-symbols need to be resolved only for
13219 large-model.
13220 For the small-model we don't need to resolve anything
13221 here. */
13226 /* Non-external symbols don't need to be resolved for
13227 large, and medium-model. */
13232 }
13235 || (HAVE_LD_PIE_COPYRELOC
13236 && flag_pie
13245 }
13246 }
13252 {
13253 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13254 of GOT tables. We should not need these anyway. */
13266 }
13270 {
13275 }
13284 {
13288 /* We need to check for both symbols and labels because VxWorks loads
13289 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13290 details. */
13294 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13295 While ABI specify also 32bit relocation but we don't produce it in
13296 small PIC model at all. */
13318 }
13321 }
13323 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13324 replace the input X, or the original X if no replacement is called for.
13325 The output parameter *WIN is 1 if the calling macro should goto WIN,
13326 0 if it should not. */
13328 bool
13331 {
13332 /* Reload can generate:
13334 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13335 (reg:DI 97))
13336 (reg:DI 2 cx))
13338 This RTX is rejected from ix86_legitimate_address_p due to
13339 non-strictness of base register 97. Following this rejection,
13340 reload pushes all three components into separate registers,
13341 creating invalid memory address RTX.
13343 Following code reloads only the invalid part of the
13344 memory address RTX. */
13350 {
13356 {
13361 }
13365 {
13370 }
13374 }
13377 }
13379 /* Determine if op is suitable RTX for an address register.
13380 Return naked register if a register or a register subreg is
13381 found, otherwise return NULL_RTX. */
13383 static rtx
13385 {
13388 /* Only SImode or DImode registers can form the address. */
13395 {
13403 /* Don't allow SUBREGs that span more than a word. It can
13404 lead to spill failures when the register is one word out
13405 of a two word structure. */
13409 /* Allow only SUBREGs of non-eliminable hard registers. */
13412 }
13414 /* Op is not a register. */
13416 }
13418 /* Recognizes RTL expressions that are valid memory addresses for an
13419 instruction. The MODE argument is the machine mode for the MEM
13420 expression that wants to use this address.
13422 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13423 convert common non-canonical forms to canonical form so that they will
13424 be recognized. */
13426 static bool
13428 {
13431 HOST_WIDE_INT scale;
13435 /* Decomposition failed. */
13444 /* Validate base register. */
13446 {
13454 /* Base is not valid. */
13456 }
13458 /* Validate index register. */
13460 {
13468 /* Index is not valid. */
13470 }
13472 /* Index and base should have the same mode. */
13477 /* Address override works only on the (%reg) part of %fs:(%reg). */
13483 /* Validate scale factor. */
13485 {
13487 /* Scale without index. */
13491 /* Scale is not a valid multiplier. */
13493 }
13495 /* Validate displacement. */
13497 {
13502 {
13503 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13504 used. While ABI specify also 32bit relocations, we don't produce
13505 them at all and use IP relative instead. */
13512 /* 64bit address unspec. */
13532 /* Invalid address unspec. */
13534 }
13537 && (flag_pic
13538 || (TARGET_MACHO
13539 #if TARGET_MACHO
13540 && MACHOPIC_INDIRECT
13542 #endif
13543 )))
13544 {
13546 is_legitimate_pic:
13548 {
13549 /* foo@dtpoff(%rX) is ok. */
13556 /* Non-constant pic memory reference. */
13558 }
13561 /* Displacement is an invalid pic construct. */
13563 #if TARGET_MACHO
13566 /* displacment must be referenced via non_lazy_pointer */
13568 #endif
13570 /* This code used to verify that a symbolic pic displacement
13571 includes the pic_offset_table_rtx register.
13573 While this is good idea, unfortunately these constructs may
13574 be created by "adds using lea" optimization for incorrect
13575 code like:
13577 int a;
13578 int foo(int i)
13579 {
13580 return *(&a+i);
13581 }
13583 This code is nonsensical, but results in addressing
13584 GOT table with pic_offset_table_rtx base. We can't
13585 just refuse it easily, since it gets matched by
13586 "addsi3" pattern, that later gets split to lea in the
13587 case output register differs from input. While this
13588 can be handled by separate addsi pattern for this case
13589 that never results in lea, this seems to be easier and
13590 correct fix for crash to disable this test. */
13591 }
13598 /* Displacement is not constant. */
13602 /* Displacement is out of range. */
13604 /* In x32 mode, constant addresses are sign extended to 64bit, so
13605 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13610 }
13612 /* Everything looks valid. */
13614 }
13616 /* Determine if a given RTX is a valid constant address. */
13618 bool
13620 {
13622 }
13623 \f
13624 /* Return a unique alias set for the GOT. */
13626 static alias_set_type
13628 {
13633 }
13635 /* Set regs_ever_live for PIC base address register
13636 to true if required. */
13637 static void
13639 {
13642 }
13644 /* Return a legitimate reference for ORIG (an address) using the
13645 register REG. If REG is 0, a new pseudo is generated.
13647 There are two types of references that must be handled:
13649 1. Global data references must load the address from the GOT, via
13650 the PIC reg. An insn is emitted to do this load, and the reg is
13651 returned.
13653 2. Static data references, constant pool addresses, and code labels
13654 compute the address as an offset from the GOT, whose base is in
13655 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13656 differentiate them from global data objects. The returned
13657 address is the PIC reg + an unspec constant.
13659 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13660 reg also appears in the address. */
13662 static rtx
13664 {
13668 #if TARGET_MACHO
13670 {
13673 /* Use the generic Mach-O PIC machinery. */
13675 }
13676 #endif
13679 {
13683 }
13689 {
13690 rtx tmpreg;
13691 /* This symbol may be referenced via a displacement from the PIC
13692 base address (@GOTOFF). */
13698 {
13700 UNSPEC_GOTOFF);
13702 }
13703 else
13708 else
13713 {
13717 }
13718 else
13720 }
13722 {
13723 /* This symbol may be referenced via a displacement from the PIC
13724 base address (@GOTOFF). */
13730 {
13732 UNSPEC_GOTOFF);
13734 }
13735 else
13741 {
13744 }
13745 }
13747 /* We can't use @GOTOFF for text labels on VxWorks;
13748 see gotoff_operand. */
13750 {
13755 /* For x64 PE-COFF there is no GOT table. So we use address
13756 directly. */
13758 {
13766 }
13768 {
13776 /* Use directly gen_movsi, otherwise the address is loaded
13777 into register for CSE. We don't want to CSE this addresses,
13778 instead we CSE addresses from the GOT table, so skip this. */
13781 }
13782 else
13783 {
13784 /* This symbol must be referenced via a load from the
13785 Global Offset Table (@GOT). */
13800 }
13801 }
13802 else
13803 {
13806 {
13808 {
13811 }
13812 else
13814 }
13816 {
13819 /* We must match stuff we generate before. Assume the only
13820 unspecs that can get here are ours. Not that we could do
13821 anything with them anyway.... */
13827 }
13829 {
13832 /* Check first to see if this is a constant offset from a @GOTOFF
13833 symbol reference. */
13836 {
13838 {
13841 UNSPEC_GOTOFF);
13847 {
13850 }
13851 }
13852 else
13853 {
13856 {
13860 }
13861 }
13862 }
13863 else
13864 {
13867 new_rtx
13871 {
13874 {
13877 new_rtx
13879 }
13880 else
13882 }
13883 else
13884 {
13885 /* For %rip addressing, we have to use just disp32, not
13886 base nor index. */
13893 {
13896 }
13898 }
13899 }
13900 }
13901 }
13903 }
13904 \f
13905 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13907 static rtx
13909 {
13913 {
13918 }
13924 }
13926 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13930 static rtx
13932 {
13934 {
13940 }
13943 {
13945 UNSPEC_PLTOFF);
13948 }
13951 }
13953 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13957 rtx
13959 {
13961 {
13962 ix86_tls_module_base_symbol
13967 }
13970 }
13972 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13973 false if we expect this to be used for a memory address and true if
13974 we expect to load the address into a register. */
13976 static rtx
13978 {
13984 /* Fall back to global dynamic model if tool chain cannot support local
13985 dynamic. */
13992 {
13997 {
14000 else
14001 {
14004 }
14005 }
14008 {
14011 else
14021 }
14022 else
14023 {
14027 {
14032 emit_call_insn
14042 }
14043 else
14045 }
14052 {
14055 else
14056 {
14059 }
14060 }
14063 {
14068 else
14074 }
14075 else
14076 {
14080 {
14083 rtx eqv;
14086 emit_call_insn
14091 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14092 share the LD_BASE result with other LD model accesses. */
14094 UNSPEC_TLS_LD_BASE);
14098 }
14099 else
14101 }
14109 {
14116 }
14121 {
14123 {
14124 /* The Sun linker took the AMD64 TLS spec literally
14125 and can only handle %rax as destination of the
14126 initial executable code sequence. */
14131 }
14133 /* Generate DImode references to avoid %fs:(%reg32)
14134 problems and linker IE->LE relaxation bug. */
14138 }
14140 {
14144 }
14146 {
14150 }
14151 else
14152 {
14155 }
14165 {
14170 }
14171 else
14172 {
14176 }
14186 {
14190 }
14191 else
14192 {
14196 }
14201 }
14204 }
14206 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14207 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14208 unique refptr-DECL symbol corresponding to symbol DECL. */
14211 {
14215 {
14217 }
14219 static void
14221 {
14227 else
14229 }
14230 };
14234 static tree
14236 {
14242 tree to;
14243 rtx rtl;
14270 else
14283 {
14285 #ifdef SUB_TARGET_RECORD_STUB
14287 #endif
14288 }
14297 }
14299 /* Expand SYMBOL into its corresponding far-addresse symbol.
14300 WANT_REG is true if we require the result be a register. */
14302 static rtx
14304 {
14305 tree imp_decl;
14306 rtx x;
14315 }
14317 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14318 true if we require the result be a register. */
14320 static rtx
14322 {
14323 tree imp_decl;
14324 rtx x;
14333 }
14335 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14336 is true if we require the result be a register. */
14338 static rtx
14340 {
14345 {
14352 {
14355 }
14356 }
14372 {
14375 }
14377 }
14379 /* Try machine-dependent ways of modifying an illegitimate address
14380 to be legitimate. If we find one, return the new, valid address.
14381 This macro is used in only one place: `memory_address' in explow.c.
14383 OLDX is the address as it was before break_out_memory_refs was called.
14384 In some cases it is useful to look at this to decide what needs to be done.
14386 It is always safe for this macro to do nothing. It exists to recognize
14387 opportunities to optimize the output.
14389 For the 80386, we handle X+REG by loading X into a register R and
14390 using R+REG. R will go in a general reg and indexing will be used.
14391 However, if REG is a broken-out memory address or multiplication,
14392 nothing needs to be done because REG can certainly go in a general reg.
14394 When -fpic is used, special handling is needed for symbolic references.
14395 See comments by legitimize_pic_address in i386.c for details. */
14397 static rtx
14399 {
14410 {
14414 }
14417 {
14421 }
14426 #if TARGET_MACHO
14429 #endif
14431 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14435 {
14440 }
14443 {
14444 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14449 {
14455 }
14460 {
14466 }
14468 /* Put multiply first if it isn't already. */
14470 {
14473 }
14475 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14476 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14477 created by virtual register instantiation, register elimination, and
14478 similar optimizations. */
14480 {
14486 }
14488 /* Canonicalize
14489 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14490 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14495 {
14496 rtx constant;
14500 {
14503 }
14505 {
14508 }
14509 else
14513 {
14520 }
14521 }
14527 {
14530 }
14533 {
14536 }
14544 {
14547 }
14553 {
14557 {
14560 }
14564 }
14567 {
14571 {
14574 }
14578 }
14579 }
14582 }
14583 \f
14584 /* Print an integer constant expression in assembler syntax. Addition
14585 and subtraction are the only arithmetic that may appear in these
14586 expressions. FILE is the stdio stream to write to, X is the rtx, and
14587 CODE is the operand print code from the output string. */
14589 static void
14591 {
14595 {
14604 else
14605 {
14608 /* Mark the decl as referenced so that cgraph will
14609 output the function. */
14613 #if TARGET_MACHO
14617 #endif
14619 }
14627 /* FALLTHRU */
14638 /* This used to output parentheses around the expression,
14639 but that does not work on the 386 (either ATT or BSD assembler). */
14645 {
14646 /* We can use %d if the number is <32 bits and positive. */
14651 else
14653 }
14654 else
14655 /* We can't handle floating point constants;
14656 TARGET_PRINT_OPERAND must handle them. */
14661 /* Some assemblers need integer constants to appear first. */
14663 {
14667 }
14668 else
14669 {
14674 }
14689 {
14693 }
14698 {
14717 /* FIXME: This might be @TPOFF in Sun ld too. */
14726 else
14736 else
14742 #if TARGET_MACHO
14747 #endif
14751 }
14756 }
14757 }
14759 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14760 We need to emit DTP-relative relocations. */
14762 static void ATTRIBUTE_UNUSED
14764 {
14769 {
14777 }
14778 }
14780 /* Return true if X is a representation of the PIC register. This copes
14781 with calls from ix86_find_base_term, where the register might have
14782 been replaced by a cselib value. */
14784 static bool
14786 {
14793 {
14801 }
14802 else
14804 }
14806 /* Helper function for ix86_delegitimize_address.
14807 Attempt to delegitimize TLS local-exec accesses. */
14809 static rtx
14811 {
14836 {
14841 }
14847 }
14849 /* In the name of slightly smaller debug output, and to cater to
14850 general assembler lossage, recognize PIC+GOTOFF and turn it back
14851 into a direct symbol reference.
14853 On Darwin, this is necessary to avoid a crash, because Darwin
14854 has a different PIC label for each routine but the DWARF debugging
14855 information is not associated with any particular routine, so it's
14856 necessary to remove references to the PIC label from RTL stored by
14857 the DWARF output code. */
14859 static rtx
14861 {
14863 /* addend is NULL or some rtx if x is something+GOTOFF where
14864 something doesn't include the PIC register. */
14866 /* reg_addend is NULL or a multiple of some register. */
14868 /* const_addend is NULL or a const_int. */
14870 /* This is the result, or NULL. */
14879 {
14886 {
14892 }
14899 {
14902 {
14907 }
14909 }
14914 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14915 and -mcmodel=medium -fpic. */
14916 }
14923 /* %ebx + GOT/GOTOFF */
14924 ;
14926 {
14927 /* %ebx + %reg * scale + GOT/GOTOFF */
14933 else
14934 {
14937 }
14938 }
14939 else
14945 {
14948 }
14969 {
14970 /* If the rest of original X doesn't involve the PIC register, add
14971 addend and subtract pic_offset_table_rtx. This can happen e.g.
14972 for code like:
14973 leal (%ebx, %ecx, 4), %ecx
14974 ...
14975 movl foo@GOTOFF(%ecx), %edx
14976 in which case we return (%ecx - %ebx) + foo
14977 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14978 and reload has completed. */
14982 pic_offset_table_rtx),
14983 result);
14985 {
14989 }
14990 else
14992 }
14994 {
14998 }
15000 }
15002 /* If X is a machine specific address (i.e. a symbol or label being
15003 referenced as a displacement from the GOT implemented using an
15004 UNSPEC), then return the base term. Otherwise return X. */
15006 rtx
15008 {
15009 rtx term;
15012 {
15026 }
15029 }
15030 \f
15031 static void
15034 {
15038 {
15041 }
15046 {
15049 {
15068 }
15072 {
15091 }
15098 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15099 Those same assemblers have the same but opposite lossage on cmov. */
15102 else
15107 {
15120 }
15127 else
15132 {
15145 }
15152 else
15162 else
15173 }
15175 }
15177 /* Print the name of register X to FILE based on its machine mode and number.
15178 If CODE is 'w', pretend the mode is HImode.
15179 If CODE is 'b', pretend the mode is QImode.
15180 If CODE is 'k', pretend the mode is SImode.
15181 If CODE is 'q', pretend the mode is DImode.
15182 If CODE is 'x', pretend the mode is V4SFmode.
15183 If CODE is 't', pretend the mode is V8SFmode.
15184 If CODE is 'g', pretend the mode is V16SFmode.
15185 If CODE is 'h', pretend the reg is the 'high' byte register.
15186 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15187 If CODE is 'd', duplicate the operand for AVX instruction.
15188 */
15190 void
15192 {
15201 {
15205 }
15232 else
15235 /* Irritatingly, AMD extended registers use different naming convention
15236 from the normal registers: "r%d[bwd]" */
15238 {
15243 {
15257 /* no suffix */
15262 }
15264 }
15268 {
15271 {
15274 }
15275 /* FALLTHRU */
15281 /* FALLTHRU */
15284 normal:
15299 {
15304 }
15307 {
15312 }
15316 }
15320 {
15323 else
15325 }
15326 }
15328 /* Meaning of CODE:
15329 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15330 C -- print opcode suffix for set/cmov insn.
15331 c -- like C, but print reversed condition
15332 F,f -- likewise, but for floating-point.
15333 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15334 otherwise nothing
15335 R -- print embeded rounding and sae.
15336 r -- print only sae.
15337 z -- print the opcode suffix for the size of the current operand.
15338 Z -- likewise, with special suffixes for x87 instructions.
15339 * -- print a star (in certain assembler syntax)
15340 A -- print an absolute memory reference.
15341 E -- print address with DImode register names if TARGET_64BIT.
15342 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15343 s -- print a shift double count, followed by the assemblers argument
15344 delimiter.
15345 b -- print the QImode name of the register for the indicated operand.
15346 %b0 would print %al if operands[0] is reg 0.
15347 w -- likewise, print the HImode name of the register.
15348 k -- likewise, print the SImode name of the register.
15349 q -- likewise, print the DImode name of the register.
15350 x -- likewise, print the V4SFmode name of the register.
15351 t -- likewise, print the V8SFmode name of the register.
15352 g -- likewise, print the V16SFmode name of the register.
15353 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15354 y -- print "st(0)" instead of "st" as a register.
15355 d -- print duplicated register operand for AVX instruction.
15356 D -- print condition for SSE cmp instruction.
15357 P -- if PIC, print an @PLT suffix.
15358 p -- print raw symbol name.
15359 X -- don't print any sort of PIC '@' suffix for a symbol.
15360 & -- print some in-use local-dynamic symbol name.
15361 H -- print a memory address offset by 8; used for sse high-parts
15362 Y -- print condition for XOP pcom* instruction.
15363 + -- print a branch hint as 'cs' or 'ds' prefix
15364 ; -- print a semicolon (after prefixes due to bug in older gas).
15365 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15366 @ -- print a segment register of thread base pointer load
15367 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15368 ! -- print MPX prefix for jxx/call/ret instructions if required.
15369 */
15371 void
15373 {
15375 {
15377 {
15380 {
15386 /* Intel syntax. For absolute addresses, registers should not
15387 be surrounded by braces. */
15389 {
15394 }
15399 }
15405 /* Wrap address in an UNSPEC to declare special handling. */
15443 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15448 {
15462 output_operand_lossage
15465 }
15468 #endif
15473 {
15474 /* Opcodes don't get size suffixes if using Intel opcodes. */
15479 {
15497 output_operand_lossage
15500 }
15501 }
15504 warning
15506 /* FALLTHRU */
15509 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15514 {
15516 {
15518 #ifdef HAVE_AS_IX86_FILDS
15520 #endif
15528 #ifdef HAVE_AS_IX86_FILDQ
15530 #else
15532 #endif
15537 }
15538 }
15540 {
15541 /* 387 opcodes don't get size suffixes
15542 if the operands are registers. */
15547 {
15563 }
15564 }
15565 else
15566 {
15567 output_operand_lossage
15570 }
15572 output_operand_lossage
15593 {
15596 }
15601 {
15652 }
15656 /* Little bit of braindamage here. The SSE compare instructions
15657 does use completely different names for the comparisons that the
15658 fp conditional moves. */
15660 {
15663 {
15666 }
15672 {
15675 }
15681 {
15684 }
15693 {
15696 }
15702 {
15705 }
15711 {
15714 }
15725 }
15730 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15733 #endif
15738 {
15742 }
15746 file);
15751 {
15755 }
15756 /* It doesn't actually matter what mode we use here, as we're
15757 only going to use this for printing. */
15759 /* Output 'qword ptr' for intel assembler dialect. */
15768 #ifdef HAVE_AS_IX86_HLE
15770 #else
15772 #endif
15774 #ifdef HAVE_AS_IX86_HLE
15776 #else
15778 #endif
15779 /* We do not want to print value of the operand. */
15808 {
15823 }
15836 {
15841 else
15844 }
15847 {
15848 rtx x;
15857 {
15862 {
15864 bool cputaken
15867 /* Emit hints only in the case default branch prediction
15868 heuristics would fail. */
15870 {
15871 /* We use 3e (DS) prefix for taken branches and
15872 2e (CS) prefix for not taken branches. */
15875 else
15877 }
15878 }
15879 }
15881 }
15884 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15886 #endif
15893 /* The kernel uses a different segment register for performance
15894 reasons; a system call would not have to trash the userspace
15895 segment register, which would be expensive. */
15898 else
15918 }
15919 }
15925 {
15926 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15929 {
15932 {
15941 else
15948 }
15950 /* Check for explicit size override (codes 'b', 'w', 'k',
15951 'q' and 'x') */
15965 }
15968 /* Avoid (%rip) for call operands. */
15974 else
15976 }
15979 {
15980 REAL_VALUE_TYPE r;
15988 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15992 else
15994 }
15997 {
15998 REAL_VALUE_TYPE r;
16007 }
16009 /* These float cases don't actually occur as immediate operands. */
16011 {
16016 }
16018 else
16019 {
16020 /* We have patterns that allow zero sets of memory, for instance.
16021 In 64-bit mode, we should probably support all 8-byte vectors,
16022 since we can in fact encode that into an immediate. */
16024 {
16027 }
16030 {
16032 {
16035 }
16038 {
16041 else
16043 }
16044 }
16049 else
16051 }
16052 }
16054 static bool
16056 {
16059 }
16060 \f
16061 /* Print a memory operand whose address is ADDR. */
16063 static void
16065 {
16074 {
16081 }
16083 {
16087 }
16089 {
16093 {
16096 }
16099 }
16101 {
16106 }
16107 else
16118 {
16129 }
16131 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16133 {
16145 }
16147 {
16148 /* Displacement only requires special attention. */
16151 {
16155 }
16158 else
16160 }
16161 else
16162 {
16163 /* Print SImode register names to force addr32 prefix. */
16165 {
16166 #ifdef ENABLE_CHECKING
16169 {
16180 }
16181 #endif
16184 }
16186 && TARGET_X32
16187 && disp
16190 {
16191 /* X32 runs in 64-bit mode, where displacement, DISP, in
16192 address DISP(%r64), is encoded as 32-bit immediate sign-
16193 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16194 address is %r64 + 0xffffffffbffffd00. When %r64 <
16195 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16196 which is invalid for x32. The correct address is %r64
16197 - 0x40000300 == 0xf7ffdd64. To properly encode
16198 -0x40000300(%r64) for x32, we zero-extend negative
16199 displacement by forcing addr32 prefix which truncates
16200 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16201 zero-extend all negative displacements, including -1(%rsp).
16202 However, for small negative displacements, sign-extension
16203 won't cause overflow. We only zero-extend negative
16204 displacements if they < -16*1024*1024, which is also used
16205 to check legitimate address displacements for PIC. */
16207 }
16210 {
16212 {
16217 else
16219 }
16225 {
16230 }
16232 }
16233 else
16234 {
16238 {
16239 /* Pull out the offset of a symbol; print any symbol itself. */
16243 {
16247 }
16255 else
16257 }
16261 {
16264 {
16268 }
16269 }
16272 else
16276 {
16281 }
16283 }
16284 }
16285 }
16287 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16289 static bool
16291 {
16292 rtx op;
16299 {
16302 /* FIXME: This might be @TPOFF in Sun ld. */
16313 else
16325 else
16332 #if TARGET_MACHO
16338 #endif
16341 {
16346 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16348 #else
16350 #endif
16353 }
16358 }
16361 }
16362 \f
16363 /* Split one or more double-mode RTL references into pairs of half-mode
16364 references. The RTL can be REG, offsettable MEM, integer constant, or
16365 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16366 split and "num" is its length. lo_half and hi_half are output arrays
16367 that parallel "operands". */
16369 void
16372 {
16373 machine_mode half_mode;
16377 {
16386 }
16391 {
16394 /* simplify_subreg refuse to split volatile memory addresses,
16395 but we still have to handle it. */
16397 {
16400 }
16401 else
16402 {
16409 }
16410 }
16411 }
16412 \f
16413 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16414 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16415 is the expression of the binary operation. The output may either be
16416 emitted here, or returned to the caller, like all output_* functions.
16418 There is no guarantee that the operands are the same mode, as they
16419 might be within FLOAT or FLOAT_EXTEND expressions. */
16421 #ifndef SYSV386_COMPAT
16422 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16423 wants to fix the assemblers because that causes incompatibility
16424 with gcc. No-one wants to fix gcc because that causes
16425 incompatibility with assemblers... You can use the option of
16426 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16427 #define SYSV386_COMPAT 1
16428 #endif
16432 {
16438 #ifdef ENABLE_CHECKING
16439 /* Even if we do not want to check the inputs, this documents input
16440 constraints. Which helps in understanding the following code. */
16450 else
16452 #endif
16455 {
16460 else
16469 else
16478 else
16487 else
16494 }
16497 {
16499 {
16503 else
16505 }
16506 else
16507 {
16511 else
16513 }
16515 }
16519 {
16525 /* know operands[0] == operands[1]. */
16528 {
16531 }
16534 {
16536 /* How is it that we are storing to a dead operand[2]?
16537 Well, presumably operands[1] is dead too. We can't
16538 store the result to st(0) as st(0) gets popped on this
16539 instruction. Instead store to operands[2] (which I
16540 think has to be st(1)). st(1) will be popped later.
16541 gcc <= 2.8.1 didn't have this check and generated
16542 assembly code that the Unixware assembler rejected. */
16544 else
16547 }
16551 else
16558 {
16561 }
16564 {
16567 }
16570 {
16571 #if SYSV386_COMPAT
16572 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16573 derived assemblers, confusingly reverse the direction of
16574 the operation for fsub{r} and fdiv{r} when the
16575 destination register is not st(0). The Intel assembler
16576 doesn't have this brain damage. Read !SYSV386_COMPAT to
16577 figure out what the hardware really does. */
16580 else
16582 #else
16584 /* As above for fmul/fadd, we can't store to st(0). */
16586 else
16588 #endif
16590 }
16593 {
16594 #if SYSV386_COMPAT
16597 else
16599 #else
16602 else
16604 #endif
16606 }
16609 {
16612 else
16615 }
16617 {
16618 #if SYSV386_COMPAT
16620 #else
16622 #endif
16623 }
16624 else
16625 {
16626 #if SYSV386_COMPAT
16628 #else
16630 #endif
16631 }
16636 }
16640 }
16642 /* Check if a 256bit AVX register is referenced inside of EXP. */
16644 static bool
16646 {
16652 }
16654 /* Return needed mode for entity in optimize_mode_switching pass. */
16656 static int
16658 {
16660 {
16661 rtx link;
16663 /* Needed mode is set to AVX_U128_CLEAN if there are
16664 no 256bit modes used in function arguments. */
16666 link;
16668 {
16670 {
16675 }
16676 }
16679 }
16681 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16682 changes state only when a 256bit register is written to, but we need
16683 to prevent the compiler from moving optimal insertion point above
16684 eventual read from 256bit register. */
16691 }
16693 /* Return mode that i387 must be switched into
16694 prior to the execution of insn. */
16696 static int
16698 {
16701 /* The mode UNINITIALIZED is used to store control word after a
16702 function call or ASM pattern. The mode ANY specify that function
16703 has no requirements on the control word and make no changes in the
16704 bits we are interested in. */
16718 {
16741 }
16744 }
16746 /* Return mode that entity must be switched into
16747 prior to the execution of insn. */
16749 static int
16751 {
16753 {
16763 }
16765 }
16767 /* Check if a 256bit AVX register is referenced in stores. */
16769 static void
16771 {
16773 {
16776 }
16777 }
16779 /* Calculate mode of upper 128bit AVX registers after the insn. */
16781 static int
16783 {
16790 /* We know that state is clean after CALL insn if there are no
16791 256bit registers used in the function return register. */
16793 {
16798 }
16800 /* Otherwise, return current mode. Remember that if insn
16801 references AVX 256bit registers, the mode was already changed
16802 to DIRTY from MODE_NEEDED. */
16804 }
16806 /* Return the mode that an insn results in. */
16808 static int
16810 {
16812 {
16822 }
16823 }
16825 static int
16827 {
16828 tree arg;
16830 /* Entry mode is set to AVX_U128_DIRTY if there are
16831 256bit modes used in function arguments. */
16834 {
16839 }
16842 }
16844 /* Return a mode that ENTITY is assumed to be
16845 switched to at function entry. */
16847 static int
16849 {
16851 {
16861 }
16862 }
16864 static int
16866 {
16869 /* Exit mode is set to AVX_U128_DIRTY if there are
16870 256bit modes used in the function return register. */
16875 }
16877 /* Return a mode that ENTITY is assumed to be
16878 switched to at function exit. */
16880 static int
16882 {
16884 {
16894 }
16895 }
16897 static int
16899 {
16901 }
16903 /* Output code to initialize control word copies used by trunc?f?i and
16904 rounding patterns. CURRENT_MODE is set to current control word,
16905 while NEW_MODE is set to new control word. */
16907 static void
16909 {
16911 rtx new_mode;
16922 {
16924 {
16926 /* round toward zero (truncate) */
16932 /* round down toward -oo */
16939 /* round up toward +oo */
16946 /* mask precision exception for nearbyint() */
16953 }
16954 }
16955 else
16956 {
16958 {
16960 /* round toward zero (truncate) */
16966 /* round down toward -oo */
16972 /* round up toward +oo */
16978 /* mask precision exception for nearbyint() */
16985 }
16986 }
16992 }
16994 /* Emit vzeroupper. */
16996 void
16998 {
17001 /* Cancel automatic vzeroupper insertion if there are
17002 live call-saved SSE registers at the insertion point. */
17014 }
17016 /* Generate one or more insns to set ENTITY to MODE. */
17018 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
17019 is the set of hard registers live at the point where the insn(s)
17020 are to be inserted. */
17022 static void
17024 HARD_REG_SET regs_live)
17025 {
17027 {
17042 }
17043 }
17045 /* Output code for INSN to convert a float to a signed int. OPERANDS
17046 are the insn operands. The output may be [HSD]Imode and the input
17047 operand may be [SDX]Fmode. */
17051 {
17056 /* Jump through a hoop or two for DImode, since the hardware has no
17057 non-popping instruction. We used to do this a different way, but
17058 that was somewhat fragile and broke with post-reload splitters. */
17068 else
17069 {
17074 else
17078 }
17081 }
17083 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17084 have the values zero or one, indicates the ffreep insn's operand
17085 from the OPERANDS array. */
17089 {
17091 #ifdef HAVE_AS_IX86_FFREEP
17093 #else
17094 {
17104 }
17105 #endif
17108 }
17111 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17112 should be used. UNORDERED_P is true when fucom should be used. */
17116 {
17122 {
17125 }
17126 else
17127 {
17130 }
17133 {
17137 else
17139 else
17142 else
17144 }
17151 {
17153 {
17156 }
17157 else
17159 }
17162 && stack_top_dies
17165 {
17166 /* If both the top of the 387 stack dies, and the other operand
17167 is also a stack register that dies, then this must be a
17168 `fcompp' float compare */
17171 {
17172 /* There is no double popping fcomi variant. Fortunately,
17173 eflags is immune from the fstp's cc clobbering. */
17176 else
17179 }
17180 else
17181 {
17184 else
17186 }
17187 }
17188 else
17189 {
17190 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17193 {
17201 NULL,
17202 NULL,
17209 NULL,
17210 NULL,
17211 NULL,
17212 NULL
17213 };
17228 }
17229 }
17231 void
17233 {
17236 #ifdef ASM_QUAD
17239 #else
17241 #endif
17244 }
17246 void
17248 {
17251 #ifdef ASM_QUAD
17254 #else
17256 #endif
17257 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17263 #if TARGET_MACHO
17265 {
17269 }
17270 #endif
17271 else
17274 }
17275 \f
17276 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17277 for the target. */
17279 void
17281 {
17282 rtx tmp;
17284 /* We play register width games, which are only valid after reload. */
17287 /* Avoid HImode and its attendant prefix byte. */
17293 {
17296 }
17299 }
17301 /* X is an unchanging MEM. If it is a constant pool reference, return
17302 the constant pool rtx, else NULL. */
17304 rtx
17306 {
17313 }
17315 void
17317 {
17325 {
17326 rtx tmp;
17330 {
17336 }
17339 }
17343 {
17346 rtx tmp;
17351 else
17355 {
17362 }
17363 }
17367 {
17369 {
17370 #if TARGET_MACHO
17371 /* dynamic-no-pic */
17373 {
17374 rtx temp = ((reload_in_progress
17382 }
17384 {
17388 }
17391 else
17392 {
17400 }
17401 /* dynamic-no-pic */
17402 #endif
17403 }
17404 else
17405 {
17409 {
17415 }
17416 }
17417 }
17418 else
17419 {
17430 /* Force large constants in 64bit compilation into register
17431 to get them CSEed. */
17443 {
17444 /* If we are loading a floating point constant to a register,
17445 force the value to memory now, since we'll get better code
17446 out the back end. */
17450 {
17455 }
17456 }
17457 }
17460 }
17462 void
17464 {
17471 /* Force constants other than zero into memory. We do not know how
17472 the instructions used to build constants modify the upper 64 bits
17473 of the register, once we have that information we may be able
17474 to handle some of them more efficiently. */
17483 /* We need to check memory alignment for SSE mode since attribute
17484 can make operands unaligned. */
17489 {
17492 /* ix86_expand_vector_move_misalign() does not like constants ... */
17498 /* ... nor both arguments in memory. */
17506 }
17508 /* Make operand1 a register if it isn't already. */
17512 {
17515 }
17518 }
17520 /* Split 32-byte AVX unaligned load and store if needed. */
17522 static void
17524 {
17525 rtx m;
17529 machine_mode mode;
17532 {
17553 }
17556 {
17559 {
17566 }
17567 /* Normal *mov<mode>_internal pattern will handle
17568 unaligned loads just fine if misaligned_operand
17569 is true, and without the UNSPEC it can be combined
17570 with arithmetic instructions. */
17573 else
17575 }
17577 {
17580 {
17585 }
17586 else
17588 }
17589 else
17591 }
17593 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17594 straight to ix86_expand_vector_move. */
17595 /* Code generation for scalar reg-reg moves of single and double precision data:
17596 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17597 movaps reg, reg
17598 else
17599 movss reg, reg
17600 if (x86_sse_partial_reg_dependency == true)
17601 movapd reg, reg
17602 else
17603 movsd reg, reg
17605 Code generation for scalar loads of double precision data:
17606 if (x86_sse_split_regs == true)
17607 movlpd mem, reg (gas syntax)
17608 else
17609 movsd mem, reg
17611 Code generation for unaligned packed loads of single precision data
17612 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17613 if (x86_sse_unaligned_move_optimal)
17614 movups mem, reg
17616 if (x86_sse_partial_reg_dependency == true)
17617 {
17618 xorps reg, reg
17619 movlps mem, reg
17620 movhps mem+8, reg
17621 }
17622 else
17623 {
17624 movlps mem, reg
17625 movhps mem+8, reg
17626 }
17628 Code generation for unaligned packed loads of double precision data
17629 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17630 if (x86_sse_unaligned_move_optimal)
17631 movupd mem, reg
17633 if (x86_sse_split_regs == true)
17634 {
17635 movlpd mem, reg
17636 movhpd mem+8, reg
17637 }
17638 else
17639 {
17640 movsd mem, reg
17641 movhpd mem+8, reg
17642 }
17643 */
17645 void
17647 {
17656 {
17658 {
17662 {
17664 {
17667 }
17668 else
17670 }
17672 /* FALLTHRU */
17676 {
17691 }
17697 else
17705 }
17708 }
17712 {
17714 {
17718 {
17720 {
17723 }
17724 else
17726 }
17728 /* FALLTHRU */
17738 }
17741 }
17744 {
17745 /* Normal *mov<mode>_internal pattern will handle
17746 unaligned loads just fine if misaligned_operand
17747 is true, and without the UNSPEC it can be combined
17748 with arithmetic instructions. */
17754 /* ??? If we have typed data, then it would appear that using
17755 movdqu is the only way to get unaligned data loaded with
17756 integer type. */
17758 {
17760 {
17763 }
17765 /* We will eventually emit movups based on insn attributes. */
17769 }
17771 {
17772 rtx zero;
17775 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17776 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17778 {
17779 /* We will eventually emit movups based on insn attributes. */
17782 }
17784 /* When SSE registers are split into halves, we can avoid
17785 writing to the top half twice. */
17787 {
17790 }
17791 else
17792 {
17793 /* ??? Not sure about the best option for the Intel chips.
17794 The following would seem to satisfy; the register is
17795 entirely cleared, breaking the dependency chain. We
17796 then store to the upper half, with a dependency depth
17797 of one. A rumor has it that Intel recommends two movsd
17798 followed by an unpacklpd, but this is unconfirmed. And
17799 given that the dependency depth of the unpacklpd would
17800 still be one, I'm not sure why this would be better. */
17802 }
17808 }
17809 else
17810 {
17811 rtx t;
17814 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17815 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17817 {
17819 {
17822 }
17829 }
17833 else
17838 else
17847 }
17848 }
17850 {
17852 {
17855 /* We will eventually emit movups based on insn attributes. */
17857 }
17859 {
17861 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17862 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17864 /* We will eventually emit movups based on insn attributes. */
17866 else
17867 {
17872 }
17873 }
17874 else
17875 {
17880 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17881 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17883 {
17886 }
17887 else
17888 {
17893 }
17894 }
17895 }
17896 else
17898 }
17900 /* Helper function of ix86_fixup_binary_operands to canonicalize
17901 operand order. Returns true if the operands should be swapped. */
17903 static bool
17905 rtx operands[])
17906 {
17911 /* If the operation is not commutative, we can't do anything. */
17915 /* Highest priority is that src1 should match dst. */
17921 /* Next highest priority is that immediate constants come second. */
17927 /* Lowest priority is that memory references should come second. */
17934 }
17937 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17938 destination to use for the operation. If different from the true
17939 destination in operands[0], a copy operation will be required. */
17941 rtx
17943 rtx operands[])
17944 {
17949 /* Canonicalize operand order. */
17951 {
17952 /* It is invalid to swap operands of different modes. */
17956 }
17958 /* Both source operands cannot be in memory. */
17960 {
17961 /* Optimization: Only read from memory once. */
17963 {
17966 }
17969 else
17971 }
17973 /* If the destination is memory, and we do not have matching source
17974 operands, do things in registers. */
17978 /* Source 1 cannot be a constant. */
17982 /* Source 1 cannot be a non-matching memory. */
17986 /* Improve address combine. */
17995 }
17997 /* Similarly, but assume that the destination has already been
17998 set up properly. */
18000 void
18003 {
18006 }
18008 /* Attempt to expand a binary operator. Make the expansion closer to the
18009 actual machine, then just general_operand, which will allow 3 separate
18010 memory references (one output, two input) in a single insn. */
18012 void
18014 rtx operands[])
18015 {
18022 /* Emit the instruction. */
18026 {
18027 /* Reload doesn't know about the flags register, and doesn't know that
18028 it doesn't want to clobber it. We can only do this with PLUS. */
18031 }
18035 {
18036 /* This is going to be an LEA; avoid splitting it later. */
18038 }
18039 else
18040 {
18043 }
18045 /* Fix up the destination if needed. */
18048 }
18050 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18051 the given OPERANDS. */
18053 void
18055 rtx operands[])
18056 {
18059 {
18062 }
18064 {
18067 }
18068 /* Optimize (__m128i) d | (__m128i) e and similar code
18069 when d and e are float vectors into float vector logical
18070 insn. In C/C++ without using intrinsics there is no other way
18071 to express vector logical operation on float vectors than
18072 to cast them temporarily to integer vectors. */
18074 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18083 {
18084 rtx dst;
18086 {
18095 {
18098 }
18099 else
18100 {
18105 }
18116 }
18117 }
18126 }
18128 /* Return TRUE or FALSE depending on whether the binary operator meets the
18129 appropriate constraints. */
18131 bool
18134 {
18139 /* Both source operands cannot be in memory. */
18143 /* Canonicalize operand order for commutative operators. */
18147 /* If the destination is memory, we must have a matching source operand. */
18151 /* Source 1 cannot be a constant. */
18155 /* Source 1 cannot be a non-matching memory. */
18157 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18165 }
18167 /* Attempt to expand a unary operator. Make the expansion closer to the
18168 actual machine, then just general_operand, which will allow 2 separate
18169 memory references (one output, one input) in a single insn. */
18171 void
18173 rtx operands[])
18174 {
18181 /* If the destination is memory, and we do not have matching source
18182 operands, do things in registers. */
18184 {
18187 else
18189 }
18191 /* When source operand is memory, destination must match. */
18195 /* Emit the instruction. */
18199 {
18200 /* Reload doesn't know about the flags register, and doesn't know that
18201 it doesn't want to clobber it. */
18204 }
18205 else
18206 {
18209 }
18211 /* Fix up the destination if needed. */
18214 }
18216 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18217 divisor are within the range [0-255]. */
18219 void
18222 {
18231 {
18244 }
18251 /* Use 8bit unsigned divimod if dividend and divisor are within
18252 the range [0-255]. */
18261 pc_rtx);
18266 /* Generate original signed/unsigned divimod. */
18271 /* Branch to the end. */
18275 /* Generate 8bit unsigned divide. */
18277 /* Don't use operands[0] for result of 8bit divide since not all
18278 registers support QImode ZERO_EXTRACT. */
18285 {
18288 }
18289 else
18290 {
18293 }
18295 /* Extract remainder from AH. */
18299 else
18300 {
18301 /* Need a new scratch register since the old one has result
18302 of 8bit divide. */
18306 }
18309 /* Zero extend quotient from AL. */
18315 }
18317 #define LEA_MAX_STALL (3)
18318 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18320 /* Increase given DISTANCE in half-cycles according to
18321 dependencies between PREV and NEXT instructions.
18322 Add 1 half-cycle if there is no dependency and
18323 go to next cycle if there is some dependecy. */
18325 static unsigned int
18327 {
18343 }
18345 /* Function checks if instruction INSN defines register number
18346 REGNO1 or REGNO2. */
18348 static bool
18350 rtx insn)
18351 {
18352 df_ref def;
18362 }
18364 /* Function checks if instruction INSN uses register number
18365 REGNO as a part of address expression. */
18367 static bool
18369 {
18370 df_ref use;
18377 }
18379 /* Search backward for non-agu definition of register number REGNO1
18380 or register number REGNO2 in basic block starting from instruction
18381 START up to head of basic block or instruction INSN.
18383 Function puts true value into *FOUND var if definition was found
18384 and false otherwise.
18386 Distance in half-cycles between START and found instruction or head
18387 of BB is added to DISTANCE and returned. */
18389 static int
18393 {
18403 {
18405 {
18408 {
18411 {
18414 }
18415 }
18418 }
18423 }
18426 }
18428 /* Search backward for non-agu definition of register number REGNO1
18429 or register number REGNO2 in INSN's basic block until
18430 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18431 2. Reach neighbour BBs boundary, or
18432 3. Reach agu definition.
18433 Returns the distance between the non-agu definition point and INSN.
18434 If no definition point, returns -1. */
18436 static int
18439 {
18450 {
18451 edge e;
18452 edge_iterator ei;
18457 {
18460 }
18466 else
18467 {
18472 {
18473 int bb_dist
18479 {
18486 }
18487 }
18490 }
18491 }
18493 /* get_attr_type may modify recog data. We want to make sure
18494 that recog data is valid for instruction INSN, on which
18495 distance_non_agu_define is called. INSN is unchanged here. */
18502 }
18504 /* Return the distance in half-cycles between INSN and the next
18505 insn that uses register number REGNO in memory address added
18506 to DISTANCE. Return -1 if REGNO0 is set.
18508 Put true value into *FOUND if register usage was found and
18509 false otherwise.
18510 Put true value into *REDEFINED if register redefinition was
18511 found and false otherwise. */
18513 static int
18517 {
18526 {
18529 /* If insn and start belong to the same bb, set prev to insn,
18530 so the call to increase_distance will increase the distance
18531 between insns by 1. */
18533 }
18538 {
18540 {
18543 {
18544 /* Return DISTANCE if OP0 is used in memory
18545 address in NEXT. */
18548 }
18551 {
18552 /* Return -1 if OP0 is set in NEXT. */
18555 }
18558 }
18564 }
18567 }
18569 /* Return the distance between INSN and the next insn that uses
18570 register number REGNO0 in memory address. Return -1 if no such
18571 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18573 static int
18575 {
18587 {
18588 edge e;
18589 edge_iterator ei;
18594 {
18597 }
18603 else
18604 {
18610 {
18611 int bb_dist
18616 {
18623 }
18624 }
18627 }
18628 }
18634 }
18636 /* Define this macro to tune LEA priority vs ADD, it take effect when
18637 there is a dilemma of choicing LEA or ADD
18638 Negative value: ADD is more preferred than LEA
18639 Zero: Netrual
18640 Positive value: LEA is more preferred than ADD*/
18641 #define IX86_LEA_PRIORITY 0
18643 /* Return true if usage of lea INSN has performance advantage
18644 over a sequence of instructions. Instructions sequence has
18645 SPLIT_COST cycles higher latency than lea latency. */
18647 static bool
18650 {
18653 /* For Silvermont if using a 2-source or 3-source LEA for
18654 non-destructive destination purposes, or due to wanting
18655 ability to use SCALE, the use of LEA is justified. */
18657 {
18665 }
18671 {
18672 /* If there is no non AGU operand definition, no AGU
18673 operand usage and split cost is 0 then both lea
18674 and non lea variants have same priority. Currently
18675 we prefer lea for 64 bit code and non lea on 32 bit
18676 code. */
18679 else
18681 }
18683 /* With longer definitions distance lea is more preferable.
18684 Here we change it to take into account splitting cost and
18685 lea priority. */
18688 /* If there is no use in memory addess then we just check
18689 that split cost exceeds AGU stall. */
18693 /* If this insn has both backward non-agu dependence and forward
18694 agu dependence, the one with short distance takes effect. */
18696 }
18698 /* Return true if it is legal to clobber flags by INSN and
18699 false otherwise. */
18701 static bool
18703 {
18705 df_ref use;
18706 bitmap live;
18709 {
18711 {
18718 }
18724 }
18728 }
18730 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18731 move and add to avoid AGU stalls. */
18733 bool
18735 {
18738 /* Check if we need to optimize. */
18742 /* Check it is correct to split here. */
18750 /* We need to split only adds with non destructive
18751 destination operand. */
18754 else
18756 }
18758 /* Return true if we should emit lea instruction instead of mov
18759 instruction. */
18761 bool
18763 {
18766 /* Check if we need to optimize. */
18770 /* Use lea for reg to reg moves only. */
18778 }
18780 /* Return true if we need to split lea into a sequence of
18781 instructions to avoid AGU stalls. */
18783 bool
18785 {
18791 /* Check we need to optimize. */
18795 /* The "at least two components" test below might not catch simple
18796 move or zero extension insns if parts.base is non-NULL and parts.disp
18797 is const0_rtx as the only components in the address, e.g. if the
18798 register is %rbp or %r13. As this test is much cheaper and moves or
18799 zero extensions are the common case, do this check first. */
18805 /* Check if it is OK to split here. */
18812 /* There should be at least two components in the address. */
18817 /* We should not split into add if non legitimate pic
18818 operand is used as displacement. */
18833 /* Compute how many cycles we will add to execution time
18834 if split lea into a sequence of instructions. */
18836 {
18837 /* Have to use mov instruction if non desctructive
18838 destination form is used. */
18842 /* Have to add index to base if both exist. */
18846 /* Have to use shift and adds if scale is 2 or greater. */
18848 {
18853 else
18855 }
18857 /* Have to use add instruction with immediate if
18858 disp is non zero. */
18862 /* Subtract the price of lea. */
18864 }
18868 }
18870 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18871 matches destination. RTX includes clobber of FLAGS_REG. */
18873 static void
18876 {
18883 }
18885 /* Return true if regno1 def is nearest to the insn. */
18887 static bool
18889 {
18896 {
18898 {
18901 }
18907 }
18909 /* None of the regs is defined in the bb. */
18911 }
18913 /* Split lea instructions into a sequence of instructions
18914 which are executed on ALU to avoid AGU stalls.
18915 It is assumed that it is allowed to clobber flags register
18916 at lea position. */
18918 void
18920 {
18936 {
18939 }
18942 {
18945 }
18951 {
18952 /* Case r1 = r1 + ... */
18954 {
18955 /* If we have a case r1 = r1 + C * r2 then we
18956 should use multiplication which is very
18957 expensive. Assume cost model is wrong if we
18958 have such case here. */
18963 }
18964 else
18965 {
18966 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18970 /* Use shift for scaling. */
18979 }
18980 }
18982 {
18985 }
18986 else
18987 {
18989 {
18992 }
18994 {
18997 }
18998 else
18999 {
19004 else
19005 {
19006 rtx tmp1;
19008 /* Find better operand for SET instruction, depending
19009 on which definition is farther from the insn. */
19012 else
19022 }
19025 }
19029 }
19030 }
19032 /* Return true if it is ok to optimize an ADD operation to LEA
19033 operation to avoid flag register consumation. For most processors,
19034 ADD is faster than LEA. For the processors like BONNELL, if the
19035 destination register of LEA holds an actual address which will be
19036 used soon, LEA is better and otherwise ADD is better. */
19038 bool
19040 {
19045 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19053 }
19055 /* Return true if destination reg of SET_BODY is shift count of
19056 USE_BODY. */
19058 static bool
19060 {
19061 rtx set_dest;
19062 rtx shift_rtx;
19065 /* Retrieve destination of SET_BODY. */
19067 {
19076 use_body))
19081 }
19083 /* Retrieve shift count of USE_BODY. */
19085 {
19097 }
19105 {
19108 /* Return true if shift count is dest of SET_BODY. */
19110 {
19111 /* Add check since it can be invoked before register
19112 allocation in pre-reload schedule. */
19118 }
19119 }
19122 }
19124 /* Return true if destination reg of SET_INSN is shift count of
19125 USE_INSN. */
19127 bool
19129 {
19132 }
19134 /* Return TRUE or FALSE depending on whether the unary operator meets the
19135 appropriate constraints. */
19137 bool
19139 machine_mode,
19141 {
19142 /* If one of operands is memory, source and destination must match. */
19148 }
19150 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19151 are ok, keeping in mind the possible movddup alternative. */
19153 bool
19155 {
19161 }
19163 /* Post-reload splitter for converting an SF or DFmode value in an
19164 SSE register into an unsigned SImode. */
19166 void
19168 {
19169 machine_mode vecmode;
19179 /* Load up the value into the low element. We must ensure that the other
19180 elements are valid floats -- zero is the easiest such value. */
19182 {
19185 else
19187 }
19188 else
19189 {
19194 else
19196 }
19216 else
19221 }
19223 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19224 Expects the 64-bit DImode to be supplied in a pair of integral
19225 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19226 -mfpmath=sse, !optimize_size only. */
19228 void
19230 {
19234 rtx x;
19240 {
19243 }
19244 else
19245 {
19249 }
19257 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19260 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19261 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19262 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19263 (0x1.0p84 + double(fp_value_hi_xmm)).
19264 Note these exponents differ by 32. */
19268 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19269 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19278 /* Add the upper and lower DFmode values together. */
19281 else
19282 {
19286 }
19289 }
19291 /* Not used, but eases macroization of patterns. */
19292 void
19294 {
19296 }
19298 /* Convert an unsigned SImode value into a DFmode. Only currently used
19299 for SSE, but applicable anywhere. */
19301 void
19303 {
19304 REAL_VALUE_TYPE TWO31r;
19319 }
19321 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19322 32-bit mode; otherwise we have a direct convert instruction. */
19324 void
19326 {
19327 REAL_VALUE_TYPE TWO32r;
19345 }
19347 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19348 For x86_32, -mfpmath=sse, !optimize_size only. */
19349 void
19351 {
19352 REAL_VALUE_TYPE ONE16r;
19371 }
19373 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19374 a vector of unsigned ints VAL to vector of floats TARGET. */
19376 void
19378 {
19380 REAL_VALUE_TYPE TWO16r;
19387 else
19392 OPTAB_DIRECT);
19403 OPTAB_DIRECT);
19405 OPTAB_DIRECT);
19408 }
19410 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19411 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19412 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19413 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19415 rtx
19417 {
19418 REAL_VALUE_TYPE TWO31r;
19433 {
19439 }
19448 OPTAB_DIRECT);
19449 else
19450 {
19456 OPTAB_DIRECT);
19457 }
19460 }
19462 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19463 then replicate the value for all elements of the vector
19464 register. */
19466 rtx
19468 {
19470 rtvec v;
19471 machine_mode scalar_mode;
19474 {
19507 }
19508 }
19510 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19511 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19512 for an SSE register. If VECT is true, then replicate the mask for
19513 all elements of the vector register. If INVERT is true, then create
19514 a mask excluding the sign bit. */
19516 rtx
19518 {
19522 rtx v;
19523 rtx mask;
19525 /* Find the sign bit, sign extended to 2*HWI. */
19527 {
19551 else
19559 {
19562 }
19563 else
19564 {
19565 rtvec vec;
19571 {
19574 }
19575 else
19585 }
19590 }
19595 /* Force this value into the low part of a fp vector constant. */
19604 }
19606 /* Generate code for floating point ABS or NEG. */
19608 void
19610 rtx operands[])
19611 {
19622 {
19628 }
19630 /* NEG and ABS performed with SSE use bitwise mask operations.
19631 Create the appropriate mask now. */
19634 else
19644 {
19646 rtvec par;
19651 else
19652 {
19655 }
19657 }
19658 else
19660 }
19662 /* Expand a copysign operation. Special case operand 0 being a constant. */
19664 void
19666 {
19680 else
19684 {
19691 {
19694 else
19695 {
19699 }
19700 }
19710 else
19714 }
19715 else
19716 {
19726 else
19730 }
19731 }
19733 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19734 be a constant, and so has already been expanded into a vector constant. */
19736 void
19738 {
19754 {
19757 }
19758 }
19760 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19761 so we have to do two masks. */
19763 void
19765 {
19780 {
19781 /* Shouldn't happen often (it's useless, obviously), but when it does
19782 we'd generate incorrect code if we continue below. */
19785 }
19788 {
19799 }
19800 else
19801 {
19803 {
19805 }
19807 {
19811 }
19815 {
19818 }
19820 {
19825 }
19827 }
19831 }
19833 /* Return TRUE or FALSE depending on whether the first SET in INSN
19834 has source and destination with matching CC modes, and that the
19835 CC mode is at least as constrained as REQ_MODE. */
19837 bool
19839 {
19840 rtx set;
19841 machine_mode set_mode;
19851 {
19861 /* FALLTHRU */
19865 /* FALLTHRU */
19869 /* FALLTHRU */
19883 }
19886 }
19888 /* Generate insn patterns to do an integer compare of OPERANDS. */
19890 static rtx
19892 {
19893 machine_mode cmpmode;
19899 /* This is very simple, but making the interface the same as in the
19900 FP case makes the rest of the code easier. */
19904 /* Return the test that should be put into the flags user, i.e.
19905 the bcc, scc, or cmov instruction. */
19907 }
19909 /* Figure out whether to use ordered or unordered fp comparisons.
19910 Return the appropriate mode to use. */
19912 machine_mode
19914 {
19915 /* ??? In order to make all comparisons reversible, we do all comparisons
19916 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19917 all forms trapping and nontrapping comparisons, we can make inequality
19918 comparisons trapping again, since it results in better code when using
19919 FCOM based compares. */
19921 }
19923 machine_mode
19925 {
19929 {
19932 }
19935 {
19936 /* Only zero flag is needed. */
19940 /* Codes needing carry flag. */
19943 /* Detect overflow checks. They need just the carry flag. */
19947 else
19952 /* Codes possibly doable only with sign flag when
19953 comparing against zero. */
19958 else
19959 /* For other cases Carry flag is not required. */
19961 /* Codes doable only with sign flag when comparing
19962 against zero, but we miss jump instruction for it
19963 so we need to use relational tests against overflow
19964 that thus needs to be zero. */
19969 else
19971 /* strcmp pattern do (use flags) and combine may ask us for proper
19972 mode. */
19977 }
19978 }
19980 /* Return the fixed registers used for condition codes. */
19982 static bool
19984 {
19988 }
19990 /* If two condition code modes are compatible, return a condition code
19991 mode which is compatible with both. Otherwise, return
19992 VOIDmode. */
19994 static machine_mode
19996 {
20013 {
20027 {
20041 }
20045 /* These are only compatible with themselves, which we already
20046 checked above. */
20048 }
20049 }
20052 /* Return a comparison we can do and that it is equivalent to
20053 swap_condition (code) apart possibly from orderedness.
20054 But, never change orderedness if TARGET_IEEE_FP, returning
20055 UNKNOWN in that case if necessary. */
20057 static enum rtx_code
20059 {
20061 {
20072 }
20073 }
20075 /* Return cost of comparison CODE using the best strategy for performance.
20076 All following functions do use number of instructions as a cost metrics.
20077 In future this should be tweaked to compute bytes for optimize_size and
20078 take into account performance of various instructions on various CPUs. */
20080 static int
20082 {
20085 /* The cost of code using bit-twiddling on %ah. */
20087 {
20110 }
20113 {
20120 }
20121 }
20123 /* Return strategy to use for floating-point. We assume that fcomi is always
20124 preferrable where available, since that is also true when looking at size
20125 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20127 enum ix86_fpcmp_strategy
20129 {
20130 /* Do fcomi/sahf based test when profitable. */
20139 }
20141 /* Swap, force into registers, or otherwise massage the two operands
20142 to a fp comparison. The operands are updated in place; the new
20143 comparison code is returned. */
20145 static enum rtx_code
20147 {
20153 /* All of the unordered compare instructions only work on registers.
20154 The same is true of the fcomi compare instructions. The XFmode
20155 compare instructions require registers except when comparing
20156 against zero or when converting operand 1 from fixed point to
20157 floating point. */
20166 {
20169 }
20170 else
20171 {
20172 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20173 things around if they appear profitable, otherwise force op0
20174 into a register. */
20180 {
20183 {
20186 }
20187 }
20193 {
20198 {
20201 }
20202 else
20204 }
20205 }
20207 /* Try to rearrange the comparison to make it cheaper. */
20211 {
20216 }
20221 }
20223 /* Convert comparison codes we use to represent FP comparison to integer
20224 code that will result in proper branch. Return UNKNOWN if no such code
20225 is available. */
20227 enum rtx_code
20229 {
20231 {
20254 }
20255 }
20257 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20259 static rtx
20261 {
20268 /* Do fcomi/sahf based test when profitable. */
20270 {
20275 tmp);
20283 tmp);
20292 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20299 /* In the unordered case, we have to check C2 for NaN's, which
20300 doesn't happen to work out to anything nice combination-wise.
20301 So do some bit twiddling on the value we've got in AH to come
20302 up with an appropriate set of condition codes. */
20306 {
20310 {
20313 }
20314 else
20315 {
20321 }
20326 {
20331 }
20332 else
20333 {
20336 }
20341 {
20344 }
20345 else
20346 {
20350 }
20355 {
20361 }
20362 else
20363 {
20366 }
20371 {
20376 }
20377 else
20378 {
20381 }
20386 {
20391 }
20392 else
20393 {
20396 }
20410 }
20415 }
20417 /* Return the test that should be put into the flags user, i.e.
20418 the bcc, scc, or cmov instruction. */
20421 const0_rtx);
20422 }
20424 static rtx
20426 {
20427 rtx ret;
20433 {
20436 }
20437 else
20441 }
20443 void
20445 {
20447 rtx tmp;
20450 {
20457 simple:
20461 pc_rtx);
20469 /* Expand DImode branch into multiple compare+branch. */
20470 {
20474 machine_mode submode;
20477 {
20480 }
20487 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20488 avoid two branches. This costs one extra insn, so disable when
20489 optimizing for size. */
20494 {
20512 }
20514 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20515 op1 is a constant and the low word is zero, then we can just
20516 examine the high word. Similarly for low word -1 and
20517 less-or-equal-than or greater-than. */
20521 {
20524 {
20527 }
20531 {
20534 }
20538 }
20540 /* Otherwise, we need two or three jumps. */
20549 {
20563 }
20565 /*
20566 * a < b =>
20567 * if (hi(a) < hi(b)) goto true;
20568 * if (hi(a) > hi(b)) goto false;
20569 * if (lo(a) < lo(b)) goto true;
20570 * false:
20571 */
20583 }
20588 }
20589 }
20591 /* Split branch based on floating point condition. */
20592 void
20595 {
20596 rtx condition;
20597 rtx i;
20600 {
20603 }
20606 tmp);
20614 }
20616 void
20618 {
20619 rtx ret;
20626 }
20628 /* Expand comparison setting or clearing carry flag. Return true when
20629 successful and set pop for the operation. */
20630 static bool
20632 {
20633 machine_mode mode =
20636 /* Do not handle double-mode compares that go through special path. */
20641 {
20642 rtx compare_op;
20647 /* Shortcut: following common codes never translate
20648 into carry flag compares. */
20653 /* These comparisons require zero flag; swap operands so they won't. */
20656 {
20659 }
20661 /* Try to expand the comparison and verify that we end up with
20662 carry flag based comparison. This fails to be true only when
20663 we decide to expand comparison using arithmetic that is not
20664 too common scenario. */
20673 else
20682 }
20688 {
20693 /* Convert a==0 into (unsigned)a<1. */
20702 /* Convert a>b into b<a or a>=b-1. */
20706 {
20708 /* Bail out on overflow. We still can swap operands but that
20709 would force loading of the constant into register. */
20714 }
20715 else
20716 {
20719 }
20722 /* Convert a>=0 into (unsigned)a<0x80000000. */
20740 }
20741 /* Swapping operands may cause constant to appear as first operand. */
20743 {
20747 }
20751 }
20753 bool
20755 {
20758 rtx compare_op;
20780 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20781 HImode insns, we'd be swallowed in word prefix ops. */
20787 {
20791 HOST_WIDE_INT diff;
20794 /* Sign bit compares are better done using shifts than we do by using
20795 sbb. */
20798 {
20799 /* Detect overlap between destination and compare sources. */
20803 {
20804 rtx flags;
20813 {
20815 compare_code
20817 }
20819 /* To simplify rest of code, restrict to the GEU case. */
20821 {
20825 }
20826 else
20827 {
20830 reverse_condition_maybe_unordered
20832 else
20835 }
20844 else
20847 }
20848 else
20849 {
20852 else
20853 {
20856 }
20858 }
20861 {
20862 /*
20863 * cmpl op0,op1
20864 * sbbl dest,dest
20865 * [addl dest, ct]
20866 *
20867 * Size 5 - 8.
20868 */
20873 }
20875 {
20876 /*
20877 * cmpl op0,op1
20878 * sbbl dest,dest
20879 * orl $ct, dest
20880 *
20881 * Size 8.
20882 */
20886 }
20888 {
20889 /*
20890 * cmpl op0,op1
20891 * sbbl dest,dest
20892 * notl dest
20893 * [addl dest, cf]
20894 *
20895 * Size 8 - 11.
20896 */
20902 }
20903 else
20904 {
20905 /*
20906 * cmpl op0,op1
20907 * sbbl dest,dest
20908 * [notl dest]
20909 * andl cf - ct, dest
20910 * [addl dest, ct]
20911 *
20912 * Size 8 - 11.
20913 */
20916 {
20920 }
20930 }
20936 }
20939 {
20944 {
20947 /* We may be reversing unordered compare to normal compare, that
20948 is not valid in general (we may convert non-trapping condition
20949 to trapping one), however on i386 we currently emit all
20950 comparisons unordered. */
20952 }
20953 else
20956 {
20960 }
20961 }
20966 {
20971 {
20976 }
20977 }
20979 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20983 {
20984 /* If lea code below could be used, only optimize
20985 if it results in a 2 insn sequence. */
20991 {
20992 /*
20993 * notl op1 (if necessary)
20994 * sarl $31, op1
20995 * orl cf, op1
20996 */
20998 {
21002 }
21013 }
21014 }
21022 {
21023 /*
21024 * xorl dest,dest
21025 * cmpl op1,op2
21026 * setcc dest
21027 * lea cf(dest*(ct-cf)),dest
21028 *
21029 * Size 14.
21030 *
21031 * This also catches the degenerate setcc-only case.
21032 */
21034 rtx tmp;
21040 /* On x86_64 the lea instruction operates on Pmode, so we need
21041 to get arithmetics done in proper mode to match. */
21044 else
21045 {
21046 rtx out1;
21049 nops++;
21051 {
21053 nops++;
21054 }
21055 }
21057 {
21059 nops++;
21060 }
21062 {
21065 else
21067 }
21072 }
21074 /*
21075 * General case: Jumpful:
21076 * xorl dest,dest cmpl op1, op2
21077 * cmpl op1, op2 movl ct, dest
21078 * setcc dest jcc 1f
21079 * decl dest movl cf, dest
21080 * andl (cf-ct),dest 1:
21081 * addl ct,dest
21082 *
21083 * Size 20. Size 14.
21084 *
21085 * This is reasonably steep, but branch mispredict costs are
21086 * high on modern cpus, so consider failing only if optimizing
21087 * for space.
21088 */
21093 {
21095 {
21100 {
21103 /* We may be reversing unordered compare to normal compare,
21104 that is not valid in general (we may convert non-trapping
21105 condition to trapping one), however on i386 we currently
21106 emit all comparisons unordered. */
21108 }
21109 else
21110 {
21114 }
21117 {
21121 }
21122 }
21125 {
21126 /* notl op1 (if needed)
21127 sarl $31, op1
21128 andl (cf-ct), op1
21129 addl ct, op1
21131 For x < 0 (resp. x <= -1) there will be no notl,
21132 so if possible swap the constants to get rid of the
21133 complement.
21134 True/false will be -1/0 while code below (store flag
21135 followed by decrement) is 0/-1, so the constants need
21136 to be exchanged once more. */
21139 {
21142 }
21143 else
21147 }
21148 else
21149 {
21153 constm1_rtx,
21155 }
21167 }
21168 }
21171 {
21172 /* Try a few things more with specific constants and a variable. */
21174 optab op;
21180 /* If one of the two operands is an interesting constant, load a
21181 constant with the above and mask it in with a logical operation. */
21184 {
21190 else
21192 }
21194 {
21200 else
21202 }
21203 else
21210 /* Recurse to get the constant loaded. */
21214 /* Mask in the interesting variable. */
21216 OPTAB_WIDEN);
21221 }
21223 /*
21224 * For comparison with above,
21225 *
21226 * movl cf,dest
21227 * movl ct,tmp
21228 * cmpl op1,op2
21229 * cmovcc tmp,dest
21230 *
21231 * Size 15.
21232 */
21254 }
21256 /* Swap, force into registers, or otherwise massage the two operands
21257 to an sse comparison with a mask result. Thus we differ a bit from
21258 ix86_prepare_fp_compare_args which expects to produce a flags result.
21260 The DEST operand exists to help determine whether to commute commutative
21261 operators. The POP0/POP1 operands are updated in place. The new
21262 comparison code is returned, or UNKNOWN if not implementable. */
21264 static enum rtx_code
21267 {
21269 {
21272 /* AVX supports all the needed comparisons. */
21275 /* We have no LTGT as an operator. We could implement it with
21276 NE & ORDERED, but this requires an extra temporary. It's
21277 not clear that it's worth it. */
21284 /* These are supported directly. */
21291 /* AVX has 3 operand comparisons, no need to swap anything. */
21294 /* For commutative operators, try to canonicalize the destination
21295 operand to be first in the comparison - this helps reload to
21296 avoid extra moves. */
21299 /* FALLTHRU */
21305 /* These are not supported directly before AVX, and furthermore
21306 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21307 comparison operands to transform into something that is
21308 supported. */
21315 }
21318 }
21320 /* Detect conditional moves that exactly match min/max operational
21321 semantics. Note that this is IEEE safe, as long as we don't
21322 interchange the operands.
21324 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21325 and TRUE if the operation is successful and instructions are emitted. */
21327 static bool
21330 {
21331 machine_mode mode;
21333 rtx tmp;
21336 ;
21339 else
21346 else
21351 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21352 but MODE may be a vector mode and thus not appropriate. */
21354 {
21356 rtvec v;
21361 }
21362 else
21363 {
21366 }
21370 }
21372 /* Expand an sse vector comparison. Return the register with the result. */
21374 static rtx
21377 {
21381 /* In general case result of comparison can differ from operands' type. */
21382 machine_mode cmp_mode;
21384 /* In AVX512F the result of comparison is an integer mask. */
21386 rtx x;
21389 {
21394 }
21395 else
21408 /* Compare patterns for int modes are unspec in AVX512F only. */
21410 {
21414 {
21431 }
21434 {
21437 }
21438 }
21442 {
21445 }
21446 else
21450 }
21452 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21453 operations. This is used for both scalar and vector conditional moves. */
21455 static void
21457 {
21461 /* In AVX512F the result of comparison is an integer mask. */
21469 {
21471 }
21474 {
21478 }
21481 {
21486 }
21489 {
21493 }
21496 {
21504 op_true,
21505 op_false)));
21506 }
21507 else
21508 {
21518 {
21532 {
21539 }
21554 {
21561 }
21585 }
21588 {
21592 }
21593 else
21594 {
21600 else
21612 }
21613 }
21614 }
21616 /* Expand a floating-point conditional move. Return true if successful. */
21618 bool
21620 {
21628 {
21629 machine_mode cmode;
21631 /* Since we've no cmove for sse registers, don't force bad register
21632 allocation just to gain access to it. Deny movcc when the
21633 comparison mode doesn't match the move mode. */
21652 }
21659 /* The floating point conditional move instructions don't directly
21660 support conditions resulting from a signed integer comparison. */
21664 {
21669 }
21676 }
21678 /* Expand a floating-point vector conditional move; a vcond operation
21679 rather than a movcc operation. */
21681 bool
21683 {
21685 rtx cmp;
21690 {
21691 rtx temp;
21693 {
21710 }
21712 OPTAB_DIRECT);
21715 }
21725 }
21727 /* Expand a signed/unsigned integral vector conditional move. */
21729 bool
21731 {
21741 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21742 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21751 {
21755 {
21761 }
21764 {
21770 }
21771 }
21780 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21784 ;
21785 else
21786 {
21787 /* Canonicalize the comparison to EQ, GT, GTU. */
21789 {
21806 /* FALLTHRU */
21816 }
21818 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21820 {
21822 {
21824 /* SSE4.1 supports EQ. */
21831 /* SSE4.2 supports GT/GTU. */
21838 }
21839 }
21841 /* Unsigned parallel compare is not supported by the hardware.
21842 Play some tricks to turn this into a signed comparison
21843 against 0. */
21845 {
21849 {
21856 {
21861 {
21870 }
21871 /* Subtract (-(INT MAX) - 1) from both operands to make
21872 them signed. */
21883 }
21892 /* Perform a parallel unsigned saturating subtraction. */
21905 }
21906 }
21907 }
21909 /* Allow the comparison to be done in one mode, but the movcc to
21910 happen in another mode. */
21912 {
21915 }
21916 else
21917 {
21923 }
21928 }
21930 /* AVX512F does support 64-byte integer vector operations,
21931 thus the longest vector we are faced with is V64QImode. */
21932 #define MAX_VECT_LEN 64
21934 struct expand_vec_perm_d
21935 {
21938 machine_mode vmode;
21942 };
21944 static bool
21947 {
21948 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21949 expander, so args are either in d, or in op0, op1 etc. */
21955 {
21986 {
21989 }
21993 {
21996 }
22000 {
22003 }
22019 {
22022 }
22026 {
22029 }
22033 {
22036 }
22040 }
22045 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22046 expander, so args are either in d, or in op0, op1 etc. */
22048 {
22056 }
22060 }
22062 /* Expand a variable vector permutation. */
22064 void
22066 {
22077 /* Number of elements in the vector. */
22086 {
22088 {
22089 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22090 an constant shuffle operand. With a tiny bit of effort we can
22091 use VPERMD instead. A re-interpretation stall for V4DFmode is
22092 unfortunate but there's no avoiding it.
22093 Similarly for V16HImode we don't have instructions for variable
22094 shuffling, while for V32QImode we can use after preparing suitable
22095 masks vpshufb; vpshufb; vpermq; vpor. */
22098 {
22102 }
22103 else
22104 {
22108 }
22111 /* Replicate the low bits of the V4DImode mask into V8SImode:
22112 mask = { A B C D }
22113 t1 = { A A B B C C D D }. */
22121 else
22124 /* Multiply the shuffle indicies by two. */
22126 OPTAB_DIRECT);
22128 /* Add one to the odd shuffle indicies:
22129 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22131 {
22134 }
22138 OPTAB_DIRECT);
22140 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22145 }
22148 {
22150 /* The VPERMD and VPERMPS instructions already properly ignore
22151 the high bits of the shuffle elements. No need for us to
22152 perform an AND ourselves. */
22154 {
22159 }
22160 else
22161 {
22167 }
22174 else
22175 {
22181 }
22185 /* By combining the two 128-bit input vectors into one 256-bit
22186 input vector, we can use VPERMD and VPERMPS for the full
22187 two-operand shuffle. */
22219 /* From mask create two adjusted masks, which contain the same
22220 bits as mask in the low 7 bits of each vector element.
22221 The first mask will have the most significant bit clear
22222 if it requests element from the same 128-bit lane
22223 and MSB set if it requests element from the other 128-bit lane.
22224 The second mask will have the opposite values of the MSB,
22225 and additionally will have its 128-bit lanes swapped.
22226 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22227 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22228 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22229 stands for other 12 bytes. */
22230 /* The bit whether element is from the same lane or the other
22231 lane is bit 4, so shift it up by 3 to the MSB position. */
22235 /* Clear MSB bits from the mask just in case it had them set. */
22237 /* After this t1 will have MSB set for elements from other lane. */
22239 /* Clear bits other than MSB. */
22241 /* Or in the lower bits from mask into t3. */
22243 /* And invert MSB bits in t1, so MSB is set for elements from the same
22244 lane. */
22246 /* Swap 128-bit lanes in t3. */
22251 /* And or in the lower bits from mask into t1. */
22254 {
22255 /* Each of these shuffles will put 0s in places where
22256 element from the other 128-bit lane is needed, otherwise
22257 will shuffle in the requested value. */
22261 /* For t3 the 128-bit lanes are swapped again. */
22266 /* And oring both together leads to the result. */
22273 }
22276 /* Similarly to the above one_operand_shuffle code,
22277 just for repeated twice for each operand. merge_two:
22278 code will merge the two results together. */
22302 }
22303 }
22306 {
22307 /* The XOP VPPERM insn supports three inputs. By ignoring the
22308 one_operand_shuffle special case, we avoid creating another
22309 set of constant vectors in memory. */
22312 /* mask = mask & {2*w-1, ...} */
22314 }
22315 else
22316 {
22317 /* mask = mask & {w-1, ...} */
22319 }
22327 /* For non-QImode operations, convert the word permutation control
22328 into a byte permutation control. */
22330 {
22335 /* Convert mask to vector of chars. */
22338 /* Replicate each of the input bytes into byte positions:
22339 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22340 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22341 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22348 else
22351 /* Convert it into the byte positions by doing
22352 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22358 }
22360 /* The actual shuffle operations all operate on V16QImode. */
22365 {
22372 }
22374 {
22381 }
22382 else
22383 {
22387 /* Shuffle the two input vectors independently. */
22393 merge_two:
22394 /* Then merge them together. The key is whether any given control
22395 element contained a bit set that indicates the second word. */
22399 {
22400 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22401 more shuffle to convert the V2DI input mask into a V4SI
22402 input mask. At which point the masking that expand_int_vcond
22403 will work as desired. */
22411 }
22433 }
22434 }
22436 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22437 true if we should do zero extension, else sign extension. HIGH_P is
22438 true if we want the N/2 high elements, else the low elements. */
22440 void
22442 {
22444 rtx tmp;
22447 {
22453 {
22457 else
22460 extract
22466 else
22469 extract
22475 else
22478 extract
22484 else
22487 extract
22493 else
22496 extract
22502 else
22505 extract
22511 else
22517 else
22523 else
22528 }
22531 {
22534 }
22536 {
22537 /* Shift higher 8 bytes to lower 8 bytes. */
22542 }
22543 else
22547 }
22548 else
22549 {
22553 {
22557 else
22563 else
22569 else
22574 }
22578 else
22585 }
22586 }
22588 /* Expand conditional increment or decrement using adb/sbb instructions.
22589 The default case using setcc followed by the conditional move can be
22590 done by generic code. */
22591 bool
22593 {
22595 rtx flags;
22597 rtx compare_op;
22600 machine_mode mode;
22615 {
22618 }
22621 {
22625 reverse_condition_maybe_unordered
22627 else
22629 }
22633 /* Construct either adc or sbb insn. */
22635 {
22637 {
22652 }
22653 }
22654 else
22655 {
22657 {
22672 }
22673 }
22677 }
22680 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22681 but works for floating pointer parameters and nonoffsetable memories.
22682 For pushes, it returns just stack offsets; the values will be saved
22683 in the right order. Maximally three parts are generated. */
22685 static int
22687 {
22692 else
22698 /* Optimize constant pool reference to immediates. This is used by fp
22699 moves, that force all constants to memory to allow combining. */
22701 {
22705 }
22708 {
22709 /* The only non-offsetable memories we handle are pushes. */
22718 }
22721 {
22723 /* Caution: if we looked through a constant pool memory above,
22724 the operand may actually have a different mode now. That's
22725 ok, since we want to pun this all the way back to an integer. */
22729 }
22732 {
22735 else
22736 {
22740 {
22744 }
22746 {
22751 }
22753 {
22754 REAL_VALUE_TYPE r;
22759 {
22766 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22767 long double may not be 80-bit. */
22776 }
22779 }
22780 else
22782 }
22783 }
22784 else
22785 {
22789 {
22792 {
22796 }
22798 {
22802 }
22804 {
22805 REAL_VALUE_TYPE r;
22811 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22814 = gen_int_mode
22817 DImode);
22818 else
22825 = gen_int_mode
22828 DImode);
22829 else
22831 }
22832 else
22834 }
22835 }
22838 }
22840 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22841 Return false when normal moves are needed; true when all required
22842 insns have been emitted. Operands 2-4 contain the input values
22843 int the correct order; operands 5-7 contain the output values. */
22845 void
22847 {
22855 /* The DFmode expanders may ask us to move double.
22856 For 64bit target this is single move. By hiding the fact
22857 here we simplify i386.md splitters. */
22859 {
22860 /* Optimize constant pool reference to immediates. This is used by
22861 fp moves, that force all constants to memory to allow combining. */
22868 {
22871 }
22872 else
22877 }
22879 /* The only non-offsettable memory we handle is push. */
22882 else
22889 /* When emitting push, take care for source operands on the stack. */
22892 {
22895 /* Compensate for the stack decrement by 4. */
22900 /* src_base refers to the stack pointer and is
22901 automatically decreased by emitted push. */
22905 }
22907 /* We need to do copy in the right order in case an address register
22908 of the source overlaps the destination. */
22910 {
22911 rtx tmp;
22914 {
22918 collisions++;
22919 }
22921 /* Collision in the middle part can be handled by reordering. */
22923 {
22926 }
22930 {
22932 {
22935 }
22936 else
22937 {
22940 }
22941 }
22943 /* If there are more collisions, we can't handle it by reordering.
22944 Do an lea to the last part and use only one colliding move. */
22946 {
22947 rtx base;
22953 /* Handle the case when the last part isn't valid for lea.
22954 Happens in 64-bit mode storing the 12-byte XFmode. */
22961 {
22964 }
22965 }
22966 }
22969 {
22971 {
22973 {
22978 }
22980 {
22983 }
22984 }
22985 else
22986 {
22987 /* In 64bit mode we don't have 32bit push available. In case this is
22988 register, it is OK - we will just use larger counterpart. We also
22989 retype memory - these comes from attempt to avoid REX prefix on
22990 moving of second half of TFmode value. */
22992 {
22994 {
23005 }
23009 }
23010 }
23014 }
23016 /* Choose correct order to not overwrite the source before it is copied. */
23026 {
23028 {
23031 }
23032 }
23033 else
23034 {
23036 {
23039 }
23040 }
23042 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23044 {
23053 }
23059 }
23061 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23062 left shift by a constant, either using a single shift or
23063 a sequence of add instructions. */
23065 static void
23067 {
23073 {
23077 }
23078 else
23079 {
23082 }
23083 }
23085 void
23087 {
23096 {
23101 {
23107 }
23108 else
23109 {
23117 }
23119 }
23126 {
23127 /* Assuming we've chosen a QImode capable registers, then 1 << N
23128 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23130 {
23146 }
23148 /* Otherwise, we can get the same results by manually performing
23149 a bit extract operation on bit 5/6, and then performing the two
23150 shifts. The two methods of getting 0/1 into low/high are exactly
23151 the same size. Avoiding the shift in the bit extract case helps
23152 pentium4 a bit; no one else seems to care much either way. */
23153 else
23154 {
23155 machine_mode half_mode;
23159 HOST_WIDE_INT bits;
23160 rtx x;
23163 {
23169 }
23170 else
23171 {
23177 }
23181 else
23189 }
23194 }
23197 {
23198 /* For -1 << N, we can avoid the shld instruction, because we
23199 know that we're shifting 0...31/63 ones into a -1. */
23203 else
23205 }
23206 else
23207 {
23215 }
23220 {
23226 }
23227 else
23228 {
23233 }
23234 }
23236 void
23238 {
23248 {
23253 {
23259 }
23261 {
23270 }
23271 else
23272 {
23280 }
23281 }
23282 else
23283 {
23295 {
23303 scratch));
23304 }
23305 else
23306 {
23311 }
23312 }
23313 }
23315 void
23317 {
23327 {
23332 {
23339 }
23340 else
23341 {
23349 }
23350 }
23351 else
23352 {
23364 {
23370 scratch));
23371 }
23372 else
23373 {
23378 }
23379 }
23380 }
23382 /* Predict just emitted jump instruction to be taken with probability PROB. */
23383 static void
23385 {
23389 }
23391 /* Helper function for the string operations below. Dest VARIABLE whether
23392 it is aligned to VALUE bytes. If true, jump to the label. */
23395 {
23400 else
23406 else
23409 }
23411 /* Adjust COUNTER by the VALUE. */
23412 static void
23414 {
23419 }
23421 /* Zero extend possibly SImode EXP to Pmode register. */
23422 rtx
23424 {
23426 }
23428 /* Divide COUNTREG by SCALE. */
23429 static rtx
23431 {
23432 rtx sc;
23444 }
23446 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23447 DImode for constant loop counts. */
23449 static machine_mode
23451 {
23459 }
23461 /* Copy the address to a Pmode register. This is used for x32 to
23462 truncate DImode TLS address to a SImode register. */
23464 static rtx
23466 {
23467 rtx reg;
23469 {
23473 }
23474 else
23475 {
23480 }
23481 }
23483 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23484 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23485 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23486 memory by VALUE (supposed to be in MODE).
23488 The size is rounded down to whole number of chunk size moved at once.
23489 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23492 static void
23497 {
23504 rtx size;
23513 /* Those two should combine. */
23515 {
23519 }
23526 /* This assert could be relaxed - in this case we'll need to compute
23527 smallest power of two, containing in PIECE_SIZE_N and pass it to
23528 offset_address. */
23534 {
23538 /* When unrolling for chips that reorder memory reads and writes,
23539 we can save registers by using single temporary.
23540 Also using 4 temporaries is overkill in 32bit mode. */
23542 {
23544 {
23546 {
23547 destmem =
23549 srcmem =
23551 }
23553 }
23554 }
23555 else
23556 {
23560 {
23563 {
23564 srcmem =
23566 }
23568 }
23570 {
23572 {
23573 destmem =
23575 }
23577 }
23578 }
23579 }
23580 else
23582 {
23584 destmem =
23587 }
23597 {
23603 else
23605 }
23606 else
23614 {
23619 }
23621 }
23623 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23624 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23625 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23626 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23627 ORIG_VALUE is the original value passed to memset to fill the memory with.
23628 Other arguments have same meaning as for previous function. */
23630 static void
23633 rtx count,
23635 {
23636 rtx destexp;
23637 rtx srcexp;
23638 rtx countreg;
23639 HOST_WIDE_INT rounded_count;
23641 /* If possible, it is shorter to use rep movs.
23642 TODO: Maybe it is better to move this logic to decide_alg. */
23653 {
23657 }
23658 else
23661 {
23666 }
23671 {
23674 }
23675 else
23676 {
23680 {
23684 }
23685 else
23688 {
23693 }
23694 else
23695 {
23698 }
23701 }
23702 }
23704 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23705 DESTMEM.
23706 SRC is passed by pointer to be updated on return.
23707 Return value is updated DST. */
23708 static rtx
23710 HOST_WIDE_INT size_to_move)
23711 {
23714 machine_mode move_mode;
23717 /* Find the widest mode in which we could perform moves.
23718 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23719 it until move of such size is supported. */
23724 {
23728 }
23730 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23731 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23733 {
23738 {
23742 }
23743 }
23749 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23753 {
23754 /* We move from memory to memory, so we'll need to do it via
23755 a temporary register. */
23766 piece_size);
23768 piece_size);
23769 }
23771 /* Update DST and SRC rtx. */
23774 }
23776 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23777 static void
23780 {
23783 {
23788 /* For now MAX_SIZE should be a power of 2. This assert could be
23789 relaxed, but it'll require a bit more complicated epilogue
23790 expanding. */
23793 {
23796 }
23798 }
23800 {
23806 }
23808 /* When there are stringops, we can cheaply increase dest and src pointers.
23809 Otherwise we save code size by maintaining offset (zero is readily
23810 available from preceding rep operation) and using x86 addressing modes.
23811 */
23813 {
23815 {
23822 }
23824 {
23831 }
23833 {
23840 }
23841 }
23842 else
23843 {
23845 rtx tmp;
23848 {
23859 }
23861 {
23874 }
23876 {
23885 }
23886 }
23887 }
23889 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23890 with value PROMOTED_VAL.
23891 SRC is passed by pointer to be updated on return.
23892 Return value is updated DST. */
23893 static rtx
23895 HOST_WIDE_INT size_to_move)
23896 {
23899 machine_mode move_mode;
23902 /* Find the widest mode in which we could perform moves.
23903 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23904 it until move of such size is supported. */
23909 {
23912 }
23919 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23923 {
23925 {
23928 piece_size);
23930 }
23938 piece_size);
23939 }
23941 /* Update DST rtx. */
23943 }
23944 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23945 static void
23948 {
23949 count =
23955 }
23957 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23958 static void
23961 {
23962 rtx dest;
23965 {
23970 /* For now MAX_SIZE should be a power of 2. This assert could be
23971 relaxed, but it'll require a bit more complicated epilogue
23972 expanding. */
23975 {
23977 {
23980 else
23982 }
23983 }
23985 }
23987 {
23990 }
23992 {
23995 {
24000 }
24001 else
24002 {
24011 }
24014 }
24016 {
24019 {
24022 }
24023 else
24024 {
24029 }
24032 }
24034 {
24040 }
24042 {
24048 }
24050 {
24056 }
24057 }
24059 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24060 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24061 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24062 ignored.
24063 Return value is updated DESTMEM. */
24064 static rtx
24069 {
24072 {
24074 {
24077 {
24080 else
24082 }
24083 else
24089 }
24090 }
24092 }
24094 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24095 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24096 and jump to DONE_LABEL. */
24097 static void
24103 {
24106 rtx modesize;
24109 /* If we do not have vector value to copy, we must reduce size. */
24111 {
24113 {
24118 }
24119 else
24121 }
24122 else
24123 {
24124 /* Choose appropriate vector mode. */
24130 }
24135 {
24138 else
24139 {
24142 }
24144 }
24150 {
24154 }
24156 {
24159 else
24160 {
24163 }
24165 }
24171 }
24173 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24174 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24175 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24176 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24177 DONE_LABEL is a label after the whole copying sequence. The label is created
24178 on demand if *DONE_LABEL is NULL.
24179 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24180 bounds after the initial copies.
24182 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24183 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24184 we will dispatch to a library call for large blocks.
24186 In pseudocode we do:
24188 if (COUNT < SIZE)
24189 {
24190 Assume that SIZE is 4. Bigger sizes are handled analogously
24191 if (COUNT & 4)
24192 {
24193 copy 4 bytes from SRCPTR to DESTPTR
24194 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24195 goto done_label
24196 }
24197 if (!COUNT)
24198 goto done_label;
24199 copy 1 byte from SRCPTR to DESTPTR
24200 if (COUNT & 2)
24201 {
24202 copy 2 bytes from SRCPTR to DESTPTR
24203 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24204 }
24205 }
24206 else
24207 {
24208 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24209 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24211 OLD_DESPTR = DESTPTR;
24212 Align DESTPTR up to DESIRED_ALIGN
24213 SRCPTR += DESTPTR - OLD_DESTPTR
24214 COUNT -= DEST_PTR - OLD_DESTPTR
24215 if (DYNAMIC_CHECK)
24216 Round COUNT down to multiple of SIZE
24217 << optional caller supplied zero size guard is here >>
24218 << optional caller suppplied dynamic check is here >>
24219 << caller supplied main copy loop is here >>
24220 }
24221 done_label:
24222 */
24223 static void
24226 machine_mode mode,
24236 {
24239 rtx modesize;
24241 rtx mode_value;
24243 /* Chose proper value to copy. */
24246 else
24250 /* See if block is big or small, handle small blocks. */
24252 {
24263 /* Handle sizes > 3. */
24270 /* Nothing to copy? Jump to DONE_LABEL if so */
24274 /* Do a byte copy. */
24278 else
24279 {
24282 }
24284 /* Handle sizes 2 and 3. */
24291 else
24292 {
24297 }
24303 }
24304 else
24308 /* Start memcpy for COUNT >= SIZE. */
24310 {
24313 }
24315 /* Copy first desired_align bytes. */
24321 {
24324 else
24325 {
24328 }
24331 }
24334 /* Copy last SIZE bytes. */
24341 else
24342 {
24348 }
24350 {
24354 else
24355 {
24358 }
24359 }
24361 /* Align destination. */
24363 {
24367 /* Align destptr up, place it to new register. */
24376 /* See how many bytes we skipped. */
24380 /* Adjust srcptr and count. */
24386 /* We copied at most size + prolog_size. */
24389 else
24392 /* Our loops always round down the bock size, but for dispatch to library
24393 we need precise value. */
24397 }
24398 else
24399 {
24401 /* Decrease count, so we won't end up copying last word twice. */
24405 else
24409 }
24410 }
24413 /* This function is like the previous one, except here we know how many bytes
24414 need to be copied. That allows us to update alignment not only of DST, which
24415 is returned, but also of SRC, which is passed as a pointer for that
24416 reason. */
24417 static rtx
24422 {
24430 {
24434 }
24439 {
24441 {
24443 {
24446 else
24448 }
24449 else
24452 }
24453 }
24460 {
24466 {
24469 {
24473 }
24478 }
24482 }
24485 }
24487 /* Return true if ALG can be used in current context.
24488 Assume we expand memset if MEMSET is true. */
24489 static bool
24491 {
24496 /* Algorithms using the rep prefix want at least edi and ecx;
24497 additionally, memset wants eax and memcpy wants esi. Don't
24498 consider such algorithms if the user has appropriated those
24499 registers for their own purposes. */
24506 }
24508 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24509 static enum stringop_alg
24513 {
24524 /* Even if the string operation call is cold, we still might spend a lot
24525 of time processing large blocks. */
24531 else
24537 else
24540 /* See maximal size for user defined algorithm. */
24542 {
24549 }
24551 /* If expected size is not known but max size is small enough
24552 so inline version is a win, set expected size into
24553 the range. */
24558 /* If user specified the algorithm, honnor it if possible. */
24562 /* rep; movq or rep; movl is the smallest variant. */
24564 {
24569 else
24572 }
24573 /* Very tiny blocks are best handled via the loop, REP is expensive to
24574 setup. */
24578 {
24582 {
24583 /* We get here if the algorithms that were not libcall-based
24584 were rep-prefix based and we are unable to use rep prefixes
24585 based on global register usage. Break out of the loop and
24586 use the heuristic below. */
24590 {
24594 {
24597 }
24598 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24599 last non-libcall inline algorithm. */
24601 {
24602 /* When the current size is best to be copied by a libcall,
24603 but we are still forced to inline, run the heuristic below
24604 that will pick code for medium sized blocks. */
24606 {
24609 }
24612 }
24614 {
24617 }
24618 }
24619 }
24620 }
24621 /* When asked to inline the call anyway, try to pick meaningful choice.
24622 We look for maximal size of block that is faster to copy by hand and
24623 take blocks of at most of that size guessing that average size will
24624 be roughly half of the block.
24626 If this turns out to be bad, we might simply specify the preferred
24627 choice in ix86_costs. */
24631 {
24634 /* If there aren't any usable algorithms, then recursing on
24635 smaller sizes isn't going to find anything. Just return the
24636 simple byte-at-a-time copy loop. */
24638 {
24639 /* Pick something reasonable. */
24643 }
24651 else
24654 }
24657 }
24659 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24660 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24661 static int
24665 machine_mode move_mode)
24666 {
24677 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24678 copying whole cacheline at once. */
24691 }
24694 /* Helper function for memcpy. For QImode value 0xXY produce
24695 0xXYXYXYXY of wide specified by MODE. This is essentially
24696 a * 0x10101010, but we can do slightly better than
24697 synth_mult by unwinding the sequence by hand on CPUs with
24698 slow multiply. */
24699 static rtx
24701 {
24703 rtx tmp;
24710 {
24718 }
24727 nops--;
24732 {
24736 OPTAB_DIRECT);
24737 }
24738 else
24739 {
24745 else
24747 else
24748 {
24751 reg =
24753 }
24763 }
24764 }
24766 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24767 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24768 alignment from ALIGN to DESIRED_ALIGN. */
24769 static rtx
24772 {
24773 rtx promoted_val;
24782 else
24786 }
24788 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24789 operations when profitable. The code depends upon architecture, block size
24790 and alignment, but always has one of the following overall structures:
24792 Aligned move sequence:
24794 1) Prologue guard: Conditional that jumps up to epilogues for small
24795 blocks that can be handled by epilogue alone. This is faster
24796 but also needed for correctness, since prologue assume the block
24797 is larger than the desired alignment.
24799 Optional dynamic check for size and libcall for large
24800 blocks is emitted here too, with -minline-stringops-dynamically.
24802 2) Prologue: copy first few bytes in order to get destination
24803 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24804 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24805 copied. We emit either a jump tree on power of two sized
24806 blocks, or a byte loop.
24808 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24809 with specified algorithm.
24811 4) Epilogue: code copying tail of the block that is too small to be
24812 handled by main body (or up to size guarded by prologue guard).
24814 Misaligned move sequence
24816 1) missaligned move prologue/epilogue containing:
24817 a) Prologue handling small memory blocks and jumping to done_label
24818 (skipped if blocks are known to be large enough)
24819 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24820 needed by single possibly misaligned move
24821 (skipped if alignment is not needed)
24822 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24824 2) Zero size guard dispatching to done_label, if needed
24826 3) dispatch to library call, if needed,
24828 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24829 with specified algorithm. */
24830 bool
24836 {
24837 rtx destreg;
24840 rtx tmp;
24856 /* TODO: Once value ranges are available, fill in proper data. */
24864 /* i386 can do misaligned access on reasonably increased cost. */
24868 /* ALIGN is the minimum of destination and source alignment, but we care here
24869 just about destination alignment. */
24875 {
24878 /* When COUNT is 0, there is nothing to do. */
24881 }
24882 else
24883 {
24892 }
24894 /* Make sure we don't need to care about overflow later on. */
24898 /* Step 0: Decide on preferred algorithm, desired alignment and
24899 size of chunks to be copied by main loop. */
24901 issetmem,
24908 /* For now vector-version of memset is generated only for memory zeroing, as
24909 creating of promoted vector value is very cheap in this case. */
24922 {
24941 /* Find the widest supported mode. */
24947 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24948 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24950 {
24955 }
24967 }
24975 /* Step 1: Prologue guard. */
24977 /* Alignment code needs count to be in register. */
24979 {
24982 {
24983 align_bytes
24987 else
24989 }
24992 }
24995 /* Misaligned move sequences handle both prologue and epilogue at once.
24996 Default code generation results in a smaller code for large alignments
24997 and also avoids redundant job when sizes are known precisely. */
24998 misaligned_prologue_used
24999 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
25005 /* Do the cheap promotion to allow better CSE across the
25006 main loop and epilogue (ie one load of the big constant in the
25007 front of all code.
25008 For now the misaligned move sequences do not have fast path
25009 without broadcasting. */
25011 {
25013 {
25019 }
25020 else
25021 {
25024 }
25025 }
25026 /* Misaligned move sequences handles both prologues and epilogues at once.
25027 Default code generation results in smaller code for large alignments and
25028 also avoids redundant job when sizes are known precisely. */
25030 {
25031 /* Misaligned move prologue handled small blocks by itself. */
25032 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25037 desired_align < align
25046 {
25047 /* It is possible that we copied enough so the main loop will not
25048 execute. */
25058 else
25060 }
25061 }
25062 /* Ensure that alignment prologue won't copy past end of block. */
25064 {
25066 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25067 Make sure it is power of 2. */
25070 /* To improve performance of small blocks, we jump around the VAL
25071 promoting mode. This mean that if the promoted VAL is not constant,
25072 we might not use it in the epilogue and have to use byte
25073 loop variant. */
25078 {
25079 /* If main algorithm works on QImode, no epilogue is needed.
25080 For small sizes just don't align anything. */
25083 else
25085 }
25088 {
25095 else
25097 }
25098 }
25100 /* Emit code to decide on runtime whether library call or inline should be
25101 used. */
25103 {
25105 {
25107 {
25111 }
25112 }
25113 else
25114 {
25124 else
25128 }
25129 }
25131 /* Step 2: Alignment prologue. */
25132 /* Do the expensive promotion once we branched off the small blocks. */
25138 {
25140 {
25141 /* Except for the first move in prologue, we no longer know
25142 constant offset in aliasing info. It don't seems to worth
25143 the pain to maintain it for the first move, so throw away
25144 the info early. */
25151 issetmem);
25152 /* At most desired_align - align bytes are copied. */
25155 else
25157 }
25158 else
25159 {
25160 /* If we know how many bytes need to be stored before dst is
25161 sufficiently aligned, maintain aliasing info accurately. */
25163 srcreg,
25164 promoted_val,
25165 vec_promoted_val,
25166 desired_align,
25167 align_bytes,
25168 issetmem);
25175 }
25177 && !min_size
25182 {
25183 /* It is possible that we copied enough so the main loop will not
25184 execute. */
25194 else
25196 }
25197 }
25199 {
25206 }
25210 /* Step 3: Main loop. */
25213 {
25236 }
25237 /* Adjust properly the offset of src and dest memory for aliasing. */
25239 {
25245 }
25246 else
25247 {
25251 }
25253 /* Step 4: Epilogue to copy the remaining bytes. */
25254 epilogue:
25256 {
25257 /* When the main loop is done, COUNT_EXP might hold original count,
25258 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25259 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25260 bytes. Compensate if needed. */
25263 {
25264 tmp =
25267 OPTAB_DIRECT);
25270 }
25273 }
25276 {
25279 epilogue_size_needed);
25280 else
25281 {
25285 epilogue_size_needed);
25286 else
25288 epilogue_size_needed);
25289 }
25290 }
25294 }
25297 /* Expand the appropriate insns for doing strlen if not just doing
25298 repnz; scasb
25300 out = result, initialized with the start address
25301 align_rtx = alignment of the address.
25302 scratch = scratch register, initialized with the startaddress when
25303 not aligned, otherwise undefined
25305 This is just the body. It needs the initializations mentioned above and
25306 some address computing at the end. These things are done in i386.md. */
25308 static void
25310 {
25312 rtx tmp;
25317 rtx mem;
25320 rtx cmp;
25326 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25328 /* Is there a known alignment and is it less than 4? */
25330 {
25333 /* Is there a known alignment and is it not 2? */
25335 {
25339 /* Leave just the 3 lower bits. */
25349 }
25350 else
25351 {
25352 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25353 check if is aligned to 4 - byte. */
25360 }
25364 /* Now compare the bytes. */
25366 /* Compare the first n unaligned byte on a byte per byte basis. */
25370 /* Increment the address. */
25373 /* Not needed with an alignment of 2 */
25375 {
25379 end_0_label);
25384 }
25387 end_0_label);
25390 }
25392 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25393 align this loop. It gives only huge programs, but does not help to
25394 speed up. */
25401 /* This formula yields a nonzero result iff one of the bytes is zero.
25402 This saves three branches inside loop and many cycles. */
25410 align_4_label);
25413 {
25419 /* If zero is not in the first two bytes, move two bytes forward. */
25425 reg,
25426 tmpreg)));
25427 /* Emit lea manually to avoid clobbering of flags. */
25435 reg2,
25436 out)));
25437 }
25438 else
25439 {
25441 /* Is zero in the first two bytes? */
25448 pc_rtx);
25452 /* Not in the first two. Move two bytes forward. */
25458 }
25460 /* Avoid branch in fixing the byte. */
25468 }
25470 /* Expand strlen. */
25472 bool
25474 {
25477 /* The generic case of strlen expander is long. Avoid it's
25478 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25481 && !TARGET_INLINE_ALL_STRINGOPS
25491 {
25492 /* Well it seems that some optimizer does not combine a call like
25493 foo(strlen(bar), strlen(bar));
25494 when the move and the subtraction is done here. It does calculate
25495 the length just once when these instructions are done inside of
25496 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25497 often used and I use one fewer register for the lifetime of
25498 output_strlen_unroll() this is better. */
25504 /* strlensi_unroll_1 returns the address of the zero at the end of
25505 the string, like memchr(), so compute the length by subtracting
25506 the start address. */
25508 }
25509 else
25510 {
25511 rtx unspec;
25513 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25526 /* If .md starts supporting :P, this can be done in .md. */
25532 }
25534 }
25536 /* For given symbol (function) construct code to compute address of it's PLT
25537 entry in large x86-64 PIC model. */
25538 static rtx
25540 {
25553 }
25555 rtx
25557 rtx callarg2,
25559 {
25569 {
25570 #if TARGET_MACHO
25573 #endif
25574 }
25575 else
25576 {
25577 /* Static functions and indirect calls don't need the pic register. */
25579 && (!TARGET_64BIT
25584 {
25588 pic_offset_table_rtx);
25589 }
25590 }
25592 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25593 parameters passed in vector registers. */
25598 {
25602 }
25605 && !TARGET_PECOFF
25613 {
25616 }
25621 {
25622 /* We should add bounds as destination register in case
25623 pointer with bounds may be returned. */
25625 {
25629 {
25634 }
25635 else
25636 {
25640 }
25641 }
25644 }
25648 {
25652 }
25656 {
25657 int const cregs_size
25662 {
25667 }
25668 }
25677 }
25679 /* Output the assembly for a call instruction. */
25683 {
25689 {
25692 /* SEH epilogue detection requires the indirect branch case
25693 to include REX.W. */
25696 else
25701 }
25703 /* SEH unwinding can require an extra nop to be emitted in several
25704 circumstances. Determine if we have one of those. */
25706 {
25710 {
25711 /* If we get to another real insn, we don't need the nop. */
25715 /* If we get to the epilogue note, prevent a catch region from
25716 being adjacent to the standard epilogue sequence. If non-
25717 call-exceptions, we'll have done this during epilogue emission. */
25719 && !flag_non_call_exceptions
25721 {
25724 }
25725 }
25727 /* If we didn't find a real insn following the call, prevent the
25728 unwinder from looking into the next function. */
25731 }
25735 else
25744 }
25745 \f
25746 /* Clear stack slot assignments remembered from previous functions.
25747 This is called from INIT_EXPANDERS once before RTL is emitted for each
25748 function. */
25752 {
25760 }
25762 /* Return a MEM corresponding to a stack slot with mode MODE.
25763 Allocate a new slot if necessary.
25765 The RTL for a function can have several slots available: N is
25766 which slot to use. */
25768 rtx
25770 {
25787 }
25789 static void
25791 {
25797 }
25798 \f
25799 /* Check whether x86 address PARTS is a pc-relative address. */
25801 static bool
25803 {
25811 {
25813 {
25830 }
25831 }
25833 }
25835 /* Calculate the length of the memory address in the instruction encoding.
25836 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25837 or other prefixes. We never generate addr32 prefix for LEA insn. */
25839 int
25841 {
25858 /* If this is not LEA instruction, add the length of addr32 prefix. */
25863 len++;
25877 /* Rule of thumb:
25878 - esp as the base always wants an index,
25879 - ebp as the base always wants a displacement,
25880 - r12 as the base always wants an index,
25881 - r13 as the base always wants a displacement. */
25883 /* Register Indirect. */
25885 {
25886 /* esp (for its index) and ebp (for its displacement) need
25887 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25888 code. */
25895 len++;
25896 }
25898 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25899 is not disp32, but disp32(%rip), so for disp32
25900 SIB byte is needed, unless print_operand_address
25901 optimizes it into disp32(%rip) or (%rip) is implied
25902 by UNSPEC. */
25904 {
25907 len++;
25908 }
25909 else
25910 {
25911 /* Find the length of the displacement constant. */
25913 {
25916 else
25918 }
25919 /* ebp always wants a displacement. Similarly r13. */
25921 len++;
25923 /* An index requires the two-byte modrm form.... */
25925 /* ...like esp (or r12), which always wants an index. */
25929 len++;
25930 }
25933 }
25935 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25936 is set, expect that insn have 8bit immediate alternative. */
25937 int
25939 {
25945 {
25950 {
25953 {
25965 }
25967 {
25970 }
25971 }
25973 {
25983 /* Immediates for DImode instructions are encoded
25984 as 32bit sign extended values. */
25990 }
25991 }
25993 }
25995 /* Compute default value for "length_address" attribute. */
25996 int
25998 {
26002 {
26013 }
26018 {
26021 {
26026 constraints++;
26029 ;
26030 /* Skip ignored operands. */
26033 }
26035 }
26037 }
26039 /* Compute default value for "length_vex" attribute. It includes
26040 2 or 3 byte VEX prefix and 1 opcode byte. */
26042 int
26045 {
26048 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26049 byte VEX prefix. */
26053 /* We can always use 2 byte VEX prefix in 32bit. */
26061 {
26062 /* REX.W bit uses 3 byte VEX prefix. */
26066 }
26067 else
26068 {
26069 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26073 }
26076 }
26077 \f
26078 /* Return the maximum number of instructions a cpu can issue. */
26080 static int
26082 {
26084 {
26116 }
26117 }
26119 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26120 by DEP_INSN and nothing set by DEP_INSN. */
26122 static bool
26124 {
26127 /* Simplify the test for uninteresting insns. */
26135 {
26138 }
26143 {
26146 }
26147 else
26153 /* This test is true if the dependent insn reads the flags but
26154 not any other potentially set register. */
26162 }
26164 /* Return true iff USE_INSN has a memory address with operands set by
26165 SET_INSN. */
26167 bool
26169 {
26174 {
26177 }
26179 }
26181 /* Helper function for exact_store_load_dependency.
26182 Return true if addr is found in insn. */
26183 static bool
26185 {
26192 {
26198 CASE_CONST_ANY:
26207 }
26211 {
26213 {
26223 }
26224 }
26226 }
26228 /* Return true if there exists exact dependency for store & load, i.e.
26229 the same memory address is used in them. */
26230 static bool
26232 {
26246 }
26248 static int
26250 {
26256 /* Anti and output dependencies have zero cost on all CPUs. */
26262 /* If we can't recognize the insns, we can't really do anything. */
26270 {
26272 /* Address Generation Interlock adds a cycle of latency. */
26274 {
26285 }
26289 /* ??? Compares pair with jump/setcc. */
26293 /* Floating point stores require value to be ready one cycle earlier. */
26301 /* INT->FP conversion is expensive. */
26305 /* There is one cycle extra latency between an FP op and a store. */
26315 /* Show ability of reorder buffer to hide latency of load by executing
26316 in parallel with previous instruction in case
26317 previous instruction is not needed to compute the address. */
26320 {
26321 /* Claim moves to take one cycle, as core can issue one load
26322 at time and the next load can start cycle later. */
26327 cost--;
26328 }
26332 /* The esp dependency is resolved before
26333 the instruction is really finished. */
26338 /* INT->FP conversion is expensive. */
26344 /* Show ability of reorder buffer to hide latency of load by executing
26345 in parallel with previous instruction in case
26346 previous instruction is not needed to compute the address. */
26349 {
26350 /* Claim moves to take one cycle, as core can issue one load
26351 at time and the next load can start cycle later. */
26357 else
26359 }
26370 /* Stack engine allows to execute push&pop instructions in parall. */
26374 /* FALLTHRU */
26380 /* Show ability of reorder buffer to hide latency of load by executing
26381 in parallel with previous instruction in case
26382 previous instruction is not needed to compute the address. */
26385 {
26389 /* Because of the difference between the length of integer and
26390 floating unit pipeline preparation stages, the memory operands
26391 for floating point are cheaper.
26393 ??? For Athlon it the difference is most probably 2. */
26396 else
26401 else
26403 }
26410 /* Stack engine allows to execute push&pop instructions in parall. */
26417 /* Show ability of reorder buffer to hide latency of load by executing
26418 in parallel with previous instruction in case
26419 previous instruction is not needed to compute the address. */
26422 {
26425 else
26427 }
26436 /* Increase cost of integer loads. */
26439 {
26442 {
26445 else
26446 {
26447 /* Increase cost of ld/st for short int types only
26448 because of store forwarding issue. */
26452 {
26453 /* Increase cost of store/load insn if exact
26454 dependence exists and it is load insn. */
26459 }
26460 }
26461 }
26462 }
26466 }
26469 }
26471 /* How many alternative schedules to try. This should be as wide as the
26472 scheduling freedom in the DFA, but no wider. Making this value too
26473 large results extra work for the scheduler. */
26475 static int
26477 {
26479 {
26491 /* We use lookahead value 4 for BD both before and after reload
26492 schedules. Plan is to have value 8 included for O3. */
26503 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26504 as many instructions can be executed on a cycle, i.e.,
26505 issue_rate. I wonder why tuning for many CPUs does not do this. */
26508 /* Don't use lookahead for pre-reload schedule to save compile time. */
26513 }
26514 }
26516 /* Return true if target platform supports macro-fusion. */
26518 static bool
26520 {
26522 }
26524 /* Check whether current microarchitecture support macro fusion
26525 for insn pair "CONDGEN + CONDJMP". Refer to
26526 "Intel Architectures Optimization Reference Manual". */
26528 static bool
26530 {
26551 {
26556 {
26560 else
26562 }
26563 }
26570 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26571 supported. */
26578 /* No fusion for RIP-relative address. */
26585 ix86_address parts;
26591 }
26596 /* Check whether conditional jump use Sign or Overflow Flags. */
26604 /* Return true for TYPE_TEST and TYPE_ICMP. */
26609 /* The following is the case that macro-fusion for alu + jmp. */
26613 /* No fusion for alu op with memory destination operand. */
26618 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26619 supported. */
26628 }
26630 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26631 execution. It is applied if
26632 (1) IMUL instruction is on the top of list;
26633 (2) There exists the only producer of independent IMUL instruction in
26634 ready list.
26635 Return index of IMUL producer if it was found and -1 otherwise. */
26636 static int
26638 {
26641 sd_iterator_def sd_it;
26642 dep_t dep;
26649 /* Check that IMUL instruction is on the top of ready list. */
26658 /* Search for producer of independent IMUL instruction. */
26660 {
26664 /* Skip IMUL instruction. */
26674 {
26675 rtx con;
26686 {
26687 sd_iterator_def sd_it1;
26688 dep_t dep1;
26689 /* Check if there is no other dependee for IMUL. */
26692 {
26693 rtx pro;
26699 }
26702 }
26703 }
26706 }
26708 }
26710 /* Try to find the best candidate on the top of ready list if two insns
26711 have the same priority - candidate is best if its dependees were
26712 scheduled earlier. Applied for Silvermont only.
26713 Return true if top 2 insns must be interchanged. */
26714 static bool
26716 {
26719 rtx set;
26720 sd_iterator_def sd_it;
26721 dep_t dep;
26724 #define INSN_TICK(INSN) (HID (INSN)->tick)
26745 {
26748 /* Determine winner more precise. */
26750 {
26751 rtx pro;
26757 }
26759 {
26760 rtx pro;
26766 }
26769 {
26770 /* Determine winner - load must win. */
26776 }
26778 }
26780 #undef INSN_TICK
26781 }
26783 /* Perform possible reodering of ready list for Atom/Silvermont only.
26784 Return issue rate. */
26785 static int
26788 {
26795 /* Set up issue rate. */
26798 /* Do reodering for BONNELL/SILVERMONT only. */
26802 /* Nothing to do if ready list contains only 1 instruction. */
26806 /* Do reodering for post-reload scheduler only. */
26811 {
26816 /* Put IMUL producer (ready[index]) at the top of ready list. */
26822 }
26824 /* Skip selective scheduling since HID is not populated in it. */
26828 {
26832 /* Swap 2 top elements of ready list. */
26836 }
26838 }
26840 static bool
26843 /* Returns true if lhs of insn is HW function argument register and set up
26844 is_spilled to true if it is likely spilled HW register. */
26845 static bool
26847 {
26848 rtx dst;
26852 /* Call instructions are not movable, ignore it. */
26863 {
26864 /* Is it likely spilled HW register? */
26869 }
26871 }
26873 /* Add output dependencies for chain of function adjacent arguments if only
26874 there is a move to likely spilled HW register. Return first argument
26875 if at least one dependence was added or NULL otherwise. */
26878 {
26886 /* Find nearest to call argument passing instruction. */
26888 {
26897 }
26901 {
26908 {
26911 }
26913 {
26914 /* Add output depdendence between two function arguments if chain
26915 of output arguments contains likely spilled HW registers. */
26919 }
26920 else
26922 }
26926 }
26928 /* Add output or anti dependency from insn to first_arg to restrict its code
26929 motion. */
26930 static void
26932 {
26933 rtx set;
26934 rtx tmp;
26936 /* Add anti dependencies for bounds stores. */
26941 {
26944 }
26951 {
26952 /* Add output dependency to the first function argument. */
26955 }
26956 /* Add anti dependency. */
26958 }
26960 /* Avoid cross block motion of function argument through adding dependency
26961 from the first non-jump instruction in bb. */
26962 static void
26964 {
26968 {
26970 {
26973 {
26976 }
26977 }
26981 }
26982 }
26984 /* Hook for pre-reload schedule - avoid motion of function arguments
26985 passed in likely spilled HW registers. */
26986 static void
26988 {
26997 {
27000 {
27001 /* Add dependee for first argument to predecessors if only
27002 region contains more than one block. */
27006 /* Skip trivial regions and region head blocks that can have
27007 predecessors outside of region. */
27009 {
27010 edge e;
27011 edge_iterator ei;
27013 /* Regions are SCCs with the exception of selective
27014 scheduling with pipelining of outer blocks enabled.
27015 So also check that immediate predecessors of a non-head
27016 block are in the same region. */
27018 {
27019 /* Avoid creating of loop-carried dependencies through
27020 using topological ordering in the region. */
27024 }
27025 }
27029 }
27030 }
27033 }
27035 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27036 HW registers to maximum, to schedule them at soon as possible. These are
27037 moves from function argument registers at the top of the function entry
27038 and moves from function return value registers after call. */
27039 static int
27041 {
27042 rtx set;
27052 {
27059 }
27062 }
27064 /* Model decoder of Core 2/i7.
27065 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27066 track the instruction fetch block boundaries and make sure that long
27067 (9+ bytes) instructions are assigned to D0. */
27069 /* Maximum length of an insn that can be handled by
27070 a secondary decoder unit. '8' for Core 2/i7. */
27073 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27074 '16' for Core 2/i7. */
27077 /* Maximum number of instructions decoder can handle per cycle.
27078 '6' for Core 2/i7. */
27082 ix86_first_cycle_multipass_data_t;
27084 const_ix86_first_cycle_multipass_data_t;
27086 /* A variable to store target state across calls to max_issue within
27087 one cycle. */
27091 /* Initialize DATA. */
27092 static void
27094 {
27095 ix86_first_cycle_multipass_data_t data
27102 }
27104 /* Advancing the cycle; reset ifetch block counts. */
27105 static void
27107 {
27114 }
27118 /* Filter out insns from ready_try that the core will not be able to issue
27119 on current cycle due to decoder. */
27120 static void
27121 core2i7_first_cycle_multipass_filter_ready_try
27124 {
27126 {
27137 (!first_cycle_insn_p
27139 /* ... or it would not fit into the ifetch block ... */
27141 /* ... or the decoder is full already ... */
27143 /* ... mask the insn out. */
27144 {
27149 }
27150 }
27151 }
27153 /* Prepare for a new round of multipass lookahead scheduling. */
27154 static void
27158 {
27159 ix86_first_cycle_multipass_data_t data
27161 const_ix86_first_cycle_multipass_data_t prev_data
27164 /* Restore the state from the end of the previous round. */
27168 /* Filter instructions that cannot be issued on current cycle due to
27169 decoder restrictions. */
27171 first_cycle_insn_p);
27172 }
27174 /* INSN is being issued in current solution. Account for its impact on
27175 the decoder model. */
27176 static void
27180 {
27181 ix86_first_cycle_multipass_data_t data
27183 const_ix86_first_cycle_multipass_data_t prev_data
27193 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27195 {
27198 }
27200 {
27204 }
27207 /* Filter out insns from ready_try that the core will not be able to issue
27208 on current cycle due to decoder. */
27211 }
27213 /* Revert the effect on ready_try. */
27214 static void
27218 {
27219 const_ix86_first_cycle_multipass_data_t data
27222 sbitmap_iterator sbi;
27226 {
27228 }
27229 }
27231 /* Save the result of multipass lookahead scheduling for the next round. */
27232 static void
27234 {
27235 const_ix86_first_cycle_multipass_data_t data
27237 ix86_first_cycle_multipass_data_t next_data
27241 {
27244 }
27245 }
27247 /* Deallocate target data. */
27248 static void
27250 {
27251 ix86_first_cycle_multipass_data_t data
27255 {
27259 }
27260 }
27262 /* Prepare for scheduling pass. */
27263 static void
27265 {
27266 /* Install scheduling hooks for current CPU. Some of these hooks are used
27267 in time-critical parts of the scheduler, so we only set them up when
27268 they are actually used. */
27270 {
27275 /* Do not perform multipass scheduling for pre-reload schedule
27276 to save compile time. */
27278 {
27294 /* Set decoder parameters. */
27299 }
27300 /* ... Fall through ... */
27310 }
27311 }
27313 \f
27314 /* Compute the alignment given to a constant that is being placed in memory.
27315 EXP is the constant and ALIGN is the alignment that the object would
27316 ordinarily have.
27317 The value of this function is used instead of that alignment to align
27318 the object. */
27320 int
27322 {
27325 {
27330 }
27336 }
27338 /* Compute the alignment for a static variable.
27339 TYPE is the data type, and ALIGN is the alignment that
27340 the object would ordinarily have. The value of this function is used
27341 instead of that alignment to align the object. */
27343 int
27345 {
27346 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27347 for symbols from other compilation units or symbols that don't need
27348 to bind locally. In order to preserve some ABI compatibility with
27349 those compilers, ensure we don't decrease alignment from what we
27350 used to assume. */
27354 /* A data structure, equal or greater than the size of a cache line
27355 (64 bytes in the Pentium 4 and other recent Intel processors, including
27356 processors based on Intel Core microarchitecture) should be aligned
27357 so that its base address is a multiple of a cache line size. */
27359 int max_align
27366 {
27370 }
27376 {
27383 }
27385 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27386 to 16byte boundary. */
27388 {
27395 }
27401 {
27406 }
27408 {
27415 }
27420 {
27425 }
27428 {
27433 }
27436 }
27438 /* Compute the alignment for a local variable or a stack slot. EXP is
27439 the data type or decl itself, MODE is the widest mode available and
27440 ALIGN is the alignment that the object would ordinarily have. The
27441 value of this macro is used instead of that alignment to align the
27442 object. */
27444 unsigned int
27447 {
27451 {
27454 }
27455 else
27456 {
27459 }
27461 /* Don't do dynamic stack realignment for long long objects with
27462 -mpreferred-stack-boundary=2. */
27471 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27472 register in MODE. We will return the largest alignment of XF
27473 and DF. */
27475 {
27479 }
27481 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27482 to 16byte boundary. Exact wording is:
27484 An array uses the same alignment as its elements, except that a local or
27485 global array variable of length at least 16 bytes or
27486 a C99 variable-length array variable always has alignment of at least 16 bytes.
27488 This was added to allow use of aligned SSE instructions at arrays. This
27489 rule is meant for static storage (where compiler can not do the analysis
27490 by itself). We follow it for automatic variables only when convenient.
27491 We fully control everything in the function compiled and functions from
27492 other unit can not rely on the alignment.
27494 Exclude va_list type. It is the common case of local array where
27495 we can not benefit from the alignment.
27497 TODO: Probably one should optimize for size only when var is not escaping. */
27500 {
27510 }
27512 {
27517 }
27519 {
27525 }
27530 {
27535 }
27538 {
27544 }
27546 }
27548 /* Compute the minimum required alignment for dynamic stack realignment
27549 purposes for a local variable, parameter or a stack slot. EXP is
27550 the data type or decl itself, MODE is its mode and ALIGN is the
27551 alignment that the object would ordinarily have. */
27553 unsigned int
27556 {
27560 {
27563 }
27564 else
27565 {
27568 }
27573 /* Don't do dynamic stack realignment for long long objects with
27574 -mpreferred-stack-boundary=2. */
27581 }
27582 \f
27583 /* Find a location for the static chain incoming to a nested function.
27584 This is a register, unless all free registers are used by arguments. */
27586 static rtx
27588 {
27591 /* While this function won't be called by the middle-end when a static
27592 chain isn't needed, it's also used throughout the backend so it's
27593 easiest to keep this check centralized. */
27598 {
27599 /* We always use R10 in 64-bit mode. */
27601 }
27602 else
27603 {
27607 /* By default in 32-bit mode we use ECX to pass the static chain. */
27611 {
27614 }
27615 else
27616 {
27619 }
27623 {
27624 /* Fastcall functions use ecx/edx for arguments, which leaves
27625 us with EAX for the static chain.
27626 Thiscall functions use ecx for arguments, which also
27627 leaves us with EAX for the static chain. */
27629 }
27631 {
27632 /* Thiscall functions use ecx for arguments, which leaves
27633 us with EAX and EDX for the static chain.
27634 We are using for abi-compatibility EAX. */
27636 }
27638 {
27639 /* For regparm 3, we have no free call-clobbered registers in
27640 which to store the static chain. In order to implement this,
27641 we have the trampoline push the static chain to the stack.
27642 However, we can't push a value below the return address when
27643 we call the nested function directly, so we have to use an
27644 alternate entry point. For this we use ESI, and have the
27645 alternate entry point push ESI, so that things appear the
27646 same once we're executing the nested function. */
27648 {
27654 }
27656 }
27657 }
27660 }
27662 /* Emit RTL insns to initialize the variable parts of a trampoline.
27663 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27664 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27665 to be passed to the target function. */
27667 static void
27669 {
27677 {
27680 /* Load the function address to r11. Try to load address using
27681 the shorter movl instead of movabs. We may want to support
27682 movq for kernel mode, but kernel does not use trampolines at
27683 the moment. FNADDR is a 32bit address and may not be in
27684 DImode when ptr_mode == SImode. Always use movl in this
27685 case. */
27688 {
27697 }
27698 else
27699 {
27706 }
27708 /* Load static chain using movabs to r10. Use the shorter movl
27709 instead of movabs when ptr_mode == SImode. */
27711 {
27714 }
27715 else
27716 {
27719 }
27728 /* Jump to r11; the last (unused) byte is a nop, only there to
27729 pad the write out to a single 32-bit store. */
27733 }
27734 else
27735 {
27738 /* Depending on the static chain location, either load a register
27739 with a constant, or push the constant to the stack. All of the
27740 instructions are the same size. */
27743 {
27745 {
27752 }
27753 }
27754 else
27769 /* Compute offset from the end of the jmp to the target function.
27770 In the case in which the trampoline stores the static chain on
27771 the stack, we need to skip the first insn which pushes the
27772 (call-saved) register static chain; this push is 1 byte. */
27779 }
27783 #ifdef HAVE_ENABLE_EXECUTE_STACK
27784 #ifdef CHECK_EXECUTE_STACK_ENABLED
27786 #endif
27789 #endif
27790 }
27791 \f
27792 /* The following file contains several enumerations and data structures
27793 built from the definitions in i386-builtin-types.def. */
27797 /* Table for the ix86 builtin non-function types. */
27800 /* Retrieve an element from the above table, building some of
27801 the types lazily. */
27803 static tree
27805 {
27817 {
27818 machine_mode mode;
27825 }
27826 else
27827 {
27833 else
27841 }
27845 }
27847 /* Table for the ix86 builtin function types. */
27850 /* Retrieve an element from the above table, building some of
27851 the types lazily. */
27853 static tree
27855 {
27856 tree type;
27865 {
27873 {
27876 }
27879 }
27880 else
27881 {
27887 }
27891 }
27894 /* Codes for all the SSE/MMX builtins. */
27895 enum ix86_builtins
27896 {
27897 IX86_BUILTIN_ADDPS,
27898 IX86_BUILTIN_ADDSS,
27899 IX86_BUILTIN_DIVPS,
27900 IX86_BUILTIN_DIVSS,
27901 IX86_BUILTIN_MULPS,
27902 IX86_BUILTIN_MULSS,
27903 IX86_BUILTIN_SUBPS,
27904 IX86_BUILTIN_SUBSS,
27906 IX86_BUILTIN_CMPEQPS,
27907 IX86_BUILTIN_CMPLTPS,
27908 IX86_BUILTIN_CMPLEPS,
27909 IX86_BUILTIN_CMPGTPS,
27910 IX86_BUILTIN_CMPGEPS,
27911 IX86_BUILTIN_CMPNEQPS,
27912 IX86_BUILTIN_CMPNLTPS,
27913 IX86_BUILTIN_CMPNLEPS,
27914 IX86_BUILTIN_CMPNGTPS,
27915 IX86_BUILTIN_CMPNGEPS,
27916 IX86_BUILTIN_CMPORDPS,
27917 IX86_BUILTIN_CMPUNORDPS,
27918 IX86_BUILTIN_CMPEQSS,
27919 IX86_BUILTIN_CMPLTSS,
27920 IX86_BUILTIN_CMPLESS,
27921 IX86_BUILTIN_CMPNEQSS,
27922 IX86_BUILTIN_CMPNLTSS,
27923 IX86_BUILTIN_CMPNLESS,
27924 IX86_BUILTIN_CMPORDSS,
27925 IX86_BUILTIN_CMPUNORDSS,
27927 IX86_BUILTIN_COMIEQSS,
27928 IX86_BUILTIN_COMILTSS,
27929 IX86_BUILTIN_COMILESS,
27930 IX86_BUILTIN_COMIGTSS,
27931 IX86_BUILTIN_COMIGESS,
27932 IX86_BUILTIN_COMINEQSS,
27933 IX86_BUILTIN_UCOMIEQSS,
27934 IX86_BUILTIN_UCOMILTSS,
27935 IX86_BUILTIN_UCOMILESS,
27936 IX86_BUILTIN_UCOMIGTSS,
27937 IX86_BUILTIN_UCOMIGESS,
27938 IX86_BUILTIN_UCOMINEQSS,
27940 IX86_BUILTIN_CVTPI2PS,
27941 IX86_BUILTIN_CVTPS2PI,
27942 IX86_BUILTIN_CVTSI2SS,
27943 IX86_BUILTIN_CVTSI642SS,
27944 IX86_BUILTIN_CVTSS2SI,
27945 IX86_BUILTIN_CVTSS2SI64,
27946 IX86_BUILTIN_CVTTPS2PI,
27947 IX86_BUILTIN_CVTTSS2SI,
27948 IX86_BUILTIN_CVTTSS2SI64,
27950 IX86_BUILTIN_MAXPS,
27951 IX86_BUILTIN_MAXSS,
27952 IX86_BUILTIN_MINPS,
27953 IX86_BUILTIN_MINSS,
27955 IX86_BUILTIN_LOADUPS,
27956 IX86_BUILTIN_STOREUPS,
27957 IX86_BUILTIN_MOVSS,
27959 IX86_BUILTIN_MOVHLPS,
27960 IX86_BUILTIN_MOVLHPS,
27961 IX86_BUILTIN_LOADHPS,
27962 IX86_BUILTIN_LOADLPS,
27963 IX86_BUILTIN_STOREHPS,
27964 IX86_BUILTIN_STORELPS,
27966 IX86_BUILTIN_MASKMOVQ,
27967 IX86_BUILTIN_MOVMSKPS,
27968 IX86_BUILTIN_PMOVMSKB,
27970 IX86_BUILTIN_MOVNTPS,
27971 IX86_BUILTIN_MOVNTQ,
27973 IX86_BUILTIN_LOADDQU,
27974 IX86_BUILTIN_STOREDQU,
27976 IX86_BUILTIN_PACKSSWB,
27977 IX86_BUILTIN_PACKSSDW,
27978 IX86_BUILTIN_PACKUSWB,
27980 IX86_BUILTIN_PADDB,
27981 IX86_BUILTIN_PADDW,
27982 IX86_BUILTIN_PADDD,
27983 IX86_BUILTIN_PADDQ,
27984 IX86_BUILTIN_PADDSB,
27985 IX86_BUILTIN_PADDSW,
27986 IX86_BUILTIN_PADDUSB,
27987 IX86_BUILTIN_PADDUSW,
27988 IX86_BUILTIN_PSUBB,
27989 IX86_BUILTIN_PSUBW,
27990 IX86_BUILTIN_PSUBD,
27991 IX86_BUILTIN_PSUBQ,
27992 IX86_BUILTIN_PSUBSB,
27993 IX86_BUILTIN_PSUBSW,
27994 IX86_BUILTIN_PSUBUSB,
27995 IX86_BUILTIN_PSUBUSW,
27997 IX86_BUILTIN_PAND,
27998 IX86_BUILTIN_PANDN,
27999 IX86_BUILTIN_POR,
28000 IX86_BUILTIN_PXOR,
28002 IX86_BUILTIN_PAVGB,
28003 IX86_BUILTIN_PAVGW,
28005 IX86_BUILTIN_PCMPEQB,
28006 IX86_BUILTIN_PCMPEQW,
28007 IX86_BUILTIN_PCMPEQD,
28008 IX86_BUILTIN_PCMPGTB,
28009 IX86_BUILTIN_PCMPGTW,
28010 IX86_BUILTIN_PCMPGTD,
28012 IX86_BUILTIN_PMADDWD,
28014 IX86_BUILTIN_PMAXSW,
28015 IX86_BUILTIN_PMAXUB,
28016 IX86_BUILTIN_PMINSW,
28017 IX86_BUILTIN_PMINUB,
28019 IX86_BUILTIN_PMULHUW,
28020 IX86_BUILTIN_PMULHW,
28021 IX86_BUILTIN_PMULLW,
28023 IX86_BUILTIN_PSADBW,
28024 IX86_BUILTIN_PSHUFW,
28026 IX86_BUILTIN_PSLLW,
28027 IX86_BUILTIN_PSLLD,
28028 IX86_BUILTIN_PSLLQ,
28029 IX86_BUILTIN_PSRAW,
28030 IX86_BUILTIN_PSRAD,
28031 IX86_BUILTIN_PSRLW,
28032 IX86_BUILTIN_PSRLD,
28033 IX86_BUILTIN_PSRLQ,
28034 IX86_BUILTIN_PSLLWI,
28035 IX86_BUILTIN_PSLLDI,
28036 IX86_BUILTIN_PSLLQI,
28037 IX86_BUILTIN_PSRAWI,
28038 IX86_BUILTIN_PSRADI,
28039 IX86_BUILTIN_PSRLWI,
28040 IX86_BUILTIN_PSRLDI,
28041 IX86_BUILTIN_PSRLQI,
28043 IX86_BUILTIN_PUNPCKHBW,
28044 IX86_BUILTIN_PUNPCKHWD,
28045 IX86_BUILTIN_PUNPCKHDQ,
28046 IX86_BUILTIN_PUNPCKLBW,
28047 IX86_BUILTIN_PUNPCKLWD,
28048 IX86_BUILTIN_PUNPCKLDQ,
28050 IX86_BUILTIN_SHUFPS,
28052 IX86_BUILTIN_RCPPS,
28053 IX86_BUILTIN_RCPSS,
28054 IX86_BUILTIN_RSQRTPS,
28055 IX86_BUILTIN_RSQRTPS_NR,
28056 IX86_BUILTIN_RSQRTSS,
28057 IX86_BUILTIN_RSQRTF,
28058 IX86_BUILTIN_SQRTPS,
28059 IX86_BUILTIN_SQRTPS_NR,
28060 IX86_BUILTIN_SQRTSS,
28062 IX86_BUILTIN_UNPCKHPS,
28063 IX86_BUILTIN_UNPCKLPS,
28065 IX86_BUILTIN_ANDPS,
28066 IX86_BUILTIN_ANDNPS,
28067 IX86_BUILTIN_ORPS,
28068 IX86_BUILTIN_XORPS,
28070 IX86_BUILTIN_EMMS,
28071 IX86_BUILTIN_LDMXCSR,
28072 IX86_BUILTIN_STMXCSR,
28073 IX86_BUILTIN_SFENCE,
28075 IX86_BUILTIN_FXSAVE,
28076 IX86_BUILTIN_FXRSTOR,
28077 IX86_BUILTIN_FXSAVE64,
28078 IX86_BUILTIN_FXRSTOR64,
28080 IX86_BUILTIN_XSAVE,
28081 IX86_BUILTIN_XRSTOR,
28082 IX86_BUILTIN_XSAVE64,
28083 IX86_BUILTIN_XRSTOR64,
28085 IX86_BUILTIN_XSAVEOPT,
28086 IX86_BUILTIN_XSAVEOPT64,
28088 IX86_BUILTIN_XSAVEC,
28089 IX86_BUILTIN_XSAVEC64,
28091 IX86_BUILTIN_XSAVES,
28092 IX86_BUILTIN_XRSTORS,
28093 IX86_BUILTIN_XSAVES64,
28094 IX86_BUILTIN_XRSTORS64,
28096 /* 3DNow! Original */
28097 IX86_BUILTIN_FEMMS,
28098 IX86_BUILTIN_PAVGUSB,
28099 IX86_BUILTIN_PF2ID,
28100 IX86_BUILTIN_PFACC,
28101 IX86_BUILTIN_PFADD,
28102 IX86_BUILTIN_PFCMPEQ,
28103 IX86_BUILTIN_PFCMPGE,
28104 IX86_BUILTIN_PFCMPGT,
28105 IX86_BUILTIN_PFMAX,
28106 IX86_BUILTIN_PFMIN,
28107 IX86_BUILTIN_PFMUL,
28108 IX86_BUILTIN_PFRCP,
28109 IX86_BUILTIN_PFRCPIT1,
28110 IX86_BUILTIN_PFRCPIT2,
28111 IX86_BUILTIN_PFRSQIT1,
28112 IX86_BUILTIN_PFRSQRT,
28113 IX86_BUILTIN_PFSUB,
28114 IX86_BUILTIN_PFSUBR,
28115 IX86_BUILTIN_PI2FD,
28116 IX86_BUILTIN_PMULHRW,
28118 /* 3DNow! Athlon Extensions */
28119 IX86_BUILTIN_PF2IW,
28120 IX86_BUILTIN_PFNACC,
28121 IX86_BUILTIN_PFPNACC,
28122 IX86_BUILTIN_PI2FW,
28123 IX86_BUILTIN_PSWAPDSI,
28124 IX86_BUILTIN_PSWAPDSF,
28126 /* SSE2 */
28127 IX86_BUILTIN_ADDPD,
28128 IX86_BUILTIN_ADDSD,
28129 IX86_BUILTIN_DIVPD,
28130 IX86_BUILTIN_DIVSD,
28131 IX86_BUILTIN_MULPD,
28132 IX86_BUILTIN_MULSD,
28133 IX86_BUILTIN_SUBPD,
28134 IX86_BUILTIN_SUBSD,
28136 IX86_BUILTIN_CMPEQPD,
28137 IX86_BUILTIN_CMPLTPD,
28138 IX86_BUILTIN_CMPLEPD,
28139 IX86_BUILTIN_CMPGTPD,
28140 IX86_BUILTIN_CMPGEPD,
28141 IX86_BUILTIN_CMPNEQPD,
28142 IX86_BUILTIN_CMPNLTPD,
28143 IX86_BUILTIN_CMPNLEPD,
28144 IX86_BUILTIN_CMPNGTPD,
28145 IX86_BUILTIN_CMPNGEPD,
28146 IX86_BUILTIN_CMPORDPD,
28147 IX86_BUILTIN_CMPUNORDPD,
28148 IX86_BUILTIN_CMPEQSD,
28149 IX86_BUILTIN_CMPLTSD,
28150 IX86_BUILTIN_CMPLESD,
28151 IX86_BUILTIN_CMPNEQSD,
28152 IX86_BUILTIN_CMPNLTSD,
28153 IX86_BUILTIN_CMPNLESD,
28154 IX86_BUILTIN_CMPORDSD,
28155 IX86_BUILTIN_CMPUNORDSD,
28157 IX86_BUILTIN_COMIEQSD,
28158 IX86_BUILTIN_COMILTSD,
28159 IX86_BUILTIN_COMILESD,
28160 IX86_BUILTIN_COMIGTSD,
28161 IX86_BUILTIN_COMIGESD,
28162 IX86_BUILTIN_COMINEQSD,
28163 IX86_BUILTIN_UCOMIEQSD,
28164 IX86_BUILTIN_UCOMILTSD,
28165 IX86_BUILTIN_UCOMILESD,
28166 IX86_BUILTIN_UCOMIGTSD,
28167 IX86_BUILTIN_UCOMIGESD,
28168 IX86_BUILTIN_UCOMINEQSD,
28170 IX86_BUILTIN_MAXPD,
28171 IX86_BUILTIN_MAXSD,
28172 IX86_BUILTIN_MINPD,
28173 IX86_BUILTIN_MINSD,
28175 IX86_BUILTIN_ANDPD,
28176 IX86_BUILTIN_ANDNPD,
28177 IX86_BUILTIN_ORPD,
28178 IX86_BUILTIN_XORPD,
28180 IX86_BUILTIN_SQRTPD,
28181 IX86_BUILTIN_SQRTSD,
28183 IX86_BUILTIN_UNPCKHPD,
28184 IX86_BUILTIN_UNPCKLPD,
28186 IX86_BUILTIN_SHUFPD,
28188 IX86_BUILTIN_LOADUPD,
28189 IX86_BUILTIN_STOREUPD,
28190 IX86_BUILTIN_MOVSD,
28192 IX86_BUILTIN_LOADHPD,
28193 IX86_BUILTIN_LOADLPD,
28195 IX86_BUILTIN_CVTDQ2PD,
28196 IX86_BUILTIN_CVTDQ2PS,
28198 IX86_BUILTIN_CVTPD2DQ,
28199 IX86_BUILTIN_CVTPD2PI,
28200 IX86_BUILTIN_CVTPD2PS,
28201 IX86_BUILTIN_CVTTPD2DQ,
28202 IX86_BUILTIN_CVTTPD2PI,
28204 IX86_BUILTIN_CVTPI2PD,
28205 IX86_BUILTIN_CVTSI2SD,
28206 IX86_BUILTIN_CVTSI642SD,
28208 IX86_BUILTIN_CVTSD2SI,
28209 IX86_BUILTIN_CVTSD2SI64,
28210 IX86_BUILTIN_CVTSD2SS,
28211 IX86_BUILTIN_CVTSS2SD,
28212 IX86_BUILTIN_CVTTSD2SI,
28213 IX86_BUILTIN_CVTTSD2SI64,
28215 IX86_BUILTIN_CVTPS2DQ,
28216 IX86_BUILTIN_CVTPS2PD,
28217 IX86_BUILTIN_CVTTPS2DQ,
28219 IX86_BUILTIN_MOVNTI,
28220 IX86_BUILTIN_MOVNTI64,
28221 IX86_BUILTIN_MOVNTPD,
28222 IX86_BUILTIN_MOVNTDQ,
28224 IX86_BUILTIN_MOVQ128,
28226 /* SSE2 MMX */
28227 IX86_BUILTIN_MASKMOVDQU,
28228 IX86_BUILTIN_MOVMSKPD,
28229 IX86_BUILTIN_PMOVMSKB128,
28231 IX86_BUILTIN_PACKSSWB128,
28232 IX86_BUILTIN_PACKSSDW128,
28233 IX86_BUILTIN_PACKUSWB128,
28235 IX86_BUILTIN_PADDB128,
28236 IX86_BUILTIN_PADDW128,
28237 IX86_BUILTIN_PADDD128,
28238 IX86_BUILTIN_PADDQ128,
28239 IX86_BUILTIN_PADDSB128,
28240 IX86_BUILTIN_PADDSW128,
28241 IX86_BUILTIN_PADDUSB128,
28242 IX86_BUILTIN_PADDUSW128,
28243 IX86_BUILTIN_PSUBB128,
28244 IX86_BUILTIN_PSUBW128,
28245 IX86_BUILTIN_PSUBD128,
28246 IX86_BUILTIN_PSUBQ128,
28247 IX86_BUILTIN_PSUBSB128,
28248 IX86_BUILTIN_PSUBSW128,
28249 IX86_BUILTIN_PSUBUSB128,
28250 IX86_BUILTIN_PSUBUSW128,
28252 IX86_BUILTIN_PAND128,
28253 IX86_BUILTIN_PANDN128,
28254 IX86_BUILTIN_POR128,
28255 IX86_BUILTIN_PXOR128,
28257 IX86_BUILTIN_PAVGB128,
28258 IX86_BUILTIN_PAVGW128,
28260 IX86_BUILTIN_PCMPEQB128,
28261 IX86_BUILTIN_PCMPEQW128,
28262 IX86_BUILTIN_PCMPEQD128,
28263 IX86_BUILTIN_PCMPGTB128,
28264 IX86_BUILTIN_PCMPGTW128,
28265 IX86_BUILTIN_PCMPGTD128,
28267 IX86_BUILTIN_PMADDWD128,
28269 IX86_BUILTIN_PMAXSW128,
28270 IX86_BUILTIN_PMAXUB128,
28271 IX86_BUILTIN_PMINSW128,
28272 IX86_BUILTIN_PMINUB128,
28274 IX86_BUILTIN_PMULUDQ,
28275 IX86_BUILTIN_PMULUDQ128,
28276 IX86_BUILTIN_PMULHUW128,
28277 IX86_BUILTIN_PMULHW128,
28278 IX86_BUILTIN_PMULLW128,
28280 IX86_BUILTIN_PSADBW128,
28281 IX86_BUILTIN_PSHUFHW,
28282 IX86_BUILTIN_PSHUFLW,
28283 IX86_BUILTIN_PSHUFD,
28285 IX86_BUILTIN_PSLLDQI128,
28286 IX86_BUILTIN_PSLLWI128,
28287 IX86_BUILTIN_PSLLDI128,
28288 IX86_BUILTIN_PSLLQI128,
28289 IX86_BUILTIN_PSRAWI128,
28290 IX86_BUILTIN_PSRADI128,
28291 IX86_BUILTIN_PSRLDQI128,
28292 IX86_BUILTIN_PSRLWI128,
28293 IX86_BUILTIN_PSRLDI128,
28294 IX86_BUILTIN_PSRLQI128,
28296 IX86_BUILTIN_PSLLDQ128,
28297 IX86_BUILTIN_PSLLW128,
28298 IX86_BUILTIN_PSLLD128,
28299 IX86_BUILTIN_PSLLQ128,
28300 IX86_BUILTIN_PSRAW128,
28301 IX86_BUILTIN_PSRAD128,
28302 IX86_BUILTIN_PSRLW128,
28303 IX86_BUILTIN_PSRLD128,
28304 IX86_BUILTIN_PSRLQ128,
28306 IX86_BUILTIN_PUNPCKHBW128,
28307 IX86_BUILTIN_PUNPCKHWD128,
28308 IX86_BUILTIN_PUNPCKHDQ128,
28309 IX86_BUILTIN_PUNPCKHQDQ128,
28310 IX86_BUILTIN_PUNPCKLBW128,
28311 IX86_BUILTIN_PUNPCKLWD128,
28312 IX86_BUILTIN_PUNPCKLDQ128,
28313 IX86_BUILTIN_PUNPCKLQDQ128,
28315 IX86_BUILTIN_CLFLUSH,
28316 IX86_BUILTIN_MFENCE,
28317 IX86_BUILTIN_LFENCE,
28318 IX86_BUILTIN_PAUSE,
28320 IX86_BUILTIN_FNSTENV,
28321 IX86_BUILTIN_FLDENV,
28322 IX86_BUILTIN_FNSTSW,
28323 IX86_BUILTIN_FNCLEX,
28325 IX86_BUILTIN_BSRSI,
28326 IX86_BUILTIN_BSRDI,
28327 IX86_BUILTIN_RDPMC,
28328 IX86_BUILTIN_RDTSC,
28329 IX86_BUILTIN_RDTSCP,
28330 IX86_BUILTIN_ROLQI,
28331 IX86_BUILTIN_ROLHI,
28332 IX86_BUILTIN_RORQI,
28333 IX86_BUILTIN_RORHI,
28335 /* SSE3. */
28336 IX86_BUILTIN_ADDSUBPS,
28337 IX86_BUILTIN_HADDPS,
28338 IX86_BUILTIN_HSUBPS,
28339 IX86_BUILTIN_MOVSHDUP,
28340 IX86_BUILTIN_MOVSLDUP,
28341 IX86_BUILTIN_ADDSUBPD,
28342 IX86_BUILTIN_HADDPD,
28343 IX86_BUILTIN_HSUBPD,
28344 IX86_BUILTIN_LDDQU,
28346 IX86_BUILTIN_MONITOR,
28347 IX86_BUILTIN_MWAIT,
28349 /* SSSE3. */
28350 IX86_BUILTIN_PHADDW,
28351 IX86_BUILTIN_PHADDD,
28352 IX86_BUILTIN_PHADDSW,
28353 IX86_BUILTIN_PHSUBW,
28354 IX86_BUILTIN_PHSUBD,
28355 IX86_BUILTIN_PHSUBSW,
28356 IX86_BUILTIN_PMADDUBSW,
28357 IX86_BUILTIN_PMULHRSW,
28358 IX86_BUILTIN_PSHUFB,
28359 IX86_BUILTIN_PSIGNB,
28360 IX86_BUILTIN_PSIGNW,
28361 IX86_BUILTIN_PSIGND,
28362 IX86_BUILTIN_PALIGNR,
28363 IX86_BUILTIN_PABSB,
28364 IX86_BUILTIN_PABSW,
28365 IX86_BUILTIN_PABSD,
28367 IX86_BUILTIN_PHADDW128,
28368 IX86_BUILTIN_PHADDD128,
28369 IX86_BUILTIN_PHADDSW128,
28370 IX86_BUILTIN_PHSUBW128,
28371 IX86_BUILTIN_PHSUBD128,
28372 IX86_BUILTIN_PHSUBSW128,
28373 IX86_BUILTIN_PMADDUBSW128,
28374 IX86_BUILTIN_PMULHRSW128,
28375 IX86_BUILTIN_PSHUFB128,
28376 IX86_BUILTIN_PSIGNB128,
28377 IX86_BUILTIN_PSIGNW128,
28378 IX86_BUILTIN_PSIGND128,
28379 IX86_BUILTIN_PALIGNR128,
28380 IX86_BUILTIN_PABSB128,
28381 IX86_BUILTIN_PABSW128,
28382 IX86_BUILTIN_PABSD128,
28384 /* AMDFAM10 - SSE4A New Instructions. */
28385 IX86_BUILTIN_MOVNTSD,
28386 IX86_BUILTIN_MOVNTSS,
28387 IX86_BUILTIN_EXTRQI,
28388 IX86_BUILTIN_EXTRQ,
28389 IX86_BUILTIN_INSERTQI,
28390 IX86_BUILTIN_INSERTQ,
28392 /* SSE4.1. */
28393 IX86_BUILTIN_BLENDPD,
28394 IX86_BUILTIN_BLENDPS,
28395 IX86_BUILTIN_BLENDVPD,
28396 IX86_BUILTIN_BLENDVPS,
28397 IX86_BUILTIN_PBLENDVB128,
28398 IX86_BUILTIN_PBLENDW128,
28400 IX86_BUILTIN_DPPD,
28401 IX86_BUILTIN_DPPS,
28403 IX86_BUILTIN_INSERTPS128,
28405 IX86_BUILTIN_MOVNTDQA,
28406 IX86_BUILTIN_MPSADBW128,
28407 IX86_BUILTIN_PACKUSDW128,
28408 IX86_BUILTIN_PCMPEQQ,
28409 IX86_BUILTIN_PHMINPOSUW128,
28411 IX86_BUILTIN_PMAXSB128,
28412 IX86_BUILTIN_PMAXSD128,
28413 IX86_BUILTIN_PMAXUD128,
28414 IX86_BUILTIN_PMAXUW128,
28416 IX86_BUILTIN_PMINSB128,
28417 IX86_BUILTIN_PMINSD128,
28418 IX86_BUILTIN_PMINUD128,
28419 IX86_BUILTIN_PMINUW128,
28421 IX86_BUILTIN_PMOVSXBW128,
28422 IX86_BUILTIN_PMOVSXBD128,
28423 IX86_BUILTIN_PMOVSXBQ128,
28424 IX86_BUILTIN_PMOVSXWD128,
28425 IX86_BUILTIN_PMOVSXWQ128,
28426 IX86_BUILTIN_PMOVSXDQ128,
28428 IX86_BUILTIN_PMOVZXBW128,
28429 IX86_BUILTIN_PMOVZXBD128,
28430 IX86_BUILTIN_PMOVZXBQ128,
28431 IX86_BUILTIN_PMOVZXWD128,
28432 IX86_BUILTIN_PMOVZXWQ128,
28433 IX86_BUILTIN_PMOVZXDQ128,
28435 IX86_BUILTIN_PMULDQ128,
28436 IX86_BUILTIN_PMULLD128,
28438 IX86_BUILTIN_ROUNDSD,
28439 IX86_BUILTIN_ROUNDSS,
28441 IX86_BUILTIN_ROUNDPD,
28442 IX86_BUILTIN_ROUNDPS,
28444 IX86_BUILTIN_FLOORPD,
28445 IX86_BUILTIN_CEILPD,
28446 IX86_BUILTIN_TRUNCPD,
28447 IX86_BUILTIN_RINTPD,
28448 IX86_BUILTIN_ROUNDPD_AZ,
28450 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28451 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28452 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28454 IX86_BUILTIN_FLOORPS,
28455 IX86_BUILTIN_CEILPS,
28456 IX86_BUILTIN_TRUNCPS,
28457 IX86_BUILTIN_RINTPS,
28458 IX86_BUILTIN_ROUNDPS_AZ,
28460 IX86_BUILTIN_FLOORPS_SFIX,
28461 IX86_BUILTIN_CEILPS_SFIX,
28462 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28464 IX86_BUILTIN_PTESTZ,
28465 IX86_BUILTIN_PTESTC,
28466 IX86_BUILTIN_PTESTNZC,
28468 IX86_BUILTIN_VEC_INIT_V2SI,
28469 IX86_BUILTIN_VEC_INIT_V4HI,
28470 IX86_BUILTIN_VEC_INIT_V8QI,
28471 IX86_BUILTIN_VEC_EXT_V2DF,
28472 IX86_BUILTIN_VEC_EXT_V2DI,
28473 IX86_BUILTIN_VEC_EXT_V4SF,
28474 IX86_BUILTIN_VEC_EXT_V4SI,
28475 IX86_BUILTIN_VEC_EXT_V8HI,
28476 IX86_BUILTIN_VEC_EXT_V2SI,
28477 IX86_BUILTIN_VEC_EXT_V4HI,
28478 IX86_BUILTIN_VEC_EXT_V16QI,
28479 IX86_BUILTIN_VEC_SET_V2DI,
28480 IX86_BUILTIN_VEC_SET_V4SF,
28481 IX86_BUILTIN_VEC_SET_V4SI,
28482 IX86_BUILTIN_VEC_SET_V8HI,
28483 IX86_BUILTIN_VEC_SET_V4HI,
28484 IX86_BUILTIN_VEC_SET_V16QI,
28486 IX86_BUILTIN_VEC_PACK_SFIX,
28487 IX86_BUILTIN_VEC_PACK_SFIX256,
28489 /* SSE4.2. */
28490 IX86_BUILTIN_CRC32QI,
28491 IX86_BUILTIN_CRC32HI,
28492 IX86_BUILTIN_CRC32SI,
28493 IX86_BUILTIN_CRC32DI,
28495 IX86_BUILTIN_PCMPESTRI128,
28496 IX86_BUILTIN_PCMPESTRM128,
28497 IX86_BUILTIN_PCMPESTRA128,
28498 IX86_BUILTIN_PCMPESTRC128,
28499 IX86_BUILTIN_PCMPESTRO128,
28500 IX86_BUILTIN_PCMPESTRS128,
28501 IX86_BUILTIN_PCMPESTRZ128,
28502 IX86_BUILTIN_PCMPISTRI128,
28503 IX86_BUILTIN_PCMPISTRM128,
28504 IX86_BUILTIN_PCMPISTRA128,
28505 IX86_BUILTIN_PCMPISTRC128,
28506 IX86_BUILTIN_PCMPISTRO128,
28507 IX86_BUILTIN_PCMPISTRS128,
28508 IX86_BUILTIN_PCMPISTRZ128,
28510 IX86_BUILTIN_PCMPGTQ,
28512 /* AES instructions */
28513 IX86_BUILTIN_AESENC128,
28514 IX86_BUILTIN_AESENCLAST128,
28515 IX86_BUILTIN_AESDEC128,
28516 IX86_BUILTIN_AESDECLAST128,
28517 IX86_BUILTIN_AESIMC128,
28518 IX86_BUILTIN_AESKEYGENASSIST128,
28520 /* PCLMUL instruction */
28521 IX86_BUILTIN_PCLMULQDQ128,
28523 /* AVX */
28524 IX86_BUILTIN_ADDPD256,
28525 IX86_BUILTIN_ADDPS256,
28526 IX86_BUILTIN_ADDSUBPD256,
28527 IX86_BUILTIN_ADDSUBPS256,
28528 IX86_BUILTIN_ANDPD256,
28529 IX86_BUILTIN_ANDPS256,
28530 IX86_BUILTIN_ANDNPD256,
28531 IX86_BUILTIN_ANDNPS256,
28532 IX86_BUILTIN_BLENDPD256,
28533 IX86_BUILTIN_BLENDPS256,
28534 IX86_BUILTIN_BLENDVPD256,
28535 IX86_BUILTIN_BLENDVPS256,
28536 IX86_BUILTIN_DIVPD256,
28537 IX86_BUILTIN_DIVPS256,
28538 IX86_BUILTIN_DPPS256,
28539 IX86_BUILTIN_HADDPD256,
28540 IX86_BUILTIN_HADDPS256,
28541 IX86_BUILTIN_HSUBPD256,
28542 IX86_BUILTIN_HSUBPS256,
28543 IX86_BUILTIN_MAXPD256,
28544 IX86_BUILTIN_MAXPS256,
28545 IX86_BUILTIN_MINPD256,
28546 IX86_BUILTIN_MINPS256,
28547 IX86_BUILTIN_MULPD256,
28548 IX86_BUILTIN_MULPS256,
28549 IX86_BUILTIN_ORPD256,
28550 IX86_BUILTIN_ORPS256,
28551 IX86_BUILTIN_SHUFPD256,
28552 IX86_BUILTIN_SHUFPS256,
28553 IX86_BUILTIN_SUBPD256,
28554 IX86_BUILTIN_SUBPS256,
28555 IX86_BUILTIN_XORPD256,
28556 IX86_BUILTIN_XORPS256,
28557 IX86_BUILTIN_CMPSD,
28558 IX86_BUILTIN_CMPSS,
28559 IX86_BUILTIN_CMPPD,
28560 IX86_BUILTIN_CMPPS,
28561 IX86_BUILTIN_CMPPD256,
28562 IX86_BUILTIN_CMPPS256,
28563 IX86_BUILTIN_CVTDQ2PD256,
28564 IX86_BUILTIN_CVTDQ2PS256,
28565 IX86_BUILTIN_CVTPD2PS256,
28566 IX86_BUILTIN_CVTPS2DQ256,
28567 IX86_BUILTIN_CVTPS2PD256,
28568 IX86_BUILTIN_CVTTPD2DQ256,
28569 IX86_BUILTIN_CVTPD2DQ256,
28570 IX86_BUILTIN_CVTTPS2DQ256,
28571 IX86_BUILTIN_EXTRACTF128PD256,
28572 IX86_BUILTIN_EXTRACTF128PS256,
28573 IX86_BUILTIN_EXTRACTF128SI256,
28574 IX86_BUILTIN_VZEROALL,
28575 IX86_BUILTIN_VZEROUPPER,
28576 IX86_BUILTIN_VPERMILVARPD,
28577 IX86_BUILTIN_VPERMILVARPS,
28578 IX86_BUILTIN_VPERMILVARPD256,
28579 IX86_BUILTIN_VPERMILVARPS256,
28580 IX86_BUILTIN_VPERMILPD,
28581 IX86_BUILTIN_VPERMILPS,
28582 IX86_BUILTIN_VPERMILPD256,
28583 IX86_BUILTIN_VPERMILPS256,
28584 IX86_BUILTIN_VPERMIL2PD,
28585 IX86_BUILTIN_VPERMIL2PS,
28586 IX86_BUILTIN_VPERMIL2PD256,
28587 IX86_BUILTIN_VPERMIL2PS256,
28588 IX86_BUILTIN_VPERM2F128PD256,
28589 IX86_BUILTIN_VPERM2F128PS256,
28590 IX86_BUILTIN_VPERM2F128SI256,
28591 IX86_BUILTIN_VBROADCASTSS,
28592 IX86_BUILTIN_VBROADCASTSD256,
28593 IX86_BUILTIN_VBROADCASTSS256,
28594 IX86_BUILTIN_VBROADCASTPD256,
28595 IX86_BUILTIN_VBROADCASTPS256,
28596 IX86_BUILTIN_VINSERTF128PD256,
28597 IX86_BUILTIN_VINSERTF128PS256,
28598 IX86_BUILTIN_VINSERTF128SI256,
28599 IX86_BUILTIN_LOADUPD256,
28600 IX86_BUILTIN_LOADUPS256,
28601 IX86_BUILTIN_STOREUPD256,
28602 IX86_BUILTIN_STOREUPS256,
28603 IX86_BUILTIN_LDDQU256,
28604 IX86_BUILTIN_MOVNTDQ256,
28605 IX86_BUILTIN_MOVNTPD256,
28606 IX86_BUILTIN_MOVNTPS256,
28607 IX86_BUILTIN_LOADDQU256,
28608 IX86_BUILTIN_STOREDQU256,
28609 IX86_BUILTIN_MASKLOADPD,
28610 IX86_BUILTIN_MASKLOADPS,
28611 IX86_BUILTIN_MASKSTOREPD,
28612 IX86_BUILTIN_MASKSTOREPS,
28613 IX86_BUILTIN_MASKLOADPD256,
28614 IX86_BUILTIN_MASKLOADPS256,
28615 IX86_BUILTIN_MASKSTOREPD256,
28616 IX86_BUILTIN_MASKSTOREPS256,
28617 IX86_BUILTIN_MOVSHDUP256,
28618 IX86_BUILTIN_MOVSLDUP256,
28619 IX86_BUILTIN_MOVDDUP256,
28621 IX86_BUILTIN_SQRTPD256,
28622 IX86_BUILTIN_SQRTPS256,
28623 IX86_BUILTIN_SQRTPS_NR256,
28624 IX86_BUILTIN_RSQRTPS256,
28625 IX86_BUILTIN_RSQRTPS_NR256,
28627 IX86_BUILTIN_RCPPS256,
28629 IX86_BUILTIN_ROUNDPD256,
28630 IX86_BUILTIN_ROUNDPS256,
28632 IX86_BUILTIN_FLOORPD256,
28633 IX86_BUILTIN_CEILPD256,
28634 IX86_BUILTIN_TRUNCPD256,
28635 IX86_BUILTIN_RINTPD256,
28636 IX86_BUILTIN_ROUNDPD_AZ256,
28638 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28639 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28640 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28642 IX86_BUILTIN_FLOORPS256,
28643 IX86_BUILTIN_CEILPS256,
28644 IX86_BUILTIN_TRUNCPS256,
28645 IX86_BUILTIN_RINTPS256,
28646 IX86_BUILTIN_ROUNDPS_AZ256,
28648 IX86_BUILTIN_FLOORPS_SFIX256,
28649 IX86_BUILTIN_CEILPS_SFIX256,
28650 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28652 IX86_BUILTIN_UNPCKHPD256,
28653 IX86_BUILTIN_UNPCKLPD256,
28654 IX86_BUILTIN_UNPCKHPS256,
28655 IX86_BUILTIN_UNPCKLPS256,
28657 IX86_BUILTIN_SI256_SI,
28658 IX86_BUILTIN_PS256_PS,
28659 IX86_BUILTIN_PD256_PD,
28660 IX86_BUILTIN_SI_SI256,
28661 IX86_BUILTIN_PS_PS256,
28662 IX86_BUILTIN_PD_PD256,
28664 IX86_BUILTIN_VTESTZPD,
28665 IX86_BUILTIN_VTESTCPD,
28666 IX86_BUILTIN_VTESTNZCPD,
28667 IX86_BUILTIN_VTESTZPS,
28668 IX86_BUILTIN_VTESTCPS,
28669 IX86_BUILTIN_VTESTNZCPS,
28670 IX86_BUILTIN_VTESTZPD256,
28671 IX86_BUILTIN_VTESTCPD256,
28672 IX86_BUILTIN_VTESTNZCPD256,
28673 IX86_BUILTIN_VTESTZPS256,
28674 IX86_BUILTIN_VTESTCPS256,
28675 IX86_BUILTIN_VTESTNZCPS256,
28676 IX86_BUILTIN_PTESTZ256,
28677 IX86_BUILTIN_PTESTC256,
28678 IX86_BUILTIN_PTESTNZC256,
28680 IX86_BUILTIN_MOVMSKPD256,
28681 IX86_BUILTIN_MOVMSKPS256,
28683 /* AVX2 */
28684 IX86_BUILTIN_MPSADBW256,
28685 IX86_BUILTIN_PABSB256,
28686 IX86_BUILTIN_PABSW256,
28687 IX86_BUILTIN_PABSD256,
28688 IX86_BUILTIN_PACKSSDW256,
28689 IX86_BUILTIN_PACKSSWB256,
28690 IX86_BUILTIN_PACKUSDW256,
28691 IX86_BUILTIN_PACKUSWB256,
28692 IX86_BUILTIN_PADDB256,
28693 IX86_BUILTIN_PADDW256,
28694 IX86_BUILTIN_PADDD256,
28695 IX86_BUILTIN_PADDQ256,
28696 IX86_BUILTIN_PADDSB256,
28697 IX86_BUILTIN_PADDSW256,
28698 IX86_BUILTIN_PADDUSB256,
28699 IX86_BUILTIN_PADDUSW256,
28700 IX86_BUILTIN_PALIGNR256,
28701 IX86_BUILTIN_AND256I,
28702 IX86_BUILTIN_ANDNOT256I,
28703 IX86_BUILTIN_PAVGB256,
28704 IX86_BUILTIN_PAVGW256,
28705 IX86_BUILTIN_PBLENDVB256,
28706 IX86_BUILTIN_PBLENDVW256,
28707 IX86_BUILTIN_PCMPEQB256,
28708 IX86_BUILTIN_PCMPEQW256,
28709 IX86_BUILTIN_PCMPEQD256,
28710 IX86_BUILTIN_PCMPEQQ256,
28711 IX86_BUILTIN_PCMPGTB256,
28712 IX86_BUILTIN_PCMPGTW256,
28713 IX86_BUILTIN_PCMPGTD256,
28714 IX86_BUILTIN_PCMPGTQ256,
28715 IX86_BUILTIN_PHADDW256,
28716 IX86_BUILTIN_PHADDD256,
28717 IX86_BUILTIN_PHADDSW256,
28718 IX86_BUILTIN_PHSUBW256,
28719 IX86_BUILTIN_PHSUBD256,
28720 IX86_BUILTIN_PHSUBSW256,
28721 IX86_BUILTIN_PMADDUBSW256,
28722 IX86_BUILTIN_PMADDWD256,
28723 IX86_BUILTIN_PMAXSB256,
28724 IX86_BUILTIN_PMAXSW256,
28725 IX86_BUILTIN_PMAXSD256,
28726 IX86_BUILTIN_PMAXUB256,
28727 IX86_BUILTIN_PMAXUW256,
28728 IX86_BUILTIN_PMAXUD256,
28729 IX86_BUILTIN_PMINSB256,
28730 IX86_BUILTIN_PMINSW256,
28731 IX86_BUILTIN_PMINSD256,
28732 IX86_BUILTIN_PMINUB256,
28733 IX86_BUILTIN_PMINUW256,
28734 IX86_BUILTIN_PMINUD256,
28735 IX86_BUILTIN_PMOVMSKB256,
28736 IX86_BUILTIN_PMOVSXBW256,
28737 IX86_BUILTIN_PMOVSXBD256,
28738 IX86_BUILTIN_PMOVSXBQ256,
28739 IX86_BUILTIN_PMOVSXWD256,
28740 IX86_BUILTIN_PMOVSXWQ256,
28741 IX86_BUILTIN_PMOVSXDQ256,
28742 IX86_BUILTIN_PMOVZXBW256,
28743 IX86_BUILTIN_PMOVZXBD256,
28744 IX86_BUILTIN_PMOVZXBQ256,
28745 IX86_BUILTIN_PMOVZXWD256,
28746 IX86_BUILTIN_PMOVZXWQ256,
28747 IX86_BUILTIN_PMOVZXDQ256,
28748 IX86_BUILTIN_PMULDQ256,
28749 IX86_BUILTIN_PMULHRSW256,
28750 IX86_BUILTIN_PMULHUW256,
28751 IX86_BUILTIN_PMULHW256,
28752 IX86_BUILTIN_PMULLW256,
28753 IX86_BUILTIN_PMULLD256,
28754 IX86_BUILTIN_PMULUDQ256,
28755 IX86_BUILTIN_POR256,
28756 IX86_BUILTIN_PSADBW256,
28757 IX86_BUILTIN_PSHUFB256,
28758 IX86_BUILTIN_PSHUFD256,
28759 IX86_BUILTIN_PSHUFHW256,
28760 IX86_BUILTIN_PSHUFLW256,
28761 IX86_BUILTIN_PSIGNB256,
28762 IX86_BUILTIN_PSIGNW256,
28763 IX86_BUILTIN_PSIGND256,
28764 IX86_BUILTIN_PSLLDQI256,
28765 IX86_BUILTIN_PSLLWI256,
28766 IX86_BUILTIN_PSLLW256,
28767 IX86_BUILTIN_PSLLDI256,
28768 IX86_BUILTIN_PSLLD256,
28769 IX86_BUILTIN_PSLLQI256,
28770 IX86_BUILTIN_PSLLQ256,
28771 IX86_BUILTIN_PSRAWI256,
28772 IX86_BUILTIN_PSRAW256,
28773 IX86_BUILTIN_PSRADI256,
28774 IX86_BUILTIN_PSRAD256,
28775 IX86_BUILTIN_PSRLDQI256,
28776 IX86_BUILTIN_PSRLWI256,
28777 IX86_BUILTIN_PSRLW256,
28778 IX86_BUILTIN_PSRLDI256,
28779 IX86_BUILTIN_PSRLD256,
28780 IX86_BUILTIN_PSRLQI256,
28781 IX86_BUILTIN_PSRLQ256,
28782 IX86_BUILTIN_PSUBB256,
28783 IX86_BUILTIN_PSUBW256,
28784 IX86_BUILTIN_PSUBD256,
28785 IX86_BUILTIN_PSUBQ256,
28786 IX86_BUILTIN_PSUBSB256,
28787 IX86_BUILTIN_PSUBSW256,
28788 IX86_BUILTIN_PSUBUSB256,
28789 IX86_BUILTIN_PSUBUSW256,
28790 IX86_BUILTIN_PUNPCKHBW256,
28791 IX86_BUILTIN_PUNPCKHWD256,
28792 IX86_BUILTIN_PUNPCKHDQ256,
28793 IX86_BUILTIN_PUNPCKHQDQ256,
28794 IX86_BUILTIN_PUNPCKLBW256,
28795 IX86_BUILTIN_PUNPCKLWD256,
28796 IX86_BUILTIN_PUNPCKLDQ256,
28797 IX86_BUILTIN_PUNPCKLQDQ256,
28798 IX86_BUILTIN_PXOR256,
28799 IX86_BUILTIN_MOVNTDQA256,
28800 IX86_BUILTIN_VBROADCASTSS_PS,
28801 IX86_BUILTIN_VBROADCASTSS_PS256,
28802 IX86_BUILTIN_VBROADCASTSD_PD256,
28803 IX86_BUILTIN_VBROADCASTSI256,
28804 IX86_BUILTIN_PBLENDD256,
28805 IX86_BUILTIN_PBLENDD128,
28806 IX86_BUILTIN_PBROADCASTB256,
28807 IX86_BUILTIN_PBROADCASTW256,
28808 IX86_BUILTIN_PBROADCASTD256,
28809 IX86_BUILTIN_PBROADCASTQ256,
28810 IX86_BUILTIN_PBROADCASTB128,
28811 IX86_BUILTIN_PBROADCASTW128,
28812 IX86_BUILTIN_PBROADCASTD128,
28813 IX86_BUILTIN_PBROADCASTQ128,
28814 IX86_BUILTIN_VPERMVARSI256,
28815 IX86_BUILTIN_VPERMDF256,
28816 IX86_BUILTIN_VPERMVARSF256,
28817 IX86_BUILTIN_VPERMDI256,
28818 IX86_BUILTIN_VPERMTI256,
28819 IX86_BUILTIN_VEXTRACT128I256,
28820 IX86_BUILTIN_VINSERT128I256,
28821 IX86_BUILTIN_MASKLOADD,
28822 IX86_BUILTIN_MASKLOADQ,
28823 IX86_BUILTIN_MASKLOADD256,
28824 IX86_BUILTIN_MASKLOADQ256,
28825 IX86_BUILTIN_MASKSTORED,
28826 IX86_BUILTIN_MASKSTOREQ,
28827 IX86_BUILTIN_MASKSTORED256,
28828 IX86_BUILTIN_MASKSTOREQ256,
28829 IX86_BUILTIN_PSLLVV4DI,
28830 IX86_BUILTIN_PSLLVV2DI,
28831 IX86_BUILTIN_PSLLVV8SI,
28832 IX86_BUILTIN_PSLLVV4SI,
28833 IX86_BUILTIN_PSRAVV8SI,
28834 IX86_BUILTIN_PSRAVV4SI,
28835 IX86_BUILTIN_PSRLVV4DI,
28836 IX86_BUILTIN_PSRLVV2DI,
28837 IX86_BUILTIN_PSRLVV8SI,
28838 IX86_BUILTIN_PSRLVV4SI,
28840 IX86_BUILTIN_GATHERSIV2DF,
28841 IX86_BUILTIN_GATHERSIV4DF,
28842 IX86_BUILTIN_GATHERDIV2DF,
28843 IX86_BUILTIN_GATHERDIV4DF,
28844 IX86_BUILTIN_GATHERSIV4SF,
28845 IX86_BUILTIN_GATHERSIV8SF,
28846 IX86_BUILTIN_GATHERDIV4SF,
28847 IX86_BUILTIN_GATHERDIV8SF,
28848 IX86_BUILTIN_GATHERSIV2DI,
28849 IX86_BUILTIN_GATHERSIV4DI,
28850 IX86_BUILTIN_GATHERDIV2DI,
28851 IX86_BUILTIN_GATHERDIV4DI,
28852 IX86_BUILTIN_GATHERSIV4SI,
28853 IX86_BUILTIN_GATHERSIV8SI,
28854 IX86_BUILTIN_GATHERDIV4SI,
28855 IX86_BUILTIN_GATHERDIV8SI,
28857 /* AVX512F */
28858 IX86_BUILTIN_SI512_SI256,
28859 IX86_BUILTIN_PD512_PD256,
28860 IX86_BUILTIN_PS512_PS256,
28861 IX86_BUILTIN_SI512_SI,
28862 IX86_BUILTIN_PD512_PD,
28863 IX86_BUILTIN_PS512_PS,
28864 IX86_BUILTIN_ADDPD512,
28865 IX86_BUILTIN_ADDPS512,
28866 IX86_BUILTIN_ADDSD_ROUND,
28867 IX86_BUILTIN_ADDSS_ROUND,
28868 IX86_BUILTIN_ALIGND512,
28869 IX86_BUILTIN_ALIGNQ512,
28870 IX86_BUILTIN_BLENDMD512,
28871 IX86_BUILTIN_BLENDMPD512,
28872 IX86_BUILTIN_BLENDMPS512,
28873 IX86_BUILTIN_BLENDMQ512,
28874 IX86_BUILTIN_BROADCASTF32X4_512,
28875 IX86_BUILTIN_BROADCASTF64X4_512,
28876 IX86_BUILTIN_BROADCASTI32X4_512,
28877 IX86_BUILTIN_BROADCASTI64X4_512,
28878 IX86_BUILTIN_BROADCASTSD512,
28879 IX86_BUILTIN_BROADCASTSS512,
28880 IX86_BUILTIN_CMPD512,
28881 IX86_BUILTIN_CMPPD512,
28882 IX86_BUILTIN_CMPPS512,
28883 IX86_BUILTIN_CMPQ512,
28884 IX86_BUILTIN_CMPSD_MASK,
28885 IX86_BUILTIN_CMPSS_MASK,
28886 IX86_BUILTIN_COMIDF,
28887 IX86_BUILTIN_COMISF,
28888 IX86_BUILTIN_COMPRESSPD512,
28889 IX86_BUILTIN_COMPRESSPDSTORE512,
28890 IX86_BUILTIN_COMPRESSPS512,
28891 IX86_BUILTIN_COMPRESSPSSTORE512,
28892 IX86_BUILTIN_CVTDQ2PD512,
28893 IX86_BUILTIN_CVTDQ2PS512,
28894 IX86_BUILTIN_CVTPD2DQ512,
28895 IX86_BUILTIN_CVTPD2PS512,
28896 IX86_BUILTIN_CVTPD2UDQ512,
28897 IX86_BUILTIN_CVTPH2PS512,
28898 IX86_BUILTIN_CVTPS2DQ512,
28899 IX86_BUILTIN_CVTPS2PD512,
28900 IX86_BUILTIN_CVTPS2PH512,
28901 IX86_BUILTIN_CVTPS2UDQ512,
28902 IX86_BUILTIN_CVTSD2SS_ROUND,
28903 IX86_BUILTIN_CVTSI2SD64,
28904 IX86_BUILTIN_CVTSI2SS32,
28905 IX86_BUILTIN_CVTSI2SS64,
28906 IX86_BUILTIN_CVTSS2SD_ROUND,
28907 IX86_BUILTIN_CVTTPD2DQ512,
28908 IX86_BUILTIN_CVTTPD2UDQ512,
28909 IX86_BUILTIN_CVTTPS2DQ512,
28910 IX86_BUILTIN_CVTTPS2UDQ512,
28911 IX86_BUILTIN_CVTUDQ2PD512,
28912 IX86_BUILTIN_CVTUDQ2PS512,
28913 IX86_BUILTIN_CVTUSI2SD32,
28914 IX86_BUILTIN_CVTUSI2SD64,
28915 IX86_BUILTIN_CVTUSI2SS32,
28916 IX86_BUILTIN_CVTUSI2SS64,
28917 IX86_BUILTIN_DIVPD512,
28918 IX86_BUILTIN_DIVPS512,
28919 IX86_BUILTIN_DIVSD_ROUND,
28920 IX86_BUILTIN_DIVSS_ROUND,
28921 IX86_BUILTIN_EXPANDPD512,
28922 IX86_BUILTIN_EXPANDPD512Z,
28923 IX86_BUILTIN_EXPANDPDLOAD512,
28924 IX86_BUILTIN_EXPANDPDLOAD512Z,
28925 IX86_BUILTIN_EXPANDPS512,
28926 IX86_BUILTIN_EXPANDPS512Z,
28927 IX86_BUILTIN_EXPANDPSLOAD512,
28928 IX86_BUILTIN_EXPANDPSLOAD512Z,
28929 IX86_BUILTIN_EXTRACTF32X4,
28930 IX86_BUILTIN_EXTRACTF64X4,
28931 IX86_BUILTIN_EXTRACTI32X4,
28932 IX86_BUILTIN_EXTRACTI64X4,
28933 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28934 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28935 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28936 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28937 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28938 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28939 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28940 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28941 IX86_BUILTIN_GETEXPPD512,
28942 IX86_BUILTIN_GETEXPPS512,
28943 IX86_BUILTIN_GETEXPSD128,
28944 IX86_BUILTIN_GETEXPSS128,
28945 IX86_BUILTIN_GETMANTPD512,
28946 IX86_BUILTIN_GETMANTPS512,
28947 IX86_BUILTIN_GETMANTSD128,
28948 IX86_BUILTIN_GETMANTSS128,
28949 IX86_BUILTIN_INSERTF32X4,
28950 IX86_BUILTIN_INSERTF64X4,
28951 IX86_BUILTIN_INSERTI32X4,
28952 IX86_BUILTIN_INSERTI64X4,
28953 IX86_BUILTIN_LOADAPD512,
28954 IX86_BUILTIN_LOADAPS512,
28955 IX86_BUILTIN_LOADDQUDI512,
28956 IX86_BUILTIN_LOADDQUSI512,
28957 IX86_BUILTIN_LOADUPD512,
28958 IX86_BUILTIN_LOADUPS512,
28959 IX86_BUILTIN_MAXPD512,
28960 IX86_BUILTIN_MAXPS512,
28961 IX86_BUILTIN_MAXSD_ROUND,
28962 IX86_BUILTIN_MAXSS_ROUND,
28963 IX86_BUILTIN_MINPD512,
28964 IX86_BUILTIN_MINPS512,
28965 IX86_BUILTIN_MINSD_ROUND,
28966 IX86_BUILTIN_MINSS_ROUND,
28967 IX86_BUILTIN_MOVAPD512,
28968 IX86_BUILTIN_MOVAPS512,
28969 IX86_BUILTIN_MOVDDUP512,
28970 IX86_BUILTIN_MOVDQA32LOAD512,
28971 IX86_BUILTIN_MOVDQA32STORE512,
28972 IX86_BUILTIN_MOVDQA32_512,
28973 IX86_BUILTIN_MOVDQA64LOAD512,
28974 IX86_BUILTIN_MOVDQA64STORE512,
28975 IX86_BUILTIN_MOVDQA64_512,
28976 IX86_BUILTIN_MOVNTDQ512,
28977 IX86_BUILTIN_MOVNTDQA512,
28978 IX86_BUILTIN_MOVNTPD512,
28979 IX86_BUILTIN_MOVNTPS512,
28980 IX86_BUILTIN_MOVSHDUP512,
28981 IX86_BUILTIN_MOVSLDUP512,
28982 IX86_BUILTIN_MULPD512,
28983 IX86_BUILTIN_MULPS512,
28984 IX86_BUILTIN_MULSD_ROUND,
28985 IX86_BUILTIN_MULSS_ROUND,
28986 IX86_BUILTIN_PABSD512,
28987 IX86_BUILTIN_PABSQ512,
28988 IX86_BUILTIN_PADDD512,
28989 IX86_BUILTIN_PADDQ512,
28990 IX86_BUILTIN_PANDD512,
28991 IX86_BUILTIN_PANDND512,
28992 IX86_BUILTIN_PANDNQ512,
28993 IX86_BUILTIN_PANDQ512,
28994 IX86_BUILTIN_PBROADCASTD512,
28995 IX86_BUILTIN_PBROADCASTD512_GPR,
28996 IX86_BUILTIN_PBROADCASTMB512,
28997 IX86_BUILTIN_PBROADCASTMW512,
28998 IX86_BUILTIN_PBROADCASTQ512,
28999 IX86_BUILTIN_PBROADCASTQ512_GPR,
29000 IX86_BUILTIN_PCMPEQD512_MASK,
29001 IX86_BUILTIN_PCMPEQQ512_MASK,
29002 IX86_BUILTIN_PCMPGTD512_MASK,
29003 IX86_BUILTIN_PCMPGTQ512_MASK,
29004 IX86_BUILTIN_PCOMPRESSD512,
29005 IX86_BUILTIN_PCOMPRESSDSTORE512,
29006 IX86_BUILTIN_PCOMPRESSQ512,
29007 IX86_BUILTIN_PCOMPRESSQSTORE512,
29008 IX86_BUILTIN_PEXPANDD512,
29009 IX86_BUILTIN_PEXPANDD512Z,
29010 IX86_BUILTIN_PEXPANDDLOAD512,
29011 IX86_BUILTIN_PEXPANDDLOAD512Z,
29012 IX86_BUILTIN_PEXPANDQ512,
29013 IX86_BUILTIN_PEXPANDQ512Z,
29014 IX86_BUILTIN_PEXPANDQLOAD512,
29015 IX86_BUILTIN_PEXPANDQLOAD512Z,
29016 IX86_BUILTIN_PMAXSD512,
29017 IX86_BUILTIN_PMAXSQ512,
29018 IX86_BUILTIN_PMAXUD512,
29019 IX86_BUILTIN_PMAXUQ512,
29020 IX86_BUILTIN_PMINSD512,
29021 IX86_BUILTIN_PMINSQ512,
29022 IX86_BUILTIN_PMINUD512,
29023 IX86_BUILTIN_PMINUQ512,
29024 IX86_BUILTIN_PMOVDB512,
29025 IX86_BUILTIN_PMOVDB512_MEM,
29026 IX86_BUILTIN_PMOVDW512,
29027 IX86_BUILTIN_PMOVDW512_MEM,
29028 IX86_BUILTIN_PMOVQB512,
29029 IX86_BUILTIN_PMOVQB512_MEM,
29030 IX86_BUILTIN_PMOVQD512,
29031 IX86_BUILTIN_PMOVQD512_MEM,
29032 IX86_BUILTIN_PMOVQW512,
29033 IX86_BUILTIN_PMOVQW512_MEM,
29034 IX86_BUILTIN_PMOVSDB512,
29035 IX86_BUILTIN_PMOVSDB512_MEM,
29036 IX86_BUILTIN_PMOVSDW512,
29037 IX86_BUILTIN_PMOVSDW512_MEM,
29038 IX86_BUILTIN_PMOVSQB512,
29039 IX86_BUILTIN_PMOVSQB512_MEM,
29040 IX86_BUILTIN_PMOVSQD512,
29041 IX86_BUILTIN_PMOVSQD512_MEM,
29042 IX86_BUILTIN_PMOVSQW512,
29043 IX86_BUILTIN_PMOVSQW512_MEM,
29044 IX86_BUILTIN_PMOVSXBD512,
29045 IX86_BUILTIN_PMOVSXBQ512,
29046 IX86_BUILTIN_PMOVSXDQ512,
29047 IX86_BUILTIN_PMOVSXWD512,
29048 IX86_BUILTIN_PMOVSXWQ512,
29049 IX86_BUILTIN_PMOVUSDB512,
29050 IX86_BUILTIN_PMOVUSDB512_MEM,
29051 IX86_BUILTIN_PMOVUSDW512,
29052 IX86_BUILTIN_PMOVUSDW512_MEM,
29053 IX86_BUILTIN_PMOVUSQB512,
29054 IX86_BUILTIN_PMOVUSQB512_MEM,
29055 IX86_BUILTIN_PMOVUSQD512,
29056 IX86_BUILTIN_PMOVUSQD512_MEM,
29057 IX86_BUILTIN_PMOVUSQW512,
29058 IX86_BUILTIN_PMOVUSQW512_MEM,
29059 IX86_BUILTIN_PMOVZXBD512,
29060 IX86_BUILTIN_PMOVZXBQ512,
29061 IX86_BUILTIN_PMOVZXDQ512,
29062 IX86_BUILTIN_PMOVZXWD512,
29063 IX86_BUILTIN_PMOVZXWQ512,
29064 IX86_BUILTIN_PMULDQ512,
29065 IX86_BUILTIN_PMULLD512,
29066 IX86_BUILTIN_PMULUDQ512,
29067 IX86_BUILTIN_PORD512,
29068 IX86_BUILTIN_PORQ512,
29069 IX86_BUILTIN_PROLD512,
29070 IX86_BUILTIN_PROLQ512,
29071 IX86_BUILTIN_PROLVD512,
29072 IX86_BUILTIN_PROLVQ512,
29073 IX86_BUILTIN_PRORD512,
29074 IX86_BUILTIN_PRORQ512,
29075 IX86_BUILTIN_PRORVD512,
29076 IX86_BUILTIN_PRORVQ512,
29077 IX86_BUILTIN_PSHUFD512,
29078 IX86_BUILTIN_PSLLD512,
29079 IX86_BUILTIN_PSLLDI512,
29080 IX86_BUILTIN_PSLLQ512,
29081 IX86_BUILTIN_PSLLQI512,
29082 IX86_BUILTIN_PSLLVV16SI,
29083 IX86_BUILTIN_PSLLVV8DI,
29084 IX86_BUILTIN_PSRAD512,
29085 IX86_BUILTIN_PSRADI512,
29086 IX86_BUILTIN_PSRAQ512,
29087 IX86_BUILTIN_PSRAQI512,
29088 IX86_BUILTIN_PSRAVV16SI,
29089 IX86_BUILTIN_PSRAVV8DI,
29090 IX86_BUILTIN_PSRLD512,
29091 IX86_BUILTIN_PSRLDI512,
29092 IX86_BUILTIN_PSRLQ512,
29093 IX86_BUILTIN_PSRLQI512,
29094 IX86_BUILTIN_PSRLVV16SI,
29095 IX86_BUILTIN_PSRLVV8DI,
29096 IX86_BUILTIN_PSUBD512,
29097 IX86_BUILTIN_PSUBQ512,
29098 IX86_BUILTIN_PTESTMD512,
29099 IX86_BUILTIN_PTESTMQ512,
29100 IX86_BUILTIN_PTESTNMD512,
29101 IX86_BUILTIN_PTESTNMQ512,
29102 IX86_BUILTIN_PUNPCKHDQ512,
29103 IX86_BUILTIN_PUNPCKHQDQ512,
29104 IX86_BUILTIN_PUNPCKLDQ512,
29105 IX86_BUILTIN_PUNPCKLQDQ512,
29106 IX86_BUILTIN_PXORD512,
29107 IX86_BUILTIN_PXORQ512,
29108 IX86_BUILTIN_RCP14PD512,
29109 IX86_BUILTIN_RCP14PS512,
29110 IX86_BUILTIN_RCP14SD,
29111 IX86_BUILTIN_RCP14SS,
29112 IX86_BUILTIN_RNDSCALEPD,
29113 IX86_BUILTIN_RNDSCALEPS,
29114 IX86_BUILTIN_RNDSCALESD,
29115 IX86_BUILTIN_RNDSCALESS,
29116 IX86_BUILTIN_RSQRT14PD512,
29117 IX86_BUILTIN_RSQRT14PS512,
29118 IX86_BUILTIN_RSQRT14SD,
29119 IX86_BUILTIN_RSQRT14SS,
29120 IX86_BUILTIN_SCALEFPD512,
29121 IX86_BUILTIN_SCALEFPS512,
29122 IX86_BUILTIN_SCALEFSD,
29123 IX86_BUILTIN_SCALEFSS,
29124 IX86_BUILTIN_SHUFPD512,
29125 IX86_BUILTIN_SHUFPS512,
29126 IX86_BUILTIN_SHUF_F32x4,
29127 IX86_BUILTIN_SHUF_F64x2,
29128 IX86_BUILTIN_SHUF_I32x4,
29129 IX86_BUILTIN_SHUF_I64x2,
29130 IX86_BUILTIN_SQRTPD512,
29131 IX86_BUILTIN_SQRTPD512_MASK,
29132 IX86_BUILTIN_SQRTPS512_MASK,
29133 IX86_BUILTIN_SQRTPS_NR512,
29134 IX86_BUILTIN_SQRTSD_ROUND,
29135 IX86_BUILTIN_SQRTSS_ROUND,
29136 IX86_BUILTIN_STOREAPD512,
29137 IX86_BUILTIN_STOREAPS512,
29138 IX86_BUILTIN_STOREDQUDI512,
29139 IX86_BUILTIN_STOREDQUSI512,
29140 IX86_BUILTIN_STOREUPD512,
29141 IX86_BUILTIN_STOREUPS512,
29142 IX86_BUILTIN_SUBPD512,
29143 IX86_BUILTIN_SUBPS512,
29144 IX86_BUILTIN_SUBSD_ROUND,
29145 IX86_BUILTIN_SUBSS_ROUND,
29146 IX86_BUILTIN_UCMPD512,
29147 IX86_BUILTIN_UCMPQ512,
29148 IX86_BUILTIN_UNPCKHPD512,
29149 IX86_BUILTIN_UNPCKHPS512,
29150 IX86_BUILTIN_UNPCKLPD512,
29151 IX86_BUILTIN_UNPCKLPS512,
29152 IX86_BUILTIN_VCVTSD2SI32,
29153 IX86_BUILTIN_VCVTSD2SI64,
29154 IX86_BUILTIN_VCVTSD2USI32,
29155 IX86_BUILTIN_VCVTSD2USI64,
29156 IX86_BUILTIN_VCVTSS2SI32,
29157 IX86_BUILTIN_VCVTSS2SI64,
29158 IX86_BUILTIN_VCVTSS2USI32,
29159 IX86_BUILTIN_VCVTSS2USI64,
29160 IX86_BUILTIN_VCVTTSD2SI32,
29161 IX86_BUILTIN_VCVTTSD2SI64,
29162 IX86_BUILTIN_VCVTTSD2USI32,
29163 IX86_BUILTIN_VCVTTSD2USI64,
29164 IX86_BUILTIN_VCVTTSS2SI32,
29165 IX86_BUILTIN_VCVTTSS2SI64,
29166 IX86_BUILTIN_VCVTTSS2USI32,
29167 IX86_BUILTIN_VCVTTSS2USI64,
29168 IX86_BUILTIN_VFMADDPD512_MASK,
29169 IX86_BUILTIN_VFMADDPD512_MASK3,
29170 IX86_BUILTIN_VFMADDPD512_MASKZ,
29171 IX86_BUILTIN_VFMADDPS512_MASK,
29172 IX86_BUILTIN_VFMADDPS512_MASK3,
29173 IX86_BUILTIN_VFMADDPS512_MASKZ,
29174 IX86_BUILTIN_VFMADDSD3_ROUND,
29175 IX86_BUILTIN_VFMADDSS3_ROUND,
29176 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29177 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29178 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29179 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29180 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29181 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29182 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29183 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29184 IX86_BUILTIN_VFMSUBPD512_MASK3,
29185 IX86_BUILTIN_VFMSUBPS512_MASK3,
29186 IX86_BUILTIN_VFMSUBSD3_MASK3,
29187 IX86_BUILTIN_VFMSUBSS3_MASK3,
29188 IX86_BUILTIN_VFNMADDPD512_MASK,
29189 IX86_BUILTIN_VFNMADDPS512_MASK,
29190 IX86_BUILTIN_VFNMSUBPD512_MASK,
29191 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29192 IX86_BUILTIN_VFNMSUBPS512_MASK,
29193 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29194 IX86_BUILTIN_VPCLZCNTD512,
29195 IX86_BUILTIN_VPCLZCNTQ512,
29196 IX86_BUILTIN_VPCONFLICTD512,
29197 IX86_BUILTIN_VPCONFLICTQ512,
29198 IX86_BUILTIN_VPERMDF512,
29199 IX86_BUILTIN_VPERMDI512,
29200 IX86_BUILTIN_VPERMI2VARD512,
29201 IX86_BUILTIN_VPERMI2VARPD512,
29202 IX86_BUILTIN_VPERMI2VARPS512,
29203 IX86_BUILTIN_VPERMI2VARQ512,
29204 IX86_BUILTIN_VPERMILPD512,
29205 IX86_BUILTIN_VPERMILPS512,
29206 IX86_BUILTIN_VPERMILVARPD512,
29207 IX86_BUILTIN_VPERMILVARPS512,
29208 IX86_BUILTIN_VPERMT2VARD512,
29209 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29210 IX86_BUILTIN_VPERMT2VARPD512,
29211 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29212 IX86_BUILTIN_VPERMT2VARPS512,
29213 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29214 IX86_BUILTIN_VPERMT2VARQ512,
29215 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29216 IX86_BUILTIN_VPERMVARDF512,
29217 IX86_BUILTIN_VPERMVARDI512,
29218 IX86_BUILTIN_VPERMVARSF512,
29219 IX86_BUILTIN_VPERMVARSI512,
29220 IX86_BUILTIN_VTERNLOGD512_MASK,
29221 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29222 IX86_BUILTIN_VTERNLOGQ512_MASK,
29223 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29225 /* Mask arithmetic operations */
29226 IX86_BUILTIN_KAND16,
29227 IX86_BUILTIN_KANDN16,
29228 IX86_BUILTIN_KNOT16,
29229 IX86_BUILTIN_KOR16,
29230 IX86_BUILTIN_KORTESTC16,
29231 IX86_BUILTIN_KORTESTZ16,
29232 IX86_BUILTIN_KUNPCKBW,
29233 IX86_BUILTIN_KXNOR16,
29234 IX86_BUILTIN_KXOR16,
29235 IX86_BUILTIN_KMOV16,
29237 /* AVX512VL. */
29238 IX86_BUILTIN_PMOVUSQD256_MEM,
29239 IX86_BUILTIN_PMOVUSQD128_MEM,
29240 IX86_BUILTIN_PMOVSQD256_MEM,
29241 IX86_BUILTIN_PMOVSQD128_MEM,
29242 IX86_BUILTIN_PMOVQD256_MEM,
29243 IX86_BUILTIN_PMOVQD128_MEM,
29244 IX86_BUILTIN_PMOVUSQW256_MEM,
29245 IX86_BUILTIN_PMOVUSQW128_MEM,
29246 IX86_BUILTIN_PMOVSQW256_MEM,
29247 IX86_BUILTIN_PMOVSQW128_MEM,
29248 IX86_BUILTIN_PMOVQW256_MEM,
29249 IX86_BUILTIN_PMOVQW128_MEM,
29250 IX86_BUILTIN_PMOVUSQB256_MEM,
29251 IX86_BUILTIN_PMOVUSQB128_MEM,
29252 IX86_BUILTIN_PMOVSQB256_MEM,
29253 IX86_BUILTIN_PMOVSQB128_MEM,
29254 IX86_BUILTIN_PMOVQB256_MEM,
29255 IX86_BUILTIN_PMOVQB128_MEM,
29256 IX86_BUILTIN_PMOVUSDW256_MEM,
29257 IX86_BUILTIN_PMOVUSDW128_MEM,
29258 IX86_BUILTIN_PMOVSDW256_MEM,
29259 IX86_BUILTIN_PMOVSDW128_MEM,
29260 IX86_BUILTIN_PMOVDW256_MEM,
29261 IX86_BUILTIN_PMOVDW128_MEM,
29262 IX86_BUILTIN_PMOVUSDB256_MEM,
29263 IX86_BUILTIN_PMOVUSDB128_MEM,
29264 IX86_BUILTIN_PMOVSDB256_MEM,
29265 IX86_BUILTIN_PMOVSDB128_MEM,
29266 IX86_BUILTIN_PMOVDB256_MEM,
29267 IX86_BUILTIN_PMOVDB128_MEM,
29268 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29269 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29270 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29271 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29272 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29273 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29274 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29275 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29276 IX86_BUILTIN_LOADAPD256_MASK,
29277 IX86_BUILTIN_LOADAPD128_MASK,
29278 IX86_BUILTIN_LOADAPS256_MASK,
29279 IX86_BUILTIN_LOADAPS128_MASK,
29280 IX86_BUILTIN_STOREAPD256_MASK,
29281 IX86_BUILTIN_STOREAPD128_MASK,
29282 IX86_BUILTIN_STOREAPS256_MASK,
29283 IX86_BUILTIN_STOREAPS128_MASK,
29284 IX86_BUILTIN_LOADUPD256_MASK,
29285 IX86_BUILTIN_LOADUPD128_MASK,
29286 IX86_BUILTIN_LOADUPS256_MASK,
29287 IX86_BUILTIN_LOADUPS128_MASK,
29288 IX86_BUILTIN_STOREUPD256_MASK,
29289 IX86_BUILTIN_STOREUPD128_MASK,
29290 IX86_BUILTIN_STOREUPS256_MASK,
29291 IX86_BUILTIN_STOREUPS128_MASK,
29292 IX86_BUILTIN_LOADDQUDI256_MASK,
29293 IX86_BUILTIN_LOADDQUDI128_MASK,
29294 IX86_BUILTIN_LOADDQUSI256_MASK,
29295 IX86_BUILTIN_LOADDQUSI128_MASK,
29296 IX86_BUILTIN_LOADDQUHI256_MASK,
29297 IX86_BUILTIN_LOADDQUHI128_MASK,
29298 IX86_BUILTIN_LOADDQUQI256_MASK,
29299 IX86_BUILTIN_LOADDQUQI128_MASK,
29300 IX86_BUILTIN_STOREDQUDI256_MASK,
29301 IX86_BUILTIN_STOREDQUDI128_MASK,
29302 IX86_BUILTIN_STOREDQUSI256_MASK,
29303 IX86_BUILTIN_STOREDQUSI128_MASK,
29304 IX86_BUILTIN_STOREDQUHI256_MASK,
29305 IX86_BUILTIN_STOREDQUHI128_MASK,
29306 IX86_BUILTIN_STOREDQUQI256_MASK,
29307 IX86_BUILTIN_STOREDQUQI128_MASK,
29308 IX86_BUILTIN_COMPRESSPDSTORE256,
29309 IX86_BUILTIN_COMPRESSPDSTORE128,
29310 IX86_BUILTIN_COMPRESSPSSTORE256,
29311 IX86_BUILTIN_COMPRESSPSSTORE128,
29312 IX86_BUILTIN_PCOMPRESSQSTORE256,
29313 IX86_BUILTIN_PCOMPRESSQSTORE128,
29314 IX86_BUILTIN_PCOMPRESSDSTORE256,
29315 IX86_BUILTIN_PCOMPRESSDSTORE128,
29316 IX86_BUILTIN_EXPANDPDLOAD256,
29317 IX86_BUILTIN_EXPANDPDLOAD128,
29318 IX86_BUILTIN_EXPANDPSLOAD256,
29319 IX86_BUILTIN_EXPANDPSLOAD128,
29320 IX86_BUILTIN_PEXPANDQLOAD256,
29321 IX86_BUILTIN_PEXPANDQLOAD128,
29322 IX86_BUILTIN_PEXPANDDLOAD256,
29323 IX86_BUILTIN_PEXPANDDLOAD128,
29324 IX86_BUILTIN_EXPANDPDLOAD256Z,
29325 IX86_BUILTIN_EXPANDPDLOAD128Z,
29326 IX86_BUILTIN_EXPANDPSLOAD256Z,
29327 IX86_BUILTIN_EXPANDPSLOAD128Z,
29328 IX86_BUILTIN_PEXPANDQLOAD256Z,
29329 IX86_BUILTIN_PEXPANDQLOAD128Z,
29330 IX86_BUILTIN_PEXPANDDLOAD256Z,
29331 IX86_BUILTIN_PEXPANDDLOAD128Z,
29332 IX86_BUILTIN_PALIGNR256_MASK,
29333 IX86_BUILTIN_PALIGNR128_MASK,
29334 IX86_BUILTIN_MOVDQA64_256_MASK,
29335 IX86_BUILTIN_MOVDQA64_128_MASK,
29336 IX86_BUILTIN_MOVDQA32_256_MASK,
29337 IX86_BUILTIN_MOVDQA32_128_MASK,
29338 IX86_BUILTIN_MOVAPD256_MASK,
29339 IX86_BUILTIN_MOVAPD128_MASK,
29340 IX86_BUILTIN_MOVAPS256_MASK,
29341 IX86_BUILTIN_MOVAPS128_MASK,
29342 IX86_BUILTIN_MOVDQUHI256_MASK,
29343 IX86_BUILTIN_MOVDQUHI128_MASK,
29344 IX86_BUILTIN_MOVDQUQI256_MASK,
29345 IX86_BUILTIN_MOVDQUQI128_MASK,
29346 IX86_BUILTIN_MINPS128_MASK,
29347 IX86_BUILTIN_MAXPS128_MASK,
29348 IX86_BUILTIN_MINPD128_MASK,
29349 IX86_BUILTIN_MAXPD128_MASK,
29350 IX86_BUILTIN_MAXPD256_MASK,
29351 IX86_BUILTIN_MAXPS256_MASK,
29352 IX86_BUILTIN_MINPD256_MASK,
29353 IX86_BUILTIN_MINPS256_MASK,
29354 IX86_BUILTIN_MULPS128_MASK,
29355 IX86_BUILTIN_DIVPS128_MASK,
29356 IX86_BUILTIN_MULPD128_MASK,
29357 IX86_BUILTIN_DIVPD128_MASK,
29358 IX86_BUILTIN_DIVPD256_MASK,
29359 IX86_BUILTIN_DIVPS256_MASK,
29360 IX86_BUILTIN_MULPD256_MASK,
29361 IX86_BUILTIN_MULPS256_MASK,
29362 IX86_BUILTIN_ADDPD128_MASK,
29363 IX86_BUILTIN_ADDPD256_MASK,
29364 IX86_BUILTIN_ADDPS128_MASK,
29365 IX86_BUILTIN_ADDPS256_MASK,
29366 IX86_BUILTIN_SUBPD128_MASK,
29367 IX86_BUILTIN_SUBPD256_MASK,
29368 IX86_BUILTIN_SUBPS128_MASK,
29369 IX86_BUILTIN_SUBPS256_MASK,
29370 IX86_BUILTIN_XORPD256_MASK,
29371 IX86_BUILTIN_XORPD128_MASK,
29372 IX86_BUILTIN_XORPS256_MASK,
29373 IX86_BUILTIN_XORPS128_MASK,
29374 IX86_BUILTIN_ORPD256_MASK,
29375 IX86_BUILTIN_ORPD128_MASK,
29376 IX86_BUILTIN_ORPS256_MASK,
29377 IX86_BUILTIN_ORPS128_MASK,
29378 IX86_BUILTIN_BROADCASTF32x2_256,
29379 IX86_BUILTIN_BROADCASTI32x2_256,
29380 IX86_BUILTIN_BROADCASTI32x2_128,
29381 IX86_BUILTIN_BROADCASTF64X2_256,
29382 IX86_BUILTIN_BROADCASTI64X2_256,
29383 IX86_BUILTIN_BROADCASTF32X4_256,
29384 IX86_BUILTIN_BROADCASTI32X4_256,
29385 IX86_BUILTIN_EXTRACTF32X4_256,
29386 IX86_BUILTIN_EXTRACTI32X4_256,
29387 IX86_BUILTIN_DBPSADBW256,
29388 IX86_BUILTIN_DBPSADBW128,
29389 IX86_BUILTIN_CVTTPD2QQ256,
29390 IX86_BUILTIN_CVTTPD2QQ128,
29391 IX86_BUILTIN_CVTTPD2UQQ256,
29392 IX86_BUILTIN_CVTTPD2UQQ128,
29393 IX86_BUILTIN_CVTPD2QQ256,
29394 IX86_BUILTIN_CVTPD2QQ128,
29395 IX86_BUILTIN_CVTPD2UQQ256,
29396 IX86_BUILTIN_CVTPD2UQQ128,
29397 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29398 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29399 IX86_BUILTIN_CVTTPS2QQ256,
29400 IX86_BUILTIN_CVTTPS2QQ128,
29401 IX86_BUILTIN_CVTTPS2UQQ256,
29402 IX86_BUILTIN_CVTTPS2UQQ128,
29403 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29404 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29405 IX86_BUILTIN_CVTTPS2UDQ256,
29406 IX86_BUILTIN_CVTTPS2UDQ128,
29407 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29408 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29409 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29410 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29411 IX86_BUILTIN_CVTPD2DQ256_MASK,
29412 IX86_BUILTIN_CVTPD2DQ128_MASK,
29413 IX86_BUILTIN_CVTDQ2PD256_MASK,
29414 IX86_BUILTIN_CVTDQ2PD128_MASK,
29415 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29416 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29417 IX86_BUILTIN_CVTDQ2PS256_MASK,
29418 IX86_BUILTIN_CVTDQ2PS128_MASK,
29419 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29420 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29421 IX86_BUILTIN_CVTPS2PD256_MASK,
29422 IX86_BUILTIN_CVTPS2PD128_MASK,
29423 IX86_BUILTIN_PBROADCASTB256_MASK,
29424 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29425 IX86_BUILTIN_PBROADCASTB128_MASK,
29426 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29427 IX86_BUILTIN_PBROADCASTW256_MASK,
29428 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29429 IX86_BUILTIN_PBROADCASTW128_MASK,
29430 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29431 IX86_BUILTIN_PBROADCASTD256_MASK,
29432 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29433 IX86_BUILTIN_PBROADCASTD128_MASK,
29434 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29435 IX86_BUILTIN_PBROADCASTQ256_MASK,
29436 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29437 IX86_BUILTIN_PBROADCASTQ128_MASK,
29438 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29439 IX86_BUILTIN_BROADCASTSS256,
29440 IX86_BUILTIN_BROADCASTSS128,
29441 IX86_BUILTIN_BROADCASTSD256,
29442 IX86_BUILTIN_EXTRACTF64X2_256,
29443 IX86_BUILTIN_EXTRACTI64X2_256,
29444 IX86_BUILTIN_INSERTF32X4_256,
29445 IX86_BUILTIN_INSERTI32X4_256,
29446 IX86_BUILTIN_PMOVSXBW256_MASK,
29447 IX86_BUILTIN_PMOVSXBW128_MASK,
29448 IX86_BUILTIN_PMOVSXBD256_MASK,
29449 IX86_BUILTIN_PMOVSXBD128_MASK,
29450 IX86_BUILTIN_PMOVSXBQ256_MASK,
29451 IX86_BUILTIN_PMOVSXBQ128_MASK,
29452 IX86_BUILTIN_PMOVSXWD256_MASK,
29453 IX86_BUILTIN_PMOVSXWD128_MASK,
29454 IX86_BUILTIN_PMOVSXWQ256_MASK,
29455 IX86_BUILTIN_PMOVSXWQ128_MASK,
29456 IX86_BUILTIN_PMOVSXDQ256_MASK,
29457 IX86_BUILTIN_PMOVSXDQ128_MASK,
29458 IX86_BUILTIN_PMOVZXBW256_MASK,
29459 IX86_BUILTIN_PMOVZXBW128_MASK,
29460 IX86_BUILTIN_PMOVZXBD256_MASK,
29461 IX86_BUILTIN_PMOVZXBD128_MASK,
29462 IX86_BUILTIN_PMOVZXBQ256_MASK,
29463 IX86_BUILTIN_PMOVZXBQ128_MASK,
29464 IX86_BUILTIN_PMOVZXWD256_MASK,
29465 IX86_BUILTIN_PMOVZXWD128_MASK,
29466 IX86_BUILTIN_PMOVZXWQ256_MASK,
29467 IX86_BUILTIN_PMOVZXWQ128_MASK,
29468 IX86_BUILTIN_PMOVZXDQ256_MASK,
29469 IX86_BUILTIN_PMOVZXDQ128_MASK,
29470 IX86_BUILTIN_REDUCEPD256_MASK,
29471 IX86_BUILTIN_REDUCEPD128_MASK,
29472 IX86_BUILTIN_REDUCEPS256_MASK,
29473 IX86_BUILTIN_REDUCEPS128_MASK,
29474 IX86_BUILTIN_REDUCESD_MASK,
29475 IX86_BUILTIN_REDUCESS_MASK,
29476 IX86_BUILTIN_VPERMVARHI256_MASK,
29477 IX86_BUILTIN_VPERMVARHI128_MASK,
29478 IX86_BUILTIN_VPERMT2VARHI256,
29479 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29480 IX86_BUILTIN_VPERMT2VARHI128,
29481 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29482 IX86_BUILTIN_VPERMI2VARHI256,
29483 IX86_BUILTIN_VPERMI2VARHI128,
29484 IX86_BUILTIN_RCP14PD256,
29485 IX86_BUILTIN_RCP14PD128,
29486 IX86_BUILTIN_RCP14PS256,
29487 IX86_BUILTIN_RCP14PS128,
29488 IX86_BUILTIN_RSQRT14PD256_MASK,
29489 IX86_BUILTIN_RSQRT14PD128_MASK,
29490 IX86_BUILTIN_RSQRT14PS256_MASK,
29491 IX86_BUILTIN_RSQRT14PS128_MASK,
29492 IX86_BUILTIN_SQRTPD256_MASK,
29493 IX86_BUILTIN_SQRTPD128_MASK,
29494 IX86_BUILTIN_SQRTPS256_MASK,
29495 IX86_BUILTIN_SQRTPS128_MASK,
29496 IX86_BUILTIN_PADDB128_MASK,
29497 IX86_BUILTIN_PADDW128_MASK,
29498 IX86_BUILTIN_PADDD128_MASK,
29499 IX86_BUILTIN_PADDQ128_MASK,
29500 IX86_BUILTIN_PSUBB128_MASK,
29501 IX86_BUILTIN_PSUBW128_MASK,
29502 IX86_BUILTIN_PSUBD128_MASK,
29503 IX86_BUILTIN_PSUBQ128_MASK,
29504 IX86_BUILTIN_PADDSB128_MASK,
29505 IX86_BUILTIN_PADDSW128_MASK,
29506 IX86_BUILTIN_PSUBSB128_MASK,
29507 IX86_BUILTIN_PSUBSW128_MASK,
29508 IX86_BUILTIN_PADDUSB128_MASK,
29509 IX86_BUILTIN_PADDUSW128_MASK,
29510 IX86_BUILTIN_PSUBUSB128_MASK,
29511 IX86_BUILTIN_PSUBUSW128_MASK,
29512 IX86_BUILTIN_PADDB256_MASK,
29513 IX86_BUILTIN_PADDW256_MASK,
29514 IX86_BUILTIN_PADDD256_MASK,
29515 IX86_BUILTIN_PADDQ256_MASK,
29516 IX86_BUILTIN_PADDSB256_MASK,
29517 IX86_BUILTIN_PADDSW256_MASK,
29518 IX86_BUILTIN_PADDUSB256_MASK,
29519 IX86_BUILTIN_PADDUSW256_MASK,
29520 IX86_BUILTIN_PSUBB256_MASK,
29521 IX86_BUILTIN_PSUBW256_MASK,
29522 IX86_BUILTIN_PSUBD256_MASK,
29523 IX86_BUILTIN_PSUBQ256_MASK,
29524 IX86_BUILTIN_PSUBSB256_MASK,
29525 IX86_BUILTIN_PSUBSW256_MASK,
29526 IX86_BUILTIN_PSUBUSB256_MASK,
29527 IX86_BUILTIN_PSUBUSW256_MASK,
29528 IX86_BUILTIN_SHUF_F64x2_256,
29529 IX86_BUILTIN_SHUF_I64x2_256,
29530 IX86_BUILTIN_SHUF_I32x4_256,
29531 IX86_BUILTIN_SHUF_F32x4_256,
29532 IX86_BUILTIN_PMOVWB128,
29533 IX86_BUILTIN_PMOVWB256,
29534 IX86_BUILTIN_PMOVSWB128,
29535 IX86_BUILTIN_PMOVSWB256,
29536 IX86_BUILTIN_PMOVUSWB128,
29537 IX86_BUILTIN_PMOVUSWB256,
29538 IX86_BUILTIN_PMOVDB128,
29539 IX86_BUILTIN_PMOVDB256,
29540 IX86_BUILTIN_PMOVSDB128,
29541 IX86_BUILTIN_PMOVSDB256,
29542 IX86_BUILTIN_PMOVUSDB128,
29543 IX86_BUILTIN_PMOVUSDB256,
29544 IX86_BUILTIN_PMOVDW128,
29545 IX86_BUILTIN_PMOVDW256,
29546 IX86_BUILTIN_PMOVSDW128,
29547 IX86_BUILTIN_PMOVSDW256,
29548 IX86_BUILTIN_PMOVUSDW128,
29549 IX86_BUILTIN_PMOVUSDW256,
29550 IX86_BUILTIN_PMOVQB128,
29551 IX86_BUILTIN_PMOVQB256,
29552 IX86_BUILTIN_PMOVSQB128,
29553 IX86_BUILTIN_PMOVSQB256,
29554 IX86_BUILTIN_PMOVUSQB128,
29555 IX86_BUILTIN_PMOVUSQB256,
29556 IX86_BUILTIN_PMOVQW128,
29557 IX86_BUILTIN_PMOVQW256,
29558 IX86_BUILTIN_PMOVSQW128,
29559 IX86_BUILTIN_PMOVSQW256,
29560 IX86_BUILTIN_PMOVUSQW128,
29561 IX86_BUILTIN_PMOVUSQW256,
29562 IX86_BUILTIN_PMOVQD128,
29563 IX86_BUILTIN_PMOVQD256,
29564 IX86_BUILTIN_PMOVSQD128,
29565 IX86_BUILTIN_PMOVSQD256,
29566 IX86_BUILTIN_PMOVUSQD128,
29567 IX86_BUILTIN_PMOVUSQD256,
29568 IX86_BUILTIN_RANGEPD256,
29569 IX86_BUILTIN_RANGEPD128,
29570 IX86_BUILTIN_RANGEPS256,
29571 IX86_BUILTIN_RANGEPS128,
29572 IX86_BUILTIN_GETEXPPS256,
29573 IX86_BUILTIN_GETEXPPD256,
29574 IX86_BUILTIN_GETEXPPS128,
29575 IX86_BUILTIN_GETEXPPD128,
29576 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29577 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29578 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29579 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29580 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29581 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29582 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29583 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29584 IX86_BUILTIN_PABSQ256,
29585 IX86_BUILTIN_PABSQ128,
29586 IX86_BUILTIN_PABSD256_MASK,
29587 IX86_BUILTIN_PABSD128_MASK,
29588 IX86_BUILTIN_PMULHRSW256_MASK,
29589 IX86_BUILTIN_PMULHRSW128_MASK,
29590 IX86_BUILTIN_PMULHUW128_MASK,
29591 IX86_BUILTIN_PMULHUW256_MASK,
29592 IX86_BUILTIN_PMULHW256_MASK,
29593 IX86_BUILTIN_PMULHW128_MASK,
29594 IX86_BUILTIN_PMULLW256_MASK,
29595 IX86_BUILTIN_PMULLW128_MASK,
29596 IX86_BUILTIN_PMULLQ256,
29597 IX86_BUILTIN_PMULLQ128,
29598 IX86_BUILTIN_ANDPD256_MASK,
29599 IX86_BUILTIN_ANDPD128_MASK,
29600 IX86_BUILTIN_ANDPS256_MASK,
29601 IX86_BUILTIN_ANDPS128_MASK,
29602 IX86_BUILTIN_ANDNPD256_MASK,
29603 IX86_BUILTIN_ANDNPD128_MASK,
29604 IX86_BUILTIN_ANDNPS256_MASK,
29605 IX86_BUILTIN_ANDNPS128_MASK,
29606 IX86_BUILTIN_PSLLWI128_MASK,
29607 IX86_BUILTIN_PSLLDI128_MASK,
29608 IX86_BUILTIN_PSLLQI128_MASK,
29609 IX86_BUILTIN_PSLLW128_MASK,
29610 IX86_BUILTIN_PSLLD128_MASK,
29611 IX86_BUILTIN_PSLLQ128_MASK,
29612 IX86_BUILTIN_PSLLWI256_MASK ,
29613 IX86_BUILTIN_PSLLW256_MASK,
29614 IX86_BUILTIN_PSLLDI256_MASK,
29615 IX86_BUILTIN_PSLLD256_MASK,
29616 IX86_BUILTIN_PSLLQI256_MASK,
29617 IX86_BUILTIN_PSLLQ256_MASK,
29618 IX86_BUILTIN_PSRADI128_MASK,
29619 IX86_BUILTIN_PSRAD128_MASK,
29620 IX86_BUILTIN_PSRADI256_MASK,
29621 IX86_BUILTIN_PSRAD256_MASK,
29622 IX86_BUILTIN_PSRAQI128_MASK,
29623 IX86_BUILTIN_PSRAQ128_MASK,
29624 IX86_BUILTIN_PSRAQI256_MASK,
29625 IX86_BUILTIN_PSRAQ256_MASK,
29626 IX86_BUILTIN_PANDD256,
29627 IX86_BUILTIN_PANDD128,
29628 IX86_BUILTIN_PSRLDI128_MASK,
29629 IX86_BUILTIN_PSRLD128_MASK,
29630 IX86_BUILTIN_PSRLDI256_MASK,
29631 IX86_BUILTIN_PSRLD256_MASK,
29632 IX86_BUILTIN_PSRLQI128_MASK,
29633 IX86_BUILTIN_PSRLQ128_MASK,
29634 IX86_BUILTIN_PSRLQI256_MASK,
29635 IX86_BUILTIN_PSRLQ256_MASK,
29636 IX86_BUILTIN_PANDQ256,
29637 IX86_BUILTIN_PANDQ128,
29638 IX86_BUILTIN_PANDND256,
29639 IX86_BUILTIN_PANDND128,
29640 IX86_BUILTIN_PANDNQ256,
29641 IX86_BUILTIN_PANDNQ128,
29642 IX86_BUILTIN_PORD256,
29643 IX86_BUILTIN_PORD128,
29644 IX86_BUILTIN_PORQ256,
29645 IX86_BUILTIN_PORQ128,
29646 IX86_BUILTIN_PXORD256,
29647 IX86_BUILTIN_PXORD128,
29648 IX86_BUILTIN_PXORQ256,
29649 IX86_BUILTIN_PXORQ128,
29650 IX86_BUILTIN_PACKSSWB256_MASK,
29651 IX86_BUILTIN_PACKSSWB128_MASK,
29652 IX86_BUILTIN_PACKUSWB256_MASK,
29653 IX86_BUILTIN_PACKUSWB128_MASK,
29654 IX86_BUILTIN_RNDSCALEPS256,
29655 IX86_BUILTIN_RNDSCALEPD256,
29656 IX86_BUILTIN_RNDSCALEPS128,
29657 IX86_BUILTIN_RNDSCALEPD128,
29658 IX86_BUILTIN_VTERNLOGQ256_MASK,
29659 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29660 IX86_BUILTIN_VTERNLOGD256_MASK,
29661 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29662 IX86_BUILTIN_VTERNLOGQ128_MASK,
29663 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29664 IX86_BUILTIN_VTERNLOGD128_MASK,
29665 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29666 IX86_BUILTIN_SCALEFPD256,
29667 IX86_BUILTIN_SCALEFPS256,
29668 IX86_BUILTIN_SCALEFPD128,
29669 IX86_BUILTIN_SCALEFPS128,
29670 IX86_BUILTIN_VFMADDPD256_MASK,
29671 IX86_BUILTIN_VFMADDPD256_MASK3,
29672 IX86_BUILTIN_VFMADDPD256_MASKZ,
29673 IX86_BUILTIN_VFMADDPD128_MASK,
29674 IX86_BUILTIN_VFMADDPD128_MASK3,
29675 IX86_BUILTIN_VFMADDPD128_MASKZ,
29676 IX86_BUILTIN_VFMADDPS256_MASK,
29677 IX86_BUILTIN_VFMADDPS256_MASK3,
29678 IX86_BUILTIN_VFMADDPS256_MASKZ,
29679 IX86_BUILTIN_VFMADDPS128_MASK,
29680 IX86_BUILTIN_VFMADDPS128_MASK3,
29681 IX86_BUILTIN_VFMADDPS128_MASKZ,
29682 IX86_BUILTIN_VFMSUBPD256_MASK3,
29683 IX86_BUILTIN_VFMSUBPD128_MASK3,
29684 IX86_BUILTIN_VFMSUBPS256_MASK3,
29685 IX86_BUILTIN_VFMSUBPS128_MASK3,
29686 IX86_BUILTIN_VFNMADDPD256_MASK,
29687 IX86_BUILTIN_VFNMADDPD128_MASK,
29688 IX86_BUILTIN_VFNMADDPS256_MASK,
29689 IX86_BUILTIN_VFNMADDPS128_MASK,
29690 IX86_BUILTIN_VFNMSUBPD256_MASK,
29691 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29692 IX86_BUILTIN_VFNMSUBPD128_MASK,
29693 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29694 IX86_BUILTIN_VFNMSUBPS256_MASK,
29695 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29696 IX86_BUILTIN_VFNMSUBPS128_MASK,
29697 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29698 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29699 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29700 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29701 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29702 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29703 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29704 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29705 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29706 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29707 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29708 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29709 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29710 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29711 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29712 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29713 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29714 IX86_BUILTIN_INSERTF64X2_256,
29715 IX86_BUILTIN_INSERTI64X2_256,
29716 IX86_BUILTIN_PSRAVV16HI,
29717 IX86_BUILTIN_PSRAVV8HI,
29718 IX86_BUILTIN_PMADDUBSW256_MASK,
29719 IX86_BUILTIN_PMADDUBSW128_MASK,
29720 IX86_BUILTIN_PMADDWD256_MASK,
29721 IX86_BUILTIN_PMADDWD128_MASK,
29722 IX86_BUILTIN_PSRLVV16HI,
29723 IX86_BUILTIN_PSRLVV8HI,
29724 IX86_BUILTIN_CVTPS2DQ256_MASK,
29725 IX86_BUILTIN_CVTPS2DQ128_MASK,
29726 IX86_BUILTIN_CVTPS2UDQ256,
29727 IX86_BUILTIN_CVTPS2UDQ128,
29728 IX86_BUILTIN_CVTPS2QQ256,
29729 IX86_BUILTIN_CVTPS2QQ128,
29730 IX86_BUILTIN_CVTPS2UQQ256,
29731 IX86_BUILTIN_CVTPS2UQQ128,
29732 IX86_BUILTIN_GETMANTPS256,
29733 IX86_BUILTIN_GETMANTPS128,
29734 IX86_BUILTIN_GETMANTPD256,
29735 IX86_BUILTIN_GETMANTPD128,
29736 IX86_BUILTIN_MOVDDUP256_MASK,
29737 IX86_BUILTIN_MOVDDUP128_MASK,
29738 IX86_BUILTIN_MOVSHDUP256_MASK,
29739 IX86_BUILTIN_MOVSHDUP128_MASK,
29740 IX86_BUILTIN_MOVSLDUP256_MASK,
29741 IX86_BUILTIN_MOVSLDUP128_MASK,
29742 IX86_BUILTIN_CVTQQ2PS256,
29743 IX86_BUILTIN_CVTQQ2PS128,
29744 IX86_BUILTIN_CVTUQQ2PS256,
29745 IX86_BUILTIN_CVTUQQ2PS128,
29746 IX86_BUILTIN_CVTQQ2PD256,
29747 IX86_BUILTIN_CVTQQ2PD128,
29748 IX86_BUILTIN_CVTUQQ2PD256,
29749 IX86_BUILTIN_CVTUQQ2PD128,
29750 IX86_BUILTIN_VPERMT2VARQ256,
29751 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29752 IX86_BUILTIN_VPERMT2VARD256,
29753 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29754 IX86_BUILTIN_VPERMI2VARQ256,
29755 IX86_BUILTIN_VPERMI2VARD256,
29756 IX86_BUILTIN_VPERMT2VARPD256,
29757 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29758 IX86_BUILTIN_VPERMT2VARPS256,
29759 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29760 IX86_BUILTIN_VPERMI2VARPD256,
29761 IX86_BUILTIN_VPERMI2VARPS256,
29762 IX86_BUILTIN_VPERMT2VARQ128,
29763 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29764 IX86_BUILTIN_VPERMT2VARD128,
29765 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29766 IX86_BUILTIN_VPERMI2VARQ128,
29767 IX86_BUILTIN_VPERMI2VARD128,
29768 IX86_BUILTIN_VPERMT2VARPD128,
29769 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29770 IX86_BUILTIN_VPERMT2VARPS128,
29771 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29772 IX86_BUILTIN_VPERMI2VARPD128,
29773 IX86_BUILTIN_VPERMI2VARPS128,
29774 IX86_BUILTIN_PSHUFB256_MASK,
29775 IX86_BUILTIN_PSHUFB128_MASK,
29776 IX86_BUILTIN_PSHUFHW256_MASK,
29777 IX86_BUILTIN_PSHUFHW128_MASK,
29778 IX86_BUILTIN_PSHUFLW256_MASK,
29779 IX86_BUILTIN_PSHUFLW128_MASK,
29780 IX86_BUILTIN_PSHUFD256_MASK,
29781 IX86_BUILTIN_PSHUFD128_MASK,
29782 IX86_BUILTIN_SHUFPD256_MASK,
29783 IX86_BUILTIN_SHUFPD128_MASK,
29784 IX86_BUILTIN_SHUFPS256_MASK,
29785 IX86_BUILTIN_SHUFPS128_MASK,
29786 IX86_BUILTIN_PROLVQ256,
29787 IX86_BUILTIN_PROLVQ128,
29788 IX86_BUILTIN_PROLQ256,
29789 IX86_BUILTIN_PROLQ128,
29790 IX86_BUILTIN_PRORVQ256,
29791 IX86_BUILTIN_PRORVQ128,
29792 IX86_BUILTIN_PRORQ256,
29793 IX86_BUILTIN_PRORQ128,
29794 IX86_BUILTIN_PSRAVQ128,
29795 IX86_BUILTIN_PSRAVQ256,
29796 IX86_BUILTIN_PSLLVV4DI_MASK,
29797 IX86_BUILTIN_PSLLVV2DI_MASK,
29798 IX86_BUILTIN_PSLLVV8SI_MASK,
29799 IX86_BUILTIN_PSLLVV4SI_MASK,
29800 IX86_BUILTIN_PSRAVV8SI_MASK,
29801 IX86_BUILTIN_PSRAVV4SI_MASK,
29802 IX86_BUILTIN_PSRLVV4DI_MASK,
29803 IX86_BUILTIN_PSRLVV2DI_MASK,
29804 IX86_BUILTIN_PSRLVV8SI_MASK,
29805 IX86_BUILTIN_PSRLVV4SI_MASK,
29806 IX86_BUILTIN_PSRAWI256_MASK,
29807 IX86_BUILTIN_PSRAW256_MASK,
29808 IX86_BUILTIN_PSRAWI128_MASK,
29809 IX86_BUILTIN_PSRAW128_MASK,
29810 IX86_BUILTIN_PSRLWI256_MASK,
29811 IX86_BUILTIN_PSRLW256_MASK,
29812 IX86_BUILTIN_PSRLWI128_MASK,
29813 IX86_BUILTIN_PSRLW128_MASK,
29814 IX86_BUILTIN_PRORVD256,
29815 IX86_BUILTIN_PROLVD256,
29816 IX86_BUILTIN_PRORD256,
29817 IX86_BUILTIN_PROLD256,
29818 IX86_BUILTIN_PRORVD128,
29819 IX86_BUILTIN_PROLVD128,
29820 IX86_BUILTIN_PRORD128,
29821 IX86_BUILTIN_PROLD128,
29822 IX86_BUILTIN_FPCLASSPD256,
29823 IX86_BUILTIN_FPCLASSPD128,
29824 IX86_BUILTIN_FPCLASSSD,
29825 IX86_BUILTIN_FPCLASSPS256,
29826 IX86_BUILTIN_FPCLASSPS128,
29827 IX86_BUILTIN_FPCLASSSS,
29828 IX86_BUILTIN_CVTB2MASK128,
29829 IX86_BUILTIN_CVTB2MASK256,
29830 IX86_BUILTIN_CVTW2MASK128,
29831 IX86_BUILTIN_CVTW2MASK256,
29832 IX86_BUILTIN_CVTD2MASK128,
29833 IX86_BUILTIN_CVTD2MASK256,
29834 IX86_BUILTIN_CVTQ2MASK128,
29835 IX86_BUILTIN_CVTQ2MASK256,
29836 IX86_BUILTIN_CVTMASK2B128,
29837 IX86_BUILTIN_CVTMASK2B256,
29838 IX86_BUILTIN_CVTMASK2W128,
29839 IX86_BUILTIN_CVTMASK2W256,
29840 IX86_BUILTIN_CVTMASK2D128,
29841 IX86_BUILTIN_CVTMASK2D256,
29842 IX86_BUILTIN_CVTMASK2Q128,
29843 IX86_BUILTIN_CVTMASK2Q256,
29844 IX86_BUILTIN_PCMPEQB128_MASK,
29845 IX86_BUILTIN_PCMPEQB256_MASK,
29846 IX86_BUILTIN_PCMPEQW128_MASK,
29847 IX86_BUILTIN_PCMPEQW256_MASK,
29848 IX86_BUILTIN_PCMPEQD128_MASK,
29849 IX86_BUILTIN_PCMPEQD256_MASK,
29850 IX86_BUILTIN_PCMPEQQ128_MASK,
29851 IX86_BUILTIN_PCMPEQQ256_MASK,
29852 IX86_BUILTIN_PCMPGTB128_MASK,
29853 IX86_BUILTIN_PCMPGTB256_MASK,
29854 IX86_BUILTIN_PCMPGTW128_MASK,
29855 IX86_BUILTIN_PCMPGTW256_MASK,
29856 IX86_BUILTIN_PCMPGTD128_MASK,
29857 IX86_BUILTIN_PCMPGTD256_MASK,
29858 IX86_BUILTIN_PCMPGTQ128_MASK,
29859 IX86_BUILTIN_PCMPGTQ256_MASK,
29860 IX86_BUILTIN_PTESTMB128,
29861 IX86_BUILTIN_PTESTMB256,
29862 IX86_BUILTIN_PTESTMW128,
29863 IX86_BUILTIN_PTESTMW256,
29864 IX86_BUILTIN_PTESTMD128,
29865 IX86_BUILTIN_PTESTMD256,
29866 IX86_BUILTIN_PTESTMQ128,
29867 IX86_BUILTIN_PTESTMQ256,
29868 IX86_BUILTIN_PTESTNMB128,
29869 IX86_BUILTIN_PTESTNMB256,
29870 IX86_BUILTIN_PTESTNMW128,
29871 IX86_BUILTIN_PTESTNMW256,
29872 IX86_BUILTIN_PTESTNMD128,
29873 IX86_BUILTIN_PTESTNMD256,
29874 IX86_BUILTIN_PTESTNMQ128,
29875 IX86_BUILTIN_PTESTNMQ256,
29876 IX86_BUILTIN_PBROADCASTMB128,
29877 IX86_BUILTIN_PBROADCASTMB256,
29878 IX86_BUILTIN_PBROADCASTMW128,
29879 IX86_BUILTIN_PBROADCASTMW256,
29880 IX86_BUILTIN_COMPRESSPD256,
29881 IX86_BUILTIN_COMPRESSPD128,
29882 IX86_BUILTIN_COMPRESSPS256,
29883 IX86_BUILTIN_COMPRESSPS128,
29884 IX86_BUILTIN_PCOMPRESSQ256,
29885 IX86_BUILTIN_PCOMPRESSQ128,
29886 IX86_BUILTIN_PCOMPRESSD256,
29887 IX86_BUILTIN_PCOMPRESSD128,
29888 IX86_BUILTIN_EXPANDPD256,
29889 IX86_BUILTIN_EXPANDPD128,
29890 IX86_BUILTIN_EXPANDPS256,
29891 IX86_BUILTIN_EXPANDPS128,
29892 IX86_BUILTIN_PEXPANDQ256,
29893 IX86_BUILTIN_PEXPANDQ128,
29894 IX86_BUILTIN_PEXPANDD256,
29895 IX86_BUILTIN_PEXPANDD128,
29896 IX86_BUILTIN_EXPANDPD256Z,
29897 IX86_BUILTIN_EXPANDPD128Z,
29898 IX86_BUILTIN_EXPANDPS256Z,
29899 IX86_BUILTIN_EXPANDPS128Z,
29900 IX86_BUILTIN_PEXPANDQ256Z,
29901 IX86_BUILTIN_PEXPANDQ128Z,
29902 IX86_BUILTIN_PEXPANDD256Z,
29903 IX86_BUILTIN_PEXPANDD128Z,
29904 IX86_BUILTIN_PMAXSD256_MASK,
29905 IX86_BUILTIN_PMINSD256_MASK,
29906 IX86_BUILTIN_PMAXUD256_MASK,
29907 IX86_BUILTIN_PMINUD256_MASK,
29908 IX86_BUILTIN_PMAXSD128_MASK,
29909 IX86_BUILTIN_PMINSD128_MASK,
29910 IX86_BUILTIN_PMAXUD128_MASK,
29911 IX86_BUILTIN_PMINUD128_MASK,
29912 IX86_BUILTIN_PMAXSQ256_MASK,
29913 IX86_BUILTIN_PMINSQ256_MASK,
29914 IX86_BUILTIN_PMAXUQ256_MASK,
29915 IX86_BUILTIN_PMINUQ256_MASK,
29916 IX86_BUILTIN_PMAXSQ128_MASK,
29917 IX86_BUILTIN_PMINSQ128_MASK,
29918 IX86_BUILTIN_PMAXUQ128_MASK,
29919 IX86_BUILTIN_PMINUQ128_MASK,
29920 IX86_BUILTIN_PMINSB256_MASK,
29921 IX86_BUILTIN_PMINUB256_MASK,
29922 IX86_BUILTIN_PMAXSB256_MASK,
29923 IX86_BUILTIN_PMAXUB256_MASK,
29924 IX86_BUILTIN_PMINSB128_MASK,
29925 IX86_BUILTIN_PMINUB128_MASK,
29926 IX86_BUILTIN_PMAXSB128_MASK,
29927 IX86_BUILTIN_PMAXUB128_MASK,
29928 IX86_BUILTIN_PMINSW256_MASK,
29929 IX86_BUILTIN_PMINUW256_MASK,
29930 IX86_BUILTIN_PMAXSW256_MASK,
29931 IX86_BUILTIN_PMAXUW256_MASK,
29932 IX86_BUILTIN_PMINSW128_MASK,
29933 IX86_BUILTIN_PMINUW128_MASK,
29934 IX86_BUILTIN_PMAXSW128_MASK,
29935 IX86_BUILTIN_PMAXUW128_MASK,
29936 IX86_BUILTIN_VPCONFLICTQ256,
29937 IX86_BUILTIN_VPCONFLICTD256,
29938 IX86_BUILTIN_VPCLZCNTQ256,
29939 IX86_BUILTIN_VPCLZCNTD256,
29940 IX86_BUILTIN_UNPCKHPD256_MASK,
29941 IX86_BUILTIN_UNPCKHPD128_MASK,
29942 IX86_BUILTIN_UNPCKHPS256_MASK,
29943 IX86_BUILTIN_UNPCKHPS128_MASK,
29944 IX86_BUILTIN_UNPCKLPD256_MASK,
29945 IX86_BUILTIN_UNPCKLPD128_MASK,
29946 IX86_BUILTIN_UNPCKLPS256_MASK,
29947 IX86_BUILTIN_VPCONFLICTQ128,
29948 IX86_BUILTIN_VPCONFLICTD128,
29949 IX86_BUILTIN_VPCLZCNTQ128,
29950 IX86_BUILTIN_VPCLZCNTD128,
29951 IX86_BUILTIN_UNPCKLPS128_MASK,
29952 IX86_BUILTIN_ALIGND256,
29953 IX86_BUILTIN_ALIGNQ256,
29954 IX86_BUILTIN_ALIGND128,
29955 IX86_BUILTIN_ALIGNQ128,
29956 IX86_BUILTIN_CVTPS2PH256_MASK,
29957 IX86_BUILTIN_CVTPS2PH_MASK,
29958 IX86_BUILTIN_CVTPH2PS_MASK,
29959 IX86_BUILTIN_CVTPH2PS256_MASK,
29960 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29961 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29962 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29963 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29964 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29965 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29966 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29967 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29968 IX86_BUILTIN_PUNPCKHBW128_MASK,
29969 IX86_BUILTIN_PUNPCKHBW256_MASK,
29970 IX86_BUILTIN_PUNPCKHWD128_MASK,
29971 IX86_BUILTIN_PUNPCKHWD256_MASK,
29972 IX86_BUILTIN_PUNPCKLBW128_MASK,
29973 IX86_BUILTIN_PUNPCKLBW256_MASK,
29974 IX86_BUILTIN_PUNPCKLWD128_MASK,
29975 IX86_BUILTIN_PUNPCKLWD256_MASK,
29976 IX86_BUILTIN_PSLLVV16HI,
29977 IX86_BUILTIN_PSLLVV8HI,
29978 IX86_BUILTIN_PACKSSDW256_MASK,
29979 IX86_BUILTIN_PACKSSDW128_MASK,
29980 IX86_BUILTIN_PACKUSDW256_MASK,
29981 IX86_BUILTIN_PACKUSDW128_MASK,
29982 IX86_BUILTIN_PAVGB256_MASK,
29983 IX86_BUILTIN_PAVGW256_MASK,
29984 IX86_BUILTIN_PAVGB128_MASK,
29985 IX86_BUILTIN_PAVGW128_MASK,
29986 IX86_BUILTIN_VPERMVARSF256_MASK,
29987 IX86_BUILTIN_VPERMVARDF256_MASK,
29988 IX86_BUILTIN_VPERMDF256_MASK,
29989 IX86_BUILTIN_PABSB256_MASK,
29990 IX86_BUILTIN_PABSB128_MASK,
29991 IX86_BUILTIN_PABSW256_MASK,
29992 IX86_BUILTIN_PABSW128_MASK,
29993 IX86_BUILTIN_VPERMILVARPD_MASK,
29994 IX86_BUILTIN_VPERMILVARPS_MASK,
29995 IX86_BUILTIN_VPERMILVARPD256_MASK,
29996 IX86_BUILTIN_VPERMILVARPS256_MASK,
29997 IX86_BUILTIN_VPERMILPD_MASK,
29998 IX86_BUILTIN_VPERMILPS_MASK,
29999 IX86_BUILTIN_VPERMILPD256_MASK,
30000 IX86_BUILTIN_VPERMILPS256_MASK,
30001 IX86_BUILTIN_BLENDMQ256,
30002 IX86_BUILTIN_BLENDMD256,
30003 IX86_BUILTIN_BLENDMPD256,
30004 IX86_BUILTIN_BLENDMPS256,
30005 IX86_BUILTIN_BLENDMQ128,
30006 IX86_BUILTIN_BLENDMD128,
30007 IX86_BUILTIN_BLENDMPD128,
30008 IX86_BUILTIN_BLENDMPS128,
30009 IX86_BUILTIN_BLENDMW256,
30010 IX86_BUILTIN_BLENDMB256,
30011 IX86_BUILTIN_BLENDMW128,
30012 IX86_BUILTIN_BLENDMB128,
30013 IX86_BUILTIN_PMULLD256_MASK,
30014 IX86_BUILTIN_PMULLD128_MASK,
30015 IX86_BUILTIN_PMULUDQ256_MASK,
30016 IX86_BUILTIN_PMULDQ256_MASK,
30017 IX86_BUILTIN_PMULDQ128_MASK,
30018 IX86_BUILTIN_PMULUDQ128_MASK,
30019 IX86_BUILTIN_CVTPD2PS256_MASK,
30020 IX86_BUILTIN_CVTPD2PS_MASK,
30021 IX86_BUILTIN_VPERMVARSI256_MASK,
30022 IX86_BUILTIN_VPERMVARDI256_MASK,
30023 IX86_BUILTIN_VPERMDI256_MASK,
30024 IX86_BUILTIN_CMPQ256,
30025 IX86_BUILTIN_CMPD256,
30026 IX86_BUILTIN_UCMPQ256,
30027 IX86_BUILTIN_UCMPD256,
30028 IX86_BUILTIN_CMPB256,
30029 IX86_BUILTIN_CMPW256,
30030 IX86_BUILTIN_UCMPB256,
30031 IX86_BUILTIN_UCMPW256,
30032 IX86_BUILTIN_CMPPD256_MASK,
30033 IX86_BUILTIN_CMPPS256_MASK,
30034 IX86_BUILTIN_CMPQ128,
30035 IX86_BUILTIN_CMPD128,
30036 IX86_BUILTIN_UCMPQ128,
30037 IX86_BUILTIN_UCMPD128,
30038 IX86_BUILTIN_CMPB128,
30039 IX86_BUILTIN_CMPW128,
30040 IX86_BUILTIN_UCMPB128,
30041 IX86_BUILTIN_UCMPW128,
30042 IX86_BUILTIN_CMPPD128_MASK,
30043 IX86_BUILTIN_CMPPS128_MASK,
30045 IX86_BUILTIN_GATHER3SIV8SF,
30046 IX86_BUILTIN_GATHER3SIV4SF,
30047 IX86_BUILTIN_GATHER3SIV4DF,
30048 IX86_BUILTIN_GATHER3SIV2DF,
30049 IX86_BUILTIN_GATHER3DIV8SF,
30050 IX86_BUILTIN_GATHER3DIV4SF,
30051 IX86_BUILTIN_GATHER3DIV4DF,
30052 IX86_BUILTIN_GATHER3DIV2DF,
30053 IX86_BUILTIN_GATHER3SIV8SI,
30054 IX86_BUILTIN_GATHER3SIV4SI,
30055 IX86_BUILTIN_GATHER3SIV4DI,
30056 IX86_BUILTIN_GATHER3SIV2DI,
30057 IX86_BUILTIN_GATHER3DIV8SI,
30058 IX86_BUILTIN_GATHER3DIV4SI,
30059 IX86_BUILTIN_GATHER3DIV4DI,
30060 IX86_BUILTIN_GATHER3DIV2DI,
30061 IX86_BUILTIN_SCATTERSIV8SF,
30062 IX86_BUILTIN_SCATTERSIV4SF,
30063 IX86_BUILTIN_SCATTERSIV4DF,
30064 IX86_BUILTIN_SCATTERSIV2DF,
30065 IX86_BUILTIN_SCATTERDIV8SF,
30066 IX86_BUILTIN_SCATTERDIV4SF,
30067 IX86_BUILTIN_SCATTERDIV4DF,
30068 IX86_BUILTIN_SCATTERDIV2DF,
30069 IX86_BUILTIN_SCATTERSIV8SI,
30070 IX86_BUILTIN_SCATTERSIV4SI,
30071 IX86_BUILTIN_SCATTERSIV4DI,
30072 IX86_BUILTIN_SCATTERSIV2DI,
30073 IX86_BUILTIN_SCATTERDIV8SI,
30074 IX86_BUILTIN_SCATTERDIV4SI,
30075 IX86_BUILTIN_SCATTERDIV4DI,
30076 IX86_BUILTIN_SCATTERDIV2DI,
30078 /* AVX512DQ. */
30079 IX86_BUILTIN_RANGESD128,
30080 IX86_BUILTIN_RANGESS128,
30081 IX86_BUILTIN_KUNPCKWD,
30082 IX86_BUILTIN_KUNPCKDQ,
30083 IX86_BUILTIN_BROADCASTF32x2_512,
30084 IX86_BUILTIN_BROADCASTI32x2_512,
30085 IX86_BUILTIN_BROADCASTF64X2_512,
30086 IX86_BUILTIN_BROADCASTI64X2_512,
30087 IX86_BUILTIN_BROADCASTF32X8_512,
30088 IX86_BUILTIN_BROADCASTI32X8_512,
30089 IX86_BUILTIN_EXTRACTF64X2_512,
30090 IX86_BUILTIN_EXTRACTF32X8,
30091 IX86_BUILTIN_EXTRACTI64X2_512,
30092 IX86_BUILTIN_EXTRACTI32X8,
30093 IX86_BUILTIN_REDUCEPD512_MASK,
30094 IX86_BUILTIN_REDUCEPS512_MASK,
30095 IX86_BUILTIN_PMULLQ512,
30096 IX86_BUILTIN_XORPD512,
30097 IX86_BUILTIN_XORPS512,
30098 IX86_BUILTIN_ORPD512,
30099 IX86_BUILTIN_ORPS512,
30100 IX86_BUILTIN_ANDPD512,
30101 IX86_BUILTIN_ANDPS512,
30102 IX86_BUILTIN_ANDNPD512,
30103 IX86_BUILTIN_ANDNPS512,
30104 IX86_BUILTIN_INSERTF32X8,
30105 IX86_BUILTIN_INSERTI32X8,
30106 IX86_BUILTIN_INSERTF64X2_512,
30107 IX86_BUILTIN_INSERTI64X2_512,
30108 IX86_BUILTIN_FPCLASSPD512,
30109 IX86_BUILTIN_FPCLASSPS512,
30110 IX86_BUILTIN_CVTD2MASK512,
30111 IX86_BUILTIN_CVTQ2MASK512,
30112 IX86_BUILTIN_CVTMASK2D512,
30113 IX86_BUILTIN_CVTMASK2Q512,
30114 IX86_BUILTIN_CVTPD2QQ512,
30115 IX86_BUILTIN_CVTPS2QQ512,
30116 IX86_BUILTIN_CVTPD2UQQ512,
30117 IX86_BUILTIN_CVTPS2UQQ512,
30118 IX86_BUILTIN_CVTQQ2PS512,
30119 IX86_BUILTIN_CVTUQQ2PS512,
30120 IX86_BUILTIN_CVTQQ2PD512,
30121 IX86_BUILTIN_CVTUQQ2PD512,
30122 IX86_BUILTIN_CVTTPS2QQ512,
30123 IX86_BUILTIN_CVTTPS2UQQ512,
30124 IX86_BUILTIN_CVTTPD2QQ512,
30125 IX86_BUILTIN_CVTTPD2UQQ512,
30126 IX86_BUILTIN_RANGEPS512,
30127 IX86_BUILTIN_RANGEPD512,
30129 /* AVX512BW. */
30130 IX86_BUILTIN_PACKUSDW512,
30131 IX86_BUILTIN_PACKSSDW512,
30132 IX86_BUILTIN_LOADDQUHI512_MASK,
30133 IX86_BUILTIN_LOADDQUQI512_MASK,
30134 IX86_BUILTIN_PSLLDQ512,
30135 IX86_BUILTIN_PSRLDQ512,
30136 IX86_BUILTIN_STOREDQUHI512_MASK,
30137 IX86_BUILTIN_STOREDQUQI512_MASK,
30138 IX86_BUILTIN_PALIGNR512,
30139 IX86_BUILTIN_PALIGNR512_MASK,
30140 IX86_BUILTIN_MOVDQUHI512_MASK,
30141 IX86_BUILTIN_MOVDQUQI512_MASK,
30142 IX86_BUILTIN_PSADBW512,
30143 IX86_BUILTIN_DBPSADBW512,
30144 IX86_BUILTIN_PBROADCASTB512,
30145 IX86_BUILTIN_PBROADCASTB512_GPR,
30146 IX86_BUILTIN_PBROADCASTW512,
30147 IX86_BUILTIN_PBROADCASTW512_GPR,
30148 IX86_BUILTIN_PMOVSXBW512_MASK,
30149 IX86_BUILTIN_PMOVZXBW512_MASK,
30150 IX86_BUILTIN_VPERMVARHI512_MASK,
30151 IX86_BUILTIN_VPERMT2VARHI512,
30152 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30153 IX86_BUILTIN_VPERMI2VARHI512,
30154 IX86_BUILTIN_PAVGB512,
30155 IX86_BUILTIN_PAVGW512,
30156 IX86_BUILTIN_PADDB512,
30157 IX86_BUILTIN_PSUBB512,
30158 IX86_BUILTIN_PSUBSB512,
30159 IX86_BUILTIN_PADDSB512,
30160 IX86_BUILTIN_PSUBUSB512,
30161 IX86_BUILTIN_PADDUSB512,
30162 IX86_BUILTIN_PSUBW512,
30163 IX86_BUILTIN_PADDW512,
30164 IX86_BUILTIN_PSUBSW512,
30165 IX86_BUILTIN_PADDSW512,
30166 IX86_BUILTIN_PSUBUSW512,
30167 IX86_BUILTIN_PADDUSW512,
30168 IX86_BUILTIN_PMAXUW512,
30169 IX86_BUILTIN_PMAXSW512,
30170 IX86_BUILTIN_PMINUW512,
30171 IX86_BUILTIN_PMINSW512,
30172 IX86_BUILTIN_PMAXUB512,
30173 IX86_BUILTIN_PMAXSB512,
30174 IX86_BUILTIN_PMINUB512,
30175 IX86_BUILTIN_PMINSB512,
30176 IX86_BUILTIN_PMOVWB512,
30177 IX86_BUILTIN_PMOVSWB512,
30178 IX86_BUILTIN_PMOVUSWB512,
30179 IX86_BUILTIN_PMULHRSW512_MASK,
30180 IX86_BUILTIN_PMULHUW512_MASK,
30181 IX86_BUILTIN_PMULHW512_MASK,
30182 IX86_BUILTIN_PMULLW512_MASK,
30183 IX86_BUILTIN_PSLLWI512_MASK,
30184 IX86_BUILTIN_PSLLW512_MASK,
30185 IX86_BUILTIN_PACKSSWB512,
30186 IX86_BUILTIN_PACKUSWB512,
30187 IX86_BUILTIN_PSRAVV32HI,
30188 IX86_BUILTIN_PMADDUBSW512_MASK,
30189 IX86_BUILTIN_PMADDWD512_MASK,
30190 IX86_BUILTIN_PSRLVV32HI,
30191 IX86_BUILTIN_PUNPCKHBW512,
30192 IX86_BUILTIN_PUNPCKHWD512,
30193 IX86_BUILTIN_PUNPCKLBW512,
30194 IX86_BUILTIN_PUNPCKLWD512,
30195 IX86_BUILTIN_PSHUFB512,
30196 IX86_BUILTIN_PSHUFHW512,
30197 IX86_BUILTIN_PSHUFLW512,
30198 IX86_BUILTIN_PSRAWI512,
30199 IX86_BUILTIN_PSRAW512,
30200 IX86_BUILTIN_PSRLWI512,
30201 IX86_BUILTIN_PSRLW512,
30202 IX86_BUILTIN_CVTB2MASK512,
30203 IX86_BUILTIN_CVTW2MASK512,
30204 IX86_BUILTIN_CVTMASK2B512,
30205 IX86_BUILTIN_CVTMASK2W512,
30206 IX86_BUILTIN_PCMPEQB512_MASK,
30207 IX86_BUILTIN_PCMPEQW512_MASK,
30208 IX86_BUILTIN_PCMPGTB512_MASK,
30209 IX86_BUILTIN_PCMPGTW512_MASK,
30210 IX86_BUILTIN_PTESTMB512,
30211 IX86_BUILTIN_PTESTMW512,
30212 IX86_BUILTIN_PTESTNMB512,
30213 IX86_BUILTIN_PTESTNMW512,
30214 IX86_BUILTIN_PSLLVV32HI,
30215 IX86_BUILTIN_PABSB512,
30216 IX86_BUILTIN_PABSW512,
30217 IX86_BUILTIN_BLENDMW512,
30218 IX86_BUILTIN_BLENDMB512,
30219 IX86_BUILTIN_CMPB512,
30220 IX86_BUILTIN_CMPW512,
30221 IX86_BUILTIN_UCMPB512,
30222 IX86_BUILTIN_UCMPW512,
30224 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30225 where all operands are 32-byte or 64-byte wide respectively. */
30226 IX86_BUILTIN_GATHERALTSIV4DF,
30227 IX86_BUILTIN_GATHERALTDIV8SF,
30228 IX86_BUILTIN_GATHERALTSIV4DI,
30229 IX86_BUILTIN_GATHERALTDIV8SI,
30230 IX86_BUILTIN_GATHER3ALTDIV16SF,
30231 IX86_BUILTIN_GATHER3ALTDIV16SI,
30232 IX86_BUILTIN_GATHER3ALTSIV4DF,
30233 IX86_BUILTIN_GATHER3ALTDIV8SF,
30234 IX86_BUILTIN_GATHER3ALTSIV4DI,
30235 IX86_BUILTIN_GATHER3ALTDIV8SI,
30236 IX86_BUILTIN_GATHER3ALTSIV8DF,
30237 IX86_BUILTIN_GATHER3ALTSIV8DI,
30238 IX86_BUILTIN_GATHER3DIV16SF,
30239 IX86_BUILTIN_GATHER3DIV16SI,
30240 IX86_BUILTIN_GATHER3DIV8DF,
30241 IX86_BUILTIN_GATHER3DIV8DI,
30242 IX86_BUILTIN_GATHER3SIV16SF,
30243 IX86_BUILTIN_GATHER3SIV16SI,
30244 IX86_BUILTIN_GATHER3SIV8DF,
30245 IX86_BUILTIN_GATHER3SIV8DI,
30246 IX86_BUILTIN_SCATTERDIV16SF,
30247 IX86_BUILTIN_SCATTERDIV16SI,
30248 IX86_BUILTIN_SCATTERDIV8DF,
30249 IX86_BUILTIN_SCATTERDIV8DI,
30250 IX86_BUILTIN_SCATTERSIV16SF,
30251 IX86_BUILTIN_SCATTERSIV16SI,
30252 IX86_BUILTIN_SCATTERSIV8DF,
30253 IX86_BUILTIN_SCATTERSIV8DI,
30255 /* AVX512PF */
30256 IX86_BUILTIN_GATHERPFQPD,
30257 IX86_BUILTIN_GATHERPFDPS,
30258 IX86_BUILTIN_GATHERPFDPD,
30259 IX86_BUILTIN_GATHERPFQPS,
30260 IX86_BUILTIN_SCATTERPFDPD,
30261 IX86_BUILTIN_SCATTERPFDPS,
30262 IX86_BUILTIN_SCATTERPFQPD,
30263 IX86_BUILTIN_SCATTERPFQPS,
30265 /* AVX-512ER */
30266 IX86_BUILTIN_EXP2PD_MASK,
30267 IX86_BUILTIN_EXP2PS_MASK,
30268 IX86_BUILTIN_EXP2PS,
30269 IX86_BUILTIN_RCP28PD,
30270 IX86_BUILTIN_RCP28PS,
30271 IX86_BUILTIN_RCP28SD,
30272 IX86_BUILTIN_RCP28SS,
30273 IX86_BUILTIN_RSQRT28PD,
30274 IX86_BUILTIN_RSQRT28PS,
30275 IX86_BUILTIN_RSQRT28SD,
30276 IX86_BUILTIN_RSQRT28SS,
30278 /* AVX-512IFMA */
30279 IX86_BUILTIN_VPMADD52LUQ512,
30280 IX86_BUILTIN_VPMADD52HUQ512,
30281 IX86_BUILTIN_VPMADD52LUQ256,
30282 IX86_BUILTIN_VPMADD52HUQ256,
30283 IX86_BUILTIN_VPMADD52LUQ128,
30284 IX86_BUILTIN_VPMADD52HUQ128,
30285 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30286 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30287 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30288 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30289 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30290 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30292 /* AVX-512VBMI */
30293 IX86_BUILTIN_VPMULTISHIFTQB512,
30294 IX86_BUILTIN_VPMULTISHIFTQB256,
30295 IX86_BUILTIN_VPMULTISHIFTQB128,
30296 IX86_BUILTIN_VPERMVARQI512_MASK,
30297 IX86_BUILTIN_VPERMT2VARQI512,
30298 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30299 IX86_BUILTIN_VPERMI2VARQI512,
30300 IX86_BUILTIN_VPERMVARQI256_MASK,
30301 IX86_BUILTIN_VPERMVARQI128_MASK,
30302 IX86_BUILTIN_VPERMT2VARQI256,
30303 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30304 IX86_BUILTIN_VPERMT2VARQI128,
30305 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30306 IX86_BUILTIN_VPERMI2VARQI256,
30307 IX86_BUILTIN_VPERMI2VARQI128,
30309 /* SHA builtins. */
30310 IX86_BUILTIN_SHA1MSG1,
30311 IX86_BUILTIN_SHA1MSG2,
30312 IX86_BUILTIN_SHA1NEXTE,
30313 IX86_BUILTIN_SHA1RNDS4,
30314 IX86_BUILTIN_SHA256MSG1,
30315 IX86_BUILTIN_SHA256MSG2,
30316 IX86_BUILTIN_SHA256RNDS2,
30318 /* CLWB instructions. */
30319 IX86_BUILTIN_CLWB,
30321 /* PCOMMIT instructions. */
30322 IX86_BUILTIN_PCOMMIT,
30324 /* CLFLUSHOPT instructions. */
30325 IX86_BUILTIN_CLFLUSHOPT,
30327 /* TFmode support builtins. */
30328 IX86_BUILTIN_INFQ,
30329 IX86_BUILTIN_HUGE_VALQ,
30330 IX86_BUILTIN_FABSQ,
30331 IX86_BUILTIN_COPYSIGNQ,
30333 /* Vectorizer support builtins. */
30334 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30335 IX86_BUILTIN_CPYSGNPS,
30336 IX86_BUILTIN_CPYSGNPD,
30337 IX86_BUILTIN_CPYSGNPS256,
30338 IX86_BUILTIN_CPYSGNPS512,
30339 IX86_BUILTIN_CPYSGNPD256,
30340 IX86_BUILTIN_CPYSGNPD512,
30341 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30342 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30345 /* FMA4 instructions. */
30346 IX86_BUILTIN_VFMADDSS,
30347 IX86_BUILTIN_VFMADDSD,
30348 IX86_BUILTIN_VFMADDPS,
30349 IX86_BUILTIN_VFMADDPD,
30350 IX86_BUILTIN_VFMADDPS256,
30351 IX86_BUILTIN_VFMADDPD256,
30352 IX86_BUILTIN_VFMADDSUBPS,
30353 IX86_BUILTIN_VFMADDSUBPD,
30354 IX86_BUILTIN_VFMADDSUBPS256,
30355 IX86_BUILTIN_VFMADDSUBPD256,
30357 /* FMA3 instructions. */
30358 IX86_BUILTIN_VFMADDSS3,
30359 IX86_BUILTIN_VFMADDSD3,
30361 /* XOP instructions. */
30362 IX86_BUILTIN_VPCMOV,
30363 IX86_BUILTIN_VPCMOV_V2DI,
30364 IX86_BUILTIN_VPCMOV_V4SI,
30365 IX86_BUILTIN_VPCMOV_V8HI,
30366 IX86_BUILTIN_VPCMOV_V16QI,
30367 IX86_BUILTIN_VPCMOV_V4SF,
30368 IX86_BUILTIN_VPCMOV_V2DF,
30369 IX86_BUILTIN_VPCMOV256,
30370 IX86_BUILTIN_VPCMOV_V4DI256,
30371 IX86_BUILTIN_VPCMOV_V8SI256,
30372 IX86_BUILTIN_VPCMOV_V16HI256,
30373 IX86_BUILTIN_VPCMOV_V32QI256,
30374 IX86_BUILTIN_VPCMOV_V8SF256,
30375 IX86_BUILTIN_VPCMOV_V4DF256,
30377 IX86_BUILTIN_VPPERM,
30379 IX86_BUILTIN_VPMACSSWW,
30380 IX86_BUILTIN_VPMACSWW,
30381 IX86_BUILTIN_VPMACSSWD,
30382 IX86_BUILTIN_VPMACSWD,
30383 IX86_BUILTIN_VPMACSSDD,
30384 IX86_BUILTIN_VPMACSDD,
30385 IX86_BUILTIN_VPMACSSDQL,
30386 IX86_BUILTIN_VPMACSSDQH,
30387 IX86_BUILTIN_VPMACSDQL,
30388 IX86_BUILTIN_VPMACSDQH,
30389 IX86_BUILTIN_VPMADCSSWD,
30390 IX86_BUILTIN_VPMADCSWD,
30392 IX86_BUILTIN_VPHADDBW,
30393 IX86_BUILTIN_VPHADDBD,
30394 IX86_BUILTIN_VPHADDBQ,
30395 IX86_BUILTIN_VPHADDWD,
30396 IX86_BUILTIN_VPHADDWQ,
30397 IX86_BUILTIN_VPHADDDQ,
30398 IX86_BUILTIN_VPHADDUBW,
30399 IX86_BUILTIN_VPHADDUBD,
30400 IX86_BUILTIN_VPHADDUBQ,
30401 IX86_BUILTIN_VPHADDUWD,
30402 IX86_BUILTIN_VPHADDUWQ,
30403 IX86_BUILTIN_VPHADDUDQ,
30404 IX86_BUILTIN_VPHSUBBW,
30405 IX86_BUILTIN_VPHSUBWD,
30406 IX86_BUILTIN_VPHSUBDQ,
30408 IX86_BUILTIN_VPROTB,
30409 IX86_BUILTIN_VPROTW,
30410 IX86_BUILTIN_VPROTD,
30411 IX86_BUILTIN_VPROTQ,
30412 IX86_BUILTIN_VPROTB_IMM,
30413 IX86_BUILTIN_VPROTW_IMM,
30414 IX86_BUILTIN_VPROTD_IMM,
30415 IX86_BUILTIN_VPROTQ_IMM,
30417 IX86_BUILTIN_VPSHLB,
30418 IX86_BUILTIN_VPSHLW,
30419 IX86_BUILTIN_VPSHLD,
30420 IX86_BUILTIN_VPSHLQ,
30421 IX86_BUILTIN_VPSHAB,
30422 IX86_BUILTIN_VPSHAW,
30423 IX86_BUILTIN_VPSHAD,
30424 IX86_BUILTIN_VPSHAQ,
30426 IX86_BUILTIN_VFRCZSS,
30427 IX86_BUILTIN_VFRCZSD,
30428 IX86_BUILTIN_VFRCZPS,
30429 IX86_BUILTIN_VFRCZPD,
30430 IX86_BUILTIN_VFRCZPS256,
30431 IX86_BUILTIN_VFRCZPD256,
30433 IX86_BUILTIN_VPCOMEQUB,
30434 IX86_BUILTIN_VPCOMNEUB,
30435 IX86_BUILTIN_VPCOMLTUB,
30436 IX86_BUILTIN_VPCOMLEUB,
30437 IX86_BUILTIN_VPCOMGTUB,
30438 IX86_BUILTIN_VPCOMGEUB,
30439 IX86_BUILTIN_VPCOMFALSEUB,
30440 IX86_BUILTIN_VPCOMTRUEUB,
30442 IX86_BUILTIN_VPCOMEQUW,
30443 IX86_BUILTIN_VPCOMNEUW,
30444 IX86_BUILTIN_VPCOMLTUW,
30445 IX86_BUILTIN_VPCOMLEUW,
30446 IX86_BUILTIN_VPCOMGTUW,
30447 IX86_BUILTIN_VPCOMGEUW,
30448 IX86_BUILTIN_VPCOMFALSEUW,
30449 IX86_BUILTIN_VPCOMTRUEUW,
30451 IX86_BUILTIN_VPCOMEQUD,
30452 IX86_BUILTIN_VPCOMNEUD,
30453 IX86_BUILTIN_VPCOMLTUD,
30454 IX86_BUILTIN_VPCOMLEUD,
30455 IX86_BUILTIN_VPCOMGTUD,
30456 IX86_BUILTIN_VPCOMGEUD,
30457 IX86_BUILTIN_VPCOMFALSEUD,
30458 IX86_BUILTIN_VPCOMTRUEUD,
30460 IX86_BUILTIN_VPCOMEQUQ,
30461 IX86_BUILTIN_VPCOMNEUQ,
30462 IX86_BUILTIN_VPCOMLTUQ,
30463 IX86_BUILTIN_VPCOMLEUQ,
30464 IX86_BUILTIN_VPCOMGTUQ,
30465 IX86_BUILTIN_VPCOMGEUQ,
30466 IX86_BUILTIN_VPCOMFALSEUQ,
30467 IX86_BUILTIN_VPCOMTRUEUQ,
30469 IX86_BUILTIN_VPCOMEQB,
30470 IX86_BUILTIN_VPCOMNEB,
30471 IX86_BUILTIN_VPCOMLTB,
30472 IX86_BUILTIN_VPCOMLEB,
30473 IX86_BUILTIN_VPCOMGTB,
30474 IX86_BUILTIN_VPCOMGEB,
30475 IX86_BUILTIN_VPCOMFALSEB,
30476 IX86_BUILTIN_VPCOMTRUEB,
30478 IX86_BUILTIN_VPCOMEQW,
30479 IX86_BUILTIN_VPCOMNEW,
30480 IX86_BUILTIN_VPCOMLTW,
30481 IX86_BUILTIN_VPCOMLEW,
30482 IX86_BUILTIN_VPCOMGTW,
30483 IX86_BUILTIN_VPCOMGEW,
30484 IX86_BUILTIN_VPCOMFALSEW,
30485 IX86_BUILTIN_VPCOMTRUEW,
30487 IX86_BUILTIN_VPCOMEQD,
30488 IX86_BUILTIN_VPCOMNED,
30489 IX86_BUILTIN_VPCOMLTD,
30490 IX86_BUILTIN_VPCOMLED,
30491 IX86_BUILTIN_VPCOMGTD,
30492 IX86_BUILTIN_VPCOMGED,
30493 IX86_BUILTIN_VPCOMFALSED,
30494 IX86_BUILTIN_VPCOMTRUED,
30496 IX86_BUILTIN_VPCOMEQQ,
30497 IX86_BUILTIN_VPCOMNEQ,
30498 IX86_BUILTIN_VPCOMLTQ,
30499 IX86_BUILTIN_VPCOMLEQ,
30500 IX86_BUILTIN_VPCOMGTQ,
30501 IX86_BUILTIN_VPCOMGEQ,
30502 IX86_BUILTIN_VPCOMFALSEQ,
30503 IX86_BUILTIN_VPCOMTRUEQ,
30505 /* LWP instructions. */
30506 IX86_BUILTIN_LLWPCB,
30507 IX86_BUILTIN_SLWPCB,
30508 IX86_BUILTIN_LWPVAL32,
30509 IX86_BUILTIN_LWPVAL64,
30510 IX86_BUILTIN_LWPINS32,
30511 IX86_BUILTIN_LWPINS64,
30513 IX86_BUILTIN_CLZS,
30515 /* RTM */
30516 IX86_BUILTIN_XBEGIN,
30517 IX86_BUILTIN_XEND,
30518 IX86_BUILTIN_XABORT,
30519 IX86_BUILTIN_XTEST,
30521 /* MPX */
30522 IX86_BUILTIN_BNDMK,
30523 IX86_BUILTIN_BNDSTX,
30524 IX86_BUILTIN_BNDLDX,
30525 IX86_BUILTIN_BNDCL,
30526 IX86_BUILTIN_BNDCU,
30527 IX86_BUILTIN_BNDRET,
30528 IX86_BUILTIN_BNDNARROW,
30529 IX86_BUILTIN_BNDINT,
30530 IX86_BUILTIN_SIZEOF,
30531 IX86_BUILTIN_BNDLOWER,
30532 IX86_BUILTIN_BNDUPPER,
30534 /* BMI instructions. */
30535 IX86_BUILTIN_BEXTR32,
30536 IX86_BUILTIN_BEXTR64,
30537 IX86_BUILTIN_CTZS,
30539 /* TBM instructions. */
30540 IX86_BUILTIN_BEXTRI32,
30541 IX86_BUILTIN_BEXTRI64,
30543 /* BMI2 instructions. */
30544 IX86_BUILTIN_BZHI32,
30545 IX86_BUILTIN_BZHI64,
30546 IX86_BUILTIN_PDEP32,
30547 IX86_BUILTIN_PDEP64,
30548 IX86_BUILTIN_PEXT32,
30549 IX86_BUILTIN_PEXT64,
30551 /* ADX instructions. */
30552 IX86_BUILTIN_ADDCARRYX32,
30553 IX86_BUILTIN_ADDCARRYX64,
30555 /* SBB instructions. */
30556 IX86_BUILTIN_SBB32,
30557 IX86_BUILTIN_SBB64,
30559 /* FSGSBASE instructions. */
30560 IX86_BUILTIN_RDFSBASE32,
30561 IX86_BUILTIN_RDFSBASE64,
30562 IX86_BUILTIN_RDGSBASE32,
30563 IX86_BUILTIN_RDGSBASE64,
30564 IX86_BUILTIN_WRFSBASE32,
30565 IX86_BUILTIN_WRFSBASE64,
30566 IX86_BUILTIN_WRGSBASE32,
30567 IX86_BUILTIN_WRGSBASE64,
30569 /* RDRND instructions. */
30570 IX86_BUILTIN_RDRAND16_STEP,
30571 IX86_BUILTIN_RDRAND32_STEP,
30572 IX86_BUILTIN_RDRAND64_STEP,
30574 /* RDSEED instructions. */
30575 IX86_BUILTIN_RDSEED16_STEP,
30576 IX86_BUILTIN_RDSEED32_STEP,
30577 IX86_BUILTIN_RDSEED64_STEP,
30579 /* F16C instructions. */
30580 IX86_BUILTIN_CVTPH2PS,
30581 IX86_BUILTIN_CVTPH2PS256,
30582 IX86_BUILTIN_CVTPS2PH,
30583 IX86_BUILTIN_CVTPS2PH256,
30585 /* CFString built-in for darwin */
30586 IX86_BUILTIN_CFSTRING,
30588 /* Builtins to get CPU type and supported features. */
30589 IX86_BUILTIN_CPU_INIT,
30590 IX86_BUILTIN_CPU_IS,
30591 IX86_BUILTIN_CPU_SUPPORTS,
30593 /* Read/write FLAGS register built-ins. */
30594 IX86_BUILTIN_READ_FLAGS,
30595 IX86_BUILTIN_WRITE_FLAGS,
30597 IX86_BUILTIN_MAX
30598 };
30600 /* Table for the ix86 builtin decls. */
30603 /* Table of all of the builtin functions that are possible with different ISA's
30604 but are waiting to be built until a function is declared to use that
30605 ISA. */
30614 };
30618 /* Bits that can still enable any inclusion of a builtin. */
30621 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30622 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30623 function decl in the ix86_builtins array. Returns the function decl or
30624 NULL_TREE, if the builtin was not added.
30626 If the front end has a special hook for builtin functions, delay adding
30627 builtin functions that aren't in the current ISA until the ISA is changed
30628 with function specific optimization. Doing so, can save about 300K for the
30629 default compiler. When the builtin is expanded, check at that time whether
30630 it is valid.
30632 If the front end doesn't have a special hook, record all builtins, even if
30633 it isn't an instruction set in the current ISA in case the user uses
30634 function specific options for a different ISA, so that we don't get scope
30635 errors if a builtin is added in the middle of a function scope. */
30641 {
30645 {
30654 {
30660 }
30661 else
30662 {
30663 /* Just a MASK where set_and_not_built_p == true can potentially
30664 include a builtin. */
30673 }
30674 }
30677 }
30679 /* Like def_builtin, but also marks the function decl "const". */
30684 {
30688 else
30692 }
30694 /* Add any new builtin functions for a given ISA that may not have been
30695 declared. This saves a bit of space compared to adding all of the
30696 declarations to the tree, even if we didn't use them. */
30698 static void
30700 {
30704 /* Bits in ISA value can be removed from potential isa values. */
30712 {
30715 {
30718 /* Don't define the builtin again. */
30724 NULL_TREE);
30731 NULL_TREE);
30734 }
30735 }
30738 }
30740 /* Bits for builtin_description.flag. */
30742 /* Set when we don't support the comparison natively, and should
30743 swap_comparison in order to support it. */
30744 #define BUILTIN_DESC_SWAP_OPERANDS 1
30746 struct builtin_description
30747 {
30754 };
30757 {
30758 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30759 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30760 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30761 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30770 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30771 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30773 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30774 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30775 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30776 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30777 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30781 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30782 };
30785 {
30786 /* SSE4.2 */
30787 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30788 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30789 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30790 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30791 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30792 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30793 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30794 };
30797 {
30798 /* SSE4.2 */
30799 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30800 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30801 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30802 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30803 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30804 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30805 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30806 };
30808 /* Special builtins with variable number of arguments. */
30810 {
30811 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30812 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30813 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30815 /* 80387 (for use internally for atomic compound assignment). */
30816 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30817 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30818 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30819 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30821 /* MMX */
30822 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30824 /* 3DNow! */
30825 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30827 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30828 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30829 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30830 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30831 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30832 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30833 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30834 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30835 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30837 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30838 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30839 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30840 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30841 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30842 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30843 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30844 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30846 /* SSE */
30847 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30848 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30849 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30851 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30852 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30853 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30854 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30856 /* SSE or 3DNow!A */
30857 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30858 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30860 /* SSE2 */
30861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30862 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30863 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30864 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30865 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30868 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30875 /* SSE3 */
30876 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30878 /* SSE4.1 */
30879 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30881 /* SSE4A */
30882 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30883 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30885 /* AVX */
30886 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30887 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30889 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30890 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30891 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30892 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30893 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30895 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30896 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30897 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30898 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30899 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30907 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30913 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30916 /* AVX2 */
30917 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30918 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30919 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30920 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30921 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30922 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30927 /* AVX512F */
30928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30976 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30977 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30978 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30979 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30980 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30981 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30983 /* FSGSBASE */
30984 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30985 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30986 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30987 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30988 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30989 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30990 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30991 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30993 /* RTM */
30994 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30995 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30996 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30998 /* AVX512BW */
30999 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
31000 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
31001 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
31002 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
31004 /* AVX512VL */
31005 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
31006 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
31007 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
31008 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
31009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31011 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31032 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31038 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31041 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
31042 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
31043 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
31044 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
31045 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31046 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31047 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31048 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31054 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31080 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31081 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31082 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31084 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31085 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31086 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31091 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31092 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31097 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31100 /* PCOMMIT. */
31101 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31102 };
31104 /* Builtins with variable number of arguments. */
31106 {
31107 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31108 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31109 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31110 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31111 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31112 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31113 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31115 /* MMX */
31116 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31117 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31118 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31136 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31158 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31161 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31162 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31163 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31168 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31170 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31174 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31175 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31176 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31177 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31179 /* 3DNow! */
31180 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31181 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31182 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31183 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31185 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31186 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31187 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31188 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31189 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31190 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31191 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31192 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31193 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31194 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31195 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31196 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31197 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31198 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31199 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31201 /* 3DNow!A */
31202 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31203 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31204 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31205 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31206 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31207 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31209 /* SSE */
31210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31212 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31214 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31216 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31218 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31220 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31221 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31225 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31226 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31227 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31228 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31231 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31255 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31256 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31260 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31261 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31262 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31263 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31265 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31267 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31268 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31269 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31270 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31271 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31275 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31277 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31279 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31280 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31283 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31284 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31286 /* SSE MMX or 3Dnow!A */
31287 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31288 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31289 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31291 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31292 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31293 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31294 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31296 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31297 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31299 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31301 /* SSE2 */
31302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31308 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31320 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31321 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31325 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31327 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31328 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31329 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31330 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31358 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31362 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31364 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31365 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31367 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31370 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31371 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31373 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31375 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31376 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31377 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31378 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31379 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31380 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31381 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31382 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31393 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31394 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31396 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31398 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31399 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31411 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31412 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31413 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31416 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31417 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31418 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31419 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31420 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31421 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31422 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31423 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31429 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31433 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31438 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31443 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31444 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31445 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31446 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31447 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31448 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31451 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31452 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31453 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31454 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31455 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31456 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31458 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31459 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31460 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31461 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31469 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31471 /* SSE2 MMX */
31472 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31473 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31475 /* SSE3 */
31476 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31477 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31479 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31480 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31481 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31482 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31483 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31484 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31486 /* SSSE3 */
31487 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31488 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31490 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31504 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31505 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31508 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31509 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31510 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31513 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31514 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31515 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31516 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31517 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31519 /* SSSE3. */
31520 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31521 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31523 /* SSE4.1 */
31524 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31525 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31543 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31550 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31553 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31556 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31557 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31558 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31559 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31560 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31562 /* SSE4.1 */
31563 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31564 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31565 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31566 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31569 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31570 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31571 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31573 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31574 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31576 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31577 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31579 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31580 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31581 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31582 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31584 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31585 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31587 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31588 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31590 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31591 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31592 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31594 /* SSE4.2 */
31595 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31596 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31597 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31598 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31599 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31601 /* SSE4A */
31602 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31603 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31604 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31605 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31607 /* AES */
31608 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31609 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31611 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31612 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31613 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31614 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31616 /* PCLMUL */
31617 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31619 /* AVX */
31620 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31621 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31624 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31625 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31628 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31634 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31635 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31636 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31637 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31638 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31639 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31640 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31641 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31642 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31643 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31644 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31645 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31668 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31669 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31670 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31673 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31675 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31691 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31693 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31695 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31707 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31708 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31721 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31722 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31732 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31733 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31734 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31755 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31756 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31758 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31760 /* AVX2 */
31761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31762 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31763 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31764 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31769 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31770 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31771 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31772 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31778 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31800 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31801 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31802 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31803 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31804 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31805 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31806 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31807 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31808 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31809 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31810 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31811 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31822 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31824 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31825 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31826 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31827 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31828 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31829 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31830 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31831 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31832 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31833 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31834 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31835 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31836 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31837 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31839 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31842 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31843 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31844 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31845 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31846 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31847 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31848 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31849 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31850 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31851 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31852 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31853 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31854 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31855 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31856 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31857 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31858 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31859 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31860 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31861 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31862 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31872 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31875 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31908 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31910 /* BMI */
31911 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31912 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31913 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31915 /* TBM */
31916 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31917 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31919 /* F16C */
31920 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31921 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31922 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31923 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31925 /* BMI2 */
31926 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31927 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31928 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31929 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31930 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31931 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31933 /* AVX512F */
31934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31989 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31990 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32100 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32101 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32102 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32103 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32135 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32140 /* Mask arithmetic operations */
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32152 /* SHA */
32153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32161 /* AVX512VL. */
32162 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32163 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32172 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32173 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32174 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32175 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32200 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32201 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32202 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32203 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32204 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32205 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32206 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32207 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32208 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32209 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32210 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32211 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32212 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32217 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32218 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32219 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32220 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32221 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32222 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32223 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32224 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32225 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32226 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32229 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32230 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32231 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32232 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32253 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32254 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32255 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32256 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32257 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32258 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32259 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32260 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32272 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32273 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32276 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32277 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32288 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32289 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32300 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32301 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32302 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32303 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32304 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32305 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32306 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32307 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32308 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32309 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32310 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32311 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32312 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32313 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32314 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32315 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32316 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32317 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32326 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32327 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32330 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32331 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32334 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32335 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32336 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32337 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32338 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32339 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32340 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32341 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32342 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32343 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32346 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32347 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32348 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32349 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32350 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32351 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32354 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32355 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32356 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32357 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32362 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32363 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32364 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32365 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32366 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32367 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32398 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32399 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32400 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32401 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32418 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32419 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32420 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32421 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32422 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32423 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32424 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32425 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32426 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32427 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32428 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32429 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32430 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32431 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32432 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32433 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32434 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32435 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32436 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32439 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32441 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32442 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32443 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32480 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32481 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32482 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32483 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32544 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32545 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32546 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32547 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32548 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32549 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32550 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32551 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32552 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32553 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32558 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32559 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32560 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32561 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32572 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32573 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32574 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32575 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32576 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32577 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32578 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32579 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32583 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32604 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32605 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32606 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32607 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32608 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32609 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32636 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32637 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32638 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32639 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32640 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32644 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32645 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32646 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32647 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32652 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32653 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32654 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32655 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32656 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32657 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32658 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32659 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32660 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32661 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32662 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32663 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32664 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32665 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32666 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32667 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32668 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32669 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32670 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32671 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32672 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32673 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32674 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32675 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32676 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32677 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32682 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32683 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32684 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32685 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32690 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32691 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32692 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32693 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32698 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32699 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32700 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32706 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32707 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32708 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32709 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32750 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32751 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32752 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32753 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32754 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32755 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32756 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32757 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32758 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32759 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32760 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32761 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32762 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32763 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32764 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32765 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32766 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32767 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32768 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32769 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32777 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32778 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32779 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32780 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32784 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32785 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32786 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32787 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32798 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32799 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32800 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32801 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32802 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32803 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32804 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32805 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32806 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32807 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32808 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32809 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32810 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32811 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32812 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32813 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32814 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32815 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32816 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32817 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32818 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32819 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32820 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32821 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32822 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32823 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32824 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32825 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32826 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32838 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32839 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32840 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32841 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32842 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32845 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32846 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32847 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32854 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32858 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32859 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32860 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32861 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32868 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32869 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32870 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32871 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32875 /* AVX512DQ. */
32876 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32877 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32878 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32879 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32880 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32881 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32882 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32883 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32884 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32885 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32886 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32887 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32888 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32889 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32890 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32891 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32892 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32893 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32894 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32895 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32896 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32897 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32898 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32899 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32900 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32901 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32902 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32903 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32904 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32905 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32906 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32908 /* AVX512BW. */
32909 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32910 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32911 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32912 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32913 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32914 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32915 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32916 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32917 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32918 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32919 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32920 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32921 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32922 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32923 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32924 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32925 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32926 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32927 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32928 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32929 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32930 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32931 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32932 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32933 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32934 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32935 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32936 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32937 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32938 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32939 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32940 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32941 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32942 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32943 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32944 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32945 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32946 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32947 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32948 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32949 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32950 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32951 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32952 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32953 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32954 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32955 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32956 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32957 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32958 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32959 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32960 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32961 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32962 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32963 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32964 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32965 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32966 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32967 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32968 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32969 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32970 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32971 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32972 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32973 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32974 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32975 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32976 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32977 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32978 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32979 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32980 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32981 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32982 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32983 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32984 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32985 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32986 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32987 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32988 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32989 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32990 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32991 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32992 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32993 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32994 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32995 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32996 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32997 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32998 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32999 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33001 /* AVX512IFMA */
33002 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33003 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33004 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33005 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33006 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33007 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33008 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33009 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33010 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33011 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33012 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33013 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33015 /* AVX512VBMI */
33016 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33017 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33018 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33019 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33020 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33021 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33022 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33023 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33024 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33025 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33026 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33027 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33028 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33029 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33030 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33031 };
33033 /* Builtins with rounding support. */
33035 {
33036 /* AVX512F */
33037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
33042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
33043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
33044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
33045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33056 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33058 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33065 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33067 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33117 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33119 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33121 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33123 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33125 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33127 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33129 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33131 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33157 /* AVX512ER */
33158 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33159 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33160 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33161 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33162 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33163 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33164 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33165 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33166 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33167 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33169 /* AVX512DQ. */
33170 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33171 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33172 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33173 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33174 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33175 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33176 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33177 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33178 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33179 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33180 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33181 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33182 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33183 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33184 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33185 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33186 };
33188 /* Bultins for MPX. */
33190 {
33191 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33192 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33193 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33194 };
33196 /* Const builtins for MPX. */
33198 {
33199 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33200 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33201 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33202 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33203 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33204 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33205 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33206 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33207 };
33209 /* FMA4 and XOP. */
33210 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33211 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33212 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33213 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33214 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33215 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33216 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33217 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33218 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33219 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33220 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33221 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33222 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33223 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33224 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33225 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33226 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33227 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33228 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33229 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33230 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33231 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33232 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33233 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33234 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33235 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33236 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33237 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33238 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33239 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33240 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33241 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33242 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33243 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33244 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33245 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33246 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33247 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33248 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33249 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33250 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33251 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33252 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33253 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33254 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33255 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33256 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33257 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33258 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33259 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33260 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33261 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33264 {
33305 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33306 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33308 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33339 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33348 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33356 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33363 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33364 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33379 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33380 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33463 };
33464 \f
33465 /* TM vector builtins. */
33467 /* Reuse the existing x86-specific `struct builtin_description' cause
33468 we're lazy. Add casts to make them fit. */
33470 {
33471 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33472 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33473 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33474 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33475 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33476 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33477 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33479 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33480 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33481 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33482 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33483 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33484 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33485 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33487 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33488 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33489 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33490 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33491 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33492 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33493 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33495 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33496 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33497 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33498 };
33500 /* TM callbacks. */
33502 /* Return the builtin decl needed to load a vector of TYPE. */
33504 static tree
33506 {
33508 {
33510 {
33517 }
33518 }
33520 }
33522 /* Return the builtin decl needed to store a vector of TYPE. */
33524 static tree
33526 {
33528 {
33530 {
33537 }
33538 }
33540 }
33541 \f
33542 /* Initialize the transactional memory vector load/store builtins. */
33544 static void
33546 {
33550 tree decl;
33557 /* If there are no builtins defined, we must be compiling in a
33558 language without trans-mem support. */
33562 /* Use whatever attributes a normal TM load has. */
33566 /* Use whatever attributes a normal TM store has. */
33570 /* Use whatever attributes a normal TM log has. */
33578 {
33582 {
33590 {
33593 }
33595 {
33598 }
33599 else
33600 {
33603 }
33605 /* The builtin without the prefix for
33606 calling it directly. */
33608 attrs);
33609 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33610 set the TYPE_ATTRIBUTES. */
33614 }
33615 }
33616 }
33618 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33619 in the current target ISA to allow the user to compile particular modules
33620 with different target specific options that differ from the command line
33621 options. */
33622 static void
33624 {
33629 /* Add all special builtins with variable number of operands. */
33633 {
33639 }
33641 /* Add all builtins with variable number of operands. */
33645 {
33651 }
33653 /* Add all builtins with rounding. */
33657 {
33663 }
33665 /* pcmpestr[im] insns. */
33669 {
33672 else
33675 }
33677 /* pcmpistr[im] insns. */
33681 {
33684 else
33687 }
33689 /* comi/ucomi insns. */
33691 {
33694 else
33697 }
33699 /* SSE */
33705 /* SSE or 3DNow!A */
33708 IX86_BUILTIN_MASKMOVQ);
33710 /* SSE2 */
33719 /* SSE3. */
33725 /* AES */
33739 /* PCLMUL */
33743 /* RDRND */
33750 IX86_BUILTIN_RDRAND64_STEP);
33752 /* AVX2 */
33754 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33755 IX86_BUILTIN_GATHERSIV2DF);
33758 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33759 IX86_BUILTIN_GATHERSIV4DF);
33762 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33763 IX86_BUILTIN_GATHERDIV2DF);
33766 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33767 IX86_BUILTIN_GATHERDIV4DF);
33770 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33771 IX86_BUILTIN_GATHERSIV4SF);
33774 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33775 IX86_BUILTIN_GATHERSIV8SF);
33778 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33779 IX86_BUILTIN_GATHERDIV4SF);
33782 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33783 IX86_BUILTIN_GATHERDIV8SF);
33786 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33787 IX86_BUILTIN_GATHERSIV2DI);
33790 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33791 IX86_BUILTIN_GATHERSIV4DI);
33794 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33795 IX86_BUILTIN_GATHERDIV2DI);
33798 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33799 IX86_BUILTIN_GATHERDIV4DI);
33802 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33803 IX86_BUILTIN_GATHERSIV4SI);
33806 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33807 IX86_BUILTIN_GATHERSIV8SI);
33810 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33811 IX86_BUILTIN_GATHERDIV4SI);
33814 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33815 IX86_BUILTIN_GATHERDIV8SI);
33818 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33819 IX86_BUILTIN_GATHERALTSIV4DF);
33822 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33823 IX86_BUILTIN_GATHERALTDIV8SF);
33826 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33827 IX86_BUILTIN_GATHERALTSIV4DI);
33830 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33831 IX86_BUILTIN_GATHERALTDIV8SI);
33833 /* AVX512F */
33835 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33836 IX86_BUILTIN_GATHER3SIV16SF);
33839 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33840 IX86_BUILTIN_GATHER3SIV8DF);
33843 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33844 IX86_BUILTIN_GATHER3DIV16SF);
33847 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33848 IX86_BUILTIN_GATHER3DIV8DF);
33851 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33852 IX86_BUILTIN_GATHER3SIV16SI);
33855 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33856 IX86_BUILTIN_GATHER3SIV8DI);
33859 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33860 IX86_BUILTIN_GATHER3DIV16SI);
33863 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33864 IX86_BUILTIN_GATHER3DIV8DI);
33867 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33868 IX86_BUILTIN_GATHER3ALTSIV8DF);
33871 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33872 IX86_BUILTIN_GATHER3ALTDIV16SF);
33875 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33876 IX86_BUILTIN_GATHER3ALTSIV8DI);
33879 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33880 IX86_BUILTIN_GATHER3ALTDIV16SI);
33883 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33884 IX86_BUILTIN_SCATTERSIV16SF);
33887 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33888 IX86_BUILTIN_SCATTERSIV8DF);
33891 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33892 IX86_BUILTIN_SCATTERDIV16SF);
33895 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33896 IX86_BUILTIN_SCATTERDIV8DF);
33899 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33900 IX86_BUILTIN_SCATTERSIV16SI);
33903 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33904 IX86_BUILTIN_SCATTERSIV8DI);
33907 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33908 IX86_BUILTIN_SCATTERDIV16SI);
33911 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33912 IX86_BUILTIN_SCATTERDIV8DI);
33914 /* AVX512VL */
33916 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33917 IX86_BUILTIN_GATHER3SIV2DF);
33920 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33921 IX86_BUILTIN_GATHER3SIV4DF);
33924 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33925 IX86_BUILTIN_GATHER3DIV2DF);
33928 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33929 IX86_BUILTIN_GATHER3DIV4DF);
33932 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33933 IX86_BUILTIN_GATHER3SIV4SF);
33936 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33937 IX86_BUILTIN_GATHER3SIV8SF);
33940 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33941 IX86_BUILTIN_GATHER3DIV4SF);
33944 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33945 IX86_BUILTIN_GATHER3DIV8SF);
33948 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33949 IX86_BUILTIN_GATHER3SIV2DI);
33952 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33953 IX86_BUILTIN_GATHER3SIV4DI);
33956 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33957 IX86_BUILTIN_GATHER3DIV2DI);
33960 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33961 IX86_BUILTIN_GATHER3DIV4DI);
33964 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33965 IX86_BUILTIN_GATHER3SIV4SI);
33968 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33969 IX86_BUILTIN_GATHER3SIV8SI);
33972 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33973 IX86_BUILTIN_GATHER3DIV4SI);
33976 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33977 IX86_BUILTIN_GATHER3DIV8SI);
33980 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33981 IX86_BUILTIN_GATHER3ALTSIV4DF);
33984 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33985 IX86_BUILTIN_GATHER3ALTDIV8SF);
33988 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33989 IX86_BUILTIN_GATHER3ALTSIV4DI);
33992 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33993 IX86_BUILTIN_GATHER3ALTDIV8SI);
33996 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33997 IX86_BUILTIN_SCATTERSIV8SF);
34000 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34001 IX86_BUILTIN_SCATTERSIV4SF);
34004 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34005 IX86_BUILTIN_SCATTERSIV4DF);
34008 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34009 IX86_BUILTIN_SCATTERSIV2DF);
34012 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34013 IX86_BUILTIN_SCATTERDIV8SF);
34016 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34017 IX86_BUILTIN_SCATTERDIV4SF);
34020 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34021 IX86_BUILTIN_SCATTERDIV4DF);
34024 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34025 IX86_BUILTIN_SCATTERDIV2DF);
34028 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34029 IX86_BUILTIN_SCATTERSIV8SI);
34032 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34033 IX86_BUILTIN_SCATTERSIV4SI);
34036 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34037 IX86_BUILTIN_SCATTERSIV4DI);
34040 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34041 IX86_BUILTIN_SCATTERSIV2DI);
34044 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34045 IX86_BUILTIN_SCATTERDIV8SI);
34048 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34049 IX86_BUILTIN_SCATTERDIV4SI);
34052 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34053 IX86_BUILTIN_SCATTERDIV4DI);
34056 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34057 IX86_BUILTIN_SCATTERDIV2DI);
34059 /* AVX512PF */
34061 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34062 IX86_BUILTIN_GATHERPFDPD);
34064 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34065 IX86_BUILTIN_GATHERPFDPS);
34067 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34068 IX86_BUILTIN_GATHERPFQPD);
34070 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34071 IX86_BUILTIN_GATHERPFQPS);
34073 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34074 IX86_BUILTIN_SCATTERPFDPD);
34076 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34077 IX86_BUILTIN_SCATTERPFDPS);
34079 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34080 IX86_BUILTIN_SCATTERPFQPD);
34082 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34083 IX86_BUILTIN_SCATTERPFQPS);
34085 /* SHA */
34101 /* RTM. */
34105 /* MMX access to the vec_init patterns. */
34110 V4HI_FTYPE_HI_HI_HI_HI,
34111 IX86_BUILTIN_VEC_INIT_V4HI);
34114 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34115 IX86_BUILTIN_VEC_INIT_V8QI);
34117 /* Access to the vec_extract patterns. */
34139 /* Access to the vec_set patterns. */
34160 /* RDSEED */
34169 /* ADCX */
34174 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34175 IX86_BUILTIN_ADDCARRYX64);
34177 /* SBB */
34182 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34183 IX86_BUILTIN_SBB64);
34185 /* Read/write FLAGS. */
34195 /* CLFLUSHOPT. */
34199 /* CLWB. */
34203 /* Add FMA4 multi-arg argument instructions */
34205 {
34211 }
34212 }
34214 static void
34216 {
34219 tree decl;
34225 {
34232 /* With no leaf and nothrow flags for MPX builtins
34233 abnormal edges may follow its call when setjmp
34234 presents in the function. Since we may have a lot
34235 of MPX builtins calls it causes lots of useless
34236 edges and enormous PHI nodes. To avoid this we mark
34237 MPX builtins as leaf and nothrow. */
34239 {
34241 NULL_TREE);
34243 }
34244 else
34245 {
34248 }
34249 }
34254 {
34262 {
34264 NULL_TREE);
34266 }
34267 else
34268 {
34271 }
34272 }
34273 }
34275 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34276 to return a pointer to VERSION_DECL if the outcome of the expression
34277 formed by PREDICATE_CHAIN is true. This function will be called during
34278 version dispatch to decide which function version to execute. It returns
34279 the basic block at the end, to which more conditions can be added. */
34281 static basic_block
34284 {
34285 gimple return_stmt;
34287 gimple convert_stmt;
34288 gimple call_cond_stmt;
34289 gimple if_else_stmt;
34295 gimple_seq gseq;
34312 {
34320 }
34323 {
34338 else
34339 {
34340 gimple assign_stmt;
34341 /* Use MIN_EXPR to check if any integer is zero?.
34342 and_expr_var = min_expr <cond_var, and_expr_var> */
34350 }
34351 }
34354 integer_zero_node,
34384 }
34386 /* This parses the attribute arguments to target in DECL and determines
34387 the right builtin to use to match the platform specification.
34388 It returns the priority value for this version decl. If PREDICATE_LIST
34389 is not NULL, it stores the list of cpu features that need to be checked
34390 before dispatching this function. */
34392 static unsigned int
34394 {
34395 tree attrs;
34397 tree target_node;
34404 /* Priority of i386 features, greater value is higher priority. This is
34405 used to decide the order in which function dispatch must happen. For
34406 instance, a version specialized for SSE4.2 should be checked for dispatch
34407 before a version for SSE3, as SSE4.2 implies SSE3. */
34408 enum feature_priority
34409 {
34411 P_MMX,
34412 P_SSE,
34413 P_SSE2,
34414 P_SSE3,
34415 P_SSSE3,
34416 P_PROC_SSSE3,
34417 P_SSE4_A,
34418 P_PROC_SSE4_A,
34419 P_SSE4_1,
34420 P_SSE4_2,
34421 P_PROC_SSE4_2,
34422 P_POPCNT,
34423 P_AVX,
34424 P_PROC_AVX,
34425 P_BMI,
34426 P_PROC_BMI,
34427 P_FMA4,
34428 P_XOP,
34429 P_PROC_XOP,
34430 P_FMA,
34431 P_PROC_FMA,
34432 P_BMI2,
34433 P_AVX2,
34434 P_PROC_AVX2,
34435 P_AVX512F,
34436 P_PROC_AVX512F
34437 };
34441 /* These are the target attribute strings for which a dispatcher is
34442 available, from fold_builtin_cpu. */
34444 static struct _feature_list
34445 {
34448 }
34450 {
34468 };
34471 static unsigned int NUM_FEATURES
34487 /* Return priority zero for default function. */
34491 /* Handle arch= if specified. For priority, set it to be 1 more than
34492 the best instruction set the processor can handle. For instance, if
34493 there is a version for atom and a version for ssse3 (the highest ISA
34494 priority for atom), the atom version must be checked for dispatch
34495 before the ssse3 version. */
34497 {
34507 {
34509 {
34517 else
34518 /* We translate "arch=corei7" and "arch=nehalem" to
34519 "corei7" so that it will be mapped to M_INTEL_COREI7
34520 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34527 else
34534 else
34578 }
34579 }
34584 {
34588 }
34591 {
34593 /* For a C string literal the length includes the trailing NULL. */
34596 predicate_chain);
34597 }
34598 }
34600 /* Process feature name. */
34607 {
34608 /* Do not process "arch=" */
34610 {
34613 }
34615 {
34617 {
34619 {
34624 predicate_chain);
34625 }
34626 /* Find the maximum priority feature. */
34631 }
34632 }
34634 {
34638 }
34640 }
34644 {
34647 attrs_str);
34649 }
34651 {
34654 }
34657 }
34659 /* This compares the priority of target features in function DECL1
34660 and DECL2. It returns positive value if DECL1 is higher priority,
34661 negative value if DECL2 is higher priority and 0 if they are the
34662 same. */
34664 static int
34666 {
34671 }
34673 /* V1 and V2 point to function versions with different priorities
34674 based on the target ISA. This function compares their priorities. */
34676 static int
34678 {
34680 {
34681 tree version_decl;
34682 tree predicate_chain;
34689 }
34691 /* This function generates the dispatch function for
34692 multi-versioned functions. DISPATCH_DECL is the function which will
34693 contain the dispatch logic. FNDECLS are the function choices for
34694 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34695 in DISPATCH_DECL in which the dispatch code is generated. */
34697 static int
34701 {
34702 tree default_decl;
34703 gimple ifunc_cpu_init_stmt;
34704 gimple_seq gseq;
34706 tree ele;
34712 struct _function_version_info
34713 {
34714 tree version_decl;
34715 tree predicate_chain;
34723 /*fndecls_p is actually a vector. */
34726 /* At least one more version other than the default. */
34733 /* The first version in the vector is the default decl. */
34739 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34740 constructors, so explicity call __builtin_cpu_init here. */
34751 {
34755 /* Get attribute string, parse it and find the right predicate decl.
34756 The predicate function could be a lengthy combination of many
34757 features, like arch-type and various isa-variants. */
34768 actual_versions++;
34769 }
34771 /* Sort the versions according to descending order of dispatch priority. The
34772 priority is based on the ISA. This is not a perfect solution. There
34773 could still be ambiguity. If more than one function version is suitable
34774 to execute, which one should be dispatched? In future, allow the user
34775 to specify a dispatch priority next to the version. */
34785 /* dispatch default version at the end. */
34791 }
34793 /* Comparator function to be used in qsort routine to sort attribute
34794 specification strings to "target". */
34796 static int
34798 {
34802 }
34804 /* ARGLIST is the argument to target attribute. This function tokenizes
34805 the comma separated arguments, sorts them and returns a string which
34806 is a unique identifier for the comma separated arguments. It also
34807 replaces non-identifier characters "=,-" with "_". */
34811 {
34812 tree arg;
34821 {
34826 argnum++;
34829 argnum++;
34830 }
34835 {
34841 }
34843 /* Replace "=,-" with "_". */
34856 {
34858 i++;
34860 }
34867 {
34872 }
34877 }
34879 /* This function changes the assembler name for functions that are
34880 versions. If DECL is a function version and has a "target"
34881 attribute, it appends the attribute string to its assembler name. */
34883 static tree
34885 {
34886 tree version_attr;
34894 "Function versions cannot be marked as gnu_inline,"
34903 /* target attribute string cannot be NULL. */
34907 version_string
34918 /* Allow assembler name to be modified if already set. */
34926 }
34928 /* This function returns true if FN1 and FN2 are versions of the same function,
34929 that is, the target strings of the function decls are different. This assumes
34930 that FN1 and FN2 have the same signature. */
34932 static bool
34934 {
34946 /* At least one function decl should have the target attribute specified. */
34950 /* Diagnose missing target attribute if one of the decls is already
34951 multi-versioned. */
34953 {
34955 {
34957 {
34962 }
34965 fn2);
34968 /* Prevent diagnosing of the same error multiple times. */
34973 }
34975 }
34980 /* The sorted target strings must be different for fn1 and fn2
34981 to be versions. */
34984 else
34991 }
34993 static tree
34995 {
34996 /* For function version, add the target suffix to the assembler name. */
35000 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35002 #endif
35005 }
35007 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35008 is true, append the full path name of the source file. */
35012 {
35020 /* Get a unique name that can be used globally without any chances
35021 of collision at link time. */
35031 /* Use '.' to concatenate names as it is demangler friendly. */
35034 suffix);
35035 else
35039 }
35041 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35043 /* Make a dispatcher declaration for the multi-versioned function DECL.
35044 Calls to DECL function will be replaced with calls to the dispatcher
35045 by the front-end. Return the decl created. */
35047 static tree
35049 {
35050 tree func_decl;
35070 /* Mark this func as external, the resolver will flip it again if
35071 it gets generated. */
35073 /* This will be of type IFUNCs have to be externally visible. */
35077 }
35079 #endif
35081 /* Returns true if decl is multi-versioned and DECL is the default function,
35082 that is it is not tagged with target specific optimization. */
35084 static bool
35086 {
35095 }
35097 /* Make a dispatcher declaration for the multi-versioned function DECL.
35098 Calls to DECL function will be replaced with calls to the dispatcher
35099 by the front-end. Returns the decl of the dispatcher function. */
35101 static tree
35103 {
35125 /* Find the default version and make it the first node. */
35127 /* Go to the beginning of the chain. */
35132 {
35137 }
35139 /* If there is no default node, just return NULL. */
35143 /* Make default info the first node. */
35145 {
35152 }
35156 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35158 {
35163 /* Right now, the dispatching is done via ifunc. */
35169 dispatcher_version_info
35174 /* Set the dispatcher for all the versions. */
35177 {
35180 }
35181 }
35182 else
35183 #endif
35184 {
35186 "multiversioning needs ifunc which is not supported "
35188 }
35191 }
35193 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35194 it to CHAIN. */
35196 static tree
35198 {
35199 tree attr_name;
35200 tree attr_arg_name;
35201 tree attr_args;
35202 tree attr;
35209 }
35211 /* Make the resolver function decl to dispatch the versions of
35212 a multi-versioned function, DEFAULT_DECL. Create an
35213 empty basic block in the resolver and store the pointer in
35214 EMPTY_BB. Return the decl of the resolver function. */
35216 static tree
35220 {
35225 /* IFUNC's have to be globally visible. So, if the default_decl is
35226 not, then the name of the IFUNC should be made unique. */
35230 /* Append the filename to the resolver function if the versions are
35231 not externally visible. This is because the resolver function has
35232 to be externally visible for the loader to find it. So, appending
35233 the filename will prevent conflicts with a resolver function from
35234 another module which is based on the same version name. */
35237 /* The resolver function should return a (void *). */
35248 /* IFUNC resolvers have to be externally visible. */
35252 /* Resolver is not external, body is generated. */
35262 {
35263 /* In this case, each translation unit with a call to this
35264 versioned function will put out a resolver. Ensure it
35265 is comdat to keep just one copy. */
35268 }
35269 /* Build result decl and add to function_decl. */
35285 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35289 /* Create the alias for dispatch to resolver here. */
35290 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35294 }
35296 /* Generate the dispatching code body to dispatch multi-versioned function
35297 DECL. The target hook is called to process the "target" attributes and
35298 provide the code to dispatch the right function at run-time. NODE points
35299 to the dispatcher decl whose body will be created. */
35301 static tree
35303 {
35304 tree resolver_decl;
35305 basic_block empty_bb;
35306 tree default_ver_decl;
35322 /* The first version in the chain corresponds to the default version. */
35325 /* node is going to be an alias, so remove the finalized bit. */
35339 {
35341 /* Check for virtual functions here again, as by this time it should
35342 have been determined if this function needs a vtable index or
35343 not. This happens for methods in derived classes that override
35344 virtual methods in base classes but are not explicitly marked as
35345 virtual. */
35350 }
35356 }
35357 /* This builds the processor_model struct type defined in
35358 libgcc/config/i386/cpuinfo.c */
35360 static tree
35362 {
35369 /* The first 3 fields are unsigned int. */
35371 {
35377 }
35379 /* The last field is an array of unsigned integers of size one. */
35390 }
35392 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35394 static tree
35396 {
35397 tree new_decl;
35400 VAR_DECL,
35402 type);
35415 }
35417 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35418 into an integer defined in libgcc/config/i386/cpuinfo.c */
35420 static tree
35422 {
35428 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35429 enum processor_features
35430 {
35432 F_MMX,
35433 F_POPCNT,
35434 F_SSE,
35435 F_SSE2,
35436 F_SSE3,
35437 F_SSSE3,
35438 F_SSE4_1,
35439 F_SSE4_2,
35440 F_AVX,
35441 F_AVX2,
35442 F_SSE4_A,
35443 F_FMA4,
35444 F_XOP,
35445 F_FMA,
35446 F_AVX512F,
35447 F_BMI,
35448 F_BMI2,
35449 F_MAX
35450 };
35452 /* These are the values for vendor types and cpu types and subtypes
35453 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35454 the corresponding start value. */
35455 enum processor_model
35456 {
35458 M_AMD,
35459 M_CPU_TYPE_START,
35460 M_INTEL_BONNELL,
35461 M_INTEL_CORE2,
35462 M_INTEL_COREI7,
35463 M_AMDFAM10H,
35464 M_AMDFAM15H,
35465 M_INTEL_SILVERMONT,
35466 M_INTEL_KNL,
35467 M_AMD_BTVER1,
35468 M_AMD_BTVER2,
35469 M_CPU_SUBTYPE_START,
35470 M_INTEL_COREI7_NEHALEM,
35471 M_INTEL_COREI7_WESTMERE,
35472 M_INTEL_COREI7_SANDYBRIDGE,
35473 M_AMDFAM10H_BARCELONA,
35474 M_AMDFAM10H_SHANGHAI,
35475 M_AMDFAM10H_ISTANBUL,
35476 M_AMDFAM15H_BDVER1,
35477 M_AMDFAM15H_BDVER2,
35478 M_AMDFAM15H_BDVER3,
35479 M_AMDFAM15H_BDVER4,
35480 M_INTEL_COREI7_IVYBRIDGE,
35481 M_INTEL_COREI7_HASWELL,
35482 M_INTEL_COREI7_BROADWELL
35483 };
35485 static struct _arch_names_table
35486 {
35489 }
35491 {
35518 };
35520 static struct _isa_names_table
35521 {
35524 }
35526 {
35545 };
35559 {
35560 /* *args must be a expr that can contain other EXPRS leading to a
35561 STRING_CST. */
35563 {
35566 }
35568 }
35573 {
35574 tree ref;
35575 tree field;
35576 tree final;
35579 unsigned int NUM_ARCH_NAMES
35588 {
35592 }
35597 /* CPU types are stored in the next field. */
35600 {
35603 }
35605 /* CPU subtypes are stored in the next field. */
35607 {
35610 }
35612 /* Get the appropriate field in __cpu_model. */
35616 /* Check the value. */
35620 }
35622 {
35623 tree ref;
35624 tree array_elt;
35625 tree field;
35626 tree final;
35629 unsigned int NUM_ISA_NAMES
35638 {
35642 }
35645 /* Get the last field, which is __cpu_features. */
35649 /* Get the appropriate field: __cpu_model.__cpu_features */
35653 /* Access the 0th element of __cpu_features array. */
35658 /* Return __cpu_model.__cpu_features[0] & field_val */
35662 }
35664 }
35666 static tree
35669 {
35671 {
35676 {
35679 }
35680 }
35682 #ifdef SUBTARGET_FOLD_BUILTIN
35684 #endif
35687 }
35689 /* Make builtins to detect cpu type and features supported. NAME is
35690 the builtin name, CODE is the builtin code, and FTYPE is the function
35691 type of the builtin. */
35693 static void
35696 {
35697 tree decl;
35698 tree type;
35706 }
35708 /* Make builtins to get CPU type and features supported. The created
35709 builtins are :
35711 __builtin_cpu_init (), to detect cpu type and features,
35712 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35713 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35714 */
35716 static void
35718 {
35725 }
35727 /* Internal method for ix86_init_builtins. */
35729 static void
35731 {
35743 sysv_va_ref =
35746 fnvoid_va_end_ms =
35748 fnvoid_va_start_ms =
35750 fnvoid_va_end_sysv =
35752 fnvoid_va_start_sysv =
35754 NULL_TREE);
35755 fnvoid_va_copy_ms =
35757 NULL_TREE);
35758 fnvoid_va_copy_sysv =
35774 }
35776 static void
35778 {
35781 /* The __float80 type. */
35784 {
35785 /* The __float80 type. */
35790 }
35793 /* The __float128 type. */
35799 /* This macro is built by i386-builtin-types.awk. */
35800 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35801 }
35803 static void
35805 {
35806 tree t;
35810 /* Builtins to get CPU type and features. */
35813 /* TFmode support builtins. */
35819 /* We will expand them to normal call if SSE isn't available since
35820 they are used by libgcc. */
35840 #ifdef SUBTARGET_INIT_BUILTINS
35841 SUBTARGET_INIT_BUILTINS;
35842 #endif
35843 }
35845 /* Return the ix86 builtin for CODE. */
35847 static tree
35849 {
35854 }
35856 /* Errors in the source file can cause expand_expr to return const0_rtx
35857 where we expect a vector. To avoid crashing, use one of the vector
35858 clear instructions. */
35859 static rtx
35861 {
35865 }
35867 /* Fixup modeless constants to fit required mode. */
35868 static rtx
35870 {
35874 }
35876 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35878 static rtx
35880 {
35881 rtx pat;
35901 {
35905 }
35919 }
35921 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35923 static rtx
35927 {
35928 rtx pat;
35936 rtx op;
35937 machine_mode mode;
35943 {
36023 }
36033 {
36040 {
36042 {
36045 {
36063 xop_rotl:
36065 {
36068 gcc_checking_assert
36070 }
36071 else
36072 {
36073 gcc_checking_assert
36084 }
36088 }
36089 }
36090 }
36091 else
36092 {
36093 non_constant:
36097 /* If we aren't optimizing, only allow one memory operand to be
36098 generated. */
36100 num_memory++;
36108 }
36112 }
36115 {
36126 else
36127 {
36133 }
36146 }
36153 }
36155 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36156 insns with vec_merge. */
36158 static rtx
36160 rtx target)
36161 {
36162 rtx pat;
36189 }
36191 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36193 static rtx
36196 {
36197 rtx pat;
36202 rtx op2;
36213 /* Swap operands if we have a comparison that isn't available in
36214 hardware. */
36236 }
36238 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36240 static rtx
36242 rtx target)
36243 {
36244 rtx pat;
36258 /* Swap operands if we have a comparison that isn't available in
36259 hardware. */
36282 const0_rtx)));
36285 }
36287 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36289 static rtx
36291 rtx target)
36292 {
36293 rtx pat;
36318 }
36320 static rtx
36323 {
36324 rtx pat;
36329 rtx op2;
36356 }
36358 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36360 static rtx
36362 rtx target)
36363 {
36364 rtx pat;
36397 const0_rtx)));
36400 }
36402 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36404 static rtx
36407 {
36408 rtx pat;
36446 {
36449 }
36452 {
36461 }
36463 {
36472 }
36473 else
36474 {
36481 }
36489 {
36494 emit_insn
36498 FLAGS_REG),
36499 const0_rtx)));
36501 }
36502 else
36504 }
36507 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36509 static rtx
36512 {
36513 rtx pat;
36541 {
36544 }
36547 {
36556 }
36558 {
36567 }
36568 else
36569 {
36576 }
36584 {
36589 emit_insn
36593 FLAGS_REG),
36594 const0_rtx)));
36596 }
36597 else
36599 }
36601 /* Subroutine of ix86_expand_builtin to take care of insns with
36602 variable number of operands. */
36604 static rtx
36607 {
36613 struct
36614 {
36615 rtx op;
36616 machine_mode mode;
36627 {
37337 }
37342 {
37345 }
37348 {
37355 }
37356 else
37357 {
37360 }
37363 {
37370 {
37371 /* SIMD shift insns take either an 8-bit immediate or
37372 register as count. But builtin functions take int as
37373 count. If count doesn't match, we put it in register. */
37375 {
37379 }
37380 }
37383 {
37386 {
37495 {
37499 {
37502 }
37508 }
37510 }
37511 }
37512 else
37513 {
37517 /* If we aren't optimizing, only allow one memory operand to
37518 be generated. */
37520 num_memory++;
37525 {
37528 }
37529 else
37530 {
37533 }
37534 }
37538 }
37541 {
37566 }
37573 }
37575 /* Transform pattern of following layout:
37576 (parallel [
37577 set (A B)
37578 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37579 ])
37580 into:
37581 (set (A B))
37583 Or:
37584 (parallel [ A B
37585 ...
37586 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37587 ...
37588 ])
37589 into:
37590 (parallel [ A B ... ]) */
37592 static rtx
37594 {
37601 {
37610 }
37611 else
37612 {
37618 {
37623 }
37625 /* No more than 1 occurence was removed. */
37629 }
37630 }
37632 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37633 with rounding. */
37634 static rtx
37637 {
37654 /* See avxintrin.h for values. */
37656 {
37660 };
37662 {
37667 };
37670 {
37673 }
37675 {
37678 }
37681 {
37684 }
37707 ? CODE_FOR_sse_ucomi_round
37714 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37716 {
37722 }
37723 else
37724 {
37727 }
37733 set_dst,
37734 const0_rtx)));
37737 }
37739 static rtx
37742 {
37743 rtx pat;
37745 struct
37746 {
37747 rtx op;
37748 machine_mode mode;
37757 {
37840 }
37850 {
37857 {
37859 {
37861 {
37877 }
37878 }
37879 }
37881 {
37883 {
37886 }
37888 /* If there is no rounding use normal version of the pattern. */
37891 }
37892 else
37893 {
37900 {
37903 }
37904 else
37905 {
37908 }
37909 }
37913 }
37916 {
37941 }
37951 }
37953 /* Subroutine of ix86_expand_builtin to take care of special insns
37954 with variable number of operands. */
37956 static rtx
37959 {
37960 tree arg;
37964 struct
37965 {
37966 rtx op;
37967 machine_mode mode;
37976 {
38016 {
38024 }
38043 /* Reserve memory operand for target. */
38046 {
38047 /* These builtins and instructions require the memory
38048 to be properly aligned. */
38067 }
38096 {
38097 /* These builtins and instructions require the memory
38098 to be properly aligned. */
38115 }
38116 /* FALLTHRU */
38154 /* Reserve memory operand for target. */
38181 {
38182 /* These builtins and instructions require the memory
38183 to be properly aligned. */
38206 }
38219 }
38224 {
38229 {
38232 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38233 on it. Try to improve it using get_pointer_alignment,
38234 and if the special builtin is one that requires strict
38235 mode alignment, also from it's GET_MODE_ALIGNMENT.
38236 Failure to do so could lead to ix86_legitimate_combined_insn
38237 rejecting all changes to such insns. */
38243 }
38244 else
38247 }
38248 else
38249 {
38256 }
38259 {
38268 {
38270 {
38276 else
38279 }
38280 }
38281 else
38282 {
38284 {
38285 /* This must be the memory operand. */
38288 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38289 on it. Try to improve it using get_pointer_alignment,
38290 and if the special builtin is one that requires strict
38291 mode alignment, also from it's GET_MODE_ALIGNMENT.
38292 Failure to do so could lead to ix86_legitimate_combined_insn
38293 rejecting all changes to such insns. */
38299 }
38300 else
38301 {
38302 /* This must be register. */
38310 else
38311 {
38314 }
38315 }
38316 }
38320 }
38323 {
38338 }
38344 }
38346 /* Return the integer constant in ARG. Constrain it to be in the range
38347 of the subparts of VEC_TYPE; issue an error if not. */
38349 static int
38351 {
38356 {
38359 }
38362 }
38364 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38365 ix86_expand_vector_init. We DO have language-level syntax for this, in
38366 the form of (type){ init-list }. Except that since we can't place emms
38367 instructions from inside the compiler, we can't allow the use of MMX
38368 registers unless the user explicitly asks for it. So we do *not* define
38369 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38370 we have builtins invoked by mmintrin.h that gives us license to emit
38371 these sorts of instructions. */
38373 static rtx
38375 {
38385 {
38388 }
38395 }
38397 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38398 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38399 had a language-level syntax for referencing vector elements. */
38401 static rtx
38403 {
38407 rtx op0;
38427 }
38429 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38430 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38431 a language-level syntax for referencing vector elements. */
38433 static rtx
38435 {
38459 /* OP0 is the source of these builtin functions and shouldn't be
38460 modified. Create a copy, use it and return it as target. */
38466 }
38468 /* Emit conditional move of SRC to DST with condition
38469 OP1 CODE OP2. */
38470 static void
38472 {
38473 rtx t;
38476 {
38481 }
38482 else
38483 {
38489 }
38490 }
38492 /* Choose max of DST and SRC and put it to DST. */
38493 static void
38495 {
38497 }
38499 /* Expand an expression EXP that calls a built-in function,
38500 with result going to TARGET if that's convenient
38501 (and in mode MODE if that's convenient).
38502 SUBTARGET may be used as the target for computing one of EXP's operands.
38503 IGNORE is nonzero if the value is to be ignored. */
38505 static rtx
38508 {
38518 /* For CPU builtins that can be folded, fold first and expand the fold. */
38520 {
38522 {
38523 /* Make it call __cpu_indicator_init in libgcc. */
38529 }
38532 {
38537 }
38538 }
38540 /* Determine whether the builtin function is available under the current ISA.
38541 Originally the builtin was not created if it wasn't applicable to the
38542 current ISA based on the command line switches. With function specific
38543 options, we need to check in the context of the function making the call
38544 whether it is supported. */
38547 {
38553 else
38554 {
38558 }
38560 }
38563 {
38581 /* Builtin arg1 is size of block but instruction op1 should
38582 be (size - 1). */
38673 /* If no bounds were specified for returned value,
38674 then use INIT bounds. It usually happens when
38675 some built-in function is expanded. */
38677 {
38686 }
38692 {
38695 /* Return value and lb. */
38697 /* Bounds. */
38699 /* Size. */
38706 /* Size was passed but we need to use (size - 1) as for bndmk. */
38710 /* Add LB to size and inverse to get UB. */
38720 /* We need to move bounds to memory before any computations. */
38723 else
38724 {
38727 }
38729 /* Generate mem expression to be used for access to LB and UB. */
38735 /* Compute LB. */
38740 /* Compute UB. UB is stored in 1's complement form. Therefore
38741 we also use max here. */
38750 }
38753 {
38771 /* Put first bounds to temporaries. */
38775 {
38779 }
38780 else
38781 {
38785 }
38787 /* Put second bounds to temporaries. */
38791 {
38795 }
38796 else
38797 {
38801 }
38803 /* Compute LB. */
38807 /* Compute UB. UB is stored in 1's complement form. Therefore
38808 we also use max here. */
38815 }
38818 {
38819 tree name;
38820 rtx symbol;
38838 }
38841 {
38852 /* We need to move bounds to memory first. */
38855 else
38856 {
38859 }
38861 /* Generate mem expression to access LB and load it. */
38866 }
38869 {
38880 /* We need to move bounds to memory first. */
38883 else
38884 {
38887 }
38889 /* Generate mem expression to access UB. */
38892 /* We need to inverse all bits of UB. */
38899 }
38904 ? CODE_FOR_mmx_maskmovq
38906 /* Note the arg order is different from the operand order. */
39027 {
39028 REAL_VALUE_TYPE inf;
39029 rtx tmp;
39041 }
39051 {
39057 insn = (TARGET_64BIT
39061 }
39063 {
39064 insn = (TARGET_64BIT
39068 }
39069 else
39070 {
39073 insn = (TARGET_64BIT
39081 {
39084 }
39086 }
39089 {
39090 /* mode is VOIDmode if __builtin_rd* has been called
39091 without lhs. */
39095 }
39098 {
39103 }
39116 {
39137 }
39143 {
39146 }
39172 {
39175 }
39181 {
39185 {
39224 }
39229 }
39230 else
39231 {
39233 {
39254 }
39256 }
39286 ? CODE_FOR_tbm_bextri_si
39289 {
39292 }
39293 else
39294 {
39303 }
39319 rdrand_step:
39326 {
39329 }
39335 /* Emit SImode conditional move. */
39337 {
39340 }
39343 else
39351 const0_rtx);
39370 rdseed_step:
39377 {
39380 }
39386 const0_rtx);
39415 addcarryx:
39423 /* Generate CF from input operand. */
39428 /* Gen ADCX instruction to compute X+Y+CF. */
39443 /* Store the result. */
39446 {
39449 }
39452 /* Return current CF value. */
39494 kortest:
39508 /* Emit kortest. */
39510 /* And use setcc to return result from flags. */
39768 gather_gen:
39769 rtx half;
39782 /* Note the arg order is different from the operand order. */
39793 else
39797 {
39821 else
39828 {
39833 }
39842 else
39849 {
39854 }
39858 }
39860 /* Force memory operand only with base register here. But we
39861 don't want to do it on memory operand for other builtin
39862 functions. */
39875 {
39878 }
39879 else
39880 {
39883 }
39885 {
39888 }
39890 /* Optimize. If mask is known to have all high bits set,
39891 replace op0 with pc_rtx to signal that the instruction
39892 overwrites the whole destination and doesn't use its
39893 previous contents. */
39895 {
39897 {
39900 }
39902 {
39905 {
39909 negative++;
39912 negative++;
39913 }
39916 }
39919 {
39920 /* Recognize also when mask is like:
39921 __v2df src = _mm_setzero_pd ();
39922 __v2df mask = _mm_cmpeq_pd (src, src);
39923 or
39924 __v8sf src = _mm256_setzero_ps ();
39925 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39926 as that is a cheaper way to load all ones into
39927 a register than having to load a constant from
39928 memory. */
39931 {
39936 {
39943 /* FALLTHRU */
39953 }
39954 }
39955 }
39956 }
39964 {
39990 }
39993 scatter_gen:
40009 /* Force memory operand only with base register here. But we
40010 don't want to do it on memory operand for other builtin
40011 functions. */
40020 {
40023 }
40024 else
40025 {
40028 }
40037 {
40040 }
40049 vec_prefetch_gen:
40069 {
40072 }
40074 {
40077 }
40082 /* Force memory operand only with base register here. But we
40083 don't want to do it on memory operand for other builtin
40084 functions. */
40091 {
40094 }
40097 {
40100 }
40116 {
40119 }
40125 }
40138 {
40142 /* Emit a normal call if SSE isn't available. */
40146 }
40175 }
40177 /* This returns the target-specific builtin with code CODE if
40178 current_function_decl has visibility on this builtin, which is checked
40179 using isa flags. Returns NULL_TREE otherwise. */
40182 {
40186 /* Determine the isa flags of current_function_decl. */
40198 else
40200 }
40202 /* Return function decl for target specific builtin
40203 for given MPX builtin passed i FCODE. */
40204 static tree
40206 {
40208 {
40244 }
40247 }
40249 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40251 Return an address to be used to load/store bounds for pointer
40252 passed in SLOT.
40254 SLOT_NO is an integer constant holding number of a target
40255 dependent special slot to be used in case SLOT is not a memory.
40257 SPECIAL_BASE is a pointer to be used as a base of fake address
40258 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40259 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40261 static rtx
40263 {
40266 /* NULL slot means we pass bounds for pointer not passed to the
40267 function at all. Register slot means we pass pointer in a
40268 register. In both these cases bounds are passed via Bounds
40269 Table. Since we do not have actual pointer stored in memory,
40270 we have to use fake addresses to access Bounds Table. We
40271 start with (special_base - sizeof (void*)) and decrease this
40272 address by pointer size to get addresses for other slots. */
40274 {
40278 }
40279 /* If pointer is passed in a memory then its address is used to
40280 access Bounds Table. */
40282 {
40286 }
40287 else
40291 }
40293 /* Expand pass uses this hook to load bounds for function parameter
40294 PTR passed in SLOT in case its bounds are not passed in a register.
40296 If SLOT is a memory, then bounds are loaded as for regular pointer
40297 loaded from memory. PTR may be NULL in case SLOT is a memory.
40298 In such case value of PTR (if required) may be loaded from SLOT.
40300 If SLOT is NULL or a register then SLOT_NO is an integer constant
40301 holding number of the target dependent special slot which should be
40302 used to obtain bounds.
40304 Return loaded bounds. */
40306 static rtx
40308 {
40310 rtx addr;
40312 /* Get address to be used to access Bounds Table. Special slots start
40313 at the location of return address of the current function. */
40316 /* Load pointer value from a memory if we don't have it. */
40318 {
40321 }
40328 }
40330 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40331 passed in SLOT in case BOUNDS are not passed in a register.
40333 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40334 stored in memory. PTR may be NULL in case SLOT is a memory.
40335 In such case value of PTR (if required) may be loaded from SLOT.
40337 If SLOT is NULL or a register then SLOT_NO is an integer constant
40338 holding number of the target dependent special slot which should be
40339 used to store BOUNDS. */
40341 static void
40343 {
40344 rtx addr;
40346 /* Get address to be used to access Bounds Table. Special slots start
40347 at the location of return address of a called function. */
40350 /* Load pointer value from a memory if we don't have it. */
40352 {
40355 }
40364 }
40366 /* Load and return bounds returned by function in SLOT. */
40368 static rtx
40370 {
40371 rtx res;
40378 }
40380 /* Store BOUNDS returned by function into SLOT. */
40382 static void
40384 {
40387 }
40389 /* Returns a function decl for a vectorized version of the builtin function
40390 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40391 if it is not available. */
40393 static tree
40395 tree type_in)
40396 {
40412 {
40415 {
40422 }
40427 {
40430 }
40435 {
40442 }
40448 /* The round insn does not trap on denormals. */
40453 {
40460 }
40466 /* The round insn does not trap on denormals. */
40471 {
40476 }
40482 /* The round insn does not trap on denormals. */
40487 {
40494 }
40500 /* The round insn does not trap on denormals. */
40505 {
40510 }
40517 {
40522 }
40529 {
40534 }
40540 /* The round insn does not trap on denormals. */
40545 {
40552 }
40558 /* The round insn does not trap on denormals. */
40563 {
40568 }
40573 {
40580 }
40585 {
40592 }
40596 /* The round insn does not trap on denormals. */
40601 {
40606 }
40610 /* The round insn does not trap on denormals. */
40615 {
40620 }
40624 /* The round insn does not trap on denormals. */
40629 {
40634 }
40638 /* The round insn does not trap on denormals. */
40643 {
40648 }
40652 /* The round insn does not trap on denormals. */
40657 {
40662 }
40666 /* The round insn does not trap on denormals. */
40671 {
40676 }
40680 /* The round insn does not trap on denormals. */
40685 {
40690 }
40694 /* The round insn does not trap on denormals. */
40699 {
40704 }
40708 /* The round insn does not trap on denormals. */
40713 {
40718 }
40722 /* The round insn does not trap on denormals. */
40727 {
40732 }
40737 {
40742 }
40747 {
40752 }
40757 }
40759 /* Dispatch to a handler for a vectorization library. */
40762 type_in);
40765 }
40767 /* Handler for an SVML-style interface to
40768 a library with vectorized intrinsics. */
40770 static tree
40772 {
40780 /* The SVML is suitable for unsafe math only. */
40793 {
40840 }
40849 {
40852 }
40853 else
40856 /* Convert to uppercase. */
40861 args;
40863 arity++;
40867 else
40870 /* Build a function declaration for the vectorized function. */
40879 }
40881 /* Handler for an ACML-style interface to
40882 a library with vectorized intrinsics. */
40884 static tree
40886 {
40894 /* The ACML is 64bits only and suitable for unsafe math only as
40895 it does not correctly support parts of IEEE with the required
40896 precision such as denormals. */
40910 {
40940 }
40947 args;
40949 arity++;
40953 else
40956 /* Build a function declaration for the vectorized function. */
40965 }
40967 /* Returns a decl of a function that implements gather load with
40968 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40969 Return NULL_TREE if it is not available. */
40971 static tree
40974 {
40990 /* v*gather* insn sign extends index to pointer mode. */
41002 {
41006 else
41012 else
41018 else
41024 else
41030 else
41036 else
41042 else
41048 else
41054 else
41060 else
41066 else
41072 else
41077 }
41080 }
41082 /* Returns a code for a target-specific builtin that implements
41083 reciprocal of the function, or NULL_TREE if not available. */
41085 static tree
41087 {
41094 /* Machine dependent builtins. */
41096 {
41097 /* Vectorized version of sqrt to rsqrt conversion. */
41106 }
41107 else
41108 /* Normal builtins. */
41110 {
41111 /* Sqrt to rsqrt conversion. */
41117 }
41118 }
41119 \f
41120 /* Helper for avx_vpermilps256_operand et al. This is also used by
41121 the expansion functions to turn the parallel back into a mask.
41122 The return value is 0 for no match and the imm8+1 for a match. */
41124 int
41126 {
41134 /* Validate that all of the elements are constants, and not totally
41135 out of range. Copy the data into an integral array to make the
41136 subsequent checks easier. */
41138 {
41148 }
41151 {
41153 /* In the 512-bit DFmode case, we can only move elements within
41154 a 128-bit lane. First fill the second part of the mask,
41155 then fallthru. */
41157 {
41161 }
41163 {
41167 }
41168 /* FALLTHRU */
41171 /* In the 256-bit DFmode case, we can only move elements within
41172 a 128-bit lane. */
41174 {
41178 }
41180 {
41184 }
41188 /* In 512 bit SFmode case, permutation in the upper 256 bits
41189 must mirror the permutation in the lower 256-bits. */
41193 /* FALLTHRU */
41196 /* In 256 bit SFmode case, we have full freedom of
41197 movement within the low 128-bit lane, but the high 128-bit
41198 lane must mirror the exact same pattern. */
41203 /* FALLTHRU */
41207 /* In the 128-bit case, we've full freedom in the placement of
41208 the elements from the source operand. */
41215 }
41217 /* Make sure success has a non-zero value by adding one. */
41219 }
41221 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41222 the expansion functions to turn the parallel back into a mask.
41223 The return value is 0 for no match and the imm8+1 for a match. */
41225 int
41227 {
41235 /* Validate that all of the elements are constants, and not totally
41236 out of range. Copy the data into an integral array to make the
41237 subsequent checks easier. */
41239 {
41249 }
41251 /* Validate that the halves of the permute are halves. */
41259 /* Reconstruct the mask. */
41261 {
41267 }
41269 /* Make sure success has a non-zero value by adding one. */
41271 }
41272 \f
41273 /* Return a register priority for hard reg REGNO. */
41274 static int
41276 {
41277 /* ebp and r13 as the base always wants a displacement, r12 as the
41278 base always wants an index. So discourage their usage in an
41279 address. */
41284 /* New x86-64 int registers result in bigger code size. Discourage
41285 them. */
41288 /* New x86-64 SSE registers result in bigger code size. Discourage
41289 them. */
41292 /* Usage of AX register results in smaller code. Prefer it. */
41296 }
41298 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41300 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41301 QImode must go into class Q_REGS.
41302 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41303 movdf to do mem-to-mem moves through integer regs. */
41305 static reg_class_t
41307 {
41310 /* We're only allowed to return a subclass of CLASS. Many of the
41311 following checks fail for NO_REGS, so eliminate that early. */
41315 /* All classes can load zeros. */
41319 /* Force constants into memory if we are loading a (nonzero) constant into
41320 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41321 instructions to load from a constant. */
41328 /* Prefer SSE regs only, if we can use them for math. */
41332 /* Floating-point constants need more complex checks. */
41334 {
41335 /* General regs can load everything. */
41339 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41340 zero above. We only want to wind up preferring 80387 registers if
41341 we plan on doing computation with them. */
41344 {
41345 /* Limit class to non-sse. */
41354 }
41357 }
41359 /* Generally when we see PLUS here, it's the function invariant
41360 (plus soft-fp const_int). Which can only be computed into general
41361 regs. */
41365 /* QImode constants are easy to load, but non-constant QImode data
41366 must go into Q_REGS. */
41368 {
41374 }
41377 }
41379 /* Discourage putting floating-point values in SSE registers unless
41380 SSE math is being used, and likewise for the 387 registers. */
41381 static reg_class_t
41383 {
41386 /* Restrict the output reload class to the register bank that we are doing
41387 math on. If we would like not to return a subset of CLASS, reject this
41388 alternative: if reload cannot do this, it will still use its choice. */
41394 {
41399 else
41401 }
41404 }
41406 static reg_class_t
41409 {
41410 /* Double-word spills from general registers to non-offsettable memory
41411 references (zero-extended addresses) require special handling. */
41417 {
41419 ? CODE_FOR_reload_noff_load
41421 /* Add the cost of moving address to a temporary. */
41425 }
41427 /* QImode spills from non-QI registers require
41428 intermediate register on 32bit targets. */
41434 {
41439 else
41445 /* Return Q_REGS if the operand is in memory. */
41448 }
41450 /* This condition handles corner case where an expression involving
41451 pointers gets vectorized. We're trying to use the address of a
41452 stack slot as a vector initializer.
41454 (set (reg:V2DI 74 [ vect_cst_.2 ])
41455 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41457 Eventually frame gets turned into sp+offset like this:
41459 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41460 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41461 (const_int 392 [0x188]))))
41463 That later gets turned into:
41465 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41466 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41467 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41469 We'll have the following reload recorded:
41471 Reload 0: reload_in (DI) =
41472 (plus:DI (reg/f:DI 7 sp)
41473 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41474 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41475 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41476 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41477 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41478 reload_reg_rtx: (reg:V2DI 22 xmm1)
41480 Which isn't going to work since SSE instructions can't handle scalar
41481 additions. Returning GENERAL_REGS forces the addition into integer
41482 register and reload can handle subsequent reloads without problems. */
41490 }
41492 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41494 static bool
41496 {
41498 {
41514 }
41517 }
41519 /* If we are copying between general and FP registers, we need a memory
41520 location. The same is true for SSE and MMX registers.
41522 To optimize register_move_cost performance, allow inline variant.
41524 The macro can't work reliably when one of the CLASSES is class containing
41525 registers from multiple units (SSE, MMX, integer). We avoid this by never
41526 combining those units in single alternative in the machine description.
41527 Ensure that this constraint holds to avoid unexpected surprises.
41529 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41530 enforce these sanity checks. */
41535 {
41544 {
41547 }
41552 /* Between mask and general, we have moves no larger than word size. */
41557 /* ??? This is a lie. We do have moves between mmx/general, and for
41558 mmx/sse2. But by saying we need secondary memory we discourage the
41559 register allocator from using the mmx registers unless needed. */
41564 {
41565 /* SSE1 doesn't have any direct moves from other classes. */
41569 /* If the target says that inter-unit moves are more expensive
41570 than moving through memory, then don't generate them. */
41575 /* Between SSE and general, we have moves no larger than word size. */
41578 }
41581 }
41583 bool
41586 {
41588 }
41590 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41592 On the 80386, this is the size of MODE in words,
41593 except in the FP regs, where a single reg is always enough. */
41595 static unsigned char
41597 {
41599 {
41604 else
41606 }
41607 else
41608 {
41611 else
41613 }
41614 }
41616 /* Return true if the registers in CLASS cannot represent the change from
41617 modes FROM to TO. */
41619 bool
41622 {
41626 /* x87 registers can't do subreg at all, as all values are reformatted
41627 to extended precision. */
41632 {
41633 /* Vector registers do not support QI or HImode loads. If we don't
41634 disallow a change to these modes, reload will assume it's ok to
41635 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41636 the vec_dupv4hi pattern. */
41639 }
41642 }
41644 /* Return the cost of moving data of mode M between a
41645 register and memory. A value of 2 is the default; this cost is
41646 relative to those in `REGISTER_MOVE_COST'.
41648 This function is used extensively by register_move_cost that is used to
41649 build tables at startup. Make it inline in this case.
41650 When IN is 2, return maximum of in and out move cost.
41652 If moving between registers and memory is more expensive than
41653 between two registers, you should define this macro to express the
41654 relative cost.
41656 Model also increased moving costs of QImode registers in non
41657 Q_REGS classes.
41658 */
41662 {
41665 {
41668 {
41680 }
41684 }
41686 {
41689 {
41701 }
41705 }
41707 {
41710 {
41719 }
41723 }
41725 {
41728 {
41734 else
41739 }
41740 else
41741 {
41746 else
41748 }
41755 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41762 else
41766 }
41767 }
41769 static int
41772 {
41774 }
41777 /* Return the cost of moving data from a register in class CLASS1 to
41778 one in class CLASS2.
41780 It is not required that the cost always equal 2 when FROM is the same as TO;
41781 on some machines it is expensive to move between registers if they are not
41782 general registers. */
41784 static int
41786 reg_class_t class2_i)
41787 {
41791 /* In case we require secondary memory, compute cost of the store followed
41792 by load. In order to avoid bad register allocation choices, we need
41793 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41796 {
41802 /* In case of copying from general_purpose_register we may emit multiple
41803 stores followed by single load causing memory size mismatch stall.
41804 Count this as arbitrarily high cost of 20. */
41809 /* In the case of FP/MMX moves, the registers actually overlap, and we
41810 have to switch modes in order to treat them differently. */
41816 }
41818 /* Moves between SSE/MMX and integer unit are expensive. */
41822 /* ??? By keeping returned value relatively high, we limit the number
41823 of moves between integer and MMX/SSE registers for all targets.
41824 Additionally, high value prevents problem with x86_modes_tieable_p(),
41825 where integer modes in MMX/SSE registers are not tieable
41826 because of missing QImode and HImode moves to, from or between
41827 MMX/SSE registers. */
41837 }
41839 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41840 MODE. */
41842 bool
41844 {
41845 /* Flags and only flags can only hold CCmode values. */
41856 || (TARGET_AVX512BW
41861 {
41862 /* We implement the move patterns for all vector modes into and
41863 out of SSE registers, even when no operation instructions
41864 are available. */
41866 /* For AVX-512 we allow, regardless of regno:
41867 - XI mode
41868 - any of 512-bit wide vector mode
41869 - any scalar mode. */
41876 /* TODO check for QI/HI scalars. */
41877 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41885 /* xmm16-xmm31 are only available for AVX-512. */
41889 /* OImode and AVX modes are available only when AVX is enabled. */
41896 }
41898 {
41899 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41900 so if the register is available at all, then we can move data of
41901 the given mode into or out of it. */
41904 }
41907 {
41908 /* Take care for QImode values - they can be in non-QI regs,
41909 but then they do cause partial register stalls. */
41914 /* LRA checks if the hard register is OK for the given mode.
41915 QImode values can live in non-QI regs, so we allow all
41916 registers here. */
41920 }
41921 /* We handle both integer and floats in the general purpose registers. */
41928 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41929 on to use that value in smaller contexts, this can easily force a
41930 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41931 supporting DImode, allow it. */
41936 }
41938 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41939 tieable integer mode. */
41941 static bool
41943 {
41945 {
41958 }
41959 }
41961 /* Return true if MODE1 is accessible in a register that can hold MODE2
41962 without copying. That is, all register classes that can hold MODE2
41963 can also hold MODE1. */
41965 bool
41967 {
41975 /* MODE2 being XFmode implies fp stack or general regs, which means we
41976 can tie any smaller floating point modes to it. Note that we do not
41977 tie this with TFmode. */
41981 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41982 that we can tie it with SFmode. */
41986 /* If MODE2 is only appropriate for an SSE register, then tie with
41987 any other mode acceptable to SSE registers. */
41997 /* If MODE2 is appropriate for an MMX register, then tie
41998 with any other mode acceptable to MMX registers. */
42005 }
42007 /* Return the cost of moving between two registers of mode MODE. */
42009 static int
42011 {
42015 {
42047 }
42049 /* Return the cost of moving between two registers of mode MODE,
42050 assuming that the move will be in pieces of at most UNITS bytes. */
42052 }
42054 /* Compute a (partial) cost for rtx X. Return true if the complete
42055 cost has been computed, and false if subexpressions should be
42056 scanned. In either case, *TOTAL contains the cost result. */
42058 static bool
42061 {
42062 rtx mask;
42069 {
42073 {
42076 }
42088 && !(TARGET_64BIT
42093 else
42099 {
42102 }
42104 {
42114 }
42116 {
42119 {
42128 }
42129 }
42130 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42131 it'll probably end up. Add a penalty for size. */
42138 /* The zero extensions is often completely free on x86_64, so make
42139 it as cheap as possible. */
42145 else
42157 {
42160 {
42163 }
42166 {
42169 }
42170 }
42171 /* FALLTHRU */
42178 {
42179 /* ??? Should be SSE vector operation cost. */
42180 /* At least for published AMD latencies, this really is the same
42181 as the latency for a simple fpu operation like fabs. */
42182 /* V*QImode is emulated with 1-11 insns. */
42184 {
42187 {
42188 /* For XOP we use vpshab, which requires a broadcast of the
42189 value to the variable shift insn. For constants this
42190 means a V16Q const in mem; even when we can perform the
42191 shift with one insn set the cost to prefer paddb. */
42193 {
42198 }
42200 }
42204 }
42205 else
42207 }
42209 {
42211 {
42214 else
42216 }
42217 else
42218 {
42221 else
42223 }
42224 }
42225 else
42226 {
42231 {
42232 /* Return the cost after shift-and truncation. */
42235 }
42236 else
42238 }
42242 {
42243 rtx sub;
42248 /* ??? SSE scalar/vector cost should be used here. */
42249 /* ??? Bald assumption that fma has the same cost as fmul. */
42253 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42264 }
42268 {
42269 /* ??? SSE scalar cost should be used here. */
42272 }
42274 {
42277 }
42279 {
42280 /* ??? SSE vector cost should be used here. */
42283 }
42285 {
42286 /* V*QImode is emulated with 7-13 insns. */
42288 {
42295 }
42296 /* V*DImode is emulated with 5-8 insns. */
42298 {
42301 else
42303 }
42304 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42305 insns, including two PMULUDQ. */
42308 else
42311 }
42312 else
42313 {
42318 {
42321 nbits++;
42322 }
42323 else
42324 /* This is arbitrary. */
42327 /* Compute costs correctly for widening multiplication. */
42331 {
42338 {
42342 else
42344 }
42348 }
42356 }
42363 /* ??? SSE cost should be used here. */
42368 /* ??? SSE vector cost should be used here. */
42370 else
42377 {
42382 {
42385 {
42393 }
42394 }
42397 {
42400 {
42406 }
42407 }
42409 {
42417 }
42418 }
42419 /* FALLTHRU */
42423 {
42424 /* ??? SSE cost should be used here. */
42427 }
42429 {
42432 }
42434 {
42435 /* ??? SSE vector cost should be used here. */
42438 }
42439 /* FALLTHRU */
42446 {
42453 }
42454 /* FALLTHRU */
42458 {
42459 /* ??? SSE cost should be used here. */
42462 }
42464 {
42467 }
42469 {
42470 /* ??? SSE vector cost should be used here. */
42473 }
42474 /* FALLTHRU */
42478 {
42479 /* ??? Should be SSE vector operation cost. */
42480 /* At least for published AMD latencies, this really is the same
42481 as the latency for a simple fpu operation like fabs. */
42483 }
42486 else
42495 {
42496 /* This kind of construct is implemented using test[bwl].
42497 Treat it as if we had an AND. */
42502 }
42512 /* ??? SSE cost should be used here. */
42517 /* ??? SSE vector cost should be used here. */
42523 /* ??? SSE cost should be used here. */
42528 /* ??? SSE vector cost should be used here. */
42540 /* ??? Assume all of these vector manipulation patterns are
42541 recognizable. In which case they all pretty much have the
42542 same cost. */
42547 /* This is masked instruction, assume the same cost,
42548 as nonmasked variant. */
42551 else
42557 }
42558 }
42560 #if TARGET_MACHO
42564 /* Given a symbol name and its associated stub, write out the
42565 definition of the stub. */
42567 void
42569 {
42574 /* For 64-bit we shouldn't get here. */
42577 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42594 else
42601 {
42603 }
42605 {
42606 /* PIC stub. */
42607 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42613 }
42614 else
42617 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42618 it needs no stub-binding-helper. */
42625 {
42628 }
42629 else
42634 /* N.B. Keep the correspondence of these
42635 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42636 old-pic/new-pic/non-pic stubs; altering this will break
42637 compatibility with existing dylibs. */
42639 {
42640 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42642 }
42643 else
42644 /* 16-byte -mdynamic-no-pic stub. */
42650 }
42653 /* Order the registers for register allocator. */
42655 void
42657 {
42661 /* First allocate the local general purpose registers. */
42666 /* Global general purpose registers. */
42671 /* x87 registers come first in case we are doing FP math
42672 using them. */
42677 /* SSE registers. */
42683 /* Extended REX SSE registers. */
42687 /* Mask register. */
42691 /* MPX bound registers. */
42695 /* x87 registers. */
42703 /* Initialize the rest of array as we do not allocate some registers
42704 at all. */
42707 }
42709 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42710 in struct attribute_spec handler. */
42711 static tree
42713 tree args,
42716 {
42721 {
42723 name);
42726 }
42728 {
42730 name);
42733 }
42735 {
42736 tree cst;
42740 {
42743 name);
42745 }
42748 {
42751 name);
42753 }
42756 }
42759 }
42761 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42762 struct attribute_spec.handler. */
42763 static tree
42766 {
42771 {
42773 name);
42776 }
42778 /* Can combine regparm with all attributes but fastcall. */
42780 {
42782 {
42784 }
42787 }
42789 {
42791 {
42793 }
42796 }
42799 }
42801 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42802 struct attribute_spec.handler. */
42803 static tree
42806 {
42809 {
42812 }
42813 else
42817 {
42819 name);
42821 }
42827 {
42829 name);
42831 }
42834 }
42836 static tree
42839 {
42841 {
42843 name);
42845 }
42847 }
42849 static bool
42851 {
42855 }
42857 /* Returns an expression indicating where the this parameter is
42858 located on entry to the FUNCTION. */
42860 static rtx
42862 {
42868 {
42873 else
42876 }
42881 {
42888 {
42893 }
42894 else
42895 {
42898 {
42904 }
42905 }
42907 }
42911 }
42913 /* Determine whether x86_output_mi_thunk can succeed. */
42915 static bool
42917 const_tree function)
42918 {
42919 /* 64-bit can handle anything. */
42923 /* For 32-bit, everything's fine if we have one free register. */
42927 /* Need a free register for vcall_offset. */
42931 /* Need a free register for GOT references. */
42935 /* Otherwise ok. */
42937 }
42939 /* Output the assembler code for a thunk function. THUNK_DECL is the
42940 declaration for the thunk function itself, FUNCTION is the decl for
42941 the target function. DELTA is an immediate constant offset to be
42942 added to THIS. If VCALL_OFFSET is nonzero, the word at
42943 *(*this + vcall_offset) should be added to THIS. */
42945 static void
42948 {
42956 else
42957 {
42963 else
42965 }
42969 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42970 pull it in now and let DELTA benefit. */
42974 {
42975 /* Put the this parameter into %eax. */
42978 }
42979 else
42982 /* Adjust the this parameter by a fixed constant. */
42984 {
42989 {
42991 {
42995 }
42996 }
42999 }
43001 /* Adjust the this parameter by a value stored in the vtable. */
43003 {
43013 /* Adjust the this parameter. */
43017 {
43021 }
43028 vcall_mem));
43029 else
43031 }
43033 /* If necessary, drop THIS back to its stack slot. */
43039 {
43042 ;
43043 else
43044 {
43048 }
43049 }
43050 else
43051 {
43053 ;
43054 #if TARGET_MACHO
43056 {
43059 }
43061 else
43062 {
43070 }
43071 }
43073 /* Our sibling call patterns do not allow memories, because we have no
43074 predicate that can distinguish between frame and non-frame memory.
43075 For our purposes here, we can get away with (ab)using a jump pattern,
43076 because we're going to do no optimization. */
43078 {
43080 {
43086 }
43087 else
43089 }
43090 else
43091 {
43093 {
43094 // CM_LARGE_PIC always uses pseudo PIC register which is
43095 // uninitialized. Since FUNCTION is local and calling it
43096 // doesn't go through PLT, we use scratch register %r11 as
43097 // PIC register and initialize it here.
43102 }
43105 {
43111 }
43117 }
43120 /* Emit just enough of rest_of_compilation to get the insns emitted.
43121 Note that use_thunk calls assemble_start_function et al. */
43127 }
43129 static void
43131 {
43135 #if TARGET_MACHO
43137 #endif
43144 }
43146 int
43148 {
43149 machine_mode mode;
43160 }
43162 /* Print call to TARGET to FILE. */
43164 static void
43166 {
43169 else
43171 }
43173 /* Output assembler code to FILE to increment profiler label # LABELNO
43174 for profiling a function entry. */
43175 void
43177 {
43181 {
43182 #ifndef NO_PROFILE_COUNTERS
43184 #endif
43188 else
43190 }
43192 {
43193 #ifndef NO_PROFILE_COUNTERS
43196 #endif
43198 }
43199 else
43200 {
43201 #ifndef NO_PROFILE_COUNTERS
43204 #endif
43206 }
43209 {
43213 }
43214 }
43216 /* We don't have exact information about the insn sizes, but we may assume
43217 quite safely that we are informed about all 1 byte insns and memory
43218 address sizes. This is enough to eliminate unnecessary padding in
43219 99% of cases. */
43221 static int
43223 {
43229 /* Discard alignments we've emit and jump instructions. */
43234 /* Important case - calls are always 5 bytes.
43235 It is common to have many calls in the row. */
43244 /* For normal instructions we rely on get_attr_length being exact,
43245 with a few exceptions. */
43247 {
43251 {
43261 /* Otherwise trust get_attr_length. */
43263 }
43268 }
43271 else
43273 }
43275 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43277 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43278 window. */
43280 static void
43282 {
43287 /* Look for all minimal intervals of instructions containing 4 jumps.
43288 The intervals are bounded by START and INSN. NBYTES is the total
43289 size of instructions in the interval including INSN and not including
43290 START. When the NBYTES is smaller than 16 bytes, it is possible
43291 that the end of START and INSN ends up in the same 16byte page.
43293 The smallest offset in the page INSN can start is the case where START
43294 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43295 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43297 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43298 have to, control transfer to label(s) can be performed through other
43299 means, and also we estimate minimum length of all asm stmts as 0. */
43301 {
43305 {
43311 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43312 already in the current 16 byte page, because otherwise
43313 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43314 bytes to reach 16 byte boundary. */
43322 {
43324 {
43329 else
43332 }
43333 }
43335 }
43344 njumps++;
43345 else
43349 {
43354 else
43357 }
43364 {
43371 }
43372 }
43373 }
43374 #endif
43376 /* AMD Athlon works faster
43377 when RET is not destination of conditional jump or directly preceded
43378 by other jump instruction. We avoid the penalty by inserting NOP just
43379 before the RET instructions in such cases. */
43380 static void
43382 {
43383 edge e;
43384 edge_iterator ei;
43387 {
43400 {
43401 edge e;
43402 edge_iterator ei;
43407 {
43410 }
43411 }
43413 {
43419 /* Empty functions get branch mispredict even when
43420 the jump destination is not visible to us. */
43423 }
43425 {
43428 }
43429 }
43430 }
43432 /* Count the minimum number of instructions in BB. Return 4 if the
43433 number of instructions >= 4. */
43435 static int
43437 {
43441 /* Count number of instructions in this block. Return 4 if the number
43442 of instructions >= 4. */
43444 {
43445 /* Only happen in exit blocks. */
43453 {
43454 insn_count++;
43457 }
43458 }
43461 }
43464 /* Count the minimum number of instructions in code path in BB.
43465 Return 4 if the number of instructions >= 4. */
43467 static int
43469 {
43470 edge e;
43471 edge_iterator ei;
43474 /* Only bother counting instructions along paths with no
43475 more than 2 basic blocks between entry and exit. Given
43476 that BB has an edge to exit, determine if a predecessor
43477 of BB has an edge from entry. If so, compute the number
43478 of instructions in the predecessor block. If there
43479 happen to be multiple such blocks, compute the minimum. */
43482 {
43483 edge prev_e;
43484 edge_iterator prev_ei;
43487 {
43490 }
43492 {
43494 {
43499 }
43500 }
43501 }
43507 }
43509 /* Pad short function to 4 instructions. */
43511 static void
43513 {
43514 edge e;
43515 edge_iterator ei;
43518 {
43521 {
43524 /* Pad short function. */
43526 {
43529 /* Find epilogue. */
43538 /* Two NOPs count as one instruction. */
43541 }
43542 }
43543 }
43544 }
43546 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43547 the epilogue, the Windows system unwinder will apply epilogue logic and
43548 produce incorrect offsets. This can be avoided by adding a nop between
43549 the last insn that can throw and the first insn of the epilogue. */
43551 static void
43553 {
43554 edge e;
43555 edge_iterator ei;
43558 {
43561 /* Find the beginning of the epilogue. */
43568 /* We only care about preceding insns that can throw. */
43573 /* Do not separate calls from their debug information. */
43579 else
43583 }
43584 }
43586 /* Implement machine specific optimizations. We implement padding of returns
43587 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43588 static void
43590 {
43591 /* We are freeing block_for_insn in the toplev to keep compatibility
43592 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43599 {
43604 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43607 #endif
43608 }
43609 }
43611 /* Return nonzero when QImode register that must be represented via REX prefix
43612 is used. */
43613 bool
43615 {
43623 }
43625 /* Return true when INSN mentions register that must be encoded using REX
43626 prefix. */
43627 bool
43629 {
43632 {
43637 }
43639 }
43641 /* If profitable, negate (without causing overflow) integer constant
43642 of mode MODE at location LOC. Return true in this case. */
43643 bool
43645 {
43646 HOST_WIDE_INT val;
43652 {
43654 /* DImode x86_64 constants must fit in 32 bits. */
43667 }
43669 /* Avoid overflows. */
43675 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43676 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43679 {
43682 }
43685 }
43687 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43688 optabs would emit if we didn't have TFmode patterns. */
43690 void
43692 {
43727 }
43728 \f
43734 /* Get a vector mode of the same size as the original but with elements
43735 twice as wide. This is only guaranteed to apply to integral vectors. */
43739 {
43740 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43745 }
43747 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43748 fill target with val via vec_duplicate. */
43750 static bool
43752 {
43755 rtx dup;
43757 /* First attempt to recognize VAL as-is. */
43761 {
43763 /* If that fails, force VAL into a register. */
43774 }
43776 }
43778 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43779 with all elements equal to VAR. Return true if successful. */
43781 static bool
43784 {
43788 {
43793 /* FALLTHRU */
43813 {
43814 rtx x;
43821 }
43834 {
43838 permute:
43846 /* Extend to SImode using a paradoxical SUBREG. */
43850 /* Insert the SImode value as low element of a V4SImode vector. */
43859 }
43870 widen:
43871 /* Replicate the value once into the next wider mode and recurse. */
43872 {
43874 rtx x;
43891 }
43897 else
43898 {
43907 }
43914 else
43915 {
43924 }
43929 }
43930 }
43932 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43933 whose ONE_VAR element is VAR, and other elements are zero. Return true
43934 if successful. */
43936 static bool
43939 {
43940 machine_mode vsimode;
43941 rtx new_target;
43946 {
43948 /* For SSE4.1, we normally use vector set. But if the second
43949 element is zero and inter-unit moves are OK, we use movq
43950 instead. */
43952 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43974 /* Use ix86_expand_vector_set in 64bit mode only. */
43979 }
43982 {
43987 }
43990 {
43995 /* FALLTHRU */
44010 else
44017 {
44018 /* We need to shuffle the value to the correct position, so
44019 create a new pseudo to store the intermediate result. */
44021 /* With SSE2, we can use the integer shuffle insns. */
44023 {
44025 const1_rtx,
44032 }
44034 /* Otherwise convert the intermediate result to V4SFmode and
44035 use the SSE1 shuffle instructions. */
44037 {
44040 }
44041 else
44045 const1_rtx,
44054 }
44069 widen:
44073 /* Zero extend the variable element to SImode and recurse. */
44086 }
44087 }
44089 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44090 consisting of the values in VALS. It is known that all elements
44091 except ONE_VAR are constants. Return true if successful. */
44093 static bool
44096 {
44098 machine_mode wmode;
44106 {
44111 /* For the two element vectors, it's just as easy to use
44112 the general case. */
44116 /* Use ix86_expand_vector_set in 64bit mode only. */
44138 widen:
44139 /* There's no way to set one QImode entry easily. Combine
44140 the variable value with its adjacent constant value, and
44141 promote to an HImode set. */
44144 {
44149 }
44150 else
44151 {
44154 }
44168 }
44173 }
44175 /* A subroutine of ix86_expand_vector_init_general. Use vector
44176 concatenate to handle the most general case: all values variable,
44177 and none identical. */
44179 static void
44182 {
44185 rtvec v;
44189 {
44192 {
44237 }
44250 {
44265 }
44270 {
44289 }
44294 {
44307 }
44310 half:
44311 /* FIXME: We process inputs backward to help RA. PR 36222. */
44315 {
44320 }
44324 {
44328 {
44332 }
44335 {
44339 }
44342 }
44344 {
44347 {
44351 }
44354 }
44355 else
44361 }
44362 }
44364 /* A subroutine of ix86_expand_vector_init_general. Use vector
44365 interleave to handle the most general case: all values variable,
44366 and none identical. */
44368 static void
44371 {
44380 {
44401 }
44404 {
44405 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44409 /* Insert the SImode value as low element of V4SImode vector. */
44413 op0),
44415 const1_rtx);
44418 /* Cast the V4SImode vector back to a vector in orignal mode. */
44422 /* Load even elements into the second position. */
44426 const1_rtx));
44428 /* Cast vector to FIRST_IMODE vector. */
44431 }
44433 /* Interleave low FIRST_IMODE vectors. */
44435 {
44439 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44442 }
44444 /* Interleave low SECOND_IMODE vectors. */
44446 {
44449 {
44454 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44455 vector. */
44458 }
44461 /* FALLTHRU */
44468 /* Cast the SECOND_IMODE vector back to a vector on original
44469 mode. */
44476 }
44477 }
44479 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44480 all values variable, and none identical. */
44482 static void
44485 {
44492 {
44497 /* FALLTHRU */
44525 half:
44549 quarter:
44578 /* FALLTHRU */
44584 /* Don't use ix86_expand_vector_init_interleave if we can't
44585 move from GPR to SSE register directly. */
44601 }
44603 {
44605 machine_mode inner_mode;
44615 {
44619 {
44625 else
44626 {
44631 }
44632 }
44635 }
44640 {
44646 }
44648 {
44654 }
44655 else
44657 }
44658 }
44660 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44661 instructions unless MMX_OK is true. */
44663 void
44665 {
44672 rtx x;
44675 {
44685 }
44687 /* Constants are best loaded from the constant pool. */
44689 {
44692 }
44694 /* If all values are identical, broadcast the value. */
44700 /* Values where only one field is non-constant are best loaded from
44701 the pool and overwritten via move later. */
44703 {
44707 one_var))
44712 }
44715 }
44717 void
44719 {
44722 machine_mode half_mode;
44724 rtx tmp;
44726 = {
44733 };
44735 = {
44742 };
44746 {
44750 {
44755 else
44759 }
44771 else
44777 {
44780 /* For the two element vectors, we implement a VEC_CONCAT with
44781 the extraction of the other element. */
44788 else
44793 }
44802 {
44808 /* tmp = target = A B C D */
44810 /* target = A A B B */
44812 /* target = X A B B */
44814 /* target = A X C D */
44821 /* tmp = target = A B C D */
44823 /* tmp = X B C D */
44825 /* target = A B X D */
44832 /* tmp = target = A B C D */
44834 /* tmp = X B C D */
44836 /* target = A B X D */
44844 }
44852 /* Element 0 handled by vec_merge below. */
44854 {
44857 }
44860 {
44861 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44862 store into element 0, then shuffle them back. */
44879 }
44880 else
44881 {
44882 /* For SSE1, we have to reuse the V4SF code. */
44886 }
44939 half:
44940 /* Compute offset. */
44946 /* Extract the half. */
44950 /* Put val in tmp at elt. */
44953 /* Put it back. */
44959 {
44966 }
44967 else
44971 {
44978 }
44979 else
44983 {
44990 }
44991 else
44995 {
45002 }
45003 else
45007 {
45014 }
45015 else
45019 {
45026 }
45027 else
45032 }
45035 {
45039 }
45040 else
45041 {
45050 }
45051 }
45053 void
45055 {
45059 rtx tmp;
45062 {
45067 /* FALLTHRU */
45080 {
45100 }
45112 {
45114 {
45134 }
45138 }
45139 else
45140 {
45141 /* For SSE1, we have to reuse the V4SF code. */
45145 }
45161 {
45165 else
45169 }
45174 {
45178 else
45182 }
45187 {
45191 else
45195 }
45200 {
45204 else
45208 }
45213 {
45217 else
45221 }
45226 {
45230 else
45234 }
45239 {
45243 else
45247 }
45252 {
45256 else
45260 }
45267 else
45276 else
45285 else
45294 else
45300 /* ??? Could extract the appropriate HImode element and shift. */
45303 }
45306 {
45310 /* Let the rtl optimizers know about the zero extension performed. */
45312 {
45315 }
45318 }
45319 else
45320 {
45327 }
45328 }
45330 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45331 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45332 The upper bits of DEST are undefined, though they shouldn't cause
45333 exceptions (some bits from src or all zeros are ok). */
45335 static void
45337 {
45340 {
45344 else
45362 else
45369 else
45377 {
45382 const1_rtx);
45383 }
45384 else
45385 {
45389 }
45411 else
45433 }
45437 }
45439 /* Expand a vector reduction. FN is the binary pattern to reduce;
45440 DEST is the destination; IN is the input vector. */
45442 void
45444 {
45449 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45453 {
45456 }
45461 {
45466 else
45470 }
45471 }
45472 \f
45473 /* Target hook for scalar_mode_supported_p. */
45474 static bool
45476 {
45481 else
45483 }
45485 /* Implements target hook vector_mode_supported_p. */
45486 static bool
45488 {
45502 }
45504 /* Implement target hook libgcc_floating_mode_supported_p. */
45505 static bool
45507 {
45509 {
45516 #ifdef IX86_NO_LIBGCC_TFMODE
45518 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45520 #else
45522 #endif
45526 }
45527 }
45529 /* Target hook for c_mode_for_suffix. */
45530 static machine_mode
45532 {
45539 }
45541 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45543 We do this in the new i386 backend to maintain source compatibility
45544 with the old cc0-based compiler. */
45546 static tree
45548 {
45550 clobbers);
45552 clobbers);
45554 }
45556 /* Implements target vector targetm.asm.encode_section_info. */
45558 static void ATTRIBUTE_UNUSED
45560 {
45565 }
45567 /* Worker function for REVERSE_CONDITION. */
45569 enum rtx_code
45571 {
45575 }
45577 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45578 to OPERANDS[0]. */
45582 {
45584 {
45587 {
45591 }
45595 }
45597 {
45601 else
45602 {
45603 /* There is no non-popping store to memory for XFmode.
45604 So if we need one, follow the store with a load. */
45607 else
45609 }
45610 }
45611 else
45613 }
45615 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45616 FP status register is set. */
45618 void
45620 {
45622 rtx temp;
45627 {
45632 }
45633 else
45634 {
45639 }
45643 pc_rtx);
45648 }
45650 /* Output code to perform a log1p XFmode calculation. */
45653 {
45659 rtx test;
45665 XFmode));
45679 }
45681 /* Emit code for round calculation. */
45683 {
45690 rtx insn;
45695 {
45707 }
45710 {
45731 }
45739 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45741 /* scratch = fxam(op1) */
45744 UNSPEC_FXAM)));
45745 /* e1 = fabs(op1) */
45748 /* e2 = e1 + 0.5 */
45753 /* res = floor(e2) */
45755 {
45760 }
45761 else
45765 {
45768 {
45775 UNSPEC_TRUNC_NOOP)));
45776 }
45792 }
45794 /* flags = signbit(a) */
45797 /* if (flags) then res = -res */
45801 pc_rtx);
45812 }
45814 /* Output code to perform a Newton-Rhapson approximation of a single precision
45815 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45818 {
45826 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45830 /* x0 = rcp(b) estimate */
45834 UNSPEC_RCP14)));
45835 else
45838 UNSPEC_RCP)));
45840 /* e0 = x0 * b */
45844 /* e0 = x0 * e0 */
45848 /* e1 = x0 + x0 */
45852 /* x1 = e1 - e0 */
45856 /* res = a * x1 */
45859 }
45861 /* Output code to perform a Newton-Rhapson approximation of a
45862 single precision floating point [reciprocal] square root. */
45866 {
45868 REAL_VALUE_TYPE r;
45885 {
45888 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45891 }
45893 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45894 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45898 /* x0 = rsqrt(a) estimate */
45901 unspec)));
45903 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45905 {
45913 /* Handle masked compare. */
45915 {
45917 /* Imm value 0x4 corresponds to not-equal comparison. */
45920 }
45921 else
45922 {
45928 }
45929 }
45931 /* e0 = x0 * a */
45934 /* e1 = e0 * x0 */
45938 /* e2 = e1 - 3. */
45945 /* e3 = -.5 * x0 */
45948 else
45949 /* e3 = -.5 * e0 */
45952 /* ret = e2 * e3 */
45955 }
45957 #ifdef TARGET_SOLARIS
45958 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45960 static void
45962 tree decl)
45963 {
45964 /* With Binutils 2.15, the "@unwind" marker must be specified on
45965 every occurrence of the ".eh_frame" section, not just the first
45966 one. */
45969 {
45973 }
45975 #ifndef USE_GAS
45977 {
45980 }
45981 #endif
45984 }
45987 /* Return the mangling of TYPE if it is an extended fundamental type. */
45991 {
45999 {
46001 /* __float128 is "g". */
46004 /* "long double" or __float80 is "e". */
46008 }
46009 }
46011 /* For 32-bit code we can save PIC register setup by using
46012 __stack_chk_fail_local hidden function instead of calling
46013 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46014 register, so it is better to call __stack_chk_fail directly. */
46016 static tree ATTRIBUTE_UNUSED
46018 {
46019 return TARGET_64BIT
46022 }
46024 /* Select a format to encode pointers in exception handling data. CODE
46025 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46026 true if the symbol may be affected by dynamic relocations.
46028 ??? All x86 object file formats are capable of representing this.
46029 After all, the relocation needed is the same as for the call insn.
46030 Whether or not a particular assembler allows us to enter such, I
46031 guess we'll have to see. */
46032 int
46034 {
46036 {
46043 }
46048 }
46049 \f
46050 /* Expand copysign from SIGN to the positive value ABS_VALUE
46051 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46052 the sign-bit. */
46053 static void
46055 {
46059 {
46060 machine_mode vmode;
46066 else
46071 {
46072 /* We need to generate a scalar mode mask in this case. */
46077 }
46078 }
46079 else
46085 }
46087 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46088 mask for masking out the sign-bit is stored in *SMASK, if that is
46089 non-null. */
46090 static rtx
46092 {
46101 else
46105 {
46106 /* We need to generate a scalar mode mask in this case. */
46111 }
46119 }
46121 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46122 swapping the operands if SWAP_OPERANDS is true. The expanded
46123 code is a forward jump to a newly created label in case the
46124 comparison is true. The generated label rtx is returned. */
46128 {
46131 rtx tmp;
46147 }
46149 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46150 using comparison code CODE. Operands are swapped for the comparison if
46151 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46152 static rtx
46155 {
46168 }
46170 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46171 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46172 static rtx
46174 {
46175 REAL_VALUE_TYPE TWO52r;
46176 rtx TWO52;
46183 }
46185 /* Expand SSE sequence for computing lround from OP1 storing
46186 into OP0. */
46187 void
46189 {
46190 /* C code for the stuff we're doing below:
46191 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46192 return (long)tmp;
46193 */
46197 rtx adj;
46199 /* load nextafter (0.5, 0.0) */
46204 /* adj = copysign (0.5, op1) */
46208 /* adj = op1 + adj */
46211 /* op0 = (imode)adj */
46213 }
46215 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46216 into OPERAND0. */
46217 void
46219 {
46220 /* C code for the stuff we're doing below (for do_floor):
46221 xi = (long)op1;
46222 xi -= (double)xi > op1 ? 1 : 0;
46223 return xi;
46224 */
46230 /* reg = (long)op1 */
46234 /* freg = (double)reg */
46238 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46249 }
46251 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46252 result in OPERAND0. */
46253 void
46255 {
46256 /* C code for the stuff we're doing below:
46257 xa = fabs (operand1);
46258 if (!isless (xa, 2**52))
46259 return operand1;
46260 xa = xa + 2**52 - 2**52;
46261 return copysign (xa, operand1);
46262 */
46270 /* xa = abs (operand1) */
46273 /* if (!isless (xa, TWO52)) goto label; */
46286 }
46288 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46289 into OPERAND0. */
46290 void
46292 {
46293 /* C code for the stuff we expand below.
46294 double xa = fabs (x), x2;
46295 if (!isless (xa, TWO52))
46296 return x;
46297 xa = xa + TWO52 - TWO52;
46298 x2 = copysign (xa, x);
46299 Compensate. Floor:
46300 if (x2 > x)
46301 x2 -= 1;
46302 Compensate. Ceil:
46303 if (x2 < x)
46304 x2 -= -1;
46305 return x2;
46306 */
46313 /* Temporary for holding the result, initialized to the input
46314 operand to ease control flow. */
46318 /* xa = abs (operand1) */
46321 /* if (!isless (xa, TWO52)) goto label; */
46324 /* xa = xa + TWO52 - TWO52; */
46328 /* xa = copysign (xa, operand1) */
46331 /* generate 1.0 or -1.0 */
46336 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46340 /* We always need to subtract here to preserve signed zero. */
46349 }
46351 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46352 into OPERAND0. */
46353 void
46355 {
46356 /* C code for the stuff we expand below.
46357 double xa = fabs (x), x2;
46358 if (!isless (xa, TWO52))
46359 return x;
46360 x2 = (double)(long)x;
46361 Compensate. Floor:
46362 if (x2 > x)
46363 x2 -= 1;
46364 Compensate. Ceil:
46365 if (x2 < x)
46366 x2 += 1;
46367 if (HONOR_SIGNED_ZEROS (mode))
46368 return copysign (x2, x);
46369 return x2;
46370 */
46377 /* Temporary for holding the result, initialized to the input
46378 operand to ease control flow. */
46382 /* xa = abs (operand1) */
46385 /* if (!isless (xa, TWO52)) goto label; */
46388 /* xa = (double)(long)x */
46393 /* generate 1.0 */
46396 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46411 }
46413 /* Expand SSE sequence for computing round from OPERAND1 storing
46414 into OPERAND0. Sequence that works without relying on DImode truncation
46415 via cvttsd2siq that is only available on 64bit targets. */
46416 void
46418 {
46419 /* C code for the stuff we expand below.
46420 double xa = fabs (x), xa2, x2;
46421 if (!isless (xa, TWO52))
46422 return x;
46423 Using the absolute value and copying back sign makes
46424 -0.0 -> -0.0 correct.
46425 xa2 = xa + TWO52 - TWO52;
46426 Compensate.
46427 dxa = xa2 - xa;
46428 if (dxa <= -0.5)
46429 xa2 += 1;
46430 else if (dxa > 0.5)
46431 xa2 -= 1;
46432 x2 = copysign (xa2, x);
46433 return x2;
46434 */
46441 /* Temporary for holding the result, initialized to the input
46442 operand to ease control flow. */
46446 /* xa = abs (operand1) */
46449 /* if (!isless (xa, TWO52)) goto label; */
46452 /* xa2 = xa + TWO52 - TWO52; */
46456 /* dxa = xa2 - xa; */
46459 /* generate 0.5, 1.0 and -0.5 */
46465 /* Compensate. */
46467 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46472 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46478 /* res = copysign (xa2, operand1) */
46485 }
46487 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46488 into OPERAND0. */
46489 void
46491 {
46492 /* C code for SSE variant we expand below.
46493 double xa = fabs (x), x2;
46494 if (!isless (xa, TWO52))
46495 return x;
46496 x2 = (double)(long)x;
46497 if (HONOR_SIGNED_ZEROS (mode))
46498 return copysign (x2, x);
46499 return x2;
46500 */
46507 /* Temporary for holding the result, initialized to the input
46508 operand to ease control flow. */
46512 /* xa = abs (operand1) */
46515 /* if (!isless (xa, TWO52)) goto label; */
46518 /* x = (double)(long)x */
46530 }
46532 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46533 into OPERAND0. */
46534 void
46536 {
46541 /* C code for SSE variant we expand below.
46542 double xa = fabs (x), x2;
46543 if (!isless (xa, TWO52))
46544 return x;
46545 xa2 = xa + TWO52 - TWO52;
46546 Compensate:
46547 if (xa2 > xa)
46548 xa2 -= 1.0;
46549 x2 = copysign (xa2, x);
46550 return x2;
46551 */
46555 /* Temporary for holding the result, initialized to the input
46556 operand to ease control flow. */
46560 /* xa = abs (operand1) */
46563 /* if (!isless (xa, TWO52)) goto label; */
46566 /* res = xa + TWO52 - TWO52; */
46571 /* generate 1.0 */
46574 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46582 /* res = copysign (res, operand1) */
46589 }
46591 /* Expand SSE sequence for computing round from OPERAND1 storing
46592 into OPERAND0. */
46593 void
46595 {
46596 /* C code for the stuff we're doing below:
46597 double xa = fabs (x);
46598 if (!isless (xa, TWO52))
46599 return x;
46600 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46601 return copysign (xa, x);
46602 */
46609 /* Temporary for holding the result, initialized to the input
46610 operand to ease control flow. */
46618 /* load nextafter (0.5, 0.0) */
46623 /* xa = xa + 0.5 */
46627 /* xa = (double)(int64_t)xa */
46632 /* res = copysign (xa, operand1) */
46639 }
46641 /* Expand SSE sequence for computing round
46642 from OP1 storing into OP0 using sse4 round insn. */
46643 void
46645 {
46654 {
46665 }
46667 /* round (a) = trunc (a + copysign (0.5, a)) */
46669 /* load nextafter (0.5, 0.0) */
46675 /* e1 = copysign (0.5, op1) */
46679 /* e2 = op1 + e1 */
46682 /* res = trunc (e2) */
46687 }
46688 \f
46690 /* Table of valid machine attributes. */
46692 {
46693 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46694 affects_type_identity } */
46695 /* Stdcall attribute says callee is responsible for popping arguments
46696 if they are not variable. */
46699 /* Fastcall attribute says callee is responsible for popping arguments
46700 if they are not variable. */
46703 /* Thiscall attribute says callee is responsible for popping arguments
46704 if they are not variable. */
46707 /* Cdecl attribute says the callee is a normal C declaration */
46710 /* Regparm attribute specifies how many integer arguments are to be
46711 passed in registers. */
46714 /* Sseregparm attribute says we are using x86_64 calling conventions
46715 for FP arguments. */
46718 /* The transactional memory builtins are implicitly regparm or fastcall
46719 depending on the ABI. Override the generic do-nothing attribute that
46720 these builtins were declared with. */
46723 /* force_align_arg_pointer says this function realigns the stack at entry. */
46726 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46731 #endif
46736 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46737 SUBTARGET_ATTRIBUTE_TABLE,
46738 #endif
46739 /* ms_abi and sysv_abi calling convention function attributes. */
46746 /* End element. */
46748 };
46750 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46751 static int
46754 {
46758 {
46803 }
46804 }
46806 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46807 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46808 insn every time. */
46812 /* Initialize vselect_insn. */
46814 static void
46816 {
46818 rtx x;
46829 }
46831 /* Construct (set target (vec_select op0 (parallel perm))) and
46832 return true if that's a valid instruction in the active ISA. */
46834 static bool
46837 {
46863 }
46865 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46867 static bool
46871 {
46872 machine_mode v2mode;
46873 rtx x;
46888 }
46890 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46891 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46893 static bool
46895 {
46905 ;
46907 ;
46909 ;
46911 ;
46912 else
46915 /* This is a blend, not a permute. Elements must stay in their
46916 respective lanes. */
46918 {
46922 }
46927 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46928 decision should be extracted elsewhere, so that we only try that
46929 sequence once all budget==3 options have been tried. */
46936 {
46966 /* See if bytes move in pairs so we can use pblendw with
46967 an immediate argument, rather than pblendvb with a vector
46968 argument. */
46971 {
46972 use_pblendvb:
46976 finish_pblendvb:
46982 else
46987 }
46992 /* FALLTHRU */
46994 do_subreg:
47001 /* See if bytes move in pairs. If not, vpblendvb must be used. */
47005 /* See if bytes move in quadruplets. If yes, vpblendd
47006 with immediate can be used. */
47011 {
47012 /* See if bytes move the same in both lanes. If yes,
47013 vpblendw with immediate can be used. */
47018 /* Use vpblendw. */
47023 }
47025 /* Use vpblendd. */
47032 /* See if words move in pairs. If yes, vpblendd can be used. */
47037 {
47038 /* See if words move the same in both lanes. If not,
47039 vpblendvb must be used. */
47042 {
47043 /* Use vpblendvb. */
47053 }
47055 /* Use vpblendw. */
47059 }
47061 /* Use vpblendd. */
47068 /* Use vpblendd. */
47076 }
47078 /* This matches five different patterns with the different modes. */
47086 }
47088 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47089 in terms of the variable form of vpermilps.
47091 Note that we will have already failed the immediate input vpermilps,
47092 which requires that the high and low part shuffle be identical; the
47093 variable form doesn't require that. */
47095 static bool
47097 {
47104 /* We can only permute within the 128-bit lane. */
47106 {
47110 }
47116 {
47119 /* Within each 128-bit lane, the elements of op0 are numbered
47120 from 0 and the elements of op1 are numbered from 4. */
47127 }
47134 }
47136 /* Return true if permutation D can be performed as VMODE permutation
47137 instead. */
47139 static bool
47141 {
47156 else
47162 }
47164 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47165 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47167 static bool
47169 {
47178 {
47180 {
47183 {
47187 /* Use vperm2i128 insn. The pattern uses
47188 V4DImode instead of V2TImode. */
47201 }
47203 }
47204 }
47205 else
47206 {
47208 {
47211 }
47213 {
47217 /* V4DImode should be already handled through
47218 expand_vselect by vpermq instruction. */
47225 {
47226 /* First see if vpermq can be used for
47227 V8SImode/V16HImode/V32QImode. */
47229 {
47237 {
47241 }
47243 }
47245 /* Next see if vpermd can be used. */
47248 }
47249 /* Or if vpermps can be used. */
47254 {
47255 /* vpshufb only works intra lanes, it is not
47256 possible to shuffle bytes in between the lanes. */
47260 }
47261 }
47263 {
47267 /* If vpermq didn't work, vpshufb won't work either. */
47275 {
47276 /* First see if vpermq can be used for
47277 V16SImode/V32HImode/V64QImode. */
47279 {
47287 {
47291 }
47293 }
47295 /* Next see if vpermd can be used. */
47298 }
47299 /* Or if vpermps can be used. */
47303 {
47304 /* vpshufb only works intra lanes, it is not
47305 possible to shuffle bytes in between the lanes. */
47309 }
47310 }
47311 else
47313 }
47324 else
47325 {
47333 else
47337 {
47341 }
47342 }
47353 {
47368 else
47370 }
47371 else
47372 {
47375 }
47380 }
47382 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47383 in a single instruction. */
47385 static bool
47387 {
47391 /* Check plain VEC_SELECT first, because AVX has instructions that could
47392 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47393 input where SEL+CONCAT may not. */
47395 {
47401 {
47407 }
47410 {
47414 }
47416 {
47417 /* Use vpbroadcast{b,w,d}. */
47420 {
47463 /* For other modes prefer other shuffles this function creates. */
47465 }
47467 {
47471 }
47472 }
47477 /* There are plenty of patterns in sse.md that are written for
47478 SEL+CONCAT and are not replicated for a single op. Perhaps
47479 that should be changed, to avoid the nastiness here. */
47481 /* Recognize interleave style patterns, which means incrementing
47482 every other permutation operand. */
47484 {
47487 }
47492 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47494 {
47496 {
47501 }
47506 }
47507 }
47509 /* Finally, try the fully general two operand permute. */
47514 /* Recognize interleave style patterns with reversed operands. */
47516 {
47518 {
47522 else
47525 }
47530 }
47532 /* Try the SSE4.1 blend variable merge instructions. */
47536 /* Try one of the AVX vpermil variable permutations. */
47540 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47541 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47545 /* Try the AVX2 vpalignr instruction. */
47549 /* Try the AVX512F vpermi2 instructions. */
47554 }
47556 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47557 in terms of a pair of pshuflw + pshufhw instructions. */
47559 static bool
47561 {
47569 /* The two permutations only operate in 64-bit lanes. */
47580 /* Emit the pshuflw. */
47587 /* Emit the pshufhw. */
47595 }
47597 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47598 the permutation using the SSSE3 palignr instruction. This succeeds
47599 when all of the elements in PERM fit within one vector and we merely
47600 need to shift them down so that a single vector permutation has a
47601 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47602 the vpalignr instruction itself can perform the requested permutation. */
47604 static bool
47606 {
47613 /* Even with AVX, palignr only operates on 128-bit vectors,
47614 in AVX2 palignr operates on both 128-bit lanes. */
47624 {
47628 {
47631 }
47640 }
47643 {
47652 }
47654 /* Given that we have SSSE3, we know we'll be able to implement the
47655 single operand permutation after the palignr with pshufb for
47656 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47657 first. */
47663 {
47668 }
47672 {
47678 else
47683 }
47689 /* For AVX2, test whether we can permute the result in one instruction. */
47691 {
47696 }
47700 {
47704 }
47705 else
47706 {
47711 shift));
47712 }
47716 /* Test for the degenerate case where the alignment by itself
47717 produces the desired permutation. */
47719 {
47722 }
47728 }
47730 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47731 the permutation using the SSE4_1 pblendv instruction. Potentially
47732 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47734 static bool
47736 {
47742 /* Use the same checks as in expand_vec_perm_blend. */
47746 ;
47748 ;
47750 ;
47751 else
47754 /* Figure out where permutation elements stay not in their
47755 respective lanes. */
47757 {
47761 }
47762 /* We can pblend the part where elements stay not in their
47763 respective lanes only when these elements are all in one
47764 half of a permutation.
47765 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47766 lanes, but both 8 and 9 >= 8
47767 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47768 respective lanes and 8 >= 8, but 2 not. */
47774 /* First we apply one operand permutation to the part where
47775 elements stay not in their respective lanes. */
47779 else
47791 else
47796 /* Next we put permuted elements into their positions. */
47800 else
47810 }
47814 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47815 a two vector permutation into a single vector permutation by using
47816 an interleave operation to merge the vectors. */
47818 static bool
47820 {
47829 {
47832 }
47834 {
47837 /* For 32-byte modes allow even d->one_operand_p.
47838 The lack of cross-lane shuffling in some instructions
47839 might prevent a single insn shuffle. */
47842 /* If expand_vec_perm_interleave3 can expand this into
47843 a 3 insn sequence, give up and let it be expanded as
47844 3 insn sequence. While that is one insn longer,
47845 it doesn't need a memory operand and in the common
47846 case that both interleave low and high permutations
47847 with the same operands are adjacent needs 4 insns
47848 for both after CSE. */
47851 }
47852 else
47855 /* Examine from whence the elements come. */
47864 {
47867 /* Split the two input vectors into 4 halves. */
47873 /* If the elements from the low halves use interleave low, and similarly
47874 for interleave high. If the elements are from mis-matched halves, we
47875 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47877 {
47878 /* punpckl* */
47880 {
47885 }
47888 }
47890 {
47891 /* punpckh* */
47893 {
47898 }
47901 }
47903 {
47904 /* shufps */
47906 {
47911 }
47913 {
47914 /* shufpd */
47919 }
47920 }
47922 {
47923 /* shufps */
47925 {
47930 }
47932 {
47933 /* shufpd */
47938 }
47939 }
47940 else
47942 }
47943 else
47944 {
47949 /* Split the two input vectors into 8 quarters. */
47955 {
47958 }
47961 {
47965 }
47967 {
47970 }
47973 {
47975 {
47976 /* Attempt to increase the likelihood that dfinal
47977 shuffle will be intra-lane. */
47981 }
47983 /* vperm2f128 or vperm2i128. */
47985 {
47990 }
47995 {
47999 {
48002 }
48003 }
48004 }
48009 {
48010 /* vpunpckl* */
48012 {
48021 }
48022 }
48025 {
48026 /* vpunpckh* */
48028 {
48037 }
48038 }
48039 else
48041 }
48043 /* Use the remapping array set up above to move the elements from their
48044 swizzled locations into their final destinations. */
48047 {
48050 /* If same_halves is true, both halves of the remapped vector are the
48051 same. Avoid cross-lane accesses if possible. */
48053 {
48056 }
48057 else
48059 }
48061 {
48064 }
48068 /* Test if the final remap can be done with a single insn. For V4SFmode or
48069 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48082 {
48085 }
48092 }
48094 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48095 a single vector cross-lane permutation into vpermq followed
48096 by any of the single insn permutations. */
48098 static bool
48100 {
48114 {
48117 }
48120 {
48125 }
48138 {
48145 }
48152 {
48157 ;
48160 else
48162 }
48171 }
48173 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48174 a vector permutation using two instructions, vperm2f128 resp.
48175 vperm2i128 followed by any single in-lane permutation. */
48177 static bool
48179 {
48193 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48194 immediate. For perm < 16 the second permutation uses
48195 d->op0 as first operand, for perm >= 16 it uses d->op1
48196 as first operand. The second operand is the result of
48197 vperm2[fi]128. */
48199 {
48200 /* Ignore permutations which do not move anything cross-lane. */
48202 {
48203 /* The second shuffle for e.g. V4DFmode has
48204 0123 and ABCD operands.
48205 Ignore AB23, as 23 is already in the second lane
48206 of the first operand. */
48208 /* And 01CD, as 01 is in the first lane of the first
48209 operand. */
48211 /* And 4567, as then the vperm2[fi]128 doesn't change
48212 anything on the original 4567 second operand. */
48214 }
48215 else
48216 {
48217 /* The second shuffle for e.g. V4DFmode has
48218 4567 and ABCD operands.
48219 Ignore AB67, as 67 is already in the second lane
48220 of the first operand. */
48222 /* And 45CD, as 45 is in the first lane of the first
48223 operand. */
48225 /* And 0123, as then the vperm2[fi]128 doesn't change
48226 anything on the original 0123 first operand. */
48228 }
48231 {
48237 else
48239 }
48242 {
48246 }
48247 else
48251 {
48255 /* Found a usable second shuffle. dfirst will be
48256 vperm2f128 on d->op0 and d->op1. */
48268 /* And dsecond is some single insn shuffle, taking
48269 d->op0 and result of vperm2f128 (if perm < 16) or
48270 d->op1 and result of vperm2f128 (otherwise). */
48279 }
48281 /* For one operand, the only useful vperm2f128 permutation is 0x01
48282 aka lanes swap. */
48285 }
48288 }
48290 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48291 a two vector permutation using 2 intra-lane interleave insns
48292 and cross-lane shuffle for 32-byte vectors. */
48294 static bool
48296 {
48303 ;
48305 ;
48306 else
48321 {
48325 else
48331 else
48337 else
48343 else
48349 else
48355 else
48360 }
48364 }
48366 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48367 a single vector permutation using a single intra-lane vector
48368 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48369 the non-swapped and swapped vectors together. */
48371 static bool
48373 {
48381 || TARGET_AVX2
48390 {
48397 }
48432 }
48434 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48435 permutation using two vperm2f128, followed by a vshufpd insn blending
48436 the two vectors together. */
48438 static bool
48440 {
48483 }
48485 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48486 permutation with two pshufb insns and an ior. We should have already
48487 failed all two instruction sequences. */
48489 static bool
48491 {
48505 /* Generate two permutation masks. If the required element is within
48506 the given vector it is shuffled into the proper lane. If the required
48507 element is in the other vector, force a zero into the lane by setting
48508 bit 7 in the permutation mask. */
48511 {
48518 {
48521 }
48522 }
48546 }
48548 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48549 with two vpshufb insns, vpermq and vpor. We should have already failed
48550 all two or three instruction sequences. */
48552 static bool
48554 {
48569 /* Generate two permutation masks. If the required element is within
48570 the same lane, it is shuffled in. If the required element from the
48571 other lane, force a zero by setting bit 7 in the permutation mask.
48572 In the other mask the mask has non-negative elements if element
48573 is requested from the other lane, but also moved to the other lane,
48574 so that the result of vpshufb can have the two V2TImode halves
48575 swapped. */
48578 {
48583 {
48586 }
48587 }
48596 /* Swap the 128-byte lanes of h into hp. */
48600 const1_rtx));
48617 }
48619 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48620 and extract-odd permutations of two V32QImode and V16QImode operand
48621 with two vpshufb insns, vpor and vpermq. We should have already
48622 failed all two or three instruction sequences. */
48624 static bool
48626 {
48645 /* Generate two permutation masks. In the first permutation mask
48646 the first quarter will contain indexes for the first half
48647 of the op0, the second quarter will contain bit 7 set, third quarter
48648 will contain indexes for the second half of the op0 and the
48649 last quarter bit 7 set. In the second permutation mask
48650 the first quarter will contain bit 7 set, the second quarter
48651 indexes for the first half of the op1, the third quarter bit 7 set
48652 and last quarter indexes for the second half of the op1.
48653 I.e. the first mask e.g. for V32QImode extract even will be:
48654 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48655 (all values masked with 0xf except for -128) and second mask
48656 for extract even will be
48657 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48660 {
48666 {
48669 }
48670 }
48689 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48697 }
48699 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48700 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48701 with two "and" and "pack" or two "shift" and "pack" insns. We should
48702 have already failed all two instruction sequences. */
48704 static bool
48706 {
48710 machine_mode half_mode;
48719 {
48721 /* Required for "pack". */
48732 /* No check as all instructions are SSE2. */
48763 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48764 general shuffles. */
48766 }
48768 /* Check that permutation is even or odd. */
48783 {
48790 }
48791 else
48792 {
48799 }
48800 /* In AVX2 for 256 bit case we need to permute pack result. */
48802 {
48808 const0_rtx,
48809 const2_rtx,
48810 const1_rtx,
48813 }
48814 else
48818 }
48820 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48821 and extract-odd permutations. */
48823 static bool
48825 {
48829 {
48836 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48840 /* Now an unpck[lh]pd will produce the result required. */
48843 else
48849 {
48858 /* Shuffle within the 128-bit lanes to produce:
48859 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48863 /* Shuffle the lanes around to produce:
48864 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48868 /* Shuffle within the 128-bit lanes to produce:
48869 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48872 /* Shuffle within the 128-bit lanes to produce:
48873 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48876 /* Shuffle the lanes around to produce:
48877 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48880 }
48887 /* These are always directly implementable by expand_vec_perm_1. */
48895 else
48896 {
48899 /* We need 2*log2(N)-1 operations to achieve odd/even
48900 with interleave. */
48909 else
48912 }
48924 {
48929 else
48934 {
48939 }
48941 }
48949 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48953 /* Now an vpunpck[lh]qdq will produce the result required. */
48956 else
48963 {
48968 else
48973 {
48978 }
48980 }
48991 /* Shuffle the lanes around into
48992 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49000 /* Swap the 2nd and 3rd position in each lane into
49001 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49007 /* Now an vpunpck[lh]qdq will produce
49008 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49012 else
49021 }
49024 }
49026 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49027 extract-even and extract-odd permutations. */
49029 static bool
49031 {
49043 }
49045 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49046 permutations. We assume that expand_vec_perm_1 has already failed. */
49048 static bool
49050 {
49058 {
49061 /* These are special-cased in sse.md so that we can optionally
49062 use the vbroadcast instruction. They expand to two insns
49063 if the input happens to be in a register. */
49070 /* These are always implementable using standard shuffle patterns. */
49075 /* These can be implemented via interleave. We save one insn by
49076 stopping once we have promoted to V4SImode and then use pshufd. */
49079 do
49080 {
49081 rtx dest;
49087 {
49091 }
49098 }
49114 /* For AVX2 broadcasts of the first element vpbroadcast* or
49115 vpermq should be used by expand_vec_perm_1. */
49121 }
49122 }
49124 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49125 broadcast permutations. */
49127 static bool
49129 {
49141 }
49143 /* Implement arbitrary permutations of two V64QImode operands
49144 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49145 static bool
49147 {
49157 machine_mode vmode;
49163 {
49170 }
49172 /* Prepare permutations such that the first one takes care of
49173 putting the even bytes into the right positions or one higher
49174 positions (ds[0]) and the second one takes care of
49175 putting the odd bytes into the right positions or one below
49176 (ds[1]). */
49179 {
49182 {
49185 }
49186 else
49187 {
49190 }
49191 }
49213 }
49215 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49216 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49217 all the shorter instruction sequences. */
49219 static bool
49221 {
49237 /* Generate 4 permutation masks. If the required element is within
49238 the same lane, it is shuffled in. If the required element from the
49239 other lane, force a zero by setting bit 7 in the permutation mask.
49240 In the other mask the mask has non-negative elements if element
49241 is requested from the other lane, but also moved to the other lane,
49242 so that the result of vpshufb can have the two V2TImode halves
49243 swapped. */
49246 {
49251 }
49257 {
49265 }
49268 {
49270 {
49273 }
49280 }
49282 /* Swap the 128-byte lanes of h[X]. */
49284 {
49290 const1_rtx));
49292 }
49295 {
49297 {
49300 }
49306 }
49309 {
49311 {
49315 }
49318 }
49328 }
49330 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49331 With all of the interface bits taken care of, perform the expansion
49332 in D and return true on success. */
49334 static bool
49336 {
49337 /* Try a single instruction expansion. */
49341 /* Try sequences of two instructions. */
49364 /* Try sequences of three instructions. */
49381 /* Try sequences of four instructions. */
49392 /* ??? Look for narrow permutations whose element orderings would
49393 allow the promotion to a wider mode. */
49395 /* ??? Look for sequences of interleave or a wider permute that place
49396 the data into the correct lanes for a half-vector shuffle like
49397 pshuf[lh]w or vpermilps. */
49399 /* ??? Look for sequences of interleave that produce the desired results.
49400 The combinatorics of punpck[lh] get pretty ugly... */
49405 /* Even longer sequences. */
49410 }
49412 /* If a permutation only uses one operand, make it clear. Returns true
49413 if the permutation references both operands. */
49415 static bool
49417 {
49425 {
49431 {
49434 }
49435 /* The elements of PERM do not suggest that only the first operand
49436 is used, but both operands are identical. Allow easier matching
49437 of the permutation by folding the permutation into the single
49438 input vector. */
49439 /* FALLTHRU */
49450 }
49453 }
49455 bool
49457 {
49462 rtx sel;
49479 {
49484 }
49491 /* If the selector says both arguments are needed, but the operands are the
49492 same, the above tried to expand with one_operand_p and flattened selector.
49493 If that didn't work, retry without one_operand_p; we succeeded with that
49494 during testing. */
49496 {
49500 }
49503 }
49505 /* Implement targetm.vectorize.vec_perm_const_ok. */
49507 static bool
49510 {
49519 /* Given sufficient ISA support we can just return true here
49520 for selected vector modes. */
49522 {
49528 /* All implementable with a single vpermi2 insn. */
49533 /* All implementable with a single vpermi2 insn. */
49538 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49546 /* All implementable with a single vpermi2 insn. */
49551 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49556 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49563 /* All implementable with a single vpperm insn. */
49566 /* All implementable with 2 pshufb + 1 ior. */
49572 /* All implementable with shufpd or unpck[lh]pd. */
49576 }
49578 /* Extract the values from the vector CST into the permutation
49579 array in D. */
49582 {
49586 }
49588 /* For all elements from second vector, fold the elements to first. */
49593 /* Check whether the mask can be applied to the vector type. */
49596 /* Implementable with shufps or pshufd. */
49600 /* Otherwise we have to go through the motions and see if we can
49601 figure out how to generate the requested permutation. */
49612 }
49614 void
49616 {
49631 /* We'll either be able to implement the permutation directly... */
49635 /* ... or we use the special-case patterns. */
49637 }
49639 static void
49641 {
49656 {
49659 }
49661 /* Note that for AVX this isn't one instruction. */
49664 }
49667 /* Expand a vector operation CODE for a V*QImode in terms of the
49668 same operation on V*HImode. */
49670 void
49672 {
49674 machine_mode himode;
49684 {
49702 }
49706 {
49708 /* Unpack data such that we've got a source byte in each low byte of
49709 each word. We don't care what goes into the high byte of each word.
49710 Rather than trying to get zero in there, most convenient is to let
49711 it be a copy of the low byte. */
49716 /* FALLTHRU */
49728 /* FALLTHRU */
49738 }
49740 /* Perform the operation. */
49747 /* Merge the data back into the right place. */
49757 {
49758 /* For SSE2, we used an full interleave, so the desired
49759 results are in the even elements. */
49762 }
49763 else
49764 {
49765 /* For AVX, the interleave used above was not cross-lane. So the
49766 extraction is evens but with the second and third quarter swapped.
49767 Happily, that is even one insn shorter than even extraction. */
49770 }
49777 }
49779 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49780 if op is CONST_VECTOR with all odd elements equal to their
49781 preceding element. */
49783 static bool
49785 {
49795 }
49797 void
49800 {
49803 rtx x;
49811 /* We only play even/odd games with vectors of SImode. */
49814 /* If we're looking for the odd results, shift those members down to
49815 the even slots. For some cpus this is faster than a PSHUFD. */
49817 {
49818 /* For XOP use vpmacsdqh, but only for smult, as it is only
49819 signed. */
49821 {
49825 }
49836 }
49839 {
49842 else
49844 }
49846 {
49849 else
49851 }
49856 else
49857 {
49860 /* The easiest way to implement this without PMULDQ is to go through
49861 the motions as if we are performing a full 64-bit multiply. With
49862 the exception that we need to do less shuffling of the elements. */
49864 /* Compute the sign-extension, aka highparts, of the two operands. */
49870 /* Multiply LO(A) * HI(B), and vice-versa. */
49876 /* Multiply LO(A) * LO(B). */
49880 /* Combine and shift the highparts into place. */
49885 /* Combine high and low parts. */
49888 }
49890 }
49892 void
49895 {
49901 {
49906 {
49907 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49908 shuffle the elements once so that all elements are in the right
49909 place for immediate use: { A C B D }. */
49914 }
49915 else
49916 {
49917 /* Put the elements into place for the multiply. */
49921 }
49926 /* Shuffle the elements between the lanes. After this we
49927 have { A B E F | C D G H } for each operand. */
49937 /* Shuffle the elements within the lanes. After this we
49938 have { A A B B | C C D D } or { E E F F | G G H H }. */
49979 }
49980 }
49982 void
49984 {
49994 /* Move the results in element 2 down to element 1; we don't care
49995 what goes in elements 2 and 3. Then we can merge the parts
49996 back together with an interleave.
49998 Note that two other sequences were tried:
49999 (1) Use interleaves at the start instead of psrldq, which allows
50000 us to use a single shufps to merge things back at the end.
50001 (2) Use shufps here to combine the two vectors, then pshufd to
50002 put the elements in the correct order.
50003 In both cases the cost of the reformatting stall was too high
50004 and the overall sequence slower. */
50015 }
50017 void
50019 {
50030 {
50031 /* op1: A,B,C,D, op2: E,F,G,H */
50040 /* t1: B,A,D,C */
50047 /* t2: (B*E),(A*F),(D*G),(C*H) */
50050 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50053 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50056 /* Multiply lower parts and add all */
50063 }
50064 else
50065 {
50066 machine_mode nmode;
50070 {
50073 }
50075 {
50078 }
50080 {
50083 }
50084 else
50088 /* Multiply low parts. */
50092 /* Shift input vectors right 32 bits so we can multiply high parts. */
50097 /* Multiply high parts by low parts. */
50103 /* Combine and shift the highparts back. */
50107 /* Combine high and low parts. */
50109 }
50113 }
50115 /* Return 1 if control tansfer instruction INSN
50116 should be encoded with bnd prefix.
50117 If insn is NULL then return 1 when control
50118 transfer instructions should be prefixed with
50119 bnd by default for current function. */
50121 bool
50123 {
50124 /* For call insns check special flag. */
50126 {
50130 }
50132 /* All other insns are prefixed only if function is instrumented. */
50134 }
50136 /* Calculate integer abs() using only SSE2 instructions. */
50138 void
50140 {
50145 {
50146 /* For 32-bit signed integer X, the best way to calculate the absolute
50147 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50159 /* For 16-bit signed integer X, the best way to calculate the absolute
50160 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50168 /* For 8-bit signed integer X, the best way to calculate the absolute
50169 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50170 as SSE2 provides the PMINUB insn. */
50180 }
50184 }
50186 /* Expand an insert into a vector register through pinsr insn.
50187 Return true if successful. */
50189 bool
50191 {
50199 {
50202 }
50208 {
50213 {
50220 {
50252 }
50266 }
50270 }
50271 }
50272 \f
50273 /* This function returns the calling abi specific va_list type node.
50274 It returns the FNDECL specific va_list type. */
50276 static tree
50278 {
50285 else
50287 }
50289 /* Returns the canonical va_list type specified by TYPE. If there
50290 is no valid TYPE provided, it return NULL_TREE. */
50292 static tree
50294 {
50297 /* Resolve references and pointers to va_list type. */
50306 {
50311 {
50312 /* If va_list is an array type, the argument may have decayed
50313 to a pointer type, e.g. by being passed to another function.
50314 In that case, unwrap both types so that we can compare the
50315 underlying records. */
50318 {
50321 }
50322 }
50329 {
50330 /* If va_list is an array type, the argument may have decayed
50331 to a pointer type, e.g. by being passed to another function.
50332 In that case, unwrap both types so that we can compare the
50333 underlying records. */
50336 {
50339 }
50340 }
50347 {
50348 /* If va_list is an array type, the argument may have decayed
50349 to a pointer type, e.g. by being passed to another function.
50350 In that case, unwrap both types so that we can compare the
50351 underlying records. */
50354 {
50357 }
50358 }
50362 }
50364 }
50366 /* Iterate through the target-specific builtin types for va_list.
50367 IDX denotes the iterator, *PTREE is set to the result type of
50368 the va_list builtin, and *PNAME to its internal type.
50369 Returns zero if there is no element for this index, otherwise
50370 IDX should be increased upon the next call.
50371 Note, do not iterate a base builtin's name like __builtin_va_list.
50372 Used from c_common_nodes_and_builtins. */
50374 static int
50376 {
50378 {
50380 {
50393 }
50394 }
50397 }
50399 #undef TARGET_SCHED_DISPATCH
50400 #define TARGET_SCHED_DISPATCH has_dispatch
50401 #undef TARGET_SCHED_DISPATCH_DO
50402 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50403 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50404 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50405 #undef TARGET_SCHED_REORDER
50406 #define TARGET_SCHED_REORDER ix86_sched_reorder
50407 #undef TARGET_SCHED_ADJUST_PRIORITY
50408 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50409 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50410 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50411 ix86_dependencies_evaluation_hook
50413 /* The size of the dispatch window is the total number of bytes of
50414 object code allowed in a window. */
50415 #define DISPATCH_WINDOW_SIZE 16
50417 /* Number of dispatch windows considered for scheduling. */
50418 #define MAX_DISPATCH_WINDOWS 3
50420 /* Maximum number of instructions in a window. */
50421 #define MAX_INSN 4
50423 /* Maximum number of immediate operands in a window. */
50424 #define MAX_IMM 4
50426 /* Maximum number of immediate bits allowed in a window. */
50427 #define MAX_IMM_SIZE 128
50429 /* Maximum number of 32 bit immediates allowed in a window. */
50430 #define MAX_IMM_32 4
50432 /* Maximum number of 64 bit immediates allowed in a window. */
50433 #define MAX_IMM_64 2
50435 /* Maximum total of loads or prefetches allowed in a window. */
50436 #define MAX_LOAD 2
50438 /* Maximum total of stores allowed in a window. */
50439 #define MAX_STORE 1
50441 #undef BIG
50442 #define BIG 100
50445 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50448 disp_load,
50449 disp_store,
50450 disp_load_store,
50451 disp_prefetch,
50452 disp_imm,
50453 disp_imm_32,
50454 disp_imm_64,
50455 disp_branch,
50456 disp_cmp,
50457 disp_jcc,
50458 disp_last
50459 };
50461 /* Number of allowable groups in a dispatch window. It is an array
50462 indexed by dispatch_group enum. 100 is used as a big number,
50463 because the number of these kind of operations does not have any
50464 effect in dispatch window, but we need them for other reasons in
50465 the table. */
50468 };
50474 };
50476 /* Instruction path. */
50482 last_path
50483 };
50485 /* sched_insn_info defines a window to the instructions scheduled in
50486 the basic block. It contains a pointer to the insn_info table and
50487 the instruction scheduled.
50489 Windows are allocated for each basic block and are linked
50490 together. */
50492 rtx insn;
50499 /* Linked list of dispatch windows. This is a two way list of
50500 dispatch windows of a basic block. It contains information about
50501 the number of uops in the window and the total number of
50502 instructions and of bytes in the object code for this dispatch
50503 window. */
50521 /* Immediate valuse used in an insn. */
50523 {
50532 /* Get dispatch group of insn. */
50534 static enum dispatch_group
50536 {
50552 }
50554 /* Return true if insn is a compare instruction. */
50556 static bool
50558 {
50566 }
50568 /* Return true if a dispatch violation encountered. */
50570 static bool
50572 {
50576 }
50578 /* Return true if insn is a branch instruction. */
50580 static bool
50582 {
50584 }
50586 /* Return true if insn is a prefetch instruction. */
50588 static bool
50590 {
50592 }
50594 /* This function initializes a dispatch window and the list container holding a
50595 pointer to the window. */
50597 static void
50599 {
50605 else
50623 {
50629 }
50631 }
50633 /* This function allocates and initializes a dispatch window and the
50634 list container holding a pointer to the window. */
50638 {
50643 }
50645 /* This routine initializes the dispatch scheduling information. It
50646 initiates building dispatch scheduler tables and constructs the
50647 first dispatch window. */
50649 static void
50651 {
50652 /* Allocate a dispatch list and a window. */
50657 }
50659 /* This function returns true if a branch is detected. End of a basic block
50660 does not have to be a branch, but here we assume only branches end a
50661 window. */
50663 static bool
50665 {
50667 }
50669 /* This function is called when the end of a window processing is reached. */
50671 static void
50673 {
50676 {
50681 }
50683 }
50685 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50686 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50687 for 48 bytes of instructions. Note that these windows are not dispatch
50688 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50692 {
50694 {
50699 }
50705 }
50707 /* Compute number of immediate operands of an instruction. */
50709 static void
50711 {
50718 {
50725 else
50736 {
50739 }
50744 }
50745 }
50747 /* Return total size of immediate operands of an instruction along with number
50748 of corresponding immediate-operands. It initializes its parameters to zero
50749 befor calling FIND_CONSTANT.
50750 INSN is the input instruction. IMM is the total of immediates.
50751 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50752 bit immediates. */
50754 static int
50756 {
50764 }
50766 /* This function indicates if an operand of an instruction is an
50767 immediate. */
50769 static bool
50771 {
50780 }
50782 /* Return single or double path for instructions. */
50784 static enum insn_path
50786 {
50796 }
50798 /* Return insn dispatch group. */
50800 static enum dispatch_group
50802 {
50820 }
50822 /* Count number of GROUP restricted instructions in a dispatch
50823 window WINDOW_LIST. */
50825 static int
50827 {
50838 {
50857 }
50870 }
50872 /* This function returns true if insn satisfies dispatch rules on the
50873 last window scheduled. */
50875 static bool
50877 {
50885 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50886 instructions should be given the lowest priority in the
50887 scheduling process in Haifa scheduler to make sure they will be
50888 scheduled in the same dispatch window as the reference to them. */
50892 /* Check nonrestricted. */
50896 /* Get last dispatch window. */
50901 {
50906 /* Window 1 is full. Go for next window. */
50908 }
50915 /* See if it fits in the first window. */
50917 {
50918 /* The first widow should have only single and double path
50919 uops. */
50925 }
50927 }
50929 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50930 dispatch window WINDOW_LIST. */
50932 static void
50934 {
50952 /* Initialize window with new instruction. */
50973 {
50976 }
50977 }
50979 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50980 If the total bytes of instructions or the number of instructions in
50981 the window exceed allowable, it allocates a new window. */
50983 static void
50985 {
51008 /* Get the last dispatch window. */
51016 else
51019 /* If current window is full, get a new window.
51020 Window number zero is full, if MAX_INSN uops are scheduled in it.
51021 Window number one is full, if window zero's bytes plus window
51022 one's bytes is 32, or if the bytes of the new instruction added
51023 to the total makes it greater than 48, or it has already MAX_INSN
51024 instructions in it. */
51033 {
51036 }
51039 {
51043 {
51046 }
51047 }
51049 {
51054 {
51057 }
51060 }
51061 else
51065 {
51066 /* End of basic block is reached do end-basic-block process. */
51069 }
51070 }
51072 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51074 DEBUG_FUNCTION static void
51076 {
51082 else
51096 {
51099 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51105 }
51106 }
51108 /* Print to stdout a dispatch window. */
51110 DEBUG_FUNCTION void
51112 {
51114 }
51116 /* Print INSN dispatch information to FILE. */
51118 DEBUG_FUNCTION static void
51120 {
51143 }
51145 /* Print to STDERR the status of the ready list with respect to
51146 dispatch windows. */
51148 DEBUG_FUNCTION void
51150 {
51158 }
51160 /* This routine is the driver of the dispatch scheduler. */
51162 static void
51164 {
51169 }
51171 /* Return TRUE if Dispatch Scheduling is supported. */
51173 static bool
51175 {
51179 {
51195 }
51198 }
51200 /* Implementation of reassociation_width target hook used by
51201 reassoc phase to identify parallelism level in reassociated
51202 tree. Statements tree_code is passed in OPC. Arguments type
51203 is passed in MODE.
51205 Currently parallel reassociation is enabled for Atom
51206 processors only and we set reassociation width to be 2
51207 because Atom may issue up to 2 instructions per cycle.
51209 Return value should be fixed if parallel reassociation is
51210 enabled for other processors. */
51212 static int
51214 {
51215 /* Vector part. */
51217 {
51220 else
51222 }
51224 /* Scalar part. */
51229 else
51231 }
51233 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51234 place emms and femms instructions. */
51236 static machine_mode
51238 {
51243 {
51262 else
51274 /* FALLTHRU */
51278 }
51279 }
51281 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51282 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51283 256bit and 128bit vectors. */
51285 static unsigned int
51287 {
51290 }
51292 \f
51294 /* Return class of registers which could be used for pseudo of MODE
51295 and of class RCLASS for spilling instead of memory. Return NO_REGS
51296 if it is not possible or non-profitable. */
51297 static reg_class_t
51299 {
51305 }
51307 /* Implement targetm.vectorize.init_cost. */
51311 {
51315 }
51317 /* Implement targetm.vectorize.add_stmt_cost. */
51319 static unsigned
51323 {
51330 /* Statements in an inner loop relative to the loop being
51331 vectorized are weighted more heavily. The value here is
51332 arbitrary and could potentially be improved with analysis. */
51338 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51339 for Silvermont as it has out of order integer pipeline and can execute
51340 2 scalar instruction per tick, but has in order SIMD pipeline. */
51343 {
51347 }
51352 }
51354 /* Implement targetm.vectorize.finish_cost. */
51356 static void
51359 {
51364 }
51366 /* Implement targetm.vectorize.destroy_cost_data. */
51368 static void
51370 {
51372 }
51374 /* Validate target specific memory model bits in VAL. */
51376 static unsigned HOST_WIDE_INT
51378 {
51385 {
51389 }
51392 {
51396 }
51398 {
51402 }
51404 }
51406 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51407 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51408 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51409 or number of vecsize_mangle variants that should be emitted. */
51411 static int
51415 {
51422 {
51426 }
51431 {
51438 /* case SCmode: */
51439 /* case DCmode: */
51445 }
51447 tree t;
51451 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51453 {
51460 /* case SCmode: */
51461 /* case DCmode: */
51467 }
51470 {
51471 /* Parse here processor clause. If not present, default to 'b'. */
51473 }
51475 {
51476 /* If the function isn't exported, we can pick up just one ISA
51477 for the clones. */
51482 else
51485 }
51486 else
51487 {
51490 }
51492 {
51505 }
51507 {
51510 else
51515 }
51517 }
51519 /* Add target attribute to SIMD clone NODE if needed. */
51521 static void
51523 {
51527 {
51542 }
51552 }
51554 /* If SIMD clone NODE can't be used in a vectorized loop
51555 in current function, return -1, otherwise return a badness of using it
51556 (0 if it is most desirable from vecsize_mangle point of view, 1
51557 slightly less desirable, etc.). */
51559 static int
51561 {
51563 {
51581 }
51582 }
51584 /* This function adjusts the unroll factor based on
51585 the hardware capabilities. For ex, bdver3 has
51586 a loop buffer which makes unrolling of smaller
51587 loops less important. This function decides the
51588 unroll factor using number of memory references
51589 (value 32 is used) as a heuristic. */
51591 static unsigned
51593 {
51602 /* Count the number of memory references within the loop body.
51603 This value determines the unrolling factor for bdver3 and bdver4
51604 architectures. */
51613 {
51618 else
51620 }
51627 }
51630 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51632 static bool
51634 {
51635 /* For x87 floating point with standard excess precision handling,
51636 there is no adddf3 pattern (since x87 floating point only has
51637 XFmode operations) so the default hook implementation gets this
51638 wrong. */
51640 }
51642 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51644 static void
51646 {
51651 {
51666 hold_fnclex);
51679 }
51681 {
51690 mxcsr_orig_var,
51700 ldmxcsr_hold_call);
51703 else
51708 ldmxcsr_clear_call);
51709 else
51713 stxmcsr_update_call);
51715 {
51721 exceptions_assign);
51722 }
51723 else
51728 ldmxcsr_update_call);
51729 }
51730 tree atomic_feraiseexcept
51735 atomic_feraiseexcept_call);
51736 }
51738 /* Return mode to be used for bounds or VOIDmode
51739 if bounds are not supported. */
51741 static enum machine_mode
51743 {
51744 /* Do not support pointer checker if MPX
51745 is not enabled. */
51747 {
51752 }
51755 }
51757 /* Return constant used to statically initialize constant bounds.
51759 This function is used to create special bound values. For now
51760 only INIT bounds and NONE bounds are expected. More special
51761 values may be added later. */
51763 static tree
51765 {
51771 /* This function is supposed to be used to create INIT and
51772 NONE bounds only. */
51777 }
51779 /* Generate a list of statements STMTS to initialize pointer bounds
51780 variable VAR with bounds LB and UB. Return the number of generated
51781 statements. */
51783 static int
51785 {
51803 }
51805 /* Initialize the GCC target structure. */
51806 #undef TARGET_RETURN_IN_MEMORY
51807 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51809 #undef TARGET_LEGITIMIZE_ADDRESS
51810 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51812 #undef TARGET_ATTRIBUTE_TABLE
51813 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51814 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51815 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51816 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51817 # undef TARGET_MERGE_DECL_ATTRIBUTES
51818 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51819 #endif
51821 #undef TARGET_COMP_TYPE_ATTRIBUTES
51822 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51824 #undef TARGET_INIT_BUILTINS
51825 #define TARGET_INIT_BUILTINS ix86_init_builtins
51826 #undef TARGET_BUILTIN_DECL
51827 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51828 #undef TARGET_EXPAND_BUILTIN
51829 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51831 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51832 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51833 ix86_builtin_vectorized_function
51835 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51836 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51838 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51839 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51841 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51842 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51844 #undef TARGET_BUILTIN_RECIPROCAL
51845 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51847 #undef TARGET_ASM_FUNCTION_EPILOGUE
51848 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51850 #undef TARGET_ENCODE_SECTION_INFO
51851 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51852 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51853 #else
51854 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51855 #endif
51857 #undef TARGET_ASM_OPEN_PAREN
51859 #undef TARGET_ASM_CLOSE_PAREN
51862 #undef TARGET_ASM_BYTE_OP
51863 #define TARGET_ASM_BYTE_OP ASM_BYTE
51865 #undef TARGET_ASM_ALIGNED_HI_OP
51866 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51867 #undef TARGET_ASM_ALIGNED_SI_OP
51868 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51869 #ifdef ASM_QUAD
51870 #undef TARGET_ASM_ALIGNED_DI_OP
51871 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51872 #endif
51874 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51875 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51877 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51878 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51880 #undef TARGET_ASM_UNALIGNED_HI_OP
51881 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51882 #undef TARGET_ASM_UNALIGNED_SI_OP
51883 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51884 #undef TARGET_ASM_UNALIGNED_DI_OP
51885 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51887 #undef TARGET_PRINT_OPERAND
51888 #define TARGET_PRINT_OPERAND ix86_print_operand
51889 #undef TARGET_PRINT_OPERAND_ADDRESS
51890 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51891 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51892 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51893 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51894 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51896 #undef TARGET_SCHED_INIT_GLOBAL
51897 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51898 #undef TARGET_SCHED_ADJUST_COST
51899 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51900 #undef TARGET_SCHED_ISSUE_RATE
51901 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51902 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51903 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51904 ia32_multipass_dfa_lookahead
51905 #undef TARGET_SCHED_MACRO_FUSION_P
51906 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51907 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51908 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51910 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51911 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51913 #undef TARGET_MEMMODEL_CHECK
51914 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51916 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51917 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51919 #ifdef HAVE_AS_TLS
51920 #undef TARGET_HAVE_TLS
51921 #define TARGET_HAVE_TLS true
51922 #endif
51923 #undef TARGET_CANNOT_FORCE_CONST_MEM
51924 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51925 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51926 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51928 #undef TARGET_DELEGITIMIZE_ADDRESS
51929 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51931 #undef TARGET_MS_BITFIELD_LAYOUT_P
51932 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51934 #if TARGET_MACHO
51935 #undef TARGET_BINDS_LOCAL_P
51936 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51937 #else
51938 #undef TARGET_BINDS_LOCAL_P
51939 #define TARGET_BINDS_LOCAL_P default_binds_local_p_2
51940 #endif
51941 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51942 #undef TARGET_BINDS_LOCAL_P
51943 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51944 #endif
51946 #undef TARGET_ASM_OUTPUT_MI_THUNK
51947 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51948 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51949 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51951 #undef TARGET_ASM_FILE_START
51952 #define TARGET_ASM_FILE_START x86_file_start
51954 #undef TARGET_OPTION_OVERRIDE
51955 #define TARGET_OPTION_OVERRIDE ix86_option_override
51957 #undef TARGET_REGISTER_MOVE_COST
51958 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51959 #undef TARGET_MEMORY_MOVE_COST
51960 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51961 #undef TARGET_RTX_COSTS
51962 #define TARGET_RTX_COSTS ix86_rtx_costs
51963 #undef TARGET_ADDRESS_COST
51964 #define TARGET_ADDRESS_COST ix86_address_cost
51966 #undef TARGET_FIXED_CONDITION_CODE_REGS
51967 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51968 #undef TARGET_CC_MODES_COMPATIBLE
51969 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51971 #undef TARGET_MACHINE_DEPENDENT_REORG
51972 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51974 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51975 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51977 #undef TARGET_BUILD_BUILTIN_VA_LIST
51978 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51980 #undef TARGET_FOLD_BUILTIN
51981 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51983 #undef TARGET_COMPARE_VERSION_PRIORITY
51984 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51986 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51987 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51988 ix86_generate_version_dispatcher_body
51990 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51991 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51992 ix86_get_function_versions_dispatcher
51994 #undef TARGET_ENUM_VA_LIST_P
51995 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51997 #undef TARGET_FN_ABI_VA_LIST
51998 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52000 #undef TARGET_CANONICAL_VA_LIST_TYPE
52001 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52003 #undef TARGET_EXPAND_BUILTIN_VA_START
52004 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52006 #undef TARGET_MD_ASM_CLOBBERS
52007 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
52009 #undef TARGET_PROMOTE_PROTOTYPES
52010 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52011 #undef TARGET_SETUP_INCOMING_VARARGS
52012 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52013 #undef TARGET_MUST_PASS_IN_STACK
52014 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52015 #undef TARGET_FUNCTION_ARG_ADVANCE
52016 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52017 #undef TARGET_FUNCTION_ARG
52018 #define TARGET_FUNCTION_ARG ix86_function_arg
52019 #undef TARGET_INIT_PIC_REG
52020 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52021 #undef TARGET_USE_PSEUDO_PIC_REG
52022 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52023 #undef TARGET_FUNCTION_ARG_BOUNDARY
52024 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52025 #undef TARGET_PASS_BY_REFERENCE
52026 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52027 #undef TARGET_INTERNAL_ARG_POINTER
52028 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52029 #undef TARGET_UPDATE_STACK_BOUNDARY
52030 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52031 #undef TARGET_GET_DRAP_RTX
52032 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52033 #undef TARGET_STRICT_ARGUMENT_NAMING
52034 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52035 #undef TARGET_STATIC_CHAIN
52036 #define TARGET_STATIC_CHAIN ix86_static_chain
52037 #undef TARGET_TRAMPOLINE_INIT
52038 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52039 #undef TARGET_RETURN_POPS_ARGS
52040 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52042 #undef TARGET_LEGITIMATE_COMBINED_INSN
52043 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52045 #undef TARGET_ASAN_SHADOW_OFFSET
52046 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52048 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52049 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52051 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52052 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52054 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52055 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52057 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52058 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52059 ix86_libgcc_floating_mode_supported_p
52061 #undef TARGET_C_MODE_FOR_SUFFIX
52062 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52064 #ifdef HAVE_AS_TLS
52065 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52066 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52067 #endif
52069 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52070 #undef TARGET_INSERT_ATTRIBUTES
52071 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52072 #endif
52074 #undef TARGET_MANGLE_TYPE
52075 #define TARGET_MANGLE_TYPE ix86_mangle_type
52077 #if !TARGET_MACHO
52078 #undef TARGET_STACK_PROTECT_FAIL
52079 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52080 #endif
52082 #undef TARGET_FUNCTION_VALUE
52083 #define TARGET_FUNCTION_VALUE ix86_function_value
52085 #undef TARGET_FUNCTION_VALUE_REGNO_P
52086 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52088 #undef TARGET_PROMOTE_FUNCTION_MODE
52089 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52091 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52092 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52094 #undef TARGET_INSTANTIATE_DECLS
52095 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52097 #undef TARGET_SECONDARY_RELOAD
52098 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52100 #undef TARGET_CLASS_MAX_NREGS
52101 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52103 #undef TARGET_PREFERRED_RELOAD_CLASS
52104 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52105 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52106 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52107 #undef TARGET_CLASS_LIKELY_SPILLED_P
52108 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52110 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52111 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52112 ix86_builtin_vectorization_cost
52113 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52114 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52115 ix86_vectorize_vec_perm_const_ok
52116 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52117 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52118 ix86_preferred_simd_mode
52119 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52120 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52121 ix86_autovectorize_vector_sizes
52122 #undef TARGET_VECTORIZE_INIT_COST
52123 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52124 #undef TARGET_VECTORIZE_ADD_STMT_COST
52125 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52126 #undef TARGET_VECTORIZE_FINISH_COST
52127 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52128 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52129 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52131 #undef TARGET_SET_CURRENT_FUNCTION
52132 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52134 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52135 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52137 #undef TARGET_OPTION_SAVE
52138 #define TARGET_OPTION_SAVE ix86_function_specific_save
52140 #undef TARGET_OPTION_RESTORE
52141 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52143 #undef TARGET_OPTION_POST_STREAM_IN
52144 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52146 #undef TARGET_OPTION_PRINT
52147 #define TARGET_OPTION_PRINT ix86_function_specific_print
52149 #undef TARGET_OPTION_FUNCTION_VERSIONS
52150 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52152 #undef TARGET_CAN_INLINE_P
52153 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52155 #undef TARGET_EXPAND_TO_RTL_HOOK
52156 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52158 #undef TARGET_LEGITIMATE_ADDRESS_P
52159 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52161 #undef TARGET_LRA_P
52162 #define TARGET_LRA_P hook_bool_void_true
52164 #undef TARGET_REGISTER_PRIORITY
52165 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52167 #undef TARGET_REGISTER_USAGE_LEVELING_P
52168 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52170 #undef TARGET_LEGITIMATE_CONSTANT_P
52171 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52173 #undef TARGET_FRAME_POINTER_REQUIRED
52174 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52176 #undef TARGET_CAN_ELIMINATE
52177 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52179 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52180 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52182 #undef TARGET_ASM_CODE_END
52183 #define TARGET_ASM_CODE_END ix86_code_end
52185 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52186 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52188 #if TARGET_MACHO
52189 #undef TARGET_INIT_LIBFUNCS
52190 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52191 #endif
52193 #undef TARGET_LOOP_UNROLL_ADJUST
52194 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52196 #undef TARGET_SPILL_CLASS
52197 #define TARGET_SPILL_CLASS ix86_spill_class
52199 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52200 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52201 ix86_simd_clone_compute_vecsize_and_simdlen
52203 #undef TARGET_SIMD_CLONE_ADJUST
52204 #define TARGET_SIMD_CLONE_ADJUST \
52205 ix86_simd_clone_adjust
52207 #undef TARGET_SIMD_CLONE_USABLE
52208 #define TARGET_SIMD_CLONE_USABLE \
52209 ix86_simd_clone_usable
52211 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52212 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52213 ix86_float_exceptions_rounding_supported_p
52215 #undef TARGET_MODE_EMIT
52216 #define TARGET_MODE_EMIT ix86_emit_mode_set
52218 #undef TARGET_MODE_NEEDED
52219 #define TARGET_MODE_NEEDED ix86_mode_needed
52221 #undef TARGET_MODE_AFTER
52222 #define TARGET_MODE_AFTER ix86_mode_after
52224 #undef TARGET_MODE_ENTRY
52225 #define TARGET_MODE_ENTRY ix86_mode_entry
52227 #undef TARGET_MODE_EXIT
52228 #define TARGET_MODE_EXIT ix86_mode_exit
52230 #undef TARGET_MODE_PRIORITY
52231 #define TARGET_MODE_PRIORITY ix86_mode_priority
52233 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52234 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52236 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52237 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52239 #undef TARGET_STORE_BOUNDS_FOR_ARG
52240 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52242 #undef TARGET_LOAD_RETURNED_BOUNDS
52243 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52245 #undef TARGET_STORE_RETURNED_BOUNDS
52246 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52248 #undef TARGET_CHKP_BOUND_MODE
52249 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52251 #undef TARGET_BUILTIN_CHKP_FUNCTION
52252 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52254 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52255 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52257 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52258 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52260 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52261 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52263 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52264 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52266 #undef TARGET_OFFLOAD_OPTIONS
52267 #define TARGET_OFFLOAD_OPTIONS \
52268 ix86_offload_options
52270 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52271 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52274 \f