1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts
;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges
;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras
;
116 /* Number of instructions combined in this function. */
118 static int combine_successes
;
120 /* Totals over entire compilation. */
122 static int total_attempts
, total_merges
, total_extras
, total_successes
;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid
;
139 static int max_uid_cuid
;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) (INSN_UID (INSN) > max_uid_cuid \
145 : uid_cuid[INSN_UID (INSN)])
147 /* Maximum register number, which is the size of the tables below. */
149 static int combine_max_regno
;
151 /* Record last point of death of (hard or pseudo) register n. */
153 static rtx
*reg_last_death
;
155 /* Record last point of modification of (hard or pseudo) register n. */
157 static rtx
*reg_last_set
;
159 /* Record the cuid of the last insn that invalidated memory
160 (anything that writes memory, and subroutine calls, but not pushes). */
162 static int mem_last_set
;
164 /* Record the cuid of the last CALL_INSN
165 so we can tell whether a potential combination crosses any calls. */
167 static int last_call_cuid
;
169 /* When `subst' is called, this is the insn that is being modified
170 (by combining in a previous insn). The PATTERN of this insn
171 is still the old pattern partially modified and it should not be
172 looked at, but this may be used to examine the successors of the insn
173 to judge whether a simplification is valid. */
175 static rtx subst_insn
;
177 /* This is an insn that belongs before subst_insn, but is not currently
178 on the insn chain. */
180 static rtx subst_prev_insn
;
182 /* This is the lowest CUID that `subst' is currently dealing with.
183 get_last_value will not return a value if the register was set at or
184 after this CUID. If not for this mechanism, we could get confused if
185 I2 or I1 in try_combine were an insn that used the old value of a register
186 to obtain a new value. In that case, we might erroneously get the
187 new value of the register when we wanted the old one. */
189 static int subst_low_cuid
;
191 /* This contains any hard registers that are used in newpat; reg_dead_at_p
192 must consider all these registers to be always live. */
194 static HARD_REG_SET newpat_used_regs
;
196 /* This is an insn to which a LOG_LINKS entry has been added. If this
197 insn is the earlier than I2 or I3, combine should rescan starting at
200 static rtx added_links_insn
;
202 /* This is the value of undobuf.num_undo when we started processing this
203 substitution. This will prevent gen_rtx_combine from re-used a piece
204 from the previous expression. Doing so can produce circular rtl
207 static int previous_num_undos
;
209 /* Basic block number of the block in which we are performing combines. */
210 static int this_basic_block
;
212 /* The next group of arrays allows the recording of the last value assigned
213 to (hard or pseudo) register n. We use this information to see if a
214 operation being processed is redundant given a prior operation performed
215 on the register. For example, an `and' with a constant is redundant if
216 all the zero bits are already known to be turned off.
218 We use an approach similar to that used by cse, but change it in the
221 (1) We do not want to reinitialize at each label.
222 (2) It is useful, but not critical, to know the actual value assigned
223 to a register. Often just its form is helpful.
225 Therefore, we maintain the following arrays:
227 reg_last_set_value the last value assigned
228 reg_last_set_label records the value of label_tick when the
229 register was assigned
230 reg_last_set_table_tick records the value of label_tick when a
231 value using the register is assigned
232 reg_last_set_invalid set to non-zero when it is not valid
233 to use the value of this register in some
236 To understand the usage of these tables, it is important to understand
237 the distinction between the value in reg_last_set_value being valid
238 and the register being validly contained in some other expression in the
241 Entry I in reg_last_set_value is valid if it is non-zero, and either
242 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
244 Register I may validly appear in any expression returned for the value
245 of another register if reg_n_sets[i] is 1. It may also appear in the
246 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
247 reg_last_set_invalid[j] is zero.
249 If an expression is found in the table containing a register which may
250 not validly appear in an expression, the register is replaced by
251 something that won't match, (clobber (const_int 0)).
253 reg_last_set_invalid[i] is set non-zero when register I is being assigned
254 to and reg_last_set_table_tick[i] == label_tick. */
256 /* Record last value assigned to (hard or pseudo) register n. */
258 static rtx
*reg_last_set_value
;
260 /* Record the value of label_tick when the value for register n is placed in
261 reg_last_set_value[n]. */
263 static int *reg_last_set_label
;
265 /* Record the value of label_tick when an expression involving register n
266 is placed in reg_last_set_value. */
268 static int *reg_last_set_table_tick
;
270 /* Set non-zero if references to register n in expressions should not be
273 static char *reg_last_set_invalid
;
275 /* Incremented for each label. */
277 static int label_tick
;
279 /* Some registers that are set more than once and used in more than one
280 basic block are nevertheless always set in similar ways. For example,
281 a QImode register may be loaded from memory in two places on a machine
282 where byte loads zero extend.
284 We record in the following array what we know about the nonzero
285 bits of a register, specifically which bits are known to be zero.
287 If an entry is zero, it means that we don't know anything special. */
289 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
291 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
292 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
294 static enum machine_mode nonzero_bits_mode
;
296 /* Nonzero if we know that a register has some leading bits that are always
297 equal to the sign bit. */
299 static char *reg_sign_bit_copies
;
301 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
302 It is zero while computing them and after combine has completed. This
303 former test prevents propagating values based on previously set values,
304 which can be incorrect if a variable is modified in a loop. */
306 static int nonzero_sign_valid
;
308 /* These arrays are maintained in parallel with reg_last_set_value
309 and are used to store the mode in which the register was last set,
310 the bits that were known to be zero when it was last set, and the
311 number of sign bits copies it was known to have when it was last set. */
313 static enum machine_mode
*reg_last_set_mode
;
314 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
315 static char *reg_last_set_sign_bit_copies
;
317 /* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
324 union {rtx r
; int i
;} old_contents
;
325 union {rtx
*r
; int *i
;} where
;
328 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
329 num_undo says how many are currently recorded.
331 storage is nonzero if we must undo the allocation of new storage.
332 The value of storage is what to pass to obfree.
334 other_insn is nonzero if we have modified some other insn in the process
335 of working on subst_insn. It must be verified too. */
343 struct undo undo
[MAX_UNDO
];
347 static struct undobuf undobuf
;
349 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
350 insn. The substitution can be undone by undo_all. If INTO is already
351 set to NEWVAL, do not record this change. Because computing NEWVAL might
352 also call SUBST, we have to compute it before we put anything into
355 #define SUBST(INTO, NEWVAL) \
356 do { rtx _new = (NEWVAL); \
357 if (undobuf.num_undo < MAX_UNDO) \
359 undobuf.undo[undobuf.num_undo].is_int = 0; \
360 undobuf.undo[undobuf.num_undo].where.r = &INTO; \
361 undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \
363 if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \
364 undobuf.num_undo++; \
368 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
370 Note that substitution for the value of a CONST_INT is not safe. */
372 #define SUBST_INT(INTO, NEWVAL) \
373 do { if (undobuf.num_undo < MAX_UNDO) \
375 undobuf.undo[undobuf.num_undo].is_int = 1; \
376 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
377 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
379 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
380 undobuf.num_undo++; \
384 /* Number of times the pseudo being substituted for
385 was found and replaced. */
387 static int n_occurrences
;
389 static void init_reg_last_arrays
PROTO(());
390 static void setup_incoming_promotions
PROTO(());
391 static void set_nonzero_bits_and_sign_copies
PROTO((rtx
, rtx
));
392 static int can_combine_p
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
393 static int combinable_i3pat
PROTO((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
394 static rtx try_combine
PROTO((rtx
, rtx
, rtx
));
395 static void undo_all
PROTO((void));
396 static rtx
*find_split_point
PROTO((rtx
*, rtx
));
397 static rtx subst
PROTO((rtx
, rtx
, rtx
, int, int));
398 static rtx simplify_rtx
PROTO((rtx
, enum machine_mode
, int, int));
399 static rtx simplify_if_then_else
PROTO((rtx
));
400 static rtx simplify_set
PROTO((rtx
));
401 static rtx simplify_logical
PROTO((rtx
, int));
402 static rtx expand_compound_operation
PROTO((rtx
));
403 static rtx expand_field_assignment
PROTO((rtx
));
404 static rtx make_extraction
PROTO((enum machine_mode
, rtx
, int, rtx
, int,
406 static rtx extract_left_shift
PROTO((rtx
, int));
407 static rtx make_compound_operation
PROTO((rtx
, enum rtx_code
));
408 static int get_pos_from_mask
PROTO((unsigned HOST_WIDE_INT
, int *));
409 static rtx force_to_mode
PROTO((rtx
, enum machine_mode
,
410 unsigned HOST_WIDE_INT
, rtx
, int));
411 static rtx if_then_else_cond
PROTO((rtx
, rtx
*, rtx
*));
412 static rtx known_cond
PROTO((rtx
, enum rtx_code
, rtx
, rtx
));
413 static int rtx_equal_for_field_assignment_p
PROTO((rtx
, rtx
));
414 static rtx make_field_assignment
PROTO((rtx
));
415 static rtx apply_distributive_law
PROTO((rtx
));
416 static rtx simplify_and_const_int
PROTO((rtx
, enum machine_mode
, rtx
,
417 unsigned HOST_WIDE_INT
));
418 static unsigned HOST_WIDE_INT nonzero_bits
PROTO((rtx
, enum machine_mode
));
419 static int num_sign_bit_copies
PROTO((rtx
, enum machine_mode
));
420 static int merge_outer_ops
PROTO((enum rtx_code
*, HOST_WIDE_INT
*,
421 enum rtx_code
, HOST_WIDE_INT
,
422 enum machine_mode
, int *));
423 static rtx simplify_shift_const
PROTO((rtx
, enum rtx_code
, enum machine_mode
,
425 static int recog_for_combine
PROTO((rtx
*, rtx
, rtx
*, int *));
426 static rtx gen_lowpart_for_combine
PROTO((enum machine_mode
, rtx
));
427 static rtx gen_rtx_combine
PVPROTO((enum rtx_code code
, enum machine_mode mode
,
429 static rtx gen_binary
PROTO((enum rtx_code
, enum machine_mode
,
431 static rtx gen_unary
PROTO((enum rtx_code
, enum machine_mode
,
432 enum machine_mode
, rtx
));
433 static enum rtx_code simplify_comparison
PROTO((enum rtx_code
, rtx
*, rtx
*));
434 static int reversible_comparison_p
PROTO((rtx
));
435 static void update_table_tick
PROTO((rtx
));
436 static void record_value_for_reg
PROTO((rtx
, rtx
, rtx
));
437 static void record_dead_and_set_regs_1
PROTO((rtx
, rtx
));
438 static void record_dead_and_set_regs
PROTO((rtx
));
439 static int get_last_value_validate
PROTO((rtx
*, int, int));
440 static rtx get_last_value
PROTO((rtx
));
441 static int use_crosses_set_p
PROTO((rtx
, int));
442 static void reg_dead_at_p_1
PROTO((rtx
, rtx
));
443 static int reg_dead_at_p
PROTO((rtx
, rtx
));
444 static void move_deaths
PROTO((rtx
, int, rtx
, rtx
*));
445 static int reg_bitfield_target_p
PROTO((rtx
, rtx
));
446 static void distribute_notes
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
447 static void distribute_links
PROTO((rtx
));
448 static void mark_used_regs_combine
PROTO((rtx
));
450 /* Main entry point for combiner. F is the first insn of the function.
451 NREGS is the first unused pseudo-reg number. */
454 combine_instructions (f
, nregs
)
458 register rtx insn
, next
, prev
;
460 register rtx links
, nextlinks
;
462 combine_attempts
= 0;
465 combine_successes
= 0;
466 undobuf
.num_undo
= previous_num_undos
= 0;
468 combine_max_regno
= nregs
;
471 = (unsigned HOST_WIDE_INT
*) alloca (nregs
* sizeof (HOST_WIDE_INT
));
472 reg_sign_bit_copies
= (char *) alloca (nregs
* sizeof (char));
474 bzero ((char *) reg_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
475 bzero (reg_sign_bit_copies
, nregs
* sizeof (char));
477 reg_last_death
= (rtx
*) alloca (nregs
* sizeof (rtx
));
478 reg_last_set
= (rtx
*) alloca (nregs
* sizeof (rtx
));
479 reg_last_set_value
= (rtx
*) alloca (nregs
* sizeof (rtx
));
480 reg_last_set_table_tick
= (int *) alloca (nregs
* sizeof (int));
481 reg_last_set_label
= (int *) alloca (nregs
* sizeof (int));
482 reg_last_set_invalid
= (char *) alloca (nregs
* sizeof (char));
484 = (enum machine_mode
*) alloca (nregs
* sizeof (enum machine_mode
));
485 reg_last_set_nonzero_bits
486 = (unsigned HOST_WIDE_INT
*) alloca (nregs
* sizeof (HOST_WIDE_INT
));
487 reg_last_set_sign_bit_copies
488 = (char *) alloca (nregs
* sizeof (char));
490 init_reg_last_arrays ();
492 init_recog_no_volatile ();
494 /* Compute maximum uid value so uid_cuid can be allocated. */
496 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
497 if (INSN_UID (insn
) > i
)
500 uid_cuid
= (int *) alloca ((i
+ 1) * sizeof (int));
503 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
505 /* Don't use reg_nonzero_bits when computing it. This can cause problems
506 when, for example, we have j <<= 1 in a loop. */
508 nonzero_sign_valid
= 0;
510 /* Compute the mapping from uids to cuids.
511 Cuids are numbers assigned to insns, like uids,
512 except that cuids increase monotonically through the code.
514 Scan all SETs and see if we can deduce anything about what
515 bits are known to be zero for some registers and how many copies
516 of the sign bit are known to exist for those registers.
518 Also set any known values so that we can use it while searching
519 for what bits are known to be set. */
523 /* We need to initialize it here, because record_dead_and_set_regs may call
525 subst_prev_insn
= NULL_RTX
;
527 setup_incoming_promotions ();
529 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
531 uid_cuid
[INSN_UID (insn
)] = ++i
;
535 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
537 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
);
538 record_dead_and_set_regs (insn
);
541 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
542 if (REG_NOTE_KIND (links
) == REG_INC
)
543 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
);
547 if (GET_CODE (insn
) == CODE_LABEL
)
551 nonzero_sign_valid
= 1;
553 /* Now scan all the insns in forward order. */
555 this_basic_block
= -1;
559 init_reg_last_arrays ();
560 setup_incoming_promotions ();
562 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
566 /* If INSN starts a new basic block, update our basic block number. */
567 if (this_basic_block
+ 1 < n_basic_blocks
568 && basic_block_head
[this_basic_block
+ 1] == insn
)
571 if (GET_CODE (insn
) == CODE_LABEL
)
574 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
576 /* Try this insn with each insn it links back to. */
578 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
579 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
)) != 0)
582 /* Try each sequence of three linked insns ending with this one. */
584 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
585 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
586 nextlinks
= XEXP (nextlinks
, 1))
587 if ((next
= try_combine (insn
, XEXP (links
, 0),
588 XEXP (nextlinks
, 0))) != 0)
592 /* Try to combine a jump insn that uses CC0
593 with a preceding insn that sets CC0, and maybe with its
594 logical predecessor as well.
595 This is how we make decrement-and-branch insns.
596 We need this special code because data flow connections
597 via CC0 do not get entered in LOG_LINKS. */
599 if (GET_CODE (insn
) == JUMP_INSN
600 && (prev
= prev_nonnote_insn (insn
)) != 0
601 && GET_CODE (prev
) == INSN
602 && sets_cc0_p (PATTERN (prev
)))
604 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
607 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
608 nextlinks
= XEXP (nextlinks
, 1))
609 if ((next
= try_combine (insn
, prev
,
610 XEXP (nextlinks
, 0))) != 0)
614 /* Do the same for an insn that explicitly references CC0. */
615 if (GET_CODE (insn
) == INSN
616 && (prev
= prev_nonnote_insn (insn
)) != 0
617 && GET_CODE (prev
) == INSN
618 && sets_cc0_p (PATTERN (prev
))
619 && GET_CODE (PATTERN (insn
)) == SET
620 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
622 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
625 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
626 nextlinks
= XEXP (nextlinks
, 1))
627 if ((next
= try_combine (insn
, prev
,
628 XEXP (nextlinks
, 0))) != 0)
632 /* Finally, see if any of the insns that this insn links to
633 explicitly references CC0. If so, try this insn, that insn,
634 and its predecessor if it sets CC0. */
635 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
636 if (GET_CODE (XEXP (links
, 0)) == INSN
637 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
638 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
639 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
640 && GET_CODE (prev
) == INSN
641 && sets_cc0_p (PATTERN (prev
))
642 && (next
= try_combine (insn
, XEXP (links
, 0), prev
)) != 0)
646 /* Try combining an insn with two different insns whose results it
648 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
649 for (nextlinks
= XEXP (links
, 1); nextlinks
;
650 nextlinks
= XEXP (nextlinks
, 1))
651 if ((next
= try_combine (insn
, XEXP (links
, 0),
652 XEXP (nextlinks
, 0))) != 0)
655 if (GET_CODE (insn
) != NOTE
)
656 record_dead_and_set_regs (insn
);
663 total_attempts
+= combine_attempts
;
664 total_merges
+= combine_merges
;
665 total_extras
+= combine_extras
;
666 total_successes
+= combine_successes
;
668 nonzero_sign_valid
= 0;
671 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
674 init_reg_last_arrays ()
676 int nregs
= combine_max_regno
;
678 bzero ((char *) reg_last_death
, nregs
* sizeof (rtx
));
679 bzero ((char *) reg_last_set
, nregs
* sizeof (rtx
));
680 bzero ((char *) reg_last_set_value
, nregs
* sizeof (rtx
));
681 bzero ((char *) reg_last_set_table_tick
, nregs
* sizeof (int));
682 bzero ((char *) reg_last_set_label
, nregs
* sizeof (int));
683 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
684 bzero ((char *) reg_last_set_mode
, nregs
* sizeof (enum machine_mode
));
685 bzero ((char *) reg_last_set_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
686 bzero (reg_last_set_sign_bit_copies
, nregs
* sizeof (char));
689 /* Set up any promoted values for incoming argument registers. */
692 setup_incoming_promotions ()
694 #ifdef PROMOTE_FUNCTION_ARGS
697 enum machine_mode mode
;
699 rtx first
= get_insns ();
701 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
702 if (FUNCTION_ARG_REGNO_P (regno
)
703 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
704 record_value_for_reg (reg
, first
,
705 gen_rtx (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
707 gen_rtx (CLOBBER
, mode
, const0_rtx
)));
711 /* Called via note_stores. If X is a pseudo that is narrower than
712 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
714 If we are setting only a portion of X and we can't figure out what
715 portion, assume all bits will be used since we don't know what will
718 Similarly, set how many bits of X are known to be copies of the sign bit
719 at all locations in the function. This is the smallest number implied
723 set_nonzero_bits_and_sign_copies (x
, set
)
729 if (GET_CODE (x
) == REG
730 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
731 /* If this register is undefined at the start of the file, we can't
732 say what its contents were. */
733 && ! (basic_block_live_at_start
[0][REGNO (x
) / REGSET_ELT_BITS
]
734 & ((REGSET_ELT_TYPE
) 1 << (REGNO (x
) % REGSET_ELT_BITS
)))
735 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
737 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
739 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
740 reg_sign_bit_copies
[REGNO (x
)] = 0;
744 /* If this is a complex assignment, see if we can convert it into a
745 simple assignment. */
746 set
= expand_field_assignment (set
);
748 /* If this is a simple assignment, or we have a paradoxical SUBREG,
749 set what we know about X. */
751 if (SET_DEST (set
) == x
752 || (GET_CODE (SET_DEST (set
)) == SUBREG
753 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
754 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
755 && SUBREG_REG (SET_DEST (set
)) == x
))
757 rtx src
= SET_SRC (set
);
759 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
760 /* If X is narrower than a word and SRC is a non-negative
761 constant that would appear negative in the mode of X,
762 sign-extend it for use in reg_nonzero_bits because some
763 machines (maybe most) will actually do the sign-extension
764 and this is the conservative approach.
766 ??? For 2.5, try to tighten up the MD files in this regard
767 instead of this kludge. */
769 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
770 && GET_CODE (src
) == CONST_INT
772 && 0 != (INTVAL (src
)
774 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
775 src
= GEN_INT (INTVAL (src
)
776 | ((HOST_WIDE_INT
) (-1)
777 << GET_MODE_BITSIZE (GET_MODE (x
))));
780 reg_nonzero_bits
[REGNO (x
)]
781 |= nonzero_bits (src
, nonzero_bits_mode
);
782 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
783 if (reg_sign_bit_copies
[REGNO (x
)] == 0
784 || reg_sign_bit_copies
[REGNO (x
)] > num
)
785 reg_sign_bit_copies
[REGNO (x
)] = num
;
789 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
790 reg_sign_bit_copies
[REGNO (x
)] = 0;
795 /* See if INSN can be combined into I3. PRED and SUCC are optionally
796 insns that were previously combined into I3 or that will be combined
797 into the merger of INSN and I3.
799 Return 0 if the combination is not allowed for any reason.
801 If the combination is allowed, *PDEST will be set to the single
802 destination of INSN and *PSRC to the single source, and this function
806 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
813 rtx set
= 0, src
, dest
;
815 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
816 && next_active_insn (succ
) == i3
)
817 : next_active_insn (insn
) == i3
);
819 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
820 or a PARALLEL consisting of such a SET and CLOBBERs.
822 If INSN has CLOBBER parallel parts, ignore them for our processing.
823 By definition, these happen during the execution of the insn. When it
824 is merged with another insn, all bets are off. If they are, in fact,
825 needed and aren't also supplied in I3, they may be added by
826 recog_for_combine. Otherwise, it won't match.
828 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
831 Get the source and destination of INSN. If more than one, can't
834 if (GET_CODE (PATTERN (insn
)) == SET
)
835 set
= PATTERN (insn
);
836 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
837 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
839 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
841 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
843 switch (GET_CODE (elt
))
845 /* We can ignore CLOBBERs. */
850 /* Ignore SETs whose result isn't used but not those that
851 have side-effects. */
852 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
853 && ! side_effects_p (elt
))
856 /* If we have already found a SET, this is a second one and
857 so we cannot combine with this insn. */
865 /* Anything else means we can't combine. */
871 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
872 so don't do anything with it. */
873 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
882 set
= expand_field_assignment (set
);
883 src
= SET_SRC (set
), dest
= SET_DEST (set
);
885 /* Don't eliminate a store in the stack pointer. */
886 if (dest
== stack_pointer_rtx
887 /* If we couldn't eliminate a field assignment, we can't combine. */
888 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
889 /* Don't combine with an insn that sets a register to itself if it has
890 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
891 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
892 /* Can't merge a function call. */
893 || GET_CODE (src
) == CALL
894 /* Don't eliminate a function call argument. */
895 || (GET_CODE (i3
) == CALL_INSN
896 && (find_reg_fusage (i3
, USE
, dest
)
897 || (GET_CODE (dest
) == REG
898 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
899 && global_regs
[REGNO (dest
)])))
900 /* Don't substitute into an incremented register. */
901 || FIND_REG_INC_NOTE (i3
, dest
)
902 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
903 /* Don't combine the end of a libcall into anything. */
904 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
905 /* Make sure that DEST is not used after SUCC but before I3. */
906 || (succ
&& ! all_adjacent
907 && reg_used_between_p (dest
, succ
, i3
))
908 /* Make sure that the value that is to be substituted for the register
909 does not use any registers whose values alter in between. However,
910 If the insns are adjacent, a use can't cross a set even though we
911 think it might (this can happen for a sequence of insns each setting
912 the same destination; reg_last_set of that register might point to
913 a NOTE). If INSN has a REG_EQUIV note, the register is always
914 equivalent to the memory so the substitution is valid even if there
915 are intervening stores. Also, don't move a volatile asm or
916 UNSPEC_VOLATILE across any other insns. */
918 && (((GET_CODE (src
) != MEM
919 || ! find_reg_note (insn
, REG_EQUIV
, src
))
920 && use_crosses_set_p (src
, INSN_CUID (insn
)))
921 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
922 || GET_CODE (src
) == UNSPEC_VOLATILE
))
923 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
924 better register allocation by not doing the combine. */
925 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
926 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
927 /* Don't combine across a CALL_INSN, because that would possibly
928 change whether the life span of some REGs crosses calls or not,
929 and it is a pain to update that information.
930 Exception: if source is a constant, moving it later can't hurt.
931 Accept that special case, because it helps -fforce-addr a lot. */
932 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
935 /* DEST must either be a REG or CC0. */
936 if (GET_CODE (dest
) == REG
)
938 /* If register alignment is being enforced for multi-word items in all
939 cases except for parameters, it is possible to have a register copy
940 insn referencing a hard register that is not allowed to contain the
941 mode being copied and which would not be valid as an operand of most
942 insns. Eliminate this problem by not combining with such an insn.
944 Also, on some machines we don't want to extend the life of a hard
947 if (GET_CODE (src
) == REG
948 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
949 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
950 /* Don't extend the life of a hard register unless it is
951 user variable (if we have few registers) or it can't
952 fit into the desired register (meaning something special
954 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
955 && (! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
))
956 #ifdef SMALL_REGISTER_CLASSES
957 || ! REG_USERVAR_P (src
)
962 else if (GET_CODE (dest
) != CC0
)
965 /* Don't substitute for a register intended as a clobberable operand.
966 Similarly, don't substitute an expression containing a register that
967 will be clobbered in I3. */
968 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
969 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
970 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
971 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
973 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
976 /* If INSN contains anything volatile, or is an `asm' (whether volatile
977 or not), reject, unless nothing volatile comes between it and I3,
978 with the exception of SUCC. */
980 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
981 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
982 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
983 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
986 /* If there are any volatile insns between INSN and I3, reject, because
987 they might affect machine state. */
989 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
990 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
991 && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
994 /* If INSN or I2 contains an autoincrement or autodecrement,
995 make sure that register is not used between there and I3,
996 and not already used in I3 either.
997 Also insist that I3 not be a jump; if it were one
998 and the incremented register were spilled, we would lose. */
1001 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1002 if (REG_NOTE_KIND (link
) == REG_INC
1003 && (GET_CODE (i3
) == JUMP_INSN
1004 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1005 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1010 /* Don't combine an insn that follows a CC0-setting insn.
1011 An insn that uses CC0 must not be separated from the one that sets it.
1012 We do, however, allow I2 to follow a CC0-setting insn if that insn
1013 is passed as I1; in that case it will be deleted also.
1014 We also allow combining in this case if all the insns are adjacent
1015 because that would leave the two CC0 insns adjacent as well.
1016 It would be more logical to test whether CC0 occurs inside I1 or I2,
1017 but that would be much slower, and this ought to be equivalent. */
1019 p
= prev_nonnote_insn (insn
);
1020 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1025 /* If we get here, we have passed all the tests and the combination is
1034 /* LOC is the location within I3 that contains its pattern or the component
1035 of a PARALLEL of the pattern. We validate that it is valid for combining.
1037 One problem is if I3 modifies its output, as opposed to replacing it
1038 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1039 so would produce an insn that is not equivalent to the original insns.
1043 (set (reg:DI 101) (reg:DI 100))
1044 (set (subreg:SI (reg:DI 101) 0) <foo>)
1046 This is NOT equivalent to:
1048 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1049 (set (reg:DI 101) (reg:DI 100))])
1051 Not only does this modify 100 (in which case it might still be valid
1052 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1054 We can also run into a problem if I2 sets a register that I1
1055 uses and I1 gets directly substituted into I3 (not via I2). In that
1056 case, we would be getting the wrong value of I2DEST into I3, so we
1057 must reject the combination. This case occurs when I2 and I1 both
1058 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1059 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1060 of a SET must prevent combination from occurring.
1062 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1063 if the destination of a SET is a hard register that isn't a user
1066 Before doing the above check, we first try to expand a field assignment
1067 into a set of logical operations.
1069 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1070 we place a register that is both set and used within I3. If more than one
1071 such register is detected, we fail.
1073 Return 1 if the combination is valid, zero otherwise. */
1076 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1082 rtx
*pi3dest_killed
;
1086 if (GET_CODE (x
) == SET
)
1088 rtx set
= expand_field_assignment (x
);
1089 rtx dest
= SET_DEST (set
);
1090 rtx src
= SET_SRC (set
);
1091 rtx inner_dest
= dest
, inner_src
= src
;
1095 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1096 || GET_CODE (inner_dest
) == SUBREG
1097 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1098 inner_dest
= XEXP (inner_dest
, 0);
1100 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1103 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1104 || GET_CODE (inner_src
) == SUBREG
1105 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1106 inner_src
= XEXP (inner_src
, 0);
1108 /* If it is better that two different modes keep two different pseudos,
1109 avoid combining them. This avoids producing the following pattern
1111 (set (subreg:SI (reg/v:QI 21) 0)
1112 (lshiftrt:SI (reg/v:SI 20)
1114 If that were made, reload could not handle the pair of
1115 reg 20/21, since it would try to get any GENERAL_REGS
1116 but some of them don't handle QImode. */
1118 if (rtx_equal_p (inner_src
, i2dest
)
1119 && GET_CODE (inner_dest
) == REG
1120 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1124 /* Check for the case where I3 modifies its output, as
1126 if ((inner_dest
!= dest
1127 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1128 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1129 /* This is the same test done in can_combine_p except that we
1130 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1132 || (GET_CODE (inner_dest
) == REG
1133 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1134 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1135 GET_MODE (inner_dest
))
1136 #ifdef SMALL_REGISTER_CLASSES
1137 || (GET_CODE (src
) != CALL
&& ! REG_USERVAR_P (inner_dest
))
1140 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1143 /* If DEST is used in I3, it is being killed in this insn,
1144 so record that for later.
1145 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1146 STACK_POINTER_REGNUM, since these are always considered to be
1147 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1148 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1149 && reg_referenced_p (dest
, PATTERN (i3
))
1150 && REGNO (dest
) != FRAME_POINTER_REGNUM
1151 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1152 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1154 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1155 && (REGNO (dest
) != ARG_POINTER_REGNUM
1156 || ! fixed_regs
[REGNO (dest
)])
1158 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1160 if (*pi3dest_killed
)
1163 *pi3dest_killed
= dest
;
1167 else if (GET_CODE (x
) == PARALLEL
)
1171 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1172 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1173 i1_not_in_src
, pi3dest_killed
))
1180 /* Try to combine the insns I1 and I2 into I3.
1181 Here I1 and I2 appear earlier than I3.
1182 I1 can be zero; then we combine just I2 into I3.
1184 It we are combining three insns and the resulting insn is not recognized,
1185 try splitting it into two insns. If that happens, I2 and I3 are retained
1186 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1189 Return 0 if the combination does not work. Then nothing is changed.
1190 If we did the combination, return the insn at which combine should
1194 try_combine (i3
, i2
, i1
)
1195 register rtx i3
, i2
, i1
;
1197 /* New patterns for I3 and I3, respectively. */
1198 rtx newpat
, newi2pat
= 0;
1199 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1200 int added_sets_1
, added_sets_2
;
1201 /* Total number of SETs to put into I3. */
1203 /* Nonzero is I2's body now appears in I3. */
1205 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1206 int insn_code_number
, i2_code_number
, other_code_number
;
1207 /* Contains I3 if the destination of I3 is used in its source, which means
1208 that the old life of I3 is being killed. If that usage is placed into
1209 I2 and not in I3, a REG_DEAD note must be made. */
1210 rtx i3dest_killed
= 0;
1211 /* SET_DEST and SET_SRC of I2 and I1. */
1212 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1213 /* PATTERN (I2), or a copy of it in certain cases. */
1215 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1216 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1217 int i1_feeds_i3
= 0;
1218 /* Notes that must be added to REG_NOTES in I3 and I2. */
1219 rtx new_i3_notes
, new_i2_notes
;
1220 /* Notes that we substituted I3 into I2 instead of the normal case. */
1221 int i3_subst_into_i2
= 0;
1222 /* Notes that I1, I2 or I3 is a MULT operation. */
1224 /* Number of clobbers of SCRATCH we had to add. */
1225 int i3_scratches
= 0, i2_scratches
= 0, other_scratches
= 0;
1232 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1233 This can occur when flow deletes an insn that it has merged into an
1234 auto-increment address. We also can't do anything if I3 has a
1235 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1238 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1239 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1240 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1241 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
))
1246 undobuf
.num_undo
= previous_num_undos
= 0;
1247 undobuf
.other_insn
= 0;
1249 /* Save the current high-water-mark so we can free storage if we didn't
1250 accept this combination. */
1251 undobuf
.storage
= (char *) oballoc (0);
1253 /* Reset the hard register usage information. */
1254 CLEAR_HARD_REG_SET (newpat_used_regs
);
1256 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1257 code below, set I1 to be the earlier of the two insns. */
1258 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1259 temp
= i1
, i1
= i2
, i2
= temp
;
1261 added_links_insn
= 0;
1263 /* First check for one important special-case that the code below will
1264 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1265 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1266 we may be able to replace that destination with the destination of I3.
1267 This occurs in the common code where we compute both a quotient and
1268 remainder into a structure, in which case we want to do the computation
1269 directly into the structure to avoid register-register copies.
1271 We make very conservative checks below and only try to handle the
1272 most common cases of this. For example, we only handle the case
1273 where I2 and I3 are adjacent to avoid making difficult register
1276 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1277 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1278 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1279 #ifdef SMALL_REGISTER_CLASSES
1280 && (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1281 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1282 || REG_USERVAR_P (SET_DEST (PATTERN (i3
))))
1284 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1285 && GET_CODE (PATTERN (i2
)) == PARALLEL
1286 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1287 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1288 below would need to check what is inside (and reg_overlap_mentioned_p
1289 doesn't support those codes anyway). Don't allow those destinations;
1290 the resulting insn isn't likely to be recognized anyway. */
1291 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1292 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1293 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1294 SET_DEST (PATTERN (i3
)))
1295 && next_real_insn (i2
) == i3
)
1297 rtx p2
= PATTERN (i2
);
1299 /* Make sure that the destination of I3,
1300 which we are going to substitute into one output of I2,
1301 is not used within another output of I2. We must avoid making this:
1302 (parallel [(set (mem (reg 69)) ...)
1303 (set (reg 69) ...)])
1304 which is not well-defined as to order of actions.
1305 (Besides, reload can't handle output reloads for this.)
1307 The problem can also happen if the dest of I3 is a memory ref,
1308 if another dest in I2 is an indirect memory ref. */
1309 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1310 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1311 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1312 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1313 SET_DEST (XVECEXP (p2
, 0, i
))))
1316 if (i
== XVECLEN (p2
, 0))
1317 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1318 if (SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1323 subst_low_cuid
= INSN_CUID (i2
);
1325 added_sets_2
= added_sets_1
= 0;
1326 i2dest
= SET_SRC (PATTERN (i3
));
1328 /* Replace the dest in I2 with our dest and make the resulting
1329 insn the new pattern for I3. Then skip to where we
1330 validate the pattern. Everything was set up above. */
1331 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1332 SET_DEST (PATTERN (i3
)));
1335 i3_subst_into_i2
= 1;
1336 goto validate_replacement
;
1341 /* If we have no I1 and I2 looks like:
1342 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1344 make up a dummy I1 that is
1347 (set (reg:CC X) (compare:CC Y (const_int 0)))
1349 (We can ignore any trailing CLOBBERs.)
1351 This undoes a previous combination and allows us to match a branch-and-
1354 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1355 && XVECLEN (PATTERN (i2
), 0) >= 2
1356 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1357 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1359 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1360 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1361 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1362 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1363 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1364 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1366 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1367 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1372 /* We make I1 with the same INSN_UID as I2. This gives it
1373 the same INSN_CUID for value tracking. Our fake I1 will
1374 never appear in the insn stream so giving it the same INSN_UID
1375 as I2 will not cause a problem. */
1377 subst_prev_insn
= i1
1378 = gen_rtx (INSN
, VOIDmode
, INSN_UID (i2
), 0, i2
,
1379 XVECEXP (PATTERN (i2
), 0, 1), -1, 0, 0);
1381 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1382 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1383 SET_DEST (PATTERN (i1
)));
1388 /* Verify that I2 and I1 are valid for combining. */
1389 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1390 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1396 /* Record whether I2DEST is used in I2SRC and similarly for the other
1397 cases. Knowing this will help in register status updating below. */
1398 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1399 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1400 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1402 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1404 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1406 /* Ensure that I3's pattern can be the destination of combines. */
1407 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1408 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1415 /* See if any of the insns is a MULT operation. Unless one is, we will
1416 reject a combination that is, since it must be slower. Be conservative
1418 if (GET_CODE (i2src
) == MULT
1419 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1420 || (GET_CODE (PATTERN (i3
)) == SET
1421 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1424 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1425 We used to do this EXCEPT in one case: I3 has a post-inc in an
1426 output operand. However, that exception can give rise to insns like
1428 which is a famous insn on the PDP-11 where the value of r3 used as the
1429 source was model-dependent. Avoid this sort of thing. */
1432 if (!(GET_CODE (PATTERN (i3
)) == SET
1433 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1434 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1435 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1436 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1437 /* It's not the exception. */
1440 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1441 if (REG_NOTE_KIND (link
) == REG_INC
1442 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1444 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1451 /* See if the SETs in I1 or I2 need to be kept around in the merged
1452 instruction: whenever the value set there is still needed past I3.
1453 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1455 For the SET in I1, we have two cases: If I1 and I2 independently
1456 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1457 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1458 in I1 needs to be kept around unless I1DEST dies or is set in either
1459 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1460 I1DEST. If so, we know I1 feeds into I2. */
1462 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1465 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1466 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1468 /* If the set in I2 needs to be kept around, we must make a copy of
1469 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1470 PATTERN (I2), we are only substituting for the original I1DEST, not into
1471 an already-substituted copy. This also prevents making self-referential
1472 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1475 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1476 ? gen_rtx (SET
, VOIDmode
, i2dest
, i2src
)
1480 i2pat
= copy_rtx (i2pat
);
1484 /* Substitute in the latest insn for the regs set by the earlier ones. */
1486 maxreg
= max_reg_num ();
1490 /* It is possible that the source of I2 or I1 may be performing an
1491 unneeded operation, such as a ZERO_EXTEND of something that is known
1492 to have the high part zero. Handle that case by letting subst look at
1493 the innermost one of them.
1495 Another way to do this would be to have a function that tries to
1496 simplify a single insn instead of merging two or more insns. We don't
1497 do this because of the potential of infinite loops and because
1498 of the potential extra memory required. However, doing it the way
1499 we are is a bit of a kludge and doesn't catch all cases.
1501 But only do this if -fexpensive-optimizations since it slows things down
1502 and doesn't usually win. */
1504 if (flag_expensive_optimizations
)
1506 /* Pass pc_rtx so no substitutions are done, just simplifications.
1507 The cases that we are interested in here do not involve the few
1508 cases were is_replaced is checked. */
1511 subst_low_cuid
= INSN_CUID (i1
);
1512 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1516 subst_low_cuid
= INSN_CUID (i2
);
1517 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1520 previous_num_undos
= undobuf
.num_undo
;
1524 /* Many machines that don't use CC0 have insns that can both perform an
1525 arithmetic operation and set the condition code. These operations will
1526 be represented as a PARALLEL with the first element of the vector
1527 being a COMPARE of an arithmetic operation with the constant zero.
1528 The second element of the vector will set some pseudo to the result
1529 of the same arithmetic operation. If we simplify the COMPARE, we won't
1530 match such a pattern and so will generate an extra insn. Here we test
1531 for this case, where both the comparison and the operation result are
1532 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1533 I2SRC. Later we will make the PARALLEL that contains I2. */
1535 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1536 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1537 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1538 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1541 enum machine_mode compare_mode
;
1543 newpat
= PATTERN (i3
);
1544 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1548 #ifdef EXTRA_CC_MODES
1549 /* See if a COMPARE with the operand we substituted in should be done
1550 with the mode that is currently being used. If not, do the same
1551 processing we do in `subst' for a SET; namely, if the destination
1552 is used only once, try to replace it with a register of the proper
1553 mode and also replace the COMPARE. */
1554 if (undobuf
.other_insn
== 0
1555 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1556 &undobuf
.other_insn
))
1557 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1559 != GET_MODE (SET_DEST (newpat
))))
1561 int regno
= REGNO (SET_DEST (newpat
));
1562 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
1564 if (regno
< FIRST_PSEUDO_REGISTER
1565 || (reg_n_sets
[regno
] == 1 && ! added_sets_2
1566 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1568 if (regno
>= FIRST_PSEUDO_REGISTER
)
1569 SUBST (regno_reg_rtx
[regno
], new_dest
);
1571 SUBST (SET_DEST (newpat
), new_dest
);
1572 SUBST (XEXP (*cc_use
, 0), new_dest
);
1573 SUBST (SET_SRC (newpat
),
1574 gen_rtx_combine (COMPARE
, compare_mode
,
1575 i2src
, const0_rtx
));
1578 undobuf
.other_insn
= 0;
1585 n_occurrences
= 0; /* `subst' counts here */
1587 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1588 need to make a unique copy of I2SRC each time we substitute it
1589 to avoid self-referential rtl. */
1591 subst_low_cuid
= INSN_CUID (i2
);
1592 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1593 ! i1_feeds_i3
&& i1dest_in_i1src
);
1594 previous_num_undos
= undobuf
.num_undo
;
1596 /* Record whether i2's body now appears within i3's body. */
1597 i2_is_used
= n_occurrences
;
1600 /* If we already got a failure, don't try to do more. Otherwise,
1601 try to substitute in I1 if we have it. */
1603 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1605 /* Before we can do this substitution, we must redo the test done
1606 above (see detailed comments there) that ensures that I1DEST
1607 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1609 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1617 subst_low_cuid
= INSN_CUID (i1
);
1618 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1619 previous_num_undos
= undobuf
.num_undo
;
1622 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1623 to count all the ways that I2SRC and I1SRC can be used. */
1624 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1625 && i2_is_used
+ added_sets_2
> 1)
1626 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1627 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1629 /* Fail if we tried to make a new register (we used to abort, but there's
1630 really no reason to). */
1631 || max_reg_num () != maxreg
1632 /* Fail if we couldn't do something and have a CLOBBER. */
1633 || GET_CODE (newpat
) == CLOBBER
1634 /* Fail if this new pattern is a MULT and we didn't have one before
1635 at the outer level. */
1636 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1643 /* If the actions of the earlier insns must be kept
1644 in addition to substituting them into the latest one,
1645 we must make a new PARALLEL for the latest insn
1646 to hold additional the SETs. */
1648 if (added_sets_1
|| added_sets_2
)
1652 if (GET_CODE (newpat
) == PARALLEL
)
1654 rtvec old
= XVEC (newpat
, 0);
1655 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1656 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1657 bcopy ((char *) &old
->elem
[0], (char *) &XVECEXP (newpat
, 0, 0),
1658 sizeof (old
->elem
[0]) * old
->num_elem
);
1663 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1664 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1665 XVECEXP (newpat
, 0, 0) = old
;
1669 XVECEXP (newpat
, 0, --total_sets
)
1670 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1671 ? gen_rtx (SET
, VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1675 /* If there is no I1, use I2's body as is. We used to also not do
1676 the subst call below if I2 was substituted into I3,
1677 but that could lose a simplification. */
1679 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1681 /* See comment where i2pat is assigned. */
1682 XVECEXP (newpat
, 0, --total_sets
)
1683 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1687 /* We come here when we are replacing a destination in I2 with the
1688 destination of I3. */
1689 validate_replacement
:
1691 /* Note which hard regs this insn has as inputs. */
1692 mark_used_regs_combine (newpat
);
1694 /* Is the result of combination a valid instruction? */
1696 = recog_for_combine (&newpat
, i3
, &new_i3_notes
, &i3_scratches
);
1698 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1699 the second SET's destination is a register that is unused. In that case,
1700 we just need the first SET. This can occur when simplifying a divmod
1701 insn. We *must* test for this case here because the code below that
1702 splits two independent SETs doesn't handle this case correctly when it
1703 updates the register status. Also check the case where the first
1704 SET's destination is unused. That would not cause incorrect code, but
1705 does cause an unneeded insn to remain. */
1707 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1708 && XVECLEN (newpat
, 0) == 2
1709 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1710 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1711 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
1712 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
1713 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
1714 && asm_noperands (newpat
) < 0)
1716 newpat
= XVECEXP (newpat
, 0, 0);
1718 = recog_for_combine (&newpat
, i3
, &new_i3_notes
, &i3_scratches
);
1721 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1722 && XVECLEN (newpat
, 0) == 2
1723 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1724 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1725 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
1726 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
1727 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
1728 && asm_noperands (newpat
) < 0)
1730 newpat
= XVECEXP (newpat
, 0, 1);
1732 = recog_for_combine (&newpat
, i3
, &new_i3_notes
, &i3_scratches
);
1735 /* If we were combining three insns and the result is a simple SET
1736 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1737 insns. There are two ways to do this. It can be split using a
1738 machine-specific method (like when you have an addition of a large
1739 constant) or by combine in the function find_split_point. */
1741 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
1742 && asm_noperands (newpat
) < 0)
1744 rtx m_split
, *split
;
1745 rtx ni2dest
= i2dest
;
1747 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1748 use I2DEST as a scratch register will help. In the latter case,
1749 convert I2DEST to the mode of the source of NEWPAT if we can. */
1751 m_split
= split_insns (newpat
, i3
);
1753 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1754 inputs of NEWPAT. */
1756 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1757 possible to try that as a scratch reg. This would require adding
1758 more code to make it work though. */
1760 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
1762 /* If I2DEST is a hard register or the only use of a pseudo,
1763 we can change its mode. */
1764 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
1765 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
1766 && GET_CODE (i2dest
) == REG
1767 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1768 || (reg_n_sets
[REGNO (i2dest
)] == 1 && ! added_sets_2
1769 && ! REG_USERVAR_P (i2dest
))))
1770 ni2dest
= gen_rtx (REG
, GET_MODE (SET_DEST (newpat
)),
1773 m_split
= split_insns (gen_rtx (PARALLEL
, VOIDmode
,
1774 gen_rtvec (2, newpat
,
1781 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
1782 && XVECLEN (m_split
, 0) == 2
1783 && (next_real_insn (i2
) == i3
1784 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
1788 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
1789 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
1791 i3set
= single_set (XVECEXP (m_split
, 0, 1));
1792 i2set
= single_set (XVECEXP (m_split
, 0, 0));
1794 /* In case we changed the mode of I2DEST, replace it in the
1795 pseudo-register table here. We can't do it above in case this
1796 code doesn't get executed and we do a split the other way. */
1798 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1799 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
1801 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
,
1804 /* If I2 or I3 has multiple SETs, we won't know how to track
1805 register status, so don't use these insns. */
1807 if (i2_code_number
>= 0 && i2set
&& i3set
)
1808 insn_code_number
= recog_for_combine (&newi3pat
, i3
, &new_i3_notes
,
1810 if (insn_code_number
>= 0)
1813 /* It is possible that both insns now set the destination of I3.
1814 If so, we must show an extra use of it. */
1816 if (insn_code_number
>= 0)
1818 rtx new_i3_dest
= SET_DEST (i3set
);
1819 rtx new_i2_dest
= SET_DEST (i2set
);
1821 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
1822 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
1823 || GET_CODE (new_i3_dest
) == SUBREG
)
1824 new_i3_dest
= XEXP (new_i3_dest
, 0);
1826 if (GET_CODE (new_i3_dest
) == REG
1827 && GET_CODE (new_i2_dest
) == REG
1828 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
1829 reg_n_sets
[REGNO (SET_DEST (i2set
))]++;
1833 /* If we can split it and use I2DEST, go ahead and see if that
1834 helps things be recognized. Verify that none of the registers
1835 are set between I2 and I3. */
1836 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
1838 && GET_CODE (i2dest
) == REG
1840 /* We need I2DEST in the proper mode. If it is a hard register
1841 or the only use of a pseudo, we can change its mode. */
1842 && (GET_MODE (*split
) == GET_MODE (i2dest
)
1843 || GET_MODE (*split
) == VOIDmode
1844 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1845 || (reg_n_sets
[REGNO (i2dest
)] == 1 && ! added_sets_2
1846 && ! REG_USERVAR_P (i2dest
)))
1847 && (next_real_insn (i2
) == i3
1848 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
1849 /* We can't overwrite I2DEST if its value is still used by
1851 && ! reg_referenced_p (i2dest
, newpat
))
1853 rtx newdest
= i2dest
;
1854 enum rtx_code split_code
= GET_CODE (*split
);
1855 enum machine_mode split_mode
= GET_MODE (*split
);
1857 /* Get NEWDEST as a register in the proper mode. We have already
1858 validated that we can do this. */
1859 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
1861 newdest
= gen_rtx (REG
, split_mode
, REGNO (i2dest
));
1863 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1864 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
1867 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1868 an ASHIFT. This can occur if it was inside a PLUS and hence
1869 appeared to be a memory address. This is a kludge. */
1870 if (split_code
== MULT
1871 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
1872 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
1874 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
1875 XEXP (*split
, 0), GEN_INT (i
)));
1876 /* Update split_code because we may not have a multiply
1878 split_code
= GET_CODE (*split
);
1881 #ifdef INSN_SCHEDULING
1882 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1883 be written as a ZERO_EXTEND. */
1884 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
1885 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
1889 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
1890 SUBST (*split
, newdest
);
1892 = recog_for_combine (&newi2pat
, i2
, &new_i2_notes
, &i2_scratches
);
1894 /* If the split point was a MULT and we didn't have one before,
1895 don't use one now. */
1896 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
1898 = recog_for_combine (&newpat
, i3
, &new_i3_notes
, &i3_scratches
);
1902 /* Check for a case where we loaded from memory in a narrow mode and
1903 then sign extended it, but we need both registers. In that case,
1904 we have a PARALLEL with both loads from the same memory location.
1905 We can split this into a load from memory followed by a register-register
1906 copy. This saves at least one insn, more if register allocation can
1909 We cannot do this if the destination of the second assignment is
1910 a register that we have already assumed is zero-extended. Similarly
1911 for a SUBREG of such a register. */
1913 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
1914 && GET_CODE (newpat
) == PARALLEL
1915 && XVECLEN (newpat
, 0) == 2
1916 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1917 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
1918 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1919 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1920 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
1921 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1923 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
1924 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
1925 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
1926 (GET_CODE (temp
) == REG
1927 && reg_nonzero_bits
[REGNO (temp
)] != 0
1928 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
1929 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
1930 && (reg_nonzero_bits
[REGNO (temp
)]
1931 != GET_MODE_MASK (word_mode
))))
1932 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
1933 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
1934 (GET_CODE (temp
) == REG
1935 && reg_nonzero_bits
[REGNO (temp
)] != 0
1936 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
1937 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
1938 && (reg_nonzero_bits
[REGNO (temp
)]
1939 != GET_MODE_MASK (word_mode
)))))
1940 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
1941 SET_SRC (XVECEXP (newpat
, 0, 1)))
1942 && ! find_reg_note (i3
, REG_UNUSED
,
1943 SET_DEST (XVECEXP (newpat
, 0, 0))))
1947 newi2pat
= XVECEXP (newpat
, 0, 0);
1948 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
1949 newpat
= XVECEXP (newpat
, 0, 1);
1950 SUBST (SET_SRC (newpat
),
1951 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
1953 = recog_for_combine (&newi2pat
, i2
, &new_i2_notes
, &i2_scratches
);
1955 if (i2_code_number
>= 0)
1957 = recog_for_combine (&newpat
, i3
, &new_i3_notes
, &i3_scratches
);
1959 if (insn_code_number
>= 0)
1964 /* If we will be able to accept this, we have made a change to the
1965 destination of I3. This can invalidate a LOG_LINKS pointing
1966 to I3. No other part of combine.c makes such a transformation.
1968 The new I3 will have a destination that was previously the
1969 destination of I1 or I2 and which was used in i2 or I3. Call
1970 distribute_links to make a LOG_LINK from the next use of
1971 that destination. */
1973 PATTERN (i3
) = newpat
;
1974 distribute_links (gen_rtx (INSN_LIST
, VOIDmode
, i3
, NULL_RTX
));
1976 /* I3 now uses what used to be its destination and which is
1977 now I2's destination. That means we need a LOG_LINK from
1978 I3 to I2. But we used to have one, so we still will.
1980 However, some later insn might be using I2's dest and have
1981 a LOG_LINK pointing at I3. We must remove this link.
1982 The simplest way to remove the link is to point it at I1,
1983 which we know will be a NOTE. */
1985 for (insn
= NEXT_INSN (i3
);
1986 insn
&& (this_basic_block
== n_basic_blocks
- 1
1987 || insn
!= basic_block_head
[this_basic_block
+ 1]);
1988 insn
= NEXT_INSN (insn
))
1990 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1991 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
1993 for (link
= LOG_LINKS (insn
); link
;
1994 link
= XEXP (link
, 1))
1995 if (XEXP (link
, 0) == i3
)
1996 XEXP (link
, 0) = i1
;
2004 /* Similarly, check for a case where we have a PARALLEL of two independent
2005 SETs but we started with three insns. In this case, we can do the sets
2006 as two separate insns. This case occurs when some SET allows two
2007 other insns to combine, but the destination of that SET is still live. */
2009 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2010 && GET_CODE (newpat
) == PARALLEL
2011 && XVECLEN (newpat
, 0) == 2
2012 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2013 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2014 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2015 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2016 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2017 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2018 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2020 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2021 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2022 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2023 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2024 XVECEXP (newpat
, 0, 0))
2025 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2026 XVECEXP (newpat
, 0, 1)))
2028 newi2pat
= XVECEXP (newpat
, 0, 1);
2029 newpat
= XVECEXP (newpat
, 0, 0);
2032 = recog_for_combine (&newi2pat
, i2
, &new_i2_notes
, &i2_scratches
);
2034 if (i2_code_number
>= 0)
2036 = recog_for_combine (&newpat
, i3
, &new_i3_notes
, &i3_scratches
);
2039 /* If it still isn't recognized, fail and change things back the way they
2041 if ((insn_code_number
< 0
2042 /* Is the result a reasonable ASM_OPERANDS? */
2043 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2049 /* If we had to change another insn, make sure it is valid also. */
2050 if (undobuf
.other_insn
)
2052 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2053 rtx new_other_notes
;
2056 CLEAR_HARD_REG_SET (newpat_used_regs
);
2059 = recog_for_combine (&other_pat
, undobuf
.other_insn
,
2060 &new_other_notes
, &other_scratches
);
2062 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2068 PATTERN (undobuf
.other_insn
) = other_pat
;
2070 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2071 are still valid. Then add any non-duplicate notes added by
2072 recog_for_combine. */
2073 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2075 next
= XEXP (note
, 1);
2077 if (REG_NOTE_KIND (note
) == REG_UNUSED
2078 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2080 if (GET_CODE (XEXP (note
, 0)) == REG
)
2081 reg_n_deaths
[REGNO (XEXP (note
, 0))]--;
2083 remove_note (undobuf
.other_insn
, note
);
2087 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2088 if (GET_CODE (XEXP (note
, 0)) == REG
)
2089 reg_n_deaths
[REGNO (XEXP (note
, 0))]++;
2091 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2092 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2095 /* We now know that we can do this combination. Merge the insns and
2096 update the status of registers and LOG_LINKS. */
2099 rtx i3notes
, i2notes
, i1notes
= 0;
2100 rtx i3links
, i2links
, i1links
= 0;
2103 /* Compute which registers we expect to eliminate. */
2104 rtx elim_i2
= (newi2pat
|| i2dest_in_i2src
|| i2dest_in_i1src
2106 rtx elim_i1
= i1
== 0 || i1dest_in_i1src
? 0 : i1dest
;
2108 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2110 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2111 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2113 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2115 /* Ensure that we do not have something that should not be shared but
2116 occurs multiple times in the new insns. Check this by first
2117 resetting all the `used' flags and then copying anything is shared. */
2119 reset_used_flags (i3notes
);
2120 reset_used_flags (i2notes
);
2121 reset_used_flags (i1notes
);
2122 reset_used_flags (newpat
);
2123 reset_used_flags (newi2pat
);
2124 if (undobuf
.other_insn
)
2125 reset_used_flags (PATTERN (undobuf
.other_insn
));
2127 i3notes
= copy_rtx_if_shared (i3notes
);
2128 i2notes
= copy_rtx_if_shared (i2notes
);
2129 i1notes
= copy_rtx_if_shared (i1notes
);
2130 newpat
= copy_rtx_if_shared (newpat
);
2131 newi2pat
= copy_rtx_if_shared (newi2pat
);
2132 if (undobuf
.other_insn
)
2133 reset_used_flags (PATTERN (undobuf
.other_insn
));
2135 INSN_CODE (i3
) = insn_code_number
;
2136 PATTERN (i3
) = newpat
;
2137 if (undobuf
.other_insn
)
2138 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2140 /* We had one special case above where I2 had more than one set and
2141 we replaced a destination of one of those sets with the destination
2142 of I3. In that case, we have to update LOG_LINKS of insns later
2143 in this basic block. Note that this (expensive) case is rare.
2145 Also, in this case, we must pretend that all REG_NOTEs for I2
2146 actually came from I3, so that REG_UNUSED notes from I2 will be
2147 properly handled. */
2149 if (i3_subst_into_i2
)
2151 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2152 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2153 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2154 && ! find_reg_note (i2
, REG_UNUSED
,
2155 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2156 for (temp
= NEXT_INSN (i2
);
2157 temp
&& (this_basic_block
== n_basic_blocks
- 1
2158 || basic_block_head
[this_basic_block
] != temp
);
2159 temp
= NEXT_INSN (temp
))
2160 if (temp
!= i3
&& GET_RTX_CLASS (GET_CODE (temp
)) == 'i')
2161 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2162 if (XEXP (link
, 0) == i2
)
2163 XEXP (link
, 0) = i3
;
2168 while (XEXP (link
, 1))
2169 link
= XEXP (link
, 1);
2170 XEXP (link
, 1) = i2notes
;
2184 INSN_CODE (i2
) = i2_code_number
;
2185 PATTERN (i2
) = newi2pat
;
2189 PUT_CODE (i2
, NOTE
);
2190 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2191 NOTE_SOURCE_FILE (i2
) = 0;
2198 PUT_CODE (i1
, NOTE
);
2199 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2200 NOTE_SOURCE_FILE (i1
) = 0;
2203 /* Get death notes for everything that is now used in either I3 or
2204 I2 and used to die in a previous insn. */
2206 move_deaths (newpat
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
), i3
, &midnotes
);
2208 move_deaths (newi2pat
, INSN_CUID (i1
), i2
, &midnotes
);
2210 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2212 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2215 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2218 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2221 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2224 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2225 know these are REG_UNUSED and want them to go to the desired insn,
2226 so we always pass it as i3. We have not counted the notes in
2227 reg_n_deaths yet, so we need to do so now. */
2229 if (newi2pat
&& new_i2_notes
)
2231 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2232 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2233 reg_n_deaths
[REGNO (XEXP (temp
, 0))]++;
2235 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2240 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2241 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2242 reg_n_deaths
[REGNO (XEXP (temp
, 0))]++;
2244 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2247 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2248 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2249 Show an additional death due to the REG_DEAD note we make here. If
2250 we discard it in distribute_notes, we will decrement it again. */
2254 if (GET_CODE (i3dest_killed
) == REG
)
2255 reg_n_deaths
[REGNO (i3dest_killed
)]++;
2257 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i3dest_killed
,
2259 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2260 NULL_RTX
, NULL_RTX
);
2263 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2264 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2265 we passed I3 in that case, it might delete I2. */
2267 if (i2dest_in_i2src
)
2269 if (GET_CODE (i2dest
) == REG
)
2270 reg_n_deaths
[REGNO (i2dest
)]++;
2272 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2273 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i2dest
, NULL_RTX
),
2274 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2276 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i2dest
, NULL_RTX
),
2277 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2278 NULL_RTX
, NULL_RTX
);
2281 if (i1dest_in_i1src
)
2283 if (GET_CODE (i1dest
) == REG
)
2284 reg_n_deaths
[REGNO (i1dest
)]++;
2286 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2287 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i1dest
, NULL_RTX
),
2288 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2290 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i1dest
, NULL_RTX
),
2291 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2292 NULL_RTX
, NULL_RTX
);
2295 distribute_links (i3links
);
2296 distribute_links (i2links
);
2297 distribute_links (i1links
);
2299 if (GET_CODE (i2dest
) == REG
)
2302 rtx i2_insn
= 0, i2_val
= 0, set
;
2304 /* The insn that used to set this register doesn't exist, and
2305 this life of the register may not exist either. See if one of
2306 I3's links points to an insn that sets I2DEST. If it does,
2307 that is now the last known value for I2DEST. If we don't update
2308 this and I2 set the register to a value that depended on its old
2309 contents, we will get confused. If this insn is used, thing
2310 will be set correctly in combine_instructions. */
2312 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2313 if ((set
= single_set (XEXP (link
, 0))) != 0
2314 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2315 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2317 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2319 /* If the reg formerly set in I2 died only once and that was in I3,
2320 zero its use count so it won't make `reload' do any work. */
2321 if (! added_sets_2
&& newi2pat
== 0 && ! i2dest_in_i2src
)
2323 regno
= REGNO (i2dest
);
2324 reg_n_sets
[regno
]--;
2325 if (reg_n_sets
[regno
] == 0
2326 && ! (basic_block_live_at_start
[0][regno
/ REGSET_ELT_BITS
]
2327 & ((REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
))))
2328 reg_n_refs
[regno
] = 0;
2332 if (i1
&& GET_CODE (i1dest
) == REG
)
2335 rtx i1_insn
= 0, i1_val
= 0, set
;
2337 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2338 if ((set
= single_set (XEXP (link
, 0))) != 0
2339 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2340 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2342 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2344 regno
= REGNO (i1dest
);
2345 if (! added_sets_1
&& ! i1dest_in_i1src
)
2347 reg_n_sets
[regno
]--;
2348 if (reg_n_sets
[regno
] == 0
2349 && ! (basic_block_live_at_start
[0][regno
/ REGSET_ELT_BITS
]
2350 & ((REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
))))
2351 reg_n_refs
[regno
] = 0;
2355 /* Update reg_nonzero_bits et al for any changes that may have been made
2358 note_stores (newpat
, set_nonzero_bits_and_sign_copies
);
2360 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
);
2362 /* If we added any (clobber (scratch)), add them to the max for a
2363 block. This is a very pessimistic calculation, since we might
2364 have had them already and this might not be the worst block, but
2365 it's not worth doing any better. */
2366 max_scratch
+= i3_scratches
+ i2_scratches
+ other_scratches
;
2368 /* If I3 is now an unconditional jump, ensure that it has a
2369 BARRIER following it since it may have initially been a
2370 conditional jump. It may also be the last nonnote insn. */
2372 if ((GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
2373 && ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2374 || GET_CODE (temp
) != BARRIER
))
2375 emit_barrier_after (i3
);
2378 combine_successes
++;
2380 /* Clear this here, so that subsequent get_last_value calls are not
2382 subst_prev_insn
= NULL_RTX
;
2384 if (added_links_insn
2385 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2386 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2387 return added_links_insn
;
2389 return newi2pat
? i2
: i3
;
2392 /* Undo all the modifications recorded in undobuf. */
2398 if (undobuf
.num_undo
> MAX_UNDO
)
2399 undobuf
.num_undo
= MAX_UNDO
;
2400 for (i
= undobuf
.num_undo
- 1; i
>= 0; i
--)
2402 if (undobuf
.undo
[i
].is_int
)
2403 *undobuf
.undo
[i
].where
.i
= undobuf
.undo
[i
].old_contents
.i
;
2405 *undobuf
.undo
[i
].where
.r
= undobuf
.undo
[i
].old_contents
.r
;
2409 obfree (undobuf
.storage
);
2410 undobuf
.num_undo
= 0;
2412 /* Clear this here, so that subsequent get_last_value calls are not
2414 subst_prev_insn
= NULL_RTX
;
2417 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2418 where we have an arithmetic expression and return that point. LOC will
2421 try_combine will call this function to see if an insn can be split into
2425 find_split_point (loc
, insn
)
2430 enum rtx_code code
= GET_CODE (x
);
2432 int len
= 0, pos
, unsignedp
;
2435 /* First special-case some codes. */
2439 #ifdef INSN_SCHEDULING
2440 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2442 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2445 return find_split_point (&SUBREG_REG (x
), insn
);
2449 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2450 using LO_SUM and HIGH. */
2451 if (GET_CODE (XEXP (x
, 0)) == CONST
2452 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2455 gen_rtx_combine (LO_SUM
, Pmode
,
2456 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2458 return &XEXP (XEXP (x
, 0), 0);
2462 /* If we have a PLUS whose second operand is a constant and the
2463 address is not valid, perhaps will can split it up using
2464 the machine-specific way to split large constants. We use
2465 the first pseudo-reg (one of the virtual regs) as a placeholder;
2466 it will not remain in the result. */
2467 if (GET_CODE (XEXP (x
, 0)) == PLUS
2468 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2469 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2471 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2472 rtx seq
= split_insns (gen_rtx (SET
, VOIDmode
, reg
, XEXP (x
, 0)),
2475 /* This should have produced two insns, each of which sets our
2476 placeholder. If the source of the second is a valid address,
2477 we can make put both sources together and make a split point
2480 if (seq
&& XVECLEN (seq
, 0) == 2
2481 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2482 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2483 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2484 && ! reg_mentioned_p (reg
,
2485 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2486 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2487 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2488 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2489 && memory_address_p (GET_MODE (x
),
2490 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2492 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2493 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2495 /* Replace the placeholder in SRC2 with SRC1. If we can
2496 find where in SRC2 it was placed, that can become our
2497 split point and we can replace this address with SRC2.
2498 Just try two obvious places. */
2500 src2
= replace_rtx (src2
, reg
, src1
);
2502 if (XEXP (src2
, 0) == src1
)
2503 split
= &XEXP (src2
, 0);
2504 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2505 && XEXP (XEXP (src2
, 0), 0) == src1
)
2506 split
= &XEXP (XEXP (src2
, 0), 0);
2510 SUBST (XEXP (x
, 0), src2
);
2515 /* If that didn't work, perhaps the first operand is complex and
2516 needs to be computed separately, so make a split point there.
2517 This will occur on machines that just support REG + CONST
2518 and have a constant moved through some previous computation. */
2520 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2521 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2522 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2524 return &XEXP (XEXP (x
, 0), 0);
2530 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2531 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2532 we need to put the operand into a register. So split at that
2535 if (SET_DEST (x
) == cc0_rtx
2536 && GET_CODE (SET_SRC (x
)) != COMPARE
2537 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2538 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2539 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2540 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2541 return &SET_SRC (x
);
2544 /* See if we can split SET_SRC as it stands. */
2545 split
= find_split_point (&SET_SRC (x
), insn
);
2546 if (split
&& split
!= &SET_SRC (x
))
2549 /* See if we can split SET_DEST as it stands. */
2550 split
= find_split_point (&SET_DEST (x
), insn
);
2551 if (split
&& split
!= &SET_DEST (x
))
2554 /* See if this is a bitfield assignment with everything constant. If
2555 so, this is an IOR of an AND, so split it into that. */
2556 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2557 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2558 <= HOST_BITS_PER_WIDE_INT
)
2559 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2560 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2561 && GET_CODE (SET_SRC (x
)) == CONST_INT
2562 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2563 + INTVAL (XEXP (SET_DEST (x
), 2)))
2564 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2565 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2567 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2568 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2569 int src
= INTVAL (SET_SRC (x
));
2570 rtx dest
= XEXP (SET_DEST (x
), 0);
2571 enum machine_mode mode
= GET_MODE (dest
);
2572 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2574 if (BITS_BIG_ENDIAN
)
2575 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2579 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2582 gen_binary (IOR
, mode
,
2583 gen_binary (AND
, mode
, dest
,
2584 GEN_INT (~ (mask
<< pos
)
2585 & GET_MODE_MASK (mode
))),
2586 GEN_INT (src
<< pos
)));
2588 SUBST (SET_DEST (x
), dest
);
2590 split
= find_split_point (&SET_SRC (x
), insn
);
2591 if (split
&& split
!= &SET_SRC (x
))
2595 /* Otherwise, see if this is an operation that we can split into two.
2596 If so, try to split that. */
2597 code
= GET_CODE (SET_SRC (x
));
2602 /* If we are AND'ing with a large constant that is only a single
2603 bit and the result is only being used in a context where we
2604 need to know if it is zero or non-zero, replace it with a bit
2605 extraction. This will avoid the large constant, which might
2606 have taken more than one insn to make. If the constant were
2607 not a valid argument to the AND but took only one insn to make,
2608 this is no worse, but if it took more than one insn, it will
2611 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2612 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2613 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
2614 && GET_CODE (SET_DEST (x
)) == REG
2615 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
2616 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
2617 && XEXP (*split
, 0) == SET_DEST (x
)
2618 && XEXP (*split
, 1) == const0_rtx
)
2620 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
2621 XEXP (SET_SRC (x
), 0),
2622 pos
, NULL_RTX
, 1, 1, 0, 0);
2623 if (extraction
!= 0)
2625 SUBST (SET_SRC (x
), extraction
);
2626 return find_split_point (loc
, insn
);
2632 inner
= XEXP (SET_SRC (x
), 0);
2634 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
2640 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2641 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
2643 inner
= XEXP (SET_SRC (x
), 0);
2644 len
= INTVAL (XEXP (SET_SRC (x
), 1));
2645 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
2647 if (BITS_BIG_ENDIAN
)
2648 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
2649 unsignedp
= (code
== ZERO_EXTRACT
);
2654 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
2656 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
2658 /* For unsigned, we have a choice of a shift followed by an
2659 AND or two shifts. Use two shifts for field sizes where the
2660 constant might be too large. We assume here that we can
2661 always at least get 8-bit constants in an AND insn, which is
2662 true for every current RISC. */
2664 if (unsignedp
&& len
<= 8)
2669 gen_rtx_combine (LSHIFTRT
, mode
,
2670 gen_lowpart_for_combine (mode
, inner
),
2672 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
2674 split
= find_split_point (&SET_SRC (x
), insn
);
2675 if (split
&& split
!= &SET_SRC (x
))
2682 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
2683 gen_rtx_combine (ASHIFT
, mode
,
2684 gen_lowpart_for_combine (mode
, inner
),
2685 GEN_INT (GET_MODE_BITSIZE (mode
)
2687 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
2689 split
= find_split_point (&SET_SRC (x
), insn
);
2690 if (split
&& split
!= &SET_SRC (x
))
2695 /* See if this is a simple operation with a constant as the second
2696 operand. It might be that this constant is out of range and hence
2697 could be used as a split point. */
2698 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2699 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2700 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
2701 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
2702 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
2703 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
2704 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
2706 return &XEXP (SET_SRC (x
), 1);
2708 /* Finally, see if this is a simple operation with its first operand
2709 not in a register. The operation might require this operand in a
2710 register, so return it as a split point. We can always do this
2711 because if the first operand were another operation, we would have
2712 already found it as a split point. */
2713 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2714 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2715 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
2716 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
2717 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
2718 return &XEXP (SET_SRC (x
), 0);
2724 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2725 it is better to write this as (not (ior A B)) so we can split it.
2726 Similarly for IOR. */
2727 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
2730 gen_rtx_combine (NOT
, GET_MODE (x
),
2731 gen_rtx_combine (code
== IOR
? AND
: IOR
,
2733 XEXP (XEXP (x
, 0), 0),
2734 XEXP (XEXP (x
, 1), 0))));
2735 return find_split_point (loc
, insn
);
2738 /* Many RISC machines have a large set of logical insns. If the
2739 second operand is a NOT, put it first so we will try to split the
2740 other operand first. */
2741 if (GET_CODE (XEXP (x
, 1)) == NOT
)
2743 rtx tem
= XEXP (x
, 0);
2744 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2745 SUBST (XEXP (x
, 1), tem
);
2750 /* Otherwise, select our actions depending on our rtx class. */
2751 switch (GET_RTX_CLASS (code
))
2753 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2755 split
= find_split_point (&XEXP (x
, 2), insn
);
2758 /* ... fall through ... */
2762 split
= find_split_point (&XEXP (x
, 1), insn
);
2765 /* ... fall through ... */
2767 /* Some machines have (and (shift ...) ...) insns. If X is not
2768 an AND, but XEXP (X, 0) is, use it as our split point. */
2769 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
2770 return &XEXP (x
, 0);
2772 split
= find_split_point (&XEXP (x
, 0), insn
);
2778 /* Otherwise, we don't have a split point. */
2782 /* Throughout X, replace FROM with TO, and return the result.
2783 The result is TO if X is FROM;
2784 otherwise the result is X, but its contents may have been modified.
2785 If they were modified, a record was made in undobuf so that
2786 undo_all will (among other things) return X to its original state.
2788 If the number of changes necessary is too much to record to undo,
2789 the excess changes are not made, so the result is invalid.
2790 The changes already made can still be undone.
2791 undobuf.num_undo is incremented for such changes, so by testing that
2792 the caller can tell whether the result is valid.
2794 `n_occurrences' is incremented each time FROM is replaced.
2796 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2798 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2799 by copying if `n_occurrences' is non-zero. */
2802 subst (x
, from
, to
, in_dest
, unique_copy
)
2803 register rtx x
, from
, to
;
2807 register enum rtx_code code
= GET_CODE (x
);
2808 enum machine_mode op0_mode
= VOIDmode
;
2810 register int len
, i
;
2813 /* Two expressions are equal if they are identical copies of a shared
2814 RTX or if they are both registers with the same register number
2817 #define COMBINE_RTX_EQUAL_P(X,Y) \
2819 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2820 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2822 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
2825 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
2828 /* If X and FROM are the same register but different modes, they will
2829 not have been seen as equal above. However, flow.c will make a
2830 LOG_LINKS entry for that case. If we do nothing, we will try to
2831 rerecognize our original insn and, when it succeeds, we will
2832 delete the feeding insn, which is incorrect.
2834 So force this insn not to match in this (rare) case. */
2835 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
2836 && REGNO (x
) == REGNO (from
))
2837 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
2839 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2840 of which may contain things that can be combined. */
2841 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
2844 /* It is possible to have a subexpression appear twice in the insn.
2845 Suppose that FROM is a register that appears within TO.
2846 Then, after that subexpression has been scanned once by `subst',
2847 the second time it is scanned, TO may be found. If we were
2848 to scan TO here, we would find FROM within it and create a
2849 self-referent rtl structure which is completely wrong. */
2850 if (COMBINE_RTX_EQUAL_P (x
, to
))
2853 len
= GET_RTX_LENGTH (code
);
2854 fmt
= GET_RTX_FORMAT (code
);
2856 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2857 set up to skip this common case. All other cases where we want to
2858 suppress replacing something inside a SET_SRC are handled via the
2861 && (GET_CODE (SET_DEST (x
)) == REG
2862 || GET_CODE (SET_DEST (x
)) == CC0
2863 || GET_CODE (SET_DEST (x
)) == PC
))
2866 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2868 op0_mode
= GET_MODE (XEXP (x
, 0));
2870 for (i
= 0; i
< len
; i
++)
2875 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2877 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
2879 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2884 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0, unique_copy
);
2886 /* If this substitution failed, this whole thing fails. */
2887 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2891 SUBST (XVECEXP (x
, i
, j
), new);
2894 else if (fmt
[i
] == 'e')
2896 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
2898 /* In general, don't install a subreg involving two modes not
2899 tieable. It can worsen register allocation, and can even
2900 make invalid reload insns, since the reg inside may need to
2901 be copied from in the outside mode, and that may be invalid
2902 if it is an fp reg copied in integer mode.
2904 We allow two exceptions to this: It is valid if it is inside
2905 another SUBREG and the mode of that SUBREG and the mode of
2906 the inside of TO is tieable and it is valid if X is a SET
2907 that copies FROM to CC0. */
2908 if (GET_CODE (to
) == SUBREG
2909 && ! MODES_TIEABLE_P (GET_MODE (to
),
2910 GET_MODE (SUBREG_REG (to
)))
2911 && ! (code
== SUBREG
2912 && MODES_TIEABLE_P (GET_MODE (x
),
2913 GET_MODE (SUBREG_REG (to
))))
2915 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
2918 return gen_rtx (CLOBBER
, VOIDmode
, const0_rtx
);
2920 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2924 /* If we are in a SET_DEST, suppress most cases unless we
2925 have gone inside a MEM, in which case we want to
2926 simplify the address. We assume here that things that
2927 are actually part of the destination have their inner
2928 parts in the first expression. This is true for SUBREG,
2929 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2930 things aside from REG and MEM that should appear in a
2932 new = subst (XEXP (x
, i
), from
, to
,
2934 && (code
== SUBREG
|| code
== STRICT_LOW_PART
2935 || code
== ZERO_EXTRACT
))
2937 && i
== 0), unique_copy
);
2939 /* If we found that we will have to reject this combination,
2940 indicate that by returning the CLOBBER ourselves, rather than
2941 an expression containing it. This will speed things up as
2942 well as prevent accidents where two CLOBBERs are considered
2943 to be equal, thus producing an incorrect simplification. */
2945 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2948 SUBST (XEXP (x
, i
), new);
2952 /* Try to simplify X. If the simplification changed the code, it is likely
2953 that further simplification will help, so loop, but limit the number
2954 of repetitions that will be performed. */
2956 for (i
= 0; i
< 4; i
++)
2958 /* If X is sufficiently simple, don't bother trying to do anything
2960 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
2961 x
= simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
2963 if (GET_CODE (x
) == code
)
2966 code
= GET_CODE (x
);
2968 /* We no longer know the original mode of operand 0 since we
2969 have changed the form of X) */
2970 op0_mode
= VOIDmode
;
2976 /* Simplify X, a piece of RTL. We just operate on the expression at the
2977 outer level; call `subst' to simplify recursively. Return the new
2980 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
2981 will be the iteration even if an expression with a code different from
2982 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
2985 simplify_rtx (x
, op0_mode
, last
, in_dest
)
2987 enum machine_mode op0_mode
;
2991 enum rtx_code code
= GET_CODE (x
);
2992 enum machine_mode mode
= GET_MODE (x
);
2996 /* If this is a commutative operation, put a constant last and a complex
2997 expression first. We don't need to do this for comparisons here. */
2998 if (GET_RTX_CLASS (code
) == 'c'
2999 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3000 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3001 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3002 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3003 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3004 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3007 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3008 SUBST (XEXP (x
, 1), temp
);
3011 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3012 sign extension of a PLUS with a constant, reverse the order of the sign
3013 extension and the addition. Note that this not the same as the original
3014 code, but overflow is undefined for signed values. Also note that the
3015 PLUS will have been partially moved "inside" the sign-extension, so that
3016 the first operand of X will really look like:
3017 (ashiftrt (plus (ashift A C4) C5) C4).
3019 (plus (ashiftrt (ashift A C4) C2) C4)
3020 and replace the first operand of X with that expression. Later parts
3021 of this function may simplify the expression further.
3023 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3024 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3025 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3027 We do this to simplify address expressions. */
3029 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3030 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3031 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3032 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3033 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3034 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3035 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3036 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3037 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3038 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3039 XEXP (XEXP (x
, 0), 1))) != 0)
3042 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3043 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3044 INTVAL (XEXP (XEXP (x
, 0), 1)));
3046 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3047 INTVAL (XEXP (XEXP (x
, 0), 1)));
3049 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3052 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3053 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3054 things. Check for cases where both arms are testing the same
3057 Don't do anything if all operands are very simple. */
3059 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3060 || GET_RTX_CLASS (code
) == '<')
3061 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3062 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3063 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3065 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3066 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3067 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3069 || (GET_RTX_CLASS (code
) == '1'
3070 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3071 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3072 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3075 rtx cond
, true, false;
3077 cond
= if_then_else_cond (x
, &true, &false);
3080 rtx cop1
= const0_rtx
;
3081 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3083 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3086 /* Simplify the alternative arms; this may collapse the true and
3087 false arms to store-flag values. */
3088 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3089 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3091 /* Restarting if we generate a store-flag expression will cause
3092 us to loop. Just drop through in this case. */
3094 /* If the result values are STORE_FLAG_VALUE and zero, we can
3095 just make the comparison operation. */
3096 if (true == const_true_rtx
&& false == const0_rtx
)
3097 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3098 else if (true == const0_rtx
&& false == const_true_rtx
)
3099 x
= gen_binary (reverse_condition (cond_code
), mode
, cond
, cop1
);
3101 /* Likewise, we can make the negate of a comparison operation
3102 if the result values are - STORE_FLAG_VALUE and zero. */
3103 else if (GET_CODE (true) == CONST_INT
3104 && INTVAL (true) == - STORE_FLAG_VALUE
3105 && false == const0_rtx
)
3106 x
= gen_unary (NEG
, mode
, mode
,
3107 gen_binary (cond_code
, mode
, cond
, cop1
));
3108 else if (GET_CODE (false) == CONST_INT
3109 && INTVAL (false) == - STORE_FLAG_VALUE
3110 && true == const0_rtx
)
3111 x
= gen_unary (NEG
, mode
, mode
,
3112 gen_binary (reverse_condition (cond_code
),
3115 return gen_rtx (IF_THEN_ELSE
, mode
,
3116 gen_binary (cond_code
, VOIDmode
, cond
, cop1
),
3119 code
= GET_CODE (x
);
3120 op0_mode
= VOIDmode
;
3124 /* Try to fold this expression in case we have constants that weren't
3127 switch (GET_RTX_CLASS (code
))
3130 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3133 temp
= simplify_relational_operation (code
, op0_mode
,
3134 XEXP (x
, 0), XEXP (x
, 1));
3135 #ifdef FLOAT_STORE_FLAG_VALUE
3136 if (temp
!= 0 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3137 temp
= ((temp
== const0_rtx
) ? CONST0_RTX (GET_MODE (x
))
3138 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE
, GET_MODE (x
)));
3143 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3147 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3148 XEXP (x
, 1), XEXP (x
, 2));
3153 x
= temp
, code
= GET_CODE (temp
);
3155 /* First see if we can apply the inverse distributive law. */
3156 if (code
== PLUS
|| code
== MINUS
3157 || code
== AND
|| code
== IOR
|| code
== XOR
)
3159 x
= apply_distributive_law (x
);
3160 code
= GET_CODE (x
);
3163 /* If CODE is an associative operation not otherwise handled, see if we
3164 can associate some operands. This can win if they are constants or
3165 if they are logically related (i.e. (a & b) & a. */
3166 if ((code
== PLUS
|| code
== MINUS
3167 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3168 || code
== DIV
|| code
== UDIV
3169 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3170 && INTEGRAL_MODE_P (mode
))
3172 if (GET_CODE (XEXP (x
, 0)) == code
)
3174 rtx other
= XEXP (XEXP (x
, 0), 0);
3175 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3176 rtx inner_op1
= XEXP (x
, 1);
3179 /* Make sure we pass the constant operand if any as the second
3180 one if this is a commutative operation. */
3181 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3183 rtx tem
= inner_op0
;
3184 inner_op0
= inner_op1
;
3187 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3188 : code
== DIV
? MULT
3189 : code
== UDIV
? MULT
3191 mode
, inner_op0
, inner_op1
);
3193 /* For commutative operations, try the other pair if that one
3195 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3197 other
= XEXP (XEXP (x
, 0), 1);
3198 inner
= simplify_binary_operation (code
, mode
,
3199 XEXP (XEXP (x
, 0), 0),
3204 return gen_binary (code
, mode
, other
, inner
);
3208 /* A little bit of algebraic simplification here. */
3212 /* Ensure that our address has any ASHIFTs converted to MULT in case
3213 address-recognizing predicates are called later. */
3214 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3215 SUBST (XEXP (x
, 0), temp
);
3219 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3220 is paradoxical. If we can't do that safely, then it becomes
3221 something nonsensical so that this combination won't take place. */
3223 if (GET_CODE (SUBREG_REG (x
)) == MEM
3224 && (GET_MODE_SIZE (mode
)
3225 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3227 rtx inner
= SUBREG_REG (x
);
3228 int endian_offset
= 0;
3229 /* Don't change the mode of the MEM
3230 if that would change the meaning of the address. */
3231 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3232 || mode_dependent_address_p (XEXP (inner
, 0)))
3233 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
3235 if (BYTES_BIG_ENDIAN
)
3237 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3238 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3239 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3240 endian_offset
-= (UNITS_PER_WORD
3241 - GET_MODE_SIZE (GET_MODE (inner
)));
3243 /* Note if the plus_constant doesn't make a valid address
3244 then this combination won't be accepted. */
3245 x
= gen_rtx (MEM
, mode
,
3246 plus_constant (XEXP (inner
, 0),
3247 (SUBREG_WORD (x
) * UNITS_PER_WORD
3249 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (inner
);
3250 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
3251 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (inner
);
3255 /* If we are in a SET_DEST, these other cases can't apply. */
3259 /* Changing mode twice with SUBREG => just change it once,
3260 or not at all if changing back to starting mode. */
3261 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3263 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3264 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3265 return SUBREG_REG (SUBREG_REG (x
));
3267 SUBST_INT (SUBREG_WORD (x
),
3268 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3269 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3272 /* SUBREG of a hard register => just change the register number
3273 and/or mode. If the hard register is not valid in that mode,
3274 suppress this combination. If the hard register is the stack,
3275 frame, or argument pointer, leave this as a SUBREG. */
3277 if (GET_CODE (SUBREG_REG (x
)) == REG
3278 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3279 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3280 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3281 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3283 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3284 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3286 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3288 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3290 return gen_rtx (REG
, mode
,
3291 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3293 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
3296 /* For a constant, try to pick up the part we want. Handle a full
3297 word and low-order part. Only do this if we are narrowing
3298 the constant; if it is being widened, we have no idea what
3299 the extra bits will have been set to. */
3301 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3302 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3303 && GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
3304 && GET_MODE_CLASS (mode
) == MODE_INT
)
3306 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3312 /* If we want a subreg of a constant, at offset 0,
3313 take the low bits. On a little-endian machine, that's
3314 always valid. On a big-endian machine, it's valid
3315 only if the constant's mode fits in one word. */
3316 if (CONSTANT_P (SUBREG_REG (x
)) && subreg_lowpart_p (x
)
3317 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3318 && (! WORDS_BIG_ENDIAN
3319 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3320 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3322 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3323 since we are saying that the high bits don't matter. */
3324 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3325 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3326 return SUBREG_REG (x
);
3328 /* Note that we cannot do any narrowing for non-constants since
3329 we might have been counting on using the fact that some bits were
3330 zero. We now do this in the SET. */
3335 /* (not (plus X -1)) can become (neg X). */
3336 if (GET_CODE (XEXP (x
, 0)) == PLUS
3337 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3338 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3340 /* Similarly, (not (neg X)) is (plus X -1). */
3341 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3342 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3345 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3346 if (GET_CODE (XEXP (x
, 0)) == XOR
3347 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3348 && (temp
= simplify_unary_operation (NOT
, mode
,
3349 XEXP (XEXP (x
, 0), 1),
3351 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3353 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3354 other than 1, but that is not valid. We could do a similar
3355 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3356 but this doesn't seem common enough to bother with. */
3357 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3358 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3359 return gen_rtx (ROTATE
, mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3360 XEXP (XEXP (x
, 0), 1));
3362 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3363 && subreg_lowpart_p (XEXP (x
, 0))
3364 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3365 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3366 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3367 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3369 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3371 x
= gen_rtx (ROTATE
, inner_mode
,
3372 gen_unary (NOT
, inner_mode
, inner_mode
, const1_rtx
),
3373 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3374 return gen_lowpart_for_combine (mode
, x
);
3377 #if STORE_FLAG_VALUE == -1
3378 /* (not (comparison foo bar)) can be done by reversing the comparison
3380 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3381 && reversible_comparison_p (XEXP (x
, 0)))
3382 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3383 mode
, XEXP (XEXP (x
, 0), 0),
3384 XEXP (XEXP (x
, 0), 1));
3386 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3387 is (lt foo (const_int 0)), so we can perform the above
3390 if (XEXP (x
, 1) == const1_rtx
3391 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3392 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3393 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3394 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3397 /* Apply De Morgan's laws to reduce number of patterns for machines
3398 with negating logical insns (and-not, nand, etc.). If result has
3399 only one NOT, put it first, since that is how the patterns are
3402 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3404 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3406 if (GET_CODE (in1
) == NOT
)
3407 in1
= XEXP (in1
, 0);
3409 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
3411 if (GET_CODE (in2
) == NOT
)
3412 in2
= XEXP (in2
, 0);
3413 else if (GET_CODE (in2
) == CONST_INT
3414 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3415 in2
= GEN_INT (GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
3417 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
3419 if (GET_CODE (in2
) == NOT
)
3422 in2
= in1
; in1
= tem
;
3425 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3431 /* (neg (plus X 1)) can become (not X). */
3432 if (GET_CODE (XEXP (x
, 0)) == PLUS
3433 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3434 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3436 /* Similarly, (neg (not X)) is (plus X 1). */
3437 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3438 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3440 /* (neg (minus X Y)) can become (minus Y X). */
3441 if (GET_CODE (XEXP (x
, 0)) == MINUS
3442 && (! FLOAT_MODE_P (mode
)
3443 /* x-y != -(y-x) with IEEE floating point. */
3444 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3446 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3447 XEXP (XEXP (x
, 0), 0));
3449 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3450 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3451 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3452 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3454 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3455 if we can then eliminate the NEG (e.g.,
3456 if the operand is a constant). */
3458 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3460 temp
= simplify_unary_operation (NEG
, mode
,
3461 XEXP (XEXP (x
, 0), 0), mode
);
3464 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
3469 temp
= expand_compound_operation (XEXP (x
, 0));
3471 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3472 replaced by (lshiftrt X C). This will convert
3473 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3475 if (GET_CODE (temp
) == ASHIFTRT
3476 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3477 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3478 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3479 INTVAL (XEXP (temp
, 1)));
3481 /* If X has only a single bit that might be nonzero, say, bit I, convert
3482 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3483 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3484 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3485 or a SUBREG of one since we'd be making the expression more
3486 complex if it was just a register. */
3488 if (GET_CODE (temp
) != REG
3489 && ! (GET_CODE (temp
) == SUBREG
3490 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3491 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3493 rtx temp1
= simplify_shift_const
3494 (NULL_RTX
, ASHIFTRT
, mode
,
3495 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3496 GET_MODE_BITSIZE (mode
) - 1 - i
),
3497 GET_MODE_BITSIZE (mode
) - 1 - i
);
3499 /* If all we did was surround TEMP with the two shifts, we
3500 haven't improved anything, so don't use it. Otherwise,
3501 we are better off with TEMP1. */
3502 if (GET_CODE (temp1
) != ASHIFTRT
3503 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3504 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3510 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3512 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3513 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3516 case FLOAT_TRUNCATE
:
3517 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3518 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
3519 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3520 return XEXP (XEXP (x
, 0), 0);
3522 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3523 (OP:SF foo:SF) if OP is NEG or ABS. */
3524 if ((GET_CODE (XEXP (x
, 0)) == ABS
3525 || GET_CODE (XEXP (x
, 0)) == NEG
)
3526 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
3527 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3528 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3529 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3531 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3532 is (float_truncate:SF x). */
3533 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3534 && subreg_lowpart_p (XEXP (x
, 0))
3535 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
3536 return SUBREG_REG (XEXP (x
, 0));
3541 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3542 using cc0, in which case we want to leave it as a COMPARE
3543 so we can distinguish it from a register-register-copy. */
3544 if (XEXP (x
, 1) == const0_rtx
)
3547 /* In IEEE floating point, x-0 is not the same as x. */
3548 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3549 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
3551 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
3557 /* (const (const X)) can become (const X). Do it this way rather than
3558 returning the inner CONST since CONST can be shared with a
3560 if (GET_CODE (XEXP (x
, 0)) == CONST
)
3561 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3566 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3567 can add in an offset. find_split_point will split this address up
3568 again if it doesn't match. */
3569 if (GET_CODE (XEXP (x
, 0)) == HIGH
3570 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
3576 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3577 outermost. That's because that's the way indexed addresses are
3578 supposed to appear. This code used to check many more cases, but
3579 they are now checked elsewhere. */
3580 if (GET_CODE (XEXP (x
, 0)) == PLUS
3581 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
3582 return gen_binary (PLUS
, mode
,
3583 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3585 XEXP (XEXP (x
, 0), 1));
3587 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3588 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3589 bit-field and can be replaced by either a sign_extend or a
3590 sign_extract. The `and' may be a zero_extend. */
3591 if (GET_CODE (XEXP (x
, 0)) == XOR
3592 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3593 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3594 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
3595 && (i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
3596 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3597 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
3598 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3599 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
3600 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
3601 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
3602 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
3604 return simplify_shift_const
3605 (NULL_RTX
, ASHIFTRT
, mode
,
3606 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3607 XEXP (XEXP (XEXP (x
, 0), 0), 0),
3608 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
3609 GET_MODE_BITSIZE (mode
) - (i
+ 1));
3611 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3612 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3613 is 1. This produces better code than the alternative immediately
3615 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3616 && reversible_comparison_p (XEXP (x
, 0))
3617 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
3618 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
)))
3620 gen_unary (NEG
, mode
, mode
,
3621 gen_binary (reverse_condition (GET_CODE (XEXP (x
, 0))),
3622 mode
, XEXP (XEXP (x
, 0), 0),
3623 XEXP (XEXP (x
, 0), 1)));
3625 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3626 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3627 the bitsize of the mode - 1. This allows simplification of
3628 "a = (b & 8) == 0;" */
3629 if (XEXP (x
, 1) == constm1_rtx
3630 && GET_CODE (XEXP (x
, 0)) != REG
3631 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
3632 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
3633 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
3634 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
3635 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3636 gen_rtx_combine (XOR
, mode
,
3637 XEXP (x
, 0), const1_rtx
),
3638 GET_MODE_BITSIZE (mode
) - 1),
3639 GET_MODE_BITSIZE (mode
) - 1);
3641 /* If we are adding two things that have no bits in common, convert
3642 the addition into an IOR. This will often be further simplified,
3643 for example in cases like ((a & 1) + (a & 2)), which can
3646 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3647 && (nonzero_bits (XEXP (x
, 0), mode
)
3648 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
3649 return gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3653 #if STORE_FLAG_VALUE == 1
3654 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3656 if (XEXP (x
, 0) == const1_rtx
3657 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
3658 && reversible_comparison_p (XEXP (x
, 1)))
3659 return gen_binary (reverse_condition (GET_CODE (XEXP (x
, 1))),
3660 mode
, XEXP (XEXP (x
, 1), 0),
3661 XEXP (XEXP (x
, 1), 1));
3664 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3665 (and <foo> (const_int pow2-1)) */
3666 if (GET_CODE (XEXP (x
, 1)) == AND
3667 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3668 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
3669 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3670 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
3671 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
3673 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3675 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
3676 return gen_binary (MINUS
, mode
,
3677 gen_binary (MINUS
, mode
, XEXP (x
, 0),
3678 XEXP (XEXP (x
, 1), 0)),
3679 XEXP (XEXP (x
, 1), 1));
3683 /* If we have (mult (plus A B) C), apply the distributive law and then
3684 the inverse distributive law to see if things simplify. This
3685 occurs mostly in addresses, often when unrolling loops. */
3687 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
3689 x
= apply_distributive_law
3690 (gen_binary (PLUS
, mode
,
3691 gen_binary (MULT
, mode
,
3692 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
3693 gen_binary (MULT
, mode
,
3694 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
3696 if (GET_CODE (x
) != MULT
)
3702 /* If this is a divide by a power of two, treat it as a shift if
3703 its first operand is a shift. */
3704 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
3705 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
3706 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
3707 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3708 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3709 || GET_CODE (XEXP (x
, 0)) == ROTATE
3710 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
3711 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
3715 case GT
: case GTU
: case GE
: case GEU
:
3716 case LT
: case LTU
: case LE
: case LEU
:
3717 /* If the first operand is a condition code, we can't do anything
3719 if (GET_CODE (XEXP (x
, 0)) == COMPARE
3720 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
3722 && XEXP (x
, 0) != cc0_rtx
3726 rtx op0
= XEXP (x
, 0);
3727 rtx op1
= XEXP (x
, 1);
3728 enum rtx_code new_code
;
3730 if (GET_CODE (op0
) == COMPARE
)
3731 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
3733 /* Simplify our comparison, if possible. */
3734 new_code
= simplify_comparison (code
, &op0
, &op1
);
3736 #if STORE_FLAG_VALUE == 1
3737 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3738 if only the low-order bit is possibly nonzero in X (such as when
3739 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3740 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3741 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3744 Remove any ZERO_EXTRACT we made when thinking this was a
3745 comparison. It may now be simpler to use, e.g., an AND. If a
3746 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3747 the call to make_compound_operation in the SET case. */
3749 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3750 && op1
== const0_rtx
3751 && nonzero_bits (op0
, mode
) == 1)
3752 return gen_lowpart_for_combine (mode
,
3753 expand_compound_operation (op0
));
3755 else if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3756 && op1
== const0_rtx
3757 && (num_sign_bit_copies (op0
, mode
)
3758 == GET_MODE_BITSIZE (mode
)))
3760 op0
= expand_compound_operation (op0
);
3761 return gen_unary (NEG
, mode
, mode
,
3762 gen_lowpart_for_combine (mode
, op0
));
3765 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3766 && op1
== const0_rtx
3767 && nonzero_bits (op0
, mode
) == 1)
3769 op0
= expand_compound_operation (op0
);
3770 return gen_binary (XOR
, mode
,
3771 gen_lowpart_for_combine (mode
, op0
),
3775 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3776 && op1
== const0_rtx
3777 && (num_sign_bit_copies (op0
, mode
)
3778 == GET_MODE_BITSIZE (mode
)))
3780 op0
= expand_compound_operation (op0
);
3781 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
3785 #if STORE_FLAG_VALUE == -1
3786 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3788 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3789 && op1
== const0_rtx
3790 && (num_sign_bit_copies (op0
, mode
)
3791 == GET_MODE_BITSIZE (mode
)))
3792 return gen_lowpart_for_combine (mode
,
3793 expand_compound_operation (op0
));
3795 else if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3796 && op1
== const0_rtx
3797 && nonzero_bits (op0
, mode
) == 1)
3799 op0
= expand_compound_operation (op0
);
3800 return gen_unary (NEG
, mode
, mode
,
3801 gen_lowpart_for_combine (mode
, op0
));
3804 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3805 && op1
== const0_rtx
3806 && (num_sign_bit_copies (op0
, mode
)
3807 == GET_MODE_BITSIZE (mode
)))
3809 op0
= expand_compound_operation (op0
);
3810 return gen_unary (NOT
, mode
, mode
,
3811 gen_lowpart_for_combine (mode
, op0
));
3814 /* If X is 0/1, (eq X 0) is X-1. */
3815 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3816 && op1
== const0_rtx
3817 && nonzero_bits (op0
, mode
) == 1)
3819 op0
= expand_compound_operation (op0
);
3820 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
3824 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3825 one bit that might be nonzero, we can convert (ne x 0) to
3826 (ashift x c) where C puts the bit in the sign bit. Remove any
3827 AND with STORE_FLAG_VALUE when we are done, since we are only
3828 going to test the sign bit. */
3829 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3830 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3831 && (STORE_FLAG_VALUE
3832 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
3833 && op1
== const0_rtx
3834 && mode
== GET_MODE (op0
)
3835 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
3837 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3838 expand_compound_operation (op0
),
3839 GET_MODE_BITSIZE (mode
) - 1 - i
);
3840 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
3846 /* If the code changed, return a whole new comparison. */
3847 if (new_code
!= code
)
3848 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
3850 /* Otherwise, keep this operation, but maybe change its operands.
3851 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3852 SUBST (XEXP (x
, 0), op0
);
3853 SUBST (XEXP (x
, 1), op1
);
3858 return simplify_if_then_else (x
);
3864 /* If we are processing SET_DEST, we are done. */
3868 return expand_compound_operation (x
);
3871 return simplify_set (x
);
3876 return simplify_logical (x
, last
);
3879 /* (abs (neg <foo>)) -> (abs <foo>) */
3880 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3881 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3883 /* If operand is something known to be positive, ignore the ABS. */
3884 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
3885 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
3886 <= HOST_BITS_PER_WIDE_INT
)
3887 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3888 & ((HOST_WIDE_INT
) 1
3889 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
3894 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3895 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
3896 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
3901 /* (ffs (*_extend <X>)) = (ffs <X>) */
3902 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3903 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3904 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3908 /* (float (sign_extend <X>)) = (float <X>). */
3909 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
3910 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3918 /* If this is a shift by a constant amount, simplify it. */
3919 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3920 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
3921 INTVAL (XEXP (x
, 1)));
3923 #ifdef SHIFT_COUNT_TRUNCATED
3924 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
3926 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
3928 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
3939 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
3942 simplify_if_then_else (x
)
3945 enum machine_mode mode
= GET_MODE (x
);
3946 rtx cond
= XEXP (x
, 0);
3947 rtx
true = XEXP (x
, 1);
3948 rtx
false = XEXP (x
, 2);
3949 enum rtx_code true_code
= GET_CODE (cond
);
3950 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
3954 /* Simplify storing of the truth value. */
3955 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
3956 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
3958 /* Also when the truth value has to be reversed. */
3959 if (comparison_p
&& reversible_comparison_p (cond
)
3960 && true == const0_rtx
&& false == const_true_rtx
)
3961 return gen_binary (reverse_condition (true_code
),
3962 mode
, XEXP (cond
, 0), XEXP (cond
, 1));
3964 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
3965 in it is being compared against certain values. Get the true and false
3966 comparisons and see if that says anything about the value of each arm. */
3968 if (comparison_p
&& reversible_comparison_p (cond
)
3969 && GET_CODE (XEXP (cond
, 0)) == REG
)
3972 rtx from
= XEXP (cond
, 0);
3973 enum rtx_code false_code
= reverse_condition (true_code
);
3974 rtx true_val
= XEXP (cond
, 1);
3975 rtx false_val
= true_val
;
3978 /* If FALSE_CODE is EQ, swap the codes and arms. */
3980 if (false_code
== EQ
)
3982 swapped
= 1, true_code
= EQ
, false_code
= NE
;
3983 temp
= true, true = false, false = temp
;
3986 /* If we are comparing against zero and the expression being tested has
3987 only a single bit that might be nonzero, that is its value when it is
3988 not equal to zero. Similarly if it is known to be -1 or 0. */
3990 if (true_code
== EQ
&& true_val
== const0_rtx
3991 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
3992 false_code
= EQ
, false_val
= GEN_INT (nzb
);
3993 else if (true_code
== EQ
&& true_val
== const0_rtx
3994 && (num_sign_bit_copies (from
, GET_MODE (from
))
3995 == GET_MODE_BITSIZE (GET_MODE (from
))))
3996 false_code
= EQ
, false_val
= constm1_rtx
;
3998 /* Now simplify an arm if we know the value of the register in the
3999 branch and it is used in the arm. Be careful due to the potential
4000 of locally-shared RTL. */
4002 if (reg_mentioned_p (from
, true))
4003 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
4004 pc_rtx
, pc_rtx
, 0, 0);
4005 if (reg_mentioned_p (from
, false))
4006 false = subst (known_cond (copy_rtx (false), false_code
,
4008 pc_rtx
, pc_rtx
, 0, 0);
4010 SUBST (XEXP (x
, 1), swapped
? false : true);
4011 SUBST (XEXP (x
, 2), swapped
? true : false);
4013 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
4016 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4017 reversed, do so to avoid needing two sets of patterns for
4018 subtract-and-branch insns. Similarly if we have a constant in the true
4019 arm, the false arm is the same as the first operand of the comparison, or
4020 the false arm is more complicated than the true arm. */
4022 if (comparison_p
&& reversible_comparison_p (cond
)
4024 || (CONSTANT_P (true)
4025 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
4026 || true == const0_rtx
4027 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4028 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4029 || (GET_CODE (true) == SUBREG
4030 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4031 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4032 || reg_mentioned_p (true, false)
4033 || rtx_equal_p (false, XEXP (cond
, 0))))
4035 true_code
= reverse_condition (true_code
);
4037 gen_binary (true_code
, GET_MODE (cond
), XEXP (cond
, 0),
4040 SUBST (XEXP (x
, 1), false);
4041 SUBST (XEXP (x
, 2), true);
4043 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
4045 /* It is possible that the conditional has been simplified out. */
4046 true_code
= GET_CODE (cond
);
4047 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4050 /* If the two arms are identical, we don't need the comparison. */
4052 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
4055 /* Convert a == b ? b : a to "a". */
4056 if (true_code
== EQ
&& ! side_effects_p (cond
)
4057 && rtx_equal_p (XEXP (cond
, 0), false)
4058 && rtx_equal_p (XEXP (cond
, 1), true))
4060 else if (true_code
== NE
&& ! side_effects_p (cond
)
4061 && rtx_equal_p (XEXP (cond
, 0), true)
4062 && rtx_equal_p (XEXP (cond
, 1), false))
4065 /* Look for cases where we have (abs x) or (neg (abs X)). */
4067 if (GET_MODE_CLASS (mode
) == MODE_INT
4068 && GET_CODE (false) == NEG
4069 && rtx_equal_p (true, XEXP (false, 0))
4071 && rtx_equal_p (true, XEXP (cond
, 0))
4072 && ! side_effects_p (true))
4077 return gen_unary (ABS
, mode
, mode
, true);
4080 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
4083 /* Look for MIN or MAX. */
4085 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4087 && rtx_equal_p (XEXP (cond
, 0), true)
4088 && rtx_equal_p (XEXP (cond
, 1), false)
4089 && ! side_effects_p (cond
))
4094 return gen_binary (SMAX
, mode
, true, false);
4097 return gen_binary (SMIN
, mode
, true, false);
4100 return gen_binary (UMAX
, mode
, true, false);
4103 return gen_binary (UMIN
, mode
, true, false);
4106 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4108 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4109 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4110 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4111 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4112 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4113 neither of the above, but it isn't worth checking for. */
4115 if (comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4117 rtx t
= make_compound_operation (true, SET
);
4118 rtx f
= make_compound_operation (false, SET
);
4119 rtx cond_op0
= XEXP (cond
, 0);
4120 rtx cond_op1
= XEXP (cond
, 1);
4121 enum rtx_code op
, extend_op
= NIL
;
4122 enum machine_mode m
= mode
;
4125 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4126 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4127 || GET_CODE (t
) == ASHIFT
4128 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4129 && rtx_equal_p (XEXP (t
, 0), f
))
4130 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4132 /* If an identity-zero op is commutative, check whether there
4133 would be a match if we swapped the operands. */
4134 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4135 || GET_CODE (t
) == XOR
)
4136 && rtx_equal_p (XEXP (t
, 1), f
))
4137 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4138 else if (GET_CODE (t
) == SIGN_EXTEND
4139 && (GET_CODE (XEXP (t
, 0)) == PLUS
4140 || GET_CODE (XEXP (t
, 0)) == MINUS
4141 || GET_CODE (XEXP (t
, 0)) == IOR
4142 || GET_CODE (XEXP (t
, 0)) == XOR
4143 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4144 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4145 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4146 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4147 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4148 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4149 && (num_sign_bit_copies (f
, GET_MODE (f
))
4150 > (GET_MODE_BITSIZE (mode
)
4151 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4153 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4154 extend_op
= SIGN_EXTEND
;
4155 m
= GET_MODE (XEXP (t
, 0));
4157 else if (GET_CODE (t
) == SIGN_EXTEND
4158 && (GET_CODE (XEXP (t
, 0)) == PLUS
4159 || GET_CODE (XEXP (t
, 0)) == IOR
4160 || GET_CODE (XEXP (t
, 0)) == XOR
)
4161 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4162 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4163 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4164 && (num_sign_bit_copies (f
, GET_MODE (f
))
4165 > (GET_MODE_BITSIZE (mode
)
4166 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4168 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4169 extend_op
= SIGN_EXTEND
;
4170 m
= GET_MODE (XEXP (t
, 0));
4172 else if (GET_CODE (t
) == ZERO_EXTEND
4173 && (GET_CODE (XEXP (t
, 0)) == PLUS
4174 || GET_CODE (XEXP (t
, 0)) == MINUS
4175 || GET_CODE (XEXP (t
, 0)) == IOR
4176 || GET_CODE (XEXP (t
, 0)) == XOR
4177 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4178 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4179 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4180 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4181 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4182 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4183 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4184 && ((nonzero_bits (f
, GET_MODE (f
))
4185 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4188 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4189 extend_op
= ZERO_EXTEND
;
4190 m
= GET_MODE (XEXP (t
, 0));
4192 else if (GET_CODE (t
) == ZERO_EXTEND
4193 && (GET_CODE (XEXP (t
, 0)) == PLUS
4194 || GET_CODE (XEXP (t
, 0)) == IOR
4195 || GET_CODE (XEXP (t
, 0)) == XOR
)
4196 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4197 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4198 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4199 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4200 && ((nonzero_bits (f
, GET_MODE (f
))
4201 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4204 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4205 extend_op
= ZERO_EXTEND
;
4206 m
= GET_MODE (XEXP (t
, 0));
4211 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4212 pc_rtx
, pc_rtx
, 0, 0);
4213 temp
= gen_binary (MULT
, m
, temp
,
4214 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4215 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4216 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4218 if (extend_op
!= NIL
)
4219 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4226 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4227 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4228 negation of a single bit, we can convert this operation to a shift. We
4229 can actually do this more generally, but it doesn't seem worth it. */
4231 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4232 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4233 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4234 && (i
= exact_log2 (INTVAL (true))) >= 0)
4235 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4236 == GET_MODE_BITSIZE (mode
))
4237 && (i
= exact_log2 (- INTVAL (true))) >= 0)))
4239 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4240 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4245 /* Simplify X, a SET expression. Return the new expression. */
4251 rtx src
= SET_SRC (x
);
4252 rtx dest
= SET_DEST (x
);
4253 enum machine_mode mode
4254 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4258 /* (set (pc) (return)) gets written as (return). */
4259 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4262 /* Now that we know for sure which bits of SRC we are using, see if we can
4263 simplify the expression for the object knowing that we only need the
4266 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4267 src
= force_to_mode (src
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
4269 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4270 the comparison result and try to simplify it unless we already have used
4271 undobuf.other_insn. */
4272 if ((GET_CODE (src
) == COMPARE
4277 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4278 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4279 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4280 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4282 enum rtx_code old_code
= GET_CODE (*cc_use
);
4283 enum rtx_code new_code
;
4285 int other_changed
= 0;
4286 enum machine_mode compare_mode
= GET_MODE (dest
);
4288 if (GET_CODE (src
) == COMPARE
)
4289 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4291 op0
= src
, op1
= const0_rtx
;
4293 /* Simplify our comparison, if possible. */
4294 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4296 #ifdef EXTRA_CC_MODES
4297 /* If this machine has CC modes other than CCmode, check to see if we
4298 need to use a different CC mode here. */
4299 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4300 #endif /* EXTRA_CC_MODES */
4302 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4303 /* If the mode changed, we have to change SET_DEST, the mode in the
4304 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4305 a hard register, just build new versions with the proper mode. If it
4306 is a pseudo, we lose unless it is only time we set the pseudo, in
4307 which case we can safely change its mode. */
4308 if (compare_mode
!= GET_MODE (dest
))
4310 int regno
= REGNO (dest
);
4311 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
4313 if (regno
< FIRST_PSEUDO_REGISTER
4314 || (reg_n_sets
[regno
] == 1 && ! REG_USERVAR_P (dest
)))
4316 if (regno
>= FIRST_PSEUDO_REGISTER
)
4317 SUBST (regno_reg_rtx
[regno
], new_dest
);
4319 SUBST (SET_DEST (x
), new_dest
);
4320 SUBST (XEXP (*cc_use
, 0), new_dest
);
4328 /* If the code changed, we have to build a new comparison in
4329 undobuf.other_insn. */
4330 if (new_code
!= old_code
)
4332 unsigned HOST_WIDE_INT mask
;
4334 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
4337 /* If the only change we made was to change an EQ into an NE or
4338 vice versa, OP0 has only one bit that might be nonzero, and OP1
4339 is zero, check if changing the user of the condition code will
4340 produce a valid insn. If it won't, we can keep the original code
4341 in that insn by surrounding our operation with an XOR. */
4343 if (((old_code
== NE
&& new_code
== EQ
)
4344 || (old_code
== EQ
&& new_code
== NE
))
4345 && ! other_changed
&& op1
== const0_rtx
4346 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4347 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4349 rtx pat
= PATTERN (other_insn
), note
= 0;
4352 if ((recog_for_combine (&pat
, other_insn
, ¬e
, &scratches
) < 0
4353 && ! check_asm_operands (pat
)))
4355 PUT_CODE (*cc_use
, old_code
);
4358 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4366 undobuf
.other_insn
= other_insn
;
4369 /* If we are now comparing against zero, change our source if
4370 needed. If we do not use cc0, we always have a COMPARE. */
4371 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
4373 SUBST (SET_SRC (x
), op0
);
4379 /* Otherwise, if we didn't previously have a COMPARE in the
4380 correct mode, we need one. */
4381 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
4384 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
4389 /* Otherwise, update the COMPARE if needed. */
4390 SUBST (XEXP (src
, 0), op0
);
4391 SUBST (XEXP (src
, 1), op1
);
4396 /* Get SET_SRC in a form where we have placed back any
4397 compound expressions. Then do the checks below. */
4398 src
= make_compound_operation (src
, SET
);
4399 SUBST (SET_SRC (x
), src
);
4402 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4403 and X being a REG or (subreg (reg)), we may be able to convert this to
4404 (set (subreg:m2 x) (op)).
4406 We can always do this if M1 is narrower than M2 because that means that
4407 we only care about the low bits of the result.
4409 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4410 perform a narrower operation that requested since the high-order bits will
4411 be undefined. On machine where it is defined, this transformation is safe
4412 as long as M1 and M2 have the same number of words. */
4414 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4415 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
4416 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
4418 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
4419 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
4420 #ifndef WORD_REGISTER_OPERATIONS
4421 && (GET_MODE_SIZE (GET_MODE (src
))
4422 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4424 #ifdef CLASS_CANNOT_CHANGE_SIZE
4425 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
4426 && (TEST_HARD_REG_BIT
4427 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
],
4429 && (GET_MODE_SIZE (GET_MODE (src
))
4430 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
4432 && (GET_CODE (dest
) == REG
4433 || (GET_CODE (dest
) == SUBREG
4434 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
4436 SUBST (SET_DEST (x
),
4437 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
4439 SUBST (SET_SRC (x
), SUBREG_REG (src
));
4441 src
= SET_SRC (x
), dest
= SET_DEST (x
);
4444 #ifdef LOAD_EXTEND_OP
4445 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4446 would require a paradoxical subreg. Replace the subreg with a
4447 zero_extend to avoid the reload that would otherwise be required. */
4449 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4450 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
4451 && SUBREG_WORD (src
) == 0
4452 && (GET_MODE_SIZE (GET_MODE (src
))
4453 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4454 && GET_CODE (SUBREG_REG (src
)) == MEM
)
4457 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
4458 GET_MODE (src
), XEXP (src
, 0)));
4464 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4465 are comparing an item known to be 0 or -1 against 0, use a logical
4466 operation instead. Check for one of the arms being an IOR of the other
4467 arm with some value. We compute three terms to be IOR'ed together. In
4468 practice, at most two will be nonzero. Then we do the IOR's. */
4470 if (GET_CODE (dest
) != PC
4471 && GET_CODE (src
) == IF_THEN_ELSE
4472 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
4473 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
4474 && XEXP (XEXP (src
, 0), 1) == const0_rtx
4475 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
4476 #ifdef HAVE_conditional_move
4477 && ! can_conditionally_move_p (GET_MODE (src
))
4479 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
4480 GET_MODE (XEXP (XEXP (src
, 0), 0)))
4481 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
4482 && ! side_effects_p (src
))
4484 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
4485 ? XEXP (src
, 1) : XEXP (src
, 2));
4486 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
4487 ? XEXP (src
, 2) : XEXP (src
, 1));
4488 rtx term1
= const0_rtx
, term2
, term3
;
4490 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
4491 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
4492 else if (GET_CODE (true) == IOR
4493 && rtx_equal_p (XEXP (true, 1), false))
4494 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
4495 else if (GET_CODE (false) == IOR
4496 && rtx_equal_p (XEXP (false, 0), true))
4497 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
4498 else if (GET_CODE (false) == IOR
4499 && rtx_equal_p (XEXP (false, 1), true))
4500 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
4502 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
4503 term3
= gen_binary (AND
, GET_MODE (src
),
4504 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
4505 XEXP (XEXP (src
, 0), 0)),
4509 gen_binary (IOR
, GET_MODE (src
),
4510 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
4516 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4517 whole thing fail. */
4518 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
4520 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
4523 /* Convert this into a field assignment operation, if possible. */
4524 return make_field_assignment (x
);
4527 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4528 result. LAST is nonzero if this is the last retry. */
4531 simplify_logical (x
, last
)
4535 enum machine_mode mode
= GET_MODE (x
);
4536 rtx op0
= XEXP (x
, 0);
4537 rtx op1
= XEXP (x
, 1);
4539 switch (GET_CODE (x
))
4542 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4543 insn (and may simplify more). */
4544 if (GET_CODE (op0
) == XOR
4545 && rtx_equal_p (XEXP (op0
, 0), op1
)
4546 && ! side_effects_p (op1
))
4547 x
= gen_binary (AND
, mode
,
4548 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
4550 if (GET_CODE (op0
) == XOR
4551 && rtx_equal_p (XEXP (op0
, 1), op1
)
4552 && ! side_effects_p (op1
))
4553 x
= gen_binary (AND
, mode
,
4554 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
4556 /* Similarly for (~ (A ^ B)) & A. */
4557 if (GET_CODE (op0
) == NOT
4558 && GET_CODE (XEXP (op0
, 0)) == XOR
4559 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
4560 && ! side_effects_p (op1
))
4561 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
4563 if (GET_CODE (op0
) == NOT
4564 && GET_CODE (XEXP (op0
, 0)) == XOR
4565 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
4566 && ! side_effects_p (op1
))
4567 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
4569 if (GET_CODE (op1
) == CONST_INT
)
4571 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
4573 /* If we have (ior (and (X C1) C2)) and the next restart would be
4574 the last, simplify this by making C1 as small as possible
4577 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
4578 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4579 && GET_CODE (op1
) == CONST_INT
)
4580 return gen_binary (IOR
, mode
,
4581 gen_binary (AND
, mode
, XEXP (op0
, 0),
4582 GEN_INT (INTVAL (XEXP (op0
, 1))
4583 & ~ INTVAL (op1
))), op1
);
4585 if (GET_CODE (x
) != AND
)
4588 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
4589 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
4590 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
4593 /* Convert (A | B) & A to A. */
4594 if (GET_CODE (op0
) == IOR
4595 && (rtx_equal_p (XEXP (op0
, 0), op1
)
4596 || rtx_equal_p (XEXP (op0
, 1), op1
))
4597 && ! side_effects_p (XEXP (op0
, 0))
4598 && ! side_effects_p (XEXP (op0
, 1)))
4601 /* In the following group of tests (and those in case IOR below),
4602 we start with some combination of logical operations and apply
4603 the distributive law followed by the inverse distributive law.
4604 Most of the time, this results in no change. However, if some of
4605 the operands are the same or inverses of each other, simplifications
4608 For example, (and (ior A B) (not B)) can occur as the result of
4609 expanding a bit field assignment. When we apply the distributive
4610 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4611 which then simplifies to (and (A (not B))).
4613 If we have (and (ior A B) C), apply the distributive law and then
4614 the inverse distributive law to see if things simplify. */
4616 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
4618 x
= apply_distributive_law
4619 (gen_binary (GET_CODE (op0
), mode
,
4620 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
4621 gen_binary (AND
, mode
, XEXP (op0
, 1), op1
)));
4622 if (GET_CODE (x
) != AND
)
4626 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
4627 return apply_distributive_law
4628 (gen_binary (GET_CODE (op1
), mode
,
4629 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
4630 gen_binary (AND
, mode
, XEXP (op1
, 1), op0
)));
4632 /* Similarly, taking advantage of the fact that
4633 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4635 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
4636 return apply_distributive_law
4637 (gen_binary (XOR
, mode
,
4638 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
4639 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 1))));
4641 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
4642 return apply_distributive_law
4643 (gen_binary (XOR
, mode
,
4644 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
4645 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 1))));
4649 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4650 if (GET_CODE (op1
) == CONST_INT
4651 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4652 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
4655 /* Convert (A & B) | A to A. */
4656 if (GET_CODE (op0
) == AND
4657 && (rtx_equal_p (XEXP (op0
, 0), op1
)
4658 || rtx_equal_p (XEXP (op0
, 1), op1
))
4659 && ! side_effects_p (XEXP (op0
, 0))
4660 && ! side_effects_p (XEXP (op0
, 1)))
4663 /* If we have (ior (and A B) C), apply the distributive law and then
4664 the inverse distributive law to see if things simplify. */
4666 if (GET_CODE (op0
) == AND
)
4668 x
= apply_distributive_law
4669 (gen_binary (AND
, mode
,
4670 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
4671 gen_binary (IOR
, mode
, XEXP (op0
, 1), op1
)));
4673 if (GET_CODE (x
) != IOR
)
4677 if (GET_CODE (op1
) == AND
)
4679 x
= apply_distributive_law
4680 (gen_binary (AND
, mode
,
4681 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
4682 gen_binary (IOR
, mode
, XEXP (op1
, 1), op0
)));
4684 if (GET_CODE (x
) != IOR
)
4688 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4689 mode size to (rotate A CX). */
4691 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
4692 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
4693 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
4694 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4695 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
4696 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
4697 == GET_MODE_BITSIZE (mode
)))
4698 return gen_rtx (ROTATE
, mode
, XEXP (op0
, 0),
4699 (GET_CODE (op0
) == ASHIFT
4700 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
4702 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4703 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4704 does not affect any of the bits in OP1, it can really be done
4705 as a PLUS and we can associate. We do this by seeing if OP1
4706 can be safely shifted left C bits. */
4707 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
4708 && GET_CODE (XEXP (op0
, 0)) == PLUS
4709 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
4710 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4711 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
4713 int count
= INTVAL (XEXP (op0
, 1));
4714 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
4716 if (mask
>> count
== INTVAL (op1
)
4717 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
4719 SUBST (XEXP (XEXP (op0
, 0), 1),
4720 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
4727 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4728 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4731 int num_negated
= 0;
4733 if (GET_CODE (op0
) == NOT
)
4734 num_negated
++, op0
= XEXP (op0
, 0);
4735 if (GET_CODE (op1
) == NOT
)
4736 num_negated
++, op1
= XEXP (op1
, 0);
4738 if (num_negated
== 2)
4740 SUBST (XEXP (x
, 0), op0
);
4741 SUBST (XEXP (x
, 1), op1
);
4743 else if (num_negated
== 1)
4744 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
4747 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4748 correspond to a machine insn or result in further simplifications
4749 if B is a constant. */
4751 if (GET_CODE (op0
) == AND
4752 && rtx_equal_p (XEXP (op0
, 1), op1
)
4753 && ! side_effects_p (op1
))
4754 return gen_binary (AND
, mode
,
4755 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
4758 else if (GET_CODE (op0
) == AND
4759 && rtx_equal_p (XEXP (op0
, 0), op1
)
4760 && ! side_effects_p (op1
))
4761 return gen_binary (AND
, mode
,
4762 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
4765 #if STORE_FLAG_VALUE == 1
4766 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4768 if (op1
== const1_rtx
4769 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
4770 && reversible_comparison_p (op0
))
4771 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
4772 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
4774 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4775 is (lt foo (const_int 0)), so we can perform the above
4778 if (op1
== const1_rtx
4779 && GET_CODE (op0
) == LSHIFTRT
4780 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4781 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4782 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
4785 /* (xor (comparison foo bar) (const_int sign-bit))
4786 when STORE_FLAG_VALUE is the sign bit. */
4787 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4788 && (STORE_FLAG_VALUE
4789 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4790 && op1
== const_true_rtx
4791 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
4792 && reversible_comparison_p (op0
))
4793 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
4794 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
4801 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4802 operations" because they can be replaced with two more basic operations.
4803 ZERO_EXTEND is also considered "compound" because it can be replaced with
4804 an AND operation, which is simpler, though only one operation.
4806 The function expand_compound_operation is called with an rtx expression
4807 and will convert it to the appropriate shifts and AND operations,
4808 simplifying at each stage.
4810 The function make_compound_operation is called to convert an expression
4811 consisting of shifts and ANDs into the equivalent compound expression.
4812 It is the inverse of this function, loosely speaking. */
4815 expand_compound_operation (x
)
4823 switch (GET_CODE (x
))
4828 /* We can't necessarily use a const_int for a multiword mode;
4829 it depends on implicitly extending the value.
4830 Since we don't know the right way to extend it,
4831 we can't tell whether the implicit way is right.
4833 Even for a mode that is no wider than a const_int,
4834 we can't win, because we need to sign extend one of its bits through
4835 the rest of it, and we don't know which bit. */
4836 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4839 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4840 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4841 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4842 reloaded. If not for that, MEM's would very rarely be safe.
4844 Reject MODEs bigger than a word, because we might not be able
4845 to reference a two-register group starting with an arbitrary register
4846 (and currently gen_lowpart might crash for a SUBREG). */
4848 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
4851 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
4852 /* If the inner object has VOIDmode (the only way this can happen
4853 is if it is a ASM_OPERANDS), we can't do anything since we don't
4854 know how much masking to do. */
4863 /* If the operand is a CLOBBER, just return it. */
4864 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
4867 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
4868 || GET_CODE (XEXP (x
, 2)) != CONST_INT
4869 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4872 len
= INTVAL (XEXP (x
, 1));
4873 pos
= INTVAL (XEXP (x
, 2));
4875 /* If this goes outside the object being extracted, replace the object
4876 with a (use (mem ...)) construct that only combine understands
4877 and is used only for this purpose. */
4878 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4879 SUBST (XEXP (x
, 0), gen_rtx (USE
, GET_MODE (x
), XEXP (x
, 0)));
4881 if (BITS_BIG_ENDIAN
)
4882 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
4890 /* If we reach here, we want to return a pair of shifts. The inner
4891 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4892 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4893 logical depending on the value of UNSIGNEDP.
4895 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4896 converted into an AND of a shift.
4898 We must check for the case where the left shift would have a negative
4899 count. This can happen in a case like (x >> 31) & 255 on machines
4900 that can't shift by a constant. On those machines, we would first
4901 combine the shift with the AND to produce a variable-position
4902 extraction. Then the constant of 31 would be substituted in to produce
4903 a such a position. */
4905 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
4906 if (modewidth
>= pos
- len
)
4907 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
4909 simplify_shift_const (NULL_RTX
, ASHIFT
,
4912 modewidth
- pos
- len
),
4915 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
4916 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
4917 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
4920 ((HOST_WIDE_INT
) 1 << len
) - 1);
4922 /* Any other cases we can't handle. */
4926 /* If we couldn't do this for some reason, return the original
4928 if (GET_CODE (tem
) == CLOBBER
)
4934 /* X is a SET which contains an assignment of one object into
4935 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4936 or certain SUBREGS). If possible, convert it into a series of
4939 We half-heartedly support variable positions, but do not at all
4940 support variable lengths. */
4943 expand_field_assignment (x
)
4947 rtx pos
; /* Always counts from low bit. */
4950 enum machine_mode compute_mode
;
4952 /* Loop until we find something we can't simplify. */
4955 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
4956 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
4958 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
4959 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
4962 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4963 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
4965 inner
= XEXP (SET_DEST (x
), 0);
4966 len
= INTVAL (XEXP (SET_DEST (x
), 1));
4967 pos
= XEXP (SET_DEST (x
), 2);
4969 /* If the position is constant and spans the width of INNER,
4970 surround INNER with a USE to indicate this. */
4971 if (GET_CODE (pos
) == CONST_INT
4972 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
4973 inner
= gen_rtx (USE
, GET_MODE (SET_DEST (x
)), inner
);
4975 if (BITS_BIG_ENDIAN
)
4977 if (GET_CODE (pos
) == CONST_INT
)
4978 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
4980 else if (GET_CODE (pos
) == MINUS
4981 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
4982 && (INTVAL (XEXP (pos
, 1))
4983 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
4984 /* If position is ADJUST - X, new position is X. */
4985 pos
= XEXP (pos
, 0);
4987 pos
= gen_binary (MINUS
, GET_MODE (pos
),
4988 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
4994 /* A SUBREG between two modes that occupy the same numbers of words
4995 can be done by moving the SUBREG to the source. */
4996 else if (GET_CODE (SET_DEST (x
)) == SUBREG
4997 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
4998 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
4999 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5000 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5002 x
= gen_rtx (SET
, VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5003 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5010 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5011 inner
= SUBREG_REG (inner
);
5013 compute_mode
= GET_MODE (inner
);
5015 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5016 if (len
< HOST_BITS_PER_WIDE_INT
)
5017 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5021 /* Now compute the equivalent expression. Make a copy of INNER
5022 for the SET_DEST in case it is a MEM into which we will substitute;
5023 we don't want shared RTL in that case. */
5024 x
= gen_rtx (SET
, VOIDmode
, copy_rtx (inner
),
5025 gen_binary (IOR
, compute_mode
,
5026 gen_binary (AND
, compute_mode
,
5027 gen_unary (NOT
, compute_mode
,
5033 gen_binary (ASHIFT
, compute_mode
,
5034 gen_binary (AND
, compute_mode
,
5035 gen_lowpart_for_combine
5045 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5046 it is an RTX that represents a variable starting position; otherwise,
5047 POS is the (constant) starting bit position (counted from the LSB).
5049 INNER may be a USE. This will occur when we started with a bitfield
5050 that went outside the boundary of the object in memory, which is
5051 allowed on most machines. To isolate this case, we produce a USE
5052 whose mode is wide enough and surround the MEM with it. The only
5053 code that understands the USE is this routine. If it is not removed,
5054 it will cause the resulting insn not to match.
5056 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5059 IN_DEST is non-zero if this is a reference in the destination of a
5060 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5061 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5064 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5065 ZERO_EXTRACT should be built even for bits starting at bit 0.
5067 MODE is the desired mode of the result (if IN_DEST == 0).
5069 The result is an RTX for the extraction or NULL_RTX if the target
5073 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5074 unsignedp
, in_dest
, in_compare
)
5075 enum machine_mode mode
;
5081 int in_dest
, in_compare
;
5083 /* This mode describes the size of the storage area
5084 to fetch the overall value from. Within that, we
5085 ignore the POS lowest bits, etc. */
5086 enum machine_mode is_mode
= GET_MODE (inner
);
5087 enum machine_mode inner_mode
;
5088 enum machine_mode wanted_inner_mode
= byte_mode
;
5089 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5090 enum machine_mode pos_mode
= word_mode
;
5091 enum machine_mode extraction_mode
= word_mode
;
5092 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5095 rtx orig_pos_rtx
= pos_rtx
;
5098 /* Get some information about INNER and get the innermost object. */
5099 if (GET_CODE (inner
) == USE
)
5100 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5101 /* We don't need to adjust the position because we set up the USE
5102 to pretend that it was a full-word object. */
5103 spans_byte
= 1, inner
= XEXP (inner
, 0);
5104 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5106 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5107 consider just the QI as the memory to extract from.
5108 The subreg adds or removes high bits; its mode is
5109 irrelevant to the meaning of this extraction,
5110 since POS and LEN count from the lsb. */
5111 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5112 is_mode
= GET_MODE (SUBREG_REG (inner
));
5113 inner
= SUBREG_REG (inner
);
5116 inner_mode
= GET_MODE (inner
);
5118 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5119 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5121 /* See if this can be done without an extraction. We never can if the
5122 width of the field is not the same as that of some integer mode. For
5123 registers, we can only avoid the extraction if the position is at the
5124 low-order bit and this is either not in the destination or we have the
5125 appropriate STRICT_LOW_PART operation available.
5127 For MEM, we can avoid an extract if the field starts on an appropriate
5128 boundary and we can change the mode of the memory reference. However,
5129 we cannot directly access the MEM if we have a USE and the underlying
5130 MEM is not TMODE. This combination means that MEM was being used in a
5131 context where bits outside its mode were being referenced; that is only
5132 valid in bit-field insns. */
5134 if (tmode
!= BLKmode
5135 && ! (spans_byte
&& inner_mode
!= tmode
)
5136 && ((pos_rtx
== 0 && pos
== 0 && GET_CODE (inner
) != MEM
5138 || (GET_CODE (inner
) == REG
5139 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5140 != CODE_FOR_nothing
))))
5141 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5143 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5144 : BITS_PER_UNIT
)) == 0
5145 /* We can't do this if we are widening INNER_MODE (it
5146 may not be aligned, for one thing). */
5147 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5148 && (inner_mode
== tmode
5149 || (! mode_dependent_address_p (XEXP (inner
, 0))
5150 && ! MEM_VOLATILE_P (inner
))))))
5152 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5153 field. If the original and current mode are the same, we need not
5154 adjust the offset. Otherwise, we do if bytes big endian.
5156 If INNER is not a MEM, get a piece consisting of the just the field
5157 of interest (in this case POS must be 0). */
5159 if (GET_CODE (inner
) == MEM
)
5162 /* POS counts from lsb, but make OFFSET count in memory order. */
5163 if (BYTES_BIG_ENDIAN
)
5164 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5166 offset
= pos
/ BITS_PER_UNIT
;
5168 new = gen_rtx (MEM
, tmode
, plus_constant (XEXP (inner
, 0), offset
));
5169 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
5170 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner
);
5171 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner
);
5173 else if (GET_CODE (inner
) == REG
)
5175 /* We can't call gen_lowpart_for_combine here since we always want
5176 a SUBREG and it would sometimes return a new hard register. */
5177 if (tmode
!= inner_mode
)
5178 new = gen_rtx (SUBREG
, tmode
, inner
,
5180 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
5181 ? ((GET_MODE_SIZE (inner_mode
)
5182 - GET_MODE_SIZE (tmode
))
5189 new = force_to_mode (inner
, tmode
,
5190 len
>= HOST_BITS_PER_WIDE_INT
5191 ? GET_MODE_MASK (tmode
)
5192 : ((HOST_WIDE_INT
) 1 << len
) - 1,
5195 /* If this extraction is going into the destination of a SET,
5196 make a STRICT_LOW_PART unless we made a MEM. */
5199 return (GET_CODE (new) == MEM
? new
5200 : (GET_CODE (new) != SUBREG
5201 ? gen_rtx (CLOBBER
, tmode
, const0_rtx
)
5202 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
5204 /* Otherwise, sign- or zero-extend unless we already are in the
5207 return (mode
== tmode
? new
5208 : gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5212 /* Unless this is a COMPARE or we have a funny memory reference,
5213 don't do anything with zero-extending field extracts starting at
5214 the low-order bit since they are simple AND operations. */
5215 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5216 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5219 /* Unless we are allowed to span bytes, reject this if we would be
5220 spanning bytes or if the position is not a constant and the length
5221 is not 1. In all other cases, we would only be going outside
5222 out object in cases when an original shift would have been
5225 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
5226 || (pos_rtx
!= 0 && len
!= 1)))
5229 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5230 and the mode for the result. */
5234 wanted_inner_reg_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][0];
5235 pos_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][2];
5236 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][3];
5241 if (! in_dest
&& unsignedp
)
5243 wanted_inner_reg_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
5244 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][3];
5245 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][0];
5250 if (! in_dest
&& ! unsignedp
)
5252 wanted_inner_reg_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][1];
5253 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][3];
5254 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][0];
5258 /* Never narrow an object, since that might not be safe. */
5260 if (mode
!= VOIDmode
5261 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
5262 extraction_mode
= mode
;
5264 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
5265 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5266 pos_mode
= GET_MODE (pos_rtx
);
5268 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5269 if we have to change the mode of memory and cannot, the desired mode is
5271 if (GET_CODE (inner
) != MEM
)
5272 wanted_inner_mode
= wanted_inner_reg_mode
;
5273 else if (inner_mode
!= wanted_inner_mode
5274 && (mode_dependent_address_p (XEXP (inner
, 0))
5275 || MEM_VOLATILE_P (inner
)))
5276 wanted_inner_mode
= extraction_mode
;
5280 if (BITS_BIG_ENDIAN
)
5282 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5283 BITS_BIG_ENDIAN style. If position is constant, compute new
5284 position. Otherwise, build subtraction.
5285 Note that POS is relative to the mode of the original argument.
5286 If it's a MEM we need to recompute POS relative to that.
5287 However, if we're extracting from (or inserting into) a register,
5288 we want to recompute POS relative to wanted_inner_mode. */
5289 int width
= (GET_CODE (inner
) == MEM
5290 ? GET_MODE_BITSIZE (is_mode
)
5291 : GET_MODE_BITSIZE (wanted_inner_mode
));
5294 pos
= width
- len
- pos
;
5297 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
5298 GEN_INT (width
- len
), pos_rtx
);
5299 /* POS may be less than 0 now, but we check for that below.
5300 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5303 /* If INNER has a wider mode, make it smaller. If this is a constant
5304 extract, try to adjust the byte to point to the byte containing
5306 if (wanted_inner_mode
!= VOIDmode
5307 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
5308 && ((GET_CODE (inner
) == MEM
5309 && (inner_mode
== wanted_inner_mode
5310 || (! mode_dependent_address_p (XEXP (inner
, 0))
5311 && ! MEM_VOLATILE_P (inner
))))))
5315 /* The computations below will be correct if the machine is big
5316 endian in both bits and bytes or little endian in bits and bytes.
5317 If it is mixed, we must adjust. */
5319 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5320 adjust OFFSET to compensate. */
5321 if (BYTES_BIG_ENDIAN
5323 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
5324 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
5326 /* If this is a constant position, we can move to the desired byte. */
5329 offset
+= pos
/ BITS_PER_UNIT
;
5330 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
5333 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
5335 && is_mode
!= wanted_inner_mode
)
5336 offset
= (GET_MODE_SIZE (is_mode
)
5337 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
5339 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
5341 rtx newmem
= gen_rtx (MEM
, wanted_inner_mode
,
5342 plus_constant (XEXP (inner
, 0), offset
));
5343 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
5344 MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (inner
);
5345 MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (inner
);
5350 /* If INNER is not memory, we can always get it into the proper mode. If we
5351 are changing its mode, POS must be a constant and smaller than the size
5353 else if (GET_CODE (inner
) != MEM
)
5355 if (GET_MODE (inner
) != wanted_inner_mode
5357 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
5360 inner
= force_to_mode (inner
, wanted_inner_mode
,
5362 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
5363 ? GET_MODE_MASK (wanted_inner_mode
)
5364 : (((HOST_WIDE_INT
) 1 << len
) - 1) << orig_pos
,
5368 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5369 have to zero extend. Otherwise, we can just use a SUBREG. */
5371 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5372 pos_rtx
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
5373 else if (pos_rtx
!= 0
5374 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5375 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
5377 /* Make POS_RTX unless we already have it and it is correct. If we don't
5378 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5380 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
5381 pos_rtx
= orig_pos_rtx
;
5383 else if (pos_rtx
== 0)
5384 pos_rtx
= GEN_INT (pos
);
5386 /* Make the required operation. See if we can use existing rtx. */
5387 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
5388 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
5390 new = gen_lowpart_for_combine (mode
, new);
5395 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5396 with any other operations in X. Return X without that shift if so. */
5399 extract_left_shift (x
, count
)
5403 enum rtx_code code
= GET_CODE (x
);
5404 enum machine_mode mode
= GET_MODE (x
);
5410 /* This is the shift itself. If it is wide enough, we will return
5411 either the value being shifted if the shift count is equal to
5412 COUNT or a shift for the difference. */
5413 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5414 && INTVAL (XEXP (x
, 1)) >= count
)
5415 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
5416 INTVAL (XEXP (x
, 1)) - count
);
5420 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
5421 return gen_unary (code
, mode
, mode
, tem
);
5425 case PLUS
: case IOR
: case XOR
: case AND
:
5426 /* If we can safely shift this constant and we find the inner shift,
5427 make a new operation. */
5428 if (GET_CODE (XEXP (x
,1)) == CONST_INT
5429 && (INTVAL (XEXP (x
, 1)) & (((HOST_WIDE_INT
) 1 << count
)) - 1) == 0
5430 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
5431 return gen_binary (code
, mode
, tem
,
5432 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
5440 /* Look at the expression rooted at X. Look for expressions
5441 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5442 Form these expressions.
5444 Return the new rtx, usually just X.
5446 Also, for machines like the Vax that don't have logical shift insns,
5447 try to convert logical to arithmetic shift operations in cases where
5448 they are equivalent. This undoes the canonicalizations to logical
5449 shifts done elsewhere.
5451 We try, as much as possible, to re-use rtl expressions to save memory.
5453 IN_CODE says what kind of expression we are processing. Normally, it is
5454 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5455 being kludges), it is MEM. When processing the arguments of a comparison
5456 or a COMPARE against zero, it is COMPARE. */
5459 make_compound_operation (x
, in_code
)
5461 enum rtx_code in_code
;
5463 enum rtx_code code
= GET_CODE (x
);
5464 enum machine_mode mode
= GET_MODE (x
);
5465 int mode_width
= GET_MODE_BITSIZE (mode
);
5467 enum rtx_code next_code
;
5473 /* Select the code to be used in recursive calls. Once we are inside an
5474 address, we stay there. If we have a comparison, set to COMPARE,
5475 but once inside, go back to our default of SET. */
5477 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
5478 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
5479 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
5480 : in_code
== COMPARE
? SET
: in_code
);
5482 /* Process depending on the code of this operation. If NEW is set
5483 non-zero, it will be returned. */
5488 /* Convert shifts by constants into multiplications if inside
5490 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
5491 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
5492 && INTVAL (XEXP (x
, 1)) >= 0)
5494 new = make_compound_operation (XEXP (x
, 0), next_code
);
5495 new = gen_rtx_combine (MULT
, mode
, new,
5496 GEN_INT ((HOST_WIDE_INT
) 1
5497 << INTVAL (XEXP (x
, 1))));
5502 /* If the second operand is not a constant, we can't do anything
5504 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5507 /* If the constant is a power of two minus one and the first operand
5508 is a logical right shift, make an extraction. */
5509 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5510 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5512 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
5513 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
5514 0, in_code
== COMPARE
);
5517 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5518 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
5519 && subreg_lowpart_p (XEXP (x
, 0))
5520 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
5521 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5523 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
5525 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
5526 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
5527 0, in_code
== COMPARE
);
5529 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5530 else if ((GET_CODE (XEXP (x
, 0)) == XOR
5531 || GET_CODE (XEXP (x
, 0)) == IOR
)
5532 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
5533 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
5534 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5536 /* Apply the distributive law, and then try to make extractions. */
5537 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
5538 gen_rtx (AND
, mode
, XEXP (XEXP (x
, 0), 0),
5540 gen_rtx (AND
, mode
, XEXP (XEXP (x
, 0), 1),
5542 new = make_compound_operation (new, in_code
);
5545 /* If we are have (and (rotate X C) M) and C is larger than the number
5546 of bits in M, this is an extraction. */
5548 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
5549 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5550 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
5551 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
5553 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
5554 new = make_extraction (mode
, new,
5555 (GET_MODE_BITSIZE (mode
)
5556 - INTVAL (XEXP (XEXP (x
, 0), 1))),
5557 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
5560 /* On machines without logical shifts, if the operand of the AND is
5561 a logical shift and our mask turns off all the propagated sign
5562 bits, we can replace the logical shift with an arithmetic shift. */
5563 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
5564 && (lshr_optab
->handlers
[(int) mode
].insn_code
5565 == CODE_FOR_nothing
)
5566 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5567 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5568 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
5569 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
5570 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
5572 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
5574 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
5575 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
5577 gen_rtx_combine (ASHIFTRT
, mode
,
5578 make_compound_operation (XEXP (XEXP (x
, 0), 0),
5580 XEXP (XEXP (x
, 0), 1)));
5583 /* If the constant is one less than a power of two, this might be
5584 representable by an extraction even if no shift is present.
5585 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5586 we are in a COMPARE. */
5587 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5588 new = make_extraction (mode
,
5589 make_compound_operation (XEXP (x
, 0),
5591 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
5593 /* If we are in a comparison and this is an AND with a power of two,
5594 convert this into the appropriate bit extract. */
5595 else if (in_code
== COMPARE
5596 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
5597 new = make_extraction (mode
,
5598 make_compound_operation (XEXP (x
, 0),
5600 i
, NULL_RTX
, 1, 1, 0, 1);
5605 /* If the sign bit is known to be zero, replace this with an
5606 arithmetic shift. */
5607 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
5608 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
5609 && mode_width
<= HOST_BITS_PER_WIDE_INT
5610 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
5612 new = gen_rtx_combine (ASHIFTRT
, mode
,
5613 make_compound_operation (XEXP (x
, 0),
5619 /* ... fall through ... */
5625 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5626 this is a SIGN_EXTRACT. */
5627 if (GET_CODE (rhs
) == CONST_INT
5628 && GET_CODE (lhs
) == ASHIFT
5629 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
5630 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
5632 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
5633 new = make_extraction (mode
, new,
5634 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
5635 NULL_RTX
, mode_width
- INTVAL (rhs
),
5636 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
5639 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5640 If so, try to merge the shifts into a SIGN_EXTEND. We could
5641 also do this for some cases of SIGN_EXTRACT, but it doesn't
5642 seem worth the effort; the case checked for occurs on Alpha. */
5644 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
5645 && ! (GET_CODE (lhs
) == SUBREG
5646 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
5647 && GET_CODE (rhs
) == CONST_INT
5648 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
5649 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
5650 new = make_extraction (mode
, make_compound_operation (new, next_code
),
5651 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
5652 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
5657 /* Call ourselves recursively on the inner expression. If we are
5658 narrowing the object and it has a different RTL code from
5659 what it originally did, do this SUBREG as a force_to_mode. */
5661 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
5662 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
5663 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
5664 && subreg_lowpart_p (x
))
5666 rtx newer
= force_to_mode (tem
, mode
,
5667 GET_MODE_MASK (mode
), NULL_RTX
, 0);
5669 /* If we have something other than a SUBREG, we might have
5670 done an expansion, so rerun outselves. */
5671 if (GET_CODE (newer
) != SUBREG
)
5672 newer
= make_compound_operation (newer
, in_code
);
5680 x
= gen_lowpart_for_combine (mode
, new);
5681 code
= GET_CODE (x
);
5684 /* Now recursively process each operand of this operation. */
5685 fmt
= GET_RTX_FORMAT (code
);
5686 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
5689 new = make_compound_operation (XEXP (x
, i
), next_code
);
5690 SUBST (XEXP (x
, i
), new);
5696 /* Given M see if it is a value that would select a field of bits
5697 within an item, but not the entire word. Return -1 if not.
5698 Otherwise, return the starting position of the field, where 0 is the
5701 *PLEN is set to the length of the field. */
5704 get_pos_from_mask (m
, plen
)
5705 unsigned HOST_WIDE_INT m
;
5708 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5709 int pos
= exact_log2 (m
& - m
);
5714 /* Now shift off the low-order zero bits and see if we have a power of
5716 *plen
= exact_log2 ((m
>> pos
) + 1);
5724 /* See if X can be simplified knowing that we will only refer to it in
5725 MODE and will only refer to those bits that are nonzero in MASK.
5726 If other bits are being computed or if masking operations are done
5727 that select a superset of the bits in MASK, they can sometimes be
5730 Return a possibly simplified expression, but always convert X to
5731 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5733 Also, if REG is non-zero and X is a register equal in value to REG,
5736 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5737 are all off in X. This is used when X will be complemented, by either
5738 NOT, NEG, or XOR. */
5741 force_to_mode (x
, mode
, mask
, reg
, just_select
)
5743 enum machine_mode mode
;
5744 unsigned HOST_WIDE_INT mask
;
5748 enum rtx_code code
= GET_CODE (x
);
5749 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
5750 enum machine_mode op_mode
;
5751 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
5754 /* If this is a CALL, don't do anything. Some of the code below
5755 will do the wrong thing since the mode of a CALL is VOIDmode. */
5759 /* We want to perform the operation is its present mode unless we know
5760 that the operation is valid in MODE, in which case we do the operation
5762 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
5763 && code_to_optab
[(int) code
] != 0
5764 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
5765 != CODE_FOR_nothing
))
5766 ? mode
: GET_MODE (x
));
5768 /* It is not valid to do a right-shift in a narrower mode
5769 than the one it came in with. */
5770 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
5771 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
5772 op_mode
= GET_MODE (x
);
5774 /* Truncate MASK to fit OP_MODE. */
5776 mask
&= GET_MODE_MASK (op_mode
);
5778 /* When we have an arithmetic operation, or a shift whose count we
5779 do not know, we need to assume that all bit the up to the highest-order
5780 bit in MASK will be needed. This is how we form such a mask. */
5782 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
5783 ? GET_MODE_MASK (op_mode
)
5784 : ((HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1)) - 1);
5786 fuller_mask
= ~ (HOST_WIDE_INT
) 0;
5788 /* Determine what bits of X are guaranteed to be (non)zero. */
5789 nonzero
= nonzero_bits (x
, mode
);
5791 /* If none of the bits in X are needed, return a zero. */
5792 if (! just_select
&& (nonzero
& mask
) == 0)
5795 /* If X is a CONST_INT, return a new one. Do this here since the
5796 test below will fail. */
5797 if (GET_CODE (x
) == CONST_INT
)
5799 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
5800 int width
= GET_MODE_BITSIZE (mode
);
5802 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5803 number, sign extend it. */
5804 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
5805 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
5806 cval
|= (HOST_WIDE_INT
) -1 << width
;
5808 return GEN_INT (cval
);
5811 /* If X is narrower than MODE and we want all the bits in X's mode, just
5812 get X in the proper mode. */
5813 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
5814 && (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
) == 0)
5815 return gen_lowpart_for_combine (mode
, x
);
5817 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
5818 MASK are already known to be zero in X, we need not do anything. */
5819 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~ mask
& nonzero
) == 0)
5825 /* If X is a (clobber (const_int)), return it since we know we are
5826 generating something that won't match. */
5830 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5831 spanned the boundary of the MEM. If we are now masking so it is
5832 within that boundary, we don't need the USE any more. */
5833 if (! BITS_BIG_ENDIAN
5834 && (mask
& ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5835 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
5842 x
= expand_compound_operation (x
);
5843 if (GET_CODE (x
) != code
)
5844 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
5848 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
5849 || rtx_equal_p (reg
, get_last_value (x
))))
5854 if (subreg_lowpart_p (x
)
5855 /* We can ignore the effect of this SUBREG if it narrows the mode or
5856 if the constant masks to zero all the bits the mode doesn't
5858 && ((GET_MODE_SIZE (GET_MODE (x
))
5859 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
5861 & GET_MODE_MASK (GET_MODE (x
))
5862 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
5863 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
5867 /* If this is an AND with a constant, convert it into an AND
5868 whose constant is the AND of that constant with MASK. If it
5869 remains an AND of MASK, delete it since it is redundant. */
5871 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5873 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
5874 mask
& INTVAL (XEXP (x
, 1)));
5876 /* If X is still an AND, see if it is an AND with a mask that
5877 is just some low-order bits. If so, and it is MASK, we don't
5880 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
5881 && INTVAL (XEXP (x
, 1)) == mask
)
5884 /* If it remains an AND, try making another AND with the bits
5885 in the mode mask that aren't in MASK turned on. If the
5886 constant in the AND is wide enough, this might make a
5887 cheaper constant. */
5889 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
5890 && GET_MODE_MASK (GET_MODE (x
)) != mask
5891 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
5893 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
5894 | (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
));
5895 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
5898 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5899 number, sign extend it. */
5900 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
5901 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
5902 cval
|= (HOST_WIDE_INT
) -1 << width
;
5904 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
5905 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
5915 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5916 low-order bits (as in an alignment operation) and FOO is already
5917 aligned to that boundary, mask C1 to that boundary as well.
5918 This may eliminate that PLUS and, later, the AND. */
5921 int width
= GET_MODE_BITSIZE (mode
);
5922 unsigned HOST_WIDE_INT smask
= mask
;
5924 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
5925 number, sign extend it. */
5927 if (width
< HOST_BITS_PER_WIDE_INT
5928 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
5929 smask
|= (HOST_WIDE_INT
) -1 << width
;
5931 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5932 && exact_log2 (- smask
) >= 0
5933 && (nonzero_bits (XEXP (x
, 0), mode
) & ~ mask
) == 0
5934 && (INTVAL (XEXP (x
, 1)) & ~ mask
) != 0)
5935 return force_to_mode (plus_constant (XEXP (x
, 0),
5936 INTVAL (XEXP (x
, 1)) & mask
),
5937 mode
, mask
, reg
, next_select
);
5940 /* ... fall through ... */
5944 /* For PLUS, MINUS and MULT, we need any bits less significant than the
5945 most significant bit in MASK since carries from those bits will
5946 affect the bits we are interested in. */
5952 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5953 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5954 operation which may be a bitfield extraction. Ensure that the
5955 constant we form is not wider than the mode of X. */
5957 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5958 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5959 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
5960 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
5961 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5962 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
5963 + floor_log2 (INTVAL (XEXP (x
, 1))))
5964 < GET_MODE_BITSIZE (GET_MODE (x
)))
5965 && (INTVAL (XEXP (x
, 1))
5966 & ~ nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
5968 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
5969 << INTVAL (XEXP (XEXP (x
, 0), 1)));
5970 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
5971 XEXP (XEXP (x
, 0), 0), temp
);
5972 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
5973 XEXP (XEXP (x
, 0), 1));
5974 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
5978 /* For most binary operations, just propagate into the operation and
5979 change the mode if we have an operation of that mode. */
5981 op0
= gen_lowpart_for_combine (op_mode
,
5982 force_to_mode (XEXP (x
, 0), mode
, mask
,
5984 op1
= gen_lowpart_for_combine (op_mode
,
5985 force_to_mode (XEXP (x
, 1), mode
, mask
,
5988 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
5989 MASK since OP1 might have been sign-extended but we never want
5990 to turn on extra bits, since combine might have previously relied
5991 on them being off. */
5992 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
5993 && (INTVAL (op1
) & mask
) != 0)
5994 op1
= GEN_INT (INTVAL (op1
) & mask
);
5996 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
5997 x
= gen_binary (code
, op_mode
, op0
, op1
);
6001 /* For left shifts, do the same, but just for the first operand.
6002 However, we cannot do anything with shifts where we cannot
6003 guarantee that the counts are smaller than the size of the mode
6004 because such a count will have a different meaning in a
6007 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6008 && INTVAL (XEXP (x
, 1)) >= 0
6009 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6010 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6011 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6012 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6015 /* If the shift count is a constant and we can do arithmetic in
6016 the mode of the shift, refine which bits we need. Otherwise, use the
6017 conservative form of the mask. */
6018 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6019 && INTVAL (XEXP (x
, 1)) >= 0
6020 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6021 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6022 mask
>>= INTVAL (XEXP (x
, 1));
6026 op0
= gen_lowpart_for_combine (op_mode
,
6027 force_to_mode (XEXP (x
, 0), op_mode
,
6028 mask
, reg
, next_select
));
6030 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6031 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6035 /* Here we can only do something if the shift count is a constant,
6036 this shift constant is valid for the host, and we can do arithmetic
6039 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6040 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6041 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6043 rtx inner
= XEXP (x
, 0);
6045 /* Select the mask of the bits we need for the shift operand. */
6046 mask
<<= INTVAL (XEXP (x
, 1));
6048 /* We can only change the mode of the shift if we can do arithmetic
6049 in the mode of the shift and MASK is no wider than the width of
6051 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6052 || (mask
& ~ GET_MODE_MASK (op_mode
)) != 0)
6053 op_mode
= GET_MODE (x
);
6055 inner
= force_to_mode (inner
, op_mode
, mask
, reg
, next_select
);
6057 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6058 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6061 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6062 shift and AND produces only copies of the sign bit (C2 is one less
6063 than a power of two), we can do this with just a shift. */
6065 if (GET_CODE (x
) == LSHIFTRT
6066 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6067 && ((INTVAL (XEXP (x
, 1))
6068 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6069 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6070 && exact_log2 (mask
+ 1) >= 0
6071 && (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6072 >= exact_log2 (mask
+ 1)))
6073 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6074 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6075 - exact_log2 (mask
+ 1)));
6079 /* If we are just looking for the sign bit, we don't need this shift at
6080 all, even if it has a variable count. */
6081 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6082 && (mask
== ((HOST_WIDE_INT
) 1
6083 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6084 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6086 /* If this is a shift by a constant, get a mask that contains those bits
6087 that are not copies of the sign bit. We then have two cases: If
6088 MASK only includes those bits, this can be a logical shift, which may
6089 allow simplifications. If MASK is a single-bit field not within
6090 those bits, we are requesting a copy of the sign bit and hence can
6091 shift the sign bit to the appropriate location. */
6093 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6094 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6098 /* If the considered data is wider then HOST_WIDE_INT, we can't
6099 represent a mask for all its bits in a single scalar.
6100 But we only care about the lower bits, so calculate these. */
6102 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6104 nonzero
= ~(HOST_WIDE_INT
)0;
6106 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6107 is the number of bits a full-width mask would have set.
6108 We need only shift if these are fewer than nonzero can
6109 hold. If not, we must keep all bits set in nonzero. */
6111 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
6112 < HOST_BITS_PER_WIDE_INT
)
6113 nonzero
>>= INTVAL (XEXP (x
, 1))
6114 + HOST_BITS_PER_WIDE_INT
6115 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
6119 nonzero
= GET_MODE_MASK (GET_MODE (x
));
6120 nonzero
>>= INTVAL (XEXP (x
, 1));
6123 if ((mask
& ~ nonzero
) == 0
6124 || (i
= exact_log2 (mask
)) >= 0)
6126 x
= simplify_shift_const
6127 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6128 i
< 0 ? INTVAL (XEXP (x
, 1))
6129 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
6131 if (GET_CODE (x
) != ASHIFTRT
)
6132 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6136 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6137 even if the shift count isn't a constant. */
6139 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
6141 /* If this is a sign-extension operation that just affects bits
6142 we don't care about, remove it. Be sure the call above returned
6143 something that is still a shift. */
6145 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
6146 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6147 && INTVAL (XEXP (x
, 1)) >= 0
6148 && (INTVAL (XEXP (x
, 1))
6149 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
6150 && GET_CODE (XEXP (x
, 0)) == ASHIFT
6151 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6152 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
6153 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
6160 /* If the shift count is constant and we can do computations
6161 in the mode of X, compute where the bits we care about are.
6162 Otherwise, we can't do anything. Don't change the mode of
6163 the shift or propagate MODE into the shift, though. */
6164 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6165 && INTVAL (XEXP (x
, 1)) >= 0)
6167 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
6168 GET_MODE (x
), GEN_INT (mask
),
6170 if (temp
&& GET_CODE(temp
) == CONST_INT
)
6172 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
6173 INTVAL (temp
), reg
, next_select
));
6178 /* If we just want the low-order bit, the NEG isn't needed since it
6179 won't change the low-order bit. */
6181 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
6183 /* We need any bits less significant than the most significant bit in
6184 MASK since carries from those bits will affect the bits we are
6190 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6191 same as the XOR case above. Ensure that the constant we form is not
6192 wider than the mode of X. */
6194 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6195 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6196 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6197 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
6198 < GET_MODE_BITSIZE (GET_MODE (x
)))
6199 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
6201 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
6202 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
6203 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
6205 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6208 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6209 use the full mask inside the NOT. */
6213 op0
= gen_lowpart_for_combine (op_mode
,
6214 force_to_mode (XEXP (x
, 0), mode
, mask
,
6216 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6217 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
6221 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6222 in STORE_FLAG_VALUE and FOO has no bits that might be nonzero not
6224 if ((mask
& ~ STORE_FLAG_VALUE
) == 0 && XEXP (x
, 0) == const0_rtx
6225 && (nonzero_bits (XEXP (x
, 0), mode
) & ~ mask
) == 0)
6226 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6231 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6232 written in a narrower mode. We play it safe and do not do so. */
6235 gen_lowpart_for_combine (GET_MODE (x
),
6236 force_to_mode (XEXP (x
, 1), mode
,
6237 mask
, reg
, next_select
)));
6239 gen_lowpart_for_combine (GET_MODE (x
),
6240 force_to_mode (XEXP (x
, 2), mode
,
6241 mask
, reg
,next_select
)));
6245 /* Ensure we return a value of the proper mode. */
6246 return gen_lowpart_for_combine (mode
, x
);
6249 /* Return nonzero if X is an expression that has one of two values depending on
6250 whether some other value is zero or nonzero. In that case, we return the
6251 value that is being tested, *PTRUE is set to the value if the rtx being
6252 returned has a nonzero value, and *PFALSE is set to the other alternative.
6254 If we return zero, we set *PTRUE and *PFALSE to X. */
6257 if_then_else_cond (x
, ptrue
, pfalse
)
6259 rtx
*ptrue
, *pfalse
;
6261 enum machine_mode mode
= GET_MODE (x
);
6262 enum rtx_code code
= GET_CODE (x
);
6263 int size
= GET_MODE_BITSIZE (mode
);
6264 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
6265 unsigned HOST_WIDE_INT nz
;
6267 /* If this is a unary operation whose operand has one of two values, apply
6268 our opcode to compute those values. */
6269 if (GET_RTX_CLASS (code
) == '1'
6270 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
6272 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
6273 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
6277 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6278 make can't possibly match and would suppress other optimizations. */
6279 else if (code
== COMPARE
)
6282 /* If this is a binary operation, see if either side has only one of two
6283 values. If either one does or if both do and they are conditional on
6284 the same value, compute the new true and false values. */
6285 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
6286 || GET_RTX_CLASS (code
) == '<')
6288 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
6289 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
6291 if ((cond0
!= 0 || cond1
!= 0)
6292 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
6294 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
6295 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
6296 return cond0
? cond0
: cond1
;
6299 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6301 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6302 operands is zero when the other is non-zero, and vice-versa. */
6304 if ((code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
6306 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
6308 rtx op0
= XEXP (XEXP (x
, 0), 1);
6309 rtx op1
= XEXP (XEXP (x
, 1), 1);
6311 cond0
= XEXP (XEXP (x
, 0), 0);
6312 cond1
= XEXP (XEXP (x
, 1), 0);
6314 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
6315 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
6316 && reversible_comparison_p (cond1
)
6317 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
6318 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
6319 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
6320 || ((swap_condition (GET_CODE (cond0
))
6321 == reverse_condition (GET_CODE (cond1
)))
6322 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
6323 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
6324 && ! side_effects_p (x
))
6326 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
6327 *pfalse
= gen_binary (MULT
, mode
,
6329 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
6335 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6337 if ((code
== MULT
|| code
== AND
|| code
== UMIN
)
6338 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
6340 cond0
= XEXP (XEXP (x
, 0), 0);
6341 cond1
= XEXP (XEXP (x
, 1), 0);
6343 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
6344 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
6345 && reversible_comparison_p (cond1
)
6346 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
6347 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
6348 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
6349 || ((swap_condition (GET_CODE (cond0
))
6350 == reverse_condition (GET_CODE (cond1
)))
6351 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
6352 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
6353 && ! side_effects_p (x
))
6355 *ptrue
= *pfalse
= const0_rtx
;
6362 else if (code
== IF_THEN_ELSE
)
6364 /* If we have IF_THEN_ELSE already, extract the condition and
6365 canonicalize it if it is NE or EQ. */
6366 cond0
= XEXP (x
, 0);
6367 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
6368 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
6369 return XEXP (cond0
, 0);
6370 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
6372 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
6373 return XEXP (cond0
, 0);
6379 /* If X is a normal SUBREG with both inner and outer modes integral,
6380 we can narrow both the true and false values of the inner expression,
6381 if there is a condition. */
6382 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
6383 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
6384 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
6385 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
6388 *ptrue
= force_to_mode (true0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
6390 = force_to_mode (false0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
6395 /* If X is a constant, this isn't special and will cause confusions
6396 if we treat it as such. Likewise if it is equivalent to a constant. */
6397 else if (CONSTANT_P (x
)
6398 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
6401 /* If X is known to be either 0 or -1, those are the true and
6402 false values when testing X. */
6403 else if (num_sign_bit_copies (x
, mode
) == size
)
6405 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
6409 /* Likewise for 0 or a single bit. */
6410 else if (exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
6412 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
6416 /* Otherwise fail; show no condition with true and false values the same. */
6417 *ptrue
= *pfalse
= x
;
6421 /* Return the value of expression X given the fact that condition COND
6422 is known to be true when applied to REG as its first operand and VAL
6423 as its second. X is known to not be shared and so can be modified in
6426 We only handle the simplest cases, and specifically those cases that
6427 arise with IF_THEN_ELSE expressions. */
6430 known_cond (x
, cond
, reg
, val
)
6435 enum rtx_code code
= GET_CODE (x
);
6440 if (side_effects_p (x
))
6443 if (cond
== EQ
&& rtx_equal_p (x
, reg
))
6446 /* If X is (abs REG) and we know something about REG's relationship
6447 with zero, we may be able to simplify this. */
6449 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
6452 case GE
: case GT
: case EQ
:
6455 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
6459 /* The only other cases we handle are MIN, MAX, and comparisons if the
6460 operands are the same as REG and VAL. */
6462 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
6464 if (rtx_equal_p (XEXP (x
, 0), val
))
6465 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
6467 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
6469 if (GET_RTX_CLASS (code
) == '<')
6470 return (comparison_dominates_p (cond
, code
) ? const_true_rtx
6471 : (comparison_dominates_p (cond
,
6472 reverse_condition (code
))
6475 else if (code
== SMAX
|| code
== SMIN
6476 || code
== UMIN
|| code
== UMAX
)
6478 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
6480 if (code
== SMAX
|| code
== UMAX
)
6481 cond
= reverse_condition (cond
);
6486 return unsignedp
? x
: XEXP (x
, 1);
6488 return unsignedp
? x
: XEXP (x
, 0);
6490 return unsignedp
? XEXP (x
, 1) : x
;
6492 return unsignedp
? XEXP (x
, 0) : x
;
6498 fmt
= GET_RTX_FORMAT (code
);
6499 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6502 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
6503 else if (fmt
[i
] == 'E')
6504 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6505 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
6512 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6513 assignment as a field assignment. */
6516 rtx_equal_for_field_assignment_p (x
, y
)
6522 if (x
== y
|| rtx_equal_p (x
, y
))
6525 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
6528 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6529 Note that all SUBREGs of MEM are paradoxical; otherwise they
6530 would have been rewritten. */
6531 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
6532 && GET_CODE (SUBREG_REG (y
)) == MEM
6533 && rtx_equal_p (SUBREG_REG (y
),
6534 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
6537 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
6538 && GET_CODE (SUBREG_REG (x
)) == MEM
6539 && rtx_equal_p (SUBREG_REG (x
),
6540 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
6543 last_x
= get_last_value (x
);
6544 last_y
= get_last_value (y
);
6546 return ((last_x
!= 0 && rtx_equal_for_field_assignment_p (last_x
, y
))
6547 || (last_y
!= 0 && rtx_equal_for_field_assignment_p (x
, last_y
))
6548 || (last_x
!= 0 && last_y
!= 0
6549 && rtx_equal_for_field_assignment_p (last_x
, last_y
)));
6552 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6553 Return that assignment if so.
6555 We only handle the most common cases. */
6558 make_field_assignment (x
)
6561 rtx dest
= SET_DEST (x
);
6562 rtx src
= SET_SRC (x
);
6568 enum machine_mode mode
;
6570 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6571 a clear of a one-bit field. We will have changed it to
6572 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6575 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
6576 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
6577 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
6578 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
6580 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
6583 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
6587 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
6588 && subreg_lowpart_p (XEXP (src
, 0))
6589 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
6590 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
6591 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
6592 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
6593 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
6595 assign
= make_extraction (VOIDmode
, dest
, 0,
6596 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
6599 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
6603 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
6605 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
6606 && XEXP (XEXP (src
, 0), 0) == const1_rtx
6607 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
6609 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
6612 return gen_rtx (SET
, VOIDmode
, assign
, const1_rtx
);
6616 /* The other case we handle is assignments into a constant-position
6617 field. They look like (ior (and DEST C1) OTHER). If C1 represents
6618 a mask that has all one bits except for a group of zero bits and
6619 OTHER is known to have zeros where C1 has ones, this is such an
6620 assignment. Compute the position and length from C1. Shift OTHER
6621 to the appropriate position, force it to the required mode, and
6622 make the extraction. Check for the AND in both operands. */
6624 if (GET_CODE (src
) != IOR
)
6627 rhs
= expand_compound_operation (XEXP (src
, 0));
6628 lhs
= expand_compound_operation (XEXP (src
, 1));
6630 if (GET_CODE (rhs
) == AND
6631 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
6632 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
6633 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
6634 else if (GET_CODE (lhs
) == AND
6635 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6636 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
6637 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
6641 pos
= get_pos_from_mask ((~ c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
6642 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
6643 || (GET_MODE_BITSIZE (GET_MODE (other
)) <= HOST_BITS_PER_WIDE_INT
6644 && (c1
& nonzero_bits (other
, GET_MODE (other
))) != 0))
6647 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
6651 /* The mode to use for the source is the mode of the assignment, or of
6652 what is inside a possible STRICT_LOW_PART. */
6653 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
6654 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
6656 /* Shift OTHER right POS places and make it the source, restricting it
6657 to the proper length and mode. */
6659 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6660 GET_MODE (src
), other
, pos
),
6662 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
6663 ? GET_MODE_MASK (mode
)
6664 : ((HOST_WIDE_INT
) 1 << len
) - 1,
6667 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
6670 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6674 apply_distributive_law (x
)
6677 enum rtx_code code
= GET_CODE (x
);
6678 rtx lhs
, rhs
, other
;
6680 enum rtx_code inner_code
;
6682 /* Distributivity is not true for floating point.
6683 It can change the value. So don't do it.
6684 -- rms and moshier@world.std.com. */
6685 if (FLOAT_MODE_P (GET_MODE (x
)))
6688 /* The outer operation can only be one of the following: */
6689 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
6690 && code
!= PLUS
&& code
!= MINUS
)
6693 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
6695 /* If either operand is a primitive we can't do anything, so get out fast. */
6696 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
6697 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
6700 lhs
= expand_compound_operation (lhs
);
6701 rhs
= expand_compound_operation (rhs
);
6702 inner_code
= GET_CODE (lhs
);
6703 if (inner_code
!= GET_CODE (rhs
))
6706 /* See if the inner and outer operations distribute. */
6713 /* These all distribute except over PLUS. */
6714 if (code
== PLUS
|| code
== MINUS
)
6719 if (code
!= PLUS
&& code
!= MINUS
)
6724 /* This is also a multiply, so it distributes over everything. */
6728 /* Non-paradoxical SUBREGs distributes over all operations, provided
6729 the inner modes and word numbers are the same, this is an extraction
6730 of a low-order part, we don't convert an fp operation to int or
6731 vice versa, and we would not be converting a single-word
6732 operation into a multi-word operation. The latter test is not
6733 required, but it prevents generating unneeded multi-word operations.
6734 Some of the previous tests are redundant given the latter test, but
6735 are retained because they are required for correctness.
6737 We produce the result slightly differently in this case. */
6739 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
6740 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
6741 || ! subreg_lowpart_p (lhs
)
6742 || (GET_MODE_CLASS (GET_MODE (lhs
))
6743 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
6744 || (GET_MODE_SIZE (GET_MODE (lhs
))
6745 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
6746 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
6749 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
6750 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
6751 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
6757 /* Set LHS and RHS to the inner operands (A and B in the example
6758 above) and set OTHER to the common operand (C in the example).
6759 These is only one way to do this unless the inner operation is
6761 if (GET_RTX_CLASS (inner_code
) == 'c'
6762 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
6763 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
6764 else if (GET_RTX_CLASS (inner_code
) == 'c'
6765 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
6766 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
6767 else if (GET_RTX_CLASS (inner_code
) == 'c'
6768 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
6769 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
6770 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
6771 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
6775 /* Form the new inner operation, seeing if it simplifies first. */
6776 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
6778 /* There is one exception to the general way of distributing:
6779 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6780 if (code
== XOR
&& inner_code
== IOR
)
6783 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
6786 /* We may be able to continuing distributing the result, so call
6787 ourselves recursively on the inner operation before forming the
6788 outer operation, which we return. */
6789 return gen_binary (inner_code
, GET_MODE (x
),
6790 apply_distributive_law (tem
), other
);
6793 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6796 Return an equivalent form, if different from X. Otherwise, return X. If
6797 X is zero, we are to always construct the equivalent form. */
6800 simplify_and_const_int (x
, mode
, varop
, constop
)
6802 enum machine_mode mode
;
6804 unsigned HOST_WIDE_INT constop
;
6806 unsigned HOST_WIDE_INT nonzero
;
6807 int width
= GET_MODE_BITSIZE (mode
);
6810 /* Simplify VAROP knowing that we will be only looking at some of the
6812 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
6814 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6815 CONST_INT, we are done. */
6816 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
6819 /* See what bits may be nonzero in VAROP. Unlike the general case of
6820 a call to nonzero_bits, here we don't care about bits outside
6823 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
6825 /* If this would be an entire word for the target, but is not for
6826 the host, then sign-extend on the host so that the number will look
6827 the same way on the host that it would on the target.
6829 For example, when building a 64 bit alpha hosted 32 bit sparc
6830 targeted compiler, then we want the 32 bit unsigned value -1 to be
6831 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
6832 The later confuses the sparc backend. */
6834 if (BITS_PER_WORD
< HOST_BITS_PER_WIDE_INT
&& BITS_PER_WORD
== width
6835 && (nonzero
& ((HOST_WIDE_INT
) 1 << (width
- 1))))
6836 nonzero
|= ((HOST_WIDE_INT
) (-1) << width
);
6838 /* Turn off all bits in the constant that are known to already be zero.
6839 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6840 which is tested below. */
6844 /* If we don't have any bits left, return zero. */
6848 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
6849 a power of two, we can replace this with a ASHIFT. */
6850 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
6851 && (i
= exact_log2 (constop
)) >= 0)
6852 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
6854 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
6855 or XOR, then try to apply the distributive law. This may eliminate
6856 operations if either branch can be simplified because of the AND.
6857 It may also make some cases more complex, but those cases probably
6858 won't match a pattern either with or without this. */
6860 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
6862 gen_lowpart_for_combine
6864 apply_distributive_law
6865 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
6866 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
6867 XEXP (varop
, 0), constop
),
6868 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
6869 XEXP (varop
, 1), constop
))));
6871 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6872 if we already had one (just check for the simplest cases). */
6873 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
6874 && GET_MODE (XEXP (x
, 0)) == mode
6875 && SUBREG_REG (XEXP (x
, 0)) == varop
)
6876 varop
= XEXP (x
, 0);
6878 varop
= gen_lowpart_for_combine (mode
, varop
);
6880 /* If we can't make the SUBREG, try to return what we were given. */
6881 if (GET_CODE (varop
) == CLOBBER
)
6882 return x
? x
: varop
;
6884 /* If we are only masking insignificant bits, return VAROP. */
6885 if (constop
== nonzero
)
6888 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6889 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
6890 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
6894 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
6895 || INTVAL (XEXP (x
, 1)) != constop
)
6896 SUBST (XEXP (x
, 1), GEN_INT (constop
));
6898 SUBST (XEXP (x
, 0), varop
);
6904 /* Given an expression, X, compute which bits in X can be non-zero.
6905 We don't care about bits outside of those defined in MODE.
6907 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6908 a shift, AND, or zero_extract, we can do better. */
6910 static unsigned HOST_WIDE_INT
6911 nonzero_bits (x
, mode
)
6913 enum machine_mode mode
;
6915 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
6916 unsigned HOST_WIDE_INT inner_nz
;
6918 int mode_width
= GET_MODE_BITSIZE (mode
);
6921 /* For floating-point values, assume all bits are needed. */
6922 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
6925 /* If X is wider than MODE, use its mode instead. */
6926 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
6928 mode
= GET_MODE (x
);
6929 nonzero
= GET_MODE_MASK (mode
);
6930 mode_width
= GET_MODE_BITSIZE (mode
);
6933 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
6934 /* Our only callers in this case look for single bit values. So
6935 just return the mode mask. Those tests will then be false. */
6938 #ifndef WORD_REGISTER_OPERATIONS
6939 /* If MODE is wider than X, but both are a single word for both the host
6940 and target machines, we can compute this from which bits of the
6941 object might be nonzero in its own mode, taking into account the fact
6942 that on many CISC machines, accessing an object in a wider mode
6943 causes the high-order bits to become undefined. So they are
6944 not known to be zero. */
6946 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
6947 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
6948 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6949 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
6951 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
6952 nonzero
|= GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
));
6957 code
= GET_CODE (x
);
6961 #ifdef POINTERS_EXTEND_UNSIGNED
6962 /* If pointers extend unsigned and this is a pointer in Pmode, say that
6963 all the bits above ptr_mode are known to be zero. */
6964 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
6965 && REGNO_POINTER_FLAG (REGNO (x
)))
6966 nonzero
&= GET_MODE_MASK (ptr_mode
);
6969 #ifdef STACK_BOUNDARY
6970 /* If this is the stack pointer, we may know something about its
6971 alignment. If PUSH_ROUNDING is defined, it is possible for the
6972 stack to be momentarily aligned only to that amount, so we pick
6973 the least alignment. */
6975 if (x
== stack_pointer_rtx
|| x
== frame_pointer_rtx
6976 || x
== arg_pointer_rtx
|| x
== hard_frame_pointer_rtx
6977 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
6978 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
6980 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6982 #ifdef PUSH_ROUNDING
6983 if (REGNO (x
) == STACK_POINTER_REGNUM
)
6984 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
6987 /* We must return here, otherwise we may get a worse result from
6988 one of the choices below. There is nothing useful below as
6989 far as the stack pointer is concerned. */
6990 return nonzero
&= ~ (sp_alignment
- 1);
6994 /* If X is a register whose nonzero bits value is current, use it.
6995 Otherwise, if X is a register whose value we can find, use that
6996 value. Otherwise, use the previously-computed global nonzero bits
6997 for this register. */
6999 if (reg_last_set_value
[REGNO (x
)] != 0
7000 && reg_last_set_mode
[REGNO (x
)] == mode
7001 && (reg_n_sets
[REGNO (x
)] == 1
7002 || reg_last_set_label
[REGNO (x
)] == label_tick
)
7003 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7004 return reg_last_set_nonzero_bits
[REGNO (x
)];
7006 tem
= get_last_value (x
);
7010 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7011 /* If X is narrower than MODE and TEM is a non-negative
7012 constant that would appear negative in the mode of X,
7013 sign-extend it for use in reg_nonzero_bits because some
7014 machines (maybe most) will actually do the sign-extension
7015 and this is the conservative approach.
7017 ??? For 2.5, try to tighten up the MD files in this regard
7018 instead of this kludge. */
7020 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7021 && GET_CODE (tem
) == CONST_INT
7023 && 0 != (INTVAL (tem
)
7024 & ((HOST_WIDE_INT
) 1
7025 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7026 tem
= GEN_INT (INTVAL (tem
)
7027 | ((HOST_WIDE_INT
) (-1)
7028 << GET_MODE_BITSIZE (GET_MODE (x
))));
7030 return nonzero_bits (tem
, mode
);
7032 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7033 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7038 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7039 /* If X is negative in MODE, sign-extend the value. */
7040 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7041 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7042 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7048 #ifdef LOAD_EXTEND_OP
7049 /* In many, if not most, RISC machines, reading a byte from memory
7050 zeros the rest of the register. Noticing that fact saves a lot
7051 of extra zero-extends. */
7052 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
7053 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
7063 /* If this produces an integer result, we know which bits are set.
7064 Code here used to clear bits outside the mode of X, but that is
7067 if (GET_MODE_CLASS (mode
) == MODE_INT
7068 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7069 nonzero
= STORE_FLAG_VALUE
;
7073 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7074 == GET_MODE_BITSIZE (GET_MODE (x
)))
7077 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
7078 nonzero
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
7082 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7083 == GET_MODE_BITSIZE (GET_MODE (x
)))
7088 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
7092 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
7093 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7094 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7098 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7099 Otherwise, show all the bits in the outer mode but not the inner
7101 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
7102 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7104 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7107 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
7108 inner_nz
|= (GET_MODE_MASK (mode
)
7109 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
7112 nonzero
&= inner_nz
;
7116 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7117 & nonzero_bits (XEXP (x
, 1), mode
));
7121 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
7122 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7123 | nonzero_bits (XEXP (x
, 1), mode
));
7126 case PLUS
: case MINUS
:
7128 case DIV
: case UDIV
:
7129 case MOD
: case UMOD
:
7130 /* We can apply the rules of arithmetic to compute the number of
7131 high- and low-order zero bits of these operations. We start by
7132 computing the width (position of the highest-order non-zero bit)
7133 and the number of low-order zero bits for each value. */
7135 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
7136 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
7137 int width0
= floor_log2 (nz0
) + 1;
7138 int width1
= floor_log2 (nz1
) + 1;
7139 int low0
= floor_log2 (nz0
& -nz0
);
7140 int low1
= floor_log2 (nz1
& -nz1
);
7141 HOST_WIDE_INT op0_maybe_minusp
7142 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7143 HOST_WIDE_INT op1_maybe_minusp
7144 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7145 int result_width
= mode_width
;
7151 result_width
= MAX (width0
, width1
) + 1;
7152 result_low
= MIN (low0
, low1
);
7155 result_low
= MIN (low0
, low1
);
7158 result_width
= width0
+ width1
;
7159 result_low
= low0
+ low1
;
7162 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7163 result_width
= width0
;
7166 result_width
= width0
;
7169 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7170 result_width
= MIN (width0
, width1
);
7171 result_low
= MIN (low0
, low1
);
7174 result_width
= MIN (width0
, width1
);
7175 result_low
= MIN (low0
, low1
);
7179 if (result_width
< mode_width
)
7180 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
7183 nonzero
&= ~ (((HOST_WIDE_INT
) 1 << result_low
) - 1);
7188 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7189 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7190 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
7194 /* If this is a SUBREG formed for a promoted variable that has
7195 been zero-extended, we know that at least the high-order bits
7196 are zero, though others might be too. */
7198 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
7199 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
7200 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
7202 /* If the inner mode is a single word for both the host and target
7203 machines, we can compute this from which bits of the inner
7204 object might be nonzero. */
7205 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
7206 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
7207 <= HOST_BITS_PER_WIDE_INT
))
7209 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
7211 #ifndef WORD_REGISTER_OPERATIONS
7212 /* On many CISC machines, accessing an object in a wider mode
7213 causes the high-order bits to become undefined. So they are
7214 not known to be zero. */
7215 if (GET_MODE_SIZE (GET_MODE (x
))
7216 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7217 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
7218 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
7227 /* The nonzero bits are in two classes: any bits within MODE
7228 that aren't in GET_MODE (x) are always significant. The rest of the
7229 nonzero bits are those that are significant in the operand of
7230 the shift when shifted the appropriate number of bits. This
7231 shows that high-order bits are cleared by the right shift and
7232 low-order bits by left shifts. */
7233 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7234 && INTVAL (XEXP (x
, 1)) >= 0
7235 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7237 enum machine_mode inner_mode
= GET_MODE (x
);
7238 int width
= GET_MODE_BITSIZE (inner_mode
);
7239 int count
= INTVAL (XEXP (x
, 1));
7240 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
7241 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7242 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
7243 unsigned HOST_WIDE_INT outer
= 0;
7245 if (mode_width
> width
)
7246 outer
= (op_nonzero
& nonzero
& ~ mode_mask
);
7248 if (code
== LSHIFTRT
)
7250 else if (code
== ASHIFTRT
)
7254 /* If the sign bit may have been nonzero before the shift, we
7255 need to mark all the places it could have been copied to
7256 by the shift as possibly nonzero. */
7257 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
7258 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
7260 else if (code
== ASHIFT
)
7263 inner
= ((inner
<< (count
% width
)
7264 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
7266 nonzero
&= (outer
| inner
);
7271 /* This is at most the number of bits in the mode. */
7272 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
7276 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
7277 | nonzero_bits (XEXP (x
, 2), mode
));
7284 /* Return the number of bits at the high-order end of X that are known to
7285 be equal to the sign bit. X will be used in mode MODE; if MODE is
7286 VOIDmode, X will be used in its own mode. The returned value will always
7287 be between 1 and the number of bits in MODE. */
7290 num_sign_bit_copies (x
, mode
)
7292 enum machine_mode mode
;
7294 enum rtx_code code
= GET_CODE (x
);
7296 int num0
, num1
, result
;
7297 unsigned HOST_WIDE_INT nonzero
;
7300 /* If we weren't given a mode, use the mode of X. If the mode is still
7301 VOIDmode, we don't know anything. Likewise if one of the modes is
7304 if (mode
== VOIDmode
)
7305 mode
= GET_MODE (x
);
7307 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
7310 bitwidth
= GET_MODE_BITSIZE (mode
);
7312 /* For a smaller object, just ignore the high bits. */
7313 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
7314 return MAX (1, (num_sign_bit_copies (x
, GET_MODE (x
))
7315 - (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
)));
7317 #ifndef WORD_REGISTER_OPERATIONS
7318 /* If this machine does not do all register operations on the entire
7319 register and MODE is wider than the mode of X, we can say nothing
7320 at all about the high-order bits. */
7321 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
7329 #ifdef POINTERS_EXTEND_UNSIGNED
7330 /* If pointers extend signed and this is a pointer in Pmode, say that
7331 all the bits above ptr_mode are known to be sign bit copies. */
7332 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
7333 && REGNO_POINTER_FLAG (REGNO (x
)))
7334 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
7337 if (reg_last_set_value
[REGNO (x
)] != 0
7338 && reg_last_set_mode
[REGNO (x
)] == mode
7339 && (reg_n_sets
[REGNO (x
)] == 1
7340 || reg_last_set_label
[REGNO (x
)] == label_tick
)
7341 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7342 return reg_last_set_sign_bit_copies
[REGNO (x
)];
7344 tem
= get_last_value (x
);
7346 return num_sign_bit_copies (tem
, mode
);
7348 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
7349 return reg_sign_bit_copies
[REGNO (x
)];
7353 #ifdef LOAD_EXTEND_OP
7354 /* Some RISC machines sign-extend all loads of smaller than a word. */
7355 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
7356 return MAX (1, bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1);
7361 /* If the constant is negative, take its 1's complement and remask.
7362 Then see how many zero bits we have. */
7363 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
7364 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
7365 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7366 nonzero
= (~ nonzero
) & GET_MODE_MASK (mode
);
7368 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
7371 /* If this is a SUBREG for a promoted object that is sign-extended
7372 and we are looking at it in a wider mode, we know that at least the
7373 high-order bits are known to be sign bit copies. */
7375 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
7376 return MAX (bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
7377 num_sign_bit_copies (SUBREG_REG (x
), mode
));
7379 /* For a smaller object, just ignore the high bits. */
7380 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
7382 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
7383 return MAX (1, (num0
7384 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
7388 #ifdef WORD_REGISTER_OPERATIONS
7389 #ifdef LOAD_EXTEND_OP
7390 /* For paradoxical SUBREGs on machines where all register operations
7391 affect the entire register, just look inside. Note that we are
7392 passing MODE to the recursive call, so the number of sign bit copies
7393 will remain relative to that mode, not the inner mode. */
7395 /* This works only if loads sign extend. Otherwise, if we get a
7396 reload for the inner part, it may be loaded from the stack, and
7397 then we lose all sign bit copies that existed before the store
7400 if ((GET_MODE_SIZE (GET_MODE (x
))
7401 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7402 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
7403 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
7409 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7410 return MAX (1, bitwidth
- INTVAL (XEXP (x
, 1)));
7414 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
7415 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
7418 /* For a smaller object, just ignore the high bits. */
7419 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
7420 return MAX (1, (num0
- (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
7424 return num_sign_bit_copies (XEXP (x
, 0), mode
);
7426 case ROTATE
: case ROTATERT
:
7427 /* If we are rotating left by a number of bits less than the number
7428 of sign bit copies, we can just subtract that amount from the
7430 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7431 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
7433 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7434 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
7435 : bitwidth
- INTVAL (XEXP (x
, 1))));
7440 /* In general, this subtracts one sign bit copy. But if the value
7441 is known to be positive, the number of sign bit copies is the
7442 same as that of the input. Finally, if the input has just one bit
7443 that might be nonzero, all the bits are copies of the sign bit. */
7444 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7448 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7450 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7451 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
7456 case IOR
: case AND
: case XOR
:
7457 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
7458 /* Logical operations will preserve the number of sign-bit copies.
7459 MIN and MAX operations always return one of the operands. */
7460 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7461 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7462 return MIN (num0
, num1
);
7464 case PLUS
: case MINUS
:
7465 /* For addition and subtraction, we can have a 1-bit carry. However,
7466 if we are subtracting 1 from a positive number, there will not
7467 be such a carry. Furthermore, if the positive number is known to
7468 be 0 or 1, we know the result is either -1 or 0. */
7470 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
7471 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
7473 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7474 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
7475 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
7476 : bitwidth
- floor_log2 (nonzero
) - 1);
7479 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7480 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7481 return MAX (1, MIN (num0
, num1
) - 1);
7484 /* The number of bits of the product is the sum of the number of
7485 bits of both terms. However, unless one of the terms if known
7486 to be positive, we must allow for an additional bit since negating
7487 a negative number can remove one sign bit copy. */
7489 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7490 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7492 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
7494 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7495 && ((nonzero_bits (XEXP (x
, 0), mode
)
7496 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7497 && ((nonzero_bits (XEXP (x
, 1), mode
)
7498 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
7501 return MAX (1, result
);
7504 /* The result must be <= the first operand. */
7505 return num_sign_bit_copies (XEXP (x
, 0), mode
);
7508 /* The result must be <= the scond operand. */
7509 return num_sign_bit_copies (XEXP (x
, 1), mode
);
7512 /* Similar to unsigned division, except that we have to worry about
7513 the case where the divisor is negative, in which case we have
7515 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7517 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7518 && (nonzero_bits (XEXP (x
, 1), mode
)
7519 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7525 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7527 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7528 && (nonzero_bits (XEXP (x
, 1), mode
)
7529 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7535 /* Shifts by a constant add to the number of bits equal to the
7537 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7538 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7539 && INTVAL (XEXP (x
, 1)) > 0)
7540 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
7545 /* Left shifts destroy copies. */
7546 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7547 || INTVAL (XEXP (x
, 1)) < 0
7548 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
7551 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7552 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
7555 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7556 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
7557 return MIN (num0
, num1
);
7559 #if STORE_FLAG_VALUE == -1
7560 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
7561 case GEU
: case GTU
: case LEU
: case LTU
:
7566 /* If we haven't been able to figure it out by one of the above rules,
7567 see if some of the high-order bits are known to be zero. If so,
7568 count those bits and return one less than that amount. If we can't
7569 safely compute the mask for this mode, always return BITWIDTH. */
7571 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
7574 nonzero
= nonzero_bits (x
, mode
);
7575 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
7576 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
7579 /* Return the number of "extended" bits there are in X, when interpreted
7580 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7581 unsigned quantities, this is the number of high-order zero bits.
7582 For signed quantities, this is the number of copies of the sign bit
7583 minus 1. In both case, this function returns the number of "spare"
7584 bits. For example, if two quantities for which this function returns
7585 at least 1 are added, the addition is known not to overflow.
7587 This function will always return 0 unless called during combine, which
7588 implies that it must be called from a define_split. */
7591 extended_count (x
, mode
, unsignedp
)
7593 enum machine_mode mode
;
7596 if (nonzero_sign_valid
== 0)
7600 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7601 && (GET_MODE_BITSIZE (mode
) - 1
7602 - floor_log2 (nonzero_bits (x
, mode
))))
7603 : num_sign_bit_copies (x
, mode
) - 1);
7606 /* This function is called from `simplify_shift_const' to merge two
7607 outer operations. Specifically, we have already found that we need
7608 to perform operation *POP0 with constant *PCONST0 at the outermost
7609 position. We would now like to also perform OP1 with constant CONST1
7610 (with *POP0 being done last).
7612 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7613 the resulting operation. *PCOMP_P is set to 1 if we would need to
7614 complement the innermost operand, otherwise it is unchanged.
7616 MODE is the mode in which the operation will be done. No bits outside
7617 the width of this mode matter. It is assumed that the width of this mode
7618 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7620 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7621 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7622 result is simply *PCONST0.
7624 If the resulting operation cannot be expressed as one operation, we
7625 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7628 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
7629 enum rtx_code
*pop0
;
7630 HOST_WIDE_INT
*pconst0
;
7632 HOST_WIDE_INT const1
;
7633 enum machine_mode mode
;
7636 enum rtx_code op0
= *pop0
;
7637 HOST_WIDE_INT const0
= *pconst0
;
7638 int width
= GET_MODE_BITSIZE (mode
);
7640 const0
&= GET_MODE_MASK (mode
);
7641 const1
&= GET_MODE_MASK (mode
);
7643 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7647 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7650 if (op1
== NIL
|| op0
== SET
)
7653 else if (op0
== NIL
)
7654 op0
= op1
, const0
= const1
;
7656 else if (op0
== op1
)
7678 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7679 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
7682 /* If the two constants aren't the same, we can't do anything. The
7683 remaining six cases can all be done. */
7684 else if (const0
!= const1
)
7692 /* (a & b) | b == b */
7694 else /* op1 == XOR */
7695 /* (a ^ b) | b == a | b */
7701 /* (a & b) ^ b == (~a) & b */
7702 op0
= AND
, *pcomp_p
= 1;
7703 else /* op1 == IOR */
7704 /* (a | b) ^ b == a & ~b */
7705 op0
= AND
, *pconst0
= ~ const0
;
7710 /* (a | b) & b == b */
7712 else /* op1 == XOR */
7713 /* (a ^ b) & b) == (~a) & b */
7718 /* Check for NO-OP cases. */
7719 const0
&= GET_MODE_MASK (mode
);
7721 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
7723 else if (const0
== 0 && op0
== AND
)
7725 else if (const0
== GET_MODE_MASK (mode
) && op0
== AND
)
7728 /* If this would be an entire word for the target, but is not for
7729 the host, then sign-extend on the host so that the number will look
7730 the same way on the host that it would on the target.
7732 For example, when building a 64 bit alpha hosted 32 bit sparc
7733 targeted compiler, then we want the 32 bit unsigned value -1 to be
7734 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7735 The later confuses the sparc backend. */
7737 if (BITS_PER_WORD
< HOST_BITS_PER_WIDE_INT
&& BITS_PER_WORD
== width
7738 && (const0
& ((HOST_WIDE_INT
) 1 << (width
- 1))))
7739 const0
|= ((HOST_WIDE_INT
) (-1) << width
);
7747 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7748 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7749 that we started with.
7751 The shift is normally computed in the widest mode we find in VAROP, as
7752 long as it isn't a different number of words than RESULT_MODE. Exceptions
7753 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7756 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
7759 enum machine_mode result_mode
;
7763 enum rtx_code orig_code
= code
;
7764 int orig_count
= count
;
7765 enum machine_mode mode
= result_mode
;
7766 enum machine_mode shift_mode
, tmode
;
7768 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
7769 /* We form (outer_op (code varop count) (outer_const)). */
7770 enum rtx_code outer_op
= NIL
;
7771 HOST_WIDE_INT outer_const
= 0;
7773 int complement_p
= 0;
7776 /* If we were given an invalid count, don't do anything except exactly
7777 what was requested. */
7779 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
7784 return gen_rtx (code
, mode
, varop
, GEN_INT (count
));
7787 /* Unless one of the branches of the `if' in this loop does a `continue',
7788 we will `break' the loop after the `if'. */
7792 /* If we have an operand of (clobber (const_int 0)), just return that
7794 if (GET_CODE (varop
) == CLOBBER
)
7797 /* If we discovered we had to complement VAROP, leave. Making a NOT
7798 here would cause an infinite loop. */
7802 /* Convert ROTATERT to ROTATE. */
7803 if (code
== ROTATERT
)
7804 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
7806 /* We need to determine what mode we will do the shift in. If the
7807 shift is a right shift or a ROTATE, we must always do it in the mode
7808 it was originally done in. Otherwise, we can do it in MODE, the
7809 widest mode encountered. */
7811 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
7812 ? result_mode
: mode
);
7814 /* Handle cases where the count is greater than the size of the mode
7815 minus 1. For ASHIFT, use the size minus one as the count (this can
7816 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7817 take the count modulo the size. For other shifts, the result is
7820 Since these shifts are being produced by the compiler by combining
7821 multiple operations, each of which are defined, we know what the
7822 result is supposed to be. */
7824 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
7826 if (code
== ASHIFTRT
)
7827 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
7828 else if (code
== ROTATE
|| code
== ROTATERT
)
7829 count
%= GET_MODE_BITSIZE (shift_mode
);
7832 /* We can't simply return zero because there may be an
7840 /* Negative counts are invalid and should not have been made (a
7841 programmer-specified negative count should have been handled
7846 /* An arithmetic right shift of a quantity known to be -1 or 0
7848 if (code
== ASHIFTRT
7849 && (num_sign_bit_copies (varop
, shift_mode
)
7850 == GET_MODE_BITSIZE (shift_mode
)))
7856 /* If we are doing an arithmetic right shift and discarding all but
7857 the sign bit copies, this is equivalent to doing a shift by the
7858 bitsize minus one. Convert it into that shift because it will often
7859 allow other simplifications. */
7861 if (code
== ASHIFTRT
7862 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
7863 >= GET_MODE_BITSIZE (shift_mode
)))
7864 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
7866 /* We simplify the tests below and elsewhere by converting
7867 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7868 `make_compound_operation' will convert it to a ASHIFTRT for
7869 those machines (such as Vax) that don't have a LSHIFTRT. */
7870 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
7872 && ((nonzero_bits (varop
, shift_mode
)
7873 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
7877 switch (GET_CODE (varop
))
7883 new = expand_compound_operation (varop
);
7892 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7893 minus the width of a smaller mode, we can do this with a
7894 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7895 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
7896 && ! mode_dependent_address_p (XEXP (varop
, 0))
7897 && ! MEM_VOLATILE_P (varop
)
7898 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
7899 MODE_INT
, 1)) != BLKmode
)
7901 if (BYTES_BIG_ENDIAN
)
7902 new = gen_rtx (MEM
, tmode
, XEXP (varop
, 0));
7904 new = gen_rtx (MEM
, tmode
,
7905 plus_constant (XEXP (varop
, 0),
7906 count
/ BITS_PER_UNIT
));
7907 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
7908 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop
);
7909 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop
);
7910 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
7911 : ZERO_EXTEND
, mode
, new);
7918 /* Similar to the case above, except that we can only do this if
7919 the resulting mode is the same as that of the underlying
7920 MEM and adjust the address depending on the *bits* endianness
7921 because of the way that bit-field extract insns are defined. */
7922 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
7923 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
7924 MODE_INT
, 1)) != BLKmode
7925 && tmode
== GET_MODE (XEXP (varop
, 0)))
7927 if (BITS_BIG_ENDIAN
)
7928 new = XEXP (varop
, 0);
7931 new = copy_rtx (XEXP (varop
, 0));
7932 SUBST (XEXP (new, 0),
7933 plus_constant (XEXP (new, 0),
7934 count
/ BITS_PER_UNIT
));
7937 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
7938 : ZERO_EXTEND
, mode
, new);
7945 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7946 the same number of words as what we've seen so far. Then store
7947 the widest mode in MODE. */
7948 if (subreg_lowpart_p (varop
)
7949 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
7950 > GET_MODE_SIZE (GET_MODE (varop
)))
7951 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
7952 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7955 varop
= SUBREG_REG (varop
);
7956 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
7957 mode
= GET_MODE (varop
);
7963 /* Some machines use MULT instead of ASHIFT because MULT
7964 is cheaper. But it is still better on those machines to
7965 merge two shifts into one. */
7966 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
7967 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
7969 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
7970 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));;
7976 /* Similar, for when divides are cheaper. */
7977 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
7978 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
7980 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
7981 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
7987 /* If we are extracting just the sign bit of an arithmetic right
7988 shift, that shift is not needed. */
7989 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
7991 varop
= XEXP (varop
, 0);
7995 /* ... fall through ... */
8000 /* Here we have two nested shifts. The result is usually the
8001 AND of a new shift with a mask. We compute the result below. */
8002 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8003 && INTVAL (XEXP (varop
, 1)) >= 0
8004 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8005 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8006 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8008 enum rtx_code first_code
= GET_CODE (varop
);
8009 int first_count
= INTVAL (XEXP (varop
, 1));
8010 unsigned HOST_WIDE_INT mask
;
8013 /* We have one common special case. We can't do any merging if
8014 the inner code is an ASHIFTRT of a smaller mode. However, if
8015 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8016 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8017 we can convert it to
8018 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8019 This simplifies certain SIGN_EXTEND operations. */
8020 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8021 && (GET_MODE_BITSIZE (result_mode
)
8022 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
8024 /* C3 has the low-order C1 bits zero. */
8026 mask
= (GET_MODE_MASK (mode
)
8027 & ~ (((HOST_WIDE_INT
) 1 << first_count
) - 1));
8029 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8030 XEXP (varop
, 0), mask
);
8031 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8033 count
= first_count
;
8038 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8039 than C1 high-order bits equal to the sign bit, we can convert
8040 this to either an ASHIFT or a ASHIFTRT depending on the
8043 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8045 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8046 && GET_MODE (varop
) == shift_mode
8047 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8050 count
-= first_count
;
8052 count
= - count
, code
= ASHIFT
;
8053 varop
= XEXP (varop
, 0);
8057 /* There are some cases we can't do. If CODE is ASHIFTRT,
8058 we can only do this if FIRST_CODE is also ASHIFTRT.
8060 We can't do the case when CODE is ROTATE and FIRST_CODE is
8063 If the mode of this shift is not the mode of the outer shift,
8064 we can't do this if either shift is a right shift or ROTATE.
8066 Finally, we can't do any of these if the mode is too wide
8067 unless the codes are the same.
8069 Handle the case where the shift codes are the same
8072 if (code
== first_code
)
8074 if (GET_MODE (varop
) != result_mode
8075 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8079 count
+= first_count
;
8080 varop
= XEXP (varop
, 0);
8084 if (code
== ASHIFTRT
8085 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8086 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8087 || (GET_MODE (varop
) != result_mode
8088 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8089 || first_code
== ROTATE
8090 || code
== ROTATE
)))
8093 /* To compute the mask to apply after the shift, shift the
8094 nonzero bits of the inner shift the same way the
8095 outer shift will. */
8097 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8100 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8103 /* Give up if we can't compute an outer operation to use. */
8105 || GET_CODE (mask_rtx
) != CONST_INT
8106 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8108 result_mode
, &complement_p
))
8111 /* If the shifts are in the same direction, we add the
8112 counts. Otherwise, we subtract them. */
8113 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8114 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8115 count
+= first_count
;
8117 count
-= first_count
;
8119 /* If COUNT is positive, the new shift is usually CODE,
8120 except for the two exceptions below, in which case it is
8121 FIRST_CODE. If the count is negative, FIRST_CODE should
8124 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8125 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8128 code
= first_code
, count
= - count
;
8130 varop
= XEXP (varop
, 0);
8134 /* If we have (A << B << C) for any shift, we can convert this to
8135 (A << C << B). This wins if A is a constant. Only try this if
8136 B is not a constant. */
8138 else if (GET_CODE (varop
) == code
8139 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8141 = simplify_binary_operation (code
, mode
,
8145 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
8152 /* Make this fit the case below. */
8153 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
8154 GEN_INT (GET_MODE_MASK (mode
)));
8160 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8161 with C the size of VAROP - 1 and the shift is logical if
8162 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8163 we have an (le X 0) operation. If we have an arithmetic shift
8164 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8165 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8167 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8168 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8169 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8170 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8171 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
8172 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8175 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
8178 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8179 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
8184 /* If we have (shift (logical)), move the logical to the outside
8185 to allow it to possibly combine with another logical and the
8186 shift to combine with another shift. This also canonicalizes to
8187 what a ZERO_EXTRACT looks like. Also, some machines have
8188 (and (shift)) insns. */
8190 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8191 && (new = simplify_binary_operation (code
, result_mode
,
8193 GEN_INT (count
))) != 0
8194 && GET_CODE(new) == CONST_INT
8195 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8196 INTVAL (new), result_mode
, &complement_p
))
8198 varop
= XEXP (varop
, 0);
8202 /* If we can't do that, try to simplify the shift in each arm of the
8203 logical expression, make a new logical expression, and apply
8204 the inverse distributive law. */
8206 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8207 XEXP (varop
, 0), count
);
8208 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8209 XEXP (varop
, 1), count
);
8211 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
8212 varop
= apply_distributive_law (varop
);
8219 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8220 says that the sign bit can be tested, FOO has mode MODE, C is
8221 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8222 that may be nonzero. */
8223 if (code
== LSHIFTRT
8224 && XEXP (varop
, 1) == const0_rtx
8225 && GET_MODE (XEXP (varop
, 0)) == result_mode
8226 && count
== GET_MODE_BITSIZE (result_mode
) - 1
8227 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8228 && ((STORE_FLAG_VALUE
8229 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
8230 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8231 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8232 (HOST_WIDE_INT
) 1, result_mode
,
8235 varop
= XEXP (varop
, 0);
8242 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8243 than the number of bits in the mode is equivalent to A. */
8244 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
8245 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
8247 varop
= XEXP (varop
, 0);
8252 /* NEG commutes with ASHIFT since it is multiplication. Move the
8253 NEG outside to allow shifts to combine. */
8255 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
8256 (HOST_WIDE_INT
) 0, result_mode
,
8259 varop
= XEXP (varop
, 0);
8265 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8266 is one less than the number of bits in the mode is
8267 equivalent to (xor A 1). */
8268 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
8269 && XEXP (varop
, 1) == constm1_rtx
8270 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8271 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8272 (HOST_WIDE_INT
) 1, result_mode
,
8276 varop
= XEXP (varop
, 0);
8280 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8281 that might be nonzero in BAR are those being shifted out and those
8282 bits are known zero in FOO, we can replace the PLUS with FOO.
8283 Similarly in the other operand order. This code occurs when
8284 we are computing the size of a variable-size array. */
8286 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8287 && count
< HOST_BITS_PER_WIDE_INT
8288 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
8289 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
8290 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
8292 varop
= XEXP (varop
, 0);
8295 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8296 && count
< HOST_BITS_PER_WIDE_INT
8297 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8298 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8300 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8301 & nonzero_bits (XEXP (varop
, 1),
8304 varop
= XEXP (varop
, 1);
8308 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8310 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
8311 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
8313 GEN_INT (count
))) != 0
8314 && GET_CODE(new) == CONST_INT
8315 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
8316 INTVAL (new), result_mode
, &complement_p
))
8318 varop
= XEXP (varop
, 0);
8324 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8325 with C the size of VAROP - 1 and the shift is logical if
8326 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8327 we have a (gt X 0) operation. If the shift is arithmetic with
8328 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8329 we have a (neg (gt X 0)) operation. */
8331 if (GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
8332 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
8333 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8334 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8335 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
8336 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
8337 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8340 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
8343 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8344 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
8354 /* We need to determine what mode to do the shift in. If the shift is
8355 a right shift or ROTATE, we must always do it in the mode it was
8356 originally done in. Otherwise, we can do it in MODE, the widest mode
8357 encountered. The code we care about is that of the shift that will
8358 actually be done, not the shift that was originally requested. */
8360 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8361 ? result_mode
: mode
);
8363 /* We have now finished analyzing the shift. The result should be
8364 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8365 OUTER_OP is non-NIL, it is an operation that needs to be applied
8366 to the result of the shift. OUTER_CONST is the relevant constant,
8367 but we must turn off all bits turned off in the shift.
8369 If we were passed a value for X, see if we can use any pieces of
8370 it. If not, make new rtx. */
8372 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
8373 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8374 && INTVAL (XEXP (x
, 1)) == count
)
8375 const_rtx
= XEXP (x
, 1);
8377 const_rtx
= GEN_INT (count
);
8379 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8380 && GET_MODE (XEXP (x
, 0)) == shift_mode
8381 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8382 varop
= XEXP (x
, 0);
8383 else if (GET_MODE (varop
) != shift_mode
)
8384 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
8386 /* If we can't make the SUBREG, try to return what we were given. */
8387 if (GET_CODE (varop
) == CLOBBER
)
8388 return x
? x
: varop
;
8390 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
8395 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
8396 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
8398 SUBST (XEXP (x
, 0), varop
);
8399 SUBST (XEXP (x
, 1), const_rtx
);
8402 /* If we have an outer operation and we just made a shift, it is
8403 possible that we could have simplified the shift were it not
8404 for the outer operation. So try to do the simplification
8407 if (outer_op
!= NIL
&& GET_CODE (x
) == code
8408 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8409 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
8410 INTVAL (XEXP (x
, 1)));
8412 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8413 turn off all the bits that the shift would have turned off. */
8414 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
8415 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
8416 GET_MODE_MASK (result_mode
) >> orig_count
);
8418 /* Do the remainder of the processing in RESULT_MODE. */
8419 x
= gen_lowpart_for_combine (result_mode
, x
);
8421 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8424 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
8426 if (outer_op
!= NIL
)
8428 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
8430 int width
= GET_MODE_BITSIZE (result_mode
);
8432 outer_const
&= GET_MODE_MASK (result_mode
);
8434 /* If this would be an entire word for the target, but is not for
8435 the host, then sign-extend on the host so that the number will
8436 look the same way on the host that it would on the target.
8438 For example, when building a 64 bit alpha hosted 32 bit sparc
8439 targeted compiler, then we want the 32 bit unsigned value -1 to be
8440 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8441 The later confuses the sparc backend. */
8443 if (BITS_PER_WORD
< HOST_BITS_PER_WIDE_INT
&& BITS_PER_WORD
== width
8444 && (outer_const
& ((HOST_WIDE_INT
) 1 << (width
- 1))))
8445 outer_const
|= ((HOST_WIDE_INT
) (-1) << width
);
8448 if (outer_op
== AND
)
8449 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
8450 else if (outer_op
== SET
)
8451 /* This means that we have determined that the result is
8452 equivalent to a constant. This should be rare. */
8453 x
= GEN_INT (outer_const
);
8454 else if (GET_RTX_CLASS (outer_op
) == '1')
8455 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
8457 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
8463 /* Like recog, but we receive the address of a pointer to a new pattern.
8464 We try to match the rtx that the pointer points to.
8465 If that fails, we may try to modify or replace the pattern,
8466 storing the replacement into the same pointer object.
8468 Modifications include deletion or addition of CLOBBERs.
8470 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8471 the CLOBBERs are placed.
8473 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8476 The value is the final insn code from the pattern ultimately matched,
8480 recog_for_combine (pnewpat
, insn
, pnotes
, padded_scratches
)
8484 int *padded_scratches
;
8486 register rtx pat
= *pnewpat
;
8487 int insn_code_number
;
8488 int num_clobbers_to_add
= 0;
8492 *padded_scratches
= 0;
8494 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8495 we use to indicate that something didn't match. If we find such a
8496 thing, force rejection. */
8497 if (GET_CODE (pat
) == PARALLEL
)
8498 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
8499 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
8500 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
8503 /* Is the result of combination a valid instruction? */
8504 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
8506 /* If it isn't, there is the possibility that we previously had an insn
8507 that clobbered some register as a side effect, but the combined
8508 insn doesn't need to do that. So try once more without the clobbers
8509 unless this represents an ASM insn. */
8511 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
8512 && GET_CODE (pat
) == PARALLEL
)
8516 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
8517 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
8520 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
8524 SUBST_INT (XVECLEN (pat
, 0), pos
);
8527 pat
= XVECEXP (pat
, 0, 0);
8529 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
8532 /* If we had any clobbers to add, make a new pattern than contains
8533 them. Then check to make sure that all of them are dead. */
8534 if (num_clobbers_to_add
)
8536 rtx newpat
= gen_rtx (PARALLEL
, VOIDmode
,
8537 gen_rtvec (GET_CODE (pat
) == PARALLEL
8538 ? XVECLEN (pat
, 0) + num_clobbers_to_add
8539 : num_clobbers_to_add
+ 1));
8541 if (GET_CODE (pat
) == PARALLEL
)
8542 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
8543 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
8545 XVECEXP (newpat
, 0, 0) = pat
;
8547 add_clobbers (newpat
, insn_code_number
);
8549 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
8550 i
< XVECLEN (newpat
, 0); i
++)
8552 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
8553 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
8555 else if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == SCRATCH
)
8556 (*padded_scratches
)++;
8557 notes
= gen_rtx (EXPR_LIST
, REG_UNUSED
,
8558 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
8566 return insn_code_number
;
8569 /* Like gen_lowpart but for use by combine. In combine it is not possible
8570 to create any new pseudoregs. However, it is safe to create
8571 invalid memory addresses, because combine will try to recognize
8572 them and all they will do is make the combine attempt fail.
8574 If for some reason this cannot do its job, an rtx
8575 (clobber (const_int 0)) is returned.
8576 An insn containing that will not be recognized. */
8581 gen_lowpart_for_combine (mode
, x
)
8582 enum machine_mode mode
;
8587 if (GET_MODE (x
) == mode
)
8590 /* We can only support MODE being wider than a word if X is a
8591 constant integer or has a mode the same size. */
8593 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
8594 && ! ((GET_MODE (x
) == VOIDmode
8595 && (GET_CODE (x
) == CONST_INT
8596 || GET_CODE (x
) == CONST_DOUBLE
))
8597 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
8598 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
8600 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8601 won't know what to do. So we will strip off the SUBREG here and
8602 process normally. */
8603 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
8606 if (GET_MODE (x
) == mode
)
8610 result
= gen_lowpart_common (mode
, x
);
8612 && GET_CODE (result
) == SUBREG
8613 && GET_CODE (SUBREG_REG (result
)) == REG
8614 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
8615 && (GET_MODE_SIZE (GET_MODE (result
))
8616 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result
)))))
8617 reg_changes_size
[REGNO (SUBREG_REG (result
))] = 1;
8622 if (GET_CODE (x
) == MEM
)
8624 register int offset
= 0;
8627 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8629 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
8630 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
8632 /* If we want to refer to something bigger than the original memref,
8633 generate a perverse subreg instead. That will force a reload
8634 of the original memref X. */
8635 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
8636 return gen_rtx (SUBREG
, mode
, x
, 0);
8638 if (WORDS_BIG_ENDIAN
)
8639 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
8640 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
8641 if (BYTES_BIG_ENDIAN
)
8643 /* Adjust the address so that the address-after-the-data is
8645 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
8646 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
8648 new = gen_rtx (MEM
, mode
, plus_constant (XEXP (x
, 0), offset
));
8649 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
8650 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x
);
8651 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x
);
8655 /* If X is a comparison operator, rewrite it in a new mode. This
8656 probably won't match, but may allow further simplifications. */
8657 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
8658 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
8660 /* If we couldn't simplify X any other way, just enclose it in a
8661 SUBREG. Normally, this SUBREG won't match, but some patterns may
8662 include an explicit SUBREG or we may simplify it further in combine. */
8667 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
8668 word
= ((GET_MODE_SIZE (GET_MODE (x
))
8669 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
8671 return gen_rtx (SUBREG
, mode
, x
, word
);
8675 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8676 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8678 If the identical expression was previously in the insn (in the undobuf),
8679 it will be returned. Only if it is not found will a new expression
8684 gen_rtx_combine
VPROTO((enum rtx_code code
, enum machine_mode mode
, ...))
8688 enum machine_mode mode
;
8700 code
= va_arg (p
, enum rtx_code
);
8701 mode
= va_arg (p
, enum machine_mode
);
8704 n_args
= GET_RTX_LENGTH (code
);
8705 fmt
= GET_RTX_FORMAT (code
);
8707 if (n_args
== 0 || n_args
> 3)
8710 /* Get each arg and verify that it is supposed to be an expression. */
8711 for (j
= 0; j
< n_args
; j
++)
8716 args
[j
] = va_arg (p
, rtx
);
8719 /* See if this is in undobuf. Be sure we don't use objects that came
8720 from another insn; this could produce circular rtl structures. */
8722 for (i
= previous_num_undos
; i
< undobuf
.num_undo
; i
++)
8723 if (!undobuf
.undo
[i
].is_int
8724 && GET_CODE (undobuf
.undo
[i
].old_contents
.r
) == code
8725 && GET_MODE (undobuf
.undo
[i
].old_contents
.r
) == mode
)
8727 for (j
= 0; j
< n_args
; j
++)
8728 if (XEXP (undobuf
.undo
[i
].old_contents
.r
, j
) != args
[j
])
8732 return undobuf
.undo
[i
].old_contents
.r
;
8735 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8736 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8737 rt
= rtx_alloc (code
);
8738 PUT_MODE (rt
, mode
);
8739 XEXP (rt
, 0) = args
[0];
8742 XEXP (rt
, 1) = args
[1];
8744 XEXP (rt
, 2) = args
[2];
8749 /* These routines make binary and unary operations by first seeing if they
8750 fold; if not, a new expression is allocated. */
8753 gen_binary (code
, mode
, op0
, op1
)
8755 enum machine_mode mode
;
8761 if (GET_RTX_CLASS (code
) == 'c'
8762 && (GET_CODE (op0
) == CONST_INT
8763 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
8764 tem
= op0
, op0
= op1
, op1
= tem
;
8766 if (GET_RTX_CLASS (code
) == '<')
8768 enum machine_mode op_mode
= GET_MODE (op0
);
8770 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8771 just (REL_OP X Y). */
8772 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
8774 op1
= XEXP (op0
, 1);
8775 op0
= XEXP (op0
, 0);
8776 op_mode
= GET_MODE (op0
);
8779 if (op_mode
== VOIDmode
)
8780 op_mode
= GET_MODE (op1
);
8781 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
8784 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
8789 /* Put complex operands first and constants second. */
8790 if (GET_RTX_CLASS (code
) == 'c'
8791 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
8792 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
8793 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
8794 || (GET_CODE (op0
) == SUBREG
8795 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
8796 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
8797 return gen_rtx_combine (code
, mode
, op1
, op0
);
8799 return gen_rtx_combine (code
, mode
, op0
, op1
);
8803 gen_unary (code
, mode
, op0_mode
, op0
)
8805 enum machine_mode mode
, op0_mode
;
8808 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
8813 return gen_rtx_combine (code
, mode
, op0
);
8816 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8817 comparison code that will be tested.
8819 The result is a possibly different comparison code to use. *POP0 and
8820 *POP1 may be updated.
8822 It is possible that we might detect that a comparison is either always
8823 true or always false. However, we do not perform general constant
8824 folding in combine, so this knowledge isn't useful. Such tautologies
8825 should have been detected earlier. Hence we ignore all such cases. */
8827 static enum rtx_code
8828 simplify_comparison (code
, pop0
, pop1
)
8837 enum machine_mode mode
, tmode
;
8839 /* Try a few ways of applying the same transformation to both operands. */
8842 #ifndef WORD_REGISTER_OPERATIONS
8843 /* The test below this one won't handle SIGN_EXTENDs on these machines,
8844 so check specially. */
8845 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
8846 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
8847 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
8848 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
8849 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
8850 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
8851 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
8852 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
8853 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
8854 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
8855 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
8856 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
8857 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
8858 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
8859 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
8860 && (INTVAL (XEXP (op0
, 1))
8861 == (GET_MODE_BITSIZE (GET_MODE (op0
))
8863 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
8865 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
8866 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
8870 /* If both operands are the same constant shift, see if we can ignore the
8871 shift. We can if the shift is a rotate or if the bits shifted out of
8872 this shift are known to be zero for both inputs and if the type of
8873 comparison is compatible with the shift. */
8874 if (GET_CODE (op0
) == GET_CODE (op1
)
8875 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
8876 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
8877 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
8878 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
8879 || (GET_CODE (op0
) == ASHIFTRT
8880 && (code
!= GTU
&& code
!= LTU
8881 && code
!= GEU
&& code
!= GEU
)))
8882 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
8883 && INTVAL (XEXP (op0
, 1)) >= 0
8884 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
8885 && XEXP (op0
, 1) == XEXP (op1
, 1))
8887 enum machine_mode mode
= GET_MODE (op0
);
8888 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8889 int shift_count
= INTVAL (XEXP (op0
, 1));
8891 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
8892 mask
&= (mask
>> shift_count
) << shift_count
;
8893 else if (GET_CODE (op0
) == ASHIFT
)
8894 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
8896 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
8897 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
8898 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
8903 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8904 SUBREGs are of the same mode, and, in both cases, the AND would
8905 be redundant if the comparison was done in the narrower mode,
8906 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8907 and the operand's possibly nonzero bits are 0xffffff01; in that case
8908 if we only care about QImode, we don't need the AND). This case
8909 occurs if the output mode of an scc insn is not SImode and
8910 STORE_FLAG_VALUE == 1 (e.g., the 386).
8912 Similarly, check for a case where the AND's are ZERO_EXTEND
8913 operations from some narrower mode even though a SUBREG is not
8916 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
8917 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
8918 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
8920 rtx inner_op0
= XEXP (op0
, 0);
8921 rtx inner_op1
= XEXP (op1
, 0);
8922 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
8923 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
8926 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
8927 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
8928 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
8929 && (GET_MODE (SUBREG_REG (inner_op0
))
8930 == GET_MODE (SUBREG_REG (inner_op1
)))
8931 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
8932 <= HOST_BITS_PER_WIDE_INT
)
8933 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
8934 GET_MODE (SUBREG_REG (op0
)))))
8935 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
8936 GET_MODE (SUBREG_REG (inner_op1
))))))
8938 op0
= SUBREG_REG (inner_op0
);
8939 op1
= SUBREG_REG (inner_op1
);
8941 /* The resulting comparison is always unsigned since we masked
8942 off the original sign bit. */
8943 code
= unsigned_condition (code
);
8949 for (tmode
= GET_CLASS_NARROWEST_MODE
8950 (GET_MODE_CLASS (GET_MODE (op0
)));
8951 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
8952 if (c0
== GET_MODE_MASK (tmode
))
8954 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
8955 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
8956 code
= unsigned_condition (code
);
8965 /* If both operands are NOT, we can strip off the outer operation
8966 and adjust the comparison code for swapped operands; similarly for
8967 NEG, except that this must be an equality comparison. */
8968 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
8969 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
8970 && (code
== EQ
|| code
== NE
)))
8971 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
8977 /* If the first operand is a constant, swap the operands and adjust the
8978 comparison code appropriately. */
8979 if (CONSTANT_P (op0
))
8981 tem
= op0
, op0
= op1
, op1
= tem
;
8982 code
= swap_condition (code
);
8985 /* We now enter a loop during which we will try to simplify the comparison.
8986 For the most part, we only are concerned with comparisons with zero,
8987 but some things may really be comparisons with zero but not start
8988 out looking that way. */
8990 while (GET_CODE (op1
) == CONST_INT
)
8992 enum machine_mode mode
= GET_MODE (op0
);
8993 int mode_width
= GET_MODE_BITSIZE (mode
);
8994 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8995 int equality_comparison_p
;
8996 int sign_bit_comparison_p
;
8997 int unsigned_comparison_p
;
8998 HOST_WIDE_INT const_op
;
9000 /* We only want to handle integral modes. This catches VOIDmode,
9001 CCmode, and the floating-point modes. An exception is that we
9002 can handle VOIDmode if OP0 is a COMPARE or a comparison
9005 if (GET_MODE_CLASS (mode
) != MODE_INT
9006 && ! (mode
== VOIDmode
9007 && (GET_CODE (op0
) == COMPARE
9008 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
9011 /* Get the constant we are comparing against and turn off all bits
9012 not on in our mode. */
9013 const_op
= INTVAL (op1
);
9014 if (mode_width
<= HOST_BITS_PER_WIDE_INT
)
9017 /* If we are comparing against a constant power of two and the value
9018 being compared can only have that single bit nonzero (e.g., it was
9019 `and'ed with that bit), we can replace this with a comparison
9022 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9023 || code
== LT
|| code
== LTU
)
9024 && mode_width
<= HOST_BITS_PER_WIDE_INT
9025 && exact_log2 (const_op
) >= 0
9026 && nonzero_bits (op0
, mode
) == const_op
)
9028 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9029 op1
= const0_rtx
, const_op
= 0;
9032 /* Similarly, if we are comparing a value known to be either -1 or
9033 0 with -1, change it to the opposite comparison against zero. */
9036 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9037 || code
== GEU
|| code
== LTU
)
9038 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9040 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9041 op1
= const0_rtx
, const_op
= 0;
9044 /* Do some canonicalizations based on the comparison code. We prefer
9045 comparisons against zero and then prefer equality comparisons.
9046 If we can reduce the size of a constant, we will do that too. */
9051 /* < C is equivalent to <= (C - 1) */
9055 op1
= GEN_INT (const_op
);
9057 /* ... fall through to LE case below. */
9063 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9067 op1
= GEN_INT (const_op
);
9071 /* If we are doing a <= 0 comparison on a value known to have
9072 a zero sign bit, we can replace this with == 0. */
9073 else if (const_op
== 0
9074 && mode_width
<= HOST_BITS_PER_WIDE_INT
9075 && (nonzero_bits (op0
, mode
)
9076 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9081 /* >= C is equivalent to > (C - 1). */
9085 op1
= GEN_INT (const_op
);
9087 /* ... fall through to GT below. */
9093 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9097 op1
= GEN_INT (const_op
);
9101 /* If we are doing a > 0 comparison on a value known to have
9102 a zero sign bit, we can replace this with != 0. */
9103 else if (const_op
== 0
9104 && mode_width
<= HOST_BITS_PER_WIDE_INT
9105 && (nonzero_bits (op0
, mode
)
9106 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9111 /* < C is equivalent to <= (C - 1). */
9115 op1
= GEN_INT (const_op
);
9117 /* ... fall through ... */
9120 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9121 else if (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1))
9123 const_op
= 0, op1
= const0_rtx
;
9131 /* unsigned <= 0 is equivalent to == 0 */
9135 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9136 else if (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
9138 const_op
= 0, op1
= const0_rtx
;
9144 /* >= C is equivalent to < (C - 1). */
9148 op1
= GEN_INT (const_op
);
9150 /* ... fall through ... */
9153 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9154 else if (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1))
9156 const_op
= 0, op1
= const0_rtx
;
9164 /* unsigned > 0 is equivalent to != 0 */
9168 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9169 else if (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
9171 const_op
= 0, op1
= const0_rtx
;
9177 /* Compute some predicates to simplify code below. */
9179 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9180 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9181 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9184 /* If this is a sign bit comparison and we can do arithmetic in
9185 MODE, say that we will only be needing the sign bit of OP0. */
9186 if (sign_bit_comparison_p
9187 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9188 op0
= force_to_mode (op0
, mode
,
9190 << (GET_MODE_BITSIZE (mode
) - 1)),
9193 /* Now try cases based on the opcode of OP0. If none of the cases
9194 does a "continue", we exit this loop immediately after the
9197 switch (GET_CODE (op0
))
9200 /* If we are extracting a single bit from a variable position in
9201 a constant that has only a single bit set and are comparing it
9202 with zero, we can convert this into an equality comparison
9203 between the position and the location of the single bit. */
9205 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
9206 && XEXP (op0
, 1) == const1_rtx
9207 && equality_comparison_p
&& const_op
== 0
9208 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9210 if (BITS_BIG_ENDIAN
)
9212 i
= (GET_MODE_BITSIZE
9213 (insn_operand_mode
[(int) CODE_FOR_extzv
][1]) - 1 - i
);
9215 i
= BITS_PER_WORD
- 1 - i
;
9218 op0
= XEXP (op0
, 2);
9222 /* Result is nonzero iff shift count is equal to I. */
9223 code
= reverse_condition (code
);
9227 /* ... fall through ... */
9230 tem
= expand_compound_operation (op0
);
9239 /* If testing for equality, we can take the NOT of the constant. */
9240 if (equality_comparison_p
9241 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9243 op0
= XEXP (op0
, 0);
9248 /* If just looking at the sign bit, reverse the sense of the
9250 if (sign_bit_comparison_p
)
9252 op0
= XEXP (op0
, 0);
9253 code
= (code
== GE
? LT
: GE
);
9259 /* If testing for equality, we can take the NEG of the constant. */
9260 if (equality_comparison_p
9261 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9263 op0
= XEXP (op0
, 0);
9268 /* The remaining cases only apply to comparisons with zero. */
9272 /* When X is ABS or is known positive,
9273 (neg X) is < 0 if and only if X != 0. */
9275 if (sign_bit_comparison_p
9276 && (GET_CODE (XEXP (op0
, 0)) == ABS
9277 || (mode_width
<= HOST_BITS_PER_WIDE_INT
9278 && (nonzero_bits (XEXP (op0
, 0), mode
)
9279 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
9281 op0
= XEXP (op0
, 0);
9282 code
= (code
== LT
? NE
: EQ
);
9286 /* If we have NEG of something whose two high-order bits are the
9287 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9288 if (num_sign_bit_copies (op0
, mode
) >= 2)
9290 op0
= XEXP (op0
, 0);
9291 code
= swap_condition (code
);
9297 /* If we are testing equality and our count is a constant, we
9298 can perform the inverse operation on our RHS. */
9299 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9300 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
9301 op1
, XEXP (op0
, 1))) != 0)
9303 op0
= XEXP (op0
, 0);
9308 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9309 a particular bit. Convert it to an AND of a constant of that
9310 bit. This will be converted into a ZERO_EXTRACT. */
9311 if (const_op
== 0 && sign_bit_comparison_p
9312 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9313 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
9315 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9318 - INTVAL (XEXP (op0
, 1)))));
9319 code
= (code
== LT
? NE
: EQ
);
9323 /* ... fall through ... */
9326 /* ABS is ignorable inside an equality comparison with zero. */
9327 if (const_op
== 0 && equality_comparison_p
)
9329 op0
= XEXP (op0
, 0);
9336 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9337 to (compare FOO CONST) if CONST fits in FOO's mode and we
9338 are either testing inequality or have an unsigned comparison
9339 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9340 if (! unsigned_comparison_p
9341 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
9342 <= HOST_BITS_PER_WIDE_INT
)
9343 && ((unsigned HOST_WIDE_INT
) const_op
9344 < (((HOST_WIDE_INT
) 1
9345 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
9347 op0
= XEXP (op0
, 0);
9353 /* Check for the case where we are comparing A - C1 with C2,
9354 both constants are smaller than 1/2 the maximum positive
9355 value in MODE, and the comparison is equality or unsigned.
9356 In that case, if A is either zero-extended to MODE or has
9357 sufficient sign bits so that the high-order bit in MODE
9358 is a copy of the sign in the inner mode, we can prove that it is
9359 safe to do the operation in the wider mode. This simplifies
9360 many range checks. */
9362 if (mode_width
<= HOST_BITS_PER_WIDE_INT
9363 && subreg_lowpart_p (op0
)
9364 && GET_CODE (SUBREG_REG (op0
)) == PLUS
9365 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
9366 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
9367 && (- INTVAL (XEXP (SUBREG_REG (op0
), 1))
9368 < GET_MODE_MASK (mode
) / 2)
9369 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
9370 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
9371 GET_MODE (SUBREG_REG (op0
)))
9372 & ~ GET_MODE_MASK (mode
))
9373 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
9374 GET_MODE (SUBREG_REG (op0
)))
9375 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
9376 - GET_MODE_BITSIZE (mode
)))))
9378 op0
= SUBREG_REG (op0
);
9382 /* If the inner mode is narrower and we are extracting the low part,
9383 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9384 if (subreg_lowpart_p (op0
)
9385 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
9386 /* Fall through */ ;
9390 /* ... fall through ... */
9393 if ((unsigned_comparison_p
|| equality_comparison_p
)
9394 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
9395 <= HOST_BITS_PER_WIDE_INT
)
9396 && ((unsigned HOST_WIDE_INT
) const_op
9397 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
9399 op0
= XEXP (op0
, 0);
9405 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9406 this for equality comparisons due to pathological cases involving
9408 if (equality_comparison_p
9409 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
9410 op1
, XEXP (op0
, 1))))
9412 op0
= XEXP (op0
, 0);
9417 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9418 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
9419 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
9421 op0
= XEXP (XEXP (op0
, 0), 0);
9422 code
= (code
== LT
? EQ
: NE
);
9428 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9429 (eq B (minus A C)), whichever simplifies. We can only do
9430 this for equality comparisons due to pathological cases involving
9432 if (equality_comparison_p
9433 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
9434 XEXP (op0
, 1), op1
)))
9436 op0
= XEXP (op0
, 0);
9441 if (equality_comparison_p
9442 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
9443 XEXP (op0
, 0), op1
)))
9445 op0
= XEXP (op0
, 1);
9450 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9451 of bits in X minus 1, is one iff X > 0. */
9452 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
9453 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9454 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
9455 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
9457 op0
= XEXP (op0
, 1);
9458 code
= (code
== GE
? LE
: GT
);
9464 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9465 if C is zero or B is a constant. */
9466 if (equality_comparison_p
9467 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
9468 XEXP (op0
, 1), op1
)))
9470 op0
= XEXP (op0
, 0);
9477 case LT
: case LTU
: case LE
: case LEU
:
9478 case GT
: case GTU
: case GE
: case GEU
:
9479 /* We can't do anything if OP0 is a condition code value, rather
9480 than an actual data value. */
9483 || XEXP (op0
, 0) == cc0_rtx
9485 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
9488 /* Get the two operands being compared. */
9489 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
9490 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
9492 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
9494 /* Check for the cases where we simply want the result of the
9495 earlier test or the opposite of that result. */
9497 || (code
== EQ
&& reversible_comparison_p (op0
))
9498 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9499 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
9500 && (STORE_FLAG_VALUE
9501 & (((HOST_WIDE_INT
) 1
9502 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
9504 || (code
== GE
&& reversible_comparison_p (op0
)))))
9506 code
= (code
== LT
|| code
== NE
9507 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
9508 op0
= tem
, op1
= tem1
;
9514 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9516 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
9517 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
9518 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
9520 op0
= XEXP (op0
, 1);
9521 code
= (code
== GE
? GT
: LE
);
9527 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9528 will be converted to a ZERO_EXTRACT later. */
9529 if (const_op
== 0 && equality_comparison_p
9530 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9531 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
9533 op0
= simplify_and_const_int
9534 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
9536 XEXP (XEXP (op0
, 0), 1)),
9541 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9542 zero and X is a comparison and C1 and C2 describe only bits set
9543 in STORE_FLAG_VALUE, we can compare with X. */
9544 if (const_op
== 0 && equality_comparison_p
9545 && mode_width
<= HOST_BITS_PER_WIDE_INT
9546 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9547 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
9548 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9549 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
9550 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9552 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
9553 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
9554 if ((~ STORE_FLAG_VALUE
& mask
) == 0
9555 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
9556 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
9557 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
9559 op0
= XEXP (XEXP (op0
, 0), 0);
9564 /* If we are doing an equality comparison of an AND of a bit equal
9565 to the sign bit, replace this with a LT or GE comparison of
9566 the underlying value. */
9567 if (equality_comparison_p
9569 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9570 && mode_width
<= HOST_BITS_PER_WIDE_INT
9571 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
9572 == (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9574 op0
= XEXP (op0
, 0);
9575 code
= (code
== EQ
? GE
: LT
);
9579 /* If this AND operation is really a ZERO_EXTEND from a narrower
9580 mode, the constant fits within that mode, and this is either an
9581 equality or unsigned comparison, try to do this comparison in
9582 the narrower mode. */
9583 if ((equality_comparison_p
|| unsigned_comparison_p
)
9584 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9585 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
9586 & GET_MODE_MASK (mode
))
9588 && const_op
>> i
== 0
9589 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
9591 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
9597 /* If we have (compare (ashift FOO N) (const_int C)) and
9598 the high order N bits of FOO (N+1 if an inequality comparison)
9599 are known to be zero, we can do this by comparing FOO with C
9600 shifted right N bits so long as the low-order N bits of C are
9602 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
9603 && INTVAL (XEXP (op0
, 1)) >= 0
9604 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
9605 < HOST_BITS_PER_WIDE_INT
)
9607 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
9608 && mode_width
<= HOST_BITS_PER_WIDE_INT
9609 && (nonzero_bits (XEXP (op0
, 0), mode
)
9610 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
9611 + ! equality_comparison_p
))) == 0)
9613 const_op
>>= INTVAL (XEXP (op0
, 1));
9614 op1
= GEN_INT (const_op
);
9615 op0
= XEXP (op0
, 0);
9619 /* If we are doing a sign bit comparison, it means we are testing
9620 a particular bit. Convert it to the appropriate AND. */
9621 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9622 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
9624 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9627 - INTVAL (XEXP (op0
, 1)))));
9628 code
= (code
== LT
? NE
: EQ
);
9632 /* If this an equality comparison with zero and we are shifting
9633 the low bit to the sign bit, we can convert this to an AND of the
9635 if (const_op
== 0 && equality_comparison_p
9636 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9637 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
9639 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9646 /* If this is an equality comparison with zero, we can do this
9647 as a logical shift, which might be much simpler. */
9648 if (equality_comparison_p
&& const_op
== 0
9649 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
9651 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
9653 INTVAL (XEXP (op0
, 1)));
9657 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9658 do the comparison in a narrower mode. */
9659 if (! unsigned_comparison_p
9660 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9661 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9662 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9663 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
9664 MODE_INT
, 1)) != BLKmode
9665 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
9666 || ((unsigned HOST_WIDE_INT
) - const_op
9667 <= GET_MODE_MASK (tmode
))))
9669 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
9673 /* ... fall through ... */
9675 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9676 the low order N bits of FOO are known to be zero, we can do this
9677 by comparing FOO with C shifted left N bits so long as no
9679 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
9680 && INTVAL (XEXP (op0
, 1)) >= 0
9681 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9682 && mode_width
<= HOST_BITS_PER_WIDE_INT
9683 && (nonzero_bits (XEXP (op0
, 0), mode
)
9684 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
9686 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
9689 const_op
<<= INTVAL (XEXP (op0
, 1));
9690 op1
= GEN_INT (const_op
);
9691 op0
= XEXP (op0
, 0);
9695 /* If we are using this shift to extract just the sign bit, we
9696 can replace this with an LT or GE comparison. */
9698 && (equality_comparison_p
|| sign_bit_comparison_p
)
9699 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9700 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
9702 op0
= XEXP (op0
, 0);
9703 code
= (code
== NE
|| code
== GT
? LT
: GE
);
9712 /* Now make any compound operations involved in this comparison. Then,
9713 check for an outmost SUBREG on OP0 that isn't doing anything or is
9714 paradoxical. The latter case can only occur when it is known that the
9715 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9716 We can never remove a SUBREG for a non-equality comparison because the
9717 sign bit is in a different place in the underlying object. */
9719 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
9720 op1
= make_compound_operation (op1
, SET
);
9722 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
9723 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
9724 && (code
== NE
|| code
== EQ
)
9725 && ((GET_MODE_SIZE (GET_MODE (op0
))
9726 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
9728 op0
= SUBREG_REG (op0
);
9729 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
9732 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
9733 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
9734 && (code
== NE
|| code
== EQ
)
9735 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
9736 <= HOST_BITS_PER_WIDE_INT
)
9737 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
9738 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
9739 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
9741 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
9742 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
9743 op0
= SUBREG_REG (op0
), op1
= tem
;
9745 /* We now do the opposite procedure: Some machines don't have compare
9746 insns in all modes. If OP0's mode is an integer mode smaller than a
9747 word and we can't do a compare in that mode, see if there is a larger
9748 mode for which we can do the compare. There are a number of cases in
9749 which we can use the wider mode. */
9751 mode
= GET_MODE (op0
);
9752 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
9753 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
9754 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
9755 for (tmode
= GET_MODE_WIDER_MODE (mode
);
9757 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
9758 tmode
= GET_MODE_WIDER_MODE (tmode
))
9759 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
9761 /* If the only nonzero bits in OP0 and OP1 are those in the
9762 narrower mode and this is an equality or unsigned comparison,
9763 we can use the wider mode. Similarly for sign-extended
9764 values, in which case it is true for all comparisons. */
9765 if (((code
== EQ
|| code
== NE
9766 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
9767 && (nonzero_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
9768 && (nonzero_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0)
9769 || ((num_sign_bit_copies (op0
, tmode
)
9770 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
9771 && (num_sign_bit_copies (op1
, tmode
)
9772 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
9774 op0
= gen_lowpart_for_combine (tmode
, op0
);
9775 op1
= gen_lowpart_for_combine (tmode
, op1
);
9779 /* If this is a test for negative, we can make an explicit
9780 test of the sign bit. */
9782 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
9783 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9785 op0
= gen_binary (AND
, tmode
,
9786 gen_lowpart_for_combine (tmode
, op0
),
9787 GEN_INT ((HOST_WIDE_INT
) 1
9788 << (GET_MODE_BITSIZE (mode
) - 1)));
9789 code
= (code
== LT
) ? NE
: EQ
;
9794 #ifdef CANONICALIZE_COMPARISON
9795 /* If this machine only supports a subset of valid comparisons, see if we
9796 can convert an unsupported one into a supported one. */
9797 CANONICALIZE_COMPARISON (code
, op0
, op1
);
9806 /* Return 1 if we know that X, a comparison operation, is not operating
9807 on a floating-point value or is EQ or NE, meaning that we can safely
9811 reversible_comparison_p (x
)
9814 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
9816 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
)
9819 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
9822 case MODE_PARTIAL_INT
:
9823 case MODE_COMPLEX_INT
:
9827 /* If the mode of the condition codes tells us that this is safe,
9828 we need look no further. */
9829 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x
, 0))))
9832 /* Otherwise try and find where the condition codes were last set and
9834 x
= get_last_value (XEXP (x
, 0));
9835 return (x
&& GET_CODE (x
) == COMPARE
9836 && ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0))));
9842 /* Utility function for following routine. Called when X is part of a value
9843 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9844 for each register mentioned. Similar to mention_regs in cse.c */
9847 update_table_tick (x
)
9850 register enum rtx_code code
= GET_CODE (x
);
9851 register char *fmt
= GET_RTX_FORMAT (code
);
9856 int regno
= REGNO (x
);
9857 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
9858 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
9860 for (i
= regno
; i
< endregno
; i
++)
9861 reg_last_set_table_tick
[i
] = label_tick
;
9866 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9867 /* Note that we can't have an "E" in values stored; see
9868 get_last_value_validate. */
9870 update_table_tick (XEXP (x
, i
));
9873 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
9874 are saying that the register is clobbered and we no longer know its
9875 value. If INSN is zero, don't update reg_last_set; this is only permitted
9876 with VALUE also zero and is used to invalidate the register. */
9879 record_value_for_reg (reg
, insn
, value
)
9884 int regno
= REGNO (reg
);
9885 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
9886 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
9889 /* If VALUE contains REG and we have a previous value for REG, substitute
9890 the previous value. */
9891 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
9895 /* Set things up so get_last_value is allowed to see anything set up to
9897 subst_low_cuid
= INSN_CUID (insn
);
9898 tem
= get_last_value (reg
);
9901 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
9904 /* For each register modified, show we don't know its value, that
9905 we don't know about its bitwise content, that its value has been
9906 updated, and that we don't know the location of the death of the
9908 for (i
= regno
; i
< endregno
; i
++)
9911 reg_last_set
[i
] = insn
;
9912 reg_last_set_value
[i
] = 0;
9913 reg_last_set_mode
[i
] = 0;
9914 reg_last_set_nonzero_bits
[i
] = 0;
9915 reg_last_set_sign_bit_copies
[i
] = 0;
9916 reg_last_death
[i
] = 0;
9919 /* Mark registers that are being referenced in this value. */
9921 update_table_tick (value
);
9923 /* Now update the status of each register being set.
9924 If someone is using this register in this block, set this register
9925 to invalid since we will get confused between the two lives in this
9926 basic block. This makes using this register always invalid. In cse, we
9927 scan the table to invalidate all entries using this register, but this
9928 is too much work for us. */
9930 for (i
= regno
; i
< endregno
; i
++)
9932 reg_last_set_label
[i
] = label_tick
;
9933 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
9934 reg_last_set_invalid
[i
] = 1;
9936 reg_last_set_invalid
[i
] = 0;
9939 /* The value being assigned might refer to X (like in "x++;"). In that
9940 case, we must replace it with (clobber (const_int 0)) to prevent
9942 if (value
&& ! get_last_value_validate (&value
,
9943 reg_last_set_label
[regno
], 0))
9945 value
= copy_rtx (value
);
9946 if (! get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
9950 /* For the main register being modified, update the value, the mode, the
9951 nonzero bits, and the number of sign bit copies. */
9953 reg_last_set_value
[regno
] = value
;
9957 subst_low_cuid
= INSN_CUID (insn
);
9958 reg_last_set_mode
[regno
] = GET_MODE (reg
);
9959 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
9960 reg_last_set_sign_bit_copies
[regno
]
9961 = num_sign_bit_copies (value
, GET_MODE (reg
));
9965 /* Used for communication between the following two routines. */
9966 static rtx record_dead_insn
;
9968 /* Called via note_stores from record_dead_and_set_regs to handle one
9969 SET or CLOBBER in an insn. */
9972 record_dead_and_set_regs_1 (dest
, setter
)
9975 if (GET_CODE (dest
) == SUBREG
)
9976 dest
= SUBREG_REG (dest
);
9978 if (GET_CODE (dest
) == REG
)
9980 /* If we are setting the whole register, we know its value. Otherwise
9981 show that we don't know the value. We can handle SUBREG in
9983 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
9984 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
9985 else if (GET_CODE (setter
) == SET
9986 && GET_CODE (SET_DEST (setter
)) == SUBREG
9987 && SUBREG_REG (SET_DEST (setter
)) == dest
9988 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
9989 && subreg_lowpart_p (SET_DEST (setter
)))
9990 record_value_for_reg (dest
, record_dead_insn
,
9991 gen_lowpart_for_combine (GET_MODE (dest
),
9994 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
9996 else if (GET_CODE (dest
) == MEM
9997 /* Ignore pushes, they clobber nothing. */
9998 && ! push_operand (dest
, GET_MODE (dest
)))
9999 mem_last_set
= INSN_CUID (record_dead_insn
);
10002 /* Update the records of when each REG was most recently set or killed
10003 for the things done by INSN. This is the last thing done in processing
10004 INSN in the combiner loop.
10006 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10007 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10008 and also the similar information mem_last_set (which insn most recently
10009 modified memory) and last_call_cuid (which insn was the most recent
10010 subroutine call). */
10013 record_dead_and_set_regs (insn
)
10019 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
10021 if (REG_NOTE_KIND (link
) == REG_DEAD
10022 && GET_CODE (XEXP (link
, 0)) == REG
)
10024 int regno
= REGNO (XEXP (link
, 0));
10026 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10027 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
10030 for (i
= regno
; i
< endregno
; i
++)
10031 reg_last_death
[i
] = insn
;
10033 else if (REG_NOTE_KIND (link
) == REG_INC
)
10034 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
10037 if (GET_CODE (insn
) == CALL_INSN
)
10039 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
10040 if (call_used_regs
[i
])
10042 reg_last_set_value
[i
] = 0;
10043 reg_last_set_mode
[i
] = 0;
10044 reg_last_set_nonzero_bits
[i
] = 0;
10045 reg_last_set_sign_bit_copies
[i
] = 0;
10046 reg_last_death
[i
] = 0;
10049 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
10052 record_dead_insn
= insn
;
10053 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
);
10056 /* Utility routine for the following function. Verify that all the registers
10057 mentioned in *LOC are valid when *LOC was part of a value set when
10058 label_tick == TICK. Return 0 if some are not.
10060 If REPLACE is non-zero, replace the invalid reference with
10061 (clobber (const_int 0)) and return 1. This replacement is useful because
10062 we often can get useful information about the form of a value (e.g., if
10063 it was produced by a shift that always produces -1 or 0) even though
10064 we don't know exactly what registers it was produced from. */
10067 get_last_value_validate (loc
, tick
, replace
)
10073 char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10074 int len
= GET_RTX_LENGTH (GET_CODE (x
));
10077 if (GET_CODE (x
) == REG
)
10079 int regno
= REGNO (x
);
10080 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10081 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10084 for (j
= regno
; j
< endregno
; j
++)
10085 if (reg_last_set_invalid
[j
]
10086 /* If this is a pseudo-register that was only set once, it is
10088 || (! (regno
>= FIRST_PSEUDO_REGISTER
&& reg_n_sets
[regno
] == 1)
10089 && reg_last_set_label
[j
] > tick
))
10092 *loc
= gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
10099 for (i
= 0; i
< len
; i
++)
10101 && get_last_value_validate (&XEXP (x
, i
), tick
, replace
) == 0)
10102 /* Don't bother with these. They shouldn't occur anyway. */
10106 /* If we haven't found a reason for it to be invalid, it is valid. */
10110 /* Get the last value assigned to X, if known. Some registers
10111 in the value may be replaced with (clobber (const_int 0)) if their value
10112 is known longer known reliably. */
10121 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10122 then convert it to the desired mode. If this is a paradoxical SUBREG,
10123 we cannot predict what values the "extra" bits might have. */
10124 if (GET_CODE (x
) == SUBREG
10125 && subreg_lowpart_p (x
)
10126 && (GET_MODE_SIZE (GET_MODE (x
))
10127 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
10128 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
10129 return gen_lowpart_for_combine (GET_MODE (x
), value
);
10131 if (GET_CODE (x
) != REG
)
10135 value
= reg_last_set_value
[regno
];
10137 /* If we don't have a value or if it isn't for this basic block, return 0. */
10140 || (reg_n_sets
[regno
] != 1
10141 && reg_last_set_label
[regno
] != label_tick
))
10144 /* If the value was set in a later insn than the ones we are processing,
10145 we can't use it even if the register was only set once, but make a quick
10146 check to see if the previous insn set it to something. This is commonly
10147 the case when the same pseudo is used by repeated insns.
10149 This does not work if there exists an instruction which is temporarily
10150 not on the insn chain. */
10152 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
10156 /* We can not do anything useful in this case, because there is
10157 an instruction which is not on the insn chain. */
10158 if (subst_prev_insn
)
10161 /* Skip over USE insns. They are not useful here, and they may have
10162 been made by combine, in which case they do not have a INSN_CUID
10163 value. We can't use prev_real_insn, because that would incorrectly
10164 take us backwards across labels. Skip over BARRIERs also, since
10165 they could have been made by combine. If we see one, we must be
10166 optimizing dead code, so it doesn't matter what we do. */
10167 for (insn
= prev_nonnote_insn (subst_insn
);
10168 insn
&& ((GET_CODE (insn
) == INSN
10169 && GET_CODE (PATTERN (insn
)) == USE
)
10170 || GET_CODE (insn
) == BARRIER
10171 || INSN_CUID (insn
) >= subst_low_cuid
);
10172 insn
= prev_nonnote_insn (insn
))
10176 && (set
= single_set (insn
)) != 0
10177 && rtx_equal_p (SET_DEST (set
), x
))
10179 value
= SET_SRC (set
);
10181 /* Make sure that VALUE doesn't reference X. Replace any
10182 explicit references with a CLOBBER. If there are any remaining
10183 references (rare), don't use the value. */
10185 if (reg_mentioned_p (x
, value
))
10186 value
= replace_rtx (copy_rtx (value
), x
,
10187 gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
));
10189 if (reg_overlap_mentioned_p (x
, value
))
10196 /* If the value has all its registers valid, return it. */
10197 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 0))
10200 /* Otherwise, make a copy and replace any invalid register with
10201 (clobber (const_int 0)). If that fails for some reason, return 0. */
10203 value
= copy_rtx (value
);
10204 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
10210 /* Return nonzero if expression X refers to a REG or to memory
10211 that is set in an instruction more recent than FROM_CUID. */
10214 use_crosses_set_p (x
, from_cuid
)
10218 register char *fmt
;
10220 register enum rtx_code code
= GET_CODE (x
);
10224 register int regno
= REGNO (x
);
10225 int endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10226 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10228 #ifdef PUSH_ROUNDING
10229 /* Don't allow uses of the stack pointer to be moved,
10230 because we don't know whether the move crosses a push insn. */
10231 if (regno
== STACK_POINTER_REGNUM
)
10234 for (;regno
< endreg
; regno
++)
10235 if (reg_last_set
[regno
]
10236 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
10241 if (code
== MEM
&& mem_last_set
> from_cuid
)
10244 fmt
= GET_RTX_FORMAT (code
);
10246 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10251 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10252 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
10255 else if (fmt
[i
] == 'e'
10256 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
10262 /* Define three variables used for communication between the following
10265 static int reg_dead_regno
, reg_dead_endregno
;
10266 static int reg_dead_flag
;
10268 /* Function called via note_stores from reg_dead_at_p.
10270 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10271 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10274 reg_dead_at_p_1 (dest
, x
)
10278 int regno
, endregno
;
10280 if (GET_CODE (dest
) != REG
)
10283 regno
= REGNO (dest
);
10284 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10285 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
10287 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
10288 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
10291 /* Return non-zero if REG is known to be dead at INSN.
10293 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10294 referencing REG, it is dead. If we hit a SET referencing REG, it is
10295 live. Otherwise, see if it is live or dead at the start of the basic
10296 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10297 must be assumed to be always live. */
10300 reg_dead_at_p (reg
, insn
)
10306 /* Set variables for reg_dead_at_p_1. */
10307 reg_dead_regno
= REGNO (reg
);
10308 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
10309 ? HARD_REGNO_NREGS (reg_dead_regno
,
10315 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10316 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
10318 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
10319 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
10323 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10324 beginning of function. */
10325 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
10326 insn
= prev_nonnote_insn (insn
))
10328 note_stores (PATTERN (insn
), reg_dead_at_p_1
);
10330 return reg_dead_flag
== 1 ? 1 : 0;
10332 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
10336 /* Get the basic block number that we were in. */
10341 for (block
= 0; block
< n_basic_blocks
; block
++)
10342 if (insn
== basic_block_head
[block
])
10345 if (block
== n_basic_blocks
)
10349 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
10350 if (basic_block_live_at_start
[block
][i
/ REGSET_ELT_BITS
]
10351 & ((REGSET_ELT_TYPE
) 1 << (i
% REGSET_ELT_BITS
)))
10357 /* Note hard registers in X that are used. This code is similar to
10358 that in flow.c, but much simpler since we don't care about pseudos. */
10361 mark_used_regs_combine (x
)
10364 register RTX_CODE code
= GET_CODE (x
);
10365 register int regno
;
10377 case ADDR_DIFF_VEC
:
10380 /* CC0 must die in the insn after it is set, so we don't need to take
10381 special note of it here. */
10387 /* If we are clobbering a MEM, mark any hard registers inside the
10388 address as used. */
10389 if (GET_CODE (XEXP (x
, 0)) == MEM
)
10390 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
10395 /* A hard reg in a wide mode may really be multiple registers.
10396 If so, mark all of them just like the first. */
10397 if (regno
< FIRST_PSEUDO_REGISTER
)
10399 /* None of this applies to the stack, frame or arg pointers */
10400 if (regno
== STACK_POINTER_REGNUM
10401 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10402 || regno
== HARD_FRAME_POINTER_REGNUM
10404 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10405 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
10407 || regno
== FRAME_POINTER_REGNUM
)
10410 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
10412 SET_HARD_REG_BIT (newpat_used_regs
, regno
+ i
);
10418 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10420 register rtx testreg
= SET_DEST (x
);
10422 while (GET_CODE (testreg
) == SUBREG
10423 || GET_CODE (testreg
) == ZERO_EXTRACT
10424 || GET_CODE (testreg
) == SIGN_EXTRACT
10425 || GET_CODE (testreg
) == STRICT_LOW_PART
)
10426 testreg
= XEXP (testreg
, 0);
10428 if (GET_CODE (testreg
) == MEM
)
10429 mark_used_regs_combine (XEXP (testreg
, 0));
10431 mark_used_regs_combine (SET_SRC (x
));
10436 /* Recursively scan the operands of this expression. */
10439 register char *fmt
= GET_RTX_FORMAT (code
);
10441 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10444 mark_used_regs_combine (XEXP (x
, i
));
10445 else if (fmt
[i
] == 'E')
10449 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
10450 mark_used_regs_combine (XVECEXP (x
, i
, j
));
10457 /* Remove register number REGNO from the dead registers list of INSN.
10459 Return the note used to record the death, if there was one. */
10462 remove_death (regno
, insn
)
10466 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
10470 reg_n_deaths
[regno
]--;
10471 remove_note (insn
, note
);
10477 /* For each register (hardware or pseudo) used within expression X, if its
10478 death is in an instruction with cuid between FROM_CUID (inclusive) and
10479 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10480 list headed by PNOTES.
10482 This is done when X is being merged by combination into TO_INSN. These
10483 notes will then be distributed as needed. */
10486 move_deaths (x
, from_cuid
, to_insn
, pnotes
)
10492 register char *fmt
;
10493 register int len
, i
;
10494 register enum rtx_code code
= GET_CODE (x
);
10498 register int regno
= REGNO (x
);
10499 register rtx where_dead
= reg_last_death
[regno
];
10500 register rtx before_dead
, after_dead
;
10502 /* WHERE_DEAD could be a USE insn made by combine, so first we
10503 make sure that we have insns with valid INSN_CUID values. */
10504 before_dead
= where_dead
;
10505 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
10506 before_dead
= PREV_INSN (before_dead
);
10507 after_dead
= where_dead
;
10508 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
10509 after_dead
= NEXT_INSN (after_dead
);
10511 if (before_dead
&& after_dead
10512 && INSN_CUID (before_dead
) >= from_cuid
10513 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
10514 || (where_dead
!= after_dead
10515 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
10517 rtx note
= remove_death (regno
, where_dead
);
10519 /* It is possible for the call above to return 0. This can occur
10520 when reg_last_death points to I2 or I1 that we combined with.
10521 In that case make a new note.
10523 We must also check for the case where X is a hard register
10524 and NOTE is a death note for a range of hard registers
10525 including X. In that case, we must put REG_DEAD notes for
10526 the remaining registers in place of NOTE. */
10528 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
10529 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
10530 != GET_MODE_SIZE (GET_MODE (x
))))
10532 int deadregno
= REGNO (XEXP (note
, 0));
10534 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
10535 GET_MODE (XEXP (note
, 0))));
10536 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
10539 for (i
= deadregno
; i
< deadend
; i
++)
10540 if (i
< regno
|| i
>= ourend
)
10541 REG_NOTES (where_dead
)
10542 = gen_rtx (EXPR_LIST
, REG_DEAD
,
10543 gen_rtx (REG
, reg_raw_mode
[i
], i
),
10544 REG_NOTES (where_dead
));
10546 /* If we didn't find any note, and we have a multi-reg hard
10547 register, then to be safe we must check for REG_DEAD notes
10548 for each register other than the first. They could have
10549 their own REG_DEAD notes lying around. */
10550 else if (note
== 0 && regno
< FIRST_PSEUDO_REGISTER
10551 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
10553 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
10557 for (i
= regno
+ 1; i
< ourend
; i
++)
10558 move_deaths (gen_rtx (REG
, reg_raw_mode
[i
], i
),
10559 from_cuid
, to_insn
, &oldnotes
);
10562 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
10564 XEXP (note
, 1) = *pnotes
;
10568 *pnotes
= gen_rtx (EXPR_LIST
, REG_DEAD
, x
, *pnotes
);
10570 reg_n_deaths
[regno
]++;
10576 else if (GET_CODE (x
) == SET
)
10578 rtx dest
= SET_DEST (x
);
10580 move_deaths (SET_SRC (x
), from_cuid
, to_insn
, pnotes
);
10582 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10583 that accesses one word of a multi-word item, some
10584 piece of everything register in the expression is used by
10585 this insn, so remove any old death. */
10587 if (GET_CODE (dest
) == ZERO_EXTRACT
10588 || GET_CODE (dest
) == STRICT_LOW_PART
10589 || (GET_CODE (dest
) == SUBREG
10590 && (((GET_MODE_SIZE (GET_MODE (dest
))
10591 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
10592 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
10593 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
10595 move_deaths (dest
, from_cuid
, to_insn
, pnotes
);
10599 /* If this is some other SUBREG, we know it replaces the entire
10600 value, so use that as the destination. */
10601 if (GET_CODE (dest
) == SUBREG
)
10602 dest
= SUBREG_REG (dest
);
10604 /* If this is a MEM, adjust deaths of anything used in the address.
10605 For a REG (the only other possibility), the entire value is
10606 being replaced so the old value is not used in this insn. */
10608 if (GET_CODE (dest
) == MEM
)
10609 move_deaths (XEXP (dest
, 0), from_cuid
, to_insn
, pnotes
);
10613 else if (GET_CODE (x
) == CLOBBER
)
10616 len
= GET_RTX_LENGTH (code
);
10617 fmt
= GET_RTX_FORMAT (code
);
10619 for (i
= 0; i
< len
; i
++)
10624 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10625 move_deaths (XVECEXP (x
, i
, j
), from_cuid
, to_insn
, pnotes
);
10627 else if (fmt
[i
] == 'e')
10628 move_deaths (XEXP (x
, i
), from_cuid
, to_insn
, pnotes
);
10632 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10633 pattern of an insn. X must be a REG. */
10636 reg_bitfield_target_p (x
, body
)
10642 if (GET_CODE (body
) == SET
)
10644 rtx dest
= SET_DEST (body
);
10646 int regno
, tregno
, endregno
, endtregno
;
10648 if (GET_CODE (dest
) == ZERO_EXTRACT
)
10649 target
= XEXP (dest
, 0);
10650 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
10651 target
= SUBREG_REG (XEXP (dest
, 0));
10655 if (GET_CODE (target
) == SUBREG
)
10656 target
= SUBREG_REG (target
);
10658 if (GET_CODE (target
) != REG
)
10661 tregno
= REGNO (target
), regno
= REGNO (x
);
10662 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
10663 return target
== x
;
10665 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
10666 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
10668 return endregno
> tregno
&& regno
< endtregno
;
10671 else if (GET_CODE (body
) == PARALLEL
)
10672 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
10673 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
10679 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10680 as appropriate. I3 and I2 are the insns resulting from the combination
10681 insns including FROM (I2 may be zero).
10683 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10684 not need REG_DEAD notes because they are being substituted for. This
10685 saves searching in the most common cases.
10687 Each note in the list is either ignored or placed on some insns, depending
10688 on the type of note. */
10691 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
10695 rtx elim_i2
, elim_i1
;
10697 rtx note
, next_note
;
10700 for (note
= notes
; note
; note
= next_note
)
10702 rtx place
= 0, place2
= 0;
10704 /* If this NOTE references a pseudo register, ensure it references
10705 the latest copy of that register. */
10706 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
10707 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
10708 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
10710 next_note
= XEXP (note
, 1);
10711 switch (REG_NOTE_KIND (note
))
10714 /* Any clobbers for i3 may still exist, and so we must process
10715 REG_UNUSED notes from that insn.
10717 Any clobbers from i2 or i1 can only exist if they were added by
10718 recog_for_combine. In that case, recog_for_combine created the
10719 necessary REG_UNUSED notes. Trying to keep any original
10720 REG_UNUSED notes from these insns can cause incorrect output
10721 if it is for the same register as the original i3 dest.
10722 In that case, we will notice that the register is set in i3,
10723 and then add a REG_UNUSED note for the destination of i3, which
10724 is wrong. However, it is possible to have REG_UNUSED notes from
10725 i2 or i1 for register which were both used and clobbered, so
10726 we keep notes from i2 or i1 if they will turn into REG_DEAD
10729 /* If this register is set or clobbered in I3, put the note there
10730 unless there is one already. */
10731 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
10733 if (from_insn
!= i3
)
10736 if (! (GET_CODE (XEXP (note
, 0)) == REG
10737 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
10738 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
10741 /* Otherwise, if this register is used by I3, then this register
10742 now dies here, so we must put a REG_DEAD note here unless there
10744 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
10745 && ! (GET_CODE (XEXP (note
, 0)) == REG
10746 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
10747 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
10749 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
10757 /* These notes say something about results of an insn. We can
10758 only support them if they used to be on I3 in which case they
10759 remain on I3. Otherwise they are ignored.
10761 If the note refers to an expression that is not a constant, we
10762 must also ignore the note since we cannot tell whether the
10763 equivalence is still true. It might be possible to do
10764 slightly better than this (we only have a problem if I2DEST
10765 or I1DEST is present in the expression), but it doesn't
10766 seem worth the trouble. */
10768 if (from_insn
== i3
10769 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
10774 case REG_NO_CONFLICT
:
10776 /* These notes say something about how a register is used. They must
10777 be present on any use of the register in I2 or I3. */
10778 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
10781 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
10791 /* It is too much trouble to try to see if this note is still
10792 correct in all situations. It is better to simply delete it. */
10796 /* If the insn previously containing this note still exists,
10797 put it back where it was. Otherwise move it to the previous
10798 insn. Adjust the corresponding REG_LIBCALL note. */
10799 if (GET_CODE (from_insn
) != NOTE
)
10803 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
10804 place
= prev_real_insn (from_insn
);
10806 XEXP (tem
, 0) = place
;
10811 /* This is handled similarly to REG_RETVAL. */
10812 if (GET_CODE (from_insn
) != NOTE
)
10816 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
10817 place
= next_real_insn (from_insn
);
10819 XEXP (tem
, 0) = place
;
10824 /* If the register is used as an input in I3, it dies there.
10825 Similarly for I2, if it is non-zero and adjacent to I3.
10827 If the register is not used as an input in either I3 or I2
10828 and it is not one of the registers we were supposed to eliminate,
10829 there are two possibilities. We might have a non-adjacent I2
10830 or we might have somehow eliminated an additional register
10831 from a computation. For example, we might have had A & B where
10832 we discover that B will always be zero. In this case we will
10833 eliminate the reference to A.
10835 In both cases, we must search to see if we can find a previous
10836 use of A and put the death note there. */
10839 && GET_CODE (from_insn
) == CALL_INSN
10840 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
10842 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
10844 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
10845 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
10848 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
10851 /* If the register is used in both I2 and I3 and it dies in I3,
10852 we might have added another reference to it. If reg_n_refs
10853 was 2, bump it to 3. This has to be correct since the
10854 register must have been set somewhere. The reason this is
10855 done is because local-alloc.c treats 2 references as a
10858 if (place
== i3
&& i2
!= 0 && GET_CODE (XEXP (note
, 0)) == REG
10859 && reg_n_refs
[REGNO (XEXP (note
, 0))]== 2
10860 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
10861 reg_n_refs
[REGNO (XEXP (note
, 0))] = 3;
10865 for (tem
= prev_nonnote_insn (i3
);
10867 && (GET_CODE (tem
) == INSN
|| GET_CODE (tem
) == CALL_INSN
);
10868 tem
= prev_nonnote_insn (tem
))
10870 /* If the register is being set at TEM, see if that is all
10871 TEM is doing. If so, delete TEM. Otherwise, make this
10872 into a REG_UNUSED note instead. */
10873 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
10875 rtx set
= single_set (tem
);
10877 /* Verify that it was the set, and not a clobber that
10878 modified the register. */
10880 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
10881 && (rtx_equal_p (XEXP (note
, 0), SET_DEST (set
))
10882 || (GET_CODE (SET_DEST (set
)) == SUBREG
10883 && rtx_equal_p (XEXP (note
, 0),
10884 XEXP (SET_DEST (set
), 0)))))
10886 /* Move the notes and links of TEM elsewhere.
10887 This might delete other dead insns recursively.
10888 First set the pattern to something that won't use
10891 PATTERN (tem
) = pc_rtx
;
10893 distribute_notes (REG_NOTES (tem
), tem
, tem
,
10894 NULL_RTX
, NULL_RTX
, NULL_RTX
);
10895 distribute_links (LOG_LINKS (tem
));
10897 PUT_CODE (tem
, NOTE
);
10898 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
10899 NOTE_SOURCE_FILE (tem
) = 0;
10903 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
10905 /* If there isn't already a REG_UNUSED note, put one
10907 if (! find_regno_note (tem
, REG_UNUSED
,
10908 REGNO (XEXP (note
, 0))))
10913 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
10914 || (GET_CODE (tem
) == CALL_INSN
10915 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
10919 /* If we are doing a 3->2 combination, and we have a
10920 register which formerly died in i3 and was not used
10921 by i2, which now no longer dies in i3 and is used in
10922 i2 but does not die in i2, and place is between i2
10923 and i3, then we may need to move a link from place to
10925 if (i2
&& INSN_UID (place
) <= max_uid_cuid
10926 && INSN_CUID (place
) > INSN_CUID (i2
)
10927 && from_insn
&& INSN_CUID (from_insn
) > INSN_CUID (i2
)
10928 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
10930 rtx links
= LOG_LINKS (place
);
10931 LOG_LINKS (place
) = 0;
10932 distribute_links (links
);
10938 /* If we haven't found an insn for the death note and it
10939 is still a REG_DEAD note, but we have hit a CODE_LABEL,
10940 insert a USE insn for the register at that label and
10941 put the death node there. This prevents problems with
10942 call-state tracking in caller-save.c. */
10943 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0 && tem
!= 0)
10946 = emit_insn_after (gen_rtx (USE
, VOIDmode
, XEXP (note
, 0)),
10949 /* If this insn was emitted between blocks, then update
10950 basic_block_head of the current block to include it. */
10951 if (basic_block_end
[this_basic_block
- 1] == tem
)
10952 basic_block_head
[this_basic_block
] = place
;
10956 /* If the register is set or already dead at PLACE, we needn't do
10957 anything with this note if it is still a REG_DEAD note.
10959 Note that we cannot use just `dead_or_set_p' here since we can
10960 convert an assignment to a register into a bit-field assignment.
10961 Therefore, we must also omit the note if the register is the
10962 target of a bitfield assignment. */
10964 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
10966 int regno
= REGNO (XEXP (note
, 0));
10968 if (dead_or_set_p (place
, XEXP (note
, 0))
10969 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
10971 /* Unless the register previously died in PLACE, clear
10972 reg_last_death. [I no longer understand why this is
10974 if (reg_last_death
[regno
] != place
)
10975 reg_last_death
[regno
] = 0;
10979 reg_last_death
[regno
] = place
;
10981 /* If this is a death note for a hard reg that is occupying
10982 multiple registers, ensure that we are still using all
10983 parts of the object. If we find a piece of the object
10984 that is unused, we must add a USE for that piece before
10985 PLACE and put the appropriate REG_DEAD note on it.
10987 An alternative would be to put a REG_UNUSED for the pieces
10988 on the insn that set the register, but that can't be done if
10989 it is not in the same block. It is simpler, though less
10990 efficient, to add the USE insns. */
10992 if (place
&& regno
< FIRST_PSEUDO_REGISTER
10993 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
10996 = regno
+ HARD_REGNO_NREGS (regno
,
10997 GET_MODE (XEXP (note
, 0)));
11001 for (i
= regno
; i
< endregno
; i
++)
11002 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
11003 && ! find_regno_fusage (place
, USE
, i
))
11005 rtx piece
= gen_rtx (REG
, reg_raw_mode
[i
], i
);
11008 /* See if we already placed a USE note for this
11009 register in front of PLACE. */
11011 GET_CODE (PREV_INSN (p
)) == INSN
11012 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
11014 if (rtx_equal_p (piece
,
11015 XEXP (PATTERN (PREV_INSN (p
)), 0)))
11024 = emit_insn_before (gen_rtx (USE
, VOIDmode
,
11027 REG_NOTES (use_insn
)
11028 = gen_rtx (EXPR_LIST
, REG_DEAD
, piece
,
11029 REG_NOTES (use_insn
));
11035 /* Check for the case where the register dying partially
11036 overlaps the register set by this insn. */
11038 for (i
= regno
; i
< endregno
; i
++)
11039 if (dead_or_set_regno_p (place
, i
))
11047 /* Put only REG_DEAD notes for pieces that are
11048 still used and that are not already dead or set. */
11050 for (i
= regno
; i
< endregno
; i
++)
11052 rtx piece
= gen_rtx (REG
, reg_raw_mode
[i
], i
);
11054 if ((reg_referenced_p (piece
, PATTERN (place
))
11055 || (GET_CODE (place
) == CALL_INSN
11056 && find_reg_fusage (place
, USE
, piece
)))
11057 && ! dead_or_set_p (place
, piece
)
11058 && ! reg_bitfield_target_p (piece
,
11060 REG_NOTES (place
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
11062 REG_NOTES (place
));
11072 /* Any other notes should not be present at this point in the
11079 XEXP (note
, 1) = REG_NOTES (place
);
11080 REG_NOTES (place
) = note
;
11082 else if ((REG_NOTE_KIND (note
) == REG_DEAD
11083 || REG_NOTE_KIND (note
) == REG_UNUSED
)
11084 && GET_CODE (XEXP (note
, 0)) == REG
)
11085 reg_n_deaths
[REGNO (XEXP (note
, 0))]--;
11089 if ((REG_NOTE_KIND (note
) == REG_DEAD
11090 || REG_NOTE_KIND (note
) == REG_UNUSED
)
11091 && GET_CODE (XEXP (note
, 0)) == REG
)
11092 reg_n_deaths
[REGNO (XEXP (note
, 0))]++;
11094 REG_NOTES (place2
) = gen_rtx (GET_CODE (note
), REG_NOTE_KIND (note
),
11095 XEXP (note
, 0), REG_NOTES (place2
));
11100 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11101 I3, I2, and I1 to new locations. This is also called in one case to
11102 add a link pointing at I3 when I3's destination is changed. */
11105 distribute_links (links
)
11108 rtx link
, next_link
;
11110 for (link
= links
; link
; link
= next_link
)
11116 next_link
= XEXP (link
, 1);
11118 /* If the insn that this link points to is a NOTE or isn't a single
11119 set, ignore it. In the latter case, it isn't clear what we
11120 can do other than ignore the link, since we can't tell which
11121 register it was for. Such links wouldn't be used by combine
11124 It is not possible for the destination of the target of the link to
11125 have been changed by combine. The only potential of this is if we
11126 replace I3, I2, and I1 by I3 and I2. But in that case the
11127 destination of I2 also remains unchanged. */
11129 if (GET_CODE (XEXP (link
, 0)) == NOTE
11130 || (set
= single_set (XEXP (link
, 0))) == 0)
11133 reg
= SET_DEST (set
);
11134 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
11135 || GET_CODE (reg
) == SIGN_EXTRACT
11136 || GET_CODE (reg
) == STRICT_LOW_PART
)
11137 reg
= XEXP (reg
, 0);
11139 /* A LOG_LINK is defined as being placed on the first insn that uses
11140 a register and points to the insn that sets the register. Start
11141 searching at the next insn after the target of the link and stop
11142 when we reach a set of the register or the end of the basic block.
11144 Note that this correctly handles the link that used to point from
11145 I3 to I2. Also note that not much searching is typically done here
11146 since most links don't point very far away. */
11148 for (insn
= NEXT_INSN (XEXP (link
, 0));
11149 (insn
&& (this_basic_block
== n_basic_blocks
- 1
11150 || basic_block_head
[this_basic_block
+ 1] != insn
));
11151 insn
= NEXT_INSN (insn
))
11152 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
11153 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
11155 if (reg_referenced_p (reg
, PATTERN (insn
)))
11159 else if (GET_CODE (insn
) == CALL_INSN
11160 && find_reg_fusage (insn
, USE
, reg
))
11166 /* If we found a place to put the link, place it there unless there
11167 is already a link to the same insn as LINK at that point. */
11173 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
11174 if (XEXP (link2
, 0) == XEXP (link
, 0))
11179 XEXP (link
, 1) = LOG_LINKS (place
);
11180 LOG_LINKS (place
) = link
;
11182 /* Set added_links_insn to the earliest insn we added a
11184 if (added_links_insn
== 0
11185 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
11186 added_links_insn
= place
;
11193 dump_combine_stats (file
)
11198 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11199 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
11203 dump_combine_total_stats (file
)
11208 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11209 total_attempts
, total_merges
, total_extras
, total_successes
);