1 ;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
3 ;; This file is part of GCC.
5 ;; GCC is free software; you can redistribute it and/or modify it
6 ;; under the terms of the GNU General Public License as published
7 ;; by the Free Software Foundation; either version 3, or (at your
8 ;; option) any later version.
10 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
11 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
13 ;; License for more details.
15 ;; You should have received a copy of the GNU General Public License
16 ;; along with GCC; see the file COPYING3. If not see
17 ;; <http://www.gnu.org/licenses/>.
19 ;; This file contains ARM instructions that support fixed-point operations.
21 (define_insn "add<mode>3"
22 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
23 (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r")
24 (match_operand:FIXED 2 "s_register_operand" "l,r")))]
27 [(set_attr "predicable" "yes")
28 (set_attr "predicable_short_it" "yes,no")
29 (set_attr "type" "alu_sreg")])
31 (define_insn "add<mode>3"
32 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
34 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
36 "sadd<qaddsub_suf>%?\\t%0, %1, %2"
37 [(set_attr "predicable" "yes")
38 (set_attr "type" "alu_dsp_reg")])
40 (define_insn "usadd<mode>3"
41 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
42 (us_plus:UQADDSUB (match_operand:UQADDSUB 1 "s_register_operand" "r")
43 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
45 "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
46 [(set_attr "predicable" "yes")
47 (set_attr "type" "alu_dsp_reg")])
49 (define_insn "ssadd<mode>3"
50 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
51 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
52 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
54 "qadd<qaddsub_suf>%?\\t%0, %1, %2"
55 [(set_attr "predicable" "yes")
56 (set_attr "type" "alu_dsp_reg")])
58 (define_insn "sub<mode>3"
59 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
60 (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r")
61 (match_operand:FIXED 2 "s_register_operand" "l,r")))]
64 [(set_attr "predicable" "yes")
65 (set_attr "predicable_short_it" "yes,no")
66 (set_attr "type" "alu_sreg")])
68 (define_insn "sub<mode>3"
69 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
70 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
71 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
73 "ssub<qaddsub_suf>%?\\t%0, %1, %2"
74 [(set_attr "predicable" "yes")
75 (set_attr "type" "alu_dsp_reg")])
77 (define_insn "ussub<mode>3"
78 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
80 (match_operand:UQADDSUB 1 "s_register_operand" "r")
81 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
83 "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
84 [(set_attr "predicable" "yes")
85 (set_attr "type" "alu_dsp_reg")])
87 (define_insn "sssub<mode>3"
88 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
89 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
90 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
92 "qsub<qaddsub_suf>%?\\t%0, %1, %2"
93 [(set_attr "predicable" "yes")
94 (set_attr "type" "alu_dsp_reg")])
96 ;; Fractional multiplies.
98 ; Note: none of these do any rounding.
100 (define_expand "mulqq3"
101 [(set (match_operand:QQ 0 "s_register_operand" "")
102 (mult:QQ (match_operand:QQ 1 "s_register_operand" "")
103 (match_operand:QQ 2 "s_register_operand" "")))]
104 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
106 rtx tmp1 = gen_reg_rtx (HImode);
107 rtx tmp2 = gen_reg_rtx (HImode);
108 rtx tmp3 = gen_reg_rtx (SImode);
110 emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1])));
111 emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2])));
112 emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2));
113 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp3, GEN_INT (8),
118 (define_expand "mulhq3"
119 [(set (match_operand:HQ 0 "s_register_operand" "")
120 (mult:HQ (match_operand:HQ 1 "s_register_operand" "")
121 (match_operand:HQ 2 "s_register_operand" "")))]
122 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
124 rtx tmp = gen_reg_rtx (SImode);
126 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
127 gen_lowpart (HImode, operands[2])));
128 /* We're doing a s.15 * s.15 multiplication, getting an s.30 result. Extract
129 an s.15 value from that. This won't overflow/saturate for _Fract
131 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp,
132 GEN_INT (16), GEN_INT (15)));
136 (define_expand "mulsq3"
137 [(set (match_operand:SQ 0 "s_register_operand" "")
138 (mult:SQ (match_operand:SQ 1 "s_register_operand" "")
139 (match_operand:SQ 2 "s_register_operand" "")))]
142 rtx tmp1 = gen_reg_rtx (DImode);
143 rtx tmp2 = gen_reg_rtx (SImode);
144 rtx tmp3 = gen_reg_rtx (SImode);
146 /* s.31 * s.31 -> s.62 multiplication. */
147 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
148 gen_lowpart (SImode, operands[2])));
149 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (31)));
150 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (1)));
151 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
156 ;; Accumulator multiplies.
158 (define_expand "mulsa3"
159 [(set (match_operand:SA 0 "s_register_operand" "")
160 (mult:SA (match_operand:SA 1 "s_register_operand" "")
161 (match_operand:SA 2 "s_register_operand" "")))]
164 rtx tmp1 = gen_reg_rtx (DImode);
165 rtx tmp2 = gen_reg_rtx (SImode);
166 rtx tmp3 = gen_reg_rtx (SImode);
168 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
169 gen_lowpart (SImode, operands[2])));
170 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15)));
171 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (17)));
172 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
177 (define_expand "mulusa3"
178 [(set (match_operand:USA 0 "s_register_operand" "")
179 (mult:USA (match_operand:USA 1 "s_register_operand" "")
180 (match_operand:USA 2 "s_register_operand" "")))]
183 rtx tmp1 = gen_reg_rtx (DImode);
184 rtx tmp2 = gen_reg_rtx (SImode);
185 rtx tmp3 = gen_reg_rtx (SImode);
187 emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
188 gen_lowpart (SImode, operands[2])));
189 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16)));
190 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16)));
191 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
196 ;; The code sequence emitted by this insn pattern uses the Q flag, which GCC
197 ;; doesn't generally know about, so we don't bother expanding to individual
198 ;; instructions. It may be better to just use an out-of-line asm libcall for
201 (define_insn "ssmulsa3"
202 [(set (match_operand:SA 0 "s_register_operand" "=r")
203 (ss_mult:SA (match_operand:SA 1 "s_register_operand" "r")
204 (match_operand:SA 2 "s_register_operand" "r")))
205 (clobber (match_scratch:DI 3 "=r"))
206 (clobber (match_scratch:SI 4 "=r"))
207 (clobber (reg:CC CC_REGNUM))]
208 "TARGET_32BIT && arm_arch6"
210 /* s16.15 * s16.15 -> s32.30. */
211 output_asm_insn ("smull\\t%Q3, %R3, %1, %2", operands);
214 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
217 output_asm_insn ("mov\\t%4, #0", operands);
218 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
222 31 high word 0 31 low word 0
224 [ S i i .... i i i ] [ i f f f ... f f ]
227 [ S i ... i f ... f f ]
229 Need 16 integral bits, so saturate at 15th bit of high word. */
231 output_asm_insn ("ssat\\t%R3, #15, %R3", operands);
232 output_asm_insn ("mrs\\t%4, APSR", operands);
233 output_asm_insn ("tst\\t%4, #1<<27", operands);
236 output_asm_insn ("mvn\\t%4, %R3, asr #32", operands);
237 output_asm_insn ("it\\tne", operands);
238 output_asm_insn ("movne\\t%Q3, %4", operands);
243 output_asm_insn ("it\\tne", operands);
244 output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands);
246 output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands);
247 output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands);
250 [(set_attr "conds" "clob")
251 (set_attr "type" "multiple")
253 (if_then_else (eq_attr "is_thumb" "yes")
254 (if_then_else (match_test "arm_restrict_it")
259 ;; Same goes for this.
261 (define_insn "usmulusa3"
262 [(set (match_operand:USA 0 "s_register_operand" "=r")
263 (us_mult:USA (match_operand:USA 1 "s_register_operand" "r")
264 (match_operand:USA 2 "s_register_operand" "r")))
265 (clobber (match_scratch:DI 3 "=r"))
266 (clobber (match_scratch:SI 4 "=r"))
267 (clobber (reg:CC CC_REGNUM))]
268 "TARGET_32BIT && arm_arch6"
270 /* 16.16 * 16.16 -> 32.32. */
271 output_asm_insn ("umull\\t%Q3, %R3, %1, %2", operands);
274 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
277 output_asm_insn ("mov\\t%4, #0", operands);
278 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
282 31 high word 0 31 low word 0
284 [ i i i .... i i i ] [ f f f f ... f f ]
287 [ i i ... i f ... f f ]
289 Need 16 integral bits, so saturate at 16th bit of high word. */
291 output_asm_insn ("usat\\t%R3, #16, %R3", operands);
292 output_asm_insn ("mrs\\t%4, APSR", operands);
293 output_asm_insn ("tst\\t%4, #1<<27", operands);
296 output_asm_insn ("sbfx\\t%4, %R3, #15, #1", operands);
297 output_asm_insn ("it\\tne", operands);
298 output_asm_insn ("movne\\t%Q3, %4", operands);
303 output_asm_insn ("it\\tne", operands);
304 output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands);
306 output_asm_insn ("lsr\\t%0, %Q3, #16", operands);
307 output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands);
310 [(set_attr "conds" "clob")
311 (set_attr "type" "multiple")
313 (if_then_else (eq_attr "is_thumb" "yes")
314 (if_then_else (match_test "arm_restrict_it")
319 (define_expand "mulha3"
320 [(set (match_operand:HA 0 "s_register_operand" "")
321 (mult:HA (match_operand:HA 1 "s_register_operand" "")
322 (match_operand:HA 2 "s_register_operand" "")))]
323 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
325 rtx tmp = gen_reg_rtx (SImode);
327 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
328 gen_lowpart (HImode, operands[2])));
329 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16),
335 (define_expand "muluha3"
336 [(set (match_operand:UHA 0 "s_register_operand" "")
337 (mult:UHA (match_operand:UHA 1 "s_register_operand" "")
338 (match_operand:UHA 2 "s_register_operand" "")))]
339 "TARGET_DSP_MULTIPLY"
341 rtx tmp1 = gen_reg_rtx (SImode);
342 rtx tmp2 = gen_reg_rtx (SImode);
343 rtx tmp3 = gen_reg_rtx (SImode);
345 /* 8.8 * 8.8 -> 16.16 multiply. */
346 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
347 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
348 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
349 emit_insn (gen_extzv (gen_lowpart (SImode, operands[0]), tmp3,
350 GEN_INT (16), GEN_INT (8)));
355 (define_expand "ssmulha3"
356 [(set (match_operand:HA 0 "s_register_operand" "")
357 (ss_mult:HA (match_operand:HA 1 "s_register_operand" "")
358 (match_operand:HA 2 "s_register_operand" "")))]
359 "TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6"
361 rtx tmp = gen_reg_rtx (SImode);
364 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
365 gen_lowpart (HImode, operands[2])));
367 rshift = gen_rtx_ASHIFTRT (SImode, tmp, GEN_INT (7));
369 emit_insn (gen_rtx_SET (gen_lowpart (HImode, operands[0]),
370 gen_rtx_SS_TRUNCATE (HImode, rshift)));
375 (define_expand "usmuluha3"
376 [(set (match_operand:UHA 0 "s_register_operand" "")
377 (us_mult:UHA (match_operand:UHA 1 "s_register_operand" "")
378 (match_operand:UHA 2 "s_register_operand" "")))]
381 rtx tmp1 = gen_reg_rtx (SImode);
382 rtx tmp2 = gen_reg_rtx (SImode);
383 rtx tmp3 = gen_reg_rtx (SImode);
384 rtx rshift_tmp = gen_reg_rtx (SImode);
386 /* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a
387 normal 32x32->32-bit multiply instead. */
388 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
389 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
391 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
393 /* The operand to "usat" is signed, so we cannot use the "..., asr #8"
394 form of that instruction since the multiplication result TMP3 may have the
395 top bit set, thus be negative and saturate to zero. Use a separate
396 logical right-shift instead. */
397 emit_insn (gen_lshrsi3 (rshift_tmp, tmp3, GEN_INT (8)));
398 emit_insn (gen_arm_usatsihi (gen_lowpart (HImode, operands[0]), rshift_tmp));
403 (define_insn "arm_ssatsihi_shift"
404 [(set (match_operand:HI 0 "s_register_operand" "=r")
405 (ss_truncate:HI (match_operator:SI 1 "sat_shift_operator"
406 [(match_operand:SI 2 "s_register_operand" "r")
407 (match_operand:SI 3 "immediate_operand" "I")])))]
408 "TARGET_32BIT && arm_arch6"
409 "ssat%?\\t%0, #16, %2%S1"
410 [(set_attr "predicable" "yes")
411 (set_attr "shift" "1")
412 (set_attr "type" "alu_shift_imm")])
414 (define_insn "arm_usatsihi"
415 [(set (match_operand:HI 0 "s_register_operand" "=r")
416 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))]
418 "usat%?\\t%0, #16, %1"
419 [(set_attr "predicable" "yes")
420 (set_attr "type" "alu_imm")]