1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx
*reg_last_reload_reg
;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload
;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload
;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx
*reg_equiv_constant
;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx
*reg_equiv_invariant
;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx
*reg_equiv_memory_loc
;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx
,gc
) *reg_equiv_memory_loc_vec
;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx
*reg_equiv_address
;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx
*reg_equiv_alt_mem_list
;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width
;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size
;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber
;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid
;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead
;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs
;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global
;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET
*pseudo_previous_regs
;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET
*pseudo_forbidden_regs
;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs
;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg
;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels
;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok
;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok
;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos
;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos
;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted
;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid
;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed
;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress
= 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
284 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack
;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj
;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj
;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj
;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain
*reload_insn_chain
;
307 /* List of all insns needing reloads. */
308 static struct insn_chain
*insns_need_reload
;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from
; /* Register number to be eliminated. */
318 int to
; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
320 int can_eliminate
; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
325 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx
; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx
; /* REG rtx for the replacement. */
334 static struct elim_table
*reg_eliminate
= 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1
[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset
;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable
;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants
;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num
;
377 static char *offsets_known_at
;
378 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
380 /* Number of labels in the current function. */
382 static int num_labels
;
384 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain
*);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain
*, int);
389 static void find_reload_regs (struct insn_chain
*);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx
, enum reg_class
);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx
);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx
, rtx
, int);
398 static void check_eliminable_occurrences (rtx
);
399 static void elimination_effects (rtx
, enum machine_mode
);
400 static int eliminate_regs_in_insn (rtx
, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx
, const_rtx
, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx
);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET
*);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx
);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain
*);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
416 static void forget_marked_reloads (regset
);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
425 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
428 static int allocate_reload_reg (struct insn_chain
*, int, int);
429 static int conflicts_with_override (rtx
);
430 static void failed_reload (rtx
, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
433 static void choose_reload_regs (struct insn_chain
*);
434 static void merge_assigned_reloads (rtx
);
435 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
437 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
439 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
440 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
441 static void emit_reload_insns (struct insn_chain
*);
442 static void delete_output_reload (rtx
, int, int, rtx
);
443 static void delete_address_reloads (rtx
, rtx
);
444 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
445 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
447 static void add_auto_inc_notes (rtx
, rtx
);
449 static void copy_eh_notes (rtx
, rtx
);
450 static void substitute (rtx
*, const_rtx
, rtx
);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
454 static rtx
emit_insn_if_valid_for_reload (rtx
);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode
,
472 LAST_VIRTUAL_REGISTER
+ 1),
474 spill_indirect_levels
= 0;
476 while (memory_address_p (QImode
, tem
))
478 spill_indirect_levels
++;
479 tem
= gen_rtx_MEM (Pmode
, tem
);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
485 indirect_symref_ok
= memory_address_p (QImode
, tem
);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
491 tem
= gen_rtx_PLUS (Pmode
,
492 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
493 gen_rtx_REG (Pmode
, i
));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem
= plus_constant (tem
, 4);
498 if (memory_address_p (QImode
, tem
))
500 double_reg_address_ok
= 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack
);
507 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
509 INIT_REG_SET (&spilled_pseudos
);
510 INIT_REG_SET (&changed_allocation_pseudos
);
511 INIT_REG_SET (&pseudos_counted
);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain
*unused_insn_chains
= 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain
*c
;
523 if (unused_insn_chains
== 0)
525 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
526 INIT_REG_SET (&c
->live_throughout
);
527 INIT_REG_SET (&c
->dead_or_set
);
531 c
= unused_insn_chains
;
532 unused_insn_chains
= c
->next
;
534 c
->is_caller_save_insn
= 0;
535 c
->need_operand_change
= 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
548 reg_set_iterator rsi
;
550 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
552 int r
= reg_renumber
[regno
];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert ((flag_ira
&& optimize
) || reload_completed
);
563 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
584 unsigned int regno
= REGNO (x
);
586 if (regno
< FIRST_PSEUDO_REGISTER
)
589 x
= eliminate_regs (x
, mem_mode
, usage
);
593 replace_pseudos_in (loc
, mem_mode
, usage
);
597 if (reg_equiv_constant
[regno
])
598 *loc
= reg_equiv_constant
[regno
];
599 else if (reg_equiv_mem
[regno
])
600 *loc
= reg_equiv_mem
[regno
];
601 else if (reg_equiv_address
[regno
])
602 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
605 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
606 || REGNO (regno_reg_rtx
[regno
]) != regno
);
607 *loc
= regno_reg_rtx
[regno
];
612 else if (code
== MEM
)
614 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
618 /* Process each of our operands recursively. */
619 fmt
= GET_RTX_FORMAT (code
);
620 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
622 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
623 else if (*fmt
== 'E')
624 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
625 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block
*tos
, *worklist
, bb
;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
646 bb
->flags
&= ~BB_REACHABLE
;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
650 *tos
++ = EXIT_BLOCK_PTR
;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos
!= worklist
)
657 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
658 if (!(e
->flags
& EDGE_ABNORMAL
))
660 basic_block src
= e
->src
;
662 if (!(src
->flags
& BB_REACHABLE
))
664 src
->flags
|= BB_REACHABLE
;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb
->flags
& BB_REACHABLE
)
675 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
676 if (e
->flags
& EDGE_ABNORMAL
)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination
;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed
;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr
;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first
, int global
)
715 struct elim_table
*ep
;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED
);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid
= get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
739 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun
->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl
->saves_all_registers
= 1;
759 if (crtl
->saves_all_registers
)
760 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
761 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
762 df_set_regs_ever_live (i
, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant
= XCNEWVEC (rtx
, max_regno
);
775 reg_equiv_invariant
= XCNEWVEC (rtx
, max_regno
);
776 reg_equiv_mem
= XCNEWVEC (rtx
, max_regno
);
777 reg_equiv_alt_mem_list
= XCNEWVEC (rtx
, max_regno
);
778 reg_equiv_address
= XCNEWVEC (rtx
, max_regno
);
779 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
780 reg_old_renumber
= XCNEWVEC (short, max_regno
);
781 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
782 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
783 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants
= 0;
792 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
794 rtx set
= single_set (insn
);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
800 && GET_MODE (insn
) != VOIDmode
)
801 PUT_MODE (insn
, VOIDmode
);
804 scan_paradoxical_subregs (PATTERN (insn
));
806 if (set
!= 0 && REG_P (SET_DEST (set
)))
808 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
814 i
= REGNO (SET_DEST (set
));
817 if (i
<= LAST_VIRTUAL_REGISTER
)
820 if (! function_invariant_p (x
)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x
)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x
, VOIDmode
))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
840 else if (function_invariant_p (x
))
842 if (GET_CODE (x
) == PLUS
)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant
[i
] = copy_rtx (x
);
847 num_eliminable_invariants
++;
849 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
851 reg_equiv_invariant
[i
] = x
;
852 num_eliminable_invariants
++;
854 else if (LEGITIMATE_CONSTANT_P (x
))
855 reg_equiv_constant
[i
] = x
;
858 reg_equiv_memory_loc
[i
]
859 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
860 if (! reg_equiv_memory_loc
[i
])
861 reg_equiv_init
[i
] = NULL_RTX
;
866 reg_equiv_init
[i
] = NULL_RTX
;
871 reg_equiv_init
[i
] = NULL_RTX
;
876 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
877 if (reg_equiv_init
[i
])
879 fprintf (dump_file
, "init_insns for %u: ", i
);
880 print_inline_rtx (dump_file
, reg_equiv_init
[i
], 20);
881 fprintf (dump_file
, "\n");
886 first_label_num
= get_first_label_num ();
887 num_labels
= max_label_num () - first_label_num
;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at
= XNEWVEC (char, num_labels
);
894 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
901 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
902 temp_pseudo_reg_arr
[n
++] = i
;
904 if (flag_ira
&& optimize
)
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
909 for (i
= 0; i
< n
; i
++)
910 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
920 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
922 maybe_fix_stack_asms ();
924 insns_need_reload
= 0;
925 something_needs_elimination
= 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs
);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
938 int can_eliminate
= 0;
941 can_eliminate
|= ep
->can_eliminate
;
944 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
946 spill_hard_reg (from
, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed
)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
953 finish_spills (global
);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress
= 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed
;
966 HOST_WIDE_INT starting_frame_size
;
968 starting_frame_size
= get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
998 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
1000 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
1002 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
1004 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
1005 else if (CONSTANT_P (XEXP (x
, 0))
1006 || (REG_P (XEXP (x
, 0))
1007 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
1008 || (GET_CODE (XEXP (x
, 0)) == PLUS
1009 && REG_P (XEXP (XEXP (x
, 0), 0))
1010 && (REGNO (XEXP (XEXP (x
, 0), 0))
1011 < FIRST_PSEUDO_REGISTER
)
1012 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
1013 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
1016 /* Make a new stack slot. Then indicate that something
1017 changed so we go back and recompute offsets for
1018 eliminable registers because the allocation of memory
1019 below might change some offset. reg_equiv_{mem,address}
1020 will be set up for this pseudo on the next pass around
1022 reg_equiv_memory_loc
[i
] = 0;
1023 reg_equiv_init
[i
] = 0;
1024 alter_reg (i
, -1, true);
1028 if (caller_save_needed
)
1029 setup_save_areas ();
1031 /* If we allocated another stack slot, redo elimination bookkeeping. */
1032 if (starting_frame_size
!= get_frame_size ())
1034 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
1036 /* If we have a stack frame, we must align it now. The
1037 stack size may be a part of the offset computation for
1038 register elimination. So if this changes the stack size,
1039 then repeat the elimination bookkeeping. We don't
1040 realign when there is no stack, as that will cause a
1041 stack frame when none is needed should
1042 STARTING_FRAME_OFFSET not be already aligned to
1044 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
1045 if (starting_frame_size
!= get_frame_size ())
1049 if (caller_save_needed
)
1051 save_call_clobbered_regs ();
1052 /* That might have allocated new insn_chain structures. */
1053 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1056 calculate_needs_all_insns (global
);
1058 if (! flag_ira
|| ! optimize
)
1059 /* Don't do it for IRA. We need this info because we don't
1060 change live_throughout and dead_or_set for chains when IRA
1062 CLEAR_REG_SET (&spilled_pseudos
);
1066 something_changed
= 0;
1068 /* If we allocated any new memory locations, make another pass
1069 since it might have changed elimination offsets. */
1070 if (starting_frame_size
!= get_frame_size ())
1071 something_changed
= 1;
1073 /* Even if the frame size remained the same, we might still have
1074 changed elimination offsets, e.g. if find_reloads called
1075 force_const_mem requiring the back end to allocate a constant
1076 pool base register that needs to be saved on the stack. */
1077 else if (!verify_initial_elim_offsets ())
1078 something_changed
= 1;
1081 HARD_REG_SET to_spill
;
1082 CLEAR_HARD_REG_SET (to_spill
);
1083 update_eliminables (&to_spill
);
1084 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
1086 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1087 if (TEST_HARD_REG_BIT (to_spill
, i
))
1089 spill_hard_reg (i
, 1);
1092 /* Regardless of the state of spills, if we previously had
1093 a register that we thought we could eliminate, but now can
1094 not eliminate, we must run another pass.
1096 Consider pseudos which have an entry in reg_equiv_* which
1097 reference an eliminable register. We must make another pass
1098 to update reg_equiv_* so that we do not substitute in the
1099 old value from when we thought the elimination could be
1101 something_changed
= 1;
1105 select_reload_regs ();
1109 if (insns_need_reload
!= 0 || did_spill
)
1110 something_changed
|= finish_spills (global
);
1112 if (! something_changed
)
1115 if (caller_save_needed
)
1116 delete_caller_save_insns ();
1118 obstack_free (&reload_obstack
, reload_firstobj
);
1121 if (flag_ira
&& optimize
)
1122 /* Restore the original insn chain order for correct reload work
1123 (e.g. for correct inheritance). */
1124 ira_sort_insn_chain (false);
1126 /* If global-alloc was run, notify it of any register eliminations we have
1129 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1130 if (ep
->can_eliminate
)
1131 mark_elimination (ep
->from
, ep
->to
);
1133 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1134 If that insn didn't set the register (i.e., it copied the register to
1135 memory), just delete that insn instead of the equivalencing insn plus
1136 anything now dead. If we call delete_dead_insn on that insn, we may
1137 delete the insn that actually sets the register if the register dies
1138 there and that is incorrect. */
1140 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1142 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1145 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1147 rtx equiv_insn
= XEXP (list
, 0);
1149 /* If we already deleted the insn or if it may trap, we can't
1150 delete it. The latter case shouldn't happen, but can
1151 if an insn has a variable address, gets a REG_EH_REGION
1152 note added to it, and then gets converted into a load
1153 from a constant address. */
1154 if (NOTE_P (equiv_insn
)
1155 || can_throw_internal (equiv_insn
))
1157 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1158 delete_dead_insn (equiv_insn
);
1160 SET_INSN_DELETED (equiv_insn
);
1165 /* Use the reload registers where necessary
1166 by generating move instructions to move the must-be-register
1167 values into or out of the reload registers. */
1169 if (insns_need_reload
!= 0 || something_needs_elimination
1170 || something_needs_operands_changed
)
1172 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1174 reload_as_needed (global
);
1176 gcc_assert (old_frame_size
== get_frame_size ());
1178 gcc_assert (verify_initial_elim_offsets ());
1181 /* If we were able to eliminate the frame pointer, show that it is no
1182 longer live at the start of any basic block. If it ls live by
1183 virtue of being in a pseudo, that pseudo will be marked live
1184 and hence the frame pointer will be known to be live via that
1187 if (! frame_pointer_needed
)
1189 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1191 /* Come here (with failure set nonzero) if we can't get enough spill
1195 CLEAR_REG_SET (&changed_allocation_pseudos
);
1196 CLEAR_REG_SET (&spilled_pseudos
);
1197 reload_in_progress
= 0;
1199 /* Now eliminate all pseudo regs by modifying them into
1200 their equivalent memory references.
1201 The REG-rtx's for the pseudos are modified in place,
1202 so all insns that used to refer to them now refer to memory.
1204 For a reg that has a reg_equiv_address, all those insns
1205 were changed by reloading so that no insns refer to it any longer;
1206 but the DECL_RTL of a variable decl may refer to it,
1207 and if so this causes the debugging info to mention the variable. */
1209 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1213 if (reg_equiv_mem
[i
])
1214 addr
= XEXP (reg_equiv_mem
[i
], 0);
1216 if (reg_equiv_address
[i
])
1217 addr
= reg_equiv_address
[i
];
1221 if (reg_renumber
[i
] < 0)
1223 rtx reg
= regno_reg_rtx
[i
];
1225 REG_USERVAR_P (reg
) = 0;
1226 PUT_CODE (reg
, MEM
);
1227 XEXP (reg
, 0) = addr
;
1228 if (reg_equiv_memory_loc
[i
])
1229 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1232 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1233 MEM_ATTRS (reg
) = 0;
1235 MEM_NOTRAP_P (reg
) = 1;
1237 else if (reg_equiv_mem
[i
])
1238 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1242 /* We must set reload_completed now since the cleanup_subreg_operands call
1243 below will re-recognize each insn and reload may have generated insns
1244 which are only valid during and after reload. */
1245 reload_completed
= 1;
1247 /* Make a pass over all the insns and delete all USEs which we inserted
1248 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1249 notes. Delete all CLOBBER insns, except those that refer to the return
1250 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1251 from misarranging variable-array code, and simplify (subreg (reg))
1252 operands. Strip and regenerate REG_INC notes that may have been moved
1255 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1261 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1262 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1264 if ((GET_CODE (PATTERN (insn
)) == USE
1265 /* We mark with QImode USEs introduced by reload itself. */
1266 && (GET_MODE (insn
) == QImode
1267 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1268 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1269 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1270 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1271 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1272 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1273 != stack_pointer_rtx
))
1274 && (!REG_P (XEXP (PATTERN (insn
), 0))
1275 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1281 /* Some CLOBBERs may survive until here and still reference unassigned
1282 pseudos with const equivalent, which may in turn cause ICE in later
1283 passes if the reference remains in place. */
1284 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1285 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1286 VOIDmode
, PATTERN (insn
));
1288 /* Discard obvious no-ops, even without -O. This optimization
1289 is fast and doesn't interfere with debugging. */
1290 if (NONJUMP_INSN_P (insn
)
1291 && GET_CODE (PATTERN (insn
)) == SET
1292 && REG_P (SET_SRC (PATTERN (insn
)))
1293 && REG_P (SET_DEST (PATTERN (insn
)))
1294 && (REGNO (SET_SRC (PATTERN (insn
)))
1295 == REGNO (SET_DEST (PATTERN (insn
)))))
1301 pnote
= ®_NOTES (insn
);
1304 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1305 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1306 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1307 *pnote
= XEXP (*pnote
, 1);
1309 pnote
= &XEXP (*pnote
, 1);
1313 add_auto_inc_notes (insn
, PATTERN (insn
));
1316 /* Simplify (subreg (reg)) if it appears as an operand. */
1317 cleanup_subreg_operands (insn
);
1319 /* Clean up invalid ASMs so that they don't confuse later passes.
1321 if (asm_noperands (PATTERN (insn
)) >= 0)
1323 extract_insn (insn
);
1324 if (!constrain_operands (1))
1326 error_for_asm (insn
,
1327 "%<asm%> operand has impossible constraints");
1334 /* If we are doing generic stack checking, give a warning if this
1335 function's frame size is larger than we expect. */
1336 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1338 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1339 static int verbose_warned
= 0;
1341 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1342 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1343 size
+= UNITS_PER_WORD
;
1345 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1347 warning (0, "frame size too large for reliable stack checking");
1348 if (! verbose_warned
)
1350 warning (0, "try reducing the number of local variables");
1356 /* Indicate that we no longer have known memory locations or constants. */
1357 if (reg_equiv_constant
)
1358 free (reg_equiv_constant
);
1359 if (reg_equiv_invariant
)
1360 free (reg_equiv_invariant
);
1361 reg_equiv_constant
= 0;
1362 reg_equiv_invariant
= 0;
1363 VEC_free (rtx
, gc
, reg_equiv_memory_loc_vec
);
1364 reg_equiv_memory_loc
= 0;
1366 free (temp_pseudo_reg_arr
);
1368 if (offsets_known_at
)
1369 free (offsets_known_at
);
1373 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1374 if (reg_equiv_alt_mem_list
[i
])
1375 free_EXPR_LIST_list (®_equiv_alt_mem_list
[i
]);
1376 free (reg_equiv_alt_mem_list
);
1378 free (reg_equiv_mem
);
1380 free (reg_equiv_address
);
1381 free (reg_max_ref_width
);
1382 free (reg_old_renumber
);
1383 free (pseudo_previous_regs
);
1384 free (pseudo_forbidden_regs
);
1386 CLEAR_HARD_REG_SET (used_spill_regs
);
1387 for (i
= 0; i
< n_spills
; i
++)
1388 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1390 /* Free all the insn_chain structures at once. */
1391 obstack_free (&reload_obstack
, reload_startobj
);
1392 unused_insn_chains
= 0;
1393 fixup_abnormal_edges ();
1395 /* Replacing pseudos with their memory equivalents might have
1396 created shared rtx. Subsequent passes would get confused
1397 by this, so unshare everything here. */
1398 unshare_all_rtl_again (first
);
1400 #ifdef STACK_BOUNDARY
1401 /* init_emit has set the alignment of the hard frame pointer
1402 to STACK_BOUNDARY. It is very likely no longer valid if
1403 the hard frame pointer was used for register allocation. */
1404 if (!frame_pointer_needed
)
1405 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1411 /* Yet another special case. Unfortunately, reg-stack forces people to
1412 write incorrect clobbers in asm statements. These clobbers must not
1413 cause the register to appear in bad_spill_regs, otherwise we'll call
1414 fatal_insn later. We clear the corresponding regnos in the live
1415 register sets to avoid this.
1416 The whole thing is rather sick, I'm afraid. */
1419 maybe_fix_stack_asms (void)
1422 const char *constraints
[MAX_RECOG_OPERANDS
];
1423 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1424 struct insn_chain
*chain
;
1426 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1429 HARD_REG_SET clobbered
, allowed
;
1432 if (! INSN_P (chain
->insn
)
1433 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1435 pat
= PATTERN (chain
->insn
);
1436 if (GET_CODE (pat
) != PARALLEL
)
1439 CLEAR_HARD_REG_SET (clobbered
);
1440 CLEAR_HARD_REG_SET (allowed
);
1442 /* First, make a mask of all stack regs that are clobbered. */
1443 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1445 rtx t
= XVECEXP (pat
, 0, i
);
1446 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1447 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1450 /* Get the operand values and constraints out of the insn. */
1451 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1452 constraints
, operand_mode
, NULL
);
1454 /* For every operand, see what registers are allowed. */
1455 for (i
= 0; i
< noperands
; i
++)
1457 const char *p
= constraints
[i
];
1458 /* For every alternative, we compute the class of registers allowed
1459 for reloading in CLS, and merge its contents into the reg set
1461 int cls
= (int) NO_REGS
;
1467 if (c
== '\0' || c
== ',' || c
== '#')
1469 /* End of one alternative - mark the regs in the current
1470 class, and reset the class. */
1471 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1477 } while (c
!= '\0' && c
!= ',');
1485 case '=': case '+': case '*': case '%': case '?': case '!':
1486 case '0': case '1': case '2': case '3': case '4': case '<':
1487 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1488 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1489 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1490 case TARGET_MEM_CONSTRAINT
:
1494 cls
= (int) reg_class_subunion
[cls
]
1495 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1500 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1504 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1505 cls
= (int) reg_class_subunion
[cls
]
1506 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1508 cls
= (int) reg_class_subunion
[cls
]
1509 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1511 p
+= CONSTRAINT_LEN (c
, p
);
1514 /* Those of the registers which are clobbered, but allowed by the
1515 constraints, must be usable as reload registers. So clear them
1516 out of the life information. */
1517 AND_HARD_REG_SET (allowed
, clobbered
);
1518 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1519 if (TEST_HARD_REG_BIT (allowed
, i
))
1521 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1522 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1529 /* Copy the global variables n_reloads and rld into the corresponding elts
1532 copy_reloads (struct insn_chain
*chain
)
1534 chain
->n_reloads
= n_reloads
;
1535 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1536 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1537 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1540 /* Walk the chain of insns, and determine for each whether it needs reloads
1541 and/or eliminations. Build the corresponding insns_need_reload list, and
1542 set something_needs_elimination as appropriate. */
1544 calculate_needs_all_insns (int global
)
1546 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1547 struct insn_chain
*chain
, *next
= 0;
1549 something_needs_elimination
= 0;
1551 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1552 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1554 rtx insn
= chain
->insn
;
1558 /* Clear out the shortcuts. */
1559 chain
->n_reloads
= 0;
1560 chain
->need_elim
= 0;
1561 chain
->need_reload
= 0;
1562 chain
->need_operand_change
= 0;
1564 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1565 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1566 what effects this has on the known offsets at labels. */
1568 if (LABEL_P (insn
) || JUMP_P (insn
)
1569 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1570 set_label_offsets (insn
, insn
, 0);
1574 rtx old_body
= PATTERN (insn
);
1575 int old_code
= INSN_CODE (insn
);
1576 rtx old_notes
= REG_NOTES (insn
);
1577 int did_elimination
= 0;
1578 int operands_changed
= 0;
1579 rtx set
= single_set (insn
);
1581 /* Skip insns that only set an equivalence. */
1582 if (set
&& REG_P (SET_DEST (set
))
1583 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1584 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1585 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))]))
1586 && reg_equiv_init
[REGNO (SET_DEST (set
))])
1589 /* If needed, eliminate any eliminable registers. */
1590 if (num_eliminable
|| num_eliminable_invariants
)
1591 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1593 /* Analyze the instruction. */
1594 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1595 global
, spill_reg_order
);
1597 /* If a no-op set needs more than one reload, this is likely
1598 to be something that needs input address reloads. We
1599 can't get rid of this cleanly later, and it is of no use
1600 anyway, so discard it now.
1601 We only do this when expensive_optimizations is enabled,
1602 since this complements reload inheritance / output
1603 reload deletion, and it can make debugging harder. */
1604 if (flag_expensive_optimizations
&& n_reloads
> 1)
1606 rtx set
= single_set (insn
);
1609 ((SET_SRC (set
) == SET_DEST (set
)
1610 && REG_P (SET_SRC (set
))
1611 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1612 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1613 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1614 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1615 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))] != NULL
1616 && reg_equiv_memory_loc
[REGNO (SET_DEST (set
))] != NULL
1617 && rtx_equal_p (reg_equiv_memory_loc
1618 [REGNO (SET_SRC (set
))],
1619 reg_equiv_memory_loc
1620 [REGNO (SET_DEST (set
))]))))
1622 if (flag_ira
&& optimize
)
1623 /* Inform IRA about the insn deletion. */
1624 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1625 REGNO (SET_SRC (set
)));
1627 /* Delete it from the reload chain. */
1629 chain
->prev
->next
= next
;
1631 reload_insn_chain
= next
;
1633 next
->prev
= chain
->prev
;
1634 chain
->next
= unused_insn_chains
;
1635 unused_insn_chains
= chain
;
1640 update_eliminable_offsets ();
1642 /* Remember for later shortcuts which insns had any reloads or
1643 register eliminations. */
1644 chain
->need_elim
= did_elimination
;
1645 chain
->need_reload
= n_reloads
> 0;
1646 chain
->need_operand_change
= operands_changed
;
1648 /* Discard any register replacements done. */
1649 if (did_elimination
)
1651 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1652 PATTERN (insn
) = old_body
;
1653 INSN_CODE (insn
) = old_code
;
1654 REG_NOTES (insn
) = old_notes
;
1655 something_needs_elimination
= 1;
1658 something_needs_operands_changed
|= operands_changed
;
1662 copy_reloads (chain
);
1663 *pprev_reload
= chain
;
1664 pprev_reload
= &chain
->next_need_reload
;
1671 /* Comparison function for qsort to decide which of two reloads
1672 should be handled first. *P1 and *P2 are the reload numbers. */
1675 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1677 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1680 /* Consider required reloads before optional ones. */
1681 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1685 /* Count all solitary classes before non-solitary ones. */
1686 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1687 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1691 /* Aside from solitaires, consider all multi-reg groups first. */
1692 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1696 /* Consider reloads in order of increasing reg-class number. */
1697 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1701 /* If reloads are equally urgent, sort by reload number,
1702 so that the results of qsort leave nothing to chance. */
1706 /* The cost of spilling each hard reg. */
1707 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1709 /* When spilling multiple hard registers, we use SPILL_COST for the first
1710 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1711 only the first hard reg for a multi-reg pseudo. */
1712 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1714 /* Map of hard regno to pseudo regno currently occupying the hard
1716 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1718 /* Update the spill cost arrays, considering that pseudo REG is live. */
1721 count_pseudo (int reg
)
1723 int freq
= REG_FREQ (reg
);
1724 int r
= reg_renumber
[reg
];
1727 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1728 || REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1729 /* Ignore spilled pseudo-registers which can be here only if IRA
1731 || (flag_ira
&& optimize
&& r
< 0))
1734 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1736 gcc_assert (r
>= 0);
1738 spill_add_cost
[r
] += freq
;
1739 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1742 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1743 spill_cost
[r
+ nregs
] += freq
;
1747 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1748 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1751 order_regs_for_reload (struct insn_chain
*chain
)
1754 HARD_REG_SET used_by_pseudos
;
1755 HARD_REG_SET used_by_pseudos2
;
1756 reg_set_iterator rsi
;
1758 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1760 memset (spill_cost
, 0, sizeof spill_cost
);
1761 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1762 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1763 hard_regno_to_pseudo_regno
[i
] = -1;
1765 /* Count number of uses of each hard reg by pseudo regs allocated to it
1766 and then order them by decreasing use. First exclude hard registers
1767 that are live in or across this insn. */
1769 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1770 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1771 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1772 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1774 /* Now find out which pseudos are allocated to it, and update
1776 CLEAR_REG_SET (&pseudos_counted
);
1778 EXECUTE_IF_SET_IN_REG_SET
1779 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1783 EXECUTE_IF_SET_IN_REG_SET
1784 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1788 CLEAR_REG_SET (&pseudos_counted
);
1791 /* Vector of reload-numbers showing the order in which the reloads should
1793 static short reload_order
[MAX_RELOADS
];
1795 /* This is used to keep track of the spill regs used in one insn. */
1796 static HARD_REG_SET used_spill_regs_local
;
1798 /* We decided to spill hard register SPILLED, which has a size of
1799 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1800 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1801 update SPILL_COST/SPILL_ADD_COST. */
1804 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1806 int freq
= REG_FREQ (reg
);
1807 int r
= reg_renumber
[reg
];
1808 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1810 /* Ignore spilled pseudo-registers which can be here only if IRA is
1812 if ((flag_ira
&& optimize
&& r
< 0)
1813 || REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1814 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1817 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1819 spill_add_cost
[r
] -= freq
;
1822 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1823 spill_cost
[r
+ nregs
] -= freq
;
1827 /* Find reload register to use for reload number ORDER. */
1830 find_reg (struct insn_chain
*chain
, int order
)
1832 int rnum
= reload_order
[order
];
1833 struct reload
*rl
= rld
+ rnum
;
1834 int best_cost
= INT_MAX
;
1836 unsigned int i
, j
, n
;
1838 HARD_REG_SET not_usable
;
1839 HARD_REG_SET used_by_other_reload
;
1840 reg_set_iterator rsi
;
1841 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1842 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1844 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1845 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1846 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1848 CLEAR_HARD_REG_SET (used_by_other_reload
);
1849 for (k
= 0; k
< order
; k
++)
1851 int other
= reload_order
[k
];
1853 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1854 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1855 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1858 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1860 #ifdef REG_ALLOC_ORDER
1861 unsigned int regno
= reg_alloc_order
[i
];
1863 unsigned int regno
= i
;
1866 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1867 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1868 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1870 int this_cost
= spill_cost
[regno
];
1872 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1874 for (j
= 1; j
< this_nregs
; j
++)
1876 this_cost
+= spill_add_cost
[regno
+ j
];
1877 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1878 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1884 if (flag_ira
&& optimize
)
1886 /* Ask IRA to find a better pseudo-register for
1888 for (n
= j
= 0; j
< this_nregs
; j
++)
1890 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1894 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1895 regno_pseudo_regs
[n
++] = r
;
1897 regno_pseudo_regs
[n
++] = -1;
1899 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1900 best_regno_pseudo_regs
,
1907 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1908 if (regno_pseudo_regs
[j
] < 0)
1915 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1917 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1919 if (this_cost
< best_cost
1920 /* Among registers with equal cost, prefer caller-saved ones, or
1921 use REG_ALLOC_ORDER if it is defined. */
1922 || (this_cost
== best_cost
1923 #ifdef REG_ALLOC_ORDER
1924 && (inv_reg_alloc_order
[regno
]
1925 < inv_reg_alloc_order
[best_reg
])
1927 && call_used_regs
[regno
]
1928 && ! call_used_regs
[best_reg
]
1933 best_cost
= this_cost
;
1941 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1943 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1944 rl
->regno
= best_reg
;
1946 EXECUTE_IF_SET_IN_REG_SET
1947 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1949 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1952 EXECUTE_IF_SET_IN_REG_SET
1953 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1955 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1958 for (i
= 0; i
< rl
->nregs
; i
++)
1960 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1961 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1962 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1963 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1968 /* Find more reload regs to satisfy the remaining need of an insn, which
1970 Do it by ascending class number, since otherwise a reg
1971 might be spilled for a big class and might fail to count
1972 for a smaller class even though it belongs to that class. */
1975 find_reload_regs (struct insn_chain
*chain
)
1979 /* In order to be certain of getting the registers we need,
1980 we must sort the reloads into order of increasing register class.
1981 Then our grabbing of reload registers will parallel the process
1982 that provided the reload registers. */
1983 for (i
= 0; i
< chain
->n_reloads
; i
++)
1985 /* Show whether this reload already has a hard reg. */
1986 if (chain
->rld
[i
].reg_rtx
)
1988 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1989 chain
->rld
[i
].regno
= regno
;
1991 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1994 chain
->rld
[i
].regno
= -1;
1995 reload_order
[i
] = i
;
1998 n_reloads
= chain
->n_reloads
;
1999 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2001 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2004 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2006 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2008 /* Compute the order of preference for hard registers to spill. */
2010 order_regs_for_reload (chain
);
2012 for (i
= 0; i
< n_reloads
; i
++)
2014 int r
= reload_order
[i
];
2016 /* Ignore reloads that got marked inoperative. */
2017 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2018 && ! rld
[r
].optional
2019 && rld
[r
].regno
== -1)
2020 if (! find_reg (chain
, i
))
2023 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2024 spill_failure (chain
->insn
, rld
[r
].rclass
);
2030 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2031 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2033 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2037 select_reload_regs (void)
2039 struct insn_chain
*chain
;
2041 /* Try to satisfy the needs for each insn. */
2042 for (chain
= insns_need_reload
; chain
!= 0;
2043 chain
= chain
->next_need_reload
)
2044 find_reload_regs (chain
);
2047 /* Delete all insns that were inserted by emit_caller_save_insns during
2050 delete_caller_save_insns (void)
2052 struct insn_chain
*c
= reload_insn_chain
;
2056 while (c
!= 0 && c
->is_caller_save_insn
)
2058 struct insn_chain
*next
= c
->next
;
2061 if (c
== reload_insn_chain
)
2062 reload_insn_chain
= next
;
2066 next
->prev
= c
->prev
;
2068 c
->prev
->next
= next
;
2069 c
->next
= unused_insn_chains
;
2070 unused_insn_chains
= c
;
2078 /* Handle the failure to find a register to spill.
2079 INSN should be one of the insns which needed this particular spill reg. */
2082 spill_failure (rtx insn
, enum reg_class rclass
)
2084 if (asm_noperands (PATTERN (insn
)) >= 0)
2085 error_for_asm (insn
, "can't find a register in class %qs while "
2086 "reloading %<asm%>",
2087 reg_class_names
[rclass
]);
2090 error ("unable to find a register to spill in class %qs",
2091 reg_class_names
[rclass
]);
2095 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2096 debug_reload_to_stream (dump_file
);
2098 fatal_insn ("this is the insn:", insn
);
2102 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2103 data that is dead in INSN. */
2106 delete_dead_insn (rtx insn
)
2108 rtx prev
= prev_real_insn (insn
);
2111 /* If the previous insn sets a register that dies in our insn, delete it
2113 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2114 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2115 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2116 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2117 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2118 delete_dead_insn (prev
);
2120 SET_INSN_DELETED (insn
);
2123 /* Modify the home of pseudo-reg I.
2124 The new home is present in reg_renumber[I].
2126 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2127 or it may be -1, meaning there is none or it is not relevant.
2128 This is used so that all pseudos spilled from a given hard reg
2129 can share one stack slot. */
2132 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2134 /* When outputting an inline function, this can happen
2135 for a reg that isn't actually used. */
2136 if (regno_reg_rtx
[i
] == 0)
2139 /* If the reg got changed to a MEM at rtl-generation time,
2141 if (!REG_P (regno_reg_rtx
[i
]))
2144 /* Modify the reg-rtx to contain the new hard reg
2145 number or else to contain its pseudo reg number. */
2146 SET_REGNO (regno_reg_rtx
[i
],
2147 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2149 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2150 allocate a stack slot for it. */
2152 if (reg_renumber
[i
] < 0
2153 && REG_N_REFS (i
) > 0
2154 && reg_equiv_constant
[i
] == 0
2155 && (reg_equiv_invariant
[i
] == 0 || reg_equiv_init
[i
] == 0)
2156 && reg_equiv_memory_loc
[i
] == 0)
2159 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2160 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2161 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2162 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2163 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2165 bool shared_p
= false;
2167 if (flag_ira
&& optimize
)
2168 /* Mark the spill for IRA. */
2169 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2170 x
= (dont_share_p
|| ! flag_ira
|| ! optimize
2171 ? NULL_RTX
: ira_reuse_stack_slot (i
, inherent_size
, total_size
));
2174 /* Each pseudo reg has an inherent size which comes from its own mode,
2175 and a total size which provides room for paradoxical subregs
2176 which refer to the pseudo reg in wider modes.
2178 We can use a slot already allocated if it provides both
2179 enough inherent space and enough total space.
2180 Otherwise, we allocate a new slot, making sure that it has no less
2181 inherent space, and no less total space, then the previous slot. */
2182 else if (from_reg
== -1 || (! dont_share_p
&& flag_ira
&& optimize
))
2184 alias_set_type alias_set
= new_alias_set ();
2186 /* No known place to spill from => no slot to reuse. */
2187 x
= assign_stack_local (mode
, total_size
,
2188 min_align
> inherent_align
2189 || total_size
> inherent_size
? -1 : 0);
2190 if (BYTES_BIG_ENDIAN
)
2191 /* Cancel the big-endian correction done in assign_stack_local.
2192 Get the address of the beginning of the slot.
2193 This is so we can do a big-endian correction unconditionally
2195 adjust
= inherent_size
- total_size
;
2197 /* Nothing can alias this slot except this pseudo. */
2198 set_mem_alias_set (x
, alias_set
);
2199 dse_record_singleton_alias_set (alias_set
, mode
);
2201 if (! dont_share_p
&& flag_ira
&& optimize
)
2202 /* Inform IRA about allocation a new stack slot. */
2203 ira_mark_new_stack_slot (x
, i
, total_size
);
2206 /* Reuse a stack slot if possible. */
2207 else if (spill_stack_slot
[from_reg
] != 0
2208 && spill_stack_slot_width
[from_reg
] >= total_size
2209 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2211 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2212 x
= spill_stack_slot
[from_reg
];
2213 /* Allocate a bigger slot. */
2216 /* Compute maximum size needed, both for inherent size
2217 and for total size. */
2220 if (spill_stack_slot
[from_reg
])
2222 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2224 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2225 if (spill_stack_slot_width
[from_reg
] > total_size
)
2226 total_size
= spill_stack_slot_width
[from_reg
];
2227 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2228 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2231 /* Make a slot with that size. */
2232 x
= assign_stack_local (mode
, total_size
,
2233 min_align
> inherent_align
2234 || total_size
> inherent_size
? -1 : 0);
2237 /* All pseudos mapped to this slot can alias each other. */
2238 if (spill_stack_slot
[from_reg
])
2240 alias_set_type alias_set
2241 = MEM_ALIAS_SET (spill_stack_slot
[from_reg
]);
2242 set_mem_alias_set (x
, alias_set
);
2243 dse_invalidate_singleton_alias_set (alias_set
);
2247 alias_set_type alias_set
= new_alias_set ();
2248 set_mem_alias_set (x
, alias_set
);
2249 dse_record_singleton_alias_set (alias_set
, mode
);
2252 if (BYTES_BIG_ENDIAN
)
2254 /* Cancel the big-endian correction done in assign_stack_local.
2255 Get the address of the beginning of the slot.
2256 This is so we can do a big-endian correction unconditionally
2258 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2261 = adjust_address_nv (x
, mode_for_size (total_size
2267 spill_stack_slot
[from_reg
] = stack_slot
;
2268 spill_stack_slot_width
[from_reg
] = total_size
;
2271 /* On a big endian machine, the "address" of the slot
2272 is the address of the low part that fits its inherent mode. */
2273 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2274 adjust
+= (total_size
- inherent_size
);
2276 /* If we have any adjustment to make, or if the stack slot is the
2277 wrong mode, make a new stack slot. */
2278 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2280 /* If we have a decl for the original register, set it for the
2281 memory. If this is a shared MEM, make a copy. */
2285 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2287 else if (REG_EXPR (regno_reg_rtx
[i
])
2288 && DECL_P (REG_EXPR (regno_reg_rtx
[i
])))
2290 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2292 /* We can do this only for the DECLs home pseudo, not for
2293 any copies of it, since otherwise when the stack slot
2294 is reused, nonoverlapping_memrefs_p might think they
2296 if (decl
&& REG_P (decl
) && REGNO (decl
) == (unsigned) i
)
2298 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2301 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2305 /* Save the stack slot for later. */
2306 reg_equiv_memory_loc
[i
] = x
;
2310 /* Mark the slots in regs_ever_live for the hard regs used by
2311 pseudo-reg number REGNO, accessed in MODE. */
2314 mark_home_live_1 (int regno
, enum machine_mode mode
)
2318 i
= reg_renumber
[regno
];
2321 lim
= end_hard_regno (mode
, i
);
2323 df_set_regs_ever_live(i
++, true);
2326 /* Mark the slots in regs_ever_live for the hard regs
2327 used by pseudo-reg number REGNO. */
2330 mark_home_live (int regno
)
2332 if (reg_renumber
[regno
] >= 0)
2333 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2336 /* This function handles the tracking of elimination offsets around branches.
2338 X is a piece of RTL being scanned.
2340 INSN is the insn that it came from, if any.
2342 INITIAL_P is nonzero if we are to set the offset to be the initial
2343 offset and zero if we are setting the offset of the label to be the
2347 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2349 enum rtx_code code
= GET_CODE (x
);
2352 struct elim_table
*p
;
2357 if (LABEL_REF_NONLOCAL_P (x
))
2362 /* ... fall through ... */
2365 /* If we know nothing about this label, set the desired offsets. Note
2366 that this sets the offset at a label to be the offset before a label
2367 if we don't know anything about the label. This is not correct for
2368 the label after a BARRIER, but is the best guess we can make. If
2369 we guessed wrong, we will suppress an elimination that might have
2370 been possible had we been able to guess correctly. */
2372 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2374 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2375 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2376 = (initial_p
? reg_eliminate
[i
].initial_offset
2377 : reg_eliminate
[i
].offset
);
2378 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2381 /* Otherwise, if this is the definition of a label and it is
2382 preceded by a BARRIER, set our offsets to the known offset of
2386 && (tem
= prev_nonnote_insn (insn
)) != 0
2388 set_offsets_for_label (insn
);
2390 /* If neither of the above cases is true, compare each offset
2391 with those previously recorded and suppress any eliminations
2392 where the offsets disagree. */
2394 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2395 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2396 != (initial_p
? reg_eliminate
[i
].initial_offset
2397 : reg_eliminate
[i
].offset
))
2398 reg_eliminate
[i
].can_eliminate
= 0;
2403 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2405 /* ... fall through ... */
2409 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2410 to indirectly and hence must have all eliminations at their
2412 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2413 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2414 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2420 /* Each of the labels in the parallel or address vector must be
2421 at their initial offsets. We want the first field for PARALLEL
2422 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2424 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2425 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2430 /* We only care about setting PC. If the source is not RETURN,
2431 IF_THEN_ELSE, or a label, disable any eliminations not at
2432 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2433 isn't one of those possibilities. For branches to a label,
2434 call ourselves recursively.
2436 Note that this can disable elimination unnecessarily when we have
2437 a non-local goto since it will look like a non-constant jump to
2438 someplace in the current function. This isn't a significant
2439 problem since such jumps will normally be when all elimination
2440 pairs are back to their initial offsets. */
2442 if (SET_DEST (x
) != pc_rtx
)
2445 switch (GET_CODE (SET_SRC (x
)))
2452 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2456 tem
= XEXP (SET_SRC (x
), 1);
2457 if (GET_CODE (tem
) == LABEL_REF
)
2458 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2459 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2462 tem
= XEXP (SET_SRC (x
), 2);
2463 if (GET_CODE (tem
) == LABEL_REF
)
2464 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2465 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2473 /* If we reach here, all eliminations must be at their initial
2474 offset because we are doing a jump to a variable address. */
2475 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2476 if (p
->offset
!= p
->initial_offset
)
2477 p
->can_eliminate
= 0;
2485 /* Scan X and replace any eliminable registers (such as fp) with a
2486 replacement (such as sp), plus an offset.
2488 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2489 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2490 MEM, we are allowed to replace a sum of a register and the constant zero
2491 with the register, which we cannot do outside a MEM. In addition, we need
2492 to record the fact that a register is referenced outside a MEM.
2494 If INSN is an insn, it is the insn containing X. If we replace a REG
2495 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2496 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2497 the REG is being modified.
2499 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2500 That's used when we eliminate in expressions stored in notes.
2501 This means, do not set ref_outside_mem even if the reference
2504 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2505 replacements done assuming all offsets are at their initial values. If
2506 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2507 encounter, return the actual location so that find_reloads will do
2508 the proper thing. */
2511 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2512 bool may_use_invariant
)
2514 enum rtx_code code
= GET_CODE (x
);
2515 struct elim_table
*ep
;
2522 if (! current_function_decl
)
2545 /* First handle the case where we encounter a bare register that
2546 is eliminable. Replace it with a PLUS. */
2547 if (regno
< FIRST_PSEUDO_REGISTER
)
2549 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2551 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2552 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2555 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2556 && reg_equiv_invariant
&& reg_equiv_invariant
[regno
])
2558 if (may_use_invariant
)
2559 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant
[regno
]),
2560 mem_mode
, insn
, true);
2561 /* There exists at least one use of REGNO that cannot be
2562 eliminated. Prevent the defining insn from being deleted. */
2563 reg_equiv_init
[regno
] = NULL_RTX
;
2564 alter_reg (regno
, -1, true);
2568 /* You might think handling MINUS in a manner similar to PLUS is a
2569 good idea. It is not. It has been tried multiple times and every
2570 time the change has had to have been reverted.
2572 Other parts of reload know a PLUS is special (gen_reload for example)
2573 and require special code to handle code a reloaded PLUS operand.
2575 Also consider backends where the flags register is clobbered by a
2576 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2577 lea instruction comes to mind). If we try to reload a MINUS, we
2578 may kill the flags register that was holding a useful value.
2580 So, please before trying to handle MINUS, consider reload as a
2581 whole instead of this little section as well as the backend issues. */
2583 /* If this is the sum of an eliminable register and a constant, rework
2585 if (REG_P (XEXP (x
, 0))
2586 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2587 && CONSTANT_P (XEXP (x
, 1)))
2589 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2591 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2593 /* The only time we want to replace a PLUS with a REG (this
2594 occurs when the constant operand of the PLUS is the negative
2595 of the offset) is when we are inside a MEM. We won't want
2596 to do so at other times because that would change the
2597 structure of the insn in a way that reload can't handle.
2598 We special-case the commonest situation in
2599 eliminate_regs_in_insn, so just replace a PLUS with a
2600 PLUS here, unless inside a MEM. */
2601 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2602 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2605 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2606 plus_constant (XEXP (x
, 1),
2607 ep
->previous_offset
));
2610 /* If the register is not eliminable, we are done since the other
2611 operand is a constant. */
2615 /* If this is part of an address, we want to bring any constant to the
2616 outermost PLUS. We will do this by doing register replacement in
2617 our operands and seeing if a constant shows up in one of them.
2619 Note that there is no risk of modifying the structure of the insn,
2620 since we only get called for its operands, thus we are either
2621 modifying the address inside a MEM, or something like an address
2622 operand of a load-address insn. */
2625 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2626 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2628 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2630 /* If one side is a PLUS and the other side is a pseudo that
2631 didn't get a hard register but has a reg_equiv_constant,
2632 we must replace the constant here since it may no longer
2633 be in the position of any operand. */
2634 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2635 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2636 && reg_renumber
[REGNO (new1
)] < 0
2637 && reg_equiv_constant
!= 0
2638 && reg_equiv_constant
[REGNO (new1
)] != 0)
2639 new1
= reg_equiv_constant
[REGNO (new1
)];
2640 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2641 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2642 && reg_renumber
[REGNO (new0
)] < 0
2643 && reg_equiv_constant
[REGNO (new0
)] != 0)
2644 new0
= reg_equiv_constant
[REGNO (new0
)];
2646 new_rtx
= form_sum (new0
, new1
);
2648 /* As above, if we are not inside a MEM we do not want to
2649 turn a PLUS into something else. We might try to do so here
2650 for an addition of 0 if we aren't optimizing. */
2651 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2652 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2660 /* If this is the product of an eliminable register and a
2661 constant, apply the distribute law and move the constant out
2662 so that we have (plus (mult ..) ..). This is needed in order
2663 to keep load-address insns valid. This case is pathological.
2664 We ignore the possibility of overflow here. */
2665 if (REG_P (XEXP (x
, 0))
2666 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2667 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2668 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2670 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2673 /* Refs inside notes don't count for this purpose. */
2674 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2675 || GET_CODE (insn
) == INSN_LIST
)))
2676 ep
->ref_outside_mem
= 1;
2679 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2680 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2683 /* ... fall through ... */
2687 /* See comments before PLUS about handling MINUS. */
2689 case DIV
: case UDIV
:
2690 case MOD
: case UMOD
:
2691 case AND
: case IOR
: case XOR
:
2692 case ROTATERT
: case ROTATE
:
2693 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2695 case GE
: case GT
: case GEU
: case GTU
:
2696 case LE
: case LT
: case LEU
: case LTU
:
2698 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2699 rtx new1
= XEXP (x
, 1)
2700 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false) : 0;
2702 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2703 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2708 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2711 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2712 if (new_rtx
!= XEXP (x
, 0))
2714 /* If this is a REG_DEAD note, it is not valid anymore.
2715 Using the eliminated version could result in creating a
2716 REG_DEAD note for the stack or frame pointer. */
2717 if (GET_MODE (x
) == REG_DEAD
)
2719 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true)
2722 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2726 /* ... fall through ... */
2729 /* Now do eliminations in the rest of the chain. If this was
2730 an EXPR_LIST, this might result in allocating more memory than is
2731 strictly needed, but it simplifies the code. */
2734 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2735 if (new_rtx
!= XEXP (x
, 1))
2737 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2745 /* We do not support elimination of a register that is modified.
2746 elimination_effects has already make sure that this does not
2752 /* We do not support elimination of a register that is modified.
2753 elimination_effects has already make sure that this does not
2754 happen. The only remaining case we need to consider here is
2755 that the increment value may be an eliminable register. */
2756 if (GET_CODE (XEXP (x
, 1)) == PLUS
2757 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2759 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2762 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2763 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2764 gen_rtx_PLUS (GET_MODE (x
),
2765 XEXP (x
, 0), new_rtx
));
2769 case STRICT_LOW_PART
:
2771 case SIGN_EXTEND
: case ZERO_EXTEND
:
2772 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2773 case FLOAT
: case FIX
:
2774 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2783 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2784 if (new_rtx
!= XEXP (x
, 0))
2785 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2789 /* Similar to above processing, but preserve SUBREG_BYTE.
2790 Convert (subreg (mem)) to (mem) if not paradoxical.
2791 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2792 pseudo didn't get a hard reg, we must replace this with the
2793 eliminated version of the memory location because push_reload
2794 may do the replacement in certain circumstances. */
2795 if (REG_P (SUBREG_REG (x
))
2796 && (GET_MODE_SIZE (GET_MODE (x
))
2797 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2798 && reg_equiv_memory_loc
!= 0
2799 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2801 new_rtx
= SUBREG_REG (x
);
2804 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false);
2806 if (new_rtx
!= SUBREG_REG (x
))
2808 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2809 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2812 && ((x_size
< new_size
2813 #ifdef WORD_REGISTER_OPERATIONS
2814 /* On these machines, combine can create rtl of the form
2815 (set (subreg:m1 (reg:m2 R) 0) ...)
2816 where m1 < m2, and expects something interesting to
2817 happen to the entire word. Moreover, it will use the
2818 (reg:m2 R) later, expecting all bits to be preserved.
2819 So if the number of words is the same, preserve the
2820 subreg so that push_reload can see it. */
2821 && ! ((x_size
- 1) / UNITS_PER_WORD
2822 == (new_size
-1 ) / UNITS_PER_WORD
)
2825 || x_size
== new_size
)
2827 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2829 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2835 /* Our only special processing is to pass the mode of the MEM to our
2836 recursive call and copy the flags. While we are here, handle this
2837 case more efficiently. */
2839 replace_equiv_address_nv (x
,
2840 eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
),
2844 /* Handle insn_list USE that a call to a pure function may generate. */
2845 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), 0, insn
, false);
2846 if (new_rtx
!= XEXP (x
, 0))
2847 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2859 /* Process each of our operands recursively. If any have changed, make a
2861 fmt
= GET_RTX_FORMAT (code
);
2862 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2866 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false);
2867 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2869 x
= shallow_copy_rtx (x
);
2872 XEXP (x
, i
) = new_rtx
;
2874 else if (*fmt
== 'E')
2877 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2879 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false);
2880 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2882 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2886 x
= shallow_copy_rtx (x
);
2889 XVEC (x
, i
) = new_v
;
2892 XVECEXP (x
, i
, j
) = new_rtx
;
2901 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2903 return eliminate_regs_1 (x
, mem_mode
, insn
, false);
2906 /* Scan rtx X for modifications of elimination target registers. Update
2907 the table of eliminables to reflect the changed state. MEM_MODE is
2908 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2911 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2913 enum rtx_code code
= GET_CODE (x
);
2914 struct elim_table
*ep
;
2939 /* First handle the case where we encounter a bare register that
2940 is eliminable. Replace it with a PLUS. */
2941 if (regno
< FIRST_PSEUDO_REGISTER
)
2943 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2945 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2948 ep
->ref_outside_mem
= 1;
2953 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2954 && reg_equiv_constant
[regno
]
2955 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2956 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2965 /* If we modify the source of an elimination rule, disable it. */
2966 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2967 if (ep
->from_rtx
== XEXP (x
, 0))
2968 ep
->can_eliminate
= 0;
2970 /* If we modify the target of an elimination rule by adding a constant,
2971 update its offset. If we modify the target in any other way, we'll
2972 have to disable the rule as well. */
2973 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2974 if (ep
->to_rtx
== XEXP (x
, 0))
2976 int size
= GET_MODE_SIZE (mem_mode
);
2978 /* If more bytes than MEM_MODE are pushed, account for them. */
2979 #ifdef PUSH_ROUNDING
2980 if (ep
->to_rtx
== stack_pointer_rtx
)
2981 size
= PUSH_ROUNDING (size
);
2983 if (code
== PRE_DEC
|| code
== POST_DEC
)
2985 else if (code
== PRE_INC
|| code
== POST_INC
)
2987 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2989 if (GET_CODE (XEXP (x
, 1)) == PLUS
2990 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2991 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
2992 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2994 ep
->can_eliminate
= 0;
2998 /* These two aren't unary operators. */
2999 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3002 /* Fall through to generic unary operation case. */
3003 case STRICT_LOW_PART
:
3005 case SIGN_EXTEND
: case ZERO_EXTEND
:
3006 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3007 case FLOAT
: case FIX
:
3008 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3017 elimination_effects (XEXP (x
, 0), mem_mode
);
3021 if (REG_P (SUBREG_REG (x
))
3022 && (GET_MODE_SIZE (GET_MODE (x
))
3023 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3024 && reg_equiv_memory_loc
!= 0
3025 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
3028 elimination_effects (SUBREG_REG (x
), mem_mode
);
3032 /* If using a register that is the source of an eliminate we still
3033 think can be performed, note it cannot be performed since we don't
3034 know how this register is used. */
3035 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3036 if (ep
->from_rtx
== XEXP (x
, 0))
3037 ep
->can_eliminate
= 0;
3039 elimination_effects (XEXP (x
, 0), mem_mode
);
3043 /* If clobbering a register that is the replacement register for an
3044 elimination we still think can be performed, note that it cannot
3045 be performed. Otherwise, we need not be concerned about it. */
3046 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3047 if (ep
->to_rtx
== XEXP (x
, 0))
3048 ep
->can_eliminate
= 0;
3050 elimination_effects (XEXP (x
, 0), mem_mode
);
3054 /* Check for setting a register that we know about. */
3055 if (REG_P (SET_DEST (x
)))
3057 /* See if this is setting the replacement register for an
3060 If DEST is the hard frame pointer, we do nothing because we
3061 assume that all assignments to the frame pointer are for
3062 non-local gotos and are being done at a time when they are valid
3063 and do not disturb anything else. Some machines want to
3064 eliminate a fake argument pointer (or even a fake frame pointer)
3065 with either the real frame or the stack pointer. Assignments to
3066 the hard frame pointer must not prevent this elimination. */
3068 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3070 if (ep
->to_rtx
== SET_DEST (x
)
3071 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3073 /* If it is being incremented, adjust the offset. Otherwise,
3074 this elimination can't be done. */
3075 rtx src
= SET_SRC (x
);
3077 if (GET_CODE (src
) == PLUS
3078 && XEXP (src
, 0) == SET_DEST (x
)
3079 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
3080 ep
->offset
-= INTVAL (XEXP (src
, 1));
3082 ep
->can_eliminate
= 0;
3086 elimination_effects (SET_DEST (x
), 0);
3087 elimination_effects (SET_SRC (x
), 0);
3091 /* Our only special processing is to pass the mode of the MEM to our
3093 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3100 fmt
= GET_RTX_FORMAT (code
);
3101 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3104 elimination_effects (XEXP (x
, i
), mem_mode
);
3105 else if (*fmt
== 'E')
3106 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3107 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3111 /* Descend through rtx X and verify that no references to eliminable registers
3112 remain. If any do remain, mark the involved register as not
3116 check_eliminable_occurrences (rtx x
)
3125 code
= GET_CODE (x
);
3127 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3129 struct elim_table
*ep
;
3131 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3132 if (ep
->from_rtx
== x
)
3133 ep
->can_eliminate
= 0;
3137 fmt
= GET_RTX_FORMAT (code
);
3138 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3141 check_eliminable_occurrences (XEXP (x
, i
));
3142 else if (*fmt
== 'E')
3145 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3146 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3151 /* Scan INSN and eliminate all eliminable registers in it.
3153 If REPLACE is nonzero, do the replacement destructively. Also
3154 delete the insn as dead it if it is setting an eliminable register.
3156 If REPLACE is zero, do all our allocations in reload_obstack.
3158 If no eliminations were done and this insn doesn't require any elimination
3159 processing (these are not identical conditions: it might be updating sp,
3160 but not referencing fp; this needs to be seen during reload_as_needed so
3161 that the offset between fp and sp can be taken into consideration), zero
3162 is returned. Otherwise, 1 is returned. */
3165 eliminate_regs_in_insn (rtx insn
, int replace
)
3167 int icode
= recog_memoized (insn
);
3168 rtx old_body
= PATTERN (insn
);
3169 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3170 rtx old_set
= single_set (insn
);
3174 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3175 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3176 struct elim_table
*ep
;
3177 rtx plus_src
, plus_cst_src
;
3179 if (! insn_is_asm
&& icode
< 0)
3181 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3182 || GET_CODE (PATTERN (insn
)) == CLOBBER
3183 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3184 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3185 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3189 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3190 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3192 /* Check for setting an eliminable register. */
3193 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3194 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3196 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3197 /* If this is setting the frame pointer register to the
3198 hardware frame pointer register and this is an elimination
3199 that will be done (tested above), this insn is really
3200 adjusting the frame pointer downward to compensate for
3201 the adjustment done before a nonlocal goto. */
3202 if (ep
->from
== FRAME_POINTER_REGNUM
3203 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3205 rtx base
= SET_SRC (old_set
);
3206 rtx base_insn
= insn
;
3207 HOST_WIDE_INT offset
= 0;
3209 while (base
!= ep
->to_rtx
)
3211 rtx prev_insn
, prev_set
;
3213 if (GET_CODE (base
) == PLUS
3214 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
3216 offset
+= INTVAL (XEXP (base
, 1));
3217 base
= XEXP (base
, 0);
3219 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3220 && (prev_set
= single_set (prev_insn
)) != 0
3221 && rtx_equal_p (SET_DEST (prev_set
), base
))
3223 base
= SET_SRC (prev_set
);
3224 base_insn
= prev_insn
;
3230 if (base
== ep
->to_rtx
)
3233 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3235 new_body
= old_body
;
3238 new_body
= copy_insn (old_body
);
3239 if (REG_NOTES (insn
))
3240 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3242 PATTERN (insn
) = new_body
;
3243 old_set
= single_set (insn
);
3245 /* First see if this insn remains valid when we
3246 make the change. If not, keep the INSN_CODE
3247 the same and let reload fit it up. */
3248 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3249 validate_change (insn
, &SET_DEST (old_set
),
3251 if (! apply_change_group ())
3253 SET_SRC (old_set
) = src
;
3254 SET_DEST (old_set
) = ep
->to_rtx
;
3263 /* In this case this insn isn't serving a useful purpose. We
3264 will delete it in reload_as_needed once we know that this
3265 elimination is, in fact, being done.
3267 If REPLACE isn't set, we can't delete this insn, but needn't
3268 process it since it won't be used unless something changes. */
3271 delete_dead_insn (insn
);
3279 /* We allow one special case which happens to work on all machines we
3280 currently support: a single set with the source or a REG_EQUAL
3281 note being a PLUS of an eliminable register and a constant. */
3282 plus_src
= plus_cst_src
= 0;
3283 if (old_set
&& REG_P (SET_DEST (old_set
)))
3285 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3286 plus_src
= SET_SRC (old_set
);
3287 /* First see if the source is of the form (plus (...) CST). */
3289 && GET_CODE (XEXP (plus_src
, 1)) == CONST_INT
)
3290 plus_cst_src
= plus_src
;
3291 else if (REG_P (SET_SRC (old_set
))
3294 /* Otherwise, see if we have a REG_EQUAL note of the form
3295 (plus (...) CST). */
3297 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3299 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3300 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3301 && GET_CODE (XEXP (links
, 0)) == PLUS
3302 && GET_CODE (XEXP (XEXP (links
, 0), 1)) == CONST_INT
)
3304 plus_cst_src
= XEXP (links
, 0);
3310 /* Check that the first operand of the PLUS is a hard reg or
3311 the lowpart subreg of one. */
3314 rtx reg
= XEXP (plus_cst_src
, 0);
3315 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3316 reg
= SUBREG_REG (reg
);
3318 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3324 rtx reg
= XEXP (plus_cst_src
, 0);
3325 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3327 if (GET_CODE (reg
) == SUBREG
)
3328 reg
= SUBREG_REG (reg
);
3330 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3331 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3333 rtx to_rtx
= ep
->to_rtx
;
3334 offset
+= ep
->offset
;
3335 offset
= trunc_int_for_mode (offset
, GET_MODE (reg
));
3337 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3338 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3340 /* If we have a nonzero offset, and the source is already
3341 a simple REG, the following transformation would
3342 increase the cost of the insn by replacing a simple REG
3343 with (plus (reg sp) CST). So try only when we already
3344 had a PLUS before. */
3345 if (offset
== 0 || plus_src
)
3347 rtx new_src
= plus_constant (to_rtx
, offset
);
3349 new_body
= old_body
;
3352 new_body
= copy_insn (old_body
);
3353 if (REG_NOTES (insn
))
3354 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3356 PATTERN (insn
) = new_body
;
3357 old_set
= single_set (insn
);
3359 /* First see if this insn remains valid when we make the
3360 change. If not, try to replace the whole pattern with
3361 a simple set (this may help if the original insn was a
3362 PARALLEL that was only recognized as single_set due to
3363 REG_UNUSED notes). If this isn't valid either, keep
3364 the INSN_CODE the same and let reload fix it up. */
3365 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3367 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3368 SET_DEST (old_set
), new_src
);
3370 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3371 SET_SRC (old_set
) = new_src
;
3378 /* This can't have an effect on elimination offsets, so skip right
3384 /* Determine the effects of this insn on elimination offsets. */
3385 elimination_effects (old_body
, 0);
3387 /* Eliminate all eliminable registers occurring in operands that
3388 can be handled by reload. */
3389 extract_insn (insn
);
3390 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3392 orig_operand
[i
] = recog_data
.operand
[i
];
3393 substed_operand
[i
] = recog_data
.operand
[i
];
3395 /* For an asm statement, every operand is eliminable. */
3396 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3398 bool is_set_src
, in_plus
;
3400 /* Check for setting a register that we know about. */
3401 if (recog_data
.operand_type
[i
] != OP_IN
3402 && REG_P (orig_operand
[i
]))
3404 /* If we are assigning to a register that can be eliminated, it
3405 must be as part of a PARALLEL, since the code above handles
3406 single SETs. We must indicate that we can no longer
3407 eliminate this reg. */
3408 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3410 if (ep
->from_rtx
== orig_operand
[i
])
3411 ep
->can_eliminate
= 0;
3414 /* Companion to the above plus substitution, we can allow
3415 invariants as the source of a plain move. */
3417 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3421 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3422 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3426 = eliminate_regs_1 (recog_data
.operand
[i
], 0,
3427 replace
? insn
: NULL_RTX
,
3428 is_set_src
|| in_plus
);
3429 if (substed_operand
[i
] != orig_operand
[i
])
3431 /* Terminate the search in check_eliminable_occurrences at
3433 *recog_data
.operand_loc
[i
] = 0;
3435 /* If an output operand changed from a REG to a MEM and INSN is an
3436 insn, write a CLOBBER insn. */
3437 if (recog_data
.operand_type
[i
] != OP_IN
3438 && REG_P (orig_operand
[i
])
3439 && MEM_P (substed_operand
[i
])
3441 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3445 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3446 *recog_data
.dup_loc
[i
]
3447 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3449 /* If any eliminable remain, they aren't eliminable anymore. */
3450 check_eliminable_occurrences (old_body
);
3452 /* Substitute the operands; the new values are in the substed_operand
3454 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3455 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3456 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3457 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3459 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3460 re-recognize the insn. We do this in case we had a simple addition
3461 but now can do this as a load-address. This saves an insn in this
3463 If re-recognition fails, the old insn code number will still be used,
3464 and some register operands may have changed into PLUS expressions.
3465 These will be handled by find_reloads by loading them into a register
3470 /* If we aren't replacing things permanently and we changed something,
3471 make another copy to ensure that all the RTL is new. Otherwise
3472 things can go wrong if find_reload swaps commutative operands
3473 and one is inside RTL that has been copied while the other is not. */
3474 new_body
= old_body
;
3477 new_body
= copy_insn (old_body
);
3478 if (REG_NOTES (insn
))
3479 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3481 PATTERN (insn
) = new_body
;
3483 /* If we had a move insn but now we don't, rerecognize it. This will
3484 cause spurious re-recognition if the old move had a PARALLEL since
3485 the new one still will, but we can't call single_set without
3486 having put NEW_BODY into the insn and the re-recognition won't
3487 hurt in this rare case. */
3488 /* ??? Why this huge if statement - why don't we just rerecognize the
3492 && ((REG_P (SET_SRC (old_set
))
3493 && (GET_CODE (new_body
) != SET
3494 || !REG_P (SET_SRC (new_body
))))
3495 /* If this was a load from or store to memory, compare
3496 the MEM in recog_data.operand to the one in the insn.
3497 If they are not equal, then rerecognize the insn. */
3499 && ((MEM_P (SET_SRC (old_set
))
3500 && SET_SRC (old_set
) != recog_data
.operand
[1])
3501 || (MEM_P (SET_DEST (old_set
))
3502 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3503 /* If this was an add insn before, rerecognize. */
3504 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3506 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3508 INSN_CODE (insn
) = new_icode
;
3512 /* Restore the old body. If there were any changes to it, we made a copy
3513 of it while the changes were still in place, so we'll correctly return
3514 a modified insn below. */
3517 /* Restore the old body. */
3518 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3519 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3520 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3521 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3524 /* Update all elimination pairs to reflect the status after the current
3525 insn. The changes we make were determined by the earlier call to
3526 elimination_effects.
3528 We also detect cases where register elimination cannot be done,
3529 namely, if a register would be both changed and referenced outside a MEM
3530 in the resulting insn since such an insn is often undefined and, even if
3531 not, we cannot know what meaning will be given to it. Note that it is
3532 valid to have a register used in an address in an insn that changes it
3533 (presumably with a pre- or post-increment or decrement).
3535 If anything changes, return nonzero. */
3537 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3539 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3540 ep
->can_eliminate
= 0;
3542 ep
->ref_outside_mem
= 0;
3544 if (ep
->previous_offset
!= ep
->offset
)
3549 /* If we changed something, perform elimination in REG_NOTES. This is
3550 needed even when REPLACE is zero because a REG_DEAD note might refer
3551 to a register that we eliminate and could cause a different number
3552 of spill registers to be needed in the final reload pass than in
3554 if (val
&& REG_NOTES (insn
) != 0)
3556 = eliminate_regs_1 (REG_NOTES (insn
), 0, REG_NOTES (insn
), true);
3561 /* Loop through all elimination pairs.
3562 Recalculate the number not at initial offset.
3564 Compute the maximum offset (minimum offset if the stack does not
3565 grow downward) for each elimination pair. */
3568 update_eliminable_offsets (void)
3570 struct elim_table
*ep
;
3572 num_not_at_initial_offset
= 0;
3573 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3575 ep
->previous_offset
= ep
->offset
;
3576 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3577 num_not_at_initial_offset
++;
3581 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3582 replacement we currently believe is valid, mark it as not eliminable if X
3583 modifies DEST in any way other than by adding a constant integer to it.
3585 If DEST is the frame pointer, we do nothing because we assume that
3586 all assignments to the hard frame pointer are nonlocal gotos and are being
3587 done at a time when they are valid and do not disturb anything else.
3588 Some machines want to eliminate a fake argument pointer with either the
3589 frame or stack pointer. Assignments to the hard frame pointer must not
3590 prevent this elimination.
3592 Called via note_stores from reload before starting its passes to scan
3593 the insns of the function. */
3596 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3600 /* A SUBREG of a hard register here is just changing its mode. We should
3601 not see a SUBREG of an eliminable hard register, but check just in
3603 if (GET_CODE (dest
) == SUBREG
)
3604 dest
= SUBREG_REG (dest
);
3606 if (dest
== hard_frame_pointer_rtx
)
3609 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3610 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3611 && (GET_CODE (x
) != SET
3612 || GET_CODE (SET_SRC (x
)) != PLUS
3613 || XEXP (SET_SRC (x
), 0) != dest
3614 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3616 reg_eliminate
[i
].can_eliminate_previous
3617 = reg_eliminate
[i
].can_eliminate
= 0;
3622 /* Verify that the initial elimination offsets did not change since the
3623 last call to set_initial_elim_offsets. This is used to catch cases
3624 where something illegal happened during reload_as_needed that could
3625 cause incorrect code to be generated if we did not check for it. */
3628 verify_initial_elim_offsets (void)
3632 if (!num_eliminable
)
3635 #ifdef ELIMINABLE_REGS
3637 struct elim_table
*ep
;
3639 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3641 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3642 if (t
!= ep
->initial_offset
)
3647 INITIAL_FRAME_POINTER_OFFSET (t
);
3648 if (t
!= reg_eliminate
[0].initial_offset
)
3655 /* Reset all offsets on eliminable registers to their initial values. */
3658 set_initial_elim_offsets (void)
3660 struct elim_table
*ep
= reg_eliminate
;
3662 #ifdef ELIMINABLE_REGS
3663 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3665 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3666 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3669 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3670 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3673 num_not_at_initial_offset
= 0;
3676 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3679 set_initial_eh_label_offset (rtx label
)
3681 set_label_offsets (label
, NULL_RTX
, 1);
3684 /* Initialize the known label offsets.
3685 Set a known offset for each forced label to be at the initial offset
3686 of each elimination. We do this because we assume that all
3687 computed jumps occur from a location where each elimination is
3688 at its initial offset.
3689 For all other labels, show that we don't know the offsets. */
3692 set_initial_label_offsets (void)
3695 memset (offsets_known_at
, 0, num_labels
);
3697 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3699 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3701 for_each_eh_label (set_initial_eh_label_offset
);
3704 /* Set all elimination offsets to the known values for the code label given
3708 set_offsets_for_label (rtx insn
)
3711 int label_nr
= CODE_LABEL_NUMBER (insn
);
3712 struct elim_table
*ep
;
3714 num_not_at_initial_offset
= 0;
3715 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3717 ep
->offset
= ep
->previous_offset
3718 = offsets_at
[label_nr
- first_label_num
][i
];
3719 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3720 num_not_at_initial_offset
++;
3724 /* See if anything that happened changes which eliminations are valid.
3725 For example, on the SPARC, whether or not the frame pointer can
3726 be eliminated can depend on what registers have been used. We need
3727 not check some conditions again (such as flag_omit_frame_pointer)
3728 since they can't have changed. */
3731 update_eliminables (HARD_REG_SET
*pset
)
3733 int previous_frame_pointer_needed
= frame_pointer_needed
;
3734 struct elim_table
*ep
;
3736 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3737 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3738 #ifdef ELIMINABLE_REGS
3739 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3742 ep
->can_eliminate
= 0;
3744 /* Look for the case where we have discovered that we can't replace
3745 register A with register B and that means that we will now be
3746 trying to replace register A with register C. This means we can
3747 no longer replace register C with register B and we need to disable
3748 such an elimination, if it exists. This occurs often with A == ap,
3749 B == sp, and C == fp. */
3751 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3753 struct elim_table
*op
;
3756 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3758 /* Find the current elimination for ep->from, if there is a
3760 for (op
= reg_eliminate
;
3761 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3762 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3768 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3770 for (op
= reg_eliminate
;
3771 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3772 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3773 op
->can_eliminate
= 0;
3777 /* See if any registers that we thought we could eliminate the previous
3778 time are no longer eliminable. If so, something has changed and we
3779 must spill the register. Also, recompute the number of eliminable
3780 registers and see if the frame pointer is needed; it is if there is
3781 no elimination of the frame pointer that we can perform. */
3783 frame_pointer_needed
= 1;
3784 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3786 if (ep
->can_eliminate
3787 && ep
->from
== FRAME_POINTER_REGNUM
3788 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3789 && (! SUPPORTS_STACK_ALIGNMENT
3790 || ! crtl
->stack_realign_needed
))
3791 frame_pointer_needed
= 0;
3793 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3795 ep
->can_eliminate_previous
= 0;
3796 SET_HARD_REG_BIT (*pset
, ep
->from
);
3801 /* If we didn't need a frame pointer last time, but we do now, spill
3802 the hard frame pointer. */
3803 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3804 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3807 /* Return true if X is used as the target register of an elimination. */
3810 elimination_target_reg_p (rtx x
)
3812 struct elim_table
*ep
;
3814 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3815 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
3821 /* Initialize the table of registers to eliminate.
3822 Pre-condition: global flag frame_pointer_needed has been set before
3823 calling this function. */
3826 init_elim_table (void)
3828 struct elim_table
*ep
;
3829 #ifdef ELIMINABLE_REGS
3830 const struct elim_table_1
*ep1
;
3834 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
3838 #ifdef ELIMINABLE_REGS
3839 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3840 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3842 ep
->from
= ep1
->from
;
3844 ep
->can_eliminate
= ep
->can_eliminate_previous
3845 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3846 && ! (ep
->to
== STACK_POINTER_REGNUM
3847 && frame_pointer_needed
3848 && (! SUPPORTS_STACK_ALIGNMENT
3849 || ! stack_realign_fp
)));
3852 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3853 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3854 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3855 = ! frame_pointer_needed
;
3858 /* Count the number of eliminable registers and build the FROM and TO
3859 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3860 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3861 We depend on this. */
3862 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3864 num_eliminable
+= ep
->can_eliminate
;
3865 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3866 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3870 /* Kick all pseudos out of hard register REGNO.
3872 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3873 because we found we can't eliminate some register. In the case, no pseudos
3874 are allowed to be in the register, even if they are only in a block that
3875 doesn't require spill registers, unlike the case when we are spilling this
3876 hard reg to produce another spill register.
3878 Return nonzero if any pseudos needed to be kicked out. */
3881 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
3887 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3888 df_set_regs_ever_live (regno
, true);
3891 /* Spill every pseudo reg that was allocated to this reg
3892 or to something that overlaps this reg. */
3894 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3895 if (reg_renumber
[i
] >= 0
3896 && (unsigned int) reg_renumber
[i
] <= regno
3897 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
3898 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3901 /* After find_reload_regs has been run for all insn that need reloads,
3902 and/or spill_hard_regs was called, this function is used to actually
3903 spill pseudo registers and try to reallocate them. It also sets up the
3904 spill_regs array for use by choose_reload_regs. */
3907 finish_spills (int global
)
3909 struct insn_chain
*chain
;
3910 int something_changed
= 0;
3912 reg_set_iterator rsi
;
3914 /* Build the spill_regs array for the function. */
3915 /* If there are some registers still to eliminate and one of the spill regs
3916 wasn't ever used before, additional stack space may have to be
3917 allocated to store this register. Thus, we may have changed the offset
3918 between the stack and frame pointers, so mark that something has changed.
3920 One might think that we need only set VAL to 1 if this is a call-used
3921 register. However, the set of registers that must be saved by the
3922 prologue is not identical to the call-used set. For example, the
3923 register used by the call insn for the return PC is a call-used register,
3924 but must be saved by the prologue. */
3927 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3928 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3930 spill_reg_order
[i
] = n_spills
;
3931 spill_regs
[n_spills
++] = i
;
3932 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
3933 something_changed
= 1;
3934 df_set_regs_ever_live (i
, true);
3937 spill_reg_order
[i
] = -1;
3939 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3940 if (! flag_ira
|| ! optimize
|| reg_renumber
[i
] >= 0)
3942 /* Record the current hard register the pseudo is allocated to
3943 in pseudo_previous_regs so we avoid reallocating it to the
3944 same hard reg in a later pass. */
3945 gcc_assert (reg_renumber
[i
] >= 0);
3947 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3948 /* Mark it as no longer having a hard register home. */
3949 reg_renumber
[i
] = -1;
3950 if (flag_ira
&& optimize
)
3951 /* Inform IRA about the change. */
3952 ira_mark_allocation_change (i
);
3953 /* We will need to scan everything again. */
3954 something_changed
= 1;
3957 /* Retry global register allocation if possible. */
3960 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3961 /* For every insn that needs reloads, set the registers used as spill
3962 regs in pseudo_forbidden_regs for every pseudo live across the
3964 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3966 EXECUTE_IF_SET_IN_REG_SET
3967 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3969 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3970 chain
->used_spill_regs
);
3972 EXECUTE_IF_SET_IN_REG_SET
3973 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3975 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3976 chain
->used_spill_regs
);
3980 if (! flag_ira
|| ! optimize
)
3982 /* Retry allocating the spilled pseudos. For each reg,
3983 merge the various reg sets that indicate which hard regs
3984 can't be used, and call retry_global_alloc. We change
3985 spill_pseudos here to only contain pseudos that did not
3986 get a new hard register. */
3987 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3988 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3990 HARD_REG_SET forbidden
;
3992 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3993 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3994 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3995 retry_global_alloc (i
, forbidden
);
3996 if (reg_renumber
[i
] >= 0)
3997 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4002 /* Retry allocating the pseudos spilled in IRA and the
4003 reload. For each reg, merge the various reg sets that
4004 indicate which hard regs can't be used, and call
4005 ira_reassign_pseudos. */
4008 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4009 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4011 if (reg_renumber
[i
] < 0)
4012 temp_pseudo_reg_arr
[n
++] = i
;
4014 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4016 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4017 bad_spill_regs_global
,
4018 pseudo_forbidden_regs
, pseudo_previous_regs
,
4020 something_changed
= 1;
4024 /* Fix up the register information in the insn chain.
4025 This involves deleting those of the spilled pseudos which did not get
4026 a new hard register home from the live_{before,after} sets. */
4027 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4029 HARD_REG_SET used_by_pseudos
;
4030 HARD_REG_SET used_by_pseudos2
;
4032 if (! flag_ira
|| ! optimize
)
4034 /* Don't do it for IRA because IRA and the reload still can
4035 assign hard registers to the spilled pseudos on next
4036 reload iterations. */
4037 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4038 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4040 /* Mark any unallocated hard regs as available for spills. That
4041 makes inheritance work somewhat better. */
4042 if (chain
->need_reload
)
4044 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4045 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4046 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4048 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4049 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4050 /* Value of chain->used_spill_regs from previous iteration
4051 may be not included in the value calculated here because
4052 of possible removing caller-saves insns (see function
4053 delete_caller_save_insns. */
4054 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4055 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4059 CLEAR_REG_SET (&changed_allocation_pseudos
);
4060 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4061 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4063 int regno
= reg_renumber
[i
];
4064 if (reg_old_renumber
[i
] == regno
)
4067 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4069 alter_reg (i
, reg_old_renumber
[i
], false);
4070 reg_old_renumber
[i
] = regno
;
4074 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4076 fprintf (dump_file
, " Register %d now in %d.\n\n",
4077 i
, reg_renumber
[i
]);
4081 return something_changed
;
4084 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4087 scan_paradoxical_subregs (rtx x
)
4091 enum rtx_code code
= GET_CODE (x
);
4102 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
4110 if (REG_P (SUBREG_REG (x
))
4111 && (GET_MODE_SIZE (GET_MODE (x
))
4112 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4114 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4115 = GET_MODE_SIZE (GET_MODE (x
));
4116 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4124 fmt
= GET_RTX_FORMAT (code
);
4125 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4128 scan_paradoxical_subregs (XEXP (x
, i
));
4129 else if (fmt
[i
] == 'E')
4132 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4133 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4138 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4139 examine all of the reload insns between PREV and NEXT exclusive, and
4140 annotate all that may trap. */
4143 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4145 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4146 unsigned int trap_count
;
4152 if (may_trap_p (PATTERN (insn
)))
4156 remove_note (insn
, note
);
4160 for (i
= NEXT_INSN (prev
); i
!= next
; i
= NEXT_INSN (i
))
4161 if (INSN_P (i
) && i
!= insn
&& may_trap_p (PATTERN (i
)))
4164 add_reg_note (i
, REG_EH_REGION
, XEXP (note
, 0));
4168 /* Reload pseudo-registers into hard regs around each insn as needed.
4169 Additional register load insns are output before the insn that needs it
4170 and perhaps store insns after insns that modify the reloaded pseudo reg.
4172 reg_last_reload_reg and reg_reloaded_contents keep track of
4173 which registers are already available in reload registers.
4174 We update these for the reloads that we perform,
4175 as the insns are scanned. */
4178 reload_as_needed (int live_known
)
4180 struct insn_chain
*chain
;
4181 #if defined (AUTO_INC_DEC)
4186 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4187 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4188 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4189 INIT_REG_SET (®_has_output_reload
);
4190 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4191 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4193 set_initial_elim_offsets ();
4195 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4198 rtx insn
= chain
->insn
;
4199 rtx old_next
= NEXT_INSN (insn
);
4201 /* If we pass a label, copy the offsets from the label information
4202 into the current offsets of each elimination. */
4204 set_offsets_for_label (insn
);
4206 else if (INSN_P (insn
))
4208 regset_head regs_to_forget
;
4209 INIT_REG_SET (®s_to_forget
);
4210 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4212 /* If this is a USE and CLOBBER of a MEM, ensure that any
4213 references to eliminable registers have been removed. */
4215 if ((GET_CODE (PATTERN (insn
)) == USE
4216 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4217 && MEM_P (XEXP (PATTERN (insn
), 0)))
4218 XEXP (XEXP (PATTERN (insn
), 0), 0)
4219 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4220 GET_MODE (XEXP (PATTERN (insn
), 0)),
4223 /* If we need to do register elimination processing, do so.
4224 This might delete the insn, in which case we are done. */
4225 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4227 eliminate_regs_in_insn (insn
, 1);
4230 update_eliminable_offsets ();
4231 CLEAR_REG_SET (®s_to_forget
);
4236 /* If need_elim is nonzero but need_reload is zero, one might think
4237 that we could simply set n_reloads to 0. However, find_reloads
4238 could have done some manipulation of the insn (such as swapping
4239 commutative operands), and these manipulations are lost during
4240 the first pass for every insn that needs register elimination.
4241 So the actions of find_reloads must be redone here. */
4243 if (! chain
->need_elim
&& ! chain
->need_reload
4244 && ! chain
->need_operand_change
)
4246 /* First find the pseudo regs that must be reloaded for this insn.
4247 This info is returned in the tables reload_... (see reload.h).
4248 Also modify the body of INSN by substituting RELOAD
4249 rtx's for those pseudo regs. */
4252 CLEAR_REG_SET (®_has_output_reload
);
4253 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4255 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4261 rtx next
= NEXT_INSN (insn
);
4264 prev
= PREV_INSN (insn
);
4266 /* Now compute which reload regs to reload them into. Perhaps
4267 reusing reload regs from previous insns, or else output
4268 load insns to reload them. Maybe output store insns too.
4269 Record the choices of reload reg in reload_reg_rtx. */
4270 choose_reload_regs (chain
);
4272 /* Merge any reloads that we didn't combine for fear of
4273 increasing the number of spill registers needed but now
4274 discover can be safely merged. */
4275 if (SMALL_REGISTER_CLASSES
)
4276 merge_assigned_reloads (insn
);
4278 /* Generate the insns to reload operands into or out of
4279 their reload regs. */
4280 emit_reload_insns (chain
);
4282 /* Substitute the chosen reload regs from reload_reg_rtx
4283 into the insn's body (or perhaps into the bodies of other
4284 load and store insn that we just made for reloading
4285 and that we moved the structure into). */
4286 subst_reloads (insn
);
4288 /* Adjust the exception region notes for loads and stores. */
4289 if (flag_non_call_exceptions
&& !CALL_P (insn
))
4290 fixup_eh_region_note (insn
, prev
, next
);
4292 /* If this was an ASM, make sure that all the reload insns
4293 we have generated are valid. If not, give an error
4295 if (asm_noperands (PATTERN (insn
)) >= 0)
4296 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4297 if (p
!= insn
&& INSN_P (p
)
4298 && GET_CODE (PATTERN (p
)) != USE
4299 && (recog_memoized (p
) < 0
4300 || (extract_insn (p
), ! constrain_operands (1))))
4302 error_for_asm (insn
,
4303 "%<asm%> operand requires "
4304 "impossible reload");
4309 if (num_eliminable
&& chain
->need_elim
)
4310 update_eliminable_offsets ();
4312 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4313 is no longer validly lying around to save a future reload.
4314 Note that this does not detect pseudos that were reloaded
4315 for this insn in order to be stored in
4316 (obeying register constraints). That is correct; such reload
4317 registers ARE still valid. */
4318 forget_marked_reloads (®s_to_forget
);
4319 CLEAR_REG_SET (®s_to_forget
);
4321 /* There may have been CLOBBER insns placed after INSN. So scan
4322 between INSN and NEXT and use them to forget old reloads. */
4323 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4324 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4325 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4328 /* Likewise for regs altered by auto-increment in this insn.
4329 REG_INC notes have been changed by reloading:
4330 find_reloads_address_1 records substitutions for them,
4331 which have been performed by subst_reloads above. */
4332 for (i
= n_reloads
- 1; i
>= 0; i
--)
4334 rtx in_reg
= rld
[i
].in_reg
;
4337 enum rtx_code code
= GET_CODE (in_reg
);
4338 /* PRE_INC / PRE_DEC will have the reload register ending up
4339 with the same value as the stack slot, but that doesn't
4340 hold true for POST_INC / POST_DEC. Either we have to
4341 convert the memory access to a true POST_INC / POST_DEC,
4342 or we can't use the reload register for inheritance. */
4343 if ((code
== POST_INC
|| code
== POST_DEC
)
4344 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4345 REGNO (rld
[i
].reg_rtx
))
4346 /* Make sure it is the inc/dec pseudo, and not
4347 some other (e.g. output operand) pseudo. */
4348 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4349 == REGNO (XEXP (in_reg
, 0))))
4352 rtx reload_reg
= rld
[i
].reg_rtx
;
4353 enum machine_mode mode
= GET_MODE (reload_reg
);
4357 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4359 /* We really want to ignore REG_INC notes here, so
4360 use PATTERN (p) as argument to reg_set_p . */
4361 if (reg_set_p (reload_reg
, PATTERN (p
)))
4363 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4368 n
= validate_replace_rtx (reload_reg
,
4369 gen_rtx_fmt_e (code
,
4374 /* We must also verify that the constraints
4375 are met after the replacement. */
4378 n
= constrain_operands (1);
4382 /* If the constraints were not met, then
4383 undo the replacement. */
4386 validate_replace_rtx (gen_rtx_fmt_e (code
,
4398 add_reg_note (p
, REG_INC
, reload_reg
);
4399 /* Mark this as having an output reload so that the
4400 REG_INC processing code below won't invalidate
4401 the reload for inheritance. */
4402 SET_HARD_REG_BIT (reg_is_output_reload
,
4403 REGNO (reload_reg
));
4404 SET_REGNO_REG_SET (®_has_output_reload
,
4405 REGNO (XEXP (in_reg
, 0)));
4408 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4411 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4412 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4413 REGNO (rld
[i
].reg_rtx
))
4414 /* Make sure it is the inc/dec pseudo, and not
4415 some other (e.g. output operand) pseudo. */
4416 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4417 == REGNO (XEXP (in_reg
, 0))))
4419 SET_HARD_REG_BIT (reg_is_output_reload
,
4420 REGNO (rld
[i
].reg_rtx
));
4421 SET_REGNO_REG_SET (®_has_output_reload
,
4422 REGNO (XEXP (in_reg
, 0)));
4426 /* If a pseudo that got a hard register is auto-incremented,
4427 we must purge records of copying it into pseudos without
4429 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4430 if (REG_NOTE_KIND (x
) == REG_INC
)
4432 /* See if this pseudo reg was reloaded in this insn.
4433 If so, its last-reload info is still valid
4434 because it is based on this insn's reload. */
4435 for (i
= 0; i
< n_reloads
; i
++)
4436 if (rld
[i
].out
== XEXP (x
, 0))
4440 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4444 /* A reload reg's contents are unknown after a label. */
4446 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4448 /* Don't assume a reload reg is still good after a call insn
4449 if it is a call-used reg, or if it contains a value that will
4450 be partially clobbered by the call. */
4451 else if (CALL_P (insn
))
4453 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4454 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4459 free (reg_last_reload_reg
);
4460 CLEAR_REG_SET (®_has_output_reload
);
4463 /* Discard all record of any value reloaded from X,
4464 or reloaded in X from someplace else;
4465 unless X is an output reload reg of the current insn.
4467 X may be a hard reg (the reload reg)
4468 or it may be a pseudo reg that was reloaded from.
4470 When DATA is non-NULL just mark the registers in regset
4471 to be forgotten later. */
4474 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4479 regset regs
= (regset
) data
;
4481 /* note_stores does give us subregs of hard regs,
4482 subreg_regno_offset requires a hard reg. */
4483 while (GET_CODE (x
) == SUBREG
)
4485 /* We ignore the subreg offset when calculating the regno,
4486 because we are using the entire underlying hard register
4496 if (regno
>= FIRST_PSEUDO_REGISTER
)
4502 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4503 /* Storing into a spilled-reg invalidates its contents.
4504 This can happen if a block-local pseudo is allocated to that reg
4505 and it wasn't spilled because this block's total need is 0.
4506 Then some insn might have an optional reload and use this reg. */
4508 for (i
= 0; i
< nr
; i
++)
4509 /* But don't do this if the reg actually serves as an output
4510 reload reg in the current instruction. */
4512 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4514 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4515 spill_reg_store
[regno
+ i
] = 0;
4521 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4524 /* Since value of X has changed,
4525 forget any value previously copied from it. */
4528 /* But don't forget a copy if this is the output reload
4529 that establishes the copy's validity. */
4531 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4532 reg_last_reload_reg
[regno
+ nr
] = 0;
4536 /* Forget the reloads marked in regset by previous function. */
4538 forget_marked_reloads (regset regs
)
4541 reg_set_iterator rsi
;
4542 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4544 if (reg
< FIRST_PSEUDO_REGISTER
4545 /* But don't do this if the reg actually serves as an output
4546 reload reg in the current instruction. */
4548 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4550 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4551 spill_reg_store
[reg
] = 0;
4554 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4555 reg_last_reload_reg
[reg
] = 0;
4559 /* The following HARD_REG_SETs indicate when each hard register is
4560 used for a reload of various parts of the current insn. */
4562 /* If reg is unavailable for all reloads. */
4563 static HARD_REG_SET reload_reg_unavailable
;
4564 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4565 static HARD_REG_SET reload_reg_used
;
4566 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4567 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4568 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4569 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4570 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4571 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4572 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4573 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4574 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4575 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4576 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4577 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4578 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4579 static HARD_REG_SET reload_reg_used_in_op_addr
;
4580 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4581 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4582 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4583 static HARD_REG_SET reload_reg_used_in_insn
;
4584 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4585 static HARD_REG_SET reload_reg_used_in_other_addr
;
4587 /* If reg is in use as a reload reg for any sort of reload. */
4588 static HARD_REG_SET reload_reg_used_at_all
;
4590 /* If reg is use as an inherited reload. We just mark the first register
4592 static HARD_REG_SET reload_reg_used_for_inherit
;
4594 /* Records which hard regs are used in any way, either as explicit use or
4595 by being allocated to a pseudo during any point of the current insn. */
4596 static HARD_REG_SET reg_used_in_insn
;
4598 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4599 TYPE. MODE is used to indicate how many consecutive regs are
4603 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4604 enum machine_mode mode
)
4606 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4609 for (i
= regno
; i
< nregs
+ regno
; i
++)
4614 SET_HARD_REG_BIT (reload_reg_used
, i
);
4617 case RELOAD_FOR_INPUT_ADDRESS
:
4618 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4621 case RELOAD_FOR_INPADDR_ADDRESS
:
4622 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4625 case RELOAD_FOR_OUTPUT_ADDRESS
:
4626 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4629 case RELOAD_FOR_OUTADDR_ADDRESS
:
4630 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4633 case RELOAD_FOR_OPERAND_ADDRESS
:
4634 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4637 case RELOAD_FOR_OPADDR_ADDR
:
4638 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4641 case RELOAD_FOR_OTHER_ADDRESS
:
4642 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4645 case RELOAD_FOR_INPUT
:
4646 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4649 case RELOAD_FOR_OUTPUT
:
4650 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4653 case RELOAD_FOR_INSN
:
4654 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4658 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4662 /* Similarly, but show REGNO is no longer in use for a reload. */
4665 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
4666 enum reload_type type
, enum machine_mode mode
)
4668 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4669 unsigned int start_regno
, end_regno
, r
;
4671 /* A complication is that for some reload types, inheritance might
4672 allow multiple reloads of the same types to share a reload register.
4673 We set check_opnum if we have to check only reloads with the same
4674 operand number, and check_any if we have to check all reloads. */
4675 int check_opnum
= 0;
4677 HARD_REG_SET
*used_in_set
;
4682 used_in_set
= &reload_reg_used
;
4685 case RELOAD_FOR_INPUT_ADDRESS
:
4686 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4689 case RELOAD_FOR_INPADDR_ADDRESS
:
4691 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4694 case RELOAD_FOR_OUTPUT_ADDRESS
:
4695 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4698 case RELOAD_FOR_OUTADDR_ADDRESS
:
4700 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4703 case RELOAD_FOR_OPERAND_ADDRESS
:
4704 used_in_set
= &reload_reg_used_in_op_addr
;
4707 case RELOAD_FOR_OPADDR_ADDR
:
4709 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4712 case RELOAD_FOR_OTHER_ADDRESS
:
4713 used_in_set
= &reload_reg_used_in_other_addr
;
4717 case RELOAD_FOR_INPUT
:
4718 used_in_set
= &reload_reg_used_in_input
[opnum
];
4721 case RELOAD_FOR_OUTPUT
:
4722 used_in_set
= &reload_reg_used_in_output
[opnum
];
4725 case RELOAD_FOR_INSN
:
4726 used_in_set
= &reload_reg_used_in_insn
;
4731 /* We resolve conflicts with remaining reloads of the same type by
4732 excluding the intervals of reload registers by them from the
4733 interval of freed reload registers. Since we only keep track of
4734 one set of interval bounds, we might have to exclude somewhat
4735 more than what would be necessary if we used a HARD_REG_SET here.
4736 But this should only happen very infrequently, so there should
4737 be no reason to worry about it. */
4739 start_regno
= regno
;
4740 end_regno
= regno
+ nregs
;
4741 if (check_opnum
|| check_any
)
4743 for (i
= n_reloads
- 1; i
>= 0; i
--)
4745 if (rld
[i
].when_needed
== type
4746 && (check_any
|| rld
[i
].opnum
== opnum
)
4749 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4750 unsigned int conflict_end
4751 = end_hard_regno (rld
[i
].mode
, conflict_start
);
4753 /* If there is an overlap with the first to-be-freed register,
4754 adjust the interval start. */
4755 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4756 start_regno
= conflict_end
;
4757 /* Otherwise, if there is a conflict with one of the other
4758 to-be-freed registers, adjust the interval end. */
4759 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4760 end_regno
= conflict_start
;
4765 for (r
= start_regno
; r
< end_regno
; r
++)
4766 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4769 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4770 specified by OPNUM and TYPE. */
4773 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
4777 /* In use for a RELOAD_OTHER means it's not available for anything. */
4778 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4779 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4785 /* In use for anything means we can't use it for RELOAD_OTHER. */
4786 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4787 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4788 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4789 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4792 for (i
= 0; i
< reload_n_operands
; i
++)
4793 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4794 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4795 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4796 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4797 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4798 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4803 case RELOAD_FOR_INPUT
:
4804 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4805 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4808 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4811 /* If it is used for some other input, can't use it. */
4812 for (i
= 0; i
< reload_n_operands
; i
++)
4813 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4816 /* If it is used in a later operand's address, can't use it. */
4817 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4818 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4819 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4824 case RELOAD_FOR_INPUT_ADDRESS
:
4825 /* Can't use a register if it is used for an input address for this
4826 operand or used as an input in an earlier one. */
4827 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4828 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4831 for (i
= 0; i
< opnum
; i
++)
4832 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4837 case RELOAD_FOR_INPADDR_ADDRESS
:
4838 /* Can't use a register if it is used for an input address
4839 for this operand or used as an input in an earlier
4841 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4844 for (i
= 0; i
< opnum
; i
++)
4845 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4850 case RELOAD_FOR_OUTPUT_ADDRESS
:
4851 /* Can't use a register if it is used for an output address for this
4852 operand or used as an output in this or a later operand. Note
4853 that multiple output operands are emitted in reverse order, so
4854 the conflicting ones are those with lower indices. */
4855 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4858 for (i
= 0; i
<= opnum
; i
++)
4859 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4864 case RELOAD_FOR_OUTADDR_ADDRESS
:
4865 /* Can't use a register if it is used for an output address
4866 for this operand or used as an output in this or a
4867 later operand. Note that multiple output operands are
4868 emitted in reverse order, so the conflicting ones are
4869 those with lower indices. */
4870 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4873 for (i
= 0; i
<= opnum
; i
++)
4874 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4879 case RELOAD_FOR_OPERAND_ADDRESS
:
4880 for (i
= 0; i
< reload_n_operands
; i
++)
4881 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4884 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4885 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4887 case RELOAD_FOR_OPADDR_ADDR
:
4888 for (i
= 0; i
< reload_n_operands
; i
++)
4889 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4892 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4894 case RELOAD_FOR_OUTPUT
:
4895 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4896 outputs, or an operand address for this or an earlier output.
4897 Note that multiple output operands are emitted in reverse order,
4898 so the conflicting ones are those with higher indices. */
4899 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4902 for (i
= 0; i
< reload_n_operands
; i
++)
4903 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4906 for (i
= opnum
; i
< reload_n_operands
; i
++)
4907 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4908 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4913 case RELOAD_FOR_INSN
:
4914 for (i
= 0; i
< reload_n_operands
; i
++)
4915 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4916 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4919 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4920 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4922 case RELOAD_FOR_OTHER_ADDRESS
:
4923 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4930 /* Return 1 if the value in reload reg REGNO, as used by a reload
4931 needed for the part of the insn specified by OPNUM and TYPE,
4932 is still available in REGNO at the end of the insn.
4934 We can assume that the reload reg was already tested for availability
4935 at the time it is needed, and we should not check this again,
4936 in case the reg has already been marked in use. */
4939 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
4946 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4947 its value must reach the end. */
4950 /* If this use is for part of the insn,
4951 its value reaches if no subsequent part uses the same register.
4952 Just like the above function, don't try to do this with lots
4955 case RELOAD_FOR_OTHER_ADDRESS
:
4956 /* Here we check for everything else, since these don't conflict
4957 with anything else and everything comes later. */
4959 for (i
= 0; i
< reload_n_operands
; i
++)
4960 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4961 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4962 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4963 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4964 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4965 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4968 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4969 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4970 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4971 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4973 case RELOAD_FOR_INPUT_ADDRESS
:
4974 case RELOAD_FOR_INPADDR_ADDRESS
:
4975 /* Similar, except that we check only for this and subsequent inputs
4976 and the address of only subsequent inputs and we do not need
4977 to check for RELOAD_OTHER objects since they are known not to
4980 for (i
= opnum
; i
< reload_n_operands
; i
++)
4981 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4984 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4985 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4986 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4989 for (i
= 0; i
< reload_n_operands
; i
++)
4990 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4991 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4992 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4995 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4998 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4999 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5000 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5002 case RELOAD_FOR_INPUT
:
5003 /* Similar to input address, except we start at the next operand for
5004 both input and input address and we do not check for
5005 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5008 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5009 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5010 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5011 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5014 /* ... fall through ... */
5016 case RELOAD_FOR_OPERAND_ADDRESS
:
5017 /* Check outputs and their addresses. */
5019 for (i
= 0; i
< reload_n_operands
; i
++)
5020 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5021 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5022 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5025 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5027 case RELOAD_FOR_OPADDR_ADDR
:
5028 for (i
= 0; i
< reload_n_operands
; i
++)
5029 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5030 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5031 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5034 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5035 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5036 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5038 case RELOAD_FOR_INSN
:
5039 /* These conflict with other outputs with RELOAD_OTHER. So
5040 we need only check for output addresses. */
5042 opnum
= reload_n_operands
;
5044 /* ... fall through ... */
5046 case RELOAD_FOR_OUTPUT
:
5047 case RELOAD_FOR_OUTPUT_ADDRESS
:
5048 case RELOAD_FOR_OUTADDR_ADDRESS
:
5049 /* We already know these can't conflict with a later output. So the
5050 only thing to check are later output addresses.
5051 Note that multiple output operands are emitted in reverse order,
5052 so the conflicting ones are those with lower indices. */
5053 for (i
= 0; i
< opnum
; i
++)
5054 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5055 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5065 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5066 every register in the range [REGNO, REGNO + NREGS). */
5069 reload_regs_reach_end_p (unsigned int regno
, int nregs
,
5070 int opnum
, enum reload_type type
)
5074 for (i
= 0; i
< nregs
; i
++)
5075 if (!reload_reg_reaches_end_p (regno
+ i
, opnum
, type
))
5081 /* Returns whether R1 and R2 are uniquely chained: the value of one
5082 is used by the other, and that value is not used by any other
5083 reload for this insn. This is used to partially undo the decision
5084 made in find_reloads when in the case of multiple
5085 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5086 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5087 reloads. This code tries to avoid the conflict created by that
5088 change. It might be cleaner to explicitly keep track of which
5089 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5090 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5091 this after the fact. */
5093 reloads_unique_chain_p (int r1
, int r2
)
5097 /* We only check input reloads. */
5098 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5101 /* Avoid anything with output reloads. */
5102 if (rld
[r1
].out
|| rld
[r2
].out
)
5105 /* "chained" means one reload is a component of the other reload,
5106 not the same as the other reload. */
5107 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5108 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5109 || rld
[r1
].optional
|| rld
[r2
].optional
5110 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5111 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5114 for (i
= 0; i
< n_reloads
; i
++)
5115 /* Look for input reloads that aren't our two */
5116 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5118 /* If our reload is mentioned at all, it isn't a simple chain. */
5119 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5126 /* The recursive function change all occurrences of WHAT in *WHERE
5129 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5138 if (*where
== what
|| rtx_equal_p (*where
, what
))
5144 code
= GET_CODE (*where
);
5145 fmt
= GET_RTX_FORMAT (code
);
5146 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5152 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5153 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5155 else if (fmt
[i
] == 'e')
5156 substitute (&XEXP (*where
, i
), what
, repl
);
5160 /* The function returns TRUE if chain of reload R1 and R2 (in any
5161 order) can be evaluated without usage of intermediate register for
5162 the reload containing another reload. It is important to see
5163 gen_reload to understand what the function is trying to do. As an
5164 example, let us have reload chain
5167 r1: <something> + const
5169 and reload R2 got reload reg HR. The function returns true if
5170 there is a correct insn HR = HR + <something>. Otherwise,
5171 gen_reload will use intermediate register (and this is the reload
5172 reg for R1) to reload <something>.
5174 We need this function to find a conflict for chain reloads. In our
5175 example, if HR = HR + <something> is incorrect insn, then we cannot
5176 use HR as a reload register for R2. If we do use it then we get a
5185 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5189 rtx out
, in
, tem
, insn
;
5190 rtx last
= get_last_insn ();
5192 /* Make r2 a component of r1. */
5193 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5199 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5200 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5201 gcc_assert (regno
>= 0);
5202 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5203 in
= copy_rtx (rld
[r1
].in
);
5204 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5206 /* If IN is a paradoxical SUBREG, remove it and try to put the
5207 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5208 if (GET_CODE (in
) == SUBREG
5209 && (GET_MODE_SIZE (GET_MODE (in
))
5210 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
5211 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
5212 in
= SUBREG_REG (in
), out
= tem
;
5214 if (GET_CODE (in
) == PLUS
5215 && (REG_P (XEXP (in
, 0))
5216 || GET_CODE (XEXP (in
, 0)) == SUBREG
5217 || MEM_P (XEXP (in
, 0)))
5218 && (REG_P (XEXP (in
, 1))
5219 || GET_CODE (XEXP (in
, 1)) == SUBREG
5220 || CONSTANT_P (XEXP (in
, 1))
5221 || MEM_P (XEXP (in
, 1))))
5223 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5224 code
= recog_memoized (insn
);
5229 extract_insn (insn
);
5230 /* We want constrain operands to treat this insn strictly in
5231 its validity determination, i.e., the way it would after
5232 reload has completed. */
5233 result
= constrain_operands (1);
5236 delete_insns_since (last
);
5240 /* It looks like other cases in gen_reload are not possible for
5241 chain reloads or do need an intermediate hard registers. */
5245 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5248 This function uses the same algorithm as reload_reg_free_p above. */
5251 reloads_conflict (int r1
, int r2
)
5253 enum reload_type r1_type
= rld
[r1
].when_needed
;
5254 enum reload_type r2_type
= rld
[r2
].when_needed
;
5255 int r1_opnum
= rld
[r1
].opnum
;
5256 int r2_opnum
= rld
[r2
].opnum
;
5258 /* RELOAD_OTHER conflicts with everything. */
5259 if (r2_type
== RELOAD_OTHER
)
5262 /* Otherwise, check conflicts differently for each type. */
5266 case RELOAD_FOR_INPUT
:
5267 return (r2_type
== RELOAD_FOR_INSN
5268 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5269 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5270 || r2_type
== RELOAD_FOR_INPUT
5271 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5272 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5273 && r2_opnum
> r1_opnum
));
5275 case RELOAD_FOR_INPUT_ADDRESS
:
5276 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5277 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5279 case RELOAD_FOR_INPADDR_ADDRESS
:
5280 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5281 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5283 case RELOAD_FOR_OUTPUT_ADDRESS
:
5284 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5285 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5287 case RELOAD_FOR_OUTADDR_ADDRESS
:
5288 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5289 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5291 case RELOAD_FOR_OPERAND_ADDRESS
:
5292 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5293 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5294 && (!reloads_unique_chain_p (r1
, r2
)
5295 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5297 case RELOAD_FOR_OPADDR_ADDR
:
5298 return (r2_type
== RELOAD_FOR_INPUT
5299 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5301 case RELOAD_FOR_OUTPUT
:
5302 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5303 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5304 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5305 && r2_opnum
>= r1_opnum
));
5307 case RELOAD_FOR_INSN
:
5308 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5309 || r2_type
== RELOAD_FOR_INSN
5310 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5312 case RELOAD_FOR_OTHER_ADDRESS
:
5313 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5323 /* Indexed by reload number, 1 if incoming value
5324 inherited from previous insns. */
5325 static char reload_inherited
[MAX_RELOADS
];
5327 /* For an inherited reload, this is the insn the reload was inherited from,
5328 if we know it. Otherwise, this is 0. */
5329 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5331 /* If nonzero, this is a place to get the value of the reload,
5332 rather than using reload_in. */
5333 static rtx reload_override_in
[MAX_RELOADS
];
5335 /* For each reload, the hard register number of the register used,
5336 or -1 if we did not need a register for this reload. */
5337 static int reload_spill_index
[MAX_RELOADS
];
5339 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5340 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5342 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5343 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5345 /* Subroutine of free_for_value_p, used to check a single register.
5346 START_REGNO is the starting regno of the full reload register
5347 (possibly comprising multiple hard registers) that we are considering. */
5350 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5351 enum reload_type type
, rtx value
, rtx out
,
5352 int reloadnum
, int ignore_address_reloads
)
5355 /* Set if we see an input reload that must not share its reload register
5356 with any new earlyclobber, but might otherwise share the reload
5357 register with an output or input-output reload. */
5358 int check_earlyclobber
= 0;
5362 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5365 if (out
== const0_rtx
)
5371 /* We use some pseudo 'time' value to check if the lifetimes of the
5372 new register use would overlap with the one of a previous reload
5373 that is not read-only or uses a different value.
5374 The 'time' used doesn't have to be linear in any shape or form, just
5376 Some reload types use different 'buckets' for each operand.
5377 So there are MAX_RECOG_OPERANDS different time values for each
5379 We compute TIME1 as the time when the register for the prospective
5380 new reload ceases to be live, and TIME2 for each existing
5381 reload as the time when that the reload register of that reload
5383 Where there is little to be gained by exact lifetime calculations,
5384 we just make conservative assumptions, i.e. a longer lifetime;
5385 this is done in the 'default:' cases. */
5388 case RELOAD_FOR_OTHER_ADDRESS
:
5389 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5390 time1
= copy
? 0 : 1;
5393 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5395 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5396 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5397 respectively, to the time values for these, we get distinct time
5398 values. To get distinct time values for each operand, we have to
5399 multiply opnum by at least three. We round that up to four because
5400 multiply by four is often cheaper. */
5401 case RELOAD_FOR_INPADDR_ADDRESS
:
5402 time1
= opnum
* 4 + 2;
5404 case RELOAD_FOR_INPUT_ADDRESS
:
5405 time1
= opnum
* 4 + 3;
5407 case RELOAD_FOR_INPUT
:
5408 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5409 executes (inclusive). */
5410 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5412 case RELOAD_FOR_OPADDR_ADDR
:
5414 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5415 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5417 case RELOAD_FOR_OPERAND_ADDRESS
:
5418 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5420 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5422 case RELOAD_FOR_OUTADDR_ADDRESS
:
5423 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5425 case RELOAD_FOR_OUTPUT_ADDRESS
:
5426 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5429 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5432 for (i
= 0; i
< n_reloads
; i
++)
5434 rtx reg
= rld
[i
].reg_rtx
;
5435 if (reg
&& REG_P (reg
)
5436 && ((unsigned) regno
- true_regnum (reg
)
5437 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5440 rtx other_input
= rld
[i
].in
;
5442 /* If the other reload loads the same input value, that
5443 will not cause a conflict only if it's loading it into
5444 the same register. */
5445 if (true_regnum (reg
) != start_regno
)
5446 other_input
= NULL_RTX
;
5447 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5448 || rld
[i
].out
|| out
)
5451 switch (rld
[i
].when_needed
)
5453 case RELOAD_FOR_OTHER_ADDRESS
:
5456 case RELOAD_FOR_INPADDR_ADDRESS
:
5457 /* find_reloads makes sure that a
5458 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5459 by at most one - the first -
5460 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5461 address reload is inherited, the address address reload
5462 goes away, so we can ignore this conflict. */
5463 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5464 && ignore_address_reloads
5465 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5466 Then the address address is still needed to store
5467 back the new address. */
5468 && ! rld
[reloadnum
].out
)
5470 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5471 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5473 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5474 && ignore_address_reloads
5475 /* Unless we are reloading an auto_inc expression. */
5476 && ! rld
[reloadnum
].out
)
5478 time2
= rld
[i
].opnum
* 4 + 2;
5480 case RELOAD_FOR_INPUT_ADDRESS
:
5481 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5482 && ignore_address_reloads
5483 && ! rld
[reloadnum
].out
)
5485 time2
= rld
[i
].opnum
* 4 + 3;
5487 case RELOAD_FOR_INPUT
:
5488 time2
= rld
[i
].opnum
* 4 + 4;
5489 check_earlyclobber
= 1;
5491 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5492 == MAX_RECOG_OPERAND * 4 */
5493 case RELOAD_FOR_OPADDR_ADDR
:
5494 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5495 && ignore_address_reloads
5496 && ! rld
[reloadnum
].out
)
5498 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5500 case RELOAD_FOR_OPERAND_ADDRESS
:
5501 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5502 check_earlyclobber
= 1;
5504 case RELOAD_FOR_INSN
:
5505 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5507 case RELOAD_FOR_OUTPUT
:
5508 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5509 instruction is executed. */
5510 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5512 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5513 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5515 case RELOAD_FOR_OUTADDR_ADDRESS
:
5516 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5517 && ignore_address_reloads
5518 && ! rld
[reloadnum
].out
)
5520 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5522 case RELOAD_FOR_OUTPUT_ADDRESS
:
5523 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5526 /* If there is no conflict in the input part, handle this
5527 like an output reload. */
5528 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5530 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5531 /* Earlyclobbered outputs must conflict with inputs. */
5532 if (earlyclobber_operand_p (rld
[i
].out
))
5533 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5538 /* RELOAD_OTHER might be live beyond instruction execution,
5539 but this is not obvious when we set time2 = 1. So check
5540 here if there might be a problem with the new reload
5541 clobbering the register used by the RELOAD_OTHER. */
5549 && (! rld
[i
].in
|| rld
[i
].out
5550 || ! rtx_equal_p (other_input
, value
)))
5551 || (out
&& rld
[reloadnum
].out_reg
5552 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5558 /* Earlyclobbered outputs must conflict with inputs. */
5559 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5565 /* Return 1 if the value in reload reg REGNO, as used by a reload
5566 needed for the part of the insn specified by OPNUM and TYPE,
5567 may be used to load VALUE into it.
5569 MODE is the mode in which the register is used, this is needed to
5570 determine how many hard regs to test.
5572 Other read-only reloads with the same value do not conflict
5573 unless OUT is nonzero and these other reloads have to live while
5574 output reloads live.
5575 If OUT is CONST0_RTX, this is a special case: it means that the
5576 test should not be for using register REGNO as reload register, but
5577 for copying from register REGNO into the reload register.
5579 RELOADNUM is the number of the reload we want to load this value for;
5580 a reload does not conflict with itself.
5582 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5583 reloads that load an address for the very reload we are considering.
5585 The caller has to make sure that there is no conflict with the return
5589 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
5590 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5591 int ignore_address_reloads
)
5593 int nregs
= hard_regno_nregs
[regno
][mode
];
5595 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5596 value
, out
, reloadnum
,
5597 ignore_address_reloads
))
5602 /* Return nonzero if the rtx X is invariant over the current function. */
5603 /* ??? Actually, the places where we use this expect exactly what is
5604 tested here, and not everything that is function invariant. In
5605 particular, the frame pointer and arg pointer are special cased;
5606 pic_offset_table_rtx is not, and we must not spill these things to
5610 function_invariant_p (const_rtx x
)
5614 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5616 if (GET_CODE (x
) == PLUS
5617 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5618 && CONSTANT_P (XEXP (x
, 1)))
5623 /* Determine whether the reload reg X overlaps any rtx'es used for
5624 overriding inheritance. Return nonzero if so. */
5627 conflicts_with_override (rtx x
)
5630 for (i
= 0; i
< n_reloads
; i
++)
5631 if (reload_override_in
[i
]
5632 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5637 /* Give an error message saying we failed to find a reload for INSN,
5638 and clear out reload R. */
5640 failed_reload (rtx insn
, int r
)
5642 if (asm_noperands (PATTERN (insn
)) < 0)
5643 /* It's the compiler's fault. */
5644 fatal_insn ("could not find a spill register", insn
);
5646 /* It's the user's fault; the operand's mode and constraint
5647 don't match. Disable this reload so we don't crash in final. */
5648 error_for_asm (insn
,
5649 "%<asm%> operand constraint incompatible with operand size");
5653 rld
[r
].optional
= 1;
5654 rld
[r
].secondary_p
= 1;
5657 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5658 for reload R. If it's valid, get an rtx for it. Return nonzero if
5661 set_reload_reg (int i
, int r
)
5664 rtx reg
= spill_reg_rtx
[i
];
5666 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5667 spill_reg_rtx
[i
] = reg
5668 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5670 regno
= true_regnum (reg
);
5672 /* Detect when the reload reg can't hold the reload mode.
5673 This used to be one `if', but Sequent compiler can't handle that. */
5674 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5676 enum machine_mode test_mode
= VOIDmode
;
5678 test_mode
= GET_MODE (rld
[r
].in
);
5679 /* If rld[r].in has VOIDmode, it means we will load it
5680 in whatever mode the reload reg has: to wit, rld[r].mode.
5681 We have already tested that for validity. */
5682 /* Aside from that, we need to test that the expressions
5683 to reload from or into have modes which are valid for this
5684 reload register. Otherwise the reload insns would be invalid. */
5685 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5686 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5687 if (! (rld
[r
].out
!= 0
5688 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5690 /* The reg is OK. */
5693 /* Mark as in use for this insn the reload regs we use
5695 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5696 rld
[r
].when_needed
, rld
[r
].mode
);
5698 rld
[r
].reg_rtx
= reg
;
5699 reload_spill_index
[r
] = spill_regs
[i
];
5706 /* Find a spill register to use as a reload register for reload R.
5707 LAST_RELOAD is nonzero if this is the last reload for the insn being
5710 Set rld[R].reg_rtx to the register allocated.
5712 We return 1 if successful, or 0 if we couldn't find a spill reg and
5713 we didn't change anything. */
5716 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
5721 /* If we put this reload ahead, thinking it is a group,
5722 then insist on finding a group. Otherwise we can grab a
5723 reg that some other reload needs.
5724 (That can happen when we have a 68000 DATA_OR_FP_REG
5725 which is a group of data regs or one fp reg.)
5726 We need not be so restrictive if there are no more reloads
5729 ??? Really it would be nicer to have smarter handling
5730 for that kind of reg class, where a problem like this is normal.
5731 Perhaps those classes should be avoided for reloading
5732 by use of more alternatives. */
5734 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5736 /* If we want a single register and haven't yet found one,
5737 take any reg in the right class and not in use.
5738 If we want a consecutive group, here is where we look for it.
5740 We use two passes so we can first look for reload regs to
5741 reuse, which are already in use for other reloads in this insn,
5742 and only then use additional registers.
5743 I think that maximizing reuse is needed to make sure we don't
5744 run out of reload regs. Suppose we have three reloads, and
5745 reloads A and B can share regs. These need two regs.
5746 Suppose A and B are given different regs.
5747 That leaves none for C. */
5748 for (pass
= 0; pass
< 2; pass
++)
5750 /* I is the index in spill_regs.
5751 We advance it round-robin between insns to use all spill regs
5752 equally, so that inherited reloads have a chance
5753 of leapfrogging each other. */
5757 for (count
= 0; count
< n_spills
; count
++)
5759 int rclass
= (int) rld
[r
].rclass
;
5765 regnum
= spill_regs
[i
];
5767 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5770 /* We check reload_reg_used to make sure we
5771 don't clobber the return register. */
5772 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5773 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5774 rld
[r
].when_needed
, rld
[r
].in
,
5776 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
5777 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5778 /* Look first for regs to share, then for unshared. But
5779 don't share regs used for inherited reloads; they are
5780 the ones we want to preserve. */
5782 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5784 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5787 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
5788 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5789 (on 68000) got us two FP regs. If NR is 1,
5790 we would reject both of them. */
5793 /* If we need only one reg, we have already won. */
5796 /* But reject a single reg if we demand a group. */
5801 /* Otherwise check that as many consecutive regs as we need
5802 are available here. */
5805 int regno
= regnum
+ nr
- 1;
5806 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
5807 && spill_reg_order
[regno
] >= 0
5808 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5809 rld
[r
].when_needed
)))
5818 /* If we found something on pass 1, omit pass 2. */
5819 if (count
< n_spills
)
5823 /* We should have found a spill register by now. */
5824 if (count
>= n_spills
)
5827 /* I is the index in SPILL_REG_RTX of the reload register we are to
5828 allocate. Get an rtx for it and find its register number. */
5830 return set_reload_reg (i
, r
);
5833 /* Initialize all the tables needed to allocate reload registers.
5834 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5835 is the array we use to restore the reg_rtx field for every reload. */
5838 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
5842 for (i
= 0; i
< n_reloads
; i
++)
5843 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5845 memset (reload_inherited
, 0, MAX_RELOADS
);
5846 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5847 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5849 CLEAR_HARD_REG_SET (reload_reg_used
);
5850 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5851 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5852 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5853 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5854 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5856 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5859 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5860 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5861 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5862 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5863 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5864 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5867 for (i
= 0; i
< reload_n_operands
; i
++)
5869 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5870 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5871 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5872 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5873 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5874 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5877 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5879 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5881 for (i
= 0; i
< n_reloads
; i
++)
5882 /* If we have already decided to use a certain register,
5883 don't use it in another way. */
5885 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5886 rld
[i
].when_needed
, rld
[i
].mode
);
5889 /* Assign hard reg targets for the pseudo-registers we must reload
5890 into hard regs for this insn.
5891 Also output the instructions to copy them in and out of the hard regs.
5893 For machines with register classes, we are responsible for
5894 finding a reload reg in the proper class. */
5897 choose_reload_regs (struct insn_chain
*chain
)
5899 rtx insn
= chain
->insn
;
5901 unsigned int max_group_size
= 1;
5902 enum reg_class group_class
= NO_REGS
;
5903 int pass
, win
, inheritance
;
5905 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5907 /* In order to be certain of getting the registers we need,
5908 we must sort the reloads into order of increasing register class.
5909 Then our grabbing of reload registers will parallel the process
5910 that provided the reload registers.
5912 Also note whether any of the reloads wants a consecutive group of regs.
5913 If so, record the maximum size of the group desired and what
5914 register class contains all the groups needed by this insn. */
5916 for (j
= 0; j
< n_reloads
; j
++)
5918 reload_order
[j
] = j
;
5919 if (rld
[j
].reg_rtx
!= NULL_RTX
)
5921 gcc_assert (REG_P (rld
[j
].reg_rtx
)
5922 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
5923 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
5926 reload_spill_index
[j
] = -1;
5928 if (rld
[j
].nregs
> 1)
5930 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5932 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
5935 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5939 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5941 /* If -O, try first with inheritance, then turning it off.
5942 If not -O, don't do inheritance.
5943 Using inheritance when not optimizing leads to paradoxes
5944 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5945 because one side of the comparison might be inherited. */
5947 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5949 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5951 /* Process the reloads in order of preference just found.
5952 Beyond this point, subregs can be found in reload_reg_rtx.
5954 This used to look for an existing reloaded home for all of the
5955 reloads, and only then perform any new reloads. But that could lose
5956 if the reloads were done out of reg-class order because a later
5957 reload with a looser constraint might have an old home in a register
5958 needed by an earlier reload with a tighter constraint.
5960 To solve this, we make two passes over the reloads, in the order
5961 described above. In the first pass we try to inherit a reload
5962 from a previous insn. If there is a later reload that needs a
5963 class that is a proper subset of the class being processed, we must
5964 also allocate a spill register during the first pass.
5966 Then make a second pass over the reloads to allocate any reloads
5967 that haven't been given registers yet. */
5969 for (j
= 0; j
< n_reloads
; j
++)
5971 int r
= reload_order
[j
];
5972 rtx search_equiv
= NULL_RTX
;
5974 /* Ignore reloads that got marked inoperative. */
5975 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5976 && ! rld
[r
].secondary_p
)
5979 /* If find_reloads chose to use reload_in or reload_out as a reload
5980 register, we don't need to chose one. Otherwise, try even if it
5981 found one since we might save an insn if we find the value lying
5983 Try also when reload_in is a pseudo without a hard reg. */
5984 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5985 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5986 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5987 && !MEM_P (rld
[r
].in
)
5988 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5991 #if 0 /* No longer needed for correct operation.
5992 It might give better code, or might not; worth an experiment? */
5993 /* If this is an optional reload, we can't inherit from earlier insns
5994 until we are sure that any non-optional reloads have been allocated.
5995 The following code takes advantage of the fact that optional reloads
5996 are at the end of reload_order. */
5997 if (rld
[r
].optional
!= 0)
5998 for (i
= 0; i
< j
; i
++)
5999 if ((rld
[reload_order
[i
]].out
!= 0
6000 || rld
[reload_order
[i
]].in
!= 0
6001 || rld
[reload_order
[i
]].secondary_p
)
6002 && ! rld
[reload_order
[i
]].optional
6003 && rld
[reload_order
[i
]].reg_rtx
== 0)
6004 allocate_reload_reg (chain
, reload_order
[i
], 0);
6007 /* First see if this pseudo is already available as reloaded
6008 for a previous insn. We cannot try to inherit for reloads
6009 that are smaller than the maximum number of registers needed
6010 for groups unless the register we would allocate cannot be used
6013 We could check here to see if this is a secondary reload for
6014 an object that is already in a register of the desired class.
6015 This would avoid the need for the secondary reload register.
6016 But this is complex because we can't easily determine what
6017 objects might want to be loaded via this reload. So let a
6018 register be allocated here. In `emit_reload_insns' we suppress
6019 one of the loads in the case described above. */
6025 enum machine_mode mode
= VOIDmode
;
6029 else if (REG_P (rld
[r
].in
))
6031 regno
= REGNO (rld
[r
].in
);
6032 mode
= GET_MODE (rld
[r
].in
);
6034 else if (REG_P (rld
[r
].in_reg
))
6036 regno
= REGNO (rld
[r
].in_reg
);
6037 mode
= GET_MODE (rld
[r
].in_reg
);
6039 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6040 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6042 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6043 if (regno
< FIRST_PSEUDO_REGISTER
)
6044 regno
= subreg_regno (rld
[r
].in_reg
);
6046 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
6047 mode
= GET_MODE (rld
[r
].in_reg
);
6050 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6051 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6053 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6054 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6055 rld
[r
].out
= rld
[r
].in
;
6059 /* This won't work, since REGNO can be a pseudo reg number.
6060 Also, it takes much more hair to keep track of all the things
6061 that can invalidate an inherited reload of part of a pseudoreg. */
6062 else if (GET_CODE (rld
[r
].in
) == SUBREG
6063 && REG_P (SUBREG_REG (rld
[r
].in
)))
6064 regno
= subreg_regno (rld
[r
].in
);
6068 && reg_last_reload_reg
[regno
] != 0
6069 #ifdef CANNOT_CHANGE_MODE_CLASS
6070 /* Verify that the register it's in can be used in
6072 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6073 GET_MODE (reg_last_reload_reg
[regno
]),
6078 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6079 rtx last_reg
= reg_last_reload_reg
[regno
];
6080 enum machine_mode need_mode
;
6082 i
= REGNO (last_reg
);
6083 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6084 last_class
= REGNO_REG_CLASS (i
);
6090 = smallest_mode_for_size (GET_MODE_BITSIZE (mode
)
6091 + byte
* BITS_PER_UNIT
,
6092 GET_MODE_CLASS (mode
));
6094 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
6095 >= GET_MODE_SIZE (need_mode
))
6096 && reg_reloaded_contents
[i
] == regno
6097 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6098 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6099 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6100 /* Even if we can't use this register as a reload
6101 register, we might use it for reload_override_in,
6102 if copying it to the desired class is cheap
6104 || ((REGISTER_MOVE_COST (mode
, last_class
, rclass
)
6105 < MEMORY_MOVE_COST (mode
, rclass
, 1))
6106 && (secondary_reload_class (1, rclass
, mode
,
6109 #ifdef SECONDARY_MEMORY_NEEDED
6110 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6115 && (rld
[r
].nregs
== max_group_size
6116 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6118 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6119 rld
[r
].when_needed
, rld
[r
].in
,
6122 /* If a group is needed, verify that all the subsequent
6123 registers still have their values intact. */
6124 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6127 for (k
= 1; k
< nr
; k
++)
6128 if (reg_reloaded_contents
[i
+ k
] != regno
6129 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6137 last_reg
= (GET_MODE (last_reg
) == mode
6138 ? last_reg
: gen_rtx_REG (mode
, i
));
6141 for (k
= 0; k
< nr
; k
++)
6142 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6145 /* We found a register that contains the
6146 value we need. If this register is the
6147 same as an `earlyclobber' operand of the
6148 current insn, just mark it as a place to
6149 reload from since we can't use it as the
6150 reload register itself. */
6152 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6153 if (reg_overlap_mentioned_for_reload_p
6154 (reg_last_reload_reg
[regno
],
6155 reload_earlyclobbers
[i1
]))
6158 if (i1
!= n_earlyclobbers
6159 || ! (free_for_value_p (i
, rld
[r
].mode
,
6161 rld
[r
].when_needed
, rld
[r
].in
,
6163 /* Don't use it if we'd clobber a pseudo reg. */
6164 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6166 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6167 /* Don't clobber the frame pointer. */
6168 || (i
== HARD_FRAME_POINTER_REGNUM
6169 && frame_pointer_needed
6171 /* Don't really use the inherited spill reg
6172 if we need it wider than we've got it. */
6173 || (GET_MODE_SIZE (rld
[r
].mode
)
6174 > GET_MODE_SIZE (mode
))
6177 /* If find_reloads chose reload_out as reload
6178 register, stay with it - that leaves the
6179 inherited register for subsequent reloads. */
6180 || (rld
[r
].out
&& rld
[r
].reg_rtx
6181 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6183 if (! rld
[r
].optional
)
6185 reload_override_in
[r
] = last_reg
;
6186 reload_inheritance_insn
[r
]
6187 = reg_reloaded_insn
[i
];
6193 /* We can use this as a reload reg. */
6194 /* Mark the register as in use for this part of
6196 mark_reload_reg_in_use (i
,
6200 rld
[r
].reg_rtx
= last_reg
;
6201 reload_inherited
[r
] = 1;
6202 reload_inheritance_insn
[r
]
6203 = reg_reloaded_insn
[i
];
6204 reload_spill_index
[r
] = i
;
6205 for (k
= 0; k
< nr
; k
++)
6206 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6214 /* Here's another way to see if the value is already lying around. */
6217 && ! reload_inherited
[r
]
6219 && (CONSTANT_P (rld
[r
].in
)
6220 || GET_CODE (rld
[r
].in
) == PLUS
6221 || REG_P (rld
[r
].in
)
6222 || MEM_P (rld
[r
].in
))
6223 && (rld
[r
].nregs
== max_group_size
6224 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6225 search_equiv
= rld
[r
].in
;
6226 /* If this is an output reload from a simple move insn, look
6227 if an equivalence for the input is available. */
6228 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
6230 rtx set
= single_set (insn
);
6233 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
6234 && CONSTANT_P (SET_SRC (set
)))
6235 search_equiv
= SET_SRC (set
);
6241 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6242 -1, NULL
, 0, rld
[r
].mode
);
6248 regno
= REGNO (equiv
);
6251 /* This must be a SUBREG of a hard register.
6252 Make a new REG since this might be used in an
6253 address and not all machines support SUBREGs
6255 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6256 regno
= subreg_regno (equiv
);
6257 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6258 /* If we choose EQUIV as the reload register, but the
6259 loop below decides to cancel the inheritance, we'll
6260 end up reloading EQUIV in rld[r].mode, not the mode
6261 it had originally. That isn't safe when EQUIV isn't
6262 available as a spill register since its value might
6263 still be live at this point. */
6264 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6265 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6270 /* If we found a spill reg, reject it unless it is free
6271 and of the desired class. */
6275 int bad_for_class
= 0;
6276 int max_regno
= regno
+ rld
[r
].nregs
;
6278 for (i
= regno
; i
< max_regno
; i
++)
6280 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6282 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6287 && ! free_for_value_p (regno
, rld
[r
].mode
,
6288 rld
[r
].opnum
, rld
[r
].when_needed
,
6289 rld
[r
].in
, rld
[r
].out
, r
, 1))
6294 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6297 /* We found a register that contains the value we need.
6298 If this register is the same as an `earlyclobber' operand
6299 of the current insn, just mark it as a place to reload from
6300 since we can't use it as the reload register itself. */
6303 for (i
= 0; i
< n_earlyclobbers
; i
++)
6304 if (reg_overlap_mentioned_for_reload_p (equiv
,
6305 reload_earlyclobbers
[i
]))
6307 if (! rld
[r
].optional
)
6308 reload_override_in
[r
] = equiv
;
6313 /* If the equiv register we have found is explicitly clobbered
6314 in the current insn, it depends on the reload type if we
6315 can use it, use it for reload_override_in, or not at all.
6316 In particular, we then can't use EQUIV for a
6317 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6321 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6322 switch (rld
[r
].when_needed
)
6324 case RELOAD_FOR_OTHER_ADDRESS
:
6325 case RELOAD_FOR_INPADDR_ADDRESS
:
6326 case RELOAD_FOR_INPUT_ADDRESS
:
6327 case RELOAD_FOR_OPADDR_ADDR
:
6330 case RELOAD_FOR_INPUT
:
6331 case RELOAD_FOR_OPERAND_ADDRESS
:
6332 if (! rld
[r
].optional
)
6333 reload_override_in
[r
] = equiv
;
6339 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6340 switch (rld
[r
].when_needed
)
6342 case RELOAD_FOR_OTHER_ADDRESS
:
6343 case RELOAD_FOR_INPADDR_ADDRESS
:
6344 case RELOAD_FOR_INPUT_ADDRESS
:
6345 case RELOAD_FOR_OPADDR_ADDR
:
6346 case RELOAD_FOR_OPERAND_ADDRESS
:
6347 case RELOAD_FOR_INPUT
:
6350 if (! rld
[r
].optional
)
6351 reload_override_in
[r
] = equiv
;
6359 /* If we found an equivalent reg, say no code need be generated
6360 to load it, and use it as our reload reg. */
6362 && (regno
!= HARD_FRAME_POINTER_REGNUM
6363 || !frame_pointer_needed
))
6365 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6367 rld
[r
].reg_rtx
= equiv
;
6368 reload_inherited
[r
] = 1;
6370 /* If reg_reloaded_valid is not set for this register,
6371 there might be a stale spill_reg_store lying around.
6372 We must clear it, since otherwise emit_reload_insns
6373 might delete the store. */
6374 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6375 spill_reg_store
[regno
] = NULL_RTX
;
6376 /* If any of the hard registers in EQUIV are spill
6377 registers, mark them as in use for this insn. */
6378 for (k
= 0; k
< nr
; k
++)
6380 i
= spill_reg_order
[regno
+ k
];
6383 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6386 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6393 /* If we found a register to use already, or if this is an optional
6394 reload, we are done. */
6395 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6399 /* No longer needed for correct operation. Might or might
6400 not give better code on the average. Want to experiment? */
6402 /* See if there is a later reload that has a class different from our
6403 class that intersects our class or that requires less register
6404 than our reload. If so, we must allocate a register to this
6405 reload now, since that reload might inherit a previous reload
6406 and take the only available register in our class. Don't do this
6407 for optional reloads since they will force all previous reloads
6408 to be allocated. Also don't do this for reloads that have been
6411 for (i
= j
+ 1; i
< n_reloads
; i
++)
6413 int s
= reload_order
[i
];
6415 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6416 && ! rld
[s
].secondary_p
)
6420 if ((rld
[s
].rclass
!= rld
[r
].rclass
6421 && reg_classes_intersect_p (rld
[r
].rclass
,
6423 || rld
[s
].nregs
< rld
[r
].nregs
)
6430 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6434 /* Now allocate reload registers for anything non-optional that
6435 didn't get one yet. */
6436 for (j
= 0; j
< n_reloads
; j
++)
6438 int r
= reload_order
[j
];
6440 /* Ignore reloads that got marked inoperative. */
6441 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6444 /* Skip reloads that already have a register allocated or are
6446 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6449 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6453 /* If that loop got all the way, we have won. */
6460 /* Loop around and try without any inheritance. */
6465 /* First undo everything done by the failed attempt
6466 to allocate with inheritance. */
6467 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6469 /* Some sanity tests to verify that the reloads found in the first
6470 pass are identical to the ones we have now. */
6471 gcc_assert (chain
->n_reloads
== n_reloads
);
6473 for (i
= 0; i
< n_reloads
; i
++)
6475 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6477 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6478 for (j
= 0; j
< n_spills
; j
++)
6479 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6480 if (! set_reload_reg (j
, i
))
6481 failed_reload (chain
->insn
, i
);
6485 /* If we thought we could inherit a reload, because it seemed that
6486 nothing else wanted the same reload register earlier in the insn,
6487 verify that assumption, now that all reloads have been assigned.
6488 Likewise for reloads where reload_override_in has been set. */
6490 /* If doing expensive optimizations, do one preliminary pass that doesn't
6491 cancel any inheritance, but removes reloads that have been needed only
6492 for reloads that we know can be inherited. */
6493 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6495 for (j
= 0; j
< n_reloads
; j
++)
6497 int r
= reload_order
[j
];
6499 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6500 check_reg
= rld
[r
].reg_rtx
;
6501 else if (reload_override_in
[r
]
6502 && (REG_P (reload_override_in
[r
])
6503 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6504 check_reg
= reload_override_in
[r
];
6507 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6508 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6509 (reload_inherited
[r
]
6510 ? rld
[r
].out
: const0_rtx
),
6515 reload_inherited
[r
] = 0;
6516 reload_override_in
[r
] = 0;
6518 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6519 reload_override_in, then we do not need its related
6520 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6521 likewise for other reload types.
6522 We handle this by removing a reload when its only replacement
6523 is mentioned in reload_in of the reload we are going to inherit.
6524 A special case are auto_inc expressions; even if the input is
6525 inherited, we still need the address for the output. We can
6526 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6527 If we succeeded removing some reload and we are doing a preliminary
6528 pass just to remove such reloads, make another pass, since the
6529 removal of one reload might allow us to inherit another one. */
6531 && rld
[r
].out
!= rld
[r
].in
6532 && remove_address_replacements (rld
[r
].in
) && pass
)
6537 /* Now that reload_override_in is known valid,
6538 actually override reload_in. */
6539 for (j
= 0; j
< n_reloads
; j
++)
6540 if (reload_override_in
[j
])
6541 rld
[j
].in
= reload_override_in
[j
];
6543 /* If this reload won't be done because it has been canceled or is
6544 optional and not inherited, clear reload_reg_rtx so other
6545 routines (such as subst_reloads) don't get confused. */
6546 for (j
= 0; j
< n_reloads
; j
++)
6547 if (rld
[j
].reg_rtx
!= 0
6548 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6549 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6550 && ! rld
[j
].secondary_p
)))
6552 int regno
= true_regnum (rld
[j
].reg_rtx
);
6554 if (spill_reg_order
[regno
] >= 0)
6555 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6556 rld
[j
].when_needed
, rld
[j
].mode
);
6558 reload_spill_index
[j
] = -1;
6561 /* Record which pseudos and which spill regs have output reloads. */
6562 for (j
= 0; j
< n_reloads
; j
++)
6564 int r
= reload_order
[j
];
6566 i
= reload_spill_index
[r
];
6568 /* I is nonneg if this reload uses a register.
6569 If rld[r].reg_rtx is 0, this is an optional reload
6570 that we opted to ignore. */
6571 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6572 && rld
[r
].reg_rtx
!= 0)
6574 int nregno
= REGNO (rld
[r
].out_reg
);
6577 if (nregno
< FIRST_PSEUDO_REGISTER
)
6578 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
6581 SET_REGNO_REG_SET (®_has_output_reload
,
6586 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6588 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6591 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
6592 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
6593 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
6598 /* Deallocate the reload register for reload R. This is called from
6599 remove_address_replacements. */
6602 deallocate_reload_reg (int r
)
6606 if (! rld
[r
].reg_rtx
)
6608 regno
= true_regnum (rld
[r
].reg_rtx
);
6610 if (spill_reg_order
[regno
] >= 0)
6611 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6613 reload_spill_index
[r
] = -1;
6616 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6617 reloads of the same item for fear that we might not have enough reload
6618 registers. However, normally they will get the same reload register
6619 and hence actually need not be loaded twice.
6621 Here we check for the most common case of this phenomenon: when we have
6622 a number of reloads for the same object, each of which were allocated
6623 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6624 reload, and is not modified in the insn itself. If we find such,
6625 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6626 This will not increase the number of spill registers needed and will
6627 prevent redundant code. */
6630 merge_assigned_reloads (rtx insn
)
6634 /* Scan all the reloads looking for ones that only load values and
6635 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6636 assigned and not modified by INSN. */
6638 for (i
= 0; i
< n_reloads
; i
++)
6640 int conflicting_input
= 0;
6641 int max_input_address_opnum
= -1;
6642 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6644 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6645 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6646 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6649 /* Look at all other reloads. Ensure that the only use of this
6650 reload_reg_rtx is in a reload that just loads the same value
6651 as we do. Note that any secondary reloads must be of the identical
6652 class since the values, modes, and result registers are the
6653 same, so we need not do anything with any secondary reloads. */
6655 for (j
= 0; j
< n_reloads
; j
++)
6657 if (i
== j
|| rld
[j
].reg_rtx
== 0
6658 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6662 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6663 && rld
[j
].opnum
> max_input_address_opnum
)
6664 max_input_address_opnum
= rld
[j
].opnum
;
6666 /* If the reload regs aren't exactly the same (e.g, different modes)
6667 or if the values are different, we can't merge this reload.
6668 But if it is an input reload, we might still merge
6669 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6671 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6672 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6673 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6675 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6676 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6677 || rld
[i
].opnum
> rld
[j
].opnum
)
6678 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6680 conflicting_input
= 1;
6681 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6682 min_conflicting_input_opnum
= rld
[j
].opnum
;
6686 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6687 we, in fact, found any matching reloads. */
6690 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6692 gcc_assert (rld
[i
].when_needed
!= RELOAD_FOR_OUTPUT
);
6694 for (j
= 0; j
< n_reloads
; j
++)
6695 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6696 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6697 && (! conflicting_input
6698 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6699 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6701 rld
[i
].when_needed
= RELOAD_OTHER
;
6703 reload_spill_index
[j
] = -1;
6704 transfer_replacements (i
, j
);
6707 /* If this is now RELOAD_OTHER, look for any reloads that
6708 load parts of this operand and set them to
6709 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6710 RELOAD_OTHER for outputs. Note that this test is
6711 equivalent to looking for reloads for this operand
6714 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6715 it may share registers with a RELOAD_FOR_INPUT, so we can
6716 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6717 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6719 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6720 instruction is assigned the same register as the earlier
6721 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6722 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6723 instruction to be deleted later on. */
6725 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6726 for (j
= 0; j
< n_reloads
; j
++)
6728 && rld
[j
].when_needed
!= RELOAD_OTHER
6729 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6730 && rld
[j
].when_needed
!= RELOAD_FOR_OUTPUT_ADDRESS
6731 && rld
[j
].when_needed
!= RELOAD_FOR_OPERAND_ADDRESS
6732 && (! conflicting_input
6733 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6734 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6735 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6741 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6742 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6743 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6745 /* Check to see if we accidentally converted two
6746 reloads that use the same reload register with
6747 different inputs to the same type. If so, the
6748 resulting code won't work. */
6750 for (k
= 0; k
< j
; k
++)
6751 gcc_assert (rld
[k
].in
== 0 || rld
[k
].reg_rtx
== 0
6752 || rld
[k
].when_needed
!= rld
[j
].when_needed
6753 || !rtx_equal_p (rld
[k
].reg_rtx
,
6755 || rtx_equal_p (rld
[k
].in
,
6762 /* These arrays are filled by emit_reload_insns and its subroutines. */
6763 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6764 static rtx other_input_address_reload_insns
= 0;
6765 static rtx other_input_reload_insns
= 0;
6766 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6767 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6768 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6769 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6770 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6771 static rtx operand_reload_insns
= 0;
6772 static rtx other_operand_reload_insns
= 0;
6773 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6775 /* Values to be put in spill_reg_store are put here first. */
6776 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6777 static HARD_REG_SET reg_reloaded_died
;
6779 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6780 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6781 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6782 adjusted register, and return true. Otherwise, return false. */
6784 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
6785 enum reg_class new_class
,
6786 enum machine_mode new_mode
)
6791 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
6793 unsigned regno
= REGNO (reg
);
6795 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
6797 if (GET_MODE (reg
) != new_mode
)
6799 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
6801 if (hard_regno_nregs
[regno
][new_mode
]
6802 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
6804 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
6812 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6813 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6814 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6815 adjusted register, and return true. Otherwise, return false. */
6817 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
6818 enum insn_code icode
)
6821 enum reg_class new_class
= scratch_reload_class (icode
);
6822 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
6824 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
6825 new_class
, new_mode
);
6828 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6829 has the number J. OLD contains the value to be used as input. */
6832 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6835 rtx insn
= chain
->insn
;
6837 rtx oldequiv_reg
= 0;
6840 enum machine_mode mode
;
6843 /* delete_output_reload is only invoked properly if old contains
6844 the original pseudo register. Since this is replaced with a
6845 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6846 find the pseudo in RELOAD_IN_REG. */
6847 if (reload_override_in
[j
]
6848 && REG_P (rl
->in_reg
))
6855 else if (REG_P (oldequiv
))
6856 oldequiv_reg
= oldequiv
;
6857 else if (GET_CODE (oldequiv
) == SUBREG
)
6858 oldequiv_reg
= SUBREG_REG (oldequiv
);
6860 reloadreg
= reload_reg_rtx_for_input
[j
];
6861 mode
= GET_MODE (reloadreg
);
6863 /* If we are reloading from a register that was recently stored in
6864 with an output-reload, see if we can prove there was
6865 actually no need to store the old value in it. */
6867 if (optimize
&& REG_P (oldequiv
)
6868 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6869 && spill_reg_store
[REGNO (oldequiv
)]
6871 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6872 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6874 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
6876 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6879 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6880 oldequiv
= SUBREG_REG (oldequiv
);
6881 if (GET_MODE (oldequiv
) != VOIDmode
6882 && mode
!= GET_MODE (oldequiv
))
6883 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6885 /* Switch to the right place to emit the reload insns. */
6886 switch (rl
->when_needed
)
6889 where
= &other_input_reload_insns
;
6891 case RELOAD_FOR_INPUT
:
6892 where
= &input_reload_insns
[rl
->opnum
];
6894 case RELOAD_FOR_INPUT_ADDRESS
:
6895 where
= &input_address_reload_insns
[rl
->opnum
];
6897 case RELOAD_FOR_INPADDR_ADDRESS
:
6898 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6900 case RELOAD_FOR_OUTPUT_ADDRESS
:
6901 where
= &output_address_reload_insns
[rl
->opnum
];
6903 case RELOAD_FOR_OUTADDR_ADDRESS
:
6904 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6906 case RELOAD_FOR_OPERAND_ADDRESS
:
6907 where
= &operand_reload_insns
;
6909 case RELOAD_FOR_OPADDR_ADDR
:
6910 where
= &other_operand_reload_insns
;
6912 case RELOAD_FOR_OTHER_ADDRESS
:
6913 where
= &other_input_address_reload_insns
;
6919 push_to_sequence (*where
);
6921 /* Auto-increment addresses must be reloaded in a special way. */
6922 if (rl
->out
&& ! rl
->out_reg
)
6924 /* We are not going to bother supporting the case where a
6925 incremented register can't be copied directly from
6926 OLDEQUIV since this seems highly unlikely. */
6927 gcc_assert (rl
->secondary_in_reload
< 0);
6929 if (reload_inherited
[j
])
6930 oldequiv
= reloadreg
;
6932 old
= XEXP (rl
->in_reg
, 0);
6934 if (optimize
&& REG_P (oldequiv
)
6935 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6936 && spill_reg_store
[REGNO (oldequiv
)]
6938 && (dead_or_set_p (insn
,
6939 spill_reg_stored_to
[REGNO (oldequiv
)])
6940 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6942 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
6944 /* Prevent normal processing of this reload. */
6946 /* Output a special code sequence for this case. */
6947 new_spill_reg_store
[REGNO (reloadreg
)]
6948 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6952 /* If we are reloading a pseudo-register that was set by the previous
6953 insn, see if we can get rid of that pseudo-register entirely
6954 by redirecting the previous insn into our reload register. */
6956 else if (optimize
&& REG_P (old
)
6957 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6958 && dead_or_set_p (insn
, old
)
6959 /* This is unsafe if some other reload
6960 uses the same reg first. */
6961 && ! conflicts_with_override (reloadreg
)
6962 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6963 rl
->when_needed
, old
, rl
->out
, j
, 0))
6965 rtx temp
= PREV_INSN (insn
);
6966 while (temp
&& NOTE_P (temp
))
6967 temp
= PREV_INSN (temp
);
6969 && NONJUMP_INSN_P (temp
)
6970 && GET_CODE (PATTERN (temp
)) == SET
6971 && SET_DEST (PATTERN (temp
)) == old
6972 /* Make sure we can access insn_operand_constraint. */
6973 && asm_noperands (PATTERN (temp
)) < 0
6974 /* This is unsafe if operand occurs more than once in current
6975 insn. Perhaps some occurrences aren't reloaded. */
6976 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6978 rtx old
= SET_DEST (PATTERN (temp
));
6979 /* Store into the reload register instead of the pseudo. */
6980 SET_DEST (PATTERN (temp
)) = reloadreg
;
6982 /* Verify that resulting insn is valid. */
6983 extract_insn (temp
);
6984 if (constrain_operands (1))
6986 /* If the previous insn is an output reload, the source is
6987 a reload register, and its spill_reg_store entry will
6988 contain the previous destination. This is now
6990 if (REG_P (SET_SRC (PATTERN (temp
)))
6991 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6993 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6994 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6997 /* If these are the only uses of the pseudo reg,
6998 pretend for GDB it lives in the reload reg we used. */
6999 if (REG_N_DEATHS (REGNO (old
)) == 1
7000 && REG_N_SETS (REGNO (old
)) == 1)
7002 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7003 if (flag_ira
&& optimize
)
7004 /* Inform IRA about the change. */
7005 ira_mark_allocation_change (REGNO (old
));
7006 alter_reg (REGNO (old
), -1, false);
7012 SET_DEST (PATTERN (temp
)) = old
;
7017 /* We can't do that, so output an insn to load RELOADREG. */
7019 /* If we have a secondary reload, pick up the secondary register
7020 and icode, if any. If OLDEQUIV and OLD are different or
7021 if this is an in-out reload, recompute whether or not we
7022 still need a secondary register and what the icode should
7023 be. If we still need a secondary register and the class or
7024 icode is different, go back to reloading from OLD if using
7025 OLDEQUIV means that we got the wrong type of register. We
7026 cannot have different class or icode due to an in-out reload
7027 because we don't make such reloads when both the input and
7028 output need secondary reload registers. */
7030 if (! special
&& rl
->secondary_in_reload
>= 0)
7032 rtx second_reload_reg
= 0;
7033 rtx third_reload_reg
= 0;
7034 int secondary_reload
= rl
->secondary_in_reload
;
7035 rtx real_oldequiv
= oldequiv
;
7038 enum insn_code icode
;
7039 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7041 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7042 and similarly for OLD.
7043 See comments in get_secondary_reload in reload.c. */
7044 /* If it is a pseudo that cannot be replaced with its
7045 equivalent MEM, we must fall back to reload_in, which
7046 will have all the necessary substitutions registered.
7047 Likewise for a pseudo that can't be replaced with its
7048 equivalent constant.
7050 Take extra care for subregs of such pseudos. Note that
7051 we cannot use reg_equiv_mem in this case because it is
7052 not in the right mode. */
7055 if (GET_CODE (tmp
) == SUBREG
)
7056 tmp
= SUBREG_REG (tmp
);
7058 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7059 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
7060 || reg_equiv_constant
[REGNO (tmp
)] != 0))
7062 if (! reg_equiv_mem
[REGNO (tmp
)]
7063 || num_not_at_initial_offset
7064 || GET_CODE (oldequiv
) == SUBREG
)
7065 real_oldequiv
= rl
->in
;
7067 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
7071 if (GET_CODE (tmp
) == SUBREG
)
7072 tmp
= SUBREG_REG (tmp
);
7074 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7075 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
7076 || reg_equiv_constant
[REGNO (tmp
)] != 0))
7078 if (! reg_equiv_mem
[REGNO (tmp
)]
7079 || num_not_at_initial_offset
7080 || GET_CODE (old
) == SUBREG
)
7083 real_old
= reg_equiv_mem
[REGNO (tmp
)];
7086 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7087 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7089 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7091 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7092 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7093 /* We'd have to add more code for quartary reloads. */
7094 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7096 icode
= rl
->secondary_in_icode
;
7098 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7099 || (rl
->in
!= 0 && rl
->out
!= 0))
7101 secondary_reload_info sri
, sri2
;
7102 enum reg_class new_class
, new_t_class
;
7104 sri
.icode
= CODE_FOR_nothing
;
7105 sri
.prev_sri
= NULL
;
7106 new_class
= targetm
.secondary_reload (1, real_oldequiv
, rl
->rclass
,
7109 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7110 second_reload_reg
= 0;
7111 else if (new_class
== NO_REGS
)
7113 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7114 third_reload_reg
, sri
.icode
))
7115 icode
= sri
.icode
, third_reload_reg
= 0;
7117 oldequiv
= old
, real_oldequiv
= real_old
;
7119 else if (sri
.icode
!= CODE_FOR_nothing
)
7120 /* We currently lack a way to express this in reloads. */
7124 sri2
.icode
= CODE_FOR_nothing
;
7125 sri2
.prev_sri
= &sri
;
7126 new_t_class
= targetm
.secondary_reload (1, real_oldequiv
,
7127 new_class
, mode
, &sri
);
7128 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7130 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7133 third_reload_reg
= 0, tertiary_icode
= sri2
.icode
;
7135 oldequiv
= old
, real_oldequiv
= real_old
;
7137 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7139 rtx intermediate
= second_reload_reg
;
7141 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7143 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7146 second_reload_reg
= intermediate
;
7147 tertiary_icode
= sri2
.icode
;
7150 oldequiv
= old
, real_oldequiv
= real_old
;
7152 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7154 rtx intermediate
= second_reload_reg
;
7156 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7158 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7161 second_reload_reg
= intermediate
;
7162 tertiary_icode
= sri2
.icode
;
7165 oldequiv
= old
, real_oldequiv
= real_old
;
7168 /* This could be handled more intelligently too. */
7169 oldequiv
= old
, real_oldequiv
= real_old
;
7173 /* If we still need a secondary reload register, check
7174 to see if it is being used as a scratch or intermediate
7175 register and generate code appropriately. If we need
7176 a scratch register, use REAL_OLDEQUIV since the form of
7177 the insn may depend on the actual address if it is
7180 if (second_reload_reg
)
7182 if (icode
!= CODE_FOR_nothing
)
7184 /* We'd have to add extra code to handle this case. */
7185 gcc_assert (!third_reload_reg
);
7187 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7188 second_reload_reg
));
7193 /* See if we need a scratch register to load the
7194 intermediate register (a tertiary reload). */
7195 if (tertiary_icode
!= CODE_FOR_nothing
)
7197 emit_insn ((GEN_FCN (tertiary_icode
)
7198 (second_reload_reg
, real_oldequiv
,
7199 third_reload_reg
)));
7201 else if (third_reload_reg
)
7203 gen_reload (third_reload_reg
, real_oldequiv
,
7206 gen_reload (second_reload_reg
, third_reload_reg
,
7211 gen_reload (second_reload_reg
, real_oldequiv
,
7215 oldequiv
= second_reload_reg
;
7220 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7222 rtx real_oldequiv
= oldequiv
;
7224 if ((REG_P (oldequiv
)
7225 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7226 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
7227 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
7228 || (GET_CODE (oldequiv
) == SUBREG
7229 && REG_P (SUBREG_REG (oldequiv
))
7230 && (REGNO (SUBREG_REG (oldequiv
))
7231 >= FIRST_PSEUDO_REGISTER
)
7232 && ((reg_equiv_memory_loc
7233 [REGNO (SUBREG_REG (oldequiv
))] != 0)
7234 || (reg_equiv_constant
7235 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
7236 || (CONSTANT_P (oldequiv
)
7237 && (PREFERRED_RELOAD_CLASS (oldequiv
,
7238 REGNO_REG_CLASS (REGNO (reloadreg
)))
7240 real_oldequiv
= rl
->in
;
7241 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7245 if (flag_non_call_exceptions
)
7246 copy_eh_notes (insn
, get_insns ());
7248 /* End this sequence. */
7249 *where
= get_insns ();
7252 /* Update reload_override_in so that delete_address_reloads_1
7253 can see the actual register usage. */
7255 reload_override_in
[j
] = oldequiv
;
7258 /* Generate insns to for the output reload RL, which is for the insn described
7259 by CHAIN and has the number J. */
7261 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7265 rtx insn
= chain
->insn
;
7268 enum machine_mode mode
;
7272 if (rl
->when_needed
== RELOAD_OTHER
)
7275 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7277 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7278 mode
= GET_MODE (rl_reg_rtx
);
7280 reloadreg
= rl_reg_rtx
;
7282 /* If we need two reload regs, set RELOADREG to the intermediate
7283 one, since it will be stored into OLD. We might need a secondary
7284 register only for an input reload, so check again here. */
7286 if (rl
->secondary_out_reload
>= 0)
7289 int secondary_reload
= rl
->secondary_out_reload
;
7290 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7292 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7293 && reg_equiv_mem
[REGNO (old
)] != 0)
7294 real_old
= reg_equiv_mem
[REGNO (old
)];
7296 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7298 rtx second_reloadreg
= reloadreg
;
7299 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7301 /* See if RELOADREG is to be used as a scratch register
7302 or as an intermediate register. */
7303 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7305 /* We'd have to add extra code to handle this case. */
7306 gcc_assert (tertiary_reload
< 0);
7308 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7309 (real_old
, second_reloadreg
, reloadreg
)));
7314 /* See if we need both a scratch and intermediate reload
7317 enum insn_code tertiary_icode
7318 = rld
[secondary_reload
].secondary_out_icode
;
7320 /* We'd have to add more code for quartary reloads. */
7321 gcc_assert (tertiary_reload
< 0
7322 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7324 if (GET_MODE (reloadreg
) != mode
)
7325 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7327 if (tertiary_icode
!= CODE_FOR_nothing
)
7329 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7332 /* Copy primary reload reg to secondary reload reg.
7333 (Note that these have been swapped above, then
7334 secondary reload reg to OLD using our insn.) */
7336 /* If REAL_OLD is a paradoxical SUBREG, remove it
7337 and try to put the opposite SUBREG on
7339 if (GET_CODE (real_old
) == SUBREG
7340 && (GET_MODE_SIZE (GET_MODE (real_old
))
7341 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7342 && 0 != (tem
= gen_lowpart_common
7343 (GET_MODE (SUBREG_REG (real_old
)),
7345 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7347 gen_reload (reloadreg
, second_reloadreg
,
7348 rl
->opnum
, rl
->when_needed
);
7349 emit_insn ((GEN_FCN (tertiary_icode
)
7350 (real_old
, reloadreg
, third_reloadreg
)));
7356 /* Copy between the reload regs here and then to
7359 gen_reload (reloadreg
, second_reloadreg
,
7360 rl
->opnum
, rl
->when_needed
);
7361 if (tertiary_reload
>= 0)
7363 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7365 gen_reload (third_reloadreg
, reloadreg
,
7366 rl
->opnum
, rl
->when_needed
);
7367 reloadreg
= third_reloadreg
;
7374 /* Output the last reload insn. */
7379 /* Don't output the last reload if OLD is not the dest of
7380 INSN and is in the src and is clobbered by INSN. */
7381 if (! flag_expensive_optimizations
7383 || !(set
= single_set (insn
))
7384 || rtx_equal_p (old
, SET_DEST (set
))
7385 || !reg_mentioned_p (old
, SET_SRC (set
))
7386 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7387 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7388 gen_reload (old
, reloadreg
, rl
->opnum
,
7392 /* Look at all insns we emitted, just to be safe. */
7393 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7396 rtx pat
= PATTERN (p
);
7398 /* If this output reload doesn't come from a spill reg,
7399 clear any memory of reloaded copies of the pseudo reg.
7400 If this output reload comes from a spill reg,
7401 reg_has_output_reload will make this do nothing. */
7402 note_stores (pat
, forget_old_reloads_1
, NULL
);
7404 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7406 rtx set
= single_set (insn
);
7407 if (reload_spill_index
[j
] < 0
7409 && SET_SRC (set
) == rl_reg_rtx
)
7411 int src
= REGNO (SET_SRC (set
));
7413 reload_spill_index
[j
] = src
;
7414 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7415 if (find_regno_note (insn
, REG_DEAD
, src
))
7416 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7418 if (HARD_REGISTER_P (rl_reg_rtx
))
7420 int s
= rl
->secondary_out_reload
;
7421 set
= single_set (p
);
7422 /* If this reload copies only to the secondary reload
7423 register, the secondary reload does the actual
7425 if (s
>= 0 && set
== NULL_RTX
)
7426 /* We can't tell what function the secondary reload
7427 has and where the actual store to the pseudo is
7428 made; leave new_spill_reg_store alone. */
7431 && SET_SRC (set
) == rl_reg_rtx
7432 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7434 /* Usually the next instruction will be the
7435 secondary reload insn; if we can confirm
7436 that it is, setting new_spill_reg_store to
7437 that insn will allow an extra optimization. */
7438 rtx s_reg
= rld
[s
].reg_rtx
;
7439 rtx next
= NEXT_INSN (p
);
7440 rld
[s
].out
= rl
->out
;
7441 rld
[s
].out_reg
= rl
->out_reg
;
7442 set
= single_set (next
);
7443 if (set
&& SET_SRC (set
) == s_reg
7444 && ! new_spill_reg_store
[REGNO (s_reg
)])
7446 SET_HARD_REG_BIT (reg_is_output_reload
,
7448 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7452 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7457 if (rl
->when_needed
== RELOAD_OTHER
)
7459 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7460 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7463 output_reload_insns
[rl
->opnum
] = get_insns ();
7465 if (flag_non_call_exceptions
)
7466 copy_eh_notes (insn
, get_insns ());
7471 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7472 and has the number J. */
7474 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7476 rtx insn
= chain
->insn
;
7477 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7478 ? rl
->in_reg
: rl
->in
);
7479 rtx reg_rtx
= rl
->reg_rtx
;
7483 enum machine_mode mode
;
7485 /* Determine the mode to reload in.
7486 This is very tricky because we have three to choose from.
7487 There is the mode the insn operand wants (rl->inmode).
7488 There is the mode of the reload register RELOADREG.
7489 There is the intrinsic mode of the operand, which we could find
7490 by stripping some SUBREGs.
7491 It turns out that RELOADREG's mode is irrelevant:
7492 we can change that arbitrarily.
7494 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7495 then the reload reg may not support QImode moves, so use SImode.
7496 If foo is in memory due to spilling a pseudo reg, this is safe,
7497 because the QImode value is in the least significant part of a
7498 slot big enough for a SImode. If foo is some other sort of
7499 memory reference, then it is impossible to reload this case,
7500 so previous passes had better make sure this never happens.
7502 Then consider a one-word union which has SImode and one of its
7503 members is a float, being fetched as (SUBREG:SF union:SI).
7504 We must fetch that as SFmode because we could be loading into
7505 a float-only register. In this case OLD's mode is correct.
7507 Consider an immediate integer: it has VOIDmode. Here we need
7508 to get a mode from something else.
7510 In some cases, there is a fourth mode, the operand's
7511 containing mode. If the insn specifies a containing mode for
7512 this operand, it overrides all others.
7514 I am not sure whether the algorithm here is always right,
7515 but it does the right things in those cases. */
7517 mode
= GET_MODE (old
);
7518 if (mode
== VOIDmode
)
7521 /* We cannot use gen_lowpart_common since it can do the wrong thing
7522 when REG_RTX has a multi-word mode. Note that REG_RTX must
7523 always be a REG here. */
7524 if (GET_MODE (reg_rtx
) != mode
)
7525 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7527 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7530 /* AUTO_INC reloads need to be handled even if inherited. We got an
7531 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7532 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7533 && ! rtx_equal_p (reg_rtx
, old
)
7535 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7537 /* When inheriting a wider reload, we have a MEM in rl->in,
7538 e.g. inheriting a SImode output reload for
7539 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7540 if (optimize
&& reload_inherited
[j
] && rl
->in
7542 && MEM_P (rl
->in_reg
)
7543 && reload_spill_index
[j
] >= 0
7544 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7545 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7547 /* If we are reloading a register that was recently stored in with an
7548 output-reload, see if we can prove there was
7549 actually no need to store the old value in it. */
7552 && (reload_inherited
[j
] || reload_override_in
[j
])
7555 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7557 /* There doesn't seem to be any reason to restrict this to pseudos
7558 and doing so loses in the case where we are copying from a
7559 register of the wrong class. */
7560 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7562 /* The insn might have already some references to stackslots
7563 replaced by MEMs, while reload_out_reg still names the
7565 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7566 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7567 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7570 /* Do output reloading for reload RL, which is for the insn described by
7571 CHAIN and has the number J.
7572 ??? At some point we need to support handling output reloads of
7573 JUMP_INSNs or insns that set cc0. */
7575 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7578 rtx insn
= chain
->insn
;
7579 /* If this is an output reload that stores something that is
7580 not loaded in this same reload, see if we can eliminate a previous
7582 rtx pseudo
= rl
->out_reg
;
7583 rtx reg_rtx
= rl
->reg_rtx
;
7585 if (rl
->out
&& reg_rtx
)
7587 enum machine_mode mode
;
7589 /* Determine the mode to reload in.
7590 See comments above (for input reloading). */
7591 mode
= GET_MODE (rl
->out
);
7592 if (mode
== VOIDmode
)
7594 /* VOIDmode should never happen for an output. */
7595 if (asm_noperands (PATTERN (insn
)) < 0)
7596 /* It's the compiler's fault. */
7597 fatal_insn ("VOIDmode on an output", insn
);
7598 error_for_asm (insn
, "output operand is constant in %<asm%>");
7599 /* Prevent crash--use something we know is valid. */
7601 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7603 if (GET_MODE (reg_rtx
) != mode
)
7604 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7606 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7611 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7612 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7613 && reg_last_reload_reg
[REGNO (pseudo
)])
7615 int pseudo_no
= REGNO (pseudo
);
7616 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7618 /* We don't need to test full validity of last_regno for
7619 inherit here; we only want to know if the store actually
7620 matches the pseudo. */
7621 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7622 && reg_reloaded_contents
[last_regno
] == pseudo_no
7623 && spill_reg_store
[last_regno
]
7624 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7625 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7631 || rtx_equal_p (old
, reg_rtx
))
7634 /* An output operand that dies right away does need a reload,
7635 but need not be copied from it. Show the new location in the
7637 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7638 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7640 XEXP (note
, 0) = reg_rtx
;
7643 /* Likewise for a SUBREG of an operand that dies. */
7644 else if (GET_CODE (old
) == SUBREG
7645 && REG_P (SUBREG_REG (old
))
7646 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7649 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7652 else if (GET_CODE (old
) == SCRATCH
)
7653 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7654 but we don't want to make an output reload. */
7657 /* If is a JUMP_INSN, we can't support output reloads yet. */
7658 gcc_assert (NONJUMP_INSN_P (insn
));
7660 emit_output_reload_insns (chain
, rld
+ j
, j
);
7663 /* A reload copies values of MODE from register SRC to register DEST.
7664 Return true if it can be treated for inheritance purposes like a
7665 group of reloads, each one reloading a single hard register. The
7666 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7667 occupy the same number of hard registers. */
7670 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7671 int src ATTRIBUTE_UNUSED
,
7672 enum machine_mode mode ATTRIBUTE_UNUSED
)
7674 #ifdef CANNOT_CHANGE_MODE_CLASS
7675 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
7676 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
7682 /* Output insns to reload values in and out of the chosen reload regs. */
7685 emit_reload_insns (struct insn_chain
*chain
)
7687 rtx insn
= chain
->insn
;
7691 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7693 for (j
= 0; j
< reload_n_operands
; j
++)
7694 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7695 = inpaddr_address_reload_insns
[j
]
7696 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7697 = outaddr_address_reload_insns
[j
]
7698 = other_output_reload_insns
[j
] = 0;
7699 other_input_address_reload_insns
= 0;
7700 other_input_reload_insns
= 0;
7701 operand_reload_insns
= 0;
7702 other_operand_reload_insns
= 0;
7704 /* Dump reloads into the dump file. */
7707 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7708 debug_reload_to_stream (dump_file
);
7711 /* Now output the instructions to copy the data into and out of the
7712 reload registers. Do these in the order that the reloads were reported,
7713 since reloads of base and index registers precede reloads of operands
7714 and the operands may need the base and index registers reloaded. */
7716 for (j
= 0; j
< n_reloads
; j
++)
7718 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
7722 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
7723 new_spill_reg_store
[i
] = 0;
7726 do_input_reload (chain
, rld
+ j
, j
);
7727 do_output_reload (chain
, rld
+ j
, j
);
7730 /* Now write all the insns we made for reloads in the order expected by
7731 the allocation functions. Prior to the insn being reloaded, we write
7732 the following reloads:
7734 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7736 RELOAD_OTHER reloads.
7738 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7739 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7740 RELOAD_FOR_INPUT reload for the operand.
7742 RELOAD_FOR_OPADDR_ADDRS reloads.
7744 RELOAD_FOR_OPERAND_ADDRESS reloads.
7746 After the insn being reloaded, we write the following:
7748 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7749 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7750 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7751 reloads for the operand. The RELOAD_OTHER output reloads are
7752 output in descending order by reload number. */
7754 emit_insn_before (other_input_address_reload_insns
, insn
);
7755 emit_insn_before (other_input_reload_insns
, insn
);
7757 for (j
= 0; j
< reload_n_operands
; j
++)
7759 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
7760 emit_insn_before (input_address_reload_insns
[j
], insn
);
7761 emit_insn_before (input_reload_insns
[j
], insn
);
7764 emit_insn_before (other_operand_reload_insns
, insn
);
7765 emit_insn_before (operand_reload_insns
, insn
);
7767 for (j
= 0; j
< reload_n_operands
; j
++)
7769 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
7770 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
7771 x
= emit_insn_after (output_reload_insns
[j
], x
);
7772 emit_insn_after (other_output_reload_insns
[j
], x
);
7775 /* For all the spill regs newly reloaded in this instruction,
7776 record what they were reloaded from, so subsequent instructions
7777 can inherit the reloads.
7779 Update spill_reg_store for the reloads of this insn.
7780 Copy the elements that were updated in the loop above. */
7782 for (j
= 0; j
< n_reloads
; j
++)
7784 int r
= reload_order
[j
];
7785 int i
= reload_spill_index
[r
];
7787 /* If this is a non-inherited input reload from a pseudo, we must
7788 clear any memory of a previous store to the same pseudo. Only do
7789 something if there will not be an output reload for the pseudo
7791 if (rld
[r
].in_reg
!= 0
7792 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7794 rtx reg
= rld
[r
].in_reg
;
7796 if (GET_CODE (reg
) == SUBREG
)
7797 reg
= SUBREG_REG (reg
);
7800 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7801 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
7803 int nregno
= REGNO (reg
);
7805 if (reg_last_reload_reg
[nregno
])
7807 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7809 if (reg_reloaded_contents
[last_regno
] == nregno
)
7810 spill_reg_store
[last_regno
] = 0;
7815 /* I is nonneg if this reload used a register.
7816 If rld[r].reg_rtx is 0, this is an optional reload
7817 that we opted to ignore. */
7819 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7821 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
7824 /* For a multi register reload, we need to check if all or part
7825 of the value lives to the end. */
7826 for (k
= 0; k
< nr
; k
++)
7827 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7828 rld
[r
].when_needed
))
7829 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7831 /* Maybe the spill reg contains a copy of reload_out. */
7833 && (REG_P (rld
[r
].out
)
7837 || REG_P (rld
[r
].out_reg
)))
7840 enum machine_mode mode
;
7843 reg
= reload_reg_rtx_for_output
[r
];
7844 mode
= GET_MODE (reg
);
7845 regno
= REGNO (reg
);
7846 nregs
= hard_regno_nregs
[regno
][mode
];
7847 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
7848 rld
[r
].when_needed
))
7850 rtx out
= (REG_P (rld
[r
].out
)
7854 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7855 int out_regno
= REGNO (out
);
7856 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
7857 : hard_regno_nregs
[out_regno
][mode
]);
7860 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
7861 spill_reg_stored_to
[regno
] = out
;
7862 reg_last_reload_reg
[out_regno
] = reg
;
7864 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
7865 && nregs
== out_nregs
7866 && inherit_piecemeal_p (out_regno
, regno
, mode
));
7868 /* If OUT_REGNO is a hard register, it may occupy more than
7869 one register. If it does, say what is in the
7870 rest of the registers assuming that both registers
7871 agree on how many words the object takes. If not,
7872 invalidate the subsequent registers. */
7874 if (HARD_REGISTER_NUM_P (out_regno
))
7875 for (k
= 1; k
< out_nregs
; k
++)
7876 reg_last_reload_reg
[out_regno
+ k
]
7877 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
7879 /* Now do the inverse operation. */
7880 for (k
= 0; k
< nregs
; k
++)
7882 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
7883 reg_reloaded_contents
[regno
+ k
]
7884 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
7887 reg_reloaded_insn
[regno
+ k
] = insn
;
7888 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
7889 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
7890 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7893 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7898 /* Maybe the spill reg contains a copy of reload_in. Only do
7899 something if there will not be an output reload for
7900 the register being reloaded. */
7901 else if (rld
[r
].out_reg
== 0
7903 && ((REG_P (rld
[r
].in
)
7904 && !HARD_REGISTER_P (rld
[r
].in
)
7905 && !REGNO_REG_SET_P (®_has_output_reload
,
7907 || (REG_P (rld
[r
].in_reg
)
7908 && !REGNO_REG_SET_P (®_has_output_reload
,
7909 REGNO (rld
[r
].in_reg
))))
7910 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
7913 enum machine_mode mode
;
7916 reg
= reload_reg_rtx_for_input
[r
];
7917 mode
= GET_MODE (reg
);
7918 regno
= REGNO (reg
);
7919 nregs
= hard_regno_nregs
[regno
][mode
];
7920 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
7921 rld
[r
].when_needed
))
7928 if (REG_P (rld
[r
].in
)
7929 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7931 else if (REG_P (rld
[r
].in_reg
))
7934 in
= XEXP (rld
[r
].in_reg
, 0);
7935 in_regno
= REGNO (in
);
7937 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
7938 : hard_regno_nregs
[in_regno
][mode
]);
7940 reg_last_reload_reg
[in_regno
] = reg
;
7942 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
7943 && nregs
== in_nregs
7944 && inherit_piecemeal_p (regno
, in_regno
, mode
));
7946 if (HARD_REGISTER_NUM_P (in_regno
))
7947 for (k
= 1; k
< in_nregs
; k
++)
7948 reg_last_reload_reg
[in_regno
+ k
]
7949 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
7951 /* Unless we inherited this reload, show we haven't
7952 recently done a store.
7953 Previous stores of inherited auto_inc expressions
7954 also have to be discarded. */
7955 if (! reload_inherited
[r
]
7956 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7957 spill_reg_store
[regno
] = 0;
7959 for (k
= 0; k
< nregs
; k
++)
7961 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
7962 reg_reloaded_contents
[regno
+ k
]
7963 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
7966 reg_reloaded_insn
[regno
+ k
] = insn
;
7967 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
7968 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
7969 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7972 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7979 /* The following if-statement was #if 0'd in 1.34 (or before...).
7980 It's reenabled in 1.35 because supposedly nothing else
7981 deals with this problem. */
7983 /* If a register gets output-reloaded from a non-spill register,
7984 that invalidates any previous reloaded copy of it.
7985 But forget_old_reloads_1 won't get to see it, because
7986 it thinks only about the original insn. So invalidate it here.
7987 Also do the same thing for RELOAD_OTHER constraints where the
7988 output is discarded. */
7990 && ((rld
[r
].out
!= 0
7991 && (REG_P (rld
[r
].out
)
7992 || (MEM_P (rld
[r
].out
)
7993 && REG_P (rld
[r
].out_reg
))))
7994 || (rld
[r
].out
== 0 && rld
[r
].out_reg
7995 && REG_P (rld
[r
].out_reg
))))
7997 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
7998 ? rld
[r
].out
: rld
[r
].out_reg
);
7999 int out_regno
= REGNO (out
);
8000 enum machine_mode mode
= GET_MODE (out
);
8002 /* REG_RTX is now set or clobbered by the main instruction.
8003 As the comment above explains, forget_old_reloads_1 only
8004 sees the original instruction, and there is no guarantee
8005 that the original instruction also clobbered REG_RTX.
8006 For example, if find_reloads sees that the input side of
8007 a matched operand pair dies in this instruction, it may
8008 use the input register as the reload register.
8010 Calling forget_old_reloads_1 is a waste of effort if
8011 REG_RTX is also the output register.
8013 If we know that REG_RTX holds the value of a pseudo
8014 register, the code after the call will record that fact. */
8015 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8016 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8018 if (!HARD_REGISTER_NUM_P (out_regno
))
8020 rtx src_reg
, store_insn
= NULL_RTX
;
8022 reg_last_reload_reg
[out_regno
] = 0;
8024 /* If we can find a hard register that is stored, record
8025 the storing insn so that we may delete this insn with
8026 delete_output_reload. */
8027 src_reg
= reload_reg_rtx_for_output
[r
];
8029 /* If this is an optional reload, try to find the source reg
8030 from an input reload. */
8033 rtx set
= single_set (insn
);
8034 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8038 src_reg
= SET_SRC (set
);
8040 for (k
= 0; k
< n_reloads
; k
++)
8042 if (rld
[k
].in
== src_reg
)
8044 src_reg
= reload_reg_rtx_for_input
[k
];
8051 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8052 if (src_reg
&& REG_P (src_reg
)
8053 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8055 int src_regno
, src_nregs
, k
;
8058 gcc_assert (GET_MODE (src_reg
) == mode
);
8059 src_regno
= REGNO (src_reg
);
8060 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8061 /* The place where to find a death note varies with
8062 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8063 necessarily checked exactly in the code that moves
8064 notes, so just check both locations. */
8065 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8066 if (! note
&& store_insn
)
8067 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8068 for (k
= 0; k
< src_nregs
; k
++)
8070 spill_reg_store
[src_regno
+ k
] = store_insn
;
8071 spill_reg_stored_to
[src_regno
+ k
] = out
;
8072 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8073 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8074 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8075 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8076 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8078 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8081 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8083 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8085 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8087 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8089 reg_last_reload_reg
[out_regno
] = src_reg
;
8090 /* We have to set reg_has_output_reload here, or else
8091 forget_old_reloads_1 will clear reg_last_reload_reg
8093 SET_REGNO_REG_SET (®_has_output_reload
,
8099 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8101 for (k
= 0; k
< out_nregs
; k
++)
8102 reg_last_reload_reg
[out_regno
+ k
] = 0;
8106 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8109 /* Go through the motions to emit INSN and test if it is strictly valid.
8110 Return the emitted insn if valid, else return NULL. */
8113 emit_insn_if_valid_for_reload (rtx insn
)
8115 rtx last
= get_last_insn ();
8118 insn
= emit_insn (insn
);
8119 code
= recog_memoized (insn
);
8123 extract_insn (insn
);
8124 /* We want constrain operands to treat this insn strictly in its
8125 validity determination, i.e., the way it would after reload has
8127 if (constrain_operands (1))
8131 delete_insns_since (last
);
8135 /* Emit code to perform a reload from IN (which may be a reload register) to
8136 OUT (which may also be a reload register). IN or OUT is from operand
8137 OPNUM with reload type TYPE.
8139 Returns first insn emitted. */
8142 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8144 rtx last
= get_last_insn ();
8147 /* If IN is a paradoxical SUBREG, remove it and try to put the
8148 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8149 if (GET_CODE (in
) == SUBREG
8150 && (GET_MODE_SIZE (GET_MODE (in
))
8151 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
8152 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
8153 in
= SUBREG_REG (in
), out
= tem
;
8154 else if (GET_CODE (out
) == SUBREG
8155 && (GET_MODE_SIZE (GET_MODE (out
))
8156 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
8157 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
8158 out
= SUBREG_REG (out
), in
= tem
;
8160 /* How to do this reload can get quite tricky. Normally, we are being
8161 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8162 register that didn't get a hard register. In that case we can just
8163 call emit_move_insn.
8165 We can also be asked to reload a PLUS that adds a register or a MEM to
8166 another register, constant or MEM. This can occur during frame pointer
8167 elimination and while reloading addresses. This case is handled by
8168 trying to emit a single insn to perform the add. If it is not valid,
8169 we use a two insn sequence.
8171 Or we can be asked to reload an unary operand that was a fragment of
8172 an addressing mode, into a register. If it isn't recognized as-is,
8173 we try making the unop operand and the reload-register the same:
8174 (set reg:X (unop:X expr:Y))
8175 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8177 Finally, we could be called to handle an 'o' constraint by putting
8178 an address into a register. In that case, we first try to do this
8179 with a named pattern of "reload_load_address". If no such pattern
8180 exists, we just emit a SET insn and hope for the best (it will normally
8181 be valid on machines that use 'o').
8183 This entire process is made complex because reload will never
8184 process the insns we generate here and so we must ensure that
8185 they will fit their constraints and also by the fact that parts of
8186 IN might be being reloaded separately and replaced with spill registers.
8187 Because of this, we are, in some sense, just guessing the right approach
8188 here. The one listed above seems to work.
8190 ??? At some point, this whole thing needs to be rethought. */
8192 if (GET_CODE (in
) == PLUS
8193 && (REG_P (XEXP (in
, 0))
8194 || GET_CODE (XEXP (in
, 0)) == SUBREG
8195 || MEM_P (XEXP (in
, 0)))
8196 && (REG_P (XEXP (in
, 1))
8197 || GET_CODE (XEXP (in
, 1)) == SUBREG
8198 || CONSTANT_P (XEXP (in
, 1))
8199 || MEM_P (XEXP (in
, 1))))
8201 /* We need to compute the sum of a register or a MEM and another
8202 register, constant, or MEM, and put it into the reload
8203 register. The best possible way of doing this is if the machine
8204 has a three-operand ADD insn that accepts the required operands.
8206 The simplest approach is to try to generate such an insn and see if it
8207 is recognized and matches its constraints. If so, it can be used.
8209 It might be better not to actually emit the insn unless it is valid,
8210 but we need to pass the insn as an operand to `recog' and
8211 `extract_insn' and it is simpler to emit and then delete the insn if
8212 not valid than to dummy things up. */
8214 rtx op0
, op1
, tem
, insn
;
8217 op0
= find_replacement (&XEXP (in
, 0));
8218 op1
= find_replacement (&XEXP (in
, 1));
8220 /* Since constraint checking is strict, commutativity won't be
8221 checked, so we need to do that here to avoid spurious failure
8222 if the add instruction is two-address and the second operand
8223 of the add is the same as the reload reg, which is frequently
8224 the case. If the insn would be A = B + A, rearrange it so
8225 it will be A = A + B as constrain_operands expects. */
8227 if (REG_P (XEXP (in
, 1))
8228 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8229 tem
= op0
, op0
= op1
, op1
= tem
;
8231 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8232 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8234 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8238 /* If that failed, we must use a conservative two-insn sequence.
8240 Use a move to copy one operand into the reload register. Prefer
8241 to reload a constant, MEM or pseudo since the move patterns can
8242 handle an arbitrary operand. If OP1 is not a constant, MEM or
8243 pseudo and OP1 is not a valid operand for an add instruction, then
8246 After reloading one of the operands into the reload register, add
8247 the reload register to the output register.
8249 If there is another way to do this for a specific machine, a
8250 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8253 code
= (int) optab_handler (add_optab
, GET_MODE (out
))->insn_code
;
8255 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8257 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8258 || (code
!= CODE_FOR_nothing
8259 && ! ((*insn_data
[code
].operand
[2].predicate
)
8260 (op1
, insn_data
[code
].operand
[2].mode
))))
8261 tem
= op0
, op0
= op1
, op1
= tem
;
8263 gen_reload (out
, op0
, opnum
, type
);
8265 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8266 This fixes a problem on the 32K where the stack pointer cannot
8267 be used as an operand of an add insn. */
8269 if (rtx_equal_p (op0
, op1
))
8272 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8275 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8276 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8280 /* If that failed, copy the address register to the reload register.
8281 Then add the constant to the reload register. */
8283 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8284 gen_reload (out
, op1
, opnum
, type
);
8285 insn
= emit_insn (gen_add2_insn (out
, op0
));
8286 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8289 #ifdef SECONDARY_MEMORY_NEEDED
8290 /* If we need a memory location to do the move, do it that way. */
8291 else if ((REG_P (in
)
8292 || (GET_CODE (in
) == SUBREG
&& REG_P (SUBREG_REG (in
))))
8293 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
8295 || (GET_CODE (out
) == SUBREG
&& REG_P (SUBREG_REG (out
))))
8296 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
8297 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
8298 REGNO_REG_CLASS (reg_or_subregno (out
)),
8301 /* Get the memory to use and rewrite both registers to its mode. */
8302 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8304 if (GET_MODE (loc
) != GET_MODE (out
))
8305 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
8307 if (GET_MODE (loc
) != GET_MODE (in
))
8308 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
8310 gen_reload (loc
, in
, opnum
, type
);
8311 gen_reload (out
, loc
, opnum
, type
);
8314 else if (REG_P (out
) && UNARY_P (in
))
8321 op1
= find_replacement (&XEXP (in
, 0));
8322 if (op1
!= XEXP (in
, 0))
8323 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8325 /* First, try a plain SET. */
8326 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8330 /* If that failed, move the inner operand to the reload
8331 register, and try the same unop with the inner expression
8332 replaced with the reload register. */
8334 if (GET_MODE (op1
) != GET_MODE (out
))
8335 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8339 gen_reload (out_moded
, op1
, opnum
, type
);
8342 = gen_rtx_SET (VOIDmode
, out
,
8343 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8345 insn
= emit_insn_if_valid_for_reload (insn
);
8348 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8352 fatal_insn ("Failure trying to reload:", set
);
8354 /* If IN is a simple operand, use gen_move_insn. */
8355 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8357 tem
= emit_insn (gen_move_insn (out
, in
));
8358 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8359 mark_jump_label (in
, tem
, 0);
8362 #ifdef HAVE_reload_load_address
8363 else if (HAVE_reload_load_address
)
8364 emit_insn (gen_reload_load_address (out
, in
));
8367 /* Otherwise, just write (set OUT IN) and hope for the best. */
8369 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8371 /* Return the first insn emitted.
8372 We can not just return get_last_insn, because there may have
8373 been multiple instructions emitted. Also note that gen_move_insn may
8374 emit more than one insn itself, so we can not assume that there is one
8375 insn emitted per emit_insn_before call. */
8377 return last
? NEXT_INSN (last
) : get_insns ();
8380 /* Delete a previously made output-reload whose result we now believe
8381 is not needed. First we double-check.
8383 INSN is the insn now being processed.
8384 LAST_RELOAD_REG is the hard register number for which we want to delete
8385 the last output reload.
8386 J is the reload-number that originally used REG. The caller has made
8387 certain that reload J doesn't use REG any longer for input.
8388 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8391 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8393 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8394 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8397 int n_inherited
= 0;
8401 /* It is possible that this reload has been only used to set another reload
8402 we eliminated earlier and thus deleted this instruction too. */
8403 if (INSN_DELETED_P (output_reload_insn
))
8406 /* Get the raw pseudo-register referred to. */
8408 while (GET_CODE (reg
) == SUBREG
)
8409 reg
= SUBREG_REG (reg
);
8410 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
8412 /* This is unsafe if the operand occurs more often in the current
8413 insn than it is inherited. */
8414 for (k
= n_reloads
- 1; k
>= 0; k
--)
8416 rtx reg2
= rld
[k
].in
;
8419 if (MEM_P (reg2
) || reload_override_in
[k
])
8420 reg2
= rld
[k
].in_reg
;
8422 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8423 reg2
= XEXP (rld
[k
].in_reg
, 0);
8425 while (GET_CODE (reg2
) == SUBREG
)
8426 reg2
= SUBREG_REG (reg2
);
8427 if (rtx_equal_p (reg2
, reg
))
8429 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8435 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8436 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8437 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8440 n_occurrences
+= count_occurrences (PATTERN (insn
),
8441 eliminate_regs (substed
, 0,
8443 for (i1
= reg_equiv_alt_mem_list
[REGNO (reg
)]; i1
; i1
= XEXP (i1
, 1))
8445 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8446 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8448 if (n_occurrences
> n_inherited
)
8451 /* If the pseudo-reg we are reloading is no longer referenced
8452 anywhere between the store into it and here,
8453 and we're within the same basic block, then the value can only
8454 pass through the reload reg and end up here.
8455 Otherwise, give up--return. */
8456 for (i1
= NEXT_INSN (output_reload_insn
);
8457 i1
!= insn
; i1
= NEXT_INSN (i1
))
8459 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8461 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8462 && reg_mentioned_p (reg
, PATTERN (i1
)))
8464 /* If this is USE in front of INSN, we only have to check that
8465 there are no more references than accounted for by inheritance. */
8466 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8468 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8469 i1
= NEXT_INSN (i1
);
8471 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8477 /* We will be deleting the insn. Remove the spill reg information. */
8478 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8480 spill_reg_store
[last_reload_reg
+ k
] = 0;
8481 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8484 /* The caller has already checked that REG dies or is set in INSN.
8485 It has also checked that we are optimizing, and thus some
8486 inaccuracies in the debugging information are acceptable.
8487 So we could just delete output_reload_insn. But in some cases
8488 we can improve the debugging information without sacrificing
8489 optimization - maybe even improving the code: See if the pseudo
8490 reg has been completely replaced with reload regs. If so, delete
8491 the store insn and forget we had a stack slot for the pseudo. */
8492 if (rld
[j
].out
!= rld
[j
].in
8493 && REG_N_DEATHS (REGNO (reg
)) == 1
8494 && REG_N_SETS (REGNO (reg
)) == 1
8495 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8496 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8500 /* We know that it was used only between here and the beginning of
8501 the current basic block. (We also know that the last use before
8502 INSN was the output reload we are thinking of deleting, but never
8503 mind that.) Search that range; see if any ref remains. */
8504 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8506 rtx set
= single_set (i2
);
8508 /* Uses which just store in the pseudo don't count,
8509 since if they are the only uses, they are dead. */
8510 if (set
!= 0 && SET_DEST (set
) == reg
)
8515 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8516 && reg_mentioned_p (reg
, PATTERN (i2
)))
8518 /* Some other ref remains; just delete the output reload we
8520 delete_address_reloads (output_reload_insn
, insn
);
8521 delete_insn (output_reload_insn
);
8526 /* Delete the now-dead stores into this pseudo. Note that this
8527 loop also takes care of deleting output_reload_insn. */
8528 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8530 rtx set
= single_set (i2
);
8532 if (set
!= 0 && SET_DEST (set
) == reg
)
8534 delete_address_reloads (i2
, insn
);
8542 /* For the debugging info, say the pseudo lives in this reload reg. */
8543 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8544 if (flag_ira
&& optimize
)
8545 /* Inform IRA about the change. */
8546 ira_mark_allocation_change (REGNO (reg
));
8547 alter_reg (REGNO (reg
), -1, false);
8551 delete_address_reloads (output_reload_insn
, insn
);
8552 delete_insn (output_reload_insn
);
8556 /* We are going to delete DEAD_INSN. Recursively delete loads of
8557 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8558 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8560 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8562 rtx set
= single_set (dead_insn
);
8563 rtx set2
, dst
, prev
, next
;
8566 rtx dst
= SET_DEST (set
);
8568 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8570 /* If we deleted the store from a reloaded post_{in,de}c expression,
8571 we can delete the matching adds. */
8572 prev
= PREV_INSN (dead_insn
);
8573 next
= NEXT_INSN (dead_insn
);
8574 if (! prev
|| ! next
)
8576 set
= single_set (next
);
8577 set2
= single_set (prev
);
8579 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8580 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
8581 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
8583 dst
= SET_DEST (set
);
8584 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8585 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8586 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8587 || (INTVAL (XEXP (SET_SRC (set
), 1))
8588 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8590 delete_related_insns (prev
);
8591 delete_related_insns (next
);
8594 /* Subfunction of delete_address_reloads: process registers found in X. */
8596 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8598 rtx prev
, set
, dst
, i2
;
8600 enum rtx_code code
= GET_CODE (x
);
8604 const char *fmt
= GET_RTX_FORMAT (code
);
8605 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8608 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8609 else if (fmt
[i
] == 'E')
8611 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8612 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8619 if (spill_reg_order
[REGNO (x
)] < 0)
8622 /* Scan backwards for the insn that sets x. This might be a way back due
8624 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8626 code
= GET_CODE (prev
);
8627 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8631 if (reg_set_p (x
, PATTERN (prev
)))
8633 if (reg_referenced_p (x
, PATTERN (prev
)))
8636 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8638 /* Check that PREV only sets the reload register. */
8639 set
= single_set (prev
);
8642 dst
= SET_DEST (set
);
8644 || ! rtx_equal_p (dst
, x
))
8646 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8648 /* Check if DST was used in a later insn -
8649 it might have been inherited. */
8650 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8656 if (reg_referenced_p (dst
, PATTERN (i2
)))
8658 /* If there is a reference to the register in the current insn,
8659 it might be loaded in a non-inherited reload. If no other
8660 reload uses it, that means the register is set before
8662 if (i2
== current_insn
)
8664 for (j
= n_reloads
- 1; j
>= 0; j
--)
8665 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8666 || reload_override_in
[j
] == dst
)
8668 for (j
= n_reloads
- 1; j
>= 0; j
--)
8669 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8678 /* If DST is still live at CURRENT_INSN, check if it is used for
8679 any reload. Note that even if CURRENT_INSN sets DST, we still
8680 have to check the reloads. */
8681 if (i2
== current_insn
)
8683 for (j
= n_reloads
- 1; j
>= 0; j
--)
8684 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8685 || reload_override_in
[j
] == dst
)
8687 /* ??? We can't finish the loop here, because dst might be
8688 allocated to a pseudo in this block if no reload in this
8689 block needs any of the classes containing DST - see
8690 spill_hard_reg. There is no easy way to tell this, so we
8691 have to scan till the end of the basic block. */
8693 if (reg_set_p (dst
, PATTERN (i2
)))
8697 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8698 reg_reloaded_contents
[REGNO (dst
)] = -1;
8702 /* Output reload-insns to reload VALUE into RELOADREG.
8703 VALUE is an autoincrement or autodecrement RTX whose operand
8704 is a register or memory location;
8705 so reloading involves incrementing that location.
8706 IN is either identical to VALUE, or some cheaper place to reload from.
8708 INC_AMOUNT is the number to increment or decrement by (always positive).
8709 This cannot be deduced from VALUE.
8711 Return the instruction that stores into RELOADREG. */
8714 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
8716 /* REG or MEM to be copied and incremented. */
8717 rtx incloc
= find_replacement (&XEXP (value
, 0));
8718 /* Nonzero if increment after copying. */
8719 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
8720 || GET_CODE (value
) == POST_MODIFY
);
8726 rtx real_in
= in
== value
? incloc
: in
;
8728 /* No hard register is equivalent to this register after
8729 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8730 we could inc/dec that register as well (maybe even using it for
8731 the source), but I'm not sure it's worth worrying about. */
8733 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8735 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
8737 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
8738 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
8742 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8743 inc_amount
= -inc_amount
;
8745 inc
= GEN_INT (inc_amount
);
8748 /* If this is post-increment, first copy the location to the reload reg. */
8749 if (post
&& real_in
!= reloadreg
)
8750 emit_insn (gen_move_insn (reloadreg
, real_in
));
8754 /* See if we can directly increment INCLOC. Use a method similar to
8755 that in gen_reload. */
8757 last
= get_last_insn ();
8758 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8759 gen_rtx_PLUS (GET_MODE (incloc
),
8762 code
= recog_memoized (add_insn
);
8765 extract_insn (add_insn
);
8766 if (constrain_operands (1))
8768 /* If this is a pre-increment and we have incremented the value
8769 where it lives, copy the incremented value to RELOADREG to
8770 be used as an address. */
8773 emit_insn (gen_move_insn (reloadreg
, incloc
));
8778 delete_insns_since (last
);
8781 /* If couldn't do the increment directly, must increment in RELOADREG.
8782 The way we do this depends on whether this is pre- or post-increment.
8783 For pre-increment, copy INCLOC to the reload register, increment it
8784 there, then save back. */
8788 if (in
!= reloadreg
)
8789 emit_insn (gen_move_insn (reloadreg
, real_in
));
8790 emit_insn (gen_add2_insn (reloadreg
, inc
));
8791 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8796 Because this might be a jump insn or a compare, and because RELOADREG
8797 may not be available after the insn in an input reload, we must do
8798 the incrementation before the insn being reloaded for.
8800 We have already copied IN to RELOADREG. Increment the copy in
8801 RELOADREG, save that back, then decrement RELOADREG so it has
8802 the original value. */
8804 emit_insn (gen_add2_insn (reloadreg
, inc
));
8805 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8806 if (GET_CODE (inc
) == CONST_INT
)
8807 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
8809 emit_insn (gen_sub2_insn (reloadreg
, inc
));
8817 add_auto_inc_notes (rtx insn
, rtx x
)
8819 enum rtx_code code
= GET_CODE (x
);
8823 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
8825 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
8829 /* Scan all the operand sub-expressions. */
8830 fmt
= GET_RTX_FORMAT (code
);
8831 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8834 add_auto_inc_notes (insn
, XEXP (x
, i
));
8835 else if (fmt
[i
] == 'E')
8836 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8837 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
8842 /* Copy EH notes from an insn to its reloads. */
8844 copy_eh_notes (rtx insn
, rtx x
)
8846 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8849 for (; x
!= 0; x
= NEXT_INSN (x
))
8851 if (may_trap_p (PATTERN (x
)))
8852 add_reg_note (x
, REG_EH_REGION
, XEXP (eh_note
, 0));
8857 /* This is used by reload pass, that does emit some instructions after
8858 abnormal calls moving basic block end, but in fact it wants to emit
8859 them on the edge. Looks for abnormal call edges, find backward the
8860 proper call and fix the damage.
8862 Similar handle instructions throwing exceptions internally. */
8864 fixup_abnormal_edges (void)
8866 bool inserted
= false;
8874 /* Look for cases we are interested in - calls or instructions causing
8876 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8878 if (e
->flags
& EDGE_ABNORMAL_CALL
)
8880 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
8881 == (EDGE_ABNORMAL
| EDGE_EH
))
8884 if (e
&& !CALL_P (BB_END (bb
))
8885 && !can_throw_internal (BB_END (bb
)))
8889 /* Get past the new insns generated. Allow notes, as the insns
8890 may be already deleted. */
8892 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
8893 && !can_throw_internal (insn
)
8894 && insn
!= BB_HEAD (bb
))
8895 insn
= PREV_INSN (insn
);
8897 if (CALL_P (insn
) || can_throw_internal (insn
))
8901 stop
= NEXT_INSN (BB_END (bb
));
8903 insn
= NEXT_INSN (insn
);
8905 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8906 if (e
->flags
& EDGE_FALLTHRU
)
8909 while (insn
&& insn
!= stop
)
8911 next
= NEXT_INSN (insn
);
8916 /* Sometimes there's still the return value USE.
8917 If it's placed after a trapping call (i.e. that
8918 call is the last insn anyway), we have no fallthru
8919 edge. Simply delete this use and don't try to insert
8920 on the non-existent edge. */
8921 if (GET_CODE (PATTERN (insn
)) != USE
)
8923 /* We're not deleting it, we're moving it. */
8924 INSN_DELETED_P (insn
) = 0;
8925 PREV_INSN (insn
) = NULL_RTX
;
8926 NEXT_INSN (insn
) = NULL_RTX
;
8928 insert_insn_on_edge (insn
, e
);
8932 else if (!BARRIER_P (insn
))
8933 set_block_for_insn (insn
, NULL
);
8938 /* It may be that we don't find any such trapping insn. In this
8939 case we discovered quite late that the insn that had been
8940 marked as can_throw_internal in fact couldn't trap at all.
8941 So we should in fact delete the EH edges out of the block. */
8943 purge_dead_edges (bb
);
8947 /* We've possibly turned single trapping insn into multiple ones. */
8948 if (flag_non_call_exceptions
)
8951 blocks
= sbitmap_alloc (last_basic_block
);
8952 sbitmap_ones (blocks
);
8953 find_many_sub_basic_blocks (blocks
);
8954 sbitmap_free (blocks
);
8958 commit_edge_insertions ();
8960 #ifdef ENABLE_CHECKING
8961 /* Verify that we didn't turn one trapping insn into many, and that
8962 we found and corrected all of the problems wrt fixups on the
8964 verify_flow_info ();