libjava/sysdep/arm/locks.h

   1 // locks.h - Thread synchronization primitives. ARM implementation.
   2
   3 /* Copyright (C) 2007  Free Software Foundation
   4
   5    This file is part of libgcj.
   6
   7 This software is copyrighted work licensed under the terms of the
   8 Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
   9 details.  */
  10
  11 #ifndef __SYSDEP_LOCKS_H__
  12 #define __SYSDEP_LOCKS_H__
  13
  14 typedef size_t obj_addr_t;      /* Integer type big enough for object   */
  15                                 /* address.                             */
  16 #if (__ARM_EABI__ && __linux)
  17
  18 // Atomically replace *addr by new_val if it was initially equal to old.
  19 // Return true if the comparison succeeded.
  20 // Assumed to have acquire semantics, i.e. later memory operations
  21 // cannot execute before the compare_and_swap finishes.
  22 inline static bool
  23 compare_and_swap(volatile obj_addr_t *addr,
  24                  obj_addr_t old,
  25                  obj_addr_t new_val)
  26 {
  27   return __sync_bool_compare_and_swap(addr, old, new_val);
  28 }
  29
  30 // Set *addr to new_val with release semantics, i.e. making sure
  31 // that prior loads and stores complete before this
  32 // assignment.
  33 inline static void
  34 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
  35 {
  36   __sync_synchronize();
  37   *(addr) = new_val;
  38 }
  39
  40 // Compare_and_swap with release semantics instead of acquire semantics.
  41 // On many architecture, the operation makes both guarantees, so the
  42 // implementation can be the same.
  43 inline static bool
  44 compare_and_swap_release(volatile obj_addr_t *addr,
  45                          obj_addr_t old,
  46                          obj_addr_t new_val)
  47 {
  48   return __sync_bool_compare_and_swap(addr, old, new_val);
  49 }
  50
  51 // Ensure that subsequent instructions do not execute on stale
  52 // data that was loaded from memory before the barrier.
  53 // On X86, the hardware ensures that reads are properly ordered.
  54 inline static void
  55 read_barrier()
  56 {
  57   __sync_synchronize();
  58 }
  59
  60 // Ensure that prior stores to memory are completed with respect to other
  61 // processors.
  62 inline static void
  63 write_barrier()
  64 {
  65   __sync_synchronize();
  66 }
  67
  68 #else
  69
  70 /* Atomic compare and exchange.  These sequences are not actually
  71    atomic; there is a race if *ADDR != OLD_VAL and we are preempted
  72    between the two swaps.  However, they are very close to atomic, and
  73    are the best that a pre-ARMv6 implementation can do without
  74    operating system support.  LinuxThreads has been using these
  75    sequences for many years.  */
  76
  77 inline static bool
  78 compare_and_swap(volatile obj_addr_t *addr,
  79                  obj_addr_t old_val,
  80                  obj_addr_t new_val)
  81 {
  82   volatile obj_addr_t result, tmp;
  83   __asm__ ("\n"
  84            "0:  ldr     %[tmp],[%[addr]]\n"
  85            "    cmp     %[tmp],%[old_val]\n"
  86            "    movne   %[result],#0\n"
  87            "    bne     1f\n"
  88            "    swp     %[result],%[new_val],[%[addr]]\n"
  89            "    cmp     %[tmp],%[result]\n"
  90            "    swpne   %[tmp],%[result],[%[addr]]\n"
  91            "    bne     0b\n"
  92            "    mov     %[result],#1\n"
  93            "1:"
  94            : [result] "=&r" (result), [tmp] "=&r" (tmp)
  95            : [addr] "r" (addr), [new_val] "r" (new_val), [old_val] "r" (old_val)
  96            : "cc", "memory");
  97
  98   return result;
  99 }
 100
 101 inline static void
 102 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
 103 {
 104   __asm__ __volatile__("" : : : "memory");
 105   *(addr) = new_val;
 106 }
 107
 108 inline static bool
 109 compare_and_swap_release(volatile obj_addr_t *addr,
 110                          obj_addr_t old,
 111                          obj_addr_t new_val)
 112 {
 113   return compare_and_swap(addr, old, new_val);
 114 }
 115
 116 // Ensure that subsequent instructions do not execute on stale
 117 // data that was loaded from memory before the barrier.
 118 inline static void
 119 read_barrier()
 120 {
 121   __asm__ __volatile__("" : : : "memory");
 122 }
 123
 124 // Ensure that prior stores to memory are completed with respect to other
 125 // processors.
 126 inline static void
 127 write_barrier()
 128 {
 129   __asm__ __volatile__("" : : : "memory");
 130 }
 131
 132 #endif
 133 #endif