libjava/sysdep/alpha/locks.h

   1 // locks.h - Thread synchronization primitives. Alpha implementation.
   2
   3 /* Copyright (C) 2002, 2011  Free Software Foundation
   4
   5    This file is part of libgcj.
   6
   7 This software is copyrighted work licensed under the terms of the
   8 Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
   9 details.  */
  10
  11 #ifndef __SYSDEP_LOCKS_H__
  12 #define __SYSDEP_LOCKS_H__
  13
  14 /* Integer type big enough for object address.  */
  15 typedef size_t obj_addr_t;
  16
  17 // Atomically replace *addr by new_val if it was initially equal to old.
  18 // Return true if the comparison succeeded.
  19 // Assumed to have acquire semantics, i.e. later memory operations
  20 // cannot execute before the compare_and_swap finishes.
  21 inline static bool
  22 compare_and_swap(volatile obj_addr_t *addr,
  23                  obj_addr_t old,
  24                  obj_addr_t new_val)
  25 {
  26   return __sync_bool_compare_and_swap(addr, old, new_val);
  27 }
  28
  29 // Set *addr to new_val with release semantics, i.e. making sure
  30 // that prior loads and stores complete before this
  31 // assignment.
  32 inline static void
  33 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
  34 {
  35   __sync_synchronize();
  36   *(addr) = new_val;
  37 }
  38
  39 // Compare_and_swap with release semantics instead of acquire semantics.
  40 // On many architecture, the operation makes both guarantees, so the
  41 // implementation can be the same.
  42 inline static bool
  43 compare_and_swap_release(volatile obj_addr_t *addr,
  44                          obj_addr_t old,
  45                          obj_addr_t new_val)
  46 {
  47   return compare_and_swap(addr, old, new_val);
  48 }
  49
  50 // Ensure that subsequent instructions do not execute on stale
  51 // data that was loaded from memory before the barrier.
  52 inline static void
  53 read_barrier()
  54 {
  55   __asm__ __volatile__("mb" : : : "memory");
  56 }
  57
  58 // Ensure that prior stores to memory are completed with respect to other
  59 // processors.
  60 inline static void
  61 write_barrier()
  62 {
  63   __asm__ __volatile__("wmb" : : : "memory");
  64 }
  65
  66 #endif