| blob | c0cf160a868f19e229e8b00901142c5e4cc01d4c |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
69 /* Not really meaningful values, but at least something. */
70 #ifndef SIMULTANEOUS_PREFETCHES
71 #define SIMULTANEOUS_PREFETCHES 3
72 #endif
73 #ifndef PREFETCH_BLOCK
74 #define PREFETCH_BLOCK 32
75 #endif
76 #ifndef HAVE_prefetch
77 #define HAVE_prefetch 0
78 #define CODE_FOR_prefetch 0
79 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
80 #endif
82 /* Give up the prefetch optimizations once we exceed a given threshold.
83 It is unlikely that we would be able to optimize something in a loop
84 with so many detected prefetches. */
85 #define MAX_PREFETCHES 100
86 /* The number of prefetch blocks that are beneficial to fetch at once before
87 a loop with a known (and low) iteration count. */
88 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
89 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
90 since it is likely that the data are already in the cache. */
91 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
93 /* Parameterize some prefetch heuristics so they can be turned on and off
94 easily for performance testing on new architectures. These can be
95 defined in target-dependent files. */
97 /* Prefetch is worthwhile only when loads/stores are dense. */
98 #ifndef PREFETCH_ONLY_DENSE_MEM
99 #define PREFETCH_ONLY_DENSE_MEM 1
100 #endif
102 /* Define what we mean by "dense" loads and stores; This value divided by 256
103 is the minimum percentage of memory references that worth prefetching. */
104 #ifndef PREFETCH_DENSE_MEM
105 #define PREFETCH_DENSE_MEM 220
106 #endif
108 /* Do not prefetch for a loop whose iteration count is known to be low. */
109 #ifndef PREFETCH_NO_LOW_LOOPCNT
110 #define PREFETCH_NO_LOW_LOOPCNT 1
111 #endif
113 /* Define what we mean by a "low" iteration count. */
114 #ifndef PREFETCH_LOW_LOOPCNT
115 #define PREFETCH_LOW_LOOPCNT 32
116 #endif
118 /* Do not prefetch for a loop that contains a function call; such a loop is
119 probably not an internal loop. */
120 #ifndef PREFETCH_NO_CALL
121 #define PREFETCH_NO_CALL 1
122 #endif
124 /* Do not prefetch accesses with an extreme stride. */
125 #ifndef PREFETCH_NO_EXTREME_STRIDE
126 #define PREFETCH_NO_EXTREME_STRIDE 1
127 #endif
129 /* Define what we mean by an "extreme" stride. */
130 #ifndef PREFETCH_EXTREME_STRIDE
131 #define PREFETCH_EXTREME_STRIDE 4096
132 #endif
134 /* Define a limit to how far apart indices can be and still be merged
135 into a single prefetch. */
136 #ifndef PREFETCH_EXTREME_DIFFERENCE
137 #define PREFETCH_EXTREME_DIFFERENCE 4096
138 #endif
140 /* Issue prefetch instructions before the loop to fetch data to be used
141 in the first few loop iterations. */
142 #ifndef PREFETCH_BEFORE_LOOP
143 #define PREFETCH_BEFORE_LOOP 1
144 #endif
146 /* Do not handle reversed order prefetches (negative stride). */
147 #ifndef PREFETCH_NO_REVERSE_ORDER
148 #define PREFETCH_NO_REVERSE_ORDER 1
149 #endif
151 /* Prefetch even if the GIV is in conditional code. */
152 #ifndef PREFETCH_CONDITIONAL
153 #define PREFETCH_CONDITIONAL 1
154 #endif
156 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
157 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
159 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
160 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
161 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
163 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
164 ((REGNO) < FIRST_PSEUDO_REGISTER \
165 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
168 /* Vector mapping INSN_UIDs to luids.
169 The luids are like uids but increase monotonically always.
170 We use them to see whether a jump comes from outside a given loop. */
174 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
175 number the insn is contained in. */
179 /* 1 + largest uid of any insn. */
183 /* Number of loops detected in current function. Used as index to the
184 next few tables. */
188 /* Bound on pseudo register number before loop optimization.
189 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
192 /* The value to pass to the next call of reg_scan_update. */
194 \f
195 /* During the analysis of a loop, a chain of `struct movable's
196 is made to record all the movable insns found.
197 Then the entire chain can be scanned to decide which to move. */
199 struct movable
200 {
205 of any registers used within the LIBCALL. */
207 that must be moved with this one. */
210 may be adjusted when matching movables
211 that load the same value are found. */
213 including other movables that force this
214 or match this one. */
216 a low part that we should avoid changing when
217 clearing the rest of the reg. */
221 /* If PARTIAL is 1, GLOBAL means something different:
222 that the reg is live outside the range from where it is set
223 to the following label. */
227 In particular, moving it does not make it
228 invariant. */
230 load SRC, rather than copying INSN. */
232 first insn of a consecutive sets group. */
235 the original insn with a copy from that
236 pseudo, rather than deleting it. */
240 };
245 /* Forward declarations. */
260 #if 0
262 #endif
303 rtx *);
364 {
365 rtx match;
366 rtx replacement;
367 rtx insn;
370 /* Nonzero iff INSN is between START and END, inclusive. */
371 #define INSN_IN_RANGE_P(INSN, START, END) \
372 (INSN_UID (INSN) < max_uid_for_loop \
373 && INSN_LUID (INSN) >= INSN_LUID (START) \
374 && INSN_LUID (INSN) <= INSN_LUID (END))
376 /* Indirect_jump_in_function is computed once per function. */
384 \f
385 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
386 copy the value of the strength reduced giv to its original register. */
389 /* Cost of using a register, to normalize the benefits of a giv. */
392 void
394 {
400 }
401 \f
402 /* Compute the mapping from uids to luids.
403 LUIDs are numbers assigned to insns, like uids,
404 except that luids increase monotonically through the code.
405 Start at insn START and stop just before END. Assign LUIDs
406 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
407 static int
409 {
411 rtx insn;
414 {
417 /* Don't assign luids to line-number NOTEs, so that the distance in
418 luids between two insns is not affected by -g. */
422 else
423 /* Give a line number note the same luid as preceding insn. */
425 }
427 }
428 \f
429 /* Entry point of this file. Perform loop optimization
430 on the current function. F is the first insn of the function
431 and DUMPFILE is a stream for output of a trace of actions taken
432 (or 0 if none should be output). */
434 void
436 {
437 rtx insn;
452 /* Count the number of loops. */
456 {
459 max_loop_num++;
460 }
462 /* Don't waste time if no loops. */
468 /* Get size to use for tables indexed by uids.
469 Leave some space for labels allocated by find_and_verify_loops. */
475 /* Allocate storage for array of loops. */
478 /* Find and process each loop.
479 First, find them, and record them in order of their beginnings. */
482 /* Allocate and initialize auxiliary loop information. */
487 /* Now find all register lifetimes. This must be done after
488 find_and_verify_loops, because it might reorder the insns in the
489 function. */
492 /* This must occur after reg_scan so that registers created by gcse
493 will have entries in the register tables.
495 We could have added a call to reg_scan after gcse_main in toplev.c,
496 but moving this call to init_alias_analysis is more efficient. */
499 /* See if we went too far. Note that get_max_uid already returns
500 one more that the maximum uid of all insn. */
503 /* Now reset it to the actual size we need. See above. */
506 /* find_and_verify_loops has already called compute_luids, but it
507 might have rearranged code afterwards, so we need to recompute
508 the luids now. */
511 /* Don't leave gaps in uid_luid for insns that have been
512 deleted. It is possible that the first or last insn
513 using some register has been deleted by cross-jumping.
514 Make sure that uid_luid for that former insn's uid
515 points to the general area where that insn used to be. */
517 {
521 }
526 /* Determine if the function has indirect jump. On some systems
527 this prevents low overhead loop instructions from being used. */
530 /* Now scan the loops, last ones first, since this means inner ones are done
531 before outer ones. */
533 {
538 }
542 /* Clean up. */
550 }
551 \f
552 /* Returns the next insn, in execution order, after INSN. START and
553 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
554 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
555 insn-stream; it is used with loops that are entered near the
556 bottom. */
558 static rtx
560 {
564 {
566 /* Go to the top of the loop, and continue there. */
568 else
569 /* We're done. */
571 }
574 /* We're done. */
578 }
580 /* Find any register references hidden inside X and add them to
581 the dependency list DEPS. This is used to look inside CLOBBER (MEM
582 when checking whether a PARALLEL can be pulled out of a loop. */
584 static rtx
586 {
590 else
591 {
595 {
601 }
602 }
604 }
606 /* Optimize one loop described by LOOP. */
608 /* ??? Could also move memory writes out of loops if the destination address
609 is invariant, the source is invariant, the memory write is not volatile,
610 and if we can prove that no read inside the loop can read this address
611 before the write occurs. If there is a read of this address after the
612 write, then we can also mark the memory read as invariant. */
614 static void
616 {
622 rtx p;
623 /* 1 if we are scanning insns that could be executed zero times. */
625 /* 1 if we are scanning insns that might never be executed
626 due to a subroutine call which might exit before they are reached. */
628 /* Number of insns in the loop. */
632 /* The SET from an insn, if it is the only SET in the insn. */
634 /* Chain describing insns movable in current loop. */
636 /* Ratio of extra register life span we can justify
637 for saving an instruction. More if loop doesn't call subroutines
638 since in that case saving an insn makes more difference
639 and more registers are available. */
641 /* Nonzero if we are scanning instructions in a sub-loop. */
650 /* Determine whether this loop starts with a jump down to a test at
651 the end. This will occur for a small number of loops with a test
652 that is too complex to duplicate in front of the loop.
654 We search for the first insn or label in the loop, skipping NOTEs.
655 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
656 (because we might have a loop executed only once that contains a
657 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
658 (in case we have a degenerate loop).
660 Note that if we mistakenly think that a loop is entered at the top
661 when, in fact, it is entered at the exit test, the only effect will be
662 slightly poorer optimization. Making the opposite error can generate
663 incorrect code. Since very few loops now start with a jump to the
664 exit test, the code here to detect that case is very conservative. */
667 p != loop_end
673 ;
677 /* If loop end is the end of the current function, then emit a
678 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
679 note insn. This is the position we use when sinking insns out of
680 the loop. */
683 else
686 /* Set up variables describing this loop. */
690 /* If loop has a jump before the first label,
691 the true entry is the target of that jump.
692 Start scan from there.
693 But record in LOOP->TOP the place where the end-test jumps
694 back to so we can scan that after the end of the loop. */
696 /* Loop entry must be unconditional jump (and not a RETURN) */
699 /* Check to see whether the jump actually
700 jumps out of the loop (meaning it's no loop).
701 This case can happen for things like
702 do {..} while (0). If this label was generated previously
703 by loop, we can't tell anything about it and have to reject
704 the loop. */
706 {
709 }
711 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
712 as required by loop_reg_used_before_p. So skip such loops. (This
713 test may never be true, but it's best to play it safe.)
715 Also, skip loops where we do not start scanning at a label. This
716 test also rejects loops starting with a JUMP_INSN that failed the
717 test above. */
721 {
726 }
728 /* Allocate extra space for REGs that might be created by load_mems.
729 We allocate a little extra slop as well, in the hopes that we
730 won't have to reallocate the regs array. */
735 {
741 }
743 /* Scan through the loop finding insns that are safe to move.
744 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
745 this reg will be considered invariant for subsequent insns.
746 We consider whether subsequent insns use the reg
747 in deciding whether it is worth actually moving.
749 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
750 and therefore it is possible that the insns we are scanning
751 would never be executed. At such times, we must make sure
752 that it is safe to execute the insn once instead of zero times.
753 When MAYBE_NEVER is 0, all insns will be executed at least once
754 so that is not a problem. */
759 {
761 in_libcall--;
763 {
766 in_libcall++;
770 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
772 #endif
774 {
782 /* Figure out what to use as a source of this insn. If a
783 REG_EQUIV note is given or if a REG_EQUAL note with a
784 constant operand is specified, use it as the source and
785 mark that we should move this insn by calling
786 emit_move_insn rather that duplicating the insn.
788 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
789 note is present. */
793 else
794 {
799 {
801 /* A libcall block can use regs that don't appear in
802 the equivalent expression. To move the libcall,
803 we must move those regs too. */
805 }
806 }
808 /* For parallels, add any possible uses to the dependencies, as
809 we can't move the insn without resolving them first.
810 MEMs inside CLOBBERs may also reference registers; these
811 count as implicit uses. */
813 {
815 {
818 dependencies
820 dependencies);
825 }
826 }
829 than the one where it is set (meaning that
830 something after this point in the loop might
831 depend on its value before the set). */
833 /* And the set is not guaranteed to be executed once
834 the loop starts, or the value before the set is
835 needed before the set occurs...
837 ??? Note we have quadratic behavior here, mitigated
838 by the fact that the previous test will often fail for
839 large loops. Rather than re-scanning the entire loop
840 each time for register usage, we should build tables
841 of the register usage and use them here instead. */
842 && (maybe_never
844 /* It is unsafe to move the set. However, it may be OK to
845 move the source into a new pseudo, and substitute a
846 reg-to-reg copy for the original insn.
848 This code used to consider it OK to move a set of a variable
849 which was not created by the user and not used in an exit
850 test.
851 That behavior is incorrect and was removed. */
854 /* Don't try to optimize a MODE_CC set with a constant
855 source. It probably will be combined with a conditional
856 jump. */
859 ;
860 /* Don't try to optimize a register that was made
861 by loop-optimization for an inner loop.
862 We don't know its life-span, so we can't compute
863 the benefit. */
865 ;
866 /* Don't move the source and add a reg-to-reg copy:
867 - with -Os (this certainly increases size),
868 - if the mode doesn't support copy operations (obviously),
869 - if the source is already a reg (the motion will gain nothing),
870 - if the source is a legitimate constant (likewise). */
872 && (optimize_size
877 ;
880 || (tem2
883 || (tem1
884 = consec_sets_invariant_p
887 p)))
888 /* If the insn can cause a trap (such as divide by zero),
889 can't move it unless it's guaranteed to be executed
890 once loop is entered. Even a function call might
891 prevent the trap insn from being reached
892 (since it might exit!) */
895 {
899 /* A potential lossage is where we have a case where two insns
900 can be combined as long as they are both in the loop, but
901 we move one of them outside the loop. For large loops,
902 this can lose. The most common case of this is the address
903 of a function being called.
905 Therefore, if this register is marked as being used
906 exactly once if we are in a loop with calls
907 (a "large loop"), see if we can replace the usage of
908 this register with the source of this SET. If we can,
909 delete this insn.
911 Don't do this if P has a REG_RETVAL note or if we have
912 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
924 && (! SMALL_REGISTER_CLASSES
928 /* This test is not redundant; SET_SRC (set) might be
929 a call-clobbered register and the life of REGNO
930 might span a call. */
937 {
938 /* Replace any usage in a REG_EQUAL note. Must copy
939 the new source, so that we don't get rtx sharing
940 between the SET_SOURCE and REG_NOTES of insn p. */
942 = (replace_rtx
948 i++)
951 }
960 m->consec
971 /* Set M->cond if either loop_invariant_p
972 or consec_sets_invariant_p returned 2
973 (only conditionally invariant). */
983 /* Add M to the end of the chain MOVABLES. */
987 {
988 /* It is possible for the first instruction to have a
989 REG_EQUAL note but a non-invariant SET_SRC, so we must
990 remember the status of the first instruction in case
991 the last instruction doesn't have a REG_EQUAL note. */
994 /* Skip this insn, not checking REG_LIBCALL notes. */
996 /* Skip the consecutive insns, if there are any. */
998 /* Back up to the last insn of the consecutive group. */
1001 /* We must now reset m->move_insn, m->is_equiv, and
1002 possibly m->set_src to correspond to the effects of
1003 all the insns. */
1007 else
1008 {
1012 else
1015 }
1016 m->is_equiv
1018 }
1019 }
1020 /* If this register is always set within a STRICT_LOW_PART
1021 or set to zero, then its high bytes are constant.
1022 So clear them outside the loop and within the loop
1023 just load the low bytes.
1024 We must check that the machine has an instruction to do so.
1025 Also, if the value loaded into the register
1026 depends on the same register, this cannot be done. */
1036 {
1039 {
1054 /* If the insn may not be executed on some cycles,
1055 we can't clear the whole reg; clear just high part.
1056 Not even if the reg is used only within this loop.
1057 Consider this:
1058 while (1)
1059 while (s != t) {
1060 if (foo ()) x = *s;
1061 use (x);
1062 }
1063 Clearing x before the inner loop could clobber a value
1064 being saved from the last time around the outer loop.
1065 However, if the reg is not used outside this loop
1066 and all uses of the register are in the same
1067 basic block as the store, there is no problem.
1069 If this insn was made by loop, we don't know its
1070 INSN_LUID and hence must make a conservative
1071 assumption. */
1074 || (labels_in_range_p
1078 else
1087 i++)
1089 /* Add M to the end of the chain MOVABLES. */
1091 }
1092 }
1093 }
1094 }
1095 /* Past a call insn, we get to insns which might not be executed
1096 because the call might exit. This matters for insns that trap.
1097 Constant and pure call insns always return, so they don't count. */
1100 /* Past a label or a jump, we get to insns for which we
1101 can't count on whether or how many times they will be
1102 executed during each iteration. Therefore, we can
1103 only move out sets of trivial variables
1104 (those not used after the loop). */
1105 /* Similar code appears twice in strength_reduce. */
1107 /* If we enter the loop in the middle, and scan around to the
1108 beginning, don't set maybe_never for that. This must be an
1109 unconditional jump, otherwise the code at the top of the
1110 loop might never be executed. Unconditional jumps are
1111 followed by a barrier then the loop_end. */
1117 {
1118 /* At the virtual top of a converted loop, insns are again known to
1119 be executed: logically, the loop begins here even though the exit
1120 code has been duplicated. */
1124 loop_depth++;
1126 loop_depth--;
1127 }
1128 }
1130 /* If one movable subsumes another, ignore that other. */
1134 /* For each movable insn, see if the reg that it loads
1135 leads when it dies right into another conditionally movable insn.
1136 If so, record that the second insn "forces" the first one,
1137 since the second can be moved only if the first is. */
1141 /* See if there are multiple movable insns that load the same value.
1142 If there are, make all but the first point at the first one
1143 through the `match' field, and add the priorities of them
1144 all together as the priority of the first. */
1148 /* Now consider each movable insn to decide whether it is worth moving.
1149 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1151 For machines with few registers this increases code size, so do not
1152 move moveables when optimizing for code size on such machines.
1153 (The 18 below is the value for i386.) */
1157 {
1160 /* Recalculate regs->array if move_movables has created new
1161 registers. */
1163 {
1169 ;
1174 }
1175 }
1177 /* Now candidates that still are negative are those not moved.
1178 Change regs->array[I].set_in_loop to indicate that those are not actually
1179 invariant. */
1184 /* Now that we've moved some things out of the loop, we might be able to
1185 hoist even more memory references. */
1188 /* Recalculate regs->array if load_mems has created new registers. */
1196 ;
1203 {
1205 /* Ensure our label doesn't go away. */
1216 }
1219 /* The movable information is required for strength reduction. */
1225 }
1226 \f
1227 /* Add elements to *OUTPUT to record all the pseudo-regs
1228 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1230 void
1232 {
1240 {
1258 }
1262 {
1266 {
1275 }
1276 }
1277 }
1278 \f
1279 /* Check what regs are referred to in the libcall block ending with INSN,
1280 aside from those mentioned in the equivalent value.
1281 If there are none, return 0.
1282 If there are one or more, return an EXPR_LIST containing all of them. */
1284 rtx
1286 {
1291 /* First, find all the regs used in the libcall block
1292 that are not mentioned as inputs to the result. */
1295 {
1300 }
1303 }
1304 \f
1305 /* Return 1 if all uses of REG
1306 are between INSN and the end of the basic block. */
1308 static int
1310 {
1312 rtx p;
1317 /* Search this basic block for the already recorded last use of the reg. */
1319 {
1321 {
1327 /* Ordinary insn: if this is the last use, we win. */
1333 /* Jump insn: if this is the last use, we win. */
1336 /* Otherwise, it's the end of the basic block, so we lose. */
1341 /* It's the end of the basic block, so we lose. */
1346 }
1347 }
1349 /* The "last use" that was recorded can't be found after the first
1350 use. This can happen when the last use was deleted while
1351 processing an inner loop, this inner loop was then completely
1352 unrolled, and the outer loop is always exited after the inner loop,
1353 so that everything after the first use becomes a single basic block. */
1355 }
1356 \f
1357 /* Compute the benefit of eliminating the insns in the block whose
1358 last insn is LAST. This may be a group of insns used to compute a
1359 value directly or can contain a library call. */
1361 static int
1363 {
1364 rtx insn;
1369 {
1372 routine. */
1376 benefit++;
1377 }
1380 }
1381 \f
1382 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1384 static rtx
1386 {
1388 {
1389 rtx temp;
1391 /* If first insn of libcall sequence, skip to end. */
1392 /* Do this at start of loop, since INSN is guaranteed to
1393 be an insn here. */
1398 do
1401 }
1404 }
1406 /* Ignore any movable whose insn falls within a libcall
1407 which is part of another movable.
1408 We make use of the fact that the movable for the libcall value
1409 was made later and so appears later on the chain. */
1411 static void
1413 {
1417 {
1418 /* Is this a movable for the value of a libcall? */
1421 {
1422 rtx insn;
1423 /* Check for earlier movables inside that range,
1424 and mark them invalid. We cannot use LUIDs here because
1425 insns created by loop.c for prior loops don't have LUIDs.
1426 Rather than reject all such insns from movables, we just
1427 explicitly check each insn in the libcall (since invariant
1428 libcalls aren't that common). */
1433 }
1434 }
1435 }
1437 /* For each movable insn, see if the reg that it loads
1438 leads when it dies right into another conditionally movable insn.
1439 If so, record that the second insn "forces" the first one,
1440 since the second can be moved only if the first is. */
1442 static void
1444 {
1448 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1450 {
1453 /* ??? Could this be a bug? What if CSE caused the
1454 register of M1 to be used after this insn?
1455 Since CSE does not update regno_last_uid,
1456 this insn M->insn might not be where it dies.
1457 But very likely this doesn't matter; what matters is
1458 that M's reg is computed from M1's reg. */
1463 /* If m->consec, m->set_src isn't valid. */
1467 /* Increase the priority of the moving the first insn
1468 since it permits the second to be moved as well. */
1470 {
1474 }
1475 }
1476 }
1477 \f
1478 /* Find invariant expressions that are equal and can be combined into
1479 one register. */
1481 static void
1483 {
1488 /* Regs that are set more than once are not allowed to match
1489 or be matched. I'm no longer sure why not. */
1490 /* Only pseudo registers are allowed to match or be matched,
1491 since move_movables does not validate the change. */
1492 /* Perhaps testing m->consec_sets would be more appropriate here? */
1499 {
1506 /* We want later insns to match the first one. Don't make the first
1507 one match any later ones. So start this loop at m->next. */
1513 /* A reg used outside the loop mustn't be eliminated. */
1515 /* A reg used for zero-extending mustn't be eliminated. */
1518 ||
1519 (
1520 /* Can combine regs with different modes loaded from the
1521 same constant only if the modes are the same or
1522 if both are integer modes with M wider or the same
1523 width as M1. The check for integer is redundant, but
1524 safe, since the only case of differing destination
1525 modes with equal sources is when both sources are
1526 VOIDmode, i.e., CONST_INT. */
1532 /* See if the source of M1 says it matches M. */
1539 {
1545 }
1546 }
1548 /* Now combine the regs used for zero-extension.
1549 This can be done for those not marked `global'
1550 provided their lives don't overlap. */
1554 {
1557 /* Combine all the registers for extension from mode MODE.
1558 Don't combine any that are used outside this loop. */
1562 {
1569 {
1570 /* First one: don't check for overlap, just record it. */
1573 }
1575 /* Make sure they extend to the same mode.
1576 (Almost always true.) */
1580 /* We already have one: check for overlap with those
1581 already combined together. */
1588 /* No overlap: we can combine this with the others. */
1594 overlap:
1595 ;
1596 }
1597 }
1599 /* Clean up. */
1601 }
1603 /* Returns the number of movable instructions in LOOP that were not
1604 moved outside the loop. */
1606 static int
1608 {
1617 }
1619 \f
1620 /* Return 1 if regs X and Y will become the same if moved. */
1622 static int
1624 {
1641 }
1643 /* Return 1 if X and Y are identical-looking rtx's.
1644 This is the Lisp function EQUAL for rtx arguments.
1646 If two registers are matching movables or a movable register and an
1647 equivalent constant, consider them equal. */
1649 static int
1652 {
1666 /* If we have a register and a constant, they may sometimes be
1667 equal. */
1670 {
1675 }
1678 {
1683 }
1685 /* Otherwise, rtx's of different codes cannot be equal. */
1689 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1690 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1695 /* These three types of rtx's can be compared nonrecursively. */
1704 /* Compare the elements. If any pair of corresponding elements
1705 fail to match, return 0 for the whole things. */
1709 {
1711 {
1723 /* Two vectors must have the same length. */
1727 /* And the corresponding elements must match. */
1746 /* These are just backpointers, so they don't matter. */
1752 /* It is believed that rtx's at this level will never
1753 contain anything but integers and other rtx's,
1754 except for within LABEL_REFs and SYMBOL_REFs. */
1757 }
1758 }
1760 }
1761 \f
1762 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1763 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1764 references is incremented once for each added note. */
1766 static void
1768 {
1772 rtx insn;
1775 {
1776 /* This code used to ignore labels that referred to dispatch tables to
1777 avoid flow generating (slightly) worse code.
1779 We no longer ignore such label references (see LABEL_REF handling in
1780 mark_jump_label for additional information). */
1783 {
1788 }
1789 }
1793 {
1799 }
1800 }
1801 \f
1802 /* Scan MOVABLES, and move the insns that deserve to be moved.
1803 If two matching movables are combined, replace one reg with the
1804 other throughout. */
1806 static void
1809 {
1814 rtx p;
1817 /* Map of pseudo-register replacements to handle combining
1818 when we move several insns that load the same value
1819 into different pseudo-registers. */
1824 {
1825 /* Describe this movable insn. */
1828 {
1849 }
1851 /* Ignore the insn if it's already done (it matched something else).
1852 Otherwise, see if it is now safe to move. */
1864 {
1866 rtx p;
1869 /* We have an insn that is safe to move.
1870 Compute its desirability. */
1881 /* An insn MUST be moved if we already moved something else
1882 which is safe only if this one is moved too: that is,
1883 if already_moved[REGNO] is nonzero. */
1885 /* An insn is desirable to move if the new lifetime of the
1886 register is no more than THRESHOLD times the old lifetime.
1887 If it's not desirable, it means the loop is so big
1888 that moving won't speed things up much,
1889 and it is liable to make register usage worse. */
1891 /* It is also desirable to move if it can be moved at no
1892 extra cost because something else was already moved. */
1895 || flag_move_all_movables
1900 {
1909 /* Now move the insns that set the reg. */
1912 {
1915 /* Find the end of this chain of matching regs.
1916 Thus, we load each reg in the chain from that one reg.
1917 And that reg is loaded with 0 directly,
1918 since it has ->match == 0. */
1924 /* Mark the moved, invariant reg as being allowed to
1925 share a hard reg with the other matching invariant. */
1929 regs_may_share
1932 regs_may_share));
1940 }
1941 /* If we are to re-generate the item being moved with a
1942 new move insn, first delete what we have and then emit
1943 the move insn before the loop. */
1945 {
1949 {
1950 /* If this is the first insn of a library call sequence,
1951 something is very wrong. */
1956 /* If this is the last insn of a libcall sequence, then
1957 delete every insn in the sequence except the last.
1958 The last insn is handled in the normal manner. */
1961 {
1965 }
1970 /* simplify_giv_expr expects that it can walk the insns
1971 at m->insn forwards and see this old sequence we are
1972 tossing here. delete_insn does preserve the next
1973 pointers, but when we skip over a NOTE we must fix
1974 it up. Otherwise that code walks into the non-deleted
1975 insn stream. */
1980 {
1981 /* Replace the original insn with a move from
1982 our newly created temp. */
1988 }
1989 }
2008 /* The more regs we move, the less we like moving them. */
2010 }
2011 else
2012 {
2014 {
2017 /* If first insn of libcall sequence, skip to end. */
2018 /* Do this at start of loop, since p is guaranteed to
2019 be an insn here. */
2024 /* If last insn of libcall sequence, move all
2025 insns except the last before the loop. The last
2026 insn is handled in the normal manner. */
2029 {
2037 {
2038 rtx body;
2039 rtx n;
2040 rtx next;
2047 /* Find the next insn after TEMP,
2048 not counting USE or NOTE insns. */
2056 /* If that is the call, this may be the insn
2057 that loads the function address.
2059 Extract the function address from the insn
2060 that loads it into a register.
2061 If this insn was cse'd, we get incorrect code.
2063 So emit a new move insn that copies the
2064 function address into the register that the
2065 call insn will use. flow.c will delete any
2066 redundant stores that we have created. */
2071 NULL_RTX)))
2072 {
2078 }
2079 /* We have the call insn.
2080 If it uses the register we suspect it might,
2081 load it with the correct address directly. */
2086 gen_move_insn
2090 {
2092 /* Because the USAGE information potentially
2093 contains objects other than hard registers
2094 we need to copy it. */
2098 }
2099 else
2108 }
2111 }
2113 {
2114 /* P sets REG to zero; but we should clear only
2115 the bits that are not covered by the mode
2116 m->savemode. */
2118 rtx sequence;
2119 rtx tem;
2122 tem = expand_simple_binop
2135 }
2137 {
2139 /* Because the USAGE information potentially
2140 contains objects other than hard registers
2141 we need to copy it. */
2145 }
2147 {
2148 rtx seq;
2149 /* The SET_SRC might not be invariant, so we must
2150 use the REG_EQUAL note. */
2163 }
2165 {
2173 }
2174 else
2178 {
2182 /* If there is a REG_EQUAL note present whose value
2183 is not loop invariant, then delete it, since it
2184 may cause problems with later optimization passes.
2185 It is possible for cse to create such notes
2186 like this as a result of record_jump_cond. */
2191 }
2200 /* If library call, now fix the REG_NOTES that contain
2201 insn pointers, namely REG_LIBCALL on FIRST
2202 and REG_RETVAL on I1. */
2204 {
2208 }
2214 /* simplify_giv_expr expects that it can walk the insns
2215 at m->insn forwards and see this old sequence we are
2216 tossing here. delete_insn does preserve the next
2217 pointers, but when we skip over a NOTE we must fix
2218 it up. Otherwise that code walks into the non-deleted
2219 insn stream. */
2224 {
2225 rtx seq;
2226 /* Replace the original insn with a move from
2227 our newly created temp. */
2233 }
2234 }
2236 /* The more regs we move, the less we like moving them. */
2238 }
2243 {
2244 /* Any other movable that loads the same register
2245 MUST be moved. */
2248 /* This reg has been moved out of one loop. */
2251 /* The reg set here is now invariant. */
2253 {
2257 }
2259 /* Change the length-of-life info for the register
2260 to say it lives at least the full length of this loop.
2261 This will help guide optimizations in outer loops. */
2264 /* This is the old insn before all the moved insns.
2265 We can't use the moved insn because it is out of range
2266 in uid_luid. Only the old insns have luids. */
2270 }
2272 /* Combine with this moved insn any other matching movables. */
2277 {
2278 rtx temp;
2280 /* Schedule the reg loaded by M1
2281 for replacement so that shares the reg of M.
2282 If the modes differ (only possible in restricted
2283 circumstances, make a SUBREG.
2285 Note this assumes that the target dependent files
2286 treat REG and SUBREG equally, including within
2287 GO_IF_LEGITIMATE_ADDRESS and in all the
2288 predicates since we never verify that replacing the
2289 original register with a SUBREG results in a
2290 recognizable insn. */
2293 else
2298 /* Get rid of the matching insn
2299 and prevent further processing of it. */
2302 /* If library call, delete all insns. */
2304 NULL_RTX)))
2306 else
2309 /* Any other movable that loads the same register
2310 MUST be moved. */
2313 /* The reg merged here is now invariant,
2314 if the reg it matches is invariant. */
2316 {
2320 i++)
2322 }
2323 }
2324 }
2327 }
2333 }
2338 /* Go through all the instructions in the loop, making
2339 all the register substitutions scheduled in REG_MAP. */
2343 {
2347 }
2349 /* Clean up. */
2352 }
2355 static void
2357 {
2360 else
2363 }
2366 static void
2368 {
2373 {
2376 }
2377 }
2378 \f
2379 #if 0
2380 /* Scan X and replace the address of any MEM in it with ADDR.
2381 REG is the address that MEM should have before the replacement. */
2383 static void
2385 {
2394 {
2406 /* Short cut for very common case. */
2411 /* Short cut for very common case. */
2416 /* If this MEM uses a reg other than the one we expected,
2417 something is wrong. */
2425 }
2429 {
2433 {
2437 }
2438 }
2439 }
2440 #endif
2441 \f
2442 /* Return the number of memory refs to addresses that vary
2443 in the rtx X. */
2445 static int
2447 {
2458 {
2475 }
2480 {
2484 {
2488 }
2489 }
2491 }
2492 \f
2493 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2494 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2495 `unknown_address_altered', `unknown_constant_address_altered', and
2496 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2497 list `store_mems' in LOOP. */
2499 static void
2501 {
2503 rtx insn;
2507 /* The label after END. Jumping here is just like falling off the
2508 end of the loop. We use next_nonnote_insn instead of next_label
2509 as a hedge against the (pathological) case where some actual insn
2510 might end up between the two. */
2529 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2534 {
2536 {
2539 }
2540 }
2544 {
2546 {
2549 {
2551 /* Count number of loops contained in this one. */
2553 }
2560 {
2563 }
2570 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2571 attached FUNCTION_USAGE expression list, not accounted for by the
2572 code above. We should note these to avoid missing dependencies in
2573 later references. */
2574 {
2575 rtx fusage_entry;
2579 {
2585 {
2590 }
2591 }
2592 }
2597 {
2601 {
2606 {
2609 }
2610 else
2611 {
2614 }
2616 do
2617 {
2619 {
2621 {
2622 /* Something tricky. */
2625 }
2628 {
2629 /* A jump outside the current loop. */
2632 }
2633 }
2637 }
2639 }
2640 else
2641 {
2642 /* A return, or something tricky. */
2644 }
2645 }
2646 /* Fall through. */
2667 }
2668 }
2670 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2672 anywhere. */
2674 /* We don't want loads for MEMs moved to a location before the
2675 one at which their stack memory becomes allocated. (Note
2676 that this is not a problem for malloc, etc., since those
2677 require actual function calls. */
2678 && ! current_function_calls_alloca
2679 /* There are ways to leave the loop other than falling off the
2680 end. */
2686 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2687 that loop_invariant_p and load_mems can use true_dependence
2688 to determine what is really clobbered. */
2690 {
2693 loop_info->store_mems
2695 }
2697 {
2701 loop_info->store_mems
2703 }
2704 }
2705 \f
2706 /* Invalidate all loops containing LABEL. */
2708 static void
2710 {
2714 }
2716 /* Scan the function looking for loops. Record the start and end of each loop.
2717 Also mark as invalid loops any loops that contain a setjmp or are branched
2718 to from outside the loop. */
2720 static void
2722 {
2723 rtx insn;
2724 rtx label;
2734 /* If there are jumps to undefined labels,
2735 treat them as jumps out of any/all loops.
2736 This also avoids writing past end of tables when there are no loops. */
2739 /* Find boundaries of loops, mark which loops are contained within
2740 loops, and invalidate loops that have setjmp. */
2745 {
2748 {
2752 num_loops++;
2776 }
2780 {
2781 /* In this case, we must invalidate our current loop and any
2782 enclosing loop. */
2784 {
2790 }
2791 }
2793 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2794 enclosing loop, but this doesn't matter. */
2796 }
2798 /* Any loop containing a label used in an initializer must be invalidated,
2799 because it can be jumped into from anywhere. */
2803 /* Any loop containing a label used for an exception handler must be
2804 invalidated, because it can be jumped into from anywhere. */
2807 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2808 loop that it is not contained within, that loop is marked invalid.
2809 If any INSN or CALL_INSN uses a label's address, then the loop containing
2810 that label is marked invalid, because it could be jumped into from
2811 anywhere.
2813 Also look for blocks of code ending in an unconditional branch that
2814 exits the loop. If such a block is surrounded by a conditional
2815 branch around the block, move the block elsewhere (see below) and
2816 invert the jump to point to the code block. This may eliminate a
2817 label in our loop and will simplify processing by both us and a
2818 possible second cse pass. */
2822 {
2826 {
2830 }
2837 /* See if this is an unconditional branch outside the loop. */
2845 {
2846 rtx p;
2852 /* Go backwards until we reach the start of the loop, a label,
2853 or a JUMP_INSN. */
2860 ;
2862 /* Check for the case where we have a jump to an inner nested
2863 loop, and do not perform the optimization in that case. */
2866 {
2869 {
2874 }
2875 }
2877 /* Make sure that the target of P is within the current loop. */
2883 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2884 we have a block of code to try to move.
2886 We look backward and then forward from the target of INSN
2887 to find a BARRIER at the same loop depth as the target.
2888 If we find such a BARRIER, we make a new label for the start
2889 of the block, invert the jump in P and point it to that label,
2890 and move the block of code to the spot we found. */
2895 /* Just ignore jumps to labels that were never emitted.
2896 These always indicate compilation errors. */
2900 /* If it's not safe to move the sequence, then we
2901 mustn't try. */
2904 {
2905 rtx target
2909 rtx tmp;
2911 /* Search for possible garbage past the conditional jumps
2912 and look for the last barrier. */
2920 /* Don't move things inside a tablejump. */
2933 /* Don't move things inside a tablejump. */
2944 {
2948 /* Ensure our label doesn't go away. */
2951 /* Verify that uid_loop is large enough and that
2952 we can invert P. */
2954 {
2957 /* If no suitable BARRIER was found, create a suitable
2958 one before TARGET. Since TARGET is a fall through
2959 path, we'll need to insert a jump around our block
2960 and add a BARRIER before TARGET.
2962 This creates an extra unconditional jump outside
2963 the loop. However, the benefits of removing rarely
2964 executed instructions from inside the loop usually
2965 outweighs the cost of the extra unconditional jump
2966 outside the loop. */
2968 {
2969 rtx temp;
2976 }
2978 /* Include the BARRIER after INSN and copy the
2979 block after LOC. */
2984 /* All those insns are now in TARGET_LOOP. */
2990 /* The label jumped to by INSN is no longer a loop
2991 exit. Unless INSN does not have a label (e.g.,
2992 it is a RETURN insn), search loop->exit_labels
2993 to find its label_ref, and remove it. Also turn
2994 off LABEL_OUTSIDE_LOOP_P bit. */
2996 {
2998 r;
3001 {
3005 else
3008 }
3014 /* If we didn't find it, then something is
3015 wrong. */
3018 }
3020 /* P is now a jump outside the loop, so it must be put
3021 in loop->exit_labels, and marked as such.
3022 The easiest way to do this is to just call
3023 mark_loop_jump again for P. */
3026 /* If INSN now jumps to the insn after it,
3027 delete INSN. */
3032 }
3034 /* Continue the loop after where the conditional
3035 branch used to jump, since the only branch insn
3036 in the block (if it still remains) is an inter-loop
3037 branch and hence needs no processing. */
3043 /* This loop will be continued with NEXT_INSN (insn). */
3045 }
3046 }
3047 }
3048 }
3049 }
3051 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3052 loops it is contained in, mark the target loop invalid.
3054 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3056 static void
3058 {
3064 {
3076 /* There could be a label reference in here. */
3088 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3100 /* Link together all labels that branch outside the loop. This
3101 is used by final_[bg]iv_value and the loop unrolling code. Also
3102 mark this LABEL_REF so we know that this branch should predict
3103 false. */
3105 /* A check to make sure the label is not in an inner nested loop,
3106 since this does not count as a loop exit. */
3108 {
3113 }
3114 else
3118 {
3127 }
3129 /* If this is inside a loop, but not in the current loop or one enclosed
3130 by it, it invalidates at least one loop. */
3135 /* We must invalidate every nested loop containing the target of this
3136 label, except those that also contain the jump insn. */
3139 {
3140 /* Stop when we reach a loop that also contains the jump insn. */
3145 /* If we get here, we know we need to invalidate a loop. */
3152 }
3156 /* If this is not setting pc, ignore. */
3178 /* Strictly speaking this is not a jump into the loop, only a possible
3179 jump out of the loop. However, we have no way to link the destination
3180 of this jump onto the list of exit labels. To be safe we mark this
3181 loop and any containing loops as invalid. */
3183 {
3185 {
3191 }
3192 }
3194 }
3195 }
3196 \f
3197 /* Return nonzero if there is a label in the range from
3198 insn INSN to and including the insn whose luid is END
3199 INSN must have an assigned luid (i.e., it must not have
3200 been previously created by loop.c). */
3202 static int
3204 {
3206 {
3210 }
3213 }
3215 /* Record that a memory reference X is being set. */
3217 static void
3220 {
3226 /* Count number of memory writes.
3227 This affects heuristics in strength_reduce. */
3230 /* BLKmode MEM means all memory is clobbered. */
3232 {
3235 else
3239 }
3243 }
3245 /* X is a value modified by an INSN that references a biv inside a loop
3246 exit test (ie, X is somehow related to the value of the biv). If X
3247 is a pseudo that is used more than once, then the biv is (effectively)
3248 used more than once. DATA is a pointer to a loop_regs structure. */
3250 static void
3252 {
3267 /* If we do not have usage information, or if we know the register
3268 is used more than once, note that fact for check_dbra_loop. */
3273 }
3274 \f
3275 /* Return nonzero if the rtx X is invariant over the current loop.
3277 The value is 2 if we refer to something only conditionally invariant.
3279 A memory ref is invariant if it is not volatile and does not conflict
3280 with anything stored in `loop_info->store_mems'. */
3282 int
3284 {
3291 rtx mem_list_entry;
3297 {
3305 /* A LABEL_REF is normally invariant, however, if we are unrolling
3306 loops, and this label is inside the loop, then it isn't invariant.
3307 This is because each unrolled copy of the loop body will have
3308 a copy of this label. If this was invariant, then an insn loading
3309 the address of this label into a register might get moved outside
3310 the loop, and then each loop body would end up using the same label.
3312 We don't know the loop bounds here though, so just fail for all
3313 labels. */
3316 else
3325 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3326 since the reg might be set by initialization within the loop. */
3337 /* Out-of-range regs can occur when we are called from unrolling.
3338 These registers created by the unroller are set in the loop,
3339 hence are never invariant.
3340 Other out-of-range regs can be generated by load_mems; those that
3341 are written to in the loop are not invariant, while those that are
3342 not written to are invariant. It would be easy for load_mems
3343 to set n_times_set correctly for these registers, however, there
3344 is no easy way to distinguish them from registers created by the
3345 unroller. */
3356 /* Volatile memory references must be rejected. Do this before
3357 checking for read-only items, so that volatile read-only items
3358 will be rejected also. */
3362 /* See if there is any dependence between a store and this load. */
3365 {
3371 }
3373 /* It's not invalidated by a store in memory
3374 but we must still verify the address is invariant. */
3378 /* Don't mess with insns declared volatile. */
3385 }
3389 {
3391 {
3397 }
3399 {
3402 {
3408 }
3410 }
3411 }
3414 }
3415 \f
3416 /* Return nonzero if all the insns in the loop that set REG
3417 are INSN and the immediately following insns,
3418 and if each of those insns sets REG in an invariant way
3419 (not counting uses of REG in them).
3421 The value is 2 if some of these insns are only conditionally invariant.
3423 We assume that INSN itself is the first set of REG
3424 and that its source is invariant. */
3426 static int
3428 rtx insn)
3429 {
3433 rtx temp;
3434 /* Number of sets we have to insist on finding after INSN. */
3440 /* If N_SETS hit the limit, we can't rely on its value. */
3447 {
3449 rtx set;
3454 /* If library call, skip to end of it. */
3463 {
3468 {
3469 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3470 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3471 notes are OK. */
3477 }
3478 }
3480 count--;
3482 {
3485 }
3486 }
3489 /* If loop_invariant_p ever returned 2, we return 2. */
3491 }
3493 #if 0
3494 /* I don't think this condition is sufficient to allow INSN
3495 to be moved, so we no longer test it. */
3497 /* Return 1 if all insns in the basic block of INSN and following INSN
3498 that set REG are invariant according to TABLE. */
3500 static int
3502 {
3507 {
3516 {
3519 }
3520 }
3521 }
3523 \f
3524 /* Look at all uses (not sets) of registers in X. For each, if it is
3525 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3526 a different insn, set USAGE[REGNO] to const0_rtx. */
3528 static void
3530 {
3542 {
3543 /* Don't count SET_DEST if it is a REG; otherwise count things
3544 in SET_DEST because if a register is partially modified, it won't
3545 show up as a potential movable so we don't care how USAGE is set
3546 for it. */
3550 }
3551 else
3553 {
3559 }
3560 }
3561 \f
3562 /* Count and record any set in X which is contained in INSN. Update
3563 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3564 in X. */
3566 static void
3568 {
3570 /* Don't move a reg that has an explicit clobber.
3571 It's not worth the pain to try to do it correctly. */
3575 {
3583 {
3587 {
3588 /* If this is the first setting of this reg
3589 in current basic block, and it was set before,
3590 it must be set in two basic blocks, so it cannot
3591 be moved out of the loop. */
3595 /* If this is not first setting in current basic block,
3596 see if reg was used in between previous one and this.
3597 If so, neither one can be moved. */
3604 }
3605 }
3606 }
3607 }
3608 \f
3609 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3610 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3611 contained in insn INSN is used by any insn that precedes INSN in
3612 cyclic order starting from the loop entry point.
3614 We don't want to use INSN_LUID here because if we restrict INSN to those
3615 that have a valid INSN_LUID, it means we cannot move an invariant out
3616 from an inner loop past two loops. */
3618 static int
3620 {
3622 rtx p;
3624 /* Scan forward checking for register usage. If we hit INSN, we
3625 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3627 {
3633 }
3636 }
3637 \f
3639 /* Information we collect about arrays that we might want to prefetch. */
3640 struct prefetch_info
3641 {
3645 index. */
3646 HOST_WIDE_INT index;
3648 iteration. */
3650 prefetch area in one iteration. */
3652 This is set only for loops with known
3653 iteration counts and is 0xffffffff
3654 otherwise. */
3658 };
3660 /* Data used by check_store function. */
3661 struct check_store_data
3662 {
3663 rtx mem_address;
3665 };
3671 /* Set mem_write when mem_address is found. Used as callback to
3672 note_stores. */
3673 static void
3675 {
3680 }
3681 \f
3682 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3683 important to get some addresses combined. Later more sophisticated
3684 transformations can be added when necessary.
3686 ??? Same trick with swapping operand is done at several other places.
3687 It can be nice to develop some common way to handle this. */
3689 static int
3691 {
3705 {
3710 }
3711 /* Compare the elements. If any pair of corresponding elements fails to
3712 match, return 0 for the whole thing. */
3716 {
3718 {
3730 /* Two vectors must have the same length. */
3734 /* And the corresponding elements must match. */
3752 /* These are just backpointers, so they don't matter. */
3758 /* It is believed that rtx's at this level will never
3759 contain anything but integers and other rtx's,
3760 except for within LABEL_REFs and SYMBOL_REFs. */
3763 }
3764 }
3766 }
3767 \f
3768 /* Remove constant addition value from the expression X (when present)
3769 and return it. */
3771 static HOST_WIDE_INT
3773 {
3777 /* Avoid clobbering a shared CONST expression. */
3779 {
3783 {
3786 }
3788 }
3791 {
3794 }
3796 /* For plus expression recurse on ourself. */
3798 {
3802 /* In case our parameter was constant, remove extra zero from the
3803 expression. */
3808 }
3811 }
3813 /* Attempt to identify accesses to arrays that are most likely to cause cache
3814 misses, and emit prefetch instructions a few prefetch blocks forward.
3816 To detect the arrays we use the GIV information that was collected by the
3817 strength reduction pass.
3819 The prefetch instructions are generated after the GIV information is done
3820 and before the strength reduction process. The new GIVs are injected into
3821 the strength reduction tables, so the prefetch addresses are optimized as
3822 well.
3824 GIVs are split into base address, stride, and constant addition values.
3825 GIVs with the same address, stride and close addition values are combined
3826 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3827 for write instructions can be used for the block we write to, on machines
3828 that support write prefetches.
3830 Several heuristics are used to determine when to prefetch. They are
3831 controlled by defined symbols that can be overridden for each target. */
3833 static void
3835 {
3851 /* Consider only loops w/o calls. When a call is done, the loop is probably
3852 slow enough to read the memory. */
3854 {
3859 }
3861 /* Don't prefetch in loops known to have few iterations. */
3865 {
3870 }
3872 /* Search all induction variables and pick those interesting for the prefetch
3873 machinery. */
3875 {
3881 /* Expect all BIVs to be executed in each iteration. This makes our
3882 analysis more conservative. */
3884 {
3885 /* Discard non-constant additions that we can't handle well yet, and
3886 BIVs that are executed multiple times; such BIVs ought to be
3887 handled in the nested loop. We accept not_every_iteration BIVs,
3888 since these only result in larger strides and make our
3889 heuristics more conservative. */
3891 {
3893 {
3899 }
3901 }
3904 {
3906 {
3912 }
3914 }
3918 }
3924 {
3925 rtx address;
3926 rtx temp;
3935 /* See whether an induction variable is interesting to us and if
3936 not, report the reason. */
3940 /* We are interested only in constant stride memory references
3941 in order to be able to compute density easily. */
3945 else
3946 {
3949 {
3952 }
3954 /* On some targets, reversed order prefetches are not
3955 worthwhile. */
3959 /* Prefetch of accesses with an extreme stride might not be
3960 worthwhile, either. */
3965 /* Ignore GIVs with varying add values; we can't predict the
3966 value for the next iteration. */
3970 /* Ignore GIVs in the nested loops; they ought to have been
3971 handled already. */
3974 }
3977 {
3983 }
3985 /* Determine the pointer to the basic array we are examining. It is
3986 the sum of the BIV's initial value and the GIV's add_val. */
3996 /* When the GIV is not always executed, we might be better off by
3997 not dirtying the cache pages. */
4000 else
4001 {
4006 }
4008 /* Attempt to find another prefetch to the same array and see if we
4009 can merge this one. */
4013 {
4014 /* In case both access same array (same location
4015 just with small difference in constant indexes), merge
4016 the prefetches. Just do the later and the earlier will
4017 get prefetched from previous iteration.
4018 The artificial threshold should not be too small,
4019 but also not bigger than small portion of memory usually
4020 traversed by single loop. */
4023 {
4032 }
4036 {
4041 }
4042 }
4044 /* Merging failed. */
4046 {
4054 num_prefetches++;
4056 {
4061 }
4062 }
4063 }
4064 }
4067 {
4070 /* Attempt to calculate the total number of bytes fetched by all
4071 iterations of the loop. Avoid overflow. */
4076 else
4081 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4086 {
4091 }
4092 else
4093 {
4099 }
4100 else
4103 /* Find how many prefetch instructions we'll use within the loop. */
4105 {
4111 }
4112 }
4114 /* Determine how many iterations ahead to prefetch within the loop, based
4115 on how many prefetches we currently expect to do within the loop. */
4117 {
4119 {
4125 }
4126 }
4127 /* We'll also use AHEAD to determine how many prefetch instructions to
4128 emit before a loop, so don't leave it zero. */
4133 {
4134 /* Update if we've decided not to prefetch anything within the loop. */
4138 /* Find how many prefetch instructions we'll use before the loop. */
4140 {
4148 }
4151 {
4171 }
4172 }
4175 {
4176 /* Record that this loop uses prefetch instructions. */
4180 {
4185 }
4186 }
4189 {
4193 {
4195 rtx insn;
4199 rtx seq;
4201 /* We can save some effort by offsetting the address on
4202 architectures with offsettable memory references. */
4205 else
4206 {
4212 }
4215 /* Make sure the address operand is valid for prefetch. */
4225 /* Check all insns emitted and record the new GIV
4226 information. */
4229 {
4234 }
4235 }
4238 {
4239 /* Emit insns before the loop to fetch the first cache lines or,
4240 if we're not prefetching within the loop, everything we expect
4241 to need. */
4243 {
4251 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4252 non-constant INIT_VAL to have the same mode as REG, which
4253 in this case we know to be Pmode. */
4255 {
4256 rtx seq;
4263 }
4269 loop_start);
4270 }
4271 }
4272 }
4275 }
4276 \f
4277 /* Communication with routines called via `note_stores'. */
4281 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4285 /* ??? Unfinished optimizations, and possible future optimizations,
4286 for the strength reduction code. */
4288 /* ??? The interaction of biv elimination, and recognition of 'constant'
4289 bivs, may cause problems. */
4291 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4292 performance problems.
4294 Perhaps don't eliminate things that can be combined with an addressing
4295 mode. Find all givs that have the same biv, mult_val, and add_val;
4296 then for each giv, check to see if its only use dies in a following
4297 memory address. If so, generate a new memory address and check to see
4298 if it is valid. If it is valid, then store the modified memory address,
4299 otherwise, mark the giv as not done so that it will get its own iv. */
4301 /* ??? Could try to optimize branches when it is known that a biv is always
4302 positive. */
4304 /* ??? When replace a biv in a compare insn, we should replace with closest
4305 giv so that an optimized branch can still be recognized by the combiner,
4306 e.g. the VAX acb insn. */
4308 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4309 was rerun in loop_optimize whenever a register was added or moved.
4310 Also, some of the optimizations could be a little less conservative. */
4311 \f
4312 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4313 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4314 callback.
4316 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4317 least once for every loop iteration except for the last one.
4319 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4320 loop iteration.
4321 */
4322 void
4324 {
4329 rtx p;
4331 /* If loop_scan_start points to the loop exit test, we have to be wary of
4332 subversive use of gotos inside expression statements. */
4336 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4340 {
4343 /* Past CODE_LABEL, we get to insns that may be executed multiple
4344 times. The only way we can be sure that they can't is if every
4345 jump insn between here and the end of the loop either
4346 returns, exits the loop, is a jump to a location that is still
4347 behind the label, or is a jump to the loop start. */
4350 {
4356 {
4361 {
4364 else
4368 }
4376 {
4379 }
4380 }
4381 }
4383 /* Past a jump, we get to insns for which we can't count
4384 on whether they will be executed during each iteration. */
4385 /* This code appears twice in strength_reduce. There is also similar
4386 code in scan_loop. */
4388 /* If we enter the loop in the middle, and scan around to the
4389 beginning, don't set not_every_iteration for that.
4390 This can be any kind of jump, since we want to know if insns
4391 will be executed if the loop is executed. */
4396 {
4399 /* If this is a jump outside the loop, then it also doesn't
4400 matter. Check to see if the target of this branch is on the
4401 loop->exits_labels list. */
4409 }
4412 {
4413 /* At the virtual top of a converted loop, insns are again known to
4414 be executed each iteration: logically, the loop begins here
4415 even though the exit code has been duplicated.
4417 Insns are also again known to be executed each iteration at
4418 the LOOP_CONT note. */
4424 loop_depth++;
4426 loop_depth--;
4427 }
4429 /* Note if we pass a loop latch. If we do, then we can not clear
4430 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4431 a loop since a jump before the last CODE_LABEL may have started
4432 a new loop iteration.
4434 Note that LOOP_TOP is only set for rotated loops and we need
4435 this check for all loops, so compare against the CODE_LABEL
4436 which immediately follows LOOP_START. */
4441 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4442 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4443 or not an insn is known to be executed each iteration of the
4444 loop, whether or not any iterations are known to occur.
4446 Therefore, if we have just passed a label and have no more labels
4447 between here and the test insn of the loop, and we have not passed
4448 a jump to the top of the loop, then we know these insns will be
4449 executed each iteration. */
4452 && !past_loop_latch
4457 }
4458 }
4459 \f
4460 static void
4462 {
4465 /* Temporary list pointers for traversing ivs->list. */
4472 /* Scan ivs->list to remove all regs that proved not to be bivs.
4473 Make a sanity check against regs->n_times_set. */
4475 {
4477 /* Above happens if register modified by subreg, etc. */
4478 /* Make sure it is not recognized as a basic induction var: */
4480 /* If never incremented, it is invariant that we decided not to
4481 move. So leave it alone. */
4483 {
4494 }
4495 else
4496 {
4501 }
4502 }
4503 }
4506 /* Determine how BIVS are initialized by looking through pre-header
4507 extended basic block. */
4508 static void
4510 {
4512 /* Temporary list pointers for traversing ivs->list. */
4515 rtx p;
4517 /* Find initial value for each biv by searching backwards from loop_start,
4518 halting at first label. Also record any test condition. */
4522 {
4523 rtx test;
4533 /* Record any test of a biv that branches around the loop if no store
4534 between it and the start of loop. We only care about tests with
4535 constants and registers and only certain of those. */
4545 {
4546 /* If an NE test, we have an initial value! */
4548 {
4552 }
4553 else
4555 }
4556 }
4557 }
4560 /* Look at the each biv and see if we can say anything better about its
4561 initial value from any initializing insns set up above. (This is done
4562 in two passes to avoid missing SETs in a PARALLEL.) */
4563 static void
4565 {
4567 /* Temporary list pointers for traversing ivs->list. */
4572 {
4573 rtx src;
4574 rtx note;
4579 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4580 is a constant, use the value of that. */
4586 else
4599 {
4603 {
4606 }
4607 }
4608 /* If we can't make it a giv,
4609 let biv keep initial value of "itself". */
4612 }
4613 }
4616 /* Search the loop for general induction variables. */
4618 static void
4620 {
4622 }
4625 /* For each giv for which we still don't know whether or not it is
4626 replaceable, check to see if it is replaceable because its final value
4627 can be calculated. */
4629 static void
4631 {
4636 {
4642 }
4643 }
4646 /* Return nonzero if it is possible to eliminate the biv BL provided
4647 all givs are reduced. This is possible if either the reg is not
4648 used outside the loop, or we can compute what its final value will
4649 be. */
4651 static int
4654 {
4655 /* For architectures with a decrement_and_branch_until_zero insn,
4656 don't do this if we put a REG_NONNEG note on the endtest for this
4657 biv. */
4659 #ifdef HAVE_decrement_and_branch_until_zero
4661 {
4666 }
4667 #endif
4669 /* Check that biv is used outside loop or if it has a final value.
4670 Compare against bl->init_insn rather than loop->start. We aren't
4671 concerned with any uses of the biv between init_insn and
4672 loop->start since these won't be affected by the value of the biv
4673 elsewhere in the function, so long as init_insn doesn't use the
4674 biv itself. */
4685 {
4693 }
4695 }
4698 /* Reduce each giv of BL that we have decided to reduce. */
4700 static void
4702 {
4706 {
4709 {
4712 /* If the code for derived givs immediately below has already
4713 allocated a new_reg, we must keep it. */
4717 #ifdef AUTO_INC_DEC
4718 /* If the target has auto-increment addressing modes, and
4719 this is an address giv, then try to put the increment
4720 immediately after its use, so that flow can create an
4721 auto-increment addressing mode. */
4724 /* We don't handle reversed biv's because bl->biv->insn
4725 does not have a valid INSN_LUID. */
4729 {
4730 /* If other giv's have been combined with this one, then
4731 this will work only if all uses of the other giv's occur
4732 before this giv's insn. This is difficult to check.
4734 We simplify this by looking for the common case where
4735 there is one DEST_REG giv, and this giv's insn is the
4736 last use of the dest_reg of that DEST_REG giv. If the
4737 increment occurs after the address giv, then we can
4738 perform the optimization. (Otherwise, the increment
4739 would have to go before other_giv, and we would not be
4740 able to combine it with the address giv to get an
4741 auto-inc address.) */
4743 {
4748 {
4751 else
4753 }
4760 }
4761 /* Check for case where increment is before the address
4762 giv. Do this test in "loop order". */
4771 else
4774 #ifdef HAVE_cc0
4775 {
4776 rtx prev;
4778 /* We can't put an insn immediately after one setting
4779 cc0, or immediately before one using cc0. */
4786 }
4787 #endif
4791 }
4792 #endif
4794 /* For each place where the biv is incremented, add an insn
4795 to increment the new, reduced reg for the giv. */
4797 {
4798 rtx insert_before;
4800 /* Skip if location is the same as a previous one. */
4807 else
4815 /* A multiply is acceptable here
4816 since this is presumed to be seldom executed. */
4820 }
4822 /* Add code at loop start to initialize giv's reduced reg. */
4827 }
4828 }
4829 }
4832 /* Check for givs whose first use is their definition and whose
4833 last use is the definition of another giv. If so, it is likely
4834 dead and should not be used to derive another giv nor to
4835 eliminate a biv. */
4837 static void
4839 {
4843 {
4850 {
4856 }
4857 }
4858 }
4861 static void
4863 {
4867 {
4874 /* Update expression if this was combined, in case other giv was
4875 replaced. */
4880 /* See if this register is known to be a pointer to something. If
4881 so, see if we can find the alignment. First see if there is a
4882 destination register that is a pointer. If so, this shares the
4883 alignment too. Next see if we can deduce anything from the
4884 computational information. If not, and this is a DEST_ADDR
4885 giv, at least we know that it's a pointer, though we don't know
4886 the alignment. */
4894 {
4903 }
4907 {
4915 }
4920 /* Store reduced reg as the address in the memref where we found
4921 this giv. */
4924 {
4926 }
4927 else
4928 {
4930 rtx note;
4932 /* Not replaceable; emit an insn to set the original giv reg from
4933 the reduced giv, same as above. */
4938 /* The original insn may have a REG_EQUAL note. This note is
4939 now incorrect and may result in invalid substitutions later.
4940 The original insn is dead, but may be part of a libcall
4941 sequence, which doesn't seem worth the bother of handling. */
4945 }
4947 /* When a loop is reversed, givs which depend on the reversed
4948 biv, and which are live outside the loop, must be set to their
4949 correct final value. This insn is only needed if the giv is
4950 not replaceable. The correct final value is the same as the
4951 value that the giv starts the reversed loop with. */
4962 {
4967 }
4968 }
4969 }
4972 static int
4975 rtx test_reg)
4976 {
4985 /* Reduce benefit if not replaceable, since we will insert a
4986 move-insn to replace the insn that calculates this giv. Don't do
4987 this unless the giv is a user variable, since it will often be
4988 marked non-replaceable because of the duplication of the exit
4989 code outside the loop. In such a case, the copies we insert are
4990 dead and will be deleted. So they don't have a cost. Similar
4991 situations exist. */
4992 /* ??? The new final_[bg]iv_value code does a much better job of
4993 finding replaceable giv's, and hence this code may no longer be
4994 necessary. */
4999 /* Decrease the benefit to count the add-insns that we will insert
5000 to increment the reduced reg for the giv. ??? This can
5001 overestimate the run-time cost of the additional insns, e.g. if
5002 there are multiple basic blocks that increment the biv, but only
5003 one of these blocks is executed during each iteration. There is
5004 no good way to detect cases like this with the current structure
5005 of the loop optimizer. This code is more accurate for
5006 determining code size than run-time benefits. */
5009 /* Decide whether to strength-reduce this giv or to leave the code
5010 unchanged (recompute it from the biv each time it is used). This
5011 decision can be made independently for each giv. */
5013 #ifdef AUTO_INC_DEC
5014 /* Attempt to guess whether autoincrement will handle some of the
5015 new add insns; if so, increase BENEFIT (undo the subtraction of
5016 add_cost that was done above). */
5018 /* Increasing the benefit is risky, since this is only a guess.
5019 Avoid increasing register pressure in cases where there would
5020 be no other benefit from reducing this giv. */
5023 {
5038 }
5039 #endif
5042 }
5045 /* Free IV structures for LOOP. */
5047 static void
5049 {
5056 {
5062 {
5065 }
5067 {
5070 }
5074 }
5075 }
5078 /* Perform strength reduction and induction variable elimination.
5080 Pseudo registers created during this function will be beyond the
5081 last valid index in several tables including
5082 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5083 problem here, because the added registers cannot be givs outside of
5084 their loop, and hence will never be reconsidered. But scan_loop
5085 must check regnos to make sure they are in bounds. */
5087 static void
5089 {
5093 rtx p;
5094 /* Temporary list pointer for traversing ivs->list. */
5096 /* Ratio of extra register life span we can justify
5097 for saving an instruction. More if loop doesn't call subroutines
5098 since in that case saving an insn makes more difference
5099 and more registers are available. */
5100 /* ??? could set this to last value of threshold in move_movables */
5102 /* Map of pseudo-register replacements. */
5114 /* Find all BIVs in loop. */
5117 /* Exit if there are no bivs. */
5119 {
5120 /* Can still unroll the loop anyways, but indicate that there is no
5121 strength reduction info available. */
5127 }
5129 /* Determine how BIVS are initialized by looking through pre-header
5130 extended basic block. */
5133 /* Look at the each biv and see if we can say anything better about its
5134 initial value from any initializing insns set up above. */
5137 /* Search the loop for general induction variables. */
5140 /* Try to calculate and save the number of loop iterations. This is
5141 set to zero if the actual number can not be calculated. This must
5142 be called after all giv's have been identified, since otherwise it may
5143 fail if the iteration variable is a giv. */
5146 #ifdef HAVE_prefetch
5149 #endif
5151 /* Now for each giv for which we still don't know whether or not it is
5152 replaceable, check to see if it is replaceable because its final value
5153 can be calculated. This must be done after loop_iterations is called,
5154 so that final_giv_value will work correctly. */
5157 /* Try to prove that the loop counter variable (if any) is always
5158 nonnegative; if so, record that fact with a REG_NONNEG note
5159 so that "decrement and branch until zero" insn can be used. */
5162 /* Create reg_map to hold substitutions for replaceable giv regs.
5163 Some givs might have been made from biv increments, so look at
5164 ivs->reg_iv_type for a suitable size. */
5168 /* Examine each iv class for feasibility of strength reduction/induction
5169 variable elimination. */
5172 {
5176 /* Test whether it will be possible to eliminate this biv
5177 provided all givs are reduced. */
5180 /* This will be true at the end, if all givs which depend on this
5181 biv have been strength reduced.
5182 We can't (currently) eliminate the biv unless this is so. */
5185 /* Check each extension dependent giv in this class to see if its
5186 root biv is safe from wrapping in the interior mode. */
5189 /* Combine all giv's for this iv_class. */
5193 {
5201 /* If an insn is not to be strength reduced, then set its ignore
5202 flag, and clear bl->all_reduced. */
5204 /* A giv that depends on a reversed biv must be reduced if it is
5205 used after the loop exit, otherwise, it would have the wrong
5206 value after the loop exit. To make it simple, just reduce all
5207 of such giv's whether or not we know they are used after the loop
5208 exit. */
5213 {
5221 }
5222 else
5223 {
5224 /* Check that we can increment the reduced giv without a
5225 multiply insn. If not, reject it. */
5230 {
5238 }
5239 }
5240 }
5242 /* Check for givs whose first use is their definition and whose
5243 last use is the definition of another giv. If so, it is likely
5244 dead and should not be used to derive another giv nor to
5245 eliminate a biv. */
5248 /* Reduce each giv that we decided to reduce. */
5251 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5252 as not reduced.
5254 For each giv register that can be reduced now: if replaceable,
5255 substitute reduced reg wherever the old giv occurs;
5256 else add new move insn "giv_reg = reduced_reg". */
5259 /* All the givs based on the biv bl have been reduced if they
5260 merit it. */
5262 /* For each giv not marked as maybe dead that has been combined with a
5263 second giv, clear any "maybe dead" mark on that second giv.
5264 v->new_reg will either be or refer to the register of the giv it
5265 combined with.
5267 Doing this clearing avoids problems in biv elimination where
5268 a giv's new_reg is a complex value that can't be put in the
5269 insn but the giv combined with (with a reg as new_reg) is
5270 marked maybe_dead. Since the register will be used in either
5271 case, we'd prefer it be used from the simpler giv. */
5277 /* Try to eliminate the biv, if it is a candidate.
5278 This won't work if ! bl->all_reduced,
5279 since the givs we planned to use might not have been reduced.
5281 We have to be careful that we didn't initially think we could
5282 eliminate this biv because of a giv that we now think may be
5283 dead and shouldn't be used as a biv replacement.
5285 Also, there is the possibility that we may have a giv that looks
5286 like it can be used to eliminate a biv, but the resulting insn
5287 isn't valid. This can happen, for example, on the 88k, where a
5288 JUMP_INSN can compare a register only with zero. Attempts to
5289 replace it with a compare with a constant will fail.
5291 Note that in cases where this call fails, we may have replaced some
5292 of the occurrences of the biv with a giv, but no harm was done in
5293 doing so in the rare cases where it can occur. */
5297 {
5298 /* ?? If we created a new test to bypass the loop entirely,
5299 or otherwise drop straight in, based on this test, then
5300 we might want to rewrite it also. This way some later
5301 pass has more hope of removing the initialization of this
5302 biv entirely. */
5304 /* If final_value != 0, then the biv may be used after loop end
5305 and we must emit an insn to set it just in case.
5307 Reversed bivs already have an insn after the loop setting their
5308 value, so we don't need another one. We can't calculate the
5309 proper final value for such a biv here anyways. */
5318 }
5319 /* See above note wrt final_value. But since we couldn't eliminate
5320 the biv, we must set the value after the loop instead of before. */
5324 }
5326 /* Go through all the instructions in the loop, making all the
5327 register substitutions scheduled in REG_MAP. */
5332 {
5336 }
5339 {
5340 /* When we completely unroll a loop we will likely not need the increment
5341 of the loop BIV and we will not need the conditional branch at the
5342 end of the loop. */
5345 #ifdef HAVE_cc0
5346 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5347 need the comparison before the conditional branch at the end of the
5348 loop. */
5350 #endif
5352 /* We'll need one copy for each loop iteration. */
5355 /* A little slop to account for the ability to remove initialization
5356 code, better CSE, and other secondary benefits of completely
5357 unrolling some loops. */
5360 /* Clamp the value. */
5363 }
5365 /* Unroll loops from within strength reduction so that we can use the
5366 induction variable information that strength_reduce has already
5367 collected. Always unroll loops that would be as small or smaller
5368 unrolled than when rolled. */
5375 #ifdef HAVE_doloop_end
5380 /* In case number of iterations is known, drop branch prediction note
5381 in the branch. Do that only in second loop pass, as loop unrolling
5382 may change the number of iterations performed. */
5384 {
5385 unsigned HOST_WIDE_INT n
5390 }
5398 }
5399 \f
5400 /*Record all basic induction variables calculated in the insn. */
5401 static rtx
5404 {
5406 rtx set;
5407 rtx dest_reg;
5408 rtx inc_val;
5409 rtx mult_val;
5415 {
5420 {
5425 {
5426 /* It is a possible basic induction variable.
5427 Create and initialize an induction structure for it. */
5434 }
5437 }
5438 }
5440 }
5441 \f
5442 /* Record all givs calculated in the insn.
5443 A register is a giv if: it is only set once, it is a function of a
5444 biv and a constant (or invariant), and it is not a biv. */
5445 static rtx
5448 {
5451 rtx set;
5452 /* Look for a general induction variable in a register. */
5457 {
5458 rtx src_reg;
5459 rtx dest_reg;
5460 rtx add_val;
5461 rtx mult_val;
5462 rtx ext_val;
5465 rtx last_consec_insn;
5474 /* Equivalent expression is a giv. */
5479 /* Don't try to handle any regs made by loop optimization.
5480 We have nothing on them in regno_first_uid, etc. */
5482 /* Don't recognize a BASIC_INDUCT_VAR here. */
5484 /* This must be the only place where the register is set. */
5486 /* or all sets must be consecutive and make a giv. */
5491 {
5494 /* If this is a library call, increase benefit. */
5498 /* Skip the consecutive insns, if there are any. */
5506 }
5507 }
5509 /* Look for givs which are memory addresses. */
5512 maybe_multiple);
5514 /* Update the status of whether giv can derive other givs. This can
5515 change when we pass a label or an insn that updates a biv. */
5520 }
5521 \f
5522 /* Return 1 if X is a valid source for an initial value (or as value being
5523 compared against in an initial test).
5525 X must be either a register or constant and must not be clobbered between
5526 the current insn and the start of the loop.
5528 INSN is the insn containing X. */
5530 static int
5532 {
5536 /* Only consider pseudos we know about initialized in insns whose luids
5537 we know. */
5542 /* Don't use call-clobbered registers across a call which clobbers it. On
5543 some machines, don't use any hard registers at all. */
5545 && (SMALL_REGISTER_CLASSES
5549 /* Don't use registers that have been clobbered before the start of the
5550 loop. */
5555 }
5556 \f
5557 /* Scan X for memory refs and check each memory address
5558 as a possible giv. INSN is the insn whose pattern X comes from.
5559 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5560 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5561 more than once in each loop iteration. */
5563 static void
5566 {
5576 {
5592 {
5593 rtx src_reg;
5594 rtx add_val;
5595 rtx mult_val;
5596 rtx ext_val;
5599 /* This code used to disable creating GIVs with mult_val == 1 and
5600 add_val == 0. However, this leads to lost optimizations when
5601 it comes time to combine a set of related DEST_ADDR GIVs, since
5602 this one would not be seen. */
5607 {
5608 /* Found one; record it. */
5616 }
5617 }
5622 }
5624 /* Recursively scan the subexpressions for other mem refs. */
5630 maybe_multiple);
5634 maybe_multiple);
5635 }
5636 \f
5637 /* Fill in the data about one biv update.
5638 V is the `struct induction' in which we record the biv. (It is
5639 allocated by the caller, with alloca.)
5640 INSN is the insn that sets it.
5641 DEST_REG is the biv's reg.
5643 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5644 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5645 being set to INC_VAL.
5647 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5648 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5649 can be executed more than once per iteration. If MAYBE_MULTIPLE
5650 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5651 executed exactly once per iteration. */
5653 static void
5657 {
5674 /* Add this to the reg's iv_class, creating a class
5675 if this is the first incrementation of the reg. */
5679 {
5680 /* Create and initialize new iv_class. */
5690 /* Set initial value to the reg itself. */
5693 /* We haven't seen the initializing insn yet. */
5703 /* Add this class to ivs->list. */
5707 /* Put it in the array of biv register classes. */
5709 }
5710 else
5711 {
5712 /* Check if location is the same as a previous one. */
5716 {
5719 }
5720 }
5722 /* Update IV_CLASS entry for this biv. */
5731 }
5732 \f
5733 /* Fill in the data about one giv.
5734 V is the `struct induction' in which we record the giv. (It is
5735 allocated by the caller, with alloca.)
5736 INSN is the insn that sets it.
5737 BENEFIT estimates the savings from deleting this insn.
5738 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5739 into a register or is used as a memory address.
5741 SRC_REG is the biv reg which the giv is computed from.
5742 DEST_REG is the giv's reg (if the giv is stored in a reg).
5743 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5744 LOCATION points to the place where this giv's value appears in INSN. */
5746 static void
5751 {
5756 rtx temp;
5758 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5759 undo the MULT canonicalization that we performed earlier. */
5789 /* The v->always_computable field is used in update_giv_derive, to
5790 determine whether a giv can be used to derive another giv. For a
5791 DEST_REG giv, INSN computes a new value for the giv, so its value
5792 isn't computable if INSN insn't executed every iteration.
5793 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5794 it does not compute a new value. Hence the value is always computable
5795 regardless of whether INSN is executed each iteration. */
5799 else
5805 {
5808 }
5810 {
5815 /* If the lifetime is zero, it means that this register is
5816 really a dead store. So mark this as a giv that can be
5817 ignored. This will not prevent the biv from being eliminated. */
5823 }
5825 /* Add the giv to the class of givs computed from one biv. */
5829 {
5832 /* Don't count DEST_ADDR. This is supposed to count the number of
5833 insns that calculate givs. */
5837 }
5838 else
5839 /* Fatal error, biv missing for this giv? */
5843 {
5846 }
5847 else
5848 {
5849 /* The giv can be replaced outright by the reduced register only if all
5850 of the following conditions are true:
5851 - the insn that sets the giv is always executed on any iteration
5852 on which the giv is used at all
5853 (there are two ways to deduce this:
5854 either the insn is executed on every iteration,
5855 or all uses follow that insn in the same basic block),
5856 - the giv is not used outside the loop
5857 - no assignments to the biv occur during the giv's lifetime. */
5860 /* Previous line always fails if INSN was moved by loop opt. */
5863 && (! not_every_iteration
5865 {
5866 /* Now check that there are no assignments to the biv within the
5867 giv's lifetime. This requires two separate checks. */
5869 /* Check each biv update, and fail if any are between the first
5870 and last use of the giv.
5872 If this loop contains an inner loop that was unrolled, then
5873 the insn modifying the biv may have been emitted by the loop
5874 unrolling code, and hence does not have a valid luid. Just
5875 mark the biv as not replaceable in this case. It is not very
5876 useful as a biv, because it is used in two different loops.
5877 It is very unlikely that we would be able to optimize the giv
5878 using this biv anyways. */
5883 {
5889 {
5893 }
5894 }
5896 /* If there are any backwards branches that go from after the
5897 biv update to before it, then this giv is not replaceable. */
5901 {
5905 }
5906 }
5907 else
5908 {
5909 /* May still be replaceable, we don't have enough info here to
5910 decide. */
5913 }
5914 }
5916 /* Record whether the add_val contains a const_int, for later use by
5917 combine_givs. */
5918 {
5923 ;
5927 {
5929 {
5934 else
5936 }
5939 }
5940 }
5944 }
5946 /* All this does is determine whether a giv can be made replaceable because
5947 its final value can be calculated. This code can not be part of record_giv
5948 above, because final_giv_value requires that the number of loop iterations
5949 be known, and that can not be accurately calculated until after all givs
5950 have been identified. */
5952 static void
5954 {
5957 /* DEST_ADDR givs will never reach here, because they are always marked
5958 replaceable above in record_giv. */
5960 /* The giv can be replaced outright by the reduced register only if all
5961 of the following conditions are true:
5962 - the insn that sets the giv is always executed on any iteration
5963 on which the giv is used at all
5964 (there are two ways to deduce this:
5965 either the insn is executed on every iteration,
5966 or all uses follow that insn in the same basic block),
5967 - its final value can be calculated (this condition is different
5968 than the one above in record_giv)
5969 - it's not used before the it's set
5970 - no assignments to the biv occur during the giv's lifetime. */
5972 #if 0
5973 /* This is only called now when replaceable is known to be false. */
5974 /* Clear replaceable, so that it won't confuse final_giv_value. */
5976 #endif
5981 {
5984 rtx last_giv_use;
5989 /* When trying to determine whether or not a biv increment occurs
5990 during the lifetime of the giv, we can ignore uses of the variable
5991 outside the loop because final_value is true. Hence we can not
5992 use regno_last_uid and regno_first_uid as above in record_giv. */
5994 /* Search the loop to determine whether any assignments to the
5995 biv occur during the giv's lifetime. Start with the insn
5996 that sets the giv, and search around the loop until we come
5997 back to that insn again.
5999 Also fail if there is a jump within the giv's lifetime that jumps
6000 to somewhere outside the lifetime but still within the loop. This
6001 catches spaghetti code where the execution order is not linear, and
6002 hence the above test fails. Here we assume that the giv lifetime
6003 does not extend from one iteration of the loop to the next, so as
6004 to make the test easier. Since the lifetime isn't known yet,
6005 this requires two loops. See also record_giv above. */
6010 {
6013 {
6016 }
6022 {
6023 /* It is possible for the BIV increment to use the GIV if we
6024 have a cycle. Thus we must be sure to check each insn for
6025 both BIV and GIV uses, and we must check for BIV uses
6026 first. */
6033 {
6035 {
6039 }
6041 }
6042 }
6043 }
6045 /* Now that the lifetime of the giv is known, check for branches
6046 from within the lifetime to outside the lifetime if it is still
6047 replaceable. */
6050 {
6053 {
6066 {
6075 }
6076 }
6077 }
6079 /* If it is replaceable, then save the final value. */
6082 }
6087 }
6088 \f
6089 /* Update the status of whether a giv can derive other givs.
6091 We need to do something special if there is or may be an update to the biv
6092 between the time the giv is defined and the time it is used to derive
6093 another giv.
6095 In addition, a giv that is only conditionally set is not allowed to
6096 derive another giv once a label has been passed.
6098 The cases we look at are when a label or an update to a biv is passed. */
6100 static void
6102 {
6106 rtx tem;
6109 /* Search all IV classes, then all bivs, and finally all givs.
6111 There are three cases we are concerned with. First we have the situation
6112 of a giv that is only updated conditionally. In that case, it may not
6113 derive any givs after a label is passed.
6115 The second case is when a biv update occurs, or may occur, after the
6116 definition of a giv. For certain biv updates (see below) that are
6117 known to occur between the giv definition and use, we can adjust the
6118 giv definition. For others, or when the biv update is conditional,
6119 we must prevent the giv from deriving any other givs. There are two
6120 sub-cases within this case.
6122 If this is a label, we are concerned with any biv update that is done
6123 conditionally, since it may be done after the giv is defined followed by
6124 a branch here (actually, we need to pass both a jump and a label, but
6125 this extra tracking doesn't seem worth it).
6127 If this is a jump, we are concerned about any biv update that may be
6128 executed multiple times. We are actually only concerned about
6129 backward jumps, but it is probably not worth performing the test
6130 on the jump again here.
6132 If this is a biv update, we must adjust the giv status to show that a
6133 subsequent biv update was performed. If this adjustment cannot be done,
6134 the giv cannot derive further givs. */
6140 {
6141 /* Skip if location is the same as a previous one. */
6146 {
6147 /* If cant_derive is already true, there is no point in
6148 checking all of these conditions again. */
6152 /* If this giv is conditionally set and we have passed a label,
6153 it cannot derive anything. */
6157 /* Skip givs that have mult_val == 0, since
6158 they are really invariants. Also skip those that are
6159 replaceable, since we know their lifetime doesn't contain
6160 any biv update. */
6164 /* The only way we can allow this giv to derive another
6165 is if this is a biv increment and we can form the product
6166 of biv->add_val and giv->mult_val. In this case, we will
6167 be able to compute a compensation. */
6169 {
6170 rtx ext_val_dummy;
6181 tem = simplify_giv_expr
6188 else
6190 }
6194 }
6195 }
6196 }
6197 \f
6198 /* Check whether an insn is an increment legitimate for a basic induction var.
6199 X is the source of insn P, or a part of it.
6200 MODE is the mode in which X should be interpreted.
6202 DEST_REG is the putative biv, also the destination of the insn.
6203 We accept patterns of these forms:
6204 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6205 REG = INVARIANT + REG
6207 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6208 store the additive term into *INC_VAL, and store the place where
6209 we found the additive term into *LOCATION.
6211 If X is an assignment of an invariant into DEST_REG, we set
6212 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6214 We also want to detect a BIV when it corresponds to a variable
6215 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6216 of the variable may be a PLUS that adds a SUBREG of that variable to
6217 an invariant and then sign- or zero-extends the result of the PLUS
6218 into the variable.
6220 Most GIVs in such cases will be in the promoted mode, since that is the
6221 probably the natural computation mode (and almost certainly the mode
6222 used for addresses) on the machine. So we view the pseudo-reg containing
6223 the variable as the BIV, as if it were simply incremented.
6225 Note that treating the entire pseudo as a BIV will result in making
6226 simple increments to any GIVs based on it. However, if the variable
6227 overflows in its declared mode but not its promoted mode, the result will
6228 be incorrect. This is acceptable if the variable is signed, since
6229 overflows in such cases are undefined, but not if it is unsigned, since
6230 those overflows are defined. So we only check for SIGN_EXTEND and
6231 not ZERO_EXTEND.
6233 If we cannot find a biv, we return 0. */
6235 static int
6239 {
6247 {
6253 {
6255 }
6260 {
6262 }
6263 else
6270 /* convert_modes can emit new instructions, e.g. when arg is a loop
6271 invariant MEM and dest_reg has a different mode.
6272 These instructions would be emitted after the end of the function
6273 and then *inc_val would be an uninitialized pseudo.
6274 Detect this and bail in this case.
6275 Other alternatives to solve this can be introducing a convert_modes
6276 variant which is allowed to fail but not allowed to emit new
6277 instructions, emit these instructions before loop start and let
6278 it be garbage collected if *inc_val is never used or saving the
6279 *inc_val initialization sequence generated here and when *inc_val
6280 is going to be actually used, emit it at some suitable place. */
6284 {
6287 }
6295 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6296 handle addition of promoted variables.
6297 ??? The comment at the start of this function is wrong: promoted
6298 variable increments don't look like it says they do. */
6304 /* If this register is assigned in a previous insn, look at its
6305 source, but don't go outside the loop or past a label. */
6307 /* If this sets a register to itself, we would repeat any previous
6308 biv increment if we applied this strategy blindly. */
6314 {
6315 rtx dest;
6316 do
6317 {
6319 }
6348 }
6349 /* Fall through. */
6351 /* Can accept constant setting of biv only when inside inner most loop.
6352 Otherwise, a biv of an inner loop may be incorrectly recognized
6353 as a biv of the outer loop,
6354 causing code to be moved INTO the inner loop. */
6361 /* convert_modes aborts if we try to convert to or from CCmode, so just
6362 exclude that case. It is very unlikely that a condition code value
6363 would be a useful iterator anyways. convert_modes aborts if we try to
6364 convert a float mode to non-float or vice versa too. */
6368 {
6369 /* Possible bug here? Perhaps we don't know the mode of X. */
6373 {
6376 }
6381 }
6382 else
6386 /* Ignore this BIV if signed arithmetic overflow is defined. */
6393 /* Similar, since this can be a sign extension. */
6398 ;
6412 location);
6417 }
6418 }
6419 \f
6420 /* A general induction variable (giv) is any quantity that is a linear
6421 function of a basic induction variable,
6422 i.e. giv = biv * mult_val + add_val.
6423 The coefficients can be any loop invariant quantity.
6424 A giv need not be computed directly from the biv;
6425 it can be computed by way of other givs. */
6427 /* Determine whether X computes a giv.
6428 If it does, return a nonzero value
6429 which is the benefit from eliminating the computation of X;
6430 set *SRC_REG to the register of the biv that it is computed from;
6431 set *ADD_VAL and *MULT_VAL to the coefficients,
6432 such that the value of X is biv * mult + add; */
6434 static int
6439 {
6443 /* If this is an invariant, forget it, it isn't a giv. */
6454 {
6457 /* Since this is now an invariant and wasn't before, it must be a giv
6458 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6459 with. */
6466 /* This is equivalent to a BIV. */
6473 /* Either (plus (biv) (invar)) or
6474 (plus (mult (biv) (invar_1)) (invar_2)). */
6476 {
6479 }
6480 else
6481 {
6484 }
6489 /* ADD_VAL is zero. */
6497 }
6499 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6500 unless they are CONST_INT). */
6508 else
6511 /* Always return true if this is a giv so it will be detected as such,
6512 even if the benefit is zero or negative. This allows elimination
6513 of bivs that might otherwise not be eliminated. */
6515 }
6516 \f
6517 /* Given an expression, X, try to form it as a linear function of a biv.
6518 We will canonicalize it to be of the form
6519 (plus (mult (BIV) (invar_1))
6520 (invar_2))
6521 with possible degeneracies.
6523 The invariant expressions must each be of a form that can be used as a
6524 machine operand. We surround then with a USE rtx (a hack, but localized
6525 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6526 routine; it is the caller's responsibility to strip them.
6528 If no such canonicalization is possible (i.e., two biv's are used or an
6529 expression that is neither invariant nor a biv or giv), this routine
6530 returns 0.
6532 For a nonzero return, the result will have a code of CONST_INT, USE,
6533 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6535 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6540 static rtx
6542 {
6547 rtx tem;
6549 /* If this is not an integer mode, or if we cannot do arithmetic in this
6550 mode, this can't be a giv. */
6557 {
6564 /* Put constant last, CONST_INT last if both constant. */
6572 /* Handle addition of zero, then addition of an invariant. */
6577 {
6580 /* Adding two invariants must result in an invariant, so enclose
6581 addition operation inside a USE and return it. */
6591 else
6600 /* biv + invar or mult + invar. Return sum. */
6604 /* (a + invar_1) + invar_2. Associate. */
6605 return
6611 arg1)),
6616 }
6618 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6619 MULT to reduce cases. */
6625 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6626 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6627 Recurse to associate the second PLUS. */
6632 return
6640 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6656 /* Handle "a - b" as "a + b * (-1)". */
6662 constm1_rtx)),
6671 /* Put constant last, CONST_INT last if both constant. */
6676 /* If second argument is not now constant, not giv. */
6680 /* Handle multiply by 0 or 1. */
6688 {
6690 /* biv * invar. Done. */
6694 /* Product of two constants. */
6698 /* invar * invar is a giv, but attempt to simplify it somehow. */
6704 {
6705 /* (invar_0 * invar_1) * invar_2. Associate. */
6712 arg1)),
6714 }
6715 /* Propagate the MULT expressions to the innermost nodes. */
6717 {
6718 /* (invar_0 + invar_1) * invar_2. Distribute. */
6724 arg1),
6728 arg1)),
6730 }
6734 /* (a * invar_1) * invar_2. Associate. */
6740 arg1)),
6744 /* (a + invar_1) * invar_2. Distribute. */
6749 arg1),
6752 arg1)),
6757 }
6760 /* Shift by constant is multiply by power of two. */
6764 return
6773 /* "-a" is "a * (-1)" */
6779 /* "~a" is "-a - 1". Silly, but easy. */
6783 const1_rtx),
6787 /* Already in proper form for invariant. */
6793 /* Conditionally recognize extensions of simple IVs. After we've
6794 computed loop traversal counts and verified the range of the
6795 source IV, we'll reevaluate this as a GIV. */
6797 {
6800 {
6803 }
6804 }
6808 /* If this is a new register, we can't deal with it. */
6812 /* Check for biv or giv. */
6814 {
6818 {
6821 /* Form expression from giv and add benefit. Ensure this giv
6822 can derive another and subtract any needed adjustment if so. */
6824 /* Increasing the benefit here is risky. The only case in which it
6825 is arguably correct is if this is the only use of V. In other
6826 cases, this will artificially inflate the benefit of the current
6827 giv, and lead to suboptimal code. Thus, it is disabled, since
6828 potentially not reducing an only marginally beneficial giv is
6829 less harmful than reducing many givs that are not really
6830 beneficial. */
6831 {
6835 }
6848 {
6851 }
6852 else
6853 {
6856 }
6858 }
6861 do_default:
6862 /* If it isn't an induction variable, and it is invariant, we
6863 may be able to simplify things further by looking through
6864 the bits we just moved outside the loop. */
6866 {
6872 {
6873 /* Ok, we found a match. Substitute and simplify. */
6875 /* If we match another movable, we must use that, as
6876 this one is going away. */
6881 /* If consec is nonzero, this is a member of a group of
6882 instructions that were moved together. We handle this
6883 case only to the point of seeking to the last insn and
6884 looking for a REG_EQUAL. Fail if we don't find one. */
6886 {
6889 do
6890 {
6892 }
6898 }
6899 else
6900 {
6904 }
6907 {
6908 /* What we are most interested in is pointer
6909 arithmetic on invariants -- only take
6910 patterns we may be able to do something with. */
6916 {
6918 benefit);
6921 }
6926 {
6931 }
6932 }
6934 }
6935 }
6937 }
6939 /* Fall through to general case. */
6941 /* If invariant, return as USE (unless CONST_INT).
6942 Otherwise, not giv. */
6947 {
6956 }
6957 else
6959 }
6960 }
6962 /* This routine folds invariants such that there is only ever one
6963 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6965 static rtx
6967 {
6973 {
6976 }
6979 {
6982 }
6983 else
6984 {
6987 }
6988 }
6990 static rtx
6992 {
6994 {
6998 else
7001 }
7004 else
7007 }
7008 \f
7009 /* Help detect a giv that is calculated by several consecutive insns;
7010 for example,
7011 giv = biv * M
7012 giv = giv + A
7013 The caller has already identified the first insn P as having a giv as dest;
7014 we check that all other insns that set the same register follow
7015 immediately after P, that they alter nothing else,
7016 and that the result of the last is still a giv.
7018 The value is 0 if the reg set in P is not really a giv.
7019 Otherwise, the value is the amount gained by eliminating
7020 all the consecutive insns that compute the value.
7022 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7023 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7025 The coefficients of the ultimate giv value are stored in
7026 *MULT_VAL and *ADD_VAL. */
7028 static int
7032 {
7038 rtx temp;
7039 rtx set;
7041 /* Indicate that this is a giv so that we can update the value produced in
7042 each insn of the multi-insn sequence.
7044 This induction structure will be used only by the call to
7045 general_induction_var below, so we can allocate it on our stack.
7046 If this is a giv, our caller will replace the induct var entry with
7047 a new induction structure. */
7068 {
7072 /* If libcall, skip to end of call sequence. */
7083 /* Giv created by equivalent expression. */
7089 {
7093 count--;
7097 }
7099 {
7100 /* Allow insns that set something other than this giv to a
7101 constant. Such insns are needed on machines which cannot
7102 include long constants and should not disqualify a giv. */
7111 }
7112 }
7117 }
7118 \f
7119 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7120 represented by G1. If no such expression can be found, or it is clear that
7121 it cannot possibly be a valid address, 0 is returned.
7123 To perform the computation, we note that
7124 G1 = x * v + a and
7125 G2 = y * v + b
7126 where `v' is the biv.
7128 So G2 = (y/b) * G1 + (b - a*y/x).
7130 Note that MULT = y/x.
7132 Update: A and B are now allowed to be additive expressions such that
7133 B contains all variables in A. That is, computing B-A will not require
7134 subtracting variables. */
7136 static rtx
7138 {
7139 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7144 /* If MULT is not 1, we cannot handle A with non-constants, since we
7145 would then be required to subtract multiples of the registers in A.
7146 This is theoretically possible, and may even apply to some Fortran
7147 constructs, but it is a lot of work and we do not attempt it here. */
7152 /* In general these structures are sorted top to bottom (down the PLUS
7153 chain), but not left to right across the PLUS. If B is a higher
7154 order giv than A, we can strip one level and recurse. If A is higher
7155 order, we'll eventually bail out, but won't know that until the end.
7156 If they are the same, we'll strip one level around this loop. */
7159 {
7171 /* We matched: remove one reg completely. */
7174 /* An alternate match. */
7177 /* An alternate match. */
7179 else
7180 {
7181 /* Indicates an extra register in B. Strip one level from B and
7182 recurse, hoping B was the higher order expression. */
7187 }
7188 }
7190 /* Here we are at the last level of A, go through the cases hoping to
7191 get rid of everything but a constant. */
7194 {
7207 }
7209 {
7211 }
7213 {
7218 }
7220 {
7225 else
7227 }
7232 }
7234 rtx
7236 {
7239 /* The value that G1 will be multiplied by must be a constant integer. Also,
7240 the only chance we have of getting a valid address is if b*c/a (see above
7241 for notation) is also an integer. */
7244 {
7252 }
7255 else
7256 {
7257 /* ??? Find out if the one is a multiple of the other? */
7259 }
7263 {
7264 /* Failed. If we've got a multiplication factor between G1 and G2,
7265 scale G1's addend and try again. */
7267 {
7271 {
7272 HOST_WIDE_INT m;
7276 }
7277 else
7278 {
7280 mult);
7281 }
7284 }
7285 }
7289 /* Form simplified final result. */
7294 else
7299 else
7300 {
7303 {
7307 }
7310 }
7311 }
7312 \f
7313 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7314 represented by G1. This indicates that G2 should be combined with G1 and
7315 that G2 can use (either directly or via an address expression) a register
7316 used to represent G1. */
7318 static rtx
7320 {
7323 /* With the introduction of ext dependent givs, we must care for modes.
7324 G2 must not use a wider mode than G1. */
7334 /* If these givs are identical, they can be combined. We use the results
7335 of express_from because the addends are not in a canonical form, so
7336 rtx_equal_p is a weaker test. */
7337 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7338 combination to be the other way round. */
7341 {
7343 }
7345 /* If G2 can be expressed as a function of G1 and that function is valid
7346 as an address and no more expensive than using a register for G2,
7347 the expression of G2 in terms of G1 can be used. */
7354 }
7355 \f
7356 /* Check each extension dependent giv in this class to see if its
7357 root biv is safe from wrapping in the interior mode, which would
7358 make the giv illegal. */
7360 static void
7362 {
7366 HOST_WIDE_INT start_val;
7372 /* Make sure the iteration data is available. We must have
7373 constants in order to be certain of no overflow. */
7379 /* Make sure the host can represent the arithmetic. */
7381 {
7383 HOST_WIDE_INT s_end_val;
7395 /* Check for host arithmetic overflow. */
7397 {
7399 HOST_WIDE_INT s_max;
7406 /* Check zero extension of biv ok. */
7408 /* Check for host arithmetic overflow. */
7409 && (neg_incr
7412 /* Check for target arithmetic overflow. */
7413 && (neg_incr
7416 {
7418 }
7420 /* Check sign extension of biv ok. */
7421 /* ??? While it is true that overflow with signed and pointer
7422 arithmetic is undefined, I fear too many programmers don't
7423 keep this fact in mind -- myself included on occasion.
7424 So leave alone with the signed overflow optimizations. */
7426 /* Check for host arithmetic overflow. */
7427 && (neg_incr
7430 /* Check for target arithmetic overflow. */
7431 && (neg_incr
7434 {
7436 }
7437 }
7438 }
7440 /* If we know the BIV is compared at run-time against an
7441 invariant value, and the increment is +/- 1, we may also
7442 be able to prove that the BIV cannot overflow. */
7448 {
7449 /* If the increment is +1, and the exit test is a <,
7450 the BIV cannot overflow. (For <=, we have the
7451 problematic case that the comparison value might
7452 be the maximum value of the range.) */
7454 {
7459 }
7461 /* Likewise for increment -1 and exit test >. */
7463 {
7468 }
7469 }
7471 /* Invalidate givs that fail the tests. */
7474 {
7479 {
7488 /* We don't know whether this value is being used as either
7489 signed or unsigned, so to safely truncate we must satisfy
7490 both. The initial check here verifies the BIV itself;
7491 once that is successful we may check its range wrt the
7492 derived GIV. This works only if we were able to determine
7493 constant start and end values above. */
7495 {
7499 /* We know from the above that both endpoints are nonnegative,
7500 and that there is no wrapping. Verify that both endpoints
7501 are within the (signed) range of the outer mode. */
7504 }
7509 }
7512 {
7514 {
7518 }
7519 }
7520 else
7521 {
7523 {
7528 else
7529 {
7534 else
7536 }
7541 }
7544 }
7545 }
7546 }
7548 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7550 rtx
7552 {
7558 /* Recall that check_ext_dependent_givs verified that the known bounds
7559 of a biv did not overflow or wrap with respect to the extension for
7560 the giv. Therefore, constants need no additional adjustment. */
7564 /* Otherwise, we must adjust the value to compensate for the
7565 differing modes of the biv and the giv. */
7567 }
7568 \f
7569 struct combine_givs_stats
7570 {
7573 };
7575 static int
7577 {
7584 /* Stabilize the sort. */
7588 }
7590 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7591 any other. If so, point SAME to the giv combined with and set NEW_REG to
7592 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7593 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7595 static void
7597 {
7598 /* Additional benefit to add for being combined multiple times. */
7606 /* Count givs, because bl->giv_count is incorrect here. */
7610 giv_count++;
7622 {
7624 rtx single_use;
7629 /* If a DEST_REG GIV is used only once, do not allow it to combine
7630 with anything, for in doing so we will gain nothing that cannot
7631 be had by simply letting the GIV with which we would have combined
7632 to be reduced on its own. The losage shows up in particular with
7633 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7634 be seen elsewhere as well. */
7641 /* Add an additional weight for zero addends. */
7646 {
7647 rtx this_combine;
7652 {
7655 }
7656 }
7658 }
7660 /* Iterate, combining until we can't. */
7661 restart:
7665 {
7668 {
7674 }
7676 }
7679 {
7685 /* If it has already been combined, skip. */
7690 {
7693 /* If it has already been combined, skip. */
7695 {
7700 /* For destination, we now may replace by mem expression instead
7701 of register. This changes the costs considerably, so add the
7702 compensation. */
7712 /* ??? The new final_[bg]iv_value code does a much better job
7713 of finding replaceable giv's, and hence this code may no
7714 longer be necessary. */
7718 /* To help optimize the next set of combinations, remove
7719 this giv from the benefits of other potential mates. */
7721 {
7725 }
7732 }
7733 }
7735 /* To help optimize the next set of combinations, remove
7736 this giv from the benefits of other potential mates. */
7738 {
7740 {
7744 }
7748 /* We've finished with this giv, and everything it touched.
7749 Restart the combination so that proper weights for the
7750 rest of the givs are properly taken into account. */
7751 /* ??? Ideally we would compact the arrays at this point, so
7752 as to not cover old ground. But sanely compacting
7753 can_combine is tricky. */
7755 }
7756 }
7758 /* Clean up. */
7761 }
7762 \f
7763 /* Generate sequence for REG = B * M + A. B is the initial value of
7764 the basic induction variable, M a multiplicative constant, A an
7765 additive constant and REG the destination register. */
7767 static rtx
7769 {
7770 rtx seq;
7771 rtx result;
7774 /* Use unsigned arithmetic. */
7782 }
7785 /* Update registers created in insn sequence SEQ. */
7787 static void
7789 {
7790 rtx insn;
7792 /* Update register info for alias analysis. */
7796 {
7803 }
7804 }
7807 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7808 is the initial value of the basic induction variable, M a
7809 multiplicative constant, A an additive constant and REG the
7810 destination register. */
7812 void
7815 {
7816 rtx seq;
7819 {
7822 }
7824 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7827 /* Increase the lifetime of any invariants moved further in code. */
7832 /* It is possible that the expansion created lots of new registers.
7833 Iterate over the sequence we just created and record them all. We
7834 must do this before inserting the sequence. */
7838 }
7841 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7842 initial value of the basic induction variable, M a multiplicative
7843 constant, A an additive constant and REG the destination
7844 register. */
7846 void
7848 {
7849 rtx seq;
7851 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7854 /* Increase the lifetime of any invariants moved further in code.
7855 ???? Is this really necessary? */
7860 /* It is possible that the expansion created lots of new registers.
7861 Iterate over the sequence we just created and record them all. We
7862 must do this before inserting the sequence. */
7866 }
7869 /* Emit insns after loop to set REG = B * M + A. B is the initial
7870 value of the basic induction variable, M a multiplicative constant,
7871 A an additive constant and REG the destination register. */
7873 void
7875 {
7876 rtx seq;
7878 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7881 /* It is possible that the expansion created lots of new registers.
7882 Iterate over the sequence we just created and record them all. We
7883 must do this before inserting the sequence. */
7887 }
7891 /* Similar to gen_add_mult, but compute cost rather than generating
7892 sequence. */
7894 static int
7896 {
7906 {
7911 }
7914 }
7915 \f
7916 /* Test whether A * B can be computed without
7917 an actual multiply insn. Value is 1 if so.
7919 ??? This function stinks because it generates a ton of wasted RTL
7920 ??? and as a result fragments GC memory to no end. There are other
7921 ??? places in the compiler which are invoked a lot and do the same
7922 ??? thing, generate wasted RTL just to see if something is possible. */
7924 static int
7926 {
7927 rtx tmp;
7930 /* If only one is constant, make it B. */
7934 /* If first constant, both constant, so don't need multiply. */
7938 /* If second not constant, neither is constant, so would need multiply. */
7942 /* One operand is constant, so might not need multiply insn. Generate the
7943 code for the multiply and see if a call or multiply, or long sequence
7944 of insns is generated. */
7953 {
7956 {
7966 {
7969 }
7972 }
7973 }
7983 }
7984 \f
7985 /* Check to see if loop can be terminated by a "decrement and branch until
7986 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7987 Also try reversing an increment loop to a decrement loop
7988 to see if the optimization can be performed.
7989 Value is nonzero if optimization was performed. */
7991 /* This is useful even if the architecture doesn't have such an insn,
7992 because it might change a loops which increments from 0 to n to a loop
7993 which decrements from n to 0. A loop that decrements to zero is usually
7994 faster than one that increments from zero. */
7996 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7997 such as approx_final_value, biv_total_increment, loop_iterations, and
7998 final_[bg]iv_value. */
8000 static int
8002 {
8007 rtx reg;
8008 rtx jump_label;
8009 rtx final_value;
8010 rtx start_value;
8011 rtx new_add_val;
8012 rtx comparison;
8013 rtx before_comparison;
8014 rtx p;
8015 rtx jump;
8016 rtx first_compare;
8021 /* If last insn is a conditional branch, and the insn before tests a
8022 register value, try to optimize it. Otherwise, we can't do anything. */
8031 /* Try to compute whether the compare/branch at the loop end is one or
8032 two instructions. */
8038 else
8041 {
8042 /* If more than one condition is present to control the loop, then
8043 do not proceed, as this function does not know how to rewrite
8044 loop tests with more than one condition.
8046 Look backwards from the first insn in the last comparison
8047 sequence and see if we've got another comparison sequence. */
8049 rtx jump1;
8053 }
8055 /* Check all of the bivs to see if the compare uses one of them.
8056 Skip biv's set more than once because we can't guarantee that
8057 it will be zero on the last iteration. Also skip if the biv is
8058 used between its update and the test insn. */
8061 {
8066 first_compare))
8068 }
8070 /* Try swapping the comparison to identify a suitable biv. */
8077 first_compare))
8078 {
8080 VOIDmode,
8084 }
8089 /* Look for the case where the basic induction variable is always
8090 nonnegative, and equals zero on the last iteration.
8091 In this case, add a reg_note REG_NONNEG, which allows the
8092 m68k DBRA instruction to be used. */
8098 {
8099 /* Initial value must be greater than 0,
8100 init_val % -dec_value == 0 to ensure that it equals zero on
8101 the last iteration */
8107 {
8108 /* register always nonnegative, add REG_NOTE to branch */
8116 }
8118 /* If the decrement is 1 and the value was tested as >= 0 before
8119 the loop, then we can safely optimize. */
8121 {
8135 {
8143 }
8144 }
8145 }
8148 {
8149 /* Try to change inc to dec, so can apply above optimization. */
8150 /* Can do this if:
8151 all registers modified are induction variables or invariant,
8152 all memory references have non-overlapping addresses
8153 (obviously true if only one write)
8154 allow 2 insns for the compare/jump at the end of the loop. */
8155 /* Also, we must avoid any instructions which use both the reversed
8156 biv and another biv. Such instructions will fail if the loop is
8157 reversed. We meet this condition by requiring that either
8158 no_use_except_counting is true, or else that there is only
8159 one biv. */
8161 /* 1 if the iteration var is used only to count iterations. */
8163 /* 1 if the loop has no memory store, or it has a single memory store
8164 which is reversible. */
8170 {
8174 /* If there are no givs for this biv, and the only exit is the
8175 fall through at the end of the loop, then
8176 see if perhaps there are no uses except to count. */
8180 {
8185 /* An insn that sets the biv is okay. */
8186 ;
8188 /* An insn that doesn't mention the biv is okay. */
8189 ;
8192 {
8193 /* If either of these insns uses the biv and sets a pseudo
8194 that has more than one usage, then the biv has uses
8195 other than counting since it's used to derive a value
8196 that is used more than one time. */
8198 regs);
8200 {
8203 }
8204 }
8205 else
8206 {
8209 }
8210 }
8212 /* A biv has uses besides counting if it is used to set
8213 another biv. */
8217 {
8220 }
8221 }
8224 /* No need to worry about MEMs. */
8225 ;
8227 {
8232 /* If the loop has a single store, and the destination address is
8233 invariant, then we can't reverse the loop, because this address
8234 might then have the wrong value at loop exit.
8235 This would work if the source was invariant also, however, in that
8236 case, the insn should have been moved out of the loop. */
8239 {
8242 /* If we could prove that each of the memory locations
8243 written to was different, then we could reverse the
8244 store -- but we don't presently have any way of
8245 knowing that. */
8248 /* If the store depends on a register that is set after the
8249 store, it depends on the initial value, and is thus not
8250 reversible. */
8252 {
8259 }
8260 }
8261 }
8262 else
8265 /* This code only acts for innermost loops. Also it simplifies
8266 the memory address check by only reversing loops with
8267 zero or one memory access.
8268 Two memory accesses could involve parts of the same array,
8269 and that can't be reversed.
8270 If the biv is used only for counting, than we don't need to worry
8271 about all these things. */
8277 && reversible_mem_store
8282 {
8283 rtx tem;
8285 /* Loop can be reversed. */
8289 /* Now check other conditions:
8291 The increment must be a constant, as must the initial value,
8292 and the comparison code must be LT.
8294 This test can probably be improved since +/- 1 in the constant
8295 can be obtained by changing LT to LE and vice versa; this is
8296 confusing. */
8299 /* for constants, LE gets turned into LT */
8304 {
8315 comparison_const_width
8317 else
8318 comparison_const_width
8322 comparison_sign_mask
8325 /* If the comparison value is not a loop invariant, then we
8326 can not reverse this loop.
8328 ??? If the insns which initialize the comparison value as
8329 a whole compute an invariant result, then we could move
8330 them out of the loop and proceed with loop reversal. */
8338 /* Normalize the initial value if it is an integer and
8339 has no other use except as a counter. This will allow
8340 a few more loops to be reversed. */
8344 {
8346 /* The code below requires comparison_val to be a multiple
8347 of add_val in order to do the loop reversal, so
8348 round up comparison_val to a multiple of add_val.
8349 Since comparison_value is constant, we know that the
8350 current comparison code is LT. */
8352 comparison_val
8354 /* We postpone overflow checks for COMPARISON_VAL here;
8355 even if there is an overflow, we might still be able to
8356 reverse the loop, if converting the loop exit test to
8357 NE is possible. */
8359 }
8361 /* First check if we can do a vanilla loop reversal. */
8363 /* If we have a decrement_and_branch_on_count,
8364 prefer the NE test, since this will allow that
8365 instruction to be generated. Note that we must
8366 use a vanilla loop reversal if the biv is used to
8367 calculate a giv or has a non-counting use. */
8368 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8369 && defined (HAVE_decrement_and_branch_on_count)
8373 #endif
8375 /* Now do postponed overflow checks on COMPARISON_VAL. */
8378 {
8379 /* Register will always be nonnegative, with value
8380 0 on last iteration */
8384 }
8388 {
8391 }
8392 else
8398 /* If the initial value is not zero, or if the comparison
8399 value is not an exact multiple of the increment, then we
8400 can not reverse this loop. */
8403 {
8406 }
8407 else
8408 {
8411 }
8415 /* Reset these in case we normalized the initial value
8416 and comparison value above. */
8419 {
8421 final_value
8423 }
8426 /* Save some info needed to produce the new insns. */
8431 /* Set start_value; if this is not a CONST_INT, we need
8432 to generate a SUB.
8433 Initialize biv to start_value before loop start.
8434 The old initializing insn will be deleted as a
8435 dead store by flow.c. */
8438 {
8441 }
8443 {
8451 start_value
8457 }
8459 {
8462 initial_value);
8466 start_value
8469 }
8470 else
8471 /* We could handle the other cases too, but it'll be
8472 better to have a testcase first. */
8475 /* We may not have a single insn which can increment a reg, so
8476 create a sequence to hold all the insns from expand_inc. */
8485 /* Update biv info to reflect its new status. */
8490 /* Update loop info. */
8499 /* Inc LABEL_NUSES so that delete_insn will
8500 not delete the label. */
8503 /* Emit an insn after the end of the loop to set the biv's
8504 proper exit value if it is used anywhere outside the loop. */
8510 /* Delete compare/branch at end of loop. */
8515 /* Add new compare/branch insn at end of loop. */
8527 ;
8533 {
8535 {
8536 /* Increment of LABEL_NUSES done above. */
8537 /* Register is now always nonnegative,
8538 so add REG_NONNEG note to the branch. */
8541 }
8543 }
8545 /* No insn may reference both the reversed and another biv or it
8546 will fail (see comment near the top of the loop reversal
8547 code).
8548 Earlier on, we have verified that the biv has no use except
8549 counting, or it is the only biv in this function.
8550 However, the code that computes no_use_except_counting does
8551 not verify reg notes. It's possible to have an insn that
8552 references another biv, and has a REG_EQUAL note with an
8553 expression based on the reversed biv. To avoid this case,
8554 remove all REG_EQUAL notes based on the reversed biv
8555 here. */
8558 {
8561 /* If this is a set of a GIV based on the reversed biv, any
8562 REG_EQUAL notes should still be correct. */
8569 {
8574 else
8576 }
8577 }
8579 /* Mark that this biv has been reversed. Each giv which depends
8580 on this biv, and which is also live past the end of the loop
8581 will have to be fixed up. */
8586 {
8590 else
8592 }
8595 }
8596 }
8597 }
8600 }
8601 \f
8602 /* Verify whether the biv BL appears to be eliminable,
8603 based on the insns in the loop that refer to it.
8605 If ELIMINATE_P is nonzero, actually do the elimination.
8607 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8608 determine whether invariant insns should be placed inside or at the
8609 start of the loop. */
8611 static int
8614 {
8617 rtx p;
8619 /* Scan all insns in the loop, stopping if we find one that uses the
8620 biv in a way that we cannot eliminate. */
8623 {
8627 rtx note;
8629 /* If this is a libcall that sets a giv, skip ahead to its end. */
8631 {
8635 {
8640 {
8647 }
8648 }
8649 }
8651 /* Closely examine the insn if the biv is mentioned. */
8656 {
8662 }
8664 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8669 }
8672 {
8677 }
8680 }
8681 \f
8682 /* INSN and REFERENCE are instructions in the same insn chain.
8683 Return nonzero if INSN is first. */
8685 int
8687 {
8691 {
8692 /* Start with test for not first so that INSN == REFERENCE yields not
8693 first. */
8699 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8700 previous insn, hence the <= comparison below does not work if
8701 P is a note. */
8712 }
8713 }
8715 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8716 the offset that we have to take into account due to auto-increment /
8717 div derivation is zero. */
8718 static int
8721 {
8722 /* If the giv V had the auto-inc address optimization applied
8723 to it, and INSN occurs between the giv insn and the biv
8724 insn, then we'd have to adjust the value used here.
8725 This is rare, so we don't bother to make this possible. */
8734 }
8736 /* If BL appears in X (part of the pattern of INSN), see if we can
8737 eliminate its use. If so, return 1. If not, return 0.
8739 If BIV does not appear in X, return 1.
8741 If ELIMINATE_P is nonzero, actually do the elimination.
8742 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8743 Depending on how many items have been moved out of the loop, it
8744 will either be before INSN (when WHERE_INSN is nonzero) or at the
8745 start of the loop (when WHERE_INSN is zero). */
8747 static int
8751 {
8757 #ifdef HAVE_cc0
8759 #endif
8765 {
8767 /* If we haven't already been able to do something with this BIV,
8768 we can't eliminate it. */
8774 /* If this sets the BIV, it is not a problem. */
8778 /* If this is an insn that defines a giv, it is also ok because
8779 it will go away when the giv is reduced. */
8784 #ifdef HAVE_cc0
8786 {
8787 /* Can replace with any giv that was reduced and
8788 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8789 Require a constant for MULT_VAL, so we know it's nonzero.
8790 ??? We disable this optimization to avoid potential
8791 overflows. */
8799 {
8806 /* If the giv has the opposite direction of change,
8807 then reverse the comparison. */
8811 else
8814 /* We can probably test that giv's reduced reg. */
8817 }
8819 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8820 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8821 Require a constant for MULT_VAL, so we know it's nonzero.
8822 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8823 overflow problem. */
8835 {
8842 /* If the giv has the opposite direction of change,
8843 then reverse the comparison. */
8847 else
8851 /* Replace biv with the giv's reduced register. */
8856 /* Insn doesn't support that constant or invariant. Copy it
8857 into a register (it will be a loop invariant.) */
8864 /* Substitute the new register for its invariant value in
8865 the compare expression. */
8869 }
8870 }
8871 #endif
8878 /* See if either argument is the biv. */
8883 else
8887 {
8888 /* First try to replace with any giv that has constant positive
8889 mult_val and constant add_val. We might be able to support
8890 negative mult_val, but it seems complex to do it in general. */
8902 {
8906 /* Don't eliminate if the linear combination that makes up
8907 the giv overflows when it is applied to ARG. */
8909 {
8910 rtx add_val;
8914 else
8920 }
8925 /* Replace biv with the giv's reduced reg. */
8928 /* If all constants are actually constant integers and
8929 the derived constant can be directly placed in the COMPARE,
8930 do so. */
8933 {
8936 }
8937 else
8938 {
8939 /* Otherwise, load it into a register. */
8944 }
8950 }
8952 /* Look for giv with positive constant mult_val and nonconst add_val.
8953 Insert insns to calculate new compare value.
8954 ??? Turn this off due to possible overflow. */
8962 {
8963 rtx tem;
8973 /* Replace biv with giv's reduced register. */
8977 /* Compute value to compare against. */
8981 /* Use it in this insn. */
8985 }
8986 }
8988 {
8990 {
8991 /* Look for giv with constant positive mult_val and nonconst
8992 add_val. Insert insns to compute new compare value.
8993 ??? Turn this off due to possible overflow. */
9000 {
9001 rtx tem;
9011 /* Replace biv with giv's reduced register. */
9015 /* Compute value to compare against. */
9022 }
9023 }
9025 /* This code has problems. Basically, you can't know when
9026 seeing if we will eliminate BL, whether a particular giv
9027 of ARG will be reduced. If it isn't going to be reduced,
9028 we can't eliminate BL. We can try forcing it to be reduced,
9029 but that can generate poor code.
9031 The problem is that the benefit of reducing TV, below should
9032 be increased if BL can actually be eliminated, but this means
9033 we might have to do a topological sort of the order in which
9034 we try to process biv. It doesn't seem worthwhile to do
9035 this sort of thing now. */
9037 #if 0
9038 /* Otherwise the reg compared with had better be a biv. */
9043 /* Look for a pair of givs, one for each biv,
9044 with identical coefficients. */
9046 {
9058 {
9065 /* Replace biv with its giv's reduced reg. */
9067 /* Replace other operand with the other giv's
9068 reduced reg. */
9071 }
9072 }
9073 #endif
9074 }
9076 /* If we get here, the biv can't be eliminated. */
9080 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9081 biv is used in it, since it will be replaced. */
9089 }
9091 /* See if any subexpression fails elimination. */
9094 {
9096 {
9109 }
9110 }
9113 }
9114 \f
9115 /* Return nonzero if the last use of REG
9116 is in an insn following INSN in the same basic block. */
9118 static int
9120 {
9121 rtx n;
9125 {
9128 }
9130 }
9131 \f
9132 /* Called via `note_stores' to record the initial value of a biv. Here we
9133 just record the location of the set and process it later. */
9135 static void
9137 {
9148 /* If this is the first set found, record it. */
9150 {
9153 }
9154 }
9155 \f
9156 /* If any of the registers in X are "old" and currently have a last use earlier
9157 than INSN, update them to have a last use of INSN. Their actual last use
9158 will be the previous insn but it will not have a valid uid_luid so we can't
9159 use it. X must be a source expression only. */
9161 static void
9163 {
9164 /* Check for the case where INSN does not have a valid luid. In this case,
9165 there is no need to modify the regno_last_uid, as this can only happen
9166 when code is inserted after the loop_end to set a pseudo's final value,
9167 and hence this insn will never be the last use of x.
9168 ???? This comment is not correct. See for example loop_givs_reduce.
9169 This may insert an insn before another new insn. */
9173 {
9175 }
9176 else
9177 {
9181 {
9187 }
9188 }
9189 }
9190 \f
9191 /* Given an insn INSN and condition COND, return the condition in a
9192 canonical form to simplify testing by callers. Specifically:
9194 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9195 (2) Both operands will be machine operands; (cc0) will have been replaced.
9196 (3) If an operand is a constant, it will be the second operand.
9197 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9198 for GE, GEU, and LEU.
9200 If the condition cannot be understood, or is an inequality floating-point
9201 comparison which needs to be reversed, 0 will be returned.
9203 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9205 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9206 insn used in locating the condition was found. If a replacement test
9207 of the condition is desired, it should be placed in front of that
9208 insn and we will be sure that the inputs are still valid.
9210 If WANT_REG is nonzero, we wish the condition to be relative to that
9211 register, if possible. Therefore, do not canonicalize the condition
9212 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9213 to be a compare to a CC mode register. */
9215 rtx
9218 {
9221 rtx set;
9222 rtx tem;
9240 /* If we are comparing a register with zero, see if the register is set
9241 in the previous insn to a COMPARE or a comparison operation. Perform
9242 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9243 in cse.c */
9248 {
9249 /* Set nonzero when we find something of interest. */
9252 #ifdef HAVE_cc0
9253 /* If comparison with cc0, import actual comparison from compare
9254 insn. */
9256 {
9267 }
9268 #endif
9270 /* If this is a COMPARE, pick up the two things being compared. */
9272 {
9276 }
9280 /* Go back to the previous insn. Stop if it is not an INSN. We also
9281 stop if it isn't a single set or if it has a REG_INC note because
9282 we don't want to bother dealing with it. */
9296 /* If this is setting OP0, get what it sets it to if it looks
9297 relevant. */
9299 {
9301 #ifdef FLOAT_STORE_FLAG_VALUE
9302 REAL_VALUE_TYPE fsfv;
9303 #endif
9305 /* ??? We may not combine comparisons done in a CCmode with
9306 comparisons not done in a CCmode. This is to aid targets
9307 like Alpha that have an IEEE compliant EQ instruction, and
9308 a non-IEEE compliant BEQ instruction. The use of CCmode is
9309 actually artificial, simply to prevent the combination, but
9310 should not affect other platforms.
9312 However, we must allow VOIDmode comparisons to match either
9313 CCmode or non-CCmode comparison, because some ports have
9314 modeless comparisons inside branch patterns.
9316 ??? This mode check should perhaps look more like the mode check
9317 in simplify_comparison in combine. */
9325 && (STORE_FLAG_VALUE
9328 #ifdef FLOAT_STORE_FLAG_VALUE
9333 #endif
9334 ))
9345 && (STORE_FLAG_VALUE
9348 #ifdef FLOAT_STORE_FLAG_VALUE
9353 #endif
9354 ))
9360 {
9363 }
9364 else
9366 }
9369 /* If this sets OP0, but not directly, we have to give up. */
9373 {
9377 {
9382 }
9387 }
9388 }
9390 /* If constant is first, put it last. */
9394 /* If OP0 is the result of a comparison, we weren't able to find what
9395 was really being compared, so fail. */
9400 /* Canonicalize any ordered comparison with integers involving equality
9401 if we can do computations in the relevant mode and we do not
9402 overflow. */
9408 {
9411 unsigned HOST_WIDE_INT max_val
9415 {
9421 /* When cross-compiling, const_val might be sign-extended from
9422 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9442 }
9443 }
9445 /* Never return CC0; return zero instead. */
9450 }
9452 /* Given a jump insn JUMP, return the condition that will cause it to branch
9453 to its JUMP_LABEL. If the condition cannot be understood, or is an
9454 inequality floating-point comparison which needs to be reversed, 0 will
9455 be returned.
9457 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9458 insn used in locating the condition was found. If a replacement test
9459 of the condition is desired, it should be placed in front of that
9460 insn and we will be sure that the inputs are still valid.
9462 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9463 compare CC mode register. */
9465 rtx
9467 {
9468 rtx cond;
9470 rtx set;
9472 /* If this is not a standard conditional jump, we can't parse it. */
9480 /* If this branches to JUMP_LABEL when the condition is false, reverse
9481 the condition. */
9482 reverse
9487 allow_cc_mode);
9488 }
9490 /* Similar to above routine, except that we also put an invariant last
9491 unless both operands are invariants. */
9493 rtx
9495 {
9505 }
9507 /* Scan the function and determine whether it has indirect (computed) jumps.
9509 This is taken mostly from flow.c; similar code exists elsewhere
9510 in the compiler. It may be useful to put this into rtlanal.c. */
9511 static int
9513 {
9514 rtx insn;
9521 }
9523 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9524 documentation for LOOP_MEMS for the definition of `appropriate'.
9525 This function is called from prescan_loop via for_each_rtx. */
9527 static int
9529 {
9538 {
9543 /* We're not interested in MEMs that are only clobbered. */
9547 /* We're not interested in the MEM associated with a
9548 CONST_DOUBLE, so there's no need to traverse into this. */
9552 /* We're not interested in any MEMs that only appear in notes. */
9556 /* This is not a MEM. */
9558 }
9560 /* See if we've already seen this MEM. */
9563 {
9565 /* The modes of the two memory accesses are different. If
9566 this happens, something tricky is going on, and we just
9567 don't optimize accesses to this MEM. */
9571 }
9573 /* Resize the array, if necessary. */
9575 {
9578 else
9583 }
9585 /* Actually insert the MEM. */
9587 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9588 because we can't put it in a register. We still store it in the
9589 table, though, so that if we see the same address later, but in a
9590 non-BLK mode, we'll not think we can optimize it at that point. */
9596 }
9599 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9601 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9602 register that is modified by an insn between FROM and TO. If the
9603 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9604 more, stop incrementing it, to avoid overflow.
9606 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9607 register I is used, if it is only used once. Otherwise, it is set
9608 to 0 (for no uses) or const0_rtx for more than one use. This
9609 parameter may be zero, in which case this processing is not done.
9611 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9612 optimize register I. */
9614 static void
9616 {
9619 /* last_set[n] is nonzero iff reg n has been set in the current
9620 basic block. In that case, it is the insn that last set reg n. */
9622 rtx insn;
9628 /* Grow the regs array if not allocated or too small. */
9630 {
9635 /* Zero the new elements. */
9638 }
9640 /* Clear previously scanned fields but do not clear n_times_set. */
9642 {
9646 }
9650 /* Scan the loop, recording register usage. */
9653 {
9655 {
9656 /* Record registers that have exactly one use. */
9659 /* Include uses in REG_EQUAL notes. */
9667 {
9671 last_set);
9672 }
9673 }
9678 /* Invalidate all registers used for function argument passing.
9679 We check rtx_varies_p for the same reason as below, to allow
9680 optimizing PIC calculations. */
9682 {
9683 rtx link;
9685 link;
9687 {
9694 }
9695 }
9696 }
9698 /* Invalidate all hard registers clobbered by calls. With one exception:
9699 a call-clobbered PIC register is still function-invariant for our
9700 purposes, since we can hoist any PIC calculations out of the loop.
9701 Thus the call to rtx_varies_p. */
9706 {
9709 }
9711 #ifdef AVOID_CCMODE_COPIES
9712 /* Don't try to move insns which set CC registers if we should not
9713 create CCmode register copies. */
9717 #endif
9719 /* Set regs->array[I].n_times_set for the new registers. */
9724 }
9726 /* Returns the number of real INSNs in the LOOP. */
9728 static int
9730 {
9732 rtx insn;
9740 }
9742 /* Move MEMs into registers for the duration of the loop. */
9744 static void
9746 {
9753 rtx end_label;
9754 /* Nonzero if the next instruction may never be executed. */
9761 /* We cannot use next_label here because it skips over normal insns. */
9766 /* Check to see if it's possible that some instructions in the loop are
9767 never executed. Also check if there is a goto out of the loop other
9768 than right after the end of the loop. */
9772 {
9776 /* If we enter the loop in the middle, and scan
9777 around to the beginning, don't set maybe_never
9778 for that. This must be an unconditional jump,
9779 otherwise the code at the top of the loop might
9780 never be executed. Unconditional jumps are
9781 followed a by barrier then loop end. */
9786 {
9787 /* If this is a jump outside of the loop but not right
9788 after the end of the loop, we would have to emit new fixup
9789 sequences for each such label. */
9791 JUMP_INSN is executed, we must be conservative. */
9800 /* Something complicated. */
9802 else
9803 /* If there are any more instructions in the loop, they
9804 might not be reached. */
9806 }
9809 }
9811 /* Find start of the extended basic block that enters the loop. */
9815 ;
9820 /* Build table of mems that get set to constant values before the
9821 loop. */
9825 /* Actually move the MEMs. */
9827 {
9828 regset_head load_copies;
9829 regset_head store_copies;
9831 rtx reg;
9833 rtx mem_list_entry;
9837 /* There's no telling whether or not MEM is modified. */
9840 /* Go through the MEMs written to in the loop to see if this
9841 one is aliased by one of them. */
9844 {
9849 {
9850 /* MEM is indeed aliased by this store. */
9853 }
9855 }
9861 /* If this MEM is written to, we must be sure that there
9862 are no reads from another MEM that aliases this one. */
9864 {
9868 {
9872 VOIDmode,
9874 rtx_varies_p))
9875 {
9876 /* It's not safe to hoist loop_info->mems[i] out of
9877 the loop because writes to it might not be
9878 seen by reads from loop_info->mems[j]. */
9881 }
9882 }
9883 }
9886 /* We can't access the MEM outside the loop; it might
9887 cause a trap that wouldn't have happened otherwise. */
9891 /* We thought we were going to lift this MEM out of the
9892 loop, but later discovered that we could not. */
9898 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9899 order to keep scan_loop from moving stores to this MEM
9900 out of the loop just because this REG is neither a
9901 user-variable nor used in the loop test. */
9906 /* Now, replace all references to the MEM with the
9907 corresponding pseudos. */
9912 {
9914 {
9915 rtx set;
9919 /* See if this copies the mem into a register that isn't
9920 modified afterwards. We'll try to do copy propagation
9921 a little further on. */
9923 /* @@@ This test is _way_ too conservative. */
9924 && ! maybe_never
9932 /* See if this copies the mem from a register that isn't
9933 modified afterwards. We'll try to remove the
9934 redundant copy later on by doing a little register
9935 renaming and copy propagation. This will help
9936 to untangle things for the BIV detection code. */
9938 && ! maybe_never
9946 /* If this is a call which uses / clobbers this memory
9947 location, we must not change the interface here. */
9951 {
9955 }
9956 else
9957 /* Replace the memory reference with the shadow register. */
9960 }
9965 }
9970 /* We couldn't replace all occurrences of the MEM. */
9972 else
9973 {
9974 /* Load the memory immediately before LOOP->START, which is
9975 the NOTE_LOOP_BEG. */
9977 rtx set;
9983 {
9987 {
9991 /* Extending hard register lifetimes causes crash
9992 on SRC targets. Doing so on non-SRC is
9993 probably also not good idea, since we most
9994 probably have pseudoregister equivalence as
9995 well. */
9998 }
9999 /* Use the constant equivalence if that is cheap enough. */
10005 {
10008 }
10010 /* If best_equiv is nonzero, we know that MEM is set to a
10011 constant or register before the loop. We will use this
10012 knowledge to initialize the shadow register with that
10013 constant or reg rather than by loading from MEM. */
10016 }
10021 {
10024 {
10027 }
10028 }
10034 {
10036 {
10039 }
10041 /* Store the memory immediately after END, which is
10042 the NOTE_LOOP_END. */
10045 }
10048 {
10053 }
10055 /* Attempt a bit of copy propagation. This helps untangle the
10056 data flow, and enables {basic,general}_induction_var to find
10057 more bivs/givs. */
10058 EXECUTE_IF_SET_IN_REG_SET
10060 {
10062 });
10065 EXECUTE_IF_SET_IN_REG_SET
10067 {
10069 });
10071 }
10072 }
10074 /* Now, we need to replace all references to the previous exit
10075 label with the new one. */
10082 }
10084 /* For communication between note_reg_stored and its caller. */
10085 struct note_reg_stored_arg
10086 {
10088 rtx reg;
10089 };
10091 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10092 is equal to ARG. */
10093 static void
10095 {
10099 }
10101 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10102 There must be exactly one insn that sets this pseudo; it will be
10103 deleted if all replacements succeed and we can prove that the register
10104 is not used after the loop. */
10106 static void
10108 {
10109 /* This is the reg that we are copying from. */
10112 rtx insn;
10113 /* These help keep track of whether we replaced all uses of the reg. */
10120 {
10121 rtx set;
10123 /* Only substitute within one extended basic block from the initializing
10124 insn. */
10131 /* Is this the initializing insn? */
10136 {
10143 }
10145 /* Only substitute after seeing the initializing insn. */
10147 {
10154 /* Stop replacing when REPLACEMENT is modified. */
10159 {
10162 /* It is possible that we've turned previously valid REG_EQUAL to
10163 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10164 REPLACEMENT is modified, we get different meaning. */
10168 }
10169 }
10170 }
10174 {
10178 {
10179 rtx first;
10180 rtx retval_note;
10182 /* Assume we're just deleting INIT_INSN. */
10184 /* Look for REG_RETVAL note. If we're deleting the end of
10185 the libcall sequence, the whole sequence can go. */
10187 /* If we found a REG_RETVAL note, find the first instruction
10188 in the sequence. */
10192 /* Delete the instructions. */
10194 }
10197 }
10198 }
10200 /* Replace all the instructions from FIRST up to and including LAST
10201 with NOTE_INSN_DELETED notes. */
10203 static void
10205 {
10207 {
10213 /* If this was the LAST instructions we're supposed to delete,
10214 we're done. */
10219 }
10220 }
10222 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10223 loop LOOP if the order of the sets of these registers can be
10224 swapped. There must be exactly one insn within the loop that sets
10225 this pseudo followed immediately by a move insn that sets
10226 REPLACEMENT with REGNO. */
10227 static void
10230 {
10231 rtx insn;
10240 {
10241 /* Search for the insn that copies REGNO to NEW_REGNO? */
10249 }
10252 {
10253 rtx prev_insn;
10254 rtx prev_set;
10256 /* Some DEF-USE info would come in handy here to make this
10257 function more general. For now, just check the previous insn
10258 which is the most likely candidate for setting REGNO. */
10266 {
10267 /* We have:
10268 (set (reg regno) (expr))
10269 (set (reg new_regno) (reg regno))
10271 so try converting this to:
10272 (set (reg new_regno) (expr))
10273 (set (reg regno) (reg new_regno))
10275 The former construct is often generated when a global
10276 variable used for an induction variable is shadowed by a
10277 register (NEW_REGNO). The latter construct improves the
10278 chances of GIV replacement and BIV elimination. */
10288 {
10295 /* Update first use of REGNO. */
10299 /* Now perform copy propagation to hopefully
10300 remove all uses of REGNO within the loop. */
10302 }
10303 }
10304 }
10305 }
10307 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10309 static int
10311 {
10313 {
10317 }
10319 }
10321 /* Returns the first MEM found in NOTE by depth-first search. */
10323 static rtx
10325 {
10329 }
10331 /* Replace MEM with its associated pseudo register. This function is
10332 called from load_mems via for_each_rtx. DATA is actually a pointer
10333 to a structure describing the instruction currently being scanned
10334 and the MEM we are currently replacing. */
10336 static int
10338 {
10346 {
10351 /* We're not interested in the MEM associated with a
10352 CONST_DOUBLE, so there's no need to traverse into one. */
10356 /* This is not a MEM. */
10358 }
10361 /* This is not the MEM we are currently replacing. */
10364 /* Actually replace the MEM. */
10368 }
10370 static void
10372 {
10373 loop_replace_args args;
10381 /* If we hoist a mem write out of the loop, then REG_EQUAL
10382 notes referring to the mem are no longer valid. */
10384 {
10389 {
10393 {
10394 /* Remove the note. */
10397 }
10398 }
10399 }
10400 }
10402 /* Replace one register with another. Called through for_each_rtx; PX points
10403 to the rtx being scanned. DATA is actually a pointer to
10404 a structure of arguments. */
10406 static int
10408 {
10419 }
10421 static void
10423 {
10424 loop_replace_args args;
10431 }
10432 \f
10433 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10434 (ignored in the interim). */
10436 static rtx
10439 rtx pattern)
10440 {
10442 }
10445 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10446 in basic block WHERE_BB (ignored in the interim) within the loop
10447 otherwise hoist PATTERN into the loop pre-header. */
10449 rtx
10451 basic_block where_bb ATTRIBUTE_UNUSED,
10453 {
10457 }
10460 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10461 WHERE_BB (ignored in the interim) within the loop. */
10463 static rtx
10465 basic_block where_bb ATTRIBUTE_UNUSED,
10467 {
10469 }
10472 /* Hoist insn for PATTERN into the loop pre-header. */
10474 rtx
10476 {
10478 }
10481 /* Hoist call insn for PATTERN into the loop pre-header. */
10483 static rtx
10485 {
10487 }
10490 /* Sink insn for PATTERN after the loop end. */
10492 rtx
10494 {
10496 }
10498 /* bl->final_value can be either general_operand or PLUS of general_operand
10499 and constant. Emit sequence of instructions to load it into REG. */
10500 static rtx
10502 {
10503 rtx seq;
10511 }
10513 /* If the loop has multiple exits, emit insn for PATTERN before the
10514 loop to ensure that it will always be executed no matter how the
10515 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10516 since this is slightly more efficient. */
10518 static rtx
10520 {
10523 else
10525 }
10526 \f
10527 static void
10529 {
10537 iv_num++;
10542 {
10545 }
10546 }
10549 static void
10552 {
10554 rtx incr;
10565 {
10568 }
10570 {
10573 }
10577 {
10581 }
10584 {
10588 }
10590 /* List the increments. */
10592 {
10596 }
10598 /* List the givs. */
10600 {
10605 else
10608 }
10609 }
10612 static void
10614 {
10625 {
10629 }
10632 }
10635 static void
10637 {
10644 else
10660 {
10662 {
10674 }
10675 }
10686 {
10690 }
10693 }
10696 void
10698 {
10700 }
10703 void
10705 {
10707 }
10710 void
10712 {
10714 }
10717 void
10719 {
10721 }
10724 #define LOOP_BLOCK_NUM_1(INSN) \
10725 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10727 /* The notes do not have an assigned block, so look at the next insn. */
10728 #define LOOP_BLOCK_NUM(INSN) \
10729 ((INSN) ? (GET_CODE (INSN) == NOTE \
10730 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10731 : LOOP_BLOCK_NUM_1 (INSN)) \
10732 : -1)
10734 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10736 static void
10739 {
10740 rtx label;
10745 /* Print diagnostics to compare our concept of a loop with
10746 what the loop notes say. */
10761 {
10781 {
10784 {
10787 }
10788 }
10791 /* This can happen when a marked loop appears as two nested loops,
10792 say from while (a || b) {}. The inner loop won't match
10793 the loop markers but the outer one will. */
10796 }
10797 }
10799 /* Call this function from the debugger to dump LOOP. */
10801 void
10803 {
10805 }
10807 /* Call this function from the debugger to dump LOOPS. */
10809 void
10811 {
10813 }