1 /* Machine description for AArch64 architecture.
2 Copyright (C
) 2009-2014 Free Software Foundation
, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software
; you can redistribute it and
/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation
; either version
3, or (at your option
)
12 GCC is distributed in the hope that it will be useful
, but
13 WITHOUT ANY WARRANTY
; without even the implied warranty of
14 MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC
; see the file COPYING3. If not see
19 <http
://www.gnu.org
/licenses
/>.
*/
24 CC_MODE (CC_ZESWP
); /* zero
-extend
LHS (but swap to make it RHS
).
*/
25 CC_MODE (CC_SESWP
); /* sign
-extend
LHS (but swap to make it RHS
).
*/
26 CC_MODE (CC_NZ
); /* Only N and Z bits of condition flags are valid.
*/
27 CC_MODE (CC_Z
); /* Only Z bit of condition flags is valid.
*/
30 VECTOR_MODES (INT
, 8); /* V8QI V4HI V2SI.
*/
31 VECTOR_MODES (INT
, 16); /* V16QI V8HI V4SI V2DI.
*/
32 VECTOR_MODES (FLOAT, 8); /* V2SF.
*/
33 VECTOR_MODES (FLOAT, 16); /* V4SF V2DF.
*/
35 /* Oct Int
: 256-bit integer mode needed for
32-byte vector arguments.
*/
38 /* Opaque integer modes for
3, 6 or
8 Neon double
registers (2 is
44 /* Vector modes for register lists.
*/
45 VECTOR_MODES (INT
, 32); /* V32QI V16HI V8SI V4DI.
*/
46 VECTOR_MODES (FLOAT, 32); /* V8SF V4DF.
*/
48 VECTOR_MODES (INT
, 48); /* V32QI V16HI V8SI V4DI.
*/
49 VECTOR_MODES (FLOAT, 48); /* V8SF V4DF.
*/
51 VECTOR_MODES (INT
, 64); /* V32QI V16HI V8SI V4DI.
*/
52 VECTOR_MODES (FLOAT, 64); /* V8SF V4DF.
*/
54 /* Quad float
: 128-bit floating mode for long doubles.
*/
55 FLOAT_MODE (TF
, 16, ieee_quad_format
);