1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2016 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
596 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
597 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
601 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
604 dump_value_slim (lra_dump_file
, original
, 1);
606 if (new_class
!= lra_get_allocno_class (regno
))
607 lra_change_class (regno
, new_class
, ", change to", false);
608 if (lra_dump_file
!= NULL
)
609 fprintf (lra_dump_file
, "\n");
612 /* If we have an input reload with a different mode, make sure it
613 will get a different hard reg. */
614 else if (REG_P (original
)
615 && REG_P (curr_insn_input_reloads
[i
].input
)
616 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
617 && (GET_MODE (original
)
618 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
621 *result_reg
= (unique_p
622 ? lra_create_new_reg_with_unique_value
623 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
624 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
625 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
633 /* The page contains code to extract memory address parts. */
635 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 ok_for_index_p_nonstrict (rtx reg
)
639 unsigned regno
= REGNO (reg
);
641 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
644 /* A version of regno_ok_for_base_p for use here, when all pseudos
645 should count as OK. Arguments as for regno_ok_for_base_p. */
647 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
648 enum rtx_code outer_code
, enum rtx_code index_code
)
650 unsigned regno
= REGNO (reg
);
652 if (regno
>= FIRST_PSEUDO_REGISTER
)
654 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
659 /* The page contains major code to choose the current insn alternative
660 and generate reloads for it. */
662 /* Return the offset from REGNO of the least significant register
665 This function is used to tell whether two registers satisfy
666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
671 lra_constraint_offset (int regno
, machine_mode mode
)
673 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
674 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
675 && SCALAR_INT_MODE_P (mode
))
676 return hard_regno_nregs
[regno
][mode
] - 1;
680 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
681 if they are the same hard reg, and has special hacks for
682 auto-increment and auto-decrement. This is specifically intended for
683 process_alt_operands to use in determining whether two operands
684 match. X is the operand whose number is the lower of the two.
686 It is supposed that X is the output operand and Y is the input
687 operand. Y_HARD_REGNO is the final hard regno of register Y or
688 register in subreg Y as we know it now. Otherwise, it is a
691 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
694 RTX_CODE code
= GET_CODE (x
);
699 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
700 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
704 i
= get_hard_regno (x
, false);
708 if ((j
= y_hard_regno
) < 0)
711 i
+= lra_constraint_offset (i
, GET_MODE (x
));
712 j
+= lra_constraint_offset (j
, GET_MODE (y
));
717 /* If two operands must match, because they are really a single
718 operand of an assembler insn, then two post-increments are invalid
719 because the assembler insn would increment only once. On the
720 other hand, a post-increment matches ordinary indexing if the
721 post-increment is the output operand. */
722 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
723 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
725 /* Two pre-increments are invalid because the assembler insn would
726 increment only once. On the other hand, a pre-increment matches
727 ordinary indexing if the pre-increment is the input operand. */
728 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
729 || GET_CODE (y
) == PRE_MODIFY
)
730 return operands_match_p (x
, XEXP (y
, 0), -1);
734 if (code
== REG
&& REG_P (y
))
735 return REGNO (x
) == REGNO (y
);
737 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
738 && x
== SUBREG_REG (y
))
740 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
741 && SUBREG_REG (x
) == y
)
744 /* Now we have disposed of all the cases in which different rtx
746 if (code
!= GET_CODE (y
))
749 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
750 if (GET_MODE (x
) != GET_MODE (y
))
759 return label_ref_label (x
) == label_ref_label (y
);
761 return XSTR (x
, 0) == XSTR (y
, 0);
767 /* Compare the elements. If any pair of corresponding elements fail
768 to match, return false for the whole things. */
770 fmt
= GET_RTX_FORMAT (code
);
771 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
777 if (XWINT (x
, i
) != XWINT (y
, i
))
782 if (XINT (x
, i
) != XINT (y
, i
))
787 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
796 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
798 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
800 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
806 /* It is believed that rtx's at this level will never
807 contain anything but integers and other rtx's, except for
808 within LABEL_REFs and SYMBOL_REFs. */
816 /* True if X is a constant that can be forced into the constant pool.
817 MODE is the mode of the operand, or VOIDmode if not known. */
818 #define CONST_POOL_OK_P(MODE, X) \
819 ((MODE) != VOIDmode \
821 && GET_CODE (X) != HIGH \
822 && !targetm.cannot_force_const_mem (MODE, X))
824 /* True if C is a non-empty register class that has too few registers
825 to be safely used as a reload target class. */
826 #define SMALL_REGISTER_CLASS_P(C) \
827 (ira_class_hard_regs_num [(C)] == 1 \
828 || (ira_class_hard_regs_num [(C)] >= 1 \
829 && targetm.class_likely_spilled_p (C)))
831 /* If REG is a reload pseudo, try to make its class satisfying CL. */
833 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
835 enum reg_class rclass
;
837 /* Do not make more accurate class from reloads generated. They are
838 mostly moves with a lot of constraints. Making more accurate
839 class may results in very narrow class and impossibility of find
840 registers for several reloads of one insn. */
841 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
843 if (GET_CODE (reg
) == SUBREG
)
844 reg
= SUBREG_REG (reg
);
845 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
847 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
848 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
851 /* Searches X for any reference to a reg with the same value as REGNO,
852 returning the rtx of the reference found if any. Otherwise,
855 regno_val_use_in (unsigned int regno
, rtx x
)
861 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
864 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
865 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
869 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
872 else if (fmt
[i
] == 'E')
873 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
874 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
881 /* Generate reloads for matching OUT and INS (array of input operand
882 numbers with end marker -1) with reg class GOAL_CLASS, considering
883 output operands OUTS (similar array to INS) needing to be in different
884 registers. Add input and output reloads correspondingly to the lists
885 *BEFORE and *AFTER. OUT might be negative. In this case we generate
886 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
887 that the output operand is early clobbered for chosen alternative. */
889 match_reload (signed char out
, signed char *ins
, signed char *outs
,
890 enum reg_class goal_class
, rtx_insn
**before
,
891 rtx_insn
**after
, bool early_clobber_p
)
895 rtx new_in_reg
, new_out_reg
, reg
;
896 machine_mode inmode
, outmode
;
897 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
898 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
900 inmode
= curr_operand_mode
[ins
[0]];
901 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
902 push_to_sequence (*before
);
903 if (inmode
!= outmode
)
905 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
908 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
910 if (SCALAR_INT_MODE_P (inmode
))
911 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
913 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
914 LRA_SUBREG_P (new_out_reg
) = 1;
915 /* If the input reg is dying here, we can use the same hard
916 register for REG and IN_RTX. We do it only for original
917 pseudos as reload pseudos can die although original
918 pseudos still live where reload pseudos dies. */
919 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
920 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
921 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
926 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
928 if (SCALAR_INT_MODE_P (outmode
))
929 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
931 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
932 /* NEW_IN_REG is non-paradoxical subreg. We don't want
933 NEW_OUT_REG living above. We add clobber clause for
934 this. This is just a temporary clobber. We can remove
935 it at the end of LRA work. */
936 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
937 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
938 LRA_SUBREG_P (new_in_reg
) = 1;
939 if (GET_CODE (in_rtx
) == SUBREG
)
941 rtx subreg_reg
= SUBREG_REG (in_rtx
);
943 /* If SUBREG_REG is dying here and sub-registers IN_RTX
944 and NEW_IN_REG are similar, we can use the same hard
945 register for REG and SUBREG_REG. */
946 if (REG_P (subreg_reg
)
947 && (int) REGNO (subreg_reg
) < lra_new_regno_start
948 && GET_MODE (subreg_reg
) == outmode
949 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
950 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
951 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
957 /* Pseudos have values -- see comments for lra_reg_info.
958 Different pseudos with the same value do not conflict even if
959 they live in the same place. When we create a pseudo we
960 assign value of original pseudo (if any) from which we
961 created the new pseudo. If we create the pseudo from the
962 input pseudo, the new pseudo will have no conflict with the
963 input pseudo which is wrong when the input pseudo lives after
964 the insn and as the new pseudo value is changed by the insn
965 output. Therefore we create the new pseudo from the output
966 except the case when we have single matched dying input
969 We cannot reuse the current output register because we might
970 have a situation like "a <- a op b", where the constraints
971 force the second input operand ("b") to match the output
972 operand ("a"). "b" must then be copied into a new register
973 so that it doesn't clobber the current value of "a".
975 We can not use the same value if the output pseudo is
976 early clobbered or the input pseudo is mentioned in the
977 output, e.g. as an address part in memory, because
978 output reload will actually extend the pseudo liveness.
979 We don't care about eliminable hard regs here as we are
980 interesting only in pseudos. */
982 /* Matching input's register value is the same as one of the other
983 output operand. Output operands in a parallel insn must be in
984 different registers. */
985 out_conflict
= false;
988 for (i
= 0; outs
[i
] >= 0; i
++)
990 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
991 if (REG_P (other_out_rtx
)
992 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1001 new_in_reg
= new_out_reg
1002 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1003 && (int) REGNO (in_rtx
) < lra_new_regno_start
1004 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1006 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1008 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1009 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1012 /* In operand can be got from transformations before processing insn
1013 constraints. One example of such transformations is subreg
1014 reloading (see function simplify_operand_subreg). The new
1015 pseudos created by the transformations might have inaccurate
1016 class (ALL_REGS) and we should make their classes more
1018 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1019 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1020 *before
= get_insns ();
1022 /* Add the new pseudo to consider values of subsequent input reload
1024 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1025 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1026 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1027 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1028 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1031 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1032 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1033 *curr_id
->operand_loc
[in
] = new_in_reg
;
1035 lra_update_dups (curr_id
, ins
);
1038 /* See a comment for the input operand above. */
1039 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1040 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1043 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1045 *after
= get_insns ();
1048 *curr_id
->operand_loc
[out
] = new_out_reg
;
1049 lra_update_dup (curr_id
, out
);
1052 /* Return register class which is union of all reg classes in insn
1053 constraint alternative string starting with P. */
1054 static enum reg_class
1055 reg_class_from_constraints (const char *p
)
1058 enum reg_class op_class
= NO_REGS
;
1061 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1068 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1072 enum constraint_num cn
= lookup_constraint (p
);
1073 enum reg_class cl
= reg_class_for_constraint (cn
);
1076 if (insn_extra_address_constraint (cn
))
1078 = (reg_class_subunion
1079 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1080 ADDRESS
, SCRATCH
)]);
1084 op_class
= reg_class_subunion
[op_class
][cl
];
1087 while ((p
+= len
), c
);
1091 /* If OP is a register, return the class of the register as per
1092 get_reg_class, otherwise return NO_REGS. */
1093 static inline enum reg_class
1094 get_op_class (rtx op
)
1096 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1099 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1100 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1101 SUBREG for VAL to make them equal. */
1103 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1105 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1107 /* Usually size of mem_pseudo is greater than val size but in
1108 rare cases it can be less as it can be defined by target
1109 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1112 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1113 GET_CODE (val
) == SUBREG
1114 ? SUBREG_REG (val
) : val
);
1115 LRA_SUBREG_P (val
) = 1;
1119 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1120 LRA_SUBREG_P (mem_pseudo
) = 1;
1123 return to_p
? gen_move_insn (mem_pseudo
, val
)
1124 : gen_move_insn (val
, mem_pseudo
);
1127 /* Process a special case insn (register move), return true if we
1128 don't need to process it anymore. INSN should be a single set
1129 insn. Set up that RTL was changed through CHANGE_P and macro
1130 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1133 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1136 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1138 enum reg_class dclass
, sclass
, secondary_class
;
1139 secondary_reload_info sri
;
1141 lra_assert (curr_insn_set
!= NULL_RTX
);
1142 dreg
= dest
= SET_DEST (curr_insn_set
);
1143 sreg
= src
= SET_SRC (curr_insn_set
);
1144 if (GET_CODE (dest
) == SUBREG
)
1145 dreg
= SUBREG_REG (dest
);
1146 if (GET_CODE (src
) == SUBREG
)
1147 sreg
= SUBREG_REG (src
);
1148 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1150 sclass
= dclass
= NO_REGS
;
1152 dclass
= get_reg_class (REGNO (dreg
));
1153 gcc_assert (dclass
< LIM_REG_CLASSES
);
1154 if (dclass
== ALL_REGS
)
1155 /* ALL_REGS is used for new pseudos created by transformations
1156 like reload of SUBREG_REG (see function
1157 simplify_operand_subreg). We don't know their class yet. We
1158 should figure out the class from processing the insn
1159 constraints not in this fast path function. Even if ALL_REGS
1160 were a right class for the pseudo, secondary_... hooks usually
1161 are not define for ALL_REGS. */
1164 sclass
= get_reg_class (REGNO (sreg
));
1165 gcc_assert (sclass
< LIM_REG_CLASSES
);
1166 if (sclass
== ALL_REGS
)
1167 /* See comments above. */
1169 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1171 #ifdef SECONDARY_MEMORY_NEEDED
1172 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1173 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1174 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1175 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1183 if (! REG_P (dreg
) || ! REG_P (sreg
))
1185 sri
.prev_sri
= NULL
;
1186 sri
.icode
= CODE_FOR_nothing
;
1188 secondary_class
= NO_REGS
;
1189 /* Set up hard register for a reload pseudo for hook
1190 secondary_reload because some targets just ignore unassigned
1191 pseudos in the hook. */
1192 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1194 dregno
= REGNO (dreg
);
1195 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1199 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1201 sregno
= REGNO (sreg
);
1202 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1206 if (sclass
!= NO_REGS
)
1208 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1209 (reg_class_t
) sclass
,
1210 GET_MODE (src
), &sri
);
1211 if (sclass
== NO_REGS
1212 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1213 && dclass
!= NO_REGS
))
1215 enum reg_class old_sclass
= secondary_class
;
1216 secondary_reload_info old_sri
= sri
;
1218 sri
.prev_sri
= NULL
;
1219 sri
.icode
= CODE_FOR_nothing
;
1222 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1223 (reg_class_t
) dclass
,
1224 GET_MODE (src
), &sri
);
1225 /* Check the target hook consistency. */
1227 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1228 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1229 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1232 reg_renumber
[sregno
] = -1;
1234 reg_renumber
[dregno
] = -1;
1235 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1239 if (secondary_class
!= NO_REGS
)
1240 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1244 if (sri
.icode
== CODE_FOR_nothing
)
1245 lra_emit_move (new_reg
, src
);
1248 enum reg_class scratch_class
;
1250 scratch_class
= (reg_class_from_constraints
1251 (insn_data
[sri
.icode
].operand
[2].constraint
));
1252 scratch_reg
= (lra_create_new_reg_with_unique_value
1253 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1254 scratch_class
, "scratch"));
1255 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1258 before
= get_insns ();
1260 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1261 if (new_reg
!= NULL_RTX
)
1262 SET_SRC (curr_insn_set
) = new_reg
;
1265 if (lra_dump_file
!= NULL
)
1267 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1268 dump_insn_slim (lra_dump_file
, curr_insn
);
1270 lra_set_insn_deleted (curr_insn
);
1276 /* The following data describe the result of process_alt_operands.
1277 The data are used in curr_insn_transform to generate reloads. */
1279 /* The chosen reg classes which should be used for the corresponding
1281 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1282 /* True if the operand should be the same as another operand and that
1283 other operand does not need a reload. */
1284 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1285 /* True if the operand does not need a reload. */
1286 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1287 /* True if the operand can be offsetable memory. */
1288 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1289 /* The number of an operand to which given operand can be matched to. */
1290 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1291 /* The number of elements in the following array. */
1292 static int goal_alt_dont_inherit_ops_num
;
1293 /* Numbers of operands whose reload pseudos should not be inherited. */
1294 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1295 /* True if the insn commutative operands should be swapped. */
1296 static bool goal_alt_swapped
;
1297 /* The chosen insn alternative. */
1298 static int goal_alt_number
;
1300 /* True if the corresponding operand is the result of an equivalence
1302 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1304 /* The following five variables are used to choose the best insn
1305 alternative. They reflect final characteristics of the best
1308 /* Number of necessary reloads and overall cost reflecting the
1309 previous value and other unpleasantness of the best alternative. */
1310 static int best_losers
, best_overall
;
1311 /* Overall number hard registers used for reloads. For example, on
1312 some targets we need 2 general registers to reload DFmode and only
1313 one floating point register. */
1314 static int best_reload_nregs
;
1315 /* Overall number reflecting distances of previous reloading the same
1316 value. The distances are counted from the current BB start. It is
1317 used to improve inheritance chances. */
1318 static int best_reload_sum
;
1320 /* True if the current insn should have no correspondingly input or
1322 static bool no_input_reloads_p
, no_output_reloads_p
;
1324 /* True if we swapped the commutative operands in the current
1326 static int curr_swapped
;
1328 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1329 register of class CL. Add any input reloads to list BEFORE. AFTER
1330 is nonnull if *LOC is an automodified value; handle that case by
1331 adding the required output reloads to list AFTER. Return true if
1332 the RTL was changed.
1334 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1335 register. Return false if the address register is correct. */
1337 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1341 enum reg_class rclass
, new_class
;
1345 bool subreg_p
, before_p
= false;
1347 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1350 reg
= SUBREG_REG (*loc
);
1351 mode
= GET_MODE (reg
);
1353 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1354 between two registers with different classes, but there normally will
1355 be "mov" which transfers element of vector register into the general
1356 register, and this normally will be a subreg which should be reloaded
1357 as a whole. This is particularly likely to be triggered when
1358 -fno-split-wide-types specified. */
1360 || in_class_p (reg
, cl
, &new_class
)
1361 || GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (ptr_mode
))
1362 loc
= &SUBREG_REG (*loc
);
1366 mode
= GET_MODE (reg
);
1371 /* Always reload memory in an address even if the target supports
1373 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1378 regno
= REGNO (reg
);
1379 rclass
= get_reg_class (regno
);
1381 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1383 if (lra_dump_file
!= NULL
)
1385 fprintf (lra_dump_file
,
1386 "Changing pseudo %d in address of insn %u on equiv ",
1387 REGNO (reg
), INSN_UID (curr_insn
));
1388 dump_value_slim (lra_dump_file
, *loc
, 1);
1389 fprintf (lra_dump_file
, "\n");
1391 *loc
= copy_rtx (*loc
);
1393 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1398 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1399 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1402 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1406 lra_change_class (regno
, new_class
, " Change to", true);
1414 push_to_sequence (*before
);
1415 lra_emit_move (new_reg
, reg
);
1416 *before
= get_insns ();
1423 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1425 *after
= get_insns ();
1431 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1432 the insn to be inserted before curr insn. AFTER returns the
1433 the insn to be inserted after curr insn. ORIGREG and NEWREG
1434 are the original reg and new reg for reload. */
1436 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1441 push_to_sequence (*before
);
1442 lra_emit_move (newreg
, origreg
);
1443 *before
= get_insns ();
1449 lra_emit_move (origreg
, newreg
);
1451 *after
= get_insns ();
1456 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1458 /* Make reloads for subreg in operand NOP with internal subreg mode
1459 REG_MODE, add new reloads for further processing. Return true if
1460 any change was done. */
1462 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1465 rtx_insn
*before
, *after
;
1466 machine_mode mode
, innermode
;
1468 rtx operand
= *curr_id
->operand_loc
[nop
];
1469 enum reg_class regclass
;
1472 before
= after
= NULL
;
1474 if (GET_CODE (operand
) != SUBREG
)
1477 mode
= GET_MODE (operand
);
1478 reg
= SUBREG_REG (operand
);
1479 innermode
= GET_MODE (reg
);
1480 type
= curr_static_id
->operand
[nop
].type
;
1485 alter_subreg (curr_id
->operand_loc
[nop
], false);
1486 subst
= *curr_id
->operand_loc
[nop
];
1487 lra_assert (MEM_P (subst
));
1488 if (! valid_address_p (innermode
, XEXP (reg
, 0),
1489 MEM_ADDR_SPACE (reg
))
1490 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1491 MEM_ADDR_SPACE (subst
))
1492 || ((get_constraint_type (lookup_constraint
1493 (curr_static_id
->operand
[nop
].constraint
))
1494 != CT_SPECIAL_MEMORY
)
1495 /* We still can reload address and if the address is
1496 valid, we can remove subreg without reloading its
1498 && valid_address_p (GET_MODE (subst
),
1500 [ira_class_hard_regs
1501 [base_reg_class (GET_MODE (subst
),
1502 MEM_ADDR_SPACE (subst
),
1503 ADDRESS
, SCRATCH
)][0]],
1504 MEM_ADDR_SPACE (subst
))))
1506 /* If we change address for paradoxical subreg of memory, the
1507 address might violate the necessary alignment or the access might
1508 be slow. So take this into consideration. We should not worry
1509 about access beyond allocated memory for paradoxical memory
1510 subregs as we don't substitute such equiv memory (see processing
1511 equivalences in function lra_constraints) and because for spilled
1512 pseudos we allocate stack memory enough for the biggest
1513 corresponding paradoxical subreg. */
1514 if (!(MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (mode
)
1515 && SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
)))
1516 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1517 && SLOW_UNALIGNED_ACCESS (innermode
, MEM_ALIGN (reg
))))
1520 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1521 enum reg_class rclass
1522 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1523 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
, reg
,
1524 rclass
, TRUE
, "slow mem", &new_reg
))
1526 bool insert_before
, insert_after
;
1527 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1529 insert_before
= (type
!= OP_OUT
1530 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1531 insert_after
= type
!= OP_IN
;
1532 insert_move_for_subreg (insert_before
? &before
: NULL
,
1533 insert_after
? &after
: NULL
,
1536 *curr_id
->operand_loc
[nop
] = operand
;
1537 SUBREG_REG (operand
) = new_reg
;
1539 /* Convert to MODE. */
1541 rclass
= (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1542 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1543 rclass
, TRUE
, "slow mem", &new_reg
))
1545 bool insert_before
, insert_after
;
1546 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1548 insert_before
= type
!= OP_OUT
;
1549 insert_after
= type
!= OP_IN
;
1550 insert_move_for_subreg (insert_before
? &before
: NULL
,
1551 insert_after
? &after
: NULL
,
1554 *curr_id
->operand_loc
[nop
] = new_reg
;
1555 lra_process_new_insns (curr_insn
, before
, after
,
1556 "Inserting slow mem reload");
1560 /* If the address was valid and became invalid, prefer to reload
1561 the memory. Typical case is when the index scale should
1562 correspond the memory. */
1563 *curr_id
->operand_loc
[nop
] = operand
;
1565 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1567 alter_subreg (curr_id
->operand_loc
[nop
], false);
1570 else if (CONSTANT_P (reg
))
1572 /* Try to simplify subreg of constant. It is usually result of
1573 equivalence substitution. */
1574 if (innermode
== VOIDmode
1575 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1576 innermode
= curr_static_id
->operand
[nop
].mode
;
1577 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1578 SUBREG_BYTE (operand
))) != NULL_RTX
)
1580 *curr_id
->operand_loc
[nop
] = new_reg
;
1584 /* Put constant into memory when we have mixed modes. It generates
1585 a better code in most cases as it does not need a secondary
1586 reload memory. It also prevents LRA looping when LRA is using
1587 secondary reload memory again and again. */
1588 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1589 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1591 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1592 alter_subreg (curr_id
->operand_loc
[nop
], false);
1595 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1596 if there may be a problem accessing OPERAND in the outer
1599 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1600 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1601 /* Don't reload paradoxical subregs because we could be looping
1602 having repeatedly final regno out of hard regs range. */
1603 && (hard_regno_nregs
[hard_regno
][innermode
]
1604 >= hard_regno_nregs
[hard_regno
][mode
])
1605 && simplify_subreg_regno (hard_regno
, innermode
,
1606 SUBREG_BYTE (operand
), mode
) < 0
1607 /* Don't reload subreg for matching reload. It is actually
1608 valid subreg in LRA. */
1609 && ! LRA_SUBREG_P (operand
))
1610 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1612 enum reg_class rclass
;
1615 /* There is a big probability that we will get the same class
1616 for the new pseudo and we will get the same insn which
1617 means infinite looping. So spill the new pseudo. */
1620 /* The class will be defined later in curr_insn_transform. */
1622 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1624 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1625 rclass
, TRUE
, "subreg reg", &new_reg
))
1627 bool insert_before
, insert_after
;
1628 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1630 insert_before
= (type
!= OP_OUT
1631 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1632 insert_after
= (type
!= OP_IN
);
1633 insert_move_for_subreg (insert_before
? &before
: NULL
,
1634 insert_after
? &after
: NULL
,
1637 SUBREG_REG (operand
) = new_reg
;
1638 lra_process_new_insns (curr_insn
, before
, after
,
1639 "Inserting subreg reload");
1642 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1643 IRA allocates hardreg to the inner pseudo reg according to its mode
1644 instead of the outermode, so the size of the hardreg may not be enough
1645 to contain the outermode operand, in that case we may need to insert
1646 reload for the reg. For the following two types of paradoxical subreg,
1647 we need to insert reload:
1648 1. If the op_type is OP_IN, and the hardreg could not be paired with
1649 other hardreg to contain the outermode operand
1650 (checked by in_hard_reg_set_p), we need to insert the reload.
1651 2. If the op_type is OP_OUT or OP_INOUT.
1653 Here is a paradoxical subreg example showing how the reload is generated:
1655 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1656 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1658 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1659 here, if reg107 is assigned to hardreg R15, because R15 is the last
1660 hardreg, compiler cannot find another hardreg to pair with R15 to
1661 contain TImode data. So we insert a TImode reload reg180 for it.
1662 After reload is inserted:
1664 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1665 (reg:DI 107 [ __comp ])) -1
1666 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1667 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1669 Two reload hard registers will be allocated to reg180 to save TImode data
1671 else if (REG_P (reg
)
1672 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1673 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1674 && (hard_regno_nregs
[hard_regno
][innermode
]
1675 < hard_regno_nregs
[hard_regno
][mode
])
1676 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1678 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1681 /* The class will be defined later in curr_insn_transform. */
1682 enum reg_class rclass
1683 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1685 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1686 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1689 bool insert_before
, insert_after
;
1691 PUT_MODE (new_reg
, mode
);
1692 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1693 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1695 insert_before
= (type
!= OP_OUT
);
1696 insert_after
= (type
!= OP_IN
);
1697 insert_move_for_subreg (insert_before
? &before
: NULL
,
1698 insert_after
? &after
: NULL
,
1701 SUBREG_REG (operand
) = new_reg
;
1702 lra_process_new_insns (curr_insn
, before
, after
,
1703 "Inserting paradoxical subreg reload");
1709 /* Return TRUE if X refers for a hard register from SET. */
1711 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1713 int i
, j
, x_hard_regno
;
1720 code
= GET_CODE (x
);
1721 mode
= GET_MODE (x
);
1725 code
= GET_CODE (x
);
1726 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1727 mode
= GET_MODE (x
);
1732 x_hard_regno
= get_hard_regno (x
, true);
1733 return (x_hard_regno
>= 0
1734 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1738 struct address_info ad
;
1740 decompose_mem_address (&ad
, x
);
1741 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1743 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1746 fmt
= GET_RTX_FORMAT (code
);
1747 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1751 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1754 else if (fmt
[i
] == 'E')
1756 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1757 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1764 /* Return true if OP is a spilled pseudo. */
1766 spilled_pseudo_p (rtx op
)
1769 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1772 /* Return true if X is a general constant. */
1774 general_constant_p (rtx x
)
1776 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1780 reg_in_class_p (rtx reg
, enum reg_class cl
)
1783 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1784 return in_class_p (reg
, cl
, NULL
);
1787 /* Return true if SET of RCLASS contains no hard regs which can be
1790 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1792 enum machine_mode mode
)
1796 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1797 COPY_HARD_REG_SET (temp
, set
);
1798 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1799 return (hard_reg_set_subset_p
1800 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1803 /* Major function to choose the current insn alternative and what
1804 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1805 negative we should consider only this alternative. Return false if
1806 we can not choose the alternative or find how to reload the
1809 process_alt_operands (int only_alternative
)
1812 int nop
, overall
, nalt
;
1813 int n_alternatives
= curr_static_id
->n_alternatives
;
1814 int n_operands
= curr_static_id
->n_operands
;
1815 /* LOSERS counts the operands that don't fit this alternative and
1816 would require loading. */
1818 /* REJECT is a count of how undesirable this alternative says it is
1819 if any reloading is required. If the alternative matches exactly
1820 then REJECT is ignored, but otherwise it gets this much counted
1821 against it in addition to the reloading needed. */
1824 /* The number of elements in the following array. */
1825 int early_clobbered_regs_num
;
1826 /* Numbers of operands which are early clobber registers. */
1827 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1828 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1829 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1830 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1831 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1832 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1833 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1834 /* The number of elements in the following array. */
1835 int curr_alt_dont_inherit_ops_num
;
1836 /* Numbers of operands whose reload pseudos should not be inherited. */
1837 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1839 /* The register when the operand is a subreg of register, otherwise the
1841 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1842 /* The register if the operand is a register or subreg of register,
1844 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1845 int hard_regno
[MAX_RECOG_OPERANDS
];
1846 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1847 int reload_nregs
, reload_sum
;
1851 /* Calculate some data common for all alternatives to speed up the
1853 for (nop
= 0; nop
< n_operands
; nop
++)
1857 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1858 /* The real hard regno of the operand after the allocation. */
1859 hard_regno
[nop
] = get_hard_regno (op
, true);
1861 operand_reg
[nop
] = reg
= op
;
1862 biggest_mode
[nop
] = GET_MODE (op
);
1863 if (GET_CODE (op
) == SUBREG
)
1865 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1866 if (GET_MODE_SIZE (biggest_mode
[nop
])
1867 < GET_MODE_SIZE (GET_MODE (reg
)))
1868 biggest_mode
[nop
] = GET_MODE (reg
);
1871 operand_reg
[nop
] = NULL_RTX
;
1872 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1873 || ((int) REGNO (reg
)
1874 == lra_get_elimination_hard_regno (REGNO (reg
))))
1875 no_subreg_reg_operand
[nop
] = reg
;
1877 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1878 /* Just use natural mode for elimination result. It should
1879 be enough for extra constraints hooks. */
1880 = regno_reg_rtx
[hard_regno
[nop
]];
1883 /* The constraints are made of several alternatives. Each operand's
1884 constraint looks like foo,bar,... with commas separating the
1885 alternatives. The first alternatives for all operands go
1886 together, the second alternatives go together, etc.
1888 First loop over alternatives. */
1889 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1890 if (only_alternative
>= 0)
1891 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1893 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1895 /* Loop over operands for one constraint alternative. */
1896 if (!TEST_BIT (preferred
, nalt
))
1899 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1900 for (nop
= 0; nop
< n_operands
; nop
++)
1902 int inc
= (curr_static_id
1903 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1904 if (lra_dump_file
!= NULL
&& inc
!= 0)
1905 fprintf (lra_dump_file
,
1906 " Staticly defined alt reject+=%d\n", inc
);
1909 early_clobbered_regs_num
= 0;
1911 for (nop
= 0; nop
< n_operands
; nop
++)
1915 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1916 bool win
, did_match
, offmemok
, early_clobber_p
;
1917 /* false => this operand can be reloaded somehow for this
1920 /* true => this operand can be reloaded if the alternative
1923 /* True if a constant forced into memory would be OK for
1926 enum reg_class this_alternative
, this_costly_alternative
;
1927 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1928 bool this_alternative_match_win
, this_alternative_win
;
1929 bool this_alternative_offmemok
;
1932 enum constraint_num cn
;
1934 opalt_num
= nalt
* n_operands
+ nop
;
1935 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1937 /* Fast track for no constraints at all. */
1938 curr_alt
[nop
] = NO_REGS
;
1939 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1940 curr_alt_win
[nop
] = true;
1941 curr_alt_match_win
[nop
] = false;
1942 curr_alt_offmemok
[nop
] = false;
1943 curr_alt_matches
[nop
] = -1;
1947 op
= no_subreg_reg_operand
[nop
];
1948 mode
= curr_operand_mode
[nop
];
1950 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1953 early_clobber_p
= false;
1954 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1956 this_costly_alternative
= this_alternative
= NO_REGS
;
1957 /* We update set of possible hard regs besides its class
1958 because reg class might be inaccurate. For example,
1959 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1960 is translated in HI_REGS because classes are merged by
1961 pairs and there is no accurate intermediate class. */
1962 CLEAR_HARD_REG_SET (this_alternative_set
);
1963 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1964 this_alternative_win
= false;
1965 this_alternative_match_win
= false;
1966 this_alternative_offmemok
= false;
1967 this_alternative_matches
= -1;
1969 /* An empty constraint should be excluded by the fast
1971 lra_assert (*p
!= 0 && *p
!= ',');
1974 /* Scan this alternative's specs for this operand; set WIN
1975 if the operand fits any letter in this alternative.
1976 Otherwise, clear BADOP if this operand could fit some
1977 letter after reloads, or set WINREG if this operand could
1978 fit after reloads provided the constraint allows some
1983 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1993 early_clobber_p
= true;
1997 op_reject
+= LRA_MAX_REJECT
;
2000 op_reject
+= LRA_LOSER_COST_FACTOR
;
2004 /* Ignore rest of this alternative. */
2008 case '0': case '1': case '2': case '3': case '4':
2009 case '5': case '6': case '7': case '8': case '9':
2014 m
= strtoul (p
, &end
, 10);
2017 lra_assert (nop
> m
);
2019 this_alternative_matches
= m
;
2020 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2021 /* We are supposed to match a previous operand.
2022 If we do, we win if that one did. If we do
2023 not, count both of the operands as losers.
2024 (This is too conservative, since most of the
2025 time only a single reload insn will be needed
2026 to make the two operands win. As a result,
2027 this alternative may be rejected when it is
2028 actually desirable.) */
2030 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2031 *curr_id
->operand_loc
[m
], m_hregno
))
2033 /* We should reject matching of an early
2034 clobber operand if the matching operand is
2035 not dying in the insn. */
2036 if (! curr_static_id
->operand
[m
].early_clobber
2037 || operand_reg
[nop
] == NULL_RTX
2038 || (find_regno_note (curr_insn
, REG_DEAD
,
2040 || REGNO (op
) == REGNO (operand_reg
[m
])))
2045 /* If we are matching a non-offsettable
2046 address where an offsettable address was
2047 expected, then we must reject this
2048 combination, because we can't reload
2050 if (curr_alt_offmemok
[m
]
2051 && MEM_P (*curr_id
->operand_loc
[m
])
2052 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2057 /* Operands don't match. Both operands must
2058 allow a reload register, otherwise we
2059 cannot make them match. */
2060 if (curr_alt
[m
] == NO_REGS
)
2062 /* Retroactively mark the operand we had to
2063 match as a loser, if it wasn't already and
2064 it wasn't matched to a register constraint
2065 (e.g it might be matched by memory). */
2067 && (operand_reg
[m
] == NULL_RTX
2068 || hard_regno
[m
] < 0))
2072 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2073 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2076 /* Prefer matching earlyclobber alternative as
2077 it results in less hard regs required for
2078 the insn than a non-matching earlyclobber
2080 if (curr_static_id
->operand
[m
].early_clobber
)
2082 if (lra_dump_file
!= NULL
)
2085 " %d Matching earlyclobber alt:"
2090 /* Otherwise we prefer no matching
2091 alternatives because it gives more freedom
2093 else if (operand_reg
[nop
] == NULL_RTX
2094 || (find_regno_note (curr_insn
, REG_DEAD
,
2095 REGNO (operand_reg
[nop
]))
2098 if (lra_dump_file
!= NULL
)
2101 " %d Matching alt: reject+=2\n",
2106 /* If we have to reload this operand and some
2107 previous operand also had to match the same
2108 thing as this operand, we don't know how to do
2110 if (!match_p
|| !curr_alt_win
[m
])
2112 for (i
= 0; i
< nop
; i
++)
2113 if (curr_alt_matches
[i
] == m
)
2121 /* This can be fixed with reloads if the operand
2122 we are supposed to match can be fixed with
2125 this_alternative
= curr_alt
[m
];
2126 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2127 winreg
= this_alternative
!= NO_REGS
;
2133 || general_constant_p (op
)
2134 || spilled_pseudo_p (op
))
2140 cn
= lookup_constraint (p
);
2141 switch (get_constraint_type (cn
))
2144 cl
= reg_class_for_constraint (cn
);
2150 if (CONST_INT_P (op
)
2151 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2157 && satisfies_memory_constraint_p (op
, cn
))
2159 else if (spilled_pseudo_p (op
))
2162 /* If we didn't already win, we can reload constants
2163 via force_const_mem or put the pseudo value into
2164 memory, or make other memory by reloading the
2165 address like for 'o'. */
2166 if (CONST_POOL_OK_P (mode
, op
)
2167 || MEM_P (op
) || REG_P (op
)
2168 /* We can restore the equiv insn by a
2170 || equiv_substition_p
[nop
])
2177 /* If we didn't already win, we can reload the address
2178 into a base register. */
2179 if (satisfies_address_constraint_p (op
, cn
))
2181 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2187 if (constraint_satisfied_p (op
, cn
))
2191 case CT_SPECIAL_MEMORY
:
2193 && satisfies_memory_constraint_p (op
, cn
))
2195 else if (spilled_pseudo_p (op
))
2202 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2203 IOR_HARD_REG_SET (this_alternative_set
,
2204 reg_class_contents
[cl
]);
2207 this_costly_alternative
2208 = reg_class_subunion
[this_costly_alternative
][cl
];
2209 IOR_HARD_REG_SET (this_costly_alternative_set
,
2210 reg_class_contents
[cl
]);
2212 if (mode
== BLKmode
)
2217 if (hard_regno
[nop
] >= 0
2218 && in_hard_reg_set_p (this_alternative_set
,
2219 mode
, hard_regno
[nop
]))
2221 else if (hard_regno
[nop
] < 0
2222 && in_class_p (op
, this_alternative
, NULL
))
2227 if (c
!= ' ' && c
!= '\t')
2228 costly_p
= c
== '*';
2230 while ((p
+= len
), c
);
2232 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2233 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2234 /* Record which operands fit this alternative. */
2237 this_alternative_win
= true;
2238 if (operand_reg
[nop
] != NULL_RTX
)
2240 if (hard_regno
[nop
] >= 0)
2242 if (in_hard_reg_set_p (this_costly_alternative_set
,
2243 mode
, hard_regno
[nop
]))
2245 if (lra_dump_file
!= NULL
)
2246 fprintf (lra_dump_file
,
2247 " %d Costly set: reject++\n",
2254 /* Prefer won reg to spilled pseudo under other
2255 equal conditions for possibe inheritance. */
2258 if (lra_dump_file
!= NULL
)
2261 " %d Non pseudo reload: reject++\n",
2265 if (in_class_p (operand_reg
[nop
],
2266 this_costly_alternative
, NULL
))
2268 if (lra_dump_file
!= NULL
)
2271 " %d Non pseudo costly reload:"
2277 /* We simulate the behavior of old reload here.
2278 Although scratches need hard registers and it
2279 might result in spilling other pseudos, no reload
2280 insns are generated for the scratches. So it
2281 might cost something but probably less than old
2282 reload pass believes. */
2285 if (lra_dump_file
!= NULL
)
2286 fprintf (lra_dump_file
,
2287 " %d Scratch win: reject+=2\n",
2294 this_alternative_match_win
= true;
2297 int const_to_mem
= 0;
2300 reject
+= op_reject
;
2301 /* Never do output reload of stack pointer. It makes
2302 impossible to do elimination when SP is changed in
2304 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2305 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2308 /* If this alternative asks for a specific reg class, see if there
2309 is at least one allocatable register in that class. */
2311 = (this_alternative
== NO_REGS
2312 || (hard_reg_set_subset_p
2313 (reg_class_contents
[this_alternative
],
2314 lra_no_alloc_regs
)));
2316 /* For asms, verify that the class for this alternative is possible
2317 for the mode that is specified. */
2318 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2321 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2322 if (HARD_REGNO_MODE_OK (i
, mode
)
2323 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2326 if (i
== FIRST_PSEUDO_REGISTER
)
2330 /* If this operand accepts a register, and if the
2331 register class has at least one allocatable register,
2332 then this operand can be reloaded. */
2333 if (winreg
&& !no_regs_p
)
2338 if (lra_dump_file
!= NULL
)
2339 fprintf (lra_dump_file
,
2340 " alt=%d: Bad operand -- refuse\n",
2345 if (this_alternative
!= NO_REGS
)
2347 HARD_REG_SET available_regs
;
2349 COPY_HARD_REG_SET (available_regs
,
2350 reg_class_contents
[this_alternative
]);
2351 AND_COMPL_HARD_REG_SET
2353 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2354 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2355 if (hard_reg_set_empty_p (available_regs
))
2357 /* There are no hard regs holding a value of given
2361 this_alternative
= NO_REGS
;
2362 if (lra_dump_file
!= NULL
)
2363 fprintf (lra_dump_file
,
2364 " %d Using memory because of"
2365 " a bad mode: reject+=2\n",
2371 if (lra_dump_file
!= NULL
)
2372 fprintf (lra_dump_file
,
2373 " alt=%d: Wrong mode -- refuse\n",
2380 /* If not assigned pseudo has a class which a subset of
2381 required reg class, it is a less costly alternative
2382 as the pseudo still can get a hard reg of necessary
2384 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2385 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2386 && ira_class_subset_p
[this_alternative
][cl
])
2388 if (lra_dump_file
!= NULL
)
2391 " %d Super set class reg: reject-=3\n", nop
);
2395 this_alternative_offmemok
= offmemok
;
2396 if (this_costly_alternative
!= NO_REGS
)
2398 if (lra_dump_file
!= NULL
)
2399 fprintf (lra_dump_file
,
2400 " %d Costly loser: reject++\n", nop
);
2403 /* If the operand is dying, has a matching constraint,
2404 and satisfies constraints of the matched operand
2405 which failed to satisfy the own constraints, most probably
2406 the reload for this operand will be gone. */
2407 if (this_alternative_matches
>= 0
2408 && !curr_alt_win
[this_alternative_matches
]
2410 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2411 && (hard_regno
[nop
] >= 0
2412 ? in_hard_reg_set_p (this_alternative_set
,
2413 mode
, hard_regno
[nop
])
2414 : in_class_p (op
, this_alternative
, NULL
)))
2416 if (lra_dump_file
!= NULL
)
2419 " %d Dying matched operand reload: reject++\n",
2425 /* Strict_low_part requires to reload the register
2426 not the sub-register. In this case we should
2427 check that a final reload hard reg can hold the
2429 if (curr_static_id
->operand
[nop
].strict_low
2431 && hard_regno
[nop
] < 0
2432 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2433 && ira_class_hard_regs_num
[this_alternative
] > 0
2434 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2435 [this_alternative
][0],
2437 (*curr_id
->operand_loc
[nop
])))
2439 if (lra_dump_file
!= NULL
)
2442 " alt=%d: Strict low subreg reload -- refuse\n",
2448 if (operand_reg
[nop
] != NULL_RTX
2449 /* Output operands and matched input operands are
2450 not inherited. The following conditions do not
2451 exactly describe the previous statement but they
2452 are pretty close. */
2453 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2454 && (this_alternative_matches
< 0
2455 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2457 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2461 /* The value of reload_sum has sense only if we
2462 process insns in their order. It happens only on
2463 the first constraints sub-pass when we do most of
2465 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2466 reload_sum
+= last_reload
- bb_reload_num
;
2468 /* If this is a constant that is reloaded into the
2469 desired class by copying it to memory first, count
2470 that as another reload. This is consistent with
2471 other code and is required to avoid choosing another
2472 alternative when the constant is moved into memory.
2473 Note that the test here is precisely the same as in
2474 the code below that calls force_const_mem. */
2475 if (CONST_POOL_OK_P (mode
, op
)
2476 && ((targetm
.preferred_reload_class
2477 (op
, this_alternative
) == NO_REGS
)
2478 || no_input_reloads_p
))
2485 /* Alternative loses if it requires a type of reload not
2486 permitted for this insn. We can always reload
2487 objects with a REG_UNUSED note. */
2488 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2489 && no_output_reloads_p
2490 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2491 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2492 && no_input_reloads_p
&& ! const_to_mem
)
2493 || (this_alternative_matches
>= 0
2494 && (no_input_reloads_p
2495 || (no_output_reloads_p
2496 && (curr_static_id
->operand
2497 [this_alternative_matches
].type
!= OP_IN
)
2498 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2499 no_subreg_reg_operand
2500 [this_alternative_matches
])))))
2502 if (lra_dump_file
!= NULL
)
2505 " alt=%d: No input/otput reload -- refuse\n",
2510 /* Alternative loses if it required class pseudo can not
2511 hold value of required mode. Such insns can be
2512 described by insn definitions with mode iterators. */
2513 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2514 && ! hard_reg_set_empty_p (this_alternative_set
)
2515 /* It is common practice for constraints to use a
2516 class which does not have actually enough regs to
2517 hold the value (e.g. x86 AREG for mode requiring
2518 more one general reg). Therefore we have 2
2519 conditions to check that the reload pseudo can
2520 not hold the mode value. */
2521 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2522 [this_alternative
][0],
2523 GET_MODE (*curr_id
->operand_loc
[nop
]))
2524 /* The above condition is not enough as the first
2525 reg in ira_class_hard_regs can be not aligned for
2526 multi-words mode values. */
2527 && (prohibited_class_reg_set_mode_p
2528 (this_alternative
, this_alternative_set
,
2529 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2531 if (lra_dump_file
!= NULL
)
2532 fprintf (lra_dump_file
,
2533 " alt=%d: reload pseudo for op %d "
2534 " can not hold the mode value -- refuse\n",
2539 /* Check strong discouragement of reload of non-constant
2540 into class THIS_ALTERNATIVE. */
2541 if (! CONSTANT_P (op
) && ! no_regs_p
2542 && (targetm
.preferred_reload_class
2543 (op
, this_alternative
) == NO_REGS
2544 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2545 && (targetm
.preferred_output_reload_class
2546 (op
, this_alternative
) == NO_REGS
))))
2548 if (lra_dump_file
!= NULL
)
2549 fprintf (lra_dump_file
,
2550 " %d Non-prefered reload: reject+=%d\n",
2551 nop
, LRA_MAX_REJECT
);
2552 reject
+= LRA_MAX_REJECT
;
2555 if (! (MEM_P (op
) && offmemok
)
2556 && ! (const_to_mem
&& constmemok
))
2558 /* We prefer to reload pseudos over reloading other
2559 things, since such reloads may be able to be
2560 eliminated later. So bump REJECT in other cases.
2561 Don't do this in the case where we are forcing a
2562 constant into memory and it will then win since
2563 we don't want to have a different alternative
2565 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2567 if (lra_dump_file
!= NULL
)
2570 " %d Non-pseudo reload: reject+=2\n",
2577 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2579 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2581 if (lra_dump_file
!= NULL
)
2584 " %d Small class reload: reject+=%d\n",
2585 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2586 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2590 /* We are trying to spill pseudo into memory. It is
2591 usually more costly than moving to a hard register
2592 although it might takes the same number of
2595 Non-pseudo spill may happen also. Suppose a target allows both
2596 register and memory in the operand constraint alternatives,
2597 then it's typical that an eliminable register has a substition
2598 of "base + offset" which can either be reloaded by a simple
2599 "new_reg <= base + offset" which will match the register
2600 constraint, or a similar reg addition followed by further spill
2601 to and reload from memory which will match the memory
2602 constraint, but this memory spill will be much more costly
2605 Code below increases the reject for both pseudo and non-pseudo
2608 && !(MEM_P (op
) && offmemok
)
2609 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2611 if (lra_dump_file
!= NULL
)
2614 " %d Spill %spseudo into memory: reject+=3\n",
2615 nop
, REG_P (op
) ? "" : "Non-");
2617 if (VECTOR_MODE_P (mode
))
2619 /* Spilling vectors into memory is usually more
2620 costly as they contain big values. */
2621 if (lra_dump_file
!= NULL
)
2624 " %d Spill vector pseudo: reject+=2\n",
2630 #ifdef SECONDARY_MEMORY_NEEDED
2631 /* If reload requires moving value through secondary
2632 memory, it will need one more insn at least. */
2633 if (this_alternative
!= NO_REGS
2634 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2635 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2636 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2638 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2639 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2643 /* Input reloads can be inherited more often than output
2644 reloads can be removed, so penalize output
2646 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2648 if (lra_dump_file
!= NULL
)
2651 " %d Non input pseudo reload: reject++\n",
2657 if (early_clobber_p
&& ! scratch_p
)
2659 if (lra_dump_file
!= NULL
)
2660 fprintf (lra_dump_file
,
2661 " %d Early clobber: reject++\n", nop
);
2664 /* ??? We check early clobbers after processing all operands
2665 (see loop below) and there we update the costs more.
2666 Should we update the cost (may be approximately) here
2667 because of early clobber register reloads or it is a rare
2668 or non-important thing to be worth to do it. */
2669 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2670 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2672 if (lra_dump_file
!= NULL
)
2673 fprintf (lra_dump_file
,
2674 " alt=%d,overall=%d,losers=%d -- refuse\n",
2675 nalt
, overall
, losers
);
2679 curr_alt
[nop
] = this_alternative
;
2680 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2681 curr_alt_win
[nop
] = this_alternative_win
;
2682 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2683 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2684 curr_alt_matches
[nop
] = this_alternative_matches
;
2686 if (this_alternative_matches
>= 0
2687 && !did_match
&& !this_alternative_win
)
2688 curr_alt_win
[this_alternative_matches
] = false;
2690 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2691 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2693 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2694 /* Prevent processing non-move insns. */
2695 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2696 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2697 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2698 && REG_P (no_subreg_reg_operand
[0])
2699 && REG_P (no_subreg_reg_operand
[1])
2700 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2701 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2702 || (! curr_alt_win
[0] && curr_alt_win
[1]
2703 && REG_P (no_subreg_reg_operand
[1])
2704 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2705 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2706 && REG_P (no_subreg_reg_operand
[0])
2707 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2708 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2709 no_subreg_reg_operand
[1])
2710 || (targetm
.preferred_reload_class
2711 (no_subreg_reg_operand
[1],
2712 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2713 /* If it is a result of recent elimination in move
2714 insn we can transform it into an add still by
2715 using this alternative. */
2716 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2718 /* We have a move insn and a new reload insn will be similar
2719 to the current insn. We should avoid such situation as it
2720 results in LRA cycling. */
2721 overall
+= LRA_MAX_REJECT
;
2724 curr_alt_dont_inherit_ops_num
= 0;
2725 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2727 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2728 HARD_REG_SET temp_set
;
2730 i
= early_clobbered_nops
[nop
];
2731 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2732 || hard_regno
[i
] < 0)
2734 lra_assert (operand_reg
[i
] != NULL_RTX
);
2735 clobbered_hard_regno
= hard_regno
[i
];
2736 CLEAR_HARD_REG_SET (temp_set
);
2737 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2738 first_conflict_j
= last_conflict_j
= -1;
2739 for (j
= 0; j
< n_operands
; j
++)
2741 /* We don't want process insides of match_operator and
2742 match_parallel because otherwise we would process
2743 their operands once again generating a wrong
2745 || curr_static_id
->operand
[j
].is_operator
)
2747 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2748 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2750 /* If we don't reload j-th operand, check conflicts. */
2751 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2752 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2754 if (first_conflict_j
< 0)
2755 first_conflict_j
= j
;
2756 last_conflict_j
= j
;
2758 if (last_conflict_j
< 0)
2760 /* If earlyclobber operand conflicts with another
2761 non-matching operand which is actually the same register
2762 as the earlyclobber operand, it is better to reload the
2763 another operand as an operand matching the earlyclobber
2764 operand can be also the same. */
2765 if (first_conflict_j
== last_conflict_j
2766 && operand_reg
[last_conflict_j
] != NULL_RTX
2767 && ! curr_alt_match_win
[last_conflict_j
]
2768 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2770 curr_alt_win
[last_conflict_j
] = false;
2771 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2774 /* Early clobber was already reflected in REJECT. */
2775 lra_assert (reject
> 0);
2776 if (lra_dump_file
!= NULL
)
2779 " %d Conflict early clobber reload: reject--\n",
2782 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2786 /* We need to reload early clobbered register and the
2787 matched registers. */
2788 for (j
= 0; j
< n_operands
; j
++)
2789 if (curr_alt_matches
[j
] == i
)
2791 curr_alt_match_win
[j
] = false;
2793 overall
+= LRA_LOSER_COST_FACTOR
;
2795 if (! curr_alt_match_win
[i
])
2796 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2799 /* Remember pseudos used for match reloads are never
2801 lra_assert (curr_alt_matches
[i
] >= 0);
2802 curr_alt_win
[curr_alt_matches
[i
]] = false;
2804 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2806 /* Early clobber was already reflected in REJECT. */
2807 lra_assert (reject
> 0);
2808 if (lra_dump_file
!= NULL
)
2811 " %d Matched conflict early clobber reloads:"
2815 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2818 if (lra_dump_file
!= NULL
)
2819 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2820 nalt
, overall
, losers
, reload_nregs
);
2822 /* If this alternative can be made to work by reloading, and it
2823 needs less reloading than the others checked so far, record
2824 it as the chosen goal for reloading. */
2825 if ((best_losers
!= 0 && losers
== 0)
2826 || (((best_losers
== 0 && losers
== 0)
2827 || (best_losers
!= 0 && losers
!= 0))
2828 && (best_overall
> overall
2829 || (best_overall
== overall
2830 /* If the cost of the reloads is the same,
2831 prefer alternative which requires minimal
2832 number of reload regs. */
2833 && (reload_nregs
< best_reload_nregs
2834 || (reload_nregs
== best_reload_nregs
2835 && (best_reload_sum
< reload_sum
2836 || (best_reload_sum
== reload_sum
2837 && nalt
< goal_alt_number
))))))))
2839 for (nop
= 0; nop
< n_operands
; nop
++)
2841 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2842 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2843 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2844 goal_alt
[nop
] = curr_alt
[nop
];
2845 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2847 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2848 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2849 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2850 goal_alt_swapped
= curr_swapped
;
2851 best_overall
= overall
;
2852 best_losers
= losers
;
2853 best_reload_nregs
= reload_nregs
;
2854 best_reload_sum
= reload_sum
;
2855 goal_alt_number
= nalt
;
2858 /* Everything is satisfied. Do not process alternatives
2867 /* Make reload base reg from address AD. */
2869 base_to_reg (struct address_info
*ad
)
2873 rtx new_inner
= NULL_RTX
;
2874 rtx new_reg
= NULL_RTX
;
2876 rtx_insn
*last_insn
= get_last_insn();
2878 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2879 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2880 get_index_code (ad
));
2881 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2883 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2884 ad
->disp_term
== NULL
2885 ? gen_int_mode (0, ad
->mode
)
2887 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2889 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base_term
));
2890 code
= recog_memoized (insn
);
2893 delete_insns_since (last_insn
);
2900 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2902 base_plus_disp_to_reg (struct address_info
*ad
)
2907 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2908 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2909 get_index_code (ad
));
2910 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2912 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2916 /* Make reload of index part of address AD. Return the new
2919 index_part_to_reg (struct address_info
*ad
)
2923 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2924 INDEX_REG_CLASS
, "index term");
2925 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2926 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2930 /* Return true if we can add a displacement to address AD, even if that
2931 makes the address invalid. The fix-up code requires any new address
2932 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2934 can_add_disp_p (struct address_info
*ad
)
2936 return (!ad
->autoinc_p
2937 && ad
->segment
== NULL
2938 && ad
->base
== ad
->base_term
2939 && ad
->disp
== ad
->disp_term
);
2942 /* Make equiv substitution in address AD. Return true if a substitution
2945 equiv_address_substitution (struct address_info
*ad
)
2947 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2948 HOST_WIDE_INT disp
, scale
;
2951 base_term
= strip_subreg (ad
->base_term
);
2952 if (base_term
== NULL
)
2953 base_reg
= new_base_reg
= NULL_RTX
;
2956 base_reg
= *base_term
;
2957 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2959 index_term
= strip_subreg (ad
->index_term
);
2960 if (index_term
== NULL
)
2961 index_reg
= new_index_reg
= NULL_RTX
;
2964 index_reg
= *index_term
;
2965 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2967 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2971 if (lra_dump_file
!= NULL
)
2973 fprintf (lra_dump_file
, "Changing address in insn %d ",
2974 INSN_UID (curr_insn
));
2975 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2977 if (base_reg
!= new_base_reg
)
2979 if (REG_P (new_base_reg
))
2981 *base_term
= new_base_reg
;
2984 else if (GET_CODE (new_base_reg
) == PLUS
2985 && REG_P (XEXP (new_base_reg
, 0))
2986 && CONST_INT_P (XEXP (new_base_reg
, 1))
2987 && can_add_disp_p (ad
))
2989 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2990 *base_term
= XEXP (new_base_reg
, 0);
2993 if (ad
->base_term2
!= NULL
)
2994 *ad
->base_term2
= *ad
->base_term
;
2996 if (index_reg
!= new_index_reg
)
2998 if (REG_P (new_index_reg
))
3000 *index_term
= new_index_reg
;
3003 else if (GET_CODE (new_index_reg
) == PLUS
3004 && REG_P (XEXP (new_index_reg
, 0))
3005 && CONST_INT_P (XEXP (new_index_reg
, 1))
3006 && can_add_disp_p (ad
)
3007 && (scale
= get_index_scale (ad
)))
3009 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
3010 *index_term
= XEXP (new_index_reg
, 0);
3016 if (ad
->disp
!= NULL
)
3017 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3020 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3021 update_address (ad
);
3025 if (lra_dump_file
!= NULL
)
3028 fprintf (lra_dump_file
, " -- no change\n");
3031 fprintf (lra_dump_file
, " on equiv ");
3032 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3033 fprintf (lra_dump_file
, "\n");
3039 /* Major function to make reloads for an address in operand NOP or
3040 check its correctness (If CHECK_ONLY_P is true). The supported
3043 1) an address that existed before LRA started, at which point it
3044 must have been valid. These addresses are subject to elimination
3045 and may have become invalid due to the elimination offset being out
3048 2) an address created by forcing a constant to memory
3049 (force_const_to_mem). The initial form of these addresses might
3050 not be valid, and it is this function's job to make them valid.
3052 3) a frame address formed from a register and a (possibly zero)
3053 constant offset. As above, these addresses might not be valid and
3054 this function must make them so.
3056 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3057 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3058 address. Return true for any RTL change.
3060 The function is a helper function which does not produce all
3061 transformations (when CHECK_ONLY_P is false) which can be
3062 necessary. It does just basic steps. To do all necessary
3063 transformations use function process_address. */
3065 process_address_1 (int nop
, bool check_only_p
,
3066 rtx_insn
**before
, rtx_insn
**after
)
3068 struct address_info ad
;
3070 HOST_WIDE_INT scale
;
3071 rtx op
= *curr_id
->operand_loc
[nop
];
3072 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3073 enum constraint_num cn
= lookup_constraint (constraint
);
3074 bool change_p
= false;
3077 && GET_MODE (op
) == BLKmode
3078 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3081 if (insn_extra_address_constraint (cn
))
3082 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3083 /* Do not attempt to decompose arbitrary addresses generated by combine
3084 for asm operands with loose constraints, e.g 'X'. */
3086 && !(get_constraint_type (cn
) == CT_FIXED_FORM
3087 && constraint_satisfied_p (op
, cn
)))
3088 decompose_mem_address (&ad
, op
);
3089 else if (GET_CODE (op
) == SUBREG
3090 && MEM_P (SUBREG_REG (op
)))
3091 decompose_mem_address (&ad
, SUBREG_REG (op
));
3094 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3095 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3096 when INDEX_REG_CLASS is a single register class. */
3097 if (ad
.base_term
!= NULL
3098 && ad
.index_term
!= NULL
3099 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3100 && REG_P (*ad
.base_term
)
3101 && REG_P (*ad
.index_term
)
3102 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3103 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3105 std::swap (ad
.base
, ad
.index
);
3106 std::swap (ad
.base_term
, ad
.index_term
);
3109 change_p
= equiv_address_substitution (&ad
);
3110 if (ad
.base_term
!= NULL
3111 && (process_addr_reg
3112 (ad
.base_term
, check_only_p
, before
,
3114 && !(REG_P (*ad
.base_term
)
3115 && find_regno_note (curr_insn
, REG_DEAD
,
3116 REGNO (*ad
.base_term
)) != NULL_RTX
)
3118 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3119 get_index_code (&ad
)))))
3122 if (ad
.base_term2
!= NULL
)
3123 *ad
.base_term2
= *ad
.base_term
;
3125 if (ad
.index_term
!= NULL
3126 && process_addr_reg (ad
.index_term
, check_only_p
,
3127 before
, NULL
, INDEX_REG_CLASS
))
3130 /* Target hooks sometimes don't treat extra-constraint addresses as
3131 legitimate address_operands, so handle them specially. */
3132 if (insn_extra_address_constraint (cn
)
3133 && satisfies_address_constraint_p (&ad
, cn
))
3139 /* There are three cases where the shape of *AD.INNER may now be invalid:
3141 1) the original address was valid, but either elimination or
3142 equiv_address_substitution was applied and that made
3143 the address invalid.
3145 2) the address is an invalid symbolic address created by
3148 3) the address is a frame address with an invalid offset.
3150 4) the address is a frame address with an invalid base.
3152 All these cases involve a non-autoinc address, so there is no
3153 point revalidating other types. */
3154 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3157 /* Any index existed before LRA started, so we can assume that the
3158 presence and shape of the index is valid. */
3159 push_to_sequence (*before
);
3160 lra_assert (ad
.disp
== ad
.disp_term
);
3161 if (ad
.base
== NULL
)
3163 if (ad
.index
== NULL
)
3166 rtx_insn
*last
= get_last_insn ();
3168 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3170 rtx addr
= *ad
.inner
;
3172 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3175 /* addr => lo_sum (new_base, addr), case (2) above. */
3176 insn
= emit_insn (gen_rtx_SET
3178 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3179 code
= recog_memoized (insn
);
3182 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3183 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3185 /* Try to put lo_sum into register. */
3186 insn
= emit_insn (gen_rtx_SET
3188 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3189 code
= recog_memoized (insn
);
3192 *ad
.inner
= new_reg
;
3193 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3203 delete_insns_since (last
);
3208 /* addr => new_base, case (2) above. */
3209 lra_emit_move (new_reg
, addr
);
3211 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3213 insn
= NEXT_INSN (insn
))
3214 if (recog_memoized (insn
) < 0)
3216 if (insn
!= NULL_RTX
)
3218 /* Do nothing if we cannot generate right insns.
3219 This is analogous to reload pass behavior. */
3220 delete_insns_since (last
);
3224 *ad
.inner
= new_reg
;
3229 /* index * scale + disp => new base + index * scale,
3231 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3232 GET_CODE (*ad
.index
));
3234 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3235 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3236 lra_emit_move (new_reg
, *ad
.disp
);
3237 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3238 new_reg
, *ad
.index
);
3241 else if (ad
.index
== NULL
)
3246 rtx_insn
*insns
, *last_insn
;
3247 /* Try to reload base into register only if the base is invalid
3248 for the address but with valid offset, case (4) above. */
3250 new_reg
= base_to_reg (&ad
);
3252 /* base + disp => new base, cases (1) and (3) above. */
3253 /* Another option would be to reload the displacement into an
3254 index register. However, postreload has code to optimize
3255 address reloads that have the same base and different
3256 displacements, so reloading into an index register would
3257 not necessarily be a win. */
3258 if (new_reg
== NULL_RTX
)
3259 new_reg
= base_plus_disp_to_reg (&ad
);
3260 insns
= get_insns ();
3261 last_insn
= get_last_insn ();
3262 /* If we generated at least two insns, try last insn source as
3263 an address. If we succeed, we generate one less insn. */
3264 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3265 && GET_CODE (SET_SRC (set
)) == PLUS
3266 && REG_P (XEXP (SET_SRC (set
), 0))
3267 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3269 *ad
.inner
= SET_SRC (set
);
3270 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3272 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3273 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3274 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3275 get_index_code (&ad
));
3276 regno
= REGNO (*ad
.base_term
);
3277 if (regno
>= FIRST_PSEUDO_REGISTER
3278 && cl
!= lra_get_allocno_class (regno
))
3279 lra_change_class (regno
, cl
, " Change to", true);
3280 new_reg
= SET_SRC (set
);
3281 delete_insns_since (PREV_INSN (last_insn
));
3284 /* Try if target can split displacement into legitimite new disp
3285 and offset. If it's the case, we replace the last insn with
3286 insns for base + offset => new_reg and set new_reg + new disp
3288 last_insn
= get_last_insn ();
3289 if ((set
= single_set (last_insn
)) != NULL_RTX
3290 && GET_CODE (SET_SRC (set
)) == PLUS
3291 && REG_P (XEXP (SET_SRC (set
), 0))
3292 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3293 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3295 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3296 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3299 rtx_insn
*new_insns
;
3301 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3302 new_insns
= get_insns ();
3304 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3305 delete_insns_since (PREV_INSN (last_insn
));
3306 add_insn (new_insns
);
3307 insns
= get_insns ();
3312 *ad
.inner
= new_reg
;
3314 else if (ad
.disp_term
!= NULL
)
3316 /* base + scale * index + disp => new base + scale * index,
3318 new_reg
= base_plus_disp_to_reg (&ad
);
3319 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3320 new_reg
, *ad
.index
);
3322 else if ((scale
= get_index_scale (&ad
)) == 1)
3324 /* The last transformation to one reg will be made in
3325 curr_insn_transform function. */
3329 else if (scale
!= 0)
3331 /* base + scale * index => base + new_reg,
3333 Index part of address may become invalid. For example, we
3334 changed pseudo on the equivalent memory and a subreg of the
3335 pseudo onto the memory of different mode for which the scale is
3337 new_reg
= index_part_to_reg (&ad
);
3338 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3339 *ad
.base_term
, new_reg
);
3343 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3345 rtx addr
= *ad
.inner
;
3347 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3348 /* addr => new_base. */
3349 lra_emit_move (new_reg
, addr
);
3350 *ad
.inner
= new_reg
;
3352 *before
= get_insns ();
3357 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3358 Use process_address_1 as a helper function. Return true for any
3361 If CHECK_ONLY_P is true, just check address correctness. Return
3362 false if the address correct. */
3364 process_address (int nop
, bool check_only_p
,
3365 rtx_insn
**before
, rtx_insn
**after
)
3369 while (process_address_1 (nop
, check_only_p
, before
, after
))
3378 /* Emit insns to reload VALUE into a new register. VALUE is an
3379 auto-increment or auto-decrement RTX whose operand is a register or
3380 memory location; so reloading involves incrementing that location.
3381 IN is either identical to VALUE, or some cheaper place to reload
3382 value being incremented/decremented from.
3384 INC_AMOUNT is the number to increment or decrement by (always
3385 positive and ignored for POST_MODIFY/PRE_MODIFY).
3387 Return pseudo containing the result. */
3389 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3391 /* REG or MEM to be copied and incremented. */
3392 rtx incloc
= XEXP (value
, 0);
3393 /* Nonzero if increment after copying. */
3394 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3395 || GET_CODE (value
) == POST_MODIFY
);
3400 rtx real_in
= in
== value
? incloc
: in
;
3404 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3406 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3407 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3408 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3409 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3410 inc
= XEXP (XEXP (value
, 1), 1);
3414 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3415 inc_amount
= -inc_amount
;
3417 inc
= GEN_INT (inc_amount
);
3420 if (! post
&& REG_P (incloc
))
3423 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3426 if (real_in
!= result
)
3428 /* First copy the location to the result register. */
3429 lra_assert (REG_P (result
));
3430 emit_insn (gen_move_insn (result
, real_in
));
3433 /* We suppose that there are insns to add/sub with the constant
3434 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3435 old reload worked with this assumption. If the assumption
3436 becomes wrong, we should use approach in function
3437 base_plus_disp_to_reg. */
3440 /* See if we can directly increment INCLOC. */
3441 last
= get_last_insn ();
3442 add_insn
= emit_insn (plus_p
3443 ? gen_add2_insn (incloc
, inc
)
3444 : gen_sub2_insn (incloc
, inc
));
3446 code
= recog_memoized (add_insn
);
3449 if (! post
&& result
!= incloc
)
3450 emit_insn (gen_move_insn (result
, incloc
));
3453 delete_insns_since (last
);
3456 /* If couldn't do the increment directly, must increment in RESULT.
3457 The way we do this depends on whether this is pre- or
3458 post-increment. For pre-increment, copy INCLOC to the reload
3459 register, increment it there, then save back. */
3462 if (real_in
!= result
)
3463 emit_insn (gen_move_insn (result
, real_in
));
3465 emit_insn (gen_add2_insn (result
, inc
));
3467 emit_insn (gen_sub2_insn (result
, inc
));
3468 if (result
!= incloc
)
3469 emit_insn (gen_move_insn (incloc
, result
));
3475 Because this might be a jump insn or a compare, and because
3476 RESULT may not be available after the insn in an input
3477 reload, we must do the incrementing before the insn being
3480 We have already copied IN to RESULT. Increment the copy in
3481 RESULT, save that back, then decrement RESULT so it has
3482 the original value. */
3484 emit_insn (gen_add2_insn (result
, inc
));
3486 emit_insn (gen_sub2_insn (result
, inc
));
3487 emit_insn (gen_move_insn (incloc
, result
));
3488 /* Restore non-modified value for the result. We prefer this
3489 way because it does not require an additional hard
3493 if (CONST_INT_P (inc
))
3494 emit_insn (gen_add2_insn (result
,
3495 gen_int_mode (-INTVAL (inc
),
3496 GET_MODE (result
))));
3498 emit_insn (gen_sub2_insn (result
, inc
));
3501 emit_insn (gen_add2_insn (result
, inc
));
3506 /* Return true if the current move insn does not need processing as we
3507 already know that it satisfies its constraints. */
3509 simple_move_p (void)
3512 enum reg_class dclass
, sclass
;
3514 lra_assert (curr_insn_set
!= NULL_RTX
);
3515 dest
= SET_DEST (curr_insn_set
);
3516 src
= SET_SRC (curr_insn_set
);
3518 /* If the instruction has multiple sets we need to process it even if it
3519 is single_set. This can happen if one or more of the SETs are dead.
3521 if (multiple_sets (curr_insn
))
3524 return ((dclass
= get_op_class (dest
)) != NO_REGS
3525 && (sclass
= get_op_class (src
)) != NO_REGS
3526 /* The backend guarantees that register moves of cost 2
3527 never need reloads. */
3528 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3531 /* Swap operands NOP and NOP + 1. */
3533 swap_operands (int nop
)
3535 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3536 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3537 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3538 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3539 /* Swap the duplicates too. */
3540 lra_update_dup (curr_id
, nop
);
3541 lra_update_dup (curr_id
, nop
+ 1);
3544 /* Main entry point of the constraint code: search the body of the
3545 current insn to choose the best alternative. It is mimicking insn
3546 alternative cost calculation model of former reload pass. That is
3547 because machine descriptions were written to use this model. This
3548 model can be changed in future. Make commutative operand exchange
3551 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3552 constraints. Return true if any change happened during function
3555 If CHECK_ONLY_P is true then don't do any transformation. Just
3556 check that the insn satisfies all constraints. If the insn does
3557 not satisfy any constraint, return true. */
3559 curr_insn_transform (bool check_only_p
)
3566 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3567 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3568 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3569 rtx_insn
*before
, *after
;
3571 /* Flag that the insn has been changed through a transformation. */
3574 #ifdef SECONDARY_MEMORY_NEEDED
3577 int max_regno_before
;
3578 int reused_alternative_num
;
3580 curr_insn_set
= single_set (curr_insn
);
3581 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3584 no_input_reloads_p
= no_output_reloads_p
= false;
3585 goal_alt_number
= -1;
3586 change_p
= sec_mem_p
= false;
3587 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3588 reloads; neither are insns that SET cc0. Insns that use CC0 are
3589 not allowed to have any input reloads. */
3590 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3591 no_output_reloads_p
= true;
3593 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3594 no_input_reloads_p
= true;
3595 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3596 no_output_reloads_p
= true;
3598 n_operands
= curr_static_id
->n_operands
;
3599 n_alternatives
= curr_static_id
->n_alternatives
;
3601 /* Just return "no reloads" if insn has no operands with
3603 if (n_operands
== 0 || n_alternatives
== 0)
3606 max_regno_before
= max_reg_num ();
3608 for (i
= 0; i
< n_operands
; i
++)
3610 goal_alt_matched
[i
][0] = -1;
3611 goal_alt_matches
[i
] = -1;
3614 commutative
= curr_static_id
->commutative
;
3616 /* Now see what we need for pseudos that didn't get hard regs or got
3617 the wrong kind of hard reg. For this, we must consider all the
3618 operands together against the register constraints. */
3620 best_losers
= best_overall
= INT_MAX
;
3621 best_reload_sum
= 0;
3623 curr_swapped
= false;
3624 goal_alt_swapped
= false;
3627 /* Make equivalence substitution and memory subreg elimination
3628 before address processing because an address legitimacy can
3629 depend on memory mode. */
3630 for (i
= 0; i
< n_operands
; i
++)
3633 bool op_change_p
= false;
3635 if (curr_static_id
->operand
[i
].is_operator
)
3638 old
= op
= *curr_id
->operand_loc
[i
];
3639 if (GET_CODE (old
) == SUBREG
)
3640 old
= SUBREG_REG (old
);
3641 subst
= get_equiv_with_elimination (old
, curr_insn
);
3642 original_subreg_reg_mode
[i
] = VOIDmode
;
3643 equiv_substition_p
[i
] = false;
3646 equiv_substition_p
[i
] = true;
3647 subst
= copy_rtx (subst
);
3648 lra_assert (REG_P (old
));
3649 if (GET_CODE (op
) != SUBREG
)
3650 *curr_id
->operand_loc
[i
] = subst
;
3653 SUBREG_REG (op
) = subst
;
3654 if (GET_MODE (subst
) == VOIDmode
)
3655 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3657 if (lra_dump_file
!= NULL
)
3659 fprintf (lra_dump_file
,
3660 "Changing pseudo %d in operand %i of insn %u on equiv ",
3661 REGNO (old
), i
, INSN_UID (curr_insn
));
3662 dump_value_slim (lra_dump_file
, subst
, 1);
3663 fprintf (lra_dump_file
, "\n");
3665 op_change_p
= change_p
= true;
3667 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3670 lra_update_dup (curr_id
, i
);
3674 /* Reload address registers and displacements. We do it before
3675 finding an alternative because of memory constraints. */
3676 before
= after
= NULL
;
3677 for (i
= 0; i
< n_operands
; i
++)
3678 if (! curr_static_id
->operand
[i
].is_operator
3679 && process_address (i
, check_only_p
, &before
, &after
))
3684 lra_update_dup (curr_id
, i
);
3688 /* If we've changed the instruction then any alternative that
3689 we chose previously may no longer be valid. */
3690 lra_set_used_insn_alternative (curr_insn
, -1);
3692 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3693 && check_and_process_move (&change_p
, &sec_mem_p
))
3698 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3699 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3700 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3701 reused_alternative_num
, INSN_UID (curr_insn
));
3703 if (process_alt_operands (reused_alternative_num
))
3707 return ! alt_p
|| best_losers
!= 0;
3709 /* If insn is commutative (it's safe to exchange a certain pair of
3710 operands) then we need to try each alternative twice, the second
3711 time matching those two operands as if we had exchanged them. To
3712 do this, really exchange them in operands.
3714 If we have just tried the alternatives the second time, return
3715 operands to normal and drop through. */
3717 if (reused_alternative_num
< 0 && commutative
>= 0)
3719 curr_swapped
= !curr_swapped
;
3722 swap_operands (commutative
);
3726 swap_operands (commutative
);
3729 if (! alt_p
&& ! sec_mem_p
)
3731 /* No alternative works with reloads?? */
3732 if (INSN_CODE (curr_insn
) >= 0)
3733 fatal_insn ("unable to generate reloads for:", curr_insn
);
3734 error_for_asm (curr_insn
,
3735 "inconsistent operand constraints in an %<asm%>");
3736 /* Avoid further trouble with this insn. */
3737 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3738 lra_invalidate_insn_data (curr_insn
);
3742 /* If the best alternative is with operands 1 and 2 swapped, swap
3743 them. Update the operand numbers of any reloads already
3746 if (goal_alt_swapped
)
3748 if (lra_dump_file
!= NULL
)
3749 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3750 INSN_UID (curr_insn
));
3752 /* Swap the duplicates too. */
3753 swap_operands (commutative
);
3757 #ifdef SECONDARY_MEMORY_NEEDED
3758 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3759 too conservatively. So we use the secondary memory only if there
3760 is no any alternative without reloads. */
3761 use_sec_mem_p
= false;
3763 use_sec_mem_p
= true;
3766 for (i
= 0; i
< n_operands
; i
++)
3767 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3769 use_sec_mem_p
= i
< n_operands
;
3774 int in
= -1, out
= -1;
3775 rtx new_reg
, src
, dest
, rld
;
3776 machine_mode sec_mode
, rld_mode
;
3778 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3779 dest
= SET_DEST (curr_insn_set
);
3780 src
= SET_SRC (curr_insn_set
);
3781 for (i
= 0; i
< n_operands
; i
++)
3782 if (*curr_id
->operand_loc
[i
] == dest
)
3784 else if (*curr_id
->operand_loc
[i
] == src
)
3786 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3787 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3788 out
= curr_static_id
->dup_num
[i
];
3789 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3790 in
= curr_static_id
->dup_num
[i
];
3791 lra_assert (out
>= 0 && in
>= 0
3792 && curr_static_id
->operand
[out
].type
== OP_OUT
3793 && curr_static_id
->operand
[in
].type
== OP_IN
);
3794 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3796 rld_mode
= GET_MODE (rld
);
3797 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3798 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3800 sec_mode
= rld_mode
;
3802 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3803 NO_REGS
, "secondary");
3804 /* If the mode is changed, it should be wider. */
3805 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3806 if (sec_mode
!= rld_mode
)
3808 /* If the target says specifically to use another mode for
3809 secondary memory moves we can not reuse the original
3811 after
= emit_spill_move (false, new_reg
, dest
);
3812 lra_process_new_insns (curr_insn
, NULL
, after
,
3813 "Inserting the sec. move");
3814 /* We may have non null BEFORE here (e.g. after address
3816 push_to_sequence (before
);
3817 before
= emit_spill_move (true, new_reg
, src
);
3819 before
= get_insns ();
3821 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3822 lra_set_insn_deleted (curr_insn
);
3824 else if (dest
== rld
)
3826 *curr_id
->operand_loc
[out
] = new_reg
;
3827 lra_update_dup (curr_id
, out
);
3828 after
= emit_spill_move (false, new_reg
, dest
);
3829 lra_process_new_insns (curr_insn
, NULL
, after
,
3830 "Inserting the sec. move");
3834 *curr_id
->operand_loc
[in
] = new_reg
;
3835 lra_update_dup (curr_id
, in
);
3836 /* See comments above. */
3837 push_to_sequence (before
);
3838 before
= emit_spill_move (true, new_reg
, src
);
3840 before
= get_insns ();
3842 lra_process_new_insns (curr_insn
, before
, NULL
,
3843 "Inserting the sec. move");
3845 lra_update_insn_regno_info (curr_insn
);
3850 lra_assert (goal_alt_number
>= 0);
3851 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3853 if (lra_dump_file
!= NULL
)
3857 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3858 goal_alt_number
, INSN_UID (curr_insn
));
3859 for (i
= 0; i
< n_operands
; i
++)
3861 p
= (curr_static_id
->operand_alternative
3862 [goal_alt_number
* n_operands
+ i
].constraint
);
3865 fprintf (lra_dump_file
, " (%d) ", i
);
3866 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3867 fputc (*p
, lra_dump_file
);
3869 if (INSN_CODE (curr_insn
) >= 0
3870 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3871 fprintf (lra_dump_file
, " {%s}", p
);
3872 if (curr_id
->sp_offset
!= 0)
3873 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3874 curr_id
->sp_offset
);
3875 fprintf (lra_dump_file
, "\n");
3878 /* Right now, for any pair of operands I and J that are required to
3879 match, with J < I, goal_alt_matches[I] is J. Add I to
3880 goal_alt_matched[J]. */
3882 for (i
= 0; i
< n_operands
; i
++)
3883 if ((j
= goal_alt_matches
[i
]) >= 0)
3885 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3887 /* We allow matching one output operand and several input
3890 || (curr_static_id
->operand
[j
].type
== OP_OUT
3891 && curr_static_id
->operand
[i
].type
== OP_IN
3892 && (curr_static_id
->operand
3893 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3894 goal_alt_matched
[j
][k
] = i
;
3895 goal_alt_matched
[j
][k
+ 1] = -1;
3898 for (i
= 0; i
< n_operands
; i
++)
3899 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3901 /* Any constants that aren't allowed and can't be reloaded into
3902 registers are here changed into memory references. */
3903 for (i
= 0; i
< n_operands
; i
++)
3904 if (goal_alt_win
[i
])
3907 enum reg_class new_class
;
3908 rtx reg
= *curr_id
->operand_loc
[i
];
3910 if (GET_CODE (reg
) == SUBREG
)
3911 reg
= SUBREG_REG (reg
);
3913 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3915 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3917 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3920 lra_change_class (regno
, new_class
, " Change to", true);
3926 const char *constraint
;
3928 rtx op
= *curr_id
->operand_loc
[i
];
3929 rtx subreg
= NULL_RTX
;
3930 machine_mode mode
= curr_operand_mode
[i
];
3932 if (GET_CODE (op
) == SUBREG
)
3935 op
= SUBREG_REG (op
);
3936 mode
= GET_MODE (op
);
3939 if (CONST_POOL_OK_P (mode
, op
)
3940 && ((targetm
.preferred_reload_class
3941 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3942 || no_input_reloads_p
))
3944 rtx tem
= force_const_mem (mode
, op
);
3947 if (subreg
!= NULL_RTX
)
3948 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3950 *curr_id
->operand_loc
[i
] = tem
;
3951 lra_update_dup (curr_id
, i
);
3952 process_address (i
, false, &before
, &after
);
3954 /* If the alternative accepts constant pool refs directly
3955 there will be no reload needed at all. */
3956 if (subreg
!= NULL_RTX
)
3958 /* Skip alternatives before the one requested. */
3959 constraint
= (curr_static_id
->operand_alternative
3960 [goal_alt_number
* n_operands
+ i
].constraint
);
3962 (c
= *constraint
) && c
!= ',' && c
!= '#';
3963 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3965 enum constraint_num cn
= lookup_constraint (constraint
);
3966 if ((insn_extra_memory_constraint (cn
)
3967 || insn_extra_special_memory_constraint (cn
))
3968 && satisfies_memory_constraint_p (tem
, cn
))
3971 if (c
== '\0' || c
== ',' || c
== '#')
3974 goal_alt_win
[i
] = true;
3980 for (i
= 0; i
< n_operands
; i
++)
3983 bool optional_p
= false;
3985 rtx op
= *curr_id
->operand_loc
[i
];
3987 if (goal_alt_win
[i
])
3989 if (goal_alt
[i
] == NO_REGS
3991 /* When we assign NO_REGS it means that we will not
3992 assign a hard register to the scratch pseudo by
3993 assigment pass and the scratch pseudo will be
3994 spilled. Spilled scratch pseudos are transformed
3995 back to scratches at the LRA end. */
3996 && lra_former_scratch_operand_p (curr_insn
, i
)
3997 && lra_former_scratch_p (REGNO (op
)))
3999 int regno
= REGNO (op
);
4000 lra_change_class (regno
, NO_REGS
, " Change to", true);
4001 if (lra_get_regno_hard_regno (regno
) >= 0)
4002 /* We don't have to mark all insn affected by the
4003 spilled pseudo as there is only one such insn, the
4005 reg_renumber
[regno
] = -1;
4006 lra_assert (bitmap_single_bit_set_p
4007 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4009 /* We can do an optional reload. If the pseudo got a hard
4010 reg, we might improve the code through inheritance. If
4011 it does not get a hard register we coalesce memory/memory
4012 moves later. Ignore move insns to avoid cycling. */
4014 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4015 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4016 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4017 && regno
< new_regno_start
4018 && ! lra_former_scratch_p (regno
)
4019 && reg_renumber
[regno
] < 0
4020 /* Check that the optional reload pseudo will be able to
4021 hold given mode value. */
4022 && ! (prohibited_class_reg_set_mode_p
4023 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4024 PSEUDO_REGNO_MODE (regno
)))
4025 && (curr_insn_set
== NULL_RTX
4026 || !((REG_P (SET_SRC (curr_insn_set
))
4027 || MEM_P (SET_SRC (curr_insn_set
))
4028 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4029 && (REG_P (SET_DEST (curr_insn_set
))
4030 || MEM_P (SET_DEST (curr_insn_set
))
4031 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4037 /* Operands that match previous ones have already been handled. */
4038 if (goal_alt_matches
[i
] >= 0)
4041 /* We should not have an operand with a non-offsettable address
4042 appearing where an offsettable address will do. It also may
4043 be a case when the address should be special in other words
4044 not a general one (e.g. it needs no index reg). */
4045 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4047 enum reg_class rclass
;
4048 rtx
*loc
= &XEXP (op
, 0);
4049 enum rtx_code code
= GET_CODE (*loc
);
4051 push_to_sequence (before
);
4052 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4054 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4055 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4056 /* This value does not matter for MODIFY. */
4057 GET_MODE_SIZE (GET_MODE (op
)));
4058 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4059 "offsetable address", &new_reg
))
4060 lra_emit_move (new_reg
, *loc
);
4061 before
= get_insns ();
4064 lra_update_dup (curr_id
, i
);
4066 else if (goal_alt_matched
[i
][0] == -1)
4070 int hard_regno
, byte
;
4071 enum op_type type
= curr_static_id
->operand
[i
].type
;
4073 loc
= curr_id
->operand_loc
[i
];
4074 mode
= curr_operand_mode
[i
];
4075 if (GET_CODE (*loc
) == SUBREG
)
4077 reg
= SUBREG_REG (*loc
);
4078 byte
= SUBREG_BYTE (*loc
);
4080 /* Strict_low_part requires reload the register not
4081 the sub-register. */
4082 && (curr_static_id
->operand
[i
].strict_low
4083 || (GET_MODE_SIZE (mode
)
4084 <= GET_MODE_SIZE (GET_MODE (reg
))
4086 = get_try_hard_regno (REGNO (reg
))) >= 0
4087 && (simplify_subreg_regno
4089 GET_MODE (reg
), byte
, mode
) < 0)
4090 && (goal_alt
[i
] == NO_REGS
4091 || (simplify_subreg_regno
4092 (ira_class_hard_regs
[goal_alt
[i
]][0],
4093 GET_MODE (reg
), byte
, mode
) >= 0)))))
4097 loc
= &SUBREG_REG (*loc
);
4098 mode
= GET_MODE (*loc
);
4102 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4103 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4106 push_to_sequence (before
);
4107 lra_emit_move (new_reg
, old
);
4108 before
= get_insns ();
4113 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4116 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4118 after
= get_insns ();
4122 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4123 if (goal_alt_dont_inherit_ops
[j
] == i
)
4125 lra_set_regno_unique_value (REGNO (new_reg
));
4128 lra_update_dup (curr_id
, i
);
4130 else if (curr_static_id
->operand
[i
].type
== OP_IN
4131 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4134 /* generate reloads for input and matched outputs. */
4135 match_inputs
[0] = i
;
4136 match_inputs
[1] = -1;
4137 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4138 goal_alt
[i
], &before
, &after
,
4139 curr_static_id
->operand_alternative
4140 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4143 else if (curr_static_id
->operand
[i
].type
== OP_OUT
4144 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4146 /* Generate reloads for output and matched inputs. */
4147 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4148 &after
, curr_static_id
->operand_alternative
4149 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4150 else if (curr_static_id
->operand
[i
].type
== OP_IN
4151 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4154 /* Generate reloads for matched inputs. */
4155 match_inputs
[0] = i
;
4156 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4157 match_inputs
[j
+ 1] = k
;
4158 match_inputs
[j
+ 1] = -1;
4159 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4163 /* We must generate code in any case when function
4164 process_alt_operands decides that it is possible. */
4167 /* Memorise processed outputs so that output remaining to be processed
4168 can avoid using the same register value (see match_reload). */
4169 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4171 outputs
[n_outputs
++] = i
;
4172 outputs
[n_outputs
] = -1;
4179 lra_assert (REG_P (reg
));
4180 regno
= REGNO (reg
);
4181 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4182 if (GET_CODE (op
) == SUBREG
)
4183 op
= SUBREG_REG (op
);
4184 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4185 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4186 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4187 if (lra_dump_file
!= NULL
)
4188 fprintf (lra_dump_file
,
4189 " Making reload reg %d for reg %d optional\n",
4193 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4194 || max_regno_before
!= max_reg_num ())
4198 lra_update_operator_dups (curr_id
);
4199 /* Something changes -- process the insn. */
4200 lra_update_insn_regno_info (curr_insn
);
4202 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4206 /* Return true if INSN satisfies all constraints. In other words, no
4207 reload insns are needed. */
4209 lra_constrain_insn (rtx_insn
*insn
)
4211 int saved_new_regno_start
= new_regno_start
;
4212 int saved_new_insn_uid_start
= new_insn_uid_start
;
4216 curr_id
= lra_get_insn_recog_data (curr_insn
);
4217 curr_static_id
= curr_id
->insn_static_data
;
4218 new_insn_uid_start
= get_max_uid ();
4219 new_regno_start
= max_reg_num ();
4220 change_p
= curr_insn_transform (true);
4221 new_regno_start
= saved_new_regno_start
;
4222 new_insn_uid_start
= saved_new_insn_uid_start
;
4226 /* Return true if X is in LIST. */
4228 in_list_p (rtx x
, rtx list
)
4230 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4231 if (XEXP (list
, 0) == x
)
4236 /* Return true if X contains an allocatable hard register (if
4237 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4239 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4245 code
= GET_CODE (x
);
4248 int regno
= REGNO (x
);
4249 HARD_REG_SET alloc_regs
;
4253 if (regno
>= FIRST_PSEUDO_REGISTER
)
4254 regno
= lra_get_regno_hard_regno (regno
);
4257 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4258 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4262 if (regno
< FIRST_PSEUDO_REGISTER
)
4266 return lra_get_regno_hard_regno (regno
) < 0;
4269 fmt
= GET_RTX_FORMAT (code
);
4270 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4274 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4277 else if (fmt
[i
] == 'E')
4279 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4280 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4287 /* Process all regs in location *LOC and change them on equivalent
4288 substitution. Return true if any change was done. */
4290 loc_equivalence_change_p (rtx
*loc
)
4292 rtx subst
, reg
, x
= *loc
;
4293 bool result
= false;
4294 enum rtx_code code
= GET_CODE (x
);
4300 reg
= SUBREG_REG (x
);
4301 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4302 && GET_MODE (subst
) == VOIDmode
)
4304 /* We cannot reload debug location. Simplify subreg here
4305 while we know the inner mode. */
4306 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4307 GET_MODE (reg
), SUBREG_BYTE (x
));
4311 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4317 /* Scan all the operand sub-expressions. */
4318 fmt
= GET_RTX_FORMAT (code
);
4319 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4322 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4323 else if (fmt
[i
] == 'E')
4324 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4326 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4331 /* Similar to loc_equivalence_change_p, but for use as
4332 simplify_replace_fn_rtx callback. DATA is insn for which the
4333 elimination is done. If it null we don't do the elimination. */
4335 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4340 rtx subst
= (data
== NULL
4341 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4348 /* Maximum number of generated reload insns per an insn. It is for
4349 preventing this pass cycling in a bug case. */
4350 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4352 /* The current iteration number of this LRA pass. */
4353 int lra_constraint_iter
;
4355 /* True if we substituted equiv which needs checking register
4356 allocation correctness because the equivalent value contains
4357 allocatable hard registers or when we restore multi-register
4359 bool lra_risky_transformations_p
;
4361 /* Return true if REGNO is referenced in more than one block. */
4363 multi_block_pseudo_p (int regno
)
4365 basic_block bb
= NULL
;
4369 if (regno
< FIRST_PSEUDO_REGISTER
)
4372 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4374 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4375 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4380 /* Return true if LIST contains a deleted insn. */
4382 contains_deleted_insn_p (rtx_insn_list
*list
)
4384 for (; list
!= NULL_RTX
; list
= list
->next ())
4385 if (NOTE_P (list
->insn ())
4386 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4391 /* Return true if X contains a pseudo dying in INSN. */
4393 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4400 return (insn
!= NULL_RTX
4401 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4402 code
= GET_CODE (x
);
4403 fmt
= GET_RTX_FORMAT (code
);
4404 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4408 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4411 else if (fmt
[i
] == 'E')
4413 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4414 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4421 /* Return true if INSN contains a dying pseudo in INSN right hand
4424 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4426 rtx set
= single_set (insn
);
4428 gcc_assert (set
!= NULL
);
4429 return dead_pseudo_p (SET_SRC (set
), insn
);
4432 /* Return true if any init insn of REGNO contains a dying pseudo in
4433 insn right hand side. */
4435 init_insn_rhs_dead_pseudo_p (int regno
)
4437 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4441 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4442 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4447 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4448 reverse only if we have one init insn with given REGNO as a
4451 reverse_equiv_p (int regno
)
4453 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4458 if (! INSN_P (insns
->insn ())
4459 || insns
->next () != NULL
)
4461 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4463 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4466 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4467 call this function only for non-reverse equivalence. */
4469 contains_reloaded_insn_p (int regno
)
4472 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4474 for (; list
!= NULL
; list
= list
->next ())
4475 if ((set
= single_set (list
->insn ())) == NULL_RTX
4476 || ! REG_P (SET_DEST (set
))
4477 || (int) REGNO (SET_DEST (set
)) != regno
)
4482 /* Entry function of LRA constraint pass. Return true if the
4483 constraint pass did change the code. */
4485 lra_constraints (bool first_p
)
4488 int i
, hard_regno
, new_insns_num
;
4489 unsigned int min_len
, new_min_len
, uid
;
4490 rtx set
, x
, reg
, dest_reg
;
4491 basic_block last_bb
;
4492 bitmap_head equiv_insn_bitmap
;
4495 lra_constraint_iter
++;
4496 if (lra_dump_file
!= NULL
)
4497 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4498 lra_constraint_iter
);
4500 if (pic_offset_table_rtx
4501 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4502 lra_risky_transformations_p
= true;
4504 lra_risky_transformations_p
= false;
4505 new_insn_uid_start
= get_max_uid ();
4506 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4507 /* Mark used hard regs for target stack size calulations. */
4508 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4509 if (lra_reg_info
[i
].nrefs
!= 0
4510 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4514 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4515 for (j
= 0; j
< nregs
; j
++)
4516 df_set_regs_ever_live (hard_regno
+ j
, true);
4518 /* Do elimination before the equivalence processing as we can spill
4519 some pseudos during elimination. */
4520 lra_eliminate (false, first_p
);
4521 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4522 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4523 if (lra_reg_info
[i
].nrefs
!= 0)
4525 ira_reg_equiv
[i
].profitable_p
= true;
4526 reg
= regno_reg_rtx
[i
];
4527 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4529 bool pseudo_p
= contains_reg_p (x
, false, false);
4531 /* After RTL transformation, we can not guarantee that
4532 pseudo in the substitution was not reloaded which might
4533 make equivalence invalid. For example, in reverse
4540 the memory address register was reloaded before the 2nd
4542 if ((! first_p
&& pseudo_p
)
4543 /* We don't use DF for compilation speed sake. So it
4544 is problematic to update live info when we use an
4545 equivalence containing pseudos in more than one
4547 || (pseudo_p
&& multi_block_pseudo_p (i
))
4548 /* If an init insn was deleted for some reason, cancel
4549 the equiv. We could update the equiv insns after
4550 transformations including an equiv insn deletion
4551 but it is not worthy as such cases are extremely
4553 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4554 /* If it is not a reverse equivalence, we check that a
4555 pseudo in rhs of the init insn is not dying in the
4556 insn. Otherwise, the live info at the beginning of
4557 the corresponding BB might be wrong after we
4558 removed the insn. When the equiv can be a
4559 constant, the right hand side of the init insn can
4561 || (! reverse_equiv_p (i
)
4562 && (init_insn_rhs_dead_pseudo_p (i
)
4563 /* If we reloaded the pseudo in an equivalence
4564 init insn, we can not remove the equiv init
4565 insns and the init insns might write into
4566 const memory in this case. */
4567 || contains_reloaded_insn_p (i
)))
4568 /* Prevent access beyond equivalent memory for
4569 paradoxical subregs. */
4571 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4572 > GET_MODE_SIZE (GET_MODE (x
))))
4573 || (pic_offset_table_rtx
4574 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4575 && (targetm
.preferred_reload_class
4576 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4577 || contains_symbol_ref_p (x
))))
4578 ira_reg_equiv
[i
].defined_p
= false;
4579 if (contains_reg_p (x
, false, true))
4580 ira_reg_equiv
[i
].profitable_p
= false;
4581 if (get_equiv (reg
) != reg
)
4582 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4585 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4587 /* We should add all insns containing pseudos which should be
4588 substituted by their equivalences. */
4589 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4590 lra_push_insn_by_uid (uid
);
4591 min_len
= lra_insn_stack_length ();
4595 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4597 curr_insn
= lra_pop_insn ();
4599 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4600 if (curr_bb
!= last_bb
)
4603 bb_reload_num
= lra_curr_reload_num
;
4605 if (min_len
> new_min_len
)
4607 min_len
= new_min_len
;
4610 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4612 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4613 MAX_RELOAD_INSNS_NUMBER
);
4615 if (DEBUG_INSN_P (curr_insn
))
4617 /* We need to check equivalence in debug insn and change
4618 pseudo to the equivalent value if necessary. */
4619 curr_id
= lra_get_insn_recog_data (curr_insn
);
4620 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4622 rtx old
= *curr_id
->operand_loc
[0];
4623 *curr_id
->operand_loc
[0]
4624 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4625 loc_equivalence_callback
, curr_insn
);
4626 if (old
!= *curr_id
->operand_loc
[0])
4628 lra_update_insn_regno_info (curr_insn
);
4633 else if (INSN_P (curr_insn
))
4635 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4637 dest_reg
= SET_DEST (set
);
4638 /* The equivalence pseudo could be set up as SUBREG in a
4639 case when it is a call restore insn in a mode
4640 different from the pseudo mode. */
4641 if (GET_CODE (dest_reg
) == SUBREG
)
4642 dest_reg
= SUBREG_REG (dest_reg
);
4643 if ((REG_P (dest_reg
)
4644 && (x
= get_equiv (dest_reg
)) != dest_reg
4645 /* Remove insns which set up a pseudo whose value
4646 can not be changed. Such insns might be not in
4647 init_insns because we don't update equiv data
4648 during insn transformations.
4650 As an example, let suppose that a pseudo got
4651 hard register and on the 1st pass was not
4652 changed to equivalent constant. We generate an
4653 additional insn setting up the pseudo because of
4654 secondary memory movement. Then the pseudo is
4655 spilled and we use the equiv constant. In this
4656 case we should remove the additional insn and
4657 this insn is not init_insns list. */
4658 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4659 /* Check that this is actually an insn setting
4660 up the equivalence. */
4661 || in_list_p (curr_insn
,
4663 [REGNO (dest_reg
)].init_insns
)))
4664 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4665 && in_list_p (curr_insn
,
4667 [REGNO (SET_SRC (set
))].init_insns
)))
4669 /* This is equiv init insn of pseudo which did not get a
4670 hard register -- remove the insn. */
4671 if (lra_dump_file
!= NULL
)
4673 fprintf (lra_dump_file
,
4674 " Removing equiv init insn %i (freq=%d)\n",
4675 INSN_UID (curr_insn
),
4676 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4677 dump_insn_slim (lra_dump_file
, curr_insn
);
4679 if (contains_reg_p (x
, true, false))
4680 lra_risky_transformations_p
= true;
4681 lra_set_insn_deleted (curr_insn
);
4685 curr_id
= lra_get_insn_recog_data (curr_insn
);
4686 curr_static_id
= curr_id
->insn_static_data
;
4687 init_curr_insn_input_reloads ();
4688 init_curr_operand_mode ();
4689 if (curr_insn_transform (false))
4691 /* Check non-transformed insns too for equiv change as USE
4692 or CLOBBER don't need reloads but can contain pseudos
4693 being changed on their equivalences. */
4694 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4695 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4697 lra_update_insn_regno_info (curr_insn
);
4702 bitmap_clear (&equiv_insn_bitmap
);
4703 /* If we used a new hard regno, changed_p should be true because the
4704 hard reg is assigned to a new pseudo. */
4705 if (flag_checking
&& !changed_p
)
4707 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4708 if (lra_reg_info
[i
].nrefs
!= 0
4709 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4711 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4713 for (j
= 0; j
< nregs
; j
++)
4714 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4720 static void initiate_invariants (void);
4721 static void finish_invariants (void);
4723 /* Initiate the LRA constraint pass. It is done once per
4726 lra_constraints_init (void)
4728 initiate_invariants ();
4731 /* Finalize the LRA constraint pass. It is done once per
4734 lra_constraints_finish (void)
4736 finish_invariants ();
4741 /* Structure describes invariants for ineheritance. */
4744 /* The order number of the invariant. */
4746 /* The invariant RTX. */
4748 /* The origin insn of the invariant. */
4752 typedef struct invariant invariant_t
;
4753 typedef invariant_t
*invariant_ptr_t
;
4754 typedef const invariant_t
*const_invariant_ptr_t
;
4756 /* Pointer to the inheritance invariants. */
4757 static vec
<invariant_ptr_t
> invariants
;
4759 /* Allocation pool for the invariants. */
4760 static object_allocator
<struct invariant
> *invariants_pool
;
4762 /* Hash table for the invariants. */
4763 static htab_t invariant_table
;
4765 /* Hash function for INVARIANT. */
4767 invariant_hash (const void *invariant
)
4769 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4770 return lra_rtx_hash (inv
);
4773 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4775 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4777 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4778 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4780 return rtx_equal_p (inv1
, inv2
);
4783 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4784 invariant which is in the table. */
4785 static invariant_ptr_t
4786 insert_invariant (rtx invariant_rtx
)
4789 invariant_t invariant
;
4790 invariant_ptr_t invariant_ptr
;
4792 invariant
.invariant_rtx
= invariant_rtx
;
4793 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4794 if (*entry_ptr
== NULL
)
4796 invariant_ptr
= invariants_pool
->allocate ();
4797 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4798 invariant_ptr
->insn
= NULL
;
4799 invariants
.safe_push (invariant_ptr
);
4800 *entry_ptr
= (void *) invariant_ptr
;
4802 return (invariant_ptr_t
) *entry_ptr
;
4805 /* Initiate the invariant table. */
4807 initiate_invariants (void)
4809 invariants
.create (100);
4810 invariants_pool
= new object_allocator
<struct invariant
> ("Inheritance invariants");
4811 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
4814 /* Finish the invariant table. */
4816 finish_invariants (void)
4818 htab_delete (invariant_table
);
4819 delete invariants_pool
;
4820 invariants
.release ();
4823 /* Make the invariant table empty. */
4825 clear_invariants (void)
4827 htab_empty (invariant_table
);
4828 invariants_pool
->release ();
4829 invariants
.truncate (0);
4834 /* This page contains code to do inheritance/split
4837 /* Number of reloads passed so far in current EBB. */
4838 static int reloads_num
;
4840 /* Number of calls passed so far in current EBB. */
4841 static int calls_num
;
4843 /* Current reload pseudo check for validity of elements in
4845 static int curr_usage_insns_check
;
4847 /* Info about last usage of registers in EBB to do inheritance/split
4848 transformation. Inheritance transformation is done from a spilled
4849 pseudo and split transformations from a hard register or a pseudo
4850 assigned to a hard register. */
4853 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4854 value INSNS is valid. The insns is chain of optional debug insns
4855 and a finishing non-debug insn using the corresponding reg. The
4856 value is also used to mark the registers which are set up in the
4857 current insn. The negated insn uid is used for this. */
4859 /* Value of global reloads_num at the last insn in INSNS. */
4861 /* Value of global reloads_nums at the last insn in INSNS. */
4863 /* It can be true only for splitting. And it means that the restore
4864 insn should be put after insn given by the following member. */
4866 /* Next insns in the current EBB which use the original reg and the
4867 original reg value is not changed between the current insn and
4868 the next insns. In order words, e.g. for inheritance, if we need
4869 to use the original reg value again in the next insns we can try
4870 to use the value in a hard register from a reload insn of the
4875 /* Map: regno -> corresponding pseudo usage insns. */
4876 static struct usage_insns
*usage_insns
;
4879 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4881 usage_insns
[regno
].check
= curr_usage_insns_check
;
4882 usage_insns
[regno
].insns
= insn
;
4883 usage_insns
[regno
].reloads_num
= reloads_num
;
4884 usage_insns
[regno
].calls_num
= calls_num
;
4885 usage_insns
[regno
].after_p
= after_p
;
4888 /* The function is used to form list REGNO usages which consists of
4889 optional debug insns finished by a non-debug insn using REGNO.
4890 RELOADS_NUM is current number of reload insns processed so far. */
4892 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
4894 rtx next_usage_insns
;
4896 if (usage_insns
[regno
].check
== curr_usage_insns_check
4897 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4898 && DEBUG_INSN_P (insn
))
4900 /* Check that we did not add the debug insn yet. */
4901 if (next_usage_insns
!= insn
4902 && (GET_CODE (next_usage_insns
) != INSN_LIST
4903 || XEXP (next_usage_insns
, 0) != insn
))
4904 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4907 else if (NONDEBUG_INSN_P (insn
))
4908 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4910 usage_insns
[regno
].check
= 0;
4913 /* Return first non-debug insn in list USAGE_INSNS. */
4915 skip_usage_debug_insns (rtx usage_insns
)
4919 /* Skip debug insns. */
4920 for (insn
= usage_insns
;
4921 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4922 insn
= XEXP (insn
, 1))
4924 return safe_as_a
<rtx_insn
*> (insn
);
4927 /* Return true if we need secondary memory moves for insn in
4928 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4931 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4932 rtx usage_insns ATTRIBUTE_UNUSED
)
4934 #ifndef SECONDARY_MEMORY_NEEDED
4941 if (inher_cl
== ALL_REGS
4942 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4944 lra_assert (INSN_P (insn
));
4945 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4947 dest
= SET_DEST (set
);
4950 lra_assert (inher_cl
!= NO_REGS
);
4951 cl
= get_reg_class (REGNO (dest
));
4952 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4953 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4957 /* Registers involved in inheritance/split in the current EBB
4958 (inheritance/split pseudos and original registers). */
4959 static bitmap_head check_only_regs
;
4961 /* Reload pseudos can not be involded in invariant inheritance in the
4963 static bitmap_head invalid_invariant_regs
;
4965 /* Do inheritance transformations for insn INSN, which defines (if
4966 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4967 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4968 form as the "insns" field of usage_insns. Return true if we
4969 succeed in such transformation.
4971 The transformations look like:
4974 ... p <- i (new insn)
4976 <- ... p ... <- ... i ...
4978 ... i <- p (new insn)
4979 <- ... p ... <- ... i ...
4981 <- ... p ... <- ... i ...
4982 where p is a spilled original pseudo and i is a new inheritance pseudo.
4985 The inheritance pseudo has the smallest class of two classes CL and
4986 class of ORIGINAL REGNO. */
4988 inherit_reload_reg (bool def_p
, int original_regno
,
4989 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4991 if (optimize_function_for_size_p (cfun
))
4994 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4995 rtx original_reg
= regno_reg_rtx
[original_regno
];
4996 rtx new_reg
, usage_insn
;
4997 rtx_insn
*new_insns
;
4999 lra_assert (! usage_insns
[original_regno
].after_p
);
5000 if (lra_dump_file
!= NULL
)
5001 fprintf (lra_dump_file
,
5002 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5003 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5005 if (lra_dump_file
!= NULL
)
5007 fprintf (lra_dump_file
,
5008 " Rejecting inheritance for %d "
5009 "because of disjoint classes %s and %s\n",
5010 original_regno
, reg_class_names
[cl
],
5011 reg_class_names
[rclass
]);
5012 fprintf (lra_dump_file
,
5013 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5017 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5018 /* We don't use a subset of two classes because it can be
5019 NO_REGS. This transformation is still profitable in most
5020 cases even if the classes are not intersected as register
5021 move is probably cheaper than a memory load. */
5022 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5024 if (lra_dump_file
!= NULL
)
5025 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5026 reg_class_names
[cl
], reg_class_names
[rclass
]);
5030 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5032 /* Reject inheritance resulting in secondary memory moves.
5033 Otherwise, there is a danger in LRA cycling. Also such
5034 transformation will be unprofitable. */
5035 if (lra_dump_file
!= NULL
)
5037 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5038 rtx set
= single_set (insn
);
5040 lra_assert (set
!= NULL_RTX
);
5042 rtx dest
= SET_DEST (set
);
5044 lra_assert (REG_P (dest
));
5045 fprintf (lra_dump_file
,
5046 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5047 "as secondary mem is needed\n",
5048 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5049 original_regno
, reg_class_names
[rclass
]);
5050 fprintf (lra_dump_file
,
5051 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5055 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5056 rclass
, "inheritance");
5059 lra_emit_move (original_reg
, new_reg
);
5061 lra_emit_move (new_reg
, original_reg
);
5062 new_insns
= get_insns ();
5064 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5066 if (lra_dump_file
!= NULL
)
5068 fprintf (lra_dump_file
,
5069 " Rejecting inheritance %d->%d "
5070 "as it results in 2 or more insns:\n",
5071 original_regno
, REGNO (new_reg
));
5072 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5073 fprintf (lra_dump_file
,
5074 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5078 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5079 lra_update_insn_regno_info (insn
);
5081 /* We now have a new usage insn for original regno. */
5082 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5083 if (lra_dump_file
!= NULL
)
5084 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5085 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5086 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5087 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5088 bitmap_set_bit (&check_only_regs
, original_regno
);
5089 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5091 lra_process_new_insns (insn
, NULL
, new_insns
,
5092 "Add original<-inheritance");
5094 lra_process_new_insns (insn
, new_insns
, NULL
,
5095 "Add inheritance<-original");
5096 while (next_usage_insns
!= NULL_RTX
)
5098 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5100 usage_insn
= next_usage_insns
;
5101 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5102 next_usage_insns
= NULL
;
5106 usage_insn
= XEXP (next_usage_insns
, 0);
5107 lra_assert (DEBUG_INSN_P (usage_insn
));
5108 next_usage_insns
= XEXP (next_usage_insns
, 1);
5110 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5111 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5112 if (lra_dump_file
!= NULL
)
5114 fprintf (lra_dump_file
,
5115 " Inheritance reuse change %d->%d (bb%d):\n",
5116 original_regno
, REGNO (new_reg
),
5117 BLOCK_FOR_INSN (usage_insn
)->index
);
5118 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5121 if (lra_dump_file
!= NULL
)
5122 fprintf (lra_dump_file
,
5123 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5127 /* Return true if we need a caller save/restore for pseudo REGNO which
5128 was assigned to a hard register. */
5130 need_for_call_save_p (int regno
)
5132 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5133 return (usage_insns
[regno
].calls_num
< calls_num
5134 && (overlaps_hard_reg_set_p
5136 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5137 ? lra_reg_info
[regno
].actual_call_used_reg_set
5138 : call_used_reg_set
,
5139 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5140 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
5141 PSEUDO_REGNO_MODE (regno
))));
5144 /* Global registers occurring in the current EBB. */
5145 static bitmap_head ebb_global_regs
;
5147 /* Return true if we need a split for hard register REGNO or pseudo
5148 REGNO which was assigned to a hard register.
5149 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5150 used for reloads since the EBB end. It is an approximation of the
5151 used hard registers in the split range. The exact value would
5152 require expensive calculations. If we were aggressive with
5153 splitting because of the approximation, the split pseudo will save
5154 the same hard register assignment and will be removed in the undo
5155 pass. We still need the approximation because too aggressive
5156 splitting would result in too inaccurate cost calculation in the
5157 assignment pass because of too many generated moves which will be
5158 probably removed in the undo pass. */
5160 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5162 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5164 lra_assert (hard_regno
>= 0);
5165 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5166 /* Don't split eliminable hard registers, otherwise we can
5167 split hard registers like hard frame pointer, which
5168 lives on BB start/end according to DF-infrastructure,
5169 when there is a pseudo assigned to the register and
5170 living in the same BB. */
5171 && (regno
>= FIRST_PSEUDO_REGISTER
5172 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5173 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5174 /* Don't split call clobbered hard regs living through
5175 calls, otherwise we might have a check problem in the
5176 assign sub-pass as in the most cases (exception is a
5177 situation when lra_risky_transformations_p value is
5178 true) the assign pass assumes that all pseudos living
5179 through calls are assigned to call saved hard regs. */
5180 && (regno
>= FIRST_PSEUDO_REGISTER
5181 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5182 || usage_insns
[regno
].calls_num
== calls_num
)
5183 /* We need at least 2 reloads to make pseudo splitting
5184 profitable. We should provide hard regno splitting in
5185 any case to solve 1st insn scheduling problem when
5186 moving hard register definition up might result in
5187 impossibility to find hard register for reload pseudo of
5188 small register class. */
5189 && (usage_insns
[regno
].reloads_num
5190 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5191 && (regno
< FIRST_PSEUDO_REGISTER
5192 /* For short living pseudos, spilling + inheritance can
5193 be considered a substitution for splitting.
5194 Therefore we do not splitting for local pseudos. It
5195 decreases also aggressiveness of splitting. The
5196 minimal number of references is chosen taking into
5197 account that for 2 references splitting has no sense
5198 as we can just spill the pseudo. */
5199 || (regno
>= FIRST_PSEUDO_REGISTER
5200 && lra_reg_info
[regno
].nrefs
> 3
5201 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5202 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5205 /* Return class for the split pseudo created from original pseudo with
5206 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5207 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5208 results in no secondary memory movements. */
5209 static enum reg_class
5210 choose_split_class (enum reg_class allocno_class
,
5211 int hard_regno ATTRIBUTE_UNUSED
,
5212 machine_mode mode ATTRIBUTE_UNUSED
)
5214 #ifndef SECONDARY_MEMORY_NEEDED
5215 return allocno_class
;
5218 enum reg_class cl
, best_cl
= NO_REGS
;
5219 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5220 = REGNO_REG_CLASS (hard_regno
);
5222 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
5223 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5224 return allocno_class
;
5226 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5228 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
5229 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
5230 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5231 && (best_cl
== NO_REGS
5232 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5238 /* Do split transformations for insn INSN, which defines or uses
5239 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5240 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5241 "insns" field of usage_insns.
5243 The transformations look like:
5246 ... s <- p (new insn -- save)
5248 ... p <- s (new insn -- restore)
5249 <- ... p ... <- ... p ...
5251 <- ... p ... <- ... p ...
5252 ... s <- p (new insn -- save)
5254 ... p <- s (new insn -- restore)
5255 <- ... p ... <- ... p ...
5257 where p is an original pseudo got a hard register or a hard
5258 register and s is a new split pseudo. The save is put before INSN
5259 if BEFORE_P is true. Return true if we succeed in such
5262 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5263 rtx next_usage_insns
)
5265 enum reg_class rclass
;
5267 int hard_regno
, nregs
;
5268 rtx new_reg
, usage_insn
;
5269 rtx_insn
*restore
, *save
;
5274 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5276 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5277 hard_regno
= original_regno
;
5278 call_save_p
= false;
5280 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5281 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5282 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5283 as part of a multi-word register. In that case, or if the biggest
5284 mode was larger than a register, just use the reg_rtx. Otherwise,
5285 limit the size to that of the biggest access in the function. */
5286 if (mode
== VOIDmode
5287 || GET_MODE_SIZE (mode
) > GET_MODE_SIZE (reg_rtx_mode
))
5289 original_reg
= regno_reg_rtx
[hard_regno
];
5290 mode
= reg_rtx_mode
;
5293 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5297 mode
= PSEUDO_REGNO_MODE (original_regno
);
5298 hard_regno
= reg_renumber
[original_regno
];
5299 nregs
= hard_regno_nregs
[hard_regno
][mode
];
5300 rclass
= lra_get_allocno_class (original_regno
);
5301 original_reg
= regno_reg_rtx
[original_regno
];
5302 call_save_p
= need_for_call_save_p (original_regno
);
5304 lra_assert (hard_regno
>= 0);
5305 if (lra_dump_file
!= NULL
)
5306 fprintf (lra_dump_file
,
5307 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5311 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5312 hard_regno_nregs
[hard_regno
][mode
],
5314 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5318 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5319 if (rclass
== NO_REGS
)
5321 if (lra_dump_file
!= NULL
)
5323 fprintf (lra_dump_file
,
5324 " Rejecting split of %d(%s): "
5325 "no good reg class for %d(%s)\n",
5327 reg_class_names
[lra_get_allocno_class (original_regno
)],
5329 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5332 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5336 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5337 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5339 save
= emit_spill_move (true, new_reg
, original_reg
);
5340 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5342 if (lra_dump_file
!= NULL
)
5346 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5347 original_regno
, REGNO (new_reg
));
5348 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5349 fprintf (lra_dump_file
,
5350 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5354 restore
= emit_spill_move (false, new_reg
, original_reg
);
5355 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5357 if (lra_dump_file
!= NULL
)
5359 fprintf (lra_dump_file
,
5360 " Rejecting split %d->%d "
5361 "resulting in > 2 restore insns:\n",
5362 original_regno
, REGNO (new_reg
));
5363 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5364 fprintf (lra_dump_file
,
5365 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5369 after_p
= usage_insns
[original_regno
].after_p
;
5370 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5371 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5372 bitmap_set_bit (&check_only_regs
, original_regno
);
5373 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
5376 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5378 usage_insn
= next_usage_insns
;
5381 usage_insn
= XEXP (next_usage_insns
, 0);
5382 lra_assert (DEBUG_INSN_P (usage_insn
));
5383 next_usage_insns
= XEXP (next_usage_insns
, 1);
5384 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5385 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5386 if (lra_dump_file
!= NULL
)
5388 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5389 original_regno
, REGNO (new_reg
));
5390 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5393 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5394 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5395 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5396 after_p
? NULL
: restore
,
5397 after_p
? restore
: NULL
,
5399 ? "Add reg<-save" : "Add reg<-split");
5400 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5401 before_p
? NULL
: save
,
5403 ? "Add save<-reg" : "Add split<-reg");
5405 /* If we are trying to split multi-register. We should check
5406 conflicts on the next assignment sub-pass. IRA can allocate on
5407 sub-register levels, LRA do this on pseudos level right now and
5408 this discrepancy may create allocation conflicts after
5410 lra_risky_transformations_p
= true;
5411 if (lra_dump_file
!= NULL
)
5412 fprintf (lra_dump_file
,
5413 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5417 /* Recognize that we need a split transformation for insn INSN, which
5418 defines or uses REGNO in its insn biggest MODE (we use it only if
5419 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5420 hard registers which might be used for reloads since the EBB end.
5421 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5422 uid before starting INSN processing. Return true if we succeed in
5423 such transformation. */
5425 split_if_necessary (int regno
, machine_mode mode
,
5426 HARD_REG_SET potential_reload_hard_regs
,
5427 bool before_p
, rtx_insn
*insn
, int max_uid
)
5431 rtx next_usage_insns
;
5433 if (regno
< FIRST_PSEUDO_REGISTER
)
5434 nregs
= hard_regno_nregs
[regno
][mode
];
5435 for (i
= 0; i
< nregs
; i
++)
5436 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5437 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5438 /* To avoid processing the register twice or more. */
5439 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5440 && INSN_UID (next_usage_insns
) < max_uid
)
5441 || (GET_CODE (next_usage_insns
) == INSN_LIST
5442 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5443 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5444 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5449 /* Return TRUE if rtx X is considered as an invariant for
5452 invariant_p (const_rtx x
)
5459 code
= GET_CODE (x
);
5460 mode
= GET_MODE (x
);
5464 code
= GET_CODE (x
);
5465 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
5466 mode
= GET_MODE (x
);
5474 int i
, nregs
, regno
= REGNO (x
);
5476 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5477 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5478 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5480 nregs
= hard_regno_nregs
[regno
][mode
];
5481 for (i
= 0; i
< nregs
; i
++)
5482 if (! fixed_regs
[regno
+ i
]
5483 /* A hard register may be clobbered in the current insn
5484 but we can ignore this case because if the hard
5485 register is used it should be set somewhere after the
5487 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5490 fmt
= GET_RTX_FORMAT (code
);
5491 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5495 if (! invariant_p (XEXP (x
, i
)))
5498 else if (fmt
[i
] == 'E')
5500 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5501 if (! invariant_p (XVECEXP (x
, i
, j
)))
5508 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5509 inheritance transformation (using dest_reg instead invariant in a
5510 subsequent insn). */
5512 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5514 invariant_ptr_t invariant_ptr
;
5515 rtx_insn
*insn
, *new_insns
;
5516 rtx insn_set
, insn_reg
, new_reg
;
5518 bool succ_p
= false;
5519 int dst_regno
= REGNO (dst_reg
);
5520 enum machine_mode dst_mode
= GET_MODE (dst_reg
);
5521 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5523 invariant_ptr
= insert_invariant (invariant_rtx
);
5524 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5526 /* We have a subsequent insn using the invariant. */
5527 insn_set
= single_set (insn
);
5528 lra_assert (insn_set
!= NULL
);
5529 insn_reg
= SET_DEST (insn_set
);
5530 lra_assert (REG_P (insn_reg
));
5531 insn_regno
= REGNO (insn_reg
);
5532 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5534 if (dst_mode
== GET_MODE (insn_reg
)
5535 /* We should consider only result move reg insns which are
5537 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5538 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5540 if (lra_dump_file
!= NULL
)
5541 fprintf (lra_dump_file
,
5542 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5543 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5544 cl
, "invariant inheritance");
5545 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5546 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5547 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5549 lra_emit_move (new_reg
, dst_reg
);
5550 new_insns
= get_insns ();
5552 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5553 "Add invariant inheritance<-original");
5555 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5556 new_insns
= get_insns ();
5558 lra_process_new_insns (insn
, NULL
, new_insns
,
5559 "Changing reload<-inheritance");
5560 lra_set_insn_deleted (insn
);
5562 if (lra_dump_file
!= NULL
)
5564 fprintf (lra_dump_file
,
5565 " Invariant inheritance reuse change %d (bb%d):\n",
5566 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5567 dump_insn_slim (lra_dump_file
, insn
);
5568 fprintf (lra_dump_file
,
5569 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5573 invariant_ptr
->insn
= curr_insn
;
5577 /* Check only registers living at the current program point in the
5579 static bitmap_head live_regs
;
5581 /* Update live info in EBB given by its HEAD and TAIL insns after
5582 inheritance/split transformation. The function removes dead moves
5585 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5590 rtx_insn
*prev_insn
;
5593 basic_block last_bb
, prev_bb
, curr_bb
;
5595 struct lra_insn_reg
*reg
;
5599 last_bb
= BLOCK_FOR_INSN (tail
);
5601 for (curr_insn
= tail
;
5602 curr_insn
!= PREV_INSN (head
);
5603 curr_insn
= prev_insn
)
5605 prev_insn
= PREV_INSN (curr_insn
);
5606 /* We need to process empty blocks too. They contain
5607 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5608 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5610 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5611 if (curr_bb
!= prev_bb
)
5613 if (prev_bb
!= NULL
)
5615 /* Update df_get_live_in (prev_bb): */
5616 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5617 if (bitmap_bit_p (&live_regs
, j
))
5618 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5620 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5622 if (curr_bb
!= last_bb
)
5624 /* Update df_get_live_out (curr_bb): */
5625 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5627 live_p
= bitmap_bit_p (&live_regs
, j
);
5629 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5630 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5636 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5638 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5642 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5644 if (! NONDEBUG_INSN_P (curr_insn
))
5646 curr_id
= lra_get_insn_recog_data (curr_insn
);
5647 curr_static_id
= curr_id
->insn_static_data
;
5649 if ((set
= single_set (curr_insn
)) != NULL_RTX
5650 && REG_P (SET_DEST (set
))
5651 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5652 && SET_DEST (set
) != pic_offset_table_rtx
5653 && bitmap_bit_p (&check_only_regs
, regno
)
5654 && ! bitmap_bit_p (&live_regs
, regno
))
5656 /* See which defined values die here. */
5657 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5658 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5659 bitmap_clear_bit (&live_regs
, reg
->regno
);
5660 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5661 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5662 bitmap_clear_bit (&live_regs
, reg
->regno
);
5663 if (curr_id
->arg_hard_regs
!= NULL
)
5664 /* Make clobbered argument hard registers die. */
5665 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5666 if (regno
>= FIRST_PSEUDO_REGISTER
)
5667 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5668 /* Mark each used value as live. */
5669 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5670 if (reg
->type
!= OP_OUT
5671 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5672 bitmap_set_bit (&live_regs
, reg
->regno
);
5673 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5674 if (reg
->type
!= OP_OUT
5675 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5676 bitmap_set_bit (&live_regs
, reg
->regno
);
5677 if (curr_id
->arg_hard_regs
!= NULL
)
5678 /* Make used argument hard registers live. */
5679 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5680 if (regno
< FIRST_PSEUDO_REGISTER
5681 && bitmap_bit_p (&check_only_regs
, regno
))
5682 bitmap_set_bit (&live_regs
, regno
);
5683 /* It is quite important to remove dead move insns because it
5684 means removing dead store. We don't need to process them for
5688 if (lra_dump_file
!= NULL
)
5690 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5691 dump_insn_slim (lra_dump_file
, curr_insn
);
5693 lra_set_insn_deleted (curr_insn
);
5698 /* The structure describes info to do an inheritance for the current
5699 insn. We need to collect such info first before doing the
5700 transformations because the transformations change the insn
5701 internal representation. */
5704 /* Original regno. */
5706 /* Subsequent insns which can inherit original reg value. */
5710 /* Array containing all info for doing inheritance from the current
5712 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5714 /* Number elements in the previous array. */
5715 static int to_inherit_num
;
5717 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5718 structure to_inherit. */
5720 add_to_inherit (int regno
, rtx insns
)
5724 for (i
= 0; i
< to_inherit_num
; i
++)
5725 if (to_inherit
[i
].regno
== regno
)
5727 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5728 to_inherit
[to_inherit_num
].regno
= regno
;
5729 to_inherit
[to_inherit_num
++].insns
= insns
;
5732 /* Return the last non-debug insn in basic block BB, or the block begin
5735 get_last_insertion_point (basic_block bb
)
5739 FOR_BB_INSNS_REVERSE (bb
, insn
)
5740 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5745 /* Set up RES by registers living on edges FROM except the edge (FROM,
5746 TO) or by registers set up in a jump insn in BB FROM. */
5748 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5751 struct lra_insn_reg
*reg
;
5755 lra_assert (to
!= NULL
);
5757 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5759 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5760 last
= get_last_insertion_point (from
);
5761 if (! JUMP_P (last
))
5763 curr_id
= lra_get_insn_recog_data (last
);
5764 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5765 if (reg
->type
!= OP_IN
)
5766 bitmap_set_bit (res
, reg
->regno
);
5769 /* Used as a temporary results of some bitmap calculations. */
5770 static bitmap_head temp_bitmap
;
5772 /* We split for reloads of small class of hard regs. The following
5773 defines how many hard regs the class should have to be qualified as
5774 small. The code is mostly oriented to x86/x86-64 architecture
5775 where some insns need to use only specific register or pair of
5776 registers and these register can live in RTL explicitly, e.g. for
5777 parameter passing. */
5778 static const int max_small_class_regs_num
= 2;
5780 /* Do inheritance/split transformations in EBB starting with HEAD and
5781 finishing on TAIL. We process EBB insns in the reverse order.
5782 Return true if we did any inheritance/split transformation in the
5785 We should avoid excessive splitting which results in worse code
5786 because of inaccurate cost calculations for spilling new split
5787 pseudos in such case. To achieve this we do splitting only if
5788 register pressure is high in given basic block and there are reload
5789 pseudos requiring hard registers. We could do more register
5790 pressure calculations at any given program point to avoid necessary
5791 splitting even more but it is to expensive and the current approach
5792 works well enough. */
5794 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5796 int i
, src_regno
, dst_regno
, nregs
;
5797 bool change_p
, succ_p
, update_reloads_num_p
;
5798 rtx_insn
*prev_insn
, *last_insn
;
5799 rtx next_usage_insns
, curr_set
;
5801 struct lra_insn_reg
*reg
;
5802 basic_block last_processed_bb
, curr_bb
= NULL
;
5803 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5807 bool head_p
, after_p
;
5810 curr_usage_insns_check
++;
5811 clear_invariants ();
5812 reloads_num
= calls_num
= 0;
5813 bitmap_clear (&check_only_regs
);
5814 bitmap_clear (&invalid_invariant_regs
);
5815 last_processed_bb
= NULL
;
5816 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5817 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5818 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5819 /* We don't process new insns generated in the loop. */
5820 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5822 prev_insn
= PREV_INSN (curr_insn
);
5823 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5824 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5825 if (last_processed_bb
!= curr_bb
)
5827 /* We are at the end of BB. Add qualified living
5828 pseudos for potential splitting. */
5829 to_process
= df_get_live_out (curr_bb
);
5830 if (last_processed_bb
!= NULL
)
5832 /* We are somewhere in the middle of EBB. */
5833 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5835 to_process
= &temp_bitmap
;
5837 last_processed_bb
= curr_bb
;
5838 last_insn
= get_last_insertion_point (curr_bb
);
5839 after_p
= (! JUMP_P (last_insn
)
5840 && (! CALL_P (last_insn
)
5841 || (find_reg_note (last_insn
,
5842 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5843 && ! SIBLING_CALL_P (last_insn
))));
5844 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5845 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5847 if ((int) j
>= lra_constraint_new_regno_start
)
5849 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5851 if (j
< FIRST_PSEUDO_REGISTER
)
5852 SET_HARD_REG_BIT (live_hard_regs
, j
);
5854 add_to_hard_reg_set (&live_hard_regs
,
5855 PSEUDO_REGNO_MODE (j
),
5857 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5861 src_regno
= dst_regno
= -1;
5862 curr_set
= single_set (curr_insn
);
5863 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
5864 dst_regno
= REGNO (SET_DEST (curr_set
));
5865 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
5866 src_regno
= REGNO (SET_SRC (curr_set
));
5867 update_reloads_num_p
= true;
5868 if (src_regno
< lra_constraint_new_regno_start
5869 && src_regno
>= FIRST_PSEUDO_REGISTER
5870 && reg_renumber
[src_regno
] < 0
5871 && dst_regno
>= lra_constraint_new_regno_start
5872 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5874 /* 'reload_pseudo <- original_pseudo'. */
5875 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5877 update_reloads_num_p
= false;
5879 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5880 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5881 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5882 curr_insn
, next_usage_insns
);
5886 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5887 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5888 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5889 reg_class_contents
[cl
]);
5891 else if (src_regno
< 0
5892 && dst_regno
>= lra_constraint_new_regno_start
5893 && invariant_p (SET_SRC (curr_set
))
5894 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
5895 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
5896 && ! bitmap_bit_p (&invalid_invariant_regs
,
5897 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
5899 /* 'reload_pseudo <- invariant'. */
5900 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5902 update_reloads_num_p
= false;
5903 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
5905 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5906 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5907 reg_class_contents
[cl
]);
5909 else if (src_regno
>= lra_constraint_new_regno_start
5910 && dst_regno
< lra_constraint_new_regno_start
5911 && dst_regno
>= FIRST_PSEUDO_REGISTER
5912 && reg_renumber
[dst_regno
] < 0
5913 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5914 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5915 && (next_usage_insns
5916 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5918 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5920 update_reloads_num_p
= false;
5921 /* 'original_pseudo <- reload_pseudo'. */
5922 if (! JUMP_P (curr_insn
)
5923 && inherit_reload_reg (true, dst_regno
, cl
,
5924 curr_insn
, next_usage_insns
))
5927 usage_insns
[dst_regno
].check
= 0;
5928 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5929 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5930 reg_class_contents
[cl
]);
5932 else if (INSN_P (curr_insn
))
5935 int max_uid
= get_max_uid ();
5937 curr_id
= lra_get_insn_recog_data (curr_insn
);
5938 curr_static_id
= curr_id
->insn_static_data
;
5940 /* Process insn definitions. */
5941 for (iter
= 0; iter
< 2; iter
++)
5942 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5945 if (reg
->type
!= OP_IN
5946 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5948 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5949 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5950 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5951 && (next_usage_insns
5952 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5954 struct lra_insn_reg
*r
;
5956 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5957 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5959 /* Don't do inheritance if the pseudo is also
5960 used in the insn. */
5962 /* We can not do inheritance right now
5963 because the current insn reg info (chain
5964 regs) can change after that. */
5965 add_to_inherit (dst_regno
, next_usage_insns
);
5967 /* We can not process one reg twice here because of
5968 usage_insns invalidation. */
5969 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5970 || reg_renumber
[dst_regno
] >= 0)
5971 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5975 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5976 potential_reload_hard_regs
,
5977 false, curr_insn
, max_uid
))
5979 CLEAR_HARD_REG_SET (s
);
5980 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5981 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5983 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5984 reg_renumber
[dst_regno
]);
5985 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5987 /* We should invalidate potential inheritance or
5988 splitting for the current insn usages to the next
5989 usage insns (see code below) as the output pseudo
5991 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5992 && reg_renumber
[dst_regno
] < 0)
5993 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5994 && (dst_regno
< FIRST_PSEUDO_REGISTER
5995 || reg_renumber
[dst_regno
] >= 0)))
5997 /* Invalidate and mark definitions. */
5998 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5999 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6002 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
6003 for (i
= 0; i
< nregs
; i
++)
6004 usage_insns
[dst_regno
+ i
].check
6005 = -(int) INSN_UID (curr_insn
);
6009 /* Process clobbered call regs. */
6010 if (curr_id
->arg_hard_regs
!= NULL
)
6011 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6012 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6013 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6014 = -(int) INSN_UID (curr_insn
);
6015 if (! JUMP_P (curr_insn
))
6016 for (i
= 0; i
< to_inherit_num
; i
++)
6017 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6018 ALL_REGS
, curr_insn
,
6019 to_inherit
[i
].insns
))
6021 if (CALL_P (curr_insn
))
6023 rtx cheap
, pat
, dest
;
6025 int regno
, hard_regno
;
6028 if ((cheap
= find_reg_note (curr_insn
,
6029 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6030 && ((cheap
= XEXP (cheap
, 0)), true)
6031 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6032 && (hard_regno
= reg_renumber
[regno
]) >= 0
6033 /* If there are pending saves/restores, the
6034 optimization is not worth. */
6035 && usage_insns
[regno
].calls_num
== calls_num
- 1
6036 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6038 /* Restore the pseudo from the call result as
6039 REG_RETURNED note says that the pseudo value is
6040 in the call result and the pseudo is an argument
6042 pat
= PATTERN (curr_insn
);
6043 if (GET_CODE (pat
) == PARALLEL
)
6044 pat
= XVECEXP (pat
, 0, 0);
6045 dest
= SET_DEST (pat
);
6046 /* For multiple return values dest is PARALLEL.
6047 Currently we handle only single return value case. */
6051 emit_move_insn (cheap
, copy_rtx (dest
));
6052 restore
= get_insns ();
6054 lra_process_new_insns (curr_insn
, NULL
, restore
,
6055 "Inserting call parameter restore");
6056 /* We don't need to save/restore of the pseudo from
6058 usage_insns
[regno
].calls_num
= calls_num
;
6059 bitmap_set_bit (&check_only_regs
, regno
);
6064 /* Process insn usages. */
6065 for (iter
= 0; iter
< 2; iter
++)
6066 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6069 if ((reg
->type
!= OP_OUT
6070 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6071 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6073 if (src_regno
>= FIRST_PSEUDO_REGISTER
6074 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6076 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6077 && (next_usage_insns
6078 = usage_insns
[src_regno
].insns
) != NULL_RTX
6079 && NONDEBUG_INSN_P (curr_insn
))
6080 add_to_inherit (src_regno
, next_usage_insns
);
6081 else if (usage_insns
[src_regno
].check
6082 != -(int) INSN_UID (curr_insn
))
6083 /* Add usages but only if the reg is not set up
6084 in the same insn. */
6085 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6087 else if (src_regno
< FIRST_PSEUDO_REGISTER
6088 || reg_renumber
[src_regno
] >= 0)
6091 rtx_insn
*use_insn
= curr_insn
;
6093 before_p
= (JUMP_P (curr_insn
)
6094 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6095 if (NONDEBUG_INSN_P (curr_insn
)
6096 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6097 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6098 potential_reload_hard_regs
,
6099 before_p
, curr_insn
, max_uid
))
6102 lra_risky_transformations_p
= true;
6105 usage_insns
[src_regno
].check
= 0;
6107 use_insn
= PREV_INSN (curr_insn
);
6109 if (NONDEBUG_INSN_P (curr_insn
))
6111 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6112 add_to_hard_reg_set (&live_hard_regs
,
6113 reg
->biggest_mode
, src_regno
);
6115 add_to_hard_reg_set (&live_hard_regs
,
6116 PSEUDO_REGNO_MODE (src_regno
),
6117 reg_renumber
[src_regno
]);
6119 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6122 /* Process used call regs. */
6123 if (curr_id
->arg_hard_regs
!= NULL
)
6124 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6125 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6127 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6128 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6130 for (i
= 0; i
< to_inherit_num
; i
++)
6132 src_regno
= to_inherit
[i
].regno
;
6133 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6134 curr_insn
, to_inherit
[i
].insns
))
6137 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6140 if (update_reloads_num_p
6141 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6144 if ((REG_P (SET_DEST (curr_set
))
6145 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6146 && reg_renumber
[regno
] < 0
6147 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6148 || (REG_P (SET_SRC (curr_set
))
6149 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6150 && reg_renumber
[regno
] < 0
6151 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6153 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6155 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6156 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6157 reg_class_contents
[cl
]);
6160 if (NONDEBUG_INSN_P (curr_insn
))
6164 /* Invalidate invariants with changed regs. */
6165 curr_id
= lra_get_insn_recog_data (curr_insn
);
6166 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6167 if (reg
->type
!= OP_IN
)
6169 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6170 bitmap_set_bit (&invalid_invariant_regs
,
6171 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6173 curr_static_id
= curr_id
->insn_static_data
;
6174 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6175 if (reg
->type
!= OP_IN
)
6176 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6177 if (curr_id
->arg_hard_regs
!= NULL
)
6178 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6179 if (regno
>= FIRST_PSEUDO_REGISTER
)
6180 bitmap_set_bit (&invalid_invariant_regs
,
6181 regno
- FIRST_PSEUDO_REGISTER
);
6183 /* We reached the start of the current basic block. */
6184 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6185 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6187 /* We reached the beginning of the current block -- do
6188 rest of spliting in the current BB. */
6189 to_process
= df_get_live_in (curr_bb
);
6190 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6192 /* We are somewhere in the middle of EBB. */
6193 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6194 curr_bb
, &temp_bitmap
);
6195 to_process
= &temp_bitmap
;
6198 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6200 if ((int) j
>= lra_constraint_new_regno_start
)
6202 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6203 && usage_insns
[j
].check
== curr_usage_insns_check
6204 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6206 if (need_for_split_p (potential_reload_hard_regs
, j
))
6208 if (lra_dump_file
!= NULL
&& head_p
)
6210 fprintf (lra_dump_file
,
6211 " ----------------------------------\n");
6214 if (split_reg (false, j
, bb_note (curr_bb
),
6218 usage_insns
[j
].check
= 0;
6226 /* This value affects EBB forming. If probability of edge from EBB to
6227 a BB is not greater than the following value, we don't add the BB
6229 #define EBB_PROBABILITY_CUTOFF \
6230 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6232 /* Current number of inheritance/split iteration. */
6233 int lra_inheritance_iter
;
6235 /* Entry function for inheritance/split pass. */
6237 lra_inheritance (void)
6240 basic_block bb
, start_bb
;
6243 lra_inheritance_iter
++;
6244 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6246 timevar_push (TV_LRA_INHERITANCE
);
6247 if (lra_dump_file
!= NULL
)
6248 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6249 lra_inheritance_iter
);
6250 curr_usage_insns_check
= 0;
6251 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6252 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6253 usage_insns
[i
].check
= 0;
6254 bitmap_initialize (&check_only_regs
, ®_obstack
);
6255 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6256 bitmap_initialize (&live_regs
, ®_obstack
);
6257 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6258 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6259 FOR_EACH_BB_FN (bb
, cfun
)
6262 if (lra_dump_file
!= NULL
)
6263 fprintf (lra_dump_file
, "EBB");
6264 /* Form a EBB starting with BB. */
6265 bitmap_clear (&ebb_global_regs
);
6266 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6269 if (lra_dump_file
!= NULL
)
6270 fprintf (lra_dump_file
, " %d", bb
->index
);
6271 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6272 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6274 e
= find_fallthru_edge (bb
->succs
);
6277 if (e
->probability
< EBB_PROBABILITY_CUTOFF
)
6281 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6282 if (lra_dump_file
!= NULL
)
6283 fprintf (lra_dump_file
, "\n");
6284 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6285 /* Remember that the EBB head and tail can change in
6287 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6289 bitmap_clear (&ebb_global_regs
);
6290 bitmap_clear (&temp_bitmap
);
6291 bitmap_clear (&live_regs
);
6292 bitmap_clear (&invalid_invariant_regs
);
6293 bitmap_clear (&check_only_regs
);
6296 timevar_pop (TV_LRA_INHERITANCE
);
6301 /* This page contains code to undo failed inheritance/split
6304 /* Current number of iteration undoing inheritance/split. */
6305 int lra_undo_inheritance_iter
;
6307 /* Fix BB live info LIVE after removing pseudos created on pass doing
6308 inheritance/split which are REMOVED_PSEUDOS. */
6310 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6315 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6316 if (bitmap_clear_bit (live
, regno
)
6317 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6318 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6321 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6326 if (GET_CODE (reg
) == SUBREG
)
6327 reg
= SUBREG_REG (reg
);
6333 /* Delete a move INSN with destination reg DREGNO and a previous
6334 clobber insn with the same regno. The inheritance/split code can
6335 generate moves with preceding clobber and when we delete such moves
6336 we should delete the clobber insn too to keep the correct life
6339 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6341 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6343 lra_set_insn_deleted (insn
);
6344 lra_assert (dregno
>= 0);
6345 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6346 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6347 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6348 lra_set_insn_deleted (prev_insn
);
6351 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6352 return true if we did any change. The undo transformations for
6353 inheritance looks like
6357 p <- i, i <- p, and i <- i3
6358 where p is original pseudo from which inheritance pseudo i was
6359 created, i and i3 are removed inheritance pseudos, i2 is another
6360 not removed inheritance pseudo. All split pseudos or other
6361 occurrences of removed inheritance pseudos are changed on the
6362 corresponding original pseudos.
6364 The function also schedules insns changed and created during
6365 inheritance/split pass for processing by the subsequent constraint
6368 remove_inheritance_pseudos (bitmap remove_pseudos
)
6371 int regno
, sregno
, prev_sregno
, dregno
;
6374 rtx_insn
*prev_insn
;
6375 bool change_p
, done_p
;
6377 change_p
= ! bitmap_empty_p (remove_pseudos
);
6378 /* We can not finish the function right away if CHANGE_P is true
6379 because we need to marks insns affected by previous
6380 inheritance/split pass for processing by the subsequent
6382 FOR_EACH_BB_FN (bb
, cfun
)
6384 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6385 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6386 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6388 if (! INSN_P (curr_insn
))
6391 sregno
= dregno
= -1;
6392 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6393 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6395 dregno
= get_regno (SET_DEST (set
));
6396 sregno
= get_regno (SET_SRC (set
));
6399 if (sregno
>= 0 && dregno
>= 0)
6401 if (bitmap_bit_p (remove_pseudos
, dregno
)
6402 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6404 /* invariant inheritance pseudo <- original pseudo */
6405 if (lra_dump_file
!= NULL
)
6407 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6408 dump_insn_slim (lra_dump_file
, curr_insn
);
6409 fprintf (lra_dump_file
, "\n");
6411 delete_move_and_clobber (curr_insn
, dregno
);
6414 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6415 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6417 /* reload pseudo <- invariant inheritance pseudo */
6419 /* We can not just change the source. It might be
6420 an insn different from the move. */
6421 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6422 rtx_insn
*new_insns
= get_insns ();
6424 lra_assert (single_set (new_insns
) != NULL
6425 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6426 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6427 "Changing reload<-invariant inheritance");
6428 delete_move_and_clobber (curr_insn
, dregno
);
6431 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6432 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6433 || (bitmap_bit_p (remove_pseudos
, dregno
)
6434 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6435 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6436 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6437 || (bitmap_bit_p (remove_pseudos
, dregno
)
6438 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6439 /* One of the following cases:
6440 original <- removed inheritance pseudo
6441 removed inherit pseudo <- another removed inherit pseudo
6442 removed inherit pseudo <- original pseudo
6444 removed_split_pseudo <- original_reg
6445 original_reg <- removed_split_pseudo */
6447 if (lra_dump_file
!= NULL
)
6449 fprintf (lra_dump_file
, " Removing %s:\n",
6450 bitmap_bit_p (&lra_split_regs
, sregno
)
6451 || bitmap_bit_p (&lra_split_regs
, dregno
)
6452 ? "split" : "inheritance");
6453 dump_insn_slim (lra_dump_file
, curr_insn
);
6455 delete_move_and_clobber (curr_insn
, dregno
);
6458 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6459 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6461 /* Search the following pattern:
6462 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6463 original_pseudo <- inherit_or_split_pseudo1
6464 where the 2nd insn is the current insn and
6465 inherit_or_split_pseudo2 is not removed. If it is found,
6466 change the current insn onto:
6467 original_pseudo <- inherit_or_split_pseudo2. */
6468 for (prev_insn
= PREV_INSN (curr_insn
);
6469 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6470 prev_insn
= PREV_INSN (prev_insn
))
6472 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6473 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6474 /* There should be no subregs in insn we are
6475 searching because only the original reg might
6476 be in subreg when we changed the mode of
6477 load/store for splitting. */
6478 && REG_P (SET_DEST (prev_set
))
6479 && REG_P (SET_SRC (prev_set
))
6480 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6481 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6482 >= FIRST_PSEUDO_REGISTER
)
6483 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6485 /* As we consider chain of inheritance or
6486 splitting described in above comment we should
6487 check that sregno and prev_sregno were
6488 inheritance/split pseudos created from the
6489 same original regno. */
6490 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6491 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6492 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6493 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6495 lra_assert (GET_MODE (SET_SRC (prev_set
))
6496 == GET_MODE (regno_reg_rtx
[sregno
]));
6497 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6498 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6500 SET_SRC (set
) = SET_SRC (prev_set
);
6501 /* As we are finishing with processing the insn
6502 here, check the destination too as it might
6503 inheritance pseudo for another pseudo. */
6504 if (bitmap_bit_p (remove_pseudos
, dregno
)
6505 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6507 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6509 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6510 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6512 SET_DEST (set
) = restore_rtx
;
6514 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6515 lra_set_used_insn_alternative_by_uid
6516 (INSN_UID (curr_insn
), -1);
6518 if (lra_dump_file
!= NULL
)
6520 fprintf (lra_dump_file
, " Change reload insn:\n");
6521 dump_insn_slim (lra_dump_file
, curr_insn
);
6528 struct lra_insn_reg
*reg
;
6529 bool restored_regs_p
= false;
6530 bool kept_regs_p
= false;
6532 curr_id
= lra_get_insn_recog_data (curr_insn
);
6533 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6536 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6537 if (restore_rtx
!= NULL_RTX
)
6539 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6541 lra_substitute_pseudo_within_insn
6542 (curr_insn
, regno
, restore_rtx
, false);
6543 restored_regs_p
= true;
6549 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6551 /* The instruction has changed since the previous
6552 constraints pass. */
6553 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6554 lra_set_used_insn_alternative_by_uid
6555 (INSN_UID (curr_insn
), -1);
6557 else if (restored_regs_p
)
6558 /* The instruction has been restored to the form that
6559 it had during the previous constraints pass. */
6560 lra_update_insn_regno_info (curr_insn
);
6561 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6563 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6564 dump_insn_slim (lra_dump_file
, curr_insn
);
6572 /* If optional reload pseudos failed to get a hard register or was not
6573 inherited, it is better to remove optional reloads. We do this
6574 transformation after undoing inheritance to figure out necessity to
6575 remove optional reloads easier. Return true if we do any
6578 undo_optional_reloads (void)
6580 bool change_p
, keep_p
;
6581 unsigned int regno
, uid
;
6582 bitmap_iterator bi
, bi2
;
6585 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
6587 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
6588 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6589 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6592 /* Keep optional reloads from previous subpasses. */
6593 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6594 /* If the original pseudo changed its allocation, just
6595 removing the optional pseudo is dangerous as the original
6596 pseudo will have longer live range. */
6597 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6599 else if (reg_renumber
[regno
] >= 0)
6600 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6602 insn
= lra_insn_recog_data
[uid
]->insn
;
6603 if ((set
= single_set (insn
)) == NULL_RTX
)
6605 src
= SET_SRC (set
);
6606 dest
= SET_DEST (set
);
6607 if (! REG_P (src
) || ! REG_P (dest
))
6609 if (REGNO (dest
) == regno
6610 /* Ignore insn for optional reloads itself. */
6611 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6612 /* Check only inheritance on last inheritance pass. */
6613 && (int) REGNO (src
) >= new_regno_start
6614 /* Check that the optional reload was inherited. */
6615 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6623 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
6624 if (lra_dump_file
!= NULL
)
6625 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6628 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
6629 bitmap_initialize (&insn_bitmap
, ®_obstack
);
6630 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
6632 if (lra_dump_file
!= NULL
)
6633 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6634 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6635 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
6637 insn
= lra_insn_recog_data
[uid
]->insn
;
6638 if ((set
= single_set (insn
)) != NULL_RTX
)
6640 src
= SET_SRC (set
);
6641 dest
= SET_DEST (set
);
6642 if (REG_P (src
) && REG_P (dest
)
6643 && ((REGNO (src
) == regno
6644 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6646 || (REGNO (dest
) == regno
6647 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6650 if (lra_dump_file
!= NULL
)
6652 fprintf (lra_dump_file
, " Deleting move %u\n",
6654 dump_insn_slim (lra_dump_file
, insn
);
6656 delete_move_and_clobber (insn
, REGNO (dest
));
6659 /* We should not worry about generation memory-memory
6660 moves here as if the corresponding inheritance did
6661 not work (inheritance pseudo did not get a hard reg),
6662 we remove the inheritance pseudo and the optional
6665 lra_substitute_pseudo_within_insn
6666 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6667 lra_update_insn_regno_info (insn
);
6668 if (lra_dump_file
!= NULL
)
6670 fprintf (lra_dump_file
,
6671 " Restoring original insn:\n");
6672 dump_insn_slim (lra_dump_file
, insn
);
6676 /* Clear restore_regnos. */
6677 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6678 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6679 bitmap_clear (&insn_bitmap
);
6680 bitmap_clear (&removed_optional_reload_pseudos
);
6684 /* Entry function for undoing inheritance/split transformation. Return true
6685 if we did any RTL change in this pass. */
6687 lra_undo_inheritance (void)
6691 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6693 bitmap_head remove_pseudos
;
6697 lra_undo_inheritance_iter
++;
6698 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6700 if (lra_dump_file
!= NULL
)
6701 fprintf (lra_dump_file
,
6702 "\n********** Undoing inheritance #%d: **********\n\n",
6703 lra_undo_inheritance_iter
);
6704 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6705 n_inherit
= n_all_inherit
= 0;
6706 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6707 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6710 if (reg_renumber
[regno
] < 0
6711 /* If the original pseudo changed its allocation, just
6712 removing inheritance is dangerous as for changing
6713 allocation we used shorter live-ranges. */
6714 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6715 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6716 bitmap_set_bit (&remove_pseudos
, regno
);
6720 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6721 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6722 n_inherit
, n_all_inherit
,
6723 (double) n_inherit
/ n_all_inherit
* 100);
6724 n_split
= n_all_split
= 0;
6725 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6726 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6728 int restore_regno
= REGNO (restore_rtx
);
6731 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6732 ? reg_renumber
[restore_regno
] : restore_regno
);
6733 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6734 bitmap_set_bit (&remove_pseudos
, regno
);
6738 if (lra_dump_file
!= NULL
)
6739 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6740 regno
, restore_regno
);
6743 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6744 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6745 n_split
, n_all_split
,
6746 (double) n_split
/ n_all_split
* 100);
6747 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6748 bitmap_clear (&remove_pseudos
);
6749 /* Clear restore_regnos. */
6750 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6751 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6752 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6753 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6754 change_p
= undo_optional_reloads () || change_p
;