2015-09-21 Steven G. Kargl <kargl@gcc.gnu.org>
[official-gcc.git] / gcc / config / frv / frv.c
blob15de223bae3e2c03c2d9bd1320ca6bcb5799e9d8
1 /* Copyright (C) 1997-2015 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "cfghooks.h"
25 #include "tree.h"
26 #include "rtl.h"
27 #include "df.h"
28 #include "alias.h"
29 #include "fold-const.h"
30 #include "varasm.h"
31 #include "stor-layout.h"
32 #include "stringpool.h"
33 #include "regs.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "output.h"
38 #include "insn-attr.h"
39 #include "flags.h"
40 #include "recog.h"
41 #include "reload.h"
42 #include "expmed.h"
43 #include "dojump.h"
44 #include "explow.h"
45 #include "calls.h"
46 #include "emit-rtl.h"
47 #include "stmt.h"
48 #include "expr.h"
49 #include "except.h"
50 #include "insn-codes.h"
51 #include "optabs.h"
52 #include "diagnostic-core.h"
53 #include "cfgrtl.h"
54 #include "cfganal.h"
55 #include "lcm.h"
56 #include "cfgbuild.h"
57 #include "cfgcleanup.h"
58 #include "tm_p.h"
59 #include "target.h"
60 #include "targhooks.h"
61 #include "langhooks.h"
62 #include "dumpfile.h"
63 #include "builtins.h"
64 #include "ifcvt.h"
65 #include "rtl-iter.h"
67 /* This file should be included last. */
68 #include "target-def.h"
70 #ifndef FRV_INLINE
71 #define FRV_INLINE inline
72 #endif
74 /* The maximum number of distinct NOP patterns. There are three:
75 nop, fnop and mnop. */
76 #define NUM_NOP_PATTERNS 3
78 /* Classification of instructions and units: integer, floating-point/media,
79 branch and control. */
80 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
82 /* The DFA names of the units, in packet order. */
83 static const char *const frv_unit_names[] =
85 "c",
86 "i0", "f0",
87 "i1", "f1",
88 "i2", "f2",
89 "i3", "f3",
90 "b0", "b1"
93 /* The classification of each unit in frv_unit_names[]. */
94 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
96 GROUP_C,
97 GROUP_I, GROUP_FM,
98 GROUP_I, GROUP_FM,
99 GROUP_I, GROUP_FM,
100 GROUP_I, GROUP_FM,
101 GROUP_B, GROUP_B
104 /* Return the DFA unit code associated with the Nth unit of integer
105 or floating-point group GROUP, */
106 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
108 /* Return the number of integer or floating-point unit UNIT
109 (1 for I1, 2 for F2, etc.). */
110 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
112 /* The DFA unit number for each unit in frv_unit_names[]. */
113 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
115 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
116 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
117 no instruction of type T has been seen. */
118 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
120 /* An array of dummy nop INSNs, one for each type of nop that the
121 target supports. */
122 static GTY(()) rtx_insn *frv_nops[NUM_NOP_PATTERNS];
124 /* The number of nop instructions in frv_nops[]. */
125 static unsigned int frv_num_nops;
127 /* The type of access. FRV_IO_UNKNOWN means the access can be either
128 a read or a write. */
129 enum frv_io_type { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE };
131 /* Information about one __builtin_read or __builtin_write access, or
132 the combination of several such accesses. The most general value
133 is all-zeros (an unknown access to an unknown address). */
134 struct frv_io {
135 enum frv_io_type type;
137 /* The constant address being accessed, or zero if not known. */
138 HOST_WIDE_INT const_address;
140 /* The run-time address, as used in operand 0 of the membar pattern. */
141 rtx var_address;
144 /* Return true if instruction INSN should be packed with the following
145 instruction. */
146 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
148 /* Set the value of PACKING_FLAG_P(INSN). */
149 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
150 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
152 /* Loop with REG set to each hard register in rtx X. */
153 #define FOR_EACH_REGNO(REG, X) \
154 for (REG = REGNO (X); \
155 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
156 REG++)
158 /* This structure contains machine specific function data. */
159 struct GTY(()) machine_function
161 /* True if we have created an rtx that relies on the stack frame. */
162 int frame_needed;
164 /* True if this function contains at least one __builtin_{read,write}*. */
165 bool has_membar_p;
168 /* Temporary register allocation support structure. */
169 typedef struct frv_tmp_reg_struct
171 HARD_REG_SET regs; /* possible registers to allocate */
172 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
174 frv_tmp_reg_t;
176 /* Register state information for VLIW re-packing phase. */
177 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
178 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
179 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
180 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
182 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
184 typedef unsigned char regstate_t;
186 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
187 memory move. */
188 enum frv_stack_op
190 FRV_LOAD,
191 FRV_STORE
194 /* Information required by frv_frame_access. */
195 typedef struct
197 /* This field is FRV_LOAD if registers are to be loaded from the stack and
198 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
199 the move is being done by the prologue code while FRV_LOAD implies it
200 is being done by the epilogue. */
201 enum frv_stack_op op;
203 /* The base register to use when accessing the stack. This may be the
204 frame pointer, stack pointer, or a temporary. The choice of register
205 depends on which part of the frame is being accessed and how big the
206 frame is. */
207 rtx base;
209 /* The offset of BASE from the bottom of the current frame, in bytes. */
210 int base_offset;
211 } frv_frame_accessor_t;
213 /* Conditional execution support gathered together in one structure. */
214 typedef struct
216 /* Linked list of insns to add if the conditional execution conversion was
217 successful. Each link points to an EXPR_LIST which points to the pattern
218 of the insn to add, and the insn to be inserted before. */
219 rtx added_insns_list;
221 /* Identify which registers are safe to allocate for if conversions to
222 conditional execution. We keep the last allocated register in the
223 register classes between COND_EXEC statements. This will mean we allocate
224 different registers for each different COND_EXEC group if we can. This
225 might allow the scheduler to intermix two different COND_EXEC sections. */
226 frv_tmp_reg_t tmp_reg;
228 /* For nested IFs, identify which CC registers are used outside of setting
229 via a compare isnsn, and using via a check insn. This will allow us to
230 know if we can rewrite the register to use a different register that will
231 be paired with the CR register controlling the nested IF-THEN blocks. */
232 HARD_REG_SET nested_cc_ok_rewrite;
234 /* Temporary registers allocated to hold constants during conditional
235 execution. */
236 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
238 /* Current number of temp registers available. */
239 int cur_scratch_regs;
241 /* Number of nested conditional execution blocks. */
242 int num_nested_cond_exec;
244 /* Map of insns that set up constants in scratch registers. */
245 bitmap scratch_insns_bitmap;
247 /* Conditional execution test register (CC0..CC7). */
248 rtx cr_reg;
250 /* Conditional execution compare register that is paired with cr_reg, so that
251 nested compares can be done. The csubcc and caddcc instructions don't
252 have enough bits to specify both a CC register to be set and a CR register
253 to do the test on, so the same bit number is used for both. Needless to
254 say, this is rather inconvenient for GCC. */
255 rtx nested_cc_reg;
257 /* Extra CR registers used for &&, ||. */
258 rtx extra_int_cr;
259 rtx extra_fp_cr;
261 /* Previous CR used in nested if, to make sure we are dealing with the same
262 nested if as the previous statement. */
263 rtx last_nested_if_cr;
265 frv_ifcvt_t;
267 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
269 /* Map register number to smallest register class. */
270 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
272 /* Cached value of frv_stack_info. */
273 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
275 /* Forward references */
277 static void frv_option_override (void);
278 static bool frv_legitimate_address_p (machine_mode, rtx, bool);
279 static int frv_default_flags_for_cpu (void);
280 static int frv_string_begins_with (const char *, const char *);
281 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
282 static void frv_print_operand (FILE *, rtx, int);
283 static void frv_print_operand_address (FILE *, rtx);
284 static bool frv_print_operand_punct_valid_p (unsigned char code);
285 static void frv_print_operand_memory_reference_reg
286 (FILE *, rtx);
287 static void frv_print_operand_memory_reference (FILE *, rtx, int);
288 static int frv_print_operand_jump_hint (rtx_insn *);
289 static const char *comparison_string (enum rtx_code, rtx);
290 static rtx frv_function_value (const_tree, const_tree,
291 bool);
292 static rtx frv_libcall_value (machine_mode,
293 const_rtx);
294 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
295 static rtx single_set_pattern (rtx);
296 static int frv_function_contains_far_jump (void);
297 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
298 enum reg_class,
299 machine_mode,
300 int, int);
301 static rtx frv_frame_offset_rtx (int);
302 static rtx frv_frame_mem (machine_mode, rtx, int);
303 static rtx frv_dwarf_store (rtx, int);
304 static void frv_frame_insn (rtx, rtx);
305 static void frv_frame_access (frv_frame_accessor_t*,
306 rtx, int);
307 static void frv_frame_access_multi (frv_frame_accessor_t*,
308 frv_stack_t *, int);
309 static void frv_frame_access_standard_regs (enum frv_stack_op,
310 frv_stack_t *);
311 static struct machine_function *frv_init_machine_status (void);
312 static rtx frv_int_to_acc (enum insn_code, int, rtx);
313 static machine_mode frv_matching_accg_mode (machine_mode);
314 static rtx frv_read_argument (tree, unsigned int);
315 static rtx frv_read_iacc_argument (machine_mode, tree, unsigned int);
316 static int frv_check_constant_argument (enum insn_code, int, rtx);
317 static rtx frv_legitimize_target (enum insn_code, rtx);
318 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
319 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
320 static rtx frv_legitimize_address (rtx, rtx, machine_mode);
321 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
322 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
323 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
324 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
325 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
326 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
327 static rtx frv_expand_int_void2arg (enum insn_code, tree);
328 static rtx frv_expand_prefetches (enum insn_code, tree);
329 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
330 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
331 static rtx frv_expand_mclracc_builtin (tree);
332 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
333 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
334 static rtx frv_expand_noargs_builtin (enum insn_code);
335 static void frv_split_iacc_move (rtx, rtx);
336 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
337 static void frv_ifcvt_add_insn (rtx, rtx, int);
338 static rtx frv_ifcvt_rewrite_mem (rtx, machine_mode, rtx);
339 static rtx frv_ifcvt_load_value (rtx, rtx);
340 static unsigned int frv_insn_unit (rtx_insn *);
341 static bool frv_issues_to_branch_unit_p (rtx_insn *);
342 static int frv_cond_flags (rtx);
343 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
344 static bool frv_registers_conflict_p (rtx);
345 static void frv_registers_update_1 (rtx, const_rtx, void *);
346 static void frv_registers_update (rtx);
347 static void frv_start_packet (void);
348 static void frv_start_packet_block (void);
349 static void frv_finish_packet (void (*) (void));
350 static bool frv_pack_insn_p (rtx_insn *);
351 static void frv_add_insn_to_packet (rtx_insn *);
352 static void frv_insert_nop_in_packet (rtx_insn *);
353 static bool frv_for_each_packet (void (*) (void));
354 static bool frv_sort_insn_group_1 (enum frv_insn_group,
355 unsigned int, unsigned int,
356 unsigned int, unsigned int,
357 state_t);
358 static int frv_compare_insns (const void *, const void *);
359 static void frv_sort_insn_group (enum frv_insn_group);
360 static void frv_reorder_packet (void);
361 static void frv_fill_unused_units (enum frv_insn_group);
362 static void frv_align_label (void);
363 static void frv_reorg_packet (void);
364 static void frv_register_nop (rtx);
365 static void frv_reorg (void);
366 static void frv_pack_insns (void);
367 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
368 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
369 static bool frv_assemble_integer (rtx, unsigned, int);
370 static void frv_init_builtins (void);
371 static rtx frv_expand_builtin (tree, rtx, rtx, machine_mode, int);
372 static void frv_init_libfuncs (void);
373 static bool frv_in_small_data_p (const_tree);
374 static void frv_asm_output_mi_thunk
375 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
376 static void frv_setup_incoming_varargs (cumulative_args_t,
377 machine_mode,
378 tree, int *, int);
379 static rtx frv_expand_builtin_saveregs (void);
380 static void frv_expand_builtin_va_start (tree, rtx);
381 static bool frv_rtx_costs (rtx, machine_mode, int, int,
382 int*, bool);
383 static int frv_register_move_cost (machine_mode,
384 reg_class_t, reg_class_t);
385 static int frv_memory_move_cost (machine_mode,
386 reg_class_t, bool);
387 static void frv_asm_out_constructor (rtx, int);
388 static void frv_asm_out_destructor (rtx, int);
389 static bool frv_function_symbol_referenced_p (rtx);
390 static bool frv_legitimate_constant_p (machine_mode, rtx);
391 static bool frv_cannot_force_const_mem (machine_mode, rtx);
392 static const char *unspec_got_name (int);
393 static void frv_output_const_unspec (FILE *,
394 const struct frv_unspec *);
395 static bool frv_function_ok_for_sibcall (tree, tree);
396 static rtx frv_struct_value_rtx (tree, int);
397 static bool frv_must_pass_in_stack (machine_mode mode, const_tree type);
398 static int frv_arg_partial_bytes (cumulative_args_t, machine_mode,
399 tree, bool);
400 static rtx frv_function_arg (cumulative_args_t, machine_mode,
401 const_tree, bool);
402 static rtx frv_function_incoming_arg (cumulative_args_t, machine_mode,
403 const_tree, bool);
404 static void frv_function_arg_advance (cumulative_args_t, machine_mode,
405 const_tree, bool);
406 static unsigned int frv_function_arg_boundary (machine_mode,
407 const_tree);
408 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
409 ATTRIBUTE_UNUSED;
410 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
411 machine_mode,
412 secondary_reload_info *);
413 static bool frv_frame_pointer_required (void);
414 static bool frv_can_eliminate (const int, const int);
415 static void frv_conditional_register_usage (void);
416 static void frv_trampoline_init (rtx, tree, rtx);
417 static bool frv_class_likely_spilled_p (reg_class_t);
419 /* Initialize the GCC target structure. */
420 #undef TARGET_PRINT_OPERAND
421 #define TARGET_PRINT_OPERAND frv_print_operand
422 #undef TARGET_PRINT_OPERAND_ADDRESS
423 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
424 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
425 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
426 #undef TARGET_ASM_FUNCTION_PROLOGUE
427 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
428 #undef TARGET_ASM_FUNCTION_EPILOGUE
429 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
430 #undef TARGET_ASM_INTEGER
431 #define TARGET_ASM_INTEGER frv_assemble_integer
432 #undef TARGET_OPTION_OVERRIDE
433 #define TARGET_OPTION_OVERRIDE frv_option_override
434 #undef TARGET_INIT_BUILTINS
435 #define TARGET_INIT_BUILTINS frv_init_builtins
436 #undef TARGET_EXPAND_BUILTIN
437 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
438 #undef TARGET_INIT_LIBFUNCS
439 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
440 #undef TARGET_IN_SMALL_DATA_P
441 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
442 #undef TARGET_REGISTER_MOVE_COST
443 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
444 #undef TARGET_MEMORY_MOVE_COST
445 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
446 #undef TARGET_RTX_COSTS
447 #define TARGET_RTX_COSTS frv_rtx_costs
448 #undef TARGET_ASM_CONSTRUCTOR
449 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
450 #undef TARGET_ASM_DESTRUCTOR
451 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
453 #undef TARGET_ASM_OUTPUT_MI_THUNK
454 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
455 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
456 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
458 #undef TARGET_SCHED_ISSUE_RATE
459 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
461 #undef TARGET_LEGITIMIZE_ADDRESS
462 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
464 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
465 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
466 #undef TARGET_LEGITIMATE_CONSTANT_P
467 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
468 #undef TARGET_CANNOT_FORCE_CONST_MEM
469 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
471 #undef TARGET_HAVE_TLS
472 #define TARGET_HAVE_TLS HAVE_AS_TLS
474 #undef TARGET_STRUCT_VALUE_RTX
475 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
476 #undef TARGET_MUST_PASS_IN_STACK
477 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
478 #undef TARGET_PASS_BY_REFERENCE
479 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
480 #undef TARGET_ARG_PARTIAL_BYTES
481 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
482 #undef TARGET_FUNCTION_ARG
483 #define TARGET_FUNCTION_ARG frv_function_arg
484 #undef TARGET_FUNCTION_INCOMING_ARG
485 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
486 #undef TARGET_FUNCTION_ARG_ADVANCE
487 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
488 #undef TARGET_FUNCTION_ARG_BOUNDARY
489 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
491 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
492 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
493 #undef TARGET_SETUP_INCOMING_VARARGS
494 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
495 #undef TARGET_MACHINE_DEPENDENT_REORG
496 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
498 #undef TARGET_EXPAND_BUILTIN_VA_START
499 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
501 #if HAVE_AS_TLS
502 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
503 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
504 #endif
506 #undef TARGET_CLASS_LIKELY_SPILLED_P
507 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
509 #undef TARGET_SECONDARY_RELOAD
510 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
512 #undef TARGET_LEGITIMATE_ADDRESS_P
513 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
515 #undef TARGET_FRAME_POINTER_REQUIRED
516 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
518 #undef TARGET_CAN_ELIMINATE
519 #define TARGET_CAN_ELIMINATE frv_can_eliminate
521 #undef TARGET_CONDITIONAL_REGISTER_USAGE
522 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
524 #undef TARGET_TRAMPOLINE_INIT
525 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
527 #undef TARGET_FUNCTION_VALUE
528 #define TARGET_FUNCTION_VALUE frv_function_value
529 #undef TARGET_LIBCALL_VALUE
530 #define TARGET_LIBCALL_VALUE frv_libcall_value
532 struct gcc_target targetm = TARGET_INITIALIZER;
534 #define FRV_SYMBOL_REF_TLS_P(RTX) \
535 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
538 /* Any function call that satisfies the machine-independent
539 requirements is eligible on FR-V. */
541 static bool
542 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
543 tree exp ATTRIBUTE_UNUSED)
545 return true;
548 /* Return true if SYMBOL is a small data symbol and relocation RELOC
549 can be used to access it directly in a load or store. */
551 static FRV_INLINE bool
552 frv_small_data_reloc_p (rtx symbol, int reloc)
554 return (GET_CODE (symbol) == SYMBOL_REF
555 && SYMBOL_REF_SMALL_P (symbol)
556 && (!TARGET_FDPIC || flag_pic == 1)
557 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
560 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
561 appropriately. */
563 bool
564 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
566 if (GET_CODE (x) == CONST)
568 unspec->offset = 0;
569 x = XEXP (x, 0);
570 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
572 unspec->offset += INTVAL (XEXP (x, 1));
573 x = XEXP (x, 0);
575 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
577 unspec->symbol = XVECEXP (x, 0, 0);
578 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
580 if (unspec->offset == 0)
581 return true;
583 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
584 && unspec->offset > 0
585 && unspec->offset < g_switch_value)
586 return true;
589 return false;
592 /* Decide whether we can force certain constants to memory. If we
593 decide we can't, the caller should be able to cope with it in
594 another way.
596 We never allow constants to be forced into memory for TARGET_FDPIC.
597 This is necessary for several reasons:
599 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
600 target-independent code will try to force them into the constant
601 pool, thus leading to infinite recursion.
603 2. We can never introduce new constant pool references during reload.
604 Any such reference would require use of the pseudo FDPIC register.
606 3. We can't represent a constant added to a function pointer (which is
607 not the same as a pointer to a function+constant).
609 4. In many cases, it's more efficient to calculate the constant in-line. */
611 static bool
612 frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED,
613 rtx x ATTRIBUTE_UNUSED)
615 return TARGET_FDPIC;
618 static int
619 frv_default_flags_for_cpu (void)
621 switch (frv_cpu_type)
623 case FRV_CPU_GENERIC:
624 return MASK_DEFAULT_FRV;
626 case FRV_CPU_FR550:
627 return MASK_DEFAULT_FR550;
629 case FRV_CPU_FR500:
630 case FRV_CPU_TOMCAT:
631 return MASK_DEFAULT_FR500;
633 case FRV_CPU_FR450:
634 return MASK_DEFAULT_FR450;
636 case FRV_CPU_FR405:
637 case FRV_CPU_FR400:
638 return MASK_DEFAULT_FR400;
640 case FRV_CPU_FR300:
641 case FRV_CPU_SIMPLE:
642 return MASK_DEFAULT_SIMPLE;
644 default:
645 gcc_unreachable ();
649 /* Implement TARGET_OPTION_OVERRIDE. */
651 static void
652 frv_option_override (void)
654 int regno;
655 unsigned int i;
657 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
659 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
660 linker about linking pic and non-pic code. */
661 if (TARGET_LIBPIC)
663 if (!flag_pic) /* -fPIC */
664 flag_pic = 2;
666 if (!global_options_set.x_g_switch_value) /* -G0 */
668 g_switch_value = 0;
672 /* A C expression whose value is a register class containing hard
673 register REGNO. In general there is more than one such class;
674 choose a class which is "minimal", meaning that no smaller class
675 also contains the register. */
677 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
679 enum reg_class rclass;
681 if (GPR_P (regno))
683 int gpr_reg = regno - GPR_FIRST;
685 if (gpr_reg == GR8_REG)
686 rclass = GR8_REGS;
688 else if (gpr_reg == GR9_REG)
689 rclass = GR9_REGS;
691 else if (gpr_reg == GR14_REG)
692 rclass = FDPIC_FPTR_REGS;
694 else if (gpr_reg == FDPIC_REGNO)
695 rclass = FDPIC_REGS;
697 else if ((gpr_reg & 3) == 0)
698 rclass = QUAD_REGS;
700 else if ((gpr_reg & 1) == 0)
701 rclass = EVEN_REGS;
703 else
704 rclass = GPR_REGS;
707 else if (FPR_P (regno))
709 int fpr_reg = regno - GPR_FIRST;
710 if ((fpr_reg & 3) == 0)
711 rclass = QUAD_FPR_REGS;
713 else if ((fpr_reg & 1) == 0)
714 rclass = FEVEN_REGS;
716 else
717 rclass = FPR_REGS;
720 else if (regno == LR_REGNO)
721 rclass = LR_REG;
723 else if (regno == LCR_REGNO)
724 rclass = LCR_REG;
726 else if (ICC_P (regno))
727 rclass = ICC_REGS;
729 else if (FCC_P (regno))
730 rclass = FCC_REGS;
732 else if (ICR_P (regno))
733 rclass = ICR_REGS;
735 else if (FCR_P (regno))
736 rclass = FCR_REGS;
738 else if (ACC_P (regno))
740 int r = regno - ACC_FIRST;
741 if ((r & 3) == 0)
742 rclass = QUAD_ACC_REGS;
743 else if ((r & 1) == 0)
744 rclass = EVEN_ACC_REGS;
745 else
746 rclass = ACC_REGS;
749 else if (ACCG_P (regno))
750 rclass = ACCG_REGS;
752 else
753 rclass = NO_REGS;
755 regno_reg_class[regno] = rclass;
758 /* Check for small data option */
759 if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC)
760 g_switch_value = SDATA_DEFAULT_SIZE;
762 /* There is no single unaligned SI op for PIC code. Sometimes we
763 need to use ".4byte" and sometimes we need to use ".picptr".
764 See frv_assemble_integer for details. */
765 if (flag_pic || TARGET_FDPIC)
766 targetm.asm_out.unaligned_op.si = 0;
768 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
769 target_flags |= MASK_LINKED_FP;
771 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
772 target_flags |= MASK_OPTIMIZE_MEMBAR;
774 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
775 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
777 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
778 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
780 init_machine_status = frv_init_machine_status;
784 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
786 static int
787 frv_string_begins_with (const char *name, const char *prefix)
789 const int prefix_len = strlen (prefix);
791 /* Remember: NAME's length includes the null terminator. */
792 return (strncmp (name, prefix, prefix_len) == 0);
795 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
797 static void
798 frv_conditional_register_usage (void)
800 int i;
802 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
803 fixed_regs[i] = call_used_regs[i] = 1;
805 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
806 fixed_regs[i] = call_used_regs[i] = 1;
808 /* Reserve the registers used for conditional execution. At present, we need
809 1 ICC and 1 ICR register. */
810 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
811 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
813 if (TARGET_FIXED_CC)
815 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
816 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
817 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
818 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
821 if (TARGET_FDPIC)
822 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
823 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
825 #if 0
826 /* If -fpic, SDA_BASE_REG is the PIC register. */
827 if (g_switch_value == 0 && !flag_pic)
828 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
830 if (!flag_pic)
831 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
832 #endif
837 * Compute the stack frame layout
839 * Register setup:
840 * +---------------+-----------------------+-----------------------+
841 * |Register |type |caller-save/callee-save|
842 * +---------------+-----------------------+-----------------------+
843 * |GR0 |Zero register | - |
844 * |GR1 |Stack pointer(SP) | - |
845 * |GR2 |Frame pointer(FP) | - |
846 * |GR3 |Hidden parameter | caller save |
847 * |GR4-GR7 | - | caller save |
848 * |GR8-GR13 |Argument register | caller save |
849 * |GR14-GR15 | - | caller save |
850 * |GR16-GR31 | - | callee save |
851 * |GR32-GR47 | - | caller save |
852 * |GR48-GR63 | - | callee save |
853 * |FR0-FR15 | - | caller save |
854 * |FR16-FR31 | - | callee save |
855 * |FR32-FR47 | - | caller save |
856 * |FR48-FR63 | - | callee save |
857 * +---------------+-----------------------+-----------------------+
859 * Stack frame setup:
860 * Low
861 * SP-> |-----------------------------------|
862 * | Argument area |
863 * |-----------------------------------|
864 * | Register save area |
865 * |-----------------------------------|
866 * | Local variable save area |
867 * FP-> |-----------------------------------|
868 * | Old FP |
869 * |-----------------------------------|
870 * | Hidden parameter save area |
871 * |-----------------------------------|
872 * | Return address(LR) storage area |
873 * |-----------------------------------|
874 * | Padding for alignment |
875 * |-----------------------------------|
876 * | Register argument area |
877 * OLD SP-> |-----------------------------------|
878 * | Parameter area |
879 * |-----------------------------------|
880 * High
882 * Argument area/Parameter area:
884 * When a function is called, this area is used for argument transfer. When
885 * the argument is set up by the caller function, this area is referred to as
886 * the argument area. When the argument is referenced by the callee function,
887 * this area is referred to as the parameter area. The area is allocated when
888 * all arguments cannot be placed on the argument register at the time of
889 * argument transfer.
891 * Register save area:
893 * This is a register save area that must be guaranteed for the caller
894 * function. This area is not secured when the register save operation is not
895 * needed.
897 * Local variable save area:
899 * This is the area for local variables and temporary variables.
901 * Old FP:
903 * This area stores the FP value of the caller function.
905 * Hidden parameter save area:
907 * This area stores the start address of the return value storage
908 * area for a struct/union return function.
909 * When a struct/union is used as the return value, the caller
910 * function stores the return value storage area start address in
911 * register GR3 and passes it to the caller function.
912 * The callee function interprets the address stored in the GR3
913 * as the return value storage area start address.
914 * When register GR3 needs to be saved into memory, the callee
915 * function saves it in the hidden parameter save area. This
916 * area is not secured when the save operation is not needed.
918 * Return address(LR) storage area:
920 * This area saves the LR. The LR stores the address of a return to the caller
921 * function for the purpose of function calling.
923 * Argument register area:
925 * This area saves the argument register. This area is not secured when the
926 * save operation is not needed.
928 * Argument:
930 * Arguments, the count of which equals the count of argument registers (6
931 * words), are positioned in registers GR8 to GR13 and delivered to the callee
932 * function. When a struct/union return function is called, the return value
933 * area address is stored in register GR3. Arguments not placed in the
934 * argument registers will be stored in the stack argument area for transfer
935 * purposes. When an 8-byte type argument is to be delivered using registers,
936 * it is divided into two and placed in two registers for transfer. When
937 * argument registers must be saved to memory, the callee function secures an
938 * argument register save area in the stack. In this case, a continuous
939 * argument register save area must be established in the parameter area. The
940 * argument register save area must be allocated as needed to cover the size of
941 * the argument register to be saved. If the function has a variable count of
942 * arguments, it saves all argument registers in the argument register save
943 * area.
945 * Argument Extension Format:
947 * When an argument is to be stored in the stack, its type is converted to an
948 * extended type in accordance with the individual argument type. The argument
949 * is freed by the caller function after the return from the callee function is
950 * made.
952 * +-----------------------+---------------+------------------------+
953 * | Argument Type |Extended Type |Stack Storage Size(byte)|
954 * +-----------------------+---------------+------------------------+
955 * |char |int | 4 |
956 * |signed char |int | 4 |
957 * |unsigned char |int | 4 |
958 * |[signed] short int |int | 4 |
959 * |unsigned short int |int | 4 |
960 * |[signed] int |No extension | 4 |
961 * |unsigned int |No extension | 4 |
962 * |[signed] long int |No extension | 4 |
963 * |unsigned long int |No extension | 4 |
964 * |[signed] long long int |No extension | 8 |
965 * |unsigned long long int |No extension | 8 |
966 * |float |double | 8 |
967 * |double |No extension | 8 |
968 * |long double |No extension | 8 |
969 * |pointer |No extension | 4 |
970 * |struct/union |- | 4 (*1) |
971 * +-----------------------+---------------+------------------------+
973 * When a struct/union is to be delivered as an argument, the caller copies it
974 * to the local variable area and delivers the address of that area.
976 * Return Value:
978 * +-------------------------------+----------------------+
979 * |Return Value Type |Return Value Interface|
980 * +-------------------------------+----------------------+
981 * |void |None |
982 * |[signed|unsigned] char |GR8 |
983 * |[signed|unsigned] short int |GR8 |
984 * |[signed|unsigned] int |GR8 |
985 * |[signed|unsigned] long int |GR8 |
986 * |pointer |GR8 |
987 * |[signed|unsigned] long long int|GR8 & GR9 |
988 * |float |GR8 |
989 * |double |GR8 & GR9 |
990 * |long double |GR8 & GR9 |
991 * |struct/union |(*1) |
992 * +-------------------------------+----------------------+
994 * When a struct/union is used as the return value, the caller function stores
995 * the start address of the return value storage area into GR3 and then passes
996 * it to the callee function. The callee function interprets GR3 as the start
997 * address of the return value storage area. When this address needs to be
998 * saved in memory, the callee function secures the hidden parameter save area
999 * and saves the address in that area.
1002 frv_stack_t *
1003 frv_stack_info (void)
1005 static frv_stack_t info, zero_info;
1006 frv_stack_t *info_ptr = &info;
1007 tree fndecl = current_function_decl;
1008 int varargs_p = 0;
1009 tree cur_arg;
1010 tree next_arg;
1011 int range;
1012 int alignment;
1013 int offset;
1015 /* If we've already calculated the values and reload is complete,
1016 just return now. */
1017 if (frv_stack_cache)
1018 return frv_stack_cache;
1020 /* Zero all fields. */
1021 info = zero_info;
1023 /* Set up the register range information. */
1024 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1025 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1026 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1027 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1029 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1030 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1031 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1032 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1034 info_ptr->regs[STACK_REGS_LR].name = "lr";
1035 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1036 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1037 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1039 info_ptr->regs[STACK_REGS_CC].name = "cc";
1040 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1041 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1042 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1044 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1045 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1046 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1048 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1049 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1050 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1051 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1052 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1054 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1055 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1056 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1057 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1059 info_ptr->regs[STACK_REGS_FP].name = "fp";
1060 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1061 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1062 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1064 /* Determine if this is a stdarg function. If so, allocate space to store
1065 the 6 arguments. */
1066 if (cfun->stdarg)
1067 varargs_p = 1;
1069 else
1071 /* Find the last argument, and see if it is __builtin_va_alist. */
1072 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1074 next_arg = DECL_CHAIN (cur_arg);
1075 if (next_arg == (tree)0)
1077 if (DECL_NAME (cur_arg)
1078 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1079 varargs_p = 1;
1081 break;
1086 /* Iterate over all of the register ranges. */
1087 for (range = 0; range < STACK_REGS_MAX; range++)
1089 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1090 int first = reg_ptr->first;
1091 int last = reg_ptr->last;
1092 int size_1word = 0;
1093 int size_2words = 0;
1094 int regno;
1096 /* Calculate which registers need to be saved & save area size. */
1097 switch (range)
1099 default:
1100 for (regno = first; regno <= last; regno++)
1102 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1103 || (crtl->calls_eh_return
1104 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1105 || (!TARGET_FDPIC && flag_pic
1106 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1108 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1109 size_1word += UNITS_PER_WORD;
1112 break;
1114 /* Calculate whether we need to create a frame after everything else
1115 has been processed. */
1116 case STACK_REGS_FP:
1117 break;
1119 case STACK_REGS_LR:
1120 if (df_regs_ever_live_p (LR_REGNO)
1121 || profile_flag
1122 /* This is set for __builtin_return_address, etc. */
1123 || cfun->machine->frame_needed
1124 || (TARGET_LINKED_FP && frame_pointer_needed)
1125 || (!TARGET_FDPIC && flag_pic
1126 && crtl->uses_pic_offset_table))
1128 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1129 size_1word += UNITS_PER_WORD;
1131 break;
1133 case STACK_REGS_STDARG:
1134 if (varargs_p)
1136 /* If this is a stdarg function with a non varardic
1137 argument split between registers and the stack,
1138 adjust the saved registers downward. */
1139 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1140 / UNITS_PER_WORD);
1142 for (regno = first; regno <= last; regno++)
1144 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1145 size_1word += UNITS_PER_WORD;
1148 info_ptr->stdarg_size = size_1word;
1150 break;
1152 case STACK_REGS_STRUCT:
1153 if (cfun->returns_struct)
1155 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1156 size_1word += UNITS_PER_WORD;
1158 break;
1162 if (size_1word)
1164 /* If this is a field, it only takes one word. */
1165 if (reg_ptr->field_p)
1166 size_1word = UNITS_PER_WORD;
1168 /* Determine which register pairs can be saved together. */
1169 else if (reg_ptr->dword_p && TARGET_DWORD)
1171 for (regno = first; regno < last; regno += 2)
1173 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1175 size_2words += 2 * UNITS_PER_WORD;
1176 size_1word -= 2 * UNITS_PER_WORD;
1177 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1178 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1183 reg_ptr->size_1word = size_1word;
1184 reg_ptr->size_2words = size_2words;
1186 if (! reg_ptr->special_p)
1188 info_ptr->regs_size_1word += size_1word;
1189 info_ptr->regs_size_2words += size_2words;
1194 /* Set up the sizes of each field in the frame body, making the sizes
1195 of each be divisible by the size of a dword if dword operations might
1196 be used, or the size of a word otherwise. */
1197 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1199 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1200 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1201 + info_ptr->regs_size_1word,
1202 alignment);
1203 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1205 info_ptr->pretend_size = crtl->args.pretend_args_size;
1207 /* Work out the size of the frame, excluding the header. Both the frame
1208 body and register parameter area will be dword-aligned. */
1209 info_ptr->total_size
1210 = (ADDR_ALIGN (info_ptr->parameter_size
1211 + info_ptr->regs_size
1212 + info_ptr->vars_size,
1213 2 * UNITS_PER_WORD)
1214 + ADDR_ALIGN (info_ptr->pretend_size
1215 + info_ptr->stdarg_size,
1216 2 * UNITS_PER_WORD));
1218 /* See if we need to create a frame at all, if so add header area. */
1219 if (info_ptr->total_size > 0
1220 || frame_pointer_needed
1221 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1222 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1224 offset = info_ptr->parameter_size;
1225 info_ptr->header_size = 4 * UNITS_PER_WORD;
1226 info_ptr->total_size += 4 * UNITS_PER_WORD;
1228 /* Calculate the offsets to save normal register pairs. */
1229 for (range = 0; range < STACK_REGS_MAX; range++)
1231 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1232 if (! reg_ptr->special_p)
1234 int first = reg_ptr->first;
1235 int last = reg_ptr->last;
1236 int regno;
1238 for (regno = first; regno <= last; regno++)
1239 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1240 && regno != FRAME_POINTER_REGNUM
1241 && (regno < FIRST_ARG_REGNUM
1242 || regno > LAST_ARG_REGNUM))
1244 info_ptr->reg_offset[regno] = offset;
1245 offset += 2 * UNITS_PER_WORD;
1250 /* Calculate the offsets to save normal single registers. */
1251 for (range = 0; range < STACK_REGS_MAX; range++)
1253 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1254 if (! reg_ptr->special_p)
1256 int first = reg_ptr->first;
1257 int last = reg_ptr->last;
1258 int regno;
1260 for (regno = first; regno <= last; regno++)
1261 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1262 && regno != FRAME_POINTER_REGNUM
1263 && (regno < FIRST_ARG_REGNUM
1264 || regno > LAST_ARG_REGNUM))
1266 info_ptr->reg_offset[regno] = offset;
1267 offset += UNITS_PER_WORD;
1272 /* Calculate the offset to save the local variables at. */
1273 offset = ADDR_ALIGN (offset, alignment);
1274 if (info_ptr->vars_size)
1276 info_ptr->vars_offset = offset;
1277 offset += info_ptr->vars_size;
1280 /* Align header to a dword-boundary. */
1281 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1283 /* Calculate the offsets in the fixed frame. */
1284 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1285 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1286 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1288 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1289 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1290 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1292 if (cfun->returns_struct)
1294 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1295 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1296 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1299 /* Calculate the offsets to store the arguments passed in registers
1300 for stdarg functions. The register pairs are first and the single
1301 register if any is last. The register save area starts on a
1302 dword-boundary. */
1303 if (info_ptr->stdarg_size)
1305 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1306 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1307 int regno;
1309 /* Skip the header. */
1310 offset += 4 * UNITS_PER_WORD;
1311 for (regno = first; regno <= last; regno++)
1313 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1315 info_ptr->reg_offset[regno] = offset;
1316 offset += 2 * UNITS_PER_WORD;
1318 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1320 info_ptr->reg_offset[regno] = offset;
1321 offset += UNITS_PER_WORD;
1327 if (reload_completed)
1328 frv_stack_cache = info_ptr;
1330 return info_ptr;
1334 /* Print the information about the frv stack offsets, etc. when debugging. */
1336 void
1337 frv_debug_stack (frv_stack_t *info)
1339 int range;
1341 if (!info)
1342 info = frv_stack_info ();
1344 fprintf (stderr, "\nStack information for function %s:\n",
1345 ((current_function_decl && DECL_NAME (current_function_decl))
1346 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1347 : "<unknown>"));
1349 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1350 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1351 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1352 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1353 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1355 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1356 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1357 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1358 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1360 for (range = 0; range < STACK_REGS_MAX; range++)
1362 frv_stack_regs_t *regs = &(info->regs[range]);
1363 if ((regs->size_1word + regs->size_2words) > 0)
1365 int first = regs->first;
1366 int last = regs->last;
1367 int regno;
1369 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1370 regs->name, regs->size_1word + regs->size_2words,
1371 regs->size_1word, regs->size_2words);
1373 for (regno = first; regno <= last; regno++)
1375 if (info->save_p[regno] == REG_SAVE_1WORD)
1376 fprintf (stderr, " %s (%d)", reg_names[regno],
1377 info->reg_offset[regno]);
1379 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1380 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1381 reg_names[regno+1], info->reg_offset[regno]);
1384 fputc ('\n', stderr);
1388 fflush (stderr);
1394 /* Used during final to control the packing of insns. The value is
1395 1 if the current instruction should be packed with the next one,
1396 0 if it shouldn't or -1 if packing is disabled altogether. */
1398 static int frv_insn_packing_flag;
1400 /* True if the current function contains a far jump. */
1402 static int
1403 frv_function_contains_far_jump (void)
1405 rtx_insn *insn = get_insns ();
1406 while (insn != NULL
1407 && !(JUMP_P (insn)
1408 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1409 insn = NEXT_INSN (insn);
1410 return (insn != NULL);
1413 /* For the FRV, this function makes sure that a function with far jumps
1414 will return correctly. It also does the VLIW packing. */
1416 static void
1417 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1419 rtx_insn *insn, *next, *last_call;
1421 /* If no frame was created, check whether the function uses a call
1422 instruction to implement a far jump. If so, save the link in gr3 and
1423 replace all returns to LR with returns to GR3. GR3 is used because it
1424 is call-clobbered, because is not available to the register allocator,
1425 and because all functions that take a hidden argument pointer will have
1426 a stack frame. */
1427 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1429 rtx_insn *insn;
1431 /* Just to check that the above comment is true. */
1432 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1434 /* Generate the instruction that saves the link register. */
1435 fprintf (file, "\tmovsg lr,gr3\n");
1437 /* Replace the LR with GR3 in *return_internal patterns. The insn
1438 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1439 simply emit a different assembly directive because bralr and jmpl
1440 execute in different units. */
1441 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1442 if (JUMP_P (insn))
1444 rtx pattern = PATTERN (insn);
1445 if (GET_CODE (pattern) == PARALLEL
1446 && XVECLEN (pattern, 0) >= 2
1447 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1448 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1450 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1451 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1452 SET_REGNO (address, GPR_FIRST + 3);
1457 frv_pack_insns ();
1459 /* Allow the garbage collector to free the nops created by frv_reorg. */
1460 memset (frv_nops, 0, sizeof (frv_nops));
1462 /* Locate CALL_ARG_LOCATION notes that have been misplaced
1463 and move them back to where they should be located. */
1464 last_call = NULL;
1465 for (insn = get_insns (); insn; insn = next)
1467 next = NEXT_INSN (insn);
1468 if (CALL_P (insn)
1469 || (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE
1470 && CALL_P (XVECEXP (PATTERN (insn), 0, 0))))
1471 last_call = insn;
1473 if (!NOTE_P (insn) || NOTE_KIND (insn) != NOTE_INSN_CALL_ARG_LOCATION)
1474 continue;
1476 if (NEXT_INSN (last_call) == insn)
1477 continue;
1479 SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1480 SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1481 SET_PREV_INSN (insn) = last_call;
1482 SET_NEXT_INSN (insn) = NEXT_INSN (last_call);
1483 SET_PREV_INSN (NEXT_INSN (insn)) = insn;
1484 SET_NEXT_INSN (PREV_INSN (insn)) = insn;
1485 last_call = insn;
1490 /* Return the next available temporary register in a given class. */
1492 static rtx
1493 frv_alloc_temp_reg (
1494 frv_tmp_reg_t *info, /* which registers are available */
1495 enum reg_class rclass, /* register class desired */
1496 machine_mode mode, /* mode to allocate register with */
1497 int mark_as_used, /* register not available after allocation */
1498 int no_abort) /* return NULL instead of aborting */
1500 int regno = info->next_reg[ (int)rclass ];
1501 int orig_regno = regno;
1502 HARD_REG_SET *reg_in_class = &reg_class_contents[ (int)rclass ];
1503 int i, nr;
1505 for (;;)
1507 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1508 && TEST_HARD_REG_BIT (info->regs, regno))
1509 break;
1511 if (++regno >= FIRST_PSEUDO_REGISTER)
1512 regno = 0;
1513 if (regno == orig_regno)
1515 gcc_assert (no_abort);
1516 return NULL_RTX;
1520 nr = HARD_REGNO_NREGS (regno, mode);
1521 info->next_reg[ (int)rclass ] = regno + nr;
1523 if (mark_as_used)
1524 for (i = 0; i < nr; i++)
1525 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1527 return gen_rtx_REG (mode, regno);
1531 /* Return an rtx with the value OFFSET, which will either be a register or a
1532 signed 12-bit integer. It can be used as the second operand in an "add"
1533 instruction, or as the index in a load or store.
1535 The function returns a constant rtx if OFFSET is small enough, otherwise
1536 it loads the constant into register OFFSET_REGNO and returns that. */
1537 static rtx
1538 frv_frame_offset_rtx (int offset)
1540 rtx offset_rtx = GEN_INT (offset);
1541 if (IN_RANGE (offset, -2048, 2047))
1542 return offset_rtx;
1543 else
1545 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1546 if (IN_RANGE (offset, -32768, 32767))
1547 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1548 else
1550 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1551 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1553 return reg_rtx;
1557 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1558 prologue and epilogue uses such expressions to access the stack. */
1559 static rtx
1560 frv_frame_mem (machine_mode mode, rtx base, int offset)
1562 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1563 base,
1564 frv_frame_offset_rtx (offset)));
1567 /* Generate a frame-related expression:
1569 (set REG (mem (plus (sp) (const_int OFFSET)))).
1571 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1572 instructions. Marking the expressions as frame-related is superfluous if
1573 the note contains just a single set. But if the note contains a PARALLEL
1574 or SEQUENCE that has several sets, each set must be individually marked
1575 as frame-related. */
1576 static rtx
1577 frv_dwarf_store (rtx reg, int offset)
1579 rtx set = gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg),
1580 plus_constant (Pmode, stack_pointer_rtx,
1581 offset)),
1582 reg);
1583 RTX_FRAME_RELATED_P (set) = 1;
1584 return set;
1587 /* Emit a frame-related instruction whose pattern is PATTERN. The
1588 instruction is the last in a sequence that cumulatively performs the
1589 operation described by DWARF_PATTERN. The instruction is marked as
1590 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1591 DWARF_PATTERN. */
1592 static void
1593 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1595 rtx insn = emit_insn (pattern);
1596 RTX_FRAME_RELATED_P (insn) = 1;
1597 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1598 dwarf_pattern,
1599 REG_NOTES (insn));
1602 /* Emit instructions that transfer REG to or from the memory location (sp +
1603 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1604 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1605 function to store registers and only the epilogue uses it to load them.
1607 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1608 The generated instruction will use BASE as its base register. BASE may
1609 simply be the stack pointer, but if several accesses are being made to a
1610 region far away from the stack pointer, it may be more efficient to set
1611 up a temporary instead.
1613 Store instructions will be frame-related and will be annotated with the
1614 overall effect of the store. Load instructions will be followed by a
1615 (use) to prevent later optimizations from zapping them.
1617 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1618 as a temporary in such cases. */
1619 static void
1620 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1622 machine_mode mode = GET_MODE (reg);
1623 rtx mem = frv_frame_mem (mode,
1624 accessor->base,
1625 stack_offset - accessor->base_offset);
1627 if (accessor->op == FRV_LOAD)
1629 if (SPR_P (REGNO (reg)))
1631 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1632 emit_insn (gen_rtx_SET (temp, mem));
1633 emit_insn (gen_rtx_SET (reg, temp));
1635 else
1637 /* We cannot use reg+reg addressing for DImode access. */
1638 if (mode == DImode
1639 && GET_CODE (XEXP (mem, 0)) == PLUS
1640 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1641 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1643 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1645 emit_move_insn (temp,
1646 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1647 XEXP (XEXP (mem, 0), 1)));
1648 mem = gen_rtx_MEM (DImode, temp);
1650 emit_insn (gen_rtx_SET (reg, mem));
1652 emit_use (reg);
1654 else
1656 if (SPR_P (REGNO (reg)))
1658 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1659 emit_insn (gen_rtx_SET (temp, reg));
1660 frv_frame_insn (gen_rtx_SET (mem, temp),
1661 frv_dwarf_store (reg, stack_offset));
1663 else if (mode == DImode)
1665 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1666 with a separate save for each register. */
1667 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1668 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1669 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1670 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1672 /* Also we cannot use reg+reg addressing. */
1673 if (GET_CODE (XEXP (mem, 0)) == PLUS
1674 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1675 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1677 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1678 emit_move_insn (temp,
1679 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1680 XEXP (XEXP (mem, 0), 1)));
1681 mem = gen_rtx_MEM (DImode, temp);
1684 frv_frame_insn (gen_rtx_SET (mem, reg),
1685 gen_rtx_PARALLEL (VOIDmode,
1686 gen_rtvec (2, set1, set2)));
1688 else
1689 frv_frame_insn (gen_rtx_SET (mem, reg),
1690 frv_dwarf_store (reg, stack_offset));
1694 /* A function that uses frv_frame_access to transfer a group of registers to
1695 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1696 is the stack information generated by frv_stack_info, and REG_SET is the
1697 number of the register set to transfer. */
1698 static void
1699 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1700 frv_stack_t *info,
1701 int reg_set)
1703 frv_stack_regs_t *regs_info;
1704 int regno;
1706 regs_info = &info->regs[reg_set];
1707 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1708 if (info->save_p[regno])
1709 frv_frame_access (accessor,
1710 info->save_p[regno] == REG_SAVE_2WORDS
1711 ? gen_rtx_REG (DImode, regno)
1712 : gen_rtx_REG (SImode, regno),
1713 info->reg_offset[regno]);
1716 /* Save or restore callee-saved registers that are kept outside the frame
1717 header. The function saves the registers if OP is FRV_STORE and restores
1718 them if OP is FRV_LOAD. INFO is the stack information generated by
1719 frv_stack_info. */
1720 static void
1721 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1723 frv_frame_accessor_t accessor;
1725 accessor.op = op;
1726 accessor.base = stack_pointer_rtx;
1727 accessor.base_offset = 0;
1728 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1729 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1730 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1734 /* Called after register allocation to add any instructions needed for the
1735 prologue. Using a prologue insn is favored compared to putting all of the
1736 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1737 it allows the scheduler to intermix instructions with the saves of
1738 the caller saved registers. In some cases, it might be necessary
1739 to emit a barrier instruction as the last insn to prevent such
1740 scheduling.
1742 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1743 so that the debug info generation code can handle them properly. */
1744 void
1745 frv_expand_prologue (void)
1747 frv_stack_t *info = frv_stack_info ();
1748 rtx sp = stack_pointer_rtx;
1749 rtx fp = frame_pointer_rtx;
1750 frv_frame_accessor_t accessor;
1752 if (TARGET_DEBUG_STACK)
1753 frv_debug_stack (info);
1755 if (flag_stack_usage_info)
1756 current_function_static_stack_size = info->total_size;
1758 if (info->total_size == 0)
1759 return;
1761 /* We're interested in three areas of the frame here:
1763 A: the register save area
1764 B: the old FP
1765 C: the header after B
1767 If the frame pointer isn't used, we'll have to set up A, B and C
1768 using the stack pointer. If the frame pointer is used, we'll access
1769 them as follows:
1771 A: set up using sp
1772 B: set up using sp or a temporary (see below)
1773 C: set up using fp
1775 We set up B using the stack pointer if the frame is small enough.
1776 Otherwise, it's more efficient to copy the old stack pointer into a
1777 temporary and use that.
1779 Note that it's important to make sure the prologue and epilogue use the
1780 same registers to access A and C, since doing otherwise will confuse
1781 the aliasing code. */
1783 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1784 isn't used, the same method will serve for C. */
1785 accessor.op = FRV_STORE;
1786 if (frame_pointer_needed && info->total_size > 2048)
1788 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1789 accessor.base_offset = info->total_size;
1790 emit_insn (gen_movsi (accessor.base, sp));
1792 else
1794 accessor.base = stack_pointer_rtx;
1795 accessor.base_offset = 0;
1798 /* Allocate the stack space. */
1800 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1801 rtx dwarf_offset = GEN_INT (-info->total_size);
1803 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1804 gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1807 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1808 and point the new one to that location. */
1809 if (frame_pointer_needed)
1811 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1813 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1814 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1815 pointer. */
1816 rtx asm_src = plus_constant (Pmode, accessor.base,
1817 fp_offset - accessor.base_offset);
1818 rtx dwarf_src = plus_constant (Pmode, sp, fp_offset);
1820 /* Store the old frame pointer at (sp + FP_OFFSET). */
1821 frv_frame_access (&accessor, fp, fp_offset);
1823 /* Set up the new frame pointer. */
1824 frv_frame_insn (gen_rtx_SET (fp, asm_src),
1825 gen_rtx_SET (fp, dwarf_src));
1827 /* Access region C from the frame pointer. */
1828 accessor.base = fp;
1829 accessor.base_offset = fp_offset;
1832 /* Set up region C. */
1833 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1834 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1835 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1837 /* Set up region A. */
1838 frv_frame_access_standard_regs (FRV_STORE, info);
1840 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1841 scheduler from moving loads before the stores saving the registers. */
1842 if (info->stdarg_size > 0)
1843 emit_insn (gen_blockage ());
1845 /* Set up pic register/small data register for this function. */
1846 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1847 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1848 gen_rtx_REG (Pmode, LR_REGNO),
1849 gen_rtx_REG (SImode, OFFSET_REGNO)));
1853 /* Under frv, all of the work is done via frv_expand_epilogue, but
1854 this function provides a convenient place to do cleanup. */
1856 static void
1857 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1858 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1860 frv_stack_cache = (frv_stack_t *)0;
1862 /* Zap last used registers for conditional execution. */
1863 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1865 /* Release the bitmap of created insns. */
1866 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1870 /* Called after register allocation to add any instructions needed for the
1871 epilogue. Using an epilogue insn is favored compared to putting all of the
1872 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1873 it allows the scheduler to intermix instructions with the saves of
1874 the caller saved registers. In some cases, it might be necessary
1875 to emit a barrier instruction as the last insn to prevent such
1876 scheduling. */
1878 void
1879 frv_expand_epilogue (bool emit_return)
1881 frv_stack_t *info = frv_stack_info ();
1882 rtx fp = frame_pointer_rtx;
1883 rtx sp = stack_pointer_rtx;
1884 rtx return_addr;
1885 int fp_offset;
1887 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1889 /* Restore the stack pointer to its original value if alloca or the like
1890 is used. */
1891 if (! crtl->sp_is_unchanging)
1892 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1894 /* Restore the callee-saved registers that were used in this function. */
1895 frv_frame_access_standard_regs (FRV_LOAD, info);
1897 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1898 no return instruction should be emitted. */
1899 if (info->save_p[LR_REGNO])
1901 int lr_offset;
1902 rtx mem;
1904 /* Use the same method to access the link register's slot as we did in
1905 the prologue. In other words, use the frame pointer if available,
1906 otherwise use the stack pointer.
1908 LR_OFFSET is the offset of the link register's slot from the start
1909 of the frame and MEM is a memory rtx for it. */
1910 lr_offset = info->reg_offset[LR_REGNO];
1911 if (frame_pointer_needed)
1912 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1913 else
1914 mem = frv_frame_mem (Pmode, sp, lr_offset);
1916 /* Load the old link register into a GPR. */
1917 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1918 emit_insn (gen_rtx_SET (return_addr, mem));
1920 else
1921 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1923 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1924 the load is preserved. */
1925 if (frame_pointer_needed)
1927 emit_insn (gen_rtx_SET (fp, gen_rtx_MEM (Pmode, fp)));
1928 emit_use (fp);
1931 /* Deallocate the stack frame. */
1932 if (info->total_size != 0)
1934 rtx offset = frv_frame_offset_rtx (info->total_size);
1935 emit_insn (gen_stack_adjust (sp, sp, offset));
1938 /* If this function uses eh_return, add the final stack adjustment now. */
1939 if (crtl->calls_eh_return)
1940 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1942 if (emit_return)
1943 emit_jump_insn (gen_epilogue_return (return_addr));
1944 else
1946 rtx lr = return_addr;
1948 if (REGNO (return_addr) != LR_REGNO)
1950 lr = gen_rtx_REG (Pmode, LR_REGNO);
1951 emit_move_insn (lr, return_addr);
1954 emit_use (lr);
1959 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1961 static void
1962 frv_asm_output_mi_thunk (FILE *file,
1963 tree thunk_fndecl ATTRIBUTE_UNUSED,
1964 HOST_WIDE_INT delta,
1965 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1966 tree function)
1968 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1969 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1970 const char *name_jmp = reg_names[JUMP_REGNO];
1971 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1973 /* Do the add using an addi if possible. */
1974 if (IN_RANGE (delta, -2048, 2047))
1975 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1976 else
1978 const char *const name_add = reg_names[TEMP_REGNO];
1979 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1980 parallel, delta, name_add);
1981 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1982 delta, name_add);
1983 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1986 if (TARGET_FDPIC)
1988 const char *name_pic = reg_names[FDPIC_REGNO];
1989 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1991 if (flag_pic != 1)
1993 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1994 assemble_name (file, name_func);
1995 fprintf (file, "),%s\n", name_jmp);
1997 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1998 assemble_name (file, name_func);
1999 fprintf (file, "),%s\n", name_jmp);
2001 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2003 else
2005 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2006 assemble_name (file, name_func);
2007 fprintf (file, "\t)), %s\n", name_jmp);
2010 else if (!flag_pic)
2012 fprintf (file, "\tsethi%s #hi(", parallel);
2013 assemble_name (file, name_func);
2014 fprintf (file, "),%s\n", name_jmp);
2016 fprintf (file, "\tsetlo #lo(");
2017 assemble_name (file, name_func);
2018 fprintf (file, "),%s\n", name_jmp);
2020 else
2022 /* Use JUMP_REGNO as a temporary PIC register. */
2023 const char *name_lr = reg_names[LR_REGNO];
2024 const char *name_gppic = name_jmp;
2025 const char *name_tmp = reg_names[TEMP_REGNO];
2027 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2028 fprintf (file, "\tcall 1f\n");
2029 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2030 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2031 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2032 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2033 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2035 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2036 assemble_name (file, name_func);
2037 fprintf (file, "),%s\n", name_tmp);
2039 fprintf (file, "\tsetlo #gprello(");
2040 assemble_name (file, name_func);
2041 fprintf (file, "),%s\n", name_tmp);
2043 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2046 /* Jump to the function address. */
2047 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2052 /* On frv, create a frame whenever we need to create stack. */
2054 static bool
2055 frv_frame_pointer_required (void)
2057 /* If we forgoing the usual linkage requirements, we only need
2058 a frame pointer if the stack pointer might change. */
2059 if (!TARGET_LINKED_FP)
2060 return !crtl->sp_is_unchanging;
2062 if (! crtl->is_leaf)
2063 return true;
2065 if (get_frame_size () != 0)
2066 return true;
2068 if (cfun->stdarg)
2069 return true;
2071 if (!crtl->sp_is_unchanging)
2072 return true;
2074 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2075 return true;
2077 if (profile_flag)
2078 return true;
2080 if (cfun->machine->frame_needed)
2081 return true;
2083 return false;
2087 /* Worker function for TARGET_CAN_ELIMINATE. */
2089 bool
2090 frv_can_eliminate (const int from, const int to)
2092 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2093 ? ! frame_pointer_needed
2094 : true);
2097 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2098 initial difference between the specified pair of registers. This macro must
2099 be defined if `ELIMINABLE_REGS' is defined. */
2101 /* See frv_stack_info for more details on the frv stack frame. */
2104 frv_initial_elimination_offset (int from, int to)
2106 frv_stack_t *info = frv_stack_info ();
2107 int ret = 0;
2109 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2110 ret = info->total_size - info->pretend_size;
2112 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2113 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2115 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2116 ret = (info->total_size
2117 - info->reg_offset[FRAME_POINTER_REGNUM]
2118 - info->pretend_size);
2120 else
2121 gcc_unreachable ();
2123 if (TARGET_DEBUG_STACK)
2124 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2125 reg_names [from], reg_names[to], ret);
2127 return ret;
2131 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2133 static void
2134 frv_setup_incoming_varargs (cumulative_args_t cum_v,
2135 machine_mode mode,
2136 tree type ATTRIBUTE_UNUSED,
2137 int *pretend_size,
2138 int second_time)
2140 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
2142 if (TARGET_DEBUG_ARG)
2143 fprintf (stderr,
2144 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2145 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2149 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2151 static rtx
2152 frv_expand_builtin_saveregs (void)
2154 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2156 if (TARGET_DEBUG_ARG)
2157 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2158 offset);
2160 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2164 /* Expand __builtin_va_start to do the va_start macro. */
2166 static void
2167 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2169 tree t;
2170 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2172 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2173 GEN_INT (UNITS_PER_WORD * num));
2175 if (TARGET_DEBUG_ARG)
2177 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2178 crtl->args.info, num);
2180 debug_rtx (nextarg);
2183 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2184 fold_convert (TREE_TYPE (valist),
2185 make_tree (sizetype, nextarg)));
2186 TREE_SIDE_EFFECTS (t) = 1;
2188 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2192 /* Expand a block move operation, and return 1 if successful. Return 0
2193 if we should let the compiler generate normal code.
2195 operands[0] is the destination
2196 operands[1] is the source
2197 operands[2] is the length
2198 operands[3] is the alignment */
2200 /* Maximum number of loads to do before doing the stores */
2201 #ifndef MAX_MOVE_REG
2202 #define MAX_MOVE_REG 4
2203 #endif
2205 /* Maximum number of total loads to do. */
2206 #ifndef TOTAL_MOVE_REG
2207 #define TOTAL_MOVE_REG 8
2208 #endif
2211 frv_expand_block_move (rtx operands[])
2213 rtx orig_dest = operands[0];
2214 rtx orig_src = operands[1];
2215 rtx bytes_rtx = operands[2];
2216 rtx align_rtx = operands[3];
2217 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2218 int align;
2219 int bytes;
2220 int offset;
2221 int num_reg;
2222 int i;
2223 rtx src_reg;
2224 rtx dest_reg;
2225 rtx src_addr;
2226 rtx dest_addr;
2227 rtx src_mem;
2228 rtx dest_mem;
2229 rtx tmp_reg;
2230 rtx stores[MAX_MOVE_REG];
2231 int move_bytes;
2232 machine_mode mode;
2234 /* If this is not a fixed size move, just call memcpy. */
2235 if (! constp)
2236 return FALSE;
2238 /* This should be a fixed size alignment. */
2239 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2241 align = INTVAL (align_rtx);
2243 /* Anything to move? */
2244 bytes = INTVAL (bytes_rtx);
2245 if (bytes <= 0)
2246 return TRUE;
2248 /* Don't support real large moves. */
2249 if (bytes > TOTAL_MOVE_REG*align)
2250 return FALSE;
2252 /* Move the address into scratch registers. */
2253 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2254 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2256 num_reg = offset = 0;
2257 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2259 /* Calculate the correct offset for src/dest. */
2260 if (offset == 0)
2262 src_addr = src_reg;
2263 dest_addr = dest_reg;
2265 else
2267 src_addr = plus_constant (Pmode, src_reg, offset);
2268 dest_addr = plus_constant (Pmode, dest_reg, offset);
2271 /* Generate the appropriate load and store, saving the stores
2272 for later. */
2273 if (bytes >= 4 && align >= 4)
2274 mode = SImode;
2275 else if (bytes >= 2 && align >= 2)
2276 mode = HImode;
2277 else
2278 mode = QImode;
2280 move_bytes = GET_MODE_SIZE (mode);
2281 tmp_reg = gen_reg_rtx (mode);
2282 src_mem = change_address (orig_src, mode, src_addr);
2283 dest_mem = change_address (orig_dest, mode, dest_addr);
2284 emit_insn (gen_rtx_SET (tmp_reg, src_mem));
2285 stores[num_reg++] = gen_rtx_SET (dest_mem, tmp_reg);
2287 if (num_reg >= MAX_MOVE_REG)
2289 for (i = 0; i < num_reg; i++)
2290 emit_insn (stores[i]);
2291 num_reg = 0;
2295 for (i = 0; i < num_reg; i++)
2296 emit_insn (stores[i]);
2298 return TRUE;
2302 /* Expand a block clear operation, and return 1 if successful. Return 0
2303 if we should let the compiler generate normal code.
2305 operands[0] is the destination
2306 operands[1] is the length
2307 operands[3] is the alignment */
2310 frv_expand_block_clear (rtx operands[])
2312 rtx orig_dest = operands[0];
2313 rtx bytes_rtx = operands[1];
2314 rtx align_rtx = operands[3];
2315 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2316 int align;
2317 int bytes;
2318 int offset;
2319 rtx dest_reg;
2320 rtx dest_addr;
2321 rtx dest_mem;
2322 int clear_bytes;
2323 machine_mode mode;
2325 /* If this is not a fixed size move, just call memcpy. */
2326 if (! constp)
2327 return FALSE;
2329 /* This should be a fixed size alignment. */
2330 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2332 align = INTVAL (align_rtx);
2334 /* Anything to move? */
2335 bytes = INTVAL (bytes_rtx);
2336 if (bytes <= 0)
2337 return TRUE;
2339 /* Don't support real large clears. */
2340 if (bytes > TOTAL_MOVE_REG*align)
2341 return FALSE;
2343 /* Move the address into a scratch register. */
2344 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2346 offset = 0;
2347 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2349 /* Calculate the correct offset for src/dest. */
2350 dest_addr = ((offset == 0)
2351 ? dest_reg
2352 : plus_constant (Pmode, dest_reg, offset));
2354 /* Generate the appropriate store of gr0. */
2355 if (bytes >= 4 && align >= 4)
2356 mode = SImode;
2357 else if (bytes >= 2 && align >= 2)
2358 mode = HImode;
2359 else
2360 mode = QImode;
2362 clear_bytes = GET_MODE_SIZE (mode);
2363 dest_mem = change_address (orig_dest, mode, dest_addr);
2364 emit_insn (gen_rtx_SET (dest_mem, const0_rtx));
2367 return TRUE;
2371 /* The following variable is used to output modifiers of assembler
2372 code of the current output insn. */
2374 static rtx *frv_insn_operands;
2376 /* The following function is used to add assembler insn code suffix .p
2377 if it is necessary. */
2379 const char *
2380 frv_asm_output_opcode (FILE *f, const char *ptr)
2382 int c;
2384 if (frv_insn_packing_flag <= 0)
2385 return ptr;
2387 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2389 c = *ptr++;
2390 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2391 || (*ptr >= 'A' && *ptr <= 'Z')))
2393 int letter = *ptr++;
2395 c = atoi (ptr);
2396 frv_print_operand (f, frv_insn_operands [c], letter);
2397 while ((c = *ptr) >= '0' && c <= '9')
2398 ptr++;
2400 else
2401 fputc (c, f);
2404 fprintf (f, ".p");
2406 return ptr;
2409 /* Set up the packing bit for the current output insn. Note that this
2410 function is not called for asm insns. */
2412 void
2413 frv_final_prescan_insn (rtx_insn *insn, rtx *opvec,
2414 int noperands ATTRIBUTE_UNUSED)
2416 if (INSN_P (insn))
2418 if (frv_insn_packing_flag >= 0)
2420 frv_insn_operands = opvec;
2421 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2423 else if (recog_memoized (insn) >= 0
2424 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2425 /* Packing optimizations have been disabled, but INSN can only
2426 be issued in M1. Insert an mnop in M0. */
2427 fprintf (asm_out_file, "\tmnop.p\n");
2433 /* A C expression whose value is RTL representing the address in a stack frame
2434 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2435 an RTL expression for the address of the stack frame itself.
2437 If you don't define this macro, the default is to return the value of
2438 FRAMEADDR--that is, the stack frame address is also the address of the stack
2439 word that points to the previous frame. */
2441 /* The default is correct, but we need to make sure the frame gets created. */
2443 frv_dynamic_chain_address (rtx frame)
2445 cfun->machine->frame_needed = 1;
2446 return frame;
2450 /* A C expression whose value is RTL representing the value of the return
2451 address for the frame COUNT steps up from the current frame, after the
2452 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2453 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2454 defined.
2456 The value of the expression must always be the correct address when COUNT is
2457 zero, but may be `NULL_RTX' if there is not way to determine the return
2458 address of other frames. */
2461 frv_return_addr_rtx (int count, rtx frame)
2463 if (count != 0)
2464 return const0_rtx;
2465 cfun->machine->frame_needed = 1;
2466 return gen_rtx_MEM (Pmode, plus_constant (Pmode, frame, 8));
2469 /* Given a memory reference MEMREF, interpret the referenced memory as
2470 an array of MODE values, and return a reference to the element
2471 specified by INDEX. Assume that any pre-modification implicit in
2472 MEMREF has already happened.
2474 MEMREF must be a legitimate operand for modes larger than SImode.
2475 frv_legitimate_address_p forbids register+register addresses, which
2476 this function cannot handle. */
2478 frv_index_memory (rtx memref, machine_mode mode, int index)
2480 rtx base = XEXP (memref, 0);
2481 if (GET_CODE (base) == PRE_MODIFY)
2482 base = XEXP (base, 0);
2483 return change_address (memref, mode,
2484 plus_constant (Pmode, base,
2485 index * GET_MODE_SIZE (mode)));
2489 /* Print a memory address as an operand to reference that memory location. */
2490 static void
2491 frv_print_operand_address (FILE * stream, rtx x)
2493 if (GET_CODE (x) == MEM)
2494 x = XEXP (x, 0);
2496 switch (GET_CODE (x))
2498 case REG:
2499 fputs (reg_names [ REGNO (x)], stream);
2500 return;
2502 case CONST_INT:
2503 fprintf (stream, "%ld", (long) INTVAL (x));
2504 return;
2506 case SYMBOL_REF:
2507 assemble_name (stream, XSTR (x, 0));
2508 return;
2510 case LABEL_REF:
2511 case CONST:
2512 output_addr_const (stream, x);
2513 return;
2515 case PLUS:
2516 /* Poorly constructed asm statements can trigger this alternative.
2517 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2518 frv_print_operand_memory_reference (stream, x, 0);
2519 return;
2521 default:
2522 break;
2525 fatal_insn ("bad insn to frv_print_operand_address:", x);
2529 static void
2530 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2532 int regno = true_regnum (x);
2533 if (GPR_P (regno))
2534 fputs (reg_names[regno], stream);
2535 else
2536 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2539 /* Print a memory reference suitable for the ld/st instructions. */
2541 static void
2542 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2544 struct frv_unspec unspec;
2545 rtx x0 = NULL_RTX;
2546 rtx x1 = NULL_RTX;
2548 switch (GET_CODE (x))
2550 case SUBREG:
2551 case REG:
2552 x0 = x;
2553 break;
2555 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2556 x0 = XEXP (x, 0);
2557 x1 = XEXP (XEXP (x, 1), 1);
2558 break;
2560 case CONST_INT:
2561 x1 = x;
2562 break;
2564 case PLUS:
2565 x0 = XEXP (x, 0);
2566 x1 = XEXP (x, 1);
2567 if (GET_CODE (x0) == CONST_INT)
2569 x0 = XEXP (x, 1);
2570 x1 = XEXP (x, 0);
2572 break;
2574 default:
2575 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2576 break;
2580 if (addr_offset)
2582 if (!x1)
2583 x1 = const0_rtx;
2584 else if (GET_CODE (x1) != CONST_INT)
2585 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2588 fputs ("@(", stream);
2589 if (!x0)
2590 fputs (reg_names[GPR_R0], stream);
2591 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2592 frv_print_operand_memory_reference_reg (stream, x0);
2593 else
2594 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2596 fputs (",", stream);
2597 if (!x1)
2598 fputs (reg_names [GPR_R0], stream);
2600 else
2602 switch (GET_CODE (x1))
2604 case SUBREG:
2605 case REG:
2606 frv_print_operand_memory_reference_reg (stream, x1);
2607 break;
2609 case CONST_INT:
2610 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2611 break;
2613 case CONST:
2614 if (!frv_const_unspec_p (x1, &unspec))
2615 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2616 frv_output_const_unspec (stream, &unspec);
2617 break;
2619 default:
2620 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2624 fputs (")", stream);
2628 /* Return 2 for likely branches and 0 for non-likely branches */
2630 #define FRV_JUMP_LIKELY 2
2631 #define FRV_JUMP_NOT_LIKELY 0
2633 static int
2634 frv_print_operand_jump_hint (rtx_insn *insn)
2636 rtx note;
2637 rtx labelref;
2638 int ret;
2639 int prob = -1;
2640 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2642 gcc_assert (JUMP_P (insn));
2644 /* Assume any non-conditional jump is likely. */
2645 if (! any_condjump_p (insn))
2646 ret = FRV_JUMP_LIKELY;
2648 else
2650 labelref = condjump_label (insn);
2651 if (labelref)
2653 rtx label = XEXP (labelref, 0);
2654 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2655 ? BACKWARD
2656 : FORWARD);
2659 note = find_reg_note (insn, REG_BR_PROB, 0);
2660 if (!note)
2661 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2663 else
2665 prob = XINT (note, 0);
2666 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2667 ? FRV_JUMP_LIKELY
2668 : FRV_JUMP_NOT_LIKELY);
2672 #if 0
2673 if (TARGET_DEBUG)
2675 char *direction;
2677 switch (jump_type)
2679 default:
2680 case UNKNOWN: direction = "unknown jump direction"; break;
2681 case BACKWARD: direction = "jump backward"; break;
2682 case FORWARD: direction = "jump forward"; break;
2685 fprintf (stderr,
2686 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n",
2687 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2688 (long)INSN_UID (insn), direction, prob,
2689 REG_BR_PROB_BASE, ret);
2691 #endif
2693 return ret;
2697 /* Return the comparison operator to use for CODE given that the ICC
2698 register is OP0. */
2700 static const char *
2701 comparison_string (enum rtx_code code, rtx op0)
2703 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2704 switch (code)
2706 default: output_operand_lossage ("bad condition code");
2707 case EQ: return "eq";
2708 case NE: return "ne";
2709 case LT: return is_nz_p ? "n" : "lt";
2710 case LE: return "le";
2711 case GT: return "gt";
2712 case GE: return is_nz_p ? "p" : "ge";
2713 case LTU: return is_nz_p ? "no" : "c";
2714 case LEU: return is_nz_p ? "eq" : "ls";
2715 case GTU: return is_nz_p ? "ne" : "hi";
2716 case GEU: return is_nz_p ? "ra" : "nc";
2720 /* Print an operand to an assembler instruction.
2722 `%' followed by a letter and a digit says to output an operand in an
2723 alternate fashion. Four letters have standard, built-in meanings
2724 described below. The hook `TARGET_PRINT_OPERAND' can define
2725 additional letters with nonstandard meanings.
2727 `%cDIGIT' can be used to substitute an operand that is a constant value
2728 without the syntax that normally indicates an immediate operand.
2730 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2731 before printing.
2733 `%aDIGIT' can be used to substitute an operand as if it were a memory
2734 reference, with the actual operand treated as the address. This may be
2735 useful when outputting a "load address" instruction, because often the
2736 assembler syntax for such an instruction requires you to write the operand
2737 as if it were a memory reference.
2739 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2741 `%=' outputs a number which is unique to each instruction in the entire
2742 compilation. This is useful for making local labels to be referred to more
2743 than once in a single template that generates multiple assembler
2744 instructions.
2746 `%' followed by a punctuation character specifies a substitution that
2747 does not use an operand. Only one case is standard: `%%' outputs a
2748 `%' into the assembler code. Other nonstandard cases can be defined
2749 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2750 punctuation characters are valid with the
2751 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2753 static void
2754 frv_print_operand (FILE * file, rtx x, int code)
2756 struct frv_unspec unspec;
2757 HOST_WIDE_INT value;
2758 int offset;
2760 if (code != 0 && !ISALPHA (code))
2761 value = 0;
2763 else if (GET_CODE (x) == CONST_INT)
2764 value = INTVAL (x);
2766 else if (GET_CODE (x) == CONST_DOUBLE)
2768 if (GET_MODE (x) == SFmode)
2770 REAL_VALUE_TYPE rv;
2771 long l;
2773 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2774 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2775 value = l;
2778 else if (GET_MODE (x) == VOIDmode)
2779 value = CONST_DOUBLE_LOW (x);
2781 else
2782 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2785 else
2786 value = 0;
2788 switch (code)
2791 case '.':
2792 /* Output r0. */
2793 fputs (reg_names[GPR_R0], file);
2794 break;
2796 case '#':
2797 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2798 break;
2800 case '@':
2801 /* Output small data area base register (gr16). */
2802 fputs (reg_names[SDA_BASE_REG], file);
2803 break;
2805 case '~':
2806 /* Output pic register (gr17). */
2807 fputs (reg_names[PIC_REGNO], file);
2808 break;
2810 case '*':
2811 /* Output the temporary integer CCR register. */
2812 fputs (reg_names[ICR_TEMP], file);
2813 break;
2815 case '&':
2816 /* Output the temporary integer CC register. */
2817 fputs (reg_names[ICC_TEMP], file);
2818 break;
2820 /* case 'a': print an address. */
2822 case 'C':
2823 /* Print appropriate test for integer branch false operation. */
2824 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2825 XEXP (x, 0)), file);
2826 break;
2828 case 'c':
2829 /* Print appropriate test for integer branch true operation. */
2830 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2831 break;
2833 case 'e':
2834 /* Print 1 for a NE and 0 for an EQ to give the final argument
2835 for a conditional instruction. */
2836 if (GET_CODE (x) == NE)
2837 fputs ("1", file);
2839 else if (GET_CODE (x) == EQ)
2840 fputs ("0", file);
2842 else
2843 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2844 break;
2846 case 'F':
2847 /* Print appropriate test for floating point branch false operation. */
2848 switch (GET_CODE (x))
2850 default:
2851 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2853 case EQ: fputs ("ne", file); break;
2854 case NE: fputs ("eq", file); break;
2855 case LT: fputs ("uge", file); break;
2856 case LE: fputs ("ug", file); break;
2857 case GT: fputs ("ule", file); break;
2858 case GE: fputs ("ul", file); break;
2860 break;
2862 case 'f':
2863 /* Print appropriate test for floating point branch true operation. */
2864 switch (GET_CODE (x))
2866 default:
2867 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2869 case EQ: fputs ("eq", file); break;
2870 case NE: fputs ("ne", file); break;
2871 case LT: fputs ("lt", file); break;
2872 case LE: fputs ("le", file); break;
2873 case GT: fputs ("gt", file); break;
2874 case GE: fputs ("ge", file); break;
2876 break;
2878 case 'g':
2879 /* Print appropriate GOT function. */
2880 if (GET_CODE (x) != CONST_INT)
2881 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2882 fputs (unspec_got_name (INTVAL (x)), file);
2883 break;
2885 case 'I':
2886 /* Print 'i' if the operand is a constant, or is a memory reference that
2887 adds a constant. */
2888 if (GET_CODE (x) == MEM)
2889 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2890 ? XEXP (XEXP (x, 0), 1)
2891 : XEXP (x, 0));
2892 else if (GET_CODE (x) == PLUS)
2893 x = XEXP (x, 1);
2895 switch (GET_CODE (x))
2897 default:
2898 break;
2900 case CONST_INT:
2901 case SYMBOL_REF:
2902 case CONST:
2903 fputs ("i", file);
2904 break;
2906 break;
2908 case 'i':
2909 /* For jump instructions, print 'i' if the operand is a constant or
2910 is an expression that adds a constant. */
2911 if (GET_CODE (x) == CONST_INT)
2912 fputs ("i", file);
2914 else
2916 if (GET_CODE (x) == CONST_INT
2917 || (GET_CODE (x) == PLUS
2918 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2919 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2920 fputs ("i", file);
2922 break;
2924 case 'L':
2925 /* Print the lower register of a double word register pair */
2926 if (GET_CODE (x) == REG)
2927 fputs (reg_names[ REGNO (x)+1 ], file);
2928 else
2929 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2930 break;
2932 /* case 'l': print a LABEL_REF. */
2934 case 'M':
2935 case 'N':
2936 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2937 for the second word of double memory operations. */
2938 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2939 switch (GET_CODE (x))
2941 default:
2942 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
2944 case MEM:
2945 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2946 break;
2948 case REG:
2949 case SUBREG:
2950 case CONST_INT:
2951 case PLUS:
2952 case SYMBOL_REF:
2953 frv_print_operand_memory_reference (file, x, offset);
2954 break;
2956 break;
2958 case 'O':
2959 /* Print the opcode of a command. */
2960 switch (GET_CODE (x))
2962 default:
2963 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
2965 case PLUS: fputs ("add", file); break;
2966 case MINUS: fputs ("sub", file); break;
2967 case AND: fputs ("and", file); break;
2968 case IOR: fputs ("or", file); break;
2969 case XOR: fputs ("xor", file); break;
2970 case ASHIFT: fputs ("sll", file); break;
2971 case ASHIFTRT: fputs ("sra", file); break;
2972 case LSHIFTRT: fputs ("srl", file); break;
2974 break;
2976 /* case 'n': negate and print a constant int. */
2978 case 'P':
2979 /* Print PIC label using operand as the number. */
2980 if (GET_CODE (x) != CONST_INT)
2981 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
2983 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2984 break;
2986 case 'U':
2987 /* Print 'u' if the operand is a update load/store. */
2988 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2989 fputs ("u", file);
2990 break;
2992 case 'z':
2993 /* If value is 0, print gr0, otherwise it must be a register. */
2994 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2995 fputs (reg_names[GPR_R0], file);
2997 else if (GET_CODE (x) == REG)
2998 fputs (reg_names [REGNO (x)], file);
3000 else
3001 fatal_insn ("bad insn in frv_print_operand, z case", x);
3002 break;
3004 case 'x':
3005 /* Print constant in hex. */
3006 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3008 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3009 break;
3012 /* Fall through. */
3014 case '\0':
3015 if (GET_CODE (x) == REG)
3016 fputs (reg_names [REGNO (x)], file);
3018 else if (GET_CODE (x) == CONST_INT
3019 || GET_CODE (x) == CONST_DOUBLE)
3020 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3022 else if (frv_const_unspec_p (x, &unspec))
3023 frv_output_const_unspec (file, &unspec);
3025 else if (GET_CODE (x) == MEM)
3026 frv_print_operand_address (file, XEXP (x, 0));
3028 else if (CONSTANT_ADDRESS_P (x))
3029 frv_print_operand_address (file, x);
3031 else
3032 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3034 break;
3036 default:
3037 fatal_insn ("frv_print_operand: unknown code", x);
3038 break;
3041 return;
3044 static bool
3045 frv_print_operand_punct_valid_p (unsigned char code)
3047 return (code == '.' || code == '#' || code == '@' || code == '~'
3048 || code == '*' || code == '&');
3052 /* A C statement (sans semicolon) for initializing the variable CUM for the
3053 state at the beginning of the argument list. The variable has type
3054 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3055 of the function which will receive the args, or 0 if the args are to a
3056 compiler support library function. The value of INDIRECT is nonzero when
3057 processing an indirect call, for example a call through a function pointer.
3058 The value of INDIRECT is zero for a call to an explicitly named function, a
3059 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3060 arguments for the function being compiled.
3062 When processing a call to a compiler support library function, LIBNAME
3063 identifies which one. It is a `symbol_ref' rtx which contains the name of
3064 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3065 being processed. Thus, each time this macro is called, either LIBNAME or
3066 FNTYPE is nonzero, but never both of them at once. */
3068 void
3069 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3070 tree fntype,
3071 rtx libname,
3072 tree fndecl,
3073 int incoming)
3075 *cum = FIRST_ARG_REGNUM;
3077 if (TARGET_DEBUG_ARG)
3079 fprintf (stderr, "\ninit_cumulative_args:");
3080 if (!fndecl && fntype)
3081 fputs (" indirect", stderr);
3083 if (incoming)
3084 fputs (" incoming", stderr);
3086 if (fntype)
3088 tree ret_type = TREE_TYPE (fntype);
3089 fprintf (stderr, " return=%s,",
3090 get_tree_code_name (TREE_CODE (ret_type)));
3093 if (libname && GET_CODE (libname) == SYMBOL_REF)
3094 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3096 if (cfun->returns_struct)
3097 fprintf (stderr, " return-struct");
3099 putc ('\n', stderr);
3104 /* Return true if we should pass an argument on the stack rather than
3105 in registers. */
3107 static bool
3108 frv_must_pass_in_stack (machine_mode mode, const_tree type)
3110 if (mode == BLKmode)
3111 return true;
3112 if (type == NULL)
3113 return false;
3114 return AGGREGATE_TYPE_P (type);
3117 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3118 argument with the specified mode and type. If it is not defined,
3119 `PARM_BOUNDARY' is used for all arguments. */
3121 static unsigned int
3122 frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED,
3123 const_tree type ATTRIBUTE_UNUSED)
3125 return BITS_PER_WORD;
3128 static rtx
3129 frv_function_arg_1 (cumulative_args_t cum_v, machine_mode mode,
3130 const_tree type ATTRIBUTE_UNUSED, bool named,
3131 bool incoming ATTRIBUTE_UNUSED)
3133 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3135 machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3136 int arg_num = *cum;
3137 rtx ret;
3138 const char *debstr;
3140 /* Return a marker for use in the call instruction. */
3141 if (xmode == VOIDmode)
3143 ret = const0_rtx;
3144 debstr = "<0>";
3147 else if (arg_num <= LAST_ARG_REGNUM)
3149 ret = gen_rtx_REG (xmode, arg_num);
3150 debstr = reg_names[arg_num];
3153 else
3155 ret = NULL_RTX;
3156 debstr = "memory";
3159 if (TARGET_DEBUG_ARG)
3160 fprintf (stderr,
3161 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3162 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3164 return ret;
3167 static rtx
3168 frv_function_arg (cumulative_args_t cum, machine_mode mode,
3169 const_tree type, bool named)
3171 return frv_function_arg_1 (cum, mode, type, named, false);
3174 static rtx
3175 frv_function_incoming_arg (cumulative_args_t cum, machine_mode mode,
3176 const_tree type, bool named)
3178 return frv_function_arg_1 (cum, mode, type, named, true);
3182 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3183 advance past an argument in the argument list. The values MODE, TYPE and
3184 NAMED describe that argument. Once this is done, the variable CUM is
3185 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3187 This macro need not do anything if the argument in question was passed on
3188 the stack. The compiler knows how to track the amount of stack space used
3189 for arguments without any special help. */
3191 static void
3192 frv_function_arg_advance (cumulative_args_t cum_v,
3193 machine_mode mode,
3194 const_tree type ATTRIBUTE_UNUSED,
3195 bool named)
3197 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3199 machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3200 int bytes = GET_MODE_SIZE (xmode);
3201 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3202 int arg_num = *cum;
3204 *cum = arg_num + words;
3206 if (TARGET_DEBUG_ARG)
3207 fprintf (stderr,
3208 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3209 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3213 /* A C expression for the number of words, at the beginning of an argument,
3214 must be put in registers. The value must be zero for arguments that are
3215 passed entirely in registers or that are entirely pushed on the stack.
3217 On some machines, certain arguments must be passed partially in registers
3218 and partially in memory. On these machines, typically the first N words of
3219 arguments are passed in registers, and the rest on the stack. If a
3220 multi-word argument (a `double' or a structure) crosses that boundary, its
3221 first few words must be passed in registers and the rest must be pushed.
3222 This macro tells the compiler when this occurs, and how many of the words
3223 should go in registers.
3225 `FUNCTION_ARG' for these arguments should return the first register to be
3226 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3227 the called function. */
3229 static int
3230 frv_arg_partial_bytes (cumulative_args_t cum, machine_mode mode,
3231 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3234 machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3235 int bytes = GET_MODE_SIZE (xmode);
3236 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3237 int arg_num = *get_cumulative_args (cum);
3238 int ret;
3240 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3241 ? LAST_ARG_REGNUM - arg_num + 1
3242 : 0);
3243 ret *= UNITS_PER_WORD;
3245 if (TARGET_DEBUG_ARG && ret)
3246 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3248 return ret;
3252 /* Implements TARGET_FUNCTION_VALUE. */
3254 static rtx
3255 frv_function_value (const_tree valtype,
3256 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3257 bool outgoing ATTRIBUTE_UNUSED)
3259 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3263 /* Implements TARGET_LIBCALL_VALUE. */
3265 static rtx
3266 frv_libcall_value (machine_mode mode,
3267 const_rtx fun ATTRIBUTE_UNUSED)
3269 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3273 /* Implements FUNCTION_VALUE_REGNO_P. */
3275 bool
3276 frv_function_value_regno_p (const unsigned int regno)
3278 return (regno == RETURN_VALUE_REGNUM);
3281 /* Return true if a register is ok to use as a base or index register. */
3283 static FRV_INLINE int
3284 frv_regno_ok_for_base_p (int regno, int strict_p)
3286 if (GPR_P (regno))
3287 return TRUE;
3289 if (strict_p)
3290 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3292 if (regno == ARG_POINTER_REGNUM)
3293 return TRUE;
3295 return (regno >= FIRST_PSEUDO_REGISTER);
3299 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3300 RTX) is a legitimate memory address on the target machine for a memory
3301 operand of mode MODE.
3303 It usually pays to define several simpler macros to serve as subroutines for
3304 this one. Otherwise it may be too complicated to understand.
3306 This macro must exist in two variants: a strict variant and a non-strict
3307 one. The strict variant is used in the reload pass. It must be defined so
3308 that any pseudo-register that has not been allocated a hard register is
3309 considered a memory reference. In contexts where some kind of register is
3310 required, a pseudo-register with no hard register must be rejected.
3312 The non-strict variant is used in other passes. It must be defined to
3313 accept all pseudo-registers in every context where some kind of register is
3314 required.
3316 Compiler source files that want to use the strict variant of this macro
3317 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3318 conditional to define the strict variant in that case and the non-strict
3319 variant otherwise.
3321 Normally, constant addresses which are the sum of a `symbol_ref' and an
3322 integer are stored inside a `const' RTX to mark them as constant.
3323 Therefore, there is no need to recognize such sums specifically as
3324 legitimate addresses. Normally you would simply recognize any `const' as
3325 legitimate.
3327 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3328 constant sums that are not marked with `const'. It assumes that a
3329 naked `plus' indicates indexing. If so, then you *must* reject such
3330 naked constant sums as illegitimate addresses, so that none of them
3331 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3334 frv_legitimate_address_p_1 (machine_mode mode,
3335 rtx x,
3336 int strict_p,
3337 int condexec_p,
3338 int allow_double_reg_p)
3340 rtx x0, x1;
3341 int ret = 0;
3342 HOST_WIDE_INT value;
3343 unsigned regno0;
3345 if (FRV_SYMBOL_REF_TLS_P (x))
3346 return 0;
3348 switch (GET_CODE (x))
3350 default:
3351 break;
3353 case SUBREG:
3354 x = SUBREG_REG (x);
3355 if (GET_CODE (x) != REG)
3356 break;
3358 /* Fall through. */
3360 case REG:
3361 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3362 break;
3364 case PRE_MODIFY:
3365 x0 = XEXP (x, 0);
3366 x1 = XEXP (x, 1);
3367 if (GET_CODE (x0) != REG
3368 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3369 || GET_CODE (x1) != PLUS
3370 || ! rtx_equal_p (x0, XEXP (x1, 0))
3371 || GET_CODE (XEXP (x1, 1)) != REG
3372 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3373 break;
3375 ret = 1;
3376 break;
3378 case CONST_INT:
3379 /* 12-bit immediate */
3380 if (condexec_p)
3381 ret = FALSE;
3382 else
3384 ret = IN_RANGE (INTVAL (x), -2048, 2047);
3386 /* If we can't use load/store double operations, make sure we can
3387 address the second word. */
3388 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3389 ret = IN_RANGE (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3390 -2048, 2047);
3392 break;
3394 case PLUS:
3395 x0 = XEXP (x, 0);
3396 x1 = XEXP (x, 1);
3398 if (GET_CODE (x0) == SUBREG)
3399 x0 = SUBREG_REG (x0);
3401 if (GET_CODE (x0) != REG)
3402 break;
3404 regno0 = REGNO (x0);
3405 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3406 break;
3408 switch (GET_CODE (x1))
3410 default:
3411 break;
3413 case SUBREG:
3414 x1 = SUBREG_REG (x1);
3415 if (GET_CODE (x1) != REG)
3416 break;
3418 /* Fall through. */
3420 case REG:
3421 /* Do not allow reg+reg addressing for modes > 1 word if we
3422 can't depend on having move double instructions. */
3423 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3424 ret = FALSE;
3425 else
3426 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3427 break;
3429 case CONST_INT:
3430 /* 12-bit immediate */
3431 if (condexec_p)
3432 ret = FALSE;
3433 else
3435 value = INTVAL (x1);
3436 ret = IN_RANGE (value, -2048, 2047);
3438 /* If we can't use load/store double operations, make sure we can
3439 address the second word. */
3440 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3441 ret = IN_RANGE (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3443 break;
3445 case CONST:
3446 if (!condexec_p && got12_operand (x1, VOIDmode))
3447 ret = TRUE;
3448 break;
3451 break;
3454 if (TARGET_DEBUG_ADDR)
3456 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3457 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3458 (condexec_p) ? ", inside conditional code" : "");
3459 debug_rtx (x);
3462 return ret;
3465 bool
3466 frv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
3468 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3471 /* Given an ADDR, generate code to inline the PLT. */
3472 static rtx
3473 gen_inlined_tls_plt (rtx addr)
3475 rtx retval, dest;
3476 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3479 dest = gen_reg_rtx (DImode);
3481 if (flag_pic == 1)
3484 -fpic version:
3486 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3487 calll #gettlsoff(ADDR)@(gr8, gr0)
3489 emit_insn (gen_tls_lddi (dest, addr, picreg));
3491 else
3494 -fPIC version:
3496 sethi.p #gottlsdeschi(ADDR), gr8
3497 setlo #gottlsdesclo(ADDR), gr8
3498 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3499 calll #gettlsoff(ADDR)@(gr8, gr0)
3501 rtx reguse = gen_reg_rtx (Pmode);
3502 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3503 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3506 retval = gen_reg_rtx (Pmode);
3507 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3508 return retval;
3511 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3512 the destination address. */
3513 static rtx
3514 gen_tlsmoff (rtx addr, rtx reg)
3516 rtx dest = gen_reg_rtx (Pmode);
3518 if (TARGET_BIG_TLS)
3520 /* sethi.p #tlsmoffhi(x), grA
3521 setlo #tlsmofflo(x), grA
3523 dest = gen_reg_rtx (Pmode);
3524 emit_insn (gen_tlsoff_hilo (dest, addr,
3525 GEN_INT (R_FRV_TLSMOFFHI)));
3526 dest = gen_rtx_PLUS (Pmode, dest, reg);
3528 else
3530 /* addi grB, #tlsmoff12(x), grC
3531 -or-
3532 ld/st @(grB, #tlsmoff12(x)), grC
3534 dest = gen_reg_rtx (Pmode);
3535 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3536 GEN_INT (R_FRV_TLSMOFF12)));
3538 return dest;
3541 /* Generate code for a TLS address. */
3542 static rtx
3543 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3545 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3546 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3548 switch (model)
3550 case TLS_MODEL_INITIAL_EXEC:
3551 if (flag_pic == 1)
3553 /* -fpic version.
3554 ldi @(gr15, #gottlsoff12(x)), gr5
3556 dest = gen_reg_rtx (Pmode);
3557 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3558 dest = gen_rtx_PLUS (Pmode, tp, dest);
3560 else
3562 /* -fPIC or anything else.
3564 sethi.p #gottlsoffhi(x), gr14
3565 setlo #gottlsofflo(x), gr14
3566 ld #tlsoff(x)@(gr15, gr14), gr9
3568 rtx tmp = gen_reg_rtx (Pmode);
3569 dest = gen_reg_rtx (Pmode);
3570 emit_insn (gen_tlsoff_hilo (tmp, addr,
3571 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3573 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3574 dest = gen_rtx_PLUS (Pmode, tp, dest);
3576 break;
3577 case TLS_MODEL_LOCAL_DYNAMIC:
3579 rtx reg, retval;
3581 if (TARGET_INLINE_PLT)
3582 retval = gen_inlined_tls_plt (GEN_INT (0));
3583 else
3585 /* call #gettlsoff(0) */
3586 retval = gen_reg_rtx (Pmode);
3587 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3590 reg = gen_reg_rtx (Pmode);
3591 emit_insn (gen_rtx_SET (reg, gen_rtx_PLUS (Pmode, retval, tp)));
3593 dest = gen_tlsmoff (addr, reg);
3596 dest = gen_reg_rtx (Pmode);
3597 emit_insn (gen_tlsoff_hilo (dest, addr,
3598 GEN_INT (R_FRV_TLSMOFFHI)));
3599 dest = gen_rtx_PLUS (Pmode, dest, reg);
3601 break;
3603 case TLS_MODEL_LOCAL_EXEC:
3604 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3605 break;
3606 case TLS_MODEL_GLOBAL_DYNAMIC:
3608 rtx retval;
3610 if (TARGET_INLINE_PLT)
3611 retval = gen_inlined_tls_plt (addr);
3612 else
3614 /* call #gettlsoff(x) */
3615 retval = gen_reg_rtx (Pmode);
3616 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3618 dest = gen_rtx_PLUS (Pmode, retval, tp);
3619 break;
3621 default:
3622 gcc_unreachable ();
3625 return dest;
3629 frv_legitimize_address (rtx x,
3630 rtx oldx ATTRIBUTE_UNUSED,
3631 machine_mode mode ATTRIBUTE_UNUSED)
3633 if (GET_CODE (x) == SYMBOL_REF)
3635 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3636 if (model != 0)
3637 return frv_legitimize_tls_address (x, model);
3640 return x;
3643 /* Test whether a local function descriptor is canonical, i.e.,
3644 whether we can use FUNCDESC_GOTOFF to compute the address of the
3645 function. */
3647 static bool
3648 frv_local_funcdesc_p (rtx fnx)
3650 tree fn;
3651 enum symbol_visibility vis;
3652 bool ret;
3654 if (! SYMBOL_REF_LOCAL_P (fnx))
3655 return FALSE;
3657 fn = SYMBOL_REF_DECL (fnx);
3659 if (! fn)
3660 return FALSE;
3662 vis = DECL_VISIBILITY (fn);
3664 if (vis == VISIBILITY_PROTECTED)
3665 /* Private function descriptors for protected functions are not
3666 canonical. Temporarily change the visibility to global. */
3667 vis = VISIBILITY_DEFAULT;
3668 else if (flag_shlib)
3669 /* If we're already compiling for a shared library (that, unlike
3670 executables, can't assume that the existence of a definition
3671 implies local binding), we can skip the re-testing. */
3672 return TRUE;
3674 ret = default_binds_local_p_1 (fn, flag_pic);
3676 DECL_VISIBILITY (fn) = vis;
3678 return ret;
3681 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3682 register. */
3685 frv_gen_GPsym2reg (rtx dest, rtx src)
3687 tree gp = get_identifier ("_gp");
3688 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3690 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3693 static const char *
3694 unspec_got_name (int i)
3696 switch (i)
3698 case R_FRV_GOT12: return "got12";
3699 case R_FRV_GOTHI: return "gothi";
3700 case R_FRV_GOTLO: return "gotlo";
3701 case R_FRV_FUNCDESC: return "funcdesc";
3702 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3703 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3704 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3705 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3706 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3707 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3708 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3709 case R_FRV_GOTOFF12: return "gotoff12";
3710 case R_FRV_GOTOFFHI: return "gotoffhi";
3711 case R_FRV_GOTOFFLO: return "gotofflo";
3712 case R_FRV_GPREL12: return "gprel12";
3713 case R_FRV_GPRELHI: return "gprelhi";
3714 case R_FRV_GPRELLO: return "gprello";
3715 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3716 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3717 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3718 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3719 case R_FRV_TLSMOFF12: return "tlsmoff12";
3720 case R_FRV_TLSDESCHI: return "tlsdeschi";
3721 case R_FRV_TLSDESCLO: return "tlsdesclo";
3722 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3723 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3724 default: gcc_unreachable ();
3728 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3729 is added inside the relocation operator. */
3731 static void
3732 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3734 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3735 output_addr_const (stream, plus_constant (Pmode, unspec->symbol,
3736 unspec->offset));
3737 fputs (")", stream);
3740 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3741 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3742 otherwise return ORIG_X. */
3745 frv_find_base_term (rtx x)
3747 struct frv_unspec unspec;
3749 if (frv_const_unspec_p (x, &unspec)
3750 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3751 return plus_constant (Pmode, unspec.symbol, unspec.offset);
3753 return x;
3756 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3757 the operand is used by a predicated instruction. */
3760 frv_legitimate_memory_operand (rtx op, machine_mode mode, int condexec_p)
3762 return ((GET_MODE (op) == mode || mode == VOIDmode)
3763 && GET_CODE (op) == MEM
3764 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3765 reload_completed, condexec_p, FALSE));
3768 void
3769 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3771 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3772 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3773 rtx c, rvrtx=0;
3774 rtx addr;
3776 if (ret_value)
3778 rvrtx = operands[0];
3779 operands ++;
3782 addr = XEXP (operands[0], 0);
3784 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3785 any calls that would involve a PLT, but can't tell, since we
3786 don't know whether an extern function is going to be provided by
3787 a separate translation unit or imported from a separate module.
3788 When compiling for shared libraries, if the function has default
3789 visibility, we assume it's overridable, so we inline the PLT, but
3790 for executables, we don't really have a way to make a good
3791 decision: a function is as likely to be imported from a shared
3792 library as it is to be defined in the executable itself. We
3793 assume executables will get global functions defined locally,
3794 whereas shared libraries will have them potentially overridden,
3795 so we only inline PLTs when compiling for shared libraries.
3797 In order to mark a function as local to a shared library, any
3798 non-default visibility attribute suffices. Unfortunately,
3799 there's no simple way to tag a function declaration as ``in a
3800 different module'', which we could then use to trigger PLT
3801 inlining on executables. There's -minline-plt, but it affects
3802 all external functions, so one would have to also mark function
3803 declarations available in the same module with non-default
3804 visibility, which is advantageous in itself. */
3805 if (GET_CODE (addr) == SYMBOL_REF
3806 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3807 || sibcall))
3809 rtx x, dest;
3810 dest = gen_reg_rtx (SImode);
3811 if (flag_pic != 1)
3812 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3813 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3814 else
3815 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3816 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3817 emit_insn (x);
3818 crtl->uses_pic_offset_table = TRUE;
3819 addr = dest;
3821 else if (GET_CODE (addr) == SYMBOL_REF)
3823 /* These are always either local, or handled through a local
3824 PLT. */
3825 if (ret_value)
3826 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3827 operands[2], picreg, lr);
3828 else
3829 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3830 emit_call_insn (c);
3831 return;
3833 else if (! ldd_address_operand (addr, Pmode))
3834 addr = force_reg (Pmode, addr);
3836 picreg = gen_reg_rtx (DImode);
3837 emit_insn (gen_movdi_ldd (picreg, addr));
3839 if (sibcall && ret_value)
3840 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3841 else if (sibcall)
3842 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3843 else if (ret_value)
3844 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3845 else
3846 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3847 emit_call_insn (c);
3850 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3851 process these separately from any offsets, such that we add any
3852 offsets to the function descriptor (the actual pointer), not to the
3853 function address. */
3855 static bool
3856 frv_function_symbol_referenced_p (rtx x)
3858 const char *format;
3859 int length;
3860 int j;
3862 if (GET_CODE (x) == SYMBOL_REF)
3863 return SYMBOL_REF_FUNCTION_P (x);
3865 length = GET_RTX_LENGTH (GET_CODE (x));
3866 format = GET_RTX_FORMAT (GET_CODE (x));
3868 for (j = 0; j < length; ++j)
3870 switch (format[j])
3872 case 'e':
3873 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3874 return TRUE;
3875 break;
3877 case 'V':
3878 case 'E':
3879 if (XVEC (x, j) != 0)
3881 int k;
3882 for (k = 0; k < XVECLEN (x, j); ++k)
3883 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3884 return TRUE;
3886 break;
3888 default:
3889 /* Nothing to do. */
3890 break;
3894 return FALSE;
3897 /* Return true if the memory operand is one that can be conditionally
3898 executed. */
3901 condexec_memory_operand (rtx op, machine_mode mode)
3903 machine_mode op_mode = GET_MODE (op);
3904 rtx addr;
3906 if (mode != VOIDmode && op_mode != mode)
3907 return FALSE;
3909 switch (op_mode)
3911 default:
3912 return FALSE;
3914 case QImode:
3915 case HImode:
3916 case SImode:
3917 case SFmode:
3918 break;
3921 if (GET_CODE (op) != MEM)
3922 return FALSE;
3924 addr = XEXP (op, 0);
3925 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3928 /* Return true if the bare return instruction can be used outside of the
3929 epilog code. For frv, we only do it if there was no stack allocation. */
3932 direct_return_p (void)
3934 frv_stack_t *info;
3936 if (!reload_completed)
3937 return FALSE;
3939 info = frv_stack_info ();
3940 return (info->total_size == 0);
3944 void
3945 frv_emit_move (machine_mode mode, rtx dest, rtx src)
3947 if (GET_CODE (src) == SYMBOL_REF)
3949 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3950 if (model != 0)
3951 src = frv_legitimize_tls_address (src, model);
3954 switch (mode)
3956 case SImode:
3957 if (frv_emit_movsi (dest, src))
3958 return;
3959 break;
3961 case QImode:
3962 case HImode:
3963 case DImode:
3964 case SFmode:
3965 case DFmode:
3966 if (!reload_in_progress
3967 && !reload_completed
3968 && !register_operand (dest, mode)
3969 && !reg_or_0_operand (src, mode))
3970 src = copy_to_mode_reg (mode, src);
3971 break;
3973 default:
3974 gcc_unreachable ();
3977 emit_insn (gen_rtx_SET (dest, src));
3980 /* Emit code to handle a MOVSI, adding in the small data register or pic
3981 register if needed to load up addresses. Return TRUE if the appropriate
3982 instructions are emitted. */
3985 frv_emit_movsi (rtx dest, rtx src)
3987 int base_regno = -1;
3988 int unspec = 0;
3989 rtx sym = src;
3990 struct frv_unspec old_unspec;
3992 if (!reload_in_progress
3993 && !reload_completed
3994 && !register_operand (dest, SImode)
3995 && (!reg_or_0_operand (src, SImode)
3996 /* Virtual registers will almost always be replaced by an
3997 add instruction, so expose this to CSE by copying to
3998 an intermediate register. */
3999 || (GET_CODE (src) == REG
4000 && IN_RANGE (REGNO (src),
4001 FIRST_VIRTUAL_REGISTER,
4002 LAST_VIRTUAL_POINTER_REGISTER))))
4004 emit_insn (gen_rtx_SET (dest, copy_to_mode_reg (SImode, src)));
4005 return TRUE;
4008 /* Explicitly add in the PIC or small data register if needed. */
4009 switch (GET_CODE (src))
4011 default:
4012 break;
4014 case LABEL_REF:
4015 handle_label:
4016 if (TARGET_FDPIC)
4018 /* Using GPREL12, we use a single GOT entry for all symbols
4019 in read-only sections, but trade sequences such as:
4021 sethi #gothi(label), gr#
4022 setlo #gotlo(label), gr#
4023 ld @(gr15,gr#), gr#
4027 ld @(gr15,#got12(_gp)), gr#
4028 sethi #gprelhi(label), gr##
4029 setlo #gprello(label), gr##
4030 add gr#, gr##, gr##
4032 We may often be able to share gr# for multiple
4033 computations of GPREL addresses, and we may often fold
4034 the final add into the pair of registers of a load or
4035 store instruction, so it's often profitable. Even when
4036 optimizing for size, we're trading a GOT entry for an
4037 additional instruction, which trades GOT space
4038 (read-write) for code size (read-only, shareable), as
4039 long as the symbol is not used in more than two different
4040 locations.
4042 With -fpie/-fpic, we'd be trading a single load for a
4043 sequence of 4 instructions, because the offset of the
4044 label can't be assumed to be addressable with 12 bits, so
4045 we don't do this. */
4046 if (TARGET_GPREL_RO)
4047 unspec = R_FRV_GPREL12;
4048 else
4049 unspec = R_FRV_GOT12;
4051 else if (flag_pic)
4052 base_regno = PIC_REGNO;
4054 break;
4056 case CONST:
4057 if (frv_const_unspec_p (src, &old_unspec))
4058 break;
4060 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4062 handle_whatever:
4063 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4064 emit_move_insn (dest, src);
4065 return TRUE;
4067 else
4069 sym = XEXP (sym, 0);
4070 if (GET_CODE (sym) == PLUS
4071 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4072 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4073 sym = XEXP (sym, 0);
4074 if (GET_CODE (sym) == SYMBOL_REF)
4075 goto handle_sym;
4076 else if (GET_CODE (sym) == LABEL_REF)
4077 goto handle_label;
4078 else
4079 goto handle_whatever;
4081 break;
4083 case SYMBOL_REF:
4084 handle_sym:
4085 if (TARGET_FDPIC)
4087 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4089 if (model != 0)
4091 src = frv_legitimize_tls_address (src, model);
4092 emit_move_insn (dest, src);
4093 return TRUE;
4096 if (SYMBOL_REF_FUNCTION_P (sym))
4098 if (frv_local_funcdesc_p (sym))
4099 unspec = R_FRV_FUNCDESC_GOTOFF12;
4100 else
4101 unspec = R_FRV_FUNCDESC_GOT12;
4103 else
4105 if (CONSTANT_POOL_ADDRESS_P (sym))
4106 switch (GET_CODE (get_pool_constant (sym)))
4108 case CONST:
4109 case SYMBOL_REF:
4110 case LABEL_REF:
4111 if (flag_pic)
4113 unspec = R_FRV_GOTOFF12;
4114 break;
4116 /* Fall through. */
4117 default:
4118 if (TARGET_GPREL_RO)
4119 unspec = R_FRV_GPREL12;
4120 else
4121 unspec = R_FRV_GOT12;
4122 break;
4124 else if (SYMBOL_REF_LOCAL_P (sym)
4125 && !SYMBOL_REF_EXTERNAL_P (sym)
4126 && SYMBOL_REF_DECL (sym)
4127 && (!DECL_P (SYMBOL_REF_DECL (sym))
4128 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4130 tree decl = SYMBOL_REF_DECL (sym);
4131 tree init = TREE_CODE (decl) == VAR_DECL
4132 ? DECL_INITIAL (decl)
4133 : TREE_CODE (decl) == CONSTRUCTOR
4134 ? decl : 0;
4135 int reloc = 0;
4136 bool named_section, readonly;
4138 if (init && init != error_mark_node)
4139 reloc = compute_reloc_for_constant (init);
4141 named_section = TREE_CODE (decl) == VAR_DECL
4142 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4143 readonly = decl_readonly_section (decl, reloc);
4145 if (named_section)
4146 unspec = R_FRV_GOT12;
4147 else if (!readonly)
4148 unspec = R_FRV_GOTOFF12;
4149 else if (readonly && TARGET_GPREL_RO)
4150 unspec = R_FRV_GPREL12;
4151 else
4152 unspec = R_FRV_GOT12;
4154 else
4155 unspec = R_FRV_GOT12;
4159 else if (SYMBOL_REF_SMALL_P (sym))
4160 base_regno = SDA_BASE_REG;
4162 else if (flag_pic)
4163 base_regno = PIC_REGNO;
4165 break;
4168 if (base_regno >= 0)
4170 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4171 emit_insn (gen_symGOTOFF2reg (dest, src,
4172 gen_rtx_REG (Pmode, base_regno),
4173 GEN_INT (R_FRV_GPREL12)));
4174 else
4175 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4176 gen_rtx_REG (Pmode, base_regno),
4177 GEN_INT (R_FRV_GPREL12)));
4178 if (base_regno == PIC_REGNO)
4179 crtl->uses_pic_offset_table = TRUE;
4180 return TRUE;
4183 if (unspec)
4185 rtx x;
4187 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4188 new uses of it once reload has begun. */
4189 gcc_assert (!reload_in_progress && !reload_completed);
4191 switch (unspec)
4193 case R_FRV_GOTOFF12:
4194 if (!frv_small_data_reloc_p (sym, unspec))
4195 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4196 GEN_INT (unspec));
4197 else
4198 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4199 break;
4200 case R_FRV_GPREL12:
4201 if (!frv_small_data_reloc_p (sym, unspec))
4202 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4203 GEN_INT (unspec));
4204 else
4205 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4206 break;
4207 case R_FRV_FUNCDESC_GOTOFF12:
4208 if (flag_pic != 1)
4209 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4210 GEN_INT (unspec));
4211 else
4212 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4213 break;
4214 default:
4215 if (flag_pic != 1)
4216 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4217 GEN_INT (unspec));
4218 else
4219 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4220 break;
4222 emit_insn (x);
4223 crtl->uses_pic_offset_table = TRUE;
4224 return TRUE;
4228 return FALSE;
4232 /* Return a string to output a single word move. */
4234 const char *
4235 output_move_single (rtx operands[], rtx insn)
4237 rtx dest = operands[0];
4238 rtx src = operands[1];
4240 if (GET_CODE (dest) == REG)
4242 int dest_regno = REGNO (dest);
4243 machine_mode mode = GET_MODE (dest);
4245 if (GPR_P (dest_regno))
4247 if (GET_CODE (src) == REG)
4249 /* gpr <- some sort of register */
4250 int src_regno = REGNO (src);
4252 if (GPR_P (src_regno))
4253 return "mov %1, %0";
4255 else if (FPR_P (src_regno))
4256 return "movfg %1, %0";
4258 else if (SPR_P (src_regno))
4259 return "movsg %1, %0";
4262 else if (GET_CODE (src) == MEM)
4264 /* gpr <- memory */
4265 switch (mode)
4267 default:
4268 break;
4270 case QImode:
4271 return "ldsb%I1%U1 %M1,%0";
4273 case HImode:
4274 return "ldsh%I1%U1 %M1,%0";
4276 case SImode:
4277 case SFmode:
4278 return "ld%I1%U1 %M1, %0";
4282 else if (GET_CODE (src) == CONST_INT
4283 || GET_CODE (src) == CONST_DOUBLE)
4285 /* gpr <- integer/floating constant */
4286 HOST_WIDE_INT value;
4288 if (GET_CODE (src) == CONST_INT)
4289 value = INTVAL (src);
4291 else if (mode == SFmode)
4293 REAL_VALUE_TYPE rv;
4294 long l;
4296 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4297 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4298 value = l;
4301 else
4302 value = CONST_DOUBLE_LOW (src);
4304 if (IN_RANGE (value, -32768, 32767))
4305 return "setlos %1, %0";
4307 return "#";
4310 else if (GET_CODE (src) == SYMBOL_REF
4311 || GET_CODE (src) == LABEL_REF
4312 || GET_CODE (src) == CONST)
4314 return "#";
4318 else if (FPR_P (dest_regno))
4320 if (GET_CODE (src) == REG)
4322 /* fpr <- some sort of register */
4323 int src_regno = REGNO (src);
4325 if (GPR_P (src_regno))
4326 return "movgf %1, %0";
4328 else if (FPR_P (src_regno))
4330 if (TARGET_HARD_FLOAT)
4331 return "fmovs %1, %0";
4332 else
4333 return "mor %1, %1, %0";
4337 else if (GET_CODE (src) == MEM)
4339 /* fpr <- memory */
4340 switch (mode)
4342 default:
4343 break;
4345 case QImode:
4346 return "ldbf%I1%U1 %M1,%0";
4348 case HImode:
4349 return "ldhf%I1%U1 %M1,%0";
4351 case SImode:
4352 case SFmode:
4353 return "ldf%I1%U1 %M1, %0";
4357 else if (ZERO_P (src))
4358 return "movgf %., %0";
4361 else if (SPR_P (dest_regno))
4363 if (GET_CODE (src) == REG)
4365 /* spr <- some sort of register */
4366 int src_regno = REGNO (src);
4368 if (GPR_P (src_regno))
4369 return "movgs %1, %0";
4371 else if (ZERO_P (src))
4372 return "movgs %., %0";
4376 else if (GET_CODE (dest) == MEM)
4378 if (GET_CODE (src) == REG)
4380 int src_regno = REGNO (src);
4381 machine_mode mode = GET_MODE (dest);
4383 if (GPR_P (src_regno))
4385 switch (mode)
4387 default:
4388 break;
4390 case QImode:
4391 return "stb%I0%U0 %1, %M0";
4393 case HImode:
4394 return "sth%I0%U0 %1, %M0";
4396 case SImode:
4397 case SFmode:
4398 return "st%I0%U0 %1, %M0";
4402 else if (FPR_P (src_regno))
4404 switch (mode)
4406 default:
4407 break;
4409 case QImode:
4410 return "stbf%I0%U0 %1, %M0";
4412 case HImode:
4413 return "sthf%I0%U0 %1, %M0";
4415 case SImode:
4416 case SFmode:
4417 return "stf%I0%U0 %1, %M0";
4422 else if (ZERO_P (src))
4424 switch (GET_MODE (dest))
4426 default:
4427 break;
4429 case QImode:
4430 return "stb%I0%U0 %., %M0";
4432 case HImode:
4433 return "sth%I0%U0 %., %M0";
4435 case SImode:
4436 case SFmode:
4437 return "st%I0%U0 %., %M0";
4442 fatal_insn ("bad output_move_single operand", insn);
4443 return "";
4447 /* Return a string to output a double word move. */
4449 const char *
4450 output_move_double (rtx operands[], rtx insn)
4452 rtx dest = operands[0];
4453 rtx src = operands[1];
4454 machine_mode mode = GET_MODE (dest);
4456 if (GET_CODE (dest) == REG)
4458 int dest_regno = REGNO (dest);
4460 if (GPR_P (dest_regno))
4462 if (GET_CODE (src) == REG)
4464 /* gpr <- some sort of register */
4465 int src_regno = REGNO (src);
4467 if (GPR_P (src_regno))
4468 return "#";
4470 else if (FPR_P (src_regno))
4472 if (((dest_regno - GPR_FIRST) & 1) == 0
4473 && ((src_regno - FPR_FIRST) & 1) == 0)
4474 return "movfgd %1, %0";
4476 return "#";
4480 else if (GET_CODE (src) == MEM)
4482 /* gpr <- memory */
4483 if (dbl_memory_one_insn_operand (src, mode))
4484 return "ldd%I1%U1 %M1, %0";
4486 return "#";
4489 else if (GET_CODE (src) == CONST_INT
4490 || GET_CODE (src) == CONST_DOUBLE)
4491 return "#";
4494 else if (FPR_P (dest_regno))
4496 if (GET_CODE (src) == REG)
4498 /* fpr <- some sort of register */
4499 int src_regno = REGNO (src);
4501 if (GPR_P (src_regno))
4503 if (((dest_regno - FPR_FIRST) & 1) == 0
4504 && ((src_regno - GPR_FIRST) & 1) == 0)
4505 return "movgfd %1, %0";
4507 return "#";
4510 else if (FPR_P (src_regno))
4512 if (TARGET_DOUBLE
4513 && ((dest_regno - FPR_FIRST) & 1) == 0
4514 && ((src_regno - FPR_FIRST) & 1) == 0)
4515 return "fmovd %1, %0";
4517 return "#";
4521 else if (GET_CODE (src) == MEM)
4523 /* fpr <- memory */
4524 if (dbl_memory_one_insn_operand (src, mode))
4525 return "lddf%I1%U1 %M1, %0";
4527 return "#";
4530 else if (ZERO_P (src))
4531 return "#";
4535 else if (GET_CODE (dest) == MEM)
4537 if (GET_CODE (src) == REG)
4539 int src_regno = REGNO (src);
4541 if (GPR_P (src_regno))
4543 if (((src_regno - GPR_FIRST) & 1) == 0
4544 && dbl_memory_one_insn_operand (dest, mode))
4545 return "std%I0%U0 %1, %M0";
4547 return "#";
4550 if (FPR_P (src_regno))
4552 if (((src_regno - FPR_FIRST) & 1) == 0
4553 && dbl_memory_one_insn_operand (dest, mode))
4554 return "stdf%I0%U0 %1, %M0";
4556 return "#";
4560 else if (ZERO_P (src))
4562 if (dbl_memory_one_insn_operand (dest, mode))
4563 return "std%I0%U0 %., %M0";
4565 return "#";
4569 fatal_insn ("bad output_move_double operand", insn);
4570 return "";
4574 /* Return a string to output a single word conditional move.
4575 Operand0 -- EQ/NE of ccr register and 0
4576 Operand1 -- CCR register
4577 Operand2 -- destination
4578 Operand3 -- source */
4580 const char *
4581 output_condmove_single (rtx operands[], rtx insn)
4583 rtx dest = operands[2];
4584 rtx src = operands[3];
4586 if (GET_CODE (dest) == REG)
4588 int dest_regno = REGNO (dest);
4589 machine_mode mode = GET_MODE (dest);
4591 if (GPR_P (dest_regno))
4593 if (GET_CODE (src) == REG)
4595 /* gpr <- some sort of register */
4596 int src_regno = REGNO (src);
4598 if (GPR_P (src_regno))
4599 return "cmov %z3, %2, %1, %e0";
4601 else if (FPR_P (src_regno))
4602 return "cmovfg %3, %2, %1, %e0";
4605 else if (GET_CODE (src) == MEM)
4607 /* gpr <- memory */
4608 switch (mode)
4610 default:
4611 break;
4613 case QImode:
4614 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4616 case HImode:
4617 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4619 case SImode:
4620 case SFmode:
4621 return "cld%I3%U3 %M3, %2, %1, %e0";
4625 else if (ZERO_P (src))
4626 return "cmov %., %2, %1, %e0";
4629 else if (FPR_P (dest_regno))
4631 if (GET_CODE (src) == REG)
4633 /* fpr <- some sort of register */
4634 int src_regno = REGNO (src);
4636 if (GPR_P (src_regno))
4637 return "cmovgf %3, %2, %1, %e0";
4639 else if (FPR_P (src_regno))
4641 if (TARGET_HARD_FLOAT)
4642 return "cfmovs %3,%2,%1,%e0";
4643 else
4644 return "cmor %3, %3, %2, %1, %e0";
4648 else if (GET_CODE (src) == MEM)
4650 /* fpr <- memory */
4651 if (mode == SImode || mode == SFmode)
4652 return "cldf%I3%U3 %M3, %2, %1, %e0";
4655 else if (ZERO_P (src))
4656 return "cmovgf %., %2, %1, %e0";
4660 else if (GET_CODE (dest) == MEM)
4662 if (GET_CODE (src) == REG)
4664 int src_regno = REGNO (src);
4665 machine_mode mode = GET_MODE (dest);
4667 if (GPR_P (src_regno))
4669 switch (mode)
4671 default:
4672 break;
4674 case QImode:
4675 return "cstb%I2%U2 %3, %M2, %1, %e0";
4677 case HImode:
4678 return "csth%I2%U2 %3, %M2, %1, %e0";
4680 case SImode:
4681 case SFmode:
4682 return "cst%I2%U2 %3, %M2, %1, %e0";
4686 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4687 return "cstf%I2%U2 %3, %M2, %1, %e0";
4690 else if (ZERO_P (src))
4692 machine_mode mode = GET_MODE (dest);
4693 switch (mode)
4695 default:
4696 break;
4698 case QImode:
4699 return "cstb%I2%U2 %., %M2, %1, %e0";
4701 case HImode:
4702 return "csth%I2%U2 %., %M2, %1, %e0";
4704 case SImode:
4705 case SFmode:
4706 return "cst%I2%U2 %., %M2, %1, %e0";
4711 fatal_insn ("bad output_condmove_single operand", insn);
4712 return "";
4716 /* Emit the appropriate code to do a comparison, returning the register the
4717 comparison was done it. */
4719 static rtx
4720 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4722 machine_mode cc_mode;
4723 rtx cc_reg;
4725 /* Floating point doesn't have comparison against a constant. */
4726 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4727 op1 = force_reg (GET_MODE (op0), op1);
4729 /* Possibly disable using anything but a fixed register in order to work
4730 around cse moving comparisons past function calls. */
4731 cc_mode = SELECT_CC_MODE (test, op0, op1);
4732 cc_reg = ((TARGET_ALLOC_CC)
4733 ? gen_reg_rtx (cc_mode)
4734 : gen_rtx_REG (cc_mode,
4735 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4737 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (cc_mode, op0, op1)));
4739 return cc_reg;
4743 /* Emit code for a conditional branch.
4744 XXX: I originally wanted to add a clobber of a CCR register to use in
4745 conditional execution, but that confuses the rest of the compiler. */
4748 frv_emit_cond_branch (rtx operands[])
4750 rtx test_rtx;
4751 rtx label_ref;
4752 rtx if_else;
4753 enum rtx_code test = GET_CODE (operands[0]);
4754 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4755 machine_mode cc_mode = GET_MODE (cc_reg);
4757 /* Branches generate:
4758 (set (pc)
4759 (if_then_else (<test>, <cc_reg>, (const_int 0))
4760 (label_ref <branch_label>)
4761 (pc))) */
4762 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4763 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4764 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4765 emit_jump_insn (gen_rtx_SET (pc_rtx, if_else));
4766 return TRUE;
4770 /* Emit code to set a gpr to 1/0 based on a comparison. */
4773 frv_emit_scc (rtx operands[])
4775 rtx set;
4776 rtx test_rtx;
4777 rtx clobber;
4778 rtx cr_reg;
4779 enum rtx_code test = GET_CODE (operands[1]);
4780 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4782 /* SCC instructions generate:
4783 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4784 (clobber (<ccr_reg>))]) */
4785 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4786 set = gen_rtx_SET (operands[0], test_rtx);
4788 cr_reg = ((TARGET_ALLOC_CC)
4789 ? gen_reg_rtx (CC_CCRmode)
4790 : gen_rtx_REG (CC_CCRmode,
4791 ((GET_MODE (cc_reg) == CC_FPmode)
4792 ? FCR_FIRST
4793 : ICR_FIRST)));
4795 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4796 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4797 return TRUE;
4801 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4802 the separate insns. */
4805 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4807 rtx ret;
4809 start_sequence ();
4811 /* Set the appropriate CCR bit. */
4812 emit_insn (gen_rtx_SET (cr_reg,
4813 gen_rtx_fmt_ee (GET_CODE (test),
4814 GET_MODE (cr_reg),
4815 cc_reg,
4816 const0_rtx)));
4818 /* Move the value into the destination. */
4819 emit_move_insn (dest, GEN_INT (value));
4821 /* Move 0 into the destination if the test failed */
4822 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4823 gen_rtx_EQ (GET_MODE (cr_reg),
4824 cr_reg,
4825 const0_rtx),
4826 gen_rtx_SET (dest, const0_rtx)));
4828 /* Finish up, return sequence. */
4829 ret = get_insns ();
4830 end_sequence ();
4831 return ret;
4835 /* Emit the code for a conditional move, return TRUE if we could do the
4836 move. */
4839 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4841 rtx set;
4842 rtx clobber_cc;
4843 rtx test2;
4844 rtx cr_reg;
4845 rtx if_rtx;
4846 enum rtx_code test = GET_CODE (test_rtx);
4847 rtx cc_reg = frv_emit_comparison (test,
4848 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4849 machine_mode cc_mode = GET_MODE (cc_reg);
4851 /* Conditional move instructions generate:
4852 (parallel [(set <target>
4853 (if_then_else (<test> <cc_reg> (const_int 0))
4854 <src1>
4855 <src2>))
4856 (clobber (<ccr_reg>))]) */
4858 /* Handle various cases of conditional move involving two constants. */
4859 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4861 HOST_WIDE_INT value1 = INTVAL (src1);
4862 HOST_WIDE_INT value2 = INTVAL (src2);
4864 /* Having 0 as one of the constants can be done by loading the other
4865 constant, and optionally moving in gr0. */
4866 if (value1 == 0 || value2 == 0)
4869 /* If the first value is within an addi range and also the difference
4870 between the two fits in an addi's range, load up the difference, then
4871 conditionally move in 0, and then unconditionally add the first
4872 value. */
4873 else if (IN_RANGE (value1, -2048, 2047)
4874 && IN_RANGE (value2 - value1, -2048, 2047))
4877 /* If neither condition holds, just force the constant into a
4878 register. */
4879 else
4881 src1 = force_reg (GET_MODE (dest), src1);
4882 src2 = force_reg (GET_MODE (dest), src2);
4886 /* If one value is a register, insure the other value is either 0 or a
4887 register. */
4888 else
4890 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4891 src1 = force_reg (GET_MODE (dest), src1);
4893 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4894 src2 = force_reg (GET_MODE (dest), src2);
4897 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4898 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4900 set = gen_rtx_SET (dest, if_rtx);
4902 cr_reg = ((TARGET_ALLOC_CC)
4903 ? gen_reg_rtx (CC_CCRmode)
4904 : gen_rtx_REG (CC_CCRmode,
4905 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4907 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4908 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4909 return TRUE;
4913 /* Split a conditional move into constituent parts, returning a SEQUENCE
4914 containing all of the insns. */
4917 frv_split_cond_move (rtx operands[])
4919 rtx dest = operands[0];
4920 rtx test = operands[1];
4921 rtx cc_reg = operands[2];
4922 rtx src1 = operands[3];
4923 rtx src2 = operands[4];
4924 rtx cr_reg = operands[5];
4925 rtx ret;
4926 machine_mode cr_mode = GET_MODE (cr_reg);
4928 start_sequence ();
4930 /* Set the appropriate CCR bit. */
4931 emit_insn (gen_rtx_SET (cr_reg,
4932 gen_rtx_fmt_ee (GET_CODE (test),
4933 GET_MODE (cr_reg),
4934 cc_reg,
4935 const0_rtx)));
4937 /* Handle various cases of conditional move involving two constants. */
4938 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4940 HOST_WIDE_INT value1 = INTVAL (src1);
4941 HOST_WIDE_INT value2 = INTVAL (src2);
4943 /* Having 0 as one of the constants can be done by loading the other
4944 constant, and optionally moving in gr0. */
4945 if (value1 == 0)
4947 emit_move_insn (dest, src2);
4948 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4949 gen_rtx_NE (cr_mode, cr_reg,
4950 const0_rtx),
4951 gen_rtx_SET (dest, src1)));
4954 else if (value2 == 0)
4956 emit_move_insn (dest, src1);
4957 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4958 gen_rtx_EQ (cr_mode, cr_reg,
4959 const0_rtx),
4960 gen_rtx_SET (dest, src2)));
4963 /* If the first value is within an addi range and also the difference
4964 between the two fits in an addi's range, load up the difference, then
4965 conditionally move in 0, and then unconditionally add the first
4966 value. */
4967 else if (IN_RANGE (value1, -2048, 2047)
4968 && IN_RANGE (value2 - value1, -2048, 2047))
4970 rtx dest_si = ((GET_MODE (dest) == SImode)
4971 ? dest
4972 : gen_rtx_SUBREG (SImode, dest, 0));
4974 emit_move_insn (dest_si, GEN_INT (value2 - value1));
4975 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4976 gen_rtx_NE (cr_mode, cr_reg,
4977 const0_rtx),
4978 gen_rtx_SET (dest_si, const0_rtx)));
4979 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
4982 else
4983 gcc_unreachable ();
4985 else
4987 /* Emit the conditional move for the test being true if needed. */
4988 if (! rtx_equal_p (dest, src1))
4989 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4990 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
4991 gen_rtx_SET (dest, src1)));
4993 /* Emit the conditional move for the test being false if needed. */
4994 if (! rtx_equal_p (dest, src2))
4995 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4996 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
4997 gen_rtx_SET (dest, src2)));
5000 /* Finish up, return sequence. */
5001 ret = get_insns ();
5002 end_sequence ();
5003 return ret;
5007 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5008 memory location that is not known to be dword-aligned. */
5009 void
5010 frv_split_double_load (rtx dest, rtx source)
5012 int regno = REGNO (dest);
5013 rtx dest1 = gen_highpart (SImode, dest);
5014 rtx dest2 = gen_lowpart (SImode, dest);
5015 rtx address = XEXP (source, 0);
5017 /* If the address is pre-modified, load the lower-numbered register
5018 first, then load the other register using an integer offset from
5019 the modified base register. This order should always be safe,
5020 since the pre-modification cannot affect the same registers as the
5021 load does.
5023 The situation for other loads is more complicated. Loading one
5024 of the registers could affect the value of ADDRESS, so we must
5025 be careful which order we do them in. */
5026 if (GET_CODE (address) == PRE_MODIFY
5027 || ! refers_to_regno_p (regno, address))
5029 /* It is safe to load the lower-numbered register first. */
5030 emit_move_insn (dest1, change_address (source, SImode, NULL));
5031 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5033 else
5035 /* ADDRESS is not pre-modified and the address depends on the
5036 lower-numbered register. Load the higher-numbered register
5037 first. */
5038 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5039 emit_move_insn (dest1, change_address (source, SImode, NULL));
5043 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5044 and SOURCE is either a double register or the constant zero. */
5045 void
5046 frv_split_double_store (rtx dest, rtx source)
5048 rtx dest1 = change_address (dest, SImode, NULL);
5049 rtx dest2 = frv_index_memory (dest, SImode, 1);
5050 if (ZERO_P (source))
5052 emit_move_insn (dest1, CONST0_RTX (SImode));
5053 emit_move_insn (dest2, CONST0_RTX (SImode));
5055 else
5057 emit_move_insn (dest1, gen_highpart (SImode, source));
5058 emit_move_insn (dest2, gen_lowpart (SImode, source));
5063 /* Split a min/max operation returning a SEQUENCE containing all of the
5064 insns. */
5067 frv_split_minmax (rtx operands[])
5069 rtx dest = operands[0];
5070 rtx minmax = operands[1];
5071 rtx src1 = operands[2];
5072 rtx src2 = operands[3];
5073 rtx cc_reg = operands[4];
5074 rtx cr_reg = operands[5];
5075 rtx ret;
5076 enum rtx_code test_code;
5077 machine_mode cr_mode = GET_MODE (cr_reg);
5079 start_sequence ();
5081 /* Figure out which test to use. */
5082 switch (GET_CODE (minmax))
5084 default:
5085 gcc_unreachable ();
5087 case SMIN: test_code = LT; break;
5088 case SMAX: test_code = GT; break;
5089 case UMIN: test_code = LTU; break;
5090 case UMAX: test_code = GTU; break;
5093 /* Issue the compare instruction. */
5094 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (GET_MODE (cc_reg),
5095 src1, src2)));
5097 /* Set the appropriate CCR bit. */
5098 emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (test_code,
5099 GET_MODE (cr_reg),
5100 cc_reg,
5101 const0_rtx)));
5103 /* If are taking the min/max of a nonzero constant, load that first, and
5104 then do a conditional move of the other value. */
5105 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5107 gcc_assert (!rtx_equal_p (dest, src1));
5109 emit_move_insn (dest, src2);
5110 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5111 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5112 gen_rtx_SET (dest, src1)));
5115 /* Otherwise, do each half of the move. */
5116 else
5118 /* Emit the conditional move for the test being true if needed. */
5119 if (! rtx_equal_p (dest, src1))
5120 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5121 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5122 gen_rtx_SET (dest, src1)));
5124 /* Emit the conditional move for the test being false if needed. */
5125 if (! rtx_equal_p (dest, src2))
5126 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5127 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5128 gen_rtx_SET (dest, src2)));
5131 /* Finish up, return sequence. */
5132 ret = get_insns ();
5133 end_sequence ();
5134 return ret;
5138 /* Split an integer abs operation returning a SEQUENCE containing all of the
5139 insns. */
5142 frv_split_abs (rtx operands[])
5144 rtx dest = operands[0];
5145 rtx src = operands[1];
5146 rtx cc_reg = operands[2];
5147 rtx cr_reg = operands[3];
5148 rtx ret;
5150 start_sequence ();
5152 /* Issue the compare < 0 instruction. */
5153 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5155 /* Set the appropriate CCR bit. */
5156 emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (LT, CC_CCRmode,
5157 cc_reg, const0_rtx)));
5159 /* Emit the conditional negate if the value is negative. */
5160 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5161 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5162 gen_negsi2 (dest, src)));
5164 /* Emit the conditional move for the test being false if needed. */
5165 if (! rtx_equal_p (dest, src))
5166 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5167 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5168 gen_rtx_SET (dest, src)));
5170 /* Finish up, return sequence. */
5171 ret = get_insns ();
5172 end_sequence ();
5173 return ret;
5177 /* Initialize machine-specific if-conversion data.
5178 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5179 initialize the static storage. */
5180 void
5181 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED)
5183 frv_ifcvt.added_insns_list = NULL_RTX;
5184 frv_ifcvt.cur_scratch_regs = 0;
5185 frv_ifcvt.num_nested_cond_exec = 0;
5186 frv_ifcvt.cr_reg = NULL_RTX;
5187 frv_ifcvt.nested_cc_reg = NULL_RTX;
5188 frv_ifcvt.extra_int_cr = NULL_RTX;
5189 frv_ifcvt.extra_fp_cr = NULL_RTX;
5190 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5194 /* Internal function to add a potential insn to the list of insns to be inserted
5195 if the conditional execution conversion is successful. */
5197 static void
5198 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5200 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5202 link->jump = before_p; /* Mark to add this before or after insn. */
5203 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5204 frv_ifcvt.added_insns_list);
5206 if (TARGET_DEBUG_COND_EXEC)
5208 fprintf (stderr,
5209 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5210 (before_p) ? "before" : "after",
5211 (int)INSN_UID (insn));
5213 debug_rtx (pattern);
5218 /* A C expression to modify the code described by the conditional if
5219 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5220 FALSE_EXPR for converting if-then and if-then-else code to conditional
5221 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5222 tests cannot be converted. */
5224 void
5225 frv_ifcvt_modify_tests (ce_if_block *ce_info, rtx *p_true, rtx *p_false)
5227 basic_block test_bb = ce_info->test_bb; /* test basic block */
5228 basic_block then_bb = ce_info->then_bb; /* THEN */
5229 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5230 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5231 rtx true_expr = *p_true;
5232 rtx cr;
5233 rtx cc;
5234 rtx nested_cc;
5235 machine_mode mode = GET_MODE (true_expr);
5236 int j;
5237 basic_block *bb;
5238 int num_bb;
5239 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5240 rtx check_insn;
5241 rtx sub_cond_exec_reg;
5242 enum rtx_code code;
5243 enum rtx_code code_true;
5244 enum rtx_code code_false;
5245 enum reg_class cc_class;
5246 enum reg_class cr_class;
5247 int cc_first;
5248 int cc_last;
5249 reg_set_iterator rsi;
5251 /* Make sure we are only dealing with hard registers. Also honor the
5252 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5253 applicable. */
5254 if (!reload_completed || !TARGET_COND_EXEC
5255 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5256 goto fail;
5258 /* Figure out which registers we can allocate for our own purposes. Only
5259 consider registers that are not preserved across function calls and are
5260 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5261 if we did not need to use them in reloading other registers. */
5262 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5263 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5264 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5265 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5266 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5268 /* If this is a nested IF, we need to discover whether the CC registers that
5269 are set/used inside of the block are used anywhere else. If not, we can
5270 change them to be the CC register that is paired with the CR register that
5271 controls the outermost IF block. */
5272 if (ce_info->pass > 1)
5274 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5275 for (j = CC_FIRST; j <= CC_LAST; j++)
5276 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5278 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5279 continue;
5281 if (else_bb
5282 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5283 continue;
5285 if (join_bb
5286 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5287 continue;
5289 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5293 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5294 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5296 frv_ifcvt.added_insns_list = NULL_RTX;
5297 frv_ifcvt.cur_scratch_regs = 0;
5299 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5300 * sizeof (basic_block));
5302 if (join_bb)
5304 unsigned int regno;
5306 /* Remove anything live at the beginning of the join block from being
5307 available for allocation. */
5308 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5310 if (regno < FIRST_PSEUDO_REGISTER)
5311 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5315 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5316 num_bb = 0;
5317 if (ce_info->num_multiple_test_blocks)
5319 basic_block multiple_test_bb = ce_info->last_test_bb;
5321 while (multiple_test_bb != test_bb)
5323 bb[num_bb++] = multiple_test_bb;
5324 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5328 /* Add in the THEN and ELSE blocks to be scanned. */
5329 bb[num_bb++] = then_bb;
5330 if (else_bb)
5331 bb[num_bb++] = else_bb;
5333 sub_cond_exec_reg = NULL_RTX;
5334 frv_ifcvt.num_nested_cond_exec = 0;
5336 /* Scan all of the blocks for registers that must not be allocated. */
5337 for (j = 0; j < num_bb; j++)
5339 rtx_insn *last_insn = BB_END (bb[j]);
5340 rtx_insn *insn = BB_HEAD (bb[j]);
5341 unsigned int regno;
5343 if (dump_file)
5344 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5345 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5346 (int) bb[j]->index,
5347 (int) INSN_UID (BB_HEAD (bb[j])),
5348 (int) INSN_UID (BB_END (bb[j])));
5350 /* Anything live at the beginning of the block is obviously unavailable
5351 for allocation. */
5352 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5354 if (regno < FIRST_PSEUDO_REGISTER)
5355 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5358 /* Loop through the insns in the block. */
5359 for (;;)
5361 /* Mark any new registers that are created as being unavailable for
5362 allocation. Also see if the CC register used in nested IFs can be
5363 reallocated. */
5364 if (INSN_P (insn))
5366 rtx pattern;
5367 rtx set;
5368 int skip_nested_if = FALSE;
5369 HARD_REG_SET mentioned_regs;
5371 CLEAR_HARD_REG_SET (mentioned_regs);
5372 find_all_hard_regs (PATTERN (insn), &mentioned_regs);
5373 AND_COMPL_HARD_REG_SET (tmp_reg->regs, mentioned_regs);
5375 pattern = PATTERN (insn);
5376 if (GET_CODE (pattern) == COND_EXEC)
5378 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5380 if (reg != sub_cond_exec_reg)
5382 sub_cond_exec_reg = reg;
5383 frv_ifcvt.num_nested_cond_exec++;
5387 set = single_set_pattern (pattern);
5388 if (set)
5390 rtx dest = SET_DEST (set);
5391 rtx src = SET_SRC (set);
5393 if (GET_CODE (dest) == REG)
5395 int regno = REGNO (dest);
5396 enum rtx_code src_code = GET_CODE (src);
5398 if (CC_P (regno) && src_code == COMPARE)
5399 skip_nested_if = TRUE;
5401 else if (CR_P (regno)
5402 && (src_code == IF_THEN_ELSE
5403 || COMPARISON_P (src)))
5404 skip_nested_if = TRUE;
5408 if (! skip_nested_if)
5409 AND_COMPL_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite,
5410 mentioned_regs);
5413 if (insn == last_insn)
5414 break;
5416 insn = NEXT_INSN (insn);
5420 /* If this is a nested if, rewrite the CC registers that are available to
5421 include the ones that can be rewritten, to increase the chance of being
5422 able to allocate a paired CC/CR register combination. */
5423 if (ce_info->pass > 1)
5425 for (j = CC_FIRST; j <= CC_LAST; j++)
5426 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5427 SET_HARD_REG_BIT (tmp_reg->regs, j);
5428 else
5429 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5432 if (dump_file)
5434 int num_gprs = 0;
5435 fprintf (dump_file, "Available GPRs: ");
5437 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5438 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5440 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5441 if (++num_gprs > GPR_TEMP_NUM+2)
5442 break;
5445 fprintf (dump_file, "%s\nAvailable CRs: ",
5446 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5448 for (j = CR_FIRST; j <= CR_LAST; j++)
5449 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5450 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5452 fputs ("\n", dump_file);
5454 if (ce_info->pass > 1)
5456 fprintf (dump_file, "Modifiable CCs: ");
5457 for (j = CC_FIRST; j <= CC_LAST; j++)
5458 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5459 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5461 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5462 frv_ifcvt.num_nested_cond_exec);
5466 /* Allocate the appropriate temporary condition code register. Try to
5467 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5468 that conditional cmp's can be done. */
5469 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5471 cr_class = ICR_REGS;
5472 cc_class = ICC_REGS;
5473 cc_first = ICC_FIRST;
5474 cc_last = ICC_LAST;
5476 else if (mode == CC_FPmode)
5478 cr_class = FCR_REGS;
5479 cc_class = FCC_REGS;
5480 cc_first = FCC_FIRST;
5481 cc_last = FCC_LAST;
5483 else
5485 cc_first = cc_last = 0;
5486 cr_class = cc_class = NO_REGS;
5489 cc = XEXP (true_expr, 0);
5490 nested_cc = cr = NULL_RTX;
5491 if (cc_class != NO_REGS)
5493 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5494 so we can execute a csubcc/caddcc/cfcmps instruction. */
5495 int cc_regno;
5497 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5499 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5501 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5502 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5504 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5505 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5506 TRUE);
5508 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5509 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5510 TRUE, TRUE);
5511 break;
5516 if (! cr)
5518 if (dump_file)
5519 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5521 goto fail;
5524 if (dump_file)
5525 fprintf (dump_file,
5526 "Will use %s for conditional execution, %s for nested comparisons\n",
5527 reg_names[ REGNO (cr)],
5528 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5530 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5531 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5532 bit being true. We don't do this for floating point, because of NaNs. */
5533 code = GET_CODE (true_expr);
5534 if (GET_MODE (cc) != CC_FPmode)
5536 code = reverse_condition (code);
5537 code_true = EQ;
5538 code_false = NE;
5540 else
5542 code_true = NE;
5543 code_false = EQ;
5546 check_insn = gen_rtx_SET (cr, gen_rtx_fmt_ee (code, CC_CCRmode,
5547 cc, const0_rtx));
5549 /* Record the check insn to be inserted later. */
5550 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5552 /* Update the tests. */
5553 frv_ifcvt.cr_reg = cr;
5554 frv_ifcvt.nested_cc_reg = nested_cc;
5555 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5556 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5557 return;
5559 /* Fail, don't do this conditional execution. */
5560 fail:
5561 *p_true = NULL_RTX;
5562 *p_false = NULL_RTX;
5563 if (dump_file)
5564 fprintf (dump_file, "Disabling this conditional execution.\n");
5566 return;
5570 /* A C expression to modify the code described by the conditional if
5571 information CE_INFO, for the basic block BB, possibly updating the tests in
5572 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5573 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5574 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5576 /* p_true and p_false are given expressions of the form:
5578 (and (eq:CC_CCR (reg:CC_CCR)
5579 (const_int 0))
5580 (eq:CC (reg:CC)
5581 (const_int 0))) */
5583 void
5584 frv_ifcvt_modify_multiple_tests (ce_if_block *ce_info,
5585 basic_block bb,
5586 rtx *p_true,
5587 rtx *p_false)
5589 rtx old_true = XEXP (*p_true, 0);
5590 rtx old_false = XEXP (*p_false, 0);
5591 rtx true_expr = XEXP (*p_true, 1);
5592 rtx false_expr = XEXP (*p_false, 1);
5593 rtx test_expr;
5594 rtx old_test;
5595 rtx cr = XEXP (old_true, 0);
5596 rtx check_insn;
5597 rtx new_cr = NULL_RTX;
5598 rtx *p_new_cr = (rtx *)0;
5599 rtx if_else;
5600 rtx compare;
5601 rtx cc;
5602 enum reg_class cr_class;
5603 machine_mode mode = GET_MODE (true_expr);
5604 rtx (*logical_func)(rtx, rtx, rtx);
5606 if (TARGET_DEBUG_COND_EXEC)
5608 fprintf (stderr,
5609 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5610 ce_info->and_and_p ? "&&" : "||");
5612 debug_rtx (*p_true);
5614 fputs ("\nfalse insn:\n", stderr);
5615 debug_rtx (*p_false);
5618 if (!TARGET_MULTI_CE)
5619 goto fail;
5621 if (GET_CODE (cr) != REG)
5622 goto fail;
5624 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5626 cr_class = ICR_REGS;
5627 p_new_cr = &frv_ifcvt.extra_int_cr;
5629 else if (mode == CC_FPmode)
5631 cr_class = FCR_REGS;
5632 p_new_cr = &frv_ifcvt.extra_fp_cr;
5634 else
5635 goto fail;
5637 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5638 more &&/|| tests. */
5639 new_cr = *p_new_cr;
5640 if (! new_cr)
5642 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5643 CC_CCRmode, TRUE, TRUE);
5644 if (! new_cr)
5645 goto fail;
5648 if (ce_info->and_and_p)
5650 old_test = old_false;
5651 test_expr = true_expr;
5652 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5653 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5654 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5656 else
5658 old_test = old_false;
5659 test_expr = false_expr;
5660 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5661 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5662 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5665 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5666 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5667 stack. */
5668 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5670 /* Now add the conditional check insn. */
5671 cc = XEXP (test_expr, 0);
5672 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5673 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5675 check_insn = gen_rtx_SET (new_cr, if_else);
5677 /* Add the new check insn to the list of check insns that need to be
5678 inserted. */
5679 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5681 if (TARGET_DEBUG_COND_EXEC)
5683 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5684 stderr);
5686 debug_rtx (*p_true);
5688 fputs ("\nfalse insn:\n", stderr);
5689 debug_rtx (*p_false);
5692 return;
5694 fail:
5695 *p_true = *p_false = NULL_RTX;
5697 /* If we allocated a CR register, release it. */
5698 if (new_cr)
5700 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5701 *p_new_cr = NULL_RTX;
5704 if (TARGET_DEBUG_COND_EXEC)
5705 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5707 return;
5711 /* Return a register which will be loaded with a value if an IF block is
5712 converted to conditional execution. This is used to rewrite instructions
5713 that use constants to ones that just use registers. */
5715 static rtx
5716 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5718 int num_alloc = frv_ifcvt.cur_scratch_regs;
5719 int i;
5720 rtx reg;
5722 /* We know gr0 == 0, so replace any errant uses. */
5723 if (value == const0_rtx)
5724 return gen_rtx_REG (SImode, GPR_FIRST);
5726 /* First search all registers currently loaded to see if we have an
5727 applicable constant. */
5728 if (CONSTANT_P (value)
5729 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5731 for (i = 0; i < num_alloc; i++)
5733 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5734 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5738 /* Have we exhausted the number of registers available? */
5739 if (num_alloc >= GPR_TEMP_NUM)
5741 if (dump_file)
5742 fprintf (dump_file, "Too many temporary registers allocated\n");
5744 return NULL_RTX;
5747 /* Allocate the new register. */
5748 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5749 if (! reg)
5751 if (dump_file)
5752 fputs ("Could not find a scratch register\n", dump_file);
5754 return NULL_RTX;
5757 frv_ifcvt.cur_scratch_regs++;
5758 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (reg, value);
5760 if (dump_file)
5762 if (GET_CODE (value) == CONST_INT)
5763 fprintf (dump_file, "Register %s will hold %ld\n",
5764 reg_names[ REGNO (reg)], (long)INTVAL (value));
5766 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5767 fprintf (dump_file, "Register %s will hold LR\n",
5768 reg_names[ REGNO (reg)]);
5770 else
5771 fprintf (dump_file, "Register %s will hold a saved value\n",
5772 reg_names[ REGNO (reg)]);
5775 return reg;
5779 /* Update a MEM used in conditional code that might contain an offset to put
5780 the offset into a scratch register, so that the conditional load/store
5781 operations can be used. This function returns the original pointer if the
5782 MEM is valid to use in conditional code, NULL if we can't load up the offset
5783 into a temporary register, or the new MEM if we were successful. */
5785 static rtx
5786 frv_ifcvt_rewrite_mem (rtx mem, machine_mode mode, rtx insn)
5788 rtx addr = XEXP (mem, 0);
5790 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5792 if (GET_CODE (addr) == PLUS)
5794 rtx addr_op0 = XEXP (addr, 0);
5795 rtx addr_op1 = XEXP (addr, 1);
5797 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5799 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5800 if (!reg)
5801 return NULL_RTX;
5803 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5806 else
5807 return NULL_RTX;
5810 else if (CONSTANT_P (addr))
5811 addr = frv_ifcvt_load_value (addr, insn);
5813 else
5814 return NULL_RTX;
5816 if (addr == NULL_RTX)
5817 return NULL_RTX;
5819 else if (XEXP (mem, 0) != addr)
5820 return change_address (mem, mode, addr);
5823 return mem;
5827 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5828 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5830 static rtx
5831 single_set_pattern (rtx pattern)
5833 rtx set;
5834 int i;
5836 if (GET_CODE (pattern) == COND_EXEC)
5837 pattern = COND_EXEC_CODE (pattern);
5839 if (GET_CODE (pattern) == SET)
5840 return pattern;
5842 else if (GET_CODE (pattern) == PARALLEL)
5844 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5846 rtx sub = XVECEXP (pattern, 0, i);
5848 switch (GET_CODE (sub))
5850 case USE:
5851 case CLOBBER:
5852 break;
5854 case SET:
5855 if (set)
5856 return 0;
5857 else
5858 set = sub;
5859 break;
5861 default:
5862 return 0;
5865 return set;
5868 return 0;
5872 /* A C expression to modify the code described by the conditional if
5873 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5874 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5875 insn cannot be converted to be executed conditionally. */
5878 frv_ifcvt_modify_insn (ce_if_block *ce_info,
5879 rtx pattern,
5880 rtx insn)
5882 rtx orig_ce_pattern = pattern;
5883 rtx set;
5884 rtx op0;
5885 rtx op1;
5886 rtx test;
5888 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5890 test = COND_EXEC_TEST (pattern);
5891 if (GET_CODE (test) == AND)
5893 rtx cr = frv_ifcvt.cr_reg;
5894 rtx test_reg;
5896 op0 = XEXP (test, 0);
5897 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5898 goto fail;
5900 op1 = XEXP (test, 1);
5901 test_reg = XEXP (op1, 0);
5902 if (GET_CODE (test_reg) != REG)
5903 goto fail;
5905 /* Is this the first nested if block in this sequence? If so, generate
5906 an andcr or andncr. */
5907 if (! frv_ifcvt.last_nested_if_cr)
5909 rtx and_op;
5911 frv_ifcvt.last_nested_if_cr = test_reg;
5912 if (GET_CODE (op0) == NE)
5913 and_op = gen_andcr (test_reg, cr, test_reg);
5914 else
5915 and_op = gen_andncr (test_reg, cr, test_reg);
5917 frv_ifcvt_add_insn (and_op, insn, TRUE);
5920 /* If this isn't the first statement in the nested if sequence, see if we
5921 are dealing with the same register. */
5922 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5923 goto fail;
5925 COND_EXEC_TEST (pattern) = test = op1;
5928 /* If this isn't a nested if, reset state variables. */
5929 else
5931 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5934 set = single_set_pattern (pattern);
5935 if (set)
5937 rtx dest = SET_DEST (set);
5938 rtx src = SET_SRC (set);
5939 machine_mode mode = GET_MODE (dest);
5941 /* Check for normal binary operators. */
5942 if (mode == SImode && ARITHMETIC_P (src))
5944 op0 = XEXP (src, 0);
5945 op1 = XEXP (src, 1);
5947 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5949 op1 = frv_ifcvt_load_value (op1, insn);
5950 if (op1)
5951 COND_EXEC_CODE (pattern)
5952 = gen_rtx_SET (dest, gen_rtx_fmt_ee (GET_CODE (src),
5953 GET_MODE (src),
5954 op0, op1));
5955 else
5956 goto fail;
5960 /* For multiply by a constant, we need to handle the sign extending
5961 correctly. Add a USE of the value after the multiply to prevent flow
5962 from cratering because only one register out of the two were used. */
5963 else if (mode == DImode && GET_CODE (src) == MULT)
5965 op0 = XEXP (src, 0);
5966 op1 = XEXP (src, 1);
5967 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
5969 op1 = frv_ifcvt_load_value (op1, insn);
5970 if (op1)
5972 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
5973 COND_EXEC_CODE (pattern)
5974 = gen_rtx_SET (dest, gen_rtx_MULT (DImode, op0, op1));
5976 else
5977 goto fail;
5980 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
5983 /* If we are just loading a constant created for a nested conditional
5984 execution statement, just load the constant without any conditional
5985 execution, since we know that the constant will not interfere with any
5986 other registers. */
5987 else if (frv_ifcvt.scratch_insns_bitmap
5988 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
5989 INSN_UID (insn))
5990 && REG_P (SET_DEST (set))
5991 /* We must not unconditionally set a scratch reg chosen
5992 for a nested if-converted block if its incoming
5993 value from the TEST block (or the result of the THEN
5994 branch) could/should propagate to the JOIN block.
5995 It suffices to test whether the register is live at
5996 the JOIN point: if it's live there, we can infer
5997 that we set it in the former JOIN block of the
5998 nested if-converted block (otherwise it wouldn't
5999 have been available as a scratch register), and it
6000 is either propagated through or set in the other
6001 conditional block. It's probably not worth trying
6002 to catch the latter case, and it could actually
6003 limit scheduling of the combined block quite
6004 severely. */
6005 && ce_info->join_bb
6006 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6007 REGNO (SET_DEST (set))))
6008 /* Similarly, we must not unconditionally set a reg
6009 used as scratch in the THEN branch if the same reg
6010 is live in the ELSE branch. */
6011 && (! ce_info->else_bb
6012 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6013 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6014 REGNO (SET_DEST (set))))))
6015 pattern = set;
6017 else if (mode == QImode || mode == HImode || mode == SImode
6018 || mode == SFmode)
6020 int changed_p = FALSE;
6022 /* Check for just loading up a constant */
6023 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6025 src = frv_ifcvt_load_value (src, insn);
6026 if (!src)
6027 goto fail;
6029 changed_p = TRUE;
6032 /* See if we need to fix up stores */
6033 if (GET_CODE (dest) == MEM)
6035 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6037 if (!new_mem)
6038 goto fail;
6040 else if (new_mem != dest)
6042 changed_p = TRUE;
6043 dest = new_mem;
6047 /* See if we need to fix up loads */
6048 if (GET_CODE (src) == MEM)
6050 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6052 if (!new_mem)
6053 goto fail;
6055 else if (new_mem != src)
6057 changed_p = TRUE;
6058 src = new_mem;
6062 /* If either src or destination changed, redo SET. */
6063 if (changed_p)
6064 COND_EXEC_CODE (pattern) = gen_rtx_SET (dest, src);
6067 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6068 rewriting the CC register to be the same as the paired CC/CR register
6069 for nested ifs. */
6070 else if (mode == CC_CCRmode && COMPARISON_P (src))
6072 int regno = REGNO (XEXP (src, 0));
6073 rtx if_else;
6075 if (ce_info->pass > 1
6076 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6077 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6079 src = gen_rtx_fmt_ee (GET_CODE (src),
6080 CC_CCRmode,
6081 frv_ifcvt.nested_cc_reg,
6082 XEXP (src, 1));
6085 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6086 pattern = gen_rtx_SET (dest, if_else);
6089 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6090 else if (ce_info->pass > 1
6091 && GET_CODE (dest) == REG
6092 && CC_P (REGNO (dest))
6093 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6094 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6095 REGNO (dest))
6096 && GET_CODE (src) == COMPARE)
6098 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6099 COND_EXEC_CODE (pattern)
6100 = gen_rtx_SET (frv_ifcvt.nested_cc_reg, copy_rtx (src));
6104 if (TARGET_DEBUG_COND_EXEC)
6106 rtx orig_pattern = PATTERN (insn);
6108 PATTERN (insn) = pattern;
6109 fprintf (stderr,
6110 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6111 ce_info->pass);
6113 debug_rtx (insn);
6114 PATTERN (insn) = orig_pattern;
6117 return pattern;
6119 fail:
6120 if (TARGET_DEBUG_COND_EXEC)
6122 rtx orig_pattern = PATTERN (insn);
6124 PATTERN (insn) = orig_ce_pattern;
6125 fprintf (stderr,
6126 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6127 ce_info->pass);
6129 debug_rtx (insn);
6130 PATTERN (insn) = orig_pattern;
6133 return NULL_RTX;
6137 /* A C expression to perform any final machine dependent modifications in
6138 converting code to conditional execution in the code described by the
6139 conditional if information CE_INFO. */
6141 void
6142 frv_ifcvt_modify_final (ce_if_block *ce_info ATTRIBUTE_UNUSED)
6144 rtx existing_insn;
6145 rtx check_insn;
6146 rtx p = frv_ifcvt.added_insns_list;
6147 int i;
6149 /* Loop inserting the check insns. The last check insn is the first test,
6150 and is the appropriate place to insert constants. */
6151 gcc_assert (p);
6155 rtx check_and_insert_insns = XEXP (p, 0);
6156 rtx old_p = p;
6158 check_insn = XEXP (check_and_insert_insns, 0);
6159 existing_insn = XEXP (check_and_insert_insns, 1);
6160 p = XEXP (p, 1);
6162 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6163 the existing insn, otherwise it is to be inserted AFTER. */
6164 if (check_and_insert_insns->jump)
6166 emit_insn_before (check_insn, existing_insn);
6167 check_and_insert_insns->jump = 0;
6169 else
6170 emit_insn_after (check_insn, existing_insn);
6172 free_EXPR_LIST_node (check_and_insert_insns);
6173 free_EXPR_LIST_node (old_p);
6175 while (p != NULL_RTX);
6177 /* Load up any constants needed into temp gprs */
6178 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6180 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6181 if (! frv_ifcvt.scratch_insns_bitmap)
6182 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6183 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6184 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6187 frv_ifcvt.added_insns_list = NULL_RTX;
6188 frv_ifcvt.cur_scratch_regs = 0;
6192 /* A C expression to cancel any machine dependent modifications in converting
6193 code to conditional execution in the code described by the conditional if
6194 information CE_INFO. */
6196 void
6197 frv_ifcvt_modify_cancel (ce_if_block *ce_info ATTRIBUTE_UNUSED)
6199 int i;
6200 rtx p = frv_ifcvt.added_insns_list;
6202 /* Loop freeing up the EXPR_LIST's allocated. */
6203 while (p != NULL_RTX)
6205 rtx check_and_jump = XEXP (p, 0);
6206 rtx old_p = p;
6208 p = XEXP (p, 1);
6209 free_EXPR_LIST_node (check_and_jump);
6210 free_EXPR_LIST_node (old_p);
6213 /* Release any temporary gprs allocated. */
6214 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6215 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6217 frv_ifcvt.added_insns_list = NULL_RTX;
6218 frv_ifcvt.cur_scratch_regs = 0;
6219 return;
6222 /* A C expression for the size in bytes of the trampoline, as an integer.
6223 The template is:
6225 setlo #0, <jmp_reg>
6226 setlo #0, <static_chain>
6227 sethi #0, <jmp_reg>
6228 sethi #0, <static_chain>
6229 jmpl @(gr0,<jmp_reg>) */
6232 frv_trampoline_size (void)
6234 if (TARGET_FDPIC)
6235 /* Allocate room for the function descriptor and the lddi
6236 instruction. */
6237 return 8 + 6 * 4;
6238 return 5 /* instructions */ * 4 /* instruction size. */;
6242 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6243 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6244 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6245 should be passed to the function when it is called.
6247 The template is:
6249 setlo #0, <jmp_reg>
6250 setlo #0, <static_chain>
6251 sethi #0, <jmp_reg>
6252 sethi #0, <static_chain>
6253 jmpl @(gr0,<jmp_reg>) */
6255 static void
6256 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6258 rtx addr = XEXP (m_tramp, 0);
6259 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6260 rtx sc_reg = force_reg (Pmode, static_chain);
6262 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6263 LCT_NORMAL, VOIDmode, 4,
6264 addr, Pmode,
6265 GEN_INT (frv_trampoline_size ()), SImode,
6266 fnaddr, Pmode,
6267 sc_reg, Pmode);
6271 /* Many machines have some registers that cannot be copied directly to or from
6272 memory or even from other types of registers. An example is the `MQ'
6273 register, which on most machines, can only be copied to or from general
6274 registers, but not memory. Some machines allow copying all registers to and
6275 from memory, but require a scratch register for stores to some memory
6276 locations (e.g., those with symbolic address on the RT, and those with
6277 certain symbolic address on the SPARC when compiling PIC). In some cases,
6278 both an intermediate and a scratch register are required.
6280 You should define these macros to indicate to the reload phase that it may
6281 need to allocate at least one register for a reload in addition to the
6282 register to contain the data. Specifically, if copying X to a register
6283 RCLASS in MODE requires an intermediate register, you should define
6284 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6285 whose registers can be used as intermediate registers or scratch registers.
6287 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6288 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6289 largest register class required. If the requirements for input and output
6290 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6291 instead of defining both macros identically.
6293 The values returned by these macros are often `GENERAL_REGS'. Return
6294 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6295 to or from a register of RCLASS in MODE without requiring a scratch register.
6296 Do not define this macro if it would always return `NO_REGS'.
6298 If a scratch register is required (either with or without an intermediate
6299 register), you should define patterns for `reload_inM' or `reload_outM', as
6300 required.. These patterns, which will normally be implemented with a
6301 `define_expand', should be similar to the `movM' patterns, except that
6302 operand 2 is the scratch register.
6304 Define constraints for the reload register and scratch register that contain
6305 a single register class. If the original reload register (whose class is
6306 RCLASS) can meet the constraint given in the pattern, the value returned by
6307 these macros is used for the class of the scratch register. Otherwise, two
6308 additional reload registers are required. Their classes are obtained from
6309 the constraints in the insn pattern.
6311 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6312 either be in a hard register or in memory. Use `true_regnum' to find out;
6313 it will return -1 if the pseudo is in memory and the hard register number if
6314 it is in a register.
6316 These macros should not be used in the case where a particular class of
6317 registers can only be copied to memory and not to another class of
6318 registers. In that case, secondary reload registers are not needed and
6319 would not be helpful. Instead, a stack location must be used to perform the
6320 copy and the `movM' pattern should use memory as an intermediate storage.
6321 This case often occurs between floating-point and general registers. */
6323 enum reg_class
6324 frv_secondary_reload_class (enum reg_class rclass,
6325 machine_mode mode ATTRIBUTE_UNUSED,
6326 rtx x)
6328 enum reg_class ret;
6330 switch (rclass)
6332 default:
6333 ret = NO_REGS;
6334 break;
6336 /* Accumulators/Accumulator guard registers need to go through floating
6337 point registers. */
6338 case QUAD_REGS:
6339 case GPR_REGS:
6340 ret = NO_REGS;
6341 if (x && GET_CODE (x) == REG)
6343 int regno = REGNO (x);
6345 if (ACC_P (regno) || ACCG_P (regno))
6346 ret = FPR_REGS;
6348 break;
6350 /* Nonzero constants should be loaded into an FPR through a GPR. */
6351 case QUAD_FPR_REGS:
6352 if (x && CONSTANT_P (x) && !ZERO_P (x))
6353 ret = GPR_REGS;
6354 else
6355 ret = NO_REGS;
6356 break;
6358 /* All of these types need gpr registers. */
6359 case ICC_REGS:
6360 case FCC_REGS:
6361 case CC_REGS:
6362 case ICR_REGS:
6363 case FCR_REGS:
6364 case CR_REGS:
6365 case LCR_REG:
6366 case LR_REG:
6367 ret = GPR_REGS;
6368 break;
6370 /* The accumulators need fpr registers. */
6371 case QUAD_ACC_REGS:
6372 case ACCG_REGS:
6373 ret = FPR_REGS;
6374 break;
6377 return ret;
6380 /* This hook exists to catch the case where secondary_reload_class() is
6381 called from init_reg_autoinc() in regclass.c - before the reload optabs
6382 have been initialised. */
6384 static reg_class_t
6385 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6386 machine_mode reload_mode,
6387 secondary_reload_info * sri)
6389 enum reg_class rclass = NO_REGS;
6390 enum reg_class reload_class = (enum reg_class) reload_class_i;
6392 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6394 sri->icode = sri->prev_sri->t_icode;
6395 return NO_REGS;
6398 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6400 if (rclass != NO_REGS)
6402 enum insn_code icode
6403 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6404 reload_mode);
6405 if (icode == 0)
6407 /* This happens when then the reload_[in|out]_optabs have
6408 not been initialised. */
6409 sri->t_icode = CODE_FOR_nothing;
6410 return rclass;
6414 /* Fall back to the default secondary reload handler. */
6415 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6419 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6421 static bool
6422 frv_class_likely_spilled_p (reg_class_t rclass)
6424 switch (rclass)
6426 default:
6427 break;
6429 case GR8_REGS:
6430 case GR9_REGS:
6431 case GR89_REGS:
6432 case FDPIC_FPTR_REGS:
6433 case FDPIC_REGS:
6434 case ICC_REGS:
6435 case FCC_REGS:
6436 case CC_REGS:
6437 case ICR_REGS:
6438 case FCR_REGS:
6439 case CR_REGS:
6440 case LCR_REG:
6441 case LR_REG:
6442 case SPR_REGS:
6443 case QUAD_ACC_REGS:
6444 case ACCG_REGS:
6445 return true;
6448 return false;
6452 /* An expression for the alignment of a structure field FIELD if the
6453 alignment computed in the usual way is COMPUTED. GCC uses this
6454 value instead of the value in `BIGGEST_ALIGNMENT' or
6455 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6457 /* The definition type of the bit field data is either char, short, long or
6458 long long. The maximum bit size is the number of bits of its own type.
6460 The bit field data is assigned to a storage unit that has an adequate size
6461 for bit field data retention and is located at the smallest address.
6463 Consecutive bit field data are packed at consecutive bits having the same
6464 storage unit, with regard to the type, beginning with the MSB and continuing
6465 toward the LSB.
6467 If a field to be assigned lies over a bit field type boundary, its
6468 assignment is completed by aligning it with a boundary suitable for the
6469 type.
6471 When a bit field having a bit length of 0 is declared, it is forcibly
6472 assigned to the next storage unit.
6474 e.g)
6475 struct {
6476 int a:2;
6477 int b:6;
6478 char c:4;
6479 int d:10;
6480 int :0;
6481 int f:2;
6482 } x;
6484 +0 +1 +2 +3
6485 &x 00000000 00000000 00000000 00000000
6486 MLM----L
6488 &x+4 00000000 00000000 00000000 00000000
6489 M--L
6491 &x+8 00000000 00000000 00000000 00000000
6492 M----------L
6494 &x+12 00000000 00000000 00000000 00000000
6500 frv_adjust_field_align (tree field, int computed)
6502 /* Make sure that the bitfield is not wider than the type. */
6503 if (DECL_BIT_FIELD (field)
6504 && !DECL_ARTIFICIAL (field))
6506 tree parent = DECL_CONTEXT (field);
6507 tree prev = NULL_TREE;
6508 tree cur;
6510 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6512 if (TREE_CODE (cur) != FIELD_DECL)
6513 continue;
6515 prev = cur;
6518 gcc_assert (cur);
6520 /* If this isn't a :0 field and if the previous element is a bitfield
6521 also, see if the type is different, if so, we will need to align the
6522 bit-field to the next boundary. */
6523 if (prev
6524 && ! DECL_PACKED (field)
6525 && ! integer_zerop (DECL_SIZE (field))
6526 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6528 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6529 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6530 computed = (prev_align > cur_align) ? prev_align : cur_align;
6534 return computed;
6538 /* A C expression that is nonzero if it is permissible to store a value of mode
6539 MODE in hard register number REGNO (or in several registers starting with
6540 that one). For a machine where all registers are equivalent, a suitable
6541 definition is
6543 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6545 It is not necessary for this macro to check for the numbers of fixed
6546 registers, because the allocation mechanism considers them to be always
6547 occupied.
6549 On some machines, double-precision values must be kept in even/odd register
6550 pairs. The way to implement that is to define this macro to reject odd
6551 register numbers for such modes.
6553 The minimum requirement for a mode to be OK in a register is that the
6554 `movMODE' instruction pattern support moves between the register and any
6555 other hard register for which the mode is OK; and that moving a value into
6556 the register and back out not alter it.
6558 Since the same instruction used to move `SImode' will work for all narrower
6559 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6560 to distinguish between these modes, provided you define patterns `movhi',
6561 etc., to take advantage of this. This is useful because of the interaction
6562 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6563 all integer modes to be tieable.
6565 Many machines have special registers for floating point arithmetic. Often
6566 people assume that floating point machine modes are allowed only in floating
6567 point registers. This is not true. Any registers that can hold integers
6568 can safely *hold* a floating point machine mode, whether or not floating
6569 arithmetic can be done on it in those registers. Integer move instructions
6570 can be used to move the values.
6572 On some machines, though, the converse is true: fixed-point machine modes
6573 may not go in floating registers. This is true if the floating registers
6574 normalize any value stored in them, because storing a non-floating value
6575 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6576 fixed-point machine modes in floating registers. But if the floating
6577 registers do not automatically normalize, if you can store any bit pattern
6578 in one and retrieve it unchanged without a trap, then any machine mode may
6579 go in a floating register, so you can define this macro to say so.
6581 The primary significance of special floating registers is rather that they
6582 are the registers acceptable in floating point arithmetic instructions.
6583 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6584 writing the proper constraints for those instructions.
6586 On some machines, the floating registers are especially slow to access, so
6587 that it is better to store a value in a stack frame than in such a register
6588 if floating point arithmetic is not being done. As long as the floating
6589 registers are not in class `GENERAL_REGS', they will not be used unless some
6590 pattern's constraint asks for one. */
6593 frv_hard_regno_mode_ok (int regno, machine_mode mode)
6595 int base;
6596 int mask;
6598 switch (mode)
6600 case CCmode:
6601 case CC_UNSmode:
6602 case CC_NZmode:
6603 return ICC_P (regno) || GPR_P (regno);
6605 case CC_CCRmode:
6606 return CR_P (regno) || GPR_P (regno);
6608 case CC_FPmode:
6609 return FCC_P (regno) || GPR_P (regno);
6611 default:
6612 break;
6615 /* Set BASE to the first register in REGNO's class. Set MASK to the
6616 bits that must be clear in (REGNO - BASE) for the register to be
6617 well-aligned. */
6618 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6620 if (ACCG_P (regno))
6622 /* ACCGs store one byte. Two-byte quantities must start in
6623 even-numbered registers, four-byte ones in registers whose
6624 numbers are divisible by four, and so on. */
6625 base = ACCG_FIRST;
6626 mask = GET_MODE_SIZE (mode) - 1;
6628 else
6630 /* The other registers store one word. */
6631 if (GPR_P (regno) || regno == AP_FIRST)
6632 base = GPR_FIRST;
6634 else if (FPR_P (regno))
6635 base = FPR_FIRST;
6637 else if (ACC_P (regno))
6638 base = ACC_FIRST;
6640 else if (SPR_P (regno))
6641 return mode == SImode;
6643 /* Fill in the table. */
6644 else
6645 return 0;
6647 /* Anything smaller than an SI is OK in any word-sized register. */
6648 if (GET_MODE_SIZE (mode) < 4)
6649 return 1;
6651 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6653 return (((regno - base) & mask) == 0);
6656 return 0;
6660 /* A C expression for the number of consecutive hard registers, starting at
6661 register number REGNO, required to hold a value of mode MODE.
6663 On a machine where all registers are exactly one word, a suitable definition
6664 of this macro is
6666 #define HARD_REGNO_NREGS(REGNO, MODE) \
6667 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6668 / UNITS_PER_WORD)) */
6670 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6671 that we can build the appropriate instructions to properly reload the
6672 values. Also, make the byte-sized accumulator guards use one guard
6673 for each byte. */
6676 frv_hard_regno_nregs (int regno, machine_mode mode)
6678 if (ACCG_P (regno))
6679 return GET_MODE_SIZE (mode);
6680 else
6681 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6685 /* A C expression for the maximum number of consecutive registers of
6686 class RCLASS needed to hold a value of mode MODE.
6688 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6689 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6690 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6692 This macro helps control the handling of multiple-word values in
6693 the reload pass.
6695 This declaration is required. */
6698 frv_class_max_nregs (enum reg_class rclass, machine_mode mode)
6700 if (rclass == ACCG_REGS)
6701 /* An N-byte value requires N accumulator guards. */
6702 return GET_MODE_SIZE (mode);
6703 else
6704 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6708 /* A C expression that is nonzero if X is a legitimate constant for an
6709 immediate operand on the target machine. You can assume that X satisfies
6710 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6711 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6713 static bool
6714 frv_legitimate_constant_p (machine_mode mode, rtx x)
6716 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6717 means that the move expanders will be expected to deal with most
6718 kinds of constant, regardless of what we return here.
6720 However, among its other duties, frv_legitimate_constant_p decides whether
6721 a constant can be entered into reg_equiv_constant[]. If we return true,
6722 reload can create new instances of the constant whenever it likes.
6724 The idea is therefore to accept as many constants as possible (to give
6725 reload more freedom) while rejecting constants that can only be created
6726 at certain times. In particular, anything with a symbolic component will
6727 require use of the pseudo FDPIC register, which is only available before
6728 reload. */
6729 if (TARGET_FDPIC)
6730 return LEGITIMATE_PIC_OPERAND_P (x);
6732 /* All of the integer constants are ok. */
6733 if (GET_CODE (x) != CONST_DOUBLE)
6734 return TRUE;
6736 /* double integer constants are ok. */
6737 if (GET_MODE (x) == VOIDmode || mode == DImode)
6738 return TRUE;
6740 /* 0 is always ok. */
6741 if (x == CONST0_RTX (mode))
6742 return TRUE;
6744 /* If floating point is just emulated, allow any constant, since it will be
6745 constructed in the GPRs. */
6746 if (!TARGET_HAS_FPRS)
6747 return TRUE;
6749 if (mode == DFmode && !TARGET_DOUBLE)
6750 return TRUE;
6752 /* Otherwise store the constant away and do a load. */
6753 return FALSE;
6756 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6757 CC_NZ for comparisons against zero in which a single Z or N flag test
6758 is enough, CC_UNS for other unsigned comparisons, and CC for other
6759 signed comparisons. */
6761 machine_mode
6762 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6764 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6765 return CC_FPmode;
6767 switch (code)
6769 case EQ:
6770 case NE:
6771 case LT:
6772 case GE:
6773 return y == const0_rtx ? CC_NZmode : CCmode;
6775 case GTU:
6776 case GEU:
6777 case LTU:
6778 case LEU:
6779 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6781 default:
6782 return CCmode;
6787 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6789 #define HIGH_COST 40
6790 #define MEDIUM_COST 3
6791 #define LOW_COST 1
6793 static int
6794 frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
6795 reg_class_t from, reg_class_t to)
6797 switch (from)
6799 default:
6800 break;
6802 case QUAD_REGS:
6803 case GPR_REGS:
6804 case GR8_REGS:
6805 case GR9_REGS:
6806 case GR89_REGS:
6807 case FDPIC_REGS:
6808 case FDPIC_FPTR_REGS:
6809 case FDPIC_CALL_REGS:
6811 switch (to)
6813 default:
6814 break;
6816 case QUAD_REGS:
6817 case GPR_REGS:
6818 case GR8_REGS:
6819 case GR9_REGS:
6820 case GR89_REGS:
6821 case FDPIC_REGS:
6822 case FDPIC_FPTR_REGS:
6823 case FDPIC_CALL_REGS:
6825 return LOW_COST;
6827 case FPR_REGS:
6828 return LOW_COST;
6830 case LCR_REG:
6831 case LR_REG:
6832 case SPR_REGS:
6833 return LOW_COST;
6836 case QUAD_FPR_REGS:
6837 switch (to)
6839 default:
6840 break;
6842 case QUAD_REGS:
6843 case GPR_REGS:
6844 case GR8_REGS:
6845 case GR9_REGS:
6846 case GR89_REGS:
6847 case FDPIC_REGS:
6848 case FDPIC_FPTR_REGS:
6849 case FDPIC_CALL_REGS:
6851 case QUAD_ACC_REGS:
6852 case ACCG_REGS:
6853 return MEDIUM_COST;
6855 case QUAD_FPR_REGS:
6856 return LOW_COST;
6859 case LCR_REG:
6860 case LR_REG:
6861 case SPR_REGS:
6862 switch (to)
6864 default:
6865 break;
6867 case QUAD_REGS:
6868 case GPR_REGS:
6869 case GR8_REGS:
6870 case GR9_REGS:
6871 case GR89_REGS:
6872 case FDPIC_REGS:
6873 case FDPIC_FPTR_REGS:
6874 case FDPIC_CALL_REGS:
6876 return MEDIUM_COST;
6879 case QUAD_ACC_REGS:
6880 case ACCG_REGS:
6881 switch (to)
6883 default:
6884 break;
6886 case QUAD_FPR_REGS:
6887 return MEDIUM_COST;
6892 return HIGH_COST;
6895 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6897 static int
6898 frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
6899 reg_class_t rclass ATTRIBUTE_UNUSED,
6900 bool in ATTRIBUTE_UNUSED)
6902 return 4;
6906 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6907 use ".picptr" to generate safe relocations for PIC code. We also
6908 need a fixup entry for aligned (non-debugging) code. */
6910 static bool
6911 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6913 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6915 if (GET_CODE (value) == CONST
6916 || GET_CODE (value) == SYMBOL_REF
6917 || GET_CODE (value) == LABEL_REF)
6919 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6920 && SYMBOL_REF_FUNCTION_P (value))
6922 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6923 output_addr_const (asm_out_file, value);
6924 fputs (")\n", asm_out_file);
6925 return true;
6927 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6928 && frv_function_symbol_referenced_p (value))
6929 return false;
6930 if (aligned_p && !TARGET_FDPIC)
6932 static int label_num = 0;
6933 char buf[256];
6934 const char *p;
6936 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6937 p = (* targetm.strip_name_encoding) (buf);
6939 fprintf (asm_out_file, "%s:\n", p);
6940 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6941 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6942 fprintf (asm_out_file, "\t.previous\n");
6944 assemble_integer_with_op ("\t.picptr\t", value);
6945 return true;
6947 if (!aligned_p)
6949 /* We've set the unaligned SI op to NULL, so we always have to
6950 handle the unaligned case here. */
6951 assemble_integer_with_op ("\t.4byte\t", value);
6952 return true;
6955 return default_assemble_integer (value, size, aligned_p);
6958 /* Function to set up the backend function structure. */
6960 static struct machine_function *
6961 frv_init_machine_status (void)
6963 return ggc_cleared_alloc<machine_function> ();
6966 /* Implement TARGET_SCHED_ISSUE_RATE. */
6969 frv_issue_rate (void)
6971 if (!TARGET_PACK)
6972 return 1;
6974 switch (frv_cpu_type)
6976 default:
6977 case FRV_CPU_FR300:
6978 case FRV_CPU_SIMPLE:
6979 return 1;
6981 case FRV_CPU_FR400:
6982 case FRV_CPU_FR405:
6983 case FRV_CPU_FR450:
6984 return 2;
6986 case FRV_CPU_GENERIC:
6987 case FRV_CPU_FR500:
6988 case FRV_CPU_TOMCAT:
6989 return 4;
6991 case FRV_CPU_FR550:
6992 return 8;
6996 /* Return the value of INSN's acc_group attribute. */
6999 frv_acc_group (rtx insn)
7001 /* This distinction only applies to the FR550 packing constraints. */
7002 if (frv_cpu_type == FRV_CPU_FR550)
7004 subrtx_iterator::array_type array;
7005 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
7006 if (REG_P (*iter))
7008 unsigned int regno = REGNO (*iter);
7009 /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if
7010 the bit 2 of the register number is set and ACC_GROUP_EVEN if
7011 it is clear. */
7012 if (ACC_P (regno))
7013 return (regno - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7014 if (ACCG_P (regno))
7015 return (regno - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7018 return ACC_GROUP_NONE;
7021 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7022 INSN will try to claim first. Since this value depends only on the
7023 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7025 static unsigned int
7026 frv_insn_unit (rtx_insn *insn)
7028 enum attr_type type;
7030 type = get_attr_type (insn);
7031 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7033 /* We haven't seen this type of instruction before. */
7034 state_t state;
7035 unsigned int unit;
7037 /* Issue the instruction on its own to see which unit it prefers. */
7038 state = alloca (state_size ());
7039 state_reset (state);
7040 state_transition (state, insn);
7042 /* Find out which unit was taken. */
7043 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7044 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7045 break;
7047 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7049 frv_type_to_unit[type] = unit;
7051 return frv_type_to_unit[type];
7054 /* Return true if INSN issues to a branch unit. */
7056 static bool
7057 frv_issues_to_branch_unit_p (rtx_insn *insn)
7059 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7062 /* The instructions in the packet, partitioned into groups. */
7063 struct frv_packet_group {
7064 /* How many instructions in the packet belong to this group. */
7065 unsigned int num_insns;
7067 /* A list of the instructions that belong to this group, in the order
7068 they appear in the rtl stream. */
7069 rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)];
7071 /* The contents of INSNS after they have been sorted into the correct
7072 assembly-language order. Element X issues to unit X. The list may
7073 contain extra nops. */
7074 rtx_insn *sorted[ARRAY_SIZE (frv_unit_codes)];
7076 /* The member of frv_nops[] to use in sorted[]. */
7077 rtx_insn *nop;
7080 /* The current state of the packing pass, implemented by frv_pack_insns. */
7081 static struct {
7082 /* The state of the pipeline DFA. */
7083 state_t dfa_state;
7085 /* Which hardware registers are set within the current packet,
7086 and the conditions under which they are set. */
7087 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7089 /* The memory locations that have been modified so far in this
7090 packet. MEM is the memref and COND is the regstate_t condition
7091 under which it is set. */
7092 struct {
7093 rtx mem;
7094 regstate_t cond;
7095 } mems[2];
7097 /* The number of valid entries in MEMS. The value is larger than
7098 ARRAY_SIZE (mems) if there were too many mems to record. */
7099 unsigned int num_mems;
7101 /* The maximum number of instructions that can be packed together. */
7102 unsigned int issue_rate;
7104 /* The instructions in the packet, partitioned into groups. */
7105 struct frv_packet_group groups[NUM_GROUPS];
7107 /* The instructions that make up the current packet. */
7108 rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)];
7109 unsigned int num_insns;
7110 } frv_packet;
7112 /* Return the regstate_t flags for the given COND_EXEC condition.
7113 Abort if the condition isn't in the right form. */
7115 static int
7116 frv_cond_flags (rtx cond)
7118 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7119 && GET_CODE (XEXP (cond, 0)) == REG
7120 && CR_P (REGNO (XEXP (cond, 0)))
7121 && XEXP (cond, 1) == const0_rtx);
7122 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7123 | (GET_CODE (cond) == NE
7124 ? REGSTATE_IF_TRUE
7125 : REGSTATE_IF_FALSE));
7129 /* Return true if something accessed under condition COND2 can
7130 conflict with something written under condition COND1. */
7132 static bool
7133 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7135 /* If either reference was unconditional, we have a conflict. */
7136 if ((cond1 & REGSTATE_IF_EITHER) == 0
7137 || (cond2 & REGSTATE_IF_EITHER) == 0)
7138 return true;
7140 /* The references might conflict if they were controlled by
7141 different CRs. */
7142 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7143 return true;
7145 /* They definitely conflict if they are controlled by the
7146 same condition. */
7147 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7148 return true;
7150 return false;
7154 /* Return true if an instruction with pattern PAT depends on an
7155 instruction in the current packet. COND describes the condition
7156 under which PAT might be set or used. */
7158 static bool
7159 frv_registers_conflict_p_1 (rtx pat, regstate_t cond)
7161 subrtx_var_iterator::array_type array;
7162 FOR_EACH_SUBRTX_VAR (iter, array, pat, NONCONST)
7164 rtx x = *iter;
7165 if (GET_CODE (x) == REG)
7167 unsigned int regno;
7168 FOR_EACH_REGNO (regno, x)
7169 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7170 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7171 return true;
7173 else if (GET_CODE (x) == MEM)
7175 /* If we ran out of memory slots, assume a conflict. */
7176 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7177 return 1;
7179 /* Check for output or true dependencies with earlier MEMs. */
7180 for (unsigned int i = 0; i < frv_packet.num_mems; i++)
7181 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7183 if (true_dependence (frv_packet.mems[i].mem, VOIDmode, x))
7184 return true;
7186 if (output_dependence (frv_packet.mems[i].mem, x))
7187 return true;
7191 /* The return values of calls aren't significant: they describe
7192 the effect of the call as a whole, not of the insn itself. */
7193 else if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL)
7194 iter.substitute (SET_SRC (x));
7196 return false;
7200 /* Return true if something in X might depend on an instruction
7201 in the current packet. */
7203 static bool
7204 frv_registers_conflict_p (rtx x)
7206 regstate_t flags;
7208 flags = 0;
7209 if (GET_CODE (x) == COND_EXEC)
7211 if (frv_registers_conflict_p_1 (XEXP (x, 0), flags))
7212 return true;
7214 flags |= frv_cond_flags (XEXP (x, 0));
7215 x = XEXP (x, 1);
7217 return frv_registers_conflict_p_1 (x, flags);
7221 /* A note_stores callback. DATA points to the regstate_t condition
7222 under which X is modified. Update FRV_PACKET accordingly. */
7224 static void
7225 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7227 unsigned int regno;
7229 if (GET_CODE (x) == REG)
7230 FOR_EACH_REGNO (regno, x)
7231 frv_packet.regstate[regno] |= *(regstate_t *) data;
7233 if (GET_CODE (x) == MEM)
7235 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7237 frv_packet.mems[frv_packet.num_mems].mem = x;
7238 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7240 frv_packet.num_mems++;
7245 /* Update the register state information for an instruction whose
7246 body is X. */
7248 static void
7249 frv_registers_update (rtx x)
7251 regstate_t flags;
7253 flags = REGSTATE_MODIFIED;
7254 if (GET_CODE (x) == COND_EXEC)
7256 flags |= frv_cond_flags (XEXP (x, 0));
7257 x = XEXP (x, 1);
7259 note_stores (x, frv_registers_update_1, &flags);
7263 /* Initialize frv_packet for the start of a new packet. */
7265 static void
7266 frv_start_packet (void)
7268 enum frv_insn_group group;
7270 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7271 frv_packet.num_mems = 0;
7272 frv_packet.num_insns = 0;
7273 for (group = GROUP_I; group < NUM_GROUPS;
7274 group = (enum frv_insn_group) (group + 1))
7275 frv_packet.groups[group].num_insns = 0;
7279 /* Likewise for the start of a new basic block. */
7281 static void
7282 frv_start_packet_block (void)
7284 state_reset (frv_packet.dfa_state);
7285 frv_start_packet ();
7289 /* Finish the current packet, if any, and start a new one. Call
7290 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7292 static void
7293 frv_finish_packet (void (*handle_packet) (void))
7295 if (frv_packet.num_insns > 0)
7297 handle_packet ();
7298 state_transition (frv_packet.dfa_state, 0);
7299 frv_start_packet ();
7304 /* Return true if INSN can be added to the current packet. Update
7305 the DFA state on success. */
7307 static bool
7308 frv_pack_insn_p (rtx_insn *insn)
7310 /* See if the packet is already as long as it can be. */
7311 if (frv_packet.num_insns == frv_packet.issue_rate)
7312 return false;
7314 /* If the scheduler thought that an instruction should start a packet,
7315 it's usually a good idea to believe it. It knows much more about
7316 the latencies than we do.
7318 There are some exceptions though:
7320 - Conditional instructions are scheduled on the assumption that
7321 they will be executed. This is usually a good thing, since it
7322 tends to avoid unnecessary stalls in the conditional code.
7323 But we want to pack conditional instructions as tightly as
7324 possible, in order to optimize the case where they aren't
7325 executed.
7327 - The scheduler will always put branches on their own, even
7328 if there's no real dependency.
7330 - There's no point putting a call in its own packet unless
7331 we have to. */
7332 if (frv_packet.num_insns > 0
7333 && NONJUMP_INSN_P (insn)
7334 && GET_MODE (insn) == TImode
7335 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7336 return false;
7338 /* Check for register conflicts. Don't do this for setlo since any
7339 conflict will be with the partnering sethi, with which it can
7340 be packed. */
7341 if (get_attr_type (insn) != TYPE_SETLO)
7342 if (frv_registers_conflict_p (PATTERN (insn)))
7343 return false;
7345 return state_transition (frv_packet.dfa_state, insn) < 0;
7349 /* Add instruction INSN to the current packet. */
7351 static void
7352 frv_add_insn_to_packet (rtx_insn *insn)
7354 struct frv_packet_group *packet_group;
7356 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7357 packet_group->insns[packet_group->num_insns++] = insn;
7358 frv_packet.insns[frv_packet.num_insns++] = insn;
7360 frv_registers_update (PATTERN (insn));
7364 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7365 packet ends in a branch or call, insert the nop before it, otherwise
7366 add to the end. */
7368 static void
7369 frv_insert_nop_in_packet (rtx_insn *insn)
7371 struct frv_packet_group *packet_group;
7372 rtx_insn *last;
7374 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7375 last = frv_packet.insns[frv_packet.num_insns - 1];
7376 if (! NONJUMP_INSN_P (last))
7378 insn = emit_insn_before (PATTERN (insn), last);
7379 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7380 frv_packet.insns[frv_packet.num_insns++] = last;
7382 else
7384 insn = emit_insn_after (PATTERN (insn), last);
7385 frv_packet.insns[frv_packet.num_insns++] = insn;
7387 packet_group->insns[packet_group->num_insns++] = insn;
7391 /* If packing is enabled, divide the instructions into packets and
7392 return true. Call HANDLE_PACKET for each complete packet. */
7394 static bool
7395 frv_for_each_packet (void (*handle_packet) (void))
7397 rtx_insn *insn, *next_insn;
7399 frv_packet.issue_rate = frv_issue_rate ();
7401 /* Early exit if we don't want to pack insns. */
7402 if (!optimize
7403 || !flag_schedule_insns_after_reload
7404 || !TARGET_VLIW_BRANCH
7405 || frv_packet.issue_rate == 1)
7406 return false;
7408 /* Set up the initial packing state. */
7409 dfa_start ();
7410 frv_packet.dfa_state = alloca (state_size ());
7412 frv_start_packet_block ();
7413 for (insn = get_insns (); insn != 0; insn = next_insn)
7415 enum rtx_code code;
7416 bool eh_insn_p;
7418 code = GET_CODE (insn);
7419 next_insn = NEXT_INSN (insn);
7421 if (code == CODE_LABEL)
7423 frv_finish_packet (handle_packet);
7424 frv_start_packet_block ();
7427 if (INSN_P (insn))
7428 switch (GET_CODE (PATTERN (insn)))
7430 case USE:
7431 case CLOBBER:
7432 break;
7434 default:
7435 /* Calls mustn't be packed on a TOMCAT. */
7436 if (CALL_P (insn) && frv_cpu_type == FRV_CPU_TOMCAT)
7437 frv_finish_packet (handle_packet);
7439 /* Since the last instruction in a packet determines the EH
7440 region, any exception-throwing instruction must come at
7441 the end of reordered packet. Insns that issue to a
7442 branch unit are bound to come last; for others it's
7443 too hard to predict. */
7444 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7445 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7446 frv_finish_packet (handle_packet);
7448 /* Finish the current packet if we can't add INSN to it.
7449 Simulate cycles until INSN is ready to issue. */
7450 if (!frv_pack_insn_p (insn))
7452 frv_finish_packet (handle_packet);
7453 while (!frv_pack_insn_p (insn))
7454 state_transition (frv_packet.dfa_state, 0);
7457 /* Add the instruction to the packet. */
7458 frv_add_insn_to_packet (insn);
7460 /* Calls and jumps end a packet, as do insns that throw
7461 an exception. */
7462 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7463 frv_finish_packet (handle_packet);
7464 break;
7467 frv_finish_packet (handle_packet);
7468 dfa_finish ();
7469 return true;
7472 /* Subroutine of frv_sort_insn_group. We are trying to sort
7473 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7474 language order. We have already picked a new position for
7475 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7476 These instructions will occupy elements [0, LOWER_SLOT) and
7477 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7478 the DFA state after issuing these instructions.
7480 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7481 of the unused instructions. Return true if one such permutation gives
7482 a valid ordering, leaving the successful permutation in sorted[].
7483 Do not modify sorted[] until a valid permutation is found. */
7485 static bool
7486 frv_sort_insn_group_1 (enum frv_insn_group group,
7487 unsigned int lower_slot, unsigned int upper_slot,
7488 unsigned int issued, unsigned int num_insns,
7489 state_t state)
7491 struct frv_packet_group *packet_group;
7492 unsigned int i;
7493 state_t test_state;
7494 size_t dfa_size;
7495 rtx_insn *insn;
7497 /* Early success if we've filled all the slots. */
7498 if (lower_slot == upper_slot)
7499 return true;
7501 packet_group = &frv_packet.groups[group];
7502 dfa_size = state_size ();
7503 test_state = alloca (dfa_size);
7505 /* Try issuing each unused instruction. */
7506 for (i = num_insns - 1; i + 1 != 0; i--)
7507 if (~issued & (1 << i))
7509 insn = packet_group->sorted[i];
7510 memcpy (test_state, state, dfa_size);
7511 if (state_transition (test_state, insn) < 0
7512 && cpu_unit_reservation_p (test_state,
7513 NTH_UNIT (group, upper_slot - 1))
7514 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7515 issued | (1 << i), num_insns,
7516 test_state))
7518 packet_group->sorted[upper_slot - 1] = insn;
7519 return true;
7523 return false;
7526 /* Compare two instructions by their frv_insn_unit. */
7528 static int
7529 frv_compare_insns (const void *first, const void *second)
7531 rtx_insn * const *insn1 = (rtx_insn * const *) first;
7532 rtx_insn * const *insn2 = (rtx_insn * const *) second;
7533 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7536 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7537 and sort it into assembly language order. See frv.md for a description of
7538 the algorithm. */
7540 static void
7541 frv_sort_insn_group (enum frv_insn_group group)
7543 struct frv_packet_group *packet_group;
7544 unsigned int first, i, nop, max_unit, num_slots;
7545 state_t state, test_state;
7546 size_t dfa_size;
7548 packet_group = &frv_packet.groups[group];
7550 /* Assume no nop is needed. */
7551 packet_group->nop = 0;
7553 if (packet_group->num_insns == 0)
7554 return;
7556 /* Copy insns[] to sorted[]. */
7557 memcpy (packet_group->sorted, packet_group->insns,
7558 sizeof (rtx) * packet_group->num_insns);
7560 /* Sort sorted[] by the unit that each insn tries to take first. */
7561 if (packet_group->num_insns > 1)
7562 qsort (packet_group->sorted, packet_group->num_insns,
7563 sizeof (rtx), frv_compare_insns);
7565 /* That's always enough for branch and control insns. */
7566 if (group == GROUP_B || group == GROUP_C)
7567 return;
7569 dfa_size = state_size ();
7570 state = alloca (dfa_size);
7571 test_state = alloca (dfa_size);
7573 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7574 consecutively and such that the DFA takes unit X when sorted[X]
7575 is added. Set STATE to the new DFA state. */
7576 state_reset (test_state);
7577 for (first = 0; first < packet_group->num_insns; first++)
7579 memcpy (state, test_state, dfa_size);
7580 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7581 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7582 break;
7585 /* If all the instructions issued in ascending order, we're done. */
7586 if (first == packet_group->num_insns)
7587 return;
7589 /* Add nops to the end of sorted[] and try each permutation until
7590 we find one that works. */
7591 for (nop = 0; nop < frv_num_nops; nop++)
7593 max_unit = frv_insn_unit (frv_nops[nop]);
7594 if (frv_unit_groups[max_unit] == group)
7596 packet_group->nop = frv_nops[nop];
7597 num_slots = UNIT_NUMBER (max_unit) + 1;
7598 for (i = packet_group->num_insns; i < num_slots; i++)
7599 packet_group->sorted[i] = frv_nops[nop];
7600 if (frv_sort_insn_group_1 (group, first, num_slots,
7601 (1 << first) - 1, num_slots, state))
7602 return;
7605 gcc_unreachable ();
7608 /* Sort the current packet into assembly-language order. Set packing
7609 flags as appropriate. */
7611 static void
7612 frv_reorder_packet (void)
7614 unsigned int cursor[NUM_GROUPS];
7615 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7616 unsigned int unit, to, from;
7617 enum frv_insn_group group;
7618 struct frv_packet_group *packet_group;
7620 /* First sort each group individually. */
7621 for (group = GROUP_I; group < NUM_GROUPS;
7622 group = (enum frv_insn_group) (group + 1))
7624 cursor[group] = 0;
7625 frv_sort_insn_group (group);
7628 /* Go through the unit template and try add an instruction from
7629 that unit's group. */
7630 to = 0;
7631 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7633 group = frv_unit_groups[unit];
7634 packet_group = &frv_packet.groups[group];
7635 if (cursor[group] < packet_group->num_insns)
7637 /* frv_reorg should have added nops for us. */
7638 gcc_assert (packet_group->sorted[cursor[group]]
7639 != packet_group->nop);
7640 insns[to++] = packet_group->sorted[cursor[group]++];
7644 gcc_assert (to == frv_packet.num_insns);
7646 /* Clear the last instruction's packing flag, thus marking the end of
7647 a packet. Reorder the other instructions relative to it. */
7648 CLEAR_PACKING_FLAG (insns[to - 1]);
7649 for (from = 0; from < to - 1; from++)
7651 remove_insn (insns[from]);
7652 add_insn_before (insns[from], insns[to - 1], NULL);
7653 SET_PACKING_FLAG (insns[from]);
7658 /* Divide instructions into packets. Reorder the contents of each
7659 packet so that they are in the correct assembly-language order.
7661 Since this pass can change the raw meaning of the rtl stream, it must
7662 only be called at the last minute, just before the instructions are
7663 written out. */
7665 static void
7666 frv_pack_insns (void)
7668 if (frv_for_each_packet (frv_reorder_packet))
7669 frv_insn_packing_flag = 0;
7670 else
7671 frv_insn_packing_flag = -1;
7674 /* See whether we need to add nops to group GROUP in order to
7675 make a valid packet. */
7677 static void
7678 frv_fill_unused_units (enum frv_insn_group group)
7680 unsigned int non_nops, nops, i;
7681 struct frv_packet_group *packet_group;
7683 packet_group = &frv_packet.groups[group];
7685 /* Sort the instructions into assembly-language order.
7686 Use nops to fill slots that are otherwise unused. */
7687 frv_sort_insn_group (group);
7689 /* See how many nops are needed before the final useful instruction. */
7690 i = nops = 0;
7691 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7692 while (packet_group->sorted[i++] == packet_group->nop)
7693 nops++;
7695 /* Insert that many nops into the instruction stream. */
7696 while (nops-- > 0)
7697 frv_insert_nop_in_packet (packet_group->nop);
7700 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7702 static bool
7703 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7705 if (io1->const_address != 0 && io2->const_address != 0)
7706 return io1->const_address == io2->const_address;
7708 if (io1->var_address != 0 && io2->var_address != 0)
7709 return rtx_equal_p (io1->var_address, io2->var_address);
7711 return false;
7714 /* Return true if operations IO1 and IO2 are guaranteed to complete
7715 in order. */
7717 static bool
7718 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7720 /* The order of writes is always preserved. */
7721 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7722 return true;
7724 /* The order of reads isn't preserved. */
7725 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7726 return false;
7728 /* One operation is a write and the other is (or could be) a read.
7729 The order is only guaranteed if the accesses are to the same
7730 doubleword. */
7731 return frv_same_doubleword_p (io1, io2);
7734 /* Generalize I/O operation X so that it covers both X and Y. */
7736 static void
7737 frv_io_union (struct frv_io *x, const struct frv_io *y)
7739 if (x->type != y->type)
7740 x->type = FRV_IO_UNKNOWN;
7741 if (!frv_same_doubleword_p (x, y))
7743 x->const_address = 0;
7744 x->var_address = 0;
7748 /* Fill IO with information about the load or store associated with
7749 membar instruction INSN. */
7751 static void
7752 frv_extract_membar (struct frv_io *io, rtx_insn *insn)
7754 extract_insn (insn);
7755 io->type = (enum frv_io_type) INTVAL (recog_data.operand[2]);
7756 io->const_address = INTVAL (recog_data.operand[1]);
7757 io->var_address = XEXP (recog_data.operand[0], 0);
7760 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7761 if X is a register and *DATA depends on X. */
7763 static void
7764 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7766 rtx *other = (rtx *) data;
7768 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7769 *other = 0;
7772 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7773 Remove every modified register from the set. */
7775 static void
7776 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7778 HARD_REG_SET *set = (HARD_REG_SET *) data;
7779 unsigned int regno;
7781 if (REG_P (x))
7782 FOR_EACH_REGNO (regno, x)
7783 CLEAR_HARD_REG_BIT (*set, regno);
7786 /* A note_uses callback that adds all registers in *X to hard register
7787 set *DATA. */
7789 static void
7790 frv_io_handle_use (rtx *x, void *data)
7792 find_all_hard_regs (*x, (HARD_REG_SET *) data);
7795 /* Go through block BB looking for membars to remove. There are two
7796 cases where intra-block analysis is enough:
7798 - a membar is redundant if it occurs between two consecutive I/O
7799 operations and if those operations are guaranteed to complete
7800 in order.
7802 - a membar for a __builtin_read is redundant if the result is
7803 used before the next I/O operation is issued.
7805 If the last membar in the block could not be removed, and there
7806 are guaranteed to be no I/O operations between that membar and
7807 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7808 store null.
7810 Describe the block's first I/O operation in *NEXT_IO. Describe
7811 an unknown operation if the block doesn't do any I/O. */
7813 static void
7814 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7815 rtx_insn **last_membar)
7817 HARD_REG_SET used_regs;
7818 rtx next_membar, set;
7819 rtx_insn *insn;
7820 bool next_is_end_p;
7822 /* NEXT_IO is the next I/O operation to be performed after the current
7823 instruction. It starts off as being an unknown operation. */
7824 memset (next_io, 0, sizeof (*next_io));
7826 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7827 next_is_end_p = true;
7829 /* If the current instruction is a __builtin_read or __builtin_write,
7830 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7831 is null if the membar has already been deleted.
7833 Note that the initialization here should only be needed to
7834 suppress warnings. */
7835 next_membar = 0;
7837 /* USED_REGS is the set of registers that are used before the
7838 next I/O instruction. */
7839 CLEAR_HARD_REG_SET (used_regs);
7841 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7842 if (CALL_P (insn))
7844 /* We can't predict what a call will do to volatile memory. */
7845 memset (next_io, 0, sizeof (struct frv_io));
7846 next_is_end_p = false;
7847 CLEAR_HARD_REG_SET (used_regs);
7849 else if (INSN_P (insn))
7850 switch (recog_memoized (insn))
7852 case CODE_FOR_optional_membar_qi:
7853 case CODE_FOR_optional_membar_hi:
7854 case CODE_FOR_optional_membar_si:
7855 case CODE_FOR_optional_membar_di:
7856 next_membar = insn;
7857 if (next_is_end_p)
7859 /* Local information isn't enough to decide whether this
7860 membar is needed. Stash it away for later. */
7861 *last_membar = insn;
7862 frv_extract_membar (next_io, insn);
7863 next_is_end_p = false;
7865 else
7867 /* Check whether the I/O operation before INSN could be
7868 reordered with one described by NEXT_IO. If it can't,
7869 INSN will not be needed. */
7870 struct frv_io prev_io;
7872 frv_extract_membar (&prev_io, insn);
7873 if (frv_io_fixed_order_p (&prev_io, next_io))
7875 if (dump_file)
7876 fprintf (dump_file,
7877 ";; [Local] Removing membar %d since order"
7878 " of accesses is guaranteed\n",
7879 INSN_UID (next_membar));
7881 insn = NEXT_INSN (insn);
7882 delete_insn (next_membar);
7883 next_membar = 0;
7885 *next_io = prev_io;
7887 break;
7889 default:
7890 /* Invalidate NEXT_IO's address if it depends on something that
7891 is clobbered by INSN. */
7892 if (next_io->var_address)
7893 note_stores (PATTERN (insn), frv_io_check_address,
7894 &next_io->var_address);
7896 /* If the next membar is associated with a __builtin_read,
7897 see if INSN reads from that address. If it does, and if
7898 the destination register is used before the next I/O access,
7899 there is no need for the membar. */
7900 set = PATTERN (insn);
7901 if (next_io->type == FRV_IO_READ
7902 && next_io->var_address != 0
7903 && next_membar != 0
7904 && GET_CODE (set) == SET
7905 && GET_CODE (SET_DEST (set)) == REG
7906 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7908 rtx src;
7910 src = SET_SRC (set);
7911 if (GET_CODE (src) == ZERO_EXTEND)
7912 src = XEXP (src, 0);
7914 if (GET_CODE (src) == MEM
7915 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
7917 if (dump_file)
7918 fprintf (dump_file,
7919 ";; [Local] Removing membar %d since the target"
7920 " of %d is used before the I/O operation\n",
7921 INSN_UID (next_membar), INSN_UID (insn));
7923 if (next_membar == *last_membar)
7924 *last_membar = 0;
7926 delete_insn (next_membar);
7927 next_membar = 0;
7931 /* If INSN has volatile references, forget about any registers
7932 that are used after it. Otherwise forget about uses that
7933 are (or might be) defined by INSN. */
7934 if (volatile_refs_p (PATTERN (insn)))
7935 CLEAR_HARD_REG_SET (used_regs);
7936 else
7937 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
7939 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
7940 break;
7944 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7945 FIRST_IO[X] describes the first operation performed by basic block X. */
7947 static void
7948 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
7949 rtx_insn *membar)
7951 struct frv_io this_io, next_io;
7952 edge succ;
7953 edge_iterator ei;
7955 /* We need to keep the membar if there is an edge to the exit block. */
7956 FOR_EACH_EDGE (succ, ei, bb->succs)
7957 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7958 if (succ->dest == EXIT_BLOCK_PTR_FOR_FN (cfun))
7959 return;
7961 /* Work out the union of all successor blocks. */
7962 ei = ei_start (bb->succs);
7963 ei_cond (ei, &succ);
7964 /* next_io = first_io[bb->succ->dest->index]; */
7965 next_io = first_io[succ->dest->index];
7966 ei = ei_start (bb->succs);
7967 if (ei_cond (ei, &succ))
7969 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
7970 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7971 frv_io_union (&next_io, &first_io[succ->dest->index]);
7973 else
7974 gcc_unreachable ();
7976 frv_extract_membar (&this_io, membar);
7977 if (frv_io_fixed_order_p (&this_io, &next_io))
7979 if (dump_file)
7980 fprintf (dump_file,
7981 ";; [Global] Removing membar %d since order of accesses"
7982 " is guaranteed\n", INSN_UID (membar));
7984 delete_insn (membar);
7988 /* Remove redundant membars from the current function. */
7990 static void
7991 frv_optimize_membar (void)
7993 basic_block bb;
7994 struct frv_io *first_io;
7995 rtx_insn **last_membar;
7997 compute_bb_for_insn ();
7998 first_io = XCNEWVEC (struct frv_io, last_basic_block_for_fn (cfun));
7999 last_membar = XCNEWVEC (rtx_insn *, last_basic_block_for_fn (cfun));
8001 FOR_EACH_BB_FN (bb, cfun)
8002 frv_optimize_membar_local (bb, &first_io[bb->index],
8003 &last_membar[bb->index]);
8005 FOR_EACH_BB_FN (bb, cfun)
8006 if (last_membar[bb->index] != 0)
8007 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8009 free (first_io);
8010 free (last_membar);
8013 /* Used by frv_reorg to keep track of the current packet's address. */
8014 static unsigned int frv_packet_address;
8016 /* If the current packet falls through to a label, try to pad the packet
8017 with nops in order to fit the label's alignment requirements. */
8019 static void
8020 frv_align_label (void)
8022 unsigned int alignment, target, nop;
8023 rtx_insn *x, *last, *barrier, *label;
8025 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8026 maximum alignment of that packet, LABEL to the last label between
8027 the packets, and BARRIER to the last barrier. */
8028 last = frv_packet.insns[frv_packet.num_insns - 1];
8029 label = barrier = 0;
8030 alignment = 4;
8031 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8033 if (LABEL_P (x))
8035 unsigned int subalign = 1 << label_to_alignment (x);
8036 alignment = MAX (alignment, subalign);
8037 label = x;
8039 if (BARRIER_P (x))
8040 barrier = x;
8043 /* If -malign-labels, and the packet falls through to an unaligned
8044 label, try introducing a nop to align that label to 8 bytes. */
8045 if (TARGET_ALIGN_LABELS
8046 && label != 0
8047 && barrier == 0
8048 && frv_packet.num_insns < frv_packet.issue_rate)
8049 alignment = MAX (alignment, 8);
8051 /* Advance the address to the end of the current packet. */
8052 frv_packet_address += frv_packet.num_insns * 4;
8054 /* Work out the target address, after alignment. */
8055 target = (frv_packet_address + alignment - 1) & -alignment;
8057 /* If the packet falls through to the label, try to find an efficient
8058 padding sequence. */
8059 if (barrier == 0)
8061 /* First try adding nops to the current packet. */
8062 for (nop = 0; nop < frv_num_nops; nop++)
8063 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8065 frv_insert_nop_in_packet (frv_nops[nop]);
8066 frv_packet_address += 4;
8069 /* If we still haven't reached the target, add some new packets that
8070 contain only nops. If there are two types of nop, insert an
8071 alternating sequence of frv_nops[0] and frv_nops[1], which will
8072 lead to packets like:
8074 nop.p
8075 mnop.p/fnop.p
8076 nop.p
8077 mnop/fnop
8079 etc. Just emit frv_nops[0] if that's the only nop we have. */
8080 last = frv_packet.insns[frv_packet.num_insns - 1];
8081 nop = 0;
8082 while (frv_packet_address < target)
8084 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8085 frv_packet_address += 4;
8086 if (frv_num_nops > 1)
8087 nop ^= 1;
8091 frv_packet_address = target;
8094 /* Subroutine of frv_reorg, called after each packet has been constructed
8095 in frv_packet. */
8097 static void
8098 frv_reorg_packet (void)
8100 frv_fill_unused_units (GROUP_I);
8101 frv_fill_unused_units (GROUP_FM);
8102 frv_align_label ();
8105 /* Add an instruction with pattern NOP to frv_nops[]. */
8107 static void
8108 frv_register_nop (rtx nop)
8110 rtx_insn *nop_insn = make_insn_raw (nop);
8111 SET_NEXT_INSN (nop_insn) = 0;
8112 SET_PREV_INSN (nop_insn) = 0;
8113 frv_nops[frv_num_nops++] = nop_insn;
8116 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8117 into packets and check whether we need to insert nops in order to
8118 fulfill the processor's issue requirements. Also, if the user has
8119 requested a certain alignment for a label, try to meet that alignment
8120 by inserting nops in the previous packet. */
8122 static void
8123 frv_reorg (void)
8125 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8126 frv_optimize_membar ();
8128 frv_num_nops = 0;
8129 frv_register_nop (gen_nop ());
8130 if (TARGET_MEDIA)
8131 frv_register_nop (gen_mnop ());
8132 if (TARGET_HARD_FLOAT)
8133 frv_register_nop (gen_fnop ());
8135 /* Estimate the length of each branch. Although this may change after
8136 we've inserted nops, it will only do so in big functions. */
8137 shorten_branches (get_insns ());
8139 frv_packet_address = 0;
8140 frv_for_each_packet (frv_reorg_packet);
8143 #define def_builtin(name, type, code) \
8144 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8146 struct builtin_description
8148 enum insn_code icode;
8149 const char *name;
8150 enum frv_builtins code;
8151 enum rtx_code comparison;
8152 unsigned int flag;
8155 /* Media intrinsics that take a single, constant argument. */
8157 static struct builtin_description bdesc_set[] =
8159 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, UNKNOWN, 0 }
8162 /* Media intrinsics that take just one argument. */
8164 static struct builtin_description bdesc_1arg[] =
8166 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, UNKNOWN, 0 },
8167 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, UNKNOWN, 0 },
8168 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, UNKNOWN, 0 },
8169 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, UNKNOWN, 0},
8170 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, UNKNOWN, 0 },
8171 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, UNKNOWN, 0 }
8174 /* Media intrinsics that take two arguments. */
8176 static struct builtin_description bdesc_2arg[] =
8178 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, UNKNOWN, 0},
8179 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, UNKNOWN, 0},
8180 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, UNKNOWN, 0},
8181 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, UNKNOWN, 0},
8182 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, UNKNOWN, 0},
8183 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, UNKNOWN, 0},
8184 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, UNKNOWN, 0},
8185 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, UNKNOWN, 0},
8186 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, UNKNOWN, 0},
8187 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, UNKNOWN, 0},
8188 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, UNKNOWN, 0},
8189 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, UNKNOWN, 0},
8190 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, UNKNOWN, 0},
8191 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, UNKNOWN, 0},
8192 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, UNKNOWN, 0},
8193 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, UNKNOWN, 0},
8194 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, UNKNOWN, 0},
8195 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, UNKNOWN, 0},
8196 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, UNKNOWN, 0},
8197 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, UNKNOWN, 0},
8198 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, UNKNOWN, 0},
8199 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, UNKNOWN, 0},
8200 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, UNKNOWN, 0},
8201 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, UNKNOWN, 0},
8202 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, UNKNOWN, 0},
8203 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, UNKNOWN, 0},
8204 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, UNKNOWN, 0}
8207 /* Integer intrinsics that take two arguments and have no return value. */
8209 static struct builtin_description bdesc_int_void2arg[] =
8211 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, UNKNOWN, 0},
8212 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, UNKNOWN, 0},
8213 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, UNKNOWN, 0}
8216 static struct builtin_description bdesc_prefetches[] =
8218 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, UNKNOWN,
8220 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, UNKNOWN, 0}
8223 /* Media intrinsics that take two arguments, the first being an ACC number. */
8225 static struct builtin_description bdesc_cut[] =
8227 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, UNKNOWN, 0},
8228 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, UNKNOWN, 0},
8229 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, UNKNOWN, 0}
8232 /* Two-argument media intrinsics with an immediate second argument. */
8234 static struct builtin_description bdesc_2argimm[] =
8236 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, UNKNOWN, 0},
8237 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, UNKNOWN, 0},
8238 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, UNKNOWN, 0},
8239 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, UNKNOWN, 0},
8240 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, UNKNOWN, 0},
8241 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, UNKNOWN, 0},
8242 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, UNKNOWN, 0},
8243 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, UNKNOWN, 0},
8244 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, UNKNOWN, 0},
8245 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, UNKNOWN, 0},
8246 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, UNKNOWN, 0},
8247 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, UNKNOWN, 0},
8248 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, UNKNOWN, 0},
8249 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, UNKNOWN, 0},
8250 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, UNKNOWN, 0},
8251 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, UNKNOWN, 0},
8252 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, UNKNOWN, 0}
8255 /* Media intrinsics that take two arguments and return void, the first argument
8256 being a pointer to 4 words in memory. */
8258 static struct builtin_description bdesc_void2arg[] =
8260 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, UNKNOWN, 0},
8261 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, UNKNOWN, 0},
8264 /* Media intrinsics that take three arguments, the first being a const_int that
8265 denotes an accumulator, and that return void. */
8267 static struct builtin_description bdesc_void3arg[] =
8269 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, UNKNOWN, 0},
8270 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, UNKNOWN, 0},
8271 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, UNKNOWN, 0},
8272 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, UNKNOWN, 0},
8273 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, UNKNOWN, 0},
8274 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, UNKNOWN, 0},
8275 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, UNKNOWN, 0},
8276 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, UNKNOWN, 0},
8277 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, UNKNOWN, 0},
8278 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, UNKNOWN, 0},
8279 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, UNKNOWN, 0},
8280 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, UNKNOWN, 0},
8281 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, UNKNOWN, 0},
8282 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, UNKNOWN, 0},
8283 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, UNKNOWN, 0},
8284 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, UNKNOWN, 0},
8285 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, UNKNOWN, 0},
8286 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, UNKNOWN, 0},
8287 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, UNKNOWN, 0},
8288 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, UNKNOWN, 0},
8289 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, UNKNOWN, 0},
8290 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, UNKNOWN, 0},
8291 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, UNKNOWN, 0},
8292 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, UNKNOWN, 0},
8293 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, UNKNOWN, 0}
8296 /* Media intrinsics that take two accumulator numbers as argument and
8297 return void. */
8299 static struct builtin_description bdesc_voidacc[] =
8301 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, UNKNOWN, 0},
8302 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, UNKNOWN, 0},
8303 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, UNKNOWN, 0},
8304 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, UNKNOWN, 0},
8305 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, UNKNOWN, 0},
8306 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, UNKNOWN, 0}
8309 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8310 a normal move and the ICODE is for the membar. */
8312 static struct builtin_description bdesc_loads[] =
8314 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8315 FRV_BUILTIN_READ8, UNKNOWN, 0},
8316 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8317 FRV_BUILTIN_READ16, UNKNOWN, 0},
8318 { CODE_FOR_optional_membar_si, "__builtin_read32",
8319 FRV_BUILTIN_READ32, UNKNOWN, 0},
8320 { CODE_FOR_optional_membar_di, "__builtin_read64",
8321 FRV_BUILTIN_READ64, UNKNOWN, 0}
8324 /* Likewise stores. */
8326 static struct builtin_description bdesc_stores[] =
8328 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8329 FRV_BUILTIN_WRITE8, UNKNOWN, 0},
8330 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8331 FRV_BUILTIN_WRITE16, UNKNOWN, 0},
8332 { CODE_FOR_optional_membar_si, "__builtin_write32",
8333 FRV_BUILTIN_WRITE32, UNKNOWN, 0},
8334 { CODE_FOR_optional_membar_di, "__builtin_write64",
8335 FRV_BUILTIN_WRITE64, UNKNOWN, 0},
8338 /* Initialize media builtins. */
8340 static void
8341 frv_init_builtins (void)
8343 tree accumulator = integer_type_node;
8344 tree integer = integer_type_node;
8345 tree voidt = void_type_node;
8346 tree uhalf = short_unsigned_type_node;
8347 tree sword1 = long_integer_type_node;
8348 tree uword1 = long_unsigned_type_node;
8349 tree sword2 = long_long_integer_type_node;
8350 tree uword2 = long_long_unsigned_type_node;
8351 tree uword4 = build_pointer_type (uword1);
8352 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8353 tree ubyte = unsigned_char_type_node;
8354 tree iacc = integer_type_node;
8356 #define UNARY(RET, T1) \
8357 build_function_type_list (RET, T1, NULL_TREE)
8359 #define BINARY(RET, T1, T2) \
8360 build_function_type_list (RET, T1, T2, NULL_TREE)
8362 #define TRINARY(RET, T1, T2, T3) \
8363 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8365 #define QUAD(RET, T1, T2, T3, T4) \
8366 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8368 tree void_ftype_void = build_function_type_list (voidt, NULL_TREE);
8370 tree void_ftype_acc = UNARY (voidt, accumulator);
8371 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8372 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8373 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8374 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8375 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8376 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8377 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8378 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8380 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8381 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8382 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8383 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8384 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8385 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8386 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8387 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8388 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8389 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8390 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8392 tree sw1_ftype_int = UNARY (sword1, integer);
8393 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8394 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8396 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8397 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8398 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8399 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8400 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8401 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8403 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8404 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8405 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8406 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8407 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8408 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8409 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8410 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8411 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8412 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8413 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8414 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8415 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8416 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8417 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8418 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8419 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8421 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8422 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8423 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8424 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8425 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8426 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8427 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8428 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8429 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8430 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8431 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8432 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8433 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8434 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8435 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8436 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8437 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8438 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8439 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8440 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8441 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8442 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8443 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8444 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8445 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8446 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8447 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8448 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8449 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8450 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8451 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8452 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8453 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8454 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8455 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8456 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8457 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8458 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8459 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8460 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8461 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8462 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8463 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8464 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8465 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8466 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8467 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8468 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8469 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8470 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8471 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8472 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8473 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8474 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8475 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8476 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8477 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8478 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8479 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8480 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8481 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8482 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8483 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8484 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8485 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8486 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8487 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8488 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8489 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8490 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8491 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8492 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8493 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8494 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8495 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8496 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8497 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8498 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8499 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8500 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8501 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8502 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8503 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8504 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8505 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8506 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8507 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8508 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8509 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8510 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8511 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8512 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8513 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8514 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8515 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8516 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8517 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8518 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8519 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8520 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8521 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8522 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8523 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8524 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8525 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8526 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8527 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8528 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8530 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8531 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8532 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8533 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8535 #undef UNARY
8536 #undef BINARY
8537 #undef TRINARY
8538 #undef QUAD
8541 /* Set the names for various arithmetic operations according to the
8542 FRV ABI. */
8543 static void
8544 frv_init_libfuncs (void)
8546 set_optab_libfunc (smod_optab, SImode, "__modi");
8547 set_optab_libfunc (umod_optab, SImode, "__umodi");
8549 set_optab_libfunc (add_optab, DImode, "__addll");
8550 set_optab_libfunc (sub_optab, DImode, "__subll");
8551 set_optab_libfunc (smul_optab, DImode, "__mulll");
8552 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8553 set_optab_libfunc (smod_optab, DImode, "__modll");
8554 set_optab_libfunc (umod_optab, DImode, "__umodll");
8555 set_optab_libfunc (and_optab, DImode, "__andll");
8556 set_optab_libfunc (ior_optab, DImode, "__orll");
8557 set_optab_libfunc (xor_optab, DImode, "__xorll");
8558 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8560 set_optab_libfunc (add_optab, SFmode, "__addf");
8561 set_optab_libfunc (sub_optab, SFmode, "__subf");
8562 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8563 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8565 set_optab_libfunc (add_optab, DFmode, "__addd");
8566 set_optab_libfunc (sub_optab, DFmode, "__subd");
8567 set_optab_libfunc (smul_optab, DFmode, "__muld");
8568 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8570 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8571 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8573 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8574 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8575 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8576 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8578 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8579 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8580 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8581 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8583 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8584 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8585 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8586 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8589 /* Convert an integer constant to an accumulator register. ICODE is the
8590 code of the target instruction, OPNUM is the number of the
8591 accumulator operand and OPVAL is the constant integer. Try both
8592 ACC and ACCG registers; only report an error if neither fit the
8593 instruction. */
8595 static rtx
8596 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8598 rtx reg;
8599 int i;
8601 /* ACCs and ACCGs are implicit global registers if media intrinsics
8602 are being used. We set up this lazily to avoid creating lots of
8603 unnecessary call_insn rtl in non-media code. */
8604 for (i = 0; i <= ACC_MASK; i++)
8605 if ((i & ACC_MASK) == i)
8606 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8608 if (GET_CODE (opval) != CONST_INT)
8610 error ("accumulator is not a constant integer");
8611 return NULL_RTX;
8613 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8615 error ("accumulator number is out of bounds");
8616 return NULL_RTX;
8619 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8620 ACC_FIRST + INTVAL (opval));
8621 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8622 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8624 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8626 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8627 return NULL_RTX;
8629 return reg;
8632 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8633 should have. */
8635 static machine_mode
8636 frv_matching_accg_mode (machine_mode mode)
8638 switch (mode)
8640 case V4SImode:
8641 return V4QImode;
8643 case DImode:
8644 return HImode;
8646 case SImode:
8647 return QImode;
8649 default:
8650 gcc_unreachable ();
8654 /* Given that a __builtin_read or __builtin_write function is accessing
8655 address ADDRESS, return the value that should be used as operand 1
8656 of the membar. */
8658 static rtx
8659 frv_io_address_cookie (rtx address)
8661 return (GET_CODE (address) == CONST_INT
8662 ? GEN_INT (INTVAL (address) / 8 * 8)
8663 : const0_rtx);
8666 /* Return the accumulator guard that should be paired with accumulator
8667 register ACC. The mode of the returned register is in the same
8668 class as ACC, but is four times smaller. */
8671 frv_matching_accg_for_acc (rtx acc)
8673 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8674 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8677 /* Read the requested argument from the call EXP given by INDEX.
8678 Return the value as an rtx. */
8680 static rtx
8681 frv_read_argument (tree exp, unsigned int index)
8683 return expand_normal (CALL_EXPR_ARG (exp, index));
8686 /* Like frv_read_argument, but interpret the argument as the number
8687 of an IACC register and return a (reg:MODE ...) rtx for it. */
8689 static rtx
8690 frv_read_iacc_argument (machine_mode mode, tree call,
8691 unsigned int index)
8693 int i, regno;
8694 rtx op;
8696 op = frv_read_argument (call, index);
8697 if (GET_CODE (op) != CONST_INT
8698 || INTVAL (op) < 0
8699 || INTVAL (op) > IACC_LAST - IACC_FIRST
8700 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8702 error ("invalid IACC argument");
8703 op = const0_rtx;
8706 /* IACCs are implicit global registers. We set up this lazily to
8707 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8708 being used. */
8709 regno = INTVAL (op) + IACC_FIRST;
8710 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8711 global_regs[regno + i] = 1;
8713 return gen_rtx_REG (mode, regno);
8716 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8717 The instruction should require a constant operand of some sort. The
8718 function prints an error if OPVAL is not valid. */
8720 static int
8721 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8723 if (GET_CODE (opval) != CONST_INT)
8725 error ("%qs expects a constant argument", insn_data[icode].name);
8726 return FALSE;
8728 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8730 error ("constant argument out of range for %qs", insn_data[icode].name);
8731 return FALSE;
8733 return TRUE;
8736 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8737 if it's not null, has the right mode, and satisfies operand 0's
8738 predicate. */
8740 static rtx
8741 frv_legitimize_target (enum insn_code icode, rtx target)
8743 machine_mode mode = insn_data[icode].operand[0].mode;
8745 if (! target
8746 || GET_MODE (target) != mode
8747 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8748 return gen_reg_rtx (mode);
8749 else
8750 return target;
8753 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8754 check whether ARG satisfies the operand's constraints. If it doesn't,
8755 copy ARG to a temporary register and return that. Otherwise return ARG
8756 itself. */
8758 static rtx
8759 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8761 machine_mode mode = insn_data[icode].operand[opnum].mode;
8763 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8764 return arg;
8765 else
8766 return copy_to_mode_reg (mode, arg);
8769 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8771 static rtx
8772 frv_volatile_memref (machine_mode mode, rtx arg)
8774 rtx mem;
8776 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8777 MEM_VOLATILE_P (mem) = 1;
8778 return mem;
8781 /* Expand builtins that take a single, constant argument. At the moment,
8782 only MHDSETS falls into this category. */
8784 static rtx
8785 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8787 rtx pat;
8788 rtx op0 = frv_read_argument (call, 0);
8790 if (! frv_check_constant_argument (icode, 1, op0))
8791 return NULL_RTX;
8793 target = frv_legitimize_target (icode, target);
8794 pat = GEN_FCN (icode) (target, op0);
8795 if (! pat)
8796 return NULL_RTX;
8798 emit_insn (pat);
8799 return target;
8802 /* Expand builtins that take one operand. */
8804 static rtx
8805 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8807 rtx pat;
8808 rtx op0 = frv_read_argument (call, 0);
8810 target = frv_legitimize_target (icode, target);
8811 op0 = frv_legitimize_argument (icode, 1, op0);
8812 pat = GEN_FCN (icode) (target, op0);
8813 if (! pat)
8814 return NULL_RTX;
8816 emit_insn (pat);
8817 return target;
8820 /* Expand builtins that take two operands. */
8822 static rtx
8823 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8825 rtx pat;
8826 rtx op0 = frv_read_argument (call, 0);
8827 rtx op1 = frv_read_argument (call, 1);
8829 target = frv_legitimize_target (icode, target);
8830 op0 = frv_legitimize_argument (icode, 1, op0);
8831 op1 = frv_legitimize_argument (icode, 2, op1);
8832 pat = GEN_FCN (icode) (target, op0, op1);
8833 if (! pat)
8834 return NULL_RTX;
8836 emit_insn (pat);
8837 return target;
8840 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8841 one. */
8843 static rtx
8844 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8846 rtx pat;
8847 rtx op0 = frv_read_argument (call, 0);
8848 rtx op1 = frv_read_argument (call, 1);
8849 rtx op2;
8851 target = frv_legitimize_target (icode, target);
8852 op0 = frv_int_to_acc (icode, 1, op0);
8853 if (! op0)
8854 return NULL_RTX;
8856 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8858 if (! frv_check_constant_argument (icode, 2, op1))
8859 return NULL_RTX;
8861 else
8862 op1 = frv_legitimize_argument (icode, 2, op1);
8864 op2 = frv_matching_accg_for_acc (op0);
8865 pat = GEN_FCN (icode) (target, op0, op1, op2);
8866 if (! pat)
8867 return NULL_RTX;
8869 emit_insn (pat);
8870 return target;
8873 /* Expand builtins that take two operands and the second is immediate. */
8875 static rtx
8876 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8878 rtx pat;
8879 rtx op0 = frv_read_argument (call, 0);
8880 rtx op1 = frv_read_argument (call, 1);
8882 if (! frv_check_constant_argument (icode, 2, op1))
8883 return NULL_RTX;
8885 target = frv_legitimize_target (icode, target);
8886 op0 = frv_legitimize_argument (icode, 1, op0);
8887 pat = GEN_FCN (icode) (target, op0, op1);
8888 if (! pat)
8889 return NULL_RTX;
8891 emit_insn (pat);
8892 return target;
8895 /* Expand builtins that take two operands, the first operand being a pointer to
8896 ints and return void. */
8898 static rtx
8899 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8901 rtx pat;
8902 rtx op0 = frv_read_argument (call, 0);
8903 rtx op1 = frv_read_argument (call, 1);
8904 machine_mode mode0 = insn_data[icode].operand[0].mode;
8905 rtx addr;
8907 if (GET_CODE (op0) != MEM)
8909 rtx reg = op0;
8911 if (! offsettable_address_p (0, mode0, op0))
8913 reg = gen_reg_rtx (Pmode);
8914 emit_insn (gen_rtx_SET (reg, op0));
8917 op0 = gen_rtx_MEM (SImode, reg);
8920 addr = XEXP (op0, 0);
8921 if (! offsettable_address_p (0, mode0, addr))
8922 addr = copy_to_mode_reg (Pmode, op0);
8924 op0 = change_address (op0, V4SImode, addr);
8925 op1 = frv_legitimize_argument (icode, 1, op1);
8926 pat = GEN_FCN (icode) (op0, op1);
8927 if (! pat)
8928 return 0;
8930 emit_insn (pat);
8931 return 0;
8934 /* Expand builtins that take two long operands and return void. */
8936 static rtx
8937 frv_expand_int_void2arg (enum insn_code icode, tree call)
8939 rtx pat;
8940 rtx op0 = frv_read_argument (call, 0);
8941 rtx op1 = frv_read_argument (call, 1);
8943 op0 = frv_legitimize_argument (icode, 1, op0);
8944 op1 = frv_legitimize_argument (icode, 1, op1);
8945 pat = GEN_FCN (icode) (op0, op1);
8946 if (! pat)
8947 return NULL_RTX;
8949 emit_insn (pat);
8950 return NULL_RTX;
8953 /* Expand prefetch builtins. These take a single address as argument. */
8955 static rtx
8956 frv_expand_prefetches (enum insn_code icode, tree call)
8958 rtx pat;
8959 rtx op0 = frv_read_argument (call, 0);
8961 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
8962 if (! pat)
8963 return 0;
8965 emit_insn (pat);
8966 return 0;
8969 /* Expand builtins that take three operands and return void. The first
8970 argument must be a constant that describes a pair or quad accumulators. A
8971 fourth argument is created that is the accumulator guard register that
8972 corresponds to the accumulator. */
8974 static rtx
8975 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
8977 rtx pat;
8978 rtx op0 = frv_read_argument (call, 0);
8979 rtx op1 = frv_read_argument (call, 1);
8980 rtx op2 = frv_read_argument (call, 2);
8981 rtx op3;
8983 op0 = frv_int_to_acc (icode, 0, op0);
8984 if (! op0)
8985 return NULL_RTX;
8987 op1 = frv_legitimize_argument (icode, 1, op1);
8988 op2 = frv_legitimize_argument (icode, 2, op2);
8989 op3 = frv_matching_accg_for_acc (op0);
8990 pat = GEN_FCN (icode) (op0, op1, op2, op3);
8991 if (! pat)
8992 return NULL_RTX;
8994 emit_insn (pat);
8995 return NULL_RTX;
8998 /* Expand builtins that perform accumulator-to-accumulator operations.
8999 These builtins take two accumulator numbers as argument and return
9000 void. */
9002 static rtx
9003 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9005 rtx pat;
9006 rtx op0 = frv_read_argument (call, 0);
9007 rtx op1 = frv_read_argument (call, 1);
9008 rtx op2;
9009 rtx op3;
9011 op0 = frv_int_to_acc (icode, 0, op0);
9012 if (! op0)
9013 return NULL_RTX;
9015 op1 = frv_int_to_acc (icode, 1, op1);
9016 if (! op1)
9017 return NULL_RTX;
9019 op2 = frv_matching_accg_for_acc (op0);
9020 op3 = frv_matching_accg_for_acc (op1);
9021 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9022 if (! pat)
9023 return NULL_RTX;
9025 emit_insn (pat);
9026 return NULL_RTX;
9029 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9030 membar and TARGET_MODE is the mode that the loaded value should have. */
9032 static rtx
9033 frv_expand_load_builtin (enum insn_code icode, machine_mode target_mode,
9034 tree call, rtx target)
9036 rtx op0 = frv_read_argument (call, 0);
9037 rtx cookie = frv_io_address_cookie (op0);
9039 if (target == 0 || !REG_P (target))
9040 target = gen_reg_rtx (target_mode);
9041 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9042 convert_move (target, op0, 1);
9043 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9044 cfun->machine->has_membar_p = 1;
9045 return target;
9048 /* Likewise __builtin_write* functions. */
9050 static rtx
9051 frv_expand_store_builtin (enum insn_code icode, tree call)
9053 rtx op0 = frv_read_argument (call, 0);
9054 rtx op1 = frv_read_argument (call, 1);
9055 rtx cookie = frv_io_address_cookie (op0);
9057 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9058 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9059 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9060 cfun->machine->has_membar_p = 1;
9061 return NULL_RTX;
9064 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9065 each argument forms one word of the two double-word input registers.
9066 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9067 to put the return value. */
9069 static rtx
9070 frv_expand_mdpackh_builtin (tree call, rtx target)
9072 enum insn_code icode = CODE_FOR_mdpackh;
9073 rtx pat, op0, op1;
9074 rtx arg1 = frv_read_argument (call, 0);
9075 rtx arg2 = frv_read_argument (call, 1);
9076 rtx arg3 = frv_read_argument (call, 2);
9077 rtx arg4 = frv_read_argument (call, 3);
9079 target = frv_legitimize_target (icode, target);
9080 op0 = gen_reg_rtx (DImode);
9081 op1 = gen_reg_rtx (DImode);
9083 /* The high half of each word is not explicitly initialized, so indicate
9084 that the input operands are not live before this point. */
9085 emit_clobber (op0);
9086 emit_clobber (op1);
9088 /* Move each argument into the low half of its associated input word. */
9089 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9090 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9091 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9092 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9094 pat = GEN_FCN (icode) (target, op0, op1);
9095 if (! pat)
9096 return NULL_RTX;
9098 emit_insn (pat);
9099 return target;
9102 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9103 number as argument. */
9105 static rtx
9106 frv_expand_mclracc_builtin (tree call)
9108 enum insn_code icode = CODE_FOR_mclracc;
9109 rtx pat;
9110 rtx op0 = frv_read_argument (call, 0);
9112 op0 = frv_int_to_acc (icode, 0, op0);
9113 if (! op0)
9114 return NULL_RTX;
9116 pat = GEN_FCN (icode) (op0);
9117 if (pat)
9118 emit_insn (pat);
9120 return NULL_RTX;
9123 /* Expand builtins that take no arguments. */
9125 static rtx
9126 frv_expand_noargs_builtin (enum insn_code icode)
9128 rtx pat = GEN_FCN (icode) (const0_rtx);
9129 if (pat)
9130 emit_insn (pat);
9132 return NULL_RTX;
9135 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9136 number or accumulator guard number as argument and return an SI integer. */
9138 static rtx
9139 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9141 rtx pat;
9142 rtx target = gen_reg_rtx (SImode);
9143 rtx op0 = frv_read_argument (call, 0);
9145 op0 = frv_int_to_acc (icode, 1, op0);
9146 if (! op0)
9147 return NULL_RTX;
9149 pat = GEN_FCN (icode) (target, op0);
9150 if (! pat)
9151 return NULL_RTX;
9153 emit_insn (pat);
9154 return target;
9157 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9158 accumulator guard as their first argument and an SImode value as their
9159 second. */
9161 static rtx
9162 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9164 rtx pat;
9165 rtx op0 = frv_read_argument (call, 0);
9166 rtx op1 = frv_read_argument (call, 1);
9168 op0 = frv_int_to_acc (icode, 0, op0);
9169 if (! op0)
9170 return NULL_RTX;
9172 op1 = frv_legitimize_argument (icode, 1, op1);
9173 pat = GEN_FCN (icode) (op0, op1);
9174 if (pat)
9175 emit_insn (pat);
9177 return NULL_RTX;
9180 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9181 to move DImode values into and out of IACC0. */
9183 static void
9184 frv_split_iacc_move (rtx dest, rtx src)
9186 machine_mode inner;
9187 int i;
9189 inner = GET_MODE (dest);
9190 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9191 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9192 simplify_gen_subreg (SImode, src, inner, i));
9195 /* Expand builtins. */
9197 static rtx
9198 frv_expand_builtin (tree exp,
9199 rtx target,
9200 rtx subtarget ATTRIBUTE_UNUSED,
9201 machine_mode mode ATTRIBUTE_UNUSED,
9202 int ignore ATTRIBUTE_UNUSED)
9204 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9205 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9206 unsigned i;
9207 struct builtin_description *d;
9209 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9211 error ("media functions are not available unless -mmedia is used");
9212 return NULL_RTX;
9215 switch (fcode)
9217 case FRV_BUILTIN_MCOP1:
9218 case FRV_BUILTIN_MCOP2:
9219 case FRV_BUILTIN_MDUNPACKH:
9220 case FRV_BUILTIN_MBTOHE:
9221 if (! TARGET_MEDIA_REV1)
9223 error ("this media function is only available on the fr500");
9224 return NULL_RTX;
9226 break;
9228 case FRV_BUILTIN_MQXMACHS:
9229 case FRV_BUILTIN_MQXMACXHS:
9230 case FRV_BUILTIN_MQMACXHS:
9231 case FRV_BUILTIN_MADDACCS:
9232 case FRV_BUILTIN_MSUBACCS:
9233 case FRV_BUILTIN_MASACCS:
9234 case FRV_BUILTIN_MDADDACCS:
9235 case FRV_BUILTIN_MDSUBACCS:
9236 case FRV_BUILTIN_MDASACCS:
9237 case FRV_BUILTIN_MABSHS:
9238 case FRV_BUILTIN_MDROTLI:
9239 case FRV_BUILTIN_MCPLHI:
9240 case FRV_BUILTIN_MCPLI:
9241 case FRV_BUILTIN_MDCUTSSI:
9242 case FRV_BUILTIN_MQSATHS:
9243 case FRV_BUILTIN_MHSETLOS:
9244 case FRV_BUILTIN_MHSETLOH:
9245 case FRV_BUILTIN_MHSETHIS:
9246 case FRV_BUILTIN_MHSETHIH:
9247 case FRV_BUILTIN_MHDSETS:
9248 case FRV_BUILTIN_MHDSETH:
9249 if (! TARGET_MEDIA_REV2)
9251 error ("this media function is only available on the fr400"
9252 " and fr550");
9253 return NULL_RTX;
9255 break;
9257 case FRV_BUILTIN_SMASS:
9258 case FRV_BUILTIN_SMSSS:
9259 case FRV_BUILTIN_SMU:
9260 case FRV_BUILTIN_ADDSS:
9261 case FRV_BUILTIN_SUBSS:
9262 case FRV_BUILTIN_SLASS:
9263 case FRV_BUILTIN_SCUTSS:
9264 case FRV_BUILTIN_IACCreadll:
9265 case FRV_BUILTIN_IACCreadl:
9266 case FRV_BUILTIN_IACCsetll:
9267 case FRV_BUILTIN_IACCsetl:
9268 if (!TARGET_FR405_BUILTINS)
9270 error ("this builtin function is only available"
9271 " on the fr405 and fr450");
9272 return NULL_RTX;
9274 break;
9276 case FRV_BUILTIN_PREFETCH:
9277 if (!TARGET_FR500_FR550_BUILTINS)
9279 error ("this builtin function is only available on the fr500"
9280 " and fr550");
9281 return NULL_RTX;
9283 break;
9285 case FRV_BUILTIN_MQLCLRHS:
9286 case FRV_BUILTIN_MQLMTHS:
9287 case FRV_BUILTIN_MQSLLHI:
9288 case FRV_BUILTIN_MQSRAHI:
9289 if (!TARGET_MEDIA_FR450)
9291 error ("this builtin function is only available on the fr450");
9292 return NULL_RTX;
9294 break;
9296 default:
9297 break;
9300 /* Expand unique builtins. */
9302 switch (fcode)
9304 case FRV_BUILTIN_MTRAP:
9305 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9307 case FRV_BUILTIN_MCLRACC:
9308 return frv_expand_mclracc_builtin (exp);
9310 case FRV_BUILTIN_MCLRACCA:
9311 if (TARGET_ACC_8)
9312 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9313 else
9314 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9316 case FRV_BUILTIN_MRDACC:
9317 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9319 case FRV_BUILTIN_MRDACCG:
9320 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9322 case FRV_BUILTIN_MWTACC:
9323 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9325 case FRV_BUILTIN_MWTACCG:
9326 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9328 case FRV_BUILTIN_MDPACKH:
9329 return frv_expand_mdpackh_builtin (exp, target);
9331 case FRV_BUILTIN_IACCreadll:
9333 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9334 if (target == 0 || !REG_P (target))
9335 target = gen_reg_rtx (DImode);
9336 frv_split_iacc_move (target, src);
9337 return target;
9340 case FRV_BUILTIN_IACCreadl:
9341 return frv_read_iacc_argument (SImode, exp, 0);
9343 case FRV_BUILTIN_IACCsetll:
9345 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9346 rtx src = frv_read_argument (exp, 1);
9347 frv_split_iacc_move (dest, force_reg (DImode, src));
9348 return 0;
9351 case FRV_BUILTIN_IACCsetl:
9353 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9354 rtx src = frv_read_argument (exp, 1);
9355 emit_move_insn (dest, force_reg (SImode, src));
9356 return 0;
9359 default:
9360 break;
9363 /* Expand groups of builtins. */
9365 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9366 if (d->code == fcode)
9367 return frv_expand_set_builtin (d->icode, exp, target);
9369 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9370 if (d->code == fcode)
9371 return frv_expand_unop_builtin (d->icode, exp, target);
9373 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9374 if (d->code == fcode)
9375 return frv_expand_binop_builtin (d->icode, exp, target);
9377 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9378 if (d->code == fcode)
9379 return frv_expand_cut_builtin (d->icode, exp, target);
9381 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9382 if (d->code == fcode)
9383 return frv_expand_binopimm_builtin (d->icode, exp, target);
9385 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9386 if (d->code == fcode)
9387 return frv_expand_voidbinop_builtin (d->icode, exp);
9389 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9390 if (d->code == fcode)
9391 return frv_expand_voidtriop_builtin (d->icode, exp);
9393 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9394 if (d->code == fcode)
9395 return frv_expand_voidaccop_builtin (d->icode, exp);
9397 for (i = 0, d = bdesc_int_void2arg;
9398 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9399 if (d->code == fcode)
9400 return frv_expand_int_void2arg (d->icode, exp);
9402 for (i = 0, d = bdesc_prefetches;
9403 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9404 if (d->code == fcode)
9405 return frv_expand_prefetches (d->icode, exp);
9407 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9408 if (d->code == fcode)
9409 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9410 exp, target);
9412 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9413 if (d->code == fcode)
9414 return frv_expand_store_builtin (d->icode, exp);
9416 return 0;
9419 static bool
9420 frv_in_small_data_p (const_tree decl)
9422 HOST_WIDE_INT size;
9423 const char *section_name;
9425 /* Don't apply the -G flag to internal compiler structures. We
9426 should leave such structures in the main data section, partly
9427 for efficiency and partly because the size of some of them
9428 (such as C++ typeinfos) is not known until later. */
9429 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9430 return false;
9432 /* If we already know which section the decl should be in, see if
9433 it's a small data section. */
9434 section_name = DECL_SECTION_NAME (decl);
9435 if (section_name)
9437 if (frv_string_begins_with (section_name, ".sdata"))
9438 return true;
9439 if (frv_string_begins_with (section_name, ".sbss"))
9440 return true;
9441 return false;
9444 size = int_size_in_bytes (TREE_TYPE (decl));
9445 if (size > 0 && size <= g_switch_value)
9446 return true;
9448 return false;
9451 static bool
9452 frv_rtx_costs (rtx x,
9453 machine_mode mode,
9454 int outer_code,
9455 int opno ATTRIBUTE_UNUSED,
9456 int *total,
9457 bool speed ATTRIBUTE_UNUSED)
9459 int code = GET_CODE (x);
9461 if (outer_code == MEM)
9463 /* Don't differentiate between memory addresses. All the ones
9464 we accept have equal cost. */
9465 *total = COSTS_N_INSNS (0);
9466 return true;
9469 switch (code)
9471 case CONST_INT:
9472 /* Make 12-bit integers really cheap. */
9473 if (IN_RANGE (INTVAL (x), -2048, 2047))
9475 *total = 0;
9476 return true;
9478 /* Fall through. */
9480 case CONST:
9481 case LABEL_REF:
9482 case SYMBOL_REF:
9483 case CONST_DOUBLE:
9484 *total = COSTS_N_INSNS (2);
9485 return true;
9487 case PLUS:
9488 case MINUS:
9489 case AND:
9490 case IOR:
9491 case XOR:
9492 case ASHIFT:
9493 case ASHIFTRT:
9494 case LSHIFTRT:
9495 case NOT:
9496 case NEG:
9497 case COMPARE:
9498 if (mode == SImode)
9499 *total = COSTS_N_INSNS (1);
9500 else if (mode == DImode)
9501 *total = COSTS_N_INSNS (2);
9502 else
9503 *total = COSTS_N_INSNS (3);
9504 return true;
9506 case MULT:
9507 if (mode == SImode)
9508 *total = COSTS_N_INSNS (2);
9509 else
9510 *total = COSTS_N_INSNS (6); /* guess */
9511 return true;
9513 case DIV:
9514 case UDIV:
9515 case MOD:
9516 case UMOD:
9517 *total = COSTS_N_INSNS (18);
9518 return true;
9520 case MEM:
9521 *total = COSTS_N_INSNS (3);
9522 return true;
9524 default:
9525 return false;
9529 static void
9530 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9532 switch_to_section (ctors_section);
9533 assemble_align (POINTER_SIZE);
9534 if (TARGET_FDPIC)
9536 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9538 gcc_assert (ok);
9539 return;
9541 assemble_integer_with_op ("\t.picptr\t", symbol);
9544 static void
9545 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9547 switch_to_section (dtors_section);
9548 assemble_align (POINTER_SIZE);
9549 if (TARGET_FDPIC)
9551 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9553 gcc_assert (ok);
9554 return;
9556 assemble_integer_with_op ("\t.picptr\t", symbol);
9559 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9561 static rtx
9562 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9563 int incoming ATTRIBUTE_UNUSED)
9565 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9568 #define TLS_BIAS (2048 - 16)
9570 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9571 We need to emit DTP-relative relocations. */
9573 static void
9574 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9576 gcc_assert (size == 4);
9577 fputs ("\t.picptr\ttlsmoff(", file);
9578 /* We want the unbiased TLS offset, so add the bias to the
9579 expression, such that the implicit biasing cancels out. */
9580 output_addr_const (file, plus_constant (Pmode, x, TLS_BIAS));
9581 fputs (")", file);
9584 #include "gt-frv.h"