1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (STACK_POINTER_REGNUM 1)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
38 (ARG_POINTER_REGNUM 67)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
55 (FRAME_POINTER_REGNUM 113)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
114 UNSPEC_MACHOPIC_OFFSET
126 UNSPEC_P8V_RELOAD_FROM_GPR
129 UNSPEC_P8V_RELOAD_FROM_VSX
143 ;; UNSPEC_VOLATILE usage
146 (define_c_enum "unspecv"
148 UNSPECV_LL ; load-locked
149 UNSPECV_SC ; store-conditional
150 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
151 UNSPECV_EH_RR ; eh_reg_restore
152 UNSPECV_ISYNC ; isync instruction
153 UNSPECV_MFTB ; move from time base
154 UNSPECV_NLGR ; non-local goto receiver
155 UNSPECV_MFFS ; Move from FPSCR
156 UNSPECV_MTFSF ; Move to FPSCR Fields
160 ;; Define an insn type attribute. This is used in function unit delay
164 add,logical,shift,insert,
166 exts,cntlz,popcnt,isel,
167 load,store,fpload,fpstore,vecload,vecstore,
169 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
171 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
172 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
174 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
175 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
177 (const_string "integer"))
179 ;; What data size does this instruction work on?
180 ;; This is used for insert, mul.
181 (define_attr "size" "8,16,32,64" (const_string "32"))
183 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
184 ;; This is used for add, logical, shift, mul.
185 (define_attr "dot" "no,yes" (const_string "no"))
187 ;; Does this instruction sign-extend its result?
188 ;; This is used for load insns.
189 (define_attr "sign_extend" "no,yes" (const_string "no"))
191 ;; Does this instruction use indexed (that is, reg+reg) addressing?
192 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
193 ;; it is automatically set based on that. If a load or store instruction
194 ;; has fewer than two operands it needs to set this attribute manually
195 ;; or the compiler will crash.
196 (define_attr "indexed" "no,yes"
197 (if_then_else (ior (match_operand 0 "indexed_address_mem")
198 (match_operand 1 "indexed_address_mem"))
200 (const_string "no")))
202 ;; Does this instruction use update addressing?
203 ;; This is used for load and store insns. See the comments for "indexed".
204 (define_attr "update" "no,yes"
205 (if_then_else (ior (match_operand 0 "update_address_mem")
206 (match_operand 1 "update_address_mem"))
208 (const_string "no")))
210 ;; Is this instruction using operands[2] as shift amount, and can that be a
212 ;; This is used for shift insns.
213 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
215 ;; Is this instruction using a shift amount from a register?
216 ;; This is used for shift insns.
217 (define_attr "var_shift" "no,yes"
218 (if_then_else (and (eq_attr "type" "shift")
219 (eq_attr "maybe_var_shift" "yes"))
220 (if_then_else (match_operand 2 "gpc_reg_operand")
223 (const_string "no")))
225 ;; Define floating point instruction sub-types for use with Xfpu.md
226 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
228 ;; Length (in bytes).
229 ; '(pc)' in the following doesn't include the instruction itself; it is
230 ; calculated as if the instruction had zero size.
231 (define_attr "length" ""
232 (if_then_else (eq_attr "type" "branch")
233 (if_then_else (and (ge (minus (match_dup 0) (pc))
235 (lt (minus (match_dup 0) (pc))
241 ;; Processor type -- this attribute must exactly match the processor_type
242 ;; enumeration in rs6000-opts.h.
244 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
245 ppc750,ppc7400,ppc7450,
246 ppc403,ppc405,ppc440,ppc476,
247 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
248 power4,power5,power6,power7,power8,
249 rs64a,mpccore,cell,ppca2,titan"
250 (const (symbol_ref "rs6000_cpu_attr")))
253 ;; If this instruction is microcoded on the CELL processor
254 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
255 (define_attr "cell_micro" "not,conditional,always"
256 (if_then_else (ior (eq_attr "type" "compare")
257 (and (eq_attr "type" "shift,mul")
258 (eq_attr "dot" "yes"))
259 (and (eq_attr "type" "load")
260 (eq_attr "sign_extend" "yes"))
261 (and (eq_attr "type" "shift")
262 (eq_attr "var_shift" "yes")))
263 (const_string "always")
264 (const_string "not")))
266 (automata_option "ndfa")
279 (include "e300c2c3.md")
280 (include "e500mc.md")
281 (include "e500mc64.md")
284 (include "power4.md")
285 (include "power5.md")
286 (include "power6.md")
287 (include "power7.md")
288 (include "power8.md")
294 (include "predicates.md")
295 (include "constraints.md")
297 (include "darwin.md")
302 ; This mode iterator allows :GPR to be used to indicate the allowable size
303 ; of whole values in GPRs.
304 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
306 ; Any supported integer mode.
307 (define_mode_iterator INT [QI HI SI DI TI PTI])
309 ; Any supported integer mode that fits in one register.
310 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
312 ; extend modes for DImode
313 (define_mode_iterator QHSI [QI HI SI])
315 ; QImode or HImode for small atomic ops
316 (define_mode_iterator QHI [QI HI])
318 ; HImode or SImode for sign extended fusion ops
319 (define_mode_iterator HSI [HI SI])
321 ; SImode or DImode, even if DImode doesn't fit in GPRs.
322 (define_mode_iterator SDI [SI DI])
324 ; The size of a pointer. Also, the size of the value that a record-condition
325 ; (one with a '.') will compare; and the size used for arithmetic carries.
326 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
328 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
329 ; PTImode is GPR only)
330 (define_mode_iterator TI2 [TI PTI])
332 ; Any hardware-supported floating-point mode
333 (define_mode_iterator FP [
334 (SF "TARGET_HARD_FLOAT
335 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
336 (DF "TARGET_HARD_FLOAT
337 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
338 (TF "!TARGET_IEEEQUAD
340 && (TARGET_FPRS || TARGET_E500_DOUBLE)
341 && TARGET_LONG_DOUBLE_128")
345 ; Any fma capable floating-point mode.
346 (define_mode_iterator FMA_F [
347 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
348 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
349 || VECTOR_UNIT_VSX_P (DFmode)")
350 (V2SF "TARGET_PAIRED_FLOAT")
351 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
352 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
355 ; Floating point move iterators to combine binary and decimal moves
356 (define_mode_iterator FMOVE32 [SF SD])
357 (define_mode_iterator FMOVE64 [DF DD])
358 (define_mode_iterator FMOVE64X [DI DF DD])
359 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
360 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
362 ; Iterators for 128 bit types for direct move
363 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
372 ; Whether a floating point move is ok, don't allow SD without hardware FP
373 (define_mode_attr fmove_ok [(SF "")
375 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
378 ; Convert REAL_VALUE to the appropriate bits
379 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
380 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
381 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
382 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
384 ; Definitions for load to 32-bit fpr register
385 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
386 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
387 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
388 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
390 ; Definitions for store from 32-bit fpr register
391 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
392 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
393 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
394 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
396 ; Definitions for 32-bit fpr direct move
397 (define_mode_attr f32_dm [(SF "wn") (SD "wm")])
399 ; These modes do not fit in integer registers in 32-bit mode.
400 ; but on e500v2, the gpr are 64 bit registers
401 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
403 ; Iterator for reciprocal estimate instructions
404 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
406 ; Iterator for just SF/DF
407 (define_mode_iterator SFDF [SF DF])
409 ; SF/DF suffix for traditional floating instructions
410 (define_mode_attr Ftrad [(SF "s") (DF "")])
412 ; SF/DF suffix for VSX instructions
413 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
415 ; SF/DF constraint for arithmetic on traditional floating point registers
416 (define_mode_attr Ff [(SF "f") (DF "d")])
418 ; SF/DF constraint for arithmetic on VSX registers
419 (define_mode_attr Fv [(SF "wy") (DF "ws")])
421 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
422 (define_mode_attr Fs [(SF "s") (DF "d")])
425 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
426 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
428 ; Conditional returns.
429 (define_code_iterator any_return [return simple_return])
430 (define_code_attr return_pred [(return "direct_return ()")
431 (simple_return "1")])
432 (define_code_attr return_str [(return "") (simple_return "simple_")])
434 ; Various instructions that come in SI and DI forms.
435 ; A generic w/d attribute, for things like cmpw/cmpd.
436 (define_mode_attr wd [(QI "b")
445 ;; How many bits in this mode?
446 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
449 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
451 ;; ISEL/ISEL64 target selection
452 (define_mode_attr sel [(SI "") (DI "64")])
454 ;; Bitmask for shift instructions
455 (define_mode_attr hH [(SI "h") (DI "H")])
457 ;; Suffix for reload patterns
458 (define_mode_attr ptrsize [(SI "32bit")
461 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
462 (DI "TARGET_64BIT")])
464 (define_mode_attr mptrsize [(SI "si")
467 (define_mode_attr ptrload [(SI "lwz")
470 (define_mode_attr ptrm [(SI "m")
473 (define_mode_attr rreg [(SF "f")
480 (define_mode_attr rreg2 [(SF "f")
483 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
484 (DF "TARGET_FCFID")])
486 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
487 (DF "TARGET_E500_DOUBLE")])
489 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
490 (DF "TARGET_DOUBLE_FLOAT")])
492 ;; Mode iterator for logical operations on 128-bit types
493 (define_mode_iterator BOOL_128 [TI
495 (V16QI "TARGET_ALTIVEC")
496 (V8HI "TARGET_ALTIVEC")
497 (V4SI "TARGET_ALTIVEC")
498 (V4SF "TARGET_ALTIVEC")
499 (V2DI "TARGET_ALTIVEC")
500 (V2DF "TARGET_ALTIVEC")
501 (V1TI "TARGET_ALTIVEC")])
503 ;; For the GPRs we use 3 constraints for register outputs, two that are the
504 ;; same as the output register, and a third where the output register is an
505 ;; early clobber, so we don't have to deal with register overlaps. For the
506 ;; vector types, we prefer to use the vector registers. For TI mode, allow
509 ;; Mode attribute for boolean operation register constraints for output
510 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
512 (V16QI "wa,v,&?r,?r,?r")
513 (V8HI "wa,v,&?r,?r,?r")
514 (V4SI "wa,v,&?r,?r,?r")
515 (V4SF "wa,v,&?r,?r,?r")
516 (V2DI "wa,v,&?r,?r,?r")
517 (V2DF "wa,v,&?r,?r,?r")
518 (V1TI "wa,v,&?r,?r,?r")])
520 ;; Mode attribute for boolean operation register constraints for operand1
521 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
529 (V1TI "wa,v,r,0,r")])
531 ;; Mode attribute for boolean operation register constraints for operand2
532 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
540 (V1TI "wa,v,r,r,0")])
542 ;; Mode attribute for boolean operation register constraints for operand1
543 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
544 ;; is used for operand1 or operand2
545 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
553 (V1TI "wa,v,r,0,0")])
555 ;; Mode attribute for the clobber of CC0 for AND expansion.
556 ;; For the 128-bit types, we never do AND immediate, but we need to
557 ;; get the correct number of X's for the number of operands.
558 (define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
568 ;; Start with fixed-point load and store insns. Here we put only the more
569 ;; complex forms. Basic data transfer is done later.
571 (define_expand "zero_extend<mode>di2"
572 [(set (match_operand:DI 0 "gpc_reg_operand" "")
573 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
577 (define_insn "*zero_extend<mode>di2_internal1"
578 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
579 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
580 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
583 rldicl %0,%1,0,<dbits>"
584 [(set_attr "type" "load,shift")])
586 (define_insn "*zero_extend<mode>di2_internal2"
587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
588 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
590 (clobber (match_scratch:DI 2 "=r,r"))]
593 rldicl. %2,%1,0,<dbits>
595 [(set_attr "type" "shift")
596 (set_attr "dot" "yes")
597 (set_attr "length" "4,8")])
600 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
601 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
603 (clobber (match_scratch:DI 2 ""))]
604 "TARGET_POWERPC64 && reload_completed"
606 (zero_extend:DI (match_dup 1)))
608 (compare:CC (match_dup 2)
612 (define_insn "*zero_extend<mode>di2_internal3"
613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
614 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
617 (zero_extend:DI (match_dup 1)))]
620 rldicl. %0,%1,0,<dbits>
622 [(set_attr "type" "shift")
623 (set_attr "dot" "yes")
624 (set_attr "length" "4,8")])
627 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
628 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
630 (set (match_operand:DI 0 "gpc_reg_operand" "")
631 (zero_extend:DI (match_dup 1)))]
632 "TARGET_POWERPC64 && reload_completed"
634 (zero_extend:DI (match_dup 1)))
636 (compare:CC (match_dup 0)
640 (define_insn "*zero_extendsidi2_lfiwzx"
641 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
642 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
643 "TARGET_POWERPC64 && TARGET_LFIWZX"
650 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
652 (define_insn "extendqidi2"
653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
654 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
657 [(set_attr "type" "exts")])
660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
661 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
663 (clobber (match_scratch:DI 2 "=r,r"))]
668 [(set_attr "type" "compare")
669 (set_attr "length" "4,8")])
672 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
673 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
675 (clobber (match_scratch:DI 2 ""))]
676 "TARGET_POWERPC64 && reload_completed"
678 (sign_extend:DI (match_dup 1)))
680 (compare:CC (match_dup 2)
685 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
686 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
688 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
689 (sign_extend:DI (match_dup 1)))]
694 [(set_attr "type" "compare")
695 (set_attr "length" "4,8")])
698 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
699 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
701 (set (match_operand:DI 0 "gpc_reg_operand" "")
702 (sign_extend:DI (match_dup 1)))]
703 "TARGET_POWERPC64 && reload_completed"
705 (sign_extend:DI (match_dup 1)))
707 (compare:CC (match_dup 0)
711 (define_expand "extendhidi2"
712 [(set (match_operand:DI 0 "gpc_reg_operand" "")
713 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
718 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
719 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
720 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
724 [(set_attr "type" "load,exts")
725 (set_attr "sign_extend" "yes")])
728 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
729 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
730 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
732 [(set_attr "type" "exts")])
735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
736 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
738 (clobber (match_scratch:DI 2 "=r,r"))]
743 [(set_attr "type" "compare")
744 (set_attr "length" "4,8")])
747 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
748 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
750 (clobber (match_scratch:DI 2 ""))]
751 "TARGET_POWERPC64 && reload_completed"
753 (sign_extend:DI (match_dup 1)))
755 (compare:CC (match_dup 2)
760 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
761 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
763 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
764 (sign_extend:DI (match_dup 1)))]
769 [(set_attr "type" "compare")
770 (set_attr "length" "4,8")])
773 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
774 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
776 (set (match_operand:DI 0 "gpc_reg_operand" "")
777 (sign_extend:DI (match_dup 1)))]
778 "TARGET_POWERPC64 && reload_completed"
780 (sign_extend:DI (match_dup 1)))
782 (compare:CC (match_dup 0)
786 (define_expand "extendsidi2"
787 [(set (match_operand:DI 0 "gpc_reg_operand" "")
788 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
792 (define_insn "*extendsidi2_lfiwax"
793 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
794 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
795 "TARGET_POWERPC64 && TARGET_LFIWAX"
802 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
803 (set_attr "sign_extend" "yes")])
805 (define_insn "*extendsidi2_nocell"
806 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
807 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r")))]
808 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
812 [(set_attr "type" "load,exts")
813 (set_attr "sign_extend" "yes")])
815 (define_insn "*extendsidi2_nocell"
816 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
817 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
818 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
820 [(set_attr "type" "exts")])
823 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
824 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
826 (clobber (match_scratch:DI 2 "=r,r"))]
831 [(set_attr "type" "compare")
832 (set_attr "length" "4,8")])
835 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
836 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
838 (clobber (match_scratch:DI 2 ""))]
839 "TARGET_POWERPC64 && reload_completed"
841 (sign_extend:DI (match_dup 1)))
843 (compare:CC (match_dup 2)
848 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
849 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
851 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
852 (sign_extend:DI (match_dup 1)))]
857 [(set_attr "type" "compare")
858 (set_attr "length" "4,8")])
861 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
862 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
864 (set (match_operand:DI 0 "gpc_reg_operand" "")
865 (sign_extend:DI (match_dup 1)))]
866 "TARGET_POWERPC64 && reload_completed"
868 (sign_extend:DI (match_dup 1)))
870 (compare:CC (match_dup 0)
874 (define_expand "zero_extendqisi2"
875 [(set (match_operand:SI 0 "gpc_reg_operand" "")
876 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
882 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
887 [(set_attr "type" "load,shift")])
890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
891 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
893 (clobber (match_scratch:SI 2 "=r,r"))]
898 [(set_attr "type" "logical,compare")
899 (set_attr "dot" "yes")
900 (set_attr "length" "4,8")])
903 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
904 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
906 (clobber (match_scratch:SI 2 ""))]
909 (zero_extend:SI (match_dup 1)))
911 (compare:CC (match_dup 2)
916 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
917 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
920 (zero_extend:SI (match_dup 1)))]
925 [(set_attr "type" "logical,compare")
926 (set_attr "dot" "yes")
927 (set_attr "length" "4,8")])
930 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
931 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
933 (set (match_operand:SI 0 "gpc_reg_operand" "")
934 (zero_extend:SI (match_dup 1)))]
937 (zero_extend:SI (match_dup 1)))
939 (compare:CC (match_dup 0)
943 (define_insn "extendqisi2"
944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
945 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
948 [(set_attr "type" "exts")])
951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
952 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
954 (clobber (match_scratch:SI 2 "=r,r"))]
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
963 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
964 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
966 (clobber (match_scratch:SI 2 ""))]
969 (sign_extend:SI (match_dup 1)))
971 (compare:CC (match_dup 2)
976 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
977 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
979 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
980 (sign_extend:SI (match_dup 1)))]
985 [(set_attr "type" "compare")
986 (set_attr "length" "4,8")])
989 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
990 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
992 (set (match_operand:SI 0 "gpc_reg_operand" "")
993 (sign_extend:SI (match_dup 1)))]
996 (sign_extend:SI (match_dup 1)))
998 (compare:CC (match_dup 0)
1003 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1004 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1008 rlwinm %0,%1,0,0xff"
1009 [(set_attr "type" "load,shift")])
1012 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1013 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1015 (clobber (match_scratch:HI 2 "=r,r"))]
1020 [(set_attr "type" "logical,compare")
1021 (set_attr "dot" "yes")
1022 (set_attr "length" "4,8")])
1025 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1026 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1028 (clobber (match_scratch:HI 2 ""))]
1031 (zero_extend:HI (match_dup 1)))
1033 (compare:CC (match_dup 2)
1038 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1039 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1041 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1042 (zero_extend:HI (match_dup 1)))]
1047 [(set_attr "type" "logical,compare")
1048 (set_attr "dot" "yes")
1049 (set_attr "length" "4,8")])
1052 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1053 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1055 (set (match_operand:HI 0 "gpc_reg_operand" "")
1056 (zero_extend:HI (match_dup 1)))]
1059 (zero_extend:HI (match_dup 1)))
1061 (compare:CC (match_dup 0)
1065 (define_insn "extendqihi2"
1066 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1067 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1070 [(set_attr "type" "exts")])
1073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1074 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1076 (clobber (match_scratch:HI 2 "=r,r"))]
1081 [(set_attr "type" "compare")
1082 (set_attr "length" "4,8")])
1085 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1086 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1088 (clobber (match_scratch:HI 2 ""))]
1091 (sign_extend:HI (match_dup 1)))
1093 (compare:CC (match_dup 2)
1098 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1099 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1101 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1102 (sign_extend:HI (match_dup 1)))]
1107 [(set_attr "type" "compare")
1108 (set_attr "length" "4,8")])
1111 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1112 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1114 (set (match_operand:HI 0 "gpc_reg_operand" "")
1115 (sign_extend:HI (match_dup 1)))]
1118 (sign_extend:HI (match_dup 1)))
1120 (compare:CC (match_dup 0)
1124 (define_expand "zero_extendhisi2"
1125 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1126 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1132 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1136 rlwinm %0,%1,0,0xffff"
1137 [(set_attr "type" "load,shift")])
1140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1141 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1143 (clobber (match_scratch:SI 2 "=r,r"))]
1148 [(set_attr "type" "logical,compare")
1149 (set_attr "dot" "yes")
1150 (set_attr "length" "4,8")])
1153 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1154 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1156 (clobber (match_scratch:SI 2 ""))]
1159 (zero_extend:SI (match_dup 1)))
1161 (compare:CC (match_dup 2)
1166 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1167 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1169 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1170 (zero_extend:SI (match_dup 1)))]
1175 [(set_attr "type" "logical,compare")
1176 (set_attr "dot" "yes")
1177 (set_attr "length" "4,8")])
1180 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1181 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1183 (set (match_operand:SI 0 "gpc_reg_operand" "")
1184 (zero_extend:SI (match_dup 1)))]
1187 (zero_extend:SI (match_dup 1)))
1189 (compare:CC (match_dup 0)
1193 (define_expand "extendhisi2"
1194 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1195 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1201 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1202 "rs6000_gen_cell_microcode"
1206 [(set_attr "type" "load,exts")
1207 (set_attr "sign_extend" "yes")])
1210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1211 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1212 "!rs6000_gen_cell_microcode"
1214 [(set_attr "type" "exts")])
1217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1218 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1220 (clobber (match_scratch:SI 2 "=r,r"))]
1225 [(set_attr "type" "compare")
1226 (set_attr "length" "4,8")])
1229 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1230 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1232 (clobber (match_scratch:SI 2 ""))]
1235 (sign_extend:SI (match_dup 1)))
1237 (compare:CC (match_dup 2)
1242 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1243 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1245 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1246 (sign_extend:SI (match_dup 1)))]
1251 [(set_attr "type" "compare")
1252 (set_attr "length" "4,8")])
1255 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1256 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1258 (set (match_operand:SI 0 "gpc_reg_operand" "")
1259 (sign_extend:SI (match_dup 1)))]
1262 (sign_extend:SI (match_dup 1)))
1264 (compare:CC (match_dup 0)
1268 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1270 (define_insn "*macchwc"
1271 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1272 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1273 (match_operand:SI 2 "gpc_reg_operand" "r")
1276 (match_operand:HI 1 "gpc_reg_operand" "r")))
1277 (match_operand:SI 4 "gpc_reg_operand" "0"))
1279 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (plus:SI (mult:SI (ashiftrt:SI
1288 [(set_attr "type" "halfmul")])
1290 (define_insn "*macchw"
1291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1292 (plus:SI (mult:SI (ashiftrt:SI
1293 (match_operand:SI 2 "gpc_reg_operand" "r")
1296 (match_operand:HI 1 "gpc_reg_operand" "r")))
1297 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1300 [(set_attr "type" "halfmul")])
1302 (define_insn "*macchwuc"
1303 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1304 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1305 (match_operand:SI 2 "gpc_reg_operand" "r")
1308 (match_operand:HI 1 "gpc_reg_operand" "r")))
1309 (match_operand:SI 4 "gpc_reg_operand" "0"))
1311 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1312 (plus:SI (mult:SI (lshiftrt:SI
1320 [(set_attr "type" "halfmul")])
1322 (define_insn "*macchwu"
1323 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1324 (plus:SI (mult:SI (lshiftrt:SI
1325 (match_operand:SI 2 "gpc_reg_operand" "r")
1328 (match_operand:HI 1 "gpc_reg_operand" "r")))
1329 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1332 [(set_attr "type" "halfmul")])
1334 (define_insn "*machhwc"
1335 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1336 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1337 (match_operand:SI 1 "gpc_reg_operand" "%r")
1340 (match_operand:SI 2 "gpc_reg_operand" "r")
1342 (match_operand:SI 4 "gpc_reg_operand" "0"))
1344 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1345 (plus:SI (mult:SI (ashiftrt:SI
1354 [(set_attr "type" "halfmul")])
1356 (define_insn "*machhw"
1357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1358 (plus:SI (mult:SI (ashiftrt:SI
1359 (match_operand:SI 1 "gpc_reg_operand" "%r")
1362 (match_operand:SI 2 "gpc_reg_operand" "r")
1364 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1367 [(set_attr "type" "halfmul")])
1369 (define_insn "*machhwuc"
1370 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1371 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1372 (match_operand:SI 1 "gpc_reg_operand" "%r")
1375 (match_operand:SI 2 "gpc_reg_operand" "r")
1377 (match_operand:SI 4 "gpc_reg_operand" "0"))
1379 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1380 (plus:SI (mult:SI (lshiftrt:SI
1389 [(set_attr "type" "halfmul")])
1391 (define_insn "*machhwu"
1392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1393 (plus:SI (mult:SI (lshiftrt:SI
1394 (match_operand:SI 1 "gpc_reg_operand" "%r")
1397 (match_operand:SI 2 "gpc_reg_operand" "r")
1399 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1402 [(set_attr "type" "halfmul")])
1404 (define_insn "*maclhwc"
1405 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1406 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1407 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1409 (match_operand:HI 2 "gpc_reg_operand" "r")))
1410 (match_operand:SI 4 "gpc_reg_operand" "0"))
1412 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1413 (plus:SI (mult:SI (sign_extend:SI
1420 [(set_attr "type" "halfmul")])
1422 (define_insn "*maclhw"
1423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1424 (plus:SI (mult:SI (sign_extend:SI
1425 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1427 (match_operand:HI 2 "gpc_reg_operand" "r")))
1428 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1431 [(set_attr "type" "halfmul")])
1433 (define_insn "*maclhwuc"
1434 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1435 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1436 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1438 (match_operand:HI 2 "gpc_reg_operand" "r")))
1439 (match_operand:SI 4 "gpc_reg_operand" "0"))
1441 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1442 (plus:SI (mult:SI (zero_extend:SI
1449 [(set_attr "type" "halfmul")])
1451 (define_insn "*maclhwu"
1452 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1453 (plus:SI (mult:SI (zero_extend:SI
1454 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1456 (match_operand:HI 2 "gpc_reg_operand" "r")))
1457 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1460 [(set_attr "type" "halfmul")])
1462 (define_insn "*nmacchwc"
1463 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1464 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1465 (mult:SI (ashiftrt:SI
1466 (match_operand:SI 2 "gpc_reg_operand" "r")
1469 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1471 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1472 (minus:SI (match_dup 4)
1473 (mult:SI (ashiftrt:SI
1480 [(set_attr "type" "halfmul")])
1482 (define_insn "*nmacchw"
1483 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1484 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1485 (mult:SI (ashiftrt:SI
1486 (match_operand:SI 2 "gpc_reg_operand" "r")
1489 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1492 [(set_attr "type" "halfmul")])
1494 (define_insn "*nmachhwc"
1495 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1496 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1497 (mult:SI (ashiftrt:SI
1498 (match_operand:SI 1 "gpc_reg_operand" "%r")
1501 (match_operand:SI 2 "gpc_reg_operand" "r")
1504 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1505 (minus:SI (match_dup 4)
1506 (mult:SI (ashiftrt:SI
1514 [(set_attr "type" "halfmul")])
1516 (define_insn "*nmachhw"
1517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1518 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1519 (mult:SI (ashiftrt:SI
1520 (match_operand:SI 1 "gpc_reg_operand" "%r")
1523 (match_operand:SI 2 "gpc_reg_operand" "r")
1527 [(set_attr "type" "halfmul")])
1529 (define_insn "*nmaclhwc"
1530 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1531 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1532 (mult:SI (sign_extend:SI
1533 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1535 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1537 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1538 (minus:SI (match_dup 4)
1539 (mult:SI (sign_extend:SI
1545 [(set_attr "type" "halfmul")])
1547 (define_insn "*nmaclhw"
1548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1549 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1550 (mult:SI (sign_extend:SI
1551 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1553 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1556 [(set_attr "type" "halfmul")])
1558 (define_insn "*mulchwc"
1559 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1560 (compare:CC (mult:SI (ashiftrt:SI
1561 (match_operand:SI 2 "gpc_reg_operand" "r")
1564 (match_operand:HI 1 "gpc_reg_operand" "r")))
1566 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1567 (mult:SI (ashiftrt:SI
1574 [(set_attr "type" "halfmul")])
1576 (define_insn "*mulchw"
1577 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1578 (mult:SI (ashiftrt:SI
1579 (match_operand:SI 2 "gpc_reg_operand" "r")
1582 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1585 [(set_attr "type" "halfmul")])
1587 (define_insn "*mulchwuc"
1588 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1589 (compare:CC (mult:SI (lshiftrt:SI
1590 (match_operand:SI 2 "gpc_reg_operand" "r")
1593 (match_operand:HI 1 "gpc_reg_operand" "r")))
1595 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1596 (mult:SI (lshiftrt:SI
1603 [(set_attr "type" "halfmul")])
1605 (define_insn "*mulchwu"
1606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1607 (mult:SI (lshiftrt:SI
1608 (match_operand:SI 2 "gpc_reg_operand" "r")
1611 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1614 [(set_attr "type" "halfmul")])
1616 (define_insn "*mulhhwc"
1617 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1618 (compare:CC (mult:SI (ashiftrt:SI
1619 (match_operand:SI 1 "gpc_reg_operand" "%r")
1622 (match_operand:SI 2 "gpc_reg_operand" "r")
1625 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1626 (mult:SI (ashiftrt:SI
1634 [(set_attr "type" "halfmul")])
1636 (define_insn "*mulhhw"
1637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1638 (mult:SI (ashiftrt:SI
1639 (match_operand:SI 1 "gpc_reg_operand" "%r")
1642 (match_operand:SI 2 "gpc_reg_operand" "r")
1646 [(set_attr "type" "halfmul")])
1648 (define_insn "*mulhhwuc"
1649 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1650 (compare:CC (mult:SI (lshiftrt:SI
1651 (match_operand:SI 1 "gpc_reg_operand" "%r")
1654 (match_operand:SI 2 "gpc_reg_operand" "r")
1657 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1658 (mult:SI (lshiftrt:SI
1666 [(set_attr "type" "halfmul")])
1668 (define_insn "*mulhhwu"
1669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1670 (mult:SI (lshiftrt:SI
1671 (match_operand:SI 1 "gpc_reg_operand" "%r")
1674 (match_operand:SI 2 "gpc_reg_operand" "r")
1678 [(set_attr "type" "halfmul")])
1680 (define_insn "*mullhwc"
1681 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1682 (compare:CC (mult:SI (sign_extend:SI
1683 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1685 (match_operand:HI 2 "gpc_reg_operand" "r")))
1687 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1688 (mult:SI (sign_extend:SI
1694 [(set_attr "type" "halfmul")])
1696 (define_insn "*mullhw"
1697 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1698 (mult:SI (sign_extend:SI
1699 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1701 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1704 [(set_attr "type" "halfmul")])
1706 (define_insn "*mullhwuc"
1707 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1708 (compare:CC (mult:SI (zero_extend:SI
1709 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1711 (match_operand:HI 2 "gpc_reg_operand" "r")))
1713 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1714 (mult:SI (zero_extend:SI
1720 [(set_attr "type" "halfmul")])
1722 (define_insn "*mullhwu"
1723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1724 (mult:SI (zero_extend:SI
1725 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1727 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1730 [(set_attr "type" "halfmul")])
1732 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1733 (define_insn "dlmzb"
1734 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1735 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1736 (match_operand:SI 2 "gpc_reg_operand" "r")]
1738 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1739 (unspec:SI [(match_dup 1)
1745 (define_expand "strlensi"
1746 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1747 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1748 (match_operand:QI 2 "const_int_operand" "")
1749 (match_operand 3 "const_int_operand" "")]
1750 UNSPEC_DLMZB_STRLEN))
1751 (clobber (match_scratch:CC 4 "=x"))]
1752 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1754 rtx result = operands[0];
1755 rtx src = operands[1];
1756 rtx search_char = operands[2];
1757 rtx align = operands[3];
1758 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1759 rtx loop_label, end_label, mem, cr0, cond;
1760 if (search_char != const0_rtx
1761 || GET_CODE (align) != CONST_INT
1762 || INTVAL (align) < 8)
1764 word1 = gen_reg_rtx (SImode);
1765 word2 = gen_reg_rtx (SImode);
1766 scratch_dlmzb = gen_reg_rtx (SImode);
1767 scratch_string = gen_reg_rtx (Pmode);
1768 loop_label = gen_label_rtx ();
1769 end_label = gen_label_rtx ();
1770 addr = force_reg (Pmode, XEXP (src, 0));
1771 emit_move_insn (scratch_string, addr);
1772 emit_label (loop_label);
1773 mem = change_address (src, SImode, scratch_string);
1774 emit_move_insn (word1, mem);
1775 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1776 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1777 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1778 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1779 emit_jump_insn (gen_rtx_SET (VOIDmode,
1781 gen_rtx_IF_THEN_ELSE (VOIDmode,
1787 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1788 emit_jump_insn (gen_rtx_SET (VOIDmode,
1790 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1792 emit_label (end_label);
1793 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1794 emit_insn (gen_subsi3 (result, scratch_string, addr));
1795 emit_insn (gen_subsi3 (result, result, const1_rtx));
1799 ;; Fixed-point arithmetic insns.
1801 (define_expand "add<mode>3"
1802 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1803 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1804 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1807 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1809 if (non_short_cint_operand (operands[2], DImode))
1812 else if (GET_CODE (operands[2]) == CONST_INT
1813 && ! add_operand (operands[2], <MODE>mode))
1815 rtx tmp = ((!can_create_pseudo_p ()
1816 || rtx_equal_p (operands[0], operands[1]))
1817 ? operands[0] : gen_reg_rtx (<MODE>mode));
1819 HOST_WIDE_INT val = INTVAL (operands[2]);
1820 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1821 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1823 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1826 /* The ordering here is important for the prolog expander.
1827 When space is allocated from the stack, adding 'low' first may
1828 produce a temporary deallocation (which would be bad). */
1829 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1830 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1835 ;; Discourage ai/addic because of carry but provide it in an alternative
1836 ;; allowing register zero as source.
1837 (define_insn "*add<mode>3_internal1"
1838 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1839 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1840 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1841 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1847 [(set_attr "type" "add")])
1849 (define_insn "addsi3_high"
1850 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1851 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1852 (high:SI (match_operand 2 "" ""))))]
1853 "TARGET_MACHO && !TARGET_64BIT"
1854 "addis %0,%1,ha16(%2)"
1855 [(set_attr "type" "add")])
1857 (define_insn "*add<mode>3_internal2"
1858 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1859 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1860 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1862 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1869 [(set_attr "type" "add,compare,compare,compare")
1870 (set_attr "dot" "yes")
1871 (set_attr "length" "4,4,8,8")])
1874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1875 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1876 (match_operand:GPR 2 "reg_or_short_operand" ""))
1878 (clobber (match_scratch:GPR 3 ""))]
1881 (plus:GPR (match_dup 1)
1884 (compare:CC (match_dup 3)
1888 (define_insn "*add<mode>3_internal3"
1889 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1890 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1891 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1893 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1894 (plus:P (match_dup 1)
1902 [(set_attr "type" "add,compare,compare,compare")
1903 (set_attr "dot" "yes")
1904 (set_attr "length" "4,4,8,8")])
1907 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1908 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1909 (match_operand:P 2 "reg_or_short_operand" ""))
1911 (set (match_operand:P 0 "gpc_reg_operand" "")
1912 (plus:P (match_dup 1) (match_dup 2)))]
1915 (plus:P (match_dup 1)
1918 (compare:CC (match_dup 0)
1922 ;; Split an add that we can't do in one insn into two insns, each of which
1923 ;; does one 16-bit part. This is used by combine. Note that the low-order
1924 ;; add should be last in case the result gets used in an address.
1927 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1928 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1929 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1931 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1932 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1934 HOST_WIDE_INT val = INTVAL (operands[2]);
1935 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1936 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1938 operands[4] = GEN_INT (low);
1939 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1940 operands[3] = GEN_INT (rest);
1941 else if (can_create_pseudo_p ())
1943 operands[3] = gen_reg_rtx (DImode);
1944 emit_move_insn (operands[3], operands[2]);
1945 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1952 (define_expand "one_cmpl<mode>2"
1953 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1954 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1957 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1959 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
1964 (define_insn "*one_cmpl<mode>2"
1965 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1966 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1972 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1974 (clobber (match_scratch:P 2 "=r,r"))]
1979 [(set_attr "type" "logical,compare")
1980 (set_attr "dot" "yes")
1981 (set_attr "length" "4,8")])
1984 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1985 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1987 (clobber (match_scratch:P 2 ""))]
1990 (not:P (match_dup 1)))
1992 (compare:CC (match_dup 2)
1997 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1998 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2000 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2001 (not:P (match_dup 1)))]
2006 [(set_attr "type" "logical,compare")
2007 (set_attr "dot" "yes")
2008 (set_attr "length" "4,8")])
2011 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
2012 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
2014 (set (match_operand:P 0 "gpc_reg_operand" "")
2015 (not:P (match_dup 1)))]
2018 (not:P (match_dup 1)))
2020 (compare:CC (match_dup 0)
2025 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2026 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
2027 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
2032 [(set_attr "type" "add")])
2035 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2036 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2037 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2039 (clobber (match_scratch:P 3 "=r,r"))]
2044 [(set_attr "type" "add")
2045 (set_attr "dot" "yes")
2046 (set_attr "length" "4,8")])
2049 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2050 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2051 (match_operand:P 2 "gpc_reg_operand" ""))
2053 (clobber (match_scratch:P 3 ""))]
2056 (minus:P (match_dup 1)
2059 (compare:CC (match_dup 3)
2064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2065 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2066 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2068 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2069 (minus:P (match_dup 1)
2075 [(set_attr "type" "add")
2076 (set_attr "dot" "yes")
2077 (set_attr "length" "4,8")])
2080 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2081 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2082 (match_operand:P 2 "gpc_reg_operand" ""))
2084 (set (match_operand:P 0 "gpc_reg_operand" "")
2085 (minus:P (match_dup 1)
2089 (minus:P (match_dup 1)
2092 (compare:CC (match_dup 0)
2096 (define_expand "sub<mode>3"
2097 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2098 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
2099 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
2103 if (GET_CODE (operands[2]) == CONST_INT)
2105 emit_insn (gen_add<mode>3 (operands[0], operands[1],
2106 negate_rtx (<MODE>mode, operands[2])));
2111 (define_expand "neg<mode>2"
2112 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2113 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2117 (define_insn "*neg<mode>2_internal"
2118 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2119 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2122 [(set_attr "type" "add")])
2125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2126 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2128 (clobber (match_scratch:P 2 "=r,r"))]
2133 [(set_attr "type" "add")
2134 (set_attr "dot" "yes")
2135 (set_attr "length" "4,8")])
2138 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2139 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2141 (clobber (match_scratch:P 2 ""))]
2144 (neg:P (match_dup 1)))
2146 (compare:CC (match_dup 2)
2151 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2152 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2154 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2155 (neg:P (match_dup 1)))]
2160 [(set_attr "type" "add")
2161 (set_attr "dot" "yes")
2162 (set_attr "length" "4,8")])
2165 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2166 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2168 (set (match_operand:P 0 "gpc_reg_operand" "")
2169 (neg:P (match_dup 1)))]
2172 (neg:P (match_dup 1)))
2174 (compare:CC (match_dup 0)
2178 (define_insn "clz<mode>2"
2179 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2180 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2183 [(set_attr "type" "cntlz")])
2185 (define_expand "ctz<mode>2"
2187 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2188 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2190 (clobber (scratch:CC))])
2191 (set (match_dup 4) (clz:GPR (match_dup 3)))
2192 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2193 (minus:GPR (match_dup 5) (match_dup 4)))]
2196 operands[2] = gen_reg_rtx (<MODE>mode);
2197 operands[3] = gen_reg_rtx (<MODE>mode);
2198 operands[4] = gen_reg_rtx (<MODE>mode);
2199 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2202 (define_expand "ffs<mode>2"
2204 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2205 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2207 (clobber (scratch:CC))])
2208 (set (match_dup 4) (clz:GPR (match_dup 3)))
2209 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2210 (minus:GPR (match_dup 5) (match_dup 4)))]
2213 operands[2] = gen_reg_rtx (<MODE>mode);
2214 operands[3] = gen_reg_rtx (<MODE>mode);
2215 operands[4] = gen_reg_rtx (<MODE>mode);
2216 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2219 (define_insn "popcntb<mode>2"
2220 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2221 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2225 [(set_attr "length" "4")
2226 (set_attr "type" "popcnt")])
2228 (define_insn "popcntd<mode>2"
2229 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2230 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2233 [(set_attr "length" "4")
2234 (set_attr "type" "popcnt")])
2236 (define_expand "popcount<mode>2"
2237 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2238 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2239 "TARGET_POPCNTB || TARGET_POPCNTD"
2241 rs6000_emit_popcount (operands[0], operands[1]);
2245 (define_insn "parity<mode>2_cmpb"
2246 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2247 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2248 "TARGET_CMPB && TARGET_POPCNTB"
2250 [(set_attr "length" "4")
2251 (set_attr "type" "popcnt")])
2253 (define_expand "parity<mode>2"
2254 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2255 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2258 rs6000_emit_parity (operands[0], operands[1]);
2262 ;; Since the hardware zeros the upper part of the register, save generating the
2263 ;; AND immediate if we are converting to unsigned
2264 (define_insn "*bswaphi2_extenddi"
2265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2267 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2270 [(set_attr "length" "4")
2271 (set_attr "type" "load")])
2273 (define_insn "*bswaphi2_extendsi"
2274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2276 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2279 [(set_attr "length" "4")
2280 (set_attr "type" "load")])
2282 (define_expand "bswaphi2"
2283 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2285 (match_operand:HI 1 "reg_or_mem_operand" "")))
2286 (clobber (match_scratch:SI 2 ""))])]
2289 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2290 operands[1] = force_reg (HImode, operands[1]);
2293 (define_insn "bswaphi2_internal"
2294 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2296 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2297 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2303 [(set_attr "length" "4,4,12")
2304 (set_attr "type" "load,store,*")])
2306 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2307 ;; correct for -mlittle as well as -mbig.
2309 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2310 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2311 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2314 (zero_extract:SI (match_dup 4)
2318 (and:SI (ashift:SI (match_dup 4)
2320 (const_int 65280))) ;; 0xff00
2322 (ior:SI (match_dup 3)
2326 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2327 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2330 (define_insn "*bswapsi2_extenddi"
2331 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2333 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2336 [(set_attr "length" "4")
2337 (set_attr "type" "load")])
2339 (define_expand "bswapsi2"
2340 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2342 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2345 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2346 operands[1] = force_reg (SImode, operands[1]);
2349 (define_insn "*bswapsi2_internal"
2350 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2352 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2358 [(set_attr "length" "4,4,12")
2359 (set_attr "type" "load,store,*")])
2361 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2362 ;; zero_extract insns do not change for -mlittle.
2364 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2365 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2368 (rotate:SI (match_dup 1) (const_int 8)))
2369 (set (zero_extract:SI (match_dup 0)
2373 (set (zero_extract:SI (match_dup 0)
2376 (rotate:SI (match_dup 1)
2380 (define_expand "bswapdi2"
2381 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2383 (match_operand:DI 1 "reg_or_mem_operand" "")))
2384 (clobber (match_scratch:DI 2 ""))
2385 (clobber (match_scratch:DI 3 ""))
2386 (clobber (match_scratch:DI 4 ""))])]
2389 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2390 operands[1] = force_reg (DImode, operands[1]);
2392 if (!TARGET_POWERPC64)
2394 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2395 that uses 64-bit registers needs the same scratch registers as 64-bit
2397 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2402 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2403 (define_insn "*bswapdi2_ldbrx"
2404 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2405 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2406 (clobber (match_scratch:DI 2 "=X,X,&r"))
2407 (clobber (match_scratch:DI 3 "=X,X,&r"))
2408 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2409 "TARGET_POWERPC64 && TARGET_LDBRX
2410 && (REG_P (operands[0]) || REG_P (operands[1]))"
2415 [(set_attr "length" "4,4,36")
2416 (set_attr "type" "load,store,*")])
2418 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2419 (define_insn "*bswapdi2_64bit"
2420 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2421 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2422 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2423 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2424 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2425 "TARGET_POWERPC64 && !TARGET_LDBRX
2426 && (REG_P (operands[0]) || REG_P (operands[1]))
2427 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2428 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2430 [(set_attr "length" "16,12,36")])
2433 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2434 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2435 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2436 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2437 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2438 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2442 rtx dest = operands[0];
2443 rtx src = operands[1];
2444 rtx op2 = operands[2];
2445 rtx op3 = operands[3];
2446 rtx op4 = operands[4];
2447 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2448 BYTES_BIG_ENDIAN ? 4 : 0);
2449 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2450 BYTES_BIG_ENDIAN ? 4 : 0);
2456 addr1 = XEXP (src, 0);
2457 if (GET_CODE (addr1) == PLUS)
2459 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2460 if (TARGET_AVOID_XFORM)
2462 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2466 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2468 else if (TARGET_AVOID_XFORM)
2470 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2475 emit_move_insn (op2, GEN_INT (4));
2476 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2479 if (BYTES_BIG_ENDIAN)
2481 word_high = change_address (src, SImode, addr1);
2482 word_low = change_address (src, SImode, addr2);
2486 word_high = change_address (src, SImode, addr2);
2487 word_low = change_address (src, SImode, addr1);
2490 emit_insn (gen_bswapsi2 (op3_32, word_low));
2491 emit_insn (gen_bswapsi2 (op4_32, word_high));
2492 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2493 emit_insn (gen_iordi3 (dest, dest, op4));
2498 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2499 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2500 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2501 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2502 (clobber (match_operand:DI 4 "" ""))]
2503 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2507 rtx dest = operands[0];
2508 rtx src = operands[1];
2509 rtx op2 = operands[2];
2510 rtx op3 = operands[3];
2511 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2512 BYTES_BIG_ENDIAN ? 4 : 0);
2513 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2514 BYTES_BIG_ENDIAN ? 4 : 0);
2520 addr1 = XEXP (dest, 0);
2521 if (GET_CODE (addr1) == PLUS)
2523 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2524 if (TARGET_AVOID_XFORM)
2526 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2530 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2532 else if (TARGET_AVOID_XFORM)
2534 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2539 emit_move_insn (op2, GEN_INT (4));
2540 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2543 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2544 if (BYTES_BIG_ENDIAN)
2546 word_high = change_address (dest, SImode, addr1);
2547 word_low = change_address (dest, SImode, addr2);
2551 word_high = change_address (dest, SImode, addr2);
2552 word_low = change_address (dest, SImode, addr1);
2554 emit_insn (gen_bswapsi2 (word_high, src_si));
2555 emit_insn (gen_bswapsi2 (word_low, op3_si));
2560 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2561 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2562 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2563 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2564 (clobber (match_operand:DI 4 "" ""))]
2565 "TARGET_POWERPC64 && reload_completed"
2569 rtx dest = operands[0];
2570 rtx src = operands[1];
2571 rtx op2 = operands[2];
2572 rtx op3 = operands[3];
2573 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2574 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2575 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2576 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2577 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2579 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2580 emit_insn (gen_bswapsi2 (dest_si, src_si));
2581 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2582 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2583 emit_insn (gen_iordi3 (dest, dest, op3));
2587 (define_insn "bswapdi2_32bit"
2588 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2589 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2590 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2591 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2593 [(set_attr "length" "16,12,36")])
2596 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2597 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2598 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2599 "!TARGET_POWERPC64 && reload_completed"
2603 rtx dest = operands[0];
2604 rtx src = operands[1];
2605 rtx op2 = operands[2];
2606 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2607 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2613 addr1 = XEXP (src, 0);
2614 if (GET_CODE (addr1) == PLUS)
2616 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2617 if (TARGET_AVOID_XFORM)
2619 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2623 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2625 else if (TARGET_AVOID_XFORM)
2627 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2632 emit_move_insn (op2, GEN_INT (4));
2633 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2636 word1 = change_address (src, SImode, addr1);
2637 word2 = change_address (src, SImode, addr2);
2639 emit_insn (gen_bswapsi2 (dest2, word1));
2640 emit_insn (gen_bswapsi2 (dest1, word2));
2645 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2646 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2647 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2648 "!TARGET_POWERPC64 && reload_completed"
2652 rtx dest = operands[0];
2653 rtx src = operands[1];
2654 rtx op2 = operands[2];
2655 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2656 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2662 addr1 = XEXP (dest, 0);
2663 if (GET_CODE (addr1) == PLUS)
2665 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2666 if (TARGET_AVOID_XFORM)
2668 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2672 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2674 else if (TARGET_AVOID_XFORM)
2676 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2681 emit_move_insn (op2, GEN_INT (4));
2682 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2685 word1 = change_address (dest, SImode, addr1);
2686 word2 = change_address (dest, SImode, addr2);
2688 emit_insn (gen_bswapsi2 (word2, src1));
2689 emit_insn (gen_bswapsi2 (word1, src2));
2694 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2695 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2696 (clobber (match_operand:SI 2 "" ""))]
2697 "!TARGET_POWERPC64 && reload_completed"
2701 rtx dest = operands[0];
2702 rtx src = operands[1];
2703 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2704 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2705 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2706 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2708 emit_insn (gen_bswapsi2 (dest1, src2));
2709 emit_insn (gen_bswapsi2 (dest2, src1));
2713 (define_insn "mulsi3"
2714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2715 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2716 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2721 [(set_attr "type" "mul")
2723 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2725 (match_operand:SI 2 "short_cint_operand" "")
2726 (const_string "16")]
2727 (const_string "32")))])
2729 (define_insn "*mulsi3_internal1"
2730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2732 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2734 (clobber (match_scratch:SI 3 "=r,r"))]
2739 [(set_attr "type" "mul")
2740 (set_attr "dot" "yes")
2741 (set_attr "length" "4,8")])
2744 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2745 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2746 (match_operand:SI 2 "gpc_reg_operand" ""))
2748 (clobber (match_scratch:SI 3 ""))]
2749 "TARGET_32BIT && reload_completed"
2751 (mult:SI (match_dup 1) (match_dup 2)))
2753 (compare:CC (match_dup 3)
2757 (define_insn "*mulsi3_internal2"
2758 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2759 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2760 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2762 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2763 (mult:SI (match_dup 1) (match_dup 2)))]
2768 [(set_attr "type" "mul")
2769 (set_attr "dot" "yes")
2770 (set_attr "length" "4,8")])
2773 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2774 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2775 (match_operand:SI 2 "gpc_reg_operand" ""))
2777 (set (match_operand:SI 0 "gpc_reg_operand" "")
2778 (mult:SI (match_dup 1) (match_dup 2)))]
2779 "TARGET_32BIT && reload_completed"
2781 (mult:SI (match_dup 1) (match_dup 2)))
2783 (compare:CC (match_dup 0)
2788 (define_insn "udiv<mode>3"
2789 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2790 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2791 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2794 [(set_attr "type" "div")
2795 (set_attr "size" "<bits>")])
2798 ;; For powers of two we can do srai/aze for divide and then adjust for
2799 ;; modulus. If it isn't a power of two, force operands into register and do
2801 (define_expand "div<mode>3"
2802 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2803 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2804 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2807 if (GET_CODE (operands[2]) != CONST_INT
2808 || INTVAL (operands[2]) <= 0
2809 || exact_log2 (INTVAL (operands[2])) < 0)
2810 operands[2] = force_reg (<MODE>mode, operands[2]);
2813 (define_insn "*div<mode>3"
2814 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2815 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2816 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2819 [(set_attr "type" "div")
2820 (set_attr "size" "<bits>")])
2822 (define_expand "mod<mode>3"
2823 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2824 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2825 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2833 if (GET_CODE (operands[2]) != CONST_INT
2834 || INTVAL (operands[2]) <= 0
2835 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2838 temp1 = gen_reg_rtx (<MODE>mode);
2839 temp2 = gen_reg_rtx (<MODE>mode);
2841 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2842 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2843 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2848 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2849 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2850 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2852 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2853 [(set_attr "type" "two")
2854 (set_attr "length" "8")])
2857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2858 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2859 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2861 (clobber (match_scratch:P 3 "=r,r"))]
2864 sra<wd>i %3,%1,%p2\;addze. %3,%3
2866 [(set_attr "type" "compare")
2867 (set_attr "length" "8,12")
2868 (set_attr "cell_micro" "not")])
2871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2872 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2873 (match_operand:GPR 2 "exact_log2_cint_operand"
2876 (clobber (match_scratch:GPR 3 ""))]
2879 (div:<MODE> (match_dup 1) (match_dup 2)))
2881 (compare:CC (match_dup 3)
2886 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2887 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2888 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2890 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2891 (div:P (match_dup 1) (match_dup 2)))]
2894 sra<wd>i %0,%1,%p2\;addze. %0,%0
2896 [(set_attr "type" "compare")
2897 (set_attr "length" "8,12")
2898 (set_attr "cell_micro" "not")])
2901 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2902 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2903 (match_operand:GPR 2 "exact_log2_cint_operand"
2906 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2907 (div:GPR (match_dup 1) (match_dup 2)))]
2910 (div:<MODE> (match_dup 1) (match_dup 2)))
2912 (compare:CC (match_dup 0)
2916 ;; Logical instructions
2917 ;; The logical instructions are mostly combined by using match_operator,
2918 ;; but the plain AND insns are somewhat different because there is no
2919 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2920 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2922 (define_expand "andsi3"
2924 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2925 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2926 (match_operand:SI 2 "and_operand" "")))
2927 (clobber (match_scratch:CC 3 ""))])]
2931 (define_insn "andsi3_mc"
2932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2933 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2934 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2935 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2936 "rs6000_gen_cell_microcode"
2939 rlwinm %0,%1,0,%m2,%M2
2942 [(set_attr "type" "*,shift,logical,logical")
2943 (set_attr "dot" "no,no,yes,yes")])
2945 (define_insn "andsi3_nomc"
2946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2947 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2948 (match_operand:SI 2 "and_operand" "?r,T")))
2949 (clobber (match_scratch:CC 3 "=X,X"))]
2950 "!rs6000_gen_cell_microcode"
2953 rlwinm %0,%1,0,%m2,%M2"
2954 [(set_attr "type" "logical,shift")])
2956 (define_insn "andsi3_internal0_nomc"
2957 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2958 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2959 (match_operand:SI 2 "and_operand" "?r,T")))]
2960 "!rs6000_gen_cell_microcode"
2963 rlwinm %0,%1,0,%m2,%M2"
2964 [(set_attr "type" "logical,shift")])
2967 ;; Note to set cr's other than cr0 we do the and immediate and then
2968 ;; the test again -- this avoids a mfcr which on the higher end
2969 ;; machines causes an execution serialization
2971 (define_insn "*andsi3_internal2_mc"
2972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2973 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2974 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2976 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2977 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2978 "TARGET_32BIT && rs6000_gen_cell_microcode"
2983 rlwinm. %3,%1,0,%m2,%M2
2988 [(set_attr "type" "logical,logical,logical,shift,\
2989 compare,compare,compare,compare")
2990 (set_attr "dot" "yes")
2991 (set_attr "length" "4,4,4,4,8,8,8,8")])
2993 (define_insn "*andsi3_internal3_mc"
2994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2995 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2996 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2998 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2999 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3000 "TARGET_64BIT && rs6000_gen_cell_microcode"
3005 rlwinm. %3,%1,0,%m2,%M2
3010 [(set_attr "type" "compare,logical,logical,shift,compare,\
3011 compare,compare,compare")
3012 (set_attr "dot" "yes")
3013 (set_attr "length" "8,4,4,4,8,8,8,8")])
3016 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3017 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3018 (match_operand:GPR 2 "and_operand" ""))
3020 (clobber (match_scratch:GPR 3 ""))
3021 (clobber (match_scratch:CC 4 ""))]
3023 [(parallel [(set (match_dup 3)
3024 (and:<MODE> (match_dup 1)
3026 (clobber (match_dup 4))])
3028 (compare:CC (match_dup 3)
3032 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3033 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3036 [(set (match_operand:CC 0 "cc_reg_operand" "")
3037 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3038 (match_operand:SI 2 "gpc_reg_operand" ""))
3040 (clobber (match_scratch:SI 3 ""))
3041 (clobber (match_scratch:CC 4 ""))]
3042 "TARGET_POWERPC64 && reload_completed"
3043 [(parallel [(set (match_dup 3)
3044 (and:SI (match_dup 1)
3046 (clobber (match_dup 4))])
3048 (compare:CC (match_dup 3)
3052 (define_insn "*andsi3_internal4"
3053 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3054 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3055 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3057 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3058 (and:SI (match_dup 1)
3060 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3061 "TARGET_32BIT && rs6000_gen_cell_microcode"
3066 rlwinm. %0,%1,0,%m2,%M2
3071 [(set_attr "type" "logical,logical,logical,shift,\
3072 compare,compare,compare,compare")
3073 (set_attr "dot" "yes")
3074 (set_attr "length" "4,4,4,4,8,8,8,8")])
3076 (define_insn "*andsi3_internal5_mc"
3077 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3078 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3079 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3081 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3082 (and:SI (match_dup 1)
3084 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3085 "TARGET_64BIT && rs6000_gen_cell_microcode"
3090 rlwinm. %0,%1,0,%m2,%M2
3095 [(set_attr "type" "compare,logical,logical,shift,compare,\
3096 compare,compare,compare")
3097 (set_attr "dot" "yes")
3098 (set_attr "length" "8,4,4,4,8,8,8,8")])
3101 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3102 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3103 (match_operand:SI 2 "and_operand" ""))
3105 (set (match_operand:SI 0 "gpc_reg_operand" "")
3106 (and:SI (match_dup 1)
3108 (clobber (match_scratch:CC 4 ""))]
3110 [(parallel [(set (match_dup 0)
3111 (and:SI (match_dup 1)
3113 (clobber (match_dup 4))])
3115 (compare:CC (match_dup 0)
3120 [(set (match_operand:CC 3 "cc_reg_operand" "")
3121 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3122 (match_operand:SI 2 "gpc_reg_operand" ""))
3124 (set (match_operand:SI 0 "gpc_reg_operand" "")
3125 (and:SI (match_dup 1)
3127 (clobber (match_scratch:CC 4 ""))]
3128 "TARGET_POWERPC64 && reload_completed"
3129 [(parallel [(set (match_dup 0)
3130 (and:SI (match_dup 1)
3132 (clobber (match_dup 4))])
3134 (compare:CC (match_dup 0)
3138 ;; Handle the PowerPC64 rlwinm corner case
3140 (define_insn_and_split "*andsi3_internal6"
3141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3142 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3143 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3148 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3151 (rotate:SI (match_dup 0) (match_dup 5)))]
3154 int mb = extract_MB (operands[2]);
3155 int me = extract_ME (operands[2]);
3156 operands[3] = GEN_INT (me + 1);
3157 operands[5] = GEN_INT (32 - (me + 1));
3158 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3160 [(set_attr "length" "8")])
3162 (define_expand "iorsi3"
3163 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3164 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3165 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3169 if (GET_CODE (operands[2]) == CONST_INT
3170 && ! logical_operand (operands[2], SImode))
3172 HOST_WIDE_INT value = INTVAL (operands[2]);
3173 rtx tmp = ((!can_create_pseudo_p ()
3174 || rtx_equal_p (operands[0], operands[1]))
3175 ? operands[0] : gen_reg_rtx (SImode));
3177 emit_insn (gen_iorsi3 (tmp, operands[1],
3178 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3179 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3184 (define_expand "xorsi3"
3185 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3186 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3187 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3191 if (GET_CODE (operands[2]) == CONST_INT
3192 && ! logical_operand (operands[2], SImode))
3194 HOST_WIDE_INT value = INTVAL (operands[2]);
3195 rtx tmp = ((!can_create_pseudo_p ()
3196 || rtx_equal_p (operands[0], operands[1]))
3197 ? operands[0] : gen_reg_rtx (SImode));
3199 emit_insn (gen_xorsi3 (tmp, operands[1],
3200 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3201 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3206 (define_insn "*boolsi3_internal1"
3207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3208 (match_operator:SI 3 "boolean_or_operator"
3209 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3210 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3217 (define_insn "*boolsi3_internal2"
3218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3219 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3220 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3221 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3223 (clobber (match_scratch:SI 3 "=r,r"))]
3228 [(set_attr "type" "logical,compare")
3229 (set_attr "dot" "yes")
3230 (set_attr "length" "4,8")])
3233 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3234 (compare:CC (match_operator:SI 4 "boolean_operator"
3235 [(match_operand:SI 1 "gpc_reg_operand" "")
3236 (match_operand:SI 2 "gpc_reg_operand" "")])
3238 (clobber (match_scratch:SI 3 ""))]
3239 "TARGET_32BIT && reload_completed"
3240 [(set (match_dup 3) (match_dup 4))
3242 (compare:CC (match_dup 3)
3246 (define_insn "*boolsi3_internal3"
3247 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3248 (compare:CC (match_operator:SI 4 "boolean_operator"
3249 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3250 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3252 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3258 [(set_attr "type" "logical,compare")
3259 (set_attr "dot" "yes")
3260 (set_attr "length" "4,8")])
3263 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3264 (compare:CC (match_operator:SI 4 "boolean_operator"
3265 [(match_operand:SI 1 "gpc_reg_operand" "")
3266 (match_operand:SI 2 "gpc_reg_operand" "")])
3268 (set (match_operand:SI 0 "gpc_reg_operand" "")
3270 "TARGET_32BIT && reload_completed"
3271 [(set (match_dup 0) (match_dup 4))
3273 (compare:CC (match_dup 0)
3277 ;; Split a logical operation that we can't do in one insn into two insns,
3278 ;; each of which does one 16-bit part. This is used by combine.
3281 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3282 (match_operator:SI 3 "boolean_or_operator"
3283 [(match_operand:SI 1 "gpc_reg_operand" "")
3284 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3286 [(set (match_dup 0) (match_dup 4))
3287 (set (match_dup 0) (match_dup 5))]
3291 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3292 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3294 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3295 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3299 (define_insn "*boolcsi3_internal1"
3300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3301 (match_operator:SI 3 "boolean_operator"
3302 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3303 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3307 (define_insn "*boolcsi3_internal2"
3308 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3309 (compare:CC (match_operator:SI 4 "boolean_operator"
3310 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3311 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3313 (clobber (match_scratch:SI 3 "=r,r"))]
3318 [(set_attr "type" "compare")
3319 (set_attr "length" "4,8")])
3322 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3323 (compare:CC (match_operator:SI 4 "boolean_operator"
3324 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3325 (match_operand:SI 2 "gpc_reg_operand" "")])
3327 (clobber (match_scratch:SI 3 ""))]
3328 "TARGET_32BIT && reload_completed"
3329 [(set (match_dup 3) (match_dup 4))
3331 (compare:CC (match_dup 3)
3335 (define_insn "*boolcsi3_internal3"
3336 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3337 (compare:CC (match_operator:SI 4 "boolean_operator"
3338 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3339 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3341 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3347 [(set_attr "type" "compare")
3348 (set_attr "length" "4,8")])
3351 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3352 (compare:CC (match_operator:SI 4 "boolean_operator"
3353 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3354 (match_operand:SI 2 "gpc_reg_operand" "")])
3356 (set (match_operand:SI 0 "gpc_reg_operand" "")
3358 "TARGET_32BIT && reload_completed"
3359 [(set (match_dup 0) (match_dup 4))
3361 (compare:CC (match_dup 0)
3365 (define_insn "*boolccsi3_internal1"
3366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3367 (match_operator:SI 3 "boolean_operator"
3368 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3369 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3373 (define_insn "*boolccsi3_internal2"
3374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3375 (compare:CC (match_operator:SI 4 "boolean_operator"
3376 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3377 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3379 (clobber (match_scratch:SI 3 "=r,r"))]
3384 [(set_attr "type" "logical,compare")
3385 (set_attr "dot" "yes")
3386 (set_attr "length" "4,8")])
3389 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3390 (compare:CC (match_operator:SI 4 "boolean_operator"
3391 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3392 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3394 (clobber (match_scratch:SI 3 ""))]
3395 "TARGET_32BIT && reload_completed"
3396 [(set (match_dup 3) (match_dup 4))
3398 (compare:CC (match_dup 3)
3402 (define_insn "*boolccsi3_internal3"
3403 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3404 (compare:CC (match_operator:SI 4 "boolean_operator"
3405 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3406 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3414 [(set_attr "type" "logical,compare")
3415 (set_attr "dot" "yes")
3416 (set_attr "length" "4,8")])
3419 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3420 (compare:CC (match_operator:SI 4 "boolean_operator"
3421 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3422 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3424 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 "TARGET_32BIT && reload_completed"
3427 [(set (match_dup 0) (match_dup 4))
3429 (compare:CC (match_dup 0)
3433 ;; Rotate and shift insns, in all their variants. These support shifts,
3434 ;; field inserts and extracts, and various combinations thereof.
3435 (define_expand "insv"
3436 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3437 (match_operand:SI 1 "const_int_operand" "")
3438 (match_operand:SI 2 "const_int_operand" ""))
3439 (match_operand 3 "gpc_reg_operand" ""))]
3443 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3444 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3445 compiler if the address of the structure is taken later. Likewise, do
3446 not handle invalid E500 subregs. */
3447 if (GET_CODE (operands[0]) == SUBREG
3448 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3449 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3450 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3453 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3454 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3457 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3462 (define_insn "insvsi_internal"
3463 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3464 (match_operand:SI 1 "const_int_operand" "i")
3465 (match_operand:SI 2 "const_int_operand" "i"))
3466 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3470 int start = INTVAL (operands[2]) & 31;
3471 int size = INTVAL (operands[1]) & 31;
3473 operands[4] = GEN_INT (32 - start - size);
3474 operands[1] = GEN_INT (start + size - 1);
3475 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3477 [(set_attr "type" "insert")])
3479 (define_insn "*insvsi_internal1"
3480 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3481 (match_operand:SI 1 "const_int_operand" "i")
3482 (match_operand:SI 2 "const_int_operand" "i"))
3483 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3484 (match_operand:SI 4 "const_int_operand" "i")))]
3485 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3488 int shift = INTVAL (operands[4]) & 31;
3489 int start = INTVAL (operands[2]) & 31;
3490 int size = INTVAL (operands[1]) & 31;
3492 operands[4] = GEN_INT (shift - start - size);
3493 operands[1] = GEN_INT (start + size - 1);
3494 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3496 [(set_attr "type" "insert")])
3498 (define_insn "*insvsi_internal2"
3499 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3500 (match_operand:SI 1 "const_int_operand" "i")
3501 (match_operand:SI 2 "const_int_operand" "i"))
3502 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3503 (match_operand:SI 4 "const_int_operand" "i")))]
3504 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3507 int shift = INTVAL (operands[4]) & 31;
3508 int start = INTVAL (operands[2]) & 31;
3509 int size = INTVAL (operands[1]) & 31;
3511 operands[4] = GEN_INT (32 - shift - start - size);
3512 operands[1] = GEN_INT (start + size - 1);
3513 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3515 [(set_attr "type" "insert")])
3517 (define_insn "*insvsi_internal3"
3518 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3519 (match_operand:SI 1 "const_int_operand" "i")
3520 (match_operand:SI 2 "const_int_operand" "i"))
3521 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3522 (match_operand:SI 4 "const_int_operand" "i")))]
3523 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3526 int shift = INTVAL (operands[4]) & 31;
3527 int start = INTVAL (operands[2]) & 31;
3528 int size = INTVAL (operands[1]) & 31;
3530 operands[4] = GEN_INT (32 - shift - start - size);
3531 operands[1] = GEN_INT (start + size - 1);
3532 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3534 [(set_attr "type" "insert")])
3536 (define_insn "*insvsi_internal4"
3537 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3538 (match_operand:SI 1 "const_int_operand" "i")
3539 (match_operand:SI 2 "const_int_operand" "i"))
3540 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3541 (match_operand:SI 4 "const_int_operand" "i")
3542 (match_operand:SI 5 "const_int_operand" "i")))]
3543 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3546 int extract_start = INTVAL (operands[5]) & 31;
3547 int extract_size = INTVAL (operands[4]) & 31;
3548 int insert_start = INTVAL (operands[2]) & 31;
3549 int insert_size = INTVAL (operands[1]) & 31;
3551 /* Align extract field with insert field */
3552 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3553 operands[1] = GEN_INT (insert_start + insert_size - 1);
3554 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3556 [(set_attr "type" "insert")])
3558 ;; combine patterns for rlwimi
3559 (define_insn "*insvsi_internal5"
3560 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3561 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3562 (match_operand:SI 1 "mask_operand" "i"))
3563 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3564 (match_operand:SI 2 "const_int_operand" "i"))
3565 (match_operand:SI 5 "mask_operand" "i"))))]
3566 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3569 int me = extract_ME(operands[5]);
3570 int mb = extract_MB(operands[5]);
3571 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3572 operands[2] = GEN_INT(mb);
3573 operands[1] = GEN_INT(me);
3574 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3576 [(set_attr "type" "insert")])
3578 (define_insn "*insvsi_internal6"
3579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3580 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3581 (match_operand:SI 2 "const_int_operand" "i"))
3582 (match_operand:SI 5 "mask_operand" "i"))
3583 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3584 (match_operand:SI 1 "mask_operand" "i"))))]
3585 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3588 int me = extract_ME(operands[5]);
3589 int mb = extract_MB(operands[5]);
3590 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3591 operands[2] = GEN_INT(mb);
3592 operands[1] = GEN_INT(me);
3593 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3595 [(set_attr "type" "insert")])
3597 (define_insn "insvdi_internal"
3598 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3599 (match_operand:SI 1 "const_int_operand" "i")
3600 (match_operand:SI 2 "const_int_operand" "i"))
3601 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3605 int start = INTVAL (operands[2]) & 63;
3606 int size = INTVAL (operands[1]) & 63;
3608 operands[1] = GEN_INT (64 - start - size);
3609 return \"rldimi %0,%3,%H1,%H2\";
3611 [(set_attr "type" "insert")
3612 (set_attr "size" "64")])
3614 (define_insn "*insvdi_internal2"
3615 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3616 (match_operand:SI 1 "const_int_operand" "i")
3617 (match_operand:SI 2 "const_int_operand" "i"))
3618 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3619 (match_operand:SI 4 "const_int_operand" "i")))]
3621 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3624 int shift = INTVAL (operands[4]) & 63;
3625 int start = (INTVAL (operands[2]) & 63) - 32;
3626 int size = INTVAL (operands[1]) & 63;
3628 operands[4] = GEN_INT (64 - shift - start - size);
3629 operands[2] = GEN_INT (start);
3630 operands[1] = GEN_INT (start + size - 1);
3631 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3634 (define_insn "*insvdi_internal3"
3635 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3636 (match_operand:SI 1 "const_int_operand" "i")
3637 (match_operand:SI 2 "const_int_operand" "i"))
3638 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3639 (match_operand:SI 4 "const_int_operand" "i")))]
3641 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3644 int shift = INTVAL (operands[4]) & 63;
3645 int start = (INTVAL (operands[2]) & 63) - 32;
3646 int size = INTVAL (operands[1]) & 63;
3648 operands[4] = GEN_INT (64 - shift - start - size);
3649 operands[2] = GEN_INT (start);
3650 operands[1] = GEN_INT (start + size - 1);
3651 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3654 (define_expand "extzv"
3655 [(set (match_operand 0 "gpc_reg_operand" "")
3656 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3657 (match_operand:SI 2 "const_int_operand" "")
3658 (match_operand:SI 3 "const_int_operand" "")))]
3662 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3663 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3664 compiler if the address of the structure is taken later. */
3665 if (GET_CODE (operands[0]) == SUBREG
3666 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3669 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3670 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3673 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3678 (define_insn "extzvsi_internal"
3679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3680 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3681 (match_operand:SI 2 "const_int_operand" "i")
3682 (match_operand:SI 3 "const_int_operand" "i")))]
3686 int start = INTVAL (operands[3]) & 31;
3687 int size = INTVAL (operands[2]) & 31;
3689 if (start + size >= 32)
3690 operands[3] = const0_rtx;
3692 operands[3] = GEN_INT (start + size);
3693 return \"rlwinm %0,%1,%3,%s2,31\";
3695 [(set_attr "type" "shift")])
3697 (define_insn "*extzvsi_internal1"
3698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3699 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3700 (match_operand:SI 2 "const_int_operand" "i,i")
3701 (match_operand:SI 3 "const_int_operand" "i,i"))
3703 (clobber (match_scratch:SI 4 "=r,r"))]
3707 int start = INTVAL (operands[3]) & 31;
3708 int size = INTVAL (operands[2]) & 31;
3710 /* Force split for non-cc0 compare. */
3711 if (which_alternative == 1)
3714 /* If the bit-field being tested fits in the upper or lower half of a
3715 word, it is possible to use andiu. or andil. to test it. This is
3716 useful because the condition register set-use delay is smaller for
3717 andi[ul]. than for rlinm. This doesn't work when the starting bit
3718 position is 0 because the LT and GT bits may be set wrong. */
3720 if ((start > 0 && start + size <= 16) || start >= 16)
3722 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3723 - (1 << (16 - (start & 15) - size))));
3725 return \"andis. %4,%1,%3\";
3727 return \"andi. %4,%1,%3\";
3730 if (start + size >= 32)
3731 operands[3] = const0_rtx;
3733 operands[3] = GEN_INT (start + size);
3734 return \"rlwinm. %4,%1,%3,%s2,31\";
3736 [(set_attr "type" "shift")
3737 (set_attr "dot" "yes")
3738 (set_attr "length" "4,8")])
3741 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3742 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3743 (match_operand:SI 2 "const_int_operand" "")
3744 (match_operand:SI 3 "const_int_operand" ""))
3746 (clobber (match_scratch:SI 4 ""))]
3749 (zero_extract:SI (match_dup 1) (match_dup 2)
3752 (compare:CC (match_dup 4)
3756 (define_insn "*extzvsi_internal2"
3757 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3758 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3759 (match_operand:SI 2 "const_int_operand" "i,i")
3760 (match_operand:SI 3 "const_int_operand" "i,i"))
3762 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3763 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3767 int start = INTVAL (operands[3]) & 31;
3768 int size = INTVAL (operands[2]) & 31;
3770 /* Force split for non-cc0 compare. */
3771 if (which_alternative == 1)
3774 /* Since we are using the output value, we can't ignore any need for
3775 a shift. The bit-field must end at the LSB. */
3776 if (start >= 16 && start + size == 32)
3778 operands[3] = GEN_INT ((1 << size) - 1);
3779 return \"andi. %0,%1,%3\";
3782 if (start + size >= 32)
3783 operands[3] = const0_rtx;
3785 operands[3] = GEN_INT (start + size);
3786 return \"rlwinm. %0,%1,%3,%s2,31\";
3788 [(set_attr "type" "shift")
3789 (set_attr "dot" "yes")
3790 (set_attr "length" "4,8")])
3793 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3794 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3795 (match_operand:SI 2 "const_int_operand" "")
3796 (match_operand:SI 3 "const_int_operand" ""))
3798 (set (match_operand:SI 0 "gpc_reg_operand" "")
3799 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3802 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3804 (compare:CC (match_dup 0)
3808 (define_insn "extzvdi_internal"
3809 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3810 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3811 (match_operand:SI 2 "const_int_operand" "i")
3812 (match_operand:SI 3 "const_int_operand" "i")))]
3816 int start = INTVAL (operands[3]) & 63;
3817 int size = INTVAL (operands[2]) & 63;
3819 if (start + size >= 64)
3820 operands[3] = const0_rtx;
3822 operands[3] = GEN_INT (start + size);
3823 operands[2] = GEN_INT (64 - size);
3824 return \"rldicl %0,%1,%3,%2\";
3826 [(set_attr "type" "shift")])
3828 (define_insn "*extzvdi_internal1"
3829 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3830 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3831 (match_operand:SI 2 "const_int_operand" "i")
3832 (match_operand:SI 3 "const_int_operand" "i"))
3834 (clobber (match_scratch:DI 4 "=r"))]
3835 "TARGET_64BIT && rs6000_gen_cell_microcode"
3838 int start = INTVAL (operands[3]) & 63;
3839 int size = INTVAL (operands[2]) & 63;
3841 if (start + size >= 64)
3842 operands[3] = const0_rtx;
3844 operands[3] = GEN_INT (start + size);
3845 operands[2] = GEN_INT (64 - size);
3846 return \"rldicl. %4,%1,%3,%2\";
3848 [(set_attr "type" "shift")
3849 (set_attr "dot" "yes")])
3851 (define_insn "*extzvdi_internal2"
3852 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3853 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3854 (match_operand:SI 2 "const_int_operand" "i")
3855 (match_operand:SI 3 "const_int_operand" "i"))
3857 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3858 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3859 "TARGET_64BIT && rs6000_gen_cell_microcode"
3862 int start = INTVAL (operands[3]) & 63;
3863 int size = INTVAL (operands[2]) & 63;
3865 if (start + size >= 64)
3866 operands[3] = const0_rtx;
3868 operands[3] = GEN_INT (start + size);
3869 operands[2] = GEN_INT (64 - size);
3870 return \"rldicl. %0,%1,%3,%2\";
3872 [(set_attr "type" "shift")
3873 (set_attr "dot" "yes")])
3876 (define_insn "rotl<mode>3"
3877 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3878 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3879 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3881 "rotl<wd>%I2 %0,%1,%<hH>2"
3882 [(set_attr "type" "shift")
3883 (set_attr "maybe_var_shift" "yes")])
3885 (define_insn "*rotlsi3_64"
3886 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3888 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3889 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3891 "rotlw%I2 %0,%1,%h2"
3892 [(set_attr "type" "shift")
3893 (set_attr "maybe_var_shift" "yes")])
3895 (define_insn_and_split "*rotl<mode>3_dot"
3896 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3897 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3898 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3900 (clobber (match_scratch:GPR 0 "=r,r"))]
3901 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3903 rotl<wd>%I2. %0,%1,%<hH>2
3905 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3907 (rotate:GPR (match_dup 1)
3910 (compare:CC (match_dup 0)
3913 [(set_attr "type" "shift")
3914 (set_attr "maybe_var_shift" "yes")
3915 (set_attr "dot" "yes")
3916 (set_attr "length" "4,8")])
3918 (define_insn_and_split "*rotl<mode>3_dot2"
3919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3920 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3921 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3923 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3924 (rotate:GPR (match_dup 1)
3926 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3928 rotl<wd>%I2. %0,%1,%<hH>2
3930 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3932 (rotate:GPR (match_dup 1)
3935 (compare:CC (match_dup 0)
3938 [(set_attr "type" "shift")
3939 (set_attr "maybe_var_shift" "yes")
3940 (set_attr "dot" "yes")
3941 (set_attr "length" "4,8")])
3944 (define_insn "*rotlsi3_internal4"
3945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3946 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3947 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3948 (match_operand:SI 3 "mask_operand" "n")))]
3950 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3951 [(set_attr "type" "shift")
3952 (set_attr "maybe_var_shift" "yes")])
3954 (define_insn "*rotlsi3_internal5"
3955 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3957 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3959 (match_operand:SI 3 "mask_operand" "n,n"))
3961 (clobber (match_scratch:SI 4 "=r,r"))]
3964 rlw%I2nm. %4,%1,%h2,%m3,%M3
3966 [(set_attr "type" "shift")
3967 (set_attr "maybe_var_shift" "yes")
3968 (set_attr "dot" "yes")
3969 (set_attr "length" "4,8")])
3972 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3974 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3975 (match_operand:SI 2 "reg_or_cint_operand" ""))
3976 (match_operand:SI 3 "mask_operand" ""))
3978 (clobber (match_scratch:SI 4 ""))]
3981 (and:SI (rotate:SI (match_dup 1)
3985 (compare:CC (match_dup 4)
3989 (define_insn "*rotlsi3_internal6"
3990 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3992 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3993 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3994 (match_operand:SI 3 "mask_operand" "n,n"))
3996 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3997 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4000 rlw%I2nm. %0,%1,%h2,%m3,%M3
4002 [(set_attr "type" "shift")
4003 (set_attr "maybe_var_shift" "yes")
4004 (set_attr "dot" "yes")
4005 (set_attr "length" "4,8")])
4008 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4010 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "reg_or_cint_operand" ""))
4012 (match_operand:SI 3 "mask_operand" ""))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4018 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4020 (compare:CC (match_dup 0)
4024 (define_insn "*rotlsi3_internal7le"
4025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4028 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4029 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4031 "rlw%I2nm %0,%1,%h2,0xff"
4032 [(set (attr "cell_micro")
4033 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4034 (const_string "not")
4035 (const_string "always")))
4036 (set_attr "type" "shift")])
4038 (define_insn "*rotlsi3_internal7be"
4039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4042 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4043 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
4045 "rlw%I2nm %0,%1,%h2,0xff"
4046 [(set (attr "cell_micro")
4047 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4048 (const_string "not")
4049 (const_string "always")))
4050 (set_attr "type" "shift")])
4052 (define_insn "*rotlsi3_internal8le"
4053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4054 (compare:CC (zero_extend:SI
4056 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4057 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4059 (clobber (match_scratch:SI 3 "=r,r"))]
4062 rlw%I2nm. %3,%1,%h2,0xff
4064 [(set_attr "type" "shift")
4065 (set_attr "maybe_var_shift" "yes")
4066 (set_attr "dot" "yes")
4067 (set_attr "length" "4,8")])
4069 (define_insn "*rotlsi3_internal8be"
4070 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4071 (compare:CC (zero_extend:SI
4073 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4074 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
4076 (clobber (match_scratch:SI 3 "=r,r"))]
4079 rlw%I2nm. %3,%1,%h2,0xff
4081 [(set_attr "type" "shift")
4082 (set_attr "maybe_var_shift" "yes")
4083 (set_attr "dot" "yes")
4084 (set_attr "length" "4,8")])
4087 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4088 (compare:CC (zero_extend:SI
4090 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4091 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4093 (clobber (match_scratch:SI 3 ""))]
4094 "!BYTES_BIG_ENDIAN && reload_completed"
4096 (zero_extend:SI (subreg:QI
4097 (rotate:SI (match_dup 1)
4100 (compare:CC (match_dup 3)
4105 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4106 (compare:CC (zero_extend:SI
4108 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4109 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4111 (clobber (match_scratch:SI 3 ""))]
4112 "BYTES_BIG_ENDIAN && reload_completed"
4114 (zero_extend:SI (subreg:QI
4115 (rotate:SI (match_dup 1)
4118 (compare:CC (match_dup 3)
4122 (define_insn "*rotlsi3_internal9le"
4123 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4124 (compare:CC (zero_extend:SI
4126 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4127 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4129 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4130 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4133 rlw%I2nm. %0,%1,%h2,0xff
4135 [(set_attr "type" "shift")
4136 (set_attr "maybe_var_shift" "yes")
4137 (set_attr "dot" "yes")
4138 (set_attr "length" "4,8")])
4140 (define_insn "*rotlsi3_internal9be"
4141 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4142 (compare:CC (zero_extend:SI
4144 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4145 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
4147 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4148 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4151 rlw%I2nm. %0,%1,%h2,0xff
4153 [(set_attr "type" "shift")
4154 (set_attr "maybe_var_shift" "yes")
4155 (set_attr "dot" "yes")
4156 (set_attr "length" "4,8")])
4159 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4160 (compare:CC (zero_extend:SI
4162 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4163 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4165 (set (match_operand:SI 0 "gpc_reg_operand" "")
4166 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4167 "!BYTES_BIG_ENDIAN && reload_completed"
4169 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4171 (compare:CC (match_dup 0)
4176 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4177 (compare:CC (zero_extend:SI
4179 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4180 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4182 (set (match_operand:SI 0 "gpc_reg_operand" "")
4183 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4184 "BYTES_BIG_ENDIAN && reload_completed"
4186 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4188 (compare:CC (match_dup 0)
4192 (define_insn "*rotlsi3_internal10le"
4193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4196 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4197 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
4199 "rlw%I2nm %0,%1,%h2,0xffff"
4200 [(set_attr "type" "shift")
4201 (set_attr "maybe_var_shift" "yes")])
4203 (define_insn "*rotlsi3_internal10be"
4204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4207 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4208 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
4210 "rlw%I2nm %0,%1,%h2,0xffff"
4211 [(set_attr "type" "shift")
4212 (set_attr "maybe_var_shift" "yes")])
4214 (define_insn "*rotlsi3_internal11le"
4215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4216 (compare:CC (zero_extend:SI
4218 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4219 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4221 (clobber (match_scratch:SI 3 "=r,r"))]
4224 rlw%I2nm. %3,%1,%h2,0xffff
4226 [(set_attr "type" "shift")
4227 (set_attr "maybe_var_shift" "yes")
4228 (set_attr "dot" "yes")
4229 (set_attr "length" "4,8")])
4231 (define_insn "*rotlsi3_internal11be"
4232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4233 (compare:CC (zero_extend:SI
4235 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4236 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4238 (clobber (match_scratch:SI 3 "=r,r"))]
4241 rlw%I2nm. %3,%1,%h2,0xffff
4243 [(set_attr "type" "shift")
4244 (set_attr "maybe_var_shift" "yes")
4245 (set_attr "dot" "yes")
4246 (set_attr "length" "4,8")])
4249 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4250 (compare:CC (zero_extend:SI
4252 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4253 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4255 (clobber (match_scratch:SI 3 ""))]
4256 "!BYTES_BIG_ENDIAN && reload_completed"
4258 (zero_extend:SI (subreg:HI
4259 (rotate:SI (match_dup 1)
4262 (compare:CC (match_dup 3)
4267 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4268 (compare:CC (zero_extend:SI
4270 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4271 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4273 (clobber (match_scratch:SI 3 ""))]
4274 "BYTES_BIG_ENDIAN && reload_completed"
4276 (zero_extend:SI (subreg:HI
4277 (rotate:SI (match_dup 1)
4280 (compare:CC (match_dup 3)
4284 (define_insn "*rotlsi3_internal12le"
4285 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4286 (compare:CC (zero_extend:SI
4288 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4289 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4291 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4292 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4295 rlw%I2nm. %0,%1,%h2,0xffff
4297 [(set_attr "type" "shift")
4298 (set_attr "maybe_var_shift" "yes")
4299 (set_attr "dot" "yes")
4300 (set_attr "length" "4,8")])
4302 (define_insn "*rotlsi3_internal12be"
4303 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4304 (compare:CC (zero_extend:SI
4306 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4307 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4309 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4310 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4313 rlw%I2nm. %0,%1,%h2,0xffff
4315 [(set_attr "type" "shift")
4316 (set_attr "maybe_var_shift" "yes")
4317 (set_attr "dot" "yes")
4318 (set_attr "length" "4,8")])
4321 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4322 (compare:CC (zero_extend:SI
4324 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4325 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4327 (set (match_operand:SI 0 "gpc_reg_operand" "")
4328 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4329 "!BYTES_BIG_ENDIAN && reload_completed"
4331 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4333 (compare:CC (match_dup 0)
4338 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4339 (compare:CC (zero_extend:SI
4341 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4342 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4344 (set (match_operand:SI 0 "gpc_reg_operand" "")
4345 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4346 "BYTES_BIG_ENDIAN && reload_completed"
4348 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4350 (compare:CC (match_dup 0)
4355 (define_insn "ashl<mode>3"
4356 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4357 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4358 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4360 "sl<wd>%I2 %0,%1,%<hH>2"
4361 [(set_attr "type" "shift")
4362 (set_attr "maybe_var_shift" "yes")])
4364 (define_insn "*ashlsi3_64"
4365 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4367 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4368 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4371 [(set_attr "type" "shift")
4372 (set_attr "maybe_var_shift" "yes")])
4374 (define_insn_and_split "*ashl<mode>3_dot"
4375 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4376 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4377 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4379 (clobber (match_scratch:GPR 0 "=r,r"))]
4380 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4382 sl<wd>%I2. %0,%1,%<hH>2
4384 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4386 (ashift:GPR (match_dup 1)
4389 (compare:CC (match_dup 0)
4392 [(set_attr "type" "shift")
4393 (set_attr "maybe_var_shift" "yes")
4394 (set_attr "dot" "yes")
4395 (set_attr "length" "4,8")])
4397 (define_insn_and_split "*ashl<mode>3_dot2"
4398 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4399 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4400 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4402 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4403 (ashift:GPR (match_dup 1)
4405 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4407 sl<wd>%I2. %0,%1,%<hH>2
4409 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4411 (ashift:GPR (match_dup 1)
4414 (compare:CC (match_dup 0)
4417 [(set_attr "type" "shift")
4418 (set_attr "maybe_var_shift" "yes")
4419 (set_attr "dot" "yes")
4420 (set_attr "length" "4,8")])
4423 (define_insn "rlwinm"
4424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4425 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4426 (match_operand:SI 2 "const_int_operand" "i"))
4427 (match_operand:SI 3 "mask_operand" "n")))]
4428 "includes_lshift_p (operands[2], operands[3])"
4429 "rlwinm %0,%1,%h2,%m3,%M3"
4430 [(set_attr "type" "shift")])
4433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4435 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4436 (match_operand:SI 2 "const_int_operand" "i,i"))
4437 (match_operand:SI 3 "mask_operand" "n,n"))
4439 (clobber (match_scratch:SI 4 "=r,r"))]
4440 "includes_lshift_p (operands[2], operands[3])"
4442 rlwinm. %4,%1,%h2,%m3,%M3
4444 [(set_attr "type" "shift")
4445 (set_attr "dot" "yes")
4446 (set_attr "length" "4,8")])
4449 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4451 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4452 (match_operand:SI 2 "const_int_operand" ""))
4453 (match_operand:SI 3 "mask_operand" ""))
4455 (clobber (match_scratch:SI 4 ""))]
4456 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4458 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4461 (compare:CC (match_dup 4)
4466 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4468 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4469 (match_operand:SI 2 "const_int_operand" "i,i"))
4470 (match_operand:SI 3 "mask_operand" "n,n"))
4472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4473 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4474 "includes_lshift_p (operands[2], operands[3])"
4476 rlwinm. %0,%1,%h2,%m3,%M3
4478 [(set_attr "type" "shift")
4479 (set_attr "dot" "yes")
4480 (set_attr "length" "4,8")])
4483 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4485 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4486 (match_operand:SI 2 "const_int_operand" ""))
4487 (match_operand:SI 3 "mask_operand" ""))
4489 (set (match_operand:SI 0 "gpc_reg_operand" "")
4490 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4491 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4493 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4495 (compare:CC (match_dup 0)
4500 (define_insn "lshr<mode>3"
4501 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4502 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4503 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4505 "sr<wd>%I2 %0,%1,%<hH>2"
4506 [(set_attr "type" "shift")
4507 (set_attr "maybe_var_shift" "yes")])
4509 (define_insn "*lshrsi3_64"
4510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4512 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4513 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4516 [(set_attr "type" "shift")
4517 (set_attr "maybe_var_shift" "yes")])
4519 (define_insn_and_split "*lshr<mode>3_dot"
4520 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4521 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4522 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4524 (clobber (match_scratch:GPR 0 "=r,r"))]
4525 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4527 sr<wd>%I2. %0,%1,%<hH>2
4529 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4531 (lshiftrt:GPR (match_dup 1)
4534 (compare:CC (match_dup 0)
4537 [(set_attr "type" "shift")
4538 (set_attr "maybe_var_shift" "yes")
4539 (set_attr "dot" "yes")
4540 (set_attr "length" "4,8")])
4542 (define_insn_and_split "*lshr<mode>3_dot2"
4543 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4544 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4545 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4547 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4548 (lshiftrt:GPR (match_dup 1)
4550 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4552 sr<wd>%I2. %0,%1,%<hH>2
4554 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4556 (lshiftrt:GPR (match_dup 1)
4559 (compare:CC (match_dup 0)
4562 [(set_attr "type" "shift")
4563 (set_attr "maybe_var_shift" "yes")
4564 (set_attr "dot" "yes")
4565 (set_attr "length" "4,8")])
4569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4570 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4571 (match_operand:SI 2 "const_int_operand" "i"))
4572 (match_operand:SI 3 "mask_operand" "n")))]
4573 "includes_rshift_p (operands[2], operands[3])"
4574 "rlwinm %0,%1,%s2,%m3,%M3"
4575 [(set_attr "type" "shift")])
4578 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4580 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4581 (match_operand:SI 2 "const_int_operand" "i,i"))
4582 (match_operand:SI 3 "mask_operand" "n,n"))
4584 (clobber (match_scratch:SI 4 "=r,r"))]
4585 "includes_rshift_p (operands[2], operands[3])"
4587 rlwinm. %4,%1,%s2,%m3,%M3
4589 [(set_attr "type" "shift")
4590 (set_attr "dot" "yes")
4591 (set_attr "length" "4,8")])
4594 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4596 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4597 (match_operand:SI 2 "const_int_operand" ""))
4598 (match_operand:SI 3 "mask_operand" ""))
4600 (clobber (match_scratch:SI 4 ""))]
4601 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4603 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4606 (compare:CC (match_dup 4)
4611 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4613 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4614 (match_operand:SI 2 "const_int_operand" "i,i"))
4615 (match_operand:SI 3 "mask_operand" "n,n"))
4617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4618 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4619 "includes_rshift_p (operands[2], operands[3])"
4621 rlwinm. %0,%1,%s2,%m3,%M3
4623 [(set_attr "type" "shift")
4624 (set_attr "dot" "yes")
4625 (set_attr "length" "4,8")])
4628 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4630 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4631 (match_operand:SI 2 "const_int_operand" ""))
4632 (match_operand:SI 3 "mask_operand" ""))
4634 (set (match_operand:SI 0 "gpc_reg_operand" "")
4635 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4636 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4638 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4640 (compare:CC (match_dup 0)
4644 (define_insn "*lshiftrt_internal1le"
4645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4648 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4649 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4650 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4651 "rlwinm %0,%1,%s2,0xff"
4652 [(set_attr "type" "shift")])
4654 (define_insn "*lshiftrt_internal1be"
4655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4658 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4659 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4660 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4661 "rlwinm %0,%1,%s2,0xff"
4662 [(set_attr "type" "shift")])
4664 (define_insn "*lshiftrt_internal2le"
4665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4669 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4670 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4672 (clobber (match_scratch:SI 3 "=r,r"))]
4673 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4675 rlwinm. %3,%1,%s2,0xff
4677 [(set_attr "type" "shift")
4678 (set_attr "dot" "yes")
4679 (set_attr "length" "4,8")])
4681 (define_insn "*lshiftrt_internal2be"
4682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4686 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4687 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4689 (clobber (match_scratch:SI 3 "=r,r"))]
4690 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4692 rlwinm. %3,%1,%s2,0xff
4694 [(set_attr "type" "shift")
4695 (set_attr "dot" "yes")
4696 (set_attr "length" "4,8")])
4699 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4703 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4704 (match_operand:SI 2 "const_int_operand" "")) 0))
4706 (clobber (match_scratch:SI 3 ""))]
4707 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4709 (zero_extend:SI (subreg:QI
4710 (lshiftrt:SI (match_dup 1)
4713 (compare:CC (match_dup 3)
4718 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4722 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4723 (match_operand:SI 2 "const_int_operand" "")) 3))
4725 (clobber (match_scratch:SI 3 ""))]
4726 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4728 (zero_extend:SI (subreg:QI
4729 (lshiftrt:SI (match_dup 1)
4732 (compare:CC (match_dup 3)
4736 (define_insn "*lshiftrt_internal3le"
4737 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4741 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4742 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4744 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4745 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4746 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4748 rlwinm. %0,%1,%s2,0xff
4750 [(set_attr "type" "shift")
4751 (set_attr "dot" "yes")
4752 (set_attr "length" "4,8")])
4754 (define_insn "*lshiftrt_internal3be"
4755 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4759 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4760 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4762 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4763 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4764 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4766 rlwinm. %0,%1,%s2,0xff
4768 [(set_attr "type" "shift")
4769 (set_attr "dot" "yes")
4770 (set_attr "length" "4,8")])
4773 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4777 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4778 (match_operand:SI 2 "const_int_operand" "")) 0))
4780 (set (match_operand:SI 0 "gpc_reg_operand" "")
4781 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4782 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4784 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4786 (compare:CC (match_dup 0)
4791 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4795 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4796 (match_operand:SI 2 "const_int_operand" "")) 3))
4798 (set (match_operand:SI 0 "gpc_reg_operand" "")
4799 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4800 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4802 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4804 (compare:CC (match_dup 0)
4808 (define_insn "*lshiftrt_internal4le"
4809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4812 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4813 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4814 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4815 "rlwinm %0,%1,%s2,0xffff"
4816 [(set_attr "type" "shift")])
4818 (define_insn "*lshiftrt_internal4be"
4819 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4822 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4823 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4824 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4825 "rlwinm %0,%1,%s2,0xffff"
4826 [(set_attr "type" "shift")])
4828 (define_insn "*lshiftrt_internal5le"
4829 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4833 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4834 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4836 (clobber (match_scratch:SI 3 "=r,r"))]
4837 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4839 rlwinm. %3,%1,%s2,0xffff
4841 [(set_attr "type" "shift")
4842 (set_attr "dot" "yes")
4843 (set_attr "length" "4,8")])
4845 (define_insn "*lshiftrt_internal5be"
4846 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4850 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4851 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4853 (clobber (match_scratch:SI 3 "=r,r"))]
4854 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4856 rlwinm. %3,%1,%s2,0xffff
4858 [(set_attr "type" "shift")
4859 (set_attr "dot" "yes")
4860 (set_attr "length" "4,8")])
4863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4867 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4868 (match_operand:SI 2 "const_int_operand" "")) 0))
4870 (clobber (match_scratch:SI 3 ""))]
4871 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4873 (zero_extend:SI (subreg:HI
4874 (lshiftrt:SI (match_dup 1)
4877 (compare:CC (match_dup 3)
4882 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4886 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4887 (match_operand:SI 2 "const_int_operand" "")) 2))
4889 (clobber (match_scratch:SI 3 ""))]
4890 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4892 (zero_extend:SI (subreg:HI
4893 (lshiftrt:SI (match_dup 1)
4896 (compare:CC (match_dup 3)
4900 (define_insn "*lshiftrt_internal5le"
4901 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4905 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4906 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4908 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4909 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4910 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4912 rlwinm. %0,%1,%s2,0xffff
4914 [(set_attr "type" "shift")
4915 (set_attr "dot" "yes")
4916 (set_attr "length" "4,8")])
4918 (define_insn "*lshiftrt_internal5be"
4919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4923 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4924 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4926 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4927 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4928 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4930 rlwinm. %0,%1,%s2,0xffff
4932 [(set_attr "type" "shift")
4933 (set_attr "dot" "yes")
4934 (set_attr "length" "4,8")])
4937 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4941 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4942 (match_operand:SI 2 "const_int_operand" "")) 0))
4944 (set (match_operand:SI 0 "gpc_reg_operand" "")
4945 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4946 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4948 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4950 (compare:CC (match_dup 0)
4955 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4959 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4960 (match_operand:SI 2 "const_int_operand" "")) 2))
4962 (set (match_operand:SI 0 "gpc_reg_operand" "")
4963 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4964 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4966 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4968 (compare:CC (match_dup 0)
4973 (define_expand "ashr<mode>3"
4974 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4975 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4976 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4979 /* The generic code does not generate optimal code for the low word
4980 (it should be a rlwimi and a rot). Until we have target code to
4981 solve this generically, keep this expander. */
4983 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4985 if (CONST_INT_P (operands[2]))
4987 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4995 (define_insn "*ashr<mode>3"
4996 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4997 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4998 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
5000 "sra<wd>%I2 %0,%1,%<hH>2"
5001 [(set_attr "type" "shift")
5002 (set_attr "maybe_var_shift" "yes")])
5004 (define_insn "*ashrsi3_64"
5005 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5007 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5008 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
5011 [(set_attr "type" "shift")
5012 (set_attr "maybe_var_shift" "yes")])
5014 (define_insn_and_split "*ashr<mode>3_dot"
5015 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5016 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
5017 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
5019 (clobber (match_scratch:GPR 0 "=r,r"))]
5020 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
5022 sra<wd>%I2. %0,%1,%<hH>2
5024 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
5026 (ashiftrt:GPR (match_dup 1)
5029 (compare:CC (match_dup 0)
5032 [(set_attr "type" "shift")
5033 (set_attr "maybe_var_shift" "yes")
5034 (set_attr "dot" "yes")
5035 (set_attr "length" "4,8")])
5037 (define_insn_and_split "*ashr<mode>3_dot2"
5038 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5039 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
5040 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
5042 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5043 (ashiftrt:GPR (match_dup 1)
5045 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
5047 sra<wd>%I2. %0,%1,%<hH>2
5049 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
5051 (ashiftrt:GPR (match_dup 1)
5054 (compare:CC (match_dup 0)
5057 [(set_attr "type" "shift")
5058 (set_attr "maybe_var_shift" "yes")
5059 (set_attr "dot" "yes")
5060 (set_attr "length" "4,8")])
5062 ;; Builtins to replace a division to generate FRE reciprocal estimate
5063 ;; instructions and the necessary fixup instructions
5064 (define_expand "recip<mode>3"
5065 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5066 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5067 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5068 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5070 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5074 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5075 ;; hardware division. This is only done before register allocation and with
5076 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5078 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5079 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5080 (match_operand 2 "gpc_reg_operand" "")))]
5081 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5082 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5083 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5086 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5090 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5091 ;; appropriate fixup.
5092 (define_expand "rsqrt<mode>2"
5093 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5094 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5095 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5097 rs6000_emit_swrsqrt (operands[0], operands[1]);
5101 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
5102 ;; modes here, and also add in conditional vsx/power8-vector support to access
5103 ;; values in the traditional Altivec registers if the appropriate
5104 ;; -mupper-regs-{df,sf} option is enabled.
5106 (define_expand "abs<mode>2"
5107 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5108 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5109 "TARGET_<MODE>_INSN"
5112 (define_insn "*abs<mode>2_fpr"
5113 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5114 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5119 [(set_attr "type" "fp")
5120 (set_attr "fp_type" "fp_addsub_<Fs>")])
5122 (define_insn "*nabs<mode>2_fpr"
5123 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5126 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
5131 [(set_attr "type" "fp")
5132 (set_attr "fp_type" "fp_addsub_<Fs>")])
5134 (define_expand "neg<mode>2"
5135 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5136 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5137 "TARGET_<MODE>_INSN"
5140 (define_insn "*neg<mode>2_fpr"
5141 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5142 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5147 [(set_attr "type" "fp")
5148 (set_attr "fp_type" "fp_addsub_<Fs>")])
5150 (define_expand "add<mode>3"
5151 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5152 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5153 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5154 "TARGET_<MODE>_INSN"
5157 (define_insn "*add<mode>3_fpr"
5158 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5159 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5160 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5163 fadd<Ftrad> %0,%1,%2
5164 xsadd<Fvsx> %x0,%x1,%x2"
5165 [(set_attr "type" "fp")
5166 (set_attr "fp_type" "fp_addsub_<Fs>")])
5168 (define_expand "sub<mode>3"
5169 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5170 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5171 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5172 "TARGET_<MODE>_INSN"
5175 (define_insn "*sub<mode>3_fpr"
5176 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5177 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5178 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5181 fsub<Ftrad> %0,%1,%2
5182 xssub<Fvsx> %x0,%x1,%x2"
5183 [(set_attr "type" "fp")
5184 (set_attr "fp_type" "fp_addsub_<Fs>")])
5186 (define_expand "mul<mode>3"
5187 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5188 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5189 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5190 "TARGET_<MODE>_INSN"
5193 (define_insn "*mul<mode>3_fpr"
5194 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5195 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5196 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5199 fmul<Ftrad> %0,%1,%2
5200 xsmul<Fvsx> %x0,%x1,%x2"
5201 [(set_attr "type" "dmul")
5202 (set_attr "fp_type" "fp_mul_<Fs>")])
5204 (define_expand "div<mode>3"
5205 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5206 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5207 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5208 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
5211 (define_insn "*div<mode>3_fpr"
5212 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5213 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5214 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5215 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
5217 fdiv<Ftrad> %0,%1,%2
5218 xsdiv<Fvsx> %x0,%x1,%x2"
5219 [(set_attr "type" "<Fs>div")
5220 (set_attr "fp_type" "fp_div_<Fs>")])
5222 (define_insn "sqrt<mode>2"
5223 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5224 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5225 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
5226 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
5229 xssqrt<Fvsx> %x0,%x1"
5230 [(set_attr "type" "<Fs>sqrt")
5231 (set_attr "fp_type" "fp_sqrt_<Fs>")])
5233 ;; Floating point reciprocal approximation
5234 (define_insn "fre<Fs>"
5235 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5236 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5242 [(set_attr "type" "fp")])
5244 (define_insn "*rsqrt<mode>2"
5245 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5246 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5248 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5250 frsqrte<Ftrad> %0,%1
5251 xsrsqrte<Fvsx> %x0,%x1"
5252 [(set_attr "type" "fp")])
5254 ;; Floating point comparisons
5255 (define_insn "*cmp<mode>_fpr"
5256 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5257 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5258 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5262 xscmpudp %0,%x1,%x2"
5263 [(set_attr "type" "fpcompare")])
5265 ;; Floating point conversions
5266 (define_expand "extendsfdf2"
5267 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5268 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5269 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5272 (define_insn_and_split "*extendsfdf2_fpr"
5273 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
5274 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5275 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5283 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5286 emit_note (NOTE_INSN_DELETED);
5289 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
5291 (define_expand "truncdfsf2"
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5293 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5294 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5297 (define_insn "*truncdfsf2_fpr"
5298 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5299 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5300 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5302 [(set_attr "type" "fp")])
5304 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5305 ;; builtins.c and optabs.c that are not correct for IBM long double
5306 ;; when little-endian.
5307 (define_expand "signbittf2"
5309 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5311 (subreg:DI (match_dup 2) 0))
5314 (set (match_operand:SI 0 "gpc_reg_operand" "")
5317 && TARGET_HARD_FLOAT
5318 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5319 && TARGET_LONG_DOUBLE_128"
5321 operands[2] = gen_reg_rtx (DFmode);
5322 operands[3] = gen_reg_rtx (DImode);
5323 if (TARGET_POWERPC64)
5325 operands[4] = gen_reg_rtx (DImode);
5326 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5327 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5328 WORDS_BIG_ENDIAN ? 4 : 0);
5332 operands[4] = gen_reg_rtx (SImode);
5333 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5334 WORDS_BIG_ENDIAN ? 0 : 4);
5335 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5339 (define_expand "copysign<mode>3"
5341 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5343 (neg:SFDF (abs:SFDF (match_dup 1))))
5344 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5345 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5349 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5350 && ((TARGET_PPC_GFXOPT
5351 && !HONOR_NANS (<MODE>mode)
5352 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5354 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5356 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5358 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5363 operands[3] = gen_reg_rtx (<MODE>mode);
5364 operands[4] = gen_reg_rtx (<MODE>mode);
5365 operands[5] = CONST0_RTX (<MODE>mode);
5368 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5369 ;; compiler from optimizing -0.0
5370 (define_insn "copysign<mode>3_fcpsgn"
5371 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5372 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5373 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5375 "TARGET_<MODE>_FPR && TARGET_CMPB"
5378 xscpsgn<Fvsx> %x0,%x2,%x1"
5379 [(set_attr "type" "fp")])
5381 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5382 ;; fsel instruction and some auxiliary computations. Then we just have a
5383 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5385 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5386 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5387 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5388 ;; define_splits to make them if made by combine. On VSX machines we have the
5389 ;; min/max instructions.
5391 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5392 ;; to allow either DF/SF to use only traditional registers.
5394 (define_expand "smax<mode>3"
5395 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5396 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5397 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5400 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5402 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5406 (define_insn "*smax<mode>3_vsx"
5407 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5408 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5409 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5410 "TARGET_<MODE>_FPR && TARGET_VSX"
5411 "xsmaxdp %x0,%x1,%x2"
5412 [(set_attr "type" "fp")])
5414 (define_expand "smin<mode>3"
5415 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5416 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5417 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5420 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5422 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5426 (define_insn "*smin<mode>3_vsx"
5427 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5428 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5429 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5430 "TARGET_<MODE>_FPR && TARGET_VSX"
5431 "xsmindp %x0,%x1,%x2"
5432 [(set_attr "type" "fp")])
5435 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5436 (match_operator:SFDF 3 "min_max_operator"
5437 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5438 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5439 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5443 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5449 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5450 (match_operator:SF 3 "min_max_operator"
5451 [(match_operand:SF 1 "gpc_reg_operand" "")
5452 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5453 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5454 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5457 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5458 operands[1], operands[2]);
5462 (define_expand "mov<mode>cc"
5463 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5464 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5465 (match_operand:GPR 2 "gpc_reg_operand" "")
5466 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5470 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5476 ;; We use the BASE_REGS for the isel input operands because, if rA is
5477 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5478 ;; because we may switch the operands and rB may end up being rA.
5480 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5481 ;; leave out the mode in operand 4 and use one pattern, but reload can
5482 ;; change the mode underneath our feet and then gets confused trying
5483 ;; to reload the value.
5484 (define_insn "isel_signed_<mode>"
5485 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5487 (match_operator 1 "scc_comparison_operator"
5488 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5490 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5491 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5494 { return output_isel (operands); }"
5495 [(set_attr "type" "isel")
5496 (set_attr "length" "4")])
5498 (define_insn "isel_unsigned_<mode>"
5499 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5501 (match_operator 1 "scc_comparison_operator"
5502 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5504 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5505 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5508 { return output_isel (operands); }"
5509 [(set_attr "type" "isel")
5510 (set_attr "length" "4")])
5512 ;; These patterns can be useful for combine; they let combine know that
5513 ;; isel can handle reversed comparisons so long as the operands are
5516 (define_insn "*isel_reversed_signed_<mode>"
5517 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5519 (match_operator 1 "scc_rev_comparison_operator"
5520 [(match_operand:CC 4 "cc_reg_operand" "y")
5522 (match_operand:GPR 2 "gpc_reg_operand" "b")
5523 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5526 { return output_isel (operands); }"
5527 [(set_attr "type" "isel")
5528 (set_attr "length" "4")])
5530 (define_insn "*isel_reversed_unsigned_<mode>"
5531 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5533 (match_operator 1 "scc_rev_comparison_operator"
5534 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5536 (match_operand:GPR 2 "gpc_reg_operand" "b")
5537 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5540 { return output_isel (operands); }"
5541 [(set_attr "type" "isel")
5542 (set_attr "length" "4")])
5544 (define_expand "movsfcc"
5545 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5546 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5547 (match_operand:SF 2 "gpc_reg_operand" "")
5548 (match_operand:SF 3 "gpc_reg_operand" "")))]
5549 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5552 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5558 (define_insn "*fselsfsf4"
5559 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5560 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5561 (match_operand:SF 4 "zero_fp_constant" "F"))
5562 (match_operand:SF 2 "gpc_reg_operand" "f")
5563 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5564 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5566 [(set_attr "type" "fp")])
5568 (define_insn "*fseldfsf4"
5569 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5570 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5571 (match_operand:DF 4 "zero_fp_constant" "F"))
5572 (match_operand:SF 2 "gpc_reg_operand" "f")
5573 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5574 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5576 [(set_attr "type" "fp")])
5578 ;; The conditional move instructions allow us to perform max and min
5579 ;; operations even when
5582 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5583 (match_operator:DF 3 "min_max_operator"
5584 [(match_operand:DF 1 "gpc_reg_operand" "")
5585 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5586 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5587 && !flag_trapping_math"
5590 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5591 operands[1], operands[2]);
5595 (define_expand "movdfcc"
5596 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5597 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5598 (match_operand:DF 2 "gpc_reg_operand" "")
5599 (match_operand:DF 3 "gpc_reg_operand" "")))]
5600 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5603 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5609 (define_insn "*fseldfdf4"
5610 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5611 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5612 (match_operand:DF 4 "zero_fp_constant" "F"))
5613 (match_operand:DF 2 "gpc_reg_operand" "d")
5614 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5615 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5617 [(set_attr "type" "fp")])
5619 (define_insn "*fselsfdf4"
5620 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5621 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5622 (match_operand:SF 4 "zero_fp_constant" "F"))
5623 (match_operand:DF 2 "gpc_reg_operand" "d")
5624 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5625 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5627 [(set_attr "type" "fp")])
5629 ;; Conversions to and from floating-point.
5631 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5632 ; don't want to support putting SImode in FPR registers.
5633 (define_insn "lfiwax"
5634 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5635 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5637 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5642 [(set_attr "type" "fpload,fpload,mffgpr")])
5644 ; This split must be run before register allocation because it allocates the
5645 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5646 ; it earlier to allow for the combiner to merge insns together where it might
5647 ; not be needed and also in case the insns are deleted as dead code.
5649 (define_insn_and_split "floatsi<mode>2_lfiwax"
5650 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5651 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5652 (clobber (match_scratch:DI 2 "=d"))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5654 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5660 rtx dest = operands[0];
5661 rtx src = operands[1];
5664 if (!MEM_P (src) && TARGET_POWERPC64
5665 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5666 tmp = convert_to_mode (DImode, src, false);
5670 if (GET_CODE (tmp) == SCRATCH)
5671 tmp = gen_reg_rtx (DImode);
5674 src = rs6000_address_for_fpconvert (src);
5675 emit_insn (gen_lfiwax (tmp, src));
5679 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5680 emit_move_insn (stack, src);
5681 emit_insn (gen_lfiwax (tmp, stack));
5684 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5687 [(set_attr "length" "12")
5688 (set_attr "type" "fpload")])
5690 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5691 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5694 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5695 (clobber (match_scratch:DI 2 "=0,d"))]
5696 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5703 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5704 if (GET_CODE (operands[2]) == SCRATCH)
5705 operands[2] = gen_reg_rtx (DImode);
5706 emit_insn (gen_lfiwax (operands[2], operands[1]));
5707 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5710 [(set_attr "length" "8")
5711 (set_attr "type" "fpload")])
5713 (define_insn "lfiwzx"
5714 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5715 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5717 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5722 [(set_attr "type" "fpload,fpload,mftgpr")])
5724 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5725 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5726 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5727 (clobber (match_scratch:DI 2 "=d"))]
5728 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5735 rtx dest = operands[0];
5736 rtx src = operands[1];
5739 if (!MEM_P (src) && TARGET_POWERPC64
5740 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5741 tmp = convert_to_mode (DImode, src, true);
5745 if (GET_CODE (tmp) == SCRATCH)
5746 tmp = gen_reg_rtx (DImode);
5749 src = rs6000_address_for_fpconvert (src);
5750 emit_insn (gen_lfiwzx (tmp, src));
5754 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5755 emit_move_insn (stack, src);
5756 emit_insn (gen_lfiwzx (tmp, stack));
5759 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5762 [(set_attr "length" "12")
5763 (set_attr "type" "fpload")])
5765 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5766 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5767 (unsigned_float:SFDF
5769 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5770 (clobber (match_scratch:DI 2 "=0,d"))]
5771 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5778 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5779 if (GET_CODE (operands[2]) == SCRATCH)
5780 operands[2] = gen_reg_rtx (DImode);
5781 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5782 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5785 [(set_attr "length" "8")
5786 (set_attr "type" "fpload")])
5788 ; For each of these conversions, there is a define_expand, a define_insn
5789 ; with a '#' template, and a define_split (with C code). The idea is
5790 ; to allow constant folding with the template of the define_insn,
5791 ; then to have the insns split later (between sched1 and final).
5793 (define_expand "floatsidf2"
5794 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5795 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5798 (clobber (match_dup 4))
5799 (clobber (match_dup 5))
5800 (clobber (match_dup 6))])]
5802 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5805 if (TARGET_E500_DOUBLE)
5807 if (!REG_P (operands[1]))
5808 operands[1] = force_reg (SImode, operands[1]);
5809 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5812 else if (TARGET_LFIWAX && TARGET_FCFID)
5814 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5817 else if (TARGET_FCFID)
5819 rtx dreg = operands[1];
5821 dreg = force_reg (SImode, dreg);
5822 dreg = convert_to_mode (DImode, dreg, false);
5823 emit_insn (gen_floatdidf2 (operands[0], dreg));
5827 if (!REG_P (operands[1]))
5828 operands[1] = force_reg (SImode, operands[1]);
5829 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5830 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5831 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5832 operands[5] = gen_reg_rtx (DFmode);
5833 operands[6] = gen_reg_rtx (SImode);
5836 (define_insn_and_split "*floatsidf2_internal"
5837 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5838 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5839 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5840 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5841 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5842 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5843 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5844 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5850 rtx lowword, highword;
5851 gcc_assert (MEM_P (operands[4]));
5852 highword = adjust_address (operands[4], SImode, 0);
5853 lowword = adjust_address (operands[4], SImode, 4);
5854 if (! WORDS_BIG_ENDIAN)
5857 tmp = highword; highword = lowword; lowword = tmp;
5860 emit_insn (gen_xorsi3 (operands[6], operands[1],
5861 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5862 emit_move_insn (lowword, operands[6]);
5863 emit_move_insn (highword, operands[2]);
5864 emit_move_insn (operands[5], operands[4]);
5865 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5868 [(set_attr "length" "24")
5869 (set_attr "type" "fp")])
5871 ;; If we don't have a direct conversion to single precision, don't enable this
5872 ;; conversion for 32-bit without fast math, because we don't have the insn to
5873 ;; generate the fixup swizzle to avoid double rounding problems.
5874 (define_expand "floatunssisf2"
5875 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5876 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5877 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5880 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5881 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5882 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5887 if (!REG_P (operands[1]))
5888 operands[1] = force_reg (SImode, operands[1]);
5890 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5892 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5897 rtx dreg = operands[1];
5899 dreg = force_reg (SImode, dreg);
5900 dreg = convert_to_mode (DImode, dreg, true);
5901 emit_insn (gen_floatdisf2 (operands[0], dreg));
5906 (define_expand "floatunssidf2"
5907 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5908 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5911 (clobber (match_dup 4))
5912 (clobber (match_dup 5))])]
5914 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5917 if (TARGET_E500_DOUBLE)
5919 if (!REG_P (operands[1]))
5920 operands[1] = force_reg (SImode, operands[1]);
5921 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5924 else if (TARGET_LFIWZX && TARGET_FCFID)
5926 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5929 else if (TARGET_FCFID)
5931 rtx dreg = operands[1];
5933 dreg = force_reg (SImode, dreg);
5934 dreg = convert_to_mode (DImode, dreg, true);
5935 emit_insn (gen_floatdidf2 (operands[0], dreg));
5939 if (!REG_P (operands[1]))
5940 operands[1] = force_reg (SImode, operands[1]);
5941 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5942 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5943 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5944 operands[5] = gen_reg_rtx (DFmode);
5947 (define_insn_and_split "*floatunssidf2_internal"
5948 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5949 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5950 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5951 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5952 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5953 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5954 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5955 && !(TARGET_FCFID && TARGET_POWERPC64)"
5961 rtx lowword, highword;
5962 gcc_assert (MEM_P (operands[4]));
5963 highword = adjust_address (operands[4], SImode, 0);
5964 lowword = adjust_address (operands[4], SImode, 4);
5965 if (! WORDS_BIG_ENDIAN)
5968 tmp = highword; highword = lowword; lowword = tmp;
5971 emit_move_insn (lowword, operands[1]);
5972 emit_move_insn (highword, operands[2]);
5973 emit_move_insn (operands[5], operands[4]);
5974 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5977 [(set_attr "length" "20")
5978 (set_attr "type" "fp")])
5980 (define_expand "fix_trunc<mode>si2"
5981 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5982 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5983 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5986 if (!<E500_CONVERT>)
5991 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5994 tmp = gen_reg_rtx (DImode);
5995 stack = rs6000_allocate_stack_temp (DImode, true, false);
5996 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6003 ; Like the convert to float patterns, this insn must be split before
6004 ; register allocation so that it can allocate the memory slot if it
6006 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6007 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6008 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6009 (clobber (match_scratch:DI 2 "=d"))]
6010 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6011 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6012 && TARGET_STFIWX && can_create_pseudo_p ()"
6017 rtx dest = operands[0];
6018 rtx src = operands[1];
6019 rtx tmp = operands[2];
6021 if (GET_CODE (tmp) == SCRATCH)
6022 tmp = gen_reg_rtx (DImode);
6024 emit_insn (gen_fctiwz_<mode> (tmp, src));
6027 dest = rs6000_address_for_fpconvert (dest);
6028 emit_insn (gen_stfiwx (dest, tmp));
6031 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6033 dest = gen_lowpart (DImode, dest);
6034 emit_move_insn (dest, tmp);
6039 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6040 emit_insn (gen_stfiwx (stack, tmp));
6041 emit_move_insn (dest, stack);
6045 [(set_attr "length" "12")
6046 (set_attr "type" "fp")])
6048 (define_insn_and_split "fix_trunc<mode>si2_internal"
6049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6050 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6051 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6052 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6053 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6060 gcc_assert (MEM_P (operands[3]));
6061 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6063 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6064 emit_move_insn (operands[3], operands[2]);
6065 emit_move_insn (operands[0], lowword);
6068 [(set_attr "length" "16")
6069 (set_attr "type" "fp")])
6071 (define_expand "fix_trunc<mode>di2"
6072 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6073 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6074 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6078 (define_insn "*fix_trunc<mode>di2_fctidz"
6079 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6080 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6081 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6082 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6084 [(set_attr "type" "fp")])
6086 (define_expand "fixuns_trunc<mode>si2"
6087 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6088 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6090 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6094 if (!<E500_CONVERT>)
6096 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6101 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6102 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6103 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6104 (clobber (match_scratch:DI 2 "=d"))]
6105 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6106 && TARGET_STFIWX && can_create_pseudo_p ()"
6111 rtx dest = operands[0];
6112 rtx src = operands[1];
6113 rtx tmp = operands[2];
6115 if (GET_CODE (tmp) == SCRATCH)
6116 tmp = gen_reg_rtx (DImode);
6118 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6121 dest = rs6000_address_for_fpconvert (dest);
6122 emit_insn (gen_stfiwx (dest, tmp));
6125 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6127 dest = gen_lowpart (DImode, dest);
6128 emit_move_insn (dest, tmp);
6133 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6134 emit_insn (gen_stfiwx (stack, tmp));
6135 emit_move_insn (dest, stack);
6139 [(set_attr "length" "12")
6140 (set_attr "type" "fp")])
6142 (define_expand "fixuns_trunc<mode>di2"
6143 [(set (match_operand:DI 0 "register_operand" "")
6144 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6145 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6148 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6149 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6150 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6151 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6152 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6154 [(set_attr "type" "fp")])
6156 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6157 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6158 ; because the first makes it clear that operand 0 is not live
6159 ; before the instruction.
6160 (define_insn "fctiwz_<mode>"
6161 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6162 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6164 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6166 [(set_attr "type" "fp")])
6168 (define_insn "fctiwuz_<mode>"
6169 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6170 (unspec:DI [(unsigned_fix:SI
6171 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6173 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6175 [(set_attr "type" "fp")])
6177 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6178 ;; since the friz instruction does not truncate the value if the floating
6179 ;; point value is < LONG_MIN or > LONG_MAX.
6180 (define_insn "*friz"
6181 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6182 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6183 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6184 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6185 && !flag_trapping_math && TARGET_FRIZ"
6187 [(set_attr "type" "fp")])
6189 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6190 ;; load to properly sign extend the value, but at least doing a store, load
6191 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6192 ;; if we have 32-bit memory ops
6193 (define_insn_and_split "*round32<mode>2_fprs"
6194 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6196 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6197 (clobber (match_scratch:DI 2 "=d"))
6198 (clobber (match_scratch:DI 3 "=d"))]
6199 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6200 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6201 && can_create_pseudo_p ()"
6206 rtx dest = operands[0];
6207 rtx src = operands[1];
6208 rtx tmp1 = operands[2];
6209 rtx tmp2 = operands[3];
6210 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6212 if (GET_CODE (tmp1) == SCRATCH)
6213 tmp1 = gen_reg_rtx (DImode);
6214 if (GET_CODE (tmp2) == SCRATCH)
6215 tmp2 = gen_reg_rtx (DImode);
6217 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6218 emit_insn (gen_stfiwx (stack, tmp1));
6219 emit_insn (gen_lfiwax (tmp2, stack));
6220 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6223 [(set_attr "type" "fpload")
6224 (set_attr "length" "16")])
6226 (define_insn_and_split "*roundu32<mode>2_fprs"
6227 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6228 (unsigned_float:SFDF
6229 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6230 (clobber (match_scratch:DI 2 "=d"))
6231 (clobber (match_scratch:DI 3 "=d"))]
6232 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6233 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6234 && can_create_pseudo_p ()"
6239 rtx dest = operands[0];
6240 rtx src = operands[1];
6241 rtx tmp1 = operands[2];
6242 rtx tmp2 = operands[3];
6243 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6245 if (GET_CODE (tmp1) == SCRATCH)
6246 tmp1 = gen_reg_rtx (DImode);
6247 if (GET_CODE (tmp2) == SCRATCH)
6248 tmp2 = gen_reg_rtx (DImode);
6250 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6251 emit_insn (gen_stfiwx (stack, tmp1));
6252 emit_insn (gen_lfiwzx (tmp2, stack));
6253 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6256 [(set_attr "type" "fpload")
6257 (set_attr "length" "16")])
6259 ;; No VSX equivalent to fctid
6260 (define_insn "lrint<mode>di2"
6261 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6262 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6264 "TARGET_<MODE>_FPR && TARGET_FPRND"
6266 [(set_attr "type" "fp")])
6268 (define_insn "btrunc<mode>2"
6269 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6270 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6272 "TARGET_<MODE>_FPR && TARGET_FPRND"
6276 [(set_attr "type" "fp")
6277 (set_attr "fp_type" "fp_addsub_<Fs>")])
6279 (define_insn "ceil<mode>2"
6280 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6281 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6283 "TARGET_<MODE>_FPR && TARGET_FPRND"
6287 [(set_attr "type" "fp")
6288 (set_attr "fp_type" "fp_addsub_<Fs>")])
6290 (define_insn "floor<mode>2"
6291 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6292 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6294 "TARGET_<MODE>_FPR && TARGET_FPRND"
6298 [(set_attr "type" "fp")
6299 (set_attr "fp_type" "fp_addsub_<Fs>")])
6301 ;; No VSX equivalent to frin
6302 (define_insn "round<mode>2"
6303 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6304 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6306 "TARGET_<MODE>_FPR && TARGET_FPRND"
6308 [(set_attr "type" "fp")
6309 (set_attr "fp_type" "fp_addsub_<Fs>")])
6311 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6312 (define_insn "stfiwx"
6313 [(set (match_operand:SI 0 "memory_operand" "=Z")
6314 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6318 [(set_attr "type" "fpstore")])
6320 ;; If we don't have a direct conversion to single precision, don't enable this
6321 ;; conversion for 32-bit without fast math, because we don't have the insn to
6322 ;; generate the fixup swizzle to avoid double rounding problems.
6323 (define_expand "floatsisf2"
6324 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6325 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6326 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6329 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6330 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6331 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6336 if (!REG_P (operands[1]))
6337 operands[1] = force_reg (SImode, operands[1]);
6339 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6341 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6344 else if (TARGET_FCFID && TARGET_LFIWAX)
6346 rtx dfreg = gen_reg_rtx (DFmode);
6347 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6348 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6353 rtx dreg = operands[1];
6355 dreg = force_reg (SImode, dreg);
6356 dreg = convert_to_mode (DImode, dreg, false);
6357 emit_insn (gen_floatdisf2 (operands[0], dreg));
6362 (define_expand "floatdidf2"
6363 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6364 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6365 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6368 (define_insn "*floatdidf2_fpr"
6369 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6370 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6371 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6372 && !VECTOR_UNIT_VSX_P (DFmode)"
6374 [(set_attr "type" "fp")])
6376 ; Allow the combiner to merge source memory operands to the conversion so that
6377 ; the optimizer/register allocator doesn't try to load the value too early in a
6378 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6379 ; hit. We will split after reload to avoid the trip through the GPRs
6381 (define_insn_and_split "*floatdidf2_mem"
6382 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6383 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6384 (clobber (match_scratch:DI 2 "=d"))]
6385 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6387 "&& reload_completed"
6388 [(set (match_dup 2) (match_dup 1))
6389 (set (match_dup 0) (float:DF (match_dup 2)))]
6391 [(set_attr "length" "8")
6392 (set_attr "type" "fpload")])
6394 (define_expand "floatunsdidf2"
6395 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6397 (match_operand:DI 1 "gpc_reg_operand" "")))]
6398 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6401 (define_insn "*floatunsdidf2_fcfidu"
6402 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6403 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6404 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6406 [(set_attr "type" "fp")
6407 (set_attr "length" "4")])
6409 (define_insn_and_split "*floatunsdidf2_mem"
6410 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6411 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6412 (clobber (match_scratch:DI 2 "=d"))]
6413 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6415 "&& reload_completed"
6416 [(set (match_dup 2) (match_dup 1))
6417 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6419 [(set_attr "length" "8")
6420 (set_attr "type" "fpload")])
6422 (define_expand "floatdisf2"
6423 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6424 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6425 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6426 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6431 rtx val = operands[1];
6432 if (!flag_unsafe_math_optimizations)
6434 rtx label = gen_label_rtx ();
6435 val = gen_reg_rtx (DImode);
6436 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6439 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6444 (define_insn "floatdisf2_fcfids"
6445 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6446 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6447 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6448 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6450 [(set_attr "type" "fp")])
6452 (define_insn_and_split "*floatdisf2_mem"
6453 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6454 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6455 (clobber (match_scratch:DI 2 "=f"))]
6456 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6457 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6459 "&& reload_completed"
6463 emit_move_insn (operands[2], operands[1]);
6464 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6467 [(set_attr "length" "8")])
6469 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6470 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6471 ;; from double rounding.
6472 ;; Instead of creating a new cpu type for two FP operations, just use fp
6473 (define_insn_and_split "floatdisf2_internal1"
6474 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6475 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6476 (clobber (match_scratch:DF 2 "=d"))]
6477 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6479 "&& reload_completed"
6481 (float:DF (match_dup 1)))
6483 (float_truncate:SF (match_dup 2)))]
6485 [(set_attr "length" "8")
6486 (set_attr "type" "fp")])
6488 ;; Twiddles bits to avoid double rounding.
6489 ;; Bits that might be truncated when converting to DFmode are replaced
6490 ;; by a bit that won't be lost at that stage, but is below the SFmode
6491 ;; rounding position.
6492 (define_expand "floatdisf2_internal2"
6493 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6495 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6497 (clobber (scratch:CC))])
6498 (set (match_dup 3) (plus:DI (match_dup 3)
6500 (set (match_dup 0) (plus:DI (match_dup 0)
6502 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6504 (set (match_dup 0) (ior:DI (match_dup 0)
6506 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6508 (clobber (scratch:CC))])
6509 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6510 (label_ref (match_operand:DI 2 "" ""))
6512 (set (match_dup 0) (match_dup 1))]
6513 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6516 operands[3] = gen_reg_rtx (DImode);
6517 operands[4] = gen_reg_rtx (CCUNSmode);
6520 (define_expand "floatunsdisf2"
6521 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6522 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6523 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6524 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6527 (define_insn "floatunsdisf2_fcfidus"
6528 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6529 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6530 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6531 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6533 [(set_attr "type" "fp")])
6535 (define_insn_and_split "*floatunsdisf2_mem"
6536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6537 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6538 (clobber (match_scratch:DI 2 "=f"))]
6539 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6540 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6542 "&& reload_completed"
6546 emit_move_insn (operands[2], operands[1]);
6547 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6550 [(set_attr "length" "8")
6551 (set_attr "type" "fpload")])
6553 ;; Define the TImode operations that can be done in a small number
6554 ;; of instructions. The & constraints are to prevent the register
6555 ;; allocator from allocating registers that overlap with the inputs
6556 ;; (for example, having an input in 7,8 and an output in 6,7). We
6557 ;; also allow for the output being the same as one of the inputs.
6559 (define_insn "addti3"
6560 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6561 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6562 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6565 if (WORDS_BIG_ENDIAN)
6566 return (GET_CODE (operands[2])) != CONST_INT
6567 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6568 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6570 return (GET_CODE (operands[2])) != CONST_INT
6571 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6572 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6574 [(set_attr "type" "two")
6575 (set_attr "length" "8")])
6577 (define_insn "subti3"
6578 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6579 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6580 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6583 if (WORDS_BIG_ENDIAN)
6584 return (GET_CODE (operands[1]) != CONST_INT)
6585 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6586 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6588 return (GET_CODE (operands[1]) != CONST_INT)
6589 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6590 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6592 [(set_attr "type" "two")
6593 (set_attr "length" "8")])
6596 ;; Define the DImode operations that can be done in a small number
6597 ;; of instructions. The & constraints are to prevent the register
6598 ;; allocator from allocating registers that overlap with the inputs
6599 ;; (for example, having an input in 7,8 and an output in 6,7). We
6600 ;; also allow for the output being the same as one of the inputs.
6602 (define_insn "*adddi3_noppc64"
6603 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6604 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6605 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6606 "! TARGET_POWERPC64"
6609 if (WORDS_BIG_ENDIAN)
6610 return (GET_CODE (operands[2])) != CONST_INT
6611 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6612 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6614 return (GET_CODE (operands[2])) != CONST_INT
6615 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6616 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6618 [(set_attr "type" "two")
6619 (set_attr "length" "8")])
6621 (define_insn "*subdi3_noppc64"
6622 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6623 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6624 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6625 "! TARGET_POWERPC64"
6628 if (WORDS_BIG_ENDIAN)
6629 return (GET_CODE (operands[1]) != CONST_INT)
6630 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6631 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6633 return (GET_CODE (operands[1]) != CONST_INT)
6634 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6635 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6637 [(set_attr "type" "two")
6638 (set_attr "length" "8")])
6640 (define_insn "*negdi2_noppc64"
6641 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6642 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6643 "! TARGET_POWERPC64"
6646 return (WORDS_BIG_ENDIAN)
6647 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6648 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6650 [(set_attr "type" "two")
6651 (set_attr "length" "8")])
6653 (define_insn "mulsidi3"
6654 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6655 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6656 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6657 "! TARGET_POWERPC64"
6659 return (WORDS_BIG_ENDIAN)
6660 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6661 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6663 [(set_attr "type" "mul")
6664 (set_attr "length" "8")])
6667 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6668 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6669 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6670 "! TARGET_POWERPC64 && reload_completed"
6673 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6674 (sign_extend:DI (match_dup 2)))
6677 (mult:SI (match_dup 1)
6681 int endian = (WORDS_BIG_ENDIAN == 0);
6682 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6683 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6686 (define_insn "umulsidi3"
6687 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6688 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6689 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6690 "! TARGET_POWERPC64"
6693 return (WORDS_BIG_ENDIAN)
6694 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6695 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6697 [(set_attr "type" "mul")
6698 (set_attr "length" "8")])
6701 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6702 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6703 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6704 "! TARGET_POWERPC64 && reload_completed"
6707 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6708 (zero_extend:DI (match_dup 2)))
6711 (mult:SI (match_dup 1)
6715 int endian = (WORDS_BIG_ENDIAN == 0);
6716 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6717 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6720 (define_insn "smulsi3_highpart"
6721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6723 (lshiftrt:DI (mult:DI (sign_extend:DI
6724 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6726 (match_operand:SI 2 "gpc_reg_operand" "r")))
6730 [(set_attr "type" "mul")])
6732 (define_insn "umulsi3_highpart"
6733 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6735 (lshiftrt:DI (mult:DI (zero_extend:DI
6736 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6738 (match_operand:SI 2 "gpc_reg_operand" "r")))
6742 [(set_attr "type" "mul")])
6744 ;; Shift by a variable amount is too complex to be worth open-coding. We
6745 ;; just handle shifts by constants.
6746 (define_insn "ashrdi3_no_power"
6747 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6748 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6749 (match_operand:SI 2 "const_int_operand" "M,i")))]
6753 switch (which_alternative)
6758 if (WORDS_BIG_ENDIAN)
6759 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6761 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6763 if (WORDS_BIG_ENDIAN)
6764 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6766 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6769 [(set_attr "type" "two,three")
6770 (set_attr "length" "8,12")])
6772 (define_insn "*ashrdisi3_noppc64be"
6773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6774 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6775 (const_int 32)) 4))]
6776 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6779 if (REGNO (operands[0]) == REGNO (operands[1]))
6782 return \"mr %0,%1\";
6784 [(set_attr "length" "4")])
6787 ;; PowerPC64 DImode operations.
6789 (define_insn "muldi3"
6790 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6791 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6792 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6797 [(set_attr "type" "mul")
6799 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6801 (match_operand:SI 2 "short_cint_operand" "")
6802 (const_string "16")]
6803 (const_string "64")))])
6805 (define_insn "*muldi3_internal1"
6806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6807 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6808 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6810 (clobber (match_scratch:DI 3 "=r,r"))]
6815 [(set_attr "type" "mul")
6816 (set_attr "size" "64")
6817 (set_attr "dot" "yes")
6818 (set_attr "length" "4,8")])
6821 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6822 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6823 (match_operand:DI 2 "gpc_reg_operand" ""))
6825 (clobber (match_scratch:DI 3 ""))]
6826 "TARGET_POWERPC64 && reload_completed"
6828 (mult:DI (match_dup 1) (match_dup 2)))
6830 (compare:CC (match_dup 3)
6834 (define_insn "*muldi3_internal2"
6835 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6836 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6837 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6839 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6840 (mult:DI (match_dup 1) (match_dup 2)))]
6845 [(set_attr "type" "mul")
6846 (set_attr "size" "64")
6847 (set_attr "dot" "yes")
6848 (set_attr "length" "4,8")])
6851 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6852 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6853 (match_operand:DI 2 "gpc_reg_operand" ""))
6855 (set (match_operand:DI 0 "gpc_reg_operand" "")
6856 (mult:DI (match_dup 1) (match_dup 2)))]
6857 "TARGET_POWERPC64 && reload_completed"
6859 (mult:DI (match_dup 1) (match_dup 2)))
6861 (compare:CC (match_dup 0)
6865 (define_insn "smuldi3_highpart"
6866 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6868 (lshiftrt:TI (mult:TI (sign_extend:TI
6869 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6871 (match_operand:DI 2 "gpc_reg_operand" "r")))
6875 [(set_attr "type" "mul")
6876 (set_attr "size" "64")])
6878 (define_insn "umuldi3_highpart"
6879 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6881 (lshiftrt:TI (mult:TI (zero_extend:TI
6882 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6884 (match_operand:DI 2 "gpc_reg_operand" "r")))
6888 [(set_attr "type" "mul")
6889 (set_attr "size" "64")])
6891 (define_expand "mulditi3"
6892 [(set (match_operand:TI 0 "gpc_reg_operand")
6893 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6894 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6897 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6898 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6899 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6900 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6901 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6905 (define_expand "umulditi3"
6906 [(set (match_operand:TI 0 "gpc_reg_operand")
6907 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6908 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6911 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6912 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6913 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6914 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6915 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6919 (define_insn "*rotldi3_internal4"
6920 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6921 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6922 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6923 (match_operand:DI 3 "mask64_operand" "n")))]
6925 "rld%I2c%B3 %0,%1,%H2,%S3"
6926 [(set_attr "type" "shift")
6927 (set_attr "maybe_var_shift" "yes")])
6929 (define_insn "*rotldi3_internal5"
6930 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6932 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6933 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6934 (match_operand:DI 3 "mask64_operand" "n,n"))
6936 (clobber (match_scratch:DI 4 "=r,r"))]
6939 rld%I2c%B3. %4,%1,%H2,%S3
6941 [(set_attr "type" "shift")
6942 (set_attr "maybe_var_shift" "yes")
6943 (set_attr "dot" "yes")
6944 (set_attr "length" "4,8")])
6947 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6949 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6950 (match_operand:DI 2 "reg_or_cint_operand" ""))
6951 (match_operand:DI 3 "mask64_operand" ""))
6953 (clobber (match_scratch:DI 4 ""))]
6954 "TARGET_POWERPC64 && reload_completed"
6956 (and:DI (rotate:DI (match_dup 1)
6960 (compare:CC (match_dup 4)
6964 (define_insn "*rotldi3_internal6"
6965 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6967 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6968 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6969 (match_operand:DI 3 "mask64_operand" "n,n"))
6971 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6972 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6975 rld%I2c%B3. %0,%1,%H2,%S3
6977 [(set_attr "type" "shift")
6978 (set_attr "maybe_var_shift" "yes")
6979 (set_attr "dot" "yes")
6980 (set_attr "length" "4,8")])
6983 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6985 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:DI 2 "reg_or_cint_operand" ""))
6987 (match_operand:DI 3 "mask64_operand" ""))
6989 (set (match_operand:DI 0 "gpc_reg_operand" "")
6990 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6991 "TARGET_POWERPC64 && reload_completed"
6993 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6995 (compare:CC (match_dup 0)
6999 (define_insn "*rotldi3_internal7le"
7000 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7003 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7004 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
7005 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7006 "rld%I2cl %0,%1,%H2,56"
7007 [(set_attr "type" "shift")
7008 (set_attr "maybe_var_shift" "yes")])
7010 (define_insn "*rotldi3_internal7be"
7011 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7014 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7015 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
7016 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7017 "rld%I2cl %0,%1,%H2,56"
7018 [(set_attr "type" "shift")
7019 (set_attr "maybe_var_shift" "yes")])
7021 (define_insn "*rotldi3_internal8le"
7022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7023 (compare:CC (zero_extend:DI
7025 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7026 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7028 (clobber (match_scratch:DI 3 "=r,r"))]
7029 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7031 rld%I2cl. %3,%1,%H2,56
7033 [(set_attr "type" "shift")
7034 (set_attr "maybe_var_shift" "yes")
7035 (set_attr "dot" "yes")
7036 (set_attr "length" "4,8")])
7038 (define_insn "*rotldi3_internal8be"
7039 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7040 (compare:CC (zero_extend:DI
7042 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7043 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
7045 (clobber (match_scratch:DI 3 "=r,r"))]
7046 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7048 rld%I2cl. %3,%1,%H2,56
7050 [(set_attr "type" "shift")
7051 (set_attr "maybe_var_shift" "yes")
7052 (set_attr "dot" "yes")
7053 (set_attr "length" "4,8")])
7056 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7057 (compare:CC (zero_extend:DI
7059 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7060 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7062 (clobber (match_scratch:DI 3 ""))]
7063 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7065 (zero_extend:DI (subreg:QI
7066 (rotate:DI (match_dup 1)
7069 (compare:CC (match_dup 3)
7074 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7075 (compare:CC (zero_extend:DI
7077 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7080 (clobber (match_scratch:DI 3 ""))]
7081 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7083 (zero_extend:DI (subreg:QI
7084 (rotate:DI (match_dup 1)
7087 (compare:CC (match_dup 3)
7091 (define_insn "*rotldi3_internal9le"
7092 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7093 (compare:CC (zero_extend:DI
7095 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7096 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7098 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7099 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7100 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7102 rld%I2cl. %0,%1,%H2,56
7104 [(set_attr "type" "shift")
7105 (set_attr "maybe_var_shift" "yes")
7106 (set_attr "dot" "yes")
7107 (set_attr "length" "4,8")])
7109 (define_insn "*rotldi3_internal9be"
7110 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7111 (compare:CC (zero_extend:DI
7113 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7114 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
7116 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7117 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7118 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7120 rld%I2cl. %0,%1,%H2,56
7122 [(set_attr "type" "shift")
7123 (set_attr "maybe_var_shift" "yes")
7124 (set_attr "dot" "yes")
7125 (set_attr "length" "4,8")])
7128 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7129 (compare:CC (zero_extend:DI
7131 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7132 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7134 (set (match_operand:DI 0 "gpc_reg_operand" "")
7135 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7136 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7138 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7140 (compare:CC (match_dup 0)
7145 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7146 (compare:CC (zero_extend:DI
7148 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7149 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7151 (set (match_operand:DI 0 "gpc_reg_operand" "")
7152 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7153 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7155 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7157 (compare:CC (match_dup 0)
7161 (define_insn "*rotldi3_internal10le"
7162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7165 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7166 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
7167 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7168 "rld%I2cl %0,%1,%H2,48"
7169 [(set_attr "type" "shift")
7170 (set_attr "maybe_var_shift" "yes")])
7172 (define_insn "*rotldi3_internal10be"
7173 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7176 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7177 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
7178 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7179 "rld%I2cl %0,%1,%H2,48"
7180 [(set_attr "type" "shift")
7181 (set_attr "maybe_var_shift" "yes")])
7183 (define_insn "*rotldi3_internal11le"
7184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7185 (compare:CC (zero_extend:DI
7187 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7188 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7190 (clobber (match_scratch:DI 3 "=r,r"))]
7191 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7193 rld%I2cl. %3,%1,%H2,48
7195 [(set_attr "type" "shift")
7196 (set_attr "maybe_var_shift" "yes")
7197 (set_attr "dot" "yes")
7198 (set_attr "length" "4,8")])
7200 (define_insn "*rotldi3_internal11be"
7201 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7202 (compare:CC (zero_extend:DI
7204 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7205 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
7207 (clobber (match_scratch:DI 3 "=r,r"))]
7208 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7210 rld%I2cl. %3,%1,%H2,48
7212 [(set_attr "type" "shift")
7213 (set_attr "maybe_var_shift" "yes")
7214 (set_attr "dot" "yes")
7215 (set_attr "length" "4,8")])
7218 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7219 (compare:CC (zero_extend:DI
7221 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7222 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7224 (clobber (match_scratch:DI 3 ""))]
7225 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7227 (zero_extend:DI (subreg:HI
7228 (rotate:DI (match_dup 1)
7231 (compare:CC (match_dup 3)
7236 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7237 (compare:CC (zero_extend:DI
7239 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7240 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7242 (clobber (match_scratch:DI 3 ""))]
7243 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7245 (zero_extend:DI (subreg:HI
7246 (rotate:DI (match_dup 1)
7249 (compare:CC (match_dup 3)
7253 (define_insn "*rotldi3_internal12le"
7254 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7255 (compare:CC (zero_extend:DI
7257 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7258 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7260 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7261 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7262 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7264 rld%I2cl. %0,%1,%H2,48
7266 [(set_attr "type" "shift")
7267 (set_attr "maybe_var_shift" "yes")
7268 (set_attr "dot" "yes")
7269 (set_attr "length" "4,8")])
7271 (define_insn "*rotldi3_internal12be"
7272 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7273 (compare:CC (zero_extend:DI
7275 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7276 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
7278 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7279 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7280 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7282 rld%I2cl. %0,%1,%H2,48
7284 [(set_attr "type" "shift")
7285 (set_attr "maybe_var_shift" "yes")
7286 (set_attr "dot" "yes")
7287 (set_attr "length" "4,8")])
7290 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7291 (compare:CC (zero_extend:DI
7293 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7294 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7296 (set (match_operand:DI 0 "gpc_reg_operand" "")
7297 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7298 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7300 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7302 (compare:CC (match_dup 0)
7307 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7308 (compare:CC (zero_extend:DI
7310 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7311 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7313 (set (match_operand:DI 0 "gpc_reg_operand" "")
7314 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7315 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7317 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7319 (compare:CC (match_dup 0)
7323 (define_insn "*rotldi3_internal13le"
7324 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7327 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7328 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
7329 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7330 "rld%I2cl %0,%1,%H2,32"
7331 [(set_attr "type" "shift")
7332 (set_attr "maybe_var_shift" "yes")])
7334 (define_insn "*rotldi3_internal13be"
7335 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7338 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7339 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
7340 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7341 "rld%I2cl %0,%1,%H2,32"
7342 [(set_attr "type" "shift")
7343 (set_attr "maybe_var_shift" "yes")])
7345 (define_insn "*rotldi3_internal14le"
7346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7347 (compare:CC (zero_extend:DI
7349 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7350 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7352 (clobber (match_scratch:DI 3 "=r,r"))]
7353 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7355 rld%I2cl. %3,%1,%H2,32
7357 [(set_attr "type" "shift")
7358 (set_attr "maybe_var_shift" "yes")
7359 (set_attr "dot" "yes")
7360 (set_attr "length" "4,8")])
7362 (define_insn "*rotldi3_internal14be"
7363 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7364 (compare:CC (zero_extend:DI
7366 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7367 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
7369 (clobber (match_scratch:DI 3 "=r,r"))]
7370 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7372 rld%I2cl. %3,%1,%H2,32
7374 [(set_attr "type" "shift")
7375 (set_attr "maybe_var_shift" "yes")
7376 (set_attr "dot" "yes")
7377 (set_attr "length" "4,8")])
7380 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7381 (compare:CC (zero_extend:DI
7383 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7384 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7386 (clobber (match_scratch:DI 3 ""))]
7387 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7389 (zero_extend:DI (subreg:SI
7390 (rotate:DI (match_dup 1)
7393 (compare:CC (match_dup 3)
7398 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7399 (compare:CC (zero_extend:DI
7401 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7402 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7404 (clobber (match_scratch:DI 3 ""))]
7405 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7407 (zero_extend:DI (subreg:SI
7408 (rotate:DI (match_dup 1)
7411 (compare:CC (match_dup 3)
7415 (define_insn "*rotldi3_internal15le"
7416 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7417 (compare:CC (zero_extend:DI
7419 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7420 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7422 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7423 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7424 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7426 rld%I2cl. %0,%1,%H2,32
7428 [(set_attr "type" "shift")
7429 (set_attr "maybe_var_shift" "yes")
7430 (set_attr "dot" "yes")
7431 (set_attr "length" "4,8")])
7433 (define_insn "*rotldi3_internal15be"
7434 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7435 (compare:CC (zero_extend:DI
7437 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7438 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
7440 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7441 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7442 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7444 rld%I2cl. %0,%1,%H2,32
7446 [(set_attr "type" "shift")
7447 (set_attr "maybe_var_shift" "yes")
7448 (set_attr "dot" "yes")
7449 (set_attr "length" "4,8")])
7452 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7453 (compare:CC (zero_extend:DI
7455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7456 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7458 (set (match_operand:DI 0 "gpc_reg_operand" "")
7459 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7460 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7462 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7464 (compare:CC (match_dup 0)
7469 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7470 (compare:CC (zero_extend:DI
7472 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7473 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7475 (set (match_operand:DI 0 "gpc_reg_operand" "")
7476 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7477 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7479 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7481 (compare:CC (match_dup 0)
7485 (define_insn "*ashldi3_internal4"
7486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7487 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7488 (match_operand:SI 2 "const_int_operand" "i"))
7489 (match_operand:DI 3 "const_int_operand" "n")))]
7490 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7491 "rldic %0,%1,%H2,%W3"
7492 [(set_attr "type" "shift")])
7494 (define_insn "ashldi3_internal5"
7495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7497 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7498 (match_operand:SI 2 "const_int_operand" "i,i"))
7499 (match_operand:DI 3 "const_int_operand" "n,n"))
7501 (clobber (match_scratch:DI 4 "=r,r"))]
7502 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7504 rldic. %4,%1,%H2,%W3
7506 [(set_attr "type" "shift")
7507 (set_attr "dot" "yes")
7508 (set_attr "length" "4,8")])
7511 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7513 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7514 (match_operand:SI 2 "const_int_operand" ""))
7515 (match_operand:DI 3 "const_int_operand" ""))
7517 (clobber (match_scratch:DI 4 ""))]
7518 "TARGET_POWERPC64 && reload_completed
7519 && includes_rldic_lshift_p (operands[2], operands[3])"
7521 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7524 (compare:CC (match_dup 4)
7528 (define_insn "*ashldi3_internal6"
7529 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7531 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7532 (match_operand:SI 2 "const_int_operand" "i,i"))
7533 (match_operand:DI 3 "const_int_operand" "n,n"))
7535 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7536 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7537 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7539 rldic. %0,%1,%H2,%W3
7541 [(set_attr "type" "shift")
7542 (set_attr "dot" "yes")
7543 (set_attr "length" "4,8")])
7546 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7548 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7549 (match_operand:SI 2 "const_int_operand" ""))
7550 (match_operand:DI 3 "const_int_operand" ""))
7552 (set (match_operand:DI 0 "gpc_reg_operand" "")
7553 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7554 "TARGET_POWERPC64 && reload_completed
7555 && includes_rldic_lshift_p (operands[2], operands[3])"
7557 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7560 (compare:CC (match_dup 0)
7564 (define_insn "*ashldi3_internal7"
7565 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7566 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7567 (match_operand:SI 2 "const_int_operand" "i"))
7568 (match_operand:DI 3 "mask64_operand" "n")))]
7569 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7570 "rldicr %0,%1,%H2,%S3"
7571 [(set_attr "type" "shift")])
7573 (define_insn "ashldi3_internal8"
7574 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7576 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7577 (match_operand:SI 2 "const_int_operand" "i,i"))
7578 (match_operand:DI 3 "mask64_operand" "n,n"))
7580 (clobber (match_scratch:DI 4 "=r,r"))]
7581 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7583 rldicr. %4,%1,%H2,%S3
7585 [(set_attr "type" "shift")
7586 (set_attr "dot" "yes")
7587 (set_attr "length" "4,8")])
7590 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7592 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7593 (match_operand:SI 2 "const_int_operand" ""))
7594 (match_operand:DI 3 "mask64_operand" ""))
7596 (clobber (match_scratch:DI 4 ""))]
7597 "TARGET_POWERPC64 && reload_completed
7598 && includes_rldicr_lshift_p (operands[2], operands[3])"
7600 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7603 (compare:CC (match_dup 4)
7607 (define_insn "*ashldi3_internal9"
7608 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7610 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7611 (match_operand:SI 2 "const_int_operand" "i,i"))
7612 (match_operand:DI 3 "mask64_operand" "n,n"))
7614 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7615 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7616 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7618 rldicr. %0,%1,%H2,%S3
7620 [(set_attr "type" "shift")
7621 (set_attr "dot" "yes")
7622 (set_attr "length" "4,8")])
7625 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7627 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7628 (match_operand:SI 2 "const_int_operand" ""))
7629 (match_operand:DI 3 "mask64_operand" ""))
7631 (set (match_operand:DI 0 "gpc_reg_operand" "")
7632 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7633 "TARGET_POWERPC64 && reload_completed
7634 && includes_rldicr_lshift_p (operands[2], operands[3])"
7636 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7639 (compare:CC (match_dup 0)
7643 (define_expand "anddi3"
7645 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7646 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7647 (match_operand:DI 2 "reg_or_cint_operand" "")))
7648 (clobber (match_scratch:CC 3 ""))])]
7651 if (!TARGET_POWERPC64)
7653 rtx cc = gen_rtx_SCRATCH (CCmode);
7654 rs6000_split_logical (operands, AND, false, false, false, cc);
7657 else if (!and64_2_operand (operands[2], DImode))
7658 operands[2] = force_reg (DImode, operands[2]);
7661 (define_insn "anddi3_mc"
7662 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7663 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7664 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7665 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7666 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7669 rldic%B2 %0,%1,0,%S2
7670 rlwinm %0,%1,0,%m2,%M2
7674 [(set_attr "type" "*,shift,shift,logical,logical,*")
7675 (set_attr "dot" "no,no,no,yes,yes,no")
7676 (set_attr "length" "4,4,4,4,4,8")])
7678 (define_insn "anddi3_nomc"
7679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7680 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7681 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7682 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7683 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7686 rldic%B2 %0,%1,0,%S2
7687 rlwinm %0,%1,0,%m2,%M2
7689 [(set_attr "type" "*,shift,shift,*")
7690 (set_attr "length" "4,4,4,8")])
7693 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7694 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7695 (match_operand:DI 2 "mask64_2_operand" "")))
7696 (clobber (match_scratch:CC 3 ""))]
7698 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7699 && !mask_operand (operands[2], DImode)
7700 && !mask64_operand (operands[2], DImode)"
7702 (and:DI (rotate:DI (match_dup 1)
7706 (and:DI (rotate:DI (match_dup 0)
7710 build_mask64_2_operands (operands[2], &operands[4]);
7713 (define_insn "*anddi3_internal2_mc"
7714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7715 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7716 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7718 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7719 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7720 "TARGET_64BIT && rs6000_gen_cell_microcode"
7723 rldic%B2. %3,%1,0,%S2
7724 rlwinm. %3,%1,0,%m2,%M2
7734 [(set_attr "type" "logical,shift,shift,logical,\
7735 logical,compare,compare,compare,compare,compare,\
7737 (set_attr "dot" "yes")
7738 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7741 [(set (match_operand:CC 0 "cc_reg_operand" "")
7742 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7743 (match_operand:DI 2 "mask64_2_operand" ""))
7745 (clobber (match_scratch:DI 3 ""))
7746 (clobber (match_scratch:CC 4 ""))]
7747 "TARGET_64BIT && reload_completed
7748 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7749 && !mask_operand (operands[2], DImode)
7750 && !mask64_operand (operands[2], DImode)"
7752 (and:DI (rotate:DI (match_dup 1)
7755 (parallel [(set (match_dup 0)
7756 (compare:CC (and:DI (rotate:DI (match_dup 3)
7760 (clobber (match_dup 3))])]
7763 build_mask64_2_operands (operands[2], &operands[5]);
7766 (define_insn "*anddi3_internal3_mc"
7767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7768 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7769 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7771 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7772 (and:DI (match_dup 1) (match_dup 2)))
7773 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7774 "TARGET_64BIT && rs6000_gen_cell_microcode"
7777 rldic%B2. %0,%1,0,%S2
7778 rlwinm. %0,%1,0,%m2,%M2
7788 [(set_attr "type" "logical,shift,shift,logical,\
7789 logical,compare,compare,compare,compare,compare,\
7791 (set_attr "dot" "yes")
7792 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7795 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7796 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7797 (match_operand:DI 2 "and64_2_operand" ""))
7799 (set (match_operand:DI 0 "gpc_reg_operand" "")
7800 (and:DI (match_dup 1) (match_dup 2)))
7801 (clobber (match_scratch:CC 4 ""))]
7802 "TARGET_64BIT && reload_completed"
7803 [(parallel [(set (match_dup 0)
7804 (and:DI (match_dup 1) (match_dup 2)))
7805 (clobber (match_dup 4))])
7807 (compare:CC (match_dup 0)
7812 [(set (match_operand:CC 3 "cc_reg_operand" "")
7813 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7814 (match_operand:DI 2 "mask64_2_operand" ""))
7816 (set (match_operand:DI 0 "gpc_reg_operand" "")
7817 (and:DI (match_dup 1) (match_dup 2)))
7818 (clobber (match_scratch:CC 4 ""))]
7819 "TARGET_64BIT && reload_completed
7820 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7821 && !mask_operand (operands[2], DImode)
7822 && !mask64_operand (operands[2], DImode)"
7824 (and:DI (rotate:DI (match_dup 1)
7827 (parallel [(set (match_dup 3)
7828 (compare:CC (and:DI (rotate:DI (match_dup 0)
7833 (and:DI (rotate:DI (match_dup 0)
7838 build_mask64_2_operands (operands[2], &operands[5]);
7841 (define_expand "iordi3"
7842 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7843 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7844 (match_operand:DI 2 "reg_or_cint_operand" "")))]
7847 if (!TARGET_POWERPC64)
7849 rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
7852 else if (!reg_or_logical_cint_operand (operands[2], DImode))
7853 operands[2] = force_reg (DImode, operands[2]);
7854 else if (non_logical_cint_operand (operands[2], DImode))
7856 HOST_WIDE_INT value;
7857 rtx tmp = ((!can_create_pseudo_p ()
7858 || rtx_equal_p (operands[0], operands[1]))
7859 ? operands[0] : gen_reg_rtx (DImode));
7861 value = INTVAL (operands[2]);
7862 emit_insn (gen_iordi3 (tmp, operands[1],
7863 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7865 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7870 (define_expand "xordi3"
7871 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7872 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7873 (match_operand:DI 2 "reg_or_cint_operand" "")))]
7876 if (!TARGET_POWERPC64)
7878 rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
7881 else if (!reg_or_logical_cint_operand (operands[2], DImode))
7882 operands[2] = force_reg (DImode, operands[2]);
7883 if (non_logical_cint_operand (operands[2], DImode))
7885 HOST_WIDE_INT value;
7886 rtx tmp = ((!can_create_pseudo_p ()
7887 || rtx_equal_p (operands[0], operands[1]))
7888 ? operands[0] : gen_reg_rtx (DImode));
7890 value = INTVAL (operands[2]);
7891 emit_insn (gen_xordi3 (tmp, operands[1],
7892 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7894 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7899 (define_insn "*booldi3_internal1"
7900 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7901 (match_operator:DI 3 "boolean_or_operator"
7902 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7903 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7910 (define_insn "*booldi3_internal2"
7911 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7912 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7913 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7914 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7916 (clobber (match_scratch:DI 3 "=r,r"))]
7921 [(set_attr "type" "logical,compare")
7922 (set_attr "dot" "yes")
7923 (set_attr "length" "4,8")])
7926 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7927 (compare:CC (match_operator:DI 4 "boolean_operator"
7928 [(match_operand:DI 1 "gpc_reg_operand" "")
7929 (match_operand:DI 2 "gpc_reg_operand" "")])
7931 (clobber (match_scratch:DI 3 ""))]
7932 "TARGET_POWERPC64 && reload_completed"
7933 [(set (match_dup 3) (match_dup 4))
7935 (compare:CC (match_dup 3)
7939 (define_insn "*booldi3_internal3"
7940 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7941 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7942 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7943 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7945 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7951 [(set_attr "type" "logical,compare")
7952 (set_attr "dot" "yes")
7953 (set_attr "length" "4,8")])
7956 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7957 (compare:CC (match_operator:DI 4 "boolean_operator"
7958 [(match_operand:DI 1 "gpc_reg_operand" "")
7959 (match_operand:DI 2 "gpc_reg_operand" "")])
7961 (set (match_operand:DI 0 "gpc_reg_operand" "")
7963 "TARGET_POWERPC64 && reload_completed"
7964 [(set (match_dup 0) (match_dup 4))
7966 (compare:CC (match_dup 0)
7970 ;; Split a logical operation that we can't do in one insn into two insns,
7971 ;; each of which does one 16-bit part. This is used by combine.
7974 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7975 (match_operator:DI 3 "boolean_or_operator"
7976 [(match_operand:DI 1 "gpc_reg_operand" "")
7977 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7979 [(set (match_dup 0) (match_dup 4))
7980 (set (match_dup 0) (match_dup 5))]
7985 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
7986 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7987 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7989 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7993 (define_insn "*boolcdi3_internal1"
7994 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7995 (match_operator:DI 3 "boolean_operator"
7996 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7997 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8001 (define_insn "*boolcdi3_internal2"
8002 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8003 (compare:CC (match_operator:DI 4 "boolean_operator"
8004 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8005 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8007 (clobber (match_scratch:DI 3 "=r,r"))]
8012 [(set_attr "type" "logical,compare")
8013 (set_attr "dot" "yes")
8014 (set_attr "length" "4,8")])
8017 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8018 (compare:CC (match_operator:DI 4 "boolean_operator"
8019 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8020 (match_operand:DI 2 "gpc_reg_operand" "")])
8022 (clobber (match_scratch:DI 3 ""))]
8023 "TARGET_POWERPC64 && reload_completed"
8024 [(set (match_dup 3) (match_dup 4))
8026 (compare:CC (match_dup 3)
8030 (define_insn "*boolcdi3_internal3"
8031 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8032 (compare:CC (match_operator:DI 4 "boolean_operator"
8033 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8034 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8036 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8042 [(set_attr "type" "logical,compare")
8043 (set_attr "dot" "yes")
8044 (set_attr "length" "4,8")])
8047 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8048 (compare:CC (match_operator:DI 4 "boolean_operator"
8049 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8050 (match_operand:DI 2 "gpc_reg_operand" "")])
8052 (set (match_operand:DI 0 "gpc_reg_operand" "")
8054 "TARGET_POWERPC64 && reload_completed"
8055 [(set (match_dup 0) (match_dup 4))
8057 (compare:CC (match_dup 0)
8061 (define_insn "*boolccdi3_internal1"
8062 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8063 (match_operator:DI 3 "boolean_operator"
8064 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8065 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8069 (define_insn "*boolccdi3_internal2"
8070 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8071 (compare:CC (match_operator:DI 4 "boolean_operator"
8072 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8073 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8075 (clobber (match_scratch:DI 3 "=r,r"))]
8080 [(set_attr "type" "logical,compare")
8081 (set_attr "dot" "yes")
8082 (set_attr "length" "4,8")])
8085 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8086 (compare:CC (match_operator:DI 4 "boolean_operator"
8087 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8088 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8090 (clobber (match_scratch:DI 3 ""))]
8091 "TARGET_POWERPC64 && reload_completed"
8092 [(set (match_dup 3) (match_dup 4))
8094 (compare:CC (match_dup 3)
8098 (define_insn "*boolccdi3_internal3"
8099 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8100 (compare:CC (match_operator:DI 4 "boolean_operator"
8101 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8102 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8104 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8110 [(set_attr "type" "logical,compare")
8111 (set_attr "dot" "yes")
8112 (set_attr "length" "4,8")])
8115 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8116 (compare:CC (match_operator:DI 4 "boolean_operator"
8117 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8118 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8120 (set (match_operand:DI 0 "gpc_reg_operand" "")
8122 "TARGET_POWERPC64 && reload_completed"
8123 [(set (match_dup 0) (match_dup 4))
8125 (compare:CC (match_dup 0)
8130 (define_insn "*eqv<mode>3"
8131 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
8133 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
8134 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
8137 [(set_attr "type" "integer")
8138 (set_attr "length" "4")])
8141 ;; 128-bit logical operations expanders
8143 (define_expand "and<mode>3"
8144 [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8146 (match_operand:BOOL_128 1 "vlogical_operand" "")
8147 (match_operand:BOOL_128 2 "vlogical_operand" "")))
8148 (clobber (match_scratch:CC 3 ""))])]
8152 (define_expand "ior<mode>3"
8153 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8154 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8155 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8159 (define_expand "xor<mode>3"
8160 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8161 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8162 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8166 (define_expand "one_cmpl<mode>2"
8167 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8168 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8172 (define_expand "nor<mode>3"
8173 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8175 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8176 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8180 (define_expand "andc<mode>3"
8181 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8183 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8184 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8188 ;; Power8 vector logical instructions.
8189 (define_expand "eqv<mode>3"
8190 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8192 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8193 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8194 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8197 ;; Rewrite nand into canonical form
8198 (define_expand "nand<mode>3"
8199 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8201 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8202 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8203 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8206 ;; The canonical form is to have the negated element first, so we need to
8207 ;; reverse arguments.
8208 (define_expand "orc<mode>3"
8209 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8211 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8212 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8213 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8216 ;; 128-bit logical operations insns and split operations
8217 (define_insn_and_split "*and<mode>3_internal"
8218 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8220 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8221 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
8222 (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
8225 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8226 return "xxland %x0,%x1,%x2";
8228 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8229 return "vand %0,%1,%2";
8233 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8236 rs6000_split_logical (operands, AND, false, false, false, operands[3]);
8241 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8242 (const_string "vecsimple")
8243 (const_string "integer")))
8244 (set (attr "length")
8246 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8249 (match_test "TARGET_POWERPC64")
8251 (const_string "16"))))])
8254 (define_insn_and_split "*bool<mode>3_internal"
8255 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8256 (match_operator:BOOL_128 3 "boolean_or_operator"
8257 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8258 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8261 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8262 return "xxl%q3 %x0,%x1,%x2";
8264 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8265 return "v%q3 %0,%1,%2";
8269 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8272 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
8278 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8279 (const_string "vecsimple")
8280 (const_string "integer")))
8281 (set (attr "length")
8283 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8286 (match_test "TARGET_POWERPC64")
8288 (const_string "16"))))])
8291 (define_insn_and_split "*boolc<mode>3_internal1"
8292 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8293 (match_operator:BOOL_128 3 "boolean_operator"
8295 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
8296 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8297 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8299 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8300 return "xxl%q3 %x0,%x1,%x2";
8302 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8303 return "v%q3 %0,%1,%2";
8307 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8308 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8311 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8317 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8318 (const_string "vecsimple")
8319 (const_string "integer")))
8320 (set (attr "length")
8322 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8325 (match_test "TARGET_POWERPC64")
8327 (const_string "16"))))])
8329 (define_insn_and_split "*boolc<mode>3_internal2"
8330 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8331 (match_operator:TI2 3 "boolean_operator"
8333 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8334 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
8335 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8337 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8340 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8344 [(set_attr "type" "integer")
8345 (set (attr "length")
8347 (match_test "TARGET_POWERPC64")
8349 (const_string "16")))])
8352 (define_insn_and_split "*boolcc<mode>3_internal1"
8353 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8354 (match_operator:BOOL_128 3 "boolean_operator"
8356 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
8358 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
8359 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8361 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8362 return "xxl%q3 %x0,%x1,%x2";
8364 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8365 return "v%q3 %0,%1,%2";
8369 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8370 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8373 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8379 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8380 (const_string "vecsimple")
8381 (const_string "integer")))
8382 (set (attr "length")
8384 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8387 (match_test "TARGET_POWERPC64")
8389 (const_string "16"))))])
8391 (define_insn_and_split "*boolcc<mode>3_internal2"
8392 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8393 (match_operator:TI2 3 "boolean_operator"
8395 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8397 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
8398 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8400 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8403 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8407 [(set_attr "type" "integer")
8408 (set (attr "length")
8410 (match_test "TARGET_POWERPC64")
8412 (const_string "16")))])
8416 (define_insn_and_split "*eqv<mode>3_internal1"
8417 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8420 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
8421 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
8424 if (vsx_register_operand (operands[0], <MODE>mode))
8425 return "xxleqv %x0,%x1,%x2";
8429 "TARGET_P8_VECTOR && reload_completed
8430 && int_reg_operand (operands[0], <MODE>mode)"
8433 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8438 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8439 (const_string "vecsimple")
8440 (const_string "integer")))
8441 (set (attr "length")
8443 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8446 (match_test "TARGET_POWERPC64")
8448 (const_string "16"))))])
8450 (define_insn_and_split "*eqv<mode>3_internal2"
8451 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8454 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
8455 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
8458 "reload_completed && !TARGET_P8_VECTOR"
8461 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8464 [(set_attr "type" "integer")
8465 (set (attr "length")
8467 (match_test "TARGET_POWERPC64")
8469 (const_string "16")))])
8471 ;; 128-bit one's complement
8472 (define_insn_and_split "*one_cmpl<mode>3_internal"
8473 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8475 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
8478 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8479 return "xxlnor %x0,%x1,%x1";
8481 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8482 return "vnor %0,%1,%1";
8486 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8489 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
8494 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8495 (const_string "vecsimple")
8496 (const_string "integer")))
8497 (set (attr "length")
8499 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8502 (match_test "TARGET_POWERPC64")
8504 (const_string "16"))))])
8507 ;; Now define ways of moving data around.
8509 ;; Set up a register with a value from the GOT table
8511 (define_expand "movsi_got"
8512 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8513 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8514 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8515 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8518 if (GET_CODE (operands[1]) == CONST)
8520 rtx offset = const0_rtx;
8521 HOST_WIDE_INT value;
8523 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8524 value = INTVAL (offset);
8527 rtx tmp = (!can_create_pseudo_p ()
8529 : gen_reg_rtx (Pmode));
8530 emit_insn (gen_movsi_got (tmp, operands[1]));
8531 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8536 operands[2] = rs6000_got_register (operands[1]);
8539 (define_insn "*movsi_got_internal"
8540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8541 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8542 (match_operand:SI 2 "gpc_reg_operand" "b")]
8544 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8545 "lwz %0,%a1@got(%2)"
8546 [(set_attr "type" "load")])
8548 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8549 ;; didn't get allocated to a hard register.
8551 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8552 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8553 (match_operand:SI 2 "memory_operand" "")]
8555 "DEFAULT_ABI == ABI_V4
8557 && (reload_in_progress || reload_completed)"
8558 [(set (match_dup 0) (match_dup 2))
8559 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8563 ;; For SI, we special-case integers that can't be loaded in one insn. We
8564 ;; do the load 16-bits at a time. We could do this by loading from memory,
8565 ;; and this is even supposed to be faster, but it is simpler not to get
8566 ;; integers in the TOC.
8567 (define_insn "movsi_low"
8568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8569 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8570 (match_operand 2 "" ""))))]
8571 "TARGET_MACHO && ! TARGET_64BIT"
8572 "lwz %0,lo16(%2)(%1)"
8573 [(set_attr "type" "load")
8574 (set_attr "length" "4")])
8576 (define_insn "*movsi_internal1"
8577 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8578 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8579 "!TARGET_SINGLE_FPU &&
8580 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8593 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
8594 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8596 (define_insn "*movsi_internal1_single"
8597 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8598 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8599 "TARGET_SINGLE_FPU &&
8600 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8615 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
8616 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8618 ;; Split a load of a large constant into the appropriate two-insn
8622 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8623 (match_operand:SI 1 "const_int_operand" ""))]
8624 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8625 && (INTVAL (operands[1]) & 0xffff) != 0"
8629 (ior:SI (match_dup 0)
8633 if (rs6000_emit_set_const (operands[0], operands[1]))
8639 (define_insn "*mov<mode>_internal2"
8640 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8641 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8643 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8649 [(set_attr "type" "cmp,logical,cmp")
8650 (set_attr "dot" "yes")
8651 (set_attr "length" "4,4,8")])
8654 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8655 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8657 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8659 [(set (match_dup 0) (match_dup 1))
8661 (compare:CC (match_dup 0)
8665 (define_insn "*movhi_internal"
8666 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8667 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8668 "gpc_reg_operand (operands[0], HImode)
8669 || gpc_reg_operand (operands[1], HImode)"
8678 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
8680 (define_expand "mov<mode>"
8681 [(set (match_operand:INT 0 "general_operand" "")
8682 (match_operand:INT 1 "any_operand" ""))]
8684 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8686 (define_insn "*movqi_internal"
8687 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8688 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8689 "gpc_reg_operand (operands[0], QImode)
8690 || gpc_reg_operand (operands[1], QImode)"
8699 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
8701 ;; Here is how to move condition codes around. When we store CC data in
8702 ;; an integer register or memory, we store just the high-order 4 bits.
8703 ;; This lets us not shift in the most common case of CR0.
8704 (define_expand "movcc"
8705 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8706 (match_operand:CC 1 "nonimmediate_operand" ""))]
8710 (define_insn "*movcc_internal1"
8711 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
8712 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
8713 "register_operand (operands[0], CCmode)
8714 || register_operand (operands[1], CCmode)"
8718 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
8721 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
8729 (cond [(eq_attr "alternative" "0,3")
8730 (const_string "cr_logical")
8731 (eq_attr "alternative" "1,2")
8732 (const_string "mtcr")
8733 (eq_attr "alternative" "6,7")
8734 (const_string "integer")
8735 (eq_attr "alternative" "8")
8736 (const_string "mfjmpr")
8737 (eq_attr "alternative" "9")
8738 (const_string "mtjmpr")
8739 (eq_attr "alternative" "10")
8740 (const_string "load")
8741 (eq_attr "alternative" "11")
8742 (const_string "store")
8743 (match_test "TARGET_MFCRF")
8744 (const_string "mfcrf")
8746 (const_string "mfcr")))
8747 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
8749 ;; For floating-point, we normally deal with the floating-point registers
8750 ;; unless -msoft-float is used. The sole exception is that parameter passing
8751 ;; can produce floating-point values in fixed-point registers. Unless the
8752 ;; value is a simple constant or already in memory, we deal with this by
8753 ;; allocating memory and copying the value explicitly via that memory location.
8755 ;; Move 32-bit binary/decimal floating point
8756 (define_expand "mov<mode>"
8757 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
8758 (match_operand:FMOVE32 1 "any_operand" ""))]
8760 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8763 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
8764 (match_operand:FMOVE32 1 "const_double_operand" ""))]
8766 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8767 || (GET_CODE (operands[0]) == SUBREG
8768 && GET_CODE (SUBREG_REG (operands[0])) == REG
8769 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8770 [(set (match_dup 2) (match_dup 3))]
8776 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8777 <real_value_to_target> (rv, l);
8779 if (! TARGET_POWERPC64)
8780 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
8782 operands[2] = gen_lowpart (SImode, operands[0]);
8784 operands[3] = gen_int_mode (l, SImode);
8787 (define_insn "mov<mode>_hardfloat"
8788 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
8789 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
8790 "(gpc_reg_operand (operands[0], <MODE>mode)
8791 || gpc_reg_operand (operands[1], <MODE>mode))
8792 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8811 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
8812 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
8814 (define_insn "*mov<mode>_softfloat"
8815 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
8816 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
8817 "(gpc_reg_operand (operands[0], <MODE>mode)
8818 || gpc_reg_operand (operands[1], <MODE>mode))
8819 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8831 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
8832 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
8835 ;; Move 64-bit binary/decimal floating point
8836 (define_expand "mov<mode>"
8837 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
8838 (match_operand:FMOVE64 1 "any_operand" ""))]
8840 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8843 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8844 (match_operand:FMOVE64 1 "const_int_operand" ""))]
8845 "! TARGET_POWERPC64 && reload_completed
8846 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8847 || (GET_CODE (operands[0]) == SUBREG
8848 && GET_CODE (SUBREG_REG (operands[0])) == REG
8849 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8850 [(set (match_dup 2) (match_dup 4))
8851 (set (match_dup 3) (match_dup 1))]
8854 int endian = (WORDS_BIG_ENDIAN == 0);
8855 HOST_WIDE_INT value = INTVAL (operands[1]);
8857 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8858 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8859 operands[4] = GEN_INT (value >> 32);
8860 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8864 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8865 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8866 "! TARGET_POWERPC64 && reload_completed
8867 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8868 || (GET_CODE (operands[0]) == SUBREG
8869 && GET_CODE (SUBREG_REG (operands[0])) == REG
8870 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8871 [(set (match_dup 2) (match_dup 4))
8872 (set (match_dup 3) (match_dup 5))]
8875 int endian = (WORDS_BIG_ENDIAN == 0);
8879 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8880 <real_value_to_target> (rv, l);
8882 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8883 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8884 operands[4] = gen_int_mode (l[endian], SImode);
8885 operands[5] = gen_int_mode (l[1 - endian], SImode);
8889 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8890 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8891 "TARGET_POWERPC64 && reload_completed
8892 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8893 || (GET_CODE (operands[0]) == SUBREG
8894 && GET_CODE (SUBREG_REG (operands[0])) == REG
8895 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8896 [(set (match_dup 2) (match_dup 3))]
8899 int endian = (WORDS_BIG_ENDIAN == 0);
8904 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8905 <real_value_to_target> (rv, l);
8907 operands[2] = gen_lowpart (DImode, operands[0]);
8908 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8909 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8910 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8912 operands[3] = gen_int_mode (val, DImode);
8915 ;; Don't have reload use general registers to load a constant. It is
8916 ;; less efficient than loading the constant into an FP register, since
8917 ;; it will probably be used there.
8919 ;; The move constraints are ordered to prefer floating point registers before
8920 ;; general purpose registers to avoid doing a store and a load to get the value
8921 ;; into a floating point register when it is needed for a floating point
8922 ;; operation. Prefer traditional floating point registers over VSX registers,
8923 ;; since the D-form version of the memory instructions does not need a GPR for
8926 (define_insn "*mov<mode>_hardfloat32"
8927 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
8928 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
8929 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8930 && (gpc_reg_operand (operands[0], <MODE>mode)
8931 || gpc_reg_operand (operands[1], <MODE>mode))"
8946 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8947 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8949 (define_insn "*mov<mode>_softfloat32"
8950 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8951 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8953 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8954 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8955 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8956 && (gpc_reg_operand (operands[0], <MODE>mode)
8957 || gpc_reg_operand (operands[1], <MODE>mode))"
8959 [(set_attr "type" "store,load,two,*,*,*")
8960 (set_attr "length" "8,8,8,8,12,16")])
8962 ; ld/std require word-aligned displacements -> 'Y' constraint.
8963 ; List Y->r and r->Y before r->r for reload.
8964 (define_insn "*mov<mode>_hardfloat64"
8965 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
8966 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
8967 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8968 && (gpc_reg_operand (operands[0], <MODE>mode)
8969 || gpc_reg_operand (operands[1], <MODE>mode))"
8991 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8992 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8994 (define_insn "*mov<mode>_softfloat64"
8995 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8996 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8997 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8998 && (gpc_reg_operand (operands[0], <MODE>mode)
8999 || gpc_reg_operand (operands[1], <MODE>mode))"
9010 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
9011 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9013 (define_expand "mov<mode>"
9014 [(set (match_operand:FMOVE128 0 "general_operand" "")
9015 (match_operand:FMOVE128 1 "any_operand" ""))]
9017 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9019 ;; It's important to list Y->r and r->Y before r->r because otherwise
9020 ;; reload, given m->r, will try to pick r->r and reload it, which
9021 ;; doesn't make progress.
9023 ;; We can't split little endian direct moves of TDmode, because the words are
9024 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
9025 ;; problematical. Don't allow direct move for this case.
9027 (define_insn_and_split "*mov<mode>_64bit_dm"
9028 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
9029 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
9030 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
9031 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
9032 && (gpc_reg_operand (operands[0], <MODE>mode)
9033 || gpc_reg_operand (operands[1], <MODE>mode))"
9035 "&& reload_completed"
9037 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9038 [(set_attr "length" "8,8,8,12,12,8,8,8")])
9040 (define_insn_and_split "*movtd_64bit_nodm"
9041 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9042 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
9043 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
9044 && (gpc_reg_operand (operands[0], TDmode)
9045 || gpc_reg_operand (operands[1], TDmode))"
9047 "&& reload_completed"
9049 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9050 [(set_attr "length" "8,8,8,12,12,8")])
9052 (define_insn_and_split "*mov<mode>_32bit"
9053 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9054 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9055 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
9056 && (gpc_reg_operand (operands[0], <MODE>mode)
9057 || gpc_reg_operand (operands[1], <MODE>mode))"
9059 "&& reload_completed"
9061 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9062 [(set_attr "length" "8,8,8,20,20,16")])
9064 (define_insn_and_split "*mov<mode>_softfloat"
9065 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9066 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9067 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9068 && (gpc_reg_operand (operands[0], <MODE>mode)
9069 || gpc_reg_operand (operands[1], <MODE>mode))"
9071 "&& reload_completed"
9073 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9074 [(set_attr "length" "20,20,16")])
9076 (define_expand "extenddftf2"
9077 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9078 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9080 && TARGET_HARD_FLOAT
9081 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9082 && TARGET_LONG_DOUBLE_128"
9084 if (TARGET_E500_DOUBLE)
9085 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9087 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9091 (define_expand "extenddftf2_fprs"
9092 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9093 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9094 (use (match_dup 2))])]
9096 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9097 && TARGET_LONG_DOUBLE_128"
9099 operands[2] = CONST0_RTX (DFmode);
9100 /* Generate GOT reference early for SVR4 PIC. */
9101 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9102 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9105 (define_insn_and_split "*extenddftf2_internal"
9106 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9107 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9108 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9110 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9111 && TARGET_LONG_DOUBLE_128"
9113 "&& reload_completed"
9116 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9117 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9118 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9120 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9125 (define_expand "extendsftf2"
9126 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9127 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9129 && TARGET_HARD_FLOAT
9130 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9131 && TARGET_LONG_DOUBLE_128"
9133 rtx tmp = gen_reg_rtx (DFmode);
9134 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9135 emit_insn (gen_extenddftf2 (operands[0], tmp));
9139 (define_expand "trunctfdf2"
9140 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9141 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9143 && TARGET_HARD_FLOAT
9144 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9145 && TARGET_LONG_DOUBLE_128"
9148 (define_insn_and_split "trunctfdf2_internal1"
9149 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9150 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9151 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9152 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9156 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9159 emit_note (NOTE_INSN_DELETED);
9162 [(set_attr "type" "fp")])
9164 (define_insn "trunctfdf2_internal2"
9165 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9166 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9167 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9168 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9169 && TARGET_LONG_DOUBLE_128"
9171 [(set_attr "type" "fp")
9172 (set_attr "fp_type" "fp_addsub_d")])
9174 (define_expand "trunctfsf2"
9175 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9176 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9178 && TARGET_HARD_FLOAT
9179 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9180 && TARGET_LONG_DOUBLE_128"
9182 if (TARGET_E500_DOUBLE)
9183 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9185 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9189 (define_insn_and_split "trunctfsf2_fprs"
9190 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9191 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9192 (clobber (match_scratch:DF 2 "=d"))]
9194 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9195 && TARGET_LONG_DOUBLE_128"
9197 "&& reload_completed"
9199 (float_truncate:DF (match_dup 1)))
9201 (float_truncate:SF (match_dup 2)))]
9204 (define_expand "floatsitf2"
9205 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9206 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9208 && TARGET_HARD_FLOAT
9209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9210 && TARGET_LONG_DOUBLE_128"
9212 rtx tmp = gen_reg_rtx (DFmode);
9213 expand_float (tmp, operands[1], false);
9214 emit_insn (gen_extenddftf2 (operands[0], tmp));
9218 ; fadd, but rounding towards zero.
9219 ; This is probably not the optimal code sequence.
9220 (define_insn "fix_trunc_helper"
9221 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9222 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9223 UNSPEC_FIX_TRUNC_TF))
9224 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9225 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9226 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9227 [(set_attr "type" "fp")
9228 (set_attr "length" "20")])
9230 (define_expand "fix_trunctfsi2"
9231 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9232 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9233 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9234 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9236 if (TARGET_E500_DOUBLE)
9237 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9239 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9243 (define_expand "fix_trunctfsi2_fprs"
9244 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9245 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9246 (clobber (match_dup 2))
9247 (clobber (match_dup 3))
9248 (clobber (match_dup 4))
9249 (clobber (match_dup 5))])]
9251 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9253 operands[2] = gen_reg_rtx (DFmode);
9254 operands[3] = gen_reg_rtx (DFmode);
9255 operands[4] = gen_reg_rtx (DImode);
9256 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9259 (define_insn_and_split "*fix_trunctfsi2_internal"
9260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9261 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9262 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9263 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9264 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9265 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9267 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9273 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9275 gcc_assert (MEM_P (operands[5]));
9276 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9278 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9279 emit_move_insn (operands[5], operands[4]);
9280 emit_move_insn (operands[0], lowword);
9284 (define_expand "negtf2"
9285 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9286 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9288 && TARGET_HARD_FLOAT
9289 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9290 && TARGET_LONG_DOUBLE_128"
9293 (define_insn "negtf2_internal"
9294 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9295 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9297 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9300 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9301 return \"fneg %L0,%L1\;fneg %0,%1\";
9303 return \"fneg %0,%1\;fneg %L0,%L1\";
9305 [(set_attr "type" "fp")
9306 (set_attr "length" "8")])
9308 (define_expand "abstf2"
9309 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9310 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9312 && TARGET_HARD_FLOAT
9313 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9314 && TARGET_LONG_DOUBLE_128"
9317 rtx label = gen_label_rtx ();
9318 if (TARGET_E500_DOUBLE)
9320 if (flag_finite_math_only && !flag_trapping_math)
9321 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9323 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9326 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9331 (define_expand "abstf2_internal"
9332 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9333 (match_operand:TF 1 "gpc_reg_operand" ""))
9334 (set (match_dup 3) (match_dup 5))
9335 (set (match_dup 5) (abs:DF (match_dup 5)))
9336 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9337 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9338 (label_ref (match_operand 2 "" ""))
9340 (set (match_dup 6) (neg:DF (match_dup 6)))]
9342 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9343 && TARGET_LONG_DOUBLE_128"
9346 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9347 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9348 operands[3] = gen_reg_rtx (DFmode);
9349 operands[4] = gen_reg_rtx (CCFPmode);
9350 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9351 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9354 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9355 ;; must have 3 arguments, and scratch register constraint must be a single
9358 ;; Reload patterns to support gpr load/store with misaligned mem.
9359 ;; and multiple gpr load/store at offset >= 0xfffc
9360 (define_expand "reload_<mode>_store"
9361 [(parallel [(match_operand 0 "memory_operand" "=m")
9362 (match_operand 1 "gpc_reg_operand" "r")
9363 (match_operand:GPR 2 "register_operand" "=&b")])]
9366 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9370 (define_expand "reload_<mode>_load"
9371 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9372 (match_operand 1 "memory_operand" "m")
9373 (match_operand:GPR 2 "register_operand" "=b")])]
9376 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9381 ;; Power8 merge instructions to allow direct move to/from floating point
9382 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
9383 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
9384 ;; value, since it is allocated in reload and not all of the flow information
9385 ;; is setup for it. We have two patterns to do the two moves between gprs and
9386 ;; fprs. There isn't a dependancy between the two, but we could potentially
9387 ;; schedule other instructions between the two instructions. TFmode is
9388 ;; currently limited to traditional FPR registers. If/when this is changed, we
9389 ;; will need to revist %L to make sure it works with VSX registers, or add an
9390 ;; %x version of %L.
9392 (define_insn "p8_fmrgow_<mode>"
9393 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
9394 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
9395 UNSPEC_P8V_FMRGOW))]
9396 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9398 [(set_attr "type" "vecperm")])
9400 (define_insn "p8_mtvsrwz_1"
9401 [(set (match_operand:TF 0 "register_operand" "=d")
9402 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
9403 UNSPEC_P8V_MTVSRWZ))]
9404 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9406 [(set_attr "type" "mftgpr")])
9408 (define_insn "p8_mtvsrwz_2"
9409 [(set (match_operand:TF 0 "register_operand" "+d")
9410 (unspec:TF [(match_dup 0)
9411 (match_operand:SI 1 "register_operand" "r")]
9412 UNSPEC_P8V_MTVSRWZ))]
9413 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9415 [(set_attr "type" "mftgpr")])
9417 (define_insn_and_split "reload_fpr_from_gpr<mode>"
9418 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
9419 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
9420 UNSPEC_P8V_RELOAD_FROM_GPR))
9421 (clobber (match_operand:TF 2 "register_operand" "=d"))]
9422 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9424 "&& reload_completed"
9427 rtx dest = operands[0];
9428 rtx src = operands[1];
9429 rtx tmp = operands[2];
9430 rtx gpr_hi_reg = gen_highpart (SImode, src);
9431 rtx gpr_lo_reg = gen_lowpart (SImode, src);
9433 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
9434 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
9435 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
9438 [(set_attr "length" "12")
9439 (set_attr "type" "three")])
9441 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
9442 (define_insn "p8_mtvsrd_1"
9443 [(set (match_operand:TF 0 "register_operand" "=ws")
9444 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
9445 UNSPEC_P8V_MTVSRD))]
9446 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9448 [(set_attr "type" "mftgpr")])
9450 (define_insn "p8_mtvsrd_2"
9451 [(set (match_operand:TF 0 "register_operand" "+ws")
9452 (unspec:TF [(match_dup 0)
9453 (match_operand:DI 1 "register_operand" "r")]
9454 UNSPEC_P8V_MTVSRD))]
9455 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9457 [(set_attr "type" "mftgpr")])
9459 (define_insn "p8_xxpermdi_<mode>"
9460 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9461 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
9462 UNSPEC_P8V_XXPERMDI))]
9463 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9464 "xxpermdi %x0,%1,%L1,0"
9465 [(set_attr "type" "vecperm")])
9467 (define_insn_and_split "reload_vsx_from_gpr<mode>"
9468 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9469 (unspec:FMOVE128_GPR
9470 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
9471 UNSPEC_P8V_RELOAD_FROM_GPR))
9472 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
9473 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9475 "&& reload_completed"
9478 rtx dest = operands[0];
9479 rtx src = operands[1];
9480 rtx tmp = operands[2];
9481 rtx gpr_hi_reg = gen_highpart (DImode, src);
9482 rtx gpr_lo_reg = gen_lowpart (DImode, src);
9484 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
9485 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
9486 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
9488 [(set_attr "length" "12")
9489 (set_attr "type" "three")])
9492 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
9493 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
9495 && (int_reg_operand (operands[0], <MODE>mode)
9496 || int_reg_operand (operands[1], <MODE>mode))"
9498 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9500 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
9501 ;; type is stored internally as double precision in the VSX registers, we have
9502 ;; to convert it from the vector format.
9504 (define_insn_and_split "reload_vsx_from_gprsf"
9505 [(set (match_operand:SF 0 "register_operand" "=wa")
9506 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
9507 UNSPEC_P8V_RELOAD_FROM_GPR))
9508 (clobber (match_operand:DI 2 "register_operand" "=r"))]
9509 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9511 "&& reload_completed"
9514 rtx op0 = operands[0];
9515 rtx op1 = operands[1];
9516 rtx op2 = operands[2];
9517 /* Also use the destination register to hold the unconverted DImode value.
9518 This is conceptually a separate value from OP0, so we use gen_rtx_REG
9519 rather than simplify_gen_subreg. */
9520 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
9521 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
9523 /* Move SF value to upper 32-bits for xscvspdpn. */
9524 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
9525 emit_move_insn (op0_di, op2);
9526 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
9529 [(set_attr "length" "8")
9530 (set_attr "type" "two")])
9532 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
9533 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
9534 ;; and then doing a move of that.
9535 (define_insn "p8_mfvsrd_3_<mode>"
9536 [(set (match_operand:DF 0 "register_operand" "=r")
9537 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9538 UNSPEC_P8V_RELOAD_FROM_VSX))]
9539 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9541 [(set_attr "type" "mftgpr")])
9543 (define_insn_and_split "reload_gpr_from_vsx<mode>"
9544 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
9545 (unspec:FMOVE128_GPR
9546 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9547 UNSPEC_P8V_RELOAD_FROM_VSX))
9548 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
9549 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9551 "&& reload_completed"
9554 rtx dest = operands[0];
9555 rtx src = operands[1];
9556 rtx tmp = operands[2];
9557 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
9558 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
9560 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
9561 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
9562 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
9564 [(set_attr "length" "12")
9565 (set_attr "type" "three")])
9567 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
9568 ;; type is stored internally as double precision, we have to convert it to the
9571 (define_insn_and_split "reload_gpr_from_vsxsf"
9572 [(set (match_operand:SF 0 "register_operand" "=r")
9573 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
9574 UNSPEC_P8V_RELOAD_FROM_VSX))
9575 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
9576 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9578 "&& reload_completed"
9581 rtx op0 = operands[0];
9582 rtx op1 = operands[1];
9583 rtx op2 = operands[2];
9584 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
9586 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
9587 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
9588 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
9591 [(set_attr "length" "12")
9592 (set_attr "type" "three")])
9594 (define_insn "p8_mfvsrd_4_disf"
9595 [(set (match_operand:DI 0 "register_operand" "=r")
9596 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
9597 UNSPEC_P8V_RELOAD_FROM_VSX))]
9598 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9600 [(set_attr "type" "mftgpr")])
9603 ;; Next come the multi-word integer load and store and the load and store
9606 ;; List r->r after r->Y, otherwise reload will try to reload a
9607 ;; non-offsettable address by using r->r which won't make progress.
9608 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9609 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9610 (define_insn "*movdi_internal32"
9611 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
9612 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
9614 && (gpc_reg_operand (operands[0], DImode)
9615 || gpc_reg_operand (operands[1], DImode))"
9624 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
9627 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9628 (match_operand:DI 1 "const_int_operand" ""))]
9629 "! TARGET_POWERPC64 && reload_completed
9630 && gpr_or_gpr_p (operands[0], operands[1])
9631 && !direct_move_p (operands[0], operands[1])"
9632 [(set (match_dup 2) (match_dup 4))
9633 (set (match_dup 3) (match_dup 1))]
9636 HOST_WIDE_INT value = INTVAL (operands[1]);
9637 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9639 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9641 operands[4] = GEN_INT (value >> 32);
9642 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9646 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9647 (match_operand:DIFD 1 "input_operand" ""))]
9648 "reload_completed && !TARGET_POWERPC64
9649 && gpr_or_gpr_p (operands[0], operands[1])
9650 && !direct_move_p (operands[0], operands[1])"
9652 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9654 (define_insn "*movdi_internal64"
9655 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
9656 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
9658 && (gpc_reg_operand (operands[0], DImode)
9659 || gpc_reg_operand (operands[1], DImode))"
9677 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
9678 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
9680 ;; Generate all one-bits and clear left or right.
9681 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9683 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9684 (match_operand:DI 1 "mask64_operand" ""))]
9685 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9686 [(set (match_dup 0) (const_int -1))
9688 (and:DI (rotate:DI (match_dup 0)
9693 ;; Split a load of a large constant into the appropriate five-instruction
9694 ;; sequence. Handle anything in a constant number of insns.
9695 ;; When non-easy constants can go in the TOC, this should use
9696 ;; easy_fp_constant predicate.
9698 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9699 (match_operand:DI 1 "const_int_operand" ""))]
9700 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9701 [(set (match_dup 0) (match_dup 2))
9702 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9705 if (rs6000_emit_set_const (operands[0], operands[1]))
9712 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9713 (match_operand:DI 1 "const_scalar_int_operand" ""))]
9714 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9715 [(set (match_dup 0) (match_dup 2))
9716 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9719 if (rs6000_emit_set_const (operands[0], operands[1]))
9725 ;; TImode/PTImode is similar, except that we usually want to compute the
9726 ;; address into a register and use lsi/stsi (the exception is during reload).
9728 (define_insn "*mov<mode>_string"
9729 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9730 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
9732 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9733 && (gpc_reg_operand (operands[0], <MODE>mode)
9734 || gpc_reg_operand (operands[1], <MODE>mode))"
9737 switch (which_alternative)
9743 return \"stswi %1,%P0,16\";
9747 /* If the address is not used in the output, we can use lsi. Otherwise,
9748 fall through to generating four loads. */
9750 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9751 return \"lswi %0,%P1,16\";
9752 /* ... fall through ... */
9759 [(set_attr "type" "store,store,load,load,*,*")
9760 (set_attr "update" "yes")
9761 (set_attr "indexed" "yes")
9762 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9763 (const_string "always")
9764 (const_string "conditional")))])
9766 (define_insn "*mov<mode>_ppc64"
9767 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
9768 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
9769 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
9770 && (gpc_reg_operand (operands[0], <MODE>mode)
9771 || gpc_reg_operand (operands[1], <MODE>mode)))"
9773 return rs6000_output_move_128bit (operands);
9775 [(set_attr "type" "store,store,load,load,*,*")
9776 (set_attr "length" "8")])
9779 [(set (match_operand:TI2 0 "int_reg_operand" "")
9780 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
9782 && (VECTOR_MEM_NONE_P (<MODE>mode)
9783 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
9784 [(set (match_dup 2) (match_dup 4))
9785 (set (match_dup 3) (match_dup 5))]
9788 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9790 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9792 if (CONST_WIDE_INT_P (operands[1]))
9794 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
9795 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
9797 else if (CONST_INT_P (operands[1]))
9799 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9800 operands[5] = operands[1];
9807 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
9808 (match_operand:TI2 1 "input_operand" ""))]
9810 && gpr_or_gpr_p (operands[0], operands[1])
9811 && !direct_move_p (operands[0], operands[1])
9812 && !quad_load_store_p (operands[0], operands[1])"
9814 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9816 (define_expand "load_multiple"
9817 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9818 (match_operand:SI 1 "" ""))
9819 (use (match_operand:SI 2 "" ""))])]
9820 "TARGET_STRING && !TARGET_POWERPC64"
9828 /* Support only loading a constant number of fixed-point registers from
9829 memory and only bother with this if more than two; the machine
9830 doesn't support more than eight. */
9831 if (GET_CODE (operands[2]) != CONST_INT
9832 || INTVAL (operands[2]) <= 2
9833 || INTVAL (operands[2]) > 8
9834 || GET_CODE (operands[1]) != MEM
9835 || GET_CODE (operands[0]) != REG
9836 || REGNO (operands[0]) >= 32)
9839 count = INTVAL (operands[2]);
9840 regno = REGNO (operands[0]);
9842 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9843 op1 = replace_equiv_address (operands[1],
9844 force_reg (SImode, XEXP (operands[1], 0)));
9846 for (i = 0; i < count; i++)
9847 XVECEXP (operands[3], 0, i)
9848 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9849 adjust_address_nv (op1, SImode, i * 4));
9852 (define_insn "*ldmsi8"
9853 [(match_parallel 0 "load_multiple_operation"
9854 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9855 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9856 (set (match_operand:SI 3 "gpc_reg_operand" "")
9857 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9858 (set (match_operand:SI 4 "gpc_reg_operand" "")
9859 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9860 (set (match_operand:SI 5 "gpc_reg_operand" "")
9861 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9862 (set (match_operand:SI 6 "gpc_reg_operand" "")
9863 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9864 (set (match_operand:SI 7 "gpc_reg_operand" "")
9865 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9866 (set (match_operand:SI 8 "gpc_reg_operand" "")
9867 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9868 (set (match_operand:SI 9 "gpc_reg_operand" "")
9869 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9870 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9872 { return rs6000_output_load_multiple (operands); }"
9873 [(set_attr "type" "load")
9874 (set_attr "update" "yes")
9875 (set_attr "indexed" "yes")
9876 (set_attr "length" "32")])
9878 (define_insn "*ldmsi7"
9879 [(match_parallel 0 "load_multiple_operation"
9880 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9881 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9882 (set (match_operand:SI 3 "gpc_reg_operand" "")
9883 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9884 (set (match_operand:SI 4 "gpc_reg_operand" "")
9885 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9886 (set (match_operand:SI 5 "gpc_reg_operand" "")
9887 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9888 (set (match_operand:SI 6 "gpc_reg_operand" "")
9889 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9890 (set (match_operand:SI 7 "gpc_reg_operand" "")
9891 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9892 (set (match_operand:SI 8 "gpc_reg_operand" "")
9893 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9894 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9896 { return rs6000_output_load_multiple (operands); }"
9897 [(set_attr "type" "load")
9898 (set_attr "update" "yes")
9899 (set_attr "indexed" "yes")
9900 (set_attr "length" "32")])
9902 (define_insn "*ldmsi6"
9903 [(match_parallel 0 "load_multiple_operation"
9904 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9905 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9906 (set (match_operand:SI 3 "gpc_reg_operand" "")
9907 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9908 (set (match_operand:SI 4 "gpc_reg_operand" "")
9909 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9910 (set (match_operand:SI 5 "gpc_reg_operand" "")
9911 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9912 (set (match_operand:SI 6 "gpc_reg_operand" "")
9913 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9914 (set (match_operand:SI 7 "gpc_reg_operand" "")
9915 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9916 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9918 { return rs6000_output_load_multiple (operands); }"
9919 [(set_attr "type" "load")
9920 (set_attr "update" "yes")
9921 (set_attr "indexed" "yes")
9922 (set_attr "length" "32")])
9924 (define_insn "*ldmsi5"
9925 [(match_parallel 0 "load_multiple_operation"
9926 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9927 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9928 (set (match_operand:SI 3 "gpc_reg_operand" "")
9929 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9930 (set (match_operand:SI 4 "gpc_reg_operand" "")
9931 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9932 (set (match_operand:SI 5 "gpc_reg_operand" "")
9933 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9934 (set (match_operand:SI 6 "gpc_reg_operand" "")
9935 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9936 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9938 { return rs6000_output_load_multiple (operands); }"
9939 [(set_attr "type" "load")
9940 (set_attr "update" "yes")
9941 (set_attr "indexed" "yes")
9942 (set_attr "length" "32")])
9944 (define_insn "*ldmsi4"
9945 [(match_parallel 0 "load_multiple_operation"
9946 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9947 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9948 (set (match_operand:SI 3 "gpc_reg_operand" "")
9949 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9950 (set (match_operand:SI 4 "gpc_reg_operand" "")
9951 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9952 (set (match_operand:SI 5 "gpc_reg_operand" "")
9953 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9954 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9956 { return rs6000_output_load_multiple (operands); }"
9957 [(set_attr "type" "load")
9958 (set_attr "update" "yes")
9959 (set_attr "indexed" "yes")
9960 (set_attr "length" "32")])
9962 (define_insn "*ldmsi3"
9963 [(match_parallel 0 "load_multiple_operation"
9964 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9965 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9966 (set (match_operand:SI 3 "gpc_reg_operand" "")
9967 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9968 (set (match_operand:SI 4 "gpc_reg_operand" "")
9969 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9970 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9972 { return rs6000_output_load_multiple (operands); }"
9973 [(set_attr "type" "load")
9974 (set_attr "update" "yes")
9975 (set_attr "indexed" "yes")
9976 (set_attr "length" "32")])
9978 (define_expand "store_multiple"
9979 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9980 (match_operand:SI 1 "" ""))
9981 (clobber (scratch:SI))
9982 (use (match_operand:SI 2 "" ""))])]
9983 "TARGET_STRING && !TARGET_POWERPC64"
9992 /* Support only storing a constant number of fixed-point registers to
9993 memory and only bother with this if more than two; the machine
9994 doesn't support more than eight. */
9995 if (GET_CODE (operands[2]) != CONST_INT
9996 || INTVAL (operands[2]) <= 2
9997 || INTVAL (operands[2]) > 8
9998 || GET_CODE (operands[0]) != MEM
9999 || GET_CODE (operands[1]) != REG
10000 || REGNO (operands[1]) >= 32)
10003 count = INTVAL (operands[2]);
10004 regno = REGNO (operands[1]);
10006 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10007 to = force_reg (SImode, XEXP (operands[0], 0));
10008 op0 = replace_equiv_address (operands[0], to);
10010 XVECEXP (operands[3], 0, 0)
10011 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10012 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10013 gen_rtx_SCRATCH (SImode));
10015 for (i = 1; i < count; i++)
10016 XVECEXP (operands[3], 0, i + 1)
10017 = gen_rtx_SET (VOIDmode,
10018 adjust_address_nv (op0, SImode, i * 4),
10019 gen_rtx_REG (SImode, regno + i));
10022 (define_insn "*stmsi8"
10023 [(match_parallel 0 "store_multiple_operation"
10024 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10025 (match_operand:SI 2 "gpc_reg_operand" "r"))
10026 (clobber (match_scratch:SI 3 "=X"))
10027 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10028 (match_operand:SI 4 "gpc_reg_operand" "r"))
10029 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10030 (match_operand:SI 5 "gpc_reg_operand" "r"))
10031 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10032 (match_operand:SI 6 "gpc_reg_operand" "r"))
10033 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10034 (match_operand:SI 7 "gpc_reg_operand" "r"))
10035 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10036 (match_operand:SI 8 "gpc_reg_operand" "r"))
10037 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10038 (match_operand:SI 9 "gpc_reg_operand" "r"))
10039 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10040 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10041 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
10043 [(set_attr "type" "store")
10044 (set_attr "update" "yes")
10045 (set_attr "indexed" "yes")
10046 (set_attr "cell_micro" "always")])
10048 (define_insn "*stmsi7"
10049 [(match_parallel 0 "store_multiple_operation"
10050 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10051 (match_operand:SI 2 "gpc_reg_operand" "r"))
10052 (clobber (match_scratch:SI 3 "=X"))
10053 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10054 (match_operand:SI 4 "gpc_reg_operand" "r"))
10055 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10056 (match_operand:SI 5 "gpc_reg_operand" "r"))
10057 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10058 (match_operand:SI 6 "gpc_reg_operand" "r"))
10059 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10060 (match_operand:SI 7 "gpc_reg_operand" "r"))
10061 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10062 (match_operand:SI 8 "gpc_reg_operand" "r"))
10063 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10064 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10065 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10067 [(set_attr "type" "store")
10068 (set_attr "update" "yes")
10069 (set_attr "indexed" "yes")
10070 (set_attr "cell_micro" "always")])
10072 (define_insn "*stmsi6"
10073 [(match_parallel 0 "store_multiple_operation"
10074 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10075 (match_operand:SI 2 "gpc_reg_operand" "r"))
10076 (clobber (match_scratch:SI 3 "=X"))
10077 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10078 (match_operand:SI 4 "gpc_reg_operand" "r"))
10079 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10080 (match_operand:SI 5 "gpc_reg_operand" "r"))
10081 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10082 (match_operand:SI 6 "gpc_reg_operand" "r"))
10083 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10084 (match_operand:SI 7 "gpc_reg_operand" "r"))
10085 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10086 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10087 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10089 [(set_attr "type" "store")
10090 (set_attr "update" "yes")
10091 (set_attr "indexed" "yes")
10092 (set_attr "cell_micro" "always")])
10094 (define_insn "*stmsi5"
10095 [(match_parallel 0 "store_multiple_operation"
10096 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10097 (match_operand:SI 2 "gpc_reg_operand" "r"))
10098 (clobber (match_scratch:SI 3 "=X"))
10099 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10100 (match_operand:SI 4 "gpc_reg_operand" "r"))
10101 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10102 (match_operand:SI 5 "gpc_reg_operand" "r"))
10103 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10104 (match_operand:SI 6 "gpc_reg_operand" "r"))
10105 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10106 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10107 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10109 [(set_attr "type" "store")
10110 (set_attr "update" "yes")
10111 (set_attr "indexed" "yes")
10112 (set_attr "cell_micro" "always")])
10114 (define_insn "*stmsi4"
10115 [(match_parallel 0 "store_multiple_operation"
10116 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10117 (match_operand:SI 2 "gpc_reg_operand" "r"))
10118 (clobber (match_scratch:SI 3 "=X"))
10119 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10120 (match_operand:SI 4 "gpc_reg_operand" "r"))
10121 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10122 (match_operand:SI 5 "gpc_reg_operand" "r"))
10123 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10124 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10125 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10127 [(set_attr "type" "store")
10128 (set_attr "update" "yes")
10129 (set_attr "indexed" "yes")
10130 (set_attr "cell_micro" "always")])
10132 (define_insn "*stmsi3"
10133 [(match_parallel 0 "store_multiple_operation"
10134 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10135 (match_operand:SI 2 "gpc_reg_operand" "r"))
10136 (clobber (match_scratch:SI 3 "=X"))
10137 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10138 (match_operand:SI 4 "gpc_reg_operand" "r"))
10139 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10140 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10141 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10143 [(set_attr "type" "store")
10144 (set_attr "update" "yes")
10145 (set_attr "indexed" "yes")
10146 (set_attr "cell_micro" "always")])
10148 (define_expand "setmemsi"
10149 [(parallel [(set (match_operand:BLK 0 "" "")
10150 (match_operand 2 "const_int_operand" ""))
10151 (use (match_operand:SI 1 "" ""))
10152 (use (match_operand:SI 3 "" ""))])]
10156 /* If value to set is not zero, use the library routine. */
10157 if (operands[2] != const0_rtx)
10160 if (expand_block_clear (operands))
10166 ;; String/block move insn.
10167 ;; Argument 0 is the destination
10168 ;; Argument 1 is the source
10169 ;; Argument 2 is the length
10170 ;; Argument 3 is the alignment
10172 (define_expand "movmemsi"
10173 [(parallel [(set (match_operand:BLK 0 "" "")
10174 (match_operand:BLK 1 "" ""))
10175 (use (match_operand:SI 2 "" ""))
10176 (use (match_operand:SI 3 "" ""))])]
10180 if (expand_block_move (operands))
10186 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10187 ;; register allocator doesn't have a clue about allocating 8 word registers.
10188 ;; rD/rS = r5 is preferred, efficient form.
10189 (define_expand "movmemsi_8reg"
10190 [(parallel [(set (match_operand 0 "" "")
10191 (match_operand 1 "" ""))
10192 (use (match_operand 2 "" ""))
10193 (use (match_operand 3 "" ""))
10194 (clobber (reg:SI 5))
10195 (clobber (reg:SI 6))
10196 (clobber (reg:SI 7))
10197 (clobber (reg:SI 8))
10198 (clobber (reg:SI 9))
10199 (clobber (reg:SI 10))
10200 (clobber (reg:SI 11))
10201 (clobber (reg:SI 12))
10202 (clobber (match_scratch:SI 4 ""))])]
10207 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10208 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10209 (use (match_operand:SI 2 "immediate_operand" "i"))
10210 (use (match_operand:SI 3 "immediate_operand" "i"))
10211 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10212 (clobber (reg:SI 6))
10213 (clobber (reg:SI 7))
10214 (clobber (reg:SI 8))
10215 (clobber (reg:SI 9))
10216 (clobber (reg:SI 10))
10217 (clobber (reg:SI 11))
10218 (clobber (reg:SI 12))
10219 (clobber (match_scratch:SI 5 "=X"))]
10221 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10222 || INTVAL (operands[2]) == 0)
10223 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10224 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10225 && REGNO (operands[4]) == 5"
10226 "lswi %4,%1,%2\;stswi %4,%0,%2"
10227 [(set_attr "type" "store")
10228 (set_attr "update" "yes")
10229 (set_attr "indexed" "yes")
10230 (set_attr "cell_micro" "always")
10231 (set_attr "length" "8")])
10233 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10234 ;; register allocator doesn't have a clue about allocating 6 word registers.
10235 ;; rD/rS = r5 is preferred, efficient form.
10236 (define_expand "movmemsi_6reg"
10237 [(parallel [(set (match_operand 0 "" "")
10238 (match_operand 1 "" ""))
10239 (use (match_operand 2 "" ""))
10240 (use (match_operand 3 "" ""))
10241 (clobber (reg:SI 5))
10242 (clobber (reg:SI 6))
10243 (clobber (reg:SI 7))
10244 (clobber (reg:SI 8))
10245 (clobber (reg:SI 9))
10246 (clobber (reg:SI 10))
10247 (clobber (match_scratch:SI 4 ""))])]
10252 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10253 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10254 (use (match_operand:SI 2 "immediate_operand" "i"))
10255 (use (match_operand:SI 3 "immediate_operand" "i"))
10256 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10257 (clobber (reg:SI 6))
10258 (clobber (reg:SI 7))
10259 (clobber (reg:SI 8))
10260 (clobber (reg:SI 9))
10261 (clobber (reg:SI 10))
10262 (clobber (match_scratch:SI 5 "=X"))]
10264 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10265 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10266 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10267 && REGNO (operands[4]) == 5"
10268 "lswi %4,%1,%2\;stswi %4,%0,%2"
10269 [(set_attr "type" "store")
10270 (set_attr "update" "yes")
10271 (set_attr "indexed" "yes")
10272 (set_attr "cell_micro" "always")
10273 (set_attr "length" "8")])
10275 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10276 ;; problems with TImode.
10277 ;; rD/rS = r5 is preferred, efficient form.
10278 (define_expand "movmemsi_4reg"
10279 [(parallel [(set (match_operand 0 "" "")
10280 (match_operand 1 "" ""))
10281 (use (match_operand 2 "" ""))
10282 (use (match_operand 3 "" ""))
10283 (clobber (reg:SI 5))
10284 (clobber (reg:SI 6))
10285 (clobber (reg:SI 7))
10286 (clobber (reg:SI 8))
10287 (clobber (match_scratch:SI 4 ""))])]
10292 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10293 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10294 (use (match_operand:SI 2 "immediate_operand" "i"))
10295 (use (match_operand:SI 3 "immediate_operand" "i"))
10296 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10297 (clobber (reg:SI 6))
10298 (clobber (reg:SI 7))
10299 (clobber (reg:SI 8))
10300 (clobber (match_scratch:SI 5 "=X"))]
10302 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10303 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10304 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10305 && REGNO (operands[4]) == 5"
10306 "lswi %4,%1,%2\;stswi %4,%0,%2"
10307 [(set_attr "type" "store")
10308 (set_attr "update" "yes")
10309 (set_attr "indexed" "yes")
10310 (set_attr "cell_micro" "always")
10311 (set_attr "length" "8")])
10313 ;; Move up to 8 bytes at a time.
10314 (define_expand "movmemsi_2reg"
10315 [(parallel [(set (match_operand 0 "" "")
10316 (match_operand 1 "" ""))
10317 (use (match_operand 2 "" ""))
10318 (use (match_operand 3 "" ""))
10319 (clobber (match_scratch:DI 4 ""))
10320 (clobber (match_scratch:SI 5 ""))])]
10321 "TARGET_STRING && ! TARGET_POWERPC64"
10325 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10326 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10327 (use (match_operand:SI 2 "immediate_operand" "i"))
10328 (use (match_operand:SI 3 "immediate_operand" "i"))
10329 (clobber (match_scratch:DI 4 "=&r"))
10330 (clobber (match_scratch:SI 5 "=X"))]
10331 "TARGET_STRING && ! TARGET_POWERPC64
10332 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10333 "lswi %4,%1,%2\;stswi %4,%0,%2"
10334 [(set_attr "type" "store")
10335 (set_attr "update" "yes")
10336 (set_attr "indexed" "yes")
10337 (set_attr "cell_micro" "always")
10338 (set_attr "length" "8")])
10340 ;; Move up to 4 bytes at a time.
10341 (define_expand "movmemsi_1reg"
10342 [(parallel [(set (match_operand 0 "" "")
10343 (match_operand 1 "" ""))
10344 (use (match_operand 2 "" ""))
10345 (use (match_operand 3 "" ""))
10346 (clobber (match_scratch:SI 4 ""))
10347 (clobber (match_scratch:SI 5 ""))])]
10352 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10353 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10354 (use (match_operand:SI 2 "immediate_operand" "i"))
10355 (use (match_operand:SI 3 "immediate_operand" "i"))
10356 (clobber (match_scratch:SI 4 "=&r"))
10357 (clobber (match_scratch:SI 5 "=X"))]
10358 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10359 "lswi %4,%1,%2\;stswi %4,%0,%2"
10360 [(set_attr "type" "store")
10361 (set_attr "update" "yes")
10362 (set_attr "indexed" "yes")
10363 (set_attr "cell_micro" "always")
10364 (set_attr "length" "8")])
10366 ;; Define insns that do load or store with update. Some of these we can
10367 ;; get by using pre-decrement or pre-increment, but the hardware can also
10368 ;; do cases where the increment is not the size of the object.
10370 ;; In all these cases, we use operands 0 and 1 for the register being
10371 ;; incremented because those are the operands that local-alloc will
10372 ;; tie and these are the pair most likely to be tieable (and the ones
10373 ;; that will benefit the most).
10375 (define_insn "*movdi_update1"
10376 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10377 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10378 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10379 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10380 (plus:DI (match_dup 1) (match_dup 2)))]
10381 "TARGET_POWERPC64 && TARGET_UPDATE
10382 && (!avoiding_indexed_address_p (DImode)
10383 || !gpc_reg_operand (operands[2], DImode))"
10387 [(set_attr "type" "load")
10388 (set_attr "update" "yes")
10389 (set_attr "indexed" "yes,no")])
10391 (define_insn "movdi_<mode>_update"
10392 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10393 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10394 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10395 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10396 (plus:P (match_dup 1) (match_dup 2)))]
10397 "TARGET_POWERPC64 && TARGET_UPDATE
10398 && (!avoiding_indexed_address_p (Pmode)
10399 || !gpc_reg_operand (operands[2], Pmode)
10400 || (REG_P (operands[0])
10401 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10405 [(set_attr "type" "store")
10406 (set_attr "update" "yes")
10407 (set_attr "indexed" "yes,no")])
10409 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10410 ;; needed for stack allocation, even if the user passes -mno-update.
10411 (define_insn "movdi_<mode>_update_stack"
10412 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10413 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10414 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10415 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10416 (plus:P (match_dup 1) (match_dup 2)))]
10421 [(set_attr "type" "store")
10422 (set_attr "update" "yes")
10423 (set_attr "indexed" "yes,no")])
10425 (define_insn "*movsi_update1"
10426 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10427 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10428 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10429 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10430 (plus:SI (match_dup 1) (match_dup 2)))]
10432 && (!avoiding_indexed_address_p (SImode)
10433 || !gpc_reg_operand (operands[2], SImode))"
10437 [(set_attr "type" "load")
10438 (set_attr "update" "yes")
10439 (set_attr "indexed" "yes,no")])
10441 (define_insn "*movsi_update2"
10442 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10444 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10445 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10446 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10447 (plus:DI (match_dup 1) (match_dup 2)))]
10448 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10449 && !avoiding_indexed_address_p (DImode)"
10451 [(set_attr "type" "load")
10452 (set_attr "sign_extend" "yes")
10453 (set_attr "update" "yes")
10454 (set_attr "indexed" "yes")])
10456 (define_insn "movsi_update"
10457 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10458 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10459 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10460 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10461 (plus:SI (match_dup 1) (match_dup 2)))]
10463 && (!avoiding_indexed_address_p (SImode)
10464 || !gpc_reg_operand (operands[2], SImode)
10465 || (REG_P (operands[0])
10466 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10470 [(set_attr "type" "store")
10471 (set_attr "update" "yes")
10472 (set_attr "indexed" "yes,no")])
10474 ;; This is an unconditional pattern; needed for stack allocation, even
10475 ;; if the user passes -mno-update.
10476 (define_insn "movsi_update_stack"
10477 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10478 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10479 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10480 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10481 (plus:SI (match_dup 1) (match_dup 2)))]
10486 [(set_attr "type" "store")
10487 (set_attr "update" "yes")
10488 (set_attr "indexed" "yes,no")])
10490 (define_insn "*movhi_update1"
10491 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10492 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10493 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10494 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10495 (plus:SI (match_dup 1) (match_dup 2)))]
10497 && (!avoiding_indexed_address_p (SImode)
10498 || !gpc_reg_operand (operands[2], SImode))"
10502 [(set_attr "type" "load")
10503 (set_attr "update" "yes")
10504 (set_attr "indexed" "yes,no")])
10506 (define_insn "*movhi_update2"
10507 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10509 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10510 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10511 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10512 (plus:SI (match_dup 1) (match_dup 2)))]
10514 && (!avoiding_indexed_address_p (SImode)
10515 || !gpc_reg_operand (operands[2], SImode))"
10519 [(set_attr "type" "load")
10520 (set_attr "update" "yes")
10521 (set_attr "indexed" "yes,no")])
10523 (define_insn "*movhi_update3"
10524 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10526 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10527 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10528 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10529 (plus:SI (match_dup 1) (match_dup 2)))]
10530 "TARGET_UPDATE && rs6000_gen_cell_microcode
10531 && (!avoiding_indexed_address_p (SImode)
10532 || !gpc_reg_operand (operands[2], SImode))"
10536 [(set_attr "type" "load")
10537 (set_attr "sign_extend" "yes")
10538 (set_attr "update" "yes")
10539 (set_attr "indexed" "yes,no")])
10541 (define_insn "*movhi_update4"
10542 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10543 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10544 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10545 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10546 (plus:SI (match_dup 1) (match_dup 2)))]
10548 && (!avoiding_indexed_address_p (SImode)
10549 || !gpc_reg_operand (operands[2], SImode))"
10553 [(set_attr "type" "store")
10554 (set_attr "update" "yes")
10555 (set_attr "indexed" "yes,no")])
10557 (define_insn "*movqi_update1"
10558 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10559 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10560 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10561 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10562 (plus:SI (match_dup 1) (match_dup 2)))]
10564 && (!avoiding_indexed_address_p (SImode)
10565 || !gpc_reg_operand (operands[2], SImode))"
10569 [(set_attr "type" "load")
10570 (set_attr "update" "yes")
10571 (set_attr "indexed" "yes,no")])
10573 (define_insn "*movqi_update2"
10574 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10576 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10577 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10578 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10579 (plus:SI (match_dup 1) (match_dup 2)))]
10581 && (!avoiding_indexed_address_p (SImode)
10582 || !gpc_reg_operand (operands[2], SImode))"
10586 [(set_attr "type" "load")
10587 (set_attr "update" "yes")
10588 (set_attr "indexed" "yes,no")])
10590 (define_insn "*movqi_update3"
10591 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10592 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10593 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10594 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10595 (plus:SI (match_dup 1) (match_dup 2)))]
10597 && (!avoiding_indexed_address_p (SImode)
10598 || !gpc_reg_operand (operands[2], SImode))"
10602 [(set_attr "type" "store")
10603 (set_attr "update" "yes")
10604 (set_attr "indexed" "yes,no")])
10606 (define_insn "*movsf_update1"
10607 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10608 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10609 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10610 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10611 (plus:SI (match_dup 1) (match_dup 2)))]
10612 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10613 && (!avoiding_indexed_address_p (SImode)
10614 || !gpc_reg_operand (operands[2], SImode))"
10618 [(set_attr "type" "fpload")
10619 (set_attr "update" "yes")
10620 (set_attr "indexed" "yes,no")])
10622 (define_insn "*movsf_update2"
10623 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10624 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10625 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10626 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10627 (plus:SI (match_dup 1) (match_dup 2)))]
10628 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10629 && (!avoiding_indexed_address_p (SImode)
10630 || !gpc_reg_operand (operands[2], SImode))"
10634 [(set_attr "type" "fpstore")
10635 (set_attr "update" "yes")
10636 (set_attr "indexed" "yes,no")])
10638 (define_insn "*movsf_update3"
10639 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10640 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10641 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10642 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10643 (plus:SI (match_dup 1) (match_dup 2)))]
10644 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10645 && (!avoiding_indexed_address_p (SImode)
10646 || !gpc_reg_operand (operands[2], SImode))"
10650 [(set_attr "type" "load")
10651 (set_attr "update" "yes")
10652 (set_attr "indexed" "yes,no")])
10654 (define_insn "*movsf_update4"
10655 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10656 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10657 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10658 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10659 (plus:SI (match_dup 1) (match_dup 2)))]
10660 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10661 && (!avoiding_indexed_address_p (SImode)
10662 || !gpc_reg_operand (operands[2], SImode))"
10666 [(set_attr "type" "store")
10667 (set_attr "update" "yes")
10668 (set_attr "indexed" "yes,no")])
10670 (define_insn "*movdf_update1"
10671 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10672 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10673 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10674 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10675 (plus:SI (match_dup 1) (match_dup 2)))]
10676 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10677 && (!avoiding_indexed_address_p (SImode)
10678 || !gpc_reg_operand (operands[2], SImode))"
10682 [(set_attr "type" "fpload")
10683 (set_attr "update" "yes")
10684 (set_attr "indexed" "yes,no")])
10686 (define_insn "*movdf_update2"
10687 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10688 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10689 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10690 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10691 (plus:SI (match_dup 1) (match_dup 2)))]
10692 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10693 && (!avoiding_indexed_address_p (SImode)
10694 || !gpc_reg_operand (operands[2], SImode))"
10698 [(set_attr "type" "fpstore")
10699 (set_attr "update" "yes")
10700 (set_attr "indexed" "yes,no")])
10703 ;; After inserting conditional returns we can sometimes have
10704 ;; unnecessary register moves. Unfortunately we cannot have a
10705 ;; modeless peephole here, because some single SImode sets have early
10706 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10707 ;; sequences, using get_attr_length here will smash the operands
10708 ;; array. Neither is there an early_cobbler_p predicate.
10709 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10711 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10712 (match_operand:DF 1 "any_operand" ""))
10713 (set (match_operand:DF 2 "gpc_reg_operand" "")
10715 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10716 && peep2_reg_dead_p (2, operands[0])"
10717 [(set (match_dup 2) (match_dup 1))])
10720 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10721 (match_operand:SF 1 "any_operand" ""))
10722 (set (match_operand:SF 2 "gpc_reg_operand" "")
10724 "peep2_reg_dead_p (2, operands[0])"
10725 [(set (match_dup 2) (match_dup 1))])
10730 ;; Mode attributes for different ABIs.
10731 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10732 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10733 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10734 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10736 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10737 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10738 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10739 (match_operand 4 "" "g")))
10740 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10741 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10743 (clobber (reg:SI LR_REGNO))]
10744 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10746 if (TARGET_CMODEL != CMODEL_SMALL)
10747 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
10750 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
10752 "&& TARGET_TLS_MARKERS"
10753 [(set (match_dup 0)
10754 (unspec:TLSmode [(match_dup 1)
10757 (parallel [(set (match_dup 0)
10758 (call (mem:TLSmode (match_dup 3))
10760 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10761 (clobber (reg:SI LR_REGNO))])]
10763 [(set_attr "type" "two")
10764 (set (attr "length")
10765 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10769 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10770 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10771 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10772 (match_operand 4 "" "g")))
10773 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10774 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10776 (clobber (reg:SI LR_REGNO))]
10777 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10781 if (TARGET_SECURE_PLT && flag_pic == 2)
10782 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10784 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10787 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10789 "&& TARGET_TLS_MARKERS"
10790 [(set (match_dup 0)
10791 (unspec:TLSmode [(match_dup 1)
10794 (parallel [(set (match_dup 0)
10795 (call (mem:TLSmode (match_dup 3))
10797 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10798 (clobber (reg:SI LR_REGNO))])]
10800 [(set_attr "type" "two")
10801 (set_attr "length" "8")])
10803 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
10804 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10805 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10806 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10808 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10809 "addi %0,%1,%2@got@tlsgd"
10810 "&& TARGET_CMODEL != CMODEL_SMALL"
10811 [(set (match_dup 3)
10813 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
10815 (lo_sum:TLSmode (match_dup 3)
10816 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
10819 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10821 [(set (attr "length")
10822 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10826 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
10827 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10829 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10830 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10832 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10833 "addis %0,%1,%2@got@tlsgd@ha"
10834 [(set_attr "length" "4")])
10836 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
10837 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10838 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10839 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10840 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10842 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10843 "addi %0,%1,%2@got@tlsgd@l"
10844 [(set_attr "length" "4")])
10846 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10847 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10848 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10849 (match_operand 2 "" "g")))
10850 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10852 (clobber (reg:SI LR_REGNO))]
10853 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10854 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10855 "bl %z1(%3@tlsgd)\;nop"
10856 [(set_attr "type" "branch")
10857 (set_attr "length" "8")])
10859 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10860 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10861 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10862 (match_operand 2 "" "g")))
10863 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10865 (clobber (reg:SI LR_REGNO))]
10866 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10870 if (TARGET_SECURE_PLT && flag_pic == 2)
10871 return "bl %z1+32768(%3@tlsgd)@plt";
10872 return "bl %z1(%3@tlsgd)@plt";
10874 return "bl %z1(%3@tlsgd)";
10876 [(set_attr "type" "branch")
10877 (set_attr "length" "4")])
10879 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10880 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10881 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10882 (match_operand 3 "" "g")))
10883 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10885 (clobber (reg:SI LR_REGNO))]
10886 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10888 if (TARGET_CMODEL != CMODEL_SMALL)
10889 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10892 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10894 "&& TARGET_TLS_MARKERS"
10895 [(set (match_dup 0)
10896 (unspec:TLSmode [(match_dup 1)]
10898 (parallel [(set (match_dup 0)
10899 (call (mem:TLSmode (match_dup 2))
10901 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10902 (clobber (reg:SI LR_REGNO))])]
10904 [(set_attr "type" "two")
10905 (set (attr "length")
10906 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10910 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10911 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10912 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10913 (match_operand 3 "" "g")))
10914 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10916 (clobber (reg:SI LR_REGNO))]
10917 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10921 if (TARGET_SECURE_PLT && flag_pic == 2)
10922 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10924 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10927 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10929 "&& TARGET_TLS_MARKERS"
10930 [(set (match_dup 0)
10931 (unspec:TLSmode [(match_dup 1)]
10933 (parallel [(set (match_dup 0)
10934 (call (mem:TLSmode (match_dup 2))
10936 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10937 (clobber (reg:SI LR_REGNO))])]
10939 [(set_attr "length" "8")])
10941 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10942 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10943 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10945 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10946 "addi %0,%1,%&@got@tlsld"
10947 "&& TARGET_CMODEL != CMODEL_SMALL"
10948 [(set (match_dup 2)
10950 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10952 (lo_sum:TLSmode (match_dup 2)
10953 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10956 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10958 [(set (attr "length")
10959 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10963 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10964 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10966 (unspec:TLSmode [(const_int 0)
10967 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10969 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10970 "addis %0,%1,%&@got@tlsld@ha"
10971 [(set_attr "length" "4")])
10973 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10974 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10975 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10976 (unspec:TLSmode [(const_int 0)
10977 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10979 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10980 "addi %0,%1,%&@got@tlsld@l"
10981 [(set_attr "length" "4")])
10983 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10984 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10985 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10986 (match_operand 2 "" "g")))
10987 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10988 (clobber (reg:SI LR_REGNO))]
10989 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10990 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10991 "bl %z1(%&@tlsld)\;nop"
10992 [(set_attr "type" "branch")
10993 (set_attr "length" "8")])
10995 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10996 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10997 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10998 (match_operand 2 "" "g")))
10999 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11000 (clobber (reg:SI LR_REGNO))]
11001 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11005 if (TARGET_SECURE_PLT && flag_pic == 2)
11006 return "bl %z1+32768(%&@tlsld)@plt";
11007 return "bl %z1(%&@tlsld)@plt";
11009 return "bl %z1(%&@tlsld)";
11011 [(set_attr "type" "branch")
11012 (set_attr "length" "4")])
11014 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11015 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11016 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11017 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11018 UNSPEC_TLSDTPREL))]
11020 "addi %0,%1,%2@dtprel")
11022 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11023 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11024 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11025 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11026 UNSPEC_TLSDTPRELHA))]
11028 "addis %0,%1,%2@dtprel@ha")
11030 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11031 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11032 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11033 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11034 UNSPEC_TLSDTPRELLO))]
11036 "addi %0,%1,%2@dtprel@l")
11038 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11039 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11040 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11041 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11042 UNSPEC_TLSGOTDTPREL))]
11044 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11045 "&& TARGET_CMODEL != CMODEL_SMALL"
11046 [(set (match_dup 3)
11048 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
11050 (lo_sum:TLSmode (match_dup 3)
11051 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11054 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11056 [(set (attr "length")
11057 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11061 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11062 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11064 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11065 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11066 UNSPEC_TLSGOTDTPREL)))]
11067 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11068 "addis %0,%1,%2@got@dtprel@ha"
11069 [(set_attr "length" "4")])
11071 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11072 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11073 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11074 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11075 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11076 UNSPEC_TLSGOTDTPREL)))]
11077 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11078 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11079 [(set_attr "length" "4")])
11081 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11082 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11083 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11084 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11087 "addi %0,%1,%2@tprel")
11089 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11090 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11091 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11092 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11093 UNSPEC_TLSTPRELHA))]
11095 "addis %0,%1,%2@tprel@ha")
11097 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11098 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11099 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11100 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11101 UNSPEC_TLSTPRELLO))]
11103 "addi %0,%1,%2@tprel@l")
11105 ;; "b" output constraint here and on tls_tls input to support linker tls
11106 ;; optimization. The linker may edit the instructions emitted by a
11107 ;; tls_got_tprel/tls_tls pair to addis,addi.
11108 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11109 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11110 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11111 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11112 UNSPEC_TLSGOTTPREL))]
11114 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11115 "&& TARGET_CMODEL != CMODEL_SMALL"
11116 [(set (match_dup 3)
11118 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
11120 (lo_sum:TLSmode (match_dup 3)
11121 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11124 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11126 [(set (attr "length")
11127 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11131 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11132 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11134 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11135 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11136 UNSPEC_TLSGOTTPREL)))]
11137 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11138 "addis %0,%1,%2@got@tprel@ha"
11139 [(set_attr "length" "4")])
11141 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11142 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11143 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11144 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11145 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11146 UNSPEC_TLSGOTTPREL)))]
11147 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11148 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11149 [(set_attr "length" "4")])
11151 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11152 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11153 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11154 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11156 "TARGET_ELF && HAVE_AS_TLS"
11157 "add %0,%1,%2@tls")
11159 (define_expand "tls_get_tpointer"
11160 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11161 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
11162 "TARGET_XCOFF && HAVE_AS_TLS"
11165 emit_insn (gen_tls_get_tpointer_internal ());
11166 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
11170 (define_insn "tls_get_tpointer_internal"
11172 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
11173 (clobber (reg:SI LR_REGNO))]
11174 "TARGET_XCOFF && HAVE_AS_TLS"
11175 "bla __get_tpointer")
11177 (define_expand "tls_get_addr<mode>"
11178 [(set (match_operand:P 0 "gpc_reg_operand" "")
11179 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
11180 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
11181 "TARGET_XCOFF && HAVE_AS_TLS"
11184 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
11185 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
11186 emit_insn (gen_tls_get_addr_internal<mode> ());
11187 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
11191 (define_insn "tls_get_addr_internal<mode>"
11193 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
11194 (clobber (reg:P 0))
11195 (clobber (reg:P 4))
11196 (clobber (reg:P 5))
11197 (clobber (reg:P 11))
11198 (clobber (reg:CC CR0_REGNO))
11199 (clobber (reg:P LR_REGNO))]
11200 "TARGET_XCOFF && HAVE_AS_TLS"
11201 "bla __tls_get_addr")
11203 ;; Next come insns related to the calling sequence.
11205 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11206 ;; We move the back-chain and decrement the stack pointer.
11208 (define_expand "allocate_stack"
11209 [(set (match_operand 0 "gpc_reg_operand" "")
11210 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11212 (minus (reg 1) (match_dup 1)))]
11215 { rtx chain = gen_reg_rtx (Pmode);
11216 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11218 rtx insn, par, set, mem;
11220 emit_move_insn (chain, stack_bot);
11222 /* Check stack bounds if necessary. */
11223 if (crtl->limit_stack)
11226 available = expand_binop (Pmode, sub_optab,
11227 stack_pointer_rtx, stack_limit_rtx,
11228 NULL_RTX, 1, OPTAB_WIDEN);
11229 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11232 if (GET_CODE (operands[1]) != CONST_INT
11233 || INTVAL (operands[1]) < -32767
11234 || INTVAL (operands[1]) > 32768)
11236 neg_op0 = gen_reg_rtx (Pmode);
11238 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11240 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11243 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11245 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11246 : gen_movdi_di_update_stack))
11247 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11249 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11250 it now and set the alias set/attributes. The above gen_*_update
11251 calls will generate a PARALLEL with the MEM set being the first
11253 par = PATTERN (insn);
11254 gcc_assert (GET_CODE (par) == PARALLEL);
11255 set = XVECEXP (par, 0, 0);
11256 gcc_assert (GET_CODE (set) == SET);
11257 mem = SET_DEST (set);
11258 gcc_assert (MEM_P (mem));
11259 MEM_NOTRAP_P (mem) = 1;
11260 set_mem_alias_set (mem, get_frame_alias_set ());
11262 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11266 ;; These patterns say how to save and restore the stack pointer. We need not
11267 ;; save the stack pointer at function level since we are careful to
11268 ;; preserve the backchain. At block level, we have to restore the backchain
11269 ;; when we restore the stack pointer.
11271 ;; For nonlocal gotos, we must save both the stack pointer and its
11272 ;; backchain and restore both. Note that in the nonlocal case, the
11273 ;; save area is a memory location.
11275 (define_expand "save_stack_function"
11276 [(match_operand 0 "any_operand" "")
11277 (match_operand 1 "any_operand" "")]
11281 (define_expand "restore_stack_function"
11282 [(match_operand 0 "any_operand" "")
11283 (match_operand 1 "any_operand" "")]
11287 ;; Adjust stack pointer (op0) to a new value (op1).
11288 ;; First copy old stack backchain to new location, and ensure that the
11289 ;; scheduler won't reorder the sp assignment before the backchain write.
11290 (define_expand "restore_stack_block"
11291 [(set (match_dup 2) (match_dup 3))
11292 (set (match_dup 4) (match_dup 2))
11294 (set (match_operand 0 "register_operand" "")
11295 (match_operand 1 "register_operand" ""))]
11301 operands[1] = force_reg (Pmode, operands[1]);
11302 operands[2] = gen_reg_rtx (Pmode);
11303 operands[3] = gen_frame_mem (Pmode, operands[0]);
11304 operands[4] = gen_frame_mem (Pmode, operands[1]);
11305 p = rtvec_alloc (1);
11306 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11307 gen_frame_mem (BLKmode, operands[0]),
11309 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11312 (define_expand "save_stack_nonlocal"
11313 [(set (match_dup 3) (match_dup 4))
11314 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11315 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11319 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11321 /* Copy the backchain to the first word, sp to the second. */
11322 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11323 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11324 operands[3] = gen_reg_rtx (Pmode);
11325 operands[4] = gen_frame_mem (Pmode, operands[1]);
11328 (define_expand "restore_stack_nonlocal"
11329 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11330 (set (match_dup 3) (match_dup 4))
11331 (set (match_dup 5) (match_dup 2))
11333 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11337 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11340 /* Restore the backchain from the first word, sp from the second. */
11341 operands[2] = gen_reg_rtx (Pmode);
11342 operands[3] = gen_reg_rtx (Pmode);
11343 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11344 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11345 operands[5] = gen_frame_mem (Pmode, operands[3]);
11346 p = rtvec_alloc (1);
11347 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11348 gen_frame_mem (BLKmode, operands[0]),
11350 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11353 ;; TOC register handling.
11355 ;; Code to initialize the TOC register...
11357 (define_insn "load_toc_aix_si"
11358 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11359 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11360 (use (reg:SI 2))])]
11361 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
11365 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11366 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11367 operands[2] = gen_rtx_REG (Pmode, 2);
11368 return \"lwz %0,%1(%2)\";
11370 [(set_attr "type" "load")
11371 (set_attr "update" "no")
11372 (set_attr "indexed" "no")])
11374 (define_insn "load_toc_aix_di"
11375 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11376 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11377 (use (reg:DI 2))])]
11378 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
11382 #ifdef TARGET_RELOCATABLE
11383 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11384 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11386 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11389 strcat (buf, \"@toc\");
11390 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11391 operands[2] = gen_rtx_REG (Pmode, 2);
11392 return \"ld %0,%1(%2)\";
11394 [(set_attr "type" "load")
11395 (set_attr "update" "no")
11396 (set_attr "indexed" "no")])
11398 (define_insn "load_toc_v4_pic_si"
11399 [(set (reg:SI LR_REGNO)
11400 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11401 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11402 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11403 [(set_attr "type" "branch")
11404 (set_attr "length" "4")])
11406 (define_expand "load_toc_v4_PIC_1"
11407 [(parallel [(set (reg:SI LR_REGNO)
11408 (match_operand:SI 0 "immediate_operand" "s"))
11409 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11410 "TARGET_ELF && DEFAULT_ABI == ABI_V4
11411 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11414 (define_insn "load_toc_v4_PIC_1_normal"
11415 [(set (reg:SI LR_REGNO)
11416 (match_operand:SI 0 "immediate_operand" "s"))
11417 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11418 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11419 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11420 "bcl 20,31,%0\\n%0:"
11421 [(set_attr "type" "branch")
11422 (set_attr "length" "4")])
11424 (define_insn "load_toc_v4_PIC_1_476"
11425 [(set (reg:SI LR_REGNO)
11426 (match_operand:SI 0 "immediate_operand" "s"))
11427 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11428 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11429 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11433 static char templ[32];
11435 get_ppc476_thunk_name (name);
11436 sprintf (templ, \"bl %s\\n%%0:\", name);
11439 [(set_attr "type" "branch")
11440 (set_attr "length" "4")])
11442 (define_expand "load_toc_v4_PIC_1b"
11443 [(parallel [(set (reg:SI LR_REGNO)
11444 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11445 (label_ref (match_operand 1 "" ""))]
11448 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11451 (define_insn "load_toc_v4_PIC_1b_normal"
11452 [(set (reg:SI LR_REGNO)
11453 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11454 (label_ref (match_operand 1 "" ""))]
11457 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11458 "bcl 20,31,$+8\;.long %0-$"
11459 [(set_attr "type" "branch")
11460 (set_attr "length" "8")])
11462 (define_insn "load_toc_v4_PIC_1b_476"
11463 [(set (reg:SI LR_REGNO)
11464 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11465 (label_ref (match_operand 1 "" ""))]
11468 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11472 static char templ[32];
11474 get_ppc476_thunk_name (name);
11475 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11478 [(set_attr "type" "branch")
11479 (set_attr "length" "16")])
11481 (define_insn "load_toc_v4_PIC_2"
11482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11483 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11484 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11485 (match_operand:SI 3 "immediate_operand" "s")))))]
11486 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11488 [(set_attr "type" "load")])
11490 (define_insn "load_toc_v4_PIC_3b"
11491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11492 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11494 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11495 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11496 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11497 "addis %0,%1,%2-%3@ha")
11499 (define_insn "load_toc_v4_PIC_3c"
11500 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11501 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11502 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11503 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11504 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11505 "addi %0,%1,%2-%3@l")
11507 ;; If the TOC is shared over a translation unit, as happens with all
11508 ;; the kinds of PIC that we support, we need to restore the TOC
11509 ;; pointer only when jumping over units of translation.
11510 ;; On Darwin, we need to reload the picbase.
11512 (define_expand "builtin_setjmp_receiver"
11513 [(use (label_ref (match_operand 0 "" "")))]
11514 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11515 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11516 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11520 if (DEFAULT_ABI == ABI_DARWIN)
11522 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11523 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11527 crtl->uses_pic_offset_table = 1;
11528 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11529 CODE_LABEL_NUMBER (operands[0]));
11530 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11532 emit_insn (gen_load_macho_picbase (tmplabrtx));
11533 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11534 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11538 rs6000_emit_load_toc_table (FALSE);
11542 ;; Largetoc support
11543 (define_insn "*largetoc_high"
11544 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11546 (unspec [(match_operand:DI 1 "" "")
11547 (match_operand:DI 2 "gpc_reg_operand" "b")]
11549 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11550 "addis %0,%2,%1@toc@ha")
11552 (define_insn "*largetoc_high_aix<mode>"
11553 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11555 (unspec [(match_operand:P 1 "" "")
11556 (match_operand:P 2 "gpc_reg_operand" "b")]
11558 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11559 "addis %0,%1@u(%2)")
11561 (define_insn "*largetoc_high_plus"
11562 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11565 (unspec [(match_operand:DI 1 "" "")
11566 (match_operand:DI 2 "gpc_reg_operand" "b")]
11568 (match_operand:DI 3 "add_cint_operand" "n"))))]
11569 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11570 "addis %0,%2,%1+%3@toc@ha")
11572 (define_insn "*largetoc_high_plus_aix<mode>"
11573 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11576 (unspec [(match_operand:P 1 "" "")
11577 (match_operand:P 2 "gpc_reg_operand" "b")]
11579 (match_operand:P 3 "add_cint_operand" "n"))))]
11580 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11581 "addis %0,%1+%3@u(%2)")
11583 (define_insn "*largetoc_low"
11584 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11585 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
11586 (match_operand:DI 2 "" "")))]
11587 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11592 (define_insn "*largetoc_low_aix<mode>"
11593 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11594 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
11595 (match_operand:P 2 "" "")))]
11596 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11599 (define_insn_and_split "*tocref<mode>"
11600 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11601 (match_operand:P 1 "small_toc_ref" "R"))]
11604 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
11605 [(set (match_dup 0) (high:P (match_dup 1)))
11606 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
11608 ;; Elf specific ways of loading addresses for non-PIC code.
11609 ;; The output of this could be r0, but we make a very strong
11610 ;; preference for a base register because it will usually
11611 ;; be needed there.
11612 (define_insn "elf_high"
11613 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11614 (high:SI (match_operand 1 "" "")))]
11615 "TARGET_ELF && ! TARGET_64BIT"
11618 (define_insn "elf_low"
11619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11620 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11621 (match_operand 2 "" "")))]
11622 "TARGET_ELF && ! TARGET_64BIT"
11627 ;; Call and call_value insns
11628 (define_expand "call"
11629 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11630 (match_operand 1 "" ""))
11631 (use (match_operand 2 "" ""))
11632 (clobber (reg:SI LR_REGNO))])]
11637 if (MACHOPIC_INDIRECT)
11638 operands[0] = machopic_indirect_call_target (operands[0]);
11641 gcc_assert (GET_CODE (operands[0]) == MEM);
11642 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11644 operands[0] = XEXP (operands[0], 0);
11646 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11648 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11652 if (GET_CODE (operands[0]) != SYMBOL_REF
11653 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11655 if (INTVAL (operands[2]) & CALL_LONG)
11656 operands[0] = rs6000_longcall_ref (operands[0]);
11658 switch (DEFAULT_ABI)
11662 operands[0] = force_reg (Pmode, operands[0]);
11666 gcc_unreachable ();
11671 (define_expand "call_value"
11672 [(parallel [(set (match_operand 0 "" "")
11673 (call (mem:SI (match_operand 1 "address_operand" ""))
11674 (match_operand 2 "" "")))
11675 (use (match_operand 3 "" ""))
11676 (clobber (reg:SI LR_REGNO))])]
11681 if (MACHOPIC_INDIRECT)
11682 operands[1] = machopic_indirect_call_target (operands[1]);
11685 gcc_assert (GET_CODE (operands[1]) == MEM);
11686 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11688 operands[1] = XEXP (operands[1], 0);
11690 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11692 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
11696 if (GET_CODE (operands[1]) != SYMBOL_REF
11697 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11699 if (INTVAL (operands[3]) & CALL_LONG)
11700 operands[1] = rs6000_longcall_ref (operands[1]);
11702 switch (DEFAULT_ABI)
11706 operands[1] = force_reg (Pmode, operands[1]);
11710 gcc_unreachable ();
11715 ;; Call to function in current module. No TOC pointer reload needed.
11716 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11717 ;; either the function was not prototyped, or it was prototyped as a
11718 ;; variable argument function. It is > 0 if FP registers were passed
11719 ;; and < 0 if they were not.
11721 (define_insn "*call_local32"
11722 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11723 (match_operand 1 "" "g,g"))
11724 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11725 (clobber (reg:SI LR_REGNO))]
11726 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11729 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11730 output_asm_insn (\"crxor 6,6,6\", operands);
11732 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11733 output_asm_insn (\"creqv 6,6,6\", operands);
11735 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11737 [(set_attr "type" "branch")
11738 (set_attr "length" "4,8")])
11740 (define_insn "*call_local64"
11741 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11742 (match_operand 1 "" "g,g"))
11743 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11744 (clobber (reg:SI LR_REGNO))]
11745 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11748 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11749 output_asm_insn (\"crxor 6,6,6\", operands);
11751 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11752 output_asm_insn (\"creqv 6,6,6\", operands);
11754 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11756 [(set_attr "type" "branch")
11757 (set_attr "length" "4,8")])
11759 (define_insn "*call_value_local32"
11760 [(set (match_operand 0 "" "")
11761 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11762 (match_operand 2 "" "g,g")))
11763 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11764 (clobber (reg:SI LR_REGNO))]
11765 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11768 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11769 output_asm_insn (\"crxor 6,6,6\", operands);
11771 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11772 output_asm_insn (\"creqv 6,6,6\", operands);
11774 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11776 [(set_attr "type" "branch")
11777 (set_attr "length" "4,8")])
11780 (define_insn "*call_value_local64"
11781 [(set (match_operand 0 "" "")
11782 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11783 (match_operand 2 "" "g,g")))
11784 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11785 (clobber (reg:SI LR_REGNO))]
11786 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11789 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11790 output_asm_insn (\"crxor 6,6,6\", operands);
11792 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11793 output_asm_insn (\"creqv 6,6,6\", operands);
11795 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11797 [(set_attr "type" "branch")
11798 (set_attr "length" "4,8")])
11801 ;; A function pointer under System V is just a normal pointer
11802 ;; operands[0] is the function pointer
11803 ;; operands[1] is the stack size to clean up
11804 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11805 ;; which indicates how to set cr1
11807 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11808 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11809 (match_operand 1 "" "g,g,g,g"))
11810 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11811 (clobber (reg:SI LR_REGNO))]
11812 "DEFAULT_ABI == ABI_V4
11813 || DEFAULT_ABI == ABI_DARWIN"
11815 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11816 output_asm_insn ("crxor 6,6,6", operands);
11818 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11819 output_asm_insn ("creqv 6,6,6", operands);
11823 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11824 (set_attr "length" "4,4,8,8")])
11826 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11827 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11828 (match_operand 1 "" "g,g"))
11829 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11830 (clobber (reg:SI LR_REGNO))]
11831 "(DEFAULT_ABI == ABI_DARWIN
11832 || (DEFAULT_ABI == ABI_V4
11833 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11835 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11836 output_asm_insn ("crxor 6,6,6", operands);
11838 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11839 output_asm_insn ("creqv 6,6,6", operands);
11842 return output_call(insn, operands, 0, 2);
11844 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11846 gcc_assert (!TARGET_SECURE_PLT);
11847 return "bl %z0@plt";
11853 "DEFAULT_ABI == ABI_V4
11854 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11855 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11856 [(parallel [(call (mem:SI (match_dup 0))
11858 (use (match_dup 2))
11859 (use (match_dup 3))
11860 (clobber (reg:SI LR_REGNO))])]
11862 operands[3] = pic_offset_table_rtx;
11864 [(set_attr "type" "branch,branch")
11865 (set_attr "length" "4,8")])
11867 (define_insn "*call_nonlocal_sysv_secure<mode>"
11868 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11869 (match_operand 1 "" "g,g"))
11870 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11871 (use (match_operand:SI 3 "register_operand" "r,r"))
11872 (clobber (reg:SI LR_REGNO))]
11873 "(DEFAULT_ABI == ABI_V4
11874 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11875 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11877 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11878 output_asm_insn ("crxor 6,6,6", operands);
11880 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11881 output_asm_insn ("creqv 6,6,6", operands);
11884 /* The magic 32768 offset here and in the other sysv call insns
11885 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11886 See sysv4.h:toc_section. */
11887 return "bl %z0+32768@plt";
11889 return "bl %z0@plt";
11891 [(set_attr "type" "branch,branch")
11892 (set_attr "length" "4,8")])
11894 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11895 [(set (match_operand 0 "" "")
11896 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11897 (match_operand 2 "" "g,g,g,g")))
11898 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11899 (clobber (reg:SI LR_REGNO))]
11900 "DEFAULT_ABI == ABI_V4
11901 || DEFAULT_ABI == ABI_DARWIN"
11903 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11904 output_asm_insn ("crxor 6,6,6", operands);
11906 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11907 output_asm_insn ("creqv 6,6,6", operands);
11911 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11912 (set_attr "length" "4,4,8,8")])
11914 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11915 [(set (match_operand 0 "" "")
11916 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11917 (match_operand 2 "" "g,g")))
11918 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11919 (clobber (reg:SI LR_REGNO))]
11920 "(DEFAULT_ABI == ABI_DARWIN
11921 || (DEFAULT_ABI == ABI_V4
11922 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11924 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11925 output_asm_insn ("crxor 6,6,6", operands);
11927 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11928 output_asm_insn ("creqv 6,6,6", operands);
11931 return output_call(insn, operands, 1, 3);
11933 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11935 gcc_assert (!TARGET_SECURE_PLT);
11936 return "bl %z1@plt";
11942 "DEFAULT_ABI == ABI_V4
11943 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11944 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11945 [(parallel [(set (match_dup 0)
11946 (call (mem:SI (match_dup 1))
11948 (use (match_dup 3))
11949 (use (match_dup 4))
11950 (clobber (reg:SI LR_REGNO))])]
11952 operands[4] = pic_offset_table_rtx;
11954 [(set_attr "type" "branch,branch")
11955 (set_attr "length" "4,8")])
11957 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11958 [(set (match_operand 0 "" "")
11959 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11960 (match_operand 2 "" "g,g")))
11961 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11962 (use (match_operand:SI 4 "register_operand" "r,r"))
11963 (clobber (reg:SI LR_REGNO))]
11964 "(DEFAULT_ABI == ABI_V4
11965 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11966 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11968 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11969 output_asm_insn ("crxor 6,6,6", operands);
11971 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11972 output_asm_insn ("creqv 6,6,6", operands);
11975 return "bl %z1+32768@plt";
11977 return "bl %z1@plt";
11979 [(set_attr "type" "branch,branch")
11980 (set_attr "length" "4,8")])
11983 ;; Call to AIX abi function in the same module.
11985 (define_insn "*call_local_aix<mode>"
11986 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11987 (match_operand 1 "" "g"))
11988 (clobber (reg:P LR_REGNO))]
11989 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11991 [(set_attr "type" "branch")
11992 (set_attr "length" "4")])
11994 (define_insn "*call_value_local_aix<mode>"
11995 [(set (match_operand 0 "" "")
11996 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11997 (match_operand 2 "" "g")))
11998 (clobber (reg:P LR_REGNO))]
11999 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12001 [(set_attr "type" "branch")
12002 (set_attr "length" "4")])
12004 ;; Call to AIX abi function which may be in another module.
12005 ;; Restore the TOC pointer (r2) after the call.
12007 (define_insn "*call_nonlocal_aix<mode>"
12008 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
12009 (match_operand 1 "" "g"))
12010 (clobber (reg:P LR_REGNO))]
12011 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12013 [(set_attr "type" "branch")
12014 (set_attr "length" "8")])
12016 (define_insn "*call_value_nonlocal_aix<mode>"
12017 [(set (match_operand 0 "" "")
12018 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
12019 (match_operand 2 "" "g")))
12020 (clobber (reg:P LR_REGNO))]
12021 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12023 [(set_attr "type" "branch")
12024 (set_attr "length" "8")])
12026 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12027 ;; Operand0 is the addresss of the function to call
12028 ;; Operand2 is the location in the function descriptor to load r2 from
12029 ;; Operand3 is the stack location to hold the current TOC pointer
12031 (define_insn "*call_indirect_aix<mode>"
12032 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12033 (match_operand 1 "" "g,g"))
12034 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12035 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12036 (clobber (reg:P LR_REGNO))]
12037 "DEFAULT_ABI == ABI_AIX"
12038 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12039 [(set_attr "type" "jmpreg")
12040 (set_attr "length" "12")])
12042 (define_insn "*call_value_indirect_aix<mode>"
12043 [(set (match_operand 0 "" "")
12044 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12045 (match_operand 2 "" "g,g")))
12046 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12047 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
12048 (clobber (reg:P LR_REGNO))]
12049 "DEFAULT_ABI == ABI_AIX"
12050 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12051 [(set_attr "type" "jmpreg")
12052 (set_attr "length" "12")])
12054 ;; Call to indirect functions with the ELFv2 ABI.
12055 ;; Operand0 is the addresss of the function to call
12056 ;; Operand2 is the stack location to hold the current TOC pointer
12058 (define_insn "*call_indirect_elfv2<mode>"
12059 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12060 (match_operand 1 "" "g,g"))
12061 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12062 (clobber (reg:P LR_REGNO))]
12063 "DEFAULT_ABI == ABI_ELFv2"
12064 "b%T0l\;<ptrload> 2,%2"
12065 [(set_attr "type" "jmpreg")
12066 (set_attr "length" "8")])
12068 (define_insn "*call_value_indirect_elfv2<mode>"
12069 [(set (match_operand 0 "" "")
12070 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12071 (match_operand 2 "" "g,g")))
12072 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12073 (clobber (reg:P LR_REGNO))]
12074 "DEFAULT_ABI == ABI_ELFv2"
12075 "b%T1l\;<ptrload> 2,%3"
12076 [(set_attr "type" "jmpreg")
12077 (set_attr "length" "8")])
12080 ;; Call subroutine returning any type.
12081 (define_expand "untyped_call"
12082 [(parallel [(call (match_operand 0 "" "")
12084 (match_operand 1 "" "")
12085 (match_operand 2 "" "")])]
12091 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12093 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12095 rtx set = XVECEXP (operands[2], 0, i);
12096 emit_move_insn (SET_DEST (set), SET_SRC (set));
12099 /* The optimizer does not know that the call sets the function value
12100 registers we stored in the result block. We avoid problems by
12101 claiming that all hard registers are used and clobbered at this
12103 emit_insn (gen_blockage ());
12108 ;; sibling call patterns
12109 (define_expand "sibcall"
12110 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12111 (match_operand 1 "" ""))
12112 (use (match_operand 2 "" ""))
12113 (use (reg:SI LR_REGNO))
12119 if (MACHOPIC_INDIRECT)
12120 operands[0] = machopic_indirect_call_target (operands[0]);
12123 gcc_assert (GET_CODE (operands[0]) == MEM);
12124 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12126 operands[0] = XEXP (operands[0], 0);
12128 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12130 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
12135 (define_expand "sibcall_value"
12136 [(parallel [(set (match_operand 0 "register_operand" "")
12137 (call (mem:SI (match_operand 1 "address_operand" ""))
12138 (match_operand 2 "" "")))
12139 (use (match_operand 3 "" ""))
12140 (use (reg:SI LR_REGNO))
12146 if (MACHOPIC_INDIRECT)
12147 operands[1] = machopic_indirect_call_target (operands[1]);
12150 gcc_assert (GET_CODE (operands[1]) == MEM);
12151 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12153 operands[1] = XEXP (operands[1], 0);
12155 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12157 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
12162 ;; this and similar patterns must be marked as using LR, otherwise
12163 ;; dataflow will try to delete the store into it. This is true
12164 ;; even when the actual reg to jump to is in CTR, when LR was
12165 ;; saved and restored around the PIC-setting BCL.
12166 (define_insn "*sibcall_local32"
12167 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12168 (match_operand 1 "" "g,g"))
12169 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12170 (use (reg:SI LR_REGNO))
12172 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12175 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12176 output_asm_insn (\"crxor 6,6,6\", operands);
12178 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12179 output_asm_insn (\"creqv 6,6,6\", operands);
12181 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12183 [(set_attr "type" "branch")
12184 (set_attr "length" "4,8")])
12186 (define_insn "*sibcall_local64"
12187 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12188 (match_operand 1 "" "g,g"))
12189 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12190 (use (reg:SI LR_REGNO))
12192 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12195 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12196 output_asm_insn (\"crxor 6,6,6\", operands);
12198 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12199 output_asm_insn (\"creqv 6,6,6\", operands);
12201 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12203 [(set_attr "type" "branch")
12204 (set_attr "length" "4,8")])
12206 (define_insn "*sibcall_value_local32"
12207 [(set (match_operand 0 "" "")
12208 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12209 (match_operand 2 "" "g,g")))
12210 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12211 (use (reg:SI LR_REGNO))
12213 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12216 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12217 output_asm_insn (\"crxor 6,6,6\", operands);
12219 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12220 output_asm_insn (\"creqv 6,6,6\", operands);
12222 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12224 [(set_attr "type" "branch")
12225 (set_attr "length" "4,8")])
12227 (define_insn "*sibcall_value_local64"
12228 [(set (match_operand 0 "" "")
12229 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12230 (match_operand 2 "" "g,g")))
12231 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12232 (use (reg:SI LR_REGNO))
12234 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12237 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12238 output_asm_insn (\"crxor 6,6,6\", operands);
12240 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12241 output_asm_insn (\"creqv 6,6,6\", operands);
12243 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12245 [(set_attr "type" "branch")
12246 (set_attr "length" "4,8")])
12248 (define_insn "*sibcall_nonlocal_sysv<mode>"
12249 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12250 (match_operand 1 "" ""))
12251 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12252 (use (reg:SI LR_REGNO))
12254 "(DEFAULT_ABI == ABI_DARWIN
12255 || DEFAULT_ABI == ABI_V4)
12256 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12259 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12260 output_asm_insn (\"crxor 6,6,6\", operands);
12262 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12263 output_asm_insn (\"creqv 6,6,6\", operands);
12265 if (which_alternative >= 2)
12267 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12269 gcc_assert (!TARGET_SECURE_PLT);
12270 return \"b %z0@plt\";
12275 [(set_attr "type" "branch")
12276 (set_attr "length" "4,8,4,8")])
12278 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12279 [(set (match_operand 0 "" "")
12280 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12281 (match_operand 2 "" "")))
12282 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12283 (use (reg:SI LR_REGNO))
12285 "(DEFAULT_ABI == ABI_DARWIN
12286 || DEFAULT_ABI == ABI_V4)
12287 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12290 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12291 output_asm_insn (\"crxor 6,6,6\", operands);
12293 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12294 output_asm_insn (\"creqv 6,6,6\", operands);
12296 if (which_alternative >= 2)
12298 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12300 gcc_assert (!TARGET_SECURE_PLT);
12301 return \"b %z1@plt\";
12306 [(set_attr "type" "branch")
12307 (set_attr "length" "4,8,4,8")])
12309 ;; AIX ABI sibling call patterns.
12311 (define_insn "*sibcall_aix<mode>"
12312 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12313 (match_operand 1 "" "g,g"))
12315 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12319 [(set_attr "type" "branch")
12320 (set_attr "length" "4")])
12322 (define_insn "*sibcall_value_aix<mode>"
12323 [(set (match_operand 0 "" "")
12324 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12325 (match_operand 2 "" "g,g")))
12327 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12331 [(set_attr "type" "branch")
12332 (set_attr "length" "4")])
12334 (define_expand "sibcall_epilogue"
12335 [(use (const_int 0))]
12338 if (!TARGET_SCHED_PROLOG)
12339 emit_insn (gen_blockage ());
12340 rs6000_emit_epilogue (TRUE);
12344 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12345 ;; all of memory. This blocks insns from being moved across this point.
12347 (define_insn "blockage"
12348 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12352 (define_expand "probe_stack"
12353 [(set (match_operand 0 "memory_operand" "=m")
12354 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12358 emit_insn (gen_probe_stack_di (operands[0]));
12360 emit_insn (gen_probe_stack_si (operands[0]));
12364 (define_insn "probe_stack_<mode>"
12365 [(set (match_operand:P 0 "memory_operand" "=m")
12366 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12369 operands[1] = gen_rtx_REG (Pmode, 0);
12370 return "st<wd>%U0%X0 %1,%0";
12372 [(set_attr "type" "store")
12373 (set (attr "update")
12374 (if_then_else (match_operand 0 "update_address_mem")
12375 (const_string "yes")
12376 (const_string "no")))
12377 (set (attr "indexed")
12378 (if_then_else (match_operand 0 "indexed_address_mem")
12379 (const_string "yes")
12380 (const_string "no")))
12381 (set_attr "length" "4")])
12383 (define_insn "probe_stack_range<P:mode>"
12384 [(set (match_operand:P 0 "register_operand" "=r")
12385 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12386 (match_operand:P 2 "register_operand" "r")]
12387 UNSPECV_PROBE_STACK_RANGE))]
12389 "* return output_probe_stack_range (operands[0], operands[2]);"
12390 [(set_attr "type" "three")])
12392 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12393 ;; signed & unsigned, and one type of branch.
12395 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12396 ;; insns, and branches.
12398 (define_expand "cbranch<mode>4"
12399 [(use (match_operator 0 "rs6000_cbranch_operator"
12400 [(match_operand:GPR 1 "gpc_reg_operand" "")
12401 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12402 (use (match_operand 3 ""))]
12406 /* Take care of the possibility that operands[2] might be negative but
12407 this might be a logical operation. That insn doesn't exist. */
12408 if (GET_CODE (operands[2]) == CONST_INT
12409 && INTVAL (operands[2]) < 0)
12411 operands[2] = force_reg (<MODE>mode, operands[2]);
12412 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12413 GET_MODE (operands[0]),
12414 operands[1], operands[2]);
12417 rs6000_emit_cbranch (<MODE>mode, operands);
12421 (define_expand "cbranch<mode>4"
12422 [(use (match_operator 0 "rs6000_cbranch_operator"
12423 [(match_operand:FP 1 "gpc_reg_operand" "")
12424 (match_operand:FP 2 "gpc_reg_operand" "")]))
12425 (use (match_operand 3 ""))]
12429 rs6000_emit_cbranch (<MODE>mode, operands);
12433 (define_expand "cstore<mode>4"
12434 [(use (match_operator 1 "rs6000_cbranch_operator"
12435 [(match_operand:GPR 2 "gpc_reg_operand" "")
12436 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12437 (clobber (match_operand:SI 0 "register_operand"))]
12441 /* Take care of the possibility that operands[3] might be negative but
12442 this might be a logical operation. That insn doesn't exist. */
12443 if (GET_CODE (operands[3]) == CONST_INT
12444 && INTVAL (operands[3]) < 0)
12446 operands[3] = force_reg (<MODE>mode, operands[3]);
12447 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12448 GET_MODE (operands[1]),
12449 operands[2], operands[3]);
12452 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12453 For SEQ, likewise, except that comparisons with zero should be done
12454 with an scc insns. However, due to the order that combine see the
12455 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12456 the cases we don't want to handle or are best handled by portable
12458 if (GET_CODE (operands[1]) == NE)
12460 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12461 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12462 && operands[3] == const0_rtx)
12464 rs6000_emit_sCOND (<MODE>mode, operands);
12468 (define_expand "cstore<mode>4"
12469 [(use (match_operator 1 "rs6000_cbranch_operator"
12470 [(match_operand:FP 2 "gpc_reg_operand" "")
12471 (match_operand:FP 3 "gpc_reg_operand" "")]))
12472 (clobber (match_operand:SI 0 "register_operand"))]
12476 rs6000_emit_sCOND (<MODE>mode, operands);
12481 (define_expand "stack_protect_set"
12482 [(match_operand 0 "memory_operand" "")
12483 (match_operand 1 "memory_operand" "")]
12486 #ifdef TARGET_THREAD_SSP_OFFSET
12487 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12488 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12489 operands[1] = gen_rtx_MEM (Pmode, addr);
12492 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12494 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12498 (define_insn "stack_protect_setsi"
12499 [(set (match_operand:SI 0 "memory_operand" "=m")
12500 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12501 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12503 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12504 [(set_attr "type" "three")
12505 (set_attr "length" "12")])
12507 (define_insn "stack_protect_setdi"
12508 [(set (match_operand:DI 0 "memory_operand" "=Y")
12509 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12510 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12512 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12513 [(set_attr "type" "three")
12514 (set_attr "length" "12")])
12516 (define_expand "stack_protect_test"
12517 [(match_operand 0 "memory_operand" "")
12518 (match_operand 1 "memory_operand" "")
12519 (match_operand 2 "" "")]
12522 rtx test, op0, op1;
12523 #ifdef TARGET_THREAD_SSP_OFFSET
12524 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12525 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12526 operands[1] = gen_rtx_MEM (Pmode, addr);
12529 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12530 test = gen_rtx_EQ (VOIDmode, op0, op1);
12531 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12535 (define_insn "stack_protect_testsi"
12536 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12537 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12538 (match_operand:SI 2 "memory_operand" "m,m")]
12540 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12541 (clobber (match_scratch:SI 3 "=&r,&r"))]
12544 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12545 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
12546 [(set_attr "length" "16,20")])
12548 (define_insn "stack_protect_testdi"
12549 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12550 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
12551 (match_operand:DI 2 "memory_operand" "Y,Y")]
12553 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12554 (clobber (match_scratch:DI 3 "=&r,&r"))]
12557 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12558 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
12559 [(set_attr "length" "16,20")])
12562 ;; Here are the actual compare insns.
12563 (define_insn "*cmp<mode>_internal1"
12564 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12565 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12566 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12568 "cmp<wd>%I2 %0,%1,%2"
12569 [(set_attr "type" "cmp")])
12571 ;; If we are comparing a register for equality with a large constant,
12572 ;; we can do this with an XOR followed by a compare. But this is profitable
12573 ;; only if the large constant is only used for the comparison (and in this
12574 ;; case we already have a register to reuse as scratch).
12576 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12577 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12580 [(set (match_operand:SI 0 "register_operand")
12581 (match_operand:SI 1 "logical_const_operand" ""))
12582 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12584 (match_operand:SI 2 "logical_const_operand" "")]))
12585 (set (match_operand:CC 4 "cc_reg_operand" "")
12586 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12589 (if_then_else (match_operator 6 "equality_operator"
12590 [(match_dup 4) (const_int 0)])
12591 (match_operand 7 "" "")
12592 (match_operand 8 "" "")))]
12593 "peep2_reg_dead_p (3, operands[0])
12594 && peep2_reg_dead_p (4, operands[4])"
12595 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12596 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12597 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12600 /* Get the constant we are comparing against, and see what it looks like
12601 when sign-extended from 16 to 32 bits. Then see what constant we could
12602 XOR with SEXTC to get the sign-extended value. */
12603 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12605 operands[1], operands[2]);
12606 HOST_WIDE_INT c = INTVAL (cnst);
12607 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12608 HOST_WIDE_INT xorv = c ^ sextc;
12610 operands[9] = GEN_INT (xorv);
12611 operands[10] = GEN_INT (sextc);
12614 (define_insn "*cmpsi_internal2"
12615 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12616 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12617 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12619 "cmplw%I2 %0,%1,%b2"
12620 [(set_attr "type" "cmp")])
12622 (define_insn "*cmpdi_internal2"
12623 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12624 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12625 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12627 "cmpld%I2 %0,%1,%b2"
12628 [(set_attr "type" "cmp")])
12630 ;; The following two insns don't exist as single insns, but if we provide
12631 ;; them, we can swap an add and compare, which will enable us to overlap more
12632 ;; of the required delay between a compare and branch. We generate code for
12633 ;; them by splitting.
12636 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12637 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12638 (match_operand:SI 2 "short_cint_operand" "i")))
12639 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12640 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12643 [(set_attr "length" "8")])
12646 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12647 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12648 (match_operand:SI 2 "u_short_cint_operand" "i")))
12649 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12650 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12653 [(set_attr "length" "8")])
12656 [(set (match_operand:CC 3 "cc_reg_operand" "")
12657 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12658 (match_operand:SI 2 "short_cint_operand" "")))
12659 (set (match_operand:SI 0 "gpc_reg_operand" "")
12660 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12662 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12663 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12666 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12667 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12668 (match_operand:SI 2 "u_short_cint_operand" "")))
12669 (set (match_operand:SI 0 "gpc_reg_operand" "")
12670 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12672 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12673 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12675 ;; Only need to compare second words if first words equal
12676 (define_insn "*cmptf_internal1"
12677 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12678 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12679 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12680 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12681 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12682 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12683 [(set_attr "type" "fpcompare")
12684 (set_attr "length" "12")])
12686 (define_insn_and_split "*cmptf_internal2"
12687 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12688 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12689 (match_operand:TF 2 "gpc_reg_operand" "d")))
12690 (clobber (match_scratch:DF 3 "=d"))
12691 (clobber (match_scratch:DF 4 "=d"))
12692 (clobber (match_scratch:DF 5 "=d"))
12693 (clobber (match_scratch:DF 6 "=d"))
12694 (clobber (match_scratch:DF 7 "=d"))
12695 (clobber (match_scratch:DF 8 "=d"))
12696 (clobber (match_scratch:DF 9 "=d"))
12697 (clobber (match_scratch:DF 10 "=d"))
12698 (clobber (match_scratch:GPR 11 "=b"))]
12699 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12700 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12702 "&& reload_completed"
12703 [(set (match_dup 3) (match_dup 14))
12704 (set (match_dup 4) (match_dup 15))
12705 (set (match_dup 9) (abs:DF (match_dup 5)))
12706 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12707 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12708 (label_ref (match_dup 12))
12710 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12711 (set (pc) (label_ref (match_dup 13)))
12713 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12714 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12715 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12716 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12719 REAL_VALUE_TYPE rv;
12720 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
12721 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
12723 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12724 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12725 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12726 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12727 operands[12] = gen_label_rtx ();
12728 operands[13] = gen_label_rtx ();
12730 operands[14] = force_const_mem (DFmode,
12731 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12732 operands[15] = force_const_mem (DFmode,
12733 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12738 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12739 operands[14] = gen_const_mem (DFmode, tocref);
12740 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12741 operands[15] = gen_const_mem (DFmode, tocref);
12742 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12743 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12747 ;; Now we have the scc insns. We can do some combinations because of the
12748 ;; way the machine works.
12750 ;; Note that this is probably faster if we can put an insn between the
12751 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12752 ;; cases the insns below which don't use an intermediate CR field will
12753 ;; be used instead.
12755 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12756 (match_operator:SI 1 "scc_comparison_operator"
12757 [(match_operand 2 "cc_reg_operand" "y")
12760 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12761 [(set (attr "type")
12762 (cond [(match_test "TARGET_MFCRF")
12763 (const_string "mfcrf")
12765 (const_string "mfcr")))
12766 (set_attr "length" "8")])
12768 ;; Same as above, but get the GT bit.
12769 (define_insn "move_from_CR_gt_bit"
12770 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12771 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12772 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12773 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
12774 [(set_attr "type" "mfcr")
12775 (set_attr "length" "8")])
12777 ;; Same as above, but get the OV/ORDERED bit.
12778 (define_insn "move_from_CR_ov_bit"
12779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12780 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
12783 "mfcr %0\;rlwinm %0,%0,%t1,1"
12784 [(set_attr "type" "mfcr")
12785 (set_attr "length" "8")])
12788 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12789 (match_operator:DI 1 "scc_comparison_operator"
12790 [(match_operand 2 "cc_reg_operand" "y")
12793 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12794 [(set (attr "type")
12795 (cond [(match_test "TARGET_MFCRF")
12796 (const_string "mfcrf")
12798 (const_string "mfcr")))
12799 (set_attr "length" "8")])
12802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12803 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12804 [(match_operand 2 "cc_reg_operand" "y,y")
12807 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12808 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12811 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
12813 [(set_attr "type" "shift")
12814 (set_attr "dot" "yes")
12815 (set_attr "length" "8,16")])
12818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12819 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12820 [(match_operand 2 "cc_reg_operand" "")
12823 (set (match_operand:SI 3 "gpc_reg_operand" "")
12824 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12825 "TARGET_32BIT && reload_completed"
12826 [(set (match_dup 3)
12827 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12829 (compare:CC (match_dup 3)
12834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12835 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12836 [(match_operand 2 "cc_reg_operand" "y")
12838 (match_operand:SI 3 "const_int_operand" "n")))]
12842 int is_bit = ccr_bit (operands[1], 1);
12843 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12846 if (is_bit >= put_bit)
12847 count = is_bit - put_bit;
12849 count = 32 - (put_bit - is_bit);
12851 operands[4] = GEN_INT (count);
12852 operands[5] = GEN_INT (put_bit);
12854 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
12856 [(set (attr "type")
12857 (cond [(match_test "TARGET_MFCRF")
12858 (const_string "mfcrf")
12860 (const_string "mfcr")))
12861 (set_attr "length" "8")])
12864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12866 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12867 [(match_operand 2 "cc_reg_operand" "y,y")
12869 (match_operand:SI 3 "const_int_operand" "n,n"))
12871 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12872 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12877 int is_bit = ccr_bit (operands[1], 1);
12878 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12881 /* Force split for non-cc0 compare. */
12882 if (which_alternative == 1)
12885 if (is_bit >= put_bit)
12886 count = is_bit - put_bit;
12888 count = 32 - (put_bit - is_bit);
12890 operands[5] = GEN_INT (count);
12891 operands[6] = GEN_INT (put_bit);
12893 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12895 [(set_attr "type" "shift")
12896 (set_attr "dot" "yes")
12897 (set_attr "length" "8,16")])
12900 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12902 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12903 [(match_operand 2 "cc_reg_operand" "")
12905 (match_operand:SI 3 "const_int_operand" ""))
12907 (set (match_operand:SI 4 "gpc_reg_operand" "")
12908 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12911 [(set (match_dup 4)
12912 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12915 (compare:CC (match_dup 4)
12919 ;; There is a 3 cycle delay between consecutive mfcr instructions
12920 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12924 (match_operator:SI 1 "scc_comparison_operator"
12925 [(match_operand 2 "cc_reg_operand" "y")
12927 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12928 (match_operator:SI 4 "scc_comparison_operator"
12929 [(match_operand 5 "cc_reg_operand" "y")
12931 "REGNO (operands[2]) != REGNO (operands[5])"
12932 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12933 [(set_attr "type" "mfcr")
12934 (set_attr "length" "12")])
12937 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12938 (match_operator:DI 1 "scc_comparison_operator"
12939 [(match_operand 2 "cc_reg_operand" "y")
12941 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12942 (match_operator:DI 4 "scc_comparison_operator"
12943 [(match_operand 5 "cc_reg_operand" "y")
12945 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12946 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12947 [(set_attr "type" "mfcr")
12948 (set_attr "length" "12")])
12950 ;; There are some scc insns that can be done directly, without a compare.
12951 ;; These are faster because they don't involve the communications between
12952 ;; the FXU and branch units. In fact, we will be replacing all of the
12953 ;; integer scc insns here or in the portable methods in emit_store_flag.
12955 ;; Also support (neg (scc ..)) since that construct is used to replace
12956 ;; branches, (plus (scc ..) ..) since that construct is common and
12957 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12958 ;; cases where it is no more expensive than (neg (scc ..)).
12960 ;; Have reload force a constant into a register for the simple insns that
12961 ;; otherwise won't accept constants. We do this because it is faster than
12962 ;; the cmp/mfcr sequence we would otherwise generate.
12964 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12967 (define_insn_and_split "*eq<mode>"
12968 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12969 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12970 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12974 [(set (match_dup 0)
12975 (clz:GPR (match_dup 3)))
12977 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12979 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12981 /* Use output operand as intermediate. */
12982 operands[3] = operands[0];
12984 if (logical_operand (operands[2], <MODE>mode))
12985 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12986 gen_rtx_XOR (<MODE>mode,
12987 operands[1], operands[2])));
12989 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12990 gen_rtx_PLUS (<MODE>mode, operands[1],
12991 negate_rtx (<MODE>mode,
12995 operands[3] = operands[1];
12997 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13000 (define_insn_and_split "*eq<mode>_compare"
13001 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13003 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13004 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13006 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13007 (eq:P (match_dup 1) (match_dup 2)))]
13011 [(set (match_dup 0)
13012 (clz:P (match_dup 4)))
13013 (parallel [(set (match_dup 3)
13014 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13017 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13019 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13021 /* Use output operand as intermediate. */
13022 operands[4] = operands[0];
13024 if (logical_operand (operands[2], <MODE>mode))
13025 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13026 gen_rtx_XOR (<MODE>mode,
13027 operands[1], operands[2])));
13029 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13030 gen_rtx_PLUS (<MODE>mode, operands[1],
13031 negate_rtx (<MODE>mode,
13035 operands[4] = operands[1];
13037 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13040 ;; We have insns of the form shown by the first define_insn below. If
13041 ;; there is something inside the comparison operation, we must split it.
13043 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13044 (plus:SI (match_operator 1 "comparison_operator"
13045 [(match_operand:SI 2 "" "")
13046 (match_operand:SI 3
13047 "reg_or_cint_operand" "")])
13048 (match_operand:SI 4 "gpc_reg_operand" "")))
13049 (clobber (match_operand:SI 5 "register_operand" ""))]
13050 "! gpc_reg_operand (operands[2], SImode)"
13051 [(set (match_dup 5) (match_dup 2))
13052 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
13055 (define_insn "*plus_eqsi"
13056 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13057 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13058 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13059 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13062 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
13063 subfic %0,%1,0\;addze %0,%3
13064 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
13065 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
13066 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
13067 [(set_attr "type" "three,two,three,three,three")
13068 (set_attr "length" "12,8,12,12,12")])
13070 (define_insn "*compare_plus_eqsi"
13071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13074 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13075 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13076 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13078 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13079 "TARGET_32BIT && optimize_size"
13081 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13082 subfic %4,%1,0\;addze. %4,%3
13083 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
13084 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
13085 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13091 [(set_attr "type" "compare")
13092 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13095 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13098 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13099 (match_operand:SI 2 "scc_eq_operand" ""))
13100 (match_operand:SI 3 "gpc_reg_operand" ""))
13102 (clobber (match_scratch:SI 4 ""))]
13103 "TARGET_32BIT && optimize_size && reload_completed"
13104 [(set (match_dup 4)
13105 (plus:SI (eq:SI (match_dup 1)
13109 (compare:CC (match_dup 4)
13113 (define_insn "*plus_eqsi_compare"
13114 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13117 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13118 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13119 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13121 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13122 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13123 "TARGET_32BIT && optimize_size"
13125 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13126 subfic %0,%1,0\;addze. %0,%3
13127 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
13128 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
13129 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13135 [(set_attr "type" "compare")
13136 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13139 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13142 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13143 (match_operand:SI 2 "scc_eq_operand" ""))
13144 (match_operand:SI 3 "gpc_reg_operand" ""))
13146 (set (match_operand:SI 0 "gpc_reg_operand" "")
13147 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13148 "TARGET_32BIT && optimize_size && reload_completed"
13149 [(set (match_dup 0)
13150 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13152 (compare:CC (match_dup 0)
13156 (define_insn "*neg_eq0<mode>"
13157 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13158 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13161 "addic %0,%1,-1\;subfe %0,%0,%0"
13162 [(set_attr "type" "two")
13163 (set_attr "length" "8")])
13165 (define_insn_and_split "*neg_eq<mode>"
13166 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13167 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13168 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13172 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13174 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13176 /* Use output operand as intermediate. */
13177 operands[3] = operands[0];
13179 if (logical_operand (operands[2], <MODE>mode))
13180 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13181 gen_rtx_XOR (<MODE>mode,
13182 operands[1], operands[2])));
13184 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13185 gen_rtx_PLUS (<MODE>mode, operands[1],
13186 negate_rtx (<MODE>mode,
13190 operands[3] = operands[1];
13193 (define_insn "*ne0_<mode>"
13194 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13195 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13197 (clobber (match_scratch:P 2 "=&r"))]
13198 "!(TARGET_32BIT && TARGET_ISEL)"
13199 "addic %2,%1,-1\;subfe %0,%2,%1"
13200 [(set_attr "type" "two")
13201 (set_attr "length" "8")])
13203 (define_insn "*plus_ne0_<mode>"
13204 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13205 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13207 (match_operand:P 2 "gpc_reg_operand" "r")))
13208 (clobber (match_scratch:P 3 "=&r"))]
13210 "addic %3,%1,-1\;addze %0,%2"
13211 [(set_attr "type" "two")
13212 (set_attr "length" "8")])
13214 (define_insn "*compare_plus_ne0_<mode>"
13215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13216 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13218 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13220 (clobber (match_scratch:P 3 "=&r,&r"))
13221 (clobber (match_scratch:P 4 "=X,&r"))]
13224 addic %3,%1,-1\;addze. %3,%2
13226 [(set_attr "type" "compare")
13227 (set_attr "length" "8,12")])
13230 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13231 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13233 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13234 (clobber (match_scratch:P 3 ""))
13235 (clobber (match_scratch:P 4 ""))]
13237 [(parallel [(set (match_dup 3)
13238 (plus:P (ne:P (match_dup 1)
13241 (clobber (match_dup 4))])
13243 (compare:CC (match_dup 3)
13248 (define_insn "*compare_plus_ne0_<mode>_1"
13249 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13250 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13252 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13253 (clobber (match_scratch:P 3 "=&r,&r"))
13254 (clobber (match_scratch:P 4 "=X,&r"))]
13257 addic %3,%1,-1\;addze. %3,%2
13259 [(set_attr "type" "compare")
13260 (set_attr "length" "8,12")])
13263 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13264 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13266 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13267 (clobber (match_scratch:P 3 ""))
13268 (clobber (match_scratch:P 4 ""))]
13270 [(parallel [(set (match_dup 3)
13271 (plus:P (ne:P (match_dup 1)
13274 (clobber (match_dup 4))])
13276 (compare:CC (match_dup 3)
13280 (define_insn "*plus_ne0_<mode>_compare"
13281 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13283 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13285 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13287 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13288 (plus:P (ne:P (match_dup 1)
13291 (clobber (match_scratch:P 3 "=&r,&r"))]
13294 addic %3,%1,-1\;addze. %0,%2
13296 [(set_attr "type" "compare")
13297 (set_attr "length" "8,12")])
13300 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13302 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13304 (match_operand:P 2 "gpc_reg_operand" ""))
13306 (set (match_operand:P 0 "gpc_reg_operand" "")
13307 (plus:P (ne:P (match_dup 1)
13310 (clobber (match_scratch:P 3 ""))]
13312 [(parallel [(set (match_dup 0)
13313 (plus:P (ne:P (match_dup 1)
13316 (clobber (match_dup 3))])
13318 (compare:CC (match_dup 0)
13322 (define_insn "*leu<mode>"
13323 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13324 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13325 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13327 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13328 [(set_attr "type" "three")
13329 (set_attr "length" "12")])
13331 (define_insn "*leu<mode>_compare"
13332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13334 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13335 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13337 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13338 (leu:P (match_dup 1) (match_dup 2)))]
13341 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13343 [(set_attr "type" "compare")
13344 (set_attr "length" "12,16")])
13347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13349 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13350 (match_operand:P 2 "reg_or_short_operand" ""))
13352 (set (match_operand:P 0 "gpc_reg_operand" "")
13353 (leu:P (match_dup 1) (match_dup 2)))]
13355 [(set (match_dup 0)
13356 (leu:P (match_dup 1) (match_dup 2)))
13358 (compare:CC (match_dup 0)
13362 (define_insn "*plus_leu<mode>"
13363 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13364 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13365 (match_operand:P 2 "reg_or_short_operand" "rI"))
13366 (match_operand:P 3 "gpc_reg_operand" "r")))]
13368 "subf%I2c %0,%1,%2\;addze %0,%3"
13369 [(set_attr "type" "two")
13370 (set_attr "length" "8")])
13373 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13375 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13376 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13377 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13379 (clobber (match_scratch:SI 4 "=&r,&r"))]
13382 subf%I2c %4,%1,%2\;addze. %4,%3
13384 [(set_attr "type" "compare")
13385 (set_attr "length" "8,12")])
13388 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13390 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13391 (match_operand:SI 2 "reg_or_short_operand" ""))
13392 (match_operand:SI 3 "gpc_reg_operand" ""))
13394 (clobber (match_scratch:SI 4 ""))]
13395 "TARGET_32BIT && reload_completed"
13396 [(set (match_dup 4)
13397 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13400 (compare:CC (match_dup 4)
13405 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13407 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13408 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13409 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13411 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13412 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13415 subf%I2c %0,%1,%2\;addze. %0,%3
13417 [(set_attr "type" "compare")
13418 (set_attr "length" "8,12")])
13421 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13423 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13424 (match_operand:SI 2 "reg_or_short_operand" ""))
13425 (match_operand:SI 3 "gpc_reg_operand" ""))
13427 (set (match_operand:SI 0 "gpc_reg_operand" "")
13428 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13429 "TARGET_32BIT && reload_completed"
13430 [(set (match_dup 0)
13431 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13433 (compare:CC (match_dup 0)
13437 (define_insn "*neg_leu<mode>"
13438 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13439 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13440 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13442 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13443 [(set_attr "type" "three")
13444 (set_attr "length" "12")])
13446 (define_insn "*and_neg_leu<mode>"
13447 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13449 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13450 (match_operand:P 2 "reg_or_short_operand" "rI")))
13451 (match_operand:P 3 "gpc_reg_operand" "r")))]
13453 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13454 [(set_attr "type" "three")
13455 (set_attr "length" "12")])
13458 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13461 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13462 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13463 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13465 (clobber (match_scratch:SI 4 "=&r,&r"))]
13468 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13470 [(set_attr "type" "compare")
13471 (set_attr "length" "12,16")])
13474 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13477 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13478 (match_operand:SI 2 "reg_or_short_operand" "")))
13479 (match_operand:SI 3 "gpc_reg_operand" ""))
13481 (clobber (match_scratch:SI 4 ""))]
13482 "TARGET_32BIT && reload_completed"
13483 [(set (match_dup 4)
13484 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13487 (compare:CC (match_dup 4)
13492 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13495 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13496 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13497 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13499 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13500 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13503 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13505 [(set_attr "type" "compare")
13506 (set_attr "length" "12,16")])
13509 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13512 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13513 (match_operand:SI 2 "reg_or_short_operand" "")))
13514 (match_operand:SI 3 "gpc_reg_operand" ""))
13516 (set (match_operand:SI 0 "gpc_reg_operand" "")
13517 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13518 "TARGET_32BIT && reload_completed"
13519 [(set (match_dup 0)
13520 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13523 (compare:CC (match_dup 0)
13527 (define_insn_and_split "*ltu<mode>"
13528 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13529 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13530 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13534 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13535 (set (match_dup 0) (neg:P (match_dup 0)))]
13538 (define_insn_and_split "*ltu<mode>_compare"
13539 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13541 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13542 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13544 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13545 (ltu:P (match_dup 1) (match_dup 2)))]
13549 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13550 (parallel [(set (match_dup 3)
13551 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13552 (set (match_dup 0) (neg:P (match_dup 0)))])]
13555 (define_insn_and_split "*plus_ltu<mode>"
13556 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13557 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13558 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13559 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13562 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13563 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13564 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13567 (define_insn_and_split "*plus_ltu<mode>_compare"
13568 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13570 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13571 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13572 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13574 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13575 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13578 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13579 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13580 (parallel [(set (match_dup 4)
13581 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13583 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13586 (define_insn "*neg_ltu<mode>"
13587 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13588 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13589 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13592 subfc %0,%2,%1\;subfe %0,%0,%0
13593 addic %0,%1,%n2\;subfe %0,%0,%0"
13594 [(set_attr "type" "two")
13595 (set_attr "length" "8")])
13597 (define_insn "*geu<mode>"
13598 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13599 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13600 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13603 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
13604 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
13605 [(set_attr "type" "three")
13606 (set_attr "length" "12")])
13608 (define_insn "*geu<mode>_compare"
13609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13611 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13612 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13614 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13615 (geu:P (match_dup 1) (match_dup 2)))]
13618 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13619 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13622 [(set_attr "type" "compare")
13623 (set_attr "length" "12,12,16,16")])
13626 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13628 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13629 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13631 (set (match_operand:P 0 "gpc_reg_operand" "")
13632 (geu:P (match_dup 1) (match_dup 2)))]
13634 [(set (match_dup 0)
13635 (geu:P (match_dup 1) (match_dup 2)))
13637 (compare:CC (match_dup 0)
13641 (define_insn "*plus_geu<mode>"
13642 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13643 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13644 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13645 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13648 subfc %0,%2,%1\;addze %0,%3
13649 addic %0,%1,%n2\;addze %0,%3"
13650 [(set_attr "type" "two")
13651 (set_attr "length" "8")])
13654 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13656 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13657 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13658 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13660 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13663 subfc %4,%2,%1\;addze. %4,%3
13664 addic %4,%1,%n2\;addze. %4,%3
13667 [(set_attr "type" "compare")
13668 (set_attr "length" "8,8,12,12")])
13671 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13673 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13674 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13675 (match_operand:SI 3 "gpc_reg_operand" ""))
13677 (clobber (match_scratch:SI 4 ""))]
13678 "TARGET_32BIT && reload_completed"
13679 [(set (match_dup 4)
13680 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13683 (compare:CC (match_dup 4)
13688 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13690 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13691 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13692 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13694 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13695 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13698 subfc %0,%2,%1\;addze. %0,%3
13699 addic %0,%1,%n2\;addze. %0,%3
13702 [(set_attr "type" "compare")
13703 (set_attr "length" "8,8,12,12")])
13706 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13708 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13709 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13710 (match_operand:SI 3 "gpc_reg_operand" ""))
13712 (set (match_operand:SI 0 "gpc_reg_operand" "")
13713 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13714 "TARGET_32BIT && reload_completed"
13715 [(set (match_dup 0)
13716 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13718 (compare:CC (match_dup 0)
13722 (define_insn "*neg_geu<mode>"
13723 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13724 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13725 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13728 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
13729 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
13730 [(set_attr "type" "three")
13731 (set_attr "length" "12")])
13733 (define_insn "*and_neg_geu<mode>"
13734 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13736 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13737 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13738 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13741 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
13742 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
13743 [(set_attr "type" "three")
13744 (set_attr "length" "12")])
13747 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13750 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13751 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13752 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13754 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13757 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
13758 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
13761 [(set_attr "type" "compare")
13762 (set_attr "length" "12,12,16,16")])
13765 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13768 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13769 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13770 (match_operand:SI 3 "gpc_reg_operand" ""))
13772 (clobber (match_scratch:SI 4 ""))]
13773 "TARGET_32BIT && reload_completed"
13774 [(set (match_dup 4)
13775 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13778 (compare:CC (match_dup 4)
13783 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13786 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13787 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13788 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13790 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13791 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13794 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
13795 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
13798 [(set_attr "type" "compare")
13799 (set_attr "length" "12,12,16,16")])
13802 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13805 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13806 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13807 (match_operand:SI 3 "gpc_reg_operand" ""))
13809 (set (match_operand:SI 0 "gpc_reg_operand" "")
13810 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13811 "TARGET_32BIT && reload_completed"
13812 [(set (match_dup 0)
13813 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13815 (compare:CC (match_dup 0)
13819 (define_insn "*plus_gt0<mode>"
13820 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13821 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13823 (match_operand:P 2 "gpc_reg_operand" "r")))]
13825 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13826 [(set_attr "type" "three")
13827 (set_attr "length" "12")])
13830 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13832 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13834 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13836 (clobber (match_scratch:SI 3 "=&r,&r"))]
13839 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13841 [(set_attr "type" "compare")
13842 (set_attr "length" "12,16")])
13845 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13847 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13849 (match_operand:SI 2 "gpc_reg_operand" ""))
13851 (clobber (match_scratch:SI 3 ""))]
13852 "TARGET_32BIT && reload_completed"
13853 [(set (match_dup 3)
13854 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13857 (compare:CC (match_dup 3)
13862 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13864 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13866 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13868 (clobber (match_scratch:DI 3 "=&r,&r"))]
13871 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13873 [(set_attr "type" "compare")
13874 (set_attr "length" "12,16")])
13877 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13879 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13881 (match_operand:DI 2 "gpc_reg_operand" ""))
13883 (clobber (match_scratch:DI 3 ""))]
13884 "TARGET_64BIT && reload_completed"
13885 [(set (match_dup 3)
13886 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13889 (compare:CC (match_dup 3)
13894 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13896 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13898 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13900 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13901 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13904 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13906 [(set_attr "type" "compare")
13907 (set_attr "length" "12,16")])
13910 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13912 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13914 (match_operand:SI 2 "gpc_reg_operand" ""))
13916 (set (match_operand:SI 0 "gpc_reg_operand" "")
13917 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13918 "TARGET_32BIT && reload_completed"
13919 [(set (match_dup 0)
13920 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13922 (compare:CC (match_dup 0)
13927 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13929 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13931 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13933 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13934 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13937 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13939 [(set_attr "type" "compare")
13940 (set_attr "length" "12,16")])
13943 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13945 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13947 (match_operand:DI 2 "gpc_reg_operand" ""))
13949 (set (match_operand:DI 0 "gpc_reg_operand" "")
13950 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13951 "TARGET_64BIT && reload_completed"
13952 [(set (match_dup 0)
13953 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13955 (compare:CC (match_dup 0)
13959 (define_insn_and_split "*gtu<mode>"
13960 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13961 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13962 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13966 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13967 (set (match_dup 0) (neg:P (match_dup 0)))]
13970 (define_insn_and_split "*gtu<mode>_compare"
13971 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13973 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13974 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13976 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13977 (gtu:P (match_dup 1) (match_dup 2)))]
13981 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13982 (parallel [(set (match_dup 3)
13983 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13984 (set (match_dup 0) (neg:P (match_dup 0)))])]
13987 (define_insn_and_split "*plus_gtu<mode>"
13988 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13989 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13990 (match_operand:P 2 "reg_or_short_operand" "rI"))
13991 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13994 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13995 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13996 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13999 (define_insn_and_split "*plus_gtu<mode>_compare"
14000 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14002 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14003 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14004 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14006 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14007 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14010 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14011 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14012 (parallel [(set (match_dup 4)
14013 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14015 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14018 (define_insn "*neg_gtu<mode>"
14019 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14020 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14021 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14023 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
14024 [(set_attr "type" "two")
14025 (set_attr "length" "8")])
14028 ;; Define both directions of branch and return. If we need a reload
14029 ;; register, we'd rather use CR0 since it is much easier to copy a
14030 ;; register CC value to there.
14034 (if_then_else (match_operator 1 "branch_comparison_operator"
14036 "cc_reg_operand" "y")
14038 (label_ref (match_operand 0 "" ""))
14043 return output_cbranch (operands[1], \"%l0\", 0, insn);
14045 [(set_attr "type" "branch")])
14049 (if_then_else (match_operator 0 "branch_comparison_operator"
14051 "cc_reg_operand" "y")
14058 return output_cbranch (operands[0], NULL, 0, insn);
14060 [(set_attr "type" "jmpreg")
14061 (set_attr "length" "4")])
14065 (if_then_else (match_operator 1 "branch_comparison_operator"
14067 "cc_reg_operand" "y")
14070 (label_ref (match_operand 0 "" ""))))]
14074 return output_cbranch (operands[1], \"%l0\", 1, insn);
14076 [(set_attr "type" "branch")])
14080 (if_then_else (match_operator 0 "branch_comparison_operator"
14082 "cc_reg_operand" "y")
14089 return output_cbranch (operands[0], NULL, 1, insn);
14091 [(set_attr "type" "jmpreg")
14092 (set_attr "length" "4")])
14094 ;; Logic on condition register values.
14096 ; This pattern matches things like
14097 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14098 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14100 ; which are generated by the branch logic.
14101 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14103 (define_insn "*cceq_ior_compare"
14104 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14105 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14106 [(match_operator:SI 2
14107 "branch_positive_comparison_operator"
14109 "cc_reg_operand" "y,y")
14111 (match_operator:SI 4
14112 "branch_positive_comparison_operator"
14114 "cc_reg_operand" "0,y")
14118 "cr%q1 %E0,%j2,%j4"
14119 [(set_attr "type" "cr_logical,delayed_cr")])
14121 ; Why is the constant -1 here, but 1 in the previous pattern?
14122 ; Because ~1 has all but the low bit set.
14124 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14125 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14126 [(not:SI (match_operator:SI 2
14127 "branch_positive_comparison_operator"
14129 "cc_reg_operand" "y,y")
14131 (match_operator:SI 4
14132 "branch_positive_comparison_operator"
14134 "cc_reg_operand" "0,y")
14138 "cr%q1 %E0,%j2,%j4"
14139 [(set_attr "type" "cr_logical,delayed_cr")])
14141 (define_insn "*cceq_rev_compare"
14142 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14143 (compare:CCEQ (match_operator:SI 1
14144 "branch_positive_comparison_operator"
14146 "cc_reg_operand" "0,y")
14151 [(set_attr "type" "cr_logical,delayed_cr")])
14153 ;; If we are comparing the result of two comparisons, this can be done
14154 ;; using creqv or crxor.
14156 (define_insn_and_split ""
14157 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14158 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14159 [(match_operand 2 "cc_reg_operand" "y")
14161 (match_operator 3 "branch_comparison_operator"
14162 [(match_operand 4 "cc_reg_operand" "y")
14167 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14171 int positive_1, positive_2;
14173 positive_1 = branch_positive_comparison_operator (operands[1],
14174 GET_MODE (operands[1]));
14175 positive_2 = branch_positive_comparison_operator (operands[3],
14176 GET_MODE (operands[3]));
14179 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14180 GET_CODE (operands[1])),
14182 operands[2], const0_rtx);
14183 else if (GET_MODE (operands[1]) != SImode)
14184 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14185 operands[2], const0_rtx);
14188 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14189 GET_CODE (operands[3])),
14191 operands[4], const0_rtx);
14192 else if (GET_MODE (operands[3]) != SImode)
14193 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14194 operands[4], const0_rtx);
14196 if (positive_1 == positive_2)
14198 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14199 operands[5] = constm1_rtx;
14203 operands[5] = const1_rtx;
14207 ;; Unconditional branch and return.
14209 (define_insn "jump"
14211 (label_ref (match_operand 0 "" "")))]
14214 [(set_attr "type" "branch")])
14216 (define_insn "<return_str>return"
14220 [(set_attr "type" "jmpreg")])
14222 (define_expand "indirect_jump"
14223 [(set (pc) (match_operand 0 "register_operand" ""))])
14225 (define_insn "*indirect_jump<mode>"
14226 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14231 [(set_attr "type" "jmpreg")])
14233 ;; Table jump for switch statements:
14234 (define_expand "tablejump"
14235 [(use (match_operand 0 "" ""))
14236 (use (label_ref (match_operand 1 "" "")))]
14241 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14243 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14247 (define_expand "tablejumpsi"
14248 [(set (match_dup 3)
14249 (plus:SI (match_operand:SI 0 "" "")
14251 (parallel [(set (pc) (match_dup 3))
14252 (use (label_ref (match_operand 1 "" "")))])]
14255 { operands[0] = force_reg (SImode, operands[0]);
14256 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14257 operands[3] = gen_reg_rtx (SImode);
14260 (define_expand "tablejumpdi"
14261 [(set (match_dup 4)
14262 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14264 (plus:DI (match_dup 4)
14266 (parallel [(set (pc) (match_dup 3))
14267 (use (label_ref (match_operand 1 "" "")))])]
14270 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14271 operands[3] = gen_reg_rtx (DImode);
14272 operands[4] = gen_reg_rtx (DImode);
14275 (define_insn "*tablejump<mode>_internal1"
14277 (match_operand:P 0 "register_operand" "c,*l"))
14278 (use (label_ref (match_operand 1 "" "")))]
14283 [(set_attr "type" "jmpreg")])
14290 (define_insn "group_ending_nop"
14291 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14295 if (rs6000_cpu_attr == CPU_POWER6)
14296 return \"ori 1,1,0\";
14297 return \"ori 2,2,0\";
14300 ;; Define the subtract-one-and-jump insns, starting with the template
14301 ;; so loop.c knows what to generate.
14303 (define_expand "doloop_end"
14304 [(use (match_operand 0 "" "")) ; loop pseudo
14305 (use (match_operand 1 "" ""))] ; label
14311 if (GET_MODE (operands[0]) != DImode)
14313 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
14317 if (GET_MODE (operands[0]) != SImode)
14319 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
14324 (define_expand "ctr<mode>"
14325 [(parallel [(set (pc)
14326 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14328 (label_ref (match_operand 1 "" ""))
14331 (plus:P (match_dup 0)
14333 (clobber (match_scratch:CC 2 ""))
14334 (clobber (match_scratch:P 3 ""))])]
14338 ;; We need to be able to do this for any operand, including MEM, or we
14339 ;; will cause reload to blow up since we don't allow output reloads on
14341 ;; For the length attribute to be calculated correctly, the
14342 ;; label MUST be operand 0.
14344 (define_insn "*ctr<mode>_internal1"
14346 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14348 (label_ref (match_operand 0 "" ""))
14350 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14351 (plus:P (match_dup 1)
14353 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14354 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14358 if (which_alternative != 0)
14360 else if (get_attr_length (insn) == 4)
14361 return \"bdnz %l0\";
14363 return \"bdz $+8\;b %l0\";
14365 [(set_attr "type" "branch")
14366 (set_attr "length" "*,12,16,16")])
14368 (define_insn "*ctr<mode>_internal2"
14370 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14373 (label_ref (match_operand 0 "" ""))))
14374 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14375 (plus:P (match_dup 1)
14377 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14378 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14382 if (which_alternative != 0)
14384 else if (get_attr_length (insn) == 4)
14385 return \"bdz %l0\";
14387 return \"bdnz $+8\;b %l0\";
14389 [(set_attr "type" "branch")
14390 (set_attr "length" "*,12,16,16")])
14392 ;; Similar but use EQ
14394 (define_insn "*ctr<mode>_internal5"
14396 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14398 (label_ref (match_operand 0 "" ""))
14400 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14401 (plus:P (match_dup 1)
14403 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14404 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14408 if (which_alternative != 0)
14410 else if (get_attr_length (insn) == 4)
14411 return \"bdz %l0\";
14413 return \"bdnz $+8\;b %l0\";
14415 [(set_attr "type" "branch")
14416 (set_attr "length" "*,12,16,16")])
14418 (define_insn "*ctr<mode>_internal6"
14420 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14423 (label_ref (match_operand 0 "" ""))))
14424 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14425 (plus:P (match_dup 1)
14427 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14428 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14432 if (which_alternative != 0)
14434 else if (get_attr_length (insn) == 4)
14435 return \"bdnz %l0\";
14437 return \"bdz $+8\;b %l0\";
14439 [(set_attr "type" "branch")
14440 (set_attr "length" "*,12,16,16")])
14442 ;; Now the splitters if we could not allocate the CTR register
14446 (if_then_else (match_operator 2 "comparison_operator"
14447 [(match_operand:P 1 "gpc_reg_operand" "")
14449 (match_operand 5 "" "")
14450 (match_operand 6 "" "")))
14451 (set (match_operand:P 0 "gpc_reg_operand" "")
14452 (plus:P (match_dup 1) (const_int -1)))
14453 (clobber (match_scratch:CC 3 ""))
14454 (clobber (match_scratch:P 4 ""))]
14456 [(parallel [(set (match_dup 3)
14457 (compare:CC (plus:P (match_dup 1)
14461 (plus:P (match_dup 1)
14463 (set (pc) (if_then_else (match_dup 7)
14467 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14468 operands[3], const0_rtx); }")
14472 (if_then_else (match_operator 2 "comparison_operator"
14473 [(match_operand:P 1 "gpc_reg_operand" "")
14475 (match_operand 5 "" "")
14476 (match_operand 6 "" "")))
14477 (set (match_operand:P 0 "nonimmediate_operand" "")
14478 (plus:P (match_dup 1) (const_int -1)))
14479 (clobber (match_scratch:CC 3 ""))
14480 (clobber (match_scratch:P 4 ""))]
14481 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14482 [(parallel [(set (match_dup 3)
14483 (compare:CC (plus:P (match_dup 1)
14487 (plus:P (match_dup 1)
14491 (set (pc) (if_then_else (match_dup 7)
14495 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14496 operands[3], const0_rtx); }")
14498 (define_insn "trap"
14499 [(trap_if (const_int 1) (const_int 0))]
14502 [(set_attr "type" "trap")])
14504 (define_expand "ctrap<mode>4"
14505 [(trap_if (match_operator 0 "ordered_comparison_operator"
14506 [(match_operand:GPR 1 "register_operand")
14507 (match_operand:GPR 2 "reg_or_short_operand")])
14508 (match_operand 3 "zero_constant" ""))]
14513 [(trap_if (match_operator 0 "ordered_comparison_operator"
14514 [(match_operand:GPR 1 "register_operand" "r")
14515 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14518 "t<wd>%V0%I2 %1,%2"
14519 [(set_attr "type" "trap")])
14521 ;; Insns related to generating the function prologue and epilogue.
14523 (define_expand "prologue"
14524 [(use (const_int 0))]
14527 rs6000_emit_prologue ();
14528 if (!TARGET_SCHED_PROLOG)
14529 emit_insn (gen_blockage ());
14533 (define_insn "*movesi_from_cr_one"
14534 [(match_parallel 0 "mfcr_operation"
14535 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14536 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14537 (match_operand 3 "immediate_operand" "n")]
14538 UNSPEC_MOVESI_FROM_CR))])]
14544 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14546 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14547 operands[4] = GEN_INT (mask);
14548 output_asm_insn (\"mfcr %1,%4\", operands);
14552 [(set_attr "type" "mfcrf")])
14554 (define_insn "movesi_from_cr"
14555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14556 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14557 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14558 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14559 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14560 UNSPEC_MOVESI_FROM_CR))]
14563 [(set_attr "type" "mfcr")])
14565 (define_insn "*crsave"
14566 [(match_parallel 0 "crsave_operation"
14567 [(set (match_operand:SI 1 "memory_operand" "=m")
14568 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14571 [(set_attr "type" "store")])
14573 (define_insn "*stmw"
14574 [(match_parallel 0 "stmw_operation"
14575 [(set (match_operand:SI 1 "memory_operand" "=m")
14576 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14579 [(set_attr "type" "store")
14580 (set_attr "update" "yes")
14581 (set_attr "indexed" "yes")])
14583 ; The following comment applies to:
14587 ; return_and_restore_gpregs*
14588 ; return_and_restore_fpregs*
14589 ; return_and_restore_fpregs_aix*
14591 ; The out-of-line save / restore functions expects one input argument.
14592 ; Since those are not standard call_insn's, we must avoid using
14593 ; MATCH_OPERAND for that argument. That way the register rename
14594 ; optimization will not try to rename this register.
14595 ; Each pattern is repeated for each possible register number used in
14596 ; various ABIs (r11, r1, and for some functions r12)
14598 (define_insn "*save_gpregs_<mode>_r11"
14599 [(match_parallel 0 "any_parallel_operand"
14600 [(clobber (reg:P 65))
14601 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14603 (set (match_operand:P 2 "memory_operand" "=m")
14604 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14607 [(set_attr "type" "branch")
14608 (set_attr "length" "4")])
14610 (define_insn "*save_gpregs_<mode>_r12"
14611 [(match_parallel 0 "any_parallel_operand"
14612 [(clobber (reg:P 65))
14613 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14615 (set (match_operand:P 2 "memory_operand" "=m")
14616 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14619 [(set_attr "type" "branch")
14620 (set_attr "length" "4")])
14622 (define_insn "*save_gpregs_<mode>_r1"
14623 [(match_parallel 0 "any_parallel_operand"
14624 [(clobber (reg:P 65))
14625 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14627 (set (match_operand:P 2 "memory_operand" "=m")
14628 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14631 [(set_attr "type" "branch")
14632 (set_attr "length" "4")])
14634 (define_insn "*save_fpregs_<mode>_r11"
14635 [(match_parallel 0 "any_parallel_operand"
14636 [(clobber (reg:P 65))
14637 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14639 (set (match_operand:DF 2 "memory_operand" "=m")
14640 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14643 [(set_attr "type" "branch")
14644 (set_attr "length" "4")])
14646 (define_insn "*save_fpregs_<mode>_r12"
14647 [(match_parallel 0 "any_parallel_operand"
14648 [(clobber (reg:P 65))
14649 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14651 (set (match_operand:DF 2 "memory_operand" "=m")
14652 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14655 [(set_attr "type" "branch")
14656 (set_attr "length" "4")])
14658 (define_insn "*save_fpregs_<mode>_r1"
14659 [(match_parallel 0 "any_parallel_operand"
14660 [(clobber (reg:P 65))
14661 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14663 (set (match_operand:DF 2 "memory_operand" "=m")
14664 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14667 [(set_attr "type" "branch")
14668 (set_attr "length" "4")])
14670 ; This is to explain that changes to the stack pointer should
14671 ; not be moved over loads from or stores to stack memory.
14672 (define_insn "stack_tie"
14673 [(match_parallel 0 "tie_operand"
14674 [(set (mem:BLK (reg 1)) (const_int 0))])]
14677 [(set_attr "length" "0")])
14679 (define_expand "epilogue"
14680 [(use (const_int 0))]
14683 if (!TARGET_SCHED_PROLOG)
14684 emit_insn (gen_blockage ());
14685 rs6000_emit_epilogue (FALSE);
14689 ; On some processors, doing the mtcrf one CC register at a time is
14690 ; faster (like on the 604e). On others, doing them all at once is
14691 ; faster; for instance, on the 601 and 750.
14693 (define_expand "movsi_to_cr_one"
14694 [(set (match_operand:CC 0 "cc_reg_operand" "")
14695 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14696 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14698 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14700 (define_insn "*movsi_to_cr"
14701 [(match_parallel 0 "mtcrf_operation"
14702 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14703 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14704 (match_operand 3 "immediate_operand" "n")]
14705 UNSPEC_MOVESI_TO_CR))])]
14711 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14712 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14713 operands[4] = GEN_INT (mask);
14714 return \"mtcrf %4,%2\";
14716 [(set_attr "type" "mtcr")])
14718 (define_insn "*mtcrfsi"
14719 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14720 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14721 (match_operand 2 "immediate_operand" "n")]
14722 UNSPEC_MOVESI_TO_CR))]
14723 "GET_CODE (operands[0]) == REG
14724 && CR_REGNO_P (REGNO (operands[0]))
14725 && GET_CODE (operands[2]) == CONST_INT
14726 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14728 [(set_attr "type" "mtcr")])
14730 ; The load-multiple instructions have similar properties.
14731 ; Note that "load_multiple" is a name known to the machine-independent
14732 ; code that actually corresponds to the PowerPC load-string.
14734 (define_insn "*lmw"
14735 [(match_parallel 0 "lmw_operation"
14736 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14737 (match_operand:SI 2 "memory_operand" "m"))])]
14740 [(set_attr "type" "load")
14741 (set_attr "update" "yes")
14742 (set_attr "indexed" "yes")
14743 (set_attr "cell_micro" "always")])
14745 (define_insn "*return_internal_<mode>"
14747 (use (match_operand:P 0 "register_operand" "lc"))]
14750 [(set_attr "type" "jmpreg")])
14752 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14753 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14755 ; The following comment applies to:
14759 ; return_and_restore_gpregs*
14760 ; return_and_restore_fpregs*
14761 ; return_and_restore_fpregs_aix*
14763 ; The out-of-line save / restore functions expects one input argument.
14764 ; Since those are not standard call_insn's, we must avoid using
14765 ; MATCH_OPERAND for that argument. That way the register rename
14766 ; optimization will not try to rename this register.
14767 ; Each pattern is repeated for each possible register number used in
14768 ; various ABIs (r11, r1, and for some functions r12)
14770 (define_insn "*restore_gpregs_<mode>_r11"
14771 [(match_parallel 0 "any_parallel_operand"
14772 [(clobber (match_operand:P 1 "register_operand" "=l"))
14773 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14775 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14776 (match_operand:P 4 "memory_operand" "m"))])]
14779 [(set_attr "type" "branch")
14780 (set_attr "length" "4")])
14782 (define_insn "*restore_gpregs_<mode>_r12"
14783 [(match_parallel 0 "any_parallel_operand"
14784 [(clobber (match_operand:P 1 "register_operand" "=l"))
14785 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14787 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14788 (match_operand:P 4 "memory_operand" "m"))])]
14791 [(set_attr "type" "branch")
14792 (set_attr "length" "4")])
14794 (define_insn "*restore_gpregs_<mode>_r1"
14795 [(match_parallel 0 "any_parallel_operand"
14796 [(clobber (match_operand:P 1 "register_operand" "=l"))
14797 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14799 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14800 (match_operand:P 4 "memory_operand" "m"))])]
14803 [(set_attr "type" "branch")
14804 (set_attr "length" "4")])
14806 (define_insn "*return_and_restore_gpregs_<mode>_r11"
14807 [(match_parallel 0 "any_parallel_operand"
14809 (clobber (match_operand:P 1 "register_operand" "=l"))
14810 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14812 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14813 (match_operand:P 4 "memory_operand" "m"))])]
14816 [(set_attr "type" "branch")
14817 (set_attr "length" "4")])
14819 (define_insn "*return_and_restore_gpregs_<mode>_r12"
14820 [(match_parallel 0 "any_parallel_operand"
14822 (clobber (match_operand:P 1 "register_operand" "=l"))
14823 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14825 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14826 (match_operand:P 4 "memory_operand" "m"))])]
14829 [(set_attr "type" "branch")
14830 (set_attr "length" "4")])
14832 (define_insn "*return_and_restore_gpregs_<mode>_r1"
14833 [(match_parallel 0 "any_parallel_operand"
14835 (clobber (match_operand:P 1 "register_operand" "=l"))
14836 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14838 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14839 (match_operand:P 4 "memory_operand" "m"))])]
14842 [(set_attr "type" "branch")
14843 (set_attr "length" "4")])
14845 (define_insn "*return_and_restore_fpregs_<mode>_r11"
14846 [(match_parallel 0 "any_parallel_operand"
14848 (clobber (match_operand:P 1 "register_operand" "=l"))
14849 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14851 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14852 (match_operand:DF 4 "memory_operand" "m"))])]
14855 [(set_attr "type" "branch")
14856 (set_attr "length" "4")])
14858 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14859 [(match_parallel 0 "any_parallel_operand"
14861 (clobber (match_operand:P 1 "register_operand" "=l"))
14862 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14864 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14865 (match_operand:DF 4 "memory_operand" "m"))])]
14868 [(set_attr "type" "branch")
14869 (set_attr "length" "4")])
14871 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14872 [(match_parallel 0 "any_parallel_operand"
14874 (clobber (match_operand:P 1 "register_operand" "=l"))
14875 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14877 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14878 (match_operand:DF 4 "memory_operand" "m"))])]
14881 [(set_attr "type" "branch")
14882 (set_attr "length" "4")])
14884 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14885 [(match_parallel 0 "any_parallel_operand"
14887 (use (match_operand:P 1 "register_operand" "l"))
14888 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14890 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14891 (match_operand:DF 4 "memory_operand" "m"))])]
14894 [(set_attr "type" "branch")
14895 (set_attr "length" "4")])
14897 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14898 [(match_parallel 0 "any_parallel_operand"
14900 (use (match_operand:P 1 "register_operand" "l"))
14901 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14903 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14904 (match_operand:DF 4 "memory_operand" "m"))])]
14907 [(set_attr "type" "branch")
14908 (set_attr "length" "4")])
14910 ; This is used in compiling the unwind routines.
14911 (define_expand "eh_return"
14912 [(use (match_operand 0 "general_operand" ""))]
14917 emit_insn (gen_eh_set_lr_si (operands[0]));
14919 emit_insn (gen_eh_set_lr_di (operands[0]));
14923 ; We can't expand this before we know where the link register is stored.
14924 (define_insn "eh_set_lr_<mode>"
14925 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14927 (clobber (match_scratch:P 1 "=&b"))]
14932 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14933 (clobber (match_scratch 1 ""))]
14938 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14942 (define_insn "prefetch"
14943 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14944 (match_operand:SI 1 "const_int_operand" "n")
14945 (match_operand:SI 2 "const_int_operand" "n"))]
14949 if (GET_CODE (operands[0]) == REG)
14950 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14951 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14953 [(set_attr "type" "load")])
14955 (define_insn "bpermd_<mode>"
14956 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14957 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14958 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14961 [(set_attr "type" "popcnt")])
14964 ;; Builtin fma support. Handle
14965 ;; Note that the conditions for expansion are in the FMA_F iterator.
14967 (define_expand "fma<mode>4"
14968 [(set (match_operand:FMA_F 0 "register_operand" "")
14970 (match_operand:FMA_F 1 "register_operand" "")
14971 (match_operand:FMA_F 2 "register_operand" "")
14972 (match_operand:FMA_F 3 "register_operand" "")))]
14976 (define_insn "*fma<mode>4_fpr"
14977 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14979 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14980 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14981 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14982 "TARGET_<MODE>_FPR"
14984 fmadd<Ftrad> %0,%1,%2,%3
14985 xsmadda<Fvsx> %x0,%x1,%x2
14986 xsmaddm<Fvsx> %x0,%x1,%x3"
14987 [(set_attr "type" "fp")
14988 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14990 ; Altivec only has fma and nfms.
14991 (define_expand "fms<mode>4"
14992 [(set (match_operand:FMA_F 0 "register_operand" "")
14994 (match_operand:FMA_F 1 "register_operand" "")
14995 (match_operand:FMA_F 2 "register_operand" "")
14996 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14997 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15000 (define_insn "*fms<mode>4_fpr"
15001 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15003 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15004 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15005 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15006 "TARGET_<MODE>_FPR"
15008 fmsub<Ftrad> %0,%1,%2,%3
15009 xsmsuba<Fvsx> %x0,%x1,%x2
15010 xsmsubm<Fvsx> %x0,%x1,%x3"
15011 [(set_attr "type" "fp")
15012 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15014 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
15015 (define_expand "fnma<mode>4"
15016 [(set (match_operand:FMA_F 0 "register_operand" "")
15019 (match_operand:FMA_F 1 "register_operand" "")
15020 (match_operand:FMA_F 2 "register_operand" "")
15021 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15022 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
15025 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
15026 (define_expand "fnms<mode>4"
15027 [(set (match_operand:FMA_F 0 "register_operand" "")
15030 (match_operand:FMA_F 1 "register_operand" "")
15031 (match_operand:FMA_F 2 "register_operand" "")
15032 (match_operand:FMA_F 3 "register_operand" ""))))]
15033 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15036 ; Not an official optab name, but used from builtins.
15037 (define_expand "nfma<mode>4"
15038 [(set (match_operand:FMA_F 0 "register_operand" "")
15041 (match_operand:FMA_F 1 "register_operand" "")
15042 (match_operand:FMA_F 2 "register_operand" "")
15043 (match_operand:FMA_F 3 "register_operand" ""))))]
15044 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15047 (define_insn "*nfma<mode>4_fpr"
15048 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15051 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15052 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15053 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15054 "TARGET_<MODE>_FPR"
15056 fnmadd<Ftrad> %0,%1,%2,%3
15057 xsnmadda<Fvsx> %x0,%x1,%x2
15058 xsnmaddm<Fvsx> %x0,%x1,%x3"
15059 [(set_attr "type" "fp")
15060 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15062 ; Not an official optab name, but used from builtins.
15063 (define_expand "nfms<mode>4"
15064 [(set (match_operand:FMA_F 0 "register_operand" "")
15067 (match_operand:FMA_F 1 "register_operand" "")
15068 (match_operand:FMA_F 2 "register_operand" "")
15069 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15073 (define_insn "*nfmssf4_fpr"
15074 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15077 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15078 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15080 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
15081 "TARGET_<MODE>_FPR"
15083 fnmsub<Ftrad> %0,%1,%2,%3
15084 xsnmsuba<Fvsx> %x0,%x1,%x2
15085 xsnmsubm<Fvsx> %x0,%x1,%x3"
15086 [(set_attr "type" "fp")
15087 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15090 (define_expand "rs6000_get_timebase"
15091 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
15094 if (TARGET_POWERPC64)
15095 emit_insn (gen_rs6000_mftb_di (operands[0]));
15097 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
15101 (define_insn "rs6000_get_timebase_ppc32"
15102 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
15103 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
15104 (clobber (match_scratch:SI 1 "=r"))
15105 (clobber (match_scratch:CC 2 "=y"))]
15106 "!TARGET_POWERPC64"
15108 if (WORDS_BIG_ENDIAN)
15111 return "mfspr %0,269\;"
15119 return "mftbu %0\;"
15128 return "mfspr %L0,269\;"
15136 return "mftbu %L0\;"
15143 [(set_attr "length" "20")])
15145 (define_insn "rs6000_mftb_<mode>"
15146 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15147 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
15151 return "mfspr %0,268";
15157 (define_insn "rs6000_mffs"
15158 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
15159 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
15160 "TARGET_HARD_FLOAT && TARGET_FPRS"
15163 (define_insn "rs6000_mtfsf"
15164 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
15165 (match_operand:DF 1 "gpc_reg_operand" "d")]
15167 "TARGET_HARD_FLOAT && TARGET_FPRS"
15171 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
15172 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
15173 ;; register that is being loaded. The fused ops must be physically adjacent.
15175 ;; We use define_peephole for the actual addis/load, and the register used to
15176 ;; hold the addis value must be the same as the register being loaded. We use
15177 ;; define_peephole2 to change the register used for addis to be the register
15178 ;; being loaded, since we can look at whether it is dead after the load insn.
15181 [(set (match_operand:P 0 "base_reg_operand" "")
15182 (match_operand:P 1 "fusion_gpr_addis" ""))
15183 (set (match_operand:INT1 2 "base_reg_operand" "")
15184 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15185 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
15187 return emit_fusion_gpr_load (operands);
15189 [(set_attr "type" "load")
15190 (set_attr "length" "8")])
15193 [(set (match_operand:P 0 "base_reg_operand" "")
15194 (match_operand:P 1 "fusion_gpr_addis" ""))
15195 (set (match_operand:INT1 2 "base_reg_operand" "")
15196 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15198 && (REGNO (operands[0]) != REGNO (operands[2])
15199 || GET_CODE (operands[3]) == SIGN_EXTEND)
15200 && fusion_gpr_load_p (operands, true)"
15203 expand_fusion_gpr_load (operands);
15208 ;; Miscellaneous ISA 2.06 (power7) instructions
15209 (define_insn "addg6s"
15210 [(set (match_operand:SI 0 "register_operand" "=r")
15211 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
15212 (match_operand:SI 2 "register_operand" "r")]
15216 [(set_attr "type" "integer")
15217 (set_attr "length" "4")])
15219 (define_insn "cdtbcd"
15220 [(set (match_operand:SI 0 "register_operand" "=r")
15221 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
15225 [(set_attr "type" "integer")
15226 (set_attr "length" "4")])
15228 (define_insn "cbcdtd"
15229 [(set (match_operand:SI 0 "register_operand" "=r")
15230 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
15234 [(set_attr "type" "integer")
15235 (set_attr "length" "4")])
15237 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
15242 (define_int_attr div_extend [(UNSPEC_DIVE "e")
15243 (UNSPEC_DIVEO "eo")
15244 (UNSPEC_DIVEU "eu")
15245 (UNSPEC_DIVEUO "euo")])
15247 (define_insn "div<div_extend>_<mode>"
15248 [(set (match_operand:GPR 0 "register_operand" "=r")
15249 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
15250 (match_operand:GPR 2 "register_operand" "r")]
15251 UNSPEC_DIV_EXTEND))]
15253 "div<wd><div_extend> %0,%1,%2"
15254 [(set_attr "type" "div")
15255 (set_attr "size" "<bits>")])
15258 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
15260 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
15261 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
15263 (define_expand "unpack<mode>"
15264 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
15266 [(match_operand:FMOVE128 1 "register_operand" "")
15267 (match_operand:QI 2 "const_0_to_1_operand" "")]
15268 UNSPEC_UNPACK_128BIT))]
15272 (define_insn_and_split "unpack<mode>_dm"
15273 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
15275 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
15276 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
15277 UNSPEC_UNPACK_128BIT))]
15278 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
15280 "&& reload_completed"
15281 [(set (match_dup 0) (match_dup 3))]
15283 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
15285 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
15287 emit_note (NOTE_INSN_DELETED);
15291 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
15293 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
15294 (set_attr "length" "4")])
15296 (define_insn_and_split "unpack<mode>_nodm"
15297 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
15299 [(match_operand:FMOVE128 1 "register_operand" "d,d")
15300 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
15301 UNSPEC_UNPACK_128BIT))]
15302 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
15304 "&& reload_completed"
15305 [(set (match_dup 0) (match_dup 3))]
15307 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
15309 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
15311 emit_note (NOTE_INSN_DELETED);
15315 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
15317 [(set_attr "type" "fp,fpstore")
15318 (set_attr "length" "4")])
15320 (define_insn_and_split "pack<mode>"
15321 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
15323 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
15324 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
15325 UNSPEC_PACK_128BIT))]
15330 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
15331 [(set (match_dup 3) (match_dup 1))
15332 (set (match_dup 4) (match_dup 2))]
15334 unsigned dest_hi = REGNO (operands[0]);
15335 unsigned dest_lo = dest_hi + 1;
15337 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
15338 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
15340 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
15341 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
15343 [(set_attr "type" "fp,fp")
15344 (set_attr "length" "4,8")])
15346 (define_insn "unpackv1ti"
15347 [(set (match_operand:DI 0 "register_operand" "=d,d")
15348 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
15349 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
15350 UNSPEC_UNPACK_128BIT))]
15353 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
15354 return ASM_COMMENT_START " xxpermdi to same register";
15356 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
15357 return "xxpermdi %x0,%x1,%x1,%3";
15359 [(set_attr "type" "vecperm")
15360 (set_attr "length" "4")])
15362 (define_insn "packv1ti"
15363 [(set (match_operand:V1TI 0 "register_operand" "=wa")
15365 [(match_operand:DI 1 "register_operand" "d")
15366 (match_operand:DI 2 "register_operand" "d")]
15367 UNSPEC_PACK_128BIT))]
15369 "xxpermdi %x0,%x1,%x2,0"
15370 [(set_attr "type" "vecperm")
15371 (set_attr "length" "4")])
15375 (include "sync.md")
15376 (include "vector.md")
15378 (include "altivec.md")
15381 (include "paired.md")
15382 (include "crypto.md")