1 /* Check that the negc instruction is generated as expected for the cases
2 below. If we see a movrt or #-1 negc sequence it means that the pattern
3 which handles the inverted case does not work properly. */
4 /* { dg-do compile } */
5 /* { dg-options "-O1" } */
7 /* { dg-final { scan-assembler-times "negc" 15 { target { ! sh2a } } } } */
8 /* { dg-final { scan-assembler-times "addc" 3 { target { ! sh2a } } } } */
10 /* { dg-final { scan-assembler-times "negc" 13 { target { sh2a } } } } */
11 /* { dg-final { scan-assembler-times "addc" 5 { target { sh2a } } } } */
12 /* { dg-final { scan-assembler-times "bld" 2 { target { sh2a } } } } */
14 /* { dg-final { scan-assembler-not "movrt|#-1|add\t|sub\t|movt" } } */
17 test00 (int a
, int b
, int* x
)
19 return (a
== b
) ? 0x7FFFFFFF : 0x80000000;
23 test00_inv (int a
, int b
)
25 return (a
!= b
) ? 0x80000000 : 0x7FFFFFFF;
31 return (a
>= b
) ? 0x7FFFFFFF : 0x80000000;
35 test01_inv (int a
, int b
)
37 return (a
< b
) ? 0x80000000 : 0x7FFFFFFF;
43 return (a
> b
) ? 0x7FFFFFFF : 0x80000000;
47 test02_inv (int a
, int b
)
49 return (a
<= b
) ? 0x80000000 : 0x7FFFFFFF;
55 return ((a
& b
) == 0) ? 0x7FFFFFFF : 0x80000000;
59 test03_inv (int a
, int b
)
61 return ((a
& b
) != 0) ? 0x80000000 : 0x7FFFFFFF;
67 return ((a
& 0x55) == 0) ? 0x7FFFFFFF : 0x80000000;
73 return ((a
& 0x55) != 0) ? 0x80000000 : 0x7FFFFFFF;
80 return a
!= b
? 0x7FFFFFFF : 0x80000000;
86 return ((a
& 0x03) == 0) ? 0x7FFFFFFF : 0x80000000;
92 return ((a
& 0x80) == 0) ? 0x7FFFFFFF : 0x80000000;
98 return ((a
& 1) == 0) ? 0x7FFFFFFF : 0x80000000;
104 /* 1x cmp/pz, 1x addc */
105 return a
< 0 ? 0x7FFFFFFF : 0x80000000;
111 /* 1x cmp/pz, 1x negc */
112 return a
>= 0 ? 0x7FFFFFFF : 0x80000000;
118 /* 1x cmp/pl, 1x negc */
119 return a
> 0 ? 0x7FFFFFFF : 0x80000000;
125 /* 1x cmp/pl, 1x addc */
126 return a
<= 0 ? 0x7FFFFFFF : 0x80000000;