gcc/rtl.def

   1 /* This file contains the definitions and documentation for the
   2    Register Transfer Expressions (rtx's) that make up the
   3    Register Transfer Language (rtl) used in the Back End of the GNU compiler.
   4    Copyright (C) 1987, 88, 92, 94, 95, 1997 Free Software Foundation, Inc.
   5
   6 This file is part of GNU CC.
   7
   8 GNU CC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 GNU CC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GNU CC; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 59 Temple Place - Suite 330,
  21 Boston, MA 02111-1307, USA.  */
  22
  23
  24 /* Expression definitions and descriptions for all targets are in this file.
  25    Some will not be used for some targets.
  26
  27    The fields in the cpp macro call "DEF_RTL_EXPR()"
  28    are used to create declarations in the C source of the compiler.
  29
  30    The fields are:
  31
  32    1.  The internal name of the rtx used in the C source.
  33    It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
  34    By convention these are in UPPER_CASE.
  35
  36    2.  The name of the rtx in the external ASCII format read by
  37    read_rtx(), and printed by print_rtx().
  38    These names are stored in rtx_name[].
  39    By convention these are the internal (field 1) names in lower_case.
  40
  41    3.  The print format, and type of each rtx->fld[] (field) in this rtx.
  42    These formats are stored in rtx_format[].
  43    The meaning of the formats is documented in front of this array in rtl.c
  44
  45    4.  The class of the rtx.  These are stored in rtx_class and are accessed
  46    via the GET_RTX_CLASS macro.  They are defined as follows:
  47
  48      "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
  49      "<" an rtx code for a comparison (e.g, EQ, NE, LT)
  50      "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
  51      "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
  52      "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
  53      "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
  54      "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
  55      "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
  56      "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
  57      "x" everything else
  58
  59    */
  60
  61 /* ---------------------------------------------------------------------
  62    Expressions (and "meta" expressions) used for structuring the
  63    rtl representation of a program.
  64    --------------------------------------------------------------------- */
  65
  66 /* an expression code name unknown to the reader */
  67 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
  68
  69 /* (NIL) is used by rtl reader and printer to represent a null pointer.  */
  70
  71 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
  72
  73 /* ---------------------------------------------------------------------
  74    Expressions used in constructing lists.
  75    --------------------------------------------------------------------- */
  76
  77 /* a linked list of expressions */
  78 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
  79
  80 /* a linked list of instructions.
  81    The insns are represented in print by their uids.  */
  82 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
  83
  84 /* ----------------------------------------------------------------------
  85    Expression types for machine descriptions.
  86    These do not appear in actual rtl code in the compiler.
  87    ---------------------------------------------------------------------- */
  88
  89 /* Appears only in machine descriptions.
  90    Means use the function named by the second arg (the string)
  91    as a predicate; if matched, store the structure that was matched
  92    in the operand table at index specified by the first arg (the integer).
  93    If the second arg is the null string, the structure is just stored.
  94
  95    A third string argument indicates to the register allocator restrictions
  96    on where the operand can be allocated.
  97
  98    If the target needs no restriction on any instruction this field should
  99    be the null string.
 100
 101    The string is prepended by:
 102    '=' to indicate the operand is only written to.
 103    '+' to indicate the operand is both read and written to.
 104
 105    Each character in the string represents an allocable class for an operand.
 106    'g' indicates the operand can be any valid class.
 107    'i' indicates the operand can be immediate (in the instruction) data.
 108    'r' indicates the operand can be in a register.
 109    'm' indicates the operand can be in memory.
 110    'o' a subset of the 'm' class.  Those memory addressing modes that
 111        can be offset at compile time (have a constant added to them).
 112
 113    Other characters indicate target dependent operand classes and
 114    are described in each target's machine description.
 115
 116    For instructions with more than one operand, sets of classes can be
 117    separated by a comma to indicate the appropriate multi-operand constraints.
 118    There must be a 1 to 1 correspondence between these sets of classes in
 119    all operands for an instruction.
 120    */
 121 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
 122
 123 /* Appears only in machine descriptions.
 124    Means match a SCRATCH or a register.  When used to generate rtl, a
 125    SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
 126    the desired mode and the first argument is the operand number.
 127    The second argument is the constraint.  */
 128 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
 129
 130 /* Appears only in machine descriptions.
 131    Means match only something equal to what is stored in the operand table
 132    at the index specified by the argument.  */
 133 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
 134
 135 /* Appears only in machine descriptions.
 136    Means apply a predicate, AND match recursively the operands of the rtx.
 137    Operand 0 is the operand-number, as in match_operand.
 138    Operand 1 is a predicate to apply (as a string, a function name).
 139    Operand 2 is a vector of expressions, each of which must match
 140    one subexpression of the rtx this construct is matching.  */
 141 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
 142
 143 /* Appears only in machine descriptions.
 144    Means to match a PARALLEL of arbitrary length.  The predicate is applied
 145    to the PARALLEL and the initial expressions in the PARALLEL are matched.
 146    Operand 0 is the operand-number, as in match_operand.
 147    Operand 1 is a predicate to apply to the PARALLEL.
 148    Operand 2 is a vector of expressions, each of which must match the
 149    corresponding element in the PARALLEL.  */
 150 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
 151
 152 /* Appears only in machine descriptions.
 153    Means match only something equal to what is stored in the operand table
 154    at the index specified by the argument.  For MATCH_OPERATOR.  */
 155 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
 156
 157 /* Appears only in machine descriptions.
 158    Means match only something equal to what is stored in the operand table
 159    at the index specified by the argument.  For MATCH_PARALLEL.  */
 160 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
 161
 162 /* Appears only in machine descriptions.
 163    Should be used only in attribute tests.
 164    The predicate in operand 0 is applied to the whole insn being checked.  */
 165 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "s", 'm')
 166
 167 /* Appears only in machine descriptions.
 168    Defines the pattern for one kind of instruction.
 169    Operand:
 170    0: names this instruction.
 171       If the name is the null string, the instruction is in the
 172       machine description just to be recognized, and will never be emitted by
 173       the tree to rtl expander.
 174    1: is the pattern.
 175    2: is a string which is a C expression
 176       giving an additional condition for recognizing this pattern.
 177       A null string means no extra condition.
 178    3: is the action to execute if this pattern is matched.
 179       If this assembler code template starts with a * then it is a fragment of
 180       C code to run to decide on a template to use.  Otherwise, it is the
 181       template to use.
 182    4: optionally, a vector of attributes for this insn.
 183      */
 184 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
 185
 186 /* Definition of a peephole optimization.
 187    1st operand: vector of insn patterns to match
 188    2nd operand: C expression that must be true
 189    3rd operand: template or C code to produce assembler output.
 190    4: optionally, a vector of attributes for this insn.
 191      */
 192 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
 193
 194 /* Definition of a split operation.
 195    1st operand: insn pattern to match
 196    2nd operand: C expression that must be true
 197    3rd operand: vector of insn patterns to place into a SEQUENCE
 198    4th operand: optionally, some C code to execute before generating the
 199         insns.  This might, for example, create some RTX's and store them in
 200         elements of `recog_operand' for use by the vector of insn-patterns.
 201         (`operands' is an alias here for `recog_operand').   */
 202 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
 203
 204 /* Definition of a combiner pattern.
 205    Operands not defined yet.  */
 206 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
 207
 208 /* Define how to generate multiple insns for a standard insn name.
 209    1st operand: the insn name.
 210    2nd operand: vector of insn-patterns.
 211         Use match_operand to substitute an element of `recog_operand'.
 212    3rd operand: C expression that must be true for this to be available.
 213         This may not test any operands.
 214    4th operand: Extra C code to execute before generating the insns.
 215         This might, for example, create some RTX's and store them in
 216         elements of `recog_operand' for use by the vector of insn-patterns.
 217         (`operands' is an alias here for `recog_operand').  */
 218 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
 219
 220 /* Define a requirement for delay slots.
 221    1st operand: Condition involving insn attributes that, if true,
 222                 indicates that the insn requires the number of delay slots
 223                 shown.
 224    2nd operand: Vector whose length is the three times the number of delay
 225                 slots required.
 226                 Each entry gives three conditions, each involving attributes.
 227                 The first must be true for an insn to occupy that delay slot
 228                 location.  The second is true for all insns that can be
 229                 annulled if the branch is true and the third is true for all
 230                 insns that can be annulled if the branch is false.
 231
 232    Multiple DEFINE_DELAYs may be present.  They indicate differing
 233    requirements for delay slots.  */
 234 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
 235
 236 /* Define a set of insns that requires a function unit.  This means that
 237    these insns produce their result after a delay and that there may be
 238    restrictions on the number of insns of this type that can be scheduled
 239    simultaneously.
 240
 241    More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
 242    Each gives a set of operations and associated delays.  The first three
 243    operands must be the same for each operation for the same function unit.
 244
 245    All delays are specified in cycles.
 246
 247    1st operand: Name of function unit (mostly for documentation)
 248    2nd operand: Number of identical function units in CPU
 249    3rd operand: Total number of simultaneous insns that can execute on this
 250                 function unit; 0 if unlimited.
 251    4th operand: Condition involving insn attribute, that, if true, specifies
 252                 those insns that this expression applies to.
 253    5th operand: Constant delay after which insn result will be
 254                 available.
 255    6th operand: Delay until next insn can be scheduled on the function unit
 256                 executing this operation.  The meaning depends on whether or
 257                 not the next operand is supplied.
 258    7th operand: If this operand is not specified, the 6th operand gives the
 259                 number of cycles after the instruction matching the 4th
 260                 operand begins using the function unit until a subsequent
 261                 insn can begin.  A value of zero should be used for a
 262                 unit with no issue constraints.  If only one operation can
 263                 be executed a time and the unit is busy for the entire time,
 264                 the 3rd operand should be specified as 1, the 6th operand
 265                 should be specified as 0, and the 7th operand should not
 266                 be specified.
 267
 268                 If this operand is specified, it is a list of attribute
 269                 expressions.  If an insn for which any of these expressions
 270                 is true is currently executing on the function unit, the
 271                 issue delay will be given by the 6th operand.  Otherwise,
 272                 the insn can be immediately scheduled (subject to the limit
 273                 on the number of simultaneous operations executing on the
 274                 unit.)  */
 275 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
 276
 277 /* Define attribute computation for `asm' instructions.  */
 278 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
 279
 280 /* SEQUENCE appears in the result of a `gen_...' function
 281    for a DEFINE_EXPAND that wants to make several insns.
 282    Its elements are the bodies of the insns that should be made.
 283    `emit_insn' takes the SEQUENCE apart and makes separate insns.  */
 284 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
 285
 286 /* Refers to the address of its argument.
 287    This appears only in machine descriptions, indicating that
 288    any expression that would be acceptable as the operand of MEM
 289    should be matched.  */
 290 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
 291
 292 /* ----------------------------------------------------------------------
 293    Expressions used for insn attributes.  These also do not appear in
 294    actual rtl code in the compiler.
 295    ---------------------------------------------------------------------- */
 296
 297 /* Definition of an insn attribute.
 298    1st operand: name of the attribute
 299    2nd operand: comma-separated list of possible attribute values
 300    3rd operand: expression for the default value of the attribute. */
 301 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
 302
 303 /* Marker for the name of an attribute. */
 304 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
 305
 306 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
 307    in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
 308    pattern.
 309
 310    (set_attr "name" "value") is equivalent to
 311    (set (attr "name") (const_string "value"))  */
 312 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
 313
 314 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
 315    specify that attribute values are to be assigned according to the
 316    alternative matched.
 317
 318    The following three expressions are equivalent:
 319
 320    (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
 321                             (eq_attrq "alternative" "2") (const_string "a2")]
 322                            (const_string "a3")))
 323    (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
 324                                  (const_string "a3")])
 325    (set_attr "att" "a1,a2,a3")
 326  */
 327 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
 328
 329 /* A conditional expression true if the value of the specified attribute of
 330    the current insn equals the specified value.  The first operand is the
 331    attribute name and the second is the comparison value.  */
 332 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
 333
 334 /* A conditional expression which is true if the specified flag is
 335    true for the insn being scheduled in reorg.
 336
 337    genattr.c defines the following flags which can be tested by
 338    (attr_flag "foo") expressions in eligible_for_delay.
 339
 340    forward, backward, very_likely, likely, very_unlikely, and unlikely.  */
 341
 342 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
 343
 344 /* ----------------------------------------------------------------------
 345    Expression types used for things in the instruction chain.
 346
 347    All formats must start with "iuu" to handle the chain.
 348    Each insn expression holds an rtl instruction and its semantics
 349    during back-end processing.
 350    See macros's in "rtl.h" for the meaning of each rtx->fld[].
 351
 352    ---------------------------------------------------------------------- */
 353
 354 /* An instruction that cannot jump.  */
 355 DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
 356
 357 /* An instruction that can possibly jump.
 358    Fields ( rtx->fld[] ) have exact same meaning as INSN's.  */
 359 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
 360
 361 /* An instruction that can possibly call a subroutine
 362    but which will not change which instruction comes next
 363    in the current function.
 364    Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
 365    All other fields ( rtx->fld[] ) have exact same meaning as INSN's.  */
 366 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
 367
 368 /* A marker that indicates that control will not flow through.  */
 369 DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
 370
 371 /* Holds a label that is followed by instructions.
 372    Operand:
 373    3: is a number that is unique in the entire compilation.
 374    4: is the user-given name of the label, if any.
 375    5: is used in jump.c for the use-count of the label.
 376    6: is used in flow.c to point to the chain of label_ref's to this label.  */
 377 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis00", 'x')
 378
 379 /* Say where in the code a source line starts, for symbol table's sake.
 380    Contains a filename and a line number.  Line numbers <= 0 are special:
 381    0 is used in a dummy placed at the front of every function
 382       just so there will never be a need to delete the first insn;
 383    -1 indicates a dummy; insns to be deleted by flow analysis and combining
 384       are really changed to NOTEs with a number of -1.
 385    -2 means beginning of a name binding contour; output N_LBRAC.
 386    -3 means end of a contour; output N_RBRAC.  */
 387 DEF_RTL_EXPR(NOTE, "note", "iuusn", 'x')
 388
 389 /* INLINE_HEADER is use by inline function machinery.  The information
 390    it contains helps to build the mapping function between the rtx's of
 391    the function to be inlined and the current function being expanded.  */
 392
 393 DEF_RTL_EXPR(INLINE_HEADER, "inline_header", "iuuuiiiiiieeiiEeEssE", 'x')
 394
 395 /* ----------------------------------------------------------------------
 396    Top level constituents of INSN, JUMP_INSN and CALL_INSN.
 397    ---------------------------------------------------------------------- */
 398
 399 /* Several operations to be done in parallel.  */
 400 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
 401
 402 /* A string that is passed through to the assembler as input.
 403      One can obviously pass comments through by using the
 404      assembler comment syntax.
 405      These occur in an insn all by themselves as the PATTERN.
 406      They also appear inside an ASM_OPERANDS
 407      as a convenient way to hold a string.  */
 408 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
 409
 410 /* An assembler instruction with operands.
 411    1st operand is the instruction template.
 412    2nd operand is the constraint for the output.
 413    3rd operand is the number of the output this expression refers to.
 414      When an insn stores more than one value, a separate ASM_OPERANDS
 415      is made for each output; this integer distinguishes them.
 416    4th is a vector of values of input operands.
 417    5th is a vector of modes and constraints for the input operands.
 418      Each element is an ASM_INPUT containing a constraint string
 419      and whose mode indicates the mode of the input operand.
 420    6th is the name of the containing source file.
 421    7th is the source line number.  */
 422 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
 423
 424 /* A machine-specific operation.
 425    1st operand is a vector of operands being used by the operation so that
 426      any needed reloads can be done.
 427    2nd operand is a unique value saying which of a number of machine-specific
 428      operations is to be performed.
 429    (Note that the vector must be the first operand because of the way that
 430    genrecog.c record positions within an insn.)
 431    This can occur all by itself in a PATTERN, as a component of a PARALLEL,
 432    or inside an expression.  */
 433 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
 434
 435 /* Similar, but a volatile operation and one which may trap.  */
 436 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
 437
 438 /* Vector of addresses, stored as full words.  */
 439 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
 440 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
 441
 442 /* Vector of address differences X0 - BASE, X1 - BASE, ...
 443    First operand is BASE; the vector contains the X's.
 444    The machine mode of this rtx says how much space to leave
 445    for each difference and is adjusted by branch shortening if
 446    CASE_VECTOR_SHORTEN_MODE is defined.
 447    The third and fourth operands store the target labels with the
 448    minimum and maximum addresses respectively.
 449    The fifth operand stores flags for use by branch shortening.
 450   Set at the start of shorten_branches:
 451    min_align: the minimum alignment for any of the target labels.
 452    base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
 453    min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
 454    max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
 455    min_after_base: true iff minimum address target label is after BASE.
 456    max_after_base: true iff maximum address target label is after BASE.
 457   Set by the actual branch shortening process:
 458    offset_unsigned: true iff offsets have to be treated as unsigned.
 459    scale: scaling that is necessary to make offsets fit into the mode.
 460
 461    The third, fourth and fifth operands are only valid when
 462    CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
 463    compilations.  */
 464
 465 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEeei", 'x')
 466
 467 /* ----------------------------------------------------------------------
 468    At the top level of an instruction (perhaps under PARALLEL).
 469    ---------------------------------------------------------------------- */
 470
 471 /* Assignment.
 472    Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
 473    Operand 2 is the value stored there.
 474    ALL assignment must use SET.
 475    Instructions that do multiple assignments must use multiple SET,
 476    under PARALLEL.  */
 477 DEF_RTL_EXPR(SET, "set", "ee", 'x')
 478
 479 /* Indicate something is used in a way that we don't want to explain.
 480    For example, subroutine calls will use the register
 481    in which the static chain is passed.  */
 482 DEF_RTL_EXPR(USE, "use", "e", 'x')
 483
 484 /* Indicate something is clobbered in a way that we don't want to explain.
 485    For example, subroutine calls will clobber some physical registers
 486    (the ones that are by convention not saved).  */
 487 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
 488
 489 /* Call a subroutine.
 490    Operand 1 is the address to call.
 491    Operand 2 is the number of arguments.  */
 492
 493 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
 494
 495 /* Return from a subroutine.  */
 496
 497 DEF_RTL_EXPR(RETURN, "return", "", 'x')
 498
 499 /* Conditional trap.
 500    Operand 1 is the condition.
 501    Operand 2 is the trap code.
 502    For an unconditional trap, make the condition (const_int 1).  */
 503 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ei", 'x')
 504
 505 /* ----------------------------------------------------------------------
 506    Primitive values for use in expressions.
 507    ---------------------------------------------------------------------- */
 508
 509 /* numeric integer constant */
 510 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
 511
 512 /* numeric double constant.
 513    Operand 0 is the MEM that stores this constant in memory,
 514    or various other things (see comments at immed_double_const in varasm.c).
 515    Operand 1 is a chain of all CONST_DOUBLEs in use in the current function.
 516    Remaining operands hold the actual value.
 517    The number of operands may be more than 2 if cross-compiling;
 518    see init_rtl.  */
 519 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", "e0ww", 'o')
 520
 521 /* String constant.  Used only for attributes right now.  */
 522 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
 523
 524 /* This is used to encapsulate an expression whose value is constant
 525    (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
 526    recognized as a constant operand rather than by arithmetic instructions.  */
 527
 528 DEF_RTL_EXPR(CONST, "const", "e", 'o')
 529
 530 /* program counter.  Ordinary jumps are represented
 531    by a SET whose first operand is (PC).  */
 532 DEF_RTL_EXPR(PC, "pc", "", 'o')
 533
 534 /* A register.  The "operand" is the register number, accessed
 535    with the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
 536    than a hardware register is being referred to.  */
 537 DEF_RTL_EXPR(REG, "reg", "i", 'o')
 538
 539 /* A scratch register.  This represents a register used only within a
 540    single insn.  It will be turned into a REG during register allocation
 541    or reload unless the constraint indicates that the register won't be
 542    needed, in which case it can remain a SCRATCH.  This code is
 543    marked as having one operand so it can be turned into a REG.  */
 544 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
 545
 546 /* One word of a multi-word value.
 547    The first operand is the complete value; the second says which word.
 548    The WORDS_BIG_ENDIAN flag controls whether word number 0
 549    (as numbered in a SUBREG) is the most or least significant word.
 550
 551    This is also used to refer to a value in a different machine mode.
 552    For example, it can be used to refer to a SImode value as if it were
 553    Qimode, or vice versa.  Then the word number is always 0.  */
 554 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
 555
 556 /* This one-argument rtx is used for move instructions
 557    that are guaranteed to alter only the low part of a destination.
 558    Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
 559    has an unspecified effect on the high part of REG,
 560    but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
 561    is guaranteed to alter only the bits of REG that are in HImode.
 562
 563    The actual instruction used is probably the same in both cases,
 564    but the register constraints may be tighter when STRICT_LOW_PART
 565    is in use.  */
 566
 567 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
 568
 569 /* (CONCAT a b) represents the virtual concatenation of a and b
 570    to make a value that has as many bits as a and b put together.
 571    This is used for complex values.  Normally it appears only
 572    in DECL_RTLs and during RTL generation, but not in the insn chain.  */
 573 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
 574
 575 /* A memory location; operand is the address.
 576    Can be nested inside a VOLATILE.  */
 577 DEF_RTL_EXPR(MEM, "mem", "e", 'o')
 578
 579 /* Reference to an assembler label in the code for this function.
 580    The operand is a CODE_LABEL found in the insn chain.
 581    The unprinted fields 1 and 2 are used in flow.c for the
 582    LABEL_NEXTREF and CONTAINING_INSN.  */
 583 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
 584
 585 /* Reference to a named label: the string that is the first operand,
 586    with `_' added implicitly in front.
 587    Exception: if the first character explicitly given is `*',
 588    to give it to the assembler, remove the `*' and do not add `_'.  */
 589 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
 590
 591 /* The condition code register is represented, in our imagination,
 592    as a register holding a value that can be compared to zero.
 593    In fact, the machine has already compared them and recorded the
 594    results; but instructions that look at the condition code
 595    pretend to be looking at the entire value and comparing it.  */
 596 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
 597
 598 /* Reference to the address of a register.  Removed by purge_addressof after
 599    CSE has elided as many as possible.
 600    1st operand: the register we may need the address of.
 601    2nd operand: the original pseudo regno we were generated for.
 602    3rd operand: the decl for the object in the register, for
 603      put_reg_in_stack.  */
 604
 605 DEF_RTL_EXPR(ADDRESSOF, "addressof", "ei0", 'o')
 606
 607 /* =====================================================================
 608    A QUEUED expression really points to a member of the queue of instructions
 609    to be output later for postincrement/postdecrement.
 610    QUEUED expressions never become part of instructions.
 611    When a QUEUED expression would be put into an instruction,
 612    instead either the incremented variable or a copy of its previous
 613    value is used.
 614
 615    Operands are:
 616    0. the variable to be incremented (a REG rtx).
 617    1. the incrementing instruction, or 0 if it hasn't been output yet.
 618    2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
 619    3. the body to use for the incrementing instruction
 620    4. the next QUEUED expression in the queue.
 621    ====================================================================== */
 622
 623 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
 624
 625 /* ----------------------------------------------------------------------
 626    Expressions for operators in an rtl pattern
 627    ---------------------------------------------------------------------- */
 628
 629 /* if_then_else.  This is used in representing ordinary
 630    conditional jump instructions.
 631      Operand:
 632      0:  condition
 633      1:  then expr
 634      2:  else expr */
 635 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
 636
 637 /* General conditional. The first operand is a vector composed of pairs of
 638    expressions.  The first element of each pair is evaluated, in turn.
 639    The value of the conditional is the second expression of the first pair
 640    whose first expression evaluates non-zero.  If none of the expressions is
 641    true, the second operand will be used as the value of the conditional.
 642
 643    This should be replaced with use of IF_THEN_ELSE.  */
 644 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
 645
 646 /* Comparison, produces a condition code result.  */
 647 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
 648
 649 /* plus */
 650 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
 651
 652 /* Operand 0 minus operand 1.  */
 653 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
 654
 655 /* Minus operand 0.  */
 656 DEF_RTL_EXPR(NEG, "neg", "e", '1')
 657
 658 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
 659
 660 /* Operand 0 divided by operand 1.  */
 661 DEF_RTL_EXPR(DIV, "div", "ee", '2')
 662 /* Remainder of operand 0 divided by operand 1.  */
 663 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
 664
 665 /* Unsigned divide and remainder.  */
 666 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
 667 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
 668
 669 /* Bitwise operations.  */
 670 DEF_RTL_EXPR(AND, "and", "ee", 'c')
 671
 672 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
 673
 674 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
 675
 676 DEF_RTL_EXPR(NOT, "not", "e", '1')
 677
 678 /* Operand:
 679      0:  value to be shifted.
 680      1:  number of bits.  */
 681 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
 682 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
 683
 684 /* Right shift operations, for machines where these are not the same
 685    as left shifting with a negative argument.  */
 686
 687 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2')
 688 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2')
 689 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2')
 690
 691 /* Minimum and maximum values of two operands.  We need both signed and
 692    unsigned forms.  (We cannot use MIN for SMIN because it conflicts
 693    with a macro of the same name.) */
 694
 695 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
 696 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
 697 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
 698 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
 699
 700 /* These unary operations are used to represent incrementation
 701    and decrementation as they occur in memory addresses.
 702    The amount of increment or decrement are not represented
 703    because they can be understood from the machine-mode of the
 704    containing MEM.  These operations exist in only two cases:
 705    1. pushes onto the stack.
 706    2. created automatically by the life_analysis pass in flow.c.  */
 707 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
 708 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
 709 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
 710 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
 711
 712 /* Comparison operations.  The ordered comparisons exist in two
 713    flavors, signed and unsigned.  */
 714 DEF_RTL_EXPR(NE, "ne", "ee", '<')
 715 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
 716 DEF_RTL_EXPR(GE, "ge", "ee", '<')
 717 DEF_RTL_EXPR(GT, "gt", "ee", '<')
 718 DEF_RTL_EXPR(LE, "le", "ee", '<')
 719 DEF_RTL_EXPR(LT, "lt", "ee", '<')
 720 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
 721 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
 722 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
 723 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
 724
 725 /* Represents the result of sign-extending the sole operand.
 726    The machine modes of the operand and of the SIGN_EXTEND expression
 727    determine how much sign-extension is going on.  */
 728 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
 729
 730 /* Similar for zero-extension (such as unsigned short to int).  */
 731 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
 732
 733 /* Similar but here the operand has a wider mode.  */
 734 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
 735
 736 /* Similar for extending floating-point values (such as SFmode to DFmode).  */
 737 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
 738 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
 739
 740 /* Conversion of fixed point operand to floating point value.  */
 741 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
 742
 743 /* With fixed-point machine mode:
 744    Conversion of floating point operand to fixed point value.
 745    Value is defined only when the operand's value is an integer.
 746    With floating-point machine mode (and operand with same mode):
 747    Operand is rounded toward zero to produce an integer value
 748    represented in floating point.  */
 749 DEF_RTL_EXPR(FIX, "fix", "e", '1')
 750
 751 /* Conversion of unsigned fixed point operand to floating point value.  */
 752 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
 753
 754 /* With fixed-point machine mode:
 755    Conversion of floating point operand to *unsigned* fixed point value.
 756    Value is defined only when the operand's value is an integer.  */
 757 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
 758
 759 /* Absolute value */
 760 DEF_RTL_EXPR(ABS, "abs", "e", '1')
 761
 762 /* Square root */
 763 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
 764
 765 /* Find first bit that is set.
 766    Value is 1 + number of trailing zeros in the arg.,
 767    or 0 if arg is 0.  */
 768 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
 769
 770 /* Reference to a signed bit-field of specified size and position.
 771    Operand 0 is the memory unit (usually SImode or QImode) which
 772    contains the field's first bit.  Operand 1 is the width, in bits.
 773    Operand 2 is the number of bits in the memory unit before the
 774    first bit of this field.
 775    If BITS_BIG_ENDIAN is defined, the first bit is the msb and
 776    operand 2 counts from the msb of the memory unit.
 777    Otherwise, the first bit is the lsb and operand 2 counts from
 778    the lsb of the memory unit.  */
 779 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
 780
 781 /* Similar for unsigned bit-field.  */
 782 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
 783
 784 /* For RISC machines.  These save memory when splitting insns.  */
 785
 786 /* HIGH are the high-order bits of a constant expression.  */
 787 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
 788
 789 /* LO_SUM is the sum of a register and the low-order bits
 790    of a constant expression.  */
 791 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
 792
 793 /*
 794 Local variables:
 795 mode:c
 796 End:
 797 */