| blob | 2129a5de7656702931f38f450674178de7fd966d |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
68 /* This file should be included last. */
71 /* Defined for convenience. */
72 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
74 /* Classifies an address.
76 ADDRESS_REG_IMM
77 A simple base register plus immediate offset.
79 ADDRESS_REG_WB
80 A base register indexed by immediate offset with writeback.
82 ADDRESS_REG_REG
83 A base register indexed by (optionally scaled) register.
85 ADDRESS_REG_UXTW
86 A base register indexed by (optionally scaled) zero-extended register.
88 ADDRESS_REG_SXTW
89 A base register indexed by (optionally scaled) sign-extended register.
91 ADDRESS_LO_SUM
92 A LO_SUM rtx with a base register and "LO12" symbol relocation.
94 ADDRESS_SYMBOLIC:
95 A constant symbolic address, in pc-relative literal pool. */
98 ADDRESS_REG_IMM,
99 ADDRESS_REG_WB,
100 ADDRESS_REG_REG,
101 ADDRESS_REG_UXTW,
102 ADDRESS_REG_SXTW,
103 ADDRESS_LO_SUM,
104 ADDRESS_SYMBOLIC
105 };
109 rtx base;
110 rtx offset;
113 };
115 struct simd_immediate_info
116 {
117 rtx value;
122 };
124 /* The current code model. */
127 #ifdef HAVE_AS_TLS
128 #undef TARGET_HAVE_TLS
129 #define TARGET_HAVE_TLS 1
130 #endif
134 const_tree,
145 /* Major revision number of the ARM Architecture implemented by the target. */
148 /* The processor for which instructions should be scheduled. */
151 /* Mask to specify which instruction scheduling options should be used. */
154 /* Global flag for PC relative loads. */
157 /* Support for command line parsing of boolean flags in the tuning
158 structures. */
159 struct aarch64_flag_desc
160 {
163 };
165 #define AARCH64_FUSION_PAIR(name, internal_name) \
166 { name, AARCH64_FUSE_##internal_name },
168 {
173 };
174 #undef AARCH64_FUION_PAIR
176 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
177 { name, AARCH64_EXTRA_TUNE_##internal_name },
179 {
184 };
185 #undef AARCH64_EXTRA_TUNING_OPTION
187 /* Tuning parameters. */
190 {
191 {
196 },
203 };
206 {
207 {
212 },
219 };
222 {
223 {
228 },
235 };
238 {
239 {
244 },
251 };
254 {
255 {
260 },
267 };
270 {
271 {
276 },
283 };
286 {
288 /* Avoid the use of slow int<->fp moves for spilling by setting
289 their cost higher than memmov_cost. */
293 };
296 {
298 /* Avoid the use of slow int<->fp moves for spilling by setting
299 their cost higher than memmov_cost. */
303 };
306 {
308 /* Avoid the use of slow int<->fp moves for spilling by setting
309 their cost higher than memmov_cost. */
313 };
316 {
318 /* Avoid the use of slow int<->fp moves for spilling by setting
319 their cost higher than memmov_cost (actual, 4 and 9). */
323 };
326 {
331 };
334 {
336 /* Avoid the use of slow int<->fp moves for spilling by setting
337 their cost higher than memmov_cost. */
341 };
344 {
346 /* Avoid the use of int<->fp moves for spilling. */
350 };
353 {
355 /* Avoid the use of int<->fp moves for spilling. */
359 };
361 /* Generic costs for vector insn classes. */
363 {
377 };
379 /* ThunderX costs for vector insn classes. */
381 {
395 };
397 /* Generic costs for vector insn classes. */
399 {
413 };
416 {
430 };
432 /* Generic costs for vector insn classes. */
434 {
448 };
450 /* Costs for vector insn classes for Vulcan. */
452 {
466 };
468 /* Generic costs for branch instructions. */
470 {
473 };
475 /* Branch costs for Cortex-A57. */
477 {
480 };
482 /* Branch costs for Vulcan. */
484 {
487 };
489 /* Generic approximation modes. */
491 {
494 AARCH64_APPROX_NONE /* recip_sqrt */
495 };
497 /* Approximation modes for Exynos M1. */
499 {
502 AARCH64_APPROX_ALL /* recip_sqrt */
503 };
505 /* Approximation modes for X-Gene 1. */
507 {
510 AARCH64_APPROX_ALL /* recip_sqrt */
511 };
514 {
536 };
539 {
562 };
565 {
588 };
591 {
614 };
617 {
640 };
643 {
666 };
669 {
691 };
694 {
716 };
719 {
741 };
744 {
767 };
770 {
792 };
794 /* Support for fine-grained override of the tuning structures. */
795 struct aarch64_tuning_override_function
796 {
799 };
804 static const struct aarch64_tuning_override_function
805 aarch64_tuning_override_functions[] =
806 {
810 };
812 /* A processor implementing AArch64. */
813 struct processor
814 {
822 };
824 /* Architectures implementing AArch64. */
826 {
827 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
828 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
830 #undef AARCH64_ARCH
832 };
834 /* Processor cores implementing AArch64. */
836 {
837 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
838 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
839 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
840 FLAGS, &COSTS##_tunings},
842 #undef AARCH64_CORE
846 };
849 /* Target specification. These are populated by the -march, -mtune, -mcpu
850 handling code or by target attributes. */
855 /* The current tuning set. */
858 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
860 /* An ISA extension in the co-processor and main instruction set space. */
861 struct aarch64_option_extension
862 {
866 };
869 {
873 }
874 aarch64_cc;
876 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
878 /* The condition codes of the processor, and the inverse function. */
880 {
883 };
885 /* Generate code to enable conditional branches in functions over 1 MiB. */
889 {
906 }
908 void
910 {
914 else
916 }
918 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
919 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
920 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
921 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
922 cost (in this case the best class is the lowest cost one). Using ALL_REGS
923 irrespectively of its cost results in bad allocations with many redundant
924 int<->FP moves which are expensive on various cores.
925 To avoid this we don't allow ALL_REGS as the allocno class, but force a
926 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
927 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
928 Otherwise set the allocno class depending on the mode.
929 The result of this is that it is no longer inefficient to have a higher
930 memory move cost than the register move cost.
931 */
933 static reg_class_t
935 reg_class_t best_class)
936 {
947 }
949 static unsigned int
951 {
955 }
957 static int
960 {
968 }
970 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
971 unsigned
973 {
981 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
982 equivalent DWARF register. */
984 }
986 /* Return TRUE if MODE is any of the large INT modes. */
987 static bool
989 {
991 }
993 /* Return TRUE if MODE is any of the vector modes. */
994 static bool
996 {
999 }
1001 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1002 static bool
1005 {
1013 }
1015 /* Implement HARD_REGNO_NREGS. */
1017 int
1019 {
1021 {
1027 }
1029 }
1031 /* Implement HARD_REGNO_MODE_OK. */
1033 int
1035 {
1040 /* The purpose of comparing with ptr_mode is to support the
1041 global register variable associated with the stack pointer
1042 register via the syntax of asm ("wsp") in ILP32. */
1052 {
1054 return
1056 else
1058 }
1061 }
1063 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1064 machine_mode
1066 machine_mode mode)
1067 {
1068 /* Handle modes that fit within single registers. */
1070 {
1073 else
1075 }
1076 /* Fall back to generic for multi-reg and very large modes. */
1077 else
1079 }
1081 /* Return true if calls to DECL should be treated as
1082 long-calls (ie called via a register). */
1083 static bool
1085 {
1087 }
1089 /* Return true if calls to symbol-ref SYM should be treated as
1090 long-calls (ie called via a register). */
1091 bool
1093 {
1095 }
1097 /* Return true if calls to symbol-ref SYM should not go through
1098 plt stubs. */
1100 bool
1102 {
1106 && decl
1107 && (!flag_plt
1113 }
1115 /* Return true if the offsets to a zero/sign-extract operation
1116 represent an expression that matches an extend operation. The
1117 operands represent the paramters from
1119 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1120 bool
1122 rtx extract_imm)
1123 {
1140 }
1142 /* Emit an insn that's a simple single-set. Both the operands must be
1143 known to be valid. */
1146 {
1148 }
1150 /* X and Y are two things to compare using CODE. Emit the compare insn and
1151 return the rtx for register 0 in the proper mode. */
1152 rtx
1154 {
1160 }
1162 /* Build the SYMBOL_REF for __tls_get_addr. */
1166 rtx
1168 {
1172 }
1174 /* Return the TLS model to use for ADDR. */
1176 static enum tls_model
1178 {
1183 {
1187 }
1192 }
1194 /* We'll allow lo_sum's in addresses in our legitimate addresses
1195 so that combine would take care of combining addresses where
1196 necessary, but for generation purposes, we'll generate the address
1197 as :
1198 RTL Absolute
1199 tmp = hi (symbol_ref); adrp x1, foo
1200 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1201 nop
1203 PIC TLS
1204 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1205 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1206 bl __tls_get_addr
1207 nop
1209 Load TLS symbol, depending on TLS mechanism and TLS access model.
1211 Global Dynamic - Traditional TLS:
1212 adrp tmp, :tlsgd:imm
1213 add dest, tmp, #:tlsgd_lo12:imm
1214 bl __tls_get_addr
1216 Global Dynamic - TLS Descriptors:
1217 adrp dest, :tlsdesc:imm
1218 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1219 add dest, dest, #:tlsdesc_lo12:imm
1220 blr tmp
1221 mrs tp, tpidr_el0
1222 add dest, dest, tp
1224 Initial Exec:
1225 mrs tp, tpidr_el0
1226 adrp tmp, :gottprel:imm
1227 ldr dest, [tmp, #:gottprel_lo12:imm]
1228 add dest, dest, tp
1230 Local Exec:
1231 mrs tp, tpidr_el0
1232 add t0, tp, #:tprel_hi12:imm, lsl #12
1233 add t0, t0, #:tprel_lo12_nc:imm
1234 */
1236 static void
1239 {
1241 {
1243 {
1244 /* In ILP32, the mode of dest can be either SImode or DImode. */
1256 }
1263 {
1266 rtx insn;
1267 rtx mem;
1269 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1270 here before rtl expand. Tree IVOPT will generate rtl pattern to
1271 decide rtx costs, in which case pic_offset_table_rtx is not
1272 initialized. For that case no need to generate the first adrp
1273 instruction as the final cost for global variable access is
1274 one instruction. */
1276 {
1277 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1278 using the page base as GOT base, the first page may be wasted,
1279 in the worst scenario, there is only 28K space for GOT).
1281 The generate instruction sequence for accessing global variable
1282 is:
1284 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1286 Only one instruction needed. But we must initialize
1287 pic_offset_table_rtx properly. We generate initialize insn for
1288 every global access, and allow CSE to remove all redundant.
1290 The final instruction sequences will look like the following
1291 for multiply global variables access.
1293 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1295 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1296 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1297 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1298 ... */
1306 }
1309 {
1312 else
1316 }
1317 else
1318 {
1323 }
1325 /* The operand is expected to be MEM. Whenever the related insn
1326 pattern changed, above code which calculate mem should be
1327 updated. */
1333 }
1336 {
1337 /* In ILP32, the mode of dest can be either SImode or DImode,
1338 while the got entry is always of SImode size. The mode of
1339 dest depends on how dest is used: if dest is assigned to a
1340 pointer (e.g. in the memory), it has SImode; it may have
1341 DImode if dest is dereferenced to access the memeory.
1342 This is why we have to handle three different ldr_got_small
1343 patterns here (two patterns for ILP32). */
1345 rtx insn;
1346 rtx mem;
1355 {
1358 else
1362 }
1363 else
1364 {
1369 }
1376 }
1379 {
1391 }
1394 {
1397 rtx tp;
1401 /* In ILP32, the got entry is always of SImode size. Unlike
1402 small GOT, the dest is fixed at reg 0. */
1405 else
1415 }
1418 {
1419 /* In ILP32, the mode of dest can be either SImode or DImode,
1420 while the got entry is always of SImode size. The mode of
1421 dest depends on how dest is used: if dest is assigned to a
1422 pointer (e.g. in the memory), it has SImode; it may have
1423 DImode if dest is dereferenced to access the memeory.
1424 This is why we have to handle three different tlsie_small
1425 patterns here (two patterns for ILP32). */
1431 {
1434 else
1435 {
1438 }
1439 }
1440 else
1441 {
1444 }
1449 }
1455 {
1463 {
1486 }
1490 }
1497 {
1502 {
1505 else
1506 {
1509 }
1510 }
1511 else
1512 {
1515 }
1519 }
1523 }
1524 }
1526 /* Emit a move from SRC to DEST. Assume that the move expanders can
1527 handle all moves if !can_create_pseudo_p (). The distinction is
1528 important because, unlike emit_move_insn, the move expanders know
1529 how to force Pmode objects into the constant pool even when the
1530 constant pool address is not itself legitimate. */
1531 static rtx
1533 {
1537 }
1539 /* Split a 128-bit move operation into two 64-bit move operations,
1540 taking care to handle partial overlap of register to register
1541 copies. Special cases are needed when moving between GP regs and
1542 FP regs. SRC can be a register, constant or memory; DST a register
1543 or memory. If either operand is memory it must not have any side
1544 effects. */
1545 void
1547 {
1558 {
1562 /* Handle FP <-> GP regs. */
1564 {
1569 {
1572 }
1573 else
1574 {
1577 }
1579 }
1581 {
1586 {
1589 }
1590 else
1591 {
1594 }
1596 }
1597 }
1604 /* At most one pairing may overlap. */
1606 {
1609 }
1610 else
1611 {
1614 }
1615 }
1617 bool
1619 {
1622 }
1624 /* Split a complex SIMD combine. */
1626 void
1628 {
1635 {
1639 {
1663 }
1667 }
1668 }
1670 /* Split a complex SIMD move. */
1672 void
1674 {
1681 {
1687 {
1711 }
1715 }
1716 }
1718 bool
1721 {
1725 }
1728 static rtx
1730 {
1733 else
1734 {
1737 }
1738 }
1741 static rtx
1743 {
1745 {
1746 rtx high;
1747 /* Load the full offset into a register. This
1748 might be improvable in the future. */
1754 }
1756 }
1758 static int
1760 machine_mode mode)
1761 {
1770 {
1774 }
1777 {
1779 {
1784 else
1787 }
1789 }
1791 /* Remaining cases are all for DImode. */
1800 {
1801 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1802 For a 64-bit bitmask try whether changing 16 bits to all ones or
1803 zeroes creates a valid bitmask. To check any repeated bitmask,
1804 try using 16 bits from the other 32-bit half of val. */
1807 {
1818 }
1820 {
1822 {
1826 }
1828 }
1829 }
1831 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1832 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1833 otherwise skip zero bits. */
1845 {
1851 num_insns ++;
1852 }
1855 }
1858 void
1860 {
1865 /* Check on what type of symbol it is. */
1869 {
1873 /* If we have (const (plus symbol offset)), separate out the offset
1874 before we start classifying the symbol. */
1879 {
1883 {
1889 }
1894 /* If we aren't generating PC relative literals, then
1895 we need to expand the literal pool access carefully.
1896 This is something that needs to be done in a number
1897 of places, so could well live as a separate function. */
1899 {
1904 }
1921 {
1927 }
1928 /* FALLTHRU */
1941 }
1942 }
1945 {
1948 else
1949 {
1953 }
1956 }
1959 }
1961 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to held
1962 intermediate value if necessary.
1964 This function is sometimes used to adjust the stack pointer, so we must
1965 ensure that it can never cause transient stack deallocation by writing an
1966 invalid value into REGNUM. */
1968 static void
1971 {
1976 /* Do nothing if mdelta is zero. */
1980 /* We only need single instruction if the offset fit into add/sub. */
1982 {
1986 }
1988 /* We need two add/sub instructions, each one performing part of the
1989 calculation. Don't do this if the addend can be loaded into register with
1990 a single instruction, in that case we prefer a move to a scratch register
1991 following by an addition. */
1993 {
2002 }
2004 /* Otherwise use generic function to handle all other situations. */
2009 {
2013 }
2014 }
2016 static bool
2018 tree exp ATTRIBUTE_UNUSED)
2019 {
2020 /* Currently, always true. */
2022 }
2024 /* Implement TARGET_PASS_BY_REFERENCE. */
2026 static bool
2028 machine_mode mode,
2029 const_tree type,
2031 {
2032 HOST_WIDE_INT size;
2033 machine_mode dummymode;
2036 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2040 /* Aggregates are passed by reference based on their size. */
2042 {
2044 }
2046 /* Variable sized arguments are always returned by reference. */
2050 /* Can this be a candidate to be passed in fp/simd register(s)? */
2053 NULL))
2056 /* Arguments which are variable sized or larger than 2 registers are
2057 passed by reference unless they are a homogenous floating point
2058 aggregate. */
2060 }
2062 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2063 static bool
2065 {
2066 machine_mode dummy_mode;
2069 /* Never happens in little-endian mode. */
2073 /* Only composite types smaller than or equal to 16 bytes can
2074 be potentially returned in registers. */
2080 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2081 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2082 is always passed/returned in the least significant bits of fp/simd
2083 register(s). */
2089 }
2091 /* Implement TARGET_FUNCTION_VALUE.
2092 Define how to find the value returned by a function. */
2094 static rtx
2097 {
2098 machine_mode mode;
2101 machine_mode ag_mode;
2108 {
2112 {
2115 }
2116 }
2120 {
2122 {
2125 }
2126 else
2127 {
2129 rtx par;
2133 {
2138 }
2140 }
2141 }
2142 else
2144 }
2146 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2147 Return true if REGNO is the number of a hard register in which the values
2148 of called function may come back. */
2150 static bool
2152 {
2153 /* Maximum of 16 bytes can be returned in the general registers. Examples
2154 of 16-byte return values are: 128-bit integers and 16-byte small
2155 structures (excluding homogeneous floating-point aggregates). */
2159 /* Up to four fp/simd registers can return a function value, e.g. a
2160 homogeneous floating-point aggregate having four members. */
2165 }
2167 /* Implement TARGET_RETURN_IN_MEMORY.
2169 If the type T of the result of a function is such that
2170 void func (T arg)
2171 would require that arg be passed as a value in a register (or set of
2172 registers) according to the parameter passing rules, then the result
2173 is returned in the same registers as would be used for such an
2174 argument. */
2176 static bool
2178 {
2179 HOST_WIDE_INT size;
2180 machine_mode ag_mode;
2186 /* Simple scalar types always returned in registers. */
2190 type,
2193 NULL))
2196 /* Types larger than 2 registers returned in memory. */
2199 }
2201 static bool
2204 {
2207 type,
2209 nregs,
2210 NULL);
2211 }
2213 /* Given MODE and TYPE of a function argument, return the alignment in
2214 bits. The idea is to suppress any stronger alignment requested by
2215 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2216 This is a helper function for local use only. */
2218 static unsigned int
2220 {
2240 }
2242 /* Layout a function argument according to the AAPCS64 rules. The rule
2243 numbers refer to the rule numbers in the AAPCS64. */
2245 static void
2247 const_tree type,
2249 {
2253 HOST_WIDE_INT size;
2255 /* We need to do this once per argument. */
2261 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2262 size
2264 UNITS_PER_WORD);
2268 mode,
2269 type,
2272 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2273 The following code thus handles passing by SIMD/FP registers first. */
2277 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2278 and homogenous short-vector aggregates (HVA). */
2280 {
2285 {
2288 {
2291 }
2292 else
2293 {
2294 rtx par;
2298 {
2301 tmp = gen_rtx_EXPR_LIST
2305 }
2307 }
2309 }
2310 else
2311 {
2312 /* C.3 NSRN is set to 8. */
2315 }
2316 }
2321 /* C6 - C9. though the sign and zero extension semantics are
2322 handled elsewhere. This is the case where the argument fits
2323 entirely general registers. */
2325 {
2330 /* C.8 if the argument has an alignment of 16 then the NGRN is
2331 rounded up to the next even number. */
2333 {
2336 }
2337 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2338 A reg is still generated for it, but the caller should be smart
2339 enough not to use it. */
2341 {
2343 }
2344 else
2345 {
2346 rtx par;
2351 {
2356 }
2358 }
2362 }
2364 /* C.11 */
2367 /* The argument is passed on stack; record the needed number of words for
2368 this argument and align the total size if necessary. */
2369 on_stack:
2375 }
2377 /* Implement TARGET_FUNCTION_ARG. */
2379 static rtx
2382 {
2391 }
2393 void
2395 const_tree fntype ATTRIBUTE_UNUSED,
2396 rtx libname ATTRIBUTE_UNUSED,
2397 const_tree fndecl ATTRIBUTE_UNUSED,
2399 {
2413 {
2420 }
2422 }
2424 static void
2426 machine_mode mode,
2427 const_tree type,
2429 {
2432 {
2442 }
2443 }
2445 bool
2447 {
2450 }
2452 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2453 PARM_BOUNDARY bits of alignment, but will be given anything up
2454 to STACK_BOUNDARY bits if the type requires it. This makes sure
2455 that both before and after the layout of each argument, the Next
2456 Stacked Argument Address (NSAA) will have a minimum alignment of
2457 8 bytes. */
2459 static unsigned int
2461 {
2469 }
2471 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2473 Return true if an argument passed on the stack should be padded upwards,
2474 i.e. if the least-significant byte of the stack slot has useful data.
2476 Small aggregate types are placed in the lowest memory address.
2478 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2480 bool
2482 {
2483 /* On little-endian targets, the least significant byte of every stack
2484 argument is passed at the lowest byte address of the stack slot. */
2488 /* Otherwise, integral, floating-point and pointer types are padded downward:
2489 the least significant byte of a stack argument is passed at the highest
2490 byte address of the stack slot. */
2497 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2499 }
2501 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2503 It specifies padding for the last (may also be the only)
2504 element of a block move between registers and memory. If
2505 assuming the block is in the memory, padding upward means that
2506 the last element is padded after its highest significant byte,
2507 while in downward padding, the last element is padded at the
2508 its least significant byte side.
2510 Small aggregates and small complex types are always padded
2511 upwards.
2513 We don't need to worry about homogeneous floating-point or
2514 short-vector aggregates; their move is not affected by the
2515 padding direction determined here. Regardless of endianness,
2516 each element of such an aggregate is put in the least
2517 significant bits of a fp/simd register.
2519 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2520 register has useful data, and return the opposite if the most
2521 significant byte does. */
2523 bool
2526 {
2528 /* Small composite types are always padded upward. */
2530 {
2535 }
2537 /* Otherwise, use the default padding. */
2539 }
2541 static machine_mode
2543 {
2545 }
2547 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2549 /* We use the 12-bit shifted immediate arithmetic instructions so values
2550 must be multiple of (1 << 12), i.e. 4096. */
2551 #define ARITH_FACTOR 4096
2553 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2554 #error Cannot use simple address calculation for stack probing
2555 #endif
2557 /* The pair of scratch registers used for stack probing. */
2558 #define PROBE_STACK_FIRST_REG 9
2559 #define PROBE_STACK_SECOND_REG 10
2561 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2562 inclusive. These are offsets from the current stack pointer. */
2564 static void
2566 {
2569 /* See the same assertion on PROBE_INTERVAL above. */
2572 /* See if we have a constant small number of probes to generate. If so,
2573 that's the easy case. */
2575 {
2582 }
2584 /* The run-time loop is made up of 8 insns in the generic case while the
2585 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2587 {
2592 stack_pointer_rtx,
2596 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2597 it exceeds SIZE. If only two probes are needed, this will not
2598 generate any code. Then probe at FIRST + SIZE. */
2600 {
2604 }
2608 {
2613 }
2614 else
2616 }
2618 /* Otherwise, do the same as above, but in a loop. Note that we must be
2619 extra careful with variables wrapping around because we might be at
2620 the very top (or the very bottom) of the address space and we have
2621 to be able to handle this case properly; in particular, we use an
2622 equality test for the loop condition. */
2623 else
2624 {
2627 /* Step 1: round SIZE to the previous multiple of the interval. */
2632 /* Step 2: compute initial and final value of the loop counter. */
2634 /* TEST_ADDR = SP + FIRST. */
2638 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2644 /* Step 3: the loop
2646 do
2647 {
2648 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2649 probe at TEST_ADDR
2650 }
2651 while (TEST_ADDR != LAST_ADDR)
2653 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2654 until it is equal to ROUNDED_SIZE. */
2658 else
2662 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2663 that SIZE is equal to ROUNDED_SIZE. */
2666 {
2670 {
2675 }
2676 else
2678 }
2679 }
2681 /* Make sure nothing is scheduled before we are done. */
2683 }
2685 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2686 absolute addresses. */
2690 {
2697 /* Loop. */
2700 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2705 /* Probe at TEST_ADDR. */
2708 /* Test if TEST_ADDR == LAST_ADDR. */
2712 /* Branch. */
2718 }
2720 static bool
2722 {
2723 /* In aarch64_override_options_after_change
2724 flag_omit_leaf_frame_pointer turns off the frame pointer by
2725 default. Turn it back on now if we've not got a leaf
2726 function. */
2732 }
2734 /* Mark the registers that need to be saved by the callee and calculate
2735 the size of the callee-saved registers area and frame record (both FP
2736 and LR may be omitted). */
2737 static void
2739 {
2746 #define SLOT_NOT_REQUIRED (-2)
2747 #define SLOT_REQUIRED (-1)
2752 /* First mark all the registers that really need to be saved... */
2759 /* ... that includes the eh data registers (if needed)... */
2765 /* ... and any callee saved register that dataflow says is live. */
2778 {
2779 /* FP and LR are placed in the linkage record. */
2785 }
2787 /* Now assign stack slots for them. */
2790 {
2797 }
2801 {
2809 }
2815 HOST_WIDE_INT varargs_and_saved_regs_size
2842 {
2843 /* Simple, small frame with no outgoing arguments:
2844 stp reg1, reg2, [sp, -frame_size]!
2845 stp reg3, reg4, [sp, 16] */
2847 }
2852 {
2853 /* Frame with small outgoing arguments:
2854 sub sp, sp, frame_size
2855 stp reg1, reg2, [sp, outgoing_args_size]
2856 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2860 }
2862 {
2863 /* Frame with large outgoing arguments but a small local area:
2864 stp reg1, reg2, [sp, -hard_fp_offset]!
2865 stp reg3, reg4, [sp, 16]
2866 sub sp, sp, outgoing_args_size */
2870 }
2873 {
2874 /* Frame with large local area and outgoing arguments (this pushes the
2875 callee-saves first, followed by the locals and outgoing area):
2876 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2877 stp reg3, reg4, [sp, 16]
2878 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2884 }
2885 else
2886 {
2887 /* Frame with large local area and outgoing arguments using frame pointer:
2888 sub sp, sp, hard_fp_offset
2889 stp x29, x30, [sp, 0]
2890 add x29, sp, 0
2891 stp reg3, reg4, [sp, 16]
2892 sub sp, sp, outgoing_args_size */
2896 }
2899 }
2901 static bool
2903 {
2905 }
2907 static unsigned
2909 {
2911 regno ++;
2913 }
2915 static void
2917 HOST_WIDE_INT adjustment)
2918 {
2929 }
2931 static rtx
2933 HOST_WIDE_INT adjustment)
2934 {
2936 {
2947 }
2948 }
2950 static void
2952 {
2967 }
2969 static rtx
2971 HOST_WIDE_INT adjustment)
2972 {
2974 {
2983 }
2984 }
2986 static void
2989 {
2996 {
3000 }
3001 else
3002 {
3007 }
3008 }
3010 static rtx
3012 rtx reg2)
3013 {
3015 {
3024 }
3025 }
3027 static rtx
3029 rtx mem2)
3030 {
3032 {
3041 }
3042 }
3045 static void
3048 {
3058 {
3060 HOST_WIDE_INT offset;
3070 offset));
3078 {
3080 rtx mem2;
3084 offset));
3086 reg2));
3088 /* The first part of a frame-related parallel insn is
3089 always assumed to be relevant to the frame
3090 calculations; subsequent parts, are only
3091 frame-related if explicitly marked. */
3094 }
3095 else
3099 }
3100 }
3102 static void
3106 {
3112 HOST_WIDE_INT offset;
3117 {
3134 {
3136 rtx mem2;
3144 }
3145 else
3148 }
3149 }
3151 /* AArch64 stack frames generated by this compiler look like:
3153 +-------------------------------+
3154 | |
3155 | incoming stack arguments |
3156 | |
3157 +-------------------------------+
3158 | | <-- incoming stack pointer (aligned)
3159 | callee-allocated save area |
3160 | for register varargs |
3161 | |
3162 +-------------------------------+
3163 | local variables | <-- frame_pointer_rtx
3164 | |
3165 +-------------------------------+
3166 | padding0 | \
3167 +-------------------------------+ |
3168 | callee-saved registers | | frame.saved_regs_size
3169 +-------------------------------+ |
3170 | LR' | |
3171 +-------------------------------+ |
3172 | FP' | / <- hard_frame_pointer_rtx (aligned)
3173 +-------------------------------+
3174 | dynamic allocation |
3175 +-------------------------------+
3176 | padding |
3177 +-------------------------------+
3178 | outgoing stack arguments | <-- arg_pointer
3179 | |
3180 +-------------------------------+
3181 | | <-- stack_pointer_rtx (aligned)
3183 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3184 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3185 unchanged. */
3187 /* Generate the prologue instructions for entry into a function.
3188 Establish the stack frame by decreasing the stack pointer with a
3189 properly calculated size and, if necessary, create a frame record
3190 filled with the values of LR and previous frame pointer. The
3191 current FP is also set up if it is in use. */
3193 void
3195 {
3211 {
3213 {
3217 }
3220 }
3228 {
3233 stack_pointer_rtx,
3237 }
3245 }
3247 /* Return TRUE if we can use a simple_return insn.
3249 This function checks whether the callee saved stack is empty, which
3250 means no restore actions are need. The pro_and_epilogue will use
3251 this to check whether shrink-wrapping opt is feasible. */
3253 bool
3255 {
3265 }
3267 /* Generate the epilogue instructions for returning from a function.
3268 This is almost exactly the reverse of the prolog sequence, except
3269 that we need to insert barriers to avoid scheduling loads that read
3270 from a deallocated stack, and we optimize the unwind records by
3271 emitting them all together if possible. */
3272 void
3274 {
3286 /* We need to add memory barrier to prevent read from deallocated stack. */
3290 /* Emit a barrier to prevent loads from a deallocated stack. */
3292 {
3295 }
3297 /* Restore the stack pointer from the frame pointer if it may not
3298 be the same as the stack pointer. */
3300 {
3302 hard_frame_pointer_rtx,
3304 /* If writeback is used when restoring callee-saves, the CFA
3305 is restored on the instruction doing the writeback. */
3307 }
3308 else
3323 {
3324 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3330 }
3335 {
3336 /* Emit delayed restores and reset the CFA to be SP. */
3341 }
3343 /* Stack adjustment for exception handler. */
3345 {
3346 /* We need to unwind the stack by the offset computed by
3347 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3348 to be SP; letting the CFA move during this adjustment
3349 is just as correct as retaining the CFA from the body
3350 of the function. Therefore, do nothing special. */
3352 }
3357 }
3359 /* Return the place to copy the exception unwinding return address to.
3360 This will probably be a stack slot, but could (in theory be the
3361 return register). */
3362 rtx
3364 {
3365 HOST_WIDE_INT fp_offset;
3375 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
3376 result in a store to save LR introduced by builtin_eh_return () being
3377 incorrectly deleted because the alias is not detected.
3378 So in the calculation of the address to copy the exception unwinding
3379 return address to, we note 2 cases.
3380 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
3381 we return a SP-relative location since all the addresses are SP-relative
3382 in this case. This prevents the store from being optimized away.
3383 If the fp_offset is not 0, then the addresses will be FP-relative and
3384 therefore we return a FP-relative location. */
3387 {
3391 else
3394 }
3396 /* If FP is not needed, we calculate the location of LR, which would be
3397 at the top of the saved registers block. */
3401 stack_pointer_rtx,
3402 fp_offset
3405 }
3407 /* Output code to add DELTA to the first argument, and then jump
3408 to FUNCTION. Used for C++ multiple inheritance. */
3409 static void
3411 HOST_WIDE_INT delta,
3412 HOST_WIDE_INT vcall_offset,
3413 tree function)
3414 {
3415 /* The this pointer is always in x0. Note that this differs from
3416 Arm where the this pointer maybe bumped to r1 if r0 is required
3417 to return a pointer to an aggregate. On AArch64 a result value
3418 pointer will be in x8. */
3428 else
3429 {
3438 {
3442 else
3444 }
3448 else
3455 else
3456 {
3458 Pmode);
3460 }
3464 else
3470 }
3472 /* Generate a tail call to the target function. */
3474 {
3477 }
3489 /* Stop pretending to be a post-reload pass. */
3491 }
3493 static bool
3495 {
3500 {
3504 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3505 TLS offsets, not real symbol references. */
3508 }
3510 }
3513 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3514 a left shift of 0 or 12 bits. */
3515 bool
3517 {
3520 );
3521 }
3524 /* Return true if val is an immediate that can be loaded into a
3525 register by a MOVZ instruction. */
3526 static bool
3528 {
3530 {
3534 }
3535 else
3536 {
3537 /* Ignore sign extension. */
3539 }
3542 }
3544 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3547 {
3553 };
3556 /* Return true if val is a valid bitmask immediate. */
3558 bool
3560 {
3564 /* Check for a single sequence of one bits and return quickly if so.
3565 The special cases of all ones and all zeroes returns false. */
3572 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3576 /* Invert if the immediate doesn't start with a zero bit - this means we
3577 only need to search for sequences of one bits. */
3581 /* Find the first set bit and set tmp to val with the first sequence of one
3582 bits removed. Return success if there is a single sequence of ones. */
3589 /* Find the next set bit and compute the difference in bit position. */
3594 /* Check the bit position difference is a power of 2, and that the first
3595 sequence of one bits fits within 'bits' bits. */
3599 /* Check the sequence of one bits is repeated 64/bits times. */
3601 }
3604 /* Return true if val is an immediate that can be loaded into a
3605 register in a single instruction. */
3606 bool
3608 {
3612 }
3614 static bool
3616 {
3624 {
3628 else
3629 /* Avoid generating a 64-bit relocation in ILP32; leave
3630 to aarch64_expand_mov_immediate to handle it properly. */
3632 }
3635 }
3637 /* Implement TARGET_CASE_VALUES_THRESHOLD.
3638 The expansion for a table switch is quite expensive due to the number
3639 of instructions, the table lookup and hard to predict indirect jump.
3640 When optimizing for speed, and -O3 enabled, use the per-core tuning if
3641 set, otherwise use tables for > 16 cases as a tradeoff between size and
3642 performance. When optimizing for size, use the default setting. */
3644 static unsigned int
3646 {
3647 /* Use the specified limit for the number of cases before using jump
3648 tables at higher optimization levels. */
3652 else
3654 }
3656 /* Return true if register REGNO is a valid index register.
3657 STRICT_P is true if REG_OK_STRICT is in effect. */
3659 bool
3661 {
3663 {
3671 }
3673 }
3675 /* Return true if register REGNO is a valid base register for mode MODE.
3676 STRICT_P is true if REG_OK_STRICT is in effect. */
3678 bool
3680 {
3682 {
3690 }
3692 /* The fake registers will be eliminated to either the stack or
3693 hard frame pointer, both of which are usually valid base registers.
3694 Reload deals with the cases where the eliminated form isn't valid. */
3699 }
3701 /* Return true if X is a valid base register for mode MODE.
3702 STRICT_P is true if REG_OK_STRICT is in effect. */
3704 static bool
3706 {
3711 }
3713 /* Return true if address offset is a valid index. If it is, fill in INFO
3714 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3716 static bool
3719 {
3721 rtx index;
3724 /* (reg:P) */
3727 {
3731 }
3732 /* (sign_extend:DI (reg:SI)) */
3737 {
3742 }
3743 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3750 {
3755 }
3756 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3763 {
3768 }
3769 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3776 {
3784 }
3785 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3786 (const_int 0xffffffff<<shift)) */
3793 {
3799 }
3800 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3807 {
3815 }
3816 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3817 (const_int 0xffffffff<<shift)) */
3824 {
3830 }
3831 /* (mult:P (reg:P) (const_int scale)) */
3836 {
3840 }
3841 /* (ashift:P (reg:P) (const_int shift)) */
3846 {
3850 }
3851 else
3862 {
3867 }
3870 }
3872 bool
3874 {
3878 }
3882 HOST_WIDE_INT offset)
3883 {
3885 }
3889 {
3893 }
3895 /* Return true if MODE is one of the modes for which we
3896 support LDP/STP operations. */
3898 static bool
3900 {
3905 }
3907 /* Return true if REGNO is a virtual pointer register, or an eliminable
3908 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
3909 include stack_pointer or hard_frame_pointer. */
3910 static bool
3912 {
3917 }
3919 /* Return true if X is a valid address for machine mode MODE. If it is,
3920 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3921 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3923 static bool
3927 {
3931 /* On BE, we use load/store pair for all large int mode load/stores. */
3933 || (BYTES_BIG_ENDIAN
3937 !load_store_pair_p
3941 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3942 REG addressing. */
3948 {
3964 {
3970 }
3975 {
3982 /* TImode and TFmode values are allowed in both pairs of X
3983 registers and individual Q registers. The available
3984 address modes are:
3985 X,X: 7-bit signed scaled offset
3986 Q: 9-bit signed offset
3987 We conservatively require an offset representable in either mode.
3988 When performing the check for pairs of X registers i.e. LDP/STP
3989 pass down DImode since that is the natural size of the LDP/STP
3990 instruction memory accesses. */
3995 /* A 7bit offset check because OImode will emit a ldp/stp
3996 instruction (only big endian will get here).
3997 For ldp/stp instructions, the offset is scaled for the size of a
3998 single element of the pair. */
4002 /* Three 9/12 bit offsets checks because CImode will emit three
4003 ldr/str instructions (only big endian will get here). */
4010 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4011 instructions (only big endian will get here). */
4020 else
4023 }
4026 {
4027 /* Look for base + (scaled/extended) index register. */
4030 {
4033 }
4036 {
4039 }
4040 }
4061 {
4062 HOST_WIDE_INT offset;
4066 /* TImode and TFmode values are allowed in both pairs of X
4067 registers and individual Q registers. The available
4068 address modes are:
4069 X,X: 7-bit signed scaled offset
4070 Q: 9-bit signed offset
4071 We conservatively require an offset representable in either mode.
4072 */
4080 else
4082 }
4088 /* load literal: pc-relative constant pool entry. Only supported
4089 for SI mode or larger. */
4093 {
4101 }
4110 {
4115 {
4116 /* The symbol and offset must be aligned to the access size. */
4123 {
4127 }
4133 else
4142 }
4143 }
4148 }
4149 }
4151 bool
4153 {
4154 rtx offset;
4158 }
4160 /* Classify the base of symbolic expression X. */
4162 enum aarch64_symbol_type
4164 {
4165 rtx offset;
4169 }
4172 /* Return TRUE if X is a legitimate address for accessing memory in
4173 mode MODE. */
4174 static bool
4176 {
4180 }
4182 /* Return TRUE if X is a legitimate address for accessing memory in
4183 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4184 pair operation. */
4185 bool
4188 {
4192 }
4194 /* Return TRUE if rtx X is immediate constant 0.0 */
4195 bool
4197 {
4204 }
4206 /* Return the fixed registers used for condition codes. */
4208 static bool
4210 {
4214 }
4216 /* Emit call insn with PAT and do aarch64-specific handling. */
4218 void
4220 {
4226 }
4228 machine_mode
4230 {
4231 /* All floating point compares return CCFP if it is an equality
4232 comparison, and CCFPE otherwise. */
4234 {
4236 {
4257 }
4258 }
4260 /* Equality comparisons of short modes against zero can be performed
4261 using the TST instruction with the appropriate bitmask. */
4276 /* A compare with a shifted operand. Because of canonicalization,
4277 the comparison will have to be swapped when we emit the assembly
4278 code. */
4286 /* Similarly for a negated operand, but we can only do this for
4287 equalities. */
4294 /* A test for unsigned overflow. */
4301 /* For everything else, return CCmode. */
4303 }
4305 static int
4308 int
4310 {
4317 }
4319 static int
4321 {
4323 {
4327 {
4341 }
4346 {
4358 }
4363 {
4375 }
4380 {
4386 }
4391 {
4395 }
4400 {
4404 }
4410 }
4413 }
4415 bool
4417 HOST_WIDE_INT minval,
4418 HOST_WIDE_INT maxval)
4419 {
4420 HOST_WIDE_INT firstval;
4437 }
4439 bool
4441 {
4443 }
4446 /* N Z C V. */
4447 #define AARCH64_CC_V 1
4448 #define AARCH64_CC_C (1 << 1)
4449 #define AARCH64_CC_Z (1 << 2)
4450 #define AARCH64_CC_N (1 << 3)
4452 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4454 {
4471 };
4473 static void
4475 {
4477 {
4478 /* An integer or symbol address without a preceding # sign. */
4481 {
4493 {
4496 }
4497 /* Fall through. */
4501 }
4505 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4506 {
4511 {
4514 }
4517 {
4530 }
4531 }
4535 {
4538 /* Print N such that 2^N == X. */
4540 {
4543 }
4546 }
4550 /* Print the number of non-zero bits in X (a const_int). */
4552 {
4555 }
4561 /* Print the higher numbered register of a pair (TImode) of regs. */
4563 {
4566 }
4573 {
4575 /* Print a condition (eq, ne, etc) or its inverse. */
4577 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
4579 {
4583 }
4586 {
4589 }
4596 }
4604 /* Print a scalar FP/SIMD register name. */
4606 {
4607 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4609 }
4617 /* Print the first FP/SIMD register name in a list. */
4619 {
4620 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4622 }
4627 /* Print a scalar FP/SIMD register name + 1. */
4629 {
4630 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4632 }
4637 /* Print bottom 16 bits of integer constant in hex. */
4639 {
4642 }
4648 /* Print a general register name or the zero register (32-bit or
4649 64-bit). */
4652 {
4655 }
4658 {
4661 }
4664 {
4667 }
4669 /* Fall through */
4672 /* Print a normal operand, if it's a general register, then we
4673 assume DImode. */
4675 {
4678 }
4681 {
4702 {
4705 HOST_WIDE_INT_MIN,
4706 HOST_WIDE_INT_MAX));
4708 }
4710 {
4712 }
4713 else
4718 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
4719 be getting CONST_DOUBLEs holding integers. */
4722 {
4725 }
4727 {
4728 #define buf_size 20
4736 #undef buf_size
4737 }
4743 }
4751 {
4778 }
4784 {
4819 }
4826 {
4832 }
4837 {
4838 HOST_WIDE_INT cond_code;
4839 /* Print nzcv. */
4842 {
4845 }
4850 }
4856 }
4857 }
4859 static void
4861 {
4866 {
4870 else
4879 else
4888 else
4897 else
4904 {
4931 }
4942 }
4945 }
4947 bool
4949 {
4956 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4957 referencing instruction, but they are constant offsets, not
4958 symbols. */
4964 {
4966 {
4972 }
4975 }
4978 }
4980 /* Implement REGNO_REG_CLASS. */
4982 enum reg_class
4984 {
4999 }
5001 static rtx
5003 {
5004 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5005 where mask is selected by alignment and size of the offset.
5006 We try to pick as large a range for the offset as possible to
5007 maximize the chance of a CSE. However, for aligned addresses
5008 we limit the range to 4k so that structures with different sized
5009 elements are likely to use the same base. We need to be careful
5010 not to split a CONST for some forms of address expression, otherwise
5011 it will generate sub-optimal code. */
5014 {
5020 {
5024 /* Force any scaling into a temp for CSE. */
5028 /* Let the pointer register be in op0. */
5032 /* If the pointer is virtual or frame related, then we know that
5033 virtual register instantiation or register elimination is going
5034 to apply a second constant. We want the two constants folded
5035 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5037 {
5041 }
5043 /* Otherwise, in order to encourage CSE (and thence loop strength
5044 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5048 }
5050 /* Does it look like we'll need a load/store-pair operation? */
5051 HOST_WIDE_INT base_offset;
5056 /* For offsets aren't a multiple of the access size, the limit is
5057 -256...255. */
5060 else
5064 {
5068 }
5069 }
5072 }
5074 /* Return the reload icode required for a constant pool in mode. */
5075 static enum insn_code
5077 {
5079 {
5115 }
5118 }
5119 static reg_class_t
5121 reg_class_t rclass,
5122 machine_mode mode,
5124 {
5126 /* If we have to disable direct literal pool loads and stores because the
5127 function is too big, then we need a scratch register. */
5132 {
5135 }
5137 /* Without the TARGET_SIMD instructions we cannot move a Q register
5138 to a Q register directly. We need a scratch. */
5142 {
5148 }
5150 /* A TFmode or TImode memory access should be handled via an FP_REGS
5151 because AArch64 has richer addressing modes for LDR/STR instructions
5152 than LDP/STP instructions. */
5161 }
5163 static bool
5165 {
5166 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5167 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5170 {
5182 }
5183 else
5184 {
5185 /* If we decided that we didn't need a leaf frame pointer but then used
5186 LR in the function, then we'll want a frame pointer after all, so
5187 prevent this elimination to ensure a frame pointer is used. */
5189 && flag_omit_leaf_frame_pointer
5192 }
5195 }
5197 HOST_WIDE_INT
5199 {
5203 {
5210 }
5213 {
5217 }
5220 }
5222 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5223 previous frame. */
5225 rtx
5227 {
5231 }
5234 static void
5236 {
5238 {
5241 }
5242 else
5243 {
5246 }
5251 }
5253 static void
5255 {
5259 /* Don't need to copy the trailing D-words, we fill those in below. */
5271 /* XXX We should really define a "clear_cache" pattern and use
5272 gen_clear_cache(). */
5277 ptr_mode);
5278 }
5280 static unsigned char
5282 {
5284 {
5291 return
5303 }
5305 }
5307 static reg_class_t
5309 {
5314 {
5320 }
5322 /* If it's an integer immediate that MOVI can't handle, then
5323 FP_REGS is not an option, so we return NO_REGS instead. */
5328 /* Register eliminiation can result in a request for
5329 SP+constant->FP_REGS. We cannot support such operations which
5330 use SP as source and an FP_REG as destination, so reject out
5331 right now. */
5333 {
5336 /* Look through a possible SUBREG introduced by ILP32. */
5342 POINTER_REGS));
5344 }
5347 }
5349 void
5351 {
5353 }
5355 static void
5357 {
5360 else
5361 {
5369 }
5370 }
5372 static void
5374 {
5377 else
5378 {
5386 }
5387 }
5391 {
5397 {
5398 {
5401 },
5402 {
5405 },
5406 {
5409 },
5410 /* We assume that DImode is only generated when not optimizing and
5411 that we don't really need 64-bit address offsets. That would
5412 imply an object file with 8GB of code in a single function! */
5413 {
5416 }
5417 };
5425 /* Need to implement table size reduction, by chaning the code below. */
5435 }
5438 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5439 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5440 operator. */
5442 int
5444 {
5446 {
5449 {
5453 }
5454 }
5456 }
5458 /* Constant pools are per function only when PC relative
5459 literal loads are true or we are in the large memory
5460 model. */
5464 {
5467 }
5469 static bool
5471 {
5472 /* Fixme:: In an ideal world this would work similar
5473 to the logic in aarch64_select_rtx_section but this
5474 breaks bootstrap in gcc go. For now we workaround
5475 this by returning false here. */
5477 }
5479 /* Select appropriate section for constants depending
5480 on where we place literal pools. */
5484 rtx x,
5486 {
5491 }
5493 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5494 void
5496 HOST_WIDE_INT offset)
5497 {
5498 /* When using per-function literal pools, we must ensure that any code
5499 section is aligned to the minimal instruction length, lest we get
5500 errors from the assembler re "unaligned instructions". */
5503 }
5505 /* Costs. */
5507 /* Helper function for rtx cost calculation. Strip a shift expression
5508 from X. Returns the inner operand if successful, or the original
5509 expression on failure. */
5510 static rtx
5512 {
5515 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5516 we can convert both to ROR during final output. */
5531 }
5533 /* Helper function for rtx cost calculation. Strip an extend
5534 expression from X. Returns the inner operand if successful, or the
5535 original expression on failure. We deal with a number of possible
5536 canonicalization variations here. */
5537 static rtx
5539 {
5542 /* Zero and sign extraction of a widened value. */
5550 /* It can also be represented (for zero-extend) as an AND with an
5551 immediate. */
5560 /* Now handle extended register, as this may also have an optional
5561 left shift by 1..4. */
5575 }
5577 /* Return true iff CODE is a shift supported in combination
5578 with arithmetic instructions. */
5580 static bool
5582 {
5584 }
5586 /* Helper function for rtx cost calculation. Calculate the cost of
5587 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5588 Return the calculated cost of the expression, recursing manually in to
5589 operands where needed. */
5591 static int
5593 {
5609 /* Integer multiply/fma. */
5611 {
5612 /* The multiply will be canonicalized as a shift, cost it as such. */
5616 {
5620 {
5622 {
5624 /* ARITH + shift-by-register. */
5627 /* ARITH + extended register. We don't have a cost field
5628 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5630 else
5631 /* ARITH + shift-by-immediate. */
5633 }
5634 else
5635 /* LSL (immediate). */
5638 }
5639 /* Strip extends as we will have costed them in the case above. */
5646 }
5648 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5649 compound and let the below cases handle it. After all, MNEG is a
5650 special-case alias of MSUB. */
5652 {
5655 }
5657 /* Integer multiplies or FMAs have zero/sign extending variants. */
5662 {
5667 {
5669 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5671 else
5672 /* MUL/SMULL/UMULL. */
5674 }
5677 }
5679 /* This is either an integer multiply or a MADD. In both cases
5680 we want to recurse and cost the operands. */
5685 {
5687 /* MADD/MSUB. */
5689 else
5690 /* MUL. */
5692 }
5695 }
5696 else
5697 {
5699 {
5700 /* Floating-point FMA/FMUL can also support negations of the
5701 operands, unless the rounding mode is upward or downward in
5702 which case FNMUL is different than FMUL with operand negation. */
5706 {
5711 }
5714 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5716 else
5717 /* FMUL/FNMUL. */
5719 }
5724 }
5725 }
5727 static int
5729 machine_mode mode,
5730 addr_space_t as ATTRIBUTE_UNUSED,
5732 {
5740 {
5742 {
5743 /* This is a CONST or SYMBOL ref which will be split
5744 in a different way depending on the code model in use.
5745 Cost it through the generic infrastructure. */
5747 /* Divide through by the cost of one instruction to
5748 bring it to the same units as the address costs. */
5750 /* The cost is then the cost of preparing the address,
5751 followed by an immediate (possibly 0) offset. */
5753 }
5754 else
5755 {
5756 /* This is most likely a jump table from a case
5757 statement. */
5759 }
5760 }
5763 {
5775 else
5794 }
5798 {
5799 /* For the sake of calculating the cost of the shifted register
5800 component, we can treat same sized modes in the same way. */
5802 {
5815 /* We can't tell, or this is a 128-bit vector. */
5819 }
5820 }
5823 }
5825 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5826 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5827 to be taken. */
5829 int
5831 {
5832 /* When optimizing for speed, use the cost of unpredictable branches. */
5838 else
5840 }
5842 /* Return true if the RTX X in mode MODE is a zero or sign extract
5843 usable in an ADD or SUB (extended register) instruction. */
5844 static bool
5846 {
5847 /* Catch add with a sign extract.
5848 This is add_<optab><mode>_multp2. */
5851 {
5862 op1))
5863 {
5865 }
5866 }
5867 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
5868 No shift. */
5874 }
5876 static bool
5878 {
5880 {
5892 }
5893 }
5895 /* Return true iff X is an rtx that will match an extr instruction
5896 i.e. as described in the *extr<mode>5_insn family of patterns.
5897 OP0 and OP1 will be set to the operands of the shifts involved
5898 on success and will be NULL_RTX otherwise. */
5900 static bool
5902 {
5917 {
5918 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
5930 {
5934 }
5935 }
5938 }
5940 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5941 storing it in *COST. Result is true if the total cost of the operation
5942 has now been calculated. */
5943 static bool
5945 {
5946 rtx inner;
5947 rtx comparator;
5951 {
5955 }
5956 else
5957 {
5961 }
5964 {
5965 /* Conditional branch. */
5968 else
5969 {
5971 {
5973 {
5974 /* TBZ/TBNZ/CBZ/CBNZ. */
5976 /* TBZ/TBNZ. */
5979 else
5980 /* CBZ/CBNZ. */
5984 }
5985 }
5987 {
5988 /* TBZ/TBNZ. */
5991 }
5992 }
5993 }
5995 {
5996 /* CCMP. */
5998 {
5999 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6003 {
6010 else
6012 }
6014 }
6016 /* It's a conditional operation based on the status flags,
6017 so it must be some flavor of CSEL. */
6019 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6025 {
6026 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6029 }
6034 }
6036 /* We don't know what this is, cost all operands. */
6038 }
6040 /* Check whether X is a bitfield operation of the form shift + extend that
6041 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6042 operand to which the bitfield operation is applied. Otherwise return
6043 NULL_RTX. */
6045 static rtx
6047 {
6061 {
6079 }
6082 }
6084 /* Return true if the mask and a shift amount from an RTX of the form
6085 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6086 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6088 bool
6090 {
6095 }
6097 /* Calculate the cost of calculating X, storing it in *COST. Result
6098 is true if the total cost of the operation has now been calculated. */
6099 static bool
6102 {
6108 /* By default, assume that everything has equivalent cost to the
6109 cheapest instruction. Any additional costs are applied as a delta
6110 above this default. */
6114 {
6116 /* The cost depends entirely on the operands to SET. */
6122 {
6125 {
6139 }
6148 /* Fall through. */
6150 /* The cost is one per vector-register copied. */
6152 {
6156 }
6157 /* const0_rtx is in general free, but we will use an
6158 instruction to set a register to 0. */
6160 {
6161 /* The cost is 1 per register copied. */
6165 }
6166 else
6167 /* Cost is just the cost of the RHS of the set. */
6173 /* Bit-field insertion. Strip any redundant widening of
6174 the RHS to meet the width of the target. */
6185 {
6186 /* MOV immediate is assumed to always be cheap. */
6188 }
6189 else
6190 {
6191 /* BFM. */
6195 }
6200 /* We can't make sense of this, assume default cost. */
6203 }
6207 /* If an instruction can incorporate a constant within the
6208 instruction, the instruction's expression avoids calling
6209 rtx_cost() on the constant. If rtx_cost() is called on a
6210 constant, then it is usually because the constant must be
6211 moved into a register by one or more instructions.
6213 The exception is constant 0, which can be expressed
6214 as XZR/WZR and is therefore free. The exception to this is
6215 if we have (set (reg) (const0_rtx)) in which case we must cost
6216 the move. However, we can catch that when we cost the SET, so
6217 we don't need to consider that here. */
6220 else
6221 {
6222 /* To an approximation, building any other constant is
6223 proportionally expensive to the number of instructions
6224 required to build that constant. This is true whether we
6225 are compiling for SPEED or otherwise. */
6228 }
6233 {
6234 /* mov[df,sf]_aarch64. */
6236 /* FMOV (scalar immediate). */
6239 {
6240 /* This will be a load from memory. */
6243 else
6245 }
6246 else
6247 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6248 or MOV v0.s[0], wzr - neither of which are modeled by the
6249 cost tables. Just use the default cost. */
6250 {
6251 }
6252 }
6258 {
6259 /* For loads we want the base cost of a load, plus an
6260 approximation for the additional cost of the addressing
6261 mode. */
6275 }
6283 {
6285 {
6286 /* FNEG. */
6288 }
6290 }
6293 {
6296 {
6297 /* CSETM. */
6300 }
6302 /* Cost this as SUB wzr, X. */
6306 }
6309 {
6310 /* Support (neg(fma...)) as a single instruction only if
6311 sign of zeros is unimportant. This matches the decision
6312 making in aarch64.md. */
6314 {
6315 /* FNMADD. */
6318 }
6320 {
6321 /* FNMUL. */
6324 }
6326 /* FNEG. */
6329 }
6336 {
6339 else
6341 }
6351 {
6355 }
6358 {
6359 /* TODO: A write to the CC flags possibly costs extra, this
6360 needs encoding in the cost tables. */
6363 /* ANDS. */
6365 {
6368 }
6371 {
6372 /* ADDS (and CMN alias). */
6375 }
6378 {
6379 /* SUBS. */
6382 }
6387 {
6388 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6389 Handle it here directly rather than going to cost_logic
6390 since we know the immediate generated for the TST is valid
6391 so we can avoid creating an intermediate rtx for it only
6392 for costing purposes. */
6399 }
6402 {
6403 /* CMN. */
6410 }
6412 /* CMP.
6414 Compare can freely swap the order of operands, and
6415 canonicalization puts the more complex operation first.
6416 But the integer MINUS logic expects the shift/extend
6417 operation in op1. */
6420 {
6423 }
6425 }
6428 {
6429 /* FCMP. */
6434 {
6436 /* FCMP supports constant 0.0 for no extra cost. */
6438 }
6440 }
6443 {
6444 /* Vector compare. */
6449 {
6450 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6451 cost. */
6453 }
6455 }
6459 {
6463 cost_minus:
6466 /* Detect valid immediates. */
6472 {
6474 /* SUB(S) (immediate). */
6477 }
6479 /* Look for SUB (extended register). */
6481 {
6489 }
6493 /* Cost this as an FMA-alike operation. */
6497 {
6500 speed);
6502 }
6507 {
6509 {
6510 /* Vector SUB. */
6512 }
6514 {
6515 /* SUB(S). */
6517 }
6519 {
6520 /* FSUB. */
6522 }
6523 }
6525 }
6528 {
6529 rtx new_op0;
6534 cost_plus:
6537 {
6538 /* CSINC. */
6542 }
6547 {
6551 /* ADD (immediate). */
6554 }
6558 /* Look for ADD (extended register). */
6560 {
6568 }
6570 /* Strip any extend, leave shifts behind as we will
6571 cost them through mult_cost. */
6576 {
6578 speed);
6580 }
6585 {
6587 {
6588 /* Vector ADD. */
6590 }
6592 {
6593 /* ADD. */
6595 }
6597 {
6598 /* FADD. */
6600 }
6601 }
6603 }
6609 {
6612 else
6614 }
6619 {
6623 {
6626 else
6628 }
6630 }
6633 {
6640 }
6641 /* Fall through. */
6644 cost_logic:
6649 {
6653 }
6661 {
6662 /* This is a UBFM/SBFM. */
6667 }
6670 {
6672 {
6673 /* We have a mask + shift version of a UBFIZ
6674 i.e. the *andim_ashift<mode>_bfiz pattern. */
6678 {
6685 }
6687 {
6688 /* We possibly get the immediate for free, this is not
6689 modelled. */
6695 }
6696 }
6697 else
6698 {
6701 /* Handle ORN, EON, or BIC. */
6707 /* If we had a shift on op0 then this is a logical-shift-
6708 by-register/immediate operation. Otherwise, this is just
6709 a logical operation. */
6711 {
6713 {
6714 /* Shift by immediate. */
6717 else
6719 }
6720 else
6722 }
6724 /* In both cases we want to cost both operands. */
6729 }
6730 }
6738 {
6739 /* Vector NOT. */
6742 }
6744 /* MVN-shifted-reg. */
6746 {
6753 }
6754 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6755 Handle the second form here taking care that 'a' in the above can
6756 be a shift. */
6758 {
6767 {
6770 else
6772 }
6775 }
6776 /* MVN. */
6785 /* If a value is written in SI mode, then zero extended to DI
6786 mode, the operation will in general be free as a write to
6787 a 'w' register implicitly zeroes the upper bits of an 'x'
6788 register. However, if this is
6790 (set (reg) (zero_extend (reg)))
6792 we must cost the explicit register move. */
6796 {
6799 /* If OP_COST is non-zero, then the cost of the zero extend
6800 is effectively the cost of the inner operation. Otherwise
6801 we have a MOV instruction and we take the cost from the MOV
6802 itself. This is true independently of whether we are
6803 optimizing for space or time. */
6808 }
6810 {
6811 /* All loads can zero extend to any size for free. */
6814 }
6818 {
6823 }
6826 {
6828 {
6829 /* UMOV. */
6831 }
6832 else
6833 {
6834 /* We generate an AND instead of UXTB/UXTH. */
6836 }
6837 }
6842 {
6843 /* LDRSH. */
6845 {
6852 }
6854 }
6858 {
6863 }
6866 {
6869 else
6871 }
6879 {
6881 {
6883 {
6884 /* Vector shift (immediate). */
6886 }
6887 else
6888 {
6889 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6890 aliases. */
6892 }
6893 }
6895 /* We can incorporate zero/sign extend for free. */
6902 }
6903 else
6904 {
6906 {
6908 {
6909 /* Vector shift (register). */
6911 }
6912 else
6913 {
6914 /* LSLV. */
6916 }
6917 }
6919 }
6929 {
6930 /* ASR (immediate) and friends. */
6932 {
6935 else
6937 }
6941 }
6942 else
6943 {
6945 /* ASR (register) and friends. */
6947 {
6950 else
6952 }
6954 }
6960 {
6961 /* LDR. */
6964 }
6967 {
6968 /* ADRP, followed by ADD. */
6972 }
6975 {
6976 /* ADR. */
6979 }
6982 {
6983 /* One extra load instruction, after accessing the GOT. */
6987 }
6992 /* ADRP/ADD (immediate). */
6999 /* UBFX/SBFX. */
7001 {
7004 else
7006 }
7008 /* We can trust that the immediates used will be correct (there
7009 are no by-register forms), so we need only cost op0. */
7015 /* aarch64_rtx_mult_cost always handles recursion to its
7016 operands. */
7020 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7021 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7022 an unconditional negate. This case should only ever be reached through
7023 the set_smod_pow2_cheap check in expmed.c. */
7027 {
7028 /* We expand to 4 instructions. Reset the baseline. */
7036 }
7038 /* Fall-through. */
7041 {
7053 }
7060 {
7064 /* There is no integer SQRT, so only DIV and UDIV can get
7065 here. */
7067 else
7069 }
7095 {
7098 else
7100 }
7102 /* FMSUB, FNMADD, and FNMSUB are free. */
7109 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7110 and the by-element operand as operand 0. */
7114 /* Catch vector-by-element operations. The by-element operand can
7115 either be (vec_duplicate (vec_select (x))) or just
7116 (vec_select (x)), depending on whether we are multiplying by
7117 a vector or a scalar.
7119 Canonicalization is not very good in these cases, FMA4 will put the
7120 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7131 /* If the remaining parameters are not registers,
7132 get the cost to put them into registers. */
7146 {
7148 {
7149 /*Vector truncate. */
7151 }
7152 else
7154 }
7159 {
7161 {
7162 /*Vector conversion. */
7164 }
7165 else
7167 }
7173 /* Strip the rounding part. They will all be implemented
7174 by the fcvt* family of instructions anyway. */
7176 {
7185 }
7188 {
7191 else
7193 }
7195 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7196 fixed-point fcvt. */
7201 {
7205 }
7212 {
7213 /* ABS (vector). */
7216 }
7218 {
7221 /* FABD, which is analogous to FADD. */
7223 {
7230 }
7231 /* Simple FABS is analogous to FNEG. */
7234 }
7235 else
7236 {
7237 /* Integer ABS will either be split to
7238 two arithmetic instructions, or will be an ABS
7239 (scalar), which we don't model. */
7243 }
7249 {
7252 else
7253 {
7254 /* FMAXNM/FMINNM/FMAX/FMIN.
7255 TODO: This may not be accurate for all implementations, but
7256 we do not model this in the cost tables. */
7258 }
7259 }
7263 /* The floating point round to integer frint* instructions. */
7265 {
7270 }
7273 {
7278 }
7283 /* Decompose <su>muldi3_highpart. */
7285 mode == DImode
7286 /* (lshiftrt:TI */
7289 /* (mult:TI */
7291 /* (ANY_EXTEND:TI (reg:DI))
7292 (ANY_EXTEND:TI (reg:DI))) */
7299 /* (const_int 64) */
7302 {
7303 /* UMULH/SMULH. */
7311 }
7313 /* Fall through. */
7316 }
7323 }
7325 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7326 calculated for X. This cost is stored in *COST. Returns true
7327 if the total cost of X was calculated. */
7328 static bool
7331 {
7335 {
7340 }
7343 }
7345 static int
7348 {
7354 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7361 /* Moving between GPR and stack cost is the same as GP2GP. */
7366 /* To/From the stack register, we move via the gprs. */
7372 {
7373 /* 128-bit operations on general registers require 2 instructions. */
7381 /* When AdvSIMD instructions are disabled it is not possible to move
7382 a 128-bit value directly between Q registers. This is handled in
7383 secondary reload. A general register is used as a scratch to move
7384 the upper DI value and the lower DI value is moved directly,
7385 hence the cost is the sum of three moves. */
7390 }
7400 }
7402 static int
7404 reg_class_t rclass ATTRIBUTE_UNUSED,
7406 {
7408 }
7410 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7411 to optimize 1.0/sqrt. */
7413 static bool
7415 {
7417 && flag_unsafe_math_optimizations
7421 }
7423 /* Function to decide when to use the approximate reciprocal square root
7424 builtin. */
7426 static tree
7428 {
7434 }
7438 /* Select reciprocal square root initial estimate insn depending on machine
7439 mode. */
7441 static rsqrte_type
7443 {
7445 {
7452 }
7453 }
7457 /* Select reciprocal square root series step insn depending on machine mode. */
7459 static rsqrts_type
7461 {
7463 {
7470 }
7471 }
7473 /* Emit instruction sequence to compute either the approximate square root
7474 or its approximate reciprocal, depending on the flag RECP, and return
7475 whether the sequence was emitted or not. */
7477 bool
7479 {
7485 machine_mode mmsk = mode_for_vector
7489 && (flag_mlow_precision_sqrt
7493 && (flag_mrecip_low_precision_sqrt
7498 || flag_trapping_math
7499 || !flag_unsafe_math_optimizations
7506 /* When calculating the approximate square root, compare the argument with
7507 0.0 and create a mask. */
7511 /* Estimate the approximate reciprocal square root. */
7515 /* Iterate over the series twice for SF and thrice for DF. */
7518 /* Optionally iterate over the series once less for faster performance
7519 while sacrificing the accuracy. */
7522 iterations--;
7524 /* Iterate over the series to calculate the approximate reciprocal square
7525 root. */
7528 {
7536 }
7539 {
7540 /* Qualify the approximate reciprocal square root when the argument is
7541 0.0 by squashing the intermediary result to 0.0. */
7547 /* Calculate the approximate square root. */
7549 }
7551 /* Finalize the approximation. */
7555 }
7559 /* Select reciprocal initial estimate insn depending on machine mode. */
7561 static recpe_type
7563 {
7565 {
7572 }
7573 }
7577 /* Select reciprocal series step insn depending on machine mode. */
7579 static recps_type
7581 {
7583 {
7590 }
7591 }
7593 /* Emit the instruction sequence to compute the approximation for the division
7594 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
7596 bool
7598 {
7609 || flag_trapping_math
7610 || !flag_unsafe_math_optimizations
7615 /* Estimate the approximate reciprocal. */
7619 /* Iterate over the series twice for SF and thrice for DF. */
7622 /* Optionally iterate over the series once less for faster performance,
7623 while sacrificing the accuracy. */
7625 iterations--;
7627 /* Iterate over the series to calculate the approximate reciprocal. */
7630 {
7635 }
7638 {
7639 /* As the approximate reciprocal of DEN is already calculated, only
7640 calculate the approximate division when NUM is not 1.0. */
7643 }
7645 /* Finalize the approximation. */
7648 }
7650 /* Return the number of instructions that can be issued per cycle. */
7651 static int
7653 {
7655 }
7657 static int
7659 {
7663 }
7666 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
7667 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
7668 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
7670 static int
7673 {
7675 }
7678 /* Vectorizer cost model target hooks. */
7680 /* Implement targetm.vectorize.builtin_vectorization_cost. */
7681 static int
7683 tree vectype,
7685 {
7689 {
7738 }
7739 }
7741 /* Implement targetm.vectorize.add_stmt_cost. */
7742 static unsigned
7746 {
7751 {
7756 /* Statements in an inner loop relative to the loop being
7757 vectorized are weighted more heavily. The value here is
7758 arbitrary and could potentially be improved with analysis. */
7764 }
7767 }
7771 /* Parse the TO_PARSE string and put the architecture struct that it
7772 selects into RES and the architectural features into ISA_FLAGS.
7773 Return an aarch64_parse_opt_result describing the parse result.
7774 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
7776 static enum aarch64_parse_opt_result
7779 {
7791 else
7798 /* Loop through the list of supported ARCHes to find a match. */
7800 {
7802 {
7806 {
7807 /* TO_PARSE string contains at least one extension. */
7808 enum aarch64_parse_opt_result ext_res
7813 }
7814 /* Extension parsing was successful. Confirm the result
7815 arch and ISA flags. */
7819 }
7820 }
7822 /* ARCH name not found in list. */
7824 }
7826 /* Parse the TO_PARSE string and put the result tuning in RES and the
7827 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
7828 describing the parse result. If there is an error parsing, RES and
7829 ISA_FLAGS are left unchanged. */
7831 static enum aarch64_parse_opt_result
7834 {
7846 else
7853 /* Loop through the list of supported CPUs to find a match. */
7855 {
7857 {
7862 {
7863 /* TO_PARSE string contains at least one extension. */
7864 enum aarch64_parse_opt_result ext_res
7869 }
7870 /* Extension parsing was successfull. Confirm the result
7871 cpu and ISA flags. */
7875 }
7876 }
7878 /* CPU name not found in list. */
7880 }
7882 /* Parse the TO_PARSE string and put the cpu it selects into RES.
7883 Return an aarch64_parse_opt_result describing the parse result.
7884 If the parsing fails the RES does not change. */
7886 static enum aarch64_parse_opt_result
7888 {
7894 /* Loop through the list of supported CPUs to find a match. */
7896 {
7898 {
7901 }
7902 }
7904 /* CPU name not found in list. */
7906 }
7908 /* Parse TOKEN, which has length LENGTH to see if it is an option
7909 described in FLAG. If it is, return the index bit for that fusion type.
7910 If not, error (printing OPTION_NAME) and return zero. */
7912 static unsigned int
7917 {
7919 {
7923 }
7927 }
7929 /* Parse OPTION which is a comma-separated list of flags to enable.
7930 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7931 default state we inherit from the CPU tuning structures. OPTION_NAME
7932 gives the top-level option we are parsing in the -moverride string,
7933 for use in error messages. */
7935 static unsigned int
7940 {
7947 {
7950 token_length,
7951 flags,
7952 option_name);
7953 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7954 in the token stream, reset the supported operations. So:
7956 adrp+add.cmp+branch.none.adrp+add
7958 would have the result of turning on only adrp+add fusion. */
7964 }
7966 /* We ended with a comma, print something. */
7968 {
7971 }
7973 /* We still have one more token to parse. */
7976 token_length,
7977 flags,
7978 option_name);
7984 }
7986 /* Support for overriding instruction fusion. */
7988 static void
7991 {
7993 aarch64_fusible_pairs,
7996 }
7998 /* Support for overriding other tuning flags. */
8000 static void
8003 {
8004 tune->extra_tuning_flags
8006 aarch64_tuning_flags,
8009 }
8011 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8012 we understand. If it is, extract the option string and handoff to
8013 the appropriate function. */
8015 void
8019 {
8025 {
8028 }
8030 /* Get the length of the option name. */
8032 /* Skip the '=' to get to the option string. */
8033 option_part++;
8036 {
8038 {
8041 }
8042 }
8046 }
8048 /* A checking mechanism for the implementation of the tls size. */
8050 static void
8052 {
8057 {
8059 /* Both the default and maximum TLS size allowed under tiny is 1M which
8060 needs two instructions to address, so we clamp the size to 24. */
8065 /* The maximum TLS size allowed under small is 4G. */
8070 /* The maximum TLS size allowed under large is 16E.
8071 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8077 }
8080 }
8082 /* Parse STRING looking for options in the format:
8083 string :: option:string
8084 option :: name=substring
8085 name :: {a-z}
8086 substring :: defined by option. */
8088 static void
8091 {
8102 {
8104 /* Make this substring look like a string. */
8108 }
8110 /* One last option to parse. */
8113 }
8116 static void
8118 {
8119 /* The logic here is that if we are disabling all frame pointer generation
8120 then we do not need to disable leaf frame pointer generation as a
8121 separate operation. But if we are *only* disabling leaf frame pointer
8122 generation then we set flag_omit_frame_pointer to true, but in
8123 aarch64_frame_pointer_required we return false only for leaf functions.
8125 PR 70044: We have to be careful about being called multiple times for the
8126 same function. Once we have decided to set flag_omit_frame_pointer just
8127 so that we can omit leaf frame pointers, we must then not interpret a
8128 second call as meaning that all frame pointer generation should be
8129 omitted. We do this by setting flag_omit_frame_pointer to a special,
8130 non-zero value. */
8139 /* If not optimizing for size, set the default
8140 alignment to what the target wants. */
8142 {
8149 }
8151 /* We default to no pc-relative literal loads. */
8155 /* If -mpc-relative-literal-loads is set on the command line, this
8156 implies that the user asked for PC relative literal loads. */
8160 /* This is PR70113. When building the Linux kernel with
8161 CONFIG_ARM64_ERRATUM_843419, support for relocations
8162 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8163 removed from the kernel to avoid loading objects with possibly
8164 offending sequences. Without -mpc-relative-literal-loads we would
8165 generate such relocations, preventing the kernel build from
8166 succeeding. */
8171 /* In the tiny memory model it makes no sense to disallow PC relative
8172 literal pool loads. */
8177 /* When enabling the lower precision Newton series for the square root, also
8178 enable it for the reciprocal square root, since the latter is an
8179 intermediary step for the former. */
8182 }
8184 /* 'Unpack' up the internal tuning structs and update the options
8185 in OPTS. The caller must have set up selected_tune and selected_arch
8186 as all the other target-specific codegen decisions are
8187 derived from them. */
8189 void
8191 {
8194 /* Make a copy of the tuning parameters attached to the core, which
8195 we may later overwrite. */
8203 /* This target defaults to strict volatile bitfields. */
8212 {
8224 }
8226 /* We don't mind passing in global_options_set here as we don't use
8227 the *options_set structs anyway. */
8229 queue_depth,
8233 /* Set the L1 cache line size. */
8241 }
8243 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8244 specified in STR and throw errors if appropriate. Put the results if
8245 they are valid in RES and ISA_FLAGS. Return whether the option is
8246 valid. */
8248 static bool
8251 {
8252 enum aarch64_parse_opt_result parse_res
8259 {
8271 }
8274 }
8276 /* Validate a command-line -march option. Parse the arch and extensions
8277 (if any) specified in STR and throw errors if appropriate. Put the
8278 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8279 option is valid. */
8281 static bool
8284 {
8285 enum aarch64_parse_opt_result parse_res
8292 {
8304 }
8307 }
8309 /* Validate a command-line -mtune option. Parse the cpu
8310 specified in STR and throw errors if appropriate. Put the
8311 result, if it is valid, in RES. Return whether the option is
8312 valid. */
8314 static bool
8316 {
8317 enum aarch64_parse_opt_result parse_res
8324 {
8333 }
8335 }
8337 /* Return the CPU corresponding to the enum CPU.
8338 If it doesn't specify a cpu, return the default. */
8342 {
8346 /* The & 0x3f is to extract the bottom 6 bits that encode the
8347 default cpu as selected by the --with-cpu GCC configure option
8348 in config.gcc.
8349 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8350 flags mechanism should be reworked to make it more sane. */
8352 }
8354 /* Return the architecture corresponding to the enum ARCH.
8355 If it doesn't specify a valid architecture, return the default. */
8359 {
8366 }
8368 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8369 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8370 tuning structs. In particular it must set selected_tune and
8371 aarch64_isa_flags that define the available ISA features and tuning
8372 decisions. It must also set selected_arch as this will be used to
8373 output the .arch asm tags for each function. */
8375 static void
8377 {
8390 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8391 If either of -march or -mtune is given, they override their
8392 respective component of -mcpu. */
8404 /* If the user did not specify a processor, choose the default
8405 one for them. This will be the CPU set during configuration using
8406 --with-cpu, otherwise it is "generic". */
8408 {
8410 {
8414 }
8415 else
8416 {
8417 /* Get default configure-time CPU. */
8420 }
8424 }
8425 /* If both -mcpu and -march are specified check that they are architecturally
8426 compatible, warn if they're not and prefer the -march ISA flags. */
8428 {
8430 {
8434 }
8439 }
8440 else
8441 {
8442 /* -mcpu but no -march. */
8449 }
8451 /* Set the arch as well as we will need it when outputing
8452 the .arch directive in assembly. */
8454 {
8457 }
8462 #ifndef HAVE_AS_MABI_OPTION
8463 /* The compiler may have been configured with 2.23.* binutils, which does
8464 not have support for ILP32. */
8467 #endif
8469 /* Make sure we properly set up the explicit options. */
8480 /* Save these options as the default ones in case we push and pop them later
8481 while processing functions with potential target attributes. */
8482 target_option_default_node = target_option_current_node
8487 }
8489 /* Implement targetm.override_options_after_change. */
8491 static void
8493 {
8495 }
8499 {
8503 }
8505 void
8507 {
8509 }
8511 /* A checking mechanism for the implementation of the various code models. */
8512 static void
8514 {
8516 {
8518 {
8523 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8525 ? AARCH64_CMODEL_SMALL_PIC
8527 #else
8529 #endif
8537 }
8538 }
8539 else
8541 }
8543 /* Implement TARGET_OPTION_SAVE. */
8545 static void
8547 {
8549 }
8551 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8552 using the information saved in PTR. */
8554 static void
8556 {
8564 }
8566 /* Implement TARGET_OPTION_PRINT. */
8568 static void
8570 {
8581 }
8585 void
8587 {
8589 }
8591 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
8592 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
8593 make sure optab availability predicates are recomputed when necessary. */
8595 void
8597 {
8602 else
8604 }
8606 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
8607 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
8608 of the function, if such exists. This function may be called multiple
8609 times on a single function so use aarch64_previous_fndecl to avoid
8610 setting up identical state. */
8612 static void
8614 {
8618 tree old_tree = (aarch64_previous_fndecl
8624 /* If current function has no attributes but the previous one did,
8625 use the default node. */
8629 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
8630 the default have been handled by aarch64_save_restore_target_globals from
8631 aarch64_pragma_target_parse. */
8637 /* First set the target options. */
8641 }
8643 /* Enum describing the various ways we can handle attributes.
8644 In many cases we can reuse the generic option handling machinery. */
8646 enum aarch64_attr_opt_type
8647 {
8651 aarch64_attr_custom /* Attribute requires a custom handling function. */
8652 };
8654 /* All the information needed to handle a target attribute.
8655 NAME is the name of the attribute.
8656 ATTR_TYPE specifies the type of behavior of the attribute as described
8657 in the definition of enum aarch64_attr_opt_type.
8658 ALLOW_NEG is true if the attribute supports a "no-" form.
8659 HANDLER is the function that takes the attribute string and whether
8660 it is a pragma or attribute and handles the option. It is needed only
8661 when the ATTR_TYPE is aarch64_attr_custom.
8662 OPT_NUM is the enum specifying the option that the attribute modifies.
8663 This is needed for attributes that mirror the behavior of a command-line
8664 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
8665 aarch64_attr_enum. */
8667 struct aarch64_attribute_info
8668 {
8674 };
8676 /* Handle the ARCH_STR argument to the arch= target attribute.
8677 PRAGMA_OR_ATTR is used in potential error messages. */
8679 static bool
8681 {
8683 enum aarch64_parse_opt_result parse_res
8687 {
8692 }
8695 {
8708 }
8711 }
8713 /* Handle the argument CPU_STR to the cpu= target attribute.
8714 PRAGMA_OR_ATTR is used in potential error messages. */
8716 static bool
8718 {
8720 enum aarch64_parse_opt_result parse_res
8724 {
8732 }
8735 {
8748 }
8751 }
8753 /* Handle the argument STR to the tune= target attribute.
8754 PRAGMA_OR_ATTR is used in potential error messages. */
8756 static bool
8758 {
8760 enum aarch64_parse_opt_result parse_res
8764 {
8769 }
8772 {
8778 }
8781 }
8783 /* Parse an architecture extensions target attribute string specified in STR.
8784 For example "+fp+nosimd". Show any errors if needed. Return TRUE
8785 if successful. Update aarch64_isa_flags to reflect the ISA features
8786 modified.
8787 PRAGMA_OR_ATTR is used in potential error messages. */
8789 static bool
8791 {
8795 /* We allow "+nothing" in the beginning to clear out all architectural
8796 features if the user wants to handpick specific features. */
8798 {
8801 }
8806 {
8809 }
8812 {
8825 }
8828 }
8830 /* The target attributes that we support. On top of these we also support just
8831 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
8832 handled explicitly in aarch64_process_one_target_attr. */
8835 {
8837 OPT_mgeneral_regs_only },
8839 OPT_mfix_cortex_a53_835769 },
8841 OPT_mfix_cortex_a53_843419 },
8845 OPT_momit_leaf_frame_pointer },
8848 OPT_march_ },
8851 OPT_mtune_ },
8853 };
8855 /* Parse ARG_STR which contains the definition of one target attribute.
8856 Show appropriate errors if any or return true if the attribute is valid.
8857 PRAGMA_OR_ATTR holds the string to use in error messages about whether
8858 we're processing a target attribute or pragma. */
8860 static bool
8862 {
8868 {
8871 }
8876 /* Skip leading whitespace. */
8878 str_to_check++;
8880 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
8881 It is easier to detect and handle it explicitly here rather than going
8882 through the machinery for the rest of the target attributes in this
8883 function. */
8888 {
8891 }
8894 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
8895 and point ARG to "foo". */
8897 {
8899 arg++;
8900 }
8904 {
8905 /* If the names don't match up, or the user has given an argument
8906 to an attribute that doesn't accept one, or didn't give an argument
8907 to an attribute that expects one, fail to match. */
8916 {
8920 }
8922 /* If the name matches but the attribute does not allow "no-" versions
8923 then we can't match. */
8925 {
8929 }
8932 {
8933 /* Has a custom handler registered.
8934 For example, cpu=, arch=, tune=. */
8941 /* Either set or unset a boolean option. */
8943 {
8951 }
8952 /* Set or unset a bit in the target_flags. aarch64_handle_option
8953 should know what mask to apply given the option number. */
8955 {
8957 /* We only need to specify the option number.
8958 aarch64_handle_option will know which mask to apply. */
8964 }
8965 /* Use the option setting machinery to set an option to an enum. */
8967 {
8974 {
8977 global_dc);
8978 }
8979 else
8980 {
8983 }
8985 }
8988 }
8989 }
8991 /* If we reached here we either have found an attribute and validated
8992 it or didn't match any. If we matched an attribute but its arguments
8993 were malformed we will have returned false already. */
8995 }
8997 /* Count how many times the character C appears in
8998 NULL-terminated string STR. */
9000 static unsigned int
9002 {
9005 {
9007 res++;
9009 str++;
9010 }
9013 }
9015 /* Parse the tree in ARGS that contains the target attribute information
9016 and update the global target options space. PRAGMA_OR_ATTR is a string
9017 to be used in error messages, specifying whether this is processing
9018 a target attribute or a target pragma. */
9020 bool
9022 {
9024 {
9025 do
9026 {
9029 {
9032 }
9037 }
9038 /* We expect to find a string to parse. */
9046 {
9049 }
9051 /* Used to catch empty spaces between commas i.e.
9052 attribute ((target ("attr1,,attr2"))). */
9055 /* Handle multiple target attributes separated by ','. */
9060 {
9061 num_attrs++;
9063 {
9066 }
9069 }
9072 {
9076 }
9079 }
9081 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9082 process attribute ((target ("..."))). */
9084 static bool
9086 {
9089 tree old_optimize;
9093 /* If what we're processing is the current pragma string then the
9094 target option node is already stored in target_option_current_node
9095 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9096 having to re-parse the string. This is especially useful to keep
9097 arm_neon.h compile times down since that header contains a lot
9098 of intrinsics enclosed in pragmas. */
9100 {
9103 }
9109 /* If the function changed the optimization levels as well as setting
9110 target options, start with the optimizations specified. */
9115 /* Save the current target options to restore at the end. */
9118 /* If fndecl already has some target attributes applied to it, unpack
9119 them so that we add this attribute on top of them, rather than
9120 overwriting them. */
9122 {
9128 }
9129 else
9136 /* Set up any additional state. */
9138 {
9140 /* Initialize SIMD builtins if we haven't already.
9141 Set current_target_pragma to NULL for the duration so that
9142 the builtin initialization code doesn't try to tag the functions
9143 being built with the attributes specified by any current pragma, thus
9144 going into an infinite recursion. */
9146 {
9151 }
9153 }
9154 else
9160 {
9165 }
9173 }
9175 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9176 tri-bool options (yes, no, don't care) and the default value is
9177 DEF, determine whether to reject inlining. */
9179 static bool
9182 {
9183 /* If the callee doesn't care, always allow inlining. */
9187 /* If the caller doesn't care, always allow inlining. */
9191 /* Otherwise, allow inlining if either the callee and caller values
9192 agree, or if the callee is using the default value. */
9194 }
9196 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9197 to inline CALLEE into CALLER based on target-specific info.
9198 Make sure that the caller and callee have compatible architectural
9199 features. Then go through the other possible target attributes
9200 and see if they can block inlining. Try not to reject always_inline
9201 callees unless they are incompatible architecturally. */
9203 static bool
9205 {
9209 /* If callee has no option attributes, then it is ok to inline. */
9220 /* Callee's ISA flags should be a subset of the caller's. */
9225 /* Allow non-strict aligned functions inlining into strict
9226 aligned ones. */
9236 /* If the architectural features match up and the callee is always_inline
9237 then the other attributes don't matter. */
9249 /* Honour explicit requests to workaround errata. */
9262 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9263 caller and calle and they don't match up, reject inlining. */
9270 /* If the callee has specific tuning overrides, respect them. */
9275 /* If the user specified tuning override strings for the
9276 caller and callee and they don't match up, reject inlining.
9277 We just do a string compare here, we don't analyze the meaning
9278 of the string, as it would be too costly for little gain. */
9286 }
9288 /* Return true if SYMBOL_REF X binds locally. */
9290 static bool
9292 {
9296 }
9298 /* Return true if SYMBOL_REF X is thread local */
9299 static bool
9301 {
9309 }
9311 /* Classify a TLS symbol into one of the TLS kinds. */
9312 enum aarch64_symbol_type
9314 {
9318 {
9325 {
9331 }
9342 else
9351 }
9352 }
9354 /* Return the method that should be used to access SYMBOL_REF or
9355 LABEL_REF X. */
9357 enum aarch64_symbol_type
9359 {
9361 {
9363 {
9378 }
9379 }
9382 {
9387 {
9389 /* When we retrieve symbol + offset address, we have to make sure
9390 the offset does not cause overflow of the final address. But
9391 we have no way of knowing the address of symbol at compile time
9392 so we can't accurately say if the distance between the PC and
9393 symbol + offset is outside the addressible range of +/-1M in the
9394 TINY code model. So we rely on images not being greater than
9395 1M and cap the offset at 1M and anything beyond 1M will have to
9396 be loaded using an alternative mechanism. Furthermore if the
9397 symbol is a weak reference to something that isn't known to
9398 resolve to a symbol in this module, then force to memory. */
9406 /* Same reasoning as the tiny code model, but the offset cap here is
9407 4G. */
9428 /* This is alright even in PIC code as the constant
9429 pool reference is always PC relative and within
9430 the same translation unit. */
9433 else
9438 }
9439 }
9441 /* By default push everything into the constant pool. */
9443 }
9445 bool
9447 {
9449 }
9451 bool
9453 {
9461 }
9463 /* Return true if X holds either a quarter-precision or
9464 floating-point +0.0 constant. */
9465 static bool
9467 {
9474 /* We only handle moving 0.0 to a TFmode register. */
9479 }
9481 static bool
9483 {
9484 /* Do not allow vector struct mode constants. We could support
9485 0 and -1 easily, but they need support in aarch64-simd.md. */
9489 /* This could probably go away because
9490 we now decompose CONST_INTs according to expand_mov_immediate. */
9501 }
9503 rtx
9505 {
9511 /* Can return in any reg. */
9514 }
9516 /* On AAPCS systems, this is the "struct __va_list". */
9519 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9520 Return the type to use as __builtin_va_list.
9522 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9524 struct __va_list
9525 {
9526 void *__stack;
9527 void *__gr_top;
9528 void *__vr_top;
9529 int __gr_offs;
9530 int __vr_offs;
9531 }; */
9533 static tree
9535 {
9536 tree va_list_name;
9539 /* Create the type. */
9541 /* Give it the required name. */
9543 TYPE_DECL,
9545 va_list_type);
9550 /* Create the fields. */
9553 ptr_type_node);
9556 ptr_type_node);
9559 ptr_type_node);
9562 integer_type_node);
9565 integer_type_node);
9567 /* Tell tree-stdarg pass about our internal offset fields.
9568 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
9569 purpose to identify whether the code is updating va_list internal
9570 offset fields through irregular way. */
9592 /* Compute its layout. */
9596 }
9598 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
9599 static void
9601 {
9605 tree t;
9619 {
9622 }
9631 NULL_TREE);
9633 NULL_TREE);
9635 NULL_TREE);
9637 NULL_TREE);
9639 NULL_TREE);
9641 /* Emit code to initialize STACK, which points to the next varargs stack
9642 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
9643 by named arguments. STACK is 8-byte aligned. */
9650 /* Emit code to initialize GRTOP, the top of the GR save area.
9651 virtual_incoming_args_rtx should have been 16 byte aligned. */
9656 /* Emit code to initialize VRTOP, the top of the VR save area.
9657 This address is gr_save_area_bytes below GRTOP, rounded
9658 down to the next 16-byte boundary. */
9668 /* Emit code to initialize GROFF, the offset from GRTOP of the
9669 next GPR argument. */
9674 /* Likewise emit code to initialize VROFF, the offset from FTOP
9675 of the next VR argument. */
9679 }
9681 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
9683 static tree
9686 {
9687 tree addr;
9693 machine_mode mode;
9720 type,
9724 {
9725 /* TYPE passed in fp/simd registers. */
9737 {
9740 }
9743 {
9745 }
9746 }
9747 else
9748 {
9749 /* TYPE passed in general registers. */
9762 {
9764 }
9765 }
9767 /* Get a local temporary for the field value. */
9770 /* Emit code to branch if off >= 0. */
9776 {
9777 /* Emit: offs = (offs + 15) & -16. */
9783 }
9784 else
9787 /* Update ap.__[g|v]r_offs */
9792 /* String up. */
9796 /* [cond2] if (ap.__[g|v]r_offs > 0) */
9801 /* String up: make sure the assignment happens before the use. */
9805 /* Prepare the trees handling the argument that is passed on the stack;
9806 the top level node will store in ON_STACK. */
9809 {
9810 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
9818 }
9819 else
9821 /* Advance ap.__stack */
9829 /* String up roundup and advance. */
9832 /* String up with arg */
9834 /* Big-endianness related address adjustment. */
9837 {
9841 }
9846 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
9856 {
9857 /* type ha; // treat as "struct {ftype field[n];}"
9858 ... [computing offs]
9859 for (i = 0; i <nregs; ++i, offs += 16)
9860 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
9861 return ha; */
9865 /* Declare a local variable. */
9869 /* Establish the base type. */
9871 {
9884 /* The half precision and quad precision are not fully supported yet. Enable
9885 the following code after the support is complete. Need to find the correct
9886 type node for __fp16 *. */
9887 #if 0
9892 #endif
9895 {
9899 }
9903 }
9905 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
9913 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
9915 {
9925 }
9929 }
9939 }
9941 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
9943 static void
9947 {
9949 CUMULATIVE_ARGS local_cum;
9953 /* The caller has advanced CUM up to, but not beyond, the last named
9954 argument. Advance a local copy of CUM past the last "real" named
9955 argument, to find out how many registers are left over. */
9959 /* Found out how many registers we need to save.
9960 Honor tree-stdvar analysis results. */
9969 {
9972 }
9975 {
9977 {
9980 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
9988 }
9990 {
9991 /* We can't use move_block_from_reg, because it will use
9992 the wrong mode, storing D regs only. */
9996 /* Set OFF to the offset from virtual_incoming_args_rtx of
9997 the first vector register. The VR save area lies below
9998 the GR one, and is aligned to 16 bytes. */
10005 {
10013 }
10014 }
10015 }
10017 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10018 any complication of having crtl->args.pretend_args_size changed. */
10023 }
10025 static void
10027 {
10030 {
10032 {
10035 }
10036 }
10037 }
10039 /* Walk down the type tree of TYPE counting consecutive base elements.
10040 If *MODEP is VOIDmode, then set it to the first valid floating point
10041 type. If a non-floating point type is found, or if a floating point
10042 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10043 otherwise return the count in the sub-tree. */
10044 static int
10046 {
10047 machine_mode mode;
10048 HOST_WIDE_INT size;
10051 {
10079 /* Use V2SImode and V4SImode as representatives of all 64-bit
10080 and 128-bit vector types. */
10083 {
10092 }
10097 /* Vector modes are considered to be opaque: two vectors are
10098 equivalent for the purposes of being homogeneous aggregates
10099 if they are the same size. */
10106 {
10110 /* Can't handle incomplete types nor sizes that are not
10111 fixed. */
10118 || !index
10129 /* There must be no padding. */
10134 }
10137 {
10140 tree field;
10142 /* Can't handle incomplete types nor sizes that are not
10143 fixed. */
10149 {
10157 }
10159 /* There must be no padding. */
10164 }
10168 {
10169 /* These aren't very interesting except in a degenerate case. */
10172 tree field;
10174 /* Can't handle incomplete types nor sizes that are not
10175 fixed. */
10181 {
10189 }
10191 /* There must be no padding. */
10196 }
10200 }
10203 }
10205 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10206 type as described in AAPCS64 \S 4.1.2.
10208 See the comment above aarch64_composite_type_p for the notes on MODE. */
10210 static bool
10212 machine_mode mode)
10213 {
10223 }
10225 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10226 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10227 array types. The C99 floating-point complex types are also considered
10228 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10229 types, which are GCC extensions and out of the scope of AAPCS64, are
10230 treated as composite types here as well.
10232 Note that MODE itself is not sufficient in determining whether a type
10233 is such a composite type or not. This is because
10234 stor-layout.c:compute_record_mode may have already changed the MODE
10235 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10236 structure with only one field may have its MODE set to the mode of the
10237 field. Also an integer mode whose size matches the size of the
10238 RECORD_TYPE type may be used to substitute the original mode
10239 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10240 solely relied on. */
10242 static bool
10244 machine_mode mode)
10245 {
10258 }
10260 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10261 shall be passed or returned in simd/fp register(s) (providing these
10262 parameter passing registers are available).
10264 Upon successful return, *COUNT returns the number of needed registers,
10265 *BASE_MODE returns the mode of the individual register and when IS_HAF
10266 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10267 floating-point aggregate or a homogeneous short-vector aggregate. */
10269 static bool
10271 const_tree type,
10275 {
10283 {
10286 }
10288 {
10292 }
10294 {
10298 {
10301 }
10302 else
10304 }
10305 else
10310 }
10312 /* Implement TARGET_STRUCT_VALUE_RTX. */
10314 static rtx
10317 {
10319 }
10321 /* Implements target hook vector_mode_supported_p. */
10322 static bool
10324 {
10336 }
10338 /* Return appropriate SIMD container
10339 for MODE within a vector of WIDTH bits. */
10340 static machine_mode
10342 {
10345 {
10348 {
10363 }
10364 else
10366 {
10377 }
10378 }
10380 }
10382 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10383 static machine_mode
10385 {
10387 }
10389 /* Return the bitmask of possible vector sizes for the vectorizer
10390 to iterate over. */
10391 static unsigned int
10393 {
10395 }
10397 /* Implement TARGET_MANGLE_TYPE. */
10401 {
10402 /* The AArch64 ABI documents say that "__va_list" has to be
10403 managled as if it is in the "std" namespace. */
10407 /* Half-precision float. */
10411 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10412 builtin types. */
10416 /* Use the default mangling. */
10418 }
10421 /* Return true if the rtx_insn contains a MEM RTX somewhere
10422 in it. */
10424 static bool
10426 {
10433 }
10435 /* Find the first rtx_insn before insn that will generate an assembly
10436 instruction. */
10440 {
10444 do
10445 {
10447 }
10451 }
10453 static bool
10455 {
10457 /* A number of these may be AArch32 only. */
10462 };
10465 {
10468 }
10471 }
10473 /* Check if there is a register dependency between a load and the insn
10474 for which we hold recog_data. */
10476 static bool
10478 {
10479 rtx load_reg;
10489 {
10495 }
10497 }
10500 /* When working around the Cortex-A53 erratum 835769,
10501 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10502 instruction and has a preceding memory instruction such that a NOP
10503 should be inserted between them. */
10505 bool
10507 {
10510 rtx body;
10523 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10524 Restore recog state to INSN to avoid state corruption. */
10532 /* If the previous insn is a memory op and there is no dependency between
10533 it and the DImode madd, emit a NOP between them. If body is NULL then we
10534 have a complex memory operation, probably a load/store pair.
10535 Be conservative for now and emit a NOP. */
10542 }
10545 /* Implement FINAL_PRESCAN_INSN. */
10547 void
10549 {
10552 }
10555 /* Return the equivalent letter for size. */
10556 static char
10558 {
10560 {
10566 }
10567 }
10569 /* Return true iff x is a uniform vector of floating-point
10570 constants, and the constant can be represented in
10571 quarter-precision form. Note, as aarch64_float_const_representable
10572 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10573 static bool
10575 {
10576 rtx elt;
10580 }
10582 /* Return true for valid and false for invalid. */
10583 bool
10586 {
10587 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
10588 matches = 1; \
10589 for (i = 0; i < idx; i += (STRIDE)) \
10590 if (!(TEST)) \
10591 matches = 0; \
10592 if (matches) \
10593 { \
10594 immtype = (CLASS); \
10595 elsize = (ELSIZE); \
10596 eshift = (SHIFT); \
10597 emvn = (NEG); \
10598 break; \
10599 }
10609 {
10615 {
10620 }
10623 }
10625 /* Splat vector constant out into a byte vector. */
10627 {
10628 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
10629 it must be laid out in the vector register in reverse order. */
10637 {
10640 }
10642 }
10644 /* Sanity check. */
10647 do
10648 {
10697 }
10704 {
10714 /* Un-invert bytes of recognized vector, if necessary. */
10720 {
10721 /* FIXME: Broken on 32-bit H_W_I hosts. */
10730 }
10731 else
10732 {
10736 /* Construct 'abcdefgh' because the assembler cannot handle
10737 generic constants. */
10742 }
10743 }
10746 #undef CHECK
10747 }
10749 /* Check of immediate shift constants are within range. */
10750 bool
10752 {
10756 else
10758 }
10760 /* Return true if X is a uniform vector where all elements
10761 are either the floating-point constant 0.0 or the
10762 integer constant 0. */
10763 bool
10765 {
10767 }
10770 /* Return the bitmask CONST_INT to select the bits required by a zero extract
10771 operation of width WIDTH at bit position POS. */
10773 rtx
10775 {
10779 unsigned HOST_WIDE_INT mask
10782 }
10784 bool
10786 {
10791 {
10796 }
10799 }
10801 bool
10803 {
10816 }
10818 /* Return a const_int vector of VAL. */
10819 rtx
10821 {
10830 }
10832 /* Check OP is a legal scalar immediate for the MOVI instruction. */
10834 bool
10836 {
10837 machine_mode vmode;
10843 }
10845 /* Construct and return a PARALLEL RTX vector with elements numbering the
10846 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
10847 the vector - from the perspective of the architecture. This does not
10848 line up with GCC's perspective on lane numbers, so we end up with
10849 different masks depending on our target endian-ness. The diagram
10850 below may help. We must draw the distinction when building masks
10851 which select one half of the vector. An instruction selecting
10852 architectural low-lanes for a big-endian target, must be described using
10853 a mask selecting GCC high-lanes.
10855 Big-Endian Little-Endian
10857 GCC 0 1 2 3 3 2 1 0
10858 | x | x | x | x | | x | x | x | x |
10859 Architecture 3 2 1 0 3 2 1 0
10861 Low Mask: { 2, 3 } { 0, 1 }
10862 High Mask: { 0, 1 } { 2, 3 }
10863 */
10865 rtx
10867 {
10873 rtx t1;
10878 else
10886 }
10888 /* Check OP for validity as a PARALLEL RTX vector with elements
10889 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
10890 from the perspective of the architecture. See the diagram above
10891 aarch64_simd_vect_par_cnst_half for more details. */
10893 bool
10896 {
10909 {
10916 }
10918 }
10920 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
10921 HIGH (exclusive). */
10922 void
10924 const_tree exp)
10925 {
10926 HOST_WIDE_INT lane;
10931 {
10934 else
10936 }
10937 }
10939 /* Return TRUE if OP is a valid vector addressing mode. */
10940 bool
10942 {
10945 }
10947 /* Emit a register copy from operand to operand, taking care not to
10948 early-clobber source registers in the process.
10950 COUNT is the number of components into which the copy needs to be
10951 decomposed. */
10952 void
10955 {
10965 else
10969 }
10971 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
10972 one of VSTRUCT modes: OI, CI, or XI. */
10973 int
10975 {
10977 }
10979 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
10980 alignment of a vector to 128 bits. */
10981 static HOST_WIDE_INT
10983 {
10986 }
10988 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
10989 static bool
10991 {
10995 /* We guarantee alignment for vectors up to 128-bits. */
11000 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11002 }
11004 /* If VALS is a vector constant that can be loaded into a register
11005 using DUP, generate instructions to do so and return an RTX to
11006 assign to the register. Otherwise return NULL_RTX. */
11007 static rtx
11009 {
11012 rtx x;
11017 /* We can load this constant by using DUP and a constant in a
11018 single ARM register. This will be cheaper than a vector
11019 load. */
11022 }
11025 /* Generate code to load VALS, which is a PARALLEL containing only
11026 constants (for vec_init) or CONST_VECTOR, efficiently into a
11027 register. Returns an RTX to copy into the register, or NULL_RTX
11028 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11029 static rtx
11031 {
11033 rtx const_dup;
11042 {
11043 /* A CONST_VECTOR must contain only CONST_INTs and
11044 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11045 Only store valid constants in a CONST_VECTOR. */
11047 {
11050 n_const++;
11051 }
11054 }
11055 else
11060 /* Load using MOVI/MVNI. */
11063 /* Loaded using DUP. */
11066 /* Load from constant pool. We can not take advantage of single-cycle
11067 LD1 because we need a PC-relative addressing mode. */
11069 else
11070 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11071 We can not construct an initializer. */
11073 }
11075 /* Expand a vector initialisation sequence, such that TARGET is
11076 initialised to contain VALS. */
11078 void
11080 {
11083 /* The number of vector elements. */
11085 /* The number of vector elements which are not constant. */
11088 /* The first element of vals. */
11092 /* Count the number of variable elements to initialise. */
11094 {
11098 else
11102 }
11104 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11105 how best to handle this. */
11107 {
11110 {
11113 }
11114 }
11116 /* Splat a single non-constant element if we can. */
11118 {
11122 }
11124 /* Initialise a vector which is part-variable. We want to first try
11125 to build those lanes which are constant in the most efficient way we
11126 can. */
11128 {
11131 /* Load constant part of vector. We really don't care what goes into the
11132 parts we will overwrite, but we're more likely to be able to load the
11133 constant efficiently if it has fewer, larger, repeating parts
11134 (see aarch64_simd_valid_immediate). */
11136 {
11142 {
11143 /* Look in the copied vector, as more elements are const. */
11146 {
11149 }
11150 }
11152 }
11154 }
11156 /* Insert the variable lanes directly. */
11162 {
11168 }
11169 }
11171 static unsigned HOST_WIDE_INT
11173 {
11174 return
11175 (!SHIFT_COUNT_TRUNCATED
11178 }
11180 /* Select a format to encode pointers in exception handling data. */
11181 int
11183 {
11186 {
11192 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11193 for everything. */
11197 /* No assumptions here. 8-byte relocs required. */
11200 }
11202 }
11204 /* The last .arch and .tune assembly strings that we printed. */
11208 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11209 by the function fndecl. */
11211 void
11213 tree fndecl)
11214 {
11220 else
11231 /* Only update the assembler .arch string if it is distinct from the last
11232 such string we printed. */
11235 {
11238 }
11240 /* Print the cpu name we're tuning for in the comments, might be
11241 useful to readers of the generated asm. Do it only when it changes
11242 from function to function and verbose assembly is requested. */
11247 {
11251 }
11253 /* Don't forget the type directive for ELF. */
11256 }
11258 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11260 static void
11262 {
11279 }
11281 /* Emit load exclusive. */
11283 static void
11286 {
11290 {
11297 }
11300 }
11302 /* Emit store exclusive. */
11304 static void
11307 {
11311 {
11318 }
11321 }
11323 /* Mark the previous jump instruction as unlikely. */
11325 static void
11327 {
11332 }
11334 /* Expand a compare and swap pattern. */
11336 void
11338 {
11343 gen_cas_fn gen;
11345 {
11346 gen_aarch64_compare_and_swapqi,
11347 gen_aarch64_compare_and_swaphi,
11348 gen_aarch64_compare_and_swapsi,
11349 gen_aarch64_compare_and_swapdi
11350 };
11352 {
11353 gen_aarch64_compare_and_swapqi_lse,
11354 gen_aarch64_compare_and_swaphi_lse,
11355 gen_aarch64_compare_and_swapsi_lse,
11356 gen_aarch64_compare_and_swapdi_lse
11357 };
11370 /* Normally the succ memory model must be stronger than fail, but in the
11371 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11372 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11379 {
11382 /* For short modes, we're going to perform the comparison in SImode,
11383 so do the zero-extension now. */
11387 /* Fall through. */
11391 /* Force the value into a register if needed. */
11398 }
11401 {
11408 }
11411 else
11422 }
11424 /* Test whether the target supports using a atomic load-operate instruction.
11425 CODE is the operation and AFTER is TRUE if the data in memory after the
11426 operation should be returned and FALSE if the data before the operation
11427 should be returned. Returns FALSE if the operation isn't supported by the
11428 architecture. */
11430 bool
11432 {
11437 {
11447 }
11448 }
11450 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11451 sequence implementing an atomic operation. */
11453 static void
11455 {
11462 {
11464 }
11465 }
11467 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11468 for the data in memory. EXPECTED is the value expected to be in memory.
11469 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11470 is the memory ordering to use. */
11472 void
11475 rtx model)
11476 {
11478 machine_mode mode;
11483 {
11490 }
11492 /* Move the expected value into the CAS destination register. */
11495 /* Emit the CAS. */
11498 /* Compare the expected value with the value loaded by the CAS, to establish
11499 whether the swap was made. */
11501 }
11503 /* Split a compare and swap pattern. */
11505 void
11507 {
11509 machine_mode mode;
11514 rtx model_rtx;
11528 {
11531 }
11534 /* The initial load can be relaxed for a __sync operation since a final
11535 barrier will be emitted to stop code hoisting. */
11539 else
11551 {
11556 }
11557 else
11558 {
11562 }
11566 /* Emit any final barrier needed for a __sync operation. */
11569 }
11571 /* Emit a BIC instruction. */
11573 static void
11575 {
11580 {
11585 }
11588 }
11590 /* Emit an atomic swap. */
11592 static void
11595 {
11599 {
11606 }
11609 }
11611 /* Operations supported by aarch64_emit_atomic_load_op. */
11613 enum aarch64_atomic_load_op_code
11614 {
11618 AARCH64_LDOP_BIC /* A & ~B */
11619 };
11621 /* Emit an atomic load-operate. */
11623 static void
11627 {
11630 {
11631 gen_aarch64_atomic_loadaddqi,
11632 gen_aarch64_atomic_loadaddhi,
11633 gen_aarch64_atomic_loadaddsi,
11634 gen_aarch64_atomic_loadadddi
11635 };
11637 {
11638 gen_aarch64_atomic_loadeorqi,
11639 gen_aarch64_atomic_loadeorhi,
11640 gen_aarch64_atomic_loadeorsi,
11641 gen_aarch64_atomic_loadeordi
11642 };
11644 {
11645 gen_aarch64_atomic_loadsetqi,
11646 gen_aarch64_atomic_loadsethi,
11647 gen_aarch64_atomic_loadsetsi,
11648 gen_aarch64_atomic_loadsetdi
11649 };
11651 {
11652 gen_aarch64_atomic_loadclrqi,
11653 gen_aarch64_atomic_loadclrhi,
11654 gen_aarch64_atomic_loadclrsi,
11655 gen_aarch64_atomic_loadclrdi
11656 };
11657 aarch64_atomic_load_op_fn gen;
11661 {
11668 }
11671 {
11678 }
11681 }
11683 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
11684 location to store the data read from memory. OUT_RESULT is the location to
11685 store the result of the operation. MEM is the memory location to read and
11686 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
11687 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
11688 be NULL. */
11690 void
11693 {
11697 aarch64_atomic_load_op_code ldop_code;
11698 rtx src;
11699 rtx x;
11707 /* Make sure the value is in a register, putting it into a destination
11708 register if it needs to be manipulated. */
11711 {
11714 }
11715 else
11719 /* Preprocess the data for the operation as necessary. If the operation is
11720 a SET then emit a swap instruction and finish. */
11722 {
11728 /* Negate the value and treat it as a PLUS. */
11729 {
11730 rtx neg_src;
11732 /* Resize the value if necessary. */
11741 }
11742 /* Fall-through. */
11756 {
11757 rtx not_src;
11759 /* Resize the value if necessary. */
11768 }
11773 /* The operation can't be done with atomic instructions. */
11775 }
11779 /* If necessary, calculate the data in memory after the update by redoing the
11780 operation from values in registers. */
11785 {
11789 }
11794 {
11810 }
11815 }
11817 /* Split an atomic operation. */
11819 void
11822 {
11828 rtx x;
11830 /* Split the atomic operation into a sequence. */
11838 else
11842 /* The initial load can be relaxed for a __sync operation since a final
11843 barrier will be emitted to stop code hoisting. */
11847 else
11851 {
11865 {
11868 }
11869 /* Fall through. */
11875 }
11885 /* Emit any final barrier needed for a __sync operation. */
11888 }
11890 static void
11892 {
11893 /* Half-precision float operations. The compiler handles all operations
11894 with NULL libfuncs by converting to SFmode. */
11896 /* Conversions. */
11900 /* Arithmetic. */
11907 /* Comparisons. */
11915 }
11917 /* Target hook for c_mode_for_suffix. */
11918 static machine_mode
11920 {
11925 }
11927 /* We can only represent floating point constants which will fit in
11928 "quarter-precision" values. These values are characterised by
11929 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
11930 by:
11932 (-1)^s * (n/16) * 2^r
11934 Where:
11935 's' is the sign bit.
11936 'n' is an integer in the range 16 <= n <= 31.
11937 'r' is an integer in the range -3 <= r <= 4. */
11939 /* Return true iff X can be represented by a quarter-precision
11940 floating point immediate operand X. Note, we cannot represent 0.0. */
11941 bool
11943 {
11944 /* This represents our current view of how many bits
11945 make up the mantissa. */
11955 /* We don't support HFmode constants yet. */
11961 /* We cannot represent infinities, NaNs or +/-zero. We won't
11962 know if we have +zero until we analyse the mantissa, but we
11963 can reject the other invalid values. */
11968 /* Extract exponent. */
11972 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
11973 highest (sign) bit, with a fixed binary point at bit point_pos.
11974 m1 holds the low part of the mantissa, m2 the high part.
11975 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
11976 bits for the mantissa, this can fail (low bits will be lost). */
11980 /* If the low part of the mantissa has bits set we cannot represent
11981 the value. */
11984 /* We have rejected the lower HOST_WIDE_INT, so update our
11985 understanding of how many bits lie in the mantissa and
11986 look only at the high HOST_WIDE_INT. */
11990 /* We can only represent values with a mantissa of the form 1.xxxx. */
11995 /* Having filtered unrepresentable values, we may now remove all
11996 but the highest 5 bits. */
11999 /* We cannot represent the value 0.0, so reject it. This is handled
12000 elsewhere. */
12004 /* Then, as bit 4 is always set, we can mask it off, leaving
12005 the mantissa in the range [0, 15]. */
12009 /* GCC internally does not use IEEE754-like encoding (where normalized
12010 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12011 Our mantissa values are shifted 4 places to the left relative to
12012 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12013 by 5 places to correct for GCC's representation. */
12017 }
12021 machine_mode mode,
12023 {
12033 /* This will return true to show const_vector is legal for use as either
12034 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12035 also update INFO to show how the immediate should be generated. */
12044 {
12046 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12047 move immediate path. */
12050 else
12051 {
12060 else
12064 }
12065 }
12078 else
12082 }
12086 machine_mode mode)
12087 {
12088 machine_mode vmode;
12094 }
12096 /* Split operands into moves from op[1] + op[2] into op[0]. */
12098 void
12100 {
12111 {
12112 /* No-op move. Can't split to nothing; emit something. */
12115 }
12117 /* Preserve register attributes for variable tracking. */
12122 /* Special case of reversed high/low parts. */
12125 {
12129 }
12131 {
12132 /* Try to avoid unnecessary moves if part of the result
12133 is in the right place already. */
12138 }
12139 else
12140 {
12145 }
12146 }
12148 /* vec_perm support. */
12150 #define MAX_VECT_LEN 16
12152 struct expand_vec_perm_d
12153 {
12156 machine_mode vmode;
12160 };
12162 /* Generate a variable permutation. */
12164 static void
12166 {
12177 {
12179 {
12180 /* Expand the argument to a V16QI mode by duplicating it. */
12184 }
12185 else
12186 {
12188 }
12189 }
12190 else
12191 {
12192 rtx pair;
12195 {
12199 }
12200 else
12201 {
12205 }
12206 }
12207 }
12209 void
12211 {
12215 rtx mask;
12217 /* The TBL instruction does not use a modulo index, so we must take care
12218 of that ourselves. */
12223 /* For big-endian, we also need to reverse the index within the vector
12224 (but not which vector). */
12226 {
12227 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12232 }
12234 }
12236 /* Recognize patterns suitable for the TRN instructions. */
12237 static bool
12239 {
12248 /* Note that these are little-endian tests.
12249 We correct for big-endian later. */
12254 else
12259 {
12264 }
12266 /* Success! */
12273 {
12276 }
12280 {
12282 {
12297 }
12298 }
12299 else
12300 {
12302 {
12317 }
12318 }
12322 }
12324 /* Recognize patterns suitable for the UZP instructions. */
12325 static bool
12327 {
12336 /* Note that these are little-endian tests.
12337 We correct for big-endian later. */
12342 else
12347 {
12351 }
12353 /* Success! */
12360 {
12363 }
12367 {
12369 {
12384 }
12385 }
12386 else
12387 {
12389 {
12404 }
12405 }
12409 }
12411 /* Recognize patterns suitable for the ZIP instructions. */
12412 static bool
12414 {
12423 /* Note that these are little-endian tests.
12424 We correct for big-endian later. */
12427 /* Do Nothing. */
12428 ;
12431 else
12436 {
12443 }
12445 /* Success! */
12452 {
12455 }
12459 {
12461 {
12476 }
12477 }
12478 else
12479 {
12481 {
12496 }
12497 }
12501 }
12503 /* Recognize patterns for the EXT insn. */
12505 static bool
12507 {
12510 rtx offset;
12514 /* Check if the extracted indices are increasing by one. */
12516 {
12519 {
12520 /* We'll pass the same vector in twice, so allow indices to wrap. */
12522 }
12525 }
12528 {
12543 }
12545 /* Success! */
12549 /* The case where (location == 0) is a no-op for both big- and little-endian,
12550 and is removed by the mid-end at optimization levels -O1 and higher. */
12553 {
12554 /* After setup, we want the high elements of the first vector (stored
12555 at the LSB end of the register), and the low elements of the second
12556 vector (stored at the MSB end of the register). So swap. */
12558 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
12560 }
12565 }
12567 /* Recognize patterns for the REV insns. */
12569 static bool
12571 {
12580 {
12583 {
12588 }
12592 {
12599 }
12603 {
12616 }
12620 }
12624 {
12625 /* This is guaranteed to be true as the value of diff
12626 is 7, 3, 1 and we should have enough elements in the
12627 queue to generate this. Getting a vector mask with a
12628 value of diff other than these values implies that
12629 something is wrong by the time we get here. */
12633 }
12635 /* Success! */
12641 }
12643 static bool
12645 {
12648 rtx in0;
12651 rtx lane;
12655 {
12658 }
12660 /* The generic preparation in aarch64_expand_vec_perm_const_1
12661 swaps the operand order and the permute indices if it finds
12662 d->perm[0] to be in the second operand. Thus, we can always
12663 use d->op0 and need not do any extra arithmetic to get the
12664 correct lane number. */
12669 {
12684 }
12688 }
12690 static bool
12692 {
12700 /* Generic code will try constant permutation twice. Once with the
12701 original mode and again with the elements lowered to QImode.
12702 So wait and don't do the selector expansion ourselves. */
12707 {
12710 /* If big-endian and two vectors we end up with a weird mixed-endian
12711 mode on NEON. Reverse the index within each word but not the word
12712 itself. */
12715 }
12721 }
12723 static bool
12725 {
12726 /* The pattern matching functions above are written to look for a small
12727 number to begin the sequence (0, 1, N/2). If we begin with an index
12728 from the second operand, we can swap the operands. */
12730 {
12738 }
12741 {
12755 }
12757 }
12759 /* Expand a vec_perm_const pattern. */
12761 bool
12763 {
12777 {
12782 }
12785 {
12794 /* The elements of PERM do not suggest that only the first operand
12795 is used, but both operands are identical. Allow easier matching
12796 of the permutation by folding the permutation into the single
12797 input vector. */
12798 /* Fall Through. */
12810 }
12813 }
12815 static bool
12818 {
12828 /* Calculate whether all elements are in one vector. */
12830 {
12834 }
12836 /* If all elements are from the second vector, reindex as if from the
12837 first vector. */
12842 /* Check whether the mask can be applied to a single vector. */
12855 }
12857 rtx
12859 {
12860 /* We have to reverse each vector because we dont have
12861 a permuted load that can reverse-load according to ABI rules. */
12862 rtx mask;
12876 }
12878 /* Implement MODES_TIEABLE_P. In principle we should always return true.
12879 However due to issues with register allocation it is preferable to avoid
12880 tieing integer scalar and FP scalar modes. Executing integer operations
12881 in general registers is better than treating them as scalar vector
12882 operations. This reduces latency and avoids redundant int<->FP moves.
12883 So tie modes if they are either the same class, or vector modes with
12884 other vector modes, vector structs or any scalar mode.
12885 */
12887 bool
12889 {
12893 /* We specifically want to allow elements of "structure" modes to
12894 be tieable to the structure. This more general condition allows
12895 other rarer situations too. */
12899 /* Also allow any scalar modes with vectors. */
12905 }
12907 /* Return a new RTX holding the result of moving POINTER forward by
12908 AMOUNT bytes. */
12910 static rtx
12912 {
12917 }
12919 /* Return a new RTX holding the result of moving POINTER forward by the
12920 size of the mode it points to. */
12922 static rtx
12924 {
12928 }
12930 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
12931 MODE bytes. */
12933 static void
12935 machine_mode mode)
12936 {
12939 /* "Cast" the pointers to the correct mode. */
12942 /* Emit the memcpy. */
12945 /* Move the pointers forward. */
12948 }
12950 /* Expand movmem, as if from a __builtin_memcpy. Return true if
12951 we succeed, otherwise return false. */
12953 bool
12955 {
12959 rtx base;
12962 /* When optimizing for size, give a better estimate of the length of a
12963 memcpy call, but use the default otherwise. */
12966 /* We can't do anything smart if the amount to copy is not constant. */
12972 /* Try to keep the number of instructions low. For cases below 16 bytes we
12973 need to make at most two moves. For cases above 16 bytes it will be one
12974 move for each 16 byte chunk, then at most two additional moves. */
12984 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
12985 1-byte chunk. */
12987 {
12989 {
12992 }
12998 }
13000 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13001 4-byte chunk, partially overlapping with the previously copied chunk. */
13003 {
13007 {
13013 }
13015 }
13017 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13018 them, then (if applicable) an 8-byte chunk. */
13020 {
13022 {
13025 }
13026 else
13027 {
13030 }
13031 }
13033 /* Finish the final bytes of the copy. We can always do this in one
13034 instruction. We either copy the exact amount we need, or partially
13035 overlap with the previous chunk we copied and copy 8-bytes. */
13044 else
13045 {
13047 {
13051 }
13052 else
13053 {
13059 }
13060 }
13063 }
13065 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13067 static unsigned HOST_WIDE_INT
13069 {
13071 }
13073 static bool
13078 {
13079 /* STORE_BY_PIECES can be used when copying a constant string, but
13080 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13081 For now we always fail this and let the move_by_pieces code copy
13082 the string from read-only memory. */
13087 }
13089 static rtx
13092 {
13096 insn_code icode;
13107 {
13135 }
13140 {
13143 }
13152 {
13155 }
13161 }
13163 static rtx
13166 {
13170 insn_code icode;
13182 {
13210 }
13215 {
13218 }
13226 {
13231 }
13242 {
13245 }
13251 }
13253 #undef TARGET_GEN_CCMP_FIRST
13254 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13256 #undef TARGET_GEN_CCMP_NEXT
13257 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13259 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13260 instruction fusion of some sort. */
13262 static bool
13264 {
13266 }
13269 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13270 should be kept together during scheduling. */
13272 static bool
13274 {
13275 rtx set_dest;
13278 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13285 {
13286 /* We are trying to match:
13287 prev (mov) == (set (reg r0) (const_int imm16))
13288 curr (movk) == (set (zero_extract (reg r0)
13289 (const_int 16)
13290 (const_int 16))
13291 (const_int imm16_1)) */
13303 {
13305 }
13306 }
13309 {
13311 /* We're trying to match:
13312 prev (adrp) == (set (reg r1)
13313 (high (symbol_ref ("SYM"))))
13314 curr (add) == (set (reg r0)
13315 (lo_sum (reg r1)
13316 (symbol_ref ("SYM"))))
13317 Note that r0 need not necessarily be the same as r1, especially
13318 during pre-regalloc scheduling. */
13322 {
13330 }
13331 }
13334 {
13336 /* We're trying to match:
13337 prev (movk) == (set (zero_extract (reg r0)
13338 (const_int 16)
13339 (const_int 32))
13340 (const_int imm16_1))
13341 curr (movk) == (set (zero_extract (reg r0)
13342 (const_int 16)
13343 (const_int 48))
13344 (const_int imm16_2)) */
13360 }
13362 {
13363 /* We're trying to match:
13364 prev (adrp) == (set (reg r0)
13365 (high (symbol_ref ("SYM"))))
13366 curr (ldr) == (set (reg r1)
13367 (mem (lo_sum (reg r0)
13368 (symbol_ref ("SYM")))))
13369 or
13370 curr (ldr) == (set (reg r1)
13371 (zero_extend (mem
13372 (lo_sum (reg r0)
13373 (symbol_ref ("SYM")))))) */
13376 {
13389 }
13390 }
13398 {
13401 /* FIXME: this misses some which is considered simple arthematic
13402 instructions for ThunderX. Simple shifts are missed here. */
13408 }
13411 }
13413 /* Return true iff the instruction fusion described by OP is enabled. */
13415 bool
13417 {
13419 }
13421 /* If MEM is in the form of [base+offset], extract the two parts
13422 of address and set to BASE and OFFSET, otherwise return false
13423 after clearing BASE and OFFSET. */
13425 bool
13427 {
13428 rtx addr;
13435 {
13439 }
13443 {
13447 }
13453 }
13455 /* Types for scheduling fusion. */
13456 enum sched_fusion_type
13457 {
13459 SCHED_FUSION_LD_SIGN_EXTEND,
13460 SCHED_FUSION_LD_ZERO_EXTEND,
13461 SCHED_FUSION_LD,
13462 SCHED_FUSION_ST,
13463 SCHED_FUSION_NUM
13464 };
13466 /* If INSN is a load or store of address in the form of [base+offset],
13467 extract the two parts and set to BASE and OFFSET. Return scheduling
13468 fusion type this INSN is. */
13470 static enum sched_fusion_type
13472 {
13490 {
13495 }
13497 {
13502 }
13507 {
13510 }
13511 else
13518 }
13520 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
13522 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
13523 and PRI are only calculated for these instructions. For other instruction,
13524 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
13525 type instruction fusion can be added by returning different priorities.
13527 It's important that irrelevant instructions get the largest FUSION_PRI. */
13529 static void
13532 {
13542 {
13546 }
13548 /* Set FUSION_PRI according to fusion type and base register. */
13551 /* Calculate PRI. */
13554 /* INSN with smaller offset goes first. */
13558 else
13563 }
13565 /* Given OPERANDS of consecutive load/store, check if we can merge
13566 them into ldp/stp. LOAD is true if they are load instructions.
13567 MODE is the mode of memory operands. */
13569 bool
13572 {
13578 {
13586 }
13587 else
13588 {
13593 }
13595 /* The mems cannot be volatile. */
13599 /* Check if the addresses are in the form of [base+offset]. */
13607 /* Check if the bases are same. */
13614 /* Check if the offsets are consecutive. */
13618 /* Check if the addresses are clobbered by load. */
13620 {
13624 /* In increasing order, the last load can clobber the address. */
13627 }
13631 else
13636 else
13639 /* Check if the registers are of same class. */
13644 }
13646 /* Given OPERANDS of consecutive load/store, check if we can merge
13647 them into ldp/stp by adjusting the offset. LOAD is true if they
13648 are load instructions. MODE is the mode of memory operands.
13650 Given below consecutive stores:
13652 str w1, [xb, 0x100]
13653 str w1, [xb, 0x104]
13654 str w1, [xb, 0x108]
13655 str w1, [xb, 0x10c]
13657 Though the offsets are out of the range supported by stp, we can
13658 still pair them after adjusting the offset, like:
13660 add scratch, xb, 0x100
13661 stp w1, w1, [scratch]
13662 stp w1, w1, [scratch, 0x8]
13664 The peephole patterns detecting this opportunity should guarantee
13665 the scratch register is avaliable. */
13667 bool
13670 {
13677 {
13690 }
13691 else
13692 {
13701 }
13702 /* Skip if memory operand is by itslef valid for ldp/stp. */
13706 /* The mems cannot be volatile. */
13711 /* Check if the addresses are in the form of [base+offset]. */
13725 /* Check if the bases are same. */
13736 /* Check if the offsets are consecutive. */
13745 /* Check if the addresses are clobbered by load. */
13747 {
13753 /* In increasing order, the last load can clobber the address. */
13756 }
13760 else
13765 else
13770 else
13775 else
13778 /* Check if the registers are of same class. */
13783 }
13785 /* Given OPERANDS of consecutive load/store, this function pairs them
13786 into ldp/stp after adjusting the offset. It depends on the fact
13787 that addresses of load/store instructions are in increasing order.
13788 MODE is the mode of memory operands. CODE is the rtl operator
13789 which should be applied to all memory operands, it's SIGN_EXTEND,
13790 ZERO_EXTEND or UNKNOWN. */
13792 bool
13795 {
13801 {
13806 }
13807 else
13808 {
13814 }
13819 /* Adjust offset thus it can fit in ldp/stp instruction. */
13827 /* Further adjust to make sure all offsets are OK. */
13829 {
13832 }
13834 /* Make sure the adjustment can be done with ADD/SUB instructions. */
13839 {
13842 }
13844 /* Create new memory references. */
13848 /* Check if the adjusted address is OK for ldp/stp. */
13867 {
13872 }
13874 {
13879 }
13882 {
13887 }
13888 else
13889 {
13894 }
13896 /* Emit adjusting instruction. */
13898 /* Emit ldp/stp instructions. */
13906 }
13908 /* Return 1 if pseudo register should be created and used to hold
13909 GOT address for PIC code. */
13911 bool
13913 {
13915 }
13917 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
13919 static int
13921 {
13923 {
13930 }
13933 }
13936 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
13937 return the log2 of that value. Otherwise return -1. */
13939 int
13941 {
13956 }
13958 /* If X is a vector of equal CONST_DOUBLE values and that value is
13959 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
13961 int
13963 {
13979 }
13981 /* Implement TARGET_PROMOTED_TYPE to promote __fp16 to float. */
13982 static tree
13984 {
13988 }
13990 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
13992 static bool
13994 optimization_type opt_type)
13995 {
13997 {
14003 }
14004 }
14006 #undef TARGET_ADDRESS_COST
14007 #define TARGET_ADDRESS_COST aarch64_address_cost
14009 /* This hook will determines whether unnamed bitfields affect the alignment
14010 of the containing structure. The hook returns true if the structure
14011 should inherit the alignment requirements of an unnamed bitfield's
14012 type. */
14013 #undef TARGET_ALIGN_ANON_BITFIELD
14014 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14016 #undef TARGET_ASM_ALIGNED_DI_OP
14019 #undef TARGET_ASM_ALIGNED_HI_OP
14022 #undef TARGET_ASM_ALIGNED_SI_OP
14025 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14026 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14027 hook_bool_const_tree_hwi_hwi_const_tree_true
14029 #undef TARGET_ASM_FILE_START
14030 #define TARGET_ASM_FILE_START aarch64_start_file
14032 #undef TARGET_ASM_OUTPUT_MI_THUNK
14033 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14035 #undef TARGET_ASM_SELECT_RTX_SECTION
14036 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14038 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14039 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14041 #undef TARGET_BUILD_BUILTIN_VA_LIST
14042 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14044 #undef TARGET_CALLEE_COPIES
14045 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14047 #undef TARGET_CAN_ELIMINATE
14048 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14050 #undef TARGET_CAN_INLINE_P
14051 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14053 #undef TARGET_CANNOT_FORCE_CONST_MEM
14054 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14056 #undef TARGET_CASE_VALUES_THRESHOLD
14057 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14059 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14060 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14062 /* Only the least significant bit is used for initialization guard
14063 variables. */
14064 #undef TARGET_CXX_GUARD_MASK_BIT
14065 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14067 #undef TARGET_C_MODE_FOR_SUFFIX
14068 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14070 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14071 #undef TARGET_DEFAULT_TARGET_FLAGS
14072 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14073 #endif
14075 #undef TARGET_CLASS_MAX_NREGS
14076 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14078 #undef TARGET_BUILTIN_DECL
14079 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14081 #undef TARGET_BUILTIN_RECIPROCAL
14082 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14084 #undef TARGET_EXPAND_BUILTIN
14085 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14087 #undef TARGET_EXPAND_BUILTIN_VA_START
14088 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14090 #undef TARGET_FOLD_BUILTIN
14091 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14093 #undef TARGET_FUNCTION_ARG
14094 #define TARGET_FUNCTION_ARG aarch64_function_arg
14096 #undef TARGET_FUNCTION_ARG_ADVANCE
14097 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14099 #undef TARGET_FUNCTION_ARG_BOUNDARY
14100 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14102 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14103 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14105 #undef TARGET_FUNCTION_VALUE
14106 #define TARGET_FUNCTION_VALUE aarch64_function_value
14108 #undef TARGET_FUNCTION_VALUE_REGNO_P
14109 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14111 #undef TARGET_FRAME_POINTER_REQUIRED
14112 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14114 #undef TARGET_GIMPLE_FOLD_BUILTIN
14115 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14117 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14118 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14120 #undef TARGET_INIT_BUILTINS
14121 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14123 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14124 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14125 aarch64_ira_change_pseudo_allocno_class
14127 #undef TARGET_LEGITIMATE_ADDRESS_P
14128 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14130 #undef TARGET_LEGITIMATE_CONSTANT_P
14131 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14133 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14134 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14136 #undef TARGET_LRA_P
14137 #define TARGET_LRA_P hook_bool_void_true
14139 #undef TARGET_MANGLE_TYPE
14140 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14142 #undef TARGET_MEMORY_MOVE_COST
14143 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14145 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14146 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14148 #undef TARGET_MUST_PASS_IN_STACK
14149 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14151 /* This target hook should return true if accesses to volatile bitfields
14152 should use the narrowest mode possible. It should return false if these
14153 accesses should use the bitfield container type. */
14154 #undef TARGET_NARROW_VOLATILE_BITFIELD
14155 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14157 #undef TARGET_OPTION_OVERRIDE
14158 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14160 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14161 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14162 aarch64_override_options_after_change
14164 #undef TARGET_OPTION_SAVE
14165 #define TARGET_OPTION_SAVE aarch64_option_save
14167 #undef TARGET_OPTION_RESTORE
14168 #define TARGET_OPTION_RESTORE aarch64_option_restore
14170 #undef TARGET_OPTION_PRINT
14171 #define TARGET_OPTION_PRINT aarch64_option_print
14173 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14174 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14176 #undef TARGET_SET_CURRENT_FUNCTION
14177 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14179 #undef TARGET_PASS_BY_REFERENCE
14180 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14182 #undef TARGET_PREFERRED_RELOAD_CLASS
14183 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14185 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14186 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14188 #undef TARGET_PROMOTED_TYPE
14189 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14191 #undef TARGET_SECONDARY_RELOAD
14192 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14194 #undef TARGET_SHIFT_TRUNCATION_MASK
14195 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14197 #undef TARGET_SETUP_INCOMING_VARARGS
14198 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14200 #undef TARGET_STRUCT_VALUE_RTX
14201 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14203 #undef TARGET_REGISTER_MOVE_COST
14204 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14206 #undef TARGET_RETURN_IN_MEMORY
14207 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14209 #undef TARGET_RETURN_IN_MSB
14210 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14212 #undef TARGET_RTX_COSTS
14213 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14215 #undef TARGET_SCHED_ISSUE_RATE
14216 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14218 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14219 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14220 aarch64_sched_first_cycle_multipass_dfa_lookahead
14222 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14223 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14224 aarch64_first_cycle_multipass_dfa_lookahead_guard
14226 #undef TARGET_TRAMPOLINE_INIT
14227 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14229 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14230 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14232 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14233 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14235 #undef TARGET_ARRAY_MODE_SUPPORTED_P
14236 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
14238 #undef TARGET_VECTORIZE_ADD_STMT_COST
14239 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
14241 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
14242 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
14243 aarch64_builtin_vectorization_cost
14245 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14246 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
14248 #undef TARGET_VECTORIZE_BUILTINS
14249 #define TARGET_VECTORIZE_BUILTINS
14251 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
14252 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
14253 aarch64_builtin_vectorized_function
14255 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
14256 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
14257 aarch64_autovectorize_vector_sizes
14259 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14260 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
14261 aarch64_atomic_assign_expand_fenv
14263 /* Section anchor support. */
14265 #undef TARGET_MIN_ANCHOR_OFFSET
14266 #define TARGET_MIN_ANCHOR_OFFSET -256
14268 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
14269 byte offset; we can do much more for larger data types, but have no way
14270 to determine the size of the access. We assume accesses are aligned. */
14271 #undef TARGET_MAX_ANCHOR_OFFSET
14272 #define TARGET_MAX_ANCHOR_OFFSET 4095
14274 #undef TARGET_VECTOR_ALIGNMENT
14275 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
14277 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
14278 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
14279 aarch64_simd_vector_alignment_reachable
14281 /* vec_perm support. */
14283 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
14284 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
14285 aarch64_vectorize_vec_perm_const_ok
14287 #undef TARGET_INIT_LIBFUNCS
14288 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
14290 #undef TARGET_FIXED_CONDITION_CODE_REGS
14291 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
14293 #undef TARGET_FLAGS_REGNUM
14294 #define TARGET_FLAGS_REGNUM CC_REGNUM
14296 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
14297 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
14299 #undef TARGET_ASAN_SHADOW_OFFSET
14300 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
14302 #undef TARGET_LEGITIMIZE_ADDRESS
14303 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
14305 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14306 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14307 aarch64_use_by_pieces_infrastructure_p
14309 #undef TARGET_CAN_USE_DOLOOP_P
14310 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
14312 #undef TARGET_SCHED_MACRO_FUSION_P
14313 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
14315 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
14316 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
14318 #undef TARGET_SCHED_FUSION_PRIORITY
14319 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
14321 #undef TARGET_UNSPEC_MAY_TRAP_P
14322 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
14324 #undef TARGET_USE_PSEUDO_PIC_REG
14325 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
14327 #undef TARGET_PRINT_OPERAND
14328 #define TARGET_PRINT_OPERAND aarch64_print_operand
14330 #undef TARGET_PRINT_OPERAND_ADDRESS
14331 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
14333 #undef TARGET_OPTAB_SUPPORTED_P
14334 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
14336 #undef TARGET_OMIT_STRUCT_RETURN_REG
14337 #define TARGET_OMIT_STRUCT_RETURN_REG true