| blob | 32ac1752cedf37dc67ed46a6ed5099ccde09cc06 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 88, 89, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
55 /* Information about the loop being processed used to compute
56 the number of loop iterations for loop unrolling and doloop
57 optimization. */
60 /* Vector mapping INSN_UIDs to luids.
61 The luids are like uids but increase monotonically always.
62 We use them to see whether a jump comes from outside a given loop. */
66 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
67 number the insn is contained in. */
71 /* 1 + largest uid of any insn. */
75 /* 1 + luid of last insn. */
79 /* Number of loops detected in current function. Used as index to the
80 next few tables. */
84 /* Indexed by loop number, contains the first and last insn of each loop. */
88 /* Likewise for the continue insn */
91 /* The first code_label that is reached in every loop iteration.
92 0 when not computed yet, initially const0_rtx if a jump couldn't be
93 followed.
94 Also set to 0 when there is no such label before the NOTE_INSN_LOOP_CONT
95 of this loop, or in verify_dominator, if a jump couldn't be followed. */
98 /* For each loop, gives the containing loop number, -1 if none. */
102 #ifdef HAVE_decrement_and_branch_on_count
103 /* Records whether resource in use by inner loop. */
108 /* Indexed by loop number, contains a nonzero value if the "loop" isn't
109 really a loop (an insn outside the loop branches into it). */
113 /* Indexed by loop number, links together all LABEL_REFs which refer to
114 code labels outside the loop. Used by routines that need to know all
115 loop exits, such as final_biv_value and final_giv_value.
117 This does not include loop exits due to return instructions. This is
118 because all bivs and givs are pseudos, and hence must be dead after a
119 return, so the presense of a return does not affect any of the
120 optimizations that use this info. It is simpler to just not include return
121 instructions on this list. */
125 /* Indexed by loop number, counts the number of LABEL_REFs on
126 loop_number_exit_labels for this loop and all loops nested inside it. */
130 /* Indexed by register number, contains the number of times the reg
131 is set during the loop being scanned.
132 During code motion, a negative value indicates a reg that has been
133 made a candidate; in particular -2 means that it is an candidate that
134 we know is equal to a constant and -1 means that it is an candidate
135 not known equal to a constant.
136 After code motion, regs moved have 0 (which is accurate now)
137 while the failed candidates have the original number of times set.
139 Therefore, at all times, == 0 indicates an invariant register;
140 < 0 a conditionally invariant one. */
144 /* Original value of set_in_loop; same except that this value
145 is not set negative for a reg whose sets have been made candidates
146 and not set to 0 for a reg that is moved. */
150 /* Index by register number, 1 indicates that the register
151 cannot be moved or strength reduced. */
155 /* Contains the insn in which a register was used if it was used
156 exactly once; contains const0_rtx if it was used more than once. */
160 /* Nonzero means reg N has already been moved out of one loop.
161 This reduces the desire to move it out of another. */
165 /* List of MEMs that are stored in this loop. */
169 /* The insn where the first of these was found. */
178 /* Array of MEMs that are used (read or written) in this loop, but
179 cannot be aliased by anything in this loop, except perhaps
180 themselves. In other words, if loop_mems[i] is altered during the
181 loop, it is altered by an expression that is rtx_equal_p to it. */
185 /* The index of the next available slot in LOOP_MEMS. */
189 /* The number of elements allocated in LOOP_MEMs. */
193 /* Nonzero if we don't know what MEMs were changed in the current
194 loop. This happens if the loop contains a call (in which case
195 `loop_info->has_call' will also be set) or if we store into more
196 than NUM_STORES MEMs. */
200 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
203 /* Count of memory write instructions discovered in the loop. */
206 /* Bound on pseudo register number before loop optimization.
207 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
210 /* This obstack is used in product_cheap_p to allocate its rtl. It
211 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
212 If we used the same obstack that it did, we would be deallocating
213 that array. */
217 /* This is where the pointer to the obstack being used for RTL is stored. */
221 #define obstack_chunk_alloc xmalloc
222 #define obstack_chunk_free free
223 \f
224 /* During the analysis of a loop, a chain of `struct movable's
225 is made to record all the movable insns found.
226 Then the entire chain can be scanned to decide which to move. */
228 struct movable
229 {
234 of any registers used within the LIBCALL. */
236 that must be moved with this one. */
239 may be adjusted when matching movables
240 that load the same value are found. */
242 including other movables that force this
243 or match this one. */
247 /* If PARTIAL is 1, GLOBAL means something different:
248 that the reg is live outside the range from where it is set
249 to the following label. */
253 In particular, moving it does not make it
254 invariant. */
256 load SRC, rather than copying INSN. */
258 first insn of a consecutive sets group. */
261 that we should avoid changing when clearing
262 the rest of the reg. */
266 };
272 /* Forward declarations. */
288 #if 0
290 #endif
309 static void record_giv PROTO((struct induction *, rtx, rtx, rtx, rtx, rtx, int, enum g_types, int, int, rtx *, rtx, rtx));
337 rtx r;
342 rtx r1;
343 rtx r2;
346 /* Nonzero iff INSN is between START and END, inclusive. */
347 #define INSN_IN_RANGE_P(INSN, START, END) \
348 (INSN_UID (INSN) < max_uid_for_loop \
349 && INSN_LUID (INSN) >= INSN_LUID (START) \
350 && INSN_LUID (INSN) <= INSN_LUID (END))
352 #ifdef HAVE_decrement_and_branch_on_count
353 /* Test whether BCT applicable and safe. */
356 /* Auxiliary function that inserts the BCT pattern into the loop. */
360 /* Indirect_jump_in_function is computed once per function. */
368 \f
369 /* Relative gain of eliminating various kinds of operations. */
371 #if 0
374 #endif
376 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
377 copy the value of the strength reduced giv to its original register. */
380 /* Cost of using a register, to normalize the benefits of a giv. */
384 void
386 {
392 #ifdef ADDRESS_COST
394 #else
396 #endif
398 /* We multiply by 2 to reconcile the difference in scale between
399 these two ways of computing costs. Otherwise the cost of a copy
400 will be far less than the cost of an add. */
404 /* Free the objects we just allocated. */
407 /* Initialize the obstack used for rtl in product_cheap_p. */
409 }
410 \f
411 /* Compute the mapping from uids to luids.
412 LUIDs are numbers assigned to insns, like uids,
413 except that luids increase monotonically through the code.
414 Start at insn START and stop just before END. Assign LUIDs
415 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
416 static int
420 {
422 rtx insn;
425 {
428 /* Don't assign luids to line-number NOTEs, so that the distance in
429 luids between two insns is not affected by -g. */
433 else
434 /* Give a line number note the same luid as preceding insn. */
436 }
438 }
439 \f
440 /* Entry point of this file. Perform loop optimization
441 on the current function. F is the first insn of the function
442 and DUMPFILE is a stream for output of a trace of actions taken
443 (or 0 if none should be output). */
445 void
447 /* f is the first instruction of a chain of insns for one function */
448 rtx f;
451 {
466 /* Count the number of loops. */
470 {
473 max_loop_num++;
474 }
476 /* Don't waste time if no loops. */
480 /* Get size to use for tables indexed by uids.
481 Leave some space for labels allocated by find_and_verify_loops. */
490 /* Allocate tables for recording each loop. We set each entry, so they need
491 not be zeroed. */
501 #ifdef HAVE_decrement_and_branch_on_count
502 /* Allocate for BCT optimization */
507 /* Find and process each loop.
508 First, find them, and record them in order of their beginnings. */
511 /* Now find all register lifetimes. This must be done after
512 find_and_verify_loops, because it might reorder the insns in the
513 function. */
516 /* This must occur after reg_scan so that registers created by gcse
517 will have entries in the register tables.
519 We could have added a call to reg_scan after gcse_main in toplev.c,
520 but moving this call to init_alias_analysis is more efficient. */
523 /* See if we went too far. Note that get_max_uid already returns
524 one more that the maximum uid of all insn. */
527 /* Now reset it to the actual size we need. See above. */
530 /* find_and_verify_loops has already called compute_luids, but it might
531 have rearranged code afterwards, so we need to recompute the luids now. */
534 /* Don't leave gaps in uid_luid for insns that have been
535 deleted. It is possible that the first or last insn
536 using some register has been deleted by cross-jumping.
537 Make sure that uid_luid for that former insn's uid
538 points to the general area where that insn used to be. */
540 {
544 }
549 /* Create a mapping from loops to BLOCK tree nodes. */
553 /* Determine if the function has indirect jump. On some systems
554 this prevents low overhead loop instructions from being used. */
557 /* Now scan the loops, last ones first, since this means inner ones are done
558 before outer ones. */
564 /* If debugging and unrolling loops, we must replicate the tree nodes
565 corresponding to the blocks inside the loop, so that the original one
566 to one mapping will remain. */
571 }
572 \f
573 /* Returns the next insn, in execution order, after INSN. START and
574 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
575 respectively. LOOP_TOP, if non-NULL, is the top of the loop in the
576 insn-stream; it is used with loops that are entered near the
577 bottom. */
579 static rtx
581 rtx insn;
582 rtx start;
583 rtx end;
584 rtx loop_top;
585 {
589 {
591 /* Go to the top of the loop, and continue there. */
593 else
594 /* We're done. */
596 }
599 /* We're done. */
603 }
605 /* Optimize one loop whose start is LOOP_START and end is END.
606 LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching
607 NOTE_INSN_LOOP_END.
608 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
610 /* ??? Could also move memory writes out of loops if the destination address
611 is invariant, the source is invariant, the memory write is not volatile,
612 and if we can prove that no read inside the loop can read this address
613 before the write occurs. If there is a read of this address after the
614 write, then we can also mark the memory read as invariant. */
616 static void
620 {
622 rtx p;
623 /* 1 if we are scanning insns that could be executed zero times. */
625 /* 1 if we are scanning insns that might never be executed
626 due to a subroutine call which might exit before they are reached. */
628 /* For a rotated loop that is entered near the bottom,
629 this is the label at the top. Otherwise it is zero. */
631 /* Jump insn that enters the loop, or 0 if control drops in. */
633 /* Place in the loop where control enters. */
634 rtx scan_start;
635 /* Number of insns in the loop. */
639 rtx temp;
640 /* The SET from an insn, if it is the only SET in the insn. */
642 /* Chain describing insns movable in current loop. */
644 /* Last element in `movables' -- so we can add elements at the end. */
646 /* Ratio of extra register life span we can justify
647 for saving an instruction. More if loop doesn't call subroutines
648 since in that case saving an insn makes more difference
649 and more registers are available. */
651 /* Nonzero if we are scanning instructions in a sub-loop. */
656 /* Determine whether this loop starts with a jump down to a test at
657 the end. This will occur for a small number of loops with a test
658 that is too complex to duplicate in front of the loop.
660 We search for the first insn or label in the loop, skipping NOTEs.
661 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
662 (because we might have a loop executed only once that contains a
663 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
664 (in case we have a degenerate loop).
666 Note that if we mistakenly think that a loop is entered at the top
667 when, in fact, it is entered at the exit test, the only effect will be
668 slightly poorer optimization. Making the opposite error can generate
669 incorrect code. Since very few loops now start with a jump to the
670 exit test, the code here to detect that case is very conservative. */
673 p != end
679 ;
683 /* Set up variables describing this loop. */
687 /* If loop has a jump before the first label,
688 the true entry is the target of that jump.
689 Start scan from there.
690 But record in LOOP_TOP the place where the end-test jumps
691 back to so we can scan that after the end of the loop. */
693 {
696 /* Loop entry must be unconditional jump (and not a RETURN) */
699 /* Check to see whether the jump actually
700 jumps out of the loop (meaning it's no loop).
701 This case can happen for things like
702 do {..} while (0). If this label was generated previously
703 by loop, we can't tell anything about it and have to reject
704 the loop. */
706 {
709 }
710 }
712 /* If SCAN_START was an insn created by loop, we don't know its luid
713 as required by loop_reg_used_before_p. So skip such loops. (This
714 test may never be true, but it's best to play it safe.)
716 Also, skip loops where we do not start scanning at a label. This
717 test also rejects loops starting with a JUMP_INSN that failed the
718 test above. */
722 {
727 }
729 /* Count number of times each reg is set during this loop.
730 Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out
731 the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */
733 /* Allocate extra space for REGS that might be created by
734 load_mems. We allocate a little extra slop as well, in the hopes
735 that even after the moving of movables creates some new registers
736 we won't have to reallocate these arrays. However, we do grow
737 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
748 {
751 }
753 #ifdef AVOID_CCMODE_COPIES
754 /* Don't try to move insns which set CC registers if we should not
755 create CCmode register copies. */
759 #endif
765 {
771 }
773 /* Scan through the loop finding insns that are safe to move.
774 Set set_in_loop negative for the reg being set, so that
775 this reg will be considered invariant for subsequent insns.
776 We consider whether subsequent insns use the reg
777 in deciding whether it is worth actually moving.
779 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
780 and therefore it is possible that the insns we are scanning
781 would never be executed. At such times, we must make sure
782 that it is safe to execute the insn once instead of zero times.
783 When MAYBE_NEVER is 0, all insns will be executed at least once
784 so that is not a problem. */
789 {
801 {
808 /* Figure out what to use as a source of this insn. If a REG_EQUIV
809 note is given or if a REG_EQUAL note with a constant operand is
810 specified, use it as the source and mark that we should move
811 this insn by calling emit_move_insn rather that duplicating the
812 insn.
814 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
815 is present. */
819 else
820 {
825 {
827 /* A libcall block can use regs that don't appear in
828 the equivalent expression. To move the libcall,
829 we must move those regs too. */
831 }
832 }
834 /* Don't try to optimize a register that was made
835 by loop-optimization for an inner loop.
836 We don't know its life-span, so we can't compute the benefit. */
838 ;
840 than the one where it is set (meaning that
841 something after this point in the loop might
842 depend on its value before the set). */
844 /* And the set is not guaranteed to be executed one
845 the loop starts, or the value before the set is
846 needed before the set occurs...
848 ??? Note we have quadratic behaviour here, mitigated
849 by the fact that the previous test will often fail for
850 large loops. Rather than re-scanning the entire loop
851 each time for register usage, we should build tables
852 of the register usage and use them here instead. */
853 && (maybe_never
856 /* It is unsafe to move the set.
858 This code used to consider it OK to move a set of a variable
859 which was not created by the user and not used in an exit test.
860 That behavior is incorrect and was removed. */
861 ;
867 || (tem1
868 = consec_sets_invariant_p
871 p)))
872 /* If the insn can cause a trap (such as divide by zero),
873 can't move it unless it's guaranteed to be executed
874 once loop is entered. Even a function call might
875 prevent the trap insn from being reached
876 (since it might exit!) */
879 {
883 /* A potential lossage is where we have a case where two insns
884 can be combined as long as they are both in the loop, but
885 we move one of them outside the loop. For large loops,
886 this can lose. The most common case of this is the address
887 of a function being called.
889 Therefore, if this register is marked as being used exactly
890 once if we are in a loop with calls (a "large loop"), see if
891 we can replace the usage of this register with the source
892 of this SET. If we can, delete this insn.
894 Don't do this if P has a REG_RETVAL note or if we have
895 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
906 && (! SMALL_REGISTER_CLASSES
909 /* This test is not redundant; SET_SRC (set) might be
910 a call-clobbered register and the life of REGNO
911 might span a call. */
913 VARRAY_RTX
917 VARRAY_RTX
919 {
920 /* Replace any usage in a REG_EQUAL note. Must copy the
921 new source, so that we don't get rtx sharing between the
922 SET_SOURCE and REG_NOTES of insn p. */
933 }
952 /* Set M->cond if either invariant_p or consec_sets_invariant_p
953 returned 2 (only conditionally invariant). */
964 /* Add M to the end of the chain MOVABLES. */
967 else
972 {
973 /* It is possible for the first instruction to have a
974 REG_EQUAL note but a non-invariant SET_SRC, so we must
975 remember the status of the first instruction in case
976 the last instruction doesn't have a REG_EQUAL note. */
979 /* Skip this insn, not checking REG_LIBCALL notes. */
981 /* Skip the consecutive insns, if there are any. */
983 /* Back up to the last insn of the consecutive group. */
986 /* We must now reset m->move_insn, m->is_equiv, and possibly
987 m->set_src to correspond to the effects of all the
988 insns. */
992 else
993 {
997 else
1000 }
1002 }
1003 }
1004 /* If this register is always set within a STRICT_LOW_PART
1005 or set to zero, then its high bytes are constant.
1006 So clear them outside the loop and within the loop
1007 just load the low bytes.
1008 We must check that the machine has an instruction to do so.
1009 Also, if the value loaded into the register
1010 depends on the same register, this cannot be done. */
1020 {
1023 {
1037 /* If the insn may not be executed on some cycles,
1038 we can't clear the whole reg; clear just high part.
1039 Not even if the reg is used only within this loop.
1040 Consider this:
1041 while (1)
1042 while (s != t) {
1043 if (foo ()) x = *s;
1044 use (x);
1045 }
1046 Clearing x before the inner loop could clobber a value
1047 being saved from the last time around the outer loop.
1048 However, if the reg is not used outside this loop
1049 and all uses of the register are in the same
1050 basic block as the store, there is no problem.
1052 If this insn was made by loop, we don't know its
1053 INSN_LUID and hence must make a conservative
1054 assumption. */
1060 || (labels_in_range_p
1064 else
1073 /* Add M to the end of the chain MOVABLES. */
1076 else
1079 }
1080 }
1081 }
1082 /* Past a call insn, we get to insns which might not be executed
1083 because the call might exit. This matters for insns that trap.
1084 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
1085 so they don't count. */
1088 /* Past a label or a jump, we get to insns for which we
1089 can't count on whether or how many times they will be
1090 executed during each iteration. Therefore, we can
1091 only move out sets of trivial variables
1092 (those not used after the loop). */
1093 /* Similar code appears twice in strength_reduce. */
1095 /* If we enter the loop in the middle, and scan around to the
1096 beginning, don't set maybe_never for that. This must be an
1097 unconditional jump, otherwise the code at the top of the
1098 loop might never be executed. Unconditional jumps are
1099 followed a by barrier then loop end. */
1105 {
1106 /* At the virtual top of a converted loop, insns are again known to
1107 be executed: logically, the loop begins here even though the exit
1108 code has been duplicated. */
1112 loop_depth++;
1114 loop_depth--;
1115 }
1116 }
1118 /* If one movable subsumes another, ignore that other. */
1122 /* For each movable insn, see if the reg that it loads
1123 leads when it dies right into another conditionally movable insn.
1124 If so, record that the second insn "forces" the first one,
1125 since the second can be moved only if the first is. */
1129 /* See if there are multiple movable insns that load the same value.
1130 If there are, make all but the first point at the first one
1131 through the `match' field, and add the priorities of them
1132 all together as the priority of the first. */
1136 /* Now consider each movable insn to decide whether it is worth moving.
1137 Store 0 in set_in_loop for each reg that is moved.
1139 Generally this increases code size, so do not move moveables when
1140 optimizing for code size. */
1146 /* Now candidates that still are negative are those not moved.
1147 Change set_in_loop to indicate that those are not actually invariant. */
1152 /* Now that we've moved some things out of the loop, we might be able to
1153 hoist even more memory references. */
1158 {
1163 }
1169 }
1170 \f
1171 /* Add elements to *OUTPUT to record all the pseudo-regs
1172 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1174 void
1178 {
1186 {
1204 }
1208 {
1212 {
1221 }
1222 }
1223 }
1224 \f
1225 /* Check what regs are referred to in the libcall block ending with INSN,
1226 aside from those mentioned in the equivalent value.
1227 If there are none, return 0.
1228 If there are one or more, return an EXPR_LIST containing all of them. */
1230 rtx
1233 {
1238 /* First, find all the regs used in the libcall block
1239 that are not mentioned as inputs to the result. */
1242 {
1247 }
1250 }
1251 \f
1252 /* Return 1 if all uses of REG
1253 are between INSN and the end of the basic block. */
1255 static int
1258 {
1260 rtx p;
1265 /* Search this basic block for the already recorded last use of the reg. */
1267 {
1269 {
1275 /* Ordinary insn: if this is the last use, we win. */
1281 /* Jump insn: if this is the last use, we win. */
1284 /* Otherwise, it's the end of the basic block, so we lose. */
1289 /* It's the end of the basic block, so we lose. */
1294 }
1295 }
1297 /* The "last use" doesn't follow the "first use"?? */
1299 }
1300 \f
1301 /* Compute the benefit of eliminating the insns in the block whose
1302 last insn is LAST. This may be a group of insns used to compute a
1303 value directly or can contain a library call. */
1305 static int
1307 rtx last;
1308 {
1309 rtx insn;
1314 {
1317 routine. */
1321 benefit++;
1322 }
1325 }
1326 \f
1327 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1329 static rtx
1331 rtx insn;
1333 {
1335 {
1336 rtx temp;
1338 /* If first insn of libcall sequence, skip to end. */
1339 /* Do this at start of loop, since INSN is guaranteed to
1340 be an insn here. */
1347 }
1350 }
1352 /* Ignore any movable whose insn falls within a libcall
1353 which is part of another movable.
1354 We make use of the fact that the movable for the libcall value
1355 was made later and so appears later on the chain. */
1357 static void
1360 {
1364 {
1365 /* Is this a movable for the value of a libcall? */
1368 {
1369 rtx insn;
1370 /* Check for earlier movables inside that range,
1371 and mark them invalid. We cannot use LUIDs here because
1372 insns created by loop.c for prior loops don't have LUIDs.
1373 Rather than reject all such insns from movables, we just
1374 explicitly check each insn in the libcall (since invariant
1375 libcalls aren't that common). */
1380 }
1381 }
1382 }
1384 /* For each movable insn, see if the reg that it loads
1385 leads when it dies right into another conditionally movable insn.
1386 If so, record that the second insn "forces" the first one,
1387 since the second can be moved only if the first is. */
1389 static void
1392 {
1395 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1397 {
1400 /* ??? Could this be a bug? What if CSE caused the
1401 register of M1 to be used after this insn?
1402 Since CSE does not update regno_last_uid,
1403 this insn M->insn might not be where it dies.
1404 But very likely this doesn't matter; what matters is
1405 that M's reg is computed from M1's reg. */
1410 /* If m->consec, m->set_src isn't valid. */
1414 /* Increase the priority of the moving the first insn
1415 since it permits the second to be moved as well. */
1417 {
1421 }
1422 }
1423 }
1424 \f
1425 /* Find invariant expressions that are equal and can be combined into
1426 one register. */
1428 static void
1432 {
1437 /* Regs that are set more than once are not allowed to match
1438 or be matched. I'm no longer sure why not. */
1439 /* Perhaps testing m->consec_sets would be more appropriate here? */
1443 {
1450 /* We want later insns to match the first one. Don't make the first
1451 one match any later ones. So start this loop at m->next. */
1454 /* A reg used outside the loop mustn't be eliminated. */
1456 /* A reg used for zero-extending mustn't be eliminated. */
1459 ||
1460 (
1461 /* Can combine regs with different modes loaded from the
1462 same constant only if the modes are the same or
1463 if both are integer modes with M wider or the same
1464 width as M1. The check for integer is redundant, but
1465 safe, since the only case of differing destination
1466 modes with equal sources is when both sources are
1467 VOIDmode, i.e., CONST_INT. */
1473 /* See if the source of M1 says it matches M. */
1477 movables))))
1480 {
1486 }
1487 }
1489 /* Now combine the regs used for zero-extension.
1490 This can be done for those not marked `global'
1491 provided their lives don't overlap. */
1495 {
1498 /* Combine all the registers for extension from mode MODE.
1499 Don't combine any that are used outside this loop. */
1503 {
1509 {
1510 /* First one: don't check for overlap, just record it. */
1513 }
1515 /* Make sure they extend to the same mode.
1516 (Almost always true.) */
1520 /* We already have one: check for overlap with those
1521 already combined together. */
1528 /* No overlap: we can combine this with the others. */
1534 overlap: ;
1535 }
1536 }
1537 }
1538 \f
1539 /* Return 1 if regs X and Y will become the same if moved. */
1541 static int
1545 {
1562 }
1564 /* Return 1 if X and Y are identical-looking rtx's.
1565 This is the Lisp function EQUAL for rtx arguments.
1567 If two registers are matching movables or a movable register and an
1568 equivalent constant, consider them equal. */
1570 static int
1574 {
1588 /* If we have a register and a constant, they may sometimes be
1589 equal. */
1592 {
1597 }
1600 {
1605 }
1607 /* Otherwise, rtx's of different codes cannot be equal. */
1611 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1612 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1617 /* These three types of rtx's can be compared nonrecursively. */
1626 /* Compare the elements. If any pair of corresponding elements
1627 fail to match, return 0 for the whole things. */
1631 {
1633 {
1645 /* Two vectors must have the same length. */
1649 /* And the corresponding elements must match. */
1666 /* These are just backpointers, so they don't matter. */
1672 /* It is believed that rtx's at this level will never
1673 contain anything but integers and other rtx's,
1674 except for within LABEL_REFs and SYMBOL_REFs. */
1677 }
1678 }
1680 }
1681 \f
1682 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1683 insns in INSNS which use the reference. */
1685 static void
1687 rtx x;
1688 rtx insns;
1689 {
1693 rtx insn;
1696 {
1697 /* This code used to ignore labels that referred to dispatch tables to
1698 avoid flow generating (slighly) worse code.
1700 We no longer ignore such label references (see LABEL_REF handling in
1701 mark_jump_label for additional information). */
1706 }
1710 {
1716 }
1717 }
1718 \f
1719 /* Scan MOVABLES, and move the insns that deserve to be moved.
1720 If two matching movables are combined, replace one reg with the
1721 other throughout. */
1723 static void
1728 rtx loop_start;
1729 rtx end;
1731 {
1735 /* Map of pseudo-register replacements to handle combining
1736 when we move several insns that load the same value
1737 into different pseudo-registers. */
1747 {
1748 /* Describe this movable insn. */
1751 {
1772 }
1774 /* Count movables. Value used in heuristics in strength_reduce. */
1775 num_movables++;
1777 /* Ignore the insn if it's already done (it matched something else).
1778 Otherwise, see if it is now safe to move. */
1790 {
1795 /* We have an insn that is safe to move.
1796 Compute its desirability. */
1807 /* An insn MUST be moved if we already moved something else
1808 which is safe only if this one is moved too: that is,
1809 if already_moved[REGNO] is nonzero. */
1811 /* An insn is desirable to move if the new lifetime of the
1812 register is no more than THRESHOLD times the old lifetime.
1813 If it's not desirable, it means the loop is so big
1814 that moving won't speed things up much,
1815 and it is liable to make register usage worse. */
1817 /* It is also desirable to move if it can be moved at no
1818 extra cost because something else was already moved. */
1821 || flag_move_all_movables
1826 {
1831 /* Now move the insns that set the reg. */
1834 {
1837 /* Find the end of this chain of matching regs.
1838 Thus, we load each reg in the chain from that one reg.
1839 And that reg is loaded with 0 directly,
1840 since it has ->match == 0. */
1846 /* Mark the moved, invariant reg as being allowed to
1847 share a hard reg with the other matching invariant. */
1851 regs_may_share
1854 regs_may_share));
1862 }
1863 /* If we are to re-generate the item being moved with a
1864 new move insn, first delete what we have and then emit
1865 the move insn before the loop. */
1867 {
1871 {
1872 /* If this is the first insn of a library call sequence,
1873 skip to the end. */
1878 /* If this is the last insn of a libcall sequence, then
1879 delete every insn in the sequence except the last.
1880 The last insn is handled in the normal manner. */
1883 {
1887 }
1892 /* simplify_giv_expr expects that it can walk the insns
1893 at m->insn forwards and see this old sequence we are
1894 tossing here. delete_insn does preserve the next
1895 pointers, but when we skip over a NOTE we must fix
1896 it up. Otherwise that code walks into the non-deleted
1897 insn stream. */
1900 }
1918 /* The more regs we move, the less we like moving them. */
1920 }
1921 else
1922 {
1924 {
1927 /* If first insn of libcall sequence, skip to end. */
1928 /* Do this at start of loop, since p is guaranteed to
1929 be an insn here. */
1934 /* If last insn of libcall sequence, move all
1935 insns except the last before the loop. The last
1936 insn is handled in the normal manner. */
1939 {
1947 {
1948 rtx body;
1949 rtx n;
1950 rtx next;
1957 /* Find the next insn after TEMP,
1958 not counting USE or NOTE insns. */
1966 /* If that is the call, this may be the insn
1967 that loads the function address.
1969 Extract the function address from the insn
1970 that loads it into a register.
1971 If this insn was cse'd, we get incorrect code.
1973 So emit a new move insn that copies the
1974 function address into the register that the
1975 call insn will use. flow.c will delete any
1976 redundant stores that we have created. */
1981 NULL_RTX)))
1982 {
1988 }
1989 /* We have the call insn.
1990 If it uses the register we suspect it might,
1991 load it with the correct address directly. */
1996 fn_address),
1997 fn_address_insn);
2000 {
2002 /* Because the USAGE information potentially
2003 contains objects other than hard registers
2004 we need to copy it. */
2008 }
2009 else
2017 }
2020 }
2022 {
2023 /* P sets REG to zero; but we should clear only
2024 the bits that are not covered by the mode
2025 m->savemode. */
2027 rtx sequence;
2028 rtx tem;
2031 tem = expand_binop
2044 }
2046 {
2048 /* Because the USAGE information potentially
2049 contains objects other than hard registers
2050 we need to copy it. */
2054 }
2056 {
2057 /* The SET_SRC might not be invariant, so we must
2058 use the REG_EQUAL note. */
2072 }
2073 else
2077 {
2080 /* If there is a REG_EQUAL note present whose value
2081 is not loop invariant, then delete it, since it
2082 may cause problems with later optimization passes.
2083 It is possible for cse to create such notes
2084 like this as a result of record_jump_cond. */
2089 }
2098 /* If library call, now fix the REG_NOTES that contain
2099 insn pointers, namely REG_LIBCALL on FIRST
2100 and REG_RETVAL on I1. */
2102 {
2106 }
2112 /* simplify_giv_expr expects that it can walk the insns
2113 at m->insn forwards and see this old sequence we are
2114 tossing here. delete_insn does preserve the next
2115 pointers, but when we skip over a NOTE we must fix
2116 it up. Otherwise that code walks into the non-deleted
2117 insn stream. */
2120 }
2122 /* The more regs we move, the less we like moving them. */
2124 }
2126 /* Any other movable that loads the same register
2127 MUST be moved. */
2130 /* This reg has been moved out of one loop. */
2133 /* The reg set here is now invariant. */
2139 /* Change the length-of-life info for the register
2140 to say it lives at least the full length of this loop.
2141 This will help guide optimizations in outer loops. */
2144 /* This is the old insn before all the moved insns.
2145 We can't use the moved insn because it is out of range
2146 in uid_luid. Only the old insns have luids. */
2151 /* Combine with this moved insn any other matching movables. */
2156 {
2157 rtx temp;
2159 /* Schedule the reg loaded by M1
2160 for replacement so that shares the reg of M.
2161 If the modes differ (only possible in restricted
2162 circumstances, make a SUBREG.
2164 Note this assumes that the target dependent files
2165 treat REG and SUBREG equally, including within
2166 GO_IF_LEGITIMATE_ADDRESS and in all the
2167 predicates since we never verify that replacing the
2168 original register with a SUBREG results in a
2169 recognizable insn. */
2172 else
2177 /* Get rid of the matching insn
2178 and prevent further processing of it. */
2181 /* if library call, delete all insn except last, which
2182 is deleted below */
2184 NULL_RTX)))
2185 {
2189 }
2192 /* Any other movable that loads the same register
2193 MUST be moved. */
2196 /* The reg merged here is now invariant,
2197 if the reg it matches is invariant. */
2200 }
2201 }
2204 }
2210 }
2215 /* Go through all the instructions in the loop, making
2216 all the register substitutions scheduled in REG_MAP. */
2220 {
2224 }
2225 }
2226 \f
2227 #if 0
2228 /* Scan X and replace the address of any MEM in it with ADDR.
2229 REG is the address that MEM should have before the replacement. */
2231 static void
2234 {
2243 {
2255 /* Short cut for very common case. */
2260 /* Short cut for very common case. */
2265 /* If this MEM uses a reg other than the one we expected,
2266 something is wrong. */
2274 }
2278 {
2282 {
2286 }
2287 }
2288 }
2289 #endif
2290 \f
2291 /* Return the number of memory refs to addresses that vary
2292 in the rtx X. */
2294 static int
2296 rtx x;
2297 {
2308 {
2325 }
2330 {
2334 {
2338 }
2339 }
2341 }
2343 \f
2344 #if 0
2345 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2346 Replace it with an instruction to load just the low bytes
2347 if the machine supports such an instruction,
2348 and insert above LOOP_START an instruction to clear the register. */
2350 static void
2353 {
2357 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2358 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2360 new
2361 = gen_rtx_SET
2363 gen_rtx_STRICT_LOW_PART
2372 {
2375 /* Clear destination register before the loop. */
2378 loop_start);
2380 /* Inside the loop, just load the low part. */
2382 }
2383 }
2384 #endif
2385 \f
2386 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2387 `has_call', `has_volatile', and `has_tablejump' within LOOP_INFO.
2388 Set the global variables `unknown_address_altered' and
2389 `num_mem_sets'. Also, fill in the array `loop_mems' and the list
2390 `loop_store_mems'. */
2392 static void
2396 {
2398 rtx insn;
2399 /* The label after END. Jumping here is just like falling off the
2400 end of the loop. We use next_nonnote_insn instead of next_label
2401 as a hedge against the (pathological) case where some actual insn
2402 might end up between the two. */
2423 {
2425 {
2427 {
2429 /* Count number of loops contained in this one. */
2431 }
2433 {
2436 {
2439 }
2440 }
2442 {
2445 }
2447 {
2448 /* If there is a NOTE_INSN_LOOP_VTOP, then this is a for
2449 or while style loop, with a loop exit test at the
2450 start. Thus, we can assume that the loop condition
2451 was true when the loop was entered. */
2454 }
2455 }
2457 {
2461 }
2463 {
2483 {
2485 {
2488 }
2489 else
2490 {
2492 }
2496 {
2498 {
2499 /* Something tricky. */
2502 }
2505 {
2506 /* A jump outside the current loop. */
2509 }
2510 }
2515 }
2516 }
2519 }
2521 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2523 !unknown_address_altered
2524 /* An exception thrown by a called function might land us
2525 anywhere. */
2527 /* We don't want loads for MEMs moved to a location before the
2528 one at which their stack memory becomes allocated. (Note
2529 that this is not a problem for malloc, etc., since those
2530 require actual function calls. */
2531 && !current_function_calls_alloca
2532 /* There are ways to leave the loop other than falling off the
2533 end. */
2538 }
2539 \f
2540 /* LOOP_NUMBER_CONT_DOMINATOR is now the last label between the loop start
2541 and the continue note that is a the destination of a (cond)jump after
2542 the continue note. If there is any (cond)jump between the loop start
2543 and what we have so far as LOOP_NUMBER_CONT_DOMINATOR that has a
2544 target between LOOP_DOMINATOR and the continue note, move
2545 LOOP_NUMBER_CONT_DOMINATOR forward to that label; if a jump's
2546 destination cannot be determined, clear LOOP_NUMBER_CONT_DOMINATOR. */
2548 static void
2551 {
2552 rtx insn;
2555 /* This can happen for an empty loop, e.g. in
2556 gcc.c-torture/compile/920410-2.c */
2559 {
2562 }
2566 {
2569 {
2573 /* If it is not a jump we can easily understand or for
2574 which we do not have jump target information in the JUMP_LABEL
2575 field (consider ADDR_VEC and ADDR_DIFF_VEC insns), then clear
2576 LOOP_NUMBER_CONT_DOMINATOR. */
2580 {
2583 }
2587 && (label_luid
2590 }
2591 }
2592 }
2594 /* Scan the function looking for loops. Record the start and end of each loop.
2595 Also mark as invalid loops any loops that contain a setjmp or are branched
2596 to from outside the loop. */
2598 static void
2600 rtx f;
2601 {
2609 /* If there are jumps to undefined labels,
2610 treat them as jumps out of any/all loops.
2611 This also avoids writing past end of tables when there are no loops. */
2614 /* Find boundaries of loops, mark which loops are contained within
2615 loops, and invalidate loops that have setjmp. */
2618 {
2621 {
2635 /* In this case, we must invalidate our current loop and any
2636 enclosing loop. */
2638 {
2644 }
2661 }
2662 /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT
2663 and NOTE_INSN_LOOP_END notes, update loop_number_loop_dominator. */
2667 {
2675 do
2676 {
2677 /* First see if we care about this loop. */
2680 {
2681 /* If the jump destination is not known, invalidate
2682 loop_number_const_dominator. */
2685 else
2686 /* Check if the destination is between loop start and
2687 cont. */
2692 /* And if there is no later destination already
2693 recorded. */
2699 }
2701 }
2703 }
2705 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2706 enclosing loop, but this doesn't matter. */
2708 }
2710 /* Any loop containing a label used in an initializer must be invalidated,
2711 because it can be jumped into from anywhere. */
2714 {
2721 }
2723 /* Any loop containing a label used for an exception handler must be
2724 invalidated, because it can be jumped into from anywhere. */
2727 {
2734 }
2736 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2737 loop that it is not contained within, that loop is marked invalid.
2738 If any INSN or CALL_INSN uses a label's address, then the loop containing
2739 that label is marked invalid, because it could be jumped into from
2740 anywhere.
2742 Also look for blocks of code ending in an unconditional branch that
2743 exits the loop. If such a block is surrounded by a conditional
2744 branch around the block, move the block elsewhere (see below) and
2745 invert the jump to point to the code block. This may eliminate a
2746 label in our loop and will simplify processing by both us and a
2747 possible second cse pass. */
2751 {
2755 {
2758 {
2765 }
2766 }
2773 /* See if this is an unconditional branch outside the loop. */
2780 {
2781 rtx p;
2787 /* Go backwards until we reach the start of the loop, a label,
2788 or a JUMP_INSN. */
2795 ;
2797 /* Check for the case where we have a jump to an inner nested
2798 loop, and do not perform the optimization in that case. */
2801 {
2804 {
2809 }
2810 }
2812 /* Make sure that the target of P is within the current loop. */
2818 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2819 we have a block of code to try to move.
2821 We look backward and then forward from the target of INSN
2822 to find a BARRIER at the same loop depth as the target.
2823 If we find such a BARRIER, we make a new label for the start
2824 of the block, invert the jump in P and point it to that label,
2825 and move the block of code to the spot we found. */
2830 /* Just ignore jumps to labels that were never emitted.
2831 These always indicate compilation errors. */
2836 /* If it's not safe to move the sequence, then we
2837 mustn't try. */
2840 {
2841 rtx target
2844 rtx loc;
2858 {
2862 /* Ensure our label doesn't go away. */
2865 /* Verify that uid_loop_num is large enough and that
2866 we can invert P. */
2868 {
2871 /* If no suitable BARRIER was found, create a suitable
2872 one before TARGET. Since TARGET is a fall through
2873 path, we'll need to insert an jump around our block
2874 and a add a BARRIER before TARGET.
2876 This creates an extra unconditional jump outside
2877 the loop. However, the benefits of removing rarely
2878 executed instructions from inside the loop usually
2879 outweighs the cost of the extra unconditional jump
2880 outside the loop. */
2882 {
2883 rtx temp;
2890 }
2892 /* Include the BARRIER after INSN and copy the
2893 block after LOC. */
2895 last_insn_to_move);
2898 /* All those insns are now in TARGET_LOOP_NUM. */
2904 /* The label jumped to by INSN is no longer a loop exit.
2905 Unless INSN does not have a label (e.g., it is a
2906 RETURN insn), search loop_number_exit_labels to find
2907 its label_ref, and remove it. Also turn off
2908 LABEL_OUTSIDE_LOOP_P bit. */
2910 {
2917 {
2921 else
2925 }
2932 /* If we didn't find it, then something is wrong. */
2935 }
2937 /* P is now a jump outside the loop, so it must be put
2938 in loop_number_exit_labels, and marked as such.
2939 The easiest way to do this is to just call
2940 mark_loop_jump again for P. */
2943 /* If INSN now jumps to the insn after it,
2944 delete INSN. */
2949 }
2951 /* Continue the loop after where the conditional
2952 branch used to jump, since the only branch insn
2953 in the block (if it still remains) is an inter-loop
2954 branch and hence needs no processing. */
2960 /* This loop will be continued with NEXT_INSN (insn). */
2962 }
2963 }
2964 }
2965 }
2966 }
2968 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2969 loops it is contained in, mark the target loop invalid.
2971 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2973 static void
2975 rtx x;
2977 {
2983 {
2995 /* There could be a label reference in here. */
3007 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3019 /* Link together all labels that branch outside the loop. This
3020 is used by final_[bg]iv_value and the loop unrolling code. Also
3021 mark this LABEL_REF so we know that this branch should predict
3022 false. */
3024 /* A check to make sure the label is not in an inner nested loop,
3025 since this does not count as a loop exit. */
3027 {
3032 }
3033 else
3037 {
3046 }
3048 /* If this is inside a loop, but not in the current loop or one enclosed
3049 by it, it invalidates at least one loop. */
3054 /* We must invalidate every nested loop containing the target of this
3055 label, except those that also contain the jump insn. */
3058 {
3059 /* Stop when we reach a loop that also contains the jump insn. */
3065 /* If we get here, we know we need to invalidate a loop. */
3072 }
3076 /* If this is not setting pc, ignore. */
3098 /* Strictly speaking this is not a jump into the loop, only a possible
3099 jump out of the loop. However, we have no way to link the destination
3100 of this jump onto the list of exit labels. To be safe we mark this
3101 loop and any containing loops as invalid. */
3103 {
3106 {
3112 }
3113 }
3115 }
3116 }
3117 \f
3118 /* Return nonzero if there is a label in the range from
3119 insn INSN to and including the insn whose luid is END
3120 INSN must have an assigned luid (i.e., it must not have
3121 been previously created by loop.c). */
3123 static int
3125 rtx insn;
3127 {
3129 {
3133 }
3136 }
3138 /* Record that a memory reference X is being set. */
3140 static void
3142 rtx x;
3143 rtx y ATTRIBUTE_UNUSED;
3144 {
3148 /* Count number of memory writes.
3149 This affects heuristics in strength_reduce. */
3150 num_mem_sets++;
3152 /* BLKmode MEM means all memory is clobbered. */
3160 }
3161 \f
3162 /* Return nonzero if the rtx X is invariant over the current loop.
3164 The value is 2 if we refer to something only conditionally invariant.
3166 If `unknown_address_altered' is nonzero, no memory ref is invariant.
3167 Otherwise, a memory ref is invariant if it does not conflict with
3168 anything stored in `loop_store_mems'. */
3170 int
3173 {
3178 rtx mem_list_entry;
3184 {
3192 /* A LABEL_REF is normally invariant, however, if we are unrolling
3193 loops, and this label is inside the loop, then it isn't invariant.
3194 This is because each unrolled copy of the loop body will have
3195 a copy of this label. If this was invariant, then an insn loading
3196 the address of this label into a register might get moved outside
3197 the loop, and then each loop body would end up using the same label.
3199 We don't know the loop bounds here though, so just fail for all
3200 labels. */
3203 else
3212 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3213 since the reg might be set by initialization within the loop. */
3230 /* Volatile memory references must be rejected. Do this before
3231 checking for read-only items, so that volatile read-only items
3232 will be rejected also. */
3236 /* Read-only items (such as constants in a constant pool) are
3237 invariant if their address is. */
3241 /* If we had a subroutine call, any location in memory could have been
3242 clobbered. */
3246 /* See if there is any dependence between a store and this load. */
3249 {
3254 }
3256 /* It's not invalidated by a store in memory
3257 but we must still verify the address is invariant. */
3261 /* Don't mess with insns declared volatile. */
3268 }
3272 {
3274 {
3280 }
3282 {
3285 {
3291 }
3293 }
3294 }
3297 }
3299 \f
3300 /* Return nonzero if all the insns in the loop that set REG
3301 are INSN and the immediately following insns,
3302 and if each of those insns sets REG in an invariant way
3303 (not counting uses of REG in them).
3305 The value is 2 if some of these insns are only conditionally invariant.
3307 We assume that INSN itself is the first set of REG
3308 and that its source is invariant. */
3310 static int
3314 {
3317 rtx temp;
3318 /* Number of sets we have to insist on finding after INSN. */
3324 /* If N_SETS hit the limit, we can't rely on its value. */
3331 {
3333 rtx set;
3338 /* If library call, skip to end of it. */
3347 {
3352 {
3353 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3354 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3355 notes are OK. */
3361 }
3362 }
3364 count--;
3366 {
3369 }
3370 }
3373 /* If invariant_p ever returned 2, we return 2. */
3375 }
3377 #if 0
3378 /* I don't think this condition is sufficient to allow INSN
3379 to be moved, so we no longer test it. */
3381 /* Return 1 if all insns in the basic block of INSN and following INSN
3382 that set REG are invariant according to TABLE. */
3384 static int
3388 {
3393 {
3402 {
3405 }
3406 }
3407 }
3409 \f
3410 /* Look at all uses (not sets) of registers in X. For each, if it is
3411 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3412 a different insn, set USAGE[REGNO] to const0_rtx. */
3414 static void
3416 rtx insn;
3417 rtx x;
3418 varray_type usage;
3419 {
3431 {
3432 /* Don't count SET_DEST if it is a REG; otherwise count things
3433 in SET_DEST because if a register is partially modified, it won't
3434 show up as a potential movable so we don't care how USAGE is set
3435 for it. */
3439 }
3440 else
3442 {
3448 }
3449 }
3450 \f
3451 /* Count and record any set in X which is contained in INSN. Update
3452 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3454 static void
3457 varray_type may_not_move;
3459 {
3461 /* Don't move a reg that has an explicit clobber.
3462 It's not worth the pain to try to do it correctly. */
3466 {
3474 {
3476 /* If this is the first setting of this reg
3477 in current basic block, and it was set before,
3478 it must be set in two basic blocks, so it cannot
3479 be moved out of the loop. */
3483 /* If this is not first setting in current basic block,
3484 see if reg was used in between previous one and this.
3485 If so, neither one can be moved. */
3492 }
3493 }
3494 }
3496 /* Increment SET_IN_LOOP at the index of each register
3497 that is modified by an insn between FROM and TO.
3498 If the value of an element of SET_IN_LOOP becomes 127 or more,
3499 stop incrementing it, to avoid overflow.
3501 Store in SINGLE_USAGE[I] the single insn in which register I is
3502 used, if it is only used once. Otherwise, it is set to 0 (for no
3503 uses) or const0_rtx for more than one use. This parameter may be zero,
3504 in which case this processing is not done.
3506 Store in *COUNT_PTR the number of actual instruction
3507 in the loop. We use this to decide what is worth moving out. */
3509 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3510 In that case, it is the insn that last set reg n. */
3512 static void
3515 varray_type may_not_move;
3516 varray_type single_usage;
3519 {
3526 {
3528 {
3531 /* Record registers that have exactly one use. */
3534 /* Include uses in REG_EQUAL notes. */
3542 {
3547 }
3548 }
3552 }
3554 }
3555 \f
3556 /* Given a loop that is bounded by LOOP_START and LOOP_END
3557 and that is entered at SCAN_START,
3558 return 1 if the register set in SET contained in insn INSN is used by
3559 any insn that precedes INSN in cyclic order starting
3560 from the loop entry point.
3562 We don't want to use INSN_LUID here because if we restrict INSN to those
3563 that have a valid INSN_LUID, it means we cannot move an invariant out
3564 from an inner loop past two loops. */
3566 static int
3569 {
3571 rtx p;
3573 /* Scan forward checking for register usage. If we hit INSN, we
3574 are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */
3576 {
3583 }
3586 }
3587 \f
3588 /* A "basic induction variable" or biv is a pseudo reg that is set
3589 (within this loop) only by incrementing or decrementing it. */
3590 /* A "general induction variable" or giv is a pseudo reg whose
3591 value is a linear function of a biv. */
3593 /* Bivs are recognized by `basic_induction_var';
3594 Givs by `general_induction_var'. */
3596 /* Indexed by register number, indicates whether or not register is an
3597 induction variable, and if so what type. */
3599 varray_type reg_iv_type;
3601 /* Indexed by register number, contains pointer to `struct induction'
3602 if register is an induction variable. This holds general info for
3603 all induction variables. */
3605 varray_type reg_iv_info;
3607 /* Indexed by register number, contains pointer to `struct iv_class'
3608 if register is a basic induction variable. This holds info describing
3609 the class (a related group) of induction variables that the biv belongs
3610 to. */
3614 /* The head of a list which links together (via the next field)
3615 every iv class for the current loop. */
3619 /* Givs made from biv increments are always splittable for loop unrolling.
3620 Since there is no regscan info for them, we have to keep track of them
3621 separately. */
3624 /* Communication with routines called via `note_stores'. */
3628 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3632 /* ??? Unfinished optimizations, and possible future optimizations,
3633 for the strength reduction code. */
3635 /* ??? The interaction of biv elimination, and recognition of 'constant'
3636 bivs, may cause problems. */
3638 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3639 performance problems.
3641 Perhaps don't eliminate things that can be combined with an addressing
3642 mode. Find all givs that have the same biv, mult_val, and add_val;
3643 then for each giv, check to see if its only use dies in a following
3644 memory address. If so, generate a new memory address and check to see
3645 if it is valid. If it is valid, then store the modified memory address,
3646 otherwise, mark the giv as not done so that it will get its own iv. */
3648 /* ??? Could try to optimize branches when it is known that a biv is always
3649 positive. */
3651 /* ??? When replace a biv in a compare insn, we should replace with closest
3652 giv so that an optimized branch can still be recognized by the combiner,
3653 e.g. the VAX acb insn. */
3655 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3656 was rerun in loop_optimize whenever a register was added or moved.
3657 Also, some of the optimizations could be a little less conservative. */
3658 \f
3659 /* Perform strength reduction and induction variable elimination.
3661 Pseudo registers created during this function will be beyond the last
3662 valid index in several tables including n_times_set and regno_last_uid.
3663 This does not cause a problem here, because the added registers cannot be
3664 givs outside of their loop, and hence will never be reconsidered.
3665 But scan_loop must check regnos to make sure they are in bounds.
3667 SCAN_START is the first instruction in the loop, as the loop would
3668 actually be executed. END is the NOTE_INSN_LOOP_END. LOOP_TOP is
3669 the first instruction in the loop, as it is layed out in the
3670 instruction stream. LOOP_START is the NOTE_INSN_LOOP_BEG.
3671 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
3673 static void
3676 rtx scan_start;
3677 rtx end;
3678 rtx loop_top;
3680 rtx loop_start;
3681 rtx loop_end;
3683 rtx loop_cont;
3685 {
3686 rtx p;
3687 rtx set;
3688 rtx inc_val;
3689 rtx mult_val;
3690 rtx dest_reg;
3692 /* This is 1 if current insn is not executed at least once for every loop
3693 iteration. */
3695 /* This is 1 if current insn may be executed more than once for every
3696 loop iteration. */
3698 /* This is 1 if we have past a branch back to the top of the loop
3699 (aka a loop latch). */
3701 /* Temporary list pointers for traversing loop_iv_list. */
3703 /* Ratio of extra register life span we can justify
3704 for saving an instruction. More if loop doesn't call subroutines
3705 since in that case saving an insn makes more difference
3706 and more registers are available. */
3707 /* ??? could set this to last value of threshold in move_movables */
3709 /* Map of pseudo-register replacements. */
3713 rtx test;
3714 rtx end_insert_before;
3719 /* If scan_start points to the loop exit test, we have to be wary of
3720 subversive use of gotos inside expression statements. */
3734 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3735 must be put before this insn, so that they will appear in the right
3736 order (i.e. loop order).
3738 If loop_end is the end of the current function, then emit a
3739 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3740 dummy note insn. */
3743 else
3746 /* Scan through loop to find all possible bivs. */
3751 {
3755 {
3760 {
3764 {
3765 /* It is a possible basic induction variable.
3766 Create and initialize an induction structure for it. */
3774 }
3777 }
3778 }
3780 /* Past CODE_LABEL, we get to insns that may be executed multiple
3781 times. The only way we can be sure that they can't is if every
3782 jump insn between here and the end of the loop either
3783 returns, exits the loop, is a jump to a location that is still
3784 behind the label, or is a jump to the loop start. */
3787 {
3793 {
3798 {
3801 else
3805 }
3813 {
3816 }
3817 }
3818 }
3820 /* Past a jump, we get to insns for which we can't count
3821 on whether they will be executed during each iteration. */
3822 /* This code appears twice in strength_reduce. There is also similar
3823 code in scan_loop. */
3825 /* If we enter the loop in the middle, and scan around to the
3826 beginning, don't set not_every_iteration for that.
3827 This can be any kind of jump, since we want to know if insns
3828 will be executed if the loop is executed. */
3832 {
3835 /* If this is a jump outside the loop, then it also doesn't
3836 matter. Check to see if the target of this branch is on the
3837 loop_number_exits_labels list. */
3840 label;
3847 }
3850 {
3851 /* At the virtual top of a converted loop, insns are again known to
3852 be executed each iteration: logically, the loop begins here
3853 even though the exit code has been duplicated.
3855 Insns are also again known to be executed each iteration at
3856 the LOOP_CONT note. */
3862 loop_depth++;
3864 loop_depth--;
3865 }
3867 /* Note if we pass a loop latch. If we do, then we can not clear
3868 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3869 a loop since a jump before the last CODE_LABEL may have started
3870 a new loop iteration.
3872 Note that LOOP_TOP is only set for rotated loops and we need
3873 this check for all loops, so compare against the CODE_LABEL
3874 which immediately follows LOOP_START. */
3878 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3879 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3880 or not an insn is known to be executed each iteration of the
3881 loop, whether or not any iterations are known to occur.
3883 Therefore, if we have just passed a label and have no more labels
3884 between here and the test insn of the loop, and we have not passed
3885 a jump to the top of the loop, then we know these insns will be
3886 executed each iteration. */
3889 && ! past_loop_latch
3894 }
3896 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3897 Make a sanity check against n_times_set. */
3899 {
3901 /* Above happens if register modified by subreg, etc. */
3902 /* Make sure it is not recognized as a basic induction var: */
3904 /* If never incremented, it is invariant that we decided not to
3905 move. So leave it alone. */
3907 {
3918 }
3919 else
3920 {
3925 }
3926 }
3928 /* Exit if there are no bivs. */
3930 {
3931 /* Can still unroll the loop anyways, but indicate that there is no
3932 strength reduction info available. */
3938 }
3940 /* Find initial value for each biv by searching backwards from loop_start,
3941 halting at first label. Also record any test condition. */
3945 {
3955 /* Record any test of a biv that branches around the loop if no store
3956 between it and the start of loop. We only care about tests with
3957 constants and registers and only certain of those. */
3967 {
3968 /* If an NE test, we have an initial value! */
3970 {
3974 }
3975 else
3977 }
3978 }
3980 /* Look at the each biv and see if we can say anything better about its
3981 initial value from any initializing insns set up above. (This is done
3982 in two passes to avoid missing SETs in a PARALLEL.) */
3984 {
3985 rtx src;
3986 rtx note;
3991 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3992 is a constant, use the value of that. */
3998 else
4009 {
4013 {
4015 {
4018 }
4019 else
4020 {
4023 }
4024 }
4025 }
4026 else
4027 {
4031 /* Biv initial value is not a simple move. If it is the sum of
4032 another biv and a constant, check if both bivs are incremented
4033 in lockstep. Then we are actually looking at a giv.
4034 For simplicity, we only handle the case where there is but a
4035 single increment, and the register is not used elsewhere. */
4044 {
4050 }
4052 /* Now, can we transform this biv into a giv? */
4057 /* init_insn is only set to insns that are before loop_start
4058 without any intervening labels. */
4061 /* The register from BL2 must be set before the register from
4062 BL is set, or we must be able to move the latter set after
4063 the former set. Currently there can't be any labels
4064 in-between when biv_total_increment returns nonzero both times
4065 but we test it here in case some day some real cfg analysis
4066 gets used to set always_computable. */
4075 {
4084 /* Let this giv be discovered by the generic code. */
4087 /* We can get better optimization if we can move the giv setting
4088 before the first giv use. */
4092 dominator)
4095 {
4096 rtx p;
4097 rtx next;
4100 {
4106 #ifdef HAVE_cc0
4109 #endif
4111 }
4115 /* Avoid problems with luids by actually moving the insn
4116 and adjusting all luids in the range. */
4121 /* If the only purpose of the init insn is to initialize
4122 this giv, delete it. */
4126 }
4128 {
4135 }
4136 /* Remove this biv from the chain. */
4138 {
4139 /* We move the following giv from *bl->next into *bl.
4140 We have to update reg_biv_class for that moved biv
4141 to point to its new address. */
4144 }
4145 else
4146 {
4149 }
4150 }
4152 /* If we can't make it a giv,
4153 let biv keep initial value of "itself". */
4156 }
4157 }
4159 /* If a biv is unconditionally incremented several times in a row, convert
4160 all but the last increment into a giv. */
4162 /* Get an upper bound for the number of registers
4163 we might have after all bivs have been processed. */
4168 /* If the loop contains volatile memory references do not allow any
4169 replacements to take place, since this could loose the volatile markers. */
4171 {
4174 /* Reallocate reg_iv_type and reg_iv_info. */
4179 {
4183 /* The biv increments lists are in reverse order. Fix this first. */
4185 {
4189 }
4191 /* We must guard against the case that an early exit between v->insn
4192 and next->insn leaves the biv live after the loop, since that
4193 would mean that we'd be missing an increment for the final
4194 value. The following test to set biv_dead_after_loop is like
4195 the first part of the test to set bl->eliminable.
4196 We don't check here if we can calculate the final value, since
4197 this can't succeed if we already know that there is a jump
4198 between v->insn and next->insn, yet next->always_executed is
4199 set and next->maybe_multiple is cleared. Such a combination
4200 implies that the jump destination is outside the loop.
4201 If we want to make this check more sophisticated, we should
4202 check each branch between v->insn and next->insn individually
4203 to see if the biv is dead at its destination. */
4210 #ifdef HAVE_decrement_and_branch_until_zero
4212 #endif
4217 {
4218 HOST_WIDE_INT offset;
4230 || ! (biv_dead_after_loop
4232 {
4235 }
4242 /* Unlike reg_iv_type / reg_iv_info, the other three arrays
4243 have been allocated with some slop space, so we may not
4244 actually need to reallocate them. If we do, the following
4245 if statement will be executed just once in this loop. */
4247 {
4248 /* Grow all the remaining arrays. */
4253 }
4256 {
4259 }
4261 /* Here we can try to eliminate the increment by combining
4262 it into the uses. */
4264 /* Set last_use_insn so that we can check against it. */
4269 {
4273 {
4275 }
4276 }
4278 /* If we can't get the LUIDs for the insns, we can't
4279 calculate the lifetime. This is likely from unrolling
4280 of an inner loop, so there is little point in making this
4281 a DEST_REG giv anyways. */
4285 {
4286 /* Change the increment at NEXT back to what it was. */
4292 }
4326 /* If next_insn has a REG_EQUAL note that mentiones OLD_REG,
4327 it must be replaced. */
4332 /* Remove the increment from the list of biv increments,
4333 and record it as a giv. */
4342 /* Now replace the biv with DEST_REG in all insns between
4343 the replaced increment and the next increment, and
4344 remember the last insn that needed a replacement. */
4348 {
4349 rtx note;
4354 {
4358 }
4360 {
4364 }
4365 }
4369 /* If the lifetime is zero, it means that this register is really
4370 a dead store. So mark this as a giv that can be ignored.
4371 This will not prevent the biv from being eliminated. */
4379 }
4380 }
4381 }
4384 /* Search the loop for general induction variables. */
4386 /* A register is a giv if: it is only set once, it is a function of a
4387 biv and a constant (or invariant), and it is not a biv. */
4394 {
4396 /* At end of a straight-in loop, we are done.
4397 At end of a loop entered at the bottom, scan the top. */
4401 {
4404 else
4408 }
4410 /* Look for a general induction variable in a register. */
4415 {
4416 rtx src_reg;
4417 rtx add_val;
4418 rtx mult_val;
4421 rtx last_consec_insn;
4430 /* Equivalent expression is a giv. */
4435 /* Don't try to handle any regs made by loop optimization.
4436 We have nothing on them in regno_first_uid, etc. */
4438 /* Don't recognize a BASIC_INDUCT_VAR here. */
4440 /* This must be the only place where the register is set. */
4442 /* or all sets must be consecutive and make a giv. */
4447 {
4451 /* If this is a library call, increase benefit. */
4455 /* Skip the consecutive insns, if there are any. */
4463 }
4464 }
4466 #ifndef DONT_REDUCE_ADDR
4467 /* Look for givs which are memory addresses. */
4468 /* This resulted in worse code on a VAX 8600. I wonder if it
4469 still does. */
4473 #endif
4475 /* Update the status of whether giv can derive other givs. This can
4476 change when we pass a label or an insn that updates a biv. */
4481 /* Past CODE_LABEL, we get to insns that may be executed multiple
4482 times. The only way we can be sure that they can't is if every
4483 every jump insn between here and the end of the loop either
4484 returns, exits the loop, is a forward jump, or is a jump
4485 to the loop start. */
4488 {
4494 {
4499 {
4502 else
4506 }
4517 {
4520 }
4521 }
4522 }
4524 /* Past a jump, we get to insns for which we can't count
4525 on whether they will be executed during each iteration. */
4526 /* This code appears twice in strength_reduce. There is also similar
4527 code in scan_loop. */
4529 /* If we enter the loop in the middle, and scan around to the
4530 beginning, don't set not_every_iteration for that.
4531 This can be any kind of jump, since we want to know if insns
4532 will be executed if the loop is executed. */
4536 {
4539 /* If this is a jump outside the loop, then it also doesn't
4540 matter. Check to see if the target of this branch is on the
4541 loop_number_exits_labels list. */
4544 label;
4551 }
4554 {
4555 /* At the virtual top of a converted loop, insns are again known to
4556 be executed each iteration: logically, the loop begins here
4557 even though the exit code has been duplicated.
4559 Insns are also again known to be executed each iteration at
4560 the LOOP_CONT note. */
4566 loop_depth++;
4568 loop_depth--;
4569 }
4571 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4572 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4573 or not an insn is known to be executed each iteration of the
4574 loop, whether or not any iterations are known to occur.
4576 Therefore, if we have just passed a label and have no more labels
4577 between here and the test insn of the loop, we know these insns
4578 will be executed each iteration. */
4584 }
4586 /* Try to calculate and save the number of loop iterations. This is
4587 set to zero if the actual number can not be calculated. This must
4588 be called after all giv's have been identified, since otherwise it may
4589 fail if the iteration variable is a giv. */
4593 /* Now for each giv for which we still don't know whether or not it is
4594 replaceable, check to see if it is replaceable because its final value
4595 can be calculated. This must be done after loop_iterations is called,
4596 so that final_giv_value will work correctly. */
4599 {
4605 }
4607 /* Try to prove that the loop counter variable (if any) is always
4608 nonnegative; if so, record that fact with a REG_NONNEG note
4609 so that "decrement and branch until zero" insn can be used. */
4612 /* Create reg_map to hold substitutions for replaceable giv regs.
4613 Some givs might have been made from biv increments, so look at
4614 reg_iv_type for a suitable size. */
4619 /* Examine each iv class for feasibility of strength reduction/induction
4620 variable elimination. */
4623 {
4630 /* Test whether it will be possible to eliminate this biv
4631 provided all givs are reduced. This is possible if either
4632 the reg is not used outside the loop, or we can compute
4633 what its final value will be.
4635 For architectures with a decrement_and_branch_until_zero insn,
4636 don't do this if we put a REG_NONNEG note on the endtest for
4637 this biv. */
4639 /* Compare against bl->init_insn rather than loop_start.
4640 We aren't concerned with any uses of the biv between
4641 init_insn and loop_start since these won't be affected
4642 by the value of the biv elsewhere in the function, so
4643 long as init_insn doesn't use the biv itself.
4644 March 14, 1989 -- self@bayes.arc.nasa.gov */
4650 #ifdef HAVE_decrement_and_branch_until_zero
4652 #endif
4656 #ifdef HAVE_decrement_and_branch_until_zero
4658 #endif
4659 ))
4662 else
4663 {
4665 {
4673 }
4674 }
4676 /* Combine all giv's for this iv_class. */
4679 /* This will be true at the end, if all givs which depend on this
4680 biv have been strength reduced.
4681 We can't (currently) eliminate the biv unless this is so. */
4684 /* Check each giv in this class to see if we will benefit by reducing
4685 it. Skip giv's combined with others. */
4687 {
4695 /* Reduce benefit if not replaceable, since we will insert
4696 a move-insn to replace the insn that calculates this giv.
4697 Don't do this unless the giv is a user variable, since it
4698 will often be marked non-replaceable because of the duplication
4699 of the exit code outside the loop. In such a case, the copies
4700 we insert are dead and will be deleted. So they don't have
4701 a cost. Similar situations exist. */
4702 /* ??? The new final_[bg]iv_value code does a much better job
4703 of finding replaceable giv's, and hence this code may no longer
4704 be necessary. */
4709 /* Decrease the benefit to count the add-insns that we will
4710 insert to increment the reduced reg for the giv. */
4713 /* Decide whether to strength-reduce this giv or to leave the code
4714 unchanged (recompute it from the biv each time it is used).
4715 This decision can be made independently for each giv. */
4717 #ifdef AUTO_INC_DEC
4718 /* Attempt to guess whether autoincrement will handle some of the
4719 new add insns; if so, increase BENEFIT (undo the subtraction of
4720 add_cost that was done above). */
4723 {
4736 }
4737 #endif
4739 /* If an insn is not to be strength reduced, then set its ignore
4740 flag, and clear all_reduced. */
4742 /* A giv that depends on a reversed biv must be reduced if it is
4743 used after the loop exit, otherwise, it would have the wrong
4744 value after the loop exit. To make it simple, just reduce all
4745 of such giv's whether or not we know they are used after the loop
4746 exit. */
4750 {
4758 }
4759 else
4760 {
4761 /* Check that we can increment the reduced giv without a
4762 multiply insn. If not, reject it. */
4767 {
4775 }
4776 }
4777 }
4779 /* Check for givs whose first use is their definition and whose
4780 last use is the definition of another giv. If so, it is likely
4781 dead and should not be used to derive another giv nor to
4782 eliminate a biv. */
4784 {
4790 {
4796 }
4799 {
4805 }
4806 }
4808 /* Now that we know which givs will be reduced, try to rearrange the
4809 combinations to reduce register pressure.
4810 recombine_givs calls find_life_end, which needs reg_iv_type and
4811 reg_iv_info to be valid for all pseudos. We do the necessary
4812 reallocation here since it allows to check if there are still
4813 more bivs to process. */
4816 {
4817 /* If there are still more bivs to process, allocate some slack
4818 space so that we're not constantly reallocating these arrays. */
4821 /* Reallocate reg_iv_type and reg_iv_info. */
4824 }
4827 /* Reduce each giv that we decided to reduce. */
4830 {
4833 {
4836 /* If the code for derived givs immediately below has already
4837 allocated a new_reg, we must keep it. */
4842 {
4845 /* In case d->dest_reg is not replaceable, we have
4846 to replace it in v->insn now. */
4853 /* For each place where the biv is incremented, add an
4854 insn to set the new, reduced reg for the giv.
4855 We used to do this only for biv_count != 1, but
4856 this fails when there is a giv after a single biv
4857 increment, e.g. when the last giv was expressed as
4858 pre-decrement. */
4860 {
4861 /* We always emit reduced giv increments before the
4862 biv increment when bl->biv_count != 1. So by
4863 emitting the add insns for derived givs after the
4864 biv increment, they pick up the updated value of
4865 the reduced giv.
4866 If the reduced giv is processed with
4867 auto_inc_opt == 1, then it is incremented earlier
4868 than the biv, hence we'll still pick up the right
4869 value.
4870 If it's processed with auto_inc_opt == -1,
4871 that implies that the biv increment is before the
4872 first reduced giv's use. The derived giv's lifetime
4873 is after the reduced giv's lifetime, hence in this
4874 case, the biv increment doesn't matter. */
4876 }
4878 }
4880 #ifdef AUTO_INC_DEC
4881 /* If the target has auto-increment addressing modes, and
4882 this is an address giv, then try to put the increment
4883 immediately after its use, so that flow can create an
4884 auto-increment addressing mode. */
4887 /* We don't handle reversed biv's because bl->biv->insn
4888 does not have a valid INSN_LUID. */
4892 {
4893 /* If other giv's have been combined with this one, then
4894 this will work only if all uses of the other giv's occur
4895 before this giv's insn. This is difficult to check.
4897 We simplify this by looking for the common case where
4898 there is one DEST_REG giv, and this giv's insn is the
4899 last use of the dest_reg of that DEST_REG giv. If the
4900 increment occurs after the address giv, then we can
4901 perform the optimization. (Otherwise, the increment
4902 would have to go before other_giv, and we would not be
4903 able to combine it with the address giv to get an
4904 auto-inc address.) */
4906 {
4911 {
4914 else
4916 }
4923 }
4924 /* Check for case where increment is before the address
4925 giv. Do this test in "loop order". */
4934 else
4937 #ifdef HAVE_cc0
4938 {
4939 rtx prev;
4941 /* We can't put an insn immediately after one setting
4942 cc0, or immediately before one using cc0. */
4949 }
4950 #endif
4954 }
4955 #endif
4957 /* For each place where the biv is incremented, add an insn
4958 to increment the new, reduced reg for the giv. */
4960 {
4961 rtx insert_before;
4967 else
4974 /* A multiply is acceptable here
4975 since this is presumed to be seldom executed. */
4978 }
4980 /* Add code at loop start to initialize giv's reduced reg. */
4984 }
4985 }
4987 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4988 as not reduced.
4990 For each giv register that can be reduced now: if replaceable,
4991 substitute reduced reg wherever the old giv occurs;
4992 else add new move insn "giv_reg = reduced_reg". */
4995 {
5002 /* Update expression if this was combined, in case other giv was
5003 replaced. */
5009 /* Store reduced reg as the address in the memref where we found
5010 this giv. */
5013 {
5016 #if 0
5017 /* I can no longer duplicate the original problem. Perhaps
5018 this is unnecessary now? */
5020 /* Replaceable; it isn't strictly necessary to delete the old
5021 insn and emit a new one, because v->dest_reg is now dead.
5023 However, especially when unrolling loops, the special
5024 handling for (set REG0 REG1) in the second cse pass may
5025 make v->dest_reg live again. To avoid this problem, emit
5026 an insn to set the original giv reg from the reduced giv.
5027 We can not delete the original insn, since it may be part
5028 of a LIBCALL, and the code in flow that eliminates dead
5029 libcalls will fail if it is deleted. */
5032 #endif
5033 }
5034 else
5035 {
5036 /* Not replaceable; emit an insn to set the original giv reg from
5037 the reduced giv, same as above. */
5040 }
5042 /* When a loop is reversed, givs which depend on the reversed
5043 biv, and which are live outside the loop, must be set to their
5044 correct final value. This insn is only needed if the giv is
5045 not replaceable. The correct final value is the same as the
5046 value that the giv starts the reversed loop with. */
5051 {
5052 rtx insert_before;
5054 /* If the loop has multiple exits, emit the insn before the
5055 loop to ensure that it will always be executed no matter
5056 how the loop exits. Otherwise, emit the insn after the loop,
5057 since this is slightly more efficient. */
5060 else
5063 insert_before);
5065 #if 0
5066 /* If the insn to set the final value of the giv was emitted
5067 before the loop, then we must delete the insn inside the loop
5068 that sets it. If this is a LIBCALL, then we must delete
5069 every insn in the libcall. Note, however, that
5070 final_giv_value will only succeed when there are multiple
5071 exits if the giv is dead at each exit, hence it does not
5072 matter that the original insn remains because it is dead
5073 anyways. */
5074 /* Delete the insn inside the loop that sets the giv since
5075 the giv is now set before (or after) the loop. */
5077 #endif
5078 }
5081 {
5086 }
5087 }
5089 /* All the givs based on the biv bl have been reduced if they
5090 merit it. */
5092 /* For each giv not marked as maybe dead that has been combined with a
5093 second giv, clear any "maybe dead" mark on that second giv.
5094 v->new_reg will either be or refer to the register of the giv it
5095 combined with.
5097 Doing this clearing avoids problems in biv elimination where a
5098 giv's new_reg is a complex value that can't be put in the insn but
5099 the giv combined with (with a reg as new_reg) is marked maybe_dead.
5100 Since the register will be used in either case, we'd prefer it be
5101 used from the simpler giv. */
5107 /* Try to eliminate the biv, if it is a candidate.
5108 This won't work if ! all_reduced,
5109 since the givs we planned to use might not have been reduced.
5111 We have to be careful that we didn't initially think we could eliminate
5112 this biv because of a giv that we now think may be dead and shouldn't
5113 be used as a biv replacement.
5115 Also, there is the possibility that we may have a giv that looks
5116 like it can be used to eliminate a biv, but the resulting insn
5117 isn't valid. This can happen, for example, on the 88k, where a
5118 JUMP_INSN can compare a register only with zero. Attempts to
5119 replace it with a compare with a constant will fail.
5121 Note that in cases where this call fails, we may have replaced some
5122 of the occurrences of the biv with a giv, but no harm was done in
5123 doing so in the rare cases where it can occur. */
5129 {
5130 /* ?? If we created a new test to bypass the loop entirely,
5131 or otherwise drop straight in, based on this test, then
5132 we might want to rewrite it also. This way some later
5133 pass has more hope of removing the initialization of this
5134 biv entirely. */
5136 /* If final_value != 0, then the biv may be used after loop end
5137 and we must emit an insn to set it just in case.
5139 Reversed bivs already have an insn after the loop setting their
5140 value, so we don't need another one. We can't calculate the
5141 proper final value for such a biv here anyways. */
5143 {
5144 rtx insert_before;
5146 /* If the loop has multiple exits, emit the insn before the
5147 loop to ensure that it will always be executed no matter
5148 how the loop exits. Otherwise, emit the insn after the
5149 loop, since this is slightly more efficient. */
5152 else
5156 end_insert_before);
5157 }
5159 #if 0
5160 /* Delete all of the instructions inside the loop which set
5161 the biv, as they are all dead. If is safe to delete them,
5162 because an insn setting a biv will never be part of a libcall. */
5163 /* However, deleting them will invalidate the regno_last_uid info,
5164 so keeping them around is more convenient. Final_biv_value
5165 will only succeed when there are multiple exits if the biv
5166 is dead at each exit, hence it does not matter that the original
5167 insn remains, because it is dead anyways. */
5170 #endif
5175 }
5176 }
5178 /* Go through all the instructions in the loop, making all the
5179 register substitutions scheduled in REG_MAP. */
5184 {
5188 }
5191 {
5192 /* When we completely unroll a loop we will likely not need the increment
5193 of the loop BIV and we will not need the conditional branch at the
5194 end of the loop. */
5197 #ifdef HAVE_cc0
5198 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5199 need the comparison before the conditional branch at the end of the
5200 loop. */
5202 #endif
5204 /* We'll need one copy for each loop iteration. */
5207 /* A little slop to account for the ability to remove initialization
5208 code, better CSE, and other secondary benefits of completely
5209 unrolling some loops. */
5212 /* Clamp the value. */
5215 }
5217 /* Unroll loops from within strength reduction so that we can use the
5218 induction variable information that strength_reduce has already
5219 collected. Always unroll loops that would be as small or smaller
5220 unrolled than when rolled. */
5227 #ifdef HAVE_decrement_and_branch_on_count
5228 /* Instrument the loop with BCT insn. */
5237 egress:
5240 }
5241 \f
5242 /* Return 1 if X is a valid source for an initial value (or as value being
5243 compared against in an initial test).
5245 X must be either a register or constant and must not be clobbered between
5246 the current insn and the start of the loop.
5248 INSN is the insn containing X. */
5250 static int
5252 rtx x;
5253 rtx insn;
5255 rtx loop_start;
5256 {
5260 /* Only consider pseudos we know about initialized in insns whose luids
5261 we know. */
5266 /* Don't use call-clobbered registers across a call which clobbers it. On
5267 some machines, don't use any hard registers at all. */
5269 && (SMALL_REGISTER_CLASSES
5273 /* Don't use registers that have been clobbered before the start of the
5274 loop. */
5279 }
5280 \f
5281 /* Scan X for memory refs and check each memory address
5282 as a possible giv. INSN is the insn whose pattern X comes from.
5283 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5284 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5285 more thanonce in each loop iteration. */
5287 static void
5289 loop_end)
5290 rtx x;
5291 rtx insn;
5294 {
5304 {
5320 {
5321 rtx src_reg;
5322 rtx add_val;
5323 rtx mult_val;
5326 /* This code used to disable creating GIVs with mult_val == 1 and
5327 add_val == 0. However, this leads to lost optimizations when
5328 it comes time to combine a set of related DEST_ADDR GIVs, since
5329 this one would not be seen. */
5333 {
5334 /* Found one; record it. */
5343 }
5344 }
5349 }
5351 /* Recursively scan the subexpressions for other mem refs. */
5362 }
5363 \f
5364 /* Fill in the data about one biv update.
5365 V is the `struct induction' in which we record the biv. (It is
5366 allocated by the caller, with alloca.)
5367 INSN is the insn that sets it.
5368 DEST_REG is the biv's reg.
5370 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5371 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5372 being set to INC_VAL.
5374 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5375 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5376 can be executed more than once per iteration. If MAYBE_MULTIPLE
5377 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5378 executed exactly once per iteration. */
5380 static void
5384 rtx insn;
5385 rtx dest_reg;
5386 rtx inc_val;
5387 rtx mult_val;
5391 {
5405 /* Add this to the reg's iv_class, creating a class
5406 if this is the first incrementation of the reg. */
5410 {
5411 /* Create and initialize new iv_class. */
5421 /* Set initial value to the reg itself. */
5423 /* We haven't seen the initializing insn yet */
5433 /* Add this class to loop_iv_list. */
5437 /* Put it in the array of biv register classes. */
5439 }
5441 /* Update IV_CLASS entry for this biv. */
5449 {
5454 {
5458 }
5459 else
5460 {
5464 }
5465 }
5466 }
5467 \f
5468 /* Fill in the data about one giv.
5469 V is the `struct induction' in which we record the giv. (It is
5470 allocated by the caller, with alloca.)
5471 INSN is the insn that sets it.
5472 BENEFIT estimates the savings from deleting this insn.
5473 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5474 into a register or is used as a memory address.
5476 SRC_REG is the biv reg which the giv is computed from.
5477 DEST_REG is the giv's reg (if the giv is stored in a reg).
5478 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5479 LOCATION points to the place where this giv's value appears in INSN. */
5481 static void
5484 loop_end)
5486 rtx insn;
5487 rtx src_reg;
5488 rtx dest_reg;
5495 {
5524 /* The v->always_computable field is used in update_giv_derive, to
5525 determine whether a giv can be used to derive another giv. For a
5526 DEST_REG giv, INSN computes a new value for the giv, so its value
5527 isn't computable if INSN insn't executed every iteration.
5528 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5529 it does not compute a new value. Hence the value is always computable
5530 regardless of whether INSN is executed each iteration. */
5534 else
5540 {
5543 }
5545 {
5551 /* If the lifetime is zero, it means that this register is
5552 really a dead store. So mark this as a giv that can be
5553 ignored. This will not prevent the biv from being eliminated. */
5559 }
5561 /* Add the giv to the class of givs computed from one biv. */
5565 {
5568 /* Don't count DEST_ADDR. This is supposed to count the number of
5569 insns that calculate givs. */
5573 }
5574 else
5575 /* Fatal error, biv missing for this giv? */
5580 else
5581 {
5582 /* The giv can be replaced outright by the reduced register only if all
5583 of the following conditions are true:
5584 - the insn that sets the giv is always executed on any iteration
5585 on which the giv is used at all
5586 (there are two ways to deduce this:
5587 either the insn is executed on every iteration,
5588 or all uses follow that insn in the same basic block),
5589 - the giv is not used outside the loop
5590 - no assignments to the biv occur during the giv's lifetime. */
5593 /* Previous line always fails if INSN was moved by loop opt. */
5595 && (! not_every_iteration
5597 {
5598 /* Now check that there are no assignments to the biv within the
5599 giv's lifetime. This requires two separate checks. */
5601 /* Check each biv update, and fail if any are between the first
5602 and last use of the giv.
5604 If this loop contains an inner loop that was unrolled, then
5605 the insn modifying the biv may have been emitted by the loop
5606 unrolling code, and hence does not have a valid luid. Just
5607 mark the biv as not replaceable in this case. It is not very
5608 useful as a biv, because it is used in two different loops.
5609 It is very unlikely that we would be able to optimize the giv
5610 using this biv anyways. */
5614 {
5620 {
5624 }
5625 }
5627 /* If there are any backwards branches that go from after the
5628 biv update to before it, then this giv is not replaceable. */
5632 {
5636 }
5637 }
5638 else
5639 {
5640 /* May still be replaceable, we don't have enough info here to
5641 decide. */
5644 }
5645 }
5647 /* Record whether the add_val contains a const_int, for later use by
5648 combine_givs. */
5649 {
5654 ;
5658 {
5660 {
5665 else
5667 }
5670 }
5671 }
5674 {
5678 else
5694 {
5697 }
5698 else
5699 {
5702 }
5705 {
5708 }
5709 else
5710 {
5713 }
5714 }
5719 }
5722 /* All this does is determine whether a giv can be made replaceable because
5723 its final value can be calculated. This code can not be part of record_giv
5724 above, because final_giv_value requires that the number of loop iterations
5725 be known, and that can not be accurately calculated until after all givs
5726 have been identified. */
5728 static void
5733 {
5739 /* DEST_ADDR givs will never reach here, because they are always marked
5740 replaceable above in record_giv. */
5742 /* The giv can be replaced outright by the reduced register only if all
5743 of the following conditions are true:
5744 - the insn that sets the giv is always executed on any iteration
5745 on which the giv is used at all
5746 (there are two ways to deduce this:
5747 either the insn is executed on every iteration,
5748 or all uses follow that insn in the same basic block),
5749 - its final value can be calculated (this condition is different
5750 than the one above in record_giv)
5751 - no assignments to the biv occur during the giv's lifetime. */
5753 #if 0
5754 /* This is only called now when replaceable is known to be false. */
5755 /* Clear replaceable, so that it won't confuse final_giv_value. */
5757 #endif
5761 {
5764 rtx last_giv_use;
5768 /* When trying to determine whether or not a biv increment occurs
5769 during the lifetime of the giv, we can ignore uses of the variable
5770 outside the loop because final_value is true. Hence we can not
5771 use regno_last_uid and regno_first_uid as above in record_giv. */
5773 /* Search the loop to determine whether any assignments to the
5774 biv occur during the giv's lifetime. Start with the insn
5775 that sets the giv, and search around the loop until we come
5776 back to that insn again.
5778 Also fail if there is a jump within the giv's lifetime that jumps
5779 to somewhere outside the lifetime but still within the loop. This
5780 catches spaghetti code where the execution order is not linear, and
5781 hence the above test fails. Here we assume that the giv lifetime
5782 does not extend from one iteration of the loop to the next, so as
5783 to make the test easier. Since the lifetime isn't known yet,
5784 this requires two loops. See also record_giv above. */
5789 {
5798 {
5800 {
5802 {
5806 }
5807 }
5812 }
5813 }
5815 /* Now that the lifetime of the giv is known, check for branches
5816 from within the lifetime to outside the lifetime if it is still
5817 replaceable. */
5820 {
5823 {
5836 {
5845 }
5846 }
5847 }
5849 /* If it is replaceable, then save the final value. */
5852 }
5857 }
5858 \f
5859 /* Update the status of whether a giv can derive other givs.
5861 We need to do something special if there is or may be an update to the biv
5862 between the time the giv is defined and the time it is used to derive
5863 another giv.
5865 In addition, a giv that is only conditionally set is not allowed to
5866 derive another giv once a label has been passed.
5868 The cases we look at are when a label or an update to a biv is passed. */
5870 static void
5872 rtx p;
5873 {
5876 rtx tem;
5879 /* Search all IV classes, then all bivs, and finally all givs.
5881 There are three cases we are concerned with. First we have the situation
5882 of a giv that is only updated conditionally. In that case, it may not
5883 derive any givs after a label is passed.
5885 The second case is when a biv update occurs, or may occur, after the
5886 definition of a giv. For certain biv updates (see below) that are
5887 known to occur between the giv definition and use, we can adjust the
5888 giv definition. For others, or when the biv update is conditional,
5889 we must prevent the giv from deriving any other givs. There are two
5890 sub-cases within this case.
5892 If this is a label, we are concerned with any biv update that is done
5893 conditionally, since it may be done after the giv is defined followed by
5894 a branch here (actually, we need to pass both a jump and a label, but
5895 this extra tracking doesn't seem worth it).
5897 If this is a jump, we are concerned about any biv update that may be
5898 executed multiple times. We are actually only concerned about
5899 backward jumps, but it is probably not worth performing the test
5900 on the jump again here.
5902 If this is a biv update, we must adjust the giv status to show that a
5903 subsequent biv update was performed. If this adjustment cannot be done,
5904 the giv cannot derive further givs. */
5910 {
5912 {
5913 /* If cant_derive is already true, there is no point in
5914 checking all of these conditions again. */
5918 /* If this giv is conditionally set and we have passed a label,
5919 it cannot derive anything. */
5923 /* Skip givs that have mult_val == 0, since
5924 they are really invariants. Also skip those that are
5925 replaceable, since we know their lifetime doesn't contain
5926 any biv update. */
5930 /* The only way we can allow this giv to derive another
5931 is if this is a biv increment and we can form the product
5932 of biv->add_val and giv->mult_val. In this case, we will
5933 be able to compute a compensation. */
5935 {
5945 tem = simplify_giv_expr
5951 else
5953 }
5957 }
5958 }
5959 }
5960 \f
5961 /* Check whether an insn is an increment legitimate for a basic induction var.
5962 X is the source of insn P, or a part of it.
5963 MODE is the mode in which X should be interpreted.
5965 DEST_REG is the putative biv, also the destination of the insn.
5966 We accept patterns of these forms:
5967 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5968 REG = INVARIANT + REG
5970 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5971 store the additive term into *INC_VAL, and store the place where
5972 we found the additive term into *LOCATION.
5974 If X is an assignment of an invariant into DEST_REG, we set
5975 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5977 We also want to detect a BIV when it corresponds to a variable
5978 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5979 of the variable may be a PLUS that adds a SUBREG of that variable to
5980 an invariant and then sign- or zero-extends the result of the PLUS
5981 into the variable.
5983 Most GIVs in such cases will be in the promoted mode, since that is the
5984 probably the natural computation mode (and almost certainly the mode
5985 used for addresses) on the machine. So we view the pseudo-reg containing
5986 the variable as the BIV, as if it were simply incremented.
5988 Note that treating the entire pseudo as a BIV will result in making
5989 simple increments to any GIVs based on it. However, if the variable
5990 overflows in its declared mode but not its promoted mode, the result will
5991 be incorrect. This is acceptable if the variable is signed, since
5992 overflows in such cases are undefined, but not if it is unsigned, since
5993 those overflows are defined. So we only check for SIGN_EXTEND and
5994 not ZERO_EXTEND.
5996 If we cannot find a biv, we return 0. */
5998 static int
6002 rtx p;
6003 rtx dest_reg;
6007 {
6015 {
6021 {
6023 }
6028 {
6030 }
6031 else
6044 /* If this is a SUBREG for a promoted variable, check the inner
6045 value. */
6052 /* If this register is assigned in a previous insn, look at its
6053 source, but don't go outside the loop or past a label. */
6057 {
6081 }
6082 /* ... fall through ... */
6084 /* Can accept constant setting of biv only when inside inner most loop.
6085 Otherwise, a biv of an inner loop may be incorrectly recognized
6086 as a biv of the outer loop,
6087 causing code to be moved INTO the inner loop. */
6094 /* convert_modes aborts if we try to convert to or from CCmode, so just
6095 exclude that case. It is very unlikely that a condition code value
6096 would be a useful iterator anyways. */
6100 {
6101 /* Possible bug here? Perhaps we don't know the mode of X. */
6105 }
6106 else
6114 /* Similar, since this can be a sign extension. */
6119 ;
6132 location);
6137 }
6138 }
6139 \f
6140 /* A general induction variable (giv) is any quantity that is a linear
6141 function of a basic induction variable,
6142 i.e. giv = biv * mult_val + add_val.
6143 The coefficients can be any loop invariant quantity.
6144 A giv need not be computed directly from the biv;
6145 it can be computed by way of other givs. */
6147 /* Determine whether X computes a giv.
6148 If it does, return a nonzero value
6149 which is the benefit from eliminating the computation of X;
6150 set *SRC_REG to the register of the biv that it is computed from;
6151 set *ADD_VAL and *MULT_VAL to the coefficients,
6152 such that the value of X is biv * mult + add; */
6154 static int
6156 rtx x;
6162 {
6166 /* If this is an invariant, forget it, it isn't a giv. */
6170 /* See if the expression could be a giv and get its form.
6171 Mark our place on the obstack in case we don't find a giv. */
6176 {
6179 }
6182 {
6185 /* Since this is now an invariant and wasn't before, it must be a giv
6186 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6187 with. */
6194 /* This is equivalent to a BIV. */
6201 /* Either (plus (biv) (invar)) or
6202 (plus (mult (biv) (invar_1)) (invar_2)). */
6204 {
6207 }
6208 else
6209 {
6212 }
6217 /* ADD_VAL is zero. */
6225 }
6227 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6228 unless they are CONST_INT). */
6235 {
6236 #ifdef ADDRESS_COST
6238 #else
6240 #endif
6241 }
6242 else
6245 /* Always return true if this is a giv so it will be detected as such,
6246 even if the benefit is zero or negative. This allows elimination
6247 of bivs that might otherwise not be eliminated. */
6249 }
6250 \f
6251 /* Given an expression, X, try to form it as a linear function of a biv.
6252 We will canonicalize it to be of the form
6253 (plus (mult (BIV) (invar_1))
6254 (invar_2))
6255 with possible degeneracies.
6257 The invariant expressions must each be of a form that can be used as a
6258 machine operand. We surround then with a USE rtx (a hack, but localized
6259 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6260 routine; it is the caller's responsibility to strip them.
6262 If no such canonicalization is possible (i.e., two biv's are used or an
6263 expression that is neither invariant nor a biv or giv), this routine
6264 returns 0.
6266 For a non-zero return, the result will have a code of CONST_INT, USE,
6267 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6269 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6274 static rtx
6276 rtx x;
6278 {
6281 rtx tem;
6283 /* If this is not an integer mode, or if we cannot do arithmetic in this
6284 mode, this can't be a giv. */
6291 {
6298 /* Put constant last, CONST_INT last if both constant. */
6306 /* Handle addition of zero, then addition of an invariant. */
6311 {
6314 /* Adding two invariants must result in an invariant, so enclose
6315 addition operation inside a USE and return it. */
6325 else
6334 /* biv + invar or mult + invar. Return sum. */
6338 /* (a + invar_1) + invar_2. Associate. */
6339 return
6344 arg1)),
6345 benefit);
6349 }
6351 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6352 MULT to reduce cases. */
6358 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6359 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6360 Recurse to associate the second PLUS. */
6365 return
6370 benefit);
6372 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6384 benefit);
6387 /* Handle "a - b" as "a + b * (-1)". */
6392 constm1_rtx)),
6393 benefit);
6401 /* Put constant last, CONST_INT last if both constant. */
6406 /* If second argument is not now constant, not giv. */
6410 /* Handle multiply by 0 or 1. */
6418 {
6420 /* biv * invar. Done. */
6424 /* Product of two constants. */
6428 /* invar * invar. It is a giv, but very few of these will
6429 actually pay off, so limit to simple registers. */
6439 {
6443 }
6444 else
6449 /* (a * invar_1) * invar_2. Associate. */
6454 arg1)),
6455 benefit);
6458 /* (a + invar_1) * invar_2. Distribute. */
6462 arg1),
6465 arg1)),
6466 benefit);
6470 }
6473 /* Shift by constant is multiply by power of two. */
6477 return
6482 benefit);
6485 /* "-a" is "a * (-1)" */
6487 benefit);
6490 /* "~a" is "-a - 1". Silly, but easy. */
6493 const1_rtx),
6494 benefit);
6497 /* Already in proper form for invariant. */
6501 /* If this is a new register, we can't deal with it. */
6505 /* Check for biv or giv. */
6507 {
6511 {
6514 /* Form expression from giv and add benefit. Ensure this giv
6515 can derive another and subtract any needed adjustment if so. */
6527 }
6530 /* If it isn't an induction variable, and it is invariant, we
6531 may be able to simplify things further by looking through
6532 the bits we just moved outside the loop. */
6534 {
6539 {
6540 /* Ok, we found a match. Substitute and simplify. */
6542 /* If we match another movable, we must use that, as
6543 this one is going away. */
6547 /* If consec is non-zero, this is a member of a group of
6548 instructions that were moved together. We handle this
6549 case only to the point of seeking to the last insn and
6550 looking for a REG_EQUAL. Fail if we don't find one. */
6552 {
6560 }
6561 else
6562 {
6566 }
6569 {
6570 /* What we are most interested in is pointer
6571 arithmetic on invariants -- only take
6572 patterns we may be able to do something with. */
6578 {
6582 }
6587 {
6591 }
6592 }
6594 }
6595 }
6597 }
6599 /* Fall through to general case. */
6601 /* If invariant, return as USE (unless CONST_INT).
6602 Otherwise, not giv. */
6607 {
6616 }
6617 else
6619 }
6620 }
6622 /* This routine folds invariants such that there is only ever one
6623 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6625 static rtx
6628 {
6634 {
6637 }
6640 {
6643 }
6644 else
6645 {
6648 }
6649 }
6651 static rtx
6655 {
6657 {
6661 else
6664 }
6667 else
6670 }
6671 \f
6672 /* Help detect a giv that is calculated by several consecutive insns;
6673 for example,
6674 giv = biv * M
6675 giv = giv + A
6676 The caller has already identified the first insn P as having a giv as dest;
6677 we check that all other insns that set the same register follow
6678 immediately after P, that they alter nothing else,
6679 and that the result of the last is still a giv.
6681 The value is 0 if the reg set in P is not really a giv.
6682 Otherwise, the value is the amount gained by eliminating
6683 all the consecutive insns that compute the value.
6685 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6686 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6688 The coefficients of the ultimate giv value are stored in
6689 *MULT_VAL and *ADD_VAL. */
6691 static int
6695 rtx p;
6696 rtx src_reg;
6697 rtx dest_reg;
6701 {
6705 rtx temp;
6706 rtx set;
6708 /* Indicate that this is a giv so that we can update the value produced in
6709 each insn of the multi-insn sequence.
6711 This induction structure will be used only by the call to
6712 general_induction_var below, so we can allocate it on our stack.
6713 If this is a giv, our caller will replace the induct var entry with
6714 a new induction structure. */
6730 {
6734 /* If libcall, skip to end of call sequence. */
6744 /* Giv created by equivalent expression. */
6749 {
6753 count--;
6757 }
6759 {
6760 /* Allow insns that set something other than this giv to a
6761 constant. Such insns are needed on machines which cannot
6762 include long constants and should not disqualify a giv. */
6771 }
6772 }
6776 }
6777 \f
6778 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6779 represented by G1. If no such expression can be found, or it is clear that
6780 it cannot possibly be a valid address, 0 is returned.
6782 To perform the computation, we note that
6783 G1 = x * v + a and
6784 G2 = y * v + b
6785 where `v' is the biv.
6787 So G2 = (y/b) * G1 + (b - a*y/x).
6789 Note that MULT = y/x.
6791 Update: A and B are now allowed to be additive expressions such that
6792 B contains all variables in A. That is, computing B-A will not require
6793 subtracting variables. */
6795 static rtx
6798 {
6799 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6804 /* If MULT is not 1, we cannot handle A with non-constants, since we
6805 would then be required to subtract multiples of the registers in A.
6806 This is theoretically possible, and may even apply to some Fortran
6807 constructs, but it is a lot of work and we do not attempt it here. */
6812 /* In general these structures are sorted top to bottom (down the PLUS
6813 chain), but not left to right across the PLUS. If B is a higher
6814 order giv than A, we can strip one level and recurse. If A is higher
6815 order, we'll eventually bail out, but won't know that until the end.
6816 If they are the same, we'll strip one level around this loop. */
6819 {
6831 /* We matched: remove one reg completely. */
6834 /* An alternate match. */
6837 /* An alternate match. */
6839 else
6840 {
6841 /* Indicates an extra register in B. Strip one level from B and
6842 recurse, hoping B was the higher order expression. */
6847 }
6848 }
6850 /* Here we are at the last level of A, go through the cases hoping to
6851 get rid of everything but a constant. */
6854 {
6867 }
6869 {
6871 }
6873 {
6878 else
6880 }
6885 }
6887 rtx
6890 {
6893 /* The value that G1 will be multiplied by must be a constant integer. Also,
6894 the only chance we have of getting a valid address is if b*c/a (see above
6895 for notation) is also an integer. */
6898 {
6903 }
6906 else
6907 {
6908 /* ??? Find out if the one is a multiple of the other? */
6910 }
6914 {
6915 /* Failed. If we've got a multiplication factor between G1 and G2,
6916 scale G1's addend and try again. */
6918 {
6922 {
6923 HOST_WIDE_INT m;
6927 }
6928 else
6929 {
6931 mult);
6932 }
6935 }
6936 }
6940 /* Form simplified final result. */
6945 else
6950 else
6951 {
6954 {
6958 }
6961 }
6963 }
6964 \f
6965 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6966 represented by G1. This indicates that G2 should be combined with G1 and
6967 that G2 can use (either directly or via an address expression) a register
6968 used to represent G1. */
6970 static rtx
6973 {
6976 /* If these givs are identical, they can be combined. We use the results
6977 of express_from because the addends are not in a canonical form, so
6978 rtx_equal_p is a weaker test. */
6979 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6980 combination to be the other way round. */
6983 {
6985 }
6987 /* If G2 can be expressed as a function of G1 and that function is valid
6988 as an address and no more expensive than using a register for G2,
6989 the expression of G2 in terms of G1 can be used. */
6993 /* ??? Looses, especially with -fforce-addr, where *g2->location
6994 will always be a register, and so anything more complicated
6995 gets discarded. */
6996 #if 0
6997 #ifdef ADDRESS_COST
6999 #else
7001 #endif
7002 #endif
7003 )
7004 {
7006 }
7009 }
7010 \f
7011 struct combine_givs_stats
7012 {
7015 };
7017 static int
7020 {
7023 /* Stabilize the sort. */
7027 }
7029 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7030 any other. If so, point SAME to the giv combined with and set NEW_REG to
7031 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7032 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7034 static void
7037 {
7038 /* Additional benefit to add for being combined multiple times. */
7046 /* Count givs, because bl->giv_count is incorrect here. */
7050 giv_count++;
7052 giv_array
7066 {
7068 rtx single_use;
7073 /* If a DEST_REG GIV is used only once, do not allow it to combine
7074 with anything, for in doing so we will gain nothing that cannot
7075 be had by simply letting the GIV with which we would have combined
7076 to be reduced on its own. The losage shows up in particular with
7077 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7078 be seen elsewhere as well. */
7085 /* Add an additional weight for zero addends. */
7090 {
7091 rtx this_combine;
7096 {
7099 }
7100 }
7102 }
7104 /* Iterate, combining until we can't. */
7105 restart:
7109 {
7112 {
7118 }
7120 }
7123 {
7129 /* If it has already been combined, skip. */
7134 {
7137 /* If it has already been combined, skip. */
7139 {
7149 /* ??? The new final_[bg]iv_value code does a much better job
7150 of finding replaceable giv's, and hence this code may no
7151 longer be necessary. */
7155 /* To help optimize the next set of combinations, remove
7156 this giv from the benefits of other potential mates. */
7158 {
7162 }
7168 }
7169 }
7171 /* To help optimize the next set of combinations, remove
7172 this giv from the benefits of other potential mates. */
7174 {
7176 {
7180 }
7184 /* We've finished with this giv, and everything it touched.
7185 Restart the combination so that proper weights for the
7186 rest of the givs are properly taken into account. */
7187 /* ??? Ideally we would compact the arrays at this point, so
7188 as to not cover old ground. But sanely compacting
7189 can_combine is tricky. */
7191 }
7192 }
7193 }
7194 \f
7195 struct recombine_givs_stats
7196 {
7199 };
7201 /* Used below as comparison function for qsort. We want a ascending luid
7202 when scanning the array starting at the end, thus the arguments are
7203 used in reverse. */
7204 static int
7207 {
7210 /* Stabilize the sort. */
7214 }
7216 /* Scan X, which is a part of INSN, for the end of life of a giv. Also
7217 look for the start of life of a giv where the start has not been seen
7218 yet to unlock the search for the end of its life.
7219 Only consider givs that belong to BIV.
7220 Return the total number of lifetime ends that have been found. */
7221 static int
7225 {
7233 {
7235 {
7238 {
7246 {
7247 /* If we see a 0 here for end_luid, it means that we have
7248 scanned the entire loop without finding any use at all.
7249 We must not predicate this code on a start_luid match
7250 since that would make the test fail for givs that have
7251 been hoisted out of inner loops. */
7253 {
7256 }
7259 }
7261 }
7263 }
7265 {
7273 {
7278 }
7280 }
7288 }
7292 {
7299 }
7301 }
7303 /* For each giv that has been combined with another, look if
7304 we can combine it with the most recently used one instead.
7305 This tends to shorten giv lifetimes, and helps the next step:
7306 try to derive givs from other givs. */
7307 static void
7312 {
7320 {
7322 giv_count++;
7323 }
7324 giv_array
7328 /* Initialize stats and set up the ix field for each giv in stats to name
7329 the corresponding index into stats. */
7331 {
7332 rtx p;
7338 /* If this giv has been hoisted out of an inner loop, use the luid of
7339 the previous insn. */
7343 i++;
7344 }
7348 /* Set up the ix field for each giv in stats to name
7349 the corresponding index into stats, and
7350 do the actual most-recently-used recombination. */
7352 {
7356 {
7358 rtx new_combine;
7360 /* combine_givs_p actually says if we can make this transformation.
7361 The other tests are here only to avoid keeping a giv alive
7362 that could otherwise be eliminated. */
7368 {
7373 /* No need to update lifetimes / benefits here since we have
7374 already decided what to reduce. */
7377 {
7383 }
7385 }
7387 }
7395 }
7398 /* For each DEST_REG giv, compute lifetime starts, and try to compute
7399 lifetime ends from regscan info. */
7401 {
7406 {
7407 /* Loop unrolling of an inner loop can even create new DEST_REG
7408 givs. */
7409 rtx p;
7415 }
7417 {
7419 {
7422 }
7424 {
7425 rtx p;
7426 /* This insn has been created by loop optimization on an inner
7427 loop. We don't have a proper start_luid that will match
7428 when we see the first set. But we do know that there will
7429 be no use before the set, so we can set end_luid to 0 so that
7430 we'll start looking for the last use right away. */
7435 ends_need_computing++;
7436 }
7437 else
7438 {
7443 /* Find the first insn that sets the giv, so that we can verify
7444 if this giv's lifetime wraps around the loop. We also need
7445 the luid of the first setting insn in order to detect the
7446 last use properly. */
7448 {
7451 count--;
7452 }
7456 {
7458 ends_need_computing++;
7459 }
7460 else
7461 {
7464 {
7466 ends_need_computing++;
7467 }
7468 }
7469 }
7470 }
7471 }
7473 /* If the regscan information was unconclusive for one or more DEST_REG
7474 givs, scan the all insn in the loop to find out lifetime ends. */
7476 {
7480 do
7481 {
7488 }
7490 }
7492 /* Set start_luid back to the last insn that sets the giv. This allows
7493 more combinations. */
7495 {
7501 }
7503 /* Now adjust lifetime ends by taking combined givs into account. */
7505 {
7513 {
7516 /* Use unsigned arithmetic to model loop wrap-around. */
7520 }
7521 }
7525 /* Try to derive DEST_REG givs from previous DEST_REG givs with the
7526 same mult_val and non-overlapping lifetime. This reduces register
7527 pressure.
7528 Once we find a DEST_REG giv that is suitable to derive others from,
7529 we set last_giv to this giv, and try to derive as many other DEST_REG
7530 givs from it without joining overlapping lifetimes. If we then
7531 encounter a DEST_REG giv that we can't derive, we set rescan to the
7532 index for this giv (unless rescan is already set).
7533 When we are finished with the current LAST_GIV (i.e. the inner loop
7534 terminates), we start again with rescan, which then becomes the new
7535 LAST_GIV. */
7537 {
7541 {
7542 rtx sum;
7548 {
7549 /* Don't use a giv that's likely to be dead to derive
7550 others - that would be likely to keep that giv alive. */
7552 {
7556 }
7558 }
7559 /* Use unsigned arithmetic to model loop wrap around. */
7564 /* Check that the giv insn we're about to use for deriving
7565 precedes all uses of that giv. Note that initializing the
7566 derived giv would defeat the purpose of reducing register
7567 pressure.
7568 ??? We could arrange to move the insn. */
7572 /* ??? Could handle libcalls, but would need more logic. */
7574 /* We would really like to know if for any giv that v
7575 is combined with, v->insn or any intervening biv increment
7576 dominates that combined giv. However, we
7577 don't have this detailed control flow information.
7578 N.B. since last_giv will be reduced, it is valid
7579 anywhere in the loop, so we don't need to check the
7580 validity of last_giv.
7581 We rely here on the fact that v->always_executed implies that
7582 there is no jump to someplace else in the loop before the
7583 giv insn, and hence any insn that is executed before the
7584 giv insn in the loop will have a lower luid. */
7587 /* Make sure we don't make the add more expensive. ADD_COST
7588 doesn't take different costs of registers and constants into
7589 account, so compare the cost of the actual SET_SRCs. */
7592 /* ??? unroll can't understand anything but reg + const_int
7593 sums. It would be cleaner to fix unroll. */
7600 {
7605 {
7611 }
7612 }
7615 }
7616 }
7617 }
7618 \f
7619 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
7621 void
7627 rtx insert_before;
7628 {
7629 rtx seq;
7630 rtx result;
7632 /* Prevent unexpected sharing of these rtx. */
7636 /* Increase the lifetime of any invariants moved further in code. */
7650 /* It is entirely possible that the expansion created lots of new
7651 registers. Iterate over the sequence we just created and
7652 record them all. */
7655 {
7658 {
7662 }
7663 }
7667 }
7668 \f
7669 /* Test whether A * B can be computed without
7670 an actual multiply insn. Value is 1 if so. */
7672 static int
7674 rtx a;
7675 rtx b;
7676 {
7678 rtx tmp;
7683 /* If only one is constant, make it B. */
7687 /* If first constant, both constant, so don't need multiply. */
7691 /* If second not constant, neither is constant, so would need multiply. */
7695 /* One operand is constant, so might not need multiply insn. Generate the
7696 code for the multiply and see if a call or multiply, or long sequence
7697 of insns is generated. */
7706 {
7711 else
7713 {
7722 {
7725 }
7726 }
7727 }
7736 /* Free any storage we obtained in generating this multiply and restore rtl
7737 allocation to its normal obstack. */
7742 }
7743 \f
7744 /* Check to see if loop can be terminated by a "decrement and branch until
7745 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7746 Also try reversing an increment loop to a decrement loop
7747 to see if the optimization can be performed.
7748 Value is nonzero if optimization was performed. */
7750 /* This is useful even if the architecture doesn't have such an insn,
7751 because it might change a loops which increments from 0 to n to a loop
7752 which decrements from n to 0. A loop that decrements to zero is usually
7753 faster than one that increments from zero. */
7755 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7756 such as approx_final_value, biv_total_increment, loop_iterations, and
7757 final_[bg]iv_value. */
7759 static int
7761 rtx loop_end;
7763 rtx loop_start;
7765 {
7767 rtx reg;
7768 rtx jump_label;
7769 rtx final_value;
7770 rtx start_value;
7771 rtx new_add_val;
7772 rtx comparison;
7773 rtx before_comparison;
7774 rtx p;
7775 rtx jump;
7776 rtx first_compare;
7779 /* If last insn is a conditional branch, and the insn before tests a
7780 register value, try to optimize it. Otherwise, we can't do anything. */
7787 /* Try to compute whether the compare/branch at the loop end is one or
7788 two instructions. */
7794 else
7797 /* Check all of the bivs to see if the compare uses one of them.
7798 Skip biv's set more than once because we can't guarantee that
7799 it will be zero on the last iteration. Also skip if the biv is
7800 used between its update and the test insn. */
7803 {
7807 first_compare))
7809 }
7814 /* Look for the case where the basic induction variable is always
7815 nonnegative, and equals zero on the last iteration.
7816 In this case, add a reg_note REG_NONNEG, which allows the
7817 m68k DBRA instruction to be used. */
7825 {
7826 /* Initial value must be greater than 0,
7827 init_val % -dec_value == 0 to ensure that it equals zero on
7828 the last iteration */
7834 {
7835 /* register always nonnegative, add REG_NOTE to branch */
7842 }
7844 /* If the decrement is 1 and the value was tested as >= 0 before
7845 the loop, then we can safely optimize. */
7847 {
7860 {
7867 }
7868 }
7869 }
7872 {
7873 /* Try to change inc to dec, so can apply above optimization. */
7874 /* Can do this if:
7875 all registers modified are induction variables or invariant,
7876 all memory references have non-overlapping addresses
7877 (obviously true if only one write)
7878 allow 2 insns for the compare/jump at the end of the loop. */
7879 /* Also, we must avoid any instructions which use both the reversed
7880 biv and another biv. Such instructions will fail if the loop is
7881 reversed. We meet this condition by requiring that either
7882 no_use_except_counting is true, or else that there is only
7883 one biv. */
7885 /* 1 if the iteration var is used only to count iterations. */
7887 /* 1 if the loop has no memory store, or it has a single memory store
7888 which is reversible. */
7893 {
7896 /* If there are no givs for this biv, and the only exit is the
7897 fall through at the end of the loop, then
7898 see if perhaps there are no uses except to count. */
7902 {
7907 /* An insn that sets the biv is okay. */
7908 ;
7911 /* Don't bother about the end test. */
7912 ;
7914 {
7917 }
7918 }
7919 }
7924 {
7929 /* If the loop has a single store, and the destination address is
7930 invariant, then we can't reverse the loop, because this address
7931 might then have the wrong value at loop exit.
7932 This would work if the source was invariant also, however, in that
7933 case, the insn should have been moved out of the loop. */
7936 {
7939 reversible_mem_store
7940 = (! unknown_address_altered
7943 /* If the store depends on a register that is set after the
7944 store, it depends on the initial value, and is thus not
7945 reversible. */
7947 {
7953 }
7954 }
7955 }
7956 else
7959 /* This code only acts for innermost loops. Also it simplifies
7960 the memory address check by only reversing loops with
7961 zero or one memory access.
7962 Two memory accesses could involve parts of the same array,
7963 and that can't be reversed.
7964 If the biv is used only for counting, than we don't need to worry
7965 about all these things. */
7970 && reversible_mem_store
7975 {
7976 rtx tem;
7978 /* Loop can be reversed. */
7982 /* Now check other conditions:
7984 The increment must be a constant, as must the initial value,
7985 and the comparison code must be LT.
7987 This test can probably be improved since +/- 1 in the constant
7988 can be obtained by changing LT to LE and vice versa; this is
7989 confusing. */
7992 /* for constants, LE gets turned into LT */
7996 {
8007 comparison_const_width
8009 else
8010 comparison_const_width
8014 comparison_sign_mask
8017 /* If the comparison value is not a loop invariant, then we
8018 can not reverse this loop.
8020 ??? If the insns which initialize the comparison value as
8021 a whole compute an invariant result, then we could move
8022 them out of the loop and proceed with loop reversal. */
8030 /* Normalize the initial value if it is an integer and
8031 has no other use except as a counter. This will allow
8032 a few more loops to be reversed. */
8036 {
8038 /* The code below requires comparison_val to be a multiple
8039 of add_val in order to do the loop reversal, so
8040 round up comparison_val to a multiple of add_val.
8041 Since comparison_value is constant, we know that the
8042 current comparison code is LT. */
8044 comparison_val
8046 /* We postpone overflow checks for COMPARISON_VAL here;
8047 even if there is an overflow, we might still be able to
8048 reverse the loop, if converting the loop exit test to
8049 NE is possible. */
8051 }
8053 /* First check if we can do a vanilla loop reversal. */
8055 /* If we have a decrement_and_branch_on_count,
8056 prefer the NE test, since this will allow that
8057 instruction to be generated. Note that we must
8058 use a vanilla loop reversal if the biv is used to
8059 calculate a giv or has a non-counting use. */
8060 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8061 && defined (HAVE_decrement_and_branch_on_count)
8065 #endif
8067 /* Now do postponed overflow checks on COMPARISON_VAL. */
8070 {
8071 /* Register will always be nonnegative, with value
8072 0 on last iteration */
8076 }
8080 {
8083 }
8084 else
8090 /* If the initial value is not zero, or if the comparison
8091 value is not an exact multiple of the increment, then we
8092 can not reverse this loop. */
8095 {
8098 }
8099 else
8100 {
8103 }
8107 /* Reset these in case we normalized the initial value
8108 and comparison value above. */
8111 {
8113 final_value
8115 }
8118 /* Save some info needed to produce the new insns. */
8125 /* Set start_value; if this is not a CONST_INT, we need
8126 to generate a SUB.
8127 Initialize biv to start_value before loop start.
8128 The old initializing insn will be deleted as a
8129 dead store by flow.c. */
8132 {
8135 loop_start);
8136 }
8138 {
8141 enum insn_code icode
8150 start_value
8154 loop_start);
8158 }
8160 {
8162 enum insn_code icode
8170 start_value
8174 loop_start);
8175 }
8176 else
8177 /* We could handle the other cases too, but it'll be
8178 better to have a testcase first. */
8181 /* We may not have a single insn which can increment a reg, so
8182 create a sequence to hold all the insns from expand_inc. */
8191 /* Update biv info to reflect its new status. */
8196 /* Update loop info. */
8205 /* Inc LABEL_NUSES so that delete_insn will
8206 not delete the label. */
8209 /* Emit an insn after the end of the loop to set the biv's
8210 proper exit value if it is used anywhere outside the loop. */
8215 loop_end);
8217 /* Delete compare/branch at end of loop. */
8222 /* Add new compare/branch insn at end of loop. */
8234 ;
8240 {
8242 {
8243 /* Increment of LABEL_NUSES done above. */
8244 /* Register is now always nonnegative,
8245 so add REG_NONNEG note to the branch. */
8248 }
8250 }
8252 /* No insn may reference both the reversed and another biv or it
8253 will fail (see comment near the top of the loop reversal
8254 code).
8255 Earlier on, we have verified that the biv has no use except
8256 counting, or it is the only biv in this function.
8257 However, the code that computes no_use_except_counting does
8258 not verify reg notes. It's possible to have an insn that
8259 references another biv, and has a REG_EQUAL note with an
8260 expression based on the reversed biv. To avoid this case,
8261 remove all REG_EQUAL notes based on the reversed biv
8262 here. */
8265 {
8268 /* If this is a set of a GIV based on the reversed biv, any
8269 REG_EQUAL notes should still be correct. */
8276 {
8281 else
8283 }
8284 }
8286 /* Mark that this biv has been reversed. Each giv which depends
8287 on this biv, and which is also live past the end of the loop
8288 will have to be fixed up. */
8293 {
8297 else
8299 }
8302 }
8303 }
8304 }
8307 }
8308 \f
8309 /* Verify whether the biv BL appears to be eliminable,
8310 based on the insns in the loop that refer to it.
8311 LOOP_START is the first insn of the loop, and END is the end insn.
8313 If ELIMINATE_P is non-zero, actually do the elimination.
8315 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8316 determine whether invariant insns should be placed inside or at the
8317 start of the loop. */
8319 static int
8322 rtx loop_start;
8323 rtx end;
8326 {
8328 rtx p;
8330 /* Scan all insns in the loop, stopping if we find one that uses the
8331 biv in a way that we cannot eliminate. */
8334 {
8338 /* If this is a libcall that sets a giv, skip ahead to its end. */
8340 {
8344 {
8349 {
8356 }
8357 }
8358 }
8362 {
8368 }
8369 }
8372 {
8377 }
8380 }
8381 \f
8382 /* INSN and REFERENCE are instructions in the same insn chain.
8383 Return non-zero if INSN is first. */
8385 int
8388 {
8392 {
8393 /* Start with test for not first so that INSN == REFERENCE yields not
8394 first. */
8400 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8401 previous insn, hence the <= comparison below does not work if
8402 P is a note. */
8413 }
8414 }
8416 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8417 the offset that we have to take into account due to auto-increment /
8418 div derivation is zero. */
8419 static int
8422 rtx insn;
8423 {
8424 /* If the giv V had the auto-inc address optimization applied
8425 to it, and INSN occurs between the giv insn and the biv
8426 insn, then we'd have to adjust the value used here.
8427 This is rare, so we don't bother to make this possible. */
8435 /* If the giv V was derived from another giv, and INSN does
8436 not occur between the giv insn and the biv insn, then we'd
8437 have to adjust the value used here. This is rare, so we don't
8438 bother to make this possible. */
8452 }
8454 /* If BL appears in X (part of the pattern of INSN), see if we can
8455 eliminate its use. If so, return 1. If not, return 0.
8457 If BIV does not appear in X, return 1.
8459 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
8460 where extra insns should be added. Depending on how many items have been
8461 moved out of the loop, it will either be before INSN or at the start of
8462 the loop. */
8464 static int
8469 rtx where;
8470 {
8476 #ifdef HAVE_cc0
8478 #endif
8484 {
8486 /* If we haven't already been able to do something with this BIV,
8487 we can't eliminate it. */
8493 /* If this sets the BIV, it is not a problem. */
8497 /* If this is an insn that defines a giv, it is also ok because
8498 it will go away when the giv is reduced. */
8503 #ifdef HAVE_cc0
8505 {
8506 /* Can replace with any giv that was reduced and
8507 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8508 Require a constant for MULT_VAL, so we know it's nonzero.
8509 ??? We disable this optimization to avoid potential
8510 overflows. */
8518 {
8525 /* If the giv has the opposite direction of change,
8526 then reverse the comparison. */
8530 else
8533 /* We can probably test that giv's reduced reg. */
8536 }
8538 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8539 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8540 Require a constant for MULT_VAL, so we know it's nonzero.
8541 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8542 overflow problem. */
8553 {
8560 /* If the giv has the opposite direction of change,
8561 then reverse the comparison. */
8565 else
8569 /* Replace biv with the giv's reduced register. */
8574 /* Insn doesn't support that constant or invariant. Copy it
8575 into a register (it will be a loop invariant.) */
8579 where);
8581 /* Substitute the new register for its invariant value in
8582 the compare expression. */
8586 }
8587 }
8588 #endif
8595 /* See if either argument is the biv. */
8600 else
8604 {
8605 /* First try to replace with any giv that has constant positive
8606 mult_val and constant add_val. We might be able to support
8607 negative mult_val, but it seems complex to do it in general. */
8618 {
8625 /* Replace biv with the giv's reduced reg. */
8628 /* If all constants are actually constant integers and
8629 the derived constant can be directly placed in the COMPARE,
8630 do so. */
8640 /* Otherwise, load it into a register. */
8646 /* If that failed, put back the change we made above. */
8648 }
8650 /* Look for giv with positive constant mult_val and nonconst add_val.
8651 Insert insns to calculate new compare value.
8652 ??? Turn this off due to possible overflow. */
8659 {
8660 rtx tem;
8670 /* Replace biv with giv's reduced register. */
8674 /* Compute value to compare against. */
8676 /* Use it in this insn. */
8680 }
8681 }
8683 {
8685 {
8686 /* Look for giv with constant positive mult_val and nonconst
8687 add_val. Insert insns to compute new compare value.
8688 ??? Turn this off due to possible overflow. */
8695 {
8696 rtx tem;
8706 /* Replace biv with giv's reduced register. */
8710 /* Compute value to compare against. */
8716 }
8717 }
8719 /* This code has problems. Basically, you can't know when
8720 seeing if we will eliminate BL, whether a particular giv
8721 of ARG will be reduced. If it isn't going to be reduced,
8722 we can't eliminate BL. We can try forcing it to be reduced,
8723 but that can generate poor code.
8725 The problem is that the benefit of reducing TV, below should
8726 be increased if BL can actually be eliminated, but this means
8727 we might have to do a topological sort of the order in which
8728 we try to process biv. It doesn't seem worthwhile to do
8729 this sort of thing now. */
8731 #if 0
8732 /* Otherwise the reg compared with had better be a biv. */
8737 /* Look for a pair of givs, one for each biv,
8738 with identical coefficients. */
8740 {
8751 {
8758 /* Replace biv with its giv's reduced reg. */
8760 /* Replace other operand with the other giv's
8761 reduced reg. */
8764 }
8765 }
8766 #endif
8767 }
8769 /* If we get here, the biv can't be eliminated. */
8773 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8774 biv is used in it, since it will be replaced. */
8782 }
8784 /* See if any subexpression fails elimination. */
8787 {
8789 {
8802 }
8803 }
8806 }
8807 \f
8808 /* Return nonzero if the last use of REG
8809 is in an insn following INSN in the same basic block. */
8811 static int
8813 rtx reg;
8814 rtx insn;
8815 {
8816 rtx n;
8820 {
8823 }
8825 }
8826 \f
8827 /* Called via `note_stores' to record the initial value of a biv. Here we
8828 just record the location of the set and process it later. */
8830 static void
8832 rtx dest;
8833 rtx set;
8834 {
8844 /* If this is the first set found, record it. */
8846 {
8849 }
8850 }
8851 \f
8852 /* If any of the registers in X are "old" and currently have a last use earlier
8853 than INSN, update them to have a last use of INSN. Their actual last use
8854 will be the previous insn but it will not have a valid uid_luid so we can't
8855 use it. */
8857 static void
8859 rtx x;
8860 rtx insn;
8861 {
8862 /* Check for the case where INSN does not have a valid luid. In this case,
8863 there is no need to modify the regno_last_uid, as this can only happen
8864 when code is inserted after the loop_end to set a pseudo's final value,
8865 and hence this insn will never be the last use of x. */
8870 else
8871 {
8875 {
8881 }
8882 }
8883 }
8884 \f
8885 /* Given a jump insn JUMP, return the condition that will cause it to branch
8886 to its JUMP_LABEL. If the condition cannot be understood, or is an
8887 inequality floating-point comparison which needs to be reversed, 0 will
8888 be returned.
8890 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8891 insn used in locating the condition was found. If a replacement test
8892 of the condition is desired, it should be placed in front of that
8893 insn and we will be sure that the inputs are still valid.
8895 The condition will be returned in a canonical form to simplify testing by
8896 callers. Specifically:
8898 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8899 (2) Both operands will be machine operands; (cc0) will have been replaced.
8900 (3) If an operand is a constant, it will be the second operand.
8901 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8902 for GE, GEU, and LEU. */
8904 rtx
8906 rtx jump;
8908 {
8911 rtx set;
8912 rtx tem;
8918 /* If this is not a standard conditional jump, we can't parse it. */
8931 /* If this branches to JUMP_LABEL when the condition is false, reverse
8932 the condition. */
8937 /* If we are comparing a register with zero, see if the register is set
8938 in the previous insn to a COMPARE or a comparison operation. Perform
8939 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8940 in cse.c */
8943 {
8944 /* Set non-zero when we find something of interest. */
8947 #ifdef HAVE_cc0
8948 /* If comparison with cc0, import actual comparison from compare
8949 insn. */
8951 {
8962 }
8963 #endif
8965 /* If this is a COMPARE, pick up the two things being compared. */
8967 {
8971 }
8975 /* Go back to the previous insn. Stop if it is not an INSN. We also
8976 stop if it isn't a single set or if it has a REG_INC note because
8977 we don't want to bother dealing with it. */
8985 /* If this is setting OP0, get what it sets it to if it looks
8986 relevant. */
8988 {
8991 /* ??? We may not combine comparisons done in a CCmode with
8992 comparisons not done in a CCmode. This is to aid targets
8993 like Alpha that have an IEEE compliant EQ instruction, and
8994 a non-IEEE compliant BEQ instruction. The use of CCmode is
8995 actually artificial, simply to prevent the combination, but
8996 should not affect other platforms.
8998 However, we must allow VOIDmode comparisons to match either
8999 CCmode or non-CCmode comparison, because some ports have
9000 modeless comparisons inside branch patterns.
9002 ??? This mode check should perhaps look more like the mode check
9003 in simplify_comparison in combine. */
9011 && (STORE_FLAG_VALUE
9014 #ifdef FLOAT_STORE_FLAG_VALUE
9018 #endif
9019 ))
9030 && (STORE_FLAG_VALUE
9033 #ifdef FLOAT_STORE_FLAG_VALUE
9037 #endif
9038 ))
9044 {
9045 /* We might have reversed a LT to get a GE here. But this wasn't
9046 actually the comparison of data, so we don't flag that we
9047 have had to reverse the condition. */
9051 }
9052 else
9054 }
9057 /* If this sets OP0, but not directly, we have to give up. */
9061 {
9065 {
9069 }
9074 }
9075 }
9077 /* If constant is first, put it last. */
9081 /* If OP0 is the result of a comparison, we weren't able to find what
9082 was really being compared, so fail. */
9086 /* Canonicalize any ordered comparison with integers involving equality
9087 if we can do computations in the relevant mode and we do not
9088 overflow. */
9093 {
9096 unsigned HOST_WIDE_INT max_val
9100 {
9106 /* When cross-compiling, const_val might be sign-extended from
9107 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9127 }
9128 }
9130 /* If this was floating-point and we reversed anything other than an
9131 EQ or NE, return zero. */
9134 && ! flag_fast_math
9138 #ifdef HAVE_cc0
9139 /* Never return CC0; return zero instead. */
9142 #endif
9145 }
9147 /* Similar to above routine, except that we also put an invariant last
9148 unless both operands are invariants. */
9150 rtx
9152 rtx x;
9153 {
9163 }
9165 #ifdef HAVE_decrement_and_branch_on_count
9166 /* Instrument loop for insertion of bct instruction. We distinguish between
9167 loops with compile-time bounds and those with run-time bounds.
9168 Information from loop_iterations() is used to compute compile-time bounds.
9169 Run-time bounds should use loop preconditioning, but currently ignored.
9170 */
9172 static void
9176 {
9182 /* If the loop condition is <= or >=, the number of iteration
9183 is 1 more than the range of the bounds of the loop. */
9190 /* It's impossible to instrument a competely unrolled loop. */
9194 /* Make sure that the count register is not in use. */
9196 {
9200 loop_num);
9202 }
9204 /* Make sure that the function has no indirect jumps. */
9206 {
9210 loop_num);
9212 }
9214 /* Make sure that the last loop insn is a conditional jump. */
9218 {
9222 loop_num);
9224 }
9226 /* Make sure that the loop does not contain a function call
9227 (the count register might be altered by the called function). */
9229 {
9233 loop_num);
9235 }
9237 /* Make sure that the loop does not jump via a table.
9238 (the count register might be used to perform the branch on table). */
9240 {
9244 loop_num);
9246 }
9248 /* Account for loop unrolling in instrumented iteration count. */
9251 else
9255 {
9256 /* Allow an enclosing outer loop to benefit if possible. */
9260 loop_num);
9262 }
9264 /* Try to instrument the loop. */
9266 /* Handle the simpler case, where the bounds are known at compile time. */
9268 {
9269 /* Mark all enclosing loops that they cannot use count register. */
9274 }
9276 /* Handle the more complex case, that the bounds are NOT known
9277 at compile time. In this case we generate run_time calculation
9278 of the number of iterations. */
9281 {
9285 loop_num);
9287 }
9291 {
9295 loop_num);
9297 }
9299 /* With runtime bounds, if the compare is of the form '!=' we give up */
9301 {
9305 loop_num);
9307 }
9308 /* Use common loop preconditioning code instead. */
9309 #if 0
9310 else
9311 {
9312 /* We rely on the existence of run-time guard to ensure that the
9313 loop executes at least once. */
9314 rtx sequence;
9315 rtx iterations_num_reg;
9317 unsigned HOST_WIDE_INT increment_value_abs
9320 /* make sure that the increment is a power of two, otherwise (an
9321 expensive) divide is needed. */
9323 {
9328 }
9330 /* compute the number of iterations */
9332 {
9333 rtx temp_reg;
9335 /* Again, the number of iterations is calculated by:
9336 ;
9337 ; compare-val - initial-val + (increment -1) + additional-iteration
9338 ; num_iterations = -----------------------------------------------------------------
9339 ; increment
9340 */
9341 /* ??? Do we have to call copy_rtx here before passing rtx to
9342 expand_binop? */
9344 {
9345 /* <, <= :the loop variable is increasing */
9349 }
9350 else
9351 {
9355 }
9365 temp_reg,
9368 else
9370 }
9375 }
9379 }
9381 /* Instrument loop by inserting a bct in it as follows:
9382 1. A new counter register is created.
9383 2. In the head of the loop the new variable is initialized to the value
9384 passed in the loop_num_iterations parameter.
9385 3. At the end of the loop, comparison of the register with 0 is generated.
9386 The created comparison follows the pattern defined for the
9387 decrement_and_branch_on_count insn, so this insn will be generated.
9388 4. The branch on the old variable are deleted. The compare must remain
9389 because it might be used elsewhere. If the loop-variable or condition
9390 register are used elsewhere, they will be eliminated by flow. */
9392 static void
9395 rtx loop_num_iterations;
9396 {
9397 rtx counter_reg;
9398 rtx start_label;
9399 rtx sequence;
9402 {
9404 {
9409 else
9412 }
9414 /* Discard original jump to continue loop. Original compare result
9415 may still be live, so it cannot be discarded explicitly. */
9418 /* Insert the label which will delimit the start of the loop. */
9422 /* Insert initialization of the count register into the loop header. */
9430 /* Insert new comparison on the count register instead of the
9431 old one, generating the needed BCT pattern (that will be
9432 later recognized by assembly generation phase). */
9434 start_label),
9435 loop_end);
9437 }
9439 }
9442 /* Scan the function and determine whether it has indirect (computed) jumps.
9444 This is taken mostly from flow.c; similar code exists elsewhere
9445 in the compiler. It may be useful to put this into rtlanal.c. */
9446 static int
9448 rtx start;
9449 {
9450 rtx insn;
9457 }
9459 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9460 documentation for LOOP_MEMS for the definition of `appropriate'.
9461 This function is called from prescan_loop via for_each_rtx. */
9463 static int
9467 {
9475 {
9480 /* We're not interested in the MEM associated with a
9481 CONST_DOUBLE, so there's no need to traverse into this. */
9485 /* This is not a MEM. */
9487 }
9489 /* See if we've already seen this MEM. */
9492 {
9494 /* The modes of the two memory accesses are different. If
9495 this happens, something tricky is going on, and we just
9496 don't optimize accesses to this MEM. */
9500 }
9502 /* Resize the array, if necessary. */
9504 {
9507 else
9513 }
9515 /* Actually insert the MEM. */
9517 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9518 because we can't put it in a register. We still store it in the
9519 table, though, so that if we see the same address later, but in a
9520 non-BLK mode, we'll not think we can optimize it at that point. */
9526 }
9528 /* Like load_mems, but also ensures that SET_IN_LOOP,
9529 MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct
9530 values after load_mems. */
9532 static void
9534 insn_count)
9535 rtx scan_start;
9536 rtx end;
9537 rtx loop_top;
9538 rtx start;
9540 {
9545 /* Recalculate set_in_loop and friends since load_mems may have
9546 created new registers. */
9548 {
9556 {
9557 /* Grow all the arrays. */
9562 }
9563 /* Clear the arrays */
9573 {
9576 }
9578 #ifdef AVOID_CCMODE_COPIES
9579 /* Don't try to move insns which set CC registers if we should not
9580 create CCmode register copies. */
9584 #endif
9586 /* Set n_times_set for the new registers. */
9590 }
9591 }
9593 /* Move MEMs into registers for the duration of the loop. SCAN_START
9594 is the first instruction in the loop (as it is executed). The
9595 other parameters are as for next_insn_in_loop. */
9597 static void
9599 rtx scan_start;
9600 rtx end;
9601 rtx loop_top;
9602 rtx start;
9603 {
9606 rtx p;
9611 {
9612 /* Nonzero if the next instruction may never be executed. */
9615 /* Check to see if it's possible that some instructions in the
9616 loop are never executed. */
9620 {
9624 /* If we enter the loop in the middle, and scan
9625 around to the beginning, don't set maybe_never
9626 for that. This must be an unconditional jump,
9627 otherwise the code at the top of the loop might
9628 never be executed. Unconditional jumps are
9629 followed a by barrier then loop end. */
9634 {
9636 /* Something complicated. */
9638 else
9639 /* If there are any more instructions in the loop, they
9640 might not be reached. */
9642 }
9645 }
9647 /* Actually move the MEMs. */
9649 {
9651 rtx reg;
9653 rtx mem_list_entry;
9657 /* There's no telling whether or not MEM is modified. */
9660 /* Go through the MEMs written to in the loop to see if this
9661 one is aliased by one of them. */
9664 {
9669 {
9670 /* MEM is indeed aliased by this store. */
9673 }
9675 }
9677 /* If this MEM is written to, we must be sure that there
9678 are no reads from another MEM that aliases this one. */
9680 {
9684 {
9688 VOIDmode,
9690 rtx_varies_p))
9691 {
9692 /* It's not safe to hoist loop_mems[i] out of
9693 the loop because writes to it might not be
9694 seen by reads from loop_mems[j]. */
9697 }
9698 }
9699 }
9702 /* We can't access the MEM outside the loop; it might
9703 cause a trap that wouldn't have happened otherwise. */
9707 /* We thought we were going to lift this MEM out of the
9708 loop, but later discovered that we could not. */
9711 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9712 order to keep scan_loop from moving stores to this MEM
9713 out of the loop just because this REG is neither a
9714 user-variable nor used in the loop test. */
9719 /* Now, replace all references to the MEM with the
9720 corresponding pesudos. */
9724 {
9725 rtx_and_int ri;
9729 }
9732 /* We couldn't replace all occurrences of the MEM. */
9734 else
9735 {
9736 rtx set;
9738 /* Load the memory immediately before START, which is
9739 the NOTE_LOOP_BEG. */
9744 {
9746 {
9747 /* We must compute the former
9748 right-after-the-end label before we insert
9749 the new one. */
9753 }
9755 /* Store the memory immediately after END, which is
9756 the NOTE_LOOP_END. */
9759 }
9762 {
9767 }
9768 }
9769 }
9770 }
9773 {
9774 /* Now, we need to replace all references to the previous exit
9775 label with the new one. */
9776 rtx_pair rr;
9781 {
9784 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9785 field. This is not handled by for_each_rtx because it doesn't
9786 handle unprinted ('0') fields. We need to update JUMP_LABEL
9787 because the immediately following unroll pass will use it.
9788 replace_label would not work anyways, because that only handles
9789 LABEL_REFs. */
9792 }
9793 }
9794 }
9796 /* Replace MEM with its associated pseudo register. This function is
9797 called from load_mems via for_each_rtx. DATA is actually an
9798 rtx_and_int * describing the instruction currently being scanned
9799 and the MEM we are currently replacing. */
9801 static int
9805 {
9807 rtx insn;
9815 {
9820 /* We're not interested in the MEM associated with a
9821 CONST_DOUBLE, so there's no need to traverse into one. */
9825 /* This is not a MEM. */
9827 }
9833 /* This is not the MEM we are currently replacing. */
9838 /* Actually replace the MEM. */
9842 }
9844 /* Replace occurrences of the old exit label for the loop with the new
9845 one. DATA is an rtx_pair containing the old and new labels,
9846 respectively. */
9848 static int
9852 {
9871 }