1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
50 enum reg_class regno_reg_class
[] =
52 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
53 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
54 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
55 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
56 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
57 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
62 /* The minimum number of integer registers that we want to save with the
63 movem instruction. Using two movel instructions instead of a single
64 moveml is about 15% faster for the 68020 and 68030 at no expense in
66 #define MIN_MOVEM_REGS 3
68 /* The minimum number of floating point registers that we want to save
69 with the fmovem instruction. */
70 #define MIN_FMOVEM_REGS 1
72 /* Structure describing stack frame layout. */
75 /* Stack pointer to frame pointer offset. */
78 /* Offset of FPU registers. */
79 HOST_WIDE_INT foffset
;
81 /* Frame size in bytes (rounded up). */
84 /* Data and address register. */
86 unsigned int reg_mask
;
90 unsigned int fpu_mask
;
92 /* Offsets relative to ARG_POINTER. */
93 HOST_WIDE_INT frame_pointer_offset
;
94 HOST_WIDE_INT stack_pointer_offset
;
96 /* Function which the above information refers to. */
100 /* Current frame information calculated by m68k_compute_frame_layout(). */
101 static struct m68k_frame current_frame
;
103 /* Structure describing an m68k address.
105 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
106 with null fields evaluating to 0. Here:
108 - BASE satisfies m68k_legitimate_base_reg_p
109 - INDEX satisfies m68k_legitimate_index_reg_p
110 - OFFSET satisfies m68k_legitimate_constant_address_p
112 INDEX is either HImode or SImode. The other fields are SImode.
114 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
115 the address is (BASE)+. */
116 struct m68k_address
{
124 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
125 static int m68k_sched_issue_rate (void);
126 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
127 static void m68k_sched_md_init_global (FILE *, int, int);
128 static void m68k_sched_md_finish_global (FILE *, int);
129 static void m68k_sched_md_init (FILE *, int, int);
130 static void m68k_sched_dfa_pre_advance_cycle (void);
131 static void m68k_sched_dfa_post_advance_cycle (void);
132 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
134 static bool m68k_handle_option (size_t, const char *, int);
135 static rtx
find_addr_reg (rtx
);
136 static const char *singlemove_string (rtx
*);
137 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
138 HOST_WIDE_INT
, tree
);
139 static rtx
m68k_struct_value_rtx (tree
, int);
140 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
141 tree args
, int flags
,
143 static void m68k_compute_frame_layout (void);
144 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
145 static bool m68k_ok_for_sibcall_p (tree
, tree
);
146 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
147 static bool m68k_rtx_costs (rtx
, int, int, int *, bool);
148 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
149 static bool m68k_return_in_memory (const_tree
, const_tree
);
153 /* Specify the identification number of the library being built */
154 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
156 /* Nonzero if the last compare/test insn had FP operands. The
157 sCC expanders peek at this to determine what to do for the
158 68060, which has no fsCC instructions. */
159 int m68k_last_compare_had_fp_operands
;
161 /* Initialize the GCC target structure. */
163 #if INT_OP_GROUP == INT_OP_DOT_WORD
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
168 #if INT_OP_GROUP == INT_OP_NO_DOT
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP "\tbyte\t"
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
177 #if INT_OP_GROUP == INT_OP_DC
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
186 #undef TARGET_ASM_UNALIGNED_HI_OP
187 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_OUTPUT_MI_THUNK
192 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
193 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
194 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
196 #undef TARGET_ASM_FILE_START_APP_OFF
197 #define TARGET_ASM_FILE_START_APP_OFF true
199 #undef TARGET_LEGITIMIZE_ADDRESS
200 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
202 #undef TARGET_SCHED_ADJUST_COST
203 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
205 #undef TARGET_SCHED_ISSUE_RATE
206 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
208 #undef TARGET_SCHED_VARIABLE_ISSUE
209 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
211 #undef TARGET_SCHED_INIT_GLOBAL
212 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
214 #undef TARGET_SCHED_FINISH_GLOBAL
215 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
217 #undef TARGET_SCHED_INIT
218 #define TARGET_SCHED_INIT m68k_sched_md_init
220 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
221 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
223 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
224 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
226 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
227 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
228 m68k_sched_first_cycle_multipass_dfa_lookahead
230 #undef TARGET_HANDLE_OPTION
231 #define TARGET_HANDLE_OPTION m68k_handle_option
233 #undef TARGET_RTX_COSTS
234 #define TARGET_RTX_COSTS m68k_rtx_costs
236 #undef TARGET_ATTRIBUTE_TABLE
237 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
239 #undef TARGET_PROMOTE_PROTOTYPES
240 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
242 #undef TARGET_STRUCT_VALUE_RTX
243 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
245 #undef TARGET_CANNOT_FORCE_CONST_MEM
246 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
248 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
249 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
251 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
252 #undef TARGET_RETURN_IN_MEMORY
253 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
256 static const struct attribute_spec m68k_attribute_table
[] =
258 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
259 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
260 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
261 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
262 { NULL
, 0, 0, false, false, false, NULL
}
265 struct gcc_target targetm
= TARGET_INITIALIZER
;
267 /* Base flags for 68k ISAs. */
268 #define FL_FOR_isa_00 FL_ISA_68000
269 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
270 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
271 generated 68881 code for 68020 and 68030 targets unless explicitly told
273 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
274 | FL_BITFIELD | FL_68881)
275 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
276 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
278 /* Base flags for ColdFire ISAs. */
279 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
280 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
281 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
282 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
283 /* ISA_C is not upwardly compatible with ISA_B. */
284 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
288 /* Traditional 68000 instruction sets. */
294 /* ColdFire instruction set variants. */
302 /* Information about one of the -march, -mcpu or -mtune arguments. */
303 struct m68k_target_selection
305 /* The argument being described. */
308 /* For -mcpu, this is the device selected by the option.
309 For -mtune and -march, it is a representative device
310 for the microarchitecture or ISA respectively. */
311 enum target_device device
;
313 /* The M68K_DEVICE fields associated with DEVICE. See the comment
314 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
316 enum uarch_type microarch
;
321 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
322 static const struct m68k_target_selection all_devices
[] =
324 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
325 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
326 #include "m68k-devices.def"
328 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
331 /* A list of all ISAs, mapping each one to a representative device.
332 Used for -march selection. */
333 static const struct m68k_target_selection all_isas
[] =
335 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
336 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
337 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
338 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
339 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
340 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
341 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
342 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
344 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
346 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
347 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
349 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
352 /* A list of all microarchitectures, mapping each one to a representative
353 device. Used for -mtune selection. */
354 static const struct m68k_target_selection all_microarchs
[] =
356 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
357 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
358 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
359 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
360 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
361 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
362 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
363 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
364 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
365 { "cfv1", mcf51qe
, NULL
, ucfv1
, isa_c
, FL_FOR_isa_c
},
366 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
367 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
369 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
370 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
374 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
377 /* The entries associated with the -mcpu, -march and -mtune settings,
378 or null for options that have not been used. */
379 const struct m68k_target_selection
*m68k_cpu_entry
;
380 const struct m68k_target_selection
*m68k_arch_entry
;
381 const struct m68k_target_selection
*m68k_tune_entry
;
383 /* Which CPU we are generating code for. */
384 enum target_device m68k_cpu
;
386 /* Which microarchitecture to tune for. */
387 enum uarch_type m68k_tune
;
389 /* Which FPU to use. */
390 enum fpu_type m68k_fpu
;
392 /* The set of FL_* flags that apply to the target processor. */
393 unsigned int m68k_cpu_flags
;
395 /* The set of FL_* flags that apply to the processor to be tuned for. */
396 unsigned int m68k_tune_flags
;
398 /* Asm templates for calling or jumping to an arbitrary symbolic address,
399 or NULL if such calls or jumps are not supported. The address is held
401 const char *m68k_symbolic_call
;
402 const char *m68k_symbolic_jump
;
404 /* Enum variable that corresponds to m68k_symbolic_call values. */
405 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
408 /* See whether TABLE has an entry with name NAME. Return true and
409 store the entry in *ENTRY if so, otherwise return false and
410 leave *ENTRY alone. */
413 m68k_find_selection (const struct m68k_target_selection
**entry
,
414 const struct m68k_target_selection
*table
,
419 for (i
= 0; table
[i
].name
; i
++)
420 if (strcmp (table
[i
].name
, name
) == 0)
428 /* Implement TARGET_HANDLE_OPTION. */
431 m68k_handle_option (size_t code
, const char *arg
, int value
)
436 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
439 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
442 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
445 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
448 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
451 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
454 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
457 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
460 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
464 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
467 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
471 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
474 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
476 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
479 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
481 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
484 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
487 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
490 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
493 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
497 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
499 case OPT_mshared_library_id_
:
500 if (value
> MAX_LIBRARY_ID
)
501 error ("-mshared-library-id=%s is not between 0 and %d",
502 arg
, MAX_LIBRARY_ID
);
506 asprintf (&tmp
, "%d", (value
* -4) - 4);
507 m68k_library_id_string
= tmp
;
516 /* Sometimes certain combinations of command options do not make
517 sense on a particular target machine. You can define a macro
518 `OVERRIDE_OPTIONS' to take account of this. This macro, if
519 defined, is executed once just after all the command options have
522 Don't use this macro to turn on various extra optimizations for
523 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
526 override_options (void)
528 const struct m68k_target_selection
*entry
;
529 unsigned long target_mask
;
537 -march=ARCH should generate code that runs any processor
538 implementing architecture ARCH. -mcpu=CPU should override -march
539 and should generate code that runs on processor CPU, making free
540 use of any instructions that CPU understands. -mtune=UARCH applies
541 on top of -mcpu or -march and optimizes the code for UARCH. It does
542 not change the target architecture. */
545 /* Complain if the -march setting is for a different microarchitecture,
546 or includes flags that the -mcpu setting doesn't. */
548 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
549 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
550 warning (0, "-mcpu=%s conflicts with -march=%s",
551 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
553 entry
= m68k_cpu_entry
;
556 entry
= m68k_arch_entry
;
559 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
561 m68k_cpu_flags
= entry
->flags
;
563 /* Use the architecture setting to derive default values for
567 /* ColdFire is lenient about alignment. */
568 if (!TARGET_COLDFIRE
)
569 target_mask
|= MASK_STRICT_ALIGNMENT
;
571 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
572 target_mask
|= MASK_BITFIELD
;
573 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
574 target_mask
|= MASK_CF_HWDIV
;
575 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
576 target_mask
|= MASK_HARD_FLOAT
;
577 target_flags
|= target_mask
& ~target_flags_explicit
;
579 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
580 m68k_cpu
= entry
->device
;
583 m68k_tune
= m68k_tune_entry
->microarch
;
584 m68k_tune_flags
= m68k_tune_entry
->flags
;
586 #ifdef M68K_DEFAULT_TUNE
587 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
589 enum target_device dev
;
590 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
591 m68k_tune_flags
= all_devices
[dev
]->flags
;
596 m68k_tune
= entry
->microarch
;
597 m68k_tune_flags
= entry
->flags
;
600 /* Set the type of FPU. */
601 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
602 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
605 /* Sanity check to ensure that msep-data and mid-sahred-library are not
606 * both specified together. Doing so simply doesn't make sense.
608 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
609 error ("cannot specify both -msep-data and -mid-shared-library");
611 /* If we're generating code for a separate A5 relative data segment,
612 * we've got to enable -fPIC as well. This might be relaxable to
613 * -fpic but it hasn't been tested properly.
615 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
618 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
619 error if the target does not support them. */
620 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
621 error ("-mpcrel -fPIC is not currently supported on selected cpu");
623 /* ??? A historic way of turning on pic, or is this intended to
624 be an embedded thing that doesn't have the same name binding
625 significance that it does on hosted ELF systems? */
626 if (TARGET_PCREL
&& flag_pic
== 0)
631 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
633 m68k_symbolic_jump
= "jra %a0";
635 else if (TARGET_ID_SHARED_LIBRARY
)
636 /* All addresses must be loaded from the GOT. */
638 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
641 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
643 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
646 /* No unconditional long branch */;
647 else if (TARGET_PCREL
)
648 m68k_symbolic_jump
= "bra%.l %c0";
650 m68k_symbolic_jump
= "bra%.l %p0";
651 /* Turn off function cse if we are doing PIC. We always want
652 function call to be done as `bsr foo@PLTPC'. */
653 /* ??? It's traditional to do this for -mpcrel too, but it isn't
654 clear how intentional that is. */
655 flag_no_function_cse
= 1;
658 switch (m68k_symbolic_call_var
)
660 case M68K_SYMBOLIC_CALL_JSR
:
661 m68k_symbolic_call
= "jsr %a0";
664 case M68K_SYMBOLIC_CALL_BSR_C
:
665 m68k_symbolic_call
= "bsr%.l %c0";
668 case M68K_SYMBOLIC_CALL_BSR_P
:
669 m68k_symbolic_call
= "bsr%.l %p0";
672 case M68K_SYMBOLIC_CALL_NONE
:
673 gcc_assert (m68k_symbolic_call
== NULL
);
680 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
681 if (align_labels
> 2)
683 warning (0, "-falign-labels=%d is not supported", align_labels
);
688 warning (0, "-falign-loops=%d is not supported", align_loops
);
693 SUBTARGET_OVERRIDE_OPTIONS
;
695 /* Setup scheduling options. */
697 m68k_sched_cpu
= CPU_CFV1
;
699 m68k_sched_cpu
= CPU_CFV2
;
701 m68k_sched_cpu
= CPU_CFV3
;
703 m68k_sched_cpu
= CPU_CFV4
;
706 m68k_sched_cpu
= CPU_UNKNOWN
;
707 flag_schedule_insns
= 0;
708 flag_schedule_insns_after_reload
= 0;
709 flag_modulo_sched
= 0;
712 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
714 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
715 m68k_sched_mac
= MAC_CF_EMAC
;
716 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
717 m68k_sched_mac
= MAC_CF_MAC
;
719 m68k_sched_mac
= MAC_NO
;
723 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
724 given argument and NAME is the argument passed to -mcpu. Return NULL
725 if -mcpu was not passed. */
728 m68k_cpp_cpu_ident (const char *prefix
)
732 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
735 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
736 given argument and NAME is the name of the representative device for
737 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
740 m68k_cpp_cpu_family (const char *prefix
)
744 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
747 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
748 "interrupt_handler" attribute and interrupt_thread if FUNC has an
749 "interrupt_thread" attribute. Otherwise, return
750 m68k_fk_normal_function. */
752 enum m68k_function_kind
753 m68k_get_function_kind (tree func
)
757 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
759 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
761 return m68k_fk_interrupt_handler
;
763 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
765 return m68k_fk_interrupt_handler
;
767 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
769 return m68k_fk_interrupt_thread
;
771 return m68k_fk_normal_function
;
774 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
775 struct attribute_spec.handler. */
777 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
778 tree args ATTRIBUTE_UNUSED
,
779 int flags ATTRIBUTE_UNUSED
,
782 if (TREE_CODE (*node
) != FUNCTION_DECL
)
784 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
785 IDENTIFIER_POINTER (name
));
786 *no_add_attrs
= true;
789 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
791 error ("multiple interrupt attributes not allowed");
792 *no_add_attrs
= true;
796 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
798 error ("interrupt_thread is available only on fido");
799 *no_add_attrs
= true;
806 m68k_compute_frame_layout (void)
810 enum m68k_function_kind func_kind
=
811 m68k_get_function_kind (current_function_decl
);
812 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
813 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
815 /* Only compute the frame once per function.
816 Don't cache information until reload has been completed. */
817 if (current_frame
.funcdef_no
== current_function_funcdef_no
821 current_frame
.size
= (get_frame_size () + 3) & -4;
825 /* Interrupt thread does not need to save any register. */
826 if (!interrupt_thread
)
827 for (regno
= 0; regno
< 16; regno
++)
828 if (m68k_save_reg (regno
, interrupt_handler
))
830 mask
|= 1 << (regno
- D0_REG
);
833 current_frame
.offset
= saved
* 4;
834 current_frame
.reg_no
= saved
;
835 current_frame
.reg_mask
= mask
;
837 current_frame
.foffset
= 0;
839 if (TARGET_HARD_FLOAT
)
841 /* Interrupt thread does not need to save any register. */
842 if (!interrupt_thread
)
843 for (regno
= 16; regno
< 24; regno
++)
844 if (m68k_save_reg (regno
, interrupt_handler
))
846 mask
|= 1 << (regno
- FP0_REG
);
849 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
850 current_frame
.offset
+= current_frame
.foffset
;
852 current_frame
.fpu_no
= saved
;
853 current_frame
.fpu_mask
= mask
;
855 /* Remember what function this frame refers to. */
856 current_frame
.funcdef_no
= current_function_funcdef_no
;
860 m68k_initial_elimination_offset (int from
, int to
)
863 /* The arg pointer points 8 bytes before the start of the arguments,
864 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
865 frame pointer in most frames. */
866 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
867 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
868 return argptr_offset
;
870 m68k_compute_frame_layout ();
872 gcc_assert (to
== STACK_POINTER_REGNUM
);
875 case ARG_POINTER_REGNUM
:
876 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
877 case FRAME_POINTER_REGNUM
:
878 return current_frame
.offset
+ current_frame
.size
;
884 /* Refer to the array `regs_ever_live' to determine which registers
885 to save; `regs_ever_live[I]' is nonzero if register number I
886 is ever used in the function. This function is responsible for
887 knowing which registers should not be saved even if used.
888 Return true if we need to save REGNO. */
891 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
893 if (flag_pic
&& regno
== PIC_REG
)
895 if (crtl
->saves_all_registers
)
897 if (crtl
->uses_pic_offset_table
)
899 /* Reload may introduce constant pool references into a function
900 that thitherto didn't need a PIC register. Note that the test
901 above will not catch that case because we will only set
902 crtl->uses_pic_offset_table when emitting
903 the address reloads. */
904 if (crtl
->uses_const_pool
)
908 if (crtl
->calls_eh_return
)
913 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
914 if (test
== INVALID_REGNUM
)
921 /* Fixed regs we never touch. */
922 if (fixed_regs
[regno
])
925 /* The frame pointer (if it is such) is handled specially. */
926 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
929 /* Interrupt handlers must also save call_used_regs
930 if they are live or when calling nested functions. */
931 if (interrupt_handler
)
933 if (df_regs_ever_live_p (regno
))
936 if (!current_function_is_leaf
&& call_used_regs
[regno
])
940 /* Never need to save registers that aren't touched. */
941 if (!df_regs_ever_live_p (regno
))
944 /* Otherwise save everything that isn't call-clobbered. */
945 return !call_used_regs
[regno
];
948 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
949 the lowest memory address. COUNT is the number of registers to be
950 moved, with register REGNO + I being moved if bit I of MASK is set.
951 STORE_P specifies the direction of the move and ADJUST_STACK_P says
952 whether or not this is pre-decrement (if STORE_P) or post-increment
953 (if !STORE_P) operation. */
956 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
957 unsigned int count
, unsigned int regno
,
958 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
961 rtx body
, addr
, src
, operands
[2];
962 enum machine_mode mode
;
964 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
965 mode
= reg_raw_mode
[regno
];
970 src
= plus_constant (base
, (count
971 * GET_MODE_SIZE (mode
)
972 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
973 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
976 for (; mask
!= 0; mask
>>= 1, regno
++)
979 addr
= plus_constant (base
, offset
);
980 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
981 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
982 XVECEXP (body
, 0, i
++)
983 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
984 offset
+= GET_MODE_SIZE (mode
);
986 gcc_assert (i
== XVECLEN (body
, 0));
988 return emit_insn (body
);
991 /* Make INSN a frame-related instruction. */
994 m68k_set_frame_related (rtx insn
)
999 RTX_FRAME_RELATED_P (insn
) = 1;
1000 body
= PATTERN (insn
);
1001 if (GET_CODE (body
) == PARALLEL
)
1002 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
1003 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
1006 /* Emit RTL for the "prologue" define_expand. */
1009 m68k_expand_prologue (void)
1011 HOST_WIDE_INT fsize_with_regs
;
1012 rtx limit
, src
, dest
, insn
;
1014 m68k_compute_frame_layout ();
1016 /* If the stack limit is a symbol, we can check it here,
1017 before actually allocating the space. */
1018 if (crtl
->limit_stack
1019 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1021 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
1022 if (!LEGITIMATE_CONSTANT_P (limit
))
1024 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1025 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1027 emit_insn (gen_cmpsi (stack_pointer_rtx
, limit
));
1028 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
1029 cc0_rtx
, const0_rtx
),
1033 fsize_with_regs
= current_frame
.size
;
1034 if (TARGET_COLDFIRE
)
1036 /* ColdFire's move multiple instructions do not allow pre-decrement
1037 addressing. Add the size of movem saves to the initial stack
1038 allocation instead. */
1039 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1040 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1041 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1042 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1045 if (frame_pointer_needed
)
1047 if (fsize_with_regs
== 0 && TUNE_68040
)
1049 /* On the 68040, two separate moves are faster than link.w 0. */
1050 dest
= gen_frame_mem (Pmode
,
1051 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1052 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1053 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1054 stack_pointer_rtx
));
1056 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1057 m68k_set_frame_related
1058 (emit_insn (gen_link (frame_pointer_rtx
,
1059 GEN_INT (-4 - fsize_with_regs
))));
1062 m68k_set_frame_related
1063 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1064 m68k_set_frame_related
1065 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1067 GEN_INT (-fsize_with_regs
))));
1070 /* If the frame pointer is needed, emit a special barrier that
1071 will prevent the scheduler from moving stores to the frame
1072 before the stack adjustment. */
1073 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1075 else if (fsize_with_regs
!= 0)
1076 m68k_set_frame_related
1077 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1079 GEN_INT (-fsize_with_regs
))));
1081 if (current_frame
.fpu_mask
)
1083 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1085 m68k_set_frame_related
1086 (m68k_emit_movem (stack_pointer_rtx
,
1087 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1088 current_frame
.fpu_no
, FP0_REG
,
1089 current_frame
.fpu_mask
, true, true));
1094 /* If we're using moveml to save the integer registers,
1095 the stack pointer will point to the bottom of the moveml
1096 save area. Find the stack offset of the first FP register. */
1097 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1100 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1101 m68k_set_frame_related
1102 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1103 current_frame
.fpu_no
, FP0_REG
,
1104 current_frame
.fpu_mask
, true, false));
1108 /* If the stack limit is not a symbol, check it here.
1109 This has the disadvantage that it may be too late... */
1110 if (crtl
->limit_stack
)
1112 if (REG_P (stack_limit_rtx
))
1114 emit_insn (gen_cmpsi (stack_pointer_rtx
, stack_limit_rtx
));
1115 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
1116 cc0_rtx
, const0_rtx
),
1119 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1120 warning (0, "stack limit expression is not supported");
1123 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1125 /* Store each register separately in the same order moveml does. */
1128 for (i
= 16; i
-- > 0; )
1129 if (current_frame
.reg_mask
& (1 << i
))
1131 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1132 dest
= gen_frame_mem (SImode
,
1133 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1134 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1139 if (TARGET_COLDFIRE
)
1140 /* The required register save space has already been allocated.
1141 The first register should be stored at (%sp). */
1142 m68k_set_frame_related
1143 (m68k_emit_movem (stack_pointer_rtx
, 0,
1144 current_frame
.reg_no
, D0_REG
,
1145 current_frame
.reg_mask
, true, false));
1147 m68k_set_frame_related
1148 (m68k_emit_movem (stack_pointer_rtx
,
1149 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1150 current_frame
.reg_no
, D0_REG
,
1151 current_frame
.reg_mask
, true, true));
1156 && crtl
->uses_pic_offset_table
)
1157 insn
= emit_insn (gen_load_got (pic_offset_table_rtx
));
1160 /* Return true if a simple (return) instruction is sufficient for this
1161 instruction (i.e. if no epilogue is needed). */
1164 m68k_use_return_insn (void)
1166 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1169 m68k_compute_frame_layout ();
1170 return current_frame
.offset
== 0;
1173 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1174 SIBCALL_P says which.
1176 The function epilogue should not depend on the current stack pointer!
1177 It should use the frame pointer only, if there is a frame pointer.
1178 This is mandatory because of alloca; we also take advantage of it to
1179 omit stack adjustments before returning. */
1182 m68k_expand_epilogue (bool sibcall_p
)
1184 HOST_WIDE_INT fsize
, fsize_with_regs
;
1185 bool big
, restore_from_sp
;
1187 m68k_compute_frame_layout ();
1189 fsize
= current_frame
.size
;
1191 restore_from_sp
= false;
1193 /* FIXME : current_function_is_leaf below is too strong.
1194 What we really need to know there is if there could be pending
1195 stack adjustment needed at that point. */
1196 restore_from_sp
= (!frame_pointer_needed
1197 || (!cfun
->calls_alloca
1198 && current_function_is_leaf
));
1200 /* fsize_with_regs is the size we need to adjust the sp when
1201 popping the frame. */
1202 fsize_with_regs
= fsize
;
1203 if (TARGET_COLDFIRE
&& restore_from_sp
)
1205 /* ColdFire's move multiple instructions do not allow post-increment
1206 addressing. Add the size of movem loads to the final deallocation
1208 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1209 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1210 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1211 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1214 if (current_frame
.offset
+ fsize
>= 0x8000
1216 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1219 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1220 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1222 /* ColdFire's move multiple instructions do not support the
1223 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1224 stack-based restore. */
1225 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1226 GEN_INT (-(current_frame
.offset
+ fsize
)));
1227 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1228 gen_rtx_REG (Pmode
, A1_REG
),
1229 frame_pointer_rtx
));
1230 restore_from_sp
= true;
1234 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1240 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1242 /* Restore each register separately in the same order moveml does. */
1244 HOST_WIDE_INT offset
;
1246 offset
= current_frame
.offset
+ fsize
;
1247 for (i
= 0; i
< 16; i
++)
1248 if (current_frame
.reg_mask
& (1 << i
))
1254 /* Generate the address -OFFSET(%fp,%a1.l). */
1255 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1256 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1257 addr
= plus_constant (addr
, -offset
);
1259 else if (restore_from_sp
)
1260 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1262 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1263 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1264 gen_frame_mem (SImode
, addr
));
1265 offset
-= GET_MODE_SIZE (SImode
);
1268 else if (current_frame
.reg_mask
)
1271 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1272 gen_rtx_REG (Pmode
, A1_REG
),
1274 -(current_frame
.offset
+ fsize
),
1275 current_frame
.reg_no
, D0_REG
,
1276 current_frame
.reg_mask
, false, false);
1277 else if (restore_from_sp
)
1278 m68k_emit_movem (stack_pointer_rtx
, 0,
1279 current_frame
.reg_no
, D0_REG
,
1280 current_frame
.reg_mask
, false,
1283 m68k_emit_movem (frame_pointer_rtx
,
1284 -(current_frame
.offset
+ fsize
),
1285 current_frame
.reg_no
, D0_REG
,
1286 current_frame
.reg_mask
, false, false);
1289 if (current_frame
.fpu_no
> 0)
1292 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1293 gen_rtx_REG (Pmode
, A1_REG
),
1295 -(current_frame
.foffset
+ fsize
),
1296 current_frame
.fpu_no
, FP0_REG
,
1297 current_frame
.fpu_mask
, false, false);
1298 else if (restore_from_sp
)
1300 if (TARGET_COLDFIRE
)
1304 /* If we used moveml to restore the integer registers, the
1305 stack pointer will still point to the bottom of the moveml
1306 save area. Find the stack offset of the first FP
1308 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1311 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1312 m68k_emit_movem (stack_pointer_rtx
, offset
,
1313 current_frame
.fpu_no
, FP0_REG
,
1314 current_frame
.fpu_mask
, false, false);
1317 m68k_emit_movem (stack_pointer_rtx
, 0,
1318 current_frame
.fpu_no
, FP0_REG
,
1319 current_frame
.fpu_mask
, false, true);
1322 m68k_emit_movem (frame_pointer_rtx
,
1323 -(current_frame
.foffset
+ fsize
),
1324 current_frame
.fpu_no
, FP0_REG
,
1325 current_frame
.fpu_mask
, false, false);
1328 if (frame_pointer_needed
)
1329 emit_insn (gen_unlink (frame_pointer_rtx
));
1330 else if (fsize_with_regs
)
1331 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1333 GEN_INT (fsize_with_regs
)));
1335 if (crtl
->calls_eh_return
)
1336 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1338 EH_RETURN_STACKADJ_RTX
));
1341 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
1344 /* Return true if X is a valid comparison operator for the dbcc
1347 Note it rejects floating point comparison operators.
1348 (In the future we could use Fdbcc).
1350 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1353 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1355 switch (GET_CODE (x
))
1357 case EQ
: case NE
: case GTU
: case LTU
:
1361 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1363 case GT
: case LT
: case GE
: case LE
:
1364 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1370 /* Return nonzero if flags are currently in the 68881 flag register. */
1372 flags_in_68881 (void)
1374 /* We could add support for these in the future */
1375 return cc_status
.flags
& CC_IN_68881
;
1378 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1381 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1383 enum m68k_function_kind kind
;
1385 /* We cannot use sibcalls for nested functions because we use the
1386 static chain register for indirect calls. */
1387 if (CALL_EXPR_STATIC_CHAIN (exp
))
1390 kind
= m68k_get_function_kind (current_function_decl
);
1391 if (kind
== m68k_fk_normal_function
)
1392 /* We can always sibcall from a normal function, because it's
1393 undefined if it is calling an interrupt function. */
1396 /* Otherwise we can only sibcall if the function kind is known to be
1398 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1404 /* Convert X to a legitimate function call memory reference and return the
1408 m68k_legitimize_call_address (rtx x
)
1410 gcc_assert (MEM_P (x
));
1411 if (call_operand (XEXP (x
, 0), VOIDmode
))
1413 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1416 /* Likewise for sibling calls. */
1419 m68k_legitimize_sibcall_address (rtx x
)
1421 gcc_assert (MEM_P (x
));
1422 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1425 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1426 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1429 /* Convert X to a legitimate address and return it if successful. Otherwise
1432 For the 68000, we handle X+REG by loading X into a register R and
1433 using R+REG. R will go in an address reg and indexing will be used.
1434 However, if REG is a broken-out memory address or multiplication,
1435 nothing needs to be done because REG can certainly go in an address reg. */
1438 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1440 if (GET_CODE (x
) == PLUS
)
1442 int ch
= (x
) != (oldx
);
1445 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1447 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1450 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1452 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1455 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1459 if (GET_CODE (XEXP (x
, 1)) == REG
1460 && GET_CODE (XEXP (x
, 0)) == REG
)
1462 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1465 x
= force_operand (x
, 0);
1469 if (memory_address_p (mode
, x
))
1472 if (GET_CODE (XEXP (x
, 0)) == REG
1473 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1474 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1475 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1477 rtx temp
= gen_reg_rtx (Pmode
);
1478 rtx val
= force_operand (XEXP (x
, 1), 0);
1479 emit_move_insn (temp
, val
);
1482 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1483 && GET_CODE (XEXP (x
, 0)) == REG
)
1484 x
= force_operand (x
, 0);
1486 else if (GET_CODE (XEXP (x
, 1)) == REG
1487 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1488 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1489 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1491 rtx temp
= gen_reg_rtx (Pmode
);
1492 rtx val
= force_operand (XEXP (x
, 0), 0);
1493 emit_move_insn (temp
, val
);
1496 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1497 && GET_CODE (XEXP (x
, 1)) == REG
)
1498 x
= force_operand (x
, 0);
1506 /* Output a dbCC; jCC sequence. Note we do not handle the
1507 floating point version of this sequence (Fdbcc). We also
1508 do not handle alternative conditions when CC_NO_OVERFLOW is
1509 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1510 kick those out before we get here. */
1513 output_dbcc_and_branch (rtx
*operands
)
1515 switch (GET_CODE (operands
[3]))
1518 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1522 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1526 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1530 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1534 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1538 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1542 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1546 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1550 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1554 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1561 /* If the decrement is to be done in SImode, then we have
1562 to compensate for the fact that dbcc decrements in HImode. */
1563 switch (GET_MODE (operands
[0]))
1566 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1578 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1581 enum rtx_code op_code
= GET_CODE (op
);
1583 /* This does not produce a useful cc. */
1586 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1587 below. Swap the operands and change the op if these requirements
1588 are not fulfilled. */
1589 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1593 operand1
= operand2
;
1595 op_code
= swap_condition (op_code
);
1597 loperands
[0] = operand1
;
1598 if (GET_CODE (operand1
) == REG
)
1599 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1601 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1602 if (operand2
!= const0_rtx
)
1604 loperands
[2] = operand2
;
1605 if (GET_CODE (operand2
) == REG
)
1606 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1608 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1610 loperands
[4] = gen_label_rtx ();
1611 if (operand2
!= const0_rtx
)
1612 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1615 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1616 output_asm_insn ("tst%.l %0", loperands
);
1618 output_asm_insn ("cmp%.w #0,%0", loperands
);
1620 output_asm_insn ("jne %l4", loperands
);
1622 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1623 output_asm_insn ("tst%.l %1", loperands
);
1625 output_asm_insn ("cmp%.w #0,%1", loperands
);
1628 loperands
[5] = dest
;
1633 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1634 CODE_LABEL_NUMBER (loperands
[4]));
1635 output_asm_insn ("seq %5", loperands
);
1639 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1640 CODE_LABEL_NUMBER (loperands
[4]));
1641 output_asm_insn ("sne %5", loperands
);
1645 loperands
[6] = gen_label_rtx ();
1646 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1647 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1648 CODE_LABEL_NUMBER (loperands
[4]));
1649 output_asm_insn ("sgt %5", loperands
);
1650 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1651 CODE_LABEL_NUMBER (loperands
[6]));
1655 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1656 CODE_LABEL_NUMBER (loperands
[4]));
1657 output_asm_insn ("shi %5", loperands
);
1661 loperands
[6] = gen_label_rtx ();
1662 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1663 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1664 CODE_LABEL_NUMBER (loperands
[4]));
1665 output_asm_insn ("slt %5", loperands
);
1666 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1667 CODE_LABEL_NUMBER (loperands
[6]));
1671 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1672 CODE_LABEL_NUMBER (loperands
[4]));
1673 output_asm_insn ("scs %5", loperands
);
1677 loperands
[6] = gen_label_rtx ();
1678 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1679 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1680 CODE_LABEL_NUMBER (loperands
[4]));
1681 output_asm_insn ("sge %5", loperands
);
1682 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1683 CODE_LABEL_NUMBER (loperands
[6]));
1687 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1688 CODE_LABEL_NUMBER (loperands
[4]));
1689 output_asm_insn ("scc %5", loperands
);
1693 loperands
[6] = gen_label_rtx ();
1694 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1695 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1696 CODE_LABEL_NUMBER (loperands
[4]));
1697 output_asm_insn ("sle %5", loperands
);
1698 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1699 CODE_LABEL_NUMBER (loperands
[6]));
1703 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1704 CODE_LABEL_NUMBER (loperands
[4]));
1705 output_asm_insn ("sls %5", loperands
);
1715 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1717 operands
[0] = countop
;
1718 operands
[1] = dataop
;
1720 if (GET_CODE (countop
) == CONST_INT
)
1722 register int count
= INTVAL (countop
);
1723 /* If COUNT is bigger than size of storage unit in use,
1724 advance to the containing unit of same size. */
1725 if (count
> signpos
)
1727 int offset
= (count
& ~signpos
) / 8;
1728 count
= count
& signpos
;
1729 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1731 if (count
== signpos
)
1732 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1734 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1736 /* These three statements used to use next_insns_test_no...
1737 but it appears that this should do the same job. */
1739 && next_insn_tests_no_inequality (insn
))
1742 && next_insn_tests_no_inequality (insn
))
1745 && next_insn_tests_no_inequality (insn
))
1747 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1748 On some m68k variants unfortunately that's slower than btst.
1749 On 68000 and higher, that should also work for all HImode operands. */
1750 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1752 if (count
== 3 && DATA_REG_P (operands
[1])
1753 && next_insn_tests_no_inequality (insn
))
1755 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1756 return "move%.w %1,%%ccr";
1758 if (count
== 2 && DATA_REG_P (operands
[1])
1759 && next_insn_tests_no_inequality (insn
))
1761 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1762 return "move%.w %1,%%ccr";
1764 /* count == 1 followed by bvc/bvs and
1765 count == 0 followed by bcc/bcs are also possible, but need
1766 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1769 cc_status
.flags
= CC_NOT_NEGATIVE
;
1771 return "btst %0,%1";
1774 /* Return true if X is a legitimate base register. STRICT_P says
1775 whether we need strict checking. */
1778 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1780 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1781 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1786 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1787 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1790 /* Return true if X is a legitimate index register. STRICT_P says
1791 whether we need strict checking. */
1794 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1796 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1801 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1802 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1805 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1806 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1807 ADDRESS if so. STRICT_P says whether we need strict checking. */
1810 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1814 /* Check for a scale factor. */
1816 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1817 && GET_CODE (x
) == MULT
1818 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1819 && (INTVAL (XEXP (x
, 1)) == 2
1820 || INTVAL (XEXP (x
, 1)) == 4
1821 || (INTVAL (XEXP (x
, 1)) == 8
1822 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1824 scale
= INTVAL (XEXP (x
, 1));
1828 /* Check for a word extension. */
1829 if (!TARGET_COLDFIRE
1830 && GET_CODE (x
) == SIGN_EXTEND
1831 && GET_MODE (XEXP (x
, 0)) == HImode
)
1834 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1836 address
->scale
= scale
;
1844 /* Return true if X is an illegitimate symbolic constant. */
1847 m68k_illegitimate_symbolic_constant_p (rtx x
)
1851 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1853 split_const (x
, &base
, &offset
);
1854 if (GET_CODE (base
) == SYMBOL_REF
1855 && !offset_within_block_p (base
, INTVAL (offset
)))
1861 /* Return true if X is a legitimate constant address that can reach
1862 bytes in the range [X, X + REACH). STRICT_P says whether we need
1866 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1870 if (!CONSTANT_ADDRESS_P (x
))
1874 && !(strict_p
&& TARGET_PCREL
)
1875 && symbolic_operand (x
, VOIDmode
))
1878 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1880 split_const (x
, &base
, &offset
);
1881 if (GET_CODE (base
) == SYMBOL_REF
1882 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1889 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1890 labels will become jump tables. */
1893 m68k_jump_table_ref_p (rtx x
)
1895 if (GET_CODE (x
) != LABEL_REF
)
1899 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1902 x
= next_nonnote_insn (x
);
1903 return x
&& JUMP_TABLE_DATA_P (x
);
1906 /* Return true if X is a legitimate address for values of mode MODE.
1907 STRICT_P says whether strict checking is needed. If the address
1908 is valid, describe its components in *ADDRESS. */
1911 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1912 bool strict_p
, struct m68k_address
*address
)
1916 memset (address
, 0, sizeof (*address
));
1918 if (mode
== BLKmode
)
1921 reach
= GET_MODE_SIZE (mode
);
1923 /* Check for (An) (mode 2). */
1924 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1930 /* Check for -(An) and (An)+ (modes 3 and 4). */
1931 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1932 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1934 address
->code
= GET_CODE (x
);
1935 address
->base
= XEXP (x
, 0);
1939 /* Check for (d16,An) (mode 5). */
1940 if (GET_CODE (x
) == PLUS
1941 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1942 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1943 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1945 address
->base
= XEXP (x
, 0);
1946 address
->offset
= XEXP (x
, 1);
1950 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1951 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1954 && GET_CODE (x
) == PLUS
1955 && XEXP (x
, 0) == pic_offset_table_rtx
1956 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1957 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1959 address
->base
= XEXP (x
, 0);
1960 address
->offset
= XEXP (x
, 1);
1964 /* The ColdFire FPU only accepts addressing modes 2-5. */
1965 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1968 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1969 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1970 All these modes are variations of mode 7. */
1971 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1973 address
->offset
= x
;
1977 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1980 ??? do_tablejump creates these addresses before placing the target
1981 label, so we have to assume that unplaced labels are jump table
1982 references. It seems unlikely that we would ever generate indexed
1983 accesses to unplaced labels in other cases. */
1984 if (GET_CODE (x
) == PLUS
1985 && m68k_jump_table_ref_p (XEXP (x
, 1))
1986 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1988 address
->offset
= XEXP (x
, 1);
1992 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1993 (bd,An,Xn.SIZE*SCALE) addresses. */
1997 /* Check for a nonzero base displacement. */
1998 if (GET_CODE (x
) == PLUS
1999 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2001 address
->offset
= XEXP (x
, 1);
2005 /* Check for a suppressed index register. */
2006 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2012 /* Check for a suppressed base register. Do not allow this case
2013 for non-symbolic offsets as it effectively gives gcc freedom
2014 to treat data registers as base registers, which can generate
2017 && symbolic_operand (address
->offset
, VOIDmode
)
2018 && m68k_decompose_index (x
, strict_p
, address
))
2023 /* Check for a nonzero base displacement. */
2024 if (GET_CODE (x
) == PLUS
2025 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2026 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2028 address
->offset
= XEXP (x
, 1);
2033 /* We now expect the sum of a base and an index. */
2034 if (GET_CODE (x
) == PLUS
)
2036 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2037 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2039 address
->base
= XEXP (x
, 0);
2043 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2044 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2046 address
->base
= XEXP (x
, 1);
2053 /* Return true if X is a legitimate address for values of mode MODE.
2054 STRICT_P says whether strict checking is needed. */
2057 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2059 struct m68k_address address
;
2061 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2064 /* Return true if X is a memory, describing its address in ADDRESS if so.
2065 Apply strict checking if called during or after reload. */
2068 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2071 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2072 reload_in_progress
|| reload_completed
,
2076 /* Return true if X matches the 'Q' constraint. It must be a memory
2077 with a base address and no constant offset or index. */
2080 m68k_matches_q_p (rtx x
)
2082 struct m68k_address address
;
2084 return (m68k_legitimate_mem_p (x
, &address
)
2085 && address
.code
== UNKNOWN
2091 /* Return true if X matches the 'U' constraint. It must be a base address
2092 with a constant offset and no index. */
2095 m68k_matches_u_p (rtx x
)
2097 struct m68k_address address
;
2099 return (m68k_legitimate_mem_p (x
, &address
)
2100 && address
.code
== UNKNOWN
2106 /* Legitimize PIC addresses. If the address is already
2107 position-independent, we return ORIG. Newly generated
2108 position-independent addresses go to REG. If we need more
2109 than one register, we lose.
2111 An address is legitimized by making an indirect reference
2112 through the Global Offset Table with the name of the symbol
2115 The assembler and linker are responsible for placing the
2116 address of the symbol in the GOT. The function prologue
2117 is responsible for initializing a5 to the starting address
2120 The assembler is also responsible for translating a symbol name
2121 into a constant displacement from the start of the GOT.
2123 A quick example may make things a little clearer:
2125 When not generating PIC code to store the value 12345 into _foo
2126 we would generate the following code:
2130 When generating PIC two transformations are made. First, the compiler
2131 loads the address of foo into a register. So the first transformation makes:
2136 The code in movsi will intercept the lea instruction and call this
2137 routine which will transform the instructions into:
2139 movel a5@(_foo:w), a0
2143 That (in a nutshell) is how *all* symbol and label references are
2147 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2152 /* First handle a simple SYMBOL_REF or LABEL_REF */
2153 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2157 if (TARGET_COLDFIRE
&& TARGET_XGOT
)
2158 /* When compiling with -mxgot switch the code for the above
2159 example will look like this:
2164 movel #12345, a0@ */
2168 /* Wrap ORIG in UNSPEC_GOTOFF to tip m68k_output_addr_const_extra
2169 to put @GOT after reference. */
2170 pic_offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, orig
),
2172 pic_offset
= gen_rtx_CONST (Pmode
, pic_offset
);
2173 emit_move_insn (reg
, pic_offset
);
2174 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
2175 pic_ref
= gen_rtx_MEM (Pmode
, reg
);
2178 pic_ref
= gen_rtx_MEM (Pmode
,
2179 gen_rtx_PLUS (Pmode
,
2180 pic_offset_table_rtx
, orig
));
2181 crtl
->uses_pic_offset_table
= 1;
2182 MEM_READONLY_P (pic_ref
) = 1;
2183 emit_move_insn (reg
, pic_ref
);
2186 else if (GET_CODE (orig
) == CONST
)
2190 /* Make sure this has not already been legitimized. */
2191 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2192 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2197 /* legitimize both operands of the PLUS */
2198 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2200 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2201 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2202 base
== reg
? 0 : reg
);
2204 if (GET_CODE (orig
) == CONST_INT
)
2205 return plus_constant (base
, INTVAL (orig
));
2206 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2207 /* Likewise, should we set special REG_NOTEs here? */
2214 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2216 /* Return the type of move that should be used for integer I. */
2219 m68k_const_method (HOST_WIDE_INT i
)
2226 /* The ColdFire doesn't have byte or word operations. */
2227 /* FIXME: This may not be useful for the m68060 either. */
2228 if (!TARGET_COLDFIRE
)
2230 /* if -256 < N < 256 but N is not in range for a moveq
2231 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2232 if (USE_MOVQ (i
^ 0xff))
2234 /* Likewise, try with not.w */
2235 if (USE_MOVQ (i
^ 0xffff))
2237 /* This is the only value where neg.w is useful */
2242 /* Try also with swap. */
2244 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2249 /* Try using MVZ/MVS with an immediate value to load constants. */
2250 if (i
>= 0 && i
<= 65535)
2252 if (i
>= -32768 && i
<= 32767)
2256 /* Otherwise, use move.l */
2260 /* Return the cost of moving constant I into a data register. */
2263 const_int_cost (HOST_WIDE_INT i
)
2265 switch (m68k_const_method (i
))
2268 /* Constants between -128 and 127 are cheap due to moveq. */
2276 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2286 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2287 bool speed ATTRIBUTE_UNUSED
)
2292 /* Constant zero is super cheap due to clr instruction. */
2293 if (x
== const0_rtx
)
2296 *total
= const_int_cost (INTVAL (x
));
2306 /* Make 0.0 cheaper than other floating constants to
2307 encourage creating tstsf and tstdf insns. */
2308 if (outer_code
== COMPARE
2309 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2315 /* These are vaguely right for a 68020. */
2316 /* The costs for long multiply have been adjusted to work properly
2317 in synth_mult on the 68020, relative to an average of the time
2318 for add and the time for shift, taking away a little more because
2319 sometimes move insns are needed. */
2320 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2325 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2326 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2328 : TARGET_COLDFIRE ? 3 : 13)
2333 : TUNE_68000_10 ? 5 \
2334 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2335 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2337 : TARGET_COLDFIRE ? 2 : 8)
2340 (TARGET_CF_HWDIV ? 11 \
2341 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2344 /* An lea costs about three times as much as a simple add. */
2345 if (GET_MODE (x
) == SImode
2346 && GET_CODE (XEXP (x
, 1)) == REG
2347 && GET_CODE (XEXP (x
, 0)) == MULT
2348 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2349 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2350 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2351 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2352 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2354 /* lea an@(dx:l:i),am */
2355 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2365 *total
= COSTS_N_INSNS(1);
2370 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2372 if (INTVAL (XEXP (x
, 1)) < 16)
2373 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2375 /* We're using clrw + swap for these cases. */
2376 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2379 *total
= COSTS_N_INSNS (10); /* Worst case. */
2382 /* A shift by a big integer takes an extra instruction. */
2383 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2384 && (INTVAL (XEXP (x
, 1)) == 16))
2386 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2389 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2390 && !(INTVAL (XEXP (x
, 1)) > 0
2391 && INTVAL (XEXP (x
, 1)) <= 8))
2393 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2399 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2400 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2401 && GET_MODE (x
) == SImode
)
2402 *total
= COSTS_N_INSNS (MULW_COST
);
2403 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2404 *total
= COSTS_N_INSNS (MULW_COST
);
2406 *total
= COSTS_N_INSNS (MULL_COST
);
2413 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2414 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2415 else if (TARGET_CF_HWDIV
)
2416 *total
= COSTS_N_INSNS (18);
2418 *total
= COSTS_N_INSNS (43); /* div.l */
2426 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2430 output_move_const_into_data_reg (rtx
*operands
)
2434 i
= INTVAL (operands
[1]);
2435 switch (m68k_const_method (i
))
2438 return "mvzw %1,%0";
2440 return "mvsw %1,%0";
2442 return "moveq %1,%0";
2445 operands
[1] = GEN_INT (i
^ 0xff);
2446 return "moveq %1,%0\n\tnot%.b %0";
2449 operands
[1] = GEN_INT (i
^ 0xffff);
2450 return "moveq %1,%0\n\tnot%.w %0";
2453 return "moveq #-128,%0\n\tneg%.w %0";
2458 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2459 return "moveq %1,%0\n\tswap %0";
2462 return "move%.l %1,%0";
2468 /* Return true if I can be handled by ISA B's mov3q instruction. */
2471 valid_mov3q_const (HOST_WIDE_INT i
)
2473 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2476 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2477 I is the value of OPERANDS[1]. */
2480 output_move_simode_const (rtx
*operands
)
2486 src
= INTVAL (operands
[1]);
2488 && (DATA_REG_P (dest
) || MEM_P (dest
))
2489 /* clr insns on 68000 read before writing. */
2490 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2491 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2493 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2494 return "mov3q%.l %1,%0";
2495 else if (src
== 0 && ADDRESS_REG_P (dest
))
2496 return "sub%.l %0,%0";
2497 else if (DATA_REG_P (dest
))
2498 return output_move_const_into_data_reg (operands
);
2499 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2501 if (valid_mov3q_const (src
))
2502 return "mov3q%.l %1,%0";
2503 return "move%.w %1,%0";
2505 else if (MEM_P (dest
)
2506 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2507 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2508 && IN_RANGE (src
, -0x8000, 0x7fff))
2510 if (valid_mov3q_const (src
))
2511 return "mov3q%.l %1,%-";
2514 return "move%.l %1,%0";
2518 output_move_simode (rtx
*operands
)
2520 if (GET_CODE (operands
[1]) == CONST_INT
)
2521 return output_move_simode_const (operands
);
2522 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2523 || GET_CODE (operands
[1]) == CONST
)
2524 && push_operand (operands
[0], SImode
))
2526 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2527 || GET_CODE (operands
[1]) == CONST
)
2528 && ADDRESS_REG_P (operands
[0]))
2529 return "lea %a1,%0";
2530 return "move%.l %1,%0";
2534 output_move_himode (rtx
*operands
)
2536 if (GET_CODE (operands
[1]) == CONST_INT
)
2538 if (operands
[1] == const0_rtx
2539 && (DATA_REG_P (operands
[0])
2540 || GET_CODE (operands
[0]) == MEM
)
2541 /* clr insns on 68000 read before writing. */
2542 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2543 || !(GET_CODE (operands
[0]) == MEM
2544 && MEM_VOLATILE_P (operands
[0]))))
2546 else if (operands
[1] == const0_rtx
2547 && ADDRESS_REG_P (operands
[0]))
2548 return "sub%.l %0,%0";
2549 else if (DATA_REG_P (operands
[0])
2550 && INTVAL (operands
[1]) < 128
2551 && INTVAL (operands
[1]) >= -128)
2552 return "moveq %1,%0";
2553 else if (INTVAL (operands
[1]) < 0x8000
2554 && INTVAL (operands
[1]) >= -0x8000)
2555 return "move%.w %1,%0";
2557 else if (CONSTANT_P (operands
[1]))
2558 return "move%.l %1,%0";
2559 return "move%.w %1,%0";
2563 output_move_qimode (rtx
*operands
)
2565 /* 68k family always modifies the stack pointer by at least 2, even for
2566 byte pushes. The 5200 (ColdFire) does not do this. */
2568 /* This case is generated by pushqi1 pattern now. */
2569 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2570 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2571 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2572 && ! ADDRESS_REG_P (operands
[1])
2573 && ! TARGET_COLDFIRE
));
2575 /* clr and st insns on 68000 read before writing. */
2576 if (!ADDRESS_REG_P (operands
[0])
2577 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2578 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2580 if (operands
[1] == const0_rtx
)
2582 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2583 && GET_CODE (operands
[1]) == CONST_INT
2584 && (INTVAL (operands
[1]) & 255) == 255)
2590 if (GET_CODE (operands
[1]) == CONST_INT
2591 && DATA_REG_P (operands
[0])
2592 && INTVAL (operands
[1]) < 128
2593 && INTVAL (operands
[1]) >= -128)
2594 return "moveq %1,%0";
2595 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2596 return "sub%.l %0,%0";
2597 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2598 return "move%.l %1,%0";
2599 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2600 from address registers. */
2601 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2602 return "move%.w %1,%0";
2603 return "move%.b %1,%0";
2607 output_move_stricthi (rtx
*operands
)
2609 if (operands
[1] == const0_rtx
2610 /* clr insns on 68000 read before writing. */
2611 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2612 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2614 return "move%.w %1,%0";
2618 output_move_strictqi (rtx
*operands
)
2620 if (operands
[1] == const0_rtx
2621 /* clr insns on 68000 read before writing. */
2622 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2623 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2625 return "move%.b %1,%0";
2628 /* Return the best assembler insn template
2629 for moving operands[1] into operands[0] as a fullword. */
2632 singlemove_string (rtx
*operands
)
2634 if (GET_CODE (operands
[1]) == CONST_INT
)
2635 return output_move_simode_const (operands
);
2636 return "move%.l %1,%0";
2640 /* Output assembler or rtl code to perform a doubleword move insn
2641 with operands OPERANDS.
2642 Pointers to 3 helper functions should be specified:
2643 HANDLE_REG_ADJUST to adjust a register by a small value,
2644 HANDLE_COMPADR to compute an address and
2645 HANDLE_MOVSI to move 4 bytes. */
2648 handle_move_double (rtx operands
[2],
2649 void (*handle_reg_adjust
) (rtx
, int),
2650 void (*handle_compadr
) (rtx
[2]),
2651 void (*handle_movsi
) (rtx
[2]))
2655 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2660 rtx addreg0
= 0, addreg1
= 0;
2661 int dest_overlapped_low
= 0;
2662 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2667 /* First classify both operands. */
2669 if (REG_P (operands
[0]))
2671 else if (offsettable_memref_p (operands
[0]))
2673 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2675 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2677 else if (GET_CODE (operands
[0]) == MEM
)
2682 if (REG_P (operands
[1]))
2684 else if (CONSTANT_P (operands
[1]))
2686 else if (offsettable_memref_p (operands
[1]))
2688 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2690 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2692 else if (GET_CODE (operands
[1]) == MEM
)
2697 /* Check for the cases that the operand constraints are not supposed
2698 to allow to happen. Generating code for these cases is
2700 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2702 /* If one operand is decrementing and one is incrementing
2703 decrement the former register explicitly
2704 and change that operand into ordinary indexing. */
2706 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2708 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2710 handle_reg_adjust (operands
[0], -size
);
2712 if (GET_MODE (operands
[1]) == XFmode
)
2713 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2714 else if (GET_MODE (operands
[0]) == DFmode
)
2715 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2717 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2720 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2722 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2724 handle_reg_adjust (operands
[1], -size
);
2726 if (GET_MODE (operands
[1]) == XFmode
)
2727 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2728 else if (GET_MODE (operands
[1]) == DFmode
)
2729 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2731 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2735 /* If an operand is an unoffsettable memory ref, find a register
2736 we can increment temporarily to make it refer to the second word. */
2738 if (optype0
== MEMOP
)
2739 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2741 if (optype1
== MEMOP
)
2742 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2744 /* Ok, we can do one word at a time.
2745 Normally we do the low-numbered word first,
2746 but if either operand is autodecrementing then we
2747 do the high-numbered word first.
2749 In either case, set up in LATEHALF the operands to use
2750 for the high-numbered word and in some cases alter the
2751 operands in OPERANDS to be suitable for the low-numbered word. */
2755 if (optype0
== REGOP
)
2757 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2758 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2760 else if (optype0
== OFFSOP
)
2762 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2763 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2767 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
2768 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
2771 if (optype1
== REGOP
)
2773 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2774 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2776 else if (optype1
== OFFSOP
)
2778 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2779 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2781 else if (optype1
== CNSTOP
)
2783 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2788 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2789 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2790 operands
[1] = GEN_INT (l
[0]);
2791 middlehalf
[1] = GEN_INT (l
[1]);
2792 latehalf
[1] = GEN_INT (l
[2]);
2796 /* No non-CONST_DOUBLE constant should ever appear
2798 gcc_assert (!CONSTANT_P (operands
[1]));
2803 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
2804 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
2808 /* size is not 12: */
2810 if (optype0
== REGOP
)
2811 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2812 else if (optype0
== OFFSOP
)
2813 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2815 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
2817 if (optype1
== REGOP
)
2818 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2819 else if (optype1
== OFFSOP
)
2820 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2821 else if (optype1
== CNSTOP
)
2822 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2824 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
2827 /* If insn is effectively movd N(sp),-(sp) then we will do the
2828 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2829 for the low word as well, to compensate for the first decrement of sp. */
2830 if (optype0
== PUSHOP
2831 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2832 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2833 operands
[1] = middlehalf
[1] = latehalf
[1];
2835 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2836 if the upper part of reg N does not appear in the MEM, arrange to
2837 emit the move late-half first. Otherwise, compute the MEM address
2838 into the upper part of N and use that as a pointer to the memory
2840 if (optype0
== REGOP
2841 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2843 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2845 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2846 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2848 /* If both halves of dest are used in the src memory address,
2849 compute the address into latehalf of dest.
2850 Note that this can't happen if the dest is two data regs. */
2852 xops
[0] = latehalf
[0];
2853 xops
[1] = XEXP (operands
[1], 0);
2855 handle_compadr (xops
);
2856 if (GET_MODE (operands
[1]) == XFmode
)
2858 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2859 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2860 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2864 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2865 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2869 && reg_overlap_mentioned_p (middlehalf
[0],
2870 XEXP (operands
[1], 0)))
2872 /* Check for two regs used by both source and dest.
2873 Note that this can't happen if the dest is all data regs.
2874 It can happen if the dest is d6, d7, a0.
2875 But in that case, latehalf is an addr reg, so
2876 the code at compadr does ok. */
2878 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2879 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2882 /* JRV says this can't happen: */
2883 gcc_assert (!addreg0
&& !addreg1
);
2885 /* Only the middle reg conflicts; simply put it last. */
2886 handle_movsi (operands
);
2887 handle_movsi (latehalf
);
2888 handle_movsi (middlehalf
);
2892 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2893 /* If the low half of dest is mentioned in the source memory
2894 address, the arrange to emit the move late half first. */
2895 dest_overlapped_low
= 1;
2898 /* If one or both operands autodecrementing,
2899 do the two words, high-numbered first. */
2901 /* Likewise, the first move would clobber the source of the second one,
2902 do them in the other order. This happens only for registers;
2903 such overlap can't happen in memory unless the user explicitly
2904 sets it up, and that is an undefined circumstance. */
2906 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2907 || (optype0
== REGOP
&& optype1
== REGOP
2908 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2909 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2910 || dest_overlapped_low
)
2912 /* Make any unoffsettable addresses point at high-numbered word. */
2914 handle_reg_adjust (addreg0
, size
- 4);
2916 handle_reg_adjust (addreg1
, size
- 4);
2919 handle_movsi (latehalf
);
2921 /* Undo the adds we just did. */
2923 handle_reg_adjust (addreg0
, -4);
2925 handle_reg_adjust (addreg1
, -4);
2929 handle_movsi (middlehalf
);
2932 handle_reg_adjust (addreg0
, -4);
2934 handle_reg_adjust (addreg1
, -4);
2937 /* Do low-numbered word. */
2939 handle_movsi (operands
);
2943 /* Normal case: do the two words, low-numbered first. */
2945 handle_movsi (operands
);
2947 /* Do the middle one of the three words for long double */
2951 handle_reg_adjust (addreg0
, 4);
2953 handle_reg_adjust (addreg1
, 4);
2955 handle_movsi (middlehalf
);
2958 /* Make any unoffsettable addresses point at high-numbered word. */
2960 handle_reg_adjust (addreg0
, 4);
2962 handle_reg_adjust (addreg1
, 4);
2965 handle_movsi (latehalf
);
2967 /* Undo the adds we just did. */
2969 handle_reg_adjust (addreg0
, -(size
- 4));
2971 handle_reg_adjust (addreg1
, -(size
- 4));
2976 /* Output assembler code to adjust REG by N. */
2978 output_reg_adjust (rtx reg
, int n
)
2982 gcc_assert (GET_MODE (reg
) == SImode
2983 && -12 <= n
&& n
!= 0 && n
<= 12);
2988 s
= "add%.l #12,%0";
2992 s
= "addq%.l #8,%0";
2996 s
= "addq%.l #4,%0";
3000 s
= "sub%.l #12,%0";
3004 s
= "subq%.l #8,%0";
3008 s
= "subq%.l #4,%0";
3016 output_asm_insn (s
, ®
);
3019 /* Emit rtl code to adjust REG by N. */
3021 emit_reg_adjust (rtx reg1
, int n
)
3025 gcc_assert (GET_MODE (reg1
) == SImode
3026 && -12 <= n
&& n
!= 0 && n
<= 12);
3028 reg1
= copy_rtx (reg1
);
3029 reg2
= copy_rtx (reg1
);
3032 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3034 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3039 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3041 output_compadr (rtx operands
[2])
3043 output_asm_insn ("lea %a1,%0", operands
);
3046 /* Output the best assembler insn for moving operands[1] into operands[0]
3049 output_movsi (rtx operands
[2])
3051 output_asm_insn (singlemove_string (operands
), operands
);
3054 /* Copy OP and change its mode to MODE. */
3056 copy_operand (rtx op
, enum machine_mode mode
)
3058 /* ??? This looks really ugly. There must be a better way
3059 to change a mode on the operand. */
3060 if (GET_MODE (op
) != VOIDmode
)
3063 op
= gen_rtx_REG (mode
, REGNO (op
));
3067 PUT_MODE (op
, mode
);
3074 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3076 emit_movsi (rtx operands
[2])
3078 operands
[0] = copy_operand (operands
[0], SImode
);
3079 operands
[1] = copy_operand (operands
[1], SImode
);
3081 emit_insn (gen_movsi (operands
[0], operands
[1]));
3084 /* Output assembler code to perform a doubleword move insn
3085 with operands OPERANDS. */
3087 output_move_double (rtx
*operands
)
3089 handle_move_double (operands
,
3090 output_reg_adjust
, output_compadr
, output_movsi
);
3095 /* Output rtl code to perform a doubleword move insn
3096 with operands OPERANDS. */
3098 m68k_emit_move_double (rtx operands
[2])
3100 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3103 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3104 new rtx with the correct mode. */
3107 force_mode (enum machine_mode mode
, rtx orig
)
3109 if (mode
== GET_MODE (orig
))
3112 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3115 return gen_rtx_REG (mode
, REGNO (orig
));
3119 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3121 return reg_renumber
&& FP_REG_P (op
);
3124 /* Emit insns to move operands[1] into operands[0].
3126 Return 1 if we have written out everything that needs to be done to
3127 do the move. Otherwise, return 0 and the caller will emit the move
3130 Note SCRATCH_REG may not be in the proper mode depending on how it
3131 will be used. This routine is responsible for creating a new copy
3132 of SCRATCH_REG in the proper mode. */
3135 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3137 register rtx operand0
= operands
[0];
3138 register rtx operand1
= operands
[1];
3142 && reload_in_progress
&& GET_CODE (operand0
) == REG
3143 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3144 operand0
= reg_equiv_mem
[REGNO (operand0
)];
3145 else if (scratch_reg
3146 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3147 && GET_CODE (SUBREG_REG (operand0
)) == REG
3148 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3150 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3151 the code which tracks sets/uses for delete_output_reload. */
3152 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3153 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
3154 SUBREG_BYTE (operand0
));
3155 operand0
= alter_subreg (&temp
);
3159 && reload_in_progress
&& GET_CODE (operand1
) == REG
3160 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3161 operand1
= reg_equiv_mem
[REGNO (operand1
)];
3162 else if (scratch_reg
3163 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3164 && GET_CODE (SUBREG_REG (operand1
)) == REG
3165 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3167 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3168 the code which tracks sets/uses for delete_output_reload. */
3169 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3170 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
3171 SUBREG_BYTE (operand1
));
3172 operand1
= alter_subreg (&temp
);
3175 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3176 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3177 != XEXP (operand0
, 0)))
3178 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3179 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3180 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3181 != XEXP (operand1
, 0)))
3182 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3184 /* Handle secondary reloads for loads/stores of FP registers where
3185 the address is symbolic by using the scratch register */
3186 if (fp_reg_operand (operand0
, mode
)
3187 && ((GET_CODE (operand1
) == MEM
3188 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3189 || ((GET_CODE (operand1
) == SUBREG
3190 && GET_CODE (XEXP (operand1
, 0)) == MEM
3191 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3194 if (GET_CODE (operand1
) == SUBREG
)
3195 operand1
= XEXP (operand1
, 0);
3197 /* SCRATCH_REG will hold an address. We want
3198 it in SImode regardless of what mode it was originally given
3200 scratch_reg
= force_mode (SImode
, scratch_reg
);
3202 /* D might not fit in 14 bits either; for such cases load D into
3204 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3206 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3207 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3209 XEXP (XEXP (operand1
, 0), 0),
3213 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3214 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3215 gen_rtx_MEM (mode
, scratch_reg
)));
3218 else if (fp_reg_operand (operand1
, mode
)
3219 && ((GET_CODE (operand0
) == MEM
3220 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3221 || ((GET_CODE (operand0
) == SUBREG
)
3222 && GET_CODE (XEXP (operand0
, 0)) == MEM
3223 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3226 if (GET_CODE (operand0
) == SUBREG
)
3227 operand0
= XEXP (operand0
, 0);
3229 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3230 it in SIMODE regardless of what mode it was originally given
3232 scratch_reg
= force_mode (SImode
, scratch_reg
);
3234 /* D might not fit in 14 bits either; for such cases load D into
3236 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3238 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3239 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3242 XEXP (XEXP (operand0
, 0),
3247 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3248 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3252 /* Handle secondary reloads for loads of FP registers from constant
3253 expressions by forcing the constant into memory.
3255 use scratch_reg to hold the address of the memory location.
3257 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3258 NO_REGS when presented with a const_int and an register class
3259 containing only FP registers. Doing so unfortunately creates
3260 more problems than it solves. Fix this for 2.5. */
3261 else if (fp_reg_operand (operand0
, mode
)
3262 && CONSTANT_P (operand1
)
3267 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3268 it in SIMODE regardless of what mode it was originally given
3270 scratch_reg
= force_mode (SImode
, scratch_reg
);
3272 /* Force the constant into memory and put the address of the
3273 memory location into scratch_reg. */
3274 xoperands
[0] = scratch_reg
;
3275 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3276 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3278 /* Now load the destination register. */
3279 emit_insn (gen_rtx_SET (mode
, operand0
,
3280 gen_rtx_MEM (mode
, scratch_reg
)));
3284 /* Now have insn-emit do whatever it normally does. */
3288 /* Split one or more DImode RTL references into pairs of SImode
3289 references. The RTL can be REG, offsettable MEM, integer constant, or
3290 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3291 split and "num" is its length. lo_half and hi_half are output arrays
3292 that parallel "operands". */
3295 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3299 rtx op
= operands
[num
];
3301 /* simplify_subreg refuses to split volatile memory addresses,
3302 but we still have to handle it. */
3303 if (GET_CODE (op
) == MEM
)
3305 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3306 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3310 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3311 GET_MODE (op
) == VOIDmode
3312 ? DImode
: GET_MODE (op
), 4);
3313 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3314 GET_MODE (op
) == VOIDmode
3315 ? DImode
: GET_MODE (op
), 0);
3320 /* Split X into a base and a constant offset, storing them in *BASE
3321 and *OFFSET respectively. */
3324 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3327 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3329 *offset
+= INTVAL (XEXP (x
, 1));
3335 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3336 instruction. STORE_P says whether the move is a load or store.
3338 If the instruction uses post-increment or pre-decrement addressing,
3339 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3340 adjustment. This adjustment will be made by the first element of
3341 PARALLEL, with the loads or stores starting at element 1. If the
3342 instruction does not use post-increment or pre-decrement addressing,
3343 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3344 start at element 0. */
3347 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3348 HOST_WIDE_INT automod_offset
, bool store_p
)
3350 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3351 HOST_WIDE_INT offset
, mem_offset
;
3353 enum reg_class rclass
;
3355 len
= XVECLEN (pattern
, 0);
3356 first
= (automod_base
!= NULL
);
3360 /* Stores must be pre-decrement and loads must be post-increment. */
3361 if (store_p
!= (automod_offset
< 0))
3364 /* Work out the base and offset for lowest memory location. */
3365 base
= automod_base
;
3366 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3370 /* Allow any valid base and offset in the first access. */
3377 for (i
= first
; i
< len
; i
++)
3379 /* We need a plain SET. */
3380 set
= XVECEXP (pattern
, 0, i
);
3381 if (GET_CODE (set
) != SET
)
3384 /* Check that we have a memory location... */
3385 mem
= XEXP (set
, !store_p
);
3386 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3389 /* ...with the right address. */
3392 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3393 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3394 There are no mode restrictions for 680x0 besides the
3395 automodification rules enforced above. */
3397 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3402 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3403 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3407 /* Check that we have a register of the required mode and class. */
3408 reg
= XEXP (set
, store_p
);
3410 || !HARD_REGISTER_P (reg
)
3411 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3416 /* The register must belong to RCLASS and have a higher number
3417 than the register in the previous SET. */
3418 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3419 || REGNO (last_reg
) >= REGNO (reg
))
3424 /* Work out which register class we need. */
3425 if (INT_REGNO_P (REGNO (reg
)))
3426 rclass
= GENERAL_REGS
;
3427 else if (FP_REGNO_P (REGNO (reg
)))
3434 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3437 /* If we have an automodification, check whether the final offset is OK. */
3438 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3441 /* Reject unprofitable cases. */
3442 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3448 /* Return the assembly code template for a movem or fmovem instruction
3449 whose pattern is given by PATTERN. Store the template's operands
3452 If the instruction uses post-increment or pre-decrement addressing,
3453 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3454 is true if this is a store instruction. */
3457 m68k_output_movem (rtx
*operands
, rtx pattern
,
3458 HOST_WIDE_INT automod_offset
, bool store_p
)
3463 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3465 first
= (automod_offset
!= 0);
3466 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3468 /* When using movem with pre-decrement addressing, register X + D0_REG
3469 is controlled by bit 15 - X. For all other addressing modes,
3470 register X + D0_REG is controlled by bit X. Confusingly, the
3471 register mask for fmovem is in the opposite order to that for
3475 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3476 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3477 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3478 if (automod_offset
< 0)
3480 if (FP_REGNO_P (regno
))
3481 mask
|= 1 << (regno
- FP0_REG
);
3483 mask
|= 1 << (15 - (regno
- D0_REG
));
3487 if (FP_REGNO_P (regno
))
3488 mask
|= 1 << (7 - (regno
- FP0_REG
));
3490 mask
|= 1 << (regno
- D0_REG
);
3495 if (automod_offset
== 0)
3496 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3497 else if (automod_offset
< 0)
3498 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3500 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3501 operands
[1] = GEN_INT (mask
);
3502 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3505 return "fmovem %1,%a0";
3507 return "fmovem %a0,%1";
3512 return "movem%.l %1,%a0";
3514 return "movem%.l %a0,%1";
3518 /* Return a REG that occurs in ADDR with coefficient 1.
3519 ADDR can be effectively incremented by incrementing REG. */
3522 find_addr_reg (rtx addr
)
3524 while (GET_CODE (addr
) == PLUS
)
3526 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3527 addr
= XEXP (addr
, 0);
3528 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3529 addr
= XEXP (addr
, 1);
3530 else if (CONSTANT_P (XEXP (addr
, 0)))
3531 addr
= XEXP (addr
, 1);
3532 else if (CONSTANT_P (XEXP (addr
, 1)))
3533 addr
= XEXP (addr
, 0);
3537 gcc_assert (GET_CODE (addr
) == REG
);
3541 /* Output assembler code to perform a 32-bit 3-operand add. */
3544 output_addsi3 (rtx
*operands
)
3546 if (! operands_match_p (operands
[0], operands
[1]))
3548 if (!ADDRESS_REG_P (operands
[1]))
3550 rtx tmp
= operands
[1];
3552 operands
[1] = operands
[2];
3556 /* These insns can result from reloads to access
3557 stack slots over 64k from the frame pointer. */
3558 if (GET_CODE (operands
[2]) == CONST_INT
3559 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3560 return "move%.l %2,%0\n\tadd%.l %1,%0";
3561 if (GET_CODE (operands
[2]) == REG
)
3562 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3563 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3565 if (GET_CODE (operands
[2]) == CONST_INT
)
3567 if (INTVAL (operands
[2]) > 0
3568 && INTVAL (operands
[2]) <= 8)
3569 return "addq%.l %2,%0";
3570 if (INTVAL (operands
[2]) < 0
3571 && INTVAL (operands
[2]) >= -8)
3573 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3574 return "subq%.l %2,%0";
3576 /* On the CPU32 it is faster to use two addql instructions to
3577 add a small integer (8 < N <= 16) to a register.
3578 Likewise for subql. */
3579 if (TUNE_CPU32
&& REG_P (operands
[0]))
3581 if (INTVAL (operands
[2]) > 8
3582 && INTVAL (operands
[2]) <= 16)
3584 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3585 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3587 if (INTVAL (operands
[2]) < -8
3588 && INTVAL (operands
[2]) >= -16)
3590 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3591 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3594 if (ADDRESS_REG_P (operands
[0])
3595 && INTVAL (operands
[2]) >= -0x8000
3596 && INTVAL (operands
[2]) < 0x8000)
3599 return "add%.w %2,%0";
3601 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3604 return "add%.l %2,%0";
3607 /* Store in cc_status the expressions that the condition codes will
3608 describe after execution of an instruction whose pattern is EXP.
3609 Do not alter them if the instruction would not alter the cc's. */
3611 /* On the 68000, all the insns to store in an address register fail to
3612 set the cc's. However, in some cases these instructions can make it
3613 possibly invalid to use the saved cc's. In those cases we clear out
3614 some or all of the saved cc's so they won't be used. */
3617 notice_update_cc (rtx exp
, rtx insn
)
3619 if (GET_CODE (exp
) == SET
)
3621 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3623 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3625 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3626 cc_status
.value1
= 0;
3627 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3628 cc_status
.value2
= 0;
3630 /* fmoves to memory or data registers do not set the condition
3631 codes. Normal moves _do_ set the condition codes, but not in
3632 a way that is appropriate for comparison with 0, because -0.0
3633 would be treated as a negative nonzero number. Note that it
3634 isn't appropriate to conditionalize this restriction on
3635 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3636 we care about the difference between -0.0 and +0.0. */
3637 else if (!FP_REG_P (SET_DEST (exp
))
3638 && SET_DEST (exp
) != cc0_rtx
3639 && (FP_REG_P (SET_SRC (exp
))
3640 || GET_CODE (SET_SRC (exp
)) == FIX
3641 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3643 /* A pair of move insns doesn't produce a useful overall cc. */
3644 else if (!FP_REG_P (SET_DEST (exp
))
3645 && !FP_REG_P (SET_SRC (exp
))
3646 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3647 && (GET_CODE (SET_SRC (exp
)) == REG
3648 || GET_CODE (SET_SRC (exp
)) == MEM
3649 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3651 else if (SET_DEST (exp
) != pc_rtx
)
3653 cc_status
.flags
= 0;
3654 cc_status
.value1
= SET_DEST (exp
);
3655 cc_status
.value2
= SET_SRC (exp
);
3658 else if (GET_CODE (exp
) == PARALLEL
3659 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3661 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3662 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3664 if (ADDRESS_REG_P (dest
))
3666 else if (dest
!= pc_rtx
)
3668 cc_status
.flags
= 0;
3669 cc_status
.value1
= dest
;
3670 cc_status
.value2
= src
;
3675 if (cc_status
.value2
!= 0
3676 && ADDRESS_REG_P (cc_status
.value2
)
3677 && GET_MODE (cc_status
.value2
) == QImode
)
3679 if (cc_status
.value2
!= 0)
3680 switch (GET_CODE (cc_status
.value2
))
3682 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3683 case ROTATE
: case ROTATERT
:
3684 /* These instructions always clear the overflow bit, and set
3685 the carry to the bit shifted out. */
3686 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
3689 case PLUS
: case MINUS
: case MULT
:
3690 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3691 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3692 cc_status
.flags
|= CC_NO_OVERFLOW
;
3695 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3696 ends with a move insn moving r2 in r2's mode.
3697 Thus, the cc's are set for r2.
3698 This can set N bit spuriously. */
3699 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3704 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3706 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3707 cc_status
.value2
= 0;
3708 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3709 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3710 cc_status
.flags
= CC_IN_68881
;
3711 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
3712 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
3714 cc_status
.flags
= CC_IN_68881
;
3715 if (!FP_REG_P (XEXP (cc_status
.value2
, 0)))
3716 cc_status
.flags
|= CC_REVERSED
;
3721 output_move_const_double (rtx
*operands
)
3723 int code
= standard_68881_constant_p (operands
[1]);
3727 static char buf
[40];
3729 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3732 return "fmove%.d %1,%0";
3736 output_move_const_single (rtx
*operands
)
3738 int code
= standard_68881_constant_p (operands
[1]);
3742 static char buf
[40];
3744 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3747 return "fmove%.s %f1,%0";
3750 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3751 from the "fmovecr" instruction.
3752 The value, anded with 0xff, gives the code to use in fmovecr
3753 to get the desired constant. */
3755 /* This code has been fixed for cross-compilation. */
3757 static int inited_68881_table
= 0;
3759 static const char *const strings_68881
[7] = {
3769 static const int codes_68881
[7] = {
3779 REAL_VALUE_TYPE values_68881
[7];
3781 /* Set up values_68881 array by converting the decimal values
3782 strings_68881 to binary. */
3785 init_68881_table (void)
3789 enum machine_mode mode
;
3792 for (i
= 0; i
< 7; i
++)
3796 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3797 values_68881
[i
] = r
;
3799 inited_68881_table
= 1;
3803 standard_68881_constant_p (rtx x
)
3808 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3809 used at all on those chips. */
3813 if (! inited_68881_table
)
3814 init_68881_table ();
3816 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3818 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3820 for (i
= 0; i
< 6; i
++)
3822 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3823 return (codes_68881
[i
]);
3826 if (GET_MODE (x
) == SFmode
)
3829 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3830 return (codes_68881
[6]);
3832 /* larger powers of ten in the constants ram are not used
3833 because they are not equal to a `double' C constant. */
3837 /* If X is a floating-point constant, return the logarithm of X base 2,
3838 or 0 if X is not a power of 2. */
3841 floating_exact_log2 (rtx x
)
3843 REAL_VALUE_TYPE r
, r1
;
3846 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3848 if (REAL_VALUES_LESS (r
, dconst1
))
3851 exp
= real_exponent (&r
);
3852 real_2expN (&r1
, exp
, DFmode
);
3853 if (REAL_VALUES_EQUAL (r1
, r
))
3859 /* A C compound statement to output to stdio stream STREAM the
3860 assembler syntax for an instruction operand X. X is an RTL
3863 CODE is a value that can be used to specify one of several ways
3864 of printing the operand. It is used when identical operands
3865 must be printed differently depending on the context. CODE
3866 comes from the `%' specification that was used to request
3867 printing of the operand. If the specification was just `%DIGIT'
3868 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3869 is the ASCII code for LTR.
3871 If X is a register, this macro should print the register's name.
3872 The names can be found in an array `reg_names' whose type is
3873 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3875 When the machine description has a specification `%PUNCT' (a `%'
3876 followed by a punctuation character), this macro is called with
3877 a null pointer for X and the punctuation character for CODE.
3879 The m68k specific codes are:
3881 '.' for dot needed in Motorola-style opcode names.
3882 '-' for an operand pushing on the stack:
3883 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3884 '+' for an operand pushing on the stack:
3885 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3886 '@' for a reference to the top word on the stack:
3887 sp@, (sp) or (%sp) depending on the style of syntax.
3888 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3889 but & in SGS syntax).
3890 '!' for the cc register (used in an `and to cc' insn).
3891 '$' for the letter `s' in an op code, but only on the 68040.
3892 '&' for the letter `d' in an op code, but only on the 68040.
3893 '/' for register prefix needed by longlong.h.
3894 '?' for m68k_library_id_string
3896 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3897 'd' to force memory addressing to be absolute, not relative.
3898 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3899 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3900 or print pair of registers as rx:ry.
3901 'p' print an address with @PLTPC attached, but only if the operand
3902 is not locally-bound. */
3905 print_operand (FILE *file
, rtx op
, int letter
)
3910 fprintf (file
, ".");
3912 else if (letter
== '#')
3913 asm_fprintf (file
, "%I");
3914 else if (letter
== '-')
3915 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3916 else if (letter
== '+')
3917 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3918 else if (letter
== '@')
3919 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3920 else if (letter
== '!')
3921 asm_fprintf (file
, "%Rfpcr");
3922 else if (letter
== '$')
3925 fprintf (file
, "s");
3927 else if (letter
== '&')
3930 fprintf (file
, "d");
3932 else if (letter
== '/')
3933 asm_fprintf (file
, "%R");
3934 else if (letter
== '?')
3935 asm_fprintf (file
, m68k_library_id_string
);
3936 else if (letter
== 'p')
3938 output_addr_const (file
, op
);
3939 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3940 fprintf (file
, "@PLTPC");
3942 else if (GET_CODE (op
) == REG
)
3945 /* Print out the second register name of a register pair.
3946 I.e., R (6) => 7. */
3947 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3949 fputs (M68K_REGNAME(REGNO (op
)), file
);
3951 else if (GET_CODE (op
) == MEM
)
3953 output_address (XEXP (op
, 0));
3954 if (letter
== 'd' && ! TARGET_68020
3955 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3956 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3957 && INTVAL (XEXP (op
, 0)) < 0x8000
3958 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3959 fprintf (file
, MOTOROLA
? ".l" : ":l");
3961 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3965 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3966 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
3967 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
3969 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3973 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3974 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3975 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
3976 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
3978 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3982 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3983 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
3984 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
3988 /* Use `print_operand_address' instead of `output_addr_const'
3989 to ensure that we print relevant PIC stuff. */
3990 asm_fprintf (file
, "%I");
3992 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3993 print_operand_address (file
, op
);
3995 output_addr_const (file
, op
);
3999 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
4002 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4004 if (GET_CODE (x
) != UNSPEC
|| XINT (x
, 1) != UNSPEC_GOTOFF
)
4007 output_addr_const (file
, XVECEXP (x
, 0, 0));
4008 /* ??? What is the non-MOTOROLA syntax? */
4009 fputs ("@GOT", file
);
4014 /* A C compound statement to output to stdio stream STREAM the
4015 assembler syntax for an instruction operand that is a memory
4016 reference whose address is ADDR. ADDR is an RTL expression.
4018 Note that this contains a kludge that knows that the only reason
4019 we have an address (plus (label_ref...) (reg...)) when not generating
4020 PIC code is in the insn before a tablejump, and we know that m68k.md
4021 generates a label LInnn: on such an insn.
4023 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4024 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4026 This routine is responsible for distinguishing between -fpic and -fPIC
4027 style relocations in an address. When generating -fpic code the
4028 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4029 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4032 print_operand_address (FILE *file
, rtx addr
)
4034 struct m68k_address address
;
4036 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4039 if (address
.code
== PRE_DEC
)
4040 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4041 M68K_REGNAME (REGNO (address
.base
)));
4042 else if (address
.code
== POST_INC
)
4043 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4044 M68K_REGNAME (REGNO (address
.base
)));
4045 else if (!address
.base
&& !address
.index
)
4047 /* A constant address. */
4048 gcc_assert (address
.offset
== addr
);
4049 if (GET_CODE (addr
) == CONST_INT
)
4051 /* (xxx).w or (xxx).l. */
4052 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4053 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4055 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4057 else if (TARGET_PCREL
)
4059 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4061 output_addr_const (file
, addr
);
4062 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4066 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4067 name ends in `.<letter>', as the last 2 characters can be
4068 mistaken as a size suffix. Put the name in parentheses. */
4069 if (GET_CODE (addr
) == SYMBOL_REF
4070 && strlen (XSTR (addr
, 0)) > 2
4071 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4074 output_addr_const (file
, addr
);
4078 output_addr_const (file
, addr
);
4085 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4086 label being accessed, otherwise it is -1. */
4087 labelno
= (address
.offset
4089 && GET_CODE (address
.offset
) == LABEL_REF
4090 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4094 /* Print the "offset(base" component. */
4096 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4101 output_addr_const (file
, address
.offset
);
4102 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
4104 fprintf (file
, "@GOT");
4105 if (flag_pic
== 1 && TARGET_68020
)
4106 fprintf (file
, ".w");
4111 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4113 /* Print the ",index" component, if any. */
4118 fprintf (file
, "%s.%c",
4119 M68K_REGNAME (REGNO (address
.index
)),
4120 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4121 if (address
.scale
!= 1)
4122 fprintf (file
, "*%d", address
.scale
);
4126 else /* !MOTOROLA */
4128 if (!address
.offset
&& !address
.index
)
4129 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4132 /* Print the "base@(offset" component. */
4134 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4138 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4139 fprintf (file
, "@(");
4142 output_addr_const (file
, address
.offset
);
4143 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
4147 fprintf (file
, ":w"); break;
4149 fprintf (file
, ":l"); break;
4155 /* Print the ",index" component, if any. */
4158 fprintf (file
, ",%s:%c",
4159 M68K_REGNAME (REGNO (address
.index
)),
4160 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4161 if (address
.scale
!= 1)
4162 fprintf (file
, ":%d", address
.scale
);
4170 /* Check for cases where a clr insns can be omitted from code using
4171 strict_low_part sets. For example, the second clrl here is not needed:
4172 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4174 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4175 insn we are checking for redundancy. TARGET is the register set by the
4179 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4184 while ((p
= PREV_INSN (p
)))
4186 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4192 /* If it isn't an insn, then give up. */
4196 if (reg_set_p (target
, p
))
4198 rtx set
= single_set (p
);
4201 /* If it isn't an easy to recognize insn, then give up. */
4205 dest
= SET_DEST (set
);
4207 /* If this sets the entire target register to zero, then our
4208 first_insn is redundant. */
4209 if (rtx_equal_p (dest
, target
)
4210 && SET_SRC (set
) == const0_rtx
)
4212 else if (GET_CODE (dest
) == STRICT_LOW_PART
4213 && GET_CODE (XEXP (dest
, 0)) == REG
4214 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4215 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4216 <= GET_MODE_SIZE (mode
)))
4217 /* This is a strict low part set which modifies less than
4218 we are using, so it is safe. */
4228 /* Operand predicates for implementing asymmetric pc-relative addressing
4229 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4230 when used as a source operand, but not as a destination operand.
4232 We model this by restricting the meaning of the basic predicates
4233 (general_operand, memory_operand, etc) to forbid the use of this
4234 addressing mode, and then define the following predicates that permit
4235 this addressing mode. These predicates can then be used for the
4236 source operands of the appropriate instructions.
4238 n.b. While it is theoretically possible to change all machine patterns
4239 to use this addressing more where permitted by the architecture,
4240 it has only been implemented for "common" cases: SImode, HImode, and
4241 QImode operands, and only for the principle operations that would
4242 require this addressing mode: data movement and simple integer operations.
4244 In parallel with these new predicates, two new constraint letters
4245 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4246 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4247 In the pcrel case 's' is only valid in combination with 'a' registers.
4248 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4249 of how these constraints are used.
4251 The use of these predicates is strictly optional, though patterns that
4252 don't will cause an extra reload register to be allocated where one
4255 lea (abc:w,%pc),%a0 ; need to reload address
4256 moveq &1,%d1 ; since write to pc-relative space
4257 movel %d1,%a0@ ; is not allowed
4259 lea (abc:w,%pc),%a1 ; no need to reload address here
4260 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4262 For more info, consult tiemann@cygnus.com.
4265 All of the ugliness with predicates and constraints is due to the
4266 simple fact that the m68k does not allow a pc-relative addressing
4267 mode as a destination. gcc does not distinguish between source and
4268 destination addresses. Hence, if we claim that pc-relative address
4269 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
4270 end up with invalid code. To get around this problem, we left
4271 pc-relative modes as invalid addresses, and then added special
4272 predicates and constraints to accept them.
4274 A cleaner way to handle this is to modify gcc to distinguish
4275 between source and destination addresses. We can then say that
4276 pc-relative is a valid source address but not a valid destination
4277 address, and hopefully avoid a lot of the predicate and constraint
4278 hackery. Unfortunately, this would be a pretty big change. It would
4279 be a useful change for a number of ports, but there aren't any current
4280 plans to undertake this.
4282 ***************************************************************************/
4286 output_andsi3 (rtx
*operands
)
4289 if (GET_CODE (operands
[2]) == CONST_INT
4290 && (INTVAL (operands
[2]) | 0xffff) == -1
4291 && (DATA_REG_P (operands
[0])
4292 || offsettable_memref_p (operands
[0]))
4293 && !TARGET_COLDFIRE
)
4295 if (GET_CODE (operands
[0]) != REG
)
4296 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4297 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4298 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4300 if (operands
[2] == const0_rtx
)
4302 return "and%.w %2,%0";
4304 if (GET_CODE (operands
[2]) == CONST_INT
4305 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
4306 && (DATA_REG_P (operands
[0])
4307 || offsettable_memref_p (operands
[0])))
4309 if (DATA_REG_P (operands
[0]))
4310 operands
[1] = GEN_INT (logval
);
4313 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4314 operands
[1] = GEN_INT (logval
% 8);
4316 /* This does not set condition codes in a standard way. */
4318 return "bclr %1,%0";
4320 return "and%.l %2,%0";
4324 output_iorsi3 (rtx
*operands
)
4326 register int logval
;
4327 if (GET_CODE (operands
[2]) == CONST_INT
4328 && INTVAL (operands
[2]) >> 16 == 0
4329 && (DATA_REG_P (operands
[0])
4330 || offsettable_memref_p (operands
[0]))
4331 && !TARGET_COLDFIRE
)
4333 if (GET_CODE (operands
[0]) != REG
)
4334 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4335 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4337 if (INTVAL (operands
[2]) == 0xffff)
4338 return "mov%.w %2,%0";
4339 return "or%.w %2,%0";
4341 if (GET_CODE (operands
[2]) == CONST_INT
4342 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4343 && (DATA_REG_P (operands
[0])
4344 || offsettable_memref_p (operands
[0])))
4346 if (DATA_REG_P (operands
[0]))
4347 operands
[1] = GEN_INT (logval
);
4350 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4351 operands
[1] = GEN_INT (logval
% 8);
4354 return "bset %1,%0";
4356 return "or%.l %2,%0";
4360 output_xorsi3 (rtx
*operands
)
4362 register int logval
;
4363 if (GET_CODE (operands
[2]) == CONST_INT
4364 && INTVAL (operands
[2]) >> 16 == 0
4365 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4366 && !TARGET_COLDFIRE
)
4368 if (! DATA_REG_P (operands
[0]))
4369 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4370 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4372 if (INTVAL (operands
[2]) == 0xffff)
4374 return "eor%.w %2,%0";
4376 if (GET_CODE (operands
[2]) == CONST_INT
4377 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4378 && (DATA_REG_P (operands
[0])
4379 || offsettable_memref_p (operands
[0])))
4381 if (DATA_REG_P (operands
[0]))
4382 operands
[1] = GEN_INT (logval
);
4385 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4386 operands
[1] = GEN_INT (logval
% 8);
4389 return "bchg %1,%0";
4391 return "eor%.l %2,%0";
4394 /* Return the instruction that should be used for a call to address X,
4395 which is known to be in operand 0. */
4400 if (symbolic_operand (x
, VOIDmode
))
4401 return m68k_symbolic_call
;
4406 /* Likewise sibling calls. */
4409 output_sibcall (rtx x
)
4411 if (symbolic_operand (x
, VOIDmode
))
4412 return m68k_symbolic_jump
;
4418 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4419 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4422 rtx this_slot
, offset
, addr
, mem
, insn
;
4424 /* Pretend to be a post-reload pass while generating rtl. */
4425 reload_completed
= 1;
4427 /* The "this" pointer is stored at 4(%sp). */
4428 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
4430 /* Add DELTA to THIS. */
4433 /* Make the offset a legitimate operand for memory addition. */
4434 offset
= GEN_INT (delta
);
4435 if ((delta
< -8 || delta
> 8)
4436 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
4438 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
4439 offset
= gen_rtx_REG (Pmode
, D0_REG
);
4441 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
4442 copy_rtx (this_slot
), offset
));
4445 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4446 if (vcall_offset
!= 0)
4448 /* Set the static chain register to *THIS. */
4449 emit_move_insn (static_chain_rtx
, this_slot
);
4450 emit_move_insn (static_chain_rtx
, gen_rtx_MEM (Pmode
, static_chain_rtx
));
4452 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4453 addr
= plus_constant (static_chain_rtx
, vcall_offset
);
4454 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
4456 emit_insn (gen_rtx_SET (VOIDmode
, static_chain_rtx
, addr
));
4457 addr
= static_chain_rtx
;
4460 /* Load the offset into %d0 and add it to THIS. */
4461 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
4462 gen_rtx_MEM (Pmode
, addr
));
4463 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
4464 copy_rtx (this_slot
),
4465 gen_rtx_REG (Pmode
, D0_REG
)));
4468 /* Jump to the target function. Use a sibcall if direct jumps are
4469 allowed, otherwise load the address into a register first. */
4470 mem
= DECL_RTL (function
);
4471 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
4473 gcc_assert (flag_pic
);
4475 if (!TARGET_SEP_DATA
)
4477 /* Use the static chain register as a temporary (call-clobbered)
4478 GOT pointer for this function. We can use the static chain
4479 register because it isn't live on entry to the thunk. */
4480 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
4481 emit_insn (gen_load_got (pic_offset_table_rtx
));
4483 legitimize_pic_address (XEXP (mem
, 0), Pmode
, static_chain_rtx
);
4484 mem
= replace_equiv_address (mem
, static_chain_rtx
);
4486 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
4487 SIBLING_CALL_P (insn
) = 1;
4489 /* Run just enough of rest_of_compilation. */
4490 insn
= get_insns ();
4491 split_all_insns_noflow ();
4492 final_start_function (insn
, file
, 1);
4493 final (insn
, file
, 1);
4494 final_end_function ();
4496 /* Clean up the vars set above. */
4497 reload_completed
= 0;
4499 /* Restore the original PIC register. */
4501 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
4502 free_after_compilation (cfun
);
4505 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4508 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4509 int incoming ATTRIBUTE_UNUSED
)
4511 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4514 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4516 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4517 unsigned int new_reg
)
4520 /* Interrupt functions can only use registers that have already been
4521 saved by the prologue, even if they would normally be
4524 if ((m68k_get_function_kind (current_function_decl
)
4525 == m68k_fk_interrupt_handler
)
4526 && !df_regs_ever_live_p (new_reg
))
4532 /* Value is true if hard register REGNO can hold a value of machine-mode
4533 MODE. On the 68000, we let the cpu registers can hold any mode, but
4534 restrict the 68881 registers to floating-point modes. */
4537 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4539 if (DATA_REGNO_P (regno
))
4541 /* Data Registers, can hold aggregate if fits in. */
4542 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4545 else if (ADDRESS_REGNO_P (regno
))
4547 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4550 else if (FP_REGNO_P (regno
))
4552 /* FPU registers, hold float or complex float of long double or
4554 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4555 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4556 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4562 /* Implement SECONDARY_RELOAD_CLASS. */
4565 m68k_secondary_reload_class (enum reg_class rclass
,
4566 enum machine_mode mode
, rtx x
)
4570 regno
= true_regnum (x
);
4572 /* If one operand of a movqi is an address register, the other
4573 operand must be a general register or constant. Other types
4574 of operand must be reloaded through a data register. */
4575 if (GET_MODE_SIZE (mode
) == 1
4576 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
4577 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
4580 /* PC-relative addresses must be loaded into an address register first. */
4582 && !reg_class_subset_p (rclass
, ADDR_REGS
)
4583 && symbolic_operand (x
, VOIDmode
))
4589 /* Implement PREFERRED_RELOAD_CLASS. */
4592 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
4594 enum reg_class secondary_class
;
4596 /* If RCLASS might need a secondary reload, try restricting it to
4597 a class that doesn't. */
4598 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
4599 if (secondary_class
!= NO_REGS
4600 && reg_class_subset_p (secondary_class
, rclass
))
4601 return secondary_class
;
4603 /* Prefer to use moveq for in-range constants. */
4604 if (GET_CODE (x
) == CONST_INT
4605 && reg_class_subset_p (DATA_REGS
, rclass
)
4606 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
4609 /* ??? Do we really need this now? */
4610 if (GET_CODE (x
) == CONST_DOUBLE
4611 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4613 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
4622 /* Return floating point values in a 68881 register. This makes 68881 code
4623 a little bit faster. It also makes -msoft-float code incompatible with
4624 hard-float code, so people have to be careful not to mix the two.
4625 For ColdFire it was decided the ABI incompatibility is undesirable.
4626 If there is need for a hard-float ABI it is probably worth doing it
4627 properly and also passing function arguments in FP registers. */
4629 m68k_libcall_value (enum machine_mode mode
)
4636 return gen_rtx_REG (mode
, FP0_REG
);
4641 return gen_rtx_REG (mode
, D0_REG
);
4645 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
4647 enum machine_mode mode
;
4649 mode
= TYPE_MODE (valtype
);
4655 return gen_rtx_REG (mode
, FP0_REG
);
4661 /* If the function returns a pointer, push that into %a0. */
4662 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4663 /* For compatibility with the large body of existing code which
4664 does not always properly declare external functions returning
4665 pointer types, the m68k/SVR4 convention is to copy the value
4666 returned for pointer functions from a0 to d0 in the function
4667 epilogue, so that callers that have neglected to properly
4668 declare the callee can still find the correct return value in
4670 return gen_rtx_PARALLEL
4673 gen_rtx_EXPR_LIST (VOIDmode
,
4674 gen_rtx_REG (mode
, A0_REG
),
4676 gen_rtx_EXPR_LIST (VOIDmode
,
4677 gen_rtx_REG (mode
, D0_REG
),
4679 else if (POINTER_TYPE_P (valtype
))
4680 return gen_rtx_REG (mode
, A0_REG
);
4682 return gen_rtx_REG (mode
, D0_REG
);
4685 /* Worker function for TARGET_RETURN_IN_MEMORY. */
4686 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
4688 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
4690 enum machine_mode mode
= TYPE_MODE (type
);
4692 if (mode
== BLKmode
)
4695 /* If TYPE's known alignment is less than the alignment of MODE that
4696 would contain the structure, then return in memory. We need to
4697 do so to maintain the compatibility between code compiled with
4698 -mstrict-align and that compiled with -mno-strict-align. */
4699 if (AGGREGATE_TYPE_P (type
)
4700 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
4707 /* CPU to schedule the program for. */
4708 enum attr_cpu m68k_sched_cpu
;
4710 /* MAC to schedule the program for. */
4711 enum attr_mac m68k_sched_mac
;
4719 /* Integer register. */
4725 /* Implicit mem reference (e.g. stack). */
4728 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
4731 /* Memory with offset but without indexing. EA mode 5. */
4734 /* Memory with indexing. EA mode 6. */
4737 /* Memory referenced by absolute address. EA mode 7. */
4740 /* Immediate operand that doesn't require extension word. */
4743 /* Immediate 16 bit operand. */
4746 /* Immediate 32 bit operand. */
4750 /* Return type of memory ADDR_RTX refers to. */
4751 static enum attr_op_type
4752 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
4754 struct m68k_address address
;
4756 if (symbolic_operand (addr_rtx
, VOIDmode
))
4757 return OP_TYPE_MEM7
;
4759 if (!m68k_decompose_address (mode
, addr_rtx
,
4760 reload_completed
, &address
))
4762 gcc_assert (!reload_completed
);
4763 /* Reload will likely fix the address to be in the register. */
4764 return OP_TYPE_MEM234
;
4767 if (address
.scale
!= 0)
4768 return OP_TYPE_MEM6
;
4770 if (address
.base
!= NULL_RTX
)
4772 if (address
.offset
== NULL_RTX
)
4773 return OP_TYPE_MEM234
;
4775 return OP_TYPE_MEM5
;
4778 gcc_assert (address
.offset
!= NULL_RTX
);
4780 return OP_TYPE_MEM7
;
4783 /* Return X or Y (depending on OPX_P) operand of INSN. */
4785 sched_get_operand (rtx insn
, bool opx_p
)
4789 if (recog_memoized (insn
) < 0)
4792 extract_constrain_insn_cached (insn
);
4795 i
= get_attr_opx (insn
);
4797 i
= get_attr_opy (insn
);
4799 if (i
>= recog_data
.n_operands
)
4802 return recog_data
.operand
[i
];
4805 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
4806 If ADDRESS_P is true, return type of memory location operand refers to. */
4807 static enum attr_op_type
4808 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
4812 op
= sched_get_operand (insn
, opx_p
);
4816 gcc_assert (!reload_completed
);
4821 return sched_address_type (QImode
, op
);
4823 if (memory_operand (op
, VOIDmode
))
4824 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
4826 if (register_operand (op
, VOIDmode
))
4828 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
4829 || (reload_completed
&& FP_REG_P (op
)))
4835 if (GET_CODE (op
) == CONST_INT
)
4841 /* Check for quick constants. */
4842 switch (get_attr_type (insn
))
4845 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
4846 return OP_TYPE_IMM_Q
;
4848 gcc_assert (!reload_completed
);
4852 if (USE_MOVQ (ival
))
4853 return OP_TYPE_IMM_Q
;
4855 gcc_assert (!reload_completed
);
4859 if (valid_mov3q_const (ival
))
4860 return OP_TYPE_IMM_Q
;
4862 gcc_assert (!reload_completed
);
4869 if (IN_RANGE (ival
, -0x8000, 0x7fff))
4870 return OP_TYPE_IMM_W
;
4872 return OP_TYPE_IMM_L
;
4875 if (GET_CODE (op
) == CONST_DOUBLE
)
4877 switch (GET_MODE (op
))
4880 return OP_TYPE_IMM_W
;
4884 return OP_TYPE_IMM_L
;
4891 if (GET_CODE (op
) == CONST
4892 || symbolic_operand (op
, VOIDmode
)
4895 switch (GET_MODE (op
))
4898 return OP_TYPE_IMM_Q
;
4901 return OP_TYPE_IMM_W
;
4904 return OP_TYPE_IMM_L
;
4907 if (GET_CODE (op
) == SYMBOL_REF
)
4908 /* ??? Just a guess. Probably we can guess better using length
4909 attribute of the instructions. */
4910 return OP_TYPE_IMM_W
;
4912 return OP_TYPE_IMM_L
;
4916 gcc_assert (!reload_completed
);
4918 if (FLOAT_MODE_P (GET_MODE (op
)))
4924 /* Implement opx_type attribute.
4925 Return type of INSN's operand X.
4926 If ADDRESS_P is true, return type of memory location operand refers to. */
4928 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
4930 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
4936 return OPX_TYPE_FPN
;
4939 return OPX_TYPE_MEM1
;
4941 case OP_TYPE_MEM234
:
4942 return OPX_TYPE_MEM234
;
4945 return OPX_TYPE_MEM5
;
4948 return OPX_TYPE_MEM6
;
4951 return OPX_TYPE_MEM7
;
4954 return OPX_TYPE_IMM_Q
;
4957 return OPX_TYPE_IMM_W
;
4960 return OPX_TYPE_IMM_L
;
4968 /* Implement opy_type attribute.
4969 Return type of INSN's operand Y.
4970 If ADDRESS_P is true, return type of memory location operand refers to. */
4972 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
4974 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
4980 return OPY_TYPE_FPN
;
4983 return OPY_TYPE_MEM1
;
4985 case OP_TYPE_MEM234
:
4986 return OPY_TYPE_MEM234
;
4989 return OPY_TYPE_MEM5
;
4992 return OPY_TYPE_MEM6
;
4995 return OPY_TYPE_MEM7
;
4998 return OPY_TYPE_IMM_Q
;
5001 return OPY_TYPE_IMM_W
;
5004 return OPY_TYPE_IMM_L
;
5012 /* Return size of INSN as int. */
5014 sched_get_attr_size_int (rtx insn
)
5018 switch (get_attr_type (insn
))
5021 /* There should be no references to m68k_sched_attr_size for 'ignore'
5035 switch (get_attr_opx_type (insn
))
5041 case OPX_TYPE_MEM234
:
5042 case OPY_TYPE_IMM_Q
:
5047 /* Here we assume that most absolute references are short. */
5049 case OPY_TYPE_IMM_W
:
5053 case OPY_TYPE_IMM_L
:
5061 switch (get_attr_opy_type (insn
))
5067 case OPY_TYPE_MEM234
:
5068 case OPY_TYPE_IMM_Q
:
5073 /* Here we assume that most absolute references are short. */
5075 case OPY_TYPE_IMM_W
:
5079 case OPY_TYPE_IMM_L
:
5089 gcc_assert (!reload_completed
);
5097 /* Return size of INSN as attribute enum value. */
5099 m68k_sched_attr_size (rtx insn
)
5101 switch (sched_get_attr_size_int (insn
))
5118 /* Return operand X or Y (depending on OPX_P) of INSN,
5119 if it is a MEM, or NULL overwise. */
5120 static enum attr_op_type
5121 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5125 switch (get_attr_opx_type (insn
))
5130 case OPX_TYPE_IMM_Q
:
5131 case OPX_TYPE_IMM_W
:
5132 case OPX_TYPE_IMM_L
:
5136 case OPX_TYPE_MEM234
:
5139 return OP_TYPE_MEM1
;
5142 return OP_TYPE_MEM6
;
5151 switch (get_attr_opy_type (insn
))
5156 case OPY_TYPE_IMM_Q
:
5157 case OPY_TYPE_IMM_W
:
5158 case OPY_TYPE_IMM_L
:
5162 case OPY_TYPE_MEM234
:
5165 return OP_TYPE_MEM1
;
5168 return OP_TYPE_MEM6
;
5177 /* Implement op_mem attribute. */
5179 m68k_sched_attr_op_mem (rtx insn
)
5181 enum attr_op_type opx
;
5182 enum attr_op_type opy
;
5184 opx
= sched_get_opxy_mem_type (insn
, true);
5185 opy
= sched_get_opxy_mem_type (insn
, false);
5187 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5190 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5192 switch (get_attr_opx_access (insn
))
5209 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5211 switch (get_attr_opx_access (insn
))
5228 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5231 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5233 switch (get_attr_opx_access (insn
))
5239 gcc_assert (!reload_completed
);
5244 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5246 switch (get_attr_opx_access (insn
))
5252 gcc_assert (!reload_completed
);
5257 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5260 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5262 switch (get_attr_opx_access (insn
))
5268 gcc_assert (!reload_completed
);
5273 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5274 gcc_assert (!reload_completed
);
5278 /* Jump instructions types. Indexed by INSN_UID.
5279 The same rtl insn can be expanded into different asm instructions
5280 depending on the cc0_status. To properly determine type of jump
5281 instructions we scan instruction stream and map jumps types to this
5283 static enum attr_type
*sched_branch_type
;
5285 /* Return the type of the jump insn. */
5287 m68k_sched_branch_type (rtx insn
)
5289 enum attr_type type
;
5291 type
= sched_branch_type
[INSN_UID (insn
)];
5293 gcc_assert (type
!= 0);
5298 /* Data for ColdFire V4 index bypass.
5299 Producer modifies register that is used as index in consumer with
5303 /* Producer instruction. */
5306 /* Consumer instruction. */
5309 /* Scale of indexed memory access within consumer.
5310 Or zero if bypass should not be effective at the moment. */
5312 } sched_cfv4_bypass_data
;
5314 /* An empty state that is used in m68k_sched_adjust_cost. */
5315 static state_t sched_adjust_cost_state
;
5317 /* Implement adjust_cost scheduler hook.
5318 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5320 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5325 if (recog_memoized (def_insn
) < 0
5326 || recog_memoized (insn
) < 0)
5329 if (sched_cfv4_bypass_data
.scale
== 1)
5330 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5332 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5333 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5334 that the data in sched_cfv4_bypass_data is up to date. */
5335 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5336 && sched_cfv4_bypass_data
.con
== insn
);
5341 sched_cfv4_bypass_data
.pro
= NULL
;
5342 sched_cfv4_bypass_data
.con
= NULL
;
5343 sched_cfv4_bypass_data
.scale
= 0;
5346 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5347 && sched_cfv4_bypass_data
.con
== NULL
5348 && sched_cfv4_bypass_data
.scale
== 0);
5350 /* Don't try to issue INSN earlier than DFA permits.
5351 This is especially useful for instructions that write to memory,
5352 as their true dependence (default) latency is better to be set to 0
5353 to workaround alias analysis limitations.
5354 This is, in fact, a machine independent tweak, so, probably,
5355 it should be moved to haifa-sched.c: insn_cost (). */
5356 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5363 /* Return maximal number of insns that can be scheduled on a single cycle. */
5365 m68k_sched_issue_rate (void)
5367 switch (m68k_sched_cpu
)
5383 /* Maximal length of instruction for current CPU.
5384 E.g. it is 3 for any ColdFire core. */
5385 static int max_insn_size
;
5387 /* Data to model instruction buffer of CPU. */
5390 /* True if instruction buffer model is modeled for current CPU. */
5393 /* Size of the instruction buffer in words. */
5396 /* Number of filled words in the instruction buffer. */
5399 /* Additional information about instruction buffer for CPUs that have
5400 a buffer of instruction records, rather then a plain buffer
5401 of instruction words. */
5402 struct _sched_ib_records
5404 /* Size of buffer in records. */
5407 /* Array to hold data on adjustements made to the size of the buffer. */
5410 /* Index of the above array. */
5414 /* An insn that reserves (marks empty) one word in the instruction buffer. */
5418 static struct _sched_ib sched_ib
;
5420 /* ID of memory unit. */
5421 static int sched_mem_unit_code
;
5423 /* Implementation of the targetm.sched.variable_issue () hook.
5424 It is called after INSN was issued. It returns the number of insns
5425 that can possibly get scheduled on the current cycle.
5426 It is used here to determine the effect of INSN on the instruction
5429 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
5430 int sched_verbose ATTRIBUTE_UNUSED
,
5431 rtx insn
, int can_issue_more
)
5435 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
5437 switch (m68k_sched_cpu
)
5441 insn_size
= sched_get_attr_size_int (insn
);
5445 insn_size
= sched_get_attr_size_int (insn
);
5447 /* ColdFire V3 and V4 cores have instruction buffers that can
5448 accumulate up to 8 instructions regardless of instructions'
5449 sizes. So we should take care not to "prefetch" 24 one-word
5450 or 12 two-words instructions.
5451 To model this behavior we temporarily decrease size of the
5452 buffer by (max_insn_size - insn_size) for next 7 instructions. */
5456 adjust
= max_insn_size
- insn_size
;
5457 sched_ib
.size
-= adjust
;
5459 if (sched_ib
.filled
> sched_ib
.size
)
5460 sched_ib
.filled
= sched_ib
.size
;
5462 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
5465 ++sched_ib
.records
.adjust_index
;
5466 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
5467 sched_ib
.records
.adjust_index
= 0;
5469 /* Undo adjustement we did 7 instructions ago. */
5471 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
5476 gcc_assert (!sched_ib
.enabled_p
);
5484 gcc_assert (insn_size
<= sched_ib
.filled
);
5487 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
5488 || asm_noperands (PATTERN (insn
)) >= 0)
5489 insn_size
= sched_ib
.filled
;
5493 sched_ib
.filled
-= insn_size
;
5495 return can_issue_more
;
5498 /* Return how many instructions should scheduler lookahead to choose the
5501 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
5503 return m68k_sched_issue_rate () - 1;
5506 /* Implementation of targetm.sched.md_init_global () hook.
5507 It is invoked once per scheduling pass and is used here
5508 to initialize scheduler constants. */
5510 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
5511 int sched_verbose ATTRIBUTE_UNUSED
,
5512 int n_insns ATTRIBUTE_UNUSED
)
5514 /* Init branch types. */
5518 sched_branch_type
= XCNEWVEC (enum attr_type
, get_max_uid () + 1);
5520 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
5523 /* !!! FIXME: Implement real scan here. */
5524 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
5528 #ifdef ENABLE_CHECKING
5529 /* Check that all instructions have DFA reservations and
5530 that all instructions can be issued from a clean state. */
5535 state
= alloca (state_size ());
5537 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
5539 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
5541 gcc_assert (insn_has_dfa_reservation_p (insn
));
5543 state_reset (state
);
5544 if (state_transition (state
, insn
) >= 0)
5551 /* Setup target cpu. */
5553 /* ColdFire V4 has a set of features to keep its instruction buffer full
5554 (e.g., a separate memory bus for instructions) and, hence, we do not model
5555 buffer for this CPU. */
5556 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
5558 switch (m68k_sched_cpu
)
5561 sched_ib
.filled
= 0;
5568 sched_ib
.records
.n_insns
= 0;
5569 sched_ib
.records
.adjust
= NULL
;
5574 sched_ib
.records
.n_insns
= 8;
5575 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
5582 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
5584 sched_adjust_cost_state
= xmalloc (state_size ());
5585 state_reset (sched_adjust_cost_state
);
5588 emit_insn (gen_ib ());
5589 sched_ib
.insn
= get_insns ();
5593 /* Scheduling pass is now finished. Free/reset static variables. */
5595 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
5596 int verbose ATTRIBUTE_UNUSED
)
5598 sched_ib
.insn
= NULL
;
5600 free (sched_adjust_cost_state
);
5601 sched_adjust_cost_state
= NULL
;
5603 sched_mem_unit_code
= 0;
5605 free (sched_ib
.records
.adjust
);
5606 sched_ib
.records
.adjust
= NULL
;
5607 sched_ib
.records
.n_insns
= 0;
5610 free (sched_branch_type
);
5611 sched_branch_type
= NULL
;
5614 /* Implementation of targetm.sched.md_init () hook.
5615 It is invoked each time scheduler starts on the new block (basic block or
5616 extended basic block). */
5618 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
5619 int sched_verbose ATTRIBUTE_UNUSED
,
5620 int n_insns ATTRIBUTE_UNUSED
)
5622 switch (m68k_sched_cpu
)
5630 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
5632 memset (sched_ib
.records
.adjust
, 0,
5633 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
5634 sched_ib
.records
.adjust_index
= 0;
5638 gcc_assert (!sched_ib
.enabled_p
);
5646 if (sched_ib
.enabled_p
)
5647 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
5648 the first cycle. Workaround that. */
5649 sched_ib
.filled
= -2;
5652 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
5653 It is invoked just before current cycle finishes and is used here
5654 to track if instruction buffer got its two words this cycle. */
5656 m68k_sched_dfa_pre_advance_cycle (void)
5658 if (!sched_ib
.enabled_p
)
5661 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
5663 sched_ib
.filled
+= 2;
5665 if (sched_ib
.filled
> sched_ib
.size
)
5666 sched_ib
.filled
= sched_ib
.size
;
5670 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
5671 It is invoked just after new cycle begins and is used here
5672 to setup number of filled words in the instruction buffer so that
5673 instructions which won't have all their words prefetched would be
5674 stalled for a cycle. */
5676 m68k_sched_dfa_post_advance_cycle (void)
5680 if (!sched_ib
.enabled_p
)
5683 /* Setup number of prefetched instruction words in the instruction
5685 i
= max_insn_size
- sched_ib
.filled
;
5689 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
5694 /* Return X or Y (depending on OPX_P) operand of INSN,
5695 if it is an integer register, or NULL overwise. */
5697 sched_get_reg_operand (rtx insn
, bool opx_p
)
5703 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
5705 op
= sched_get_operand (insn
, true);
5706 gcc_assert (op
!= NULL
);
5708 if (!reload_completed
&& !REG_P (op
))
5714 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
5716 op
= sched_get_operand (insn
, false);
5717 gcc_assert (op
!= NULL
);
5719 if (!reload_completed
&& !REG_P (op
))
5727 /* Return true, if X or Y (depending on OPX_P) operand of INSN
5730 sched_mem_operand_p (rtx insn
, bool opx_p
)
5732 switch (sched_get_opxy_mem_type (insn
, opx_p
))
5743 /* Return X or Y (depending on OPX_P) operand of INSN,
5744 if it is a MEM, or NULL overwise. */
5746 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
5766 if (opy_p
&& sched_mem_operand_p (insn
, false))
5767 return sched_get_operand (insn
, false);
5769 if (opx_p
&& sched_mem_operand_p (insn
, true))
5770 return sched_get_operand (insn
, true);
5776 /* Return non-zero if PRO modifies register used as part of
5779 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
5784 pro_x
= sched_get_reg_operand (pro
, true);
5788 con_mem_read
= sched_get_mem_operand (con
, true, false);
5789 gcc_assert (con_mem_read
!= NULL
);
5791 if (reg_mentioned_p (pro_x
, con_mem_read
))
5797 /* Helper function for m68k_sched_indexed_address_bypass_p.
5798 if PRO modifies register used as index in CON,
5799 return scale of indexed memory access in CON. Return zero overwise. */
5801 sched_get_indexed_address_scale (rtx pro
, rtx con
)
5805 struct m68k_address address
;
5807 reg
= sched_get_reg_operand (pro
, true);
5811 mem
= sched_get_mem_operand (con
, true, false);
5812 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
5814 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
5818 if (REGNO (reg
) == REGNO (address
.index
))
5820 gcc_assert (address
.scale
!= 0);
5821 return address
.scale
;
5827 /* Return non-zero if PRO modifies register used
5828 as index with scale 2 or 4 in CON. */
5830 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
5832 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5833 && sched_cfv4_bypass_data
.con
== NULL
5834 && sched_cfv4_bypass_data
.scale
== 0);
5836 switch (sched_get_indexed_address_scale (pro
, con
))
5839 /* We can't have a variable latency bypass, so
5840 remember to adjust the insn cost in adjust_cost hook. */
5841 sched_cfv4_bypass_data
.pro
= pro
;
5842 sched_cfv4_bypass_data
.con
= con
;
5843 sched_cfv4_bypass_data
.scale
= 1;