1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
70 ;; Special formats used for outputting 390 instructions.
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %G: print the size of the operand in bytes.
76 ;; %O: print only the displacement of a memory reference.
77 ;; %R: print only the base register of a memory reference.
78 ;; %S: print S-type memory reference (base+displacement).
79 ;; %N: print the second word of a DImode operand.
80 ;; %M: print the second word of a TImode operand.
81 ;; %Y: print shift count operand.
83 ;; %b: print integer X as if it's an unsigned byte.
84 ;; %x: print integer X as if it's an unsigned halfword.
85 ;; %h: print integer X as if it's a signed halfword.
86 ;; %i: print the first nonzero HImode part of X.
87 ;; %j: print the first HImode part unequal to -1 of X.
88 ;; %k: print the first nonzero SImode part of X.
89 ;; %m: print the first SImode part unequal to -1 of X.
90 ;; %o: print integer X as if it's an unsigned 32bit word.
92 ;; We have a special constraint for pattern matching.
94 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
107 ; GOT/PLT and lt-relative accesses
108 (UNSPEC_LTREL_OFFSET 100)
109 (UNSPEC_LTREL_BASE 101)
117 (UNSPEC_RELOAD_BASE 210)
118 (UNSPEC_MAIN_BASE 211)
123 ; TLS relocation specifiers
128 (UNSPEC_GOTNTPOFF 504)
129 (UNSPEC_INDNTPOFF 505)
132 (UNSPEC_TLSLDM_NTPOFF 511)
133 (UNSPEC_TLS_LOAD 512)
139 ; Stack Smashing Protector
145 ;; UNSPEC_VOLATILE usage
153 (UNSPECV_TPF_PROLOGUE 20)
154 (UNSPECV_TPF_EPILOGUE 21)
158 (UNSPECV_POOL_SECTION 201)
159 (UNSPECV_POOL_ALIGN 202)
160 (UNSPECV_POOL_ENTRY 203)
161 (UNSPECV_MAIN_POOL 300)
177 ; Sibling call register.
179 ; Literal pool base register.
181 ; Return address register.
183 ; Condition code register.
185 ; Thread local storage pointer register.
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimpdf,fsimpsf,
203 floaddf,floadsf,fstoredf,fstoresf,
204 fmuldf,fmulsf,fdivdf,fdivsf,
205 ftoi,itof,fsqrtdf,fsqrtsf,
207 (cond [(eq_attr "op_type" "NN") (const_string "other")
208 (eq_attr "op_type" "SS") (const_string "cs")]
209 (const_string "integer")))
211 ;; Another attribute used for scheduling purposes:
212 ;; agen: Instruction uses the address generation unit
213 ;; reg: Instruction does not use the agen unit
215 (define_attr "atype" "agen,reg"
216 (cond [(eq_attr "op_type" "E") (const_string "reg")
217 (eq_attr "op_type" "RR") (const_string "reg")
218 (eq_attr "op_type" "RX") (const_string "agen")
219 (eq_attr "op_type" "RI") (const_string "reg")
220 (eq_attr "op_type" "RRE") (const_string "reg")
221 (eq_attr "op_type" "RS") (const_string "agen")
222 (eq_attr "op_type" "RSI") (const_string "agen")
223 (eq_attr "op_type" "S") (const_string "agen")
224 (eq_attr "op_type" "SI") (const_string "agen")
225 (eq_attr "op_type" "SS") (const_string "agen")
226 (eq_attr "op_type" "SSE") (const_string "agen")
227 (eq_attr "op_type" "RXE") (const_string "agen")
228 (eq_attr "op_type" "RSE") (const_string "agen")
229 (eq_attr "op_type" "RIL") (const_string "agen")
230 (eq_attr "op_type" "RXY") (const_string "agen")
231 (eq_attr "op_type" "RSY") (const_string "agen")
232 (eq_attr "op_type" "SIY") (const_string "agen")]
233 (const_string "agen")))
237 (define_attr "length" ""
238 (cond [(eq_attr "op_type" "E") (const_int 2)
239 (eq_attr "op_type" "RR") (const_int 2)
240 (eq_attr "op_type" "RX") (const_int 4)
241 (eq_attr "op_type" "RI") (const_int 4)
242 (eq_attr "op_type" "RRE") (const_int 4)
243 (eq_attr "op_type" "RS") (const_int 4)
244 (eq_attr "op_type" "RSI") (const_int 4)
245 (eq_attr "op_type" "S") (const_int 4)
246 (eq_attr "op_type" "SI") (const_int 4)
247 (eq_attr "op_type" "SS") (const_int 6)
248 (eq_attr "op_type" "SSE") (const_int 6)
249 (eq_attr "op_type" "RXE") (const_int 6)
250 (eq_attr "op_type" "RSE") (const_int 6)
251 (eq_attr "op_type" "RIL") (const_int 6)
252 (eq_attr "op_type" "RXY") (const_int 6)
253 (eq_attr "op_type" "RSY") (const_int 6)
254 (eq_attr "op_type" "SIY") (const_int 6)]
258 ;; Processor type. This attribute must exactly match the processor_type
259 ;; enumeration in s390.h. The current machine description does not
260 ;; distinguish between g5 and g6, but there are differences between the two
261 ;; CPUs could in theory be modeled.
263 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
264 (const (symbol_ref "s390_tune")))
266 ;; Pipeline description for z900. For lack of anything better,
267 ;; this description is also used for the g5 and g6.
270 ;; Pipeline description for z990.
274 (include "predicates.md")
281 ;; This mode macro allows DF and SF patterns to be generated from the
283 (define_mode_macro FPR [DF SF])
285 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
286 ;; from the same template.
287 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
289 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
290 ;; from the same template.
291 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
292 (define_mode_macro DSI [DI SI])
294 ;; This mode macro allows :P to be used for patterns that operate on
295 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
296 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
297 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
299 ;; This mode macro allows the QI and HI patterns to be defined from
300 ;; the same template.
301 (define_mode_macro HQI [HI QI])
303 ;; This mode macro allows the integer patterns to be defined from the
305 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
307 ;; This macro allows to unify all 'bCOND' expander patterns.
308 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
309 ordered uneq unlt ungt unle unge ltgt])
311 ;; This macro allows to unify all 'sCOND' patterns.
312 (define_code_macro SCOND [ltu gtu leu geu])
314 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
315 ;; the same template.
316 (define_code_macro SHIFT [ashift lshiftrt])
318 ;; These macros allow to combine most atomic operations.
319 (define_code_macro ATOMIC [and ior xor plus minus mult])
320 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
321 (plus "add") (minus "sub") (mult "nand")])
324 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
325 ;; and "ltebr" in SFmode.
326 (define_mode_attr de [(DF "d") (SF "e")])
328 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
329 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
330 (define_mode_attr dee [(DF "d") (SF "ee")])
332 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
333 ;; 'ashift' and "srdl" in 'lshiftrt'.
334 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
336 ;; In SHIFT templates, this attribute holds the correct standard name for the
337 ;; pattern itself and the corresponding function calls.
338 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
340 ;; This attribute handles differences in the instruction 'type' and will result
341 ;; in "RRE" for DImode and "RR" for SImode.
342 (define_mode_attr E [(DI "E") (SI "")])
344 ;; This attribute handles differences in the instruction 'type' and will result
345 ;; in "RSE" for TImode and "RS" for DImode.
346 (define_mode_attr TE [(TI "E") (DI "")])
348 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
349 ;; and "lcr" in SImode.
350 (define_mode_attr g [(DI "g") (SI "")])
352 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
353 ;; and "cds" in DImode.
354 (define_mode_attr tg [(TI "g") (DI "")])
356 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
357 ;; and "cfdbr" in SImode.
358 (define_mode_attr gf [(DI "g") (SI "f")])
360 ;; ICM mask required to load MODE value into the lowest subreg
361 ;; of a SImode register.
362 (define_mode_attr icm_lo [(HI "3") (QI "1")])
364 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
365 ;; HImode and "llgc" in QImode.
366 (define_mode_attr hc [(HI "h") (QI "c")])
368 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
370 (define_mode_attr DBL [(DI "TI") (SI "DI")])
372 ;; Maximum unsigned integer that fits in MODE.
373 (define_mode_attr max_uint [(HI "65535") (QI "255")])
377 ;;- Compare instructions.
380 (define_expand "cmp<mode>"
381 [(set (reg:CC CC_REGNUM)
382 (compare:CC (match_operand:GPR 0 "register_operand" "")
383 (match_operand:GPR 1 "general_operand" "")))]
386 s390_compare_op0 = operands[0];
387 s390_compare_op1 = operands[1];
391 (define_expand "cmp<mode>"
392 [(set (reg:CC CC_REGNUM)
393 (compare:CC (match_operand:FPR 0 "register_operand" "")
394 (match_operand:FPR 1 "general_operand" "")))]
397 s390_compare_op0 = operands[0];
398 s390_compare_op1 = operands[1];
403 ; Test-under-Mask instructions
405 (define_insn "*tmqi_mem"
406 [(set (reg CC_REGNUM)
407 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
408 (match_operand:QI 1 "immediate_operand" "n,n"))
409 (match_operand:QI 2 "immediate_operand" "n,n")))]
410 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
414 [(set_attr "op_type" "SI,SIY")])
416 (define_insn "*tmdi_reg"
417 [(set (reg CC_REGNUM)
418 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
419 (match_operand:DI 1 "immediate_operand"
420 "N0HD0,N1HD0,N2HD0,N3HD0"))
421 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
423 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
424 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
430 [(set_attr "op_type" "RI")])
432 (define_insn "*tmsi_reg"
433 [(set (reg CC_REGNUM)
434 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
435 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
436 (match_operand:SI 2 "immediate_operand" "n,n")))]
437 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
438 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
442 [(set_attr "op_type" "RI")])
444 (define_insn "*tm<mode>_full"
445 [(set (reg CC_REGNUM)
446 (compare (match_operand:HQI 0 "register_operand" "d")
447 (match_operand:HQI 1 "immediate_operand" "n")))]
448 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
450 [(set_attr "op_type" "RI")])
453 ; Load-and-Test instructions
455 (define_insn "*tstdi_sign"
456 [(set (reg CC_REGNUM)
457 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
458 (const_int 32)) (const_int 32))
459 (match_operand:DI 1 "const0_operand" "")))
460 (set (match_operand:DI 2 "register_operand" "=d")
461 (sign_extend:DI (match_dup 0)))]
462 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
464 [(set_attr "op_type" "RRE")])
466 (define_insn "*tstdi_extimm"
467 [(set (reg CC_REGNUM)
468 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
469 (match_operand:DI 1 "const0_operand" "")))
470 (set (match_operand:DI 2 "register_operand" "=d,d")
472 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
476 [(set_attr "op_type" "RRE,RXY")])
478 (define_insn "*tstdi_cconly_extimm"
479 [(set (reg CC_REGNUM)
480 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
481 (match_operand:DI 1 "const0_operand" "")))
482 (clobber (match_scratch:DI 2 "=X,d"))]
483 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
487 [(set_attr "op_type" "RRE,RXY")])
489 (define_insn "*tstdi"
490 [(set (reg CC_REGNUM)
491 (compare (match_operand:DI 0 "register_operand" "d")
492 (match_operand:DI 1 "const0_operand" "")))
493 (set (match_operand:DI 2 "register_operand" "=d")
495 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
497 [(set_attr "op_type" "RRE")])
499 (define_insn "*tstdi_cconly"
500 [(set (reg CC_REGNUM)
501 (compare (match_operand:DI 0 "register_operand" "d")
502 (match_operand:DI 1 "const0_operand" "")))]
503 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
505 [(set_attr "op_type" "RRE")])
507 (define_insn "*tstdi_cconly_31"
508 [(set (reg CC_REGNUM)
509 (compare (match_operand:DI 0 "register_operand" "d")
510 (match_operand:DI 1 "const0_operand" "")))]
511 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
513 [(set_attr "op_type" "RS")
514 (set_attr "atype" "reg")])
516 (define_insn "*tstsi_extimm"
517 [(set (reg CC_REGNUM)
518 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
519 (match_operand:SI 1 "const0_operand" "")))
520 (set (match_operand:SI 2 "register_operand" "=d,d")
522 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
526 [(set_attr "op_type" "RR,RXY")])
528 (define_insn "*tstsi_cconly_extimm"
529 [(set (reg CC_REGNUM)
530 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
531 (match_operand:SI 1 "const0_operand" "")))
532 (clobber (match_scratch:SI 2 "=X,d"))]
533 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
537 [(set_attr "op_type" "RR,RXY")])
539 (define_insn "*tstsi"
540 [(set (reg CC_REGNUM)
541 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
542 (match_operand:SI 1 "const0_operand" "")))
543 (set (match_operand:SI 2 "register_operand" "=d,d,d")
545 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
550 [(set_attr "op_type" "RR,RS,RSY")])
552 (define_insn "*tstsi_cconly"
553 [(set (reg CC_REGNUM)
554 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
555 (match_operand:SI 1 "const0_operand" "")))
556 (clobber (match_scratch:SI 2 "=X,d,d"))]
557 "s390_match_ccmode(insn, CCSmode)"
562 [(set_attr "op_type" "RR,RS,RSY")])
564 (define_insn "*tstsi_cconly2"
565 [(set (reg CC_REGNUM)
566 (compare (match_operand:SI 0 "register_operand" "d")
567 (match_operand:SI 1 "const0_operand" "")))]
568 "s390_match_ccmode(insn, CCSmode)"
570 [(set_attr "op_type" "RR")])
572 (define_insn "*tst<mode>CCT"
573 [(set (reg CC_REGNUM)
574 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
575 (match_operand:HQI 1 "const0_operand" "")))
576 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
578 "s390_match_ccmode(insn, CCTmode)"
581 icmy\t%2,<icm_lo>,%S0
583 [(set_attr "op_type" "RS,RSY,RI")])
585 (define_insn "*tsthiCCT_cconly"
586 [(set (reg CC_REGNUM)
587 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
588 (match_operand:HI 1 "const0_operand" "")))
589 (clobber (match_scratch:HI 2 "=d,d,X"))]
590 "s390_match_ccmode(insn, CCTmode)"
595 [(set_attr "op_type" "RS,RSY,RI")])
597 (define_insn "*tstqiCCT_cconly"
598 [(set (reg CC_REGNUM)
599 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
600 (match_operand:QI 1 "const0_operand" "")))]
601 "s390_match_ccmode(insn, CCTmode)"
606 [(set_attr "op_type" "SI,SIY,RI")])
608 (define_insn "*tst<mode>"
609 [(set (reg CC_REGNUM)
610 (compare (match_operand:HQI 0 "s_operand" "Q,S")
611 (match_operand:HQI 1 "const0_operand" "")))
612 (set (match_operand:HQI 2 "register_operand" "=d,d")
614 "s390_match_ccmode(insn, CCSmode)"
617 icmy\t%2,<icm_lo>,%S0"
618 [(set_attr "op_type" "RS,RSY")])
620 (define_insn "*tst<mode>_cconly"
621 [(set (reg CC_REGNUM)
622 (compare (match_operand:HQI 0 "s_operand" "Q,S")
623 (match_operand:HQI 1 "const0_operand" "")))
624 (clobber (match_scratch:HQI 2 "=d,d"))]
625 "s390_match_ccmode(insn, CCSmode)"
628 icmy\t%2,<icm_lo>,%S0"
629 [(set_attr "op_type" "RS,RSY")])
632 ; Compare (equality) instructions
634 (define_insn "*cmpdi_cct"
635 [(set (reg CC_REGNUM)
636 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
637 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
638 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
645 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
647 (define_insn "*cmpsi_cct"
648 [(set (reg CC_REGNUM)
649 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
650 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
651 "s390_match_ccmode (insn, CCTmode)"
659 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
662 ; Compare (signed) instructions
664 (define_insn "*cmpdi_ccs_sign"
665 [(set (reg CC_REGNUM)
666 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
667 (match_operand:DI 0 "register_operand" "d,d")))]
668 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
672 [(set_attr "op_type" "RRE,RXY")])
674 (define_insn "*cmpdi_ccs"
675 [(set (reg CC_REGNUM)
676 (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
677 (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
678 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
684 [(set_attr "op_type" "RRE,RI,RIL,RXY")])
686 (define_insn "*cmpsi_ccs_sign"
687 [(set (reg CC_REGNUM)
688 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
689 (match_operand:SI 0 "register_operand" "d,d")))]
690 "s390_match_ccmode(insn, CCSRmode)"
694 [(set_attr "op_type" "RX,RXY")])
696 (define_insn "*cmpsi_ccs"
697 [(set (reg CC_REGNUM)
698 (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
699 (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
700 "s390_match_ccmode(insn, CCSmode)"
707 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
710 ; Compare (unsigned) instructions
712 (define_insn "*cmpdi_ccu_zero"
713 [(set (reg CC_REGNUM)
714 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
715 (match_operand:DI 0 "register_operand" "d,d")))]
716 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
720 [(set_attr "op_type" "RRE,RXY")])
722 (define_insn "*cmpdi_ccu"
723 [(set (reg CC_REGNUM)
724 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
725 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
726 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
733 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
735 (define_insn "*cmpsi_ccu"
736 [(set (reg CC_REGNUM)
737 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
738 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
739 "s390_match_ccmode (insn, CCUmode)"
747 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
749 (define_insn "*cmphi_ccu"
750 [(set (reg CC_REGNUM)
751 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
752 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
753 "s390_match_ccmode (insn, CCUmode)
754 && !register_operand (operands[1], HImode)"
760 [(set_attr "op_type" "RS,RSY,SS,SS")])
762 (define_insn "*cmpqi_ccu"
763 [(set (reg CC_REGNUM)
764 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
765 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
766 "s390_match_ccmode (insn, CCUmode)
767 && !register_operand (operands[1], QImode)"
775 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
778 ; Block compare (CLC) instruction patterns.
781 [(set (reg CC_REGNUM)
782 (compare (match_operand:BLK 0 "memory_operand" "Q")
783 (match_operand:BLK 1 "memory_operand" "Q")))
784 (use (match_operand 2 "const_int_operand" "n"))]
785 "s390_match_ccmode (insn, CCUmode)
786 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
787 "clc\t%O0(%2,%R0),%S1"
788 [(set_attr "op_type" "SS")])
791 [(set (reg CC_REGNUM)
792 (compare (match_operand 0 "memory_operand" "")
793 (match_operand 1 "memory_operand" "")))]
795 && s390_match_ccmode (insn, CCUmode)
796 && GET_MODE (operands[0]) == GET_MODE (operands[1])
797 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
799 [(set (match_dup 0) (match_dup 1))
800 (use (match_dup 2))])]
802 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
803 operands[0] = adjust_address (operands[0], BLKmode, 0);
804 operands[1] = adjust_address (operands[1], BLKmode, 0);
806 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
807 operands[0], operands[1]);
808 operands[0] = SET_DEST (PATTERN (curr_insn));
812 ; (DF|SF) instructions
814 (define_insn "*cmp<mode>_ccs_0"
815 [(set (reg CC_REGNUM)
816 (compare (match_operand:FPR 0 "register_operand" "f")
817 (match_operand:FPR 1 "const0_operand" "")))]
818 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
820 [(set_attr "op_type" "RRE")
821 (set_attr "type" "fsimp<mode>")])
823 (define_insn "*cmp<mode>_ccs_0_ibm"
824 [(set (reg CC_REGNUM)
825 (compare (match_operand:FPR 0 "register_operand" "f")
826 (match_operand:FPR 1 "const0_operand" "")))]
827 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
829 [(set_attr "op_type" "RR")
830 (set_attr "type" "fsimp<mode>")])
832 (define_insn "*cmp<mode>_ccs"
833 [(set (reg CC_REGNUM)
834 (compare (match_operand:FPR 0 "register_operand" "f,f")
835 (match_operand:FPR 1 "general_operand" "f,R")))]
836 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
840 [(set_attr "op_type" "RRE,RXE")
841 (set_attr "type" "fsimp<mode>")])
843 (define_insn "*cmp<mode>_ccs_ibm"
844 [(set (reg CC_REGNUM)
845 (compare (match_operand:FPR 0 "register_operand" "f,f")
846 (match_operand:FPR 1 "general_operand" "f,R")))]
847 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
851 [(set_attr "op_type" "RR,RX")
852 (set_attr "type" "fsimp<mode>")])
856 ;;- Move instructions.
860 ; movti instruction pattern(s).
864 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
865 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
873 [(set_attr "op_type" "RSY,RSY,*,*,SS")
874 (set_attr "type" "lm,stm,*,*,*")])
877 [(set (match_operand:TI 0 "nonimmediate_operand" "")
878 (match_operand:TI 1 "general_operand" ""))]
879 "TARGET_64BIT && reload_completed
880 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
881 [(set (match_dup 2) (match_dup 4))
882 (set (match_dup 3) (match_dup 5))]
884 operands[2] = operand_subword (operands[0], 0, 0, TImode);
885 operands[3] = operand_subword (operands[0], 1, 0, TImode);
886 operands[4] = operand_subword (operands[1], 0, 0, TImode);
887 operands[5] = operand_subword (operands[1], 1, 0, TImode);
891 [(set (match_operand:TI 0 "nonimmediate_operand" "")
892 (match_operand:TI 1 "general_operand" ""))]
893 "TARGET_64BIT && reload_completed
894 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
895 [(set (match_dup 2) (match_dup 4))
896 (set (match_dup 3) (match_dup 5))]
898 operands[2] = operand_subword (operands[0], 1, 0, TImode);
899 operands[3] = operand_subword (operands[0], 0, 0, TImode);
900 operands[4] = operand_subword (operands[1], 1, 0, TImode);
901 operands[5] = operand_subword (operands[1], 0, 0, TImode);
905 [(set (match_operand:TI 0 "register_operand" "")
906 (match_operand:TI 1 "memory_operand" ""))]
907 "TARGET_64BIT && reload_completed
908 && !s_operand (operands[1], VOIDmode)"
909 [(set (match_dup 0) (match_dup 1))]
911 rtx addr = operand_subword (operands[0], 1, 0, TImode);
912 s390_load_address (addr, XEXP (operands[1], 0));
913 operands[1] = replace_equiv_address (operands[1], addr);
916 (define_expand "reload_outti"
917 [(parallel [(match_operand:TI 0 "" "")
918 (match_operand:TI 1 "register_operand" "d")
919 (match_operand:DI 2 "register_operand" "=&a")])]
922 gcc_assert (MEM_P (operands[0]));
923 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
924 operands[0] = replace_equiv_address (operands[0], operands[2]);
925 emit_move_insn (operands[0], operands[1]);
930 ; movdi instruction pattern(s).
933 (define_expand "movdi"
934 [(set (match_operand:DI 0 "general_operand" "")
935 (match_operand:DI 1 "general_operand" ""))]
938 /* Handle symbolic constants. */
939 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
940 emit_symbolic_move (operands);
943 (define_insn "*movdi_larl"
944 [(set (match_operand:DI 0 "register_operand" "=d")
945 (match_operand:DI 1 "larl_operand" "X"))]
947 && !FP_REG_P (operands[0])"
949 [(set_attr "op_type" "RIL")
950 (set_attr "type" "larl")])
952 (define_insn "*movdi_64extimm"
953 [(set (match_operand:DI 0 "nonimmediate_operand"
954 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
955 (match_operand:DI 1 "general_operand"
956 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
957 "TARGET_64BIT && TARGET_EXTIMM"
981 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
982 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
983 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
984 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
986 (define_insn "*movdi_64"
987 [(set (match_operand:DI 0 "nonimmediate_operand"
988 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
989 (match_operand:DI 1 "general_operand"
990 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
991 "TARGET_64BIT && !TARGET_EXTIMM"
1012 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
1013 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1014 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
1015 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1018 [(set (match_operand:DI 0 "register_operand" "")
1019 (match_operand:DI 1 "register_operand" ""))]
1020 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1021 [(set (match_dup 2) (match_dup 3))
1022 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1023 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1024 "operands[2] = gen_lowpart (SImode, operands[0]);
1025 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1028 [(set (match_operand:DI 0 "register_operand" "")
1029 (match_operand:DI 1 "register_operand" ""))]
1030 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1031 && dead_or_set_p (insn, operands[1])"
1032 [(set (match_dup 3) (match_dup 2))
1033 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1034 (set (match_dup 4) (match_dup 2))]
1035 "operands[2] = gen_lowpart (SImode, operands[1]);
1036 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1039 [(set (match_operand:DI 0 "register_operand" "")
1040 (match_operand:DI 1 "register_operand" ""))]
1041 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1042 && !dead_or_set_p (insn, operands[1])"
1043 [(set (match_dup 3) (match_dup 2))
1044 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1045 (set (match_dup 4) (match_dup 2))
1046 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1047 "operands[2] = gen_lowpart (SImode, operands[1]);
1048 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1050 (define_insn "*movdi_31"
1051 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1052 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1067 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1068 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1071 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1072 (match_operand:DI 1 "general_operand" ""))]
1073 "!TARGET_64BIT && reload_completed
1074 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1075 [(set (match_dup 2) (match_dup 4))
1076 (set (match_dup 3) (match_dup 5))]
1078 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1079 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1080 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1081 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1085 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1086 (match_operand:DI 1 "general_operand" ""))]
1087 "!TARGET_64BIT && reload_completed
1088 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1089 [(set (match_dup 2) (match_dup 4))
1090 (set (match_dup 3) (match_dup 5))]
1092 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1093 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1094 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1095 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1099 [(set (match_operand:DI 0 "register_operand" "")
1100 (match_operand:DI 1 "memory_operand" ""))]
1101 "!TARGET_64BIT && reload_completed
1102 && !FP_REG_P (operands[0])
1103 && !s_operand (operands[1], VOIDmode)"
1104 [(set (match_dup 0) (match_dup 1))]
1106 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1107 s390_load_address (addr, XEXP (operands[1], 0));
1108 operands[1] = replace_equiv_address (operands[1], addr);
1111 (define_expand "reload_outdi"
1112 [(parallel [(match_operand:DI 0 "" "")
1113 (match_operand:DI 1 "register_operand" "d")
1114 (match_operand:SI 2 "register_operand" "=&a")])]
1117 gcc_assert (MEM_P (operands[0]));
1118 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1119 operands[0] = replace_equiv_address (operands[0], operands[2]);
1120 emit_move_insn (operands[0], operands[1]);
1125 [(set (match_operand:DI 0 "register_operand" "")
1126 (mem:DI (match_operand 1 "address_operand" "")))]
1128 && !FP_REG_P (operands[0])
1129 && GET_CODE (operands[1]) == SYMBOL_REF
1130 && CONSTANT_POOL_ADDRESS_P (operands[1])
1131 && get_pool_mode (operands[1]) == DImode
1132 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1133 [(set (match_dup 0) (match_dup 2))]
1134 "operands[2] = get_pool_constant (operands[1]);")
1136 (define_insn "*la_64"
1137 [(set (match_operand:DI 0 "register_operand" "=d,d")
1138 (match_operand:QI 1 "address_operand" "U,W"))]
1143 [(set_attr "op_type" "RX,RXY")
1144 (set_attr "type" "la")])
1148 [(set (match_operand:DI 0 "register_operand" "")
1149 (match_operand:QI 1 "address_operand" ""))
1150 (clobber (reg:CC CC_REGNUM))])]
1152 && preferred_la_operand_p (operands[1], const0_rtx)"
1153 [(set (match_dup 0) (match_dup 1))]
1157 [(set (match_operand:DI 0 "register_operand" "")
1158 (match_operand:DI 1 "register_operand" ""))
1161 (plus:DI (match_dup 0)
1162 (match_operand:DI 2 "nonmemory_operand" "")))
1163 (clobber (reg:CC CC_REGNUM))])]
1165 && !reg_overlap_mentioned_p (operands[0], operands[2])
1166 && preferred_la_operand_p (operands[1], operands[2])"
1167 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1170 (define_expand "reload_indi"
1171 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1172 (match_operand:DI 1 "s390_plus_operand" "")
1173 (match_operand:DI 2 "register_operand" "=&a")])]
1176 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1181 ; movsi instruction pattern(s).
1184 (define_expand "movsi"
1185 [(set (match_operand:SI 0 "general_operand" "")
1186 (match_operand:SI 1 "general_operand" ""))]
1189 /* Handle symbolic constants. */
1190 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1191 emit_symbolic_move (operands);
1194 (define_insn "*movsi_larl"
1195 [(set (match_operand:SI 0 "register_operand" "=d")
1196 (match_operand:SI 1 "larl_operand" "X"))]
1197 "!TARGET_64BIT && TARGET_CPU_ZARCH
1198 && !FP_REG_P (operands[0])"
1200 [(set_attr "op_type" "RIL")
1201 (set_attr "type" "larl")])
1203 (define_insn "*movsi_zarch"
1204 [(set (match_operand:SI 0 "nonimmediate_operand"
1205 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1206 (match_operand:SI 1 "general_operand"
1207 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1230 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1231 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1232 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1233 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1235 (define_insn "*movsi_esa"
1236 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1237 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1252 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1253 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1256 [(set (match_operand:SI 0 "register_operand" "")
1257 (mem:SI (match_operand 1 "address_operand" "")))]
1258 "!FP_REG_P (operands[0])
1259 && GET_CODE (operands[1]) == SYMBOL_REF
1260 && CONSTANT_POOL_ADDRESS_P (operands[1])
1261 && get_pool_mode (operands[1]) == SImode
1262 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1263 [(set (match_dup 0) (match_dup 2))]
1264 "operands[2] = get_pool_constant (operands[1]);")
1266 (define_insn "*la_31"
1267 [(set (match_operand:SI 0 "register_operand" "=d,d")
1268 (match_operand:QI 1 "address_operand" "U,W"))]
1269 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1273 [(set_attr "op_type" "RX,RXY")
1274 (set_attr "type" "la")])
1278 [(set (match_operand:SI 0 "register_operand" "")
1279 (match_operand:QI 1 "address_operand" ""))
1280 (clobber (reg:CC CC_REGNUM))])]
1282 && preferred_la_operand_p (operands[1], const0_rtx)"
1283 [(set (match_dup 0) (match_dup 1))]
1287 [(set (match_operand:SI 0 "register_operand" "")
1288 (match_operand:SI 1 "register_operand" ""))
1291 (plus:SI (match_dup 0)
1292 (match_operand:SI 2 "nonmemory_operand" "")))
1293 (clobber (reg:CC CC_REGNUM))])]
1295 && !reg_overlap_mentioned_p (operands[0], operands[2])
1296 && preferred_la_operand_p (operands[1], operands[2])"
1297 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1300 (define_insn "*la_31_and"
1301 [(set (match_operand:SI 0 "register_operand" "=d,d")
1302 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1303 (const_int 2147483647)))]
1308 [(set_attr "op_type" "RX,RXY")
1309 (set_attr "type" "la")])
1311 (define_insn_and_split "*la_31_and_cc"
1312 [(set (match_operand:SI 0 "register_operand" "=d")
1313 (and:SI (match_operand:QI 1 "address_operand" "p")
1314 (const_int 2147483647)))
1315 (clobber (reg:CC CC_REGNUM))]
1318 "&& reload_completed"
1320 (and:SI (match_dup 1) (const_int 2147483647)))]
1322 [(set_attr "op_type" "RX")
1323 (set_attr "type" "la")])
1325 (define_insn "force_la_31"
1326 [(set (match_operand:SI 0 "register_operand" "=d,d")
1327 (match_operand:QI 1 "address_operand" "U,W"))
1328 (use (const_int 0))]
1333 [(set_attr "op_type" "RX")
1334 (set_attr "type" "la")])
1336 (define_expand "reload_insi"
1337 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1338 (match_operand:SI 1 "s390_plus_operand" "")
1339 (match_operand:SI 2 "register_operand" "=&a")])]
1342 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1347 ; movhi instruction pattern(s).
1350 (define_expand "movhi"
1351 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1352 (match_operand:HI 1 "general_operand" ""))]
1355 /* Make it explicit that loading a register from memory
1356 always sign-extends (at least) to SImode. */
1357 if (optimize && !no_new_pseudos
1358 && register_operand (operands[0], VOIDmode)
1359 && GET_CODE (operands[1]) == MEM)
1361 rtx tmp = gen_reg_rtx (SImode);
1362 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1363 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1364 operands[1] = gen_lowpart (HImode, tmp);
1368 (define_insn "*movhi"
1369 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1370 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1380 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1381 (set_attr "type" "lr,*,*,*,store,store,*")])
1384 [(set (match_operand:HI 0 "register_operand" "")
1385 (mem:HI (match_operand 1 "address_operand" "")))]
1386 "GET_CODE (operands[1]) == SYMBOL_REF
1387 && CONSTANT_POOL_ADDRESS_P (operands[1])
1388 && get_pool_mode (operands[1]) == HImode
1389 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1390 [(set (match_dup 0) (match_dup 2))]
1391 "operands[2] = get_pool_constant (operands[1]);")
1394 ; movqi instruction pattern(s).
1397 (define_expand "movqi"
1398 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1399 (match_operand:QI 1 "general_operand" ""))]
1402 /* On z/Architecture, zero-extending from memory to register
1403 is just as fast as a QImode load. */
1404 if (TARGET_ZARCH && optimize && !no_new_pseudos
1405 && register_operand (operands[0], VOIDmode)
1406 && GET_CODE (operands[1]) == MEM)
1408 rtx tmp = gen_reg_rtx (word_mode);
1409 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1410 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1411 operands[1] = gen_lowpart (QImode, tmp);
1415 (define_insn "*movqi"
1416 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1417 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1429 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1430 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1433 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1434 (mem:QI (match_operand 1 "address_operand" "")))]
1435 "GET_CODE (operands[1]) == SYMBOL_REF
1436 && CONSTANT_POOL_ADDRESS_P (operands[1])
1437 && get_pool_mode (operands[1]) == QImode
1438 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1439 [(set (match_dup 0) (match_dup 2))]
1440 "operands[2] = get_pool_constant (operands[1]);")
1443 ; movstrictqi instruction pattern(s).
1446 (define_insn "*movstrictqi"
1447 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1448 (match_operand:QI 1 "memory_operand" "R,T"))]
1453 [(set_attr "op_type" "RX,RXY")])
1456 ; movstricthi instruction pattern(s).
1459 (define_insn "*movstricthi"
1460 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1461 (match_operand:HI 1 "memory_operand" "Q,S"))
1462 (clobber (reg:CC CC_REGNUM))]
1467 [(set_attr "op_type" "RS,RSY")])
1470 ; movstrictsi instruction pattern(s).
1473 (define_insn "movstrictsi"
1474 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1475 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1482 [(set_attr "op_type" "RR,RX,RXY,RRE")
1483 (set_attr "type" "lr,load,load,*")])
1486 ; movdf instruction pattern(s).
1489 (define_expand "movdf"
1490 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1491 (match_operand:DF 1 "general_operand" ""))]
1495 (define_insn "*movdf_64"
1496 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1497 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1510 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1511 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1513 (define_insn "*movdf_31"
1514 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1515 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1531 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1532 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1533 lm,lm,stm,stm,*,*,*")])
1536 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1537 (match_operand:DF 1 "general_operand" ""))]
1538 "!TARGET_64BIT && reload_completed
1539 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1540 [(set (match_dup 2) (match_dup 4))
1541 (set (match_dup 3) (match_dup 5))]
1543 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1544 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1545 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1546 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1550 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1551 (match_operand:DF 1 "general_operand" ""))]
1552 "!TARGET_64BIT && reload_completed
1553 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1554 [(set (match_dup 2) (match_dup 4))
1555 (set (match_dup 3) (match_dup 5))]
1557 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1558 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1559 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1560 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1564 [(set (match_operand:DF 0 "register_operand" "")
1565 (match_operand:DF 1 "memory_operand" ""))]
1566 "!TARGET_64BIT && reload_completed
1567 && !FP_REG_P (operands[0])
1568 && !s_operand (operands[1], VOIDmode)"
1569 [(set (match_dup 0) (match_dup 1))]
1571 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1572 s390_load_address (addr, XEXP (operands[1], 0));
1573 operands[1] = replace_equiv_address (operands[1], addr);
1576 (define_expand "reload_outdf"
1577 [(parallel [(match_operand:DF 0 "" "")
1578 (match_operand:DF 1 "register_operand" "d")
1579 (match_operand:SI 2 "register_operand" "=&a")])]
1582 gcc_assert (MEM_P (operands[0]));
1583 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1584 operands[0] = replace_equiv_address (operands[0], operands[2]);
1585 emit_move_insn (operands[0], operands[1]);
1590 ; movsf instruction pattern(s).
1593 (define_insn "movsf"
1594 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1595 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1610 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1611 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1612 lr,load,load,store,store,*")])
1615 ; movcc instruction pattern
1618 (define_insn "movcc"
1619 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1620 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1630 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1631 (set_attr "type" "lr,*,*,store,store,load,load")])
1634 ; Block move (MVC) patterns.
1638 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1639 (match_operand:BLK 1 "memory_operand" "Q"))
1640 (use (match_operand 2 "const_int_operand" "n"))]
1641 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1642 "mvc\t%O0(%2,%R0),%S1"
1643 [(set_attr "op_type" "SS")])
1646 [(set (match_operand 0 "memory_operand" "")
1647 (match_operand 1 "memory_operand" ""))]
1649 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1650 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1652 [(set (match_dup 0) (match_dup 1))
1653 (use (match_dup 2))])]
1655 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1656 operands[0] = adjust_address (operands[0], BLKmode, 0);
1657 operands[1] = adjust_address (operands[1], BLKmode, 0);
1662 [(set (match_operand:BLK 0 "memory_operand" "")
1663 (match_operand:BLK 1 "memory_operand" ""))
1664 (use (match_operand 2 "const_int_operand" ""))])
1666 [(set (match_operand:BLK 3 "memory_operand" "")
1667 (match_operand:BLK 4 "memory_operand" ""))
1668 (use (match_operand 5 "const_int_operand" ""))])]
1669 "s390_offset_p (operands[0], operands[3], operands[2])
1670 && s390_offset_p (operands[1], operands[4], operands[2])
1671 && !s390_overlap_p (operands[0], operands[1],
1672 INTVAL (operands[2]) + INTVAL (operands[5]))
1673 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1675 [(set (match_dup 6) (match_dup 7))
1676 (use (match_dup 8))])]
1677 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1678 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1679 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1683 ; load_multiple pattern(s).
1685 ; ??? Due to reload problems with replacing registers inside match_parallel
1686 ; we currently support load_multiple/store_multiple only after reload.
1689 (define_expand "load_multiple"
1690 [(match_par_dup 3 [(set (match_operand 0 "" "")
1691 (match_operand 1 "" ""))
1692 (use (match_operand 2 "" ""))])]
1695 enum machine_mode mode;
1701 /* Support only loading a constant number of fixed-point registers from
1702 memory and only bother with this if more than two */
1703 if (GET_CODE (operands[2]) != CONST_INT
1704 || INTVAL (operands[2]) < 2
1705 || INTVAL (operands[2]) > 16
1706 || GET_CODE (operands[1]) != MEM
1707 || GET_CODE (operands[0]) != REG
1708 || REGNO (operands[0]) >= 16)
1711 count = INTVAL (operands[2]);
1712 regno = REGNO (operands[0]);
1713 mode = GET_MODE (operands[0]);
1714 if (mode != SImode && mode != word_mode)
1717 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1720 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1722 from = XEXP (operands[1], 0);
1725 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1726 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1727 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1729 from = XEXP (XEXP (operands[1], 0), 0);
1730 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1737 from = force_reg (Pmode, XEXP (operands[1], 0));
1741 for (i = 0; i < count; i++)
1742 XVECEXP (operands[3], 0, i)
1743 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1744 change_address (operands[1], mode,
1745 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1748 (define_insn "*load_multiple_di"
1749 [(match_parallel 0 "load_multiple_operation"
1750 [(set (match_operand:DI 1 "register_operand" "=r")
1751 (match_operand:DI 2 "s_operand" "QS"))])]
1752 "reload_completed && word_mode == DImode"
1754 int words = XVECLEN (operands[0], 0);
1755 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1756 return "lmg\t%1,%0,%S2";
1758 [(set_attr "op_type" "RSY")
1759 (set_attr "type" "lm")])
1761 (define_insn "*load_multiple_si"
1762 [(match_parallel 0 "load_multiple_operation"
1763 [(set (match_operand:SI 1 "register_operand" "=r,r")
1764 (match_operand:SI 2 "s_operand" "Q,S"))])]
1767 int words = XVECLEN (operands[0], 0);
1768 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1769 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1771 [(set_attr "op_type" "RS,RSY")
1772 (set_attr "type" "lm")])
1775 ; store multiple pattern(s).
1778 (define_expand "store_multiple"
1779 [(match_par_dup 3 [(set (match_operand 0 "" "")
1780 (match_operand 1 "" ""))
1781 (use (match_operand 2 "" ""))])]
1784 enum machine_mode mode;
1790 /* Support only storing a constant number of fixed-point registers to
1791 memory and only bother with this if more than two. */
1792 if (GET_CODE (operands[2]) != CONST_INT
1793 || INTVAL (operands[2]) < 2
1794 || INTVAL (operands[2]) > 16
1795 || GET_CODE (operands[0]) != MEM
1796 || GET_CODE (operands[1]) != REG
1797 || REGNO (operands[1]) >= 16)
1800 count = INTVAL (operands[2]);
1801 regno = REGNO (operands[1]);
1802 mode = GET_MODE (operands[1]);
1803 if (mode != SImode && mode != word_mode)
1806 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1810 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1812 to = XEXP (operands[0], 0);
1815 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1816 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1817 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1819 to = XEXP (XEXP (operands[0], 0), 0);
1820 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1827 to = force_reg (Pmode, XEXP (operands[0], 0));
1831 for (i = 0; i < count; i++)
1832 XVECEXP (operands[3], 0, i)
1833 = gen_rtx_SET (VOIDmode,
1834 change_address (operands[0], mode,
1835 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1836 gen_rtx_REG (mode, regno + i));
1839 (define_insn "*store_multiple_di"
1840 [(match_parallel 0 "store_multiple_operation"
1841 [(set (match_operand:DI 1 "s_operand" "=QS")
1842 (match_operand:DI 2 "register_operand" "r"))])]
1843 "reload_completed && word_mode == DImode"
1845 int words = XVECLEN (operands[0], 0);
1846 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1847 return "stmg\t%2,%0,%S1";
1849 [(set_attr "op_type" "RSY")
1850 (set_attr "type" "stm")])
1853 (define_insn "*store_multiple_si"
1854 [(match_parallel 0 "store_multiple_operation"
1855 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1856 (match_operand:SI 2 "register_operand" "r,r"))])]
1859 int words = XVECLEN (operands[0], 0);
1860 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1861 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1863 [(set_attr "op_type" "RS,RSY")
1864 (set_attr "type" "stm")])
1867 ;; String instructions.
1870 (define_insn "*execute"
1871 [(match_parallel 0 ""
1872 [(unspec [(match_operand 1 "register_operand" "a")
1873 (match_operand:BLK 2 "memory_operand" "R")
1874 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1875 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1876 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1878 [(set_attr "op_type" "RX")
1879 (set_attr "type" "cs")])
1883 ; strlenM instruction pattern(s).
1886 (define_expand "strlen<mode>"
1887 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1890 (unspec:P [(const_int 0)
1891 (match_operand:BLK 1 "memory_operand" "")
1893 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1894 (clobber (scratch:P))
1895 (clobber (reg:CC CC_REGNUM))])
1897 [(set (match_operand:P 0 "register_operand" "")
1898 (minus:P (match_dup 4) (match_dup 5)))
1899 (clobber (reg:CC CC_REGNUM))])]
1902 operands[4] = gen_reg_rtx (Pmode);
1903 operands[5] = gen_reg_rtx (Pmode);
1904 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1905 operands[1] = replace_equiv_address (operands[1], operands[5]);
1908 (define_insn "*strlen<mode>"
1909 [(set (match_operand:P 0 "register_operand" "=a")
1910 (unspec:P [(match_operand:P 2 "general_operand" "0")
1911 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1913 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1914 (clobber (match_scratch:P 1 "=a"))
1915 (clobber (reg:CC CC_REGNUM))]
1917 "srst\t%0,%1\;jo\t.-4"
1918 [(set_attr "length" "8")
1919 (set_attr "type" "vs")])
1922 ; cmpstrM instruction pattern(s).
1925 (define_expand "cmpstrsi"
1926 [(set (reg:SI 0) (const_int 0))
1928 [(clobber (match_operand 3 "" ""))
1929 (clobber (match_dup 4))
1930 (set (reg:CCU CC_REGNUM)
1931 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1932 (match_operand:BLK 2 "memory_operand" "")))
1935 [(set (match_operand:SI 0 "register_operand" "=d")
1936 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1937 (clobber (reg:CC CC_REGNUM))])]
1940 /* As the result of CMPINT is inverted compared to what we need,
1941 we have to swap the operands. */
1942 rtx op1 = operands[2];
1943 rtx op2 = operands[1];
1944 rtx addr1 = gen_reg_rtx (Pmode);
1945 rtx addr2 = gen_reg_rtx (Pmode);
1947 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1948 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1949 operands[1] = replace_equiv_address_nv (op1, addr1);
1950 operands[2] = replace_equiv_address_nv (op2, addr2);
1951 operands[3] = addr1;
1952 operands[4] = addr2;
1955 (define_insn "*cmpstr<mode>"
1956 [(clobber (match_operand:P 0 "register_operand" "=d"))
1957 (clobber (match_operand:P 1 "register_operand" "=d"))
1958 (set (reg:CCU CC_REGNUM)
1959 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1960 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1963 "clst\t%0,%1\;jo\t.-4"
1964 [(set_attr "length" "8")
1965 (set_attr "type" "vs")])
1968 ; movstr instruction pattern.
1971 (define_expand "movstr"
1972 [(set (reg:SI 0) (const_int 0))
1974 [(clobber (match_dup 3))
1975 (set (match_operand:BLK 1 "memory_operand" "")
1976 (match_operand:BLK 2 "memory_operand" ""))
1977 (set (match_operand 0 "register_operand" "")
1978 (unspec [(match_dup 1)
1980 (reg:SI 0)] UNSPEC_MVST))
1981 (clobber (reg:CC CC_REGNUM))])]
1984 rtx addr1 = gen_reg_rtx (Pmode);
1985 rtx addr2 = gen_reg_rtx (Pmode);
1987 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1988 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1989 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1990 operands[2] = replace_equiv_address_nv (operands[2], addr2);
1991 operands[3] = addr2;
1994 (define_insn "*movstr"
1995 [(clobber (match_operand:P 2 "register_operand" "=d"))
1996 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
1997 (mem:BLK (match_operand:P 3 "register_operand" "2")))
1998 (set (match_operand:P 0 "register_operand" "=d")
1999 (unspec [(mem:BLK (match_dup 1))
2000 (mem:BLK (match_dup 3))
2001 (reg:SI 0)] UNSPEC_MVST))
2002 (clobber (reg:CC CC_REGNUM))]
2004 "mvst\t%1,%2\;jo\t.-4"
2005 [(set_attr "length" "8")
2006 (set_attr "type" "vs")])
2010 ; movmemM instruction pattern(s).
2013 (define_expand "movmem<mode>"
2014 [(set (match_operand:BLK 0 "memory_operand" "")
2015 (match_operand:BLK 1 "memory_operand" ""))
2016 (use (match_operand:GPR 2 "general_operand" ""))
2017 (match_operand 3 "" "")]
2019 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2021 ; Move a block that is up to 256 bytes in length.
2022 ; The block length is taken as (operands[2] % 256) + 1.
2024 (define_expand "movmem_short"
2026 [(set (match_operand:BLK 0 "memory_operand" "")
2027 (match_operand:BLK 1 "memory_operand" ""))
2028 (use (match_operand 2 "nonmemory_operand" ""))
2029 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2030 (clobber (match_dup 3))])]
2032 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2034 (define_insn "*movmem_short"
2035 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2036 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2037 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2038 (use (match_operand 3 "immediate_operand" "X,R,X"))
2039 (clobber (match_scratch 4 "=X,X,&a"))]
2040 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2041 && GET_MODE (operands[4]) == Pmode"
2043 [(set_attr "type" "cs")])
2046 [(set (match_operand:BLK 0 "memory_operand" "")
2047 (match_operand:BLK 1 "memory_operand" ""))
2048 (use (match_operand 2 "const_int_operand" ""))
2049 (use (match_operand 3 "immediate_operand" ""))
2050 (clobber (scratch))]
2053 [(set (match_dup 0) (match_dup 1))
2054 (use (match_dup 2))])]
2055 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2058 [(set (match_operand:BLK 0 "memory_operand" "")
2059 (match_operand:BLK 1 "memory_operand" ""))
2060 (use (match_operand 2 "register_operand" ""))
2061 (use (match_operand 3 "memory_operand" ""))
2062 (clobber (scratch))]
2065 [(unspec [(match_dup 2) (match_dup 3)
2066 (const_int 0)] UNSPEC_EXECUTE)
2067 (set (match_dup 0) (match_dup 1))
2068 (use (const_int 1))])]
2072 [(set (match_operand:BLK 0 "memory_operand" "")
2073 (match_operand:BLK 1 "memory_operand" ""))
2074 (use (match_operand 2 "register_operand" ""))
2075 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2076 (clobber (match_operand 3 "register_operand" ""))]
2077 "reload_completed && TARGET_CPU_ZARCH"
2078 [(set (match_dup 3) (label_ref (match_dup 4)))
2080 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2081 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2082 (set (match_dup 0) (match_dup 1))
2083 (use (const_int 1))])]
2084 "operands[4] = gen_label_rtx ();")
2086 ; Move a block of arbitrary length.
2088 (define_expand "movmem_long"
2090 [(clobber (match_dup 2))
2091 (clobber (match_dup 3))
2092 (set (match_operand:BLK 0 "memory_operand" "")
2093 (match_operand:BLK 1 "memory_operand" ""))
2094 (use (match_operand 2 "general_operand" ""))
2096 (clobber (reg:CC CC_REGNUM))])]
2099 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2100 rtx reg0 = gen_reg_rtx (dword_mode);
2101 rtx reg1 = gen_reg_rtx (dword_mode);
2102 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2103 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2104 rtx len0 = gen_lowpart (Pmode, reg0);
2105 rtx len1 = gen_lowpart (Pmode, reg1);
2107 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2108 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2109 emit_move_insn (len0, operands[2]);
2111 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2112 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2113 emit_move_insn (len1, operands[2]);
2115 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2116 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2121 (define_insn "*movmem_long"
2122 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2123 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2124 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2125 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2128 (clobber (reg:CC CC_REGNUM))]
2130 "mvcle\t%0,%1,0\;jo\t.-4"
2131 [(set_attr "length" "8")
2132 (set_attr "type" "vs")])
2135 ; setmemM instruction pattern(s).
2138 (define_expand "setmem<mode>"
2139 [(set (match_operand:BLK 0 "memory_operand" "")
2140 (match_operand:QI 2 "general_operand" ""))
2141 (use (match_operand:GPR 1 "general_operand" ""))
2142 (match_operand 3 "" "")]
2144 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2146 ; Clear a block that is up to 256 bytes in length.
2147 ; The block length is taken as (operands[1] % 256) + 1.
2149 (define_expand "clrmem_short"
2151 [(set (match_operand:BLK 0 "memory_operand" "")
2153 (use (match_operand 1 "nonmemory_operand" ""))
2154 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2155 (clobber (match_dup 2))
2156 (clobber (reg:CC CC_REGNUM))])]
2158 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2160 (define_insn "*clrmem_short"
2161 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2163 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2164 (use (match_operand 2 "immediate_operand" "X,R,X"))
2165 (clobber (match_scratch 3 "=X,X,&a"))
2166 (clobber (reg:CC CC_REGNUM))]
2167 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2168 && GET_MODE (operands[3]) == Pmode"
2170 [(set_attr "type" "cs")])
2173 [(set (match_operand:BLK 0 "memory_operand" "")
2175 (use (match_operand 1 "const_int_operand" ""))
2176 (use (match_operand 2 "immediate_operand" ""))
2178 (clobber (reg:CC CC_REGNUM))]
2181 [(set (match_dup 0) (const_int 0))
2183 (clobber (reg:CC CC_REGNUM))])]
2184 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2187 [(set (match_operand:BLK 0 "memory_operand" "")
2189 (use (match_operand 1 "register_operand" ""))
2190 (use (match_operand 2 "memory_operand" ""))
2192 (clobber (reg:CC CC_REGNUM))]
2195 [(unspec [(match_dup 1) (match_dup 2)
2196 (const_int 0)] UNSPEC_EXECUTE)
2197 (set (match_dup 0) (const_int 0))
2199 (clobber (reg:CC CC_REGNUM))])]
2203 [(set (match_operand:BLK 0 "memory_operand" "")
2205 (use (match_operand 1 "register_operand" ""))
2206 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2207 (clobber (match_operand 2 "register_operand" ""))
2208 (clobber (reg:CC CC_REGNUM))]
2209 "reload_completed && TARGET_CPU_ZARCH"
2210 [(set (match_dup 2) (label_ref (match_dup 3)))
2212 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2213 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2214 (set (match_dup 0) (const_int 0))
2216 (clobber (reg:CC CC_REGNUM))])]
2217 "operands[3] = gen_label_rtx ();")
2219 ; Initialize a block of arbitrary length with (operands[2] % 256).
2221 (define_expand "setmem_long"
2223 [(clobber (match_dup 1))
2224 (set (match_operand:BLK 0 "memory_operand" "")
2225 (match_operand 2 "shift_count_or_setmem_operand" ""))
2226 (use (match_operand 1 "general_operand" ""))
2228 (clobber (reg:CC CC_REGNUM))])]
2231 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2232 rtx reg0 = gen_reg_rtx (dword_mode);
2233 rtx reg1 = gen_reg_rtx (dword_mode);
2234 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2235 rtx len0 = gen_lowpart (Pmode, reg0);
2237 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2238 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2239 emit_move_insn (len0, operands[1]);
2241 emit_move_insn (reg1, const0_rtx);
2243 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2248 (define_insn "*setmem_long"
2249 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2250 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2251 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2253 (use (match_operand:<DBL> 1 "register_operand" "d"))
2254 (clobber (reg:CC CC_REGNUM))]
2256 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2257 [(set_attr "length" "8")
2258 (set_attr "type" "vs")])
2260 (define_insn "*setmem_long_and"
2261 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2262 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2263 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2264 (match_operand 4 "const_int_operand" "n")))
2266 (use (match_operand:<DBL> 1 "register_operand" "d"))
2267 (clobber (reg:CC CC_REGNUM))]
2268 "(INTVAL (operands[4]) & 255) == 255"
2269 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2270 [(set_attr "length" "8")
2271 (set_attr "type" "vs")])
2273 ; cmpmemM instruction pattern(s).
2276 (define_expand "cmpmemsi"
2277 [(set (match_operand:SI 0 "register_operand" "")
2278 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2279 (match_operand:BLK 2 "memory_operand" "") ) )
2280 (use (match_operand:SI 3 "general_operand" ""))
2281 (use (match_operand:SI 4 "" ""))]
2283 "s390_expand_cmpmem (operands[0], operands[1],
2284 operands[2], operands[3]); DONE;")
2286 ; Compare a block that is up to 256 bytes in length.
2287 ; The block length is taken as (operands[2] % 256) + 1.
2289 (define_expand "cmpmem_short"
2291 [(set (reg:CCU CC_REGNUM)
2292 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2293 (match_operand:BLK 1 "memory_operand" "")))
2294 (use (match_operand 2 "nonmemory_operand" ""))
2295 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2296 (clobber (match_dup 3))])]
2298 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2300 (define_insn "*cmpmem_short"
2301 [(set (reg:CCU CC_REGNUM)
2302 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2303 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2304 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2305 (use (match_operand 3 "immediate_operand" "X,R,X"))
2306 (clobber (match_scratch 4 "=X,X,&a"))]
2307 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2308 && GET_MODE (operands[4]) == Pmode"
2310 [(set_attr "type" "cs")])
2313 [(set (reg:CCU CC_REGNUM)
2314 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2315 (match_operand:BLK 1 "memory_operand" "")))
2316 (use (match_operand 2 "const_int_operand" ""))
2317 (use (match_operand 3 "immediate_operand" ""))
2318 (clobber (scratch))]
2321 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2322 (use (match_dup 2))])]
2323 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2326 [(set (reg:CCU CC_REGNUM)
2327 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2328 (match_operand:BLK 1 "memory_operand" "")))
2329 (use (match_operand 2 "register_operand" ""))
2330 (use (match_operand 3 "memory_operand" ""))
2331 (clobber (scratch))]
2334 [(unspec [(match_dup 2) (match_dup 3)
2335 (const_int 0)] UNSPEC_EXECUTE)
2336 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2337 (use (const_int 1))])]
2341 [(set (reg:CCU CC_REGNUM)
2342 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2343 (match_operand:BLK 1 "memory_operand" "")))
2344 (use (match_operand 2 "register_operand" ""))
2345 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2346 (clobber (match_operand 3 "register_operand" ""))]
2347 "reload_completed && TARGET_CPU_ZARCH"
2348 [(set (match_dup 3) (label_ref (match_dup 4)))
2350 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2351 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2352 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2353 (use (const_int 1))])]
2354 "operands[4] = gen_label_rtx ();")
2356 ; Compare a block of arbitrary length.
2358 (define_expand "cmpmem_long"
2360 [(clobber (match_dup 2))
2361 (clobber (match_dup 3))
2362 (set (reg:CCU CC_REGNUM)
2363 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2364 (match_operand:BLK 1 "memory_operand" "")))
2365 (use (match_operand 2 "general_operand" ""))
2366 (use (match_dup 3))])]
2369 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2370 rtx reg0 = gen_reg_rtx (dword_mode);
2371 rtx reg1 = gen_reg_rtx (dword_mode);
2372 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2373 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2374 rtx len0 = gen_lowpart (Pmode, reg0);
2375 rtx len1 = gen_lowpart (Pmode, reg1);
2377 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2378 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2379 emit_move_insn (len0, operands[2]);
2381 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2382 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2383 emit_move_insn (len1, operands[2]);
2385 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2386 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2391 (define_insn "*cmpmem_long"
2392 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2393 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2394 (set (reg:CCU CC_REGNUM)
2395 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2396 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2398 (use (match_dup 3))]
2400 "clcle\t%0,%1,0\;jo\t.-4"
2401 [(set_attr "length" "8")
2402 (set_attr "type" "vs")])
2404 ; Convert CCUmode condition code to integer.
2405 ; Result is zero if EQ, positive if LTU, negative if GTU.
2407 (define_insn_and_split "cmpint"
2408 [(set (match_operand:SI 0 "register_operand" "=d")
2409 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2411 (clobber (reg:CC CC_REGNUM))]
2415 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2417 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2418 (clobber (reg:CC CC_REGNUM))])])
2420 (define_insn_and_split "*cmpint_cc"
2421 [(set (reg CC_REGNUM)
2422 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2425 (set (match_operand:SI 0 "register_operand" "=d")
2426 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2427 "s390_match_ccmode (insn, CCSmode)"
2429 "&& reload_completed"
2430 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2432 [(set (match_dup 2) (match_dup 3))
2433 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2435 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2436 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2437 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2440 (define_insn_and_split "*cmpint_sign"
2441 [(set (match_operand:DI 0 "register_operand" "=d")
2442 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2444 (clobber (reg:CC CC_REGNUM))]
2447 "&& reload_completed"
2448 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2450 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2451 (clobber (reg:CC CC_REGNUM))])])
2453 (define_insn_and_split "*cmpint_sign_cc"
2454 [(set (reg CC_REGNUM)
2455 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2456 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2458 (const_int 32)) (const_int 32))
2460 (set (match_operand:DI 0 "register_operand" "=d")
2461 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2462 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2464 "&& reload_completed"
2465 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2467 [(set (match_dup 2) (match_dup 3))
2468 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2470 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2471 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2472 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2477 ;;- Conversion instructions.
2480 (define_insn "*sethighpartsi"
2481 [(set (match_operand:SI 0 "register_operand" "=d,d")
2482 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2483 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2484 (clobber (reg:CC CC_REGNUM))]
2489 [(set_attr "op_type" "RS,RSY")])
2491 (define_insn "*sethighpartdi_64"
2492 [(set (match_operand:DI 0 "register_operand" "=d")
2493 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2494 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2495 (clobber (reg:CC CC_REGNUM))]
2498 [(set_attr "op_type" "RSY")])
2500 (define_insn "*sethighpartdi_31"
2501 [(set (match_operand:DI 0 "register_operand" "=d,d")
2502 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2503 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2504 (clobber (reg:CC CC_REGNUM))]
2509 [(set_attr "op_type" "RS,RSY")])
2511 (define_insn_and_split "*extzv<mode>"
2512 [(set (match_operand:GPR 0 "register_operand" "=d")
2513 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2514 (match_operand 2 "const_int_operand" "n")
2516 (clobber (reg:CC CC_REGNUM))]
2517 "INTVAL (operands[2]) > 0
2518 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2520 "&& reload_completed"
2522 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2523 (clobber (reg:CC CC_REGNUM))])
2524 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2526 int bitsize = INTVAL (operands[2]);
2527 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2528 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2530 operands[1] = adjust_address (operands[1], BLKmode, 0);
2531 set_mem_size (operands[1], GEN_INT (size));
2532 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2533 operands[3] = GEN_INT (mask);
2536 (define_insn_and_split "*extv<mode>"
2537 [(set (match_operand:GPR 0 "register_operand" "=d")
2538 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2539 (match_operand 2 "const_int_operand" "n")
2541 (clobber (reg:CC CC_REGNUM))]
2542 "INTVAL (operands[2]) > 0
2543 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2545 "&& reload_completed"
2547 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2548 (clobber (reg:CC CC_REGNUM))])
2550 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2551 (clobber (reg:CC CC_REGNUM))])]
2553 int bitsize = INTVAL (operands[2]);
2554 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2555 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2557 operands[1] = adjust_address (operands[1], BLKmode, 0);
2558 set_mem_size (operands[1], GEN_INT (size));
2559 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2560 operands[3] = GEN_INT (mask);
2564 ; insv instruction patterns
2567 (define_expand "insv"
2568 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2569 (match_operand 1 "const_int_operand" "")
2570 (match_operand 2 "const_int_operand" ""))
2571 (match_operand 3 "general_operand" ""))]
2574 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2579 (define_insn "*insv<mode>_mem_reg"
2580 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2581 (match_operand 1 "const_int_operand" "n,n")
2583 (match_operand:P 2 "register_operand" "d,d"))]
2584 "INTVAL (operands[1]) > 0
2585 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2586 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2588 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2590 operands[1] = GEN_INT ((1ul << size) - 1);
2591 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2592 : "stcmy\t%2,%1,%S0";
2594 [(set_attr "op_type" "RS,RSY")])
2596 (define_insn "*insvdi_mem_reghigh"
2597 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2598 (match_operand 1 "const_int_operand" "n")
2600 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2603 && INTVAL (operands[1]) > 0
2604 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2605 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2607 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2609 operands[1] = GEN_INT ((1ul << size) - 1);
2610 return "stcmh\t%2,%1,%S0";
2612 [(set_attr "op_type" "RSY")])
2614 (define_insn "*insv<mode>_reg_imm"
2615 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2617 (match_operand 1 "const_int_operand" "n"))
2618 (match_operand 2 "const_int_operand" "n"))]
2620 && INTVAL (operands[1]) >= 0
2621 && INTVAL (operands[1]) < BITS_PER_WORD
2622 && INTVAL (operands[1]) % 16 == 0"
2624 switch (BITS_PER_WORD - INTVAL (operands[1]))
2626 case 64: return "iihh\t%0,%x2"; break;
2627 case 48: return "iihl\t%0,%x2"; break;
2628 case 32: return "iilh\t%0,%x2"; break;
2629 case 16: return "iill\t%0,%x2"; break;
2630 default: gcc_unreachable();
2633 [(set_attr "op_type" "RI")])
2635 (define_insn "*insv<mode>_reg_extimm"
2636 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2638 (match_operand 1 "const_int_operand" "n"))
2639 (match_operand 2 "const_int_operand" "n"))]
2641 && INTVAL (operands[1]) >= 0
2642 && INTVAL (operands[1]) < BITS_PER_WORD
2643 && INTVAL (operands[1]) % 32 == 0"
2645 switch (BITS_PER_WORD - INTVAL (operands[1]))
2647 case 64: return "iihf\t%0,%o2"; break;
2648 case 32: return "iilf\t%0,%o2"; break;
2649 default: gcc_unreachable();
2652 [(set_attr "op_type" "RIL")])
2655 ; extendsidi2 instruction pattern(s).
2658 (define_expand "extendsidi2"
2659 [(set (match_operand:DI 0 "register_operand" "")
2660 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2665 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2666 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2667 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2668 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2673 (define_insn "*extendsidi2"
2674 [(set (match_operand:DI 0 "register_operand" "=d,d")
2675 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2680 [(set_attr "op_type" "RRE,RXY")])
2683 ; extend(hi|qi)di2 instruction pattern(s).
2686 (define_expand "extend<mode>di2"
2687 [(set (match_operand:DI 0 "register_operand" "")
2688 (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2693 rtx tmp = gen_reg_rtx (SImode);
2694 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2695 emit_insn (gen_extendsidi2 (operands[0], tmp));
2698 else if (!TARGET_EXTIMM)
2700 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2701 GET_MODE_BITSIZE (<MODE>mode));
2702 operands[1] = gen_lowpart (DImode, operands[1]);
2703 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2704 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2709 (define_insn "*extendhidi2_extimm"
2710 [(set (match_operand:DI 0 "register_operand" "=d,d")
2711 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2712 "TARGET_64BIT && TARGET_EXTIMM"
2716 [(set_attr "op_type" "RRE,RXY")])
2718 (define_insn "*extendhidi2"
2719 [(set (match_operand:DI 0 "register_operand" "=d")
2720 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2723 [(set_attr "op_type" "RXY")])
2725 (define_insn "*extendqidi2_extimm"
2726 [(set (match_operand:DI 0 "register_operand" "=d,d")
2727 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2728 "TARGET_64BIT && TARGET_EXTIMM"
2732 [(set_attr "op_type" "RRE,RXY")])
2734 (define_insn "*extendqidi2"
2735 [(set (match_operand:DI 0 "register_operand" "=d")
2736 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2737 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2739 [(set_attr "op_type" "RXY")])
2741 (define_insn_and_split "*extendqidi2_short_displ"
2742 [(set (match_operand:DI 0 "register_operand" "=d")
2743 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2744 (clobber (reg:CC CC_REGNUM))]
2745 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2747 "&& reload_completed"
2749 [(set (match_dup 0) (unspec:DI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2750 (clobber (reg:CC CC_REGNUM))])
2752 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2753 (clobber (reg:CC CC_REGNUM))])]
2755 operands[1] = adjust_address (operands[1], BLKmode, 0);
2756 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2760 ; extend(hi|qi)si2 instruction pattern(s).
2763 (define_expand "extend<mode>si2"
2764 [(set (match_operand:SI 0 "register_operand" "")
2765 (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2770 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2771 GET_MODE_BITSIZE(<MODE>mode));
2772 operands[1] = gen_lowpart (SImode, operands[1]);
2773 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2774 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2779 (define_insn "*extendhisi2_extimm"
2780 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2781 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2787 [(set_attr "op_type" "RRE,RX,RXY")])
2789 (define_insn "*extendhisi2"
2790 [(set (match_operand:SI 0 "register_operand" "=d,d")
2791 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2796 [(set_attr "op_type" "RX,RXY")])
2798 (define_insn "*extendqisi2_extimm"
2799 [(set (match_operand:SI 0 "register_operand" "=d,d")
2800 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2805 [(set_attr "op_type" "RRE,RXY")])
2807 (define_insn "*extendqisi2"
2808 [(set (match_operand:SI 0 "register_operand" "=d")
2809 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2810 "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
2812 [(set_attr "op_type" "RXY")])
2814 (define_insn_and_split "*extendqisi2_short_displ"
2815 [(set (match_operand:SI 0 "register_operand" "=d")
2816 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2817 (clobber (reg:CC CC_REGNUM))]
2818 "!TARGET_LONG_DISPLACEMENT"
2820 "&& reload_completed"
2822 [(set (match_dup 0) (unspec:SI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2823 (clobber (reg:CC CC_REGNUM))])
2825 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2826 (clobber (reg:CC CC_REGNUM))])]
2828 operands[1] = adjust_address (operands[1], BLKmode, 0);
2829 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2833 ; extendqihi2 instruction pattern(s).
2838 ; zero_extendsidi2 instruction pattern(s).
2841 (define_expand "zero_extendsidi2"
2842 [(set (match_operand:DI 0 "register_operand" "")
2843 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2848 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2849 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2850 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2855 (define_insn "*zero_extendsidi2"
2856 [(set (match_operand:DI 0 "register_operand" "=d,d")
2857 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2862 [(set_attr "op_type" "RRE,RXY")])
2865 ; zero_extend(hi|qi)di2 instruction pattern(s).
2868 (define_expand "zero_extend<mode>di2"
2869 [(set (match_operand:DI 0 "register_operand" "")
2870 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2875 rtx tmp = gen_reg_rtx (SImode);
2876 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2877 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2880 else if (!TARGET_EXTIMM)
2882 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2883 GET_MODE_BITSIZE(<MODE>mode));
2884 operands[1] = gen_lowpart (DImode, operands[1]);
2885 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2886 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2891 (define_insn "*zero_extend<mode>di2_extimm"
2892 [(set (match_operand:DI 0 "register_operand" "=d,d")
2893 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2894 "TARGET_64BIT && TARGET_EXTIMM"
2898 [(set_attr "op_type" "RRE,RXY")])
2900 (define_insn "*zero_extend<mode>di2"
2901 [(set (match_operand:DI 0 "register_operand" "=d")
2902 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2903 "TARGET_64BIT && !TARGET_EXTIMM"
2905 [(set_attr "op_type" "RXY")])
2908 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2911 (define_insn "*llgt_sidi"
2912 [(set (match_operand:DI 0 "register_operand" "=d")
2913 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2914 (const_int 2147483647)))]
2917 [(set_attr "op_type" "RXE")])
2919 (define_insn_and_split "*llgt_sidi_split"
2920 [(set (match_operand:DI 0 "register_operand" "=d")
2921 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2922 (const_int 2147483647)))
2923 (clobber (reg:CC CC_REGNUM))]
2926 "&& reload_completed"
2928 (and:DI (subreg:DI (match_dup 1) 0)
2929 (const_int 2147483647)))]
2932 (define_insn "*llgt_sisi"
2933 [(set (match_operand:SI 0 "register_operand" "=d,d")
2934 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2935 (const_int 2147483647)))]
2940 [(set_attr "op_type" "RRE,RXE")])
2942 (define_insn "*llgt_didi"
2943 [(set (match_operand:DI 0 "register_operand" "=d,d")
2944 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2945 (const_int 2147483647)))]
2950 [(set_attr "op_type" "RRE,RXE")])
2953 [(set (match_operand:GPR 0 "register_operand" "")
2954 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2955 (const_int 2147483647)))
2956 (clobber (reg:CC CC_REGNUM))]
2957 "TARGET_ZARCH && reload_completed"
2959 (and:GPR (match_dup 1)
2960 (const_int 2147483647)))]
2964 ; zero_extend(hi|qi)si2 instruction pattern(s).
2967 (define_expand "zero_extend<mode>si2"
2968 [(set (match_operand:SI 0 "register_operand" "")
2969 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2974 operands[1] = gen_lowpart (SImode, operands[1]);
2975 emit_insn (gen_andsi3 (operands[0], operands[1],
2976 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2981 (define_insn "*zero_extend<mode>si2_extimm"
2982 [(set (match_operand:SI 0 "register_operand" "=d,d")
2983 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2988 [(set_attr "op_type" "RRE,RXY")])
2990 (define_insn "*zero_extend<mode>si2_64"
2991 [(set (match_operand:SI 0 "register_operand" "=d")
2992 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2993 "TARGET_ZARCH && !TARGET_EXTIMM"
2995 [(set_attr "op_type" "RXY")])
2997 (define_insn_and_split "*zero_extendhisi2_31"
2998 [(set (match_operand:SI 0 "register_operand" "=&d")
2999 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3000 (clobber (reg:CC CC_REGNUM))]
3003 "&& reload_completed"
3004 [(set (match_dup 0) (const_int 0))
3006 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3007 (clobber (reg:CC CC_REGNUM))])]
3008 "operands[2] = gen_lowpart (HImode, operands[0]);")
3010 (define_insn_and_split "*zero_extendqisi2_31"
3011 [(set (match_operand:SI 0 "register_operand" "=&d")
3012 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3015 "&& reload_completed"
3016 [(set (match_dup 0) (const_int 0))
3017 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3018 "operands[2] = gen_lowpart (QImode, operands[0]);")
3021 ; zero_extendqihi2 instruction pattern(s).
3024 (define_expand "zero_extendqihi2"
3025 [(set (match_operand:HI 0 "register_operand" "")
3026 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3027 "TARGET_ZARCH && !TARGET_EXTIMM"
3029 operands[1] = gen_lowpart (HImode, operands[1]);
3030 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3034 (define_insn "*zero_extendqihi2_64"
3035 [(set (match_operand:HI 0 "register_operand" "=d")
3036 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3037 "TARGET_ZARCH && !TARGET_EXTIMM"
3039 [(set_attr "op_type" "RXY")])
3041 (define_insn_and_split "*zero_extendqihi2_31"
3042 [(set (match_operand:HI 0 "register_operand" "=&d")
3043 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3046 "&& reload_completed"
3047 [(set (match_dup 0) (const_int 0))
3048 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3049 "operands[2] = gen_lowpart (QImode, operands[0]);")
3053 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
3056 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
3057 [(set (match_operand:GPR 0 "register_operand" "")
3058 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
3059 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3061 rtx label1 = gen_label_rtx ();
3062 rtx label2 = gen_label_rtx ();
3063 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
3064 REAL_VALUE_TYPE cmp, sub;
3066 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
3067 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
3068 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
3070 emit_insn (gen_cmp<FPR:mode> (operands[1],
3071 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
3072 emit_jump_insn (gen_blt (label1));
3073 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
3074 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
3075 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
3079 emit_label (label1);
3080 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
3081 operands[1], GEN_INT(5)));
3082 emit_label (label2);
3086 (define_expand "fix_trunc<FPR:mode>di2"
3087 [(set (match_operand:DI 0 "register_operand" "")
3088 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
3089 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3091 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
3092 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
3097 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
3098 [(set (match_operand:GPR 0 "register_operand" "=d")
3099 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
3100 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3101 (clobber (reg:CC CC_REGNUM))]
3102 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3103 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
3104 [(set_attr "op_type" "RRE")
3105 (set_attr "type" "ftoi")])
3108 ; fix_truncdfsi2 instruction pattern(s).
3111 (define_expand "fix_truncdfsi2"
3112 [(set (match_operand:SI 0 "register_operand" "")
3113 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3116 if (TARGET_IBM_FLOAT)
3118 /* This is the algorithm from POP chapter A.5.7.2. */
3120 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3121 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3122 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3124 operands[1] = force_reg (DFmode, operands[1]);
3125 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3126 two31r, two32, temp));
3130 operands[1] = force_reg (DFmode, operands[1]);
3131 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3137 (define_insn "fix_truncdfsi2_ibm"
3138 [(set (match_operand:SI 0 "register_operand" "=d")
3139 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3140 (use (match_operand:DI 2 "immediate_operand" "m"))
3141 (use (match_operand:DI 3 "immediate_operand" "m"))
3142 (use (match_operand:BLK 4 "memory_operand" "m"))
3143 (clobber (reg:CC CC_REGNUM))]
3144 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3146 output_asm_insn ("sd\t%1,%2", operands);
3147 output_asm_insn ("aw\t%1,%3", operands);
3148 output_asm_insn ("std\t%1,%4", operands);
3149 output_asm_insn ("xi\t%N4,128", operands);
3152 [(set_attr "length" "20")])
3155 ; fix_truncsfsi2 instruction pattern(s).
3158 (define_expand "fix_truncsfsi2"
3159 [(set (match_operand:SI 0 "register_operand" "")
3160 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3163 if (TARGET_IBM_FLOAT)
3165 /* Convert to DFmode and then use the POP algorithm. */
3166 rtx temp = gen_reg_rtx (DFmode);
3167 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3168 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3172 operands[1] = force_reg (SFmode, operands[1]);
3173 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3180 ; floatdi(df|sf)2 instruction pattern(s).
3183 (define_insn "floatdi<mode>2"
3184 [(set (match_operand:FPR 0 "register_operand" "=f")
3185 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3186 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3188 [(set_attr "op_type" "RRE")
3189 (set_attr "type" "itof" )])
3192 ; floatsidf2 instruction pattern(s).
3195 (define_expand "floatsidf2"
3196 [(set (match_operand:DF 0 "register_operand" "")
3197 (float:DF (match_operand:SI 1 "register_operand" "")))]
3200 if (TARGET_IBM_FLOAT)
3202 /* This is the algorithm from POP chapter A.5.7.1. */
3204 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3205 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3207 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3212 (define_insn "floatsidf2_ieee"
3213 [(set (match_operand:DF 0 "register_operand" "=f")
3214 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3215 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3217 [(set_attr "op_type" "RRE")
3218 (set_attr "type" "itof" )])
3220 (define_insn "floatsidf2_ibm"
3221 [(set (match_operand:DF 0 "register_operand" "=f")
3222 (float:DF (match_operand:SI 1 "register_operand" "d")))
3223 (use (match_operand:DI 2 "immediate_operand" "m"))
3224 (use (match_operand:BLK 3 "memory_operand" "m"))
3225 (clobber (reg:CC CC_REGNUM))]
3226 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3228 output_asm_insn ("st\t%1,%N3", operands);
3229 output_asm_insn ("xi\t%N3,128", operands);
3230 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3231 output_asm_insn ("ld\t%0,%3", operands);
3234 [(set_attr "length" "20")])
3237 ; floatsisf2 instruction pattern(s).
3240 (define_expand "floatsisf2"
3241 [(set (match_operand:SF 0 "register_operand" "")
3242 (float:SF (match_operand:SI 1 "register_operand" "")))]
3245 if (TARGET_IBM_FLOAT)
3247 /* Use the POP algorithm to convert to DFmode and then truncate. */
3248 rtx temp = gen_reg_rtx (DFmode);
3249 emit_insn (gen_floatsidf2 (temp, operands[1]));
3250 emit_insn (gen_truncdfsf2 (operands[0], temp));
3255 (define_insn "floatsisf2_ieee"
3256 [(set (match_operand:SF 0 "register_operand" "=f")
3257 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3258 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3260 [(set_attr "op_type" "RRE")
3261 (set_attr "type" "itof" )])
3264 ; truncdfsf2 instruction pattern(s).
3267 (define_expand "truncdfsf2"
3268 [(set (match_operand:SF 0 "register_operand" "")
3269 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3273 (define_insn "truncdfsf2_ieee"
3274 [(set (match_operand:SF 0 "register_operand" "=f")
3275 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3276 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3278 [(set_attr "op_type" "RRE")])
3280 (define_insn "truncdfsf2_ibm"
3281 [(set (match_operand:SF 0 "register_operand" "=f,f")
3282 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3283 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3287 [(set_attr "op_type" "RR,RX")
3288 (set_attr "type" "floadsf")])
3291 ; extendsfdf2 instruction pattern(s).
3294 (define_expand "extendsfdf2"
3295 [(set (match_operand:DF 0 "register_operand" "")
3296 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3299 if (TARGET_IBM_FLOAT)
3301 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3306 (define_insn "extendsfdf2_ieee"
3307 [(set (match_operand:DF 0 "register_operand" "=f,f")
3308 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3309 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3313 [(set_attr "op_type" "RRE,RXE")
3314 (set_attr "type" "floadsf")])
3316 (define_insn "extendsfdf2_ibm"
3317 [(set (match_operand:DF 0 "register_operand" "=f,f")
3318 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3319 (clobber (reg:CC CC_REGNUM))]
3320 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3322 sdr\t%0,%0\;ler\t%0,%1
3323 sdr\t%0,%0\;le\t%0,%1"
3324 [(set_attr "length" "4,6")
3325 (set_attr "type" "floadsf")])
3329 ;; ARITHMETIC OPERATIONS
3331 ; arithmetic operations set the ConditionCode,
3332 ; because of unpredictable Bits in Register for Halfword and Byte
3333 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3336 ;;- Add instructions.
3340 ; addti3 instruction pattern(s).
3343 (define_insn_and_split "addti3"
3344 [(set (match_operand:TI 0 "register_operand" "=&d")
3345 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3346 (match_operand:TI 2 "general_operand" "do") ) )
3347 (clobber (reg:CC CC_REGNUM))]
3350 "&& reload_completed"
3352 [(set (reg:CCL1 CC_REGNUM)
3353 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3355 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3357 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3358 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3359 (clobber (reg:CC CC_REGNUM))])]
3360 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3361 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3362 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3363 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3364 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3365 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3368 ; adddi3 instruction pattern(s).
3371 (define_insn "*adddi3_sign"
3372 [(set (match_operand:DI 0 "register_operand" "=d,d")
3373 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3374 (match_operand:DI 1 "register_operand" "0,0")))
3375 (clobber (reg:CC CC_REGNUM))]
3380 [(set_attr "op_type" "RRE,RXY")])
3382 (define_insn "*adddi3_zero_cc"
3383 [(set (reg CC_REGNUM)
3384 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3385 (match_operand:DI 1 "register_operand" "0,0"))
3387 (set (match_operand:DI 0 "register_operand" "=d,d")
3388 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3389 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3393 [(set_attr "op_type" "RRE,RXY")])
3395 (define_insn "*adddi3_zero_cconly"
3396 [(set (reg CC_REGNUM)
3397 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3398 (match_operand:DI 1 "register_operand" "0,0"))
3400 (clobber (match_scratch:DI 0 "=d,d"))]
3401 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3405 [(set_attr "op_type" "RRE,RXY")])
3407 (define_insn "*adddi3_zero"
3408 [(set (match_operand:DI 0 "register_operand" "=d,d")
3409 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3410 (match_operand:DI 1 "register_operand" "0,0")))
3411 (clobber (reg:CC CC_REGNUM))]
3416 [(set_attr "op_type" "RRE,RXY")])
3418 (define_insn "*adddi3_imm_cc"
3419 [(set (reg CC_REGNUM)
3420 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
3421 (match_operand:DI 2 "const_int_operand" "K,Os"))
3423 (set (match_operand:DI 0 "register_operand" "=d,d")
3424 (plus:DI (match_dup 1) (match_dup 2)))]
3426 && s390_match_ccmode (insn, CCAmode)
3427 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3428 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
3432 [(set_attr "op_type" "RI,RIL")])
3434 (define_insn "*adddi3_carry1_cc"
3435 [(set (reg CC_REGNUM)
3436 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3437 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3439 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3440 (plus:DI (match_dup 1) (match_dup 2)))]
3441 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3447 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3449 (define_insn "*adddi3_carry1_cconly"
3450 [(set (reg CC_REGNUM)
3451 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3452 (match_operand:DI 2 "general_operand" "d,m"))
3454 (clobber (match_scratch:DI 0 "=d,d"))]
3455 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3459 [(set_attr "op_type" "RRE,RXY")])
3461 (define_insn "*adddi3_carry2_cc"
3462 [(set (reg CC_REGNUM)
3463 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3464 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3466 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3467 (plus:DI (match_dup 1) (match_dup 2)))]
3468 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3474 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3476 (define_insn "*adddi3_carry2_cconly"
3477 [(set (reg CC_REGNUM)
3478 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3479 (match_operand:DI 2 "general_operand" "d,m"))
3481 (clobber (match_scratch:DI 0 "=d,d"))]
3482 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3486 [(set_attr "op_type" "RRE,RXY")])
3488 (define_insn "*adddi3_cc"
3489 [(set (reg CC_REGNUM)
3490 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3491 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3493 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3494 (plus:DI (match_dup 1) (match_dup 2)))]
3495 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3501 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3503 (define_insn "*adddi3_cconly"
3504 [(set (reg CC_REGNUM)
3505 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3506 (match_operand:DI 2 "general_operand" "d,m"))
3508 (clobber (match_scratch:DI 0 "=d,d"))]
3509 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3513 [(set_attr "op_type" "RRE,RXY")])
3515 (define_insn "*adddi3_cconly2"
3516 [(set (reg CC_REGNUM)
3517 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3518 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3519 (clobber (match_scratch:DI 0 "=d,d"))]
3520 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3524 [(set_attr "op_type" "RRE,RXY")])
3526 (define_insn "*adddi3_64"
3527 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
3528 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
3529 (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
3530 (clobber (reg:CC CC_REGNUM))]
3538 [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
3540 (define_insn_and_split "*adddi3_31z"
3541 [(set (match_operand:DI 0 "register_operand" "=&d")
3542 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3543 (match_operand:DI 2 "general_operand" "do") ) )
3544 (clobber (reg:CC CC_REGNUM))]
3545 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3547 "&& reload_completed"
3549 [(set (reg:CCL1 CC_REGNUM)
3550 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3552 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3554 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3555 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3556 (clobber (reg:CC CC_REGNUM))])]
3557 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3558 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3559 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3560 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3561 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3562 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3564 (define_insn_and_split "*adddi3_31"
3565 [(set (match_operand:DI 0 "register_operand" "=&d")
3566 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3567 (match_operand:DI 2 "general_operand" "do") ) )
3568 (clobber (reg:CC CC_REGNUM))]
3571 "&& reload_completed"
3573 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3574 (clobber (reg:CC CC_REGNUM))])
3576 [(set (reg:CCL1 CC_REGNUM)
3577 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3579 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3581 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3583 (label_ref (match_dup 9))))
3585 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3586 (clobber (reg:CC CC_REGNUM))])
3588 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3589 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3590 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3591 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3592 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3593 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3594 operands[9] = gen_label_rtx ();")
3596 (define_expand "adddi3"
3598 [(set (match_operand:DI 0 "register_operand" "")
3599 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3600 (match_operand:DI 2 "general_operand" "")))
3601 (clobber (reg:CC CC_REGNUM))])]
3606 ; addsi3 instruction pattern(s).
3609 (define_insn "*addsi3_imm_cc"
3610 [(set (reg CC_REGNUM)
3611 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3612 (match_operand:SI 2 "const_int_operand" "K,Os"))
3614 (set (match_operand:SI 0 "register_operand" "=d,d")
3615 (plus:SI (match_dup 1) (match_dup 2)))]
3616 "s390_match_ccmode (insn, CCAmode)
3617 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3618 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3619 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
3623 [(set_attr "op_type" "RI,RIL")])
3625 (define_insn "*addsi3_carry1_cc"
3626 [(set (reg CC_REGNUM)
3627 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3628 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3630 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3631 (plus:SI (match_dup 1) (match_dup 2)))]
3632 "s390_match_ccmode (insn, CCL1mode)"
3638 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3640 (define_insn "*addsi3_carry1_cconly"
3641 [(set (reg CC_REGNUM)
3642 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3643 (match_operand:SI 2 "general_operand" "d,R,T"))
3645 (clobber (match_scratch:SI 0 "=d,d,d"))]
3646 "s390_match_ccmode (insn, CCL1mode)"
3651 [(set_attr "op_type" "RR,RX,RXY")])
3653 (define_insn "*addsi3_carry2_cc"
3654 [(set (reg CC_REGNUM)
3655 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3656 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3658 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3659 (plus:SI (match_dup 1) (match_dup 2)))]
3660 "s390_match_ccmode (insn, CCL1mode)"
3666 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3668 (define_insn "*addsi3_carry2_cconly"
3669 [(set (reg CC_REGNUM)
3670 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3671 (match_operand:SI 2 "general_operand" "d,R,T"))
3673 (clobber (match_scratch:SI 0 "=d,d,d"))]
3674 "s390_match_ccmode (insn, CCL1mode)"
3679 [(set_attr "op_type" "RR,RX,RXY")])
3681 (define_insn "*addsi3_cc"
3682 [(set (reg CC_REGNUM)
3683 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3684 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3686 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3687 (plus:SI (match_dup 1) (match_dup 2)))]
3688 "s390_match_ccmode (insn, CCLmode)"
3694 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3696 (define_insn "*addsi3_cconly"
3697 [(set (reg CC_REGNUM)
3698 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3699 (match_operand:SI 2 "general_operand" "d,R,T"))
3701 (clobber (match_scratch:SI 0 "=d,d,d"))]
3702 "s390_match_ccmode (insn, CCLmode)"
3707 [(set_attr "op_type" "RR,RX,RXY")])
3709 (define_insn "*addsi3_cconly2"
3710 [(set (reg CC_REGNUM)
3711 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3712 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3713 (clobber (match_scratch:SI 0 "=d,d,d"))]
3714 "s390_match_ccmode (insn, CCLmode)"
3719 [(set_attr "op_type" "RR,RX,RXY")])
3721 (define_insn "*addsi3_sign"
3722 [(set (match_operand:SI 0 "register_operand" "=d,d")
3723 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3724 (match_operand:SI 1 "register_operand" "0,0")))
3725 (clobber (reg:CC CC_REGNUM))]
3730 [(set_attr "op_type" "RX,RXY")])
3732 (define_insn "addsi3"
3733 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
3734 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
3735 (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
3736 (clobber (reg:CC CC_REGNUM))]
3744 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
3747 ; add(df|sf)3 instruction pattern(s).
3750 (define_expand "add<mode>3"
3752 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3753 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3754 (match_operand:FPR 2 "general_operand" "f,R")))
3755 (clobber (reg:CC CC_REGNUM))])]
3759 (define_insn "*add<mode>3"
3760 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3761 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3762 (match_operand:FPR 2 "general_operand" "f,R")))
3763 (clobber (reg:CC CC_REGNUM))]
3764 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3768 [(set_attr "op_type" "RRE,RXE")
3769 (set_attr "type" "fsimp<mode>")])
3771 (define_insn "*add<mode>3_cc"
3772 [(set (reg CC_REGNUM)
3773 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3774 (match_operand:FPR 2 "general_operand" "f,R"))
3775 (match_operand:FPR 3 "const0_operand" "")))
3776 (set (match_operand:FPR 0 "register_operand" "=f,f")
3777 (plus:FPR (match_dup 1) (match_dup 2)))]
3778 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3782 [(set_attr "op_type" "RRE,RXE")
3783 (set_attr "type" "fsimp<mode>")])
3785 (define_insn "*add<mode>3_cconly"
3786 [(set (reg CC_REGNUM)
3787 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3788 (match_operand:FPR 2 "general_operand" "f,R"))
3789 (match_operand:FPR 3 "const0_operand" "")))
3790 (clobber (match_scratch:FPR 0 "=f,f"))]
3791 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3795 [(set_attr "op_type" "RRE,RXE")
3796 (set_attr "type" "fsimp<mode>")])
3798 (define_insn "*add<mode>3_ibm"
3799 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3800 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3801 (match_operand:FPR 2 "general_operand" "f,R")))
3802 (clobber (reg:CC CC_REGNUM))]
3803 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3807 [(set_attr "op_type" "RR,RX")
3808 (set_attr "type" "fsimp<mode>")])
3812 ;;- Subtract instructions.
3816 ; subti3 instruction pattern(s).
3819 (define_insn_and_split "subti3"
3820 [(set (match_operand:TI 0 "register_operand" "=&d")
3821 (minus:TI (match_operand:TI 1 "register_operand" "0")
3822 (match_operand:TI 2 "general_operand" "do") ) )
3823 (clobber (reg:CC CC_REGNUM))]
3826 "&& reload_completed"
3828 [(set (reg:CCL2 CC_REGNUM)
3829 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3831 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3833 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3834 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3835 (clobber (reg:CC CC_REGNUM))])]
3836 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3837 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3838 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3839 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3840 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3841 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3844 ; subdi3 instruction pattern(s).
3847 (define_insn "*subdi3_sign"
3848 [(set (match_operand:DI 0 "register_operand" "=d,d")
3849 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3850 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3851 (clobber (reg:CC CC_REGNUM))]
3856 [(set_attr "op_type" "RRE,RXY")])
3858 (define_insn "*subdi3_zero_cc"
3859 [(set (reg CC_REGNUM)
3860 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3861 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3863 (set (match_operand:DI 0 "register_operand" "=d,d")
3864 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3865 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3869 [(set_attr "op_type" "RRE,RXY")])
3871 (define_insn "*subdi3_zero_cconly"
3872 [(set (reg CC_REGNUM)
3873 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3874 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3876 (clobber (match_scratch:DI 0 "=d,d"))]
3877 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3881 [(set_attr "op_type" "RRE,RXY")])
3883 (define_insn "*subdi3_zero"
3884 [(set (match_operand:DI 0 "register_operand" "=d,d")
3885 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3886 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3887 (clobber (reg:CC CC_REGNUM))]
3892 [(set_attr "op_type" "RRE,RXY")])
3894 (define_insn "*subdi3_borrow_cc"
3895 [(set (reg CC_REGNUM)
3896 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3897 (match_operand:DI 2 "general_operand" "d,m"))
3899 (set (match_operand:DI 0 "register_operand" "=d,d")
3900 (minus:DI (match_dup 1) (match_dup 2)))]
3901 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3905 [(set_attr "op_type" "RRE,RXY")])
3907 (define_insn "*subdi3_borrow_cconly"
3908 [(set (reg CC_REGNUM)
3909 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3910 (match_operand:DI 2 "general_operand" "d,m"))
3912 (clobber (match_scratch:DI 0 "=d,d"))]
3913 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3917 [(set_attr "op_type" "RRE,RXY")])
3919 (define_insn "*subdi3_cc"
3920 [(set (reg CC_REGNUM)
3921 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3922 (match_operand:DI 2 "general_operand" "d,m"))
3924 (set (match_operand:DI 0 "register_operand" "=d,d")
3925 (minus:DI (match_dup 1) (match_dup 2)))]
3926 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3930 [(set_attr "op_type" "RRE,RXY")])
3932 (define_insn "*subdi3_cc2"
3933 [(set (reg CC_REGNUM)
3934 (compare (match_operand:DI 1 "register_operand" "0,0")
3935 (match_operand:DI 2 "general_operand" "d,m")))
3936 (set (match_operand:DI 0 "register_operand" "=d,d")
3937 (minus:DI (match_dup 1) (match_dup 2)))]
3938 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3942 [(set_attr "op_type" "RRE,RXY")])
3944 (define_insn "*subdi3_cconly"
3945 [(set (reg CC_REGNUM)
3946 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3947 (match_operand:DI 2 "general_operand" "d,m"))
3949 (clobber (match_scratch:DI 0 "=d,d"))]
3950 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3954 [(set_attr "op_type" "RRE,RXY")])
3956 (define_insn "*subdi3_cconly2"
3957 [(set (reg CC_REGNUM)
3958 (compare (match_operand:DI 1 "register_operand" "0,0")
3959 (match_operand:DI 2 "general_operand" "d,m")))
3960 (clobber (match_scratch:DI 0 "=d,d"))]
3961 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3965 [(set_attr "op_type" "RRE,RXY")])
3967 (define_insn "*subdi3_64"
3968 [(set (match_operand:DI 0 "register_operand" "=d,d")
3969 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3970 (match_operand:DI 2 "general_operand" "d,m") ) )
3971 (clobber (reg:CC CC_REGNUM))]
3976 [(set_attr "op_type" "RRE,RRE")])
3978 (define_insn_and_split "*subdi3_31z"
3979 [(set (match_operand:DI 0 "register_operand" "=&d")
3980 (minus:DI (match_operand:DI 1 "register_operand" "0")
3981 (match_operand:DI 2 "general_operand" "do") ) )
3982 (clobber (reg:CC CC_REGNUM))]
3983 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3985 "&& reload_completed"
3987 [(set (reg:CCL2 CC_REGNUM)
3988 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3990 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3992 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3993 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3994 (clobber (reg:CC CC_REGNUM))])]
3995 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3996 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3997 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3998 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3999 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4000 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4002 (define_insn_and_split "*subdi3_31"
4003 [(set (match_operand:DI 0 "register_operand" "=&d")
4004 (minus:DI (match_operand:DI 1 "register_operand" "0")
4005 (match_operand:DI 2 "general_operand" "do") ) )
4006 (clobber (reg:CC CC_REGNUM))]
4009 "&& reload_completed"
4011 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4012 (clobber (reg:CC CC_REGNUM))])
4014 [(set (reg:CCL2 CC_REGNUM)
4015 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4017 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4019 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4021 (label_ref (match_dup 9))))
4023 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4024 (clobber (reg:CC CC_REGNUM))])
4026 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4027 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4028 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4029 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4030 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4031 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4032 operands[9] = gen_label_rtx ();")
4034 (define_expand "subdi3"
4036 [(set (match_operand:DI 0 "register_operand" "")
4037 (minus:DI (match_operand:DI 1 "register_operand" "")
4038 (match_operand:DI 2 "general_operand" "")))
4039 (clobber (reg:CC CC_REGNUM))])]
4044 ; subsi3 instruction pattern(s).
4047 (define_insn "*subsi3_borrow_cc"
4048 [(set (reg CC_REGNUM)
4049 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4050 (match_operand:SI 2 "general_operand" "d,R,T"))
4052 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4053 (minus:SI (match_dup 1) (match_dup 2)))]
4054 "s390_match_ccmode (insn, CCL2mode)"
4059 [(set_attr "op_type" "RR,RX,RXY")])
4061 (define_insn "*subsi3_borrow_cconly"
4062 [(set (reg CC_REGNUM)
4063 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4064 (match_operand:SI 2 "general_operand" "d,R,T"))
4066 (clobber (match_scratch:SI 0 "=d,d,d"))]
4067 "s390_match_ccmode (insn, CCL2mode)"
4072 [(set_attr "op_type" "RR,RX,RXY")])
4074 (define_insn "*subsi3_cc"
4075 [(set (reg CC_REGNUM)
4076 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4077 (match_operand:SI 2 "general_operand" "d,R,T"))
4079 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4080 (minus:SI (match_dup 1) (match_dup 2)))]
4081 "s390_match_ccmode (insn, CCLmode)"
4086 [(set_attr "op_type" "RR,RX,RXY")])
4088 (define_insn "*subsi3_cc2"
4089 [(set (reg CC_REGNUM)
4090 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4091 (match_operand:SI 2 "general_operand" "d,R,T")))
4092 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4093 (minus:SI (match_dup 1) (match_dup 2)))]
4094 "s390_match_ccmode (insn, CCL3mode)"
4099 [(set_attr "op_type" "RR,RX,RXY")])
4101 (define_insn "*subsi3_cconly"
4102 [(set (reg CC_REGNUM)
4103 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4104 (match_operand:SI 2 "general_operand" "d,R,T"))
4106 (clobber (match_scratch:SI 0 "=d,d,d"))]
4107 "s390_match_ccmode (insn, CCLmode)"
4112 [(set_attr "op_type" "RR,RX,RXY")])
4114 (define_insn "*subsi3_cconly2"
4115 [(set (reg CC_REGNUM)
4116 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4117 (match_operand:SI 2 "general_operand" "d,R,T")))
4118 (clobber (match_scratch:SI 0 "=d,d,d"))]
4119 "s390_match_ccmode (insn, CCL3mode)"
4124 [(set_attr "op_type" "RR,RX,RXY")])
4126 (define_insn "*subsi3_sign"
4127 [(set (match_operand:SI 0 "register_operand" "=d,d")
4128 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4129 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4130 (clobber (reg:CC CC_REGNUM))]
4135 [(set_attr "op_type" "RX,RXY")])
4137 (define_insn "subsi3"
4138 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4139 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4140 (match_operand:SI 2 "general_operand" "d,R,T")))
4141 (clobber (reg:CC CC_REGNUM))]
4147 [(set_attr "op_type" "RR,RX,RXY")])
4151 ; sub(df|sf)3 instruction pattern(s).
4154 (define_expand "sub<mode>3"
4156 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4157 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4158 (match_operand:FPR 2 "general_operand" "f,R")))
4159 (clobber (reg:CC CC_REGNUM))])]
4163 (define_insn "*sub<mode>3"
4164 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4165 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4166 (match_operand:FPR 2 "general_operand" "f,R")))
4167 (clobber (reg:CC CC_REGNUM))]
4168 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4172 [(set_attr "op_type" "RRE,RXE")
4173 (set_attr "type" "fsimp<mode>")])
4175 (define_insn "*sub<mode>3_cc"
4176 [(set (reg CC_REGNUM)
4177 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4178 (match_operand:FPR 2 "general_operand" "f,R"))
4179 (match_operand:FPR 3 "const0_operand" "")))
4180 (set (match_operand:FPR 0 "register_operand" "=f,f")
4181 (minus:FPR (match_dup 1) (match_dup 2)))]
4182 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4186 [(set_attr "op_type" "RRE,RXE")
4187 (set_attr "type" "fsimp<mode>")])
4189 (define_insn "*sub<mode>3_cconly"
4190 [(set (reg CC_REGNUM)
4191 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4192 (match_operand:FPR 2 "general_operand" "f,R"))
4193 (match_operand:FPR 3 "const0_operand" "")))
4194 (clobber (match_scratch:FPR 0 "=f,f"))]
4195 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4199 [(set_attr "op_type" "RRE,RXE")
4200 (set_attr "type" "fsimp<mode>")])
4202 (define_insn "*sub<mode>3_ibm"
4203 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4204 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4205 (match_operand:FPR 2 "general_operand" "f,R")))
4206 (clobber (reg:CC CC_REGNUM))]
4207 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4211 [(set_attr "op_type" "RR,RX")
4212 (set_attr "type" "fsimp<mode>")])
4216 ;;- Conditional add/subtract instructions.
4220 ; add(di|si)cc instruction pattern(s).
4223 (define_insn "*add<mode>3_alc_cc"
4224 [(set (reg CC_REGNUM)
4226 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4227 (match_operand:GPR 2 "general_operand" "d,m"))
4228 (match_operand:GPR 3 "s390_alc_comparison" ""))
4230 (set (match_operand:GPR 0 "register_operand" "=d,d")
4231 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4232 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4236 [(set_attr "op_type" "RRE,RXY")])
4238 (define_insn "*add<mode>3_alc"
4239 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4240 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4241 (match_operand:GPR 2 "general_operand" "d,m"))
4242 (match_operand:GPR 3 "s390_alc_comparison" "")))
4243 (clobber (reg:CC CC_REGNUM))]
4248 [(set_attr "op_type" "RRE,RXY")])
4250 (define_insn "*sub<mode>3_slb_cc"
4251 [(set (reg CC_REGNUM)
4253 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4254 (match_operand:GPR 2 "general_operand" "d,m"))
4255 (match_operand:GPR 3 "s390_slb_comparison" ""))
4257 (set (match_operand:GPR 0 "register_operand" "=d,d")
4258 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4259 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4263 [(set_attr "op_type" "RRE,RXY")])
4265 (define_insn "*sub<mode>3_slb"
4266 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4267 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4268 (match_operand:GPR 2 "general_operand" "d,m"))
4269 (match_operand:GPR 3 "s390_slb_comparison" "")))
4270 (clobber (reg:CC CC_REGNUM))]
4275 [(set_attr "op_type" "RRE,RXY")])
4277 (define_expand "add<mode>cc"
4278 [(match_operand:GPR 0 "register_operand" "")
4279 (match_operand 1 "comparison_operator" "")
4280 (match_operand:GPR 2 "register_operand" "")
4281 (match_operand:GPR 3 "const_int_operand" "")]
4283 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4284 s390_compare_op0, s390_compare_op1,
4285 operands[0], operands[2],
4286 operands[3])) FAIL; DONE;")
4289 ; scond instruction pattern(s).
4292 (define_insn_and_split "*scond<mode>"
4293 [(set (match_operand:GPR 0 "register_operand" "=&d")
4294 (match_operand:GPR 1 "s390_alc_comparison" ""))
4295 (clobber (reg:CC CC_REGNUM))]
4298 "&& reload_completed"
4299 [(set (match_dup 0) (const_int 0))
4301 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4303 (clobber (reg:CC CC_REGNUM))])]
4306 (define_insn_and_split "*scond<mode>_neg"
4307 [(set (match_operand:GPR 0 "register_operand" "=&d")
4308 (match_operand:GPR 1 "s390_slb_comparison" ""))
4309 (clobber (reg:CC CC_REGNUM))]
4312 "&& reload_completed"
4313 [(set (match_dup 0) (const_int 0))
4315 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4317 (clobber (reg:CC CC_REGNUM))])
4319 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4320 (clobber (reg:CC CC_REGNUM))])]
4324 (define_expand "s<code>"
4325 [(set (match_operand:SI 0 "register_operand" "")
4326 (SCOND (match_dup 0)
4329 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4330 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4332 (define_expand "seq"
4334 [(set (match_operand:SI 0 "register_operand" "=d")
4336 (clobber (reg:CC CC_REGNUM))])
4338 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4339 (clobber (reg:CC CC_REGNUM))])]
4342 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4344 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4345 PUT_MODE (operands[1], SImode);
4348 (define_insn_and_split "*sne"
4349 [(set (match_operand:SI 0 "register_operand" "=d")
4350 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4352 (clobber (reg:CC CC_REGNUM))]
4357 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4358 (clobber (reg:CC CC_REGNUM))])])
4362 ;;- Multiply instructions.
4366 ; muldi3 instruction pattern(s).
4369 (define_insn "*muldi3_sign"
4370 [(set (match_operand:DI 0 "register_operand" "=d,d")
4371 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4372 (match_operand:DI 1 "register_operand" "0,0")))]
4377 [(set_attr "op_type" "RRE,RXY")
4378 (set_attr "type" "imuldi")])
4380 (define_insn "muldi3"
4381 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4382 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4383 (match_operand:DI 2 "general_operand" "d,K,m")))]
4389 [(set_attr "op_type" "RRE,RI,RXY")
4390 (set_attr "type" "imuldi")])
4393 ; mulsi3 instruction pattern(s).
4396 (define_insn "*mulsi3_sign"
4397 [(set (match_operand:SI 0 "register_operand" "=d")
4398 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4399 (match_operand:SI 1 "register_operand" "0")))]
4402 [(set_attr "op_type" "RX")
4403 (set_attr "type" "imulhi")])
4405 (define_insn "mulsi3"
4406 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4407 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4408 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4415 [(set_attr "op_type" "RRE,RI,RX,RXY")
4416 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4419 ; mulsidi3 instruction pattern(s).
4422 (define_insn "mulsidi3"
4423 [(set (match_operand:DI 0 "register_operand" "=d,d")
4424 (mult:DI (sign_extend:DI
4425 (match_operand:SI 1 "register_operand" "%0,0"))
4427 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4432 [(set_attr "op_type" "RR,RX")
4433 (set_attr "type" "imulsi")])
4436 ; umulsidi3 instruction pattern(s).
4439 (define_insn "umulsidi3"
4440 [(set (match_operand:DI 0 "register_operand" "=d,d")
4441 (mult:DI (zero_extend:DI
4442 (match_operand:SI 1 "register_operand" "%0,0"))
4444 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4445 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4449 [(set_attr "op_type" "RRE,RXY")
4450 (set_attr "type" "imulsi")])
4453 ; mul(df|sf)3 instruction pattern(s).
4456 (define_expand "mul<mode>3"
4457 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4458 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4459 (match_operand:FPR 2 "general_operand" "f,R")))]
4463 (define_insn "*mul<mode>3"
4464 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4465 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4466 (match_operand:FPR 2 "general_operand" "f,R")))]
4467 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4471 [(set_attr "op_type" "RRE,RXE")
4472 (set_attr "type" "fmul<mode>")])
4474 (define_insn "*mul<mode>3_ibm"
4475 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4476 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4477 (match_operand:FPR 2 "general_operand" "f,R")))]
4478 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4482 [(set_attr "op_type" "RR,RX")
4483 (set_attr "type" "fmul<mode>")])
4485 (define_insn "*fmadd<mode>"
4486 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4487 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4488 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4489 (match_operand:FPR 3 "register_operand" "0,0")))]
4490 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4494 [(set_attr "op_type" "RRE,RXE")
4495 (set_attr "type" "fmul<mode>")])
4497 (define_insn "*fmsub<mode>"
4498 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4499 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4500 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4501 (match_operand:FPR 3 "register_operand" "0,0")))]
4502 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4506 [(set_attr "op_type" "RRE,RXE")
4507 (set_attr "type" "fmul<mode>")])
4510 ;;- Divide and modulo instructions.
4514 ; divmoddi4 instruction pattern(s).
4517 (define_expand "divmoddi4"
4518 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4519 (div:DI (match_operand:DI 1 "register_operand" "")
4520 (match_operand:DI 2 "general_operand" "")))
4521 (set (match_operand:DI 3 "general_operand" "")
4522 (mod:DI (match_dup 1) (match_dup 2)))])
4523 (clobber (match_dup 4))]
4526 rtx insn, div_equal, mod_equal;
4528 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4529 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4531 operands[4] = gen_reg_rtx(TImode);
4532 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4534 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4536 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4538 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4540 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4545 (define_insn "divmodtidi3"
4546 [(set (match_operand:TI 0 "register_operand" "=d,d")
4550 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4551 (match_operand:DI 2 "general_operand" "d,m")))
4553 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4558 [(set_attr "op_type" "RRE,RXY")
4559 (set_attr "type" "idiv")])
4561 (define_insn "divmodtisi3"
4562 [(set (match_operand:TI 0 "register_operand" "=d,d")
4566 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4568 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4571 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4576 [(set_attr "op_type" "RRE,RXY")
4577 (set_attr "type" "idiv")])
4580 ; udivmoddi4 instruction pattern(s).
4583 (define_expand "udivmoddi4"
4584 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4585 (udiv:DI (match_operand:DI 1 "general_operand" "")
4586 (match_operand:DI 2 "nonimmediate_operand" "")))
4587 (set (match_operand:DI 3 "general_operand" "")
4588 (umod:DI (match_dup 1) (match_dup 2)))])
4589 (clobber (match_dup 4))]
4592 rtx insn, div_equal, mod_equal, equal;
4594 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4595 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4596 equal = gen_rtx_IOR (TImode,
4597 gen_rtx_ASHIFT (TImode,
4598 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4600 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4602 operands[4] = gen_reg_rtx(TImode);
4603 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4604 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4605 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4606 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4608 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4610 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4612 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4614 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4616 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4621 (define_insn "udivmodtidi3"
4622 [(set (match_operand:TI 0 "register_operand" "=d,d")
4627 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4629 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4633 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4638 [(set_attr "op_type" "RRE,RXY")
4639 (set_attr "type" "idiv")])
4642 ; divmodsi4 instruction pattern(s).
4645 (define_expand "divmodsi4"
4646 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4647 (div:SI (match_operand:SI 1 "general_operand" "")
4648 (match_operand:SI 2 "nonimmediate_operand" "")))
4649 (set (match_operand:SI 3 "general_operand" "")
4650 (mod:SI (match_dup 1) (match_dup 2)))])
4651 (clobber (match_dup 4))]
4654 rtx insn, div_equal, mod_equal, equal;
4656 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4657 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4658 equal = gen_rtx_IOR (DImode,
4659 gen_rtx_ASHIFT (DImode,
4660 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4662 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4664 operands[4] = gen_reg_rtx(DImode);
4665 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4666 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4668 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4670 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4672 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4674 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4676 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4681 (define_insn "divmoddisi3"
4682 [(set (match_operand:DI 0 "register_operand" "=d,d")
4687 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4689 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4693 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4698 [(set_attr "op_type" "RR,RX")
4699 (set_attr "type" "idiv")])
4702 ; udivsi3 and umodsi3 instruction pattern(s).
4705 (define_expand "udivmodsi4"
4706 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4707 (udiv:SI (match_operand:SI 1 "general_operand" "")
4708 (match_operand:SI 2 "nonimmediate_operand" "")))
4709 (set (match_operand:SI 3 "general_operand" "")
4710 (umod:SI (match_dup 1) (match_dup 2)))])
4711 (clobber (match_dup 4))]
4712 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4714 rtx insn, div_equal, mod_equal, equal;
4716 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4717 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4718 equal = gen_rtx_IOR (DImode,
4719 gen_rtx_ASHIFT (DImode,
4720 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4722 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4724 operands[4] = gen_reg_rtx(DImode);
4725 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4726 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4727 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4728 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4730 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4732 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4734 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4736 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4738 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4743 (define_insn "udivmoddisi3"
4744 [(set (match_operand:DI 0 "register_operand" "=d,d")
4749 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4751 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4755 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4756 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4760 [(set_attr "op_type" "RRE,RXY")
4761 (set_attr "type" "idiv")])
4763 (define_expand "udivsi3"
4764 [(set (match_operand:SI 0 "register_operand" "=d")
4765 (udiv:SI (match_operand:SI 1 "general_operand" "")
4766 (match_operand:SI 2 "general_operand" "")))
4767 (clobber (match_dup 3))]
4768 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4770 rtx insn, udiv_equal, umod_equal, equal;
4772 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4773 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4774 equal = gen_rtx_IOR (DImode,
4775 gen_rtx_ASHIFT (DImode,
4776 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4778 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4780 operands[3] = gen_reg_rtx (DImode);
4782 if (CONSTANT_P (operands[2]))
4784 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4786 rtx label1 = gen_label_rtx ();
4788 operands[1] = make_safe_from (operands[1], operands[0]);
4789 emit_move_insn (operands[0], const0_rtx);
4790 emit_insn (gen_cmpsi (operands[1], operands[2]));
4791 emit_jump_insn (gen_bltu (label1));
4792 emit_move_insn (operands[0], const1_rtx);
4793 emit_label (label1);
4797 operands[2] = force_reg (SImode, operands[2]);
4798 operands[2] = make_safe_from (operands[2], operands[0]);
4800 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4801 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4804 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4806 insn = emit_move_insn (operands[0],
4807 gen_lowpart (SImode, operands[3]));
4809 gen_rtx_EXPR_LIST (REG_EQUAL,
4810 udiv_equal, REG_NOTES (insn));
4815 rtx label1 = gen_label_rtx ();
4816 rtx label2 = gen_label_rtx ();
4817 rtx label3 = gen_label_rtx ();
4819 operands[1] = force_reg (SImode, operands[1]);
4820 operands[1] = make_safe_from (operands[1], operands[0]);
4821 operands[2] = force_reg (SImode, operands[2]);
4822 operands[2] = make_safe_from (operands[2], operands[0]);
4824 emit_move_insn (operands[0], const0_rtx);
4825 emit_insn (gen_cmpsi (operands[2], operands[1]));
4826 emit_jump_insn (gen_bgtu (label3));
4827 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4828 emit_jump_insn (gen_blt (label2));
4829 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4830 emit_jump_insn (gen_beq (label1));
4831 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4832 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4835 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4837 insn = emit_move_insn (operands[0],
4838 gen_lowpart (SImode, operands[3]));
4840 gen_rtx_EXPR_LIST (REG_EQUAL,
4841 udiv_equal, REG_NOTES (insn));
4843 emit_label (label1);
4844 emit_move_insn (operands[0], operands[1]);
4846 emit_label (label2);
4847 emit_move_insn (operands[0], const1_rtx);
4848 emit_label (label3);
4850 emit_move_insn (operands[0], operands[0]);
4854 (define_expand "umodsi3"
4855 [(set (match_operand:SI 0 "register_operand" "=d")
4856 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4857 (match_operand:SI 2 "nonimmediate_operand" "")))
4858 (clobber (match_dup 3))]
4859 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4861 rtx insn, udiv_equal, umod_equal, equal;
4863 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4864 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4865 equal = gen_rtx_IOR (DImode,
4866 gen_rtx_ASHIFT (DImode,
4867 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4869 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4871 operands[3] = gen_reg_rtx (DImode);
4873 if (CONSTANT_P (operands[2]))
4875 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4877 rtx label1 = gen_label_rtx ();
4879 operands[1] = make_safe_from (operands[1], operands[0]);
4880 emit_move_insn (operands[0], operands[1]);
4881 emit_insn (gen_cmpsi (operands[0], operands[2]));
4882 emit_jump_insn (gen_bltu (label1));
4883 emit_insn (gen_abssi2 (operands[0], operands[2]));
4884 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4885 emit_label (label1);
4889 operands[2] = force_reg (SImode, operands[2]);
4890 operands[2] = make_safe_from (operands[2], operands[0]);
4892 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4893 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4896 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4898 insn = emit_move_insn (operands[0],
4899 gen_highpart (SImode, operands[3]));
4901 gen_rtx_EXPR_LIST (REG_EQUAL,
4902 umod_equal, REG_NOTES (insn));
4907 rtx label1 = gen_label_rtx ();
4908 rtx label2 = gen_label_rtx ();
4909 rtx label3 = gen_label_rtx ();
4911 operands[1] = force_reg (SImode, operands[1]);
4912 operands[1] = make_safe_from (operands[1], operands[0]);
4913 operands[2] = force_reg (SImode, operands[2]);
4914 operands[2] = make_safe_from (operands[2], operands[0]);
4916 emit_move_insn(operands[0], operands[1]);
4917 emit_insn (gen_cmpsi (operands[2], operands[1]));
4918 emit_jump_insn (gen_bgtu (label3));
4919 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4920 emit_jump_insn (gen_blt (label2));
4921 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4922 emit_jump_insn (gen_beq (label1));
4923 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4924 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4927 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4929 insn = emit_move_insn (operands[0],
4930 gen_highpart (SImode, operands[3]));
4932 gen_rtx_EXPR_LIST (REG_EQUAL,
4933 umod_equal, REG_NOTES (insn));
4935 emit_label (label1);
4936 emit_move_insn (operands[0], const0_rtx);
4938 emit_label (label2);
4939 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4940 emit_label (label3);
4946 ; div(df|sf)3 instruction pattern(s).
4949 (define_expand "div<mode>3"
4950 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4951 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4952 (match_operand:FPR 2 "general_operand" "f,R")))]
4956 (define_insn "*div<mode>3"
4957 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4958 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4959 (match_operand:FPR 2 "general_operand" "f,R")))]
4960 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4964 [(set_attr "op_type" "RRE,RXE")
4965 (set_attr "type" "fdiv<mode>")])
4967 (define_insn "*div<mode>3_ibm"
4968 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4969 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4970 (match_operand:FPR 2 "general_operand" "f,R")))]
4971 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4975 [(set_attr "op_type" "RR,RX")
4976 (set_attr "type" "fdiv<mode>")])
4980 ;;- And instructions.
4983 (define_expand "and<mode>3"
4984 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4985 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4986 (match_operand:INT 2 "general_operand" "")))
4987 (clobber (reg:CC CC_REGNUM))]
4989 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4992 ; anddi3 instruction pattern(s).
4995 (define_insn "*anddi3_cc"
4996 [(set (reg CC_REGNUM)
4997 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4998 (match_operand:DI 2 "general_operand" "d,m"))
5000 (set (match_operand:DI 0 "register_operand" "=d,d")
5001 (and:DI (match_dup 1) (match_dup 2)))]
5002 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5006 [(set_attr "op_type" "RRE,RXY")])
5008 (define_insn "*anddi3_cconly"
5009 [(set (reg CC_REGNUM)
5010 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5011 (match_operand:DI 2 "general_operand" "d,m"))
5013 (clobber (match_scratch:DI 0 "=d,d"))]
5014 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5015 /* Do not steal TM patterns. */
5016 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5020 [(set_attr "op_type" "RRE,RXY")])
5022 (define_insn "*anddi3_extimm"
5023 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5024 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5025 "%d,o,0,0,0,0,0,0,0,0,0,0")
5026 (match_operand:DI 2 "general_operand"
5027 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5028 (clobber (reg:CC CC_REGNUM))]
5029 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5043 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5045 (define_insn "*anddi3"
5046 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5047 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5048 "%d,o,0,0,0,0,0,0,0,0")
5049 (match_operand:DI 2 "general_operand"
5050 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5051 (clobber (reg:CC CC_REGNUM))]
5052 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5064 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5067 [(set (match_operand:DI 0 "s_operand" "")
5068 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5069 (clobber (reg:CC CC_REGNUM))]
5072 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5073 (clobber (reg:CC CC_REGNUM))])]
5074 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5078 ; andsi3 instruction pattern(s).
5081 (define_insn "*andsi3_cc"
5082 [(set (reg CC_REGNUM)
5083 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5084 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5086 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5087 (and:SI (match_dup 1) (match_dup 2)))]
5088 "s390_match_ccmode(insn, CCTmode)"
5094 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5096 (define_insn "*andsi3_cconly"
5097 [(set (reg CC_REGNUM)
5098 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5099 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5101 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5102 "s390_match_ccmode(insn, CCTmode)
5103 /* Do not steal TM patterns. */
5104 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5110 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5112 (define_insn "*andsi3_zarch"
5113 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5114 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5115 "%d,o,0,0,0,0,0,0,0,0")
5116 (match_operand:SI 2 "general_operand"
5117 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5118 (clobber (reg:CC CC_REGNUM))]
5119 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5131 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5133 (define_insn "*andsi3_esa"
5134 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5135 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5136 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5137 (clobber (reg:CC CC_REGNUM))]
5138 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5144 [(set_attr "op_type" "RR,RX,SI,SS")])
5147 [(set (match_operand:SI 0 "s_operand" "")
5148 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5149 (clobber (reg:CC CC_REGNUM))]
5152 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5153 (clobber (reg:CC CC_REGNUM))])]
5154 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5157 ; andhi3 instruction pattern(s).
5160 (define_insn "*andhi3_zarch"
5161 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5162 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5163 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5164 (clobber (reg:CC CC_REGNUM))]
5165 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5171 [(set_attr "op_type" "RR,RI,SI,SS")])
5173 (define_insn "*andhi3_esa"
5174 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5175 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5176 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5177 (clobber (reg:CC CC_REGNUM))]
5178 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5183 [(set_attr "op_type" "RR,SI,SS")])
5186 [(set (match_operand:HI 0 "s_operand" "")
5187 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5188 (clobber (reg:CC CC_REGNUM))]
5191 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5192 (clobber (reg:CC CC_REGNUM))])]
5193 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5196 ; andqi3 instruction pattern(s).
5199 (define_insn "*andqi3_zarch"
5200 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5201 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5202 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5203 (clobber (reg:CC CC_REGNUM))]
5204 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5211 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5213 (define_insn "*andqi3_esa"
5214 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5215 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5216 (match_operand:QI 2 "general_operand" "d,n,Q")))
5217 (clobber (reg:CC CC_REGNUM))]
5218 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5223 [(set_attr "op_type" "RR,SI,SS")])
5226 ; Block and (NC) patterns.
5230 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5231 (and:BLK (match_dup 0)
5232 (match_operand:BLK 1 "memory_operand" "Q")))
5233 (use (match_operand 2 "const_int_operand" "n"))
5234 (clobber (reg:CC CC_REGNUM))]
5235 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5236 "nc\t%O0(%2,%R0),%S1"
5237 [(set_attr "op_type" "SS")])
5240 [(set (match_operand 0 "memory_operand" "")
5242 (match_operand 1 "memory_operand" "")))
5243 (clobber (reg:CC CC_REGNUM))]
5245 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5246 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5248 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5250 (clobber (reg:CC CC_REGNUM))])]
5252 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5253 operands[0] = adjust_address (operands[0], BLKmode, 0);
5254 operands[1] = adjust_address (operands[1], BLKmode, 0);
5259 [(set (match_operand:BLK 0 "memory_operand" "")
5260 (and:BLK (match_dup 0)
5261 (match_operand:BLK 1 "memory_operand" "")))
5262 (use (match_operand 2 "const_int_operand" ""))
5263 (clobber (reg:CC CC_REGNUM))])
5265 [(set (match_operand:BLK 3 "memory_operand" "")
5266 (and:BLK (match_dup 3)
5267 (match_operand:BLK 4 "memory_operand" "")))
5268 (use (match_operand 5 "const_int_operand" ""))
5269 (clobber (reg:CC CC_REGNUM))])]
5270 "s390_offset_p (operands[0], operands[3], operands[2])
5271 && s390_offset_p (operands[1], operands[4], operands[2])
5272 && !s390_overlap_p (operands[0], operands[1],
5273 INTVAL (operands[2]) + INTVAL (operands[5]))
5274 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5276 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5278 (clobber (reg:CC CC_REGNUM))])]
5279 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5280 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5281 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5285 ;;- Bit set (inclusive or) instructions.
5288 (define_expand "ior<mode>3"
5289 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5290 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5291 (match_operand:INT 2 "general_operand" "")))
5292 (clobber (reg:CC CC_REGNUM))]
5294 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5297 ; iordi3 instruction pattern(s).
5300 (define_insn "*iordi3_cc"
5301 [(set (reg CC_REGNUM)
5302 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5303 (match_operand:DI 2 "general_operand" "d,m"))
5305 (set (match_operand:DI 0 "register_operand" "=d,d")
5306 (ior:DI (match_dup 1) (match_dup 2)))]
5307 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5311 [(set_attr "op_type" "RRE,RXY")])
5313 (define_insn "*iordi3_cconly"
5314 [(set (reg CC_REGNUM)
5315 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5316 (match_operand:DI 2 "general_operand" "d,m"))
5318 (clobber (match_scratch:DI 0 "=d,d"))]
5319 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5323 [(set_attr "op_type" "RRE,RXY")])
5325 (define_insn "*iordi3_extimm"
5326 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5327 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5328 (match_operand:DI 2 "general_operand"
5329 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5330 (clobber (reg:CC CC_REGNUM))]
5331 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5343 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5345 (define_insn "*iordi3"
5346 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5347 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5348 (match_operand:DI 2 "general_operand"
5349 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5350 (clobber (reg:CC CC_REGNUM))]
5351 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5361 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5364 [(set (match_operand:DI 0 "s_operand" "")
5365 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5366 (clobber (reg:CC CC_REGNUM))]
5369 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5370 (clobber (reg:CC CC_REGNUM))])]
5371 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5374 ; iorsi3 instruction pattern(s).
5377 (define_insn "*iorsi3_cc"
5378 [(set (reg CC_REGNUM)
5379 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5380 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5382 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5383 (ior:SI (match_dup 1) (match_dup 2)))]
5384 "s390_match_ccmode(insn, CCTmode)"
5390 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5392 (define_insn "*iorsi3_cconly"
5393 [(set (reg CC_REGNUM)
5394 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5395 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5397 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5398 "s390_match_ccmode(insn, CCTmode)"
5404 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5406 (define_insn "*iorsi3_zarch"
5407 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5408 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5409 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5410 (clobber (reg:CC CC_REGNUM))]
5411 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5421 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5423 (define_insn "*iorsi3_esa"
5424 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5425 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5426 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5427 (clobber (reg:CC CC_REGNUM))]
5428 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5434 [(set_attr "op_type" "RR,RX,SI,SS")])
5437 [(set (match_operand:SI 0 "s_operand" "")
5438 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5439 (clobber (reg:CC CC_REGNUM))]
5442 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5443 (clobber (reg:CC CC_REGNUM))])]
5444 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5447 ; iorhi3 instruction pattern(s).
5450 (define_insn "*iorhi3_zarch"
5451 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5452 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5453 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5454 (clobber (reg:CC CC_REGNUM))]
5455 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5461 [(set_attr "op_type" "RR,RI,SI,SS")])
5463 (define_insn "*iorhi3_esa"
5464 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5465 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5466 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5467 (clobber (reg:CC CC_REGNUM))]
5468 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5473 [(set_attr "op_type" "RR,SI,SS")])
5476 [(set (match_operand:HI 0 "s_operand" "")
5477 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5478 (clobber (reg:CC CC_REGNUM))]
5481 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5482 (clobber (reg:CC CC_REGNUM))])]
5483 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5486 ; iorqi3 instruction pattern(s).
5489 (define_insn "*iorqi3_zarch"
5490 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5491 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5492 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5493 (clobber (reg:CC CC_REGNUM))]
5494 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5501 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5503 (define_insn "*iorqi3_esa"
5504 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5505 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5506 (match_operand:QI 2 "general_operand" "d,n,Q")))
5507 (clobber (reg:CC CC_REGNUM))]
5508 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5513 [(set_attr "op_type" "RR,SI,SS")])
5516 ; Block inclusive or (OC) patterns.
5520 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5521 (ior:BLK (match_dup 0)
5522 (match_operand:BLK 1 "memory_operand" "Q")))
5523 (use (match_operand 2 "const_int_operand" "n"))
5524 (clobber (reg:CC CC_REGNUM))]
5525 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5526 "oc\t%O0(%2,%R0),%S1"
5527 [(set_attr "op_type" "SS")])
5530 [(set (match_operand 0 "memory_operand" "")
5532 (match_operand 1 "memory_operand" "")))
5533 (clobber (reg:CC CC_REGNUM))]
5535 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5536 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5538 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5540 (clobber (reg:CC CC_REGNUM))])]
5542 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5543 operands[0] = adjust_address (operands[0], BLKmode, 0);
5544 operands[1] = adjust_address (operands[1], BLKmode, 0);
5549 [(set (match_operand:BLK 0 "memory_operand" "")
5550 (ior:BLK (match_dup 0)
5551 (match_operand:BLK 1 "memory_operand" "")))
5552 (use (match_operand 2 "const_int_operand" ""))
5553 (clobber (reg:CC CC_REGNUM))])
5555 [(set (match_operand:BLK 3 "memory_operand" "")
5556 (ior:BLK (match_dup 3)
5557 (match_operand:BLK 4 "memory_operand" "")))
5558 (use (match_operand 5 "const_int_operand" ""))
5559 (clobber (reg:CC CC_REGNUM))])]
5560 "s390_offset_p (operands[0], operands[3], operands[2])
5561 && s390_offset_p (operands[1], operands[4], operands[2])
5562 && !s390_overlap_p (operands[0], operands[1],
5563 INTVAL (operands[2]) + INTVAL (operands[5]))
5564 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5566 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5568 (clobber (reg:CC CC_REGNUM))])]
5569 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5570 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5571 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5575 ;;- Xor instructions.
5578 (define_expand "xor<mode>3"
5579 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5580 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5581 (match_operand:INT 2 "general_operand" "")))
5582 (clobber (reg:CC CC_REGNUM))]
5584 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5587 ; xordi3 instruction pattern(s).
5590 (define_insn "*xordi3_cc"
5591 [(set (reg CC_REGNUM)
5592 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5593 (match_operand:DI 2 "general_operand" "d,m"))
5595 (set (match_operand:DI 0 "register_operand" "=d,d")
5596 (xor:DI (match_dup 1) (match_dup 2)))]
5597 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5601 [(set_attr "op_type" "RRE,RXY")])
5603 (define_insn "*xordi3_cconly"
5604 [(set (reg CC_REGNUM)
5605 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5606 (match_operand:DI 2 "general_operand" "d,m"))
5608 (clobber (match_scratch:DI 0 "=d,d"))]
5609 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5613 [(set_attr "op_type" "RRE,RXY")])
5615 (define_insn "*xordi3_extimm"
5616 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5617 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5618 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5619 (clobber (reg:CC CC_REGNUM))]
5620 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5628 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5630 (define_insn "*xordi3"
5631 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5632 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5633 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5634 (clobber (reg:CC CC_REGNUM))]
5635 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5641 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5644 [(set (match_operand:DI 0 "s_operand" "")
5645 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5646 (clobber (reg:CC CC_REGNUM))]
5649 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5650 (clobber (reg:CC CC_REGNUM))])]
5651 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5654 ; xorsi3 instruction pattern(s).
5657 (define_insn "*xorsi3_cc"
5658 [(set (reg CC_REGNUM)
5659 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5660 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5662 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5663 (xor:SI (match_dup 1) (match_dup 2)))]
5664 "s390_match_ccmode(insn, CCTmode)"
5670 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5672 (define_insn "*xorsi3_cconly"
5673 [(set (reg CC_REGNUM)
5674 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5675 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5677 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5678 "s390_match_ccmode(insn, CCTmode)"
5684 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5686 (define_insn "*xorsi3"
5687 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5688 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5689 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5690 (clobber (reg:CC CC_REGNUM))]
5691 "s390_logical_operator_ok_p (operands)"
5699 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5702 [(set (match_operand:SI 0 "s_operand" "")
5703 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5704 (clobber (reg:CC CC_REGNUM))]
5707 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5708 (clobber (reg:CC CC_REGNUM))])]
5709 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5712 ; xorhi3 instruction pattern(s).
5715 (define_insn "*xorhi3"
5716 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5717 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5718 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5719 (clobber (reg:CC CC_REGNUM))]
5720 "s390_logical_operator_ok_p (operands)"
5726 [(set_attr "op_type" "RIL,RR,SI,SS")])
5729 [(set (match_operand:HI 0 "s_operand" "")
5730 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5731 (clobber (reg:CC CC_REGNUM))]
5734 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5735 (clobber (reg:CC CC_REGNUM))])]
5736 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5739 ; xorqi3 instruction pattern(s).
5742 (define_insn "*xorqi3"
5743 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5744 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5745 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5746 (clobber (reg:CC CC_REGNUM))]
5747 "s390_logical_operator_ok_p (operands)"
5754 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5757 ; Block exclusive or (XC) patterns.
5761 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5762 (xor:BLK (match_dup 0)
5763 (match_operand:BLK 1 "memory_operand" "Q")))
5764 (use (match_operand 2 "const_int_operand" "n"))
5765 (clobber (reg:CC CC_REGNUM))]
5766 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5767 "xc\t%O0(%2,%R0),%S1"
5768 [(set_attr "op_type" "SS")])
5771 [(set (match_operand 0 "memory_operand" "")
5773 (match_operand 1 "memory_operand" "")))
5774 (clobber (reg:CC CC_REGNUM))]
5776 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5777 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5779 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5781 (clobber (reg:CC CC_REGNUM))])]
5783 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5784 operands[0] = adjust_address (operands[0], BLKmode, 0);
5785 operands[1] = adjust_address (operands[1], BLKmode, 0);
5790 [(set (match_operand:BLK 0 "memory_operand" "")
5791 (xor:BLK (match_dup 0)
5792 (match_operand:BLK 1 "memory_operand" "")))
5793 (use (match_operand 2 "const_int_operand" ""))
5794 (clobber (reg:CC CC_REGNUM))])
5796 [(set (match_operand:BLK 3 "memory_operand" "")
5797 (xor:BLK (match_dup 3)
5798 (match_operand:BLK 4 "memory_operand" "")))
5799 (use (match_operand 5 "const_int_operand" ""))
5800 (clobber (reg:CC CC_REGNUM))])]
5801 "s390_offset_p (operands[0], operands[3], operands[2])
5802 && s390_offset_p (operands[1], operands[4], operands[2])
5803 && !s390_overlap_p (operands[0], operands[1],
5804 INTVAL (operands[2]) + INTVAL (operands[5]))
5805 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5807 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5809 (clobber (reg:CC CC_REGNUM))])]
5810 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5811 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5812 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5815 ; Block xor (XC) patterns with src == dest.
5818 (define_insn "*xc_zero"
5819 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5821 (use (match_operand 1 "const_int_operand" "n"))
5822 (clobber (reg:CC CC_REGNUM))]
5823 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5824 "xc\t%O0(%1,%R0),%S0"
5825 [(set_attr "op_type" "SS")])
5829 [(set (match_operand:BLK 0 "memory_operand" "")
5831 (use (match_operand 1 "const_int_operand" ""))
5832 (clobber (reg:CC CC_REGNUM))])
5834 [(set (match_operand:BLK 2 "memory_operand" "")
5836 (use (match_operand 3 "const_int_operand" ""))
5837 (clobber (reg:CC CC_REGNUM))])]
5838 "s390_offset_p (operands[0], operands[2], operands[1])
5839 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5841 [(set (match_dup 4) (const_int 0))
5843 (clobber (reg:CC CC_REGNUM))])]
5844 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5845 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5849 ;;- Negate instructions.
5853 ; neg(di|si)2 instruction pattern(s).
5856 (define_expand "neg<mode>2"
5858 [(set (match_operand:DSI 0 "register_operand" "=d")
5859 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5860 (clobber (reg:CC CC_REGNUM))])]
5864 (define_insn "*negdi2_sign_cc"
5865 [(set (reg CC_REGNUM)
5866 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5867 (match_operand:SI 1 "register_operand" "d") 0)
5868 (const_int 32)) (const_int 32)))
5870 (set (match_operand:DI 0 "register_operand" "=d")
5871 (neg:DI (sign_extend:DI (match_dup 1))))]
5872 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5874 [(set_attr "op_type" "RRE")])
5876 (define_insn "*negdi2_sign"
5877 [(set (match_operand:DI 0 "register_operand" "=d")
5878 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5879 (clobber (reg:CC CC_REGNUM))]
5882 [(set_attr "op_type" "RRE")])
5884 (define_insn "*neg<mode>2_cc"
5885 [(set (reg CC_REGNUM)
5886 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5888 (set (match_operand:GPR 0 "register_operand" "=d")
5889 (neg:GPR (match_dup 1)))]
5890 "s390_match_ccmode (insn, CCAmode)"
5892 [(set_attr "op_type" "RR<E>")])
5894 (define_insn "*neg<mode>2_cconly"
5895 [(set (reg CC_REGNUM)
5896 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5898 (clobber (match_scratch:GPR 0 "=d"))]
5899 "s390_match_ccmode (insn, CCAmode)"
5901 [(set_attr "op_type" "RR<E>")])
5903 (define_insn "*neg<mode>2"
5904 [(set (match_operand:GPR 0 "register_operand" "=d")
5905 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5906 (clobber (reg:CC CC_REGNUM))]
5909 [(set_attr "op_type" "RR<E>")])
5911 (define_insn_and_split "*negdi2_31"
5912 [(set (match_operand:DI 0 "register_operand" "=d")
5913 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5914 (clobber (reg:CC CC_REGNUM))]
5917 "&& reload_completed"
5919 [(set (match_dup 2) (neg:SI (match_dup 3)))
5920 (clobber (reg:CC CC_REGNUM))])
5922 [(set (reg:CCAP CC_REGNUM)
5923 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5924 (set (match_dup 4) (neg:SI (match_dup 5)))])
5926 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5928 (label_ref (match_dup 6))))
5930 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5931 (clobber (reg:CC CC_REGNUM))])
5933 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5934 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5935 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5936 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5937 operands[6] = gen_label_rtx ();")
5940 ; neg(df|sf)2 instruction pattern(s).
5943 (define_expand "neg<mode>2"
5945 [(set (match_operand:FPR 0 "register_operand" "=f")
5946 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5947 (clobber (reg:CC CC_REGNUM))])]
5951 (define_insn "*neg<mode>2_cc"
5952 [(set (reg CC_REGNUM)
5953 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5954 (match_operand:FPR 2 "const0_operand" "")))
5955 (set (match_operand:FPR 0 "register_operand" "=f")
5956 (neg:FPR (match_dup 1)))]
5957 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5959 [(set_attr "op_type" "RRE")
5960 (set_attr "type" "fsimp<mode>")])
5962 (define_insn "*neg<mode>2_cconly"
5963 [(set (reg CC_REGNUM)
5964 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5965 (match_operand:FPR 2 "const0_operand" "")))
5966 (clobber (match_scratch:FPR 0 "=f"))]
5967 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5969 [(set_attr "op_type" "RRE")
5970 (set_attr "type" "fsimp<mode>")])
5972 (define_insn "*neg<mode>2"
5973 [(set (match_operand:FPR 0 "register_operand" "=f")
5974 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5975 (clobber (reg:CC CC_REGNUM))]
5976 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5978 [(set_attr "op_type" "RRE")
5979 (set_attr "type" "fsimp<mode>")])
5981 (define_insn "*neg<mode>2_ibm"
5982 [(set (match_operand:FPR 0 "register_operand" "=f")
5983 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5984 (clobber (reg:CC CC_REGNUM))]
5985 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5987 [(set_attr "op_type" "RR")
5988 (set_attr "type" "fsimp<mode>")])
5992 ;;- Absolute value instructions.
5996 ; abs(di|si)2 instruction pattern(s).
5999 (define_insn "*absdi2_sign_cc"
6000 [(set (reg CC_REGNUM)
6001 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6002 (match_operand:SI 1 "register_operand" "d") 0)
6003 (const_int 32)) (const_int 32)))
6005 (set (match_operand:DI 0 "register_operand" "=d")
6006 (abs:DI (sign_extend:DI (match_dup 1))))]
6007 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6009 [(set_attr "op_type" "RRE")])
6011 (define_insn "*absdi2_sign"
6012 [(set (match_operand:DI 0 "register_operand" "=d")
6013 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6014 (clobber (reg:CC CC_REGNUM))]
6017 [(set_attr "op_type" "RRE")])
6019 (define_insn "*abs<mode>2_cc"
6020 [(set (reg CC_REGNUM)
6021 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6023 (set (match_operand:GPR 0 "register_operand" "=d")
6024 (abs:GPR (match_dup 1)))]
6025 "s390_match_ccmode (insn, CCAmode)"
6027 [(set_attr "op_type" "RR<E>")])
6029 (define_insn "*abs<mode>2_cconly"
6030 [(set (reg CC_REGNUM)
6031 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6033 (clobber (match_scratch:GPR 0 "=d"))]
6034 "s390_match_ccmode (insn, CCAmode)"
6036 [(set_attr "op_type" "RR<E>")])
6038 (define_insn "abs<mode>2"
6039 [(set (match_operand:GPR 0 "register_operand" "=d")
6040 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6041 (clobber (reg:CC CC_REGNUM))]
6044 [(set_attr "op_type" "RR<E>")])
6047 ; abs(df|sf)2 instruction pattern(s).
6050 (define_expand "abs<mode>2"
6052 [(set (match_operand:FPR 0 "register_operand" "=f")
6053 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6054 (clobber (reg:CC CC_REGNUM))])]
6058 (define_insn "*abs<mode>2_cc"
6059 [(set (reg CC_REGNUM)
6060 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6061 (match_operand:FPR 2 "const0_operand" "")))
6062 (set (match_operand:FPR 0 "register_operand" "=f")
6063 (abs:FPR (match_dup 1)))]
6064 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6066 [(set_attr "op_type" "RRE")
6067 (set_attr "type" "fsimp<mode>")])
6069 (define_insn "*abs<mode>2_cconly"
6070 [(set (reg CC_REGNUM)
6071 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6072 (match_operand:FPR 2 "const0_operand" "")))
6073 (clobber (match_scratch:FPR 0 "=f"))]
6074 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6076 [(set_attr "op_type" "RRE")
6077 (set_attr "type" "fsimp<mode>")])
6079 (define_insn "*abs<mode>2"
6080 [(set (match_operand:FPR 0 "register_operand" "=f")
6081 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6082 (clobber (reg:CC CC_REGNUM))]
6083 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6085 [(set_attr "op_type" "RRE")
6086 (set_attr "type" "fsimp<mode>")])
6088 (define_insn "*abs<mode>2_ibm"
6089 [(set (match_operand:FPR 0 "register_operand" "=f")
6090 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6091 (clobber (reg:CC CC_REGNUM))]
6092 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6094 [(set_attr "op_type" "RR")
6095 (set_attr "type" "fsimp<mode>")])
6098 ;;- Negated absolute value instructions
6105 (define_insn "*negabsdi2_sign_cc"
6106 [(set (reg CC_REGNUM)
6107 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6108 (match_operand:SI 1 "register_operand" "d") 0)
6109 (const_int 32)) (const_int 32))))
6111 (set (match_operand:DI 0 "register_operand" "=d")
6112 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6113 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6115 [(set_attr "op_type" "RRE")])
6117 (define_insn "*negabsdi2_sign"
6118 [(set (match_operand:DI 0 "register_operand" "=d")
6119 (neg:DI (abs:DI (sign_extend:DI
6120 (match_operand:SI 1 "register_operand" "d")))))
6121 (clobber (reg:CC CC_REGNUM))]
6124 [(set_attr "op_type" "RRE")])
6126 (define_insn "*negabs<mode>2_cc"
6127 [(set (reg CC_REGNUM)
6128 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6130 (set (match_operand:GPR 0 "register_operand" "=d")
6131 (neg:GPR (abs:GPR (match_dup 1))))]
6132 "s390_match_ccmode (insn, CCAmode)"
6134 [(set_attr "op_type" "RR<E>")])
6136 (define_insn "*negabs<mode>2_cconly"
6137 [(set (reg CC_REGNUM)
6138 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6140 (clobber (match_scratch:GPR 0 "=d"))]
6141 "s390_match_ccmode (insn, CCAmode)"
6143 [(set_attr "op_type" "RR<E>")])
6145 (define_insn "*negabs<mode>2"
6146 [(set (match_operand:GPR 0 "register_operand" "=d")
6147 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6148 (clobber (reg:CC CC_REGNUM))]
6151 [(set_attr "op_type" "RR<E>")])
6157 (define_insn "*negabs<mode>2_cc"
6158 [(set (reg CC_REGNUM)
6159 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6160 (match_operand:FPR 2 "const0_operand" "")))
6161 (set (match_operand:FPR 0 "register_operand" "=f")
6162 (neg:FPR (abs:FPR (match_dup 1))))]
6163 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6165 [(set_attr "op_type" "RRE")
6166 (set_attr "type" "fsimp<mode>")])
6168 (define_insn "*negabs<mode>2_cconly"
6169 [(set (reg CC_REGNUM)
6170 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6171 (match_operand:FPR 2 "const0_operand" "")))
6172 (clobber (match_scratch:FPR 0 "=f"))]
6173 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6175 [(set_attr "op_type" "RRE")
6176 (set_attr "type" "fsimp<mode>")])
6178 (define_insn "*negabs<mode>2"
6179 [(set (match_operand:FPR 0 "register_operand" "=f")
6180 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6181 (clobber (reg:CC CC_REGNUM))]
6182 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6184 [(set_attr "op_type" "RRE")
6185 (set_attr "type" "fsimp<mode>")])
6188 ;;- Square root instructions.
6192 ; sqrt(df|sf)2 instruction pattern(s).
6195 (define_insn "sqrt<mode>2"
6196 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6197 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
6198 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6202 [(set_attr "op_type" "RRE,RXE")
6203 (set_attr "type" "fsqrt<mode>")])
6207 ;;- One complement instructions.
6211 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6214 (define_expand "one_cmpl<mode>2"
6216 [(set (match_operand:INT 0 "register_operand" "")
6217 (xor:INT (match_operand:INT 1 "register_operand" "")
6219 (clobber (reg:CC CC_REGNUM))])]
6225 ;; Find leftmost bit instructions.
6228 (define_expand "clzdi2"
6229 [(set (match_operand:DI 0 "register_operand" "=d")
6230 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6231 "TARGET_EXTIMM && TARGET_64BIT"
6233 rtx insn, clz_equal;
6234 rtx wide_reg = gen_reg_rtx (TImode);
6235 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6237 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6239 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6241 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6243 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6248 (define_insn "clztidi2"
6249 [(set (match_operand:TI 0 "register_operand" "=d")
6253 (xor:DI (match_operand:DI 1 "register_operand" "d")
6254 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6255 (subreg:SI (clz:DI (match_dup 1)) 4))))
6258 (zero_extend:TI (clz:DI (match_dup 1)))))
6259 (clobber (reg:CC CC_REGNUM))]
6260 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6261 == (unsigned HOST_WIDE_INT) 1 << 63
6262 && TARGET_EXTIMM && TARGET_64BIT"
6264 [(set_attr "op_type" "RRE")])
6268 ;;- Rotate instructions.
6272 ; rotl(di|si)3 instruction pattern(s).
6275 (define_insn "rotl<mode>3"
6276 [(set (match_operand:GPR 0 "register_operand" "=d")
6277 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6278 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6281 [(set_attr "op_type" "RSE")
6282 (set_attr "atype" "reg")])
6284 (define_insn "*rotl<mode>3_and"
6285 [(set (match_operand:GPR 0 "register_operand" "=d")
6286 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6287 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6288 (match_operand:SI 3 "const_int_operand" "n"))))]
6289 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6291 [(set_attr "op_type" "RSE")
6292 (set_attr "atype" "reg")])
6296 ;;- Shift instructions.
6300 ; (ashl|lshr)di3 instruction pattern(s).
6303 (define_expand "<shift>di3"
6304 [(set (match_operand:DI 0 "register_operand" "")
6305 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
6306 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6310 (define_insn "*<shift>di3_31"
6311 [(set (match_operand:DI 0 "register_operand" "=d")
6312 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6313 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6316 [(set_attr "op_type" "RS")
6317 (set_attr "atype" "reg")])
6319 (define_insn "*<shift>di3_64"
6320 [(set (match_operand:DI 0 "register_operand" "=d")
6321 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6322 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6324 "s<lr>lg\t%0,%1,%Y2"
6325 [(set_attr "op_type" "RSE")
6326 (set_attr "atype" "reg")])
6328 (define_insn "*<shift>di3_31_and"
6329 [(set (match_operand:DI 0 "register_operand" "=d")
6330 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6331 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6332 (match_operand:SI 3 "const_int_operand" "n"))))]
6333 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6335 [(set_attr "op_type" "RS")
6336 (set_attr "atype" "reg")])
6338 (define_insn "*<shift>di3_64_and"
6339 [(set (match_operand:DI 0 "register_operand" "=d")
6340 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6341 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6342 (match_operand:SI 3 "const_int_operand" "n"))))]
6343 "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6344 "s<lr>lg\t%0,%1,%Y2"
6345 [(set_attr "op_type" "RSE")
6346 (set_attr "atype" "reg")])
6349 ; ashrdi3 instruction pattern(s).
6352 (define_expand "ashrdi3"
6354 [(set (match_operand:DI 0 "register_operand" "")
6355 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6356 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6357 (clobber (reg:CC CC_REGNUM))])]
6361 (define_insn "*ashrdi3_cc_31"
6362 [(set (reg CC_REGNUM)
6363 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6364 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6366 (set (match_operand:DI 0 "register_operand" "=d")
6367 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6368 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6370 [(set_attr "op_type" "RS")
6371 (set_attr "atype" "reg")])
6373 (define_insn "*ashrdi3_cconly_31"
6374 [(set (reg CC_REGNUM)
6375 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6376 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6378 (clobber (match_scratch:DI 0 "=d"))]
6379 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6381 [(set_attr "op_type" "RS")
6382 (set_attr "atype" "reg")])
6384 (define_insn "*ashrdi3_31"
6385 [(set (match_operand:DI 0 "register_operand" "=d")
6386 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6387 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6388 (clobber (reg:CC CC_REGNUM))]
6391 [(set_attr "op_type" "RS")
6392 (set_attr "atype" "reg")])
6394 (define_insn "*ashrdi3_cc_64"
6395 [(set (reg CC_REGNUM)
6396 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6397 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6399 (set (match_operand:DI 0 "register_operand" "=d")
6400 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6401 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6403 [(set_attr "op_type" "RSE")
6404 (set_attr "atype" "reg")])
6406 (define_insn "*ashrdi3_cconly_64"
6407 [(set (reg CC_REGNUM)
6408 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6409 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6411 (clobber (match_scratch:DI 0 "=d"))]
6412 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6414 [(set_attr "op_type" "RSE")
6415 (set_attr "atype" "reg")])
6417 (define_insn "*ashrdi3_64"
6418 [(set (match_operand:DI 0 "register_operand" "=d")
6419 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6420 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6421 (clobber (reg:CC CC_REGNUM))]
6424 [(set_attr "op_type" "RSE")
6425 (set_attr "atype" "reg")])
6428 ; shift pattern with implicit ANDs
6430 (define_insn "*ashrdi3_cc_31_and"
6431 [(set (reg CC_REGNUM)
6432 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6433 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6434 (match_operand:SI 3 "const_int_operand" "n")))
6436 (set (match_operand:DI 0 "register_operand" "=d")
6437 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6438 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6439 && (INTVAL (operands[3]) & 63) == 63"
6441 [(set_attr "op_type" "RS")
6442 (set_attr "atype" "reg")])
6444 (define_insn "*ashrdi3_cconly_31_and"
6445 [(set (reg CC_REGNUM)
6446 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6447 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6448 (match_operand:SI 3 "const_int_operand" "n")))
6450 (clobber (match_scratch:DI 0 "=d"))]
6451 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6452 && (INTVAL (operands[3]) & 63) == 63"
6454 [(set_attr "op_type" "RS")
6455 (set_attr "atype" "reg")])
6457 (define_insn "*ashrdi3_31_and"
6458 [(set (match_operand:DI 0 "register_operand" "=d")
6459 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6460 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6461 (match_operand:SI 3 "const_int_operand" "n"))))
6462 (clobber (reg:CC CC_REGNUM))]
6463 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6465 [(set_attr "op_type" "RS")
6466 (set_attr "atype" "reg")])
6468 (define_insn "*ashrdi3_cc_64_and"
6469 [(set (reg CC_REGNUM)
6470 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6471 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6472 (match_operand:SI 3 "const_int_operand" "n")))
6474 (set (match_operand:DI 0 "register_operand" "=d")
6475 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6476 "TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6477 && (INTVAL (operands[3]) & 63) == 63"
6479 [(set_attr "op_type" "RSE")
6480 (set_attr "atype" "reg")])
6482 (define_insn "*ashrdi3_cconly_64_and"
6483 [(set (reg CC_REGNUM)
6484 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6485 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6486 (match_operand:SI 3 "const_int_operand" "n")))
6488 (clobber (match_scratch:DI 0 "=d"))]
6489 "TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6490 && (INTVAL (operands[3]) & 63) == 63"
6492 [(set_attr "op_type" "RSE")
6493 (set_attr "atype" "reg")])
6495 (define_insn "*ashrdi3_64_and"
6496 [(set (match_operand:DI 0 "register_operand" "=d")
6497 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6498 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6499 (match_operand:SI 3 "const_int_operand" "n"))))
6500 (clobber (reg:CC CC_REGNUM))]
6501 "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6503 [(set_attr "op_type" "RSE")
6504 (set_attr "atype" "reg")])
6507 ; (ashl|lshr)si3 instruction pattern(s).
6510 (define_insn "<shift>si3"
6511 [(set (match_operand:SI 0 "register_operand" "=d")
6512 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6513 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6516 [(set_attr "op_type" "RS")
6517 (set_attr "atype" "reg")])
6519 (define_insn "*<shift>si3_and"
6520 [(set (match_operand:SI 0 "register_operand" "=d")
6521 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6522 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6523 (match_operand:SI 3 "const_int_operand" "n"))))]
6524 "(INTVAL (operands[3]) & 63) == 63"
6526 [(set_attr "op_type" "RS")
6527 (set_attr "atype" "reg")])
6530 ; ashrsi3 instruction pattern(s).
6533 (define_insn "*ashrsi3_cc"
6534 [(set (reg CC_REGNUM)
6535 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6536 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6538 (set (match_operand:SI 0 "register_operand" "=d")
6539 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6540 "s390_match_ccmode(insn, CCSmode)"
6542 [(set_attr "op_type" "RS")
6543 (set_attr "atype" "reg")])
6546 (define_insn "*ashrsi3_cconly"
6547 [(set (reg CC_REGNUM)
6548 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6549 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6551 (clobber (match_scratch:SI 0 "=d"))]
6552 "s390_match_ccmode(insn, CCSmode)"
6554 [(set_attr "op_type" "RS")
6555 (set_attr "atype" "reg")])
6557 (define_insn "ashrsi3"
6558 [(set (match_operand:SI 0 "register_operand" "=d")
6559 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6560 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6561 (clobber (reg:CC CC_REGNUM))]
6564 [(set_attr "op_type" "RS")
6565 (set_attr "atype" "reg")])
6567 ; with implicit ANDs
6569 (define_insn "*ashrsi3_cc_and"
6570 [(set (reg CC_REGNUM)
6571 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6572 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6573 (match_operand:SI 3 "const_int_operand" "n")))
6575 (set (match_operand:SI 0 "register_operand" "=d")
6576 (ashiftrt:SI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6577 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6579 [(set_attr "op_type" "RS")
6580 (set_attr "atype" "reg")])
6583 (define_insn "*ashrsi3_cconly_and"
6584 [(set (reg CC_REGNUM)
6585 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6586 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6587 (match_operand:SI 3 "const_int_operand" "n")))
6589 (clobber (match_scratch:SI 0 "=d"))]
6590 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6592 [(set_attr "op_type" "RS")
6593 (set_attr "atype" "reg")])
6595 (define_insn "*ashrsi3_and"
6596 [(set (match_operand:SI 0 "register_operand" "=d")
6597 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6598 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6599 (match_operand:SI 3 "const_int_operand" "n"))))
6600 (clobber (reg:CC CC_REGNUM))]
6601 "(INTVAL (operands[3]) & 63) == 63"
6603 [(set_attr "op_type" "RS")
6604 (set_attr "atype" "reg")])
6608 ;; Branch instruction patterns.
6611 (define_expand "b<code>"
6613 (if_then_else (COMPARE (match_operand 0 "" "")
6618 "s390_emit_jump (operands[0],
6619 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6623 ;;- Conditional jump instructions.
6626 (define_insn "*cjump_64"
6629 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6630 (label_ref (match_operand 0 "" ""))
6634 if (get_attr_length (insn) == 4)
6637 return "jg%C1\t%l0";
6639 [(set_attr "op_type" "RI")
6640 (set_attr "type" "branch")
6641 (set (attr "length")
6642 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6643 (const_int 4) (const_int 6)))])
6645 (define_insn "*cjump_31"
6648 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6649 (label_ref (match_operand 0 "" ""))
6653 gcc_assert (get_attr_length (insn) == 4);
6656 [(set_attr "op_type" "RI")
6657 (set_attr "type" "branch")
6658 (set (attr "length")
6659 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6660 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6661 (const_int 4) (const_int 6))
6662 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6663 (const_int 4) (const_int 8))))])
6665 (define_insn "*cjump_long"
6668 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6669 (match_operand 0 "address_operand" "U")
6673 if (get_attr_op_type (insn) == OP_TYPE_RR)
6678 [(set (attr "op_type")
6679 (if_then_else (match_operand 0 "register_operand" "")
6680 (const_string "RR") (const_string "RX")))
6681 (set_attr "type" "branch")
6682 (set_attr "atype" "agen")])
6686 ;;- Negated conditional jump instructions.
6689 (define_insn "*icjump_64"
6692 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6694 (label_ref (match_operand 0 "" ""))))]
6697 if (get_attr_length (insn) == 4)
6700 return "jg%D1\t%l0";
6702 [(set_attr "op_type" "RI")
6703 (set_attr "type" "branch")
6704 (set (attr "length")
6705 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6706 (const_int 4) (const_int 6)))])
6708 (define_insn "*icjump_31"
6711 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6713 (label_ref (match_operand 0 "" ""))))]
6716 gcc_assert (get_attr_length (insn) == 4);
6719 [(set_attr "op_type" "RI")
6720 (set_attr "type" "branch")
6721 (set (attr "length")
6722 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6723 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6724 (const_int 4) (const_int 6))
6725 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6726 (const_int 4) (const_int 8))))])
6728 (define_insn "*icjump_long"
6731 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6733 (match_operand 0 "address_operand" "U")))]
6736 if (get_attr_op_type (insn) == OP_TYPE_RR)
6741 [(set (attr "op_type")
6742 (if_then_else (match_operand 0 "register_operand" "")
6743 (const_string "RR") (const_string "RX")))
6744 (set_attr "type" "branch")
6745 (set_attr "atype" "agen")])
6748 ;;- Trap instructions.
6752 [(trap_if (const_int 1) (const_int 0))]
6755 [(set_attr "op_type" "RI")
6756 (set_attr "type" "branch")])
6758 (define_expand "conditional_trap"
6759 [(trap_if (match_operand 0 "comparison_operator" "")
6760 (match_operand 1 "general_operand" ""))]
6763 if (operands[1] != const0_rtx) FAIL;
6764 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6765 s390_compare_op0, s390_compare_op1);
6768 (define_insn "*trap"
6769 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6773 [(set_attr "op_type" "RI")
6774 (set_attr "type" "branch")])
6777 ;;- Loop instructions.
6779 ;; This is all complicated by the fact that since this is a jump insn
6780 ;; we must handle our own output reloads.
6782 (define_expand "doloop_end"
6783 [(use (match_operand 0 "" "")) ; loop pseudo
6784 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6785 (use (match_operand 2 "" "")) ; max iterations
6786 (use (match_operand 3 "" "")) ; loop level
6787 (use (match_operand 4 "" ""))] ; label
6790 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6791 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6792 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6793 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6794 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6795 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6802 (define_insn_and_split "doloop_si64"
6805 (ne (match_operand:SI 1 "register_operand" "d,d")
6807 (label_ref (match_operand 0 "" ""))
6809 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6810 (plus:SI (match_dup 1) (const_int -1)))
6811 (clobber (match_scratch:SI 3 "=X,&1"))
6812 (clobber (reg:CC CC_REGNUM))]
6815 if (which_alternative != 0)
6817 else if (get_attr_length (insn) == 4)
6818 return "brct\t%1,%l0";
6820 return "ahi\t%1,-1\;jgne\t%l0";
6822 "&& reload_completed
6823 && (! REG_P (operands[2])
6824 || ! rtx_equal_p (operands[1], operands[2]))"
6825 [(parallel [(set (reg:CCAN CC_REGNUM)
6826 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6828 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6829 (set (match_dup 2) (match_dup 3))
6830 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6831 (label_ref (match_dup 0))
6834 [(set_attr "op_type" "RI")
6835 (set_attr "type" "branch")
6836 (set (attr "length")
6837 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6838 (const_int 4) (const_int 10)))])
6840 (define_insn_and_split "doloop_si31"
6843 (ne (match_operand:SI 1 "register_operand" "d,d")
6845 (label_ref (match_operand 0 "" ""))
6847 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6848 (plus:SI (match_dup 1) (const_int -1)))
6849 (clobber (match_scratch:SI 3 "=X,&1"))
6850 (clobber (reg:CC CC_REGNUM))]
6853 if (which_alternative != 0)
6855 else if (get_attr_length (insn) == 4)
6856 return "brct\t%1,%l0";
6860 "&& reload_completed
6861 && (! REG_P (operands[2])
6862 || ! rtx_equal_p (operands[1], operands[2]))"
6863 [(parallel [(set (reg:CCAN CC_REGNUM)
6864 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6866 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6867 (set (match_dup 2) (match_dup 3))
6868 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6869 (label_ref (match_dup 0))
6872 [(set_attr "op_type" "RI")
6873 (set_attr "type" "branch")
6874 (set (attr "length")
6875 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6876 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6877 (const_int 4) (const_int 6))
6878 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6879 (const_int 4) (const_int 8))))])
6881 (define_insn "*doloop_si_long"
6884 (ne (match_operand:SI 1 "register_operand" "d,d")
6886 (match_operand 0 "address_operand" "U,U")
6888 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6889 (plus:SI (match_dup 1) (const_int -1)))
6890 (clobber (match_scratch:SI 3 "=X,&1"))
6891 (clobber (reg:CC CC_REGNUM))]
6894 if (get_attr_op_type (insn) == OP_TYPE_RR)
6895 return "bctr\t%1,%0";
6897 return "bct\t%1,%a0";
6899 [(set (attr "op_type")
6900 (if_then_else (match_operand 0 "register_operand" "")
6901 (const_string "RR") (const_string "RX")))
6902 (set_attr "type" "branch")
6903 (set_attr "atype" "agen")])
6905 (define_insn_and_split "doloop_di"
6908 (ne (match_operand:DI 1 "register_operand" "d,d")
6910 (label_ref (match_operand 0 "" ""))
6912 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6913 (plus:DI (match_dup 1) (const_int -1)))
6914 (clobber (match_scratch:DI 3 "=X,&1"))
6915 (clobber (reg:CC CC_REGNUM))]
6918 if (which_alternative != 0)
6920 else if (get_attr_length (insn) == 4)
6921 return "brctg\t%1,%l0";
6923 return "aghi\t%1,-1\;jgne\t%l0";
6925 "&& reload_completed
6926 && (! REG_P (operands[2])
6927 || ! rtx_equal_p (operands[1], operands[2]))"
6928 [(parallel [(set (reg:CCAN CC_REGNUM)
6929 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6931 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6932 (set (match_dup 2) (match_dup 3))
6933 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6934 (label_ref (match_dup 0))
6937 [(set_attr "op_type" "RI")
6938 (set_attr "type" "branch")
6939 (set (attr "length")
6940 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6941 (const_int 4) (const_int 10)))])
6944 ;;- Unconditional jump instructions.
6948 ; jump instruction pattern(s).
6951 (define_expand "jump"
6952 [(match_operand 0 "" "")]
6954 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6956 (define_insn "*jump64"
6957 [(set (pc) (label_ref (match_operand 0 "" "")))]
6960 if (get_attr_length (insn) == 4)
6965 [(set_attr "op_type" "RI")
6966 (set_attr "type" "branch")
6967 (set (attr "length")
6968 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6969 (const_int 4) (const_int 6)))])
6971 (define_insn "*jump31"
6972 [(set (pc) (label_ref (match_operand 0 "" "")))]
6975 gcc_assert (get_attr_length (insn) == 4);
6978 [(set_attr "op_type" "RI")
6979 (set_attr "type" "branch")
6980 (set (attr "length")
6981 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6982 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6983 (const_int 4) (const_int 6))
6984 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6985 (const_int 4) (const_int 8))))])
6988 ; indirect-jump instruction pattern(s).
6991 (define_insn "indirect_jump"
6992 [(set (pc) (match_operand 0 "address_operand" "U"))]
6995 if (get_attr_op_type (insn) == OP_TYPE_RR)
7000 [(set (attr "op_type")
7001 (if_then_else (match_operand 0 "register_operand" "")
7002 (const_string "RR") (const_string "RX")))
7003 (set_attr "type" "branch")
7004 (set_attr "atype" "agen")])
7007 ; casesi instruction pattern(s).
7010 (define_insn "casesi_jump"
7011 [(set (pc) (match_operand 0 "address_operand" "U"))
7012 (use (label_ref (match_operand 1 "" "")))]
7015 if (get_attr_op_type (insn) == OP_TYPE_RR)
7020 [(set (attr "op_type")
7021 (if_then_else (match_operand 0 "register_operand" "")
7022 (const_string "RR") (const_string "RX")))
7023 (set_attr "type" "branch")
7024 (set_attr "atype" "agen")])
7026 (define_expand "casesi"
7027 [(match_operand:SI 0 "general_operand" "")
7028 (match_operand:SI 1 "general_operand" "")
7029 (match_operand:SI 2 "general_operand" "")
7030 (label_ref (match_operand 3 "" ""))
7031 (label_ref (match_operand 4 "" ""))]
7034 rtx index = gen_reg_rtx (SImode);
7035 rtx base = gen_reg_rtx (Pmode);
7036 rtx target = gen_reg_rtx (Pmode);
7038 emit_move_insn (index, operands[0]);
7039 emit_insn (gen_subsi3 (index, index, operands[1]));
7040 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7043 if (Pmode != SImode)
7044 index = convert_to_mode (Pmode, index, 1);
7045 if (GET_CODE (index) != REG)
7046 index = copy_to_mode_reg (Pmode, index);
7049 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7051 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7053 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7055 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7056 emit_move_insn (target, index);
7059 target = gen_rtx_PLUS (Pmode, base, target);
7060 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7067 ;;- Jump to subroutine.
7072 ; untyped call instruction pattern(s).
7075 ;; Call subroutine returning any type.
7076 (define_expand "untyped_call"
7077 [(parallel [(call (match_operand 0 "" "")
7079 (match_operand 1 "" "")
7080 (match_operand 2 "" "")])]
7085 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7087 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7089 rtx set = XVECEXP (operands[2], 0, i);
7090 emit_move_insn (SET_DEST (set), SET_SRC (set));
7093 /* The optimizer does not know that the call sets the function value
7094 registers we stored in the result block. We avoid problems by
7095 claiming that all hard registers are used and clobbered at this
7097 emit_insn (gen_blockage ());
7102 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7103 ;; all of memory. This blocks insns from being moved across this point.
7105 (define_insn "blockage"
7106 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7109 [(set_attr "type" "none")
7110 (set_attr "length" "0")])
7116 (define_expand "sibcall"
7117 [(call (match_operand 0 "" "")
7118 (match_operand 1 "" ""))]
7121 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7125 (define_insn "*sibcall_br"
7126 [(call (mem:QI (reg SIBCALL_REGNUM))
7127 (match_operand 0 "const_int_operand" "n"))]
7128 "SIBLING_CALL_P (insn)
7129 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7131 [(set_attr "op_type" "RR")
7132 (set_attr "type" "branch")
7133 (set_attr "atype" "agen")])
7135 (define_insn "*sibcall_brc"
7136 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7137 (match_operand 1 "const_int_operand" "n"))]
7138 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7140 [(set_attr "op_type" "RI")
7141 (set_attr "type" "branch")])
7143 (define_insn "*sibcall_brcl"
7144 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7145 (match_operand 1 "const_int_operand" "n"))]
7146 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7148 [(set_attr "op_type" "RIL")
7149 (set_attr "type" "branch")])
7152 ; sibcall_value patterns
7155 (define_expand "sibcall_value"
7156 [(set (match_operand 0 "" "")
7157 (call (match_operand 1 "" "")
7158 (match_operand 2 "" "")))]
7161 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7165 (define_insn "*sibcall_value_br"
7166 [(set (match_operand 0 "" "")
7167 (call (mem:QI (reg SIBCALL_REGNUM))
7168 (match_operand 1 "const_int_operand" "n")))]
7169 "SIBLING_CALL_P (insn)
7170 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7172 [(set_attr "op_type" "RR")
7173 (set_attr "type" "branch")
7174 (set_attr "atype" "agen")])
7176 (define_insn "*sibcall_value_brc"
7177 [(set (match_operand 0 "" "")
7178 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7179 (match_operand 2 "const_int_operand" "n")))]
7180 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7182 [(set_attr "op_type" "RI")
7183 (set_attr "type" "branch")])
7185 (define_insn "*sibcall_value_brcl"
7186 [(set (match_operand 0 "" "")
7187 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7188 (match_operand 2 "const_int_operand" "n")))]
7189 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7191 [(set_attr "op_type" "RIL")
7192 (set_attr "type" "branch")])
7196 ; call instruction pattern(s).
7199 (define_expand "call"
7200 [(call (match_operand 0 "" "")
7201 (match_operand 1 "" ""))
7202 (use (match_operand 2 "" ""))]
7205 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7206 gen_rtx_REG (Pmode, RETURN_REGNUM));
7210 (define_insn "*bras"
7211 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7212 (match_operand 1 "const_int_operand" "n"))
7213 (clobber (match_operand 2 "register_operand" "=r"))]
7214 "!SIBLING_CALL_P (insn)
7215 && TARGET_SMALL_EXEC
7216 && GET_MODE (operands[2]) == Pmode"
7218 [(set_attr "op_type" "RI")
7219 (set_attr "type" "jsr")])
7221 (define_insn "*brasl"
7222 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7223 (match_operand 1 "const_int_operand" "n"))
7224 (clobber (match_operand 2 "register_operand" "=r"))]
7225 "!SIBLING_CALL_P (insn)
7227 && GET_MODE (operands[2]) == Pmode"
7229 [(set_attr "op_type" "RIL")
7230 (set_attr "type" "jsr")])
7232 (define_insn "*basr"
7233 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7234 (match_operand 1 "const_int_operand" "n"))
7235 (clobber (match_operand 2 "register_operand" "=r"))]
7236 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7238 if (get_attr_op_type (insn) == OP_TYPE_RR)
7239 return "basr\t%2,%0";
7241 return "bas\t%2,%a0";
7243 [(set (attr "op_type")
7244 (if_then_else (match_operand 0 "register_operand" "")
7245 (const_string "RR") (const_string "RX")))
7246 (set_attr "type" "jsr")
7247 (set_attr "atype" "agen")])
7250 ; call_value instruction pattern(s).
7253 (define_expand "call_value"
7254 [(set (match_operand 0 "" "")
7255 (call (match_operand 1 "" "")
7256 (match_operand 2 "" "")))
7257 (use (match_operand 3 "" ""))]
7260 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7261 gen_rtx_REG (Pmode, RETURN_REGNUM));
7265 (define_insn "*bras_r"
7266 [(set (match_operand 0 "" "")
7267 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7268 (match_operand:SI 2 "const_int_operand" "n")))
7269 (clobber (match_operand 3 "register_operand" "=r"))]
7270 "!SIBLING_CALL_P (insn)
7271 && TARGET_SMALL_EXEC
7272 && GET_MODE (operands[3]) == Pmode"
7274 [(set_attr "op_type" "RI")
7275 (set_attr "type" "jsr")])
7277 (define_insn "*brasl_r"
7278 [(set (match_operand 0 "" "")
7279 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7280 (match_operand 2 "const_int_operand" "n")))
7281 (clobber (match_operand 3 "register_operand" "=r"))]
7282 "!SIBLING_CALL_P (insn)
7284 && GET_MODE (operands[3]) == Pmode"
7286 [(set_attr "op_type" "RIL")
7287 (set_attr "type" "jsr")])
7289 (define_insn "*basr_r"
7290 [(set (match_operand 0 "" "")
7291 (call (mem:QI (match_operand 1 "address_operand" "U"))
7292 (match_operand 2 "const_int_operand" "n")))
7293 (clobber (match_operand 3 "register_operand" "=r"))]
7294 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7296 if (get_attr_op_type (insn) == OP_TYPE_RR)
7297 return "basr\t%3,%1";
7299 return "bas\t%3,%a1";
7301 [(set (attr "op_type")
7302 (if_then_else (match_operand 1 "register_operand" "")
7303 (const_string "RR") (const_string "RX")))
7304 (set_attr "type" "jsr")
7305 (set_attr "atype" "agen")])
7308 ;;- Thread-local storage support.
7311 (define_expand "get_tp_64"
7312 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7316 (define_expand "get_tp_31"
7317 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7321 (define_expand "set_tp_64"
7322 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7323 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7327 (define_expand "set_tp_31"
7328 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7329 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7333 (define_insn "*set_tp"
7334 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7337 [(set_attr "type" "none")
7338 (set_attr "length" "0")])
7340 (define_insn "*tls_load_64"
7341 [(set (match_operand:DI 0 "register_operand" "=d")
7342 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7343 (match_operand:DI 2 "" "")]
7347 [(set_attr "op_type" "RXE")])
7349 (define_insn "*tls_load_31"
7350 [(set (match_operand:SI 0 "register_operand" "=d,d")
7351 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7352 (match_operand:SI 2 "" "")]
7358 [(set_attr "op_type" "RX,RXY")])
7360 (define_insn "*bras_tls"
7361 [(set (match_operand 0 "" "")
7362 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7363 (match_operand 2 "const_int_operand" "n")))
7364 (clobber (match_operand 3 "register_operand" "=r"))
7365 (use (match_operand 4 "" ""))]
7366 "!SIBLING_CALL_P (insn)
7367 && TARGET_SMALL_EXEC
7368 && GET_MODE (operands[3]) == Pmode"
7370 [(set_attr "op_type" "RI")
7371 (set_attr "type" "jsr")])
7373 (define_insn "*brasl_tls"
7374 [(set (match_operand 0 "" "")
7375 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7376 (match_operand 2 "const_int_operand" "n")))
7377 (clobber (match_operand 3 "register_operand" "=r"))
7378 (use (match_operand 4 "" ""))]
7379 "!SIBLING_CALL_P (insn)
7381 && GET_MODE (operands[3]) == Pmode"
7383 [(set_attr "op_type" "RIL")
7384 (set_attr "type" "jsr")])
7386 (define_insn "*basr_tls"
7387 [(set (match_operand 0 "" "")
7388 (call (mem:QI (match_operand 1 "address_operand" "U"))
7389 (match_operand 2 "const_int_operand" "n")))
7390 (clobber (match_operand 3 "register_operand" "=r"))
7391 (use (match_operand 4 "" ""))]
7392 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7394 if (get_attr_op_type (insn) == OP_TYPE_RR)
7395 return "basr\t%3,%1%J4";
7397 return "bas\t%3,%a1%J4";
7399 [(set (attr "op_type")
7400 (if_then_else (match_operand 1 "register_operand" "")
7401 (const_string "RR") (const_string "RX")))
7402 (set_attr "type" "jsr")
7403 (set_attr "atype" "agen")])
7406 ;;- Atomic operations
7410 ; memory barrier pattern.
7413 (define_expand "memory_barrier"
7414 [(set (mem:BLK (match_dup 0))
7415 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7418 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7419 MEM_VOLATILE_P (operands[0]) = 1;
7422 (define_insn "*memory_barrier"
7423 [(set (match_operand:BLK 0 "" "")
7424 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7427 [(set_attr "op_type" "RR")])
7430 ; compare and swap patterns.
7433 (define_expand "sync_compare_and_swap<mode>"
7435 [(set (match_operand:TDSI 0 "register_operand" "")
7436 (match_operand:TDSI 1 "memory_operand" ""))
7438 (unspec_volatile:TDSI
7440 (match_operand:TDSI 2 "register_operand" "")
7441 (match_operand:TDSI 3 "register_operand" "")]
7443 (set (reg:CCZ1 CC_REGNUM)
7444 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7447 (define_expand "sync_compare_and_swap<mode>"
7449 [(set (match_operand:HQI 0 "register_operand" "")
7450 (match_operand:HQI 1 "memory_operand" ""))
7452 (unspec_volatile:HQI
7454 (match_operand:HQI 2 "general_operand" "")
7455 (match_operand:HQI 3 "general_operand" "")]
7457 (set (reg:CCZ1 CC_REGNUM)
7458 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7460 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7461 operands[2], operands[3]); DONE;")
7463 (define_expand "sync_compare_and_swap_cc<mode>"
7465 [(set (match_operand:TDSI 0 "register_operand" "")
7466 (match_operand:TDSI 1 "memory_operand" ""))
7468 (unspec_volatile:TDSI
7470 (match_operand:TDSI 2 "register_operand" "")
7471 (match_operand:TDSI 3 "register_operand" "")]
7474 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7477 /* Emulate compare. */
7478 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7479 s390_compare_op0 = operands[1];
7480 s390_compare_op1 = operands[2];
7481 s390_compare_emitted = operands[4];
7484 (define_insn "*sync_compare_and_swap<mode>"
7485 [(set (match_operand:DP 0 "register_operand" "=r")
7486 (match_operand:DP 1 "memory_operand" "+Q"))
7490 (match_operand:DP 2 "register_operand" "0")
7491 (match_operand:DP 3 "register_operand" "r")]
7493 (set (reg:CCZ1 CC_REGNUM)
7494 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7496 "cds<tg>\t%0,%3,%S1"
7497 [(set_attr "op_type" "RS<TE>")
7498 (set_attr "type" "sem")])
7500 (define_insn "*sync_compare_and_swap<mode>"
7501 [(set (match_operand:GPR 0 "register_operand" "=r")
7502 (match_operand:GPR 1 "memory_operand" "+Q"))
7504 (unspec_volatile:GPR
7506 (match_operand:GPR 2 "register_operand" "0")
7507 (match_operand:GPR 3 "register_operand" "r")]
7509 (set (reg:CCZ1 CC_REGNUM)
7510 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7513 [(set_attr "op_type" "RS<E>")
7514 (set_attr "type" "sem")])
7518 ; Other atomic instruction patterns.
7521 (define_expand "sync_lock_test_and_set<mode>"
7522 [(match_operand:HQI 0 "register_operand")
7523 (match_operand:HQI 1 "memory_operand")
7524 (match_operand:HQI 2 "general_operand")]
7526 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7527 operands[2], false); DONE;")
7529 (define_expand "sync_<atomic><mode>"
7530 [(set (match_operand:HQI 0 "memory_operand")
7531 (ATOMIC:HQI (match_dup 0)
7532 (match_operand:HQI 1 "general_operand")))]
7534 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7535 operands[1], false); DONE;")
7537 (define_expand "sync_old_<atomic><mode>"
7538 [(set (match_operand:HQI 0 "register_operand")
7539 (match_operand:HQI 1 "memory_operand"))
7541 (ATOMIC:HQI (match_dup 1)
7542 (match_operand:HQI 2 "general_operand")))]
7544 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7545 operands[2], false); DONE;")
7547 (define_expand "sync_new_<atomic><mode>"
7548 [(set (match_operand:HQI 0 "register_operand")
7549 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7550 (match_operand:HQI 2 "general_operand")))
7551 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7553 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7554 operands[2], true); DONE;")
7557 ;;- Miscellaneous instructions.
7561 ; allocate stack instruction pattern(s).
7564 (define_expand "allocate_stack"
7565 [(match_operand 0 "general_operand" "")
7566 (match_operand 1 "general_operand" "")]
7569 rtx temp = gen_reg_rtx (Pmode);
7571 emit_move_insn (temp, s390_back_chain_rtx ());
7572 anti_adjust_stack (operands[1]);
7573 emit_move_insn (s390_back_chain_rtx (), temp);
7575 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7581 ; setjmp instruction pattern.
7584 (define_expand "builtin_setjmp_receiver"
7585 [(match_operand 0 "" "")]
7588 emit_insn (s390_load_got ());
7589 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7593 ;; These patterns say how to save and restore the stack pointer. We need not
7594 ;; save the stack pointer at function level since we are careful to
7595 ;; preserve the backchain. At block level, we have to restore the backchain
7596 ;; when we restore the stack pointer.
7598 ;; For nonlocal gotos, we must save both the stack pointer and its
7599 ;; backchain and restore both. Note that in the nonlocal case, the
7600 ;; save area is a memory location.
7602 (define_expand "save_stack_function"
7603 [(match_operand 0 "general_operand" "")
7604 (match_operand 1 "general_operand" "")]
7608 (define_expand "restore_stack_function"
7609 [(match_operand 0 "general_operand" "")
7610 (match_operand 1 "general_operand" "")]
7614 (define_expand "restore_stack_block"
7615 [(match_operand 0 "register_operand" "")
7616 (match_operand 1 "register_operand" "")]
7619 rtx temp = gen_reg_rtx (Pmode);
7621 emit_move_insn (temp, s390_back_chain_rtx ());
7622 emit_move_insn (operands[0], operands[1]);
7623 emit_move_insn (s390_back_chain_rtx (), temp);
7628 (define_expand "save_stack_nonlocal"
7629 [(match_operand 0 "memory_operand" "")
7630 (match_operand 1 "register_operand" "")]
7633 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7634 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7636 /* Copy the backchain to the first word, sp to the second and the
7637 literal pool base to the third. */
7639 if (TARGET_BACKCHAIN)
7641 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7642 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7645 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7646 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7651 (define_expand "restore_stack_nonlocal"
7652 [(match_operand 0 "register_operand" "")
7653 (match_operand 1 "memory_operand" "")]
7656 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7657 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7658 rtx temp = NULL_RTX;
7660 /* Restore the backchain from the first word, sp from the second and the
7661 literal pool base from the third. */
7663 if (TARGET_BACKCHAIN)
7664 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7666 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7667 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7670 emit_move_insn (s390_back_chain_rtx (), temp);
7672 emit_insn (gen_rtx_USE (VOIDmode, base));
7676 (define_expand "exception_receiver"
7680 s390_set_has_landing_pad_p (true);
7685 ; nop instruction pattern(s).
7692 [(set_attr "op_type" "RR")])
7696 ; Special literal pool access instruction pattern(s).
7699 (define_insn "*pool_entry"
7700 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7701 UNSPECV_POOL_ENTRY)]
7704 enum machine_mode mode = GET_MODE (PATTERN (insn));
7705 unsigned int align = GET_MODE_BITSIZE (mode);
7706 s390_output_pool_entry (operands[0], mode, align);
7709 [(set (attr "length")
7710 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7712 (define_insn "pool_align"
7713 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7714 UNSPECV_POOL_ALIGN)]
7717 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7719 (define_insn "pool_section_start"
7720 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7723 [(set_attr "length" "0")])
7725 (define_insn "pool_section_end"
7726 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7729 [(set_attr "length" "0")])
7731 (define_insn "main_base_31_small"
7732 [(set (match_operand 0 "register_operand" "=a")
7733 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7734 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7736 [(set_attr "op_type" "RR")
7737 (set_attr "type" "la")])
7739 (define_insn "main_base_31_large"
7740 [(set (match_operand 0 "register_operand" "=a")
7741 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7742 (set (pc) (label_ref (match_operand 2 "" "")))]
7743 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7745 [(set_attr "op_type" "RI")])
7747 (define_insn "main_base_64"
7748 [(set (match_operand 0 "register_operand" "=a")
7749 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7750 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7752 [(set_attr "op_type" "RIL")
7753 (set_attr "type" "larl")])
7755 (define_insn "main_pool"
7756 [(set (match_operand 0 "register_operand" "=a")
7757 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7758 "GET_MODE (operands[0]) == Pmode"
7763 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7764 (const_string "larl") (const_string "la")))])
7766 (define_insn "reload_base_31"
7767 [(set (match_operand 0 "register_operand" "=a")
7768 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7769 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7770 "basr\t%0,0\;la\t%0,%1-.(%0)"
7771 [(set_attr "length" "6")
7772 (set_attr "type" "la")])
7774 (define_insn "reload_base_64"
7775 [(set (match_operand 0 "register_operand" "=a")
7776 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7777 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7779 [(set_attr "op_type" "RIL")
7780 (set_attr "type" "larl")])
7783 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7788 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7791 ;; Insns related to generating the function prologue and epilogue.
7795 (define_expand "prologue"
7796 [(use (const_int 0))]
7798 "s390_emit_prologue (); DONE;")
7800 (define_expand "epilogue"
7801 [(use (const_int 1))]
7803 "s390_emit_epilogue (false); DONE;")
7805 (define_expand "sibcall_epilogue"
7806 [(use (const_int 0))]
7808 "s390_emit_epilogue (true); DONE;")
7810 (define_insn "*return"
7812 (use (match_operand 0 "register_operand" "a"))]
7813 "GET_MODE (operands[0]) == Pmode"
7815 [(set_attr "op_type" "RR")
7816 (set_attr "type" "jsr")
7817 (set_attr "atype" "agen")])
7820 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7821 ;; pointer. This is used for compatibility.
7823 (define_expand "ptr_extend"
7824 [(set (match_operand:DI 0 "register_operand" "=r")
7825 (match_operand:SI 1 "register_operand" "r"))]
7828 emit_insn (gen_anddi3 (operands[0],
7829 gen_lowpart (DImode, operands[1]),
7830 GEN_INT (0x7fffffff)));
7834 ;; Instruction definition to expand eh_return macro to support
7835 ;; swapping in special linkage return addresses.
7837 (define_expand "eh_return"
7838 [(use (match_operand 0 "register_operand" ""))]
7841 s390_emit_tpf_eh_return (operands[0]);
7846 ; Stack Protector Patterns
7849 (define_expand "stack_protect_set"
7850 [(set (match_operand 0 "memory_operand" "")
7851 (match_operand 1 "memory_operand" ""))]
7854 #ifdef TARGET_THREAD_SSP_OFFSET
7856 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7857 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7860 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7862 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7867 (define_insn "stack_protect_set<mode>"
7868 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7869 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7871 "mvc\t%O0(%G0,%R0),%S1"
7872 [(set_attr "op_type" "SS")])
7874 (define_expand "stack_protect_test"
7875 [(set (reg:CC CC_REGNUM)
7876 (compare (match_operand 0 "memory_operand" "")
7877 (match_operand 1 "memory_operand" "")))
7878 (match_operand 2 "" "")]
7881 #ifdef TARGET_THREAD_SSP_OFFSET
7883 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7884 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7886 s390_compare_op0 = operands[0];
7887 s390_compare_op1 = operands[1];
7888 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7891 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7893 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7895 emit_jump_insn (gen_beq (operands[2]));
7900 (define_insn "stack_protect_test<mode>"
7901 [(set (reg:CCZ CC_REGNUM)
7902 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7903 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7905 "clc\t%O0(%G0,%R0),%S1"
7906 [(set_attr "op_type" "SS")])