1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
56 [; Relocation specifiers
66 (UNSPEC_STACK_PROBE 10)
67 (UNSPEC_STACK_ALLOC 11)
69 (UNSPEC_SSE_PROLOGUE_SAVE 13)
74 (UNSPEC_TLS_LD_BASE 17)
76 ; Other random patterns
87 ; For SSE/MMX support:
98 (UNSPEC_NOP 45) ; prevents combiner cleverness
113 [(UNSPECV_BLOCKAGE 0)
114 (UNSPECV_EH_RETURN 13)
122 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
125 ;; In C guard expressions, put expressions which may be compile-time
126 ;; constants first. This allows for better optimization. For
127 ;; example, write "TARGET_64BIT && reload_completed", not
128 ;; "reload_completed && TARGET_64BIT".
131 ;; Processor type. This attribute must exactly match the processor_type
132 ;; enumeration in i386.h.
133 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
134 (const (symbol_ref "ix86_cpu")))
136 ;; A basic instruction type. Refinements due to arguments to be
137 ;; provided in other attributes.
140 alu,alu1,negnot,imov,imovx,lea,
141 incdec,ishift,rotate,imul,idiv,
142 icmp,test,ibr,setcc,icmov,
145 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
146 sselog,sseiadd,sseishft,sseimul,
147 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
148 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
149 (const_string "other"))
151 ;; Main data type used by the insn
153 "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF"
154 (const_string "unknown"))
156 ;; The CPU unit operations uses.
157 (define_attr "unit" "integer,i387,sse,mmx,unknown"
158 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
159 (const_string "i387")
160 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
161 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv")
163 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
164 (const_string "mmx")]
165 (const_string "integer")))
167 ;; The (bounding maximum) length of an instruction immediate.
168 (define_attr "length_immediate" ""
169 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv")
171 (eq_attr "unit" "i387,sse,mmx")
173 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,imul,
175 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
176 (eq_attr "type" "imov,test")
177 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
178 (eq_attr "type" "call")
179 (if_then_else (match_operand 0 "constant_call_address_operand" "")
182 (eq_attr "type" "callv")
183 (if_then_else (match_operand 1 "constant_call_address_operand" "")
186 (eq_attr "type" "ibr")
187 (if_then_else (and (ge (minus (match_dup 0) (pc))
189 (lt (minus (match_dup 0) (pc))
194 (symbol_ref "/* Update immediate_length and other attributes! */
197 ;; The (bounding maximum) length of an instruction address.
198 (define_attr "length_address" ""
199 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
201 (and (eq_attr "type" "call")
202 (match_operand 1 "constant_call_address_operand" ""))
204 (and (eq_attr "type" "callv")
205 (match_operand 1 "constant_call_address_operand" ""))
208 (symbol_ref "ix86_attr_length_address_default (insn)")))
210 ;; Set when length prefix is used.
211 (define_attr "prefix_data16" ""
212 (if_then_else (ior (eq_attr "mode" "HI")
213 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
217 ;; Set when string REP prefix is used.
218 (define_attr "prefix_rep" ""
219 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
223 ;; Set when 0f opcode prefix is used.
224 (define_attr "prefix_0f" ""
228 sselog,sseiadd,sseishft,sseimul,
229 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
230 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
234 ;; Set when modrm byte is used.
235 (define_attr "modrm" ""
236 (cond [(eq_attr "type" "str,cld")
238 (eq_attr "unit" "i387")
240 (and (eq_attr "type" "incdec")
241 (ior (match_operand:SI 1 "register_operand" "")
242 (match_operand:HI 1 "register_operand" "")))
244 (and (eq_attr "type" "push")
245 (not (match_operand 1 "memory_operand" "")))
247 (and (eq_attr "type" "pop")
248 (not (match_operand 0 "memory_operand" "")))
250 (and (eq_attr "type" "imov")
251 (and (match_operand 0 "register_operand" "")
252 (match_operand 1 "immediate_operand" "")))
257 ;; The (bounding maximum) length of an instruction in bytes.
258 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
259 ;; to split it and compute proper length as for other insns.
260 (define_attr "length" ""
261 (cond [(eq_attr "type" "other,multi,fistp")
263 (eq_attr "unit" "i387")
265 (plus (attr "prefix_data16")
266 (attr "length_address")))]
267 (plus (plus (attr "modrm")
268 (plus (attr "prefix_0f")
270 (plus (attr "prefix_rep")
271 (plus (attr "prefix_data16")
272 (plus (attr "length_immediate")
273 (attr "length_address")))))))
275 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
276 ;; `store' if there is a simple memory reference therein, or `unknown'
277 ;; if the instruction is complex.
279 (define_attr "memory" "none,load,store,both,unknown"
280 (cond [(eq_attr "type" "other,multi,str")
281 (const_string "unknown")
282 (eq_attr "type" "lea,fcmov,fpspc,cld")
283 (const_string "none")
284 (eq_attr "type" "fistp")
285 (const_string "both")
286 (eq_attr "type" "push")
287 (if_then_else (match_operand 1 "memory_operand" "")
288 (const_string "both")
289 (const_string "store"))
290 (eq_attr "type" "pop,setcc")
291 (if_then_else (match_operand 0 "memory_operand" "")
292 (const_string "both")
293 (const_string "load"))
294 (eq_attr "type" "icmp,test,ssecmp,mmxcmp,fcmp")
295 (if_then_else (ior (match_operand 0 "memory_operand" "")
296 (match_operand 1 "memory_operand" ""))
297 (const_string "load")
298 (const_string "none"))
299 (eq_attr "type" "ibr")
300 (if_then_else (match_operand 0 "memory_operand" "")
301 (const_string "load")
302 (const_string "none"))
303 (eq_attr "type" "call")
304 (if_then_else (match_operand 0 "constant_call_address_operand" "")
305 (const_string "none")
306 (const_string "load"))
307 (eq_attr "type" "callv")
308 (if_then_else (match_operand 1 "constant_call_address_operand" "")
309 (const_string "none")
310 (const_string "load"))
311 (and (eq_attr "type" "alu1,negnot")
312 (match_operand 1 "memory_operand" ""))
313 (const_string "both")
314 (and (match_operand 0 "memory_operand" "")
315 (match_operand 1 "memory_operand" ""))
316 (const_string "both")
317 (match_operand 0 "memory_operand" "")
318 (const_string "store")
319 (match_operand 1 "memory_operand" "")
320 (const_string "load")
323 imov,imovx,icmp,test,
325 sse,ssemov,ssecmp,ssecvt,
326 mmx,mmxmov,mmxcmp,mmxcvt")
327 (match_operand 2 "memory_operand" ""))
328 (const_string "load")
329 (and (eq_attr "type" "icmov")
330 (match_operand 3 "memory_operand" ""))
331 (const_string "load")
333 (const_string "none")))
335 ;; Indicates if an instruction has both an immediate and a displacement.
337 (define_attr "imm_disp" "false,true,unknown"
338 (cond [(eq_attr "type" "other,multi")
339 (const_string "unknown")
340 (and (eq_attr "type" "icmp,test,imov")
341 (and (match_operand 0 "memory_displacement_operand" "")
342 (match_operand 1 "immediate_operand" "")))
343 (const_string "true")
344 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
345 (and (match_operand 0 "memory_displacement_operand" "")
346 (match_operand 2 "immediate_operand" "")))
347 (const_string "true")
349 (const_string "false")))
351 ;; Indicates if an FP operation has an integer source.
353 (define_attr "fp_int_src" "false,true"
354 (const_string "false"))
356 ;; Describe a user's asm statement.
357 (define_asm_attributes
358 [(set_attr "length" "128")
359 (set_attr "type" "multi")])
361 (include "pentium.md")
364 (include "athlon.md")
366 ;; Compare instructions.
368 ;; All compare insns have expanders that save the operands away without
369 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
370 ;; after the cmp) will actually emit the cmpM.
372 (define_expand "cmpdi"
374 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
375 (match_operand:DI 1 "x86_64_general_operand" "")))]
378 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
379 operands[0] = force_reg (DImode, operands[0]);
380 ix86_compare_op0 = operands[0];
381 ix86_compare_op1 = operands[1];
385 (define_expand "cmpsi"
387 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
388 (match_operand:SI 1 "general_operand" "")))]
391 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
392 operands[0] = force_reg (SImode, operands[0]);
393 ix86_compare_op0 = operands[0];
394 ix86_compare_op1 = operands[1];
398 (define_expand "cmphi"
400 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
401 (match_operand:HI 1 "general_operand" "")))]
404 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
405 operands[0] = force_reg (HImode, operands[0]);
406 ix86_compare_op0 = operands[0];
407 ix86_compare_op1 = operands[1];
411 (define_expand "cmpqi"
413 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
414 (match_operand:QI 1 "general_operand" "")))]
417 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
418 operands[0] = force_reg (QImode, operands[0]);
419 ix86_compare_op0 = operands[0];
420 ix86_compare_op1 = operands[1];
424 (define_insn "cmpdi_ccno_1_rex64"
426 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
427 (match_operand:DI 1 "const0_operand" "n,n")))]
428 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
430 test{q}\t{%0, %0|%0, %0}
431 cmp{q}\t{%1, %0|%0, %1}"
432 [(set_attr "type" "test,icmp")
433 (set_attr "length_immediate" "0,1")
434 (set_attr "mode" "DI")])
436 (define_insn "*cmpdi_minus_1_rex64"
438 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
439 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
441 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
442 "cmp{q}\t{%1, %0|%0, %1}"
443 [(set_attr "type" "icmp")
444 (set_attr "mode" "DI")])
446 (define_expand "cmpdi_1_rex64"
448 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
449 (match_operand:DI 1 "general_operand" "")))]
453 (define_insn "cmpdi_1_insn_rex64"
455 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
456 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
457 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
458 "cmp{q}\t{%1, %0|%0, %1}"
459 [(set_attr "type" "icmp")
460 (set_attr "mode" "DI")])
463 (define_insn "*cmpsi_ccno_1"
465 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
466 (match_operand:SI 1 "const0_operand" "n,n")))]
467 "ix86_match_ccmode (insn, CCNOmode)"
469 test{l}\t{%0, %0|%0, %0}
470 cmp{l}\t{%1, %0|%0, %1}"
471 [(set_attr "type" "test,icmp")
472 (set_attr "length_immediate" "0,1")
473 (set_attr "mode" "SI")])
475 (define_insn "*cmpsi_minus_1"
477 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
478 (match_operand:SI 1 "general_operand" "ri,mr"))
480 "ix86_match_ccmode (insn, CCGOCmode)"
481 "cmp{l}\t{%1, %0|%0, %1}"
482 [(set_attr "type" "icmp")
483 (set_attr "mode" "SI")])
485 (define_expand "cmpsi_1"
487 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
488 (match_operand:SI 1 "general_operand" "ri,mr")))]
492 (define_insn "*cmpsi_1_insn"
494 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
495 (match_operand:SI 1 "general_operand" "ri,mr")))]
496 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
497 && ix86_match_ccmode (insn, CCmode)"
498 "cmp{l}\t{%1, %0|%0, %1}"
499 [(set_attr "type" "icmp")
500 (set_attr "mode" "SI")])
502 (define_insn "*cmphi_ccno_1"
504 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
505 (match_operand:HI 1 "const0_operand" "n,n")))]
506 "ix86_match_ccmode (insn, CCNOmode)"
508 test{w}\t{%0, %0|%0, %0}
509 cmp{w}\t{%1, %0|%0, %1}"
510 [(set_attr "type" "test,icmp")
511 (set_attr "length_immediate" "0,1")
512 (set_attr "mode" "HI")])
514 (define_insn "*cmphi_minus_1"
516 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
517 (match_operand:HI 1 "general_operand" "ri,mr"))
519 "ix86_match_ccmode (insn, CCGOCmode)"
520 "cmp{w}\t{%1, %0|%0, %1}"
521 [(set_attr "type" "icmp")
522 (set_attr "mode" "HI")])
524 (define_insn "*cmphi_1"
526 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
527 (match_operand:HI 1 "general_operand" "ri,mr")))]
528 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
529 && ix86_match_ccmode (insn, CCmode)"
530 "cmp{w}\t{%1, %0|%0, %1}"
531 [(set_attr "type" "icmp")
532 (set_attr "mode" "HI")])
534 (define_insn "*cmpqi_ccno_1"
536 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
537 (match_operand:QI 1 "const0_operand" "n,n")))]
538 "ix86_match_ccmode (insn, CCNOmode)"
540 test{b}\t{%0, %0|%0, %0}
541 cmp{b}\t{$0, %0|%0, 0}"
542 [(set_attr "type" "test,icmp")
543 (set_attr "length_immediate" "0,1")
544 (set_attr "mode" "QI")])
546 (define_insn "*cmpqi_1"
548 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
549 (match_operand:QI 1 "general_operand" "qi,mq")))]
550 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
551 && ix86_match_ccmode (insn, CCmode)"
552 "cmp{b}\t{%1, %0|%0, %1}"
553 [(set_attr "type" "icmp")
554 (set_attr "mode" "QI")])
556 (define_insn "*cmpqi_minus_1"
558 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
559 (match_operand:QI 1 "general_operand" "qi,mq"))
561 "ix86_match_ccmode (insn, CCGOCmode)"
562 "cmp{b}\t{%1, %0|%0, %1}"
563 [(set_attr "type" "icmp")
564 (set_attr "mode" "QI")])
566 (define_insn "*cmpqi_ext_1"
569 (match_operand:QI 0 "general_operand" "Qm")
572 (match_operand 1 "ext_register_operand" "Q")
575 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
576 "cmp{b}\t{%h1, %0|%0, %h1}"
577 [(set_attr "type" "icmp")
578 (set_attr "mode" "QI")])
580 (define_insn "*cmpqi_ext_1_rex64"
583 (match_operand:QI 0 "register_operand" "Q")
586 (match_operand 1 "ext_register_operand" "Q")
589 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
590 "cmp{b}\t{%h1, %0|%0, %h1}"
591 [(set_attr "type" "icmp")
592 (set_attr "mode" "QI")])
594 (define_insn "*cmpqi_ext_2"
599 (match_operand 0 "ext_register_operand" "Q")
602 (match_operand:QI 1 "const0_operand" "n")))]
603 "ix86_match_ccmode (insn, CCNOmode)"
605 [(set_attr "type" "test")
606 (set_attr "length_immediate" "0")
607 (set_attr "mode" "QI")])
609 (define_expand "cmpqi_ext_3"
614 (match_operand 0 "ext_register_operand" "")
617 (match_operand:QI 1 "general_operand" "")))]
621 (define_insn "cmpqi_ext_3_insn"
626 (match_operand 0 "ext_register_operand" "Q")
629 (match_operand:QI 1 "general_operand" "Qmn")))]
630 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
631 "cmp{b}\t{%1, %h0|%h0, %1}"
632 [(set_attr "type" "icmp")
633 (set_attr "mode" "QI")])
635 (define_insn "cmpqi_ext_3_insn_rex64"
640 (match_operand 0 "ext_register_operand" "Q")
643 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
644 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
645 "cmp{b}\t{%1, %h0|%h0, %1}"
646 [(set_attr "type" "icmp")
647 (set_attr "mode" "QI")])
649 (define_insn "*cmpqi_ext_4"
654 (match_operand 0 "ext_register_operand" "Q")
659 (match_operand 1 "ext_register_operand" "Q")
662 "ix86_match_ccmode (insn, CCmode)"
663 "cmp{b}\t{%h1, %h0|%h0, %h1}"
664 [(set_attr "type" "icmp")
665 (set_attr "mode" "QI")])
667 ;; These implement float point compares.
668 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
669 ;; which would allow mix and match FP modes on the compares. Which is what
670 ;; the old patterns did, but with many more of them.
672 (define_expand "cmpxf"
674 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
675 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
676 "!TARGET_64BIT && TARGET_80387"
678 ix86_compare_op0 = operands[0];
679 ix86_compare_op1 = operands[1];
683 (define_expand "cmptf"
685 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
686 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
689 ix86_compare_op0 = operands[0];
690 ix86_compare_op1 = operands[1];
694 (define_expand "cmpdf"
696 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
697 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
698 "TARGET_80387 || TARGET_SSE2"
700 ix86_compare_op0 = operands[0];
701 ix86_compare_op1 = operands[1];
705 (define_expand "cmpsf"
707 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
708 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
709 "TARGET_80387 || TARGET_SSE"
711 ix86_compare_op0 = operands[0];
712 ix86_compare_op1 = operands[1];
716 ;; FP compares, step 1:
717 ;; Set the FP condition codes.
719 ;; CCFPmode compare with exceptions
720 ;; CCFPUmode compare with no exceptions
722 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
723 ;; and that fp moves clobber the condition codes, and that there is
724 ;; currently no way to describe this fact to reg-stack. So there are
725 ;; no splitters yet for this.
727 ;; %%% YIKES! This scheme does not retain a strong connection between
728 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
729 ;; work! Only allow tos/mem with tos in op 0.
731 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
732 ;; things aren't as bad as they sound...
734 (define_insn "*cmpfp_0"
735 [(set (match_operand:HI 0 "register_operand" "=a")
737 [(compare:CCFP (match_operand 1 "register_operand" "f")
738 (match_operand 2 "const0_operand" "X"))]
741 && FLOAT_MODE_P (GET_MODE (operands[1]))
742 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
744 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
745 return "ftst\;fnstsw\t%0\;fstp\t%y0";
747 return "ftst\;fnstsw\t%0";
749 [(set_attr "type" "multi")
750 (set_attr "mode" "unknownfp")])
752 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
753 ;; used to manage the reg stack popping would not be preserved.
755 (define_insn "*cmpfp_2_sf"
758 (match_operand:SF 0 "register_operand" "f")
759 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
761 "* return output_fp_compare (insn, operands, 0, 0);"
762 [(set_attr "type" "fcmp")
763 (set_attr "mode" "SF")])
765 (define_insn "*cmpfp_2_sf_1"
766 [(set (match_operand:HI 0 "register_operand" "=a")
769 (match_operand:SF 1 "register_operand" "f")
770 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
773 "* return output_fp_compare (insn, operands, 2, 0);"
774 [(set_attr "type" "fcmp")
775 (set_attr "mode" "SF")])
777 (define_insn "*cmpfp_2_df"
780 (match_operand:DF 0 "register_operand" "f")
781 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
783 "* return output_fp_compare (insn, operands, 0, 0);"
784 [(set_attr "type" "fcmp")
785 (set_attr "mode" "DF")])
787 (define_insn "*cmpfp_2_df_1"
788 [(set (match_operand:HI 0 "register_operand" "=a")
791 (match_operand:DF 1 "register_operand" "f")
792 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
795 "* return output_fp_compare (insn, operands, 2, 0);"
796 [(set_attr "type" "multi")
797 (set_attr "mode" "DF")])
799 (define_insn "*cmpfp_2_xf"
802 (match_operand:XF 0 "register_operand" "f")
803 (match_operand:XF 1 "register_operand" "f")))]
804 "!TARGET_64BIT && TARGET_80387"
805 "* return output_fp_compare (insn, operands, 0, 0);"
806 [(set_attr "type" "fcmp")
807 (set_attr "mode" "XF")])
809 (define_insn "*cmpfp_2_tf"
812 (match_operand:TF 0 "register_operand" "f")
813 (match_operand:TF 1 "register_operand" "f")))]
815 "* return output_fp_compare (insn, operands, 0, 0);"
816 [(set_attr "type" "fcmp")
817 (set_attr "mode" "XF")])
819 (define_insn "*cmpfp_2_xf_1"
820 [(set (match_operand:HI 0 "register_operand" "=a")
823 (match_operand:XF 1 "register_operand" "f")
824 (match_operand:XF 2 "register_operand" "f"))]
826 "!TARGET_64BIT && TARGET_80387"
827 "* return output_fp_compare (insn, operands, 2, 0);"
828 [(set_attr "type" "multi")
829 (set_attr "mode" "XF")])
831 (define_insn "*cmpfp_2_tf_1"
832 [(set (match_operand:HI 0 "register_operand" "=a")
835 (match_operand:TF 1 "register_operand" "f")
836 (match_operand:TF 2 "register_operand" "f"))]
839 "* return output_fp_compare (insn, operands, 2, 0);"
840 [(set_attr "type" "multi")
841 (set_attr "mode" "XF")])
843 (define_insn "*cmpfp_2u"
846 (match_operand 0 "register_operand" "f")
847 (match_operand 1 "register_operand" "f")))]
849 && FLOAT_MODE_P (GET_MODE (operands[0]))
850 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
851 "* return output_fp_compare (insn, operands, 0, 1);"
852 [(set_attr "type" "fcmp")
853 (set_attr "mode" "unknownfp")])
855 (define_insn "*cmpfp_2u_1"
856 [(set (match_operand:HI 0 "register_operand" "=a")
859 (match_operand 1 "register_operand" "f")
860 (match_operand 2 "register_operand" "f"))]
863 && FLOAT_MODE_P (GET_MODE (operands[1]))
864 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
865 "* return output_fp_compare (insn, operands, 2, 1);"
866 [(set_attr "type" "multi")
867 (set_attr "mode" "unknownfp")])
869 ;; Patterns to match the SImode-in-memory ficom instructions.
871 ;; %%% Play games with accepting gp registers, as otherwise we have to
872 ;; force them to memory during rtl generation, which is no good. We
873 ;; can get rid of this once we teach reload to do memory input reloads
876 (define_insn "*ficom_1"
879 (match_operand 0 "register_operand" "f,f")
880 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
881 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
882 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
885 ;; Split the not-really-implemented gp register case into a
886 ;; push-op-pop sequence.
888 ;; %%% This is most efficient, but am I gonna get in trouble
889 ;; for separating cc0_setter and cc0_user?
894 (match_operand:SF 0 "register_operand" "")
895 (float (match_operand:SI 1 "register_operand" ""))))]
896 "0 && TARGET_80387 && reload_completed"
897 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
898 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
899 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
900 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
901 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
902 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
904 ;; FP compares, step 2
905 ;; Move the fpsw to ax.
907 (define_insn "x86_fnstsw_1"
908 [(set (match_operand:HI 0 "register_operand" "=a")
909 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
912 [(set_attr "length" "2")
913 (set_attr "mode" "SI")
914 (set_attr "unit" "i387")
915 (set_attr "ppro_uops" "few")])
917 ;; FP compares, step 3
918 ;; Get ax into flags, general case.
920 (define_insn "x86_sahf_1"
922 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
925 [(set_attr "length" "1")
926 (set_attr "athlon_decode" "vector")
927 (set_attr "mode" "SI")
928 (set_attr "ppro_uops" "one")])
930 ;; Pentium Pro can do steps 1 through 3 in one go.
932 (define_insn "*cmpfp_i"
934 (compare:CCFP (match_operand 0 "register_operand" "f")
935 (match_operand 1 "register_operand" "f")))]
936 "TARGET_80387 && TARGET_CMOVE
937 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
938 && FLOAT_MODE_P (GET_MODE (operands[0]))
939 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
940 "* return output_fp_compare (insn, operands, 1, 0);"
941 [(set_attr "type" "fcmp")
942 (set_attr "mode" "unknownfp")
943 (set_attr "athlon_decode" "vector")])
945 (define_insn "*cmpfp_i_sse"
947 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
948 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
950 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
951 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
952 "* return output_fp_compare (insn, operands, 1, 0);"
953 [(set_attr "type" "fcmp,ssecmp")
954 (set_attr "mode" "unknownfp")
955 (set_attr "athlon_decode" "vector")])
957 (define_insn "*cmpfp_i_sse_only"
959 (compare:CCFP (match_operand 0 "register_operand" "x")
960 (match_operand 1 "nonimmediate_operand" "xm")))]
961 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
962 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
963 "* return output_fp_compare (insn, operands, 1, 0);"
964 [(set_attr "type" "ssecmp")
965 (set_attr "mode" "unknownfp")
966 (set_attr "athlon_decode" "vector")])
968 (define_insn "*cmpfp_iu"
970 (compare:CCFPU (match_operand 0 "register_operand" "f")
971 (match_operand 1 "register_operand" "f")))]
972 "TARGET_80387 && TARGET_CMOVE
973 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
974 && FLOAT_MODE_P (GET_MODE (operands[0]))
975 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
976 "* return output_fp_compare (insn, operands, 1, 1);"
977 [(set_attr "type" "fcmp")
978 (set_attr "mode" "unknownfp")
979 (set_attr "athlon_decode" "vector")])
981 (define_insn "*cmpfp_iu_sse"
983 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
984 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
986 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
987 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
988 "* return output_fp_compare (insn, operands, 1, 1);"
989 [(set_attr "type" "fcmp,ssecmp")
990 (set_attr "mode" "unknownfp")
991 (set_attr "athlon_decode" "vector")])
993 (define_insn "*cmpfp_iu_sse_only"
995 (compare:CCFPU (match_operand 0 "register_operand" "x")
996 (match_operand 1 "nonimmediate_operand" "xm")))]
997 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
998 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
999 "* return output_fp_compare (insn, operands, 1, 1);"
1000 [(set_attr "type" "ssecmp")
1001 (set_attr "mode" "unknownfp")
1002 (set_attr "athlon_decode" "vector")])
1004 ;; Move instructions.
1006 ;; General case of fullword move.
1008 (define_expand "movsi"
1009 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1010 (match_operand:SI 1 "general_operand" ""))]
1012 "ix86_expand_move (SImode, operands); DONE;")
1014 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1017 ;; %%% We don't use a post-inc memory reference because x86 is not a
1018 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1019 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1020 ;; targets without our curiosities, and it is just as easy to represent
1021 ;; this differently.
1023 (define_insn "*pushsi2"
1024 [(set (match_operand:SI 0 "push_operand" "=<")
1025 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1028 [(set_attr "type" "push")
1029 (set_attr "mode" "SI")])
1031 ;; For 64BIT abi we always round up to 8 bytes.
1032 (define_insn "*pushsi2_rex64"
1033 [(set (match_operand:SI 0 "push_operand" "=X")
1034 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1037 [(set_attr "type" "push")
1038 (set_attr "mode" "SI")])
1040 (define_insn "*pushsi2_prologue"
1041 [(set (match_operand:SI 0 "push_operand" "=<")
1042 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1043 (clobber (mem:BLK (scratch)))]
1046 [(set_attr "type" "push")
1047 (set_attr "mode" "SI")])
1049 (define_insn "*popsi1_epilogue"
1050 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1051 (mem:SI (reg:SI 7)))
1053 (plus:SI (reg:SI 7) (const_int 4)))
1054 (clobber (mem:BLK (scratch)))]
1057 [(set_attr "type" "pop")
1058 (set_attr "mode" "SI")])
1060 (define_insn "popsi1"
1061 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1062 (mem:SI (reg:SI 7)))
1064 (plus:SI (reg:SI 7) (const_int 4)))]
1067 [(set_attr "type" "pop")
1068 (set_attr "mode" "SI")])
1070 (define_insn "*movsi_xor"
1071 [(set (match_operand:SI 0 "register_operand" "=r")
1072 (match_operand:SI 1 "const0_operand" "i"))
1073 (clobber (reg:CC 17))]
1074 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1075 "xor{l}\t{%0, %0|%0, %0}"
1076 [(set_attr "type" "alu1")
1077 (set_attr "mode" "SI")
1078 (set_attr "length_immediate" "0")])
1080 (define_insn "*movsi_or"
1081 [(set (match_operand:SI 0 "register_operand" "=r")
1082 (match_operand:SI 1 "immediate_operand" "i"))
1083 (clobber (reg:CC 17))]
1084 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1085 && INTVAL (operands[1]) == -1
1086 && (TARGET_PENTIUM || optimize_size)"
1088 operands[1] = constm1_rtx;
1089 return "or{l}\t{%1, %0|%0, %1}";
1091 [(set_attr "type" "alu1")
1092 (set_attr "mode" "SI")
1093 (set_attr "length_immediate" "1")])
1095 ; The first alternative is used only to compute proper length of instruction.
1096 ; Reload's algorithm does not take into account the cost of spill instructions
1097 ; needed to free register in given class, so avoid it from choosing the first
1098 ; alternative when eax is not available.
1100 (define_insn "*movsi_1"
1101 [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1102 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1103 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1105 switch (get_attr_type (insn))
1108 if (get_attr_mode (insn) == TImode)
1109 return "movdqa\t{%1, %0|%0, %1}";
1110 return "movd\t{%1, %0|%0, %1}";
1113 if (get_attr_mode (insn) == DImode)
1114 return "movq\t{%1, %0|%0, %1}";
1115 return "movd\t{%1, %0|%0, %1}";
1118 return "lea{l}\t{%1, %0|%0, %1}";
1121 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1123 return "mov{l}\t{%1, %0|%0, %1}";
1127 (cond [(eq_attr "alternative" "4,5,6")
1128 (const_string "mmxmov")
1129 (eq_attr "alternative" "7,8,9")
1130 (const_string "ssemov")
1131 (and (ne (symbol_ref "flag_pic") (const_int 0))
1132 (match_operand:SI 1 "symbolic_operand" ""))
1133 (const_string "lea")
1135 (const_string "imov")))
1136 (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
1137 (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1139 ;; Stores and loads of ax to arbitary constant address.
1140 ;; We fake an second form of instruction to force reload to load address
1141 ;; into register when rax is not available
1142 (define_insn "*movabssi_1_rex64"
1143 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1144 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1147 movabs{l}\t{%1, %P0|%P0, %1}
1148 mov{l}\t{%1, %a0|%a0, %1}
1149 movabs{l}\t{%1, %a0|%a0, %1}"
1150 [(set_attr "type" "imov")
1151 (set_attr "modrm" "0,*,*")
1152 (set_attr "length_address" "8,0,0")
1153 (set_attr "length_immediate" "0,*,*")
1154 (set_attr "memory" "store")
1155 (set_attr "mode" "SI")])
1157 (define_insn "*movabssi_2_rex64"
1158 [(set (match_operand:SI 0 "register_operand" "=a,r")
1159 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1162 movabs{l}\t{%P1, %0|%0, %P1}
1163 mov{l}\t{%a1, %0|%0, %a1}"
1164 [(set_attr "type" "imov")
1165 (set_attr "modrm" "0,*")
1166 (set_attr "length_address" "8,0")
1167 (set_attr "length_immediate" "0")
1168 (set_attr "memory" "load")
1169 (set_attr "mode" "SI")])
1171 (define_insn "*swapsi"
1172 [(set (match_operand:SI 0 "register_operand" "+r")
1173 (match_operand:SI 1 "register_operand" "+r"))
1178 [(set_attr "type" "imov")
1179 (set_attr "pent_pair" "np")
1180 (set_attr "athlon_decode" "vector")
1181 (set_attr "mode" "SI")
1182 (set_attr "modrm" "0")
1183 (set_attr "ppro_uops" "few")])
1185 (define_expand "movhi"
1186 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1187 (match_operand:HI 1 "general_operand" ""))]
1189 "ix86_expand_move (HImode, operands); DONE;")
1191 (define_insn "*pushhi2"
1192 [(set (match_operand:HI 0 "push_operand" "=<,<")
1193 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1196 push{w}\t{|WORD PTR }%1
1198 [(set_attr "type" "push")
1199 (set_attr "mode" "HI")])
1201 ;; For 64BIT abi we always round up to 8 bytes.
1202 (define_insn "*pushhi2_rex64"
1203 [(set (match_operand:HI 0 "push_operand" "=X")
1204 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1207 [(set_attr "type" "push")
1208 (set_attr "mode" "QI")])
1210 ; The first alternative is used only to compute proper length of instruction.
1211 ; Reload's algorithm does not take into account the cost of spill instructions
1212 ; needed to free register in given class, so avoid it from choosing the first
1213 ; alternative when eax is not available.
1215 (define_insn "*movhi_1"
1216 [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
1217 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1218 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1220 switch (get_attr_type (insn))
1223 /* movzwl is faster than movw on p2 due to partial word stalls,
1224 though not as fast as an aligned movl. */
1225 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1227 if (get_attr_mode (insn) == MODE_SI)
1228 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1230 return "mov{w}\t{%1, %0|%0, %1}";
1234 (cond [(and (eq_attr "alternative" "0,1")
1235 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1237 (eq (symbol_ref "TARGET_HIMODE_MATH")
1239 (const_string "imov")
1240 (and (eq_attr "alternative" "2,3,4")
1241 (match_operand:HI 1 "aligned_operand" ""))
1242 (const_string "imov")
1243 (and (ne (symbol_ref "TARGET_MOVX")
1245 (eq_attr "alternative" "0,1,3,4"))
1246 (const_string "imovx")
1248 (const_string "imov")))
1250 (cond [(eq_attr "type" "imovx")
1252 (and (eq_attr "alternative" "2,3,4")
1253 (match_operand:HI 1 "aligned_operand" ""))
1255 (and (eq_attr "alternative" "0,1")
1256 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1258 (eq (symbol_ref "TARGET_HIMODE_MATH")
1262 (const_string "HI")))
1263 (set_attr "modrm" "0,*,*,0,*,*")])
1265 ;; Stores and loads of ax to arbitary constant address.
1266 ;; We fake an second form of instruction to force reload to load address
1267 ;; into register when rax is not available
1268 (define_insn "*movabshi_1_rex64"
1269 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1270 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1273 movabs{w}\t{%1, %P0|%P0, %1}
1274 mov{w}\t{%1, %a0|%a0, %1}
1275 movabs{w}\t{%1, %a0|%a0, %1}"
1276 [(set_attr "type" "imov")
1277 (set_attr "modrm" "0,*,*")
1278 (set_attr "length_address" "8,0,0")
1279 (set_attr "length_immediate" "0,*,*")
1280 (set_attr "memory" "store")
1281 (set_attr "mode" "HI")])
1283 (define_insn "*movabshi_2_rex64"
1284 [(set (match_operand:HI 0 "register_operand" "=a,r")
1285 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1288 movabs{w}\t{%P1, %0|%0, %P1}
1289 mov{w}\t{%a1, %0|%0, %a1}"
1290 [(set_attr "type" "imov")
1291 (set_attr "modrm" "0,*")
1292 (set_attr "length_address" "8,0")
1293 (set_attr "length_immediate" "0")
1294 (set_attr "memory" "load")
1295 (set_attr "mode" "HI")])
1297 (define_insn "*swaphi_1"
1298 [(set (match_operand:HI 0 "register_operand" "+r")
1299 (match_operand:HI 1 "register_operand" "+r"))
1302 "TARGET_PARTIAL_REG_STALL"
1304 [(set_attr "type" "imov")
1305 (set_attr "pent_pair" "np")
1306 (set_attr "mode" "HI")
1307 (set_attr "modrm" "0")
1308 (set_attr "ppro_uops" "few")])
1310 (define_insn "*swaphi_2"
1311 [(set (match_operand:HI 0 "register_operand" "+r")
1312 (match_operand:HI 1 "register_operand" "+r"))
1315 "! TARGET_PARTIAL_REG_STALL"
1317 [(set_attr "type" "imov")
1318 (set_attr "pent_pair" "np")
1319 (set_attr "mode" "SI")
1320 (set_attr "modrm" "0")
1321 (set_attr "ppro_uops" "few")])
1323 (define_expand "movstricthi"
1324 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1325 (match_operand:HI 1 "general_operand" ""))]
1326 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1328 /* Don't generate memory->memory moves, go through a register */
1329 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1330 operands[1] = force_reg (HImode, operands[1]);
1333 (define_insn "*movstricthi_1"
1334 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1335 (match_operand:HI 1 "general_operand" "rn,m"))]
1336 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1337 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1338 "mov{w}\t{%1, %0|%0, %1}"
1339 [(set_attr "type" "imov")
1340 (set_attr "mode" "HI")])
1342 (define_insn "*movstricthi_xor"
1343 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1344 (match_operand:HI 1 "const0_operand" "i"))
1345 (clobber (reg:CC 17))]
1347 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1348 "xor{w}\t{%0, %0|%0, %0}"
1349 [(set_attr "type" "alu1")
1350 (set_attr "mode" "HI")
1351 (set_attr "length_immediate" "0")])
1353 (define_expand "movqi"
1354 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1355 (match_operand:QI 1 "general_operand" ""))]
1357 "ix86_expand_move (QImode, operands); DONE;")
1359 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1360 ;; "push a byte". But actually we use pushw, which has the effect
1361 ;; of rounding the amount pushed up to a halfword.
1363 (define_insn "*pushqi2"
1364 [(set (match_operand:QI 0 "push_operand" "=X,X")
1365 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1368 push{w}\t{|word ptr }%1
1370 [(set_attr "type" "push")
1371 (set_attr "mode" "HI")])
1373 ;; For 64BIT abi we always round up to 8 bytes.
1374 (define_insn "*pushqi2_rex64"
1375 [(set (match_operand:QI 0 "push_operand" "=X")
1376 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1379 [(set_attr "type" "push")
1380 (set_attr "mode" "QI")])
1382 ;; Situation is quite tricky about when to choose full sized (SImode) move
1383 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1384 ;; partial register dependency machines (such as AMD Athlon), where QImode
1385 ;; moves issue extra dependency and for partial register stalls machines
1386 ;; that don't use QImode patterns (and QImode move cause stall on the next
1389 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1390 ;; register stall machines with, where we use QImode instructions, since
1391 ;; partial register stall can be caused there. Then we use movzx.
1392 (define_insn "*movqi_1"
1393 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1394 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1395 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1397 switch (get_attr_type (insn))
1400 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1402 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1404 if (get_attr_mode (insn) == MODE_SI)
1405 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1407 return "mov{b}\t{%1, %0|%0, %1}";
1411 (cond [(and (eq_attr "alternative" "3")
1412 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1414 (eq (symbol_ref "TARGET_QIMODE_MATH")
1416 (const_string "imov")
1417 (eq_attr "alternative" "3,5")
1418 (const_string "imovx")
1419 (and (ne (symbol_ref "TARGET_MOVX")
1421 (eq_attr "alternative" "2"))
1422 (const_string "imovx")
1424 (const_string "imov")))
1426 (cond [(eq_attr "alternative" "3,4,5")
1428 (eq_attr "alternative" "6")
1430 (eq_attr "type" "imovx")
1432 (and (eq_attr "type" "imov")
1433 (and (eq_attr "alternative" "0,1,2")
1434 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1437 ;; Avoid partial register stalls when not using QImode arithmetic
1438 (and (eq_attr "type" "imov")
1439 (and (eq_attr "alternative" "0,1,2")
1440 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1442 (eq (symbol_ref "TARGET_QIMODE_MATH")
1446 (const_string "QI")))])
1448 (define_expand "reload_outqi"
1449 [(parallel [(match_operand:QI 0 "" "=m")
1450 (match_operand:QI 1 "register_operand" "r")
1451 (match_operand:QI 2 "register_operand" "=&q")])]
1455 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1457 if (reg_overlap_mentioned_p (op2, op0))
1459 if (! q_regs_operand (op1, QImode))
1461 emit_insn (gen_movqi (op2, op1));
1464 emit_insn (gen_movqi (op0, op1));
1468 (define_insn "*swapqi"
1469 [(set (match_operand:QI 0 "register_operand" "+r")
1470 (match_operand:QI 1 "register_operand" "+r"))
1475 [(set_attr "type" "imov")
1476 (set_attr "pent_pair" "np")
1477 (set_attr "mode" "QI")
1478 (set_attr "modrm" "0")
1479 (set_attr "ppro_uops" "few")])
1481 (define_expand "movstrictqi"
1482 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1483 (match_operand:QI 1 "general_operand" ""))]
1484 "! TARGET_PARTIAL_REG_STALL"
1486 /* Don't generate memory->memory moves, go through a register. */
1487 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1488 operands[1] = force_reg (QImode, operands[1]);
1491 (define_insn "*movstrictqi_1"
1492 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1493 (match_operand:QI 1 "general_operand" "*qn,m"))]
1494 "! TARGET_PARTIAL_REG_STALL
1495 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1496 "mov{b}\t{%1, %0|%0, %1}"
1497 [(set_attr "type" "imov")
1498 (set_attr "mode" "QI")])
1500 (define_insn "*movstrictqi_xor"
1501 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1502 (match_operand:QI 1 "const0_operand" "i"))
1503 (clobber (reg:CC 17))]
1504 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1505 "xor{b}\t{%0, %0|%0, %0}"
1506 [(set_attr "type" "alu1")
1507 (set_attr "mode" "QI")
1508 (set_attr "length_immediate" "0")])
1510 (define_insn "*movsi_extv_1"
1511 [(set (match_operand:SI 0 "register_operand" "=R")
1512 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1516 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1517 [(set_attr "type" "imovx")
1518 (set_attr "mode" "SI")])
1520 (define_insn "*movhi_extv_1"
1521 [(set (match_operand:HI 0 "register_operand" "=R")
1522 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1526 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1527 [(set_attr "type" "imovx")
1528 (set_attr "mode" "SI")])
1530 (define_insn "*movqi_extv_1"
1531 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1532 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1537 switch (get_attr_type (insn))
1540 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1542 return "mov{b}\t{%h1, %0|%0, %h1}";
1546 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1547 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1548 (ne (symbol_ref "TARGET_MOVX")
1550 (const_string "imovx")
1551 (const_string "imov")))
1553 (if_then_else (eq_attr "type" "imovx")
1555 (const_string "QI")))])
1557 (define_insn "*movqi_extv_1_rex64"
1558 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1559 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1564 switch (get_attr_type (insn))
1567 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1569 return "mov{b}\t{%h1, %0|%0, %h1}";
1573 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1574 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1575 (ne (symbol_ref "TARGET_MOVX")
1577 (const_string "imovx")
1578 (const_string "imov")))
1580 (if_then_else (eq_attr "type" "imovx")
1582 (const_string "QI")))])
1584 ;; Stores and loads of ax to arbitary constant address.
1585 ;; We fake an second form of instruction to force reload to load address
1586 ;; into register when rax is not available
1587 (define_insn "*movabsqi_1_rex64"
1588 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1589 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1592 movabs{b}\t{%1, %P0|%P0, %1}
1593 mov{b}\t{%1, %a0|%a0, %1}
1594 movabs{b}\t{%1, %a0|%a0, %1}"
1595 [(set_attr "type" "imov")
1596 (set_attr "modrm" "0,*,*")
1597 (set_attr "length_address" "8,0,0")
1598 (set_attr "length_immediate" "0,*,*")
1599 (set_attr "memory" "store")
1600 (set_attr "mode" "QI")])
1602 (define_insn "*movabsqi_2_rex64"
1603 [(set (match_operand:QI 0 "register_operand" "=a,r")
1604 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1607 movabs{b}\t{%P1, %0|%0, %P1}
1608 mov{b}\t{%a1, %0|%0, %a1}"
1609 [(set_attr "type" "imov")
1610 (set_attr "modrm" "0,*")
1611 (set_attr "length_address" "8,0")
1612 (set_attr "length_immediate" "0")
1613 (set_attr "memory" "load")
1614 (set_attr "mode" "QI")])
1616 (define_insn "*movsi_extzv_1"
1617 [(set (match_operand:SI 0 "register_operand" "=R")
1618 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1622 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1623 [(set_attr "type" "imovx")
1624 (set_attr "mode" "SI")])
1626 (define_insn "*movqi_extzv_2"
1627 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1628 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1633 switch (get_attr_type (insn))
1636 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1638 return "mov{b}\t{%h1, %0|%0, %h1}";
1642 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1643 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1644 (ne (symbol_ref "TARGET_MOVX")
1646 (const_string "imovx")
1647 (const_string "imov")))
1649 (if_then_else (eq_attr "type" "imovx")
1651 (const_string "QI")))])
1653 (define_insn "*movqi_extzv_2_rex64"
1654 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1655 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1660 switch (get_attr_type (insn))
1663 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1665 return "mov{b}\t{%h1, %0|%0, %h1}";
1669 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1670 (ne (symbol_ref "TARGET_MOVX")
1672 (const_string "imovx")
1673 (const_string "imov")))
1675 (if_then_else (eq_attr "type" "imovx")
1677 (const_string "QI")))])
1679 (define_insn "movsi_insv_1"
1680 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1683 (match_operand:SI 1 "general_operand" "Qmn"))]
1685 "mov{b}\t{%b1, %h0|%h0, %b1}"
1686 [(set_attr "type" "imov")
1687 (set_attr "mode" "QI")])
1689 (define_insn "*movsi_insv_1_rex64"
1690 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1693 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1695 "mov{b}\t{%b1, %h0|%h0, %b1}"
1696 [(set_attr "type" "imov")
1697 (set_attr "mode" "QI")])
1699 (define_insn "*movqi_insv_2"
1700 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1703 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1707 "mov{b}\t{%h1, %h0|%h0, %h1}"
1708 [(set_attr "type" "imov")
1709 (set_attr "mode" "QI")])
1711 (define_expand "movdi"
1712 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1713 (match_operand:DI 1 "general_operand" ""))]
1715 "ix86_expand_move (DImode, operands); DONE;")
1717 (define_insn "*pushdi"
1718 [(set (match_operand:DI 0 "push_operand" "=<")
1719 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1723 (define_insn "pushdi2_rex64"
1724 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1725 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1730 [(set_attr "type" "push,multi")
1731 (set_attr "mode" "DI")])
1733 ;; Convert impossible pushes of immediate to existing instructions.
1734 ;; First try to get scratch register and go through it. In case this
1735 ;; fails, push sign extended lower part first and then overwrite
1736 ;; upper part by 32bit move.
1738 [(match_scratch:DI 2 "r")
1739 (set (match_operand:DI 0 "push_operand" "")
1740 (match_operand:DI 1 "immediate_operand" ""))]
1741 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1742 && !x86_64_immediate_operand (operands[1], DImode)"
1743 [(set (match_dup 2) (match_dup 1))
1744 (set (match_dup 0) (match_dup 2))]
1747 ;; We need to define this as both peepholer and splitter for case
1748 ;; peephole2 pass is not run.
1750 [(set (match_operand:DI 0 "push_operand" "")
1751 (match_operand:DI 1 "immediate_operand" ""))]
1752 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1753 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1754 [(set (match_dup 0) (match_dup 1))
1755 (set (match_dup 2) (match_dup 3))]
1756 "split_di (operands + 1, 1, operands + 2, operands + 3);
1757 operands[1] = gen_lowpart (DImode, operands[2]);
1758 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1763 [(set (match_operand:DI 0 "push_operand" "")
1764 (match_operand:DI 1 "immediate_operand" ""))]
1765 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1766 && !symbolic_operand (operands[1], DImode)
1767 && !x86_64_immediate_operand (operands[1], DImode)"
1768 [(set (match_dup 0) (match_dup 1))
1769 (set (match_dup 2) (match_dup 3))]
1770 "split_di (operands + 1, 1, operands + 2, operands + 3);
1771 operands[1] = gen_lowpart (DImode, operands[2]);
1772 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1776 (define_insn "*pushdi2_prologue_rex64"
1777 [(set (match_operand:DI 0 "push_operand" "=<")
1778 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1779 (clobber (mem:BLK (scratch)))]
1782 [(set_attr "type" "push")
1783 (set_attr "mode" "DI")])
1785 (define_insn "*popdi1_epilogue_rex64"
1786 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1787 (mem:DI (reg:DI 7)))
1789 (plus:DI (reg:DI 7) (const_int 8)))
1790 (clobber (mem:BLK (scratch)))]
1793 [(set_attr "type" "pop")
1794 (set_attr "mode" "DI")])
1796 (define_insn "popdi1"
1797 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1798 (mem:DI (reg:DI 7)))
1800 (plus:DI (reg:DI 7) (const_int 8)))]
1803 [(set_attr "type" "pop")
1804 (set_attr "mode" "DI")])
1806 (define_insn "*movdi_xor_rex64"
1807 [(set (match_operand:DI 0 "register_operand" "=r")
1808 (match_operand:DI 1 "const0_operand" "i"))
1809 (clobber (reg:CC 17))]
1810 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1811 && reload_completed"
1812 "xor{l}\t{%k0, %k0|%k0, %k0}"
1813 [(set_attr "type" "alu1")
1814 (set_attr "mode" "SI")
1815 (set_attr "length_immediate" "0")])
1817 (define_insn "*movdi_or_rex64"
1818 [(set (match_operand:DI 0 "register_operand" "=r")
1819 (match_operand:DI 1 "const_int_operand" "i"))
1820 (clobber (reg:CC 17))]
1821 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1823 && GET_CODE (operands[1]) == CONST_INT
1824 && INTVAL (operands[1]) == -1"
1826 operands[1] = constm1_rtx;
1827 return "or{q}\t{%1, %0|%0, %1}";
1829 [(set_attr "type" "alu1")
1830 (set_attr "mode" "DI")
1831 (set_attr "length_immediate" "1")])
1833 (define_insn "*movdi_2"
1834 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1835 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1837 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1841 movq\t{%1, %0|%0, %1}
1842 movq\t{%1, %0|%0, %1}
1843 movq\t{%1, %0|%0, %1}
1844 movdqa\t{%1, %0|%0, %1}
1845 movq\t{%1, %0|%0, %1}"
1846 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1847 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1850 [(set (match_operand:DI 0 "push_operand" "")
1851 (match_operand:DI 1 "general_operand" ""))]
1852 "!TARGET_64BIT && reload_completed
1853 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1855 "ix86_split_long_move (operands); DONE;")
1857 ;; %%% This multiword shite has got to go.
1859 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1860 (match_operand:DI 1 "general_operand" ""))]
1861 "!TARGET_64BIT && reload_completed
1862 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1863 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1865 "ix86_split_long_move (operands); DONE;")
1867 (define_insn "*movdi_1_rex64"
1868 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
1869 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
1871 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1873 switch (get_attr_type (insn))
1876 if (register_operand (operands[0], DImode)
1877 && register_operand (operands[1], DImode))
1878 return "movdqa\t{%1, %0|%0, %1}";
1881 return "movq\t{%1, %0|%0, %1}";
1885 return "lea{q}\t{%a1, %0|%0, %a1}";
1887 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1889 if (get_attr_mode (insn) == MODE_SI)
1890 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1891 else if (which_alternative == 2)
1892 return "movabs{q}\t{%1, %0|%0, %1}";
1894 return "mov{q}\t{%1, %0|%0, %1}";
1898 (cond [(eq_attr "alternative" "5,6")
1899 (const_string "mmxmov")
1900 (eq_attr "alternative" "7,8")
1901 (const_string "ssemov")
1902 (eq_attr "alternative" "4")
1903 (const_string "multi")
1904 (and (ne (symbol_ref "flag_pic") (const_int 0))
1905 (match_operand:DI 1 "symbolic_operand" ""))
1906 (const_string "lea")
1908 (const_string "imov")))
1909 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
1910 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
1911 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
1913 ;; Stores and loads of ax to arbitary constant address.
1914 ;; We fake an second form of instruction to force reload to load address
1915 ;; into register when rax is not available
1916 (define_insn "*movabsdi_1_rex64"
1917 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1918 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
1921 movabs{q}\t{%1, %P0|%P0, %1}
1922 mov{q}\t{%1, %a0|%a0, %1}
1923 movabs{q}\t{%1, %a0|%a0, %1}"
1924 [(set_attr "type" "imov")
1925 (set_attr "modrm" "0,*,*")
1926 (set_attr "length_address" "8,0,0")
1927 (set_attr "length_immediate" "0,*,*")
1928 (set_attr "memory" "store")
1929 (set_attr "mode" "DI")])
1931 (define_insn "*movabsdi_2_rex64"
1932 [(set (match_operand:DI 0 "register_operand" "=a,r")
1933 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1936 movabs{q}\t{%P1, %0|%0, %P1}
1937 mov{q}\t{%a1, %0|%0, %a1}"
1938 [(set_attr "type" "imov")
1939 (set_attr "modrm" "0,*")
1940 (set_attr "length_address" "8,0")
1941 (set_attr "length_immediate" "0")
1942 (set_attr "memory" "load")
1943 (set_attr "mode" "DI")])
1945 ;; Convert impossible stores of immediate to existing instructions.
1946 ;; First try to get scratch register and go through it. In case this
1947 ;; fails, move by 32bit parts.
1949 [(match_scratch:DI 2 "r")
1950 (set (match_operand:DI 0 "memory_operand" "")
1951 (match_operand:DI 1 "immediate_operand" ""))]
1952 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1953 && !x86_64_immediate_operand (operands[1], DImode)"
1954 [(set (match_dup 2) (match_dup 1))
1955 (set (match_dup 0) (match_dup 2))]
1958 ;; We need to define this as both peepholer and splitter for case
1959 ;; peephole2 pass is not run.
1961 [(set (match_operand:DI 0 "memory_operand" "")
1962 (match_operand:DI 1 "immediate_operand" ""))]
1963 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1964 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1965 [(set (match_dup 2) (match_dup 3))
1966 (set (match_dup 4) (match_dup 5))]
1967 "split_di (operands, 2, operands + 2, operands + 4);")
1970 [(set (match_operand:DI 0 "memory_operand" "")
1971 (match_operand:DI 1 "immediate_operand" ""))]
1972 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1973 && !symbolic_operand (operands[1], DImode)
1974 && !x86_64_immediate_operand (operands[1], DImode)"
1975 [(set (match_dup 2) (match_dup 3))
1976 (set (match_dup 4) (match_dup 5))]
1977 "split_di (operands, 2, operands + 2, operands + 4);")
1979 (define_insn "*swapdi_rex64"
1980 [(set (match_operand:DI 0 "register_operand" "+r")
1981 (match_operand:DI 1 "register_operand" "+r"))
1986 [(set_attr "type" "imov")
1987 (set_attr "pent_pair" "np")
1988 (set_attr "athlon_decode" "vector")
1989 (set_attr "mode" "DI")
1990 (set_attr "modrm" "0")
1991 (set_attr "ppro_uops" "few")])
1994 (define_expand "movsf"
1995 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1996 (match_operand:SF 1 "general_operand" ""))]
1998 "ix86_expand_move (SFmode, operands); DONE;")
2000 (define_insn "*pushsf"
2001 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2002 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2005 switch (which_alternative)
2008 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2009 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2010 operands[2] = stack_pointer_rtx;
2011 operands[3] = GEN_INT (4);
2012 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2013 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2015 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2018 return "push{l}\t%1";
2026 [(set_attr "type" "multi,push,multi")
2027 (set_attr "mode" "SF,SI,SF")])
2029 (define_insn "*pushsf_rex64"
2030 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2031 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2034 switch (which_alternative)
2037 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2038 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2039 operands[2] = stack_pointer_rtx;
2040 operands[3] = GEN_INT (8);
2041 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2042 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2044 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2047 return "push{q}\t%q1";
2056 [(set_attr "type" "multi,push,multi")
2057 (set_attr "mode" "SF,DI,SF")])
2060 [(set (match_operand:SF 0 "push_operand" "")
2061 (match_operand:SF 1 "memory_operand" ""))]
2063 && GET_CODE (operands[1]) == MEM
2064 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2065 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2068 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2071 ;; %%% Kill this when call knows how to work this out.
2073 [(set (match_operand:SF 0 "push_operand" "")
2074 (match_operand:SF 1 "register_operand" ""))]
2075 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2076 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2077 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2080 [(set (match_operand:SF 0 "push_operand" "")
2081 (match_operand:SF 1 "register_operand" ""))]
2082 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2083 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2084 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2086 (define_insn "*movsf_1"
2087 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2088 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))]
2089 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2090 && (reload_in_progress || reload_completed
2091 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2092 || GET_CODE (operands[1]) != CONST_DOUBLE
2093 || memory_operand (operands[0], SFmode))"
2095 switch (which_alternative)
2098 if (REG_P (operands[1])
2099 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2101 else if (STACK_TOP_P (operands[0]))
2102 return "fld%z1\t%y1";
2107 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2108 return "fstp%z0\t%y0";
2110 return "fst%z0\t%y0";
2113 switch (standard_80387_constant_p (operands[1]))
2124 return "mov{l}\t{%1, %0|%0, %1}";
2127 return "pxor\t%0, %0";
2129 return "xorps\t%0, %0";
2131 if (TARGET_PARTIAL_REG_DEPENDENCY)
2132 return "movaps\t{%1, %0|%0, %1}";
2134 return "movss\t{%1, %0|%0, %1}";
2137 return "movss\t{%1, %0|%0, %1}";
2141 return "movd\t{%1, %0|%0, %1}";
2144 return "movq\t{%1, %0|%0, %1}";
2150 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2151 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
2153 (define_insn "*swapsf"
2154 [(set (match_operand:SF 0 "register_operand" "+f")
2155 (match_operand:SF 1 "register_operand" "+f"))
2158 "reload_completed || !TARGET_SSE"
2160 if (STACK_TOP_P (operands[0]))
2165 [(set_attr "type" "fxch")
2166 (set_attr "mode" "SF")])
2168 (define_expand "movdf"
2169 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2170 (match_operand:DF 1 "general_operand" ""))]
2172 "ix86_expand_move (DFmode, operands); DONE;")
2174 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2175 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2176 ;; On the average, pushdf using integers can be still shorter. Allow this
2177 ;; pattern for optimize_size too.
2179 (define_insn "*pushdf_nointeger"
2180 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2181 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2182 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2184 switch (which_alternative)
2187 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2188 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2189 operands[2] = stack_pointer_rtx;
2190 operands[3] = GEN_INT (8);
2191 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2192 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2194 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2205 [(set_attr "type" "multi")
2206 (set_attr "mode" "DF,SI,SI,DF")])
2208 (define_insn "*pushdf_integer"
2209 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2210 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2211 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2213 switch (which_alternative)
2216 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2217 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2218 operands[2] = stack_pointer_rtx;
2219 operands[3] = GEN_INT (8);
2221 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2222 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2224 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2226 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2227 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2229 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2240 [(set_attr "type" "multi")
2241 (set_attr "mode" "DF,SI,DF")])
2243 ;; %%% Kill this when call knows how to work this out.
2245 [(set (match_operand:DF 0 "push_operand" "")
2246 (match_operand:DF 1 "register_operand" ""))]
2247 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2248 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2249 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2253 [(set (match_operand:DF 0 "push_operand" "")
2254 (match_operand:DF 1 "register_operand" ""))]
2255 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2256 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2257 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2261 [(set (match_operand:DF 0 "push_operand" "")
2262 (match_operand:DF 1 "general_operand" ""))]
2265 "ix86_split_long_move (operands); DONE;")
2267 ;; Moving is usually shorter when only FP registers are used. This separate
2268 ;; movdf pattern avoids the use of integer registers for FP operations
2269 ;; when optimizing for size.
2271 (define_insn "*movdf_nointeger"
2272 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2273 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2274 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2275 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2276 && (reload_in_progress || reload_completed
2277 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2278 || GET_CODE (operands[1]) != CONST_DOUBLE
2279 || memory_operand (operands[0], DFmode))"
2281 switch (which_alternative)
2284 if (REG_P (operands[1])
2285 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2287 else if (STACK_TOP_P (operands[0]))
2288 return "fld%z1\t%y1";
2293 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2294 return "fstp%z0\t%y0";
2296 return "fst%z0\t%y0";
2299 switch (standard_80387_constant_p (operands[1]))
2312 return "pxor\t%0, %0";
2314 if (TARGET_PARTIAL_REG_DEPENDENCY)
2315 return "movapd\t{%1, %0|%0, %1}";
2317 return "movsd\t{%1, %0|%0, %1}";
2320 return "movsd\t{%1, %0|%0, %1}";
2326 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2327 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2329 (define_insn "*movdf_integer"
2330 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2331 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2332 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2333 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2334 && (reload_in_progress || reload_completed
2335 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2336 || GET_CODE (operands[1]) != CONST_DOUBLE
2337 || memory_operand (operands[0], DFmode))"
2339 switch (which_alternative)
2342 if (REG_P (operands[1])
2343 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2345 else if (STACK_TOP_P (operands[0]))
2346 return "fld%z1\t%y1";
2351 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2352 return "fstp%z0\t%y0";
2354 return "fst%z0\t%y0";
2357 switch (standard_80387_constant_p (operands[1]))
2371 return "pxor\t%0, %0";
2373 if (TARGET_PARTIAL_REG_DEPENDENCY)
2374 return "movapd\t{%1, %0|%0, %1}";
2376 return "movsd\t{%1, %0|%0, %1}";
2379 return "movsd\t{%1, %0|%0, %1}";
2385 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2386 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2389 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2390 (match_operand:DF 1 "general_operand" ""))]
2392 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2393 && ! (ANY_FP_REG_P (operands[0]) ||
2394 (GET_CODE (operands[0]) == SUBREG
2395 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2396 && ! (ANY_FP_REG_P (operands[1]) ||
2397 (GET_CODE (operands[1]) == SUBREG
2398 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2400 "ix86_split_long_move (operands); DONE;")
2402 (define_insn "*swapdf"
2403 [(set (match_operand:DF 0 "register_operand" "+f")
2404 (match_operand:DF 1 "register_operand" "+f"))
2407 "reload_completed || !TARGET_SSE2"
2409 if (STACK_TOP_P (operands[0]))
2414 [(set_attr "type" "fxch")
2415 (set_attr "mode" "DF")])
2417 (define_expand "movxf"
2418 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2419 (match_operand:XF 1 "general_operand" ""))]
2421 "ix86_expand_move (XFmode, operands); DONE;")
2423 (define_expand "movtf"
2424 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2425 (match_operand:TF 1 "general_operand" ""))]
2427 "ix86_expand_move (TFmode, operands); DONE;")
2429 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2430 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
2431 ;; Pushing using integer instructions is longer except for constants
2432 ;; and direct memory references.
2433 ;; (assuming that any given constant is pushed only once, but this ought to be
2434 ;; handled elsewhere).
2436 (define_insn "*pushxf_nointeger"
2437 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2438 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2439 "!TARGET_64BIT && optimize_size"
2441 switch (which_alternative)
2444 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2445 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2446 operands[2] = stack_pointer_rtx;
2447 operands[3] = GEN_INT (12);
2448 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2449 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2451 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2461 [(set_attr "type" "multi")
2462 (set_attr "mode" "XF,SI,SI")])
2464 (define_insn "*pushtf_nointeger"
2465 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2466 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2469 switch (which_alternative)
2472 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2473 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2474 operands[2] = stack_pointer_rtx;
2475 operands[3] = GEN_INT (16);
2476 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2477 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2479 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2489 [(set_attr "type" "multi")
2490 (set_attr "mode" "XF,SI,SI")])
2492 (define_insn "*pushxf_integer"
2493 [(set (match_operand:XF 0 "push_operand" "=<,<")
2494 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2495 "!TARGET_64BIT && !optimize_size"
2497 switch (which_alternative)
2500 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2501 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2502 operands[2] = stack_pointer_rtx;
2503 operands[3] = GEN_INT (12);
2504 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2505 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2507 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2516 [(set_attr "type" "multi")
2517 (set_attr "mode" "XF,SI")])
2519 (define_insn "*pushtf_integer"
2520 [(set (match_operand:TF 0 "push_operand" "=<,<")
2521 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2524 switch (which_alternative)
2527 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2528 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2529 operands[2] = stack_pointer_rtx;
2530 operands[3] = GEN_INT (16);
2532 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2533 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2535 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2537 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2538 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2540 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2549 [(set_attr "type" "multi")
2550 (set_attr "mode" "XF,SI")])
2553 [(set (match_operand 0 "push_operand" "")
2554 (match_operand 1 "general_operand" ""))]
2556 && (GET_MODE (operands[0]) == XFmode
2557 || GET_MODE (operands[0]) == TFmode
2558 || GET_MODE (operands[0]) == DFmode)
2559 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
2561 "ix86_split_long_move (operands); DONE;")
2564 [(set (match_operand:XF 0 "push_operand" "")
2565 (match_operand:XF 1 "register_operand" ""))]
2566 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2567 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2568 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2571 [(set (match_operand:TF 0 "push_operand" "")
2572 (match_operand:TF 1 "register_operand" ""))]
2573 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2574 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2575 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2578 [(set (match_operand:TF 0 "push_operand" "")
2579 (match_operand:TF 1 "register_operand" ""))]
2580 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2581 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2582 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2584 ;; Do not use integer registers when optimizing for size
2585 (define_insn "*movxf_nointeger"
2586 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2587 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2590 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2591 && (reload_in_progress || reload_completed
2592 || GET_CODE (operands[1]) != CONST_DOUBLE
2593 || memory_operand (operands[0], XFmode))"
2595 switch (which_alternative)
2598 if (REG_P (operands[1])
2599 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2601 else if (STACK_TOP_P (operands[0]))
2602 return "fld%z1\t%y1";
2607 /* There is no non-popping store to memory for XFmode. So if
2608 we need one, follow the store with a load. */
2609 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2610 return "fstp%z0\t%y0\;fld%z0\t%y0";
2612 return "fstp%z0\t%y0";
2615 switch (standard_80387_constant_p (operands[1]))
2629 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2630 (set_attr "mode" "XF,XF,XF,SI,SI")])
2632 (define_insn "*movtf_nointeger"
2633 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2634 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2635 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2637 && (reload_in_progress || reload_completed
2638 || GET_CODE (operands[1]) != CONST_DOUBLE
2639 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2640 || memory_operand (operands[0], TFmode))"
2642 switch (which_alternative)
2645 if (REG_P (operands[1])
2646 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2648 else if (STACK_TOP_P (operands[0]))
2649 return "fld%z1\t%y1";
2654 /* There is no non-popping store to memory for XFmode. So if
2655 we need one, follow the store with a load. */
2656 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2657 return "fstp%z0\t%y0\;fld%z0\t%y0";
2659 return "fstp%z0\t%y0";
2662 switch (standard_80387_constant_p (operands[1]))
2676 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2677 (set_attr "mode" "XF,XF,XF,SI,SI")])
2679 (define_insn "*movxf_integer"
2680 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2681 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2684 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2685 && (reload_in_progress || reload_completed
2686 || GET_CODE (operands[1]) != CONST_DOUBLE
2687 || memory_operand (operands[0], XFmode))"
2689 switch (which_alternative)
2692 if (REG_P (operands[1])
2693 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2695 else if (STACK_TOP_P (operands[0]))
2696 return "fld%z1\t%y1";
2701 /* There is no non-popping store to memory for XFmode. So if
2702 we need one, follow the store with a load. */
2703 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2704 return "fstp%z0\t%y0\;fld%z0\t%y0";
2706 return "fstp%z0\t%y0";
2709 switch (standard_80387_constant_p (operands[1]))
2723 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2724 (set_attr "mode" "XF,XF,XF,SI,SI")])
2726 (define_insn "*movtf_integer"
2727 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2728 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2729 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2731 && (reload_in_progress || reload_completed
2732 || GET_CODE (operands[1]) != CONST_DOUBLE
2733 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2734 || memory_operand (operands[0], TFmode))"
2736 switch (which_alternative)
2739 if (REG_P (operands[1])
2740 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2742 else if (STACK_TOP_P (operands[0]))
2743 return "fld%z1\t%y1";
2748 /* There is no non-popping store to memory for XFmode. So if
2749 we need one, follow the store with a load. */
2750 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2751 return "fstp%z0\t%y0\;fld%z0\t%y0";
2753 return "fstp%z0\t%y0";
2756 switch (standard_80387_constant_p (operands[1]))
2770 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2771 (set_attr "mode" "XF,XF,XF,SI,SI")])
2774 [(set (match_operand 0 "nonimmediate_operand" "")
2775 (match_operand 1 "general_operand" ""))]
2777 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2778 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
2779 && ! (ANY_FP_REG_P (operands[0]) ||
2780 (GET_CODE (operands[0]) == SUBREG
2781 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2782 && ! (ANY_FP_REG_P (operands[1]) ||
2783 (GET_CODE (operands[1]) == SUBREG
2784 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2786 "ix86_split_long_move (operands); DONE;")
2789 [(set (match_operand 0 "register_operand" "")
2790 (match_operand 1 "memory_operand" ""))]
2792 && GET_CODE (operands[1]) == MEM
2793 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
2794 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2795 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2796 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
2797 && (!(SSE_REG_P (operands[0]) ||
2798 (GET_CODE (operands[0]) == SUBREG
2799 && SSE_REG_P (SUBREG_REG (operands[0]))))
2800 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
2801 && (!(FP_REG_P (operands[0]) ||
2802 (GET_CODE (operands[0]) == SUBREG
2803 && FP_REG_P (SUBREG_REG (operands[0]))))
2804 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
2807 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2809 (define_insn "swapxf"
2810 [(set (match_operand:XF 0 "register_operand" "+f")
2811 (match_operand:XF 1 "register_operand" "+f"))
2816 if (STACK_TOP_P (operands[0]))
2821 [(set_attr "type" "fxch")
2822 (set_attr "mode" "XF")])
2824 (define_insn "swaptf"
2825 [(set (match_operand:TF 0 "register_operand" "+f")
2826 (match_operand:TF 1 "register_operand" "+f"))
2831 if (STACK_TOP_P (operands[0]))
2836 [(set_attr "type" "fxch")
2837 (set_attr "mode" "XF")])
2839 ;; Zero extension instructions
2841 (define_expand "zero_extendhisi2"
2842 [(set (match_operand:SI 0 "register_operand" "")
2843 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2846 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2848 operands[1] = force_reg (HImode, operands[1]);
2849 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2854 (define_insn "zero_extendhisi2_and"
2855 [(set (match_operand:SI 0 "register_operand" "=r")
2856 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2857 (clobber (reg:CC 17))]
2858 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2860 [(set_attr "type" "alu1")
2861 (set_attr "mode" "SI")])
2864 [(set (match_operand:SI 0 "register_operand" "")
2865 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2866 (clobber (reg:CC 17))]
2867 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2868 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2869 (clobber (reg:CC 17))])]
2872 (define_insn "*zero_extendhisi2_movzwl"
2873 [(set (match_operand:SI 0 "register_operand" "=r")
2874 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2875 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2876 "movz{wl|x}\t{%1, %0|%0, %1}"
2877 [(set_attr "type" "imovx")
2878 (set_attr "mode" "SI")])
2880 (define_expand "zero_extendqihi2"
2882 [(set (match_operand:HI 0 "register_operand" "")
2883 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2884 (clobber (reg:CC 17))])]
2888 (define_insn "*zero_extendqihi2_and"
2889 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2890 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2891 (clobber (reg:CC 17))]
2892 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2894 [(set_attr "type" "alu1")
2895 (set_attr "mode" "HI")])
2897 (define_insn "*zero_extendqihi2_movzbw_and"
2898 [(set (match_operand:HI 0 "register_operand" "=r,r")
2899 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2900 (clobber (reg:CC 17))]
2901 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2903 [(set_attr "type" "imovx,alu1")
2904 (set_attr "mode" "HI")])
2906 (define_insn "*zero_extendqihi2_movzbw"
2907 [(set (match_operand:HI 0 "register_operand" "=r")
2908 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2909 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2910 "movz{bw|x}\t{%1, %0|%0, %1}"
2911 [(set_attr "type" "imovx")
2912 (set_attr "mode" "HI")])
2914 ;; For the movzbw case strip only the clobber
2916 [(set (match_operand:HI 0 "register_operand" "")
2917 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2918 (clobber (reg:CC 17))]
2920 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2921 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2922 [(set (match_operand:HI 0 "register_operand" "")
2923 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
2925 ;; When source and destination does not overlap, clear destination
2926 ;; first and then do the movb
2928 [(set (match_operand:HI 0 "register_operand" "")
2929 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2930 (clobber (reg:CC 17))]
2932 && ANY_QI_REG_P (operands[0])
2933 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2934 && !reg_overlap_mentioned_p (operands[0], operands[1])"
2935 [(set (match_dup 0) (const_int 0))
2936 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2937 "operands[2] = gen_lowpart (QImode, operands[0]);")
2939 ;; Rest is handled by single and.
2941 [(set (match_operand:HI 0 "register_operand" "")
2942 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
2943 (clobber (reg:CC 17))]
2945 && true_regnum (operands[0]) == true_regnum (operands[1])"
2946 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
2947 (clobber (reg:CC 17))])]
2950 (define_expand "zero_extendqisi2"
2952 [(set (match_operand:SI 0 "register_operand" "")
2953 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
2954 (clobber (reg:CC 17))])]
2958 (define_insn "*zero_extendqisi2_and"
2959 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
2960 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2961 (clobber (reg:CC 17))]
2962 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2964 [(set_attr "type" "alu1")
2965 (set_attr "mode" "SI")])
2967 (define_insn "*zero_extendqisi2_movzbw_and"
2968 [(set (match_operand:SI 0 "register_operand" "=r,r")
2969 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2970 (clobber (reg:CC 17))]
2971 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2973 [(set_attr "type" "imovx,alu1")
2974 (set_attr "mode" "SI")])
2976 (define_insn "*zero_extendqisi2_movzbw"
2977 [(set (match_operand:SI 0 "register_operand" "=r")
2978 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2979 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2980 "movz{bl|x}\t{%1, %0|%0, %1}"
2981 [(set_attr "type" "imovx")
2982 (set_attr "mode" "SI")])
2984 ;; For the movzbl case strip only the clobber
2986 [(set (match_operand:SI 0 "register_operand" "")
2987 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
2988 (clobber (reg:CC 17))]
2990 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2991 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2993 (zero_extend:SI (match_dup 1)))])
2995 ;; When source and destination does not overlap, clear destination
2996 ;; first and then do the movb
2998 [(set (match_operand:SI 0 "register_operand" "")
2999 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3000 (clobber (reg:CC 17))]
3002 && ANY_QI_REG_P (operands[0])
3003 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3004 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3005 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3006 [(set (match_dup 0) (const_int 0))
3007 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3008 "operands[2] = gen_lowpart (QImode, operands[0]);")
3010 ;; Rest is handled by single and.
3012 [(set (match_operand:SI 0 "register_operand" "")
3013 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3014 (clobber (reg:CC 17))]
3016 && true_regnum (operands[0]) == true_regnum (operands[1])"
3017 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3018 (clobber (reg:CC 17))])]
3021 ;; %%% Kill me once multi-word ops are sane.
3022 (define_expand "zero_extendsidi2"
3023 [(set (match_operand:DI 0 "register_operand" "=r")
3024 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3028 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3033 (define_insn "zero_extendsidi2_32"
3034 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3035 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3036 (clobber (reg:CC 17))]
3039 [(set_attr "mode" "SI")])
3041 (define_insn "zero_extendsidi2_rex64"
3042 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3043 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3046 mov\t{%k1, %k0|%k0, %k1}
3048 [(set_attr "type" "imovx,imov")
3049 (set_attr "mode" "SI,DI")])
3052 [(set (match_operand:DI 0 "memory_operand" "")
3053 (zero_extend:DI (match_dup 0)))]
3055 [(set (match_dup 4) (const_int 0))]
3056 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3059 [(set (match_operand:DI 0 "register_operand" "")
3060 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3061 (clobber (reg:CC 17))]
3062 "!TARGET_64BIT && reload_completed
3063 && true_regnum (operands[0]) == true_regnum (operands[1])"
3064 [(set (match_dup 4) (const_int 0))]
3065 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3068 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3069 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3070 (clobber (reg:CC 17))]
3071 "!TARGET_64BIT && reload_completed"
3072 [(set (match_dup 3) (match_dup 1))
3073 (set (match_dup 4) (const_int 0))]
3074 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3076 (define_insn "zero_extendhidi2"
3077 [(set (match_operand:DI 0 "register_operand" "=r,r")
3078 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3081 movz{wl|x}\t{%1, %k0|%k0, %1}
3082 movz{wq|x}\t{%1, %0|%0, %1}"
3083 [(set_attr "type" "imovx")
3084 (set_attr "mode" "SI,DI")])
3086 (define_insn "zero_extendqidi2"
3087 [(set (match_operand:DI 0 "register_operand" "=r,r")
3088 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3091 movz{bl|x}\t{%1, %k0|%k0, %1}
3092 movz{bq|x}\t{%1, %0|%0, %1}"
3093 [(set_attr "type" "imovx")
3094 (set_attr "mode" "SI,DI")])
3096 ;; Sign extension instructions
3098 (define_expand "extendsidi2"
3099 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3100 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3101 (clobber (reg:CC 17))
3102 (clobber (match_scratch:SI 2 ""))])]
3107 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3112 (define_insn "*extendsidi2_1"
3113 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3114 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3115 (clobber (reg:CC 17))
3116 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3120 (define_insn "extendsidi2_rex64"
3121 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3122 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3126 movs{lq|x}\t{%1,%0|%0, %1}"
3127 [(set_attr "type" "imovx")
3128 (set_attr "mode" "DI")
3129 (set_attr "prefix_0f" "0")
3130 (set_attr "modrm" "0,1")])
3132 (define_insn "extendhidi2"
3133 [(set (match_operand:DI 0 "register_operand" "=r")
3134 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3136 "movs{wq|x}\t{%1,%0|%0, %1}"
3137 [(set_attr "type" "imovx")
3138 (set_attr "mode" "DI")])
3140 (define_insn "extendqidi2"
3141 [(set (match_operand:DI 0 "register_operand" "=r")
3142 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3144 "movs{bq|x}\t{%1,%0|%0, %1}"
3145 [(set_attr "type" "imovx")
3146 (set_attr "mode" "DI")])
3148 ;; Extend to memory case when source register does die.
3150 [(set (match_operand:DI 0 "memory_operand" "")
3151 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3152 (clobber (reg:CC 17))
3153 (clobber (match_operand:SI 2 "register_operand" ""))]
3155 && dead_or_set_p (insn, operands[1])
3156 && !reg_mentioned_p (operands[1], operands[0]))"
3157 [(set (match_dup 3) (match_dup 1))
3158 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3159 (clobber (reg:CC 17))])
3160 (set (match_dup 4) (match_dup 1))]
3161 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3163 ;; Extend to memory case when source register does not die.
3165 [(set (match_operand:DI 0 "memory_operand" "")
3166 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3167 (clobber (reg:CC 17))
3168 (clobber (match_operand:SI 2 "register_operand" ""))]
3172 split_di (&operands[0], 1, &operands[3], &operands[4]);
3174 emit_move_insn (operands[3], operands[1]);
3176 /* Generate a cltd if possible and doing so it profitable. */
3177 if (true_regnum (operands[1]) == 0
3178 && true_regnum (operands[2]) == 1
3179 && (optimize_size || TARGET_USE_CLTD))
3181 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3185 emit_move_insn (operands[2], operands[1]);
3186 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3188 emit_move_insn (operands[4], operands[2]);
3192 ;; Extend to register case. Optimize case where source and destination
3193 ;; registers match and cases where we can use cltd.
3195 [(set (match_operand:DI 0 "register_operand" "")
3196 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3197 (clobber (reg:CC 17))
3198 (clobber (match_scratch:SI 2 ""))]
3202 split_di (&operands[0], 1, &operands[3], &operands[4]);
3204 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3205 emit_move_insn (operands[3], operands[1]);
3207 /* Generate a cltd if possible and doing so it profitable. */
3208 if (true_regnum (operands[3]) == 0
3209 && (optimize_size || TARGET_USE_CLTD))
3211 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3215 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3216 emit_move_insn (operands[4], operands[1]);
3218 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3222 (define_insn "extendhisi2"
3223 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3224 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3227 switch (get_attr_prefix_0f (insn))
3230 return "{cwtl|cwde}";
3232 return "movs{wl|x}\t{%1,%0|%0, %1}";
3235 [(set_attr "type" "imovx")
3236 (set_attr "mode" "SI")
3237 (set (attr "prefix_0f")
3238 ;; movsx is short decodable while cwtl is vector decoded.
3239 (if_then_else (and (eq_attr "cpu" "!k6")
3240 (eq_attr "alternative" "0"))
3242 (const_string "1")))
3244 (if_then_else (eq_attr "prefix_0f" "0")
3246 (const_string "1")))])
3248 (define_insn "*extendhisi2_zext"
3249 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3251 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3254 switch (get_attr_prefix_0f (insn))
3257 return "{cwtl|cwde}";
3259 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3262 [(set_attr "type" "imovx")
3263 (set_attr "mode" "SI")
3264 (set (attr "prefix_0f")
3265 ;; movsx is short decodable while cwtl is vector decoded.
3266 (if_then_else (and (eq_attr "cpu" "!k6")
3267 (eq_attr "alternative" "0"))
3269 (const_string "1")))
3271 (if_then_else (eq_attr "prefix_0f" "0")
3273 (const_string "1")))])
3275 (define_insn "extendqihi2"
3276 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3277 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3280 switch (get_attr_prefix_0f (insn))
3283 return "{cbtw|cbw}";
3285 return "movs{bw|x}\t{%1,%0|%0, %1}";
3288 [(set_attr "type" "imovx")
3289 (set_attr "mode" "HI")
3290 (set (attr "prefix_0f")
3291 ;; movsx is short decodable while cwtl is vector decoded.
3292 (if_then_else (and (eq_attr "cpu" "!k6")
3293 (eq_attr "alternative" "0"))
3295 (const_string "1")))
3297 (if_then_else (eq_attr "prefix_0f" "0")
3299 (const_string "1")))])
3301 (define_insn "extendqisi2"
3302 [(set (match_operand:SI 0 "register_operand" "=r")
3303 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3305 "movs{bl|x}\t{%1,%0|%0, %1}"
3306 [(set_attr "type" "imovx")
3307 (set_attr "mode" "SI")])
3309 (define_insn "*extendqisi2_zext"
3310 [(set (match_operand:DI 0 "register_operand" "=r")
3312 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3314 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3315 [(set_attr "type" "imovx")
3316 (set_attr "mode" "SI")])
3318 ;; Conversions between float and double.
3320 ;; These are all no-ops in the model used for the 80387. So just
3323 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3324 (define_insn "*dummy_extendsfdf2"
3325 [(set (match_operand:DF 0 "push_operand" "=<")
3326 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3331 [(set (match_operand:DF 0 "push_operand" "")
3332 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3333 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3334 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3335 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3338 [(set (match_operand:DF 0 "push_operand" "")
3339 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3340 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3341 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3342 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3344 (define_insn "*dummy_extendsfxf2"
3345 [(set (match_operand:XF 0 "push_operand" "=<")
3346 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3351 [(set (match_operand:XF 0 "push_operand" "")
3352 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3353 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3354 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3355 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3357 (define_insn "*dummy_extendsftf2"
3358 [(set (match_operand:TF 0 "push_operand" "=<")
3359 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3364 [(set (match_operand:TF 0 "push_operand" "")
3365 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3366 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3367 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3368 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3371 [(set (match_operand:TF 0 "push_operand" "")
3372 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3373 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3374 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3375 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3377 (define_insn "*dummy_extenddfxf2"
3378 [(set (match_operand:XF 0 "push_operand" "=<")
3379 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3384 [(set (match_operand:XF 0 "push_operand" "")
3385 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
3386 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3387 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3388 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3390 (define_insn "*dummy_extenddftf2"
3391 [(set (match_operand:TF 0 "push_operand" "=<")
3392 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3397 [(set (match_operand:TF 0 "push_operand" "")
3398 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3399 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3400 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3401 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3404 [(set (match_operand:TF 0 "push_operand" "")
3405 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3406 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3407 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3408 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3410 (define_expand "extendsfdf2"
3411 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3412 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3413 "TARGET_80387 || TARGET_SSE2"
3415 /* ??? Needed for compress_float_constant since all fp constants
3416 are LEGITIMATE_CONSTANT_P. */
3417 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3418 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3419 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3420 operands[1] = force_reg (SFmode, operands[1]);
3423 (define_insn "*extendsfdf2_1"
3424 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3425 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3426 "(TARGET_80387 || TARGET_SSE2)
3427 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3429 switch (which_alternative)
3432 if (REG_P (operands[1])
3433 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3435 else if (STACK_TOP_P (operands[0]))
3436 return "fld%z1\t%y1";
3441 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3442 return "fstp%z0\t%y0";
3445 return "fst%z0\t%y0";
3447 return "cvtss2sd\t{%1, %0|%0, %1}";
3453 [(set_attr "type" "fmov,fmov,ssecvt")
3454 (set_attr "mode" "SF,XF,DF")])
3456 (define_insn "*extendsfdf2_1_sse_only"
3457 [(set (match_operand:DF 0 "register_operand" "=Y")
3458 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3459 "!TARGET_80387 && TARGET_SSE2
3460 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3461 "cvtss2sd\t{%1, %0|%0, %1}"
3462 [(set_attr "type" "ssecvt")
3463 (set_attr "mode" "DF")])
3465 (define_expand "extendsfxf2"
3466 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3467 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3468 "!TARGET_64BIT && TARGET_80387"
3470 /* ??? Needed for compress_float_constant since all fp constants
3471 are LEGITIMATE_CONSTANT_P. */
3472 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3473 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3474 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3475 operands[1] = force_reg (SFmode, operands[1]);
3478 (define_insn "*extendsfxf2_1"
3479 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3480 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3481 "!TARGET_64BIT && TARGET_80387
3482 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3484 switch (which_alternative)
3487 if (REG_P (operands[1])
3488 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3490 else if (STACK_TOP_P (operands[0]))
3491 return "fld%z1\t%y1";
3496 /* There is no non-popping store to memory for XFmode. So if
3497 we need one, follow the store with a load. */
3498 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3499 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3501 return "fstp%z0\t%y0";
3507 [(set_attr "type" "fmov")
3508 (set_attr "mode" "SF,XF")])
3510 (define_expand "extendsftf2"
3511 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3512 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3515 /* ??? Needed for compress_float_constant since all fp constants
3516 are LEGITIMATE_CONSTANT_P. */
3517 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3518 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3519 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3520 operands[1] = force_reg (SFmode, operands[1]);
3523 (define_insn "*extendsftf2_1"
3524 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3525 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3527 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3529 switch (which_alternative)
3532 if (REG_P (operands[1])
3533 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3535 else if (STACK_TOP_P (operands[0]))
3536 return "fld%z1\t%y1";
3541 /* There is no non-popping store to memory for XFmode. So if
3542 we need one, follow the store with a load. */
3543 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3544 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3546 return "fstp%z0\t%y0";
3552 [(set_attr "type" "fmov")
3553 (set_attr "mode" "SF,XF")])
3555 (define_expand "extenddfxf2"
3556 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3557 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3558 "!TARGET_64BIT && TARGET_80387"
3560 /* ??? Needed for compress_float_constant since all fp constants
3561 are LEGITIMATE_CONSTANT_P. */
3562 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3563 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3564 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3565 operands[1] = force_reg (DFmode, operands[1]);
3568 (define_insn "*extenddfxf2_1"
3569 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3570 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3571 "!TARGET_64BIT && TARGET_80387
3572 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3574 switch (which_alternative)
3577 if (REG_P (operands[1])
3578 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3580 else if (STACK_TOP_P (operands[0]))
3581 return "fld%z1\t%y1";
3586 /* There is no non-popping store to memory for XFmode. So if
3587 we need one, follow the store with a load. */
3588 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3589 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3591 return "fstp%z0\t%y0";
3597 [(set_attr "type" "fmov")
3598 (set_attr "mode" "DF,XF")])
3600 (define_expand "extenddftf2"
3601 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3602 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3605 /* ??? Needed for compress_float_constant since all fp constants
3606 are LEGITIMATE_CONSTANT_P. */
3607 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3608 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3609 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3610 operands[1] = force_reg (DFmode, operands[1]);
3613 (define_insn "*extenddftf2_1"
3614 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3615 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3617 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3619 switch (which_alternative)
3622 if (REG_P (operands[1])
3623 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3625 else if (STACK_TOP_P (operands[0]))
3626 return "fld%z1\t%y1";
3631 /* There is no non-popping store to memory for XFmode. So if
3632 we need one, follow the store with a load. */
3633 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3634 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3636 return "fstp%z0\t%y0";
3642 [(set_attr "type" "fmov")
3643 (set_attr "mode" "DF,XF")])
3645 ;; %%% This seems bad bad news.
3646 ;; This cannot output into an f-reg because there is no way to be sure
3647 ;; of truncating in that case. Otherwise this is just like a simple move
3648 ;; insn. So we pretend we can output to a reg in order to get better
3649 ;; register preferencing, but we really use a stack slot.
3651 (define_expand "truncdfsf2"
3652 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3654 (match_operand:DF 1 "register_operand" "")))
3655 (clobber (match_dup 2))])]
3656 "TARGET_80387 || TARGET_SSE2"
3659 operands[2] = assign_386_stack_local (SFmode, 0);
3662 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3667 (define_insn "*truncdfsf2_1"
3668 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3670 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3671 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3672 "TARGET_80387 && !TARGET_SSE2"
3674 switch (which_alternative)
3677 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3678 return "fstp%z0\t%y0";
3680 return "fst%z0\t%y0";
3685 [(set_attr "type" "fmov,multi,multi,multi")
3686 (set_attr "mode" "SF,SF,SF,SF")])
3688 (define_insn "*truncdfsf2_1_sse"
3689 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
3691 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
3692 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3693 "TARGET_80387 && TARGET_SSE2"
3695 switch (which_alternative)
3698 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3699 return "fstp%z0\t%y0";
3701 return "fst%z0\t%y0";
3703 return "cvtsd2ss\t{%1, %0|%0, %1}";
3708 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3709 (set_attr "mode" "SF,SF,SF,SF,DF")])
3711 (define_insn "*truncdfsf2_2"
3712 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
3714 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3715 "TARGET_80387 && TARGET_SSE2
3716 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3718 switch (which_alternative)
3721 return "cvtsd2ss\t{%1, %0|%0, %1}";
3723 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3724 return "fstp%z0\t%y0";
3726 return "fst%z0\t%y0";
3731 [(set_attr "type" "ssecvt,fmov")
3732 (set_attr "mode" "DF,SF")])
3734 (define_insn "truncdfsf2_3"
3735 [(set (match_operand:SF 0 "memory_operand" "=m")
3737 (match_operand:DF 1 "register_operand" "f")))]
3740 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3741 return "fstp%z0\t%y0";
3743 return "fst%z0\t%y0";
3745 [(set_attr "type" "fmov")
3746 (set_attr "mode" "SF")])
3748 (define_insn "truncdfsf2_sse_only"
3749 [(set (match_operand:SF 0 "register_operand" "=Y")
3751 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3752 "!TARGET_80387 && TARGET_SSE2"
3753 "cvtsd2ss\t{%1, %0|%0, %1}"
3754 [(set_attr "type" "ssecvt")
3755 (set_attr "mode" "DF")])
3758 [(set (match_operand:SF 0 "memory_operand" "")
3760 (match_operand:DF 1 "register_operand" "")))
3761 (clobber (match_operand:SF 2 "memory_operand" ""))]
3763 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3767 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3769 (match_operand:DF 1 "nonimmediate_operand" "")))
3770 (clobber (match_operand 2 "" ""))]
3771 "TARGET_80387 && reload_completed
3772 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
3773 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3777 [(set (match_operand:SF 0 "register_operand" "")
3779 (match_operand:DF 1 "register_operand" "")))
3780 (clobber (match_operand:SF 2 "memory_operand" ""))]
3781 "TARGET_80387 && reload_completed
3782 && FP_REG_P (operands[1])"
3783 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3784 (set (match_dup 0) (match_dup 2))]
3787 (define_expand "truncxfsf2"
3788 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3790 (match_operand:XF 1 "register_operand" "")))
3791 (clobber (match_dup 2))])]
3792 "!TARGET_64BIT && TARGET_80387"
3793 "operands[2] = assign_386_stack_local (SFmode, 0);")
3795 (define_insn "*truncxfsf2_1"
3796 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3798 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3799 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3800 "!TARGET_64BIT && TARGET_80387"
3802 switch (which_alternative)
3805 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3806 return "fstp%z0\t%y0";
3808 return "fst%z0\t%y0";
3813 [(set_attr "type" "fmov,multi,multi,multi")
3814 (set_attr "mode" "SF")])
3816 (define_insn "*truncxfsf2_2"
3817 [(set (match_operand:SF 0 "memory_operand" "=m")
3819 (match_operand:XF 1 "register_operand" "f")))]
3820 "!TARGET_64BIT && TARGET_80387"
3822 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3823 return "fstp%z0\t%y0";
3825 return "fst%z0\t%y0";
3827 [(set_attr "type" "fmov")
3828 (set_attr "mode" "SF")])
3831 [(set (match_operand:SF 0 "memory_operand" "")
3833 (match_operand:XF 1 "register_operand" "")))
3834 (clobber (match_operand:SF 2 "memory_operand" ""))]
3836 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3840 [(set (match_operand:SF 0 "register_operand" "")
3842 (match_operand:XF 1 "register_operand" "")))
3843 (clobber (match_operand:SF 2 "memory_operand" ""))]
3844 "TARGET_80387 && reload_completed"
3845 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3846 (set (match_dup 0) (match_dup 2))]
3849 (define_expand "trunctfsf2"
3850 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3852 (match_operand:TF 1 "register_operand" "")))
3853 (clobber (match_dup 2))])]
3855 "operands[2] = assign_386_stack_local (SFmode, 0);")
3857 (define_insn "*trunctfsf2_1"
3858 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3860 (match_operand:TF 1 "register_operand" "f,f,f,f")))
3861 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3864 switch (which_alternative)
3867 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3868 return "fstp%z0\t%y0";
3870 return "fst%z0\t%y0";
3875 [(set_attr "type" "fmov,multi,multi,multi")
3876 (set_attr "mode" "SF")])
3878 (define_insn "*trunctfsf2_2"
3879 [(set (match_operand:SF 0 "memory_operand" "=m")
3881 (match_operand:TF 1 "register_operand" "f")))]
3884 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3885 return "fstp%z0\t%y0";
3887 return "fst%z0\t%y0";
3889 [(set_attr "type" "fmov")
3890 (set_attr "mode" "SF")])
3893 [(set (match_operand:SF 0 "memory_operand" "")
3895 (match_operand:TF 1 "register_operand" "")))
3896 (clobber (match_operand:SF 2 "memory_operand" ""))]
3898 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3902 [(set (match_operand:SF 0 "register_operand" "")
3904 (match_operand:TF 1 "register_operand" "")))
3905 (clobber (match_operand:SF 2 "memory_operand" ""))]
3906 "TARGET_80387 && reload_completed"
3907 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3908 (set (match_dup 0) (match_dup 2))]
3912 (define_expand "truncxfdf2"
3913 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3915 (match_operand:XF 1 "register_operand" "")))
3916 (clobber (match_dup 2))])]
3917 "!TARGET_64BIT && TARGET_80387"
3918 "operands[2] = assign_386_stack_local (DFmode, 0);")
3920 (define_insn "*truncxfdf2_1"
3921 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3923 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3924 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3925 "!TARGET_64BIT && TARGET_80387"
3927 switch (which_alternative)
3930 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3931 return "fstp%z0\t%y0";
3933 return "fst%z0\t%y0";
3939 [(set_attr "type" "fmov,multi,multi,multi")
3940 (set_attr "mode" "DF")])
3942 (define_insn "*truncxfdf2_2"
3943 [(set (match_operand:DF 0 "memory_operand" "=m")
3945 (match_operand:XF 1 "register_operand" "f")))]
3946 "!TARGET_64BIT && TARGET_80387"
3948 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3949 return "fstp%z0\t%y0";
3951 return "fst%z0\t%y0";
3953 [(set_attr "type" "fmov")
3954 (set_attr "mode" "DF")])
3957 [(set (match_operand:DF 0 "memory_operand" "")
3959 (match_operand:XF 1 "register_operand" "")))
3960 (clobber (match_operand:DF 2 "memory_operand" ""))]
3962 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
3966 [(set (match_operand:DF 0 "register_operand" "")
3968 (match_operand:XF 1 "register_operand" "")))
3969 (clobber (match_operand:DF 2 "memory_operand" ""))]
3970 "TARGET_80387 && reload_completed"
3971 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
3972 (set (match_dup 0) (match_dup 2))]
3975 (define_expand "trunctfdf2"
3976 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3978 (match_operand:TF 1 "register_operand" "")))
3979 (clobber (match_dup 2))])]
3981 "operands[2] = assign_386_stack_local (DFmode, 0);")
3983 (define_insn "*trunctfdf2_1"
3984 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3986 (match_operand:TF 1 "register_operand" "f,f,f,f")))
3987 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3990 switch (which_alternative)
3993 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3994 return "fstp%z0\t%y0";
3996 return "fst%z0\t%y0";
4002 [(set_attr "type" "fmov,multi,multi,multi")
4003 (set_attr "mode" "DF")])
4005 (define_insn "*trunctfdf2_2"
4006 [(set (match_operand:DF 0 "memory_operand" "=m")
4008 (match_operand:TF 1 "register_operand" "f")))]
4011 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4012 return "fstp%z0\t%y0";
4014 return "fst%z0\t%y0";
4016 [(set_attr "type" "fmov")
4017 (set_attr "mode" "DF")])
4020 [(set (match_operand:DF 0 "memory_operand" "")
4022 (match_operand:TF 1 "register_operand" "")))
4023 (clobber (match_operand:DF 2 "memory_operand" ""))]
4025 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4029 [(set (match_operand:DF 0 "register_operand" "")
4031 (match_operand:TF 1 "register_operand" "")))
4032 (clobber (match_operand:DF 2 "memory_operand" ""))]
4033 "TARGET_80387 && reload_completed"
4034 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4035 (set (match_dup 0) (match_dup 2))]
4039 ;; %%% Break up all these bad boys.
4041 ;; Signed conversion to DImode.
4043 (define_expand "fix_truncxfdi2"
4044 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4045 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4046 "!TARGET_64BIT && TARGET_80387"
4049 (define_expand "fix_trunctfdi2"
4050 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4051 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4055 (define_expand "fix_truncdfdi2"
4056 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4057 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4058 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4060 if (TARGET_64BIT && TARGET_SSE2)
4062 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4063 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4064 if (out != operands[0])
4065 emit_move_insn (operands[0], out);
4070 (define_expand "fix_truncsfdi2"
4071 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4072 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4073 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4075 if (TARGET_SSE && TARGET_64BIT)
4077 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4078 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4079 if (out != operands[0])
4080 emit_move_insn (operands[0], out);
4085 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4086 ;; of the machinery.
4087 (define_insn_and_split "*fix_truncdi_1"
4088 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4089 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4090 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4091 && !reload_completed && !reload_in_progress
4092 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4097 operands[2] = assign_386_stack_local (HImode, 1);
4098 operands[3] = assign_386_stack_local (HImode, 2);
4099 if (memory_operand (operands[0], VOIDmode))
4100 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4101 operands[2], operands[3]));
4104 operands[4] = assign_386_stack_local (DImode, 0);
4105 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4106 operands[2], operands[3],
4111 [(set_attr "type" "fistp")])
4113 (define_insn "fix_truncdi_nomemory"
4114 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4115 (fix:DI (match_operand 1 "register_operand" "f,f")))
4116 (use (match_operand:HI 2 "memory_operand" "m,m"))
4117 (use (match_operand:HI 3 "memory_operand" "m,m"))
4118 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4119 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4120 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4121 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4123 [(set_attr "type" "fistp")])
4125 (define_insn "fix_truncdi_memory"
4126 [(set (match_operand:DI 0 "memory_operand" "=m")
4127 (fix:DI (match_operand 1 "register_operand" "f")))
4128 (use (match_operand:HI 2 "memory_operand" "m"))
4129 (use (match_operand:HI 3 "memory_operand" "m"))
4130 (clobber (match_scratch:DF 4 "=&1f"))]
4131 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4132 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4133 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4134 [(set_attr "type" "fistp")])
4137 [(set (match_operand:DI 0 "register_operand" "")
4138 (fix:DI (match_operand 1 "register_operand" "")))
4139 (use (match_operand:HI 2 "memory_operand" ""))
4140 (use (match_operand:HI 3 "memory_operand" ""))
4141 (clobber (match_operand:DI 4 "memory_operand" ""))
4142 (clobber (match_scratch 5 ""))]
4144 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4147 (clobber (match_dup 5))])
4148 (set (match_dup 0) (match_dup 4))]
4152 [(set (match_operand:DI 0 "memory_operand" "")
4153 (fix:DI (match_operand 1 "register_operand" "")))
4154 (use (match_operand:HI 2 "memory_operand" ""))
4155 (use (match_operand:HI 3 "memory_operand" ""))
4156 (clobber (match_operand:DI 4 "memory_operand" ""))
4157 (clobber (match_scratch 5 ""))]
4159 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4162 (clobber (match_dup 5))])]
4165 ;; When SSE available, it is always faster to use it!
4166 (define_insn "fix_truncsfdi_sse"
4167 [(set (match_operand:DI 0 "register_operand" "=r")
4168 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4169 "TARGET_64BIT && TARGET_SSE"
4170 "cvttss2si{q}\t{%1, %0|%0, %1}"
4171 [(set_attr "type" "ssecvt")])
4173 (define_insn "fix_truncdfdi_sse"
4174 [(set (match_operand:DI 0 "register_operand" "=r")
4175 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4176 "TARGET_64BIT && TARGET_SSE2"
4177 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4178 [(set_attr "type" "ssecvt")])
4180 ;; Signed conversion to SImode.
4182 (define_expand "fix_truncxfsi2"
4183 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4184 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4185 "!TARGET_64BIT && TARGET_80387"
4188 (define_expand "fix_trunctfsi2"
4189 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4190 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4194 (define_expand "fix_truncdfsi2"
4195 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4196 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4197 "TARGET_80387 || TARGET_SSE2"
4201 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4202 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4203 if (out != operands[0])
4204 emit_move_insn (operands[0], out);
4209 (define_expand "fix_truncsfsi2"
4210 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4211 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4212 "TARGET_80387 || TARGET_SSE"
4216 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4217 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4218 if (out != operands[0])
4219 emit_move_insn (operands[0], out);
4224 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4225 ;; of the machinery.
4226 (define_insn_and_split "*fix_truncsi_1"
4227 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4228 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4229 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4230 && !reload_completed && !reload_in_progress
4231 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4236 operands[2] = assign_386_stack_local (HImode, 1);
4237 operands[3] = assign_386_stack_local (HImode, 2);
4238 if (memory_operand (operands[0], VOIDmode))
4239 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4240 operands[2], operands[3]));
4243 operands[4] = assign_386_stack_local (SImode, 0);
4244 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4245 operands[2], operands[3],
4250 [(set_attr "type" "fistp")])
4252 (define_insn "fix_truncsi_nomemory"
4253 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4254 (fix:SI (match_operand 1 "register_operand" "f,f")))
4255 (use (match_operand:HI 2 "memory_operand" "m,m"))
4256 (use (match_operand:HI 3 "memory_operand" "m,m"))
4257 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4258 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4259 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4261 [(set_attr "type" "fistp")])
4263 (define_insn "fix_truncsi_memory"
4264 [(set (match_operand:SI 0 "memory_operand" "=m")
4265 (fix:SI (match_operand 1 "register_operand" "f")))
4266 (use (match_operand:HI 2 "memory_operand" "m"))
4267 (use (match_operand:HI 3 "memory_operand" "m"))]
4268 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4269 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4270 "* return output_fix_trunc (insn, operands);"
4271 [(set_attr "type" "fistp")])
4273 ;; When SSE available, it is always faster to use it!
4274 (define_insn "fix_truncsfsi_sse"
4275 [(set (match_operand:SI 0 "register_operand" "=r")
4276 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4278 "cvttss2si\t{%1, %0|%0, %1}"
4279 [(set_attr "type" "ssecvt")])
4281 (define_insn "fix_truncdfsi_sse"
4282 [(set (match_operand:SI 0 "register_operand" "=r")
4283 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4285 "cvttsd2si\t{%1, %0|%0, %1}"
4286 [(set_attr "type" "ssecvt")])
4289 [(set (match_operand:SI 0 "register_operand" "")
4290 (fix:SI (match_operand 1 "register_operand" "")))
4291 (use (match_operand:HI 2 "memory_operand" ""))
4292 (use (match_operand:HI 3 "memory_operand" ""))
4293 (clobber (match_operand:SI 4 "memory_operand" ""))]
4295 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4297 (use (match_dup 3))])
4298 (set (match_dup 0) (match_dup 4))]
4302 [(set (match_operand:SI 0 "memory_operand" "")
4303 (fix:SI (match_operand 1 "register_operand" "")))
4304 (use (match_operand:HI 2 "memory_operand" ""))
4305 (use (match_operand:HI 3 "memory_operand" ""))
4306 (clobber (match_operand:SI 4 "memory_operand" ""))]
4308 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4310 (use (match_dup 3))])]
4313 ;; Signed conversion to HImode.
4315 (define_expand "fix_truncxfhi2"
4316 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4317 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4318 "!TARGET_64BIT && TARGET_80387"
4321 (define_expand "fix_trunctfhi2"
4322 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4323 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4327 (define_expand "fix_truncdfhi2"
4328 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4329 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4330 "TARGET_80387 && !TARGET_SSE2"
4333 (define_expand "fix_truncsfhi2"
4334 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4335 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4336 "TARGET_80387 && !TARGET_SSE"
4339 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4340 ;; of the machinery.
4341 (define_insn_and_split "*fix_trunchi_1"
4342 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4343 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4344 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4345 && !reload_completed && !reload_in_progress
4346 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4351 operands[2] = assign_386_stack_local (HImode, 1);
4352 operands[3] = assign_386_stack_local (HImode, 2);
4353 if (memory_operand (operands[0], VOIDmode))
4354 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4355 operands[2], operands[3]));
4358 operands[4] = assign_386_stack_local (HImode, 0);
4359 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4360 operands[2], operands[3],
4365 [(set_attr "type" "fistp")])
4367 (define_insn "fix_trunchi_nomemory"
4368 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4369 (fix:HI (match_operand 1 "register_operand" "f,f")))
4370 (use (match_operand:HI 2 "memory_operand" "m,m"))
4371 (use (match_operand:HI 3 "memory_operand" "m,m"))
4372 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4373 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4374 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4376 [(set_attr "type" "fistp")])
4378 (define_insn "fix_trunchi_memory"
4379 [(set (match_operand:HI 0 "memory_operand" "=m")
4380 (fix:HI (match_operand 1 "register_operand" "f")))
4381 (use (match_operand:HI 2 "memory_operand" "m"))
4382 (use (match_operand:HI 3 "memory_operand" "m"))]
4383 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4384 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4385 "* return output_fix_trunc (insn, operands);"
4386 [(set_attr "type" "fistp")])
4389 [(set (match_operand:HI 0 "memory_operand" "")
4390 (fix:HI (match_operand 1 "register_operand" "")))
4391 (use (match_operand:HI 2 "memory_operand" ""))
4392 (use (match_operand:HI 3 "memory_operand" ""))
4393 (clobber (match_operand:HI 4 "memory_operand" ""))]
4395 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4397 (use (match_dup 3))])]
4401 [(set (match_operand:HI 0 "register_operand" "")
4402 (fix:HI (match_operand 1 "register_operand" "")))
4403 (use (match_operand:HI 2 "memory_operand" ""))
4404 (use (match_operand:HI 3 "memory_operand" ""))
4405 (clobber (match_operand:HI 4 "memory_operand" ""))]
4407 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4410 (clobber (match_dup 4))])
4411 (set (match_dup 0) (match_dup 4))]
4415 (define_insn "x86_fnstcw_1"
4416 [(set (match_operand:HI 0 "memory_operand" "=m")
4417 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4420 [(set_attr "length" "2")
4421 (set_attr "mode" "HI")
4422 (set_attr "unit" "i387")
4423 (set_attr "ppro_uops" "few")])
4425 (define_insn "x86_fldcw_1"
4427 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4430 [(set_attr "length" "2")
4431 (set_attr "mode" "HI")
4432 (set_attr "unit" "i387")
4433 (set_attr "athlon_decode" "vector")
4434 (set_attr "ppro_uops" "few")])
4436 ;; Conversion between fixed point and floating point.
4438 ;; Even though we only accept memory inputs, the backend _really_
4439 ;; wants to be able to do this between registers.
4441 (define_insn "floathisf2"
4442 [(set (match_operand:SF 0 "register_operand" "=f,f")
4443 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4444 "TARGET_80387 && !TARGET_SSE"
4448 [(set_attr "type" "fmov,multi")
4449 (set_attr "mode" "SF")
4450 (set_attr "fp_int_src" "true")])
4452 (define_expand "floatsisf2"
4453 [(set (match_operand:SF 0 "register_operand" "")
4454 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4455 "TARGET_SSE || TARGET_80387"
4458 (define_insn "*floatsisf2_i387"
4459 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4460 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4461 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4465 cvtsi2ss\t{%1, %0|%0, %1}"
4466 [(set_attr "type" "fmov,multi,ssecvt")
4467 (set_attr "mode" "SF")
4468 (set_attr "fp_int_src" "true")])
4470 (define_insn "*floatsisf2_sse"
4471 [(set (match_operand:SF 0 "register_operand" "=x")
4472 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4474 "cvtsi2ss\t{%1, %0|%0, %1}"
4475 [(set_attr "type" "ssecvt")
4476 (set_attr "mode" "SF")
4477 (set_attr "fp_int_src" "true")])
4479 (define_expand "floatdisf2"
4480 [(set (match_operand:SF 0 "register_operand" "")
4481 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4482 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4485 (define_insn "*floatdisf2_i387_only"
4486 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4487 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4488 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4492 [(set_attr "type" "fmov,multi")
4493 (set_attr "mode" "SF")
4494 (set_attr "fp_int_src" "true")])
4496 (define_insn "*floatdisf2_i387"
4497 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4498 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4499 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4503 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4504 [(set_attr "type" "fmov,multi,ssecvt")
4505 (set_attr "mode" "SF")
4506 (set_attr "fp_int_src" "true")])
4508 (define_insn "*floatdisf2_sse"
4509 [(set (match_operand:SF 0 "register_operand" "=x")
4510 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4511 "TARGET_64BIT && TARGET_SSE"
4512 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4513 [(set_attr "type" "ssecvt")
4514 (set_attr "mode" "SF")
4515 (set_attr "fp_int_src" "true")])
4517 (define_insn "floathidf2"
4518 [(set (match_operand:DF 0 "register_operand" "=f,f")
4519 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4520 "TARGET_80387 && !TARGET_SSE2"
4524 [(set_attr "type" "fmov,multi")
4525 (set_attr "mode" "DF")
4526 (set_attr "fp_int_src" "true")])
4528 (define_expand "floatsidf2"
4529 [(set (match_operand:DF 0 "register_operand" "")
4530 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4531 "TARGET_80387 || TARGET_SSE2"
4534 (define_insn "*floatsidf2_i387"
4535 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4536 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4537 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4541 cvtsi2sd\t{%1, %0|%0, %1}"
4542 [(set_attr "type" "fmov,multi,ssecvt")
4543 (set_attr "mode" "DF")
4544 (set_attr "fp_int_src" "true")])
4546 (define_insn "*floatsidf2_sse"
4547 [(set (match_operand:DF 0 "register_operand" "=Y")
4548 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4550 "cvtsi2sd\t{%1, %0|%0, %1}"
4551 [(set_attr "type" "ssecvt")
4552 (set_attr "mode" "DF")
4553 (set_attr "fp_int_src" "true")])
4555 (define_expand "floatdidf2"
4556 [(set (match_operand:DF 0 "register_operand" "")
4557 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4558 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4561 (define_insn "*floatdidf2_i387_only"
4562 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4563 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4564 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4568 [(set_attr "type" "fmov,multi")
4569 (set_attr "mode" "DF")
4570 (set_attr "fp_int_src" "true")])
4572 (define_insn "*floatdidf2_i387"
4573 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4574 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4575 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4579 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4580 [(set_attr "type" "fmov,multi,ssecvt")
4581 (set_attr "mode" "DF")
4582 (set_attr "fp_int_src" "true")])
4584 (define_insn "*floatdidf2_sse"
4585 [(set (match_operand:DF 0 "register_operand" "=Y")
4586 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4588 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4589 [(set_attr "type" "ssecvt")
4590 (set_attr "mode" "DF")
4591 (set_attr "fp_int_src" "true")])
4593 (define_insn "floathixf2"
4594 [(set (match_operand:XF 0 "register_operand" "=f,f")
4595 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4596 "!TARGET_64BIT && TARGET_80387"
4600 [(set_attr "type" "fmov,multi")
4601 (set_attr "mode" "XF")
4602 (set_attr "fp_int_src" "true")])
4604 (define_insn "floathitf2"
4605 [(set (match_operand:TF 0 "register_operand" "=f,f")
4606 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4611 [(set_attr "type" "fmov,multi")
4612 (set_attr "mode" "XF")
4613 (set_attr "fp_int_src" "true")])
4615 (define_insn "floatsixf2"
4616 [(set (match_operand:XF 0 "register_operand" "=f,f")
4617 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4618 "!TARGET_64BIT && TARGET_80387"
4622 [(set_attr "type" "fmov,multi")
4623 (set_attr "mode" "XF")
4624 (set_attr "fp_int_src" "true")])
4626 (define_insn "floatsitf2"
4627 [(set (match_operand:TF 0 "register_operand" "=f,f")
4628 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4633 [(set_attr "type" "fmov,multi")
4634 (set_attr "mode" "XF")
4635 (set_attr "fp_int_src" "true")])
4637 (define_insn "floatdixf2"
4638 [(set (match_operand:XF 0 "register_operand" "=f,f")
4639 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4640 "!TARGET_64BIT && TARGET_80387"
4644 [(set_attr "type" "fmov,multi")
4645 (set_attr "mode" "XF")
4646 (set_attr "fp_int_src" "true")])
4648 (define_insn "floatditf2"
4649 [(set (match_operand:TF 0 "register_operand" "=f,f")
4650 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4655 [(set_attr "type" "fmov,multi")
4656 (set_attr "mode" "XF")
4657 (set_attr "fp_int_src" "true")])
4659 ;; %%% Kill these when reload knows how to do it.
4661 [(set (match_operand 0 "register_operand" "")
4662 (float (match_operand 1 "register_operand" "")))]
4663 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
4664 && FP_REG_P (operands[0])"
4667 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4668 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4669 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4670 ix86_free_from_memory (GET_MODE (operands[1]));
4676 ;; %%% splits for addsidi3
4677 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4678 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4679 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4681 (define_expand "adddi3"
4682 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4683 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4684 (match_operand:DI 2 "x86_64_general_operand" "")))
4685 (clobber (reg:CC 17))]
4687 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4689 (define_insn "*adddi3_1"
4690 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4691 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4692 (match_operand:DI 2 "general_operand" "roiF,riF")))
4693 (clobber (reg:CC 17))]
4698 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4699 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4700 (match_operand:DI 2 "general_operand" "")))
4701 (clobber (reg:CC 17))]
4702 "!TARGET_64BIT && reload_completed"
4703 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
4705 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4706 (parallel [(set (match_dup 3)
4707 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4710 (clobber (reg:CC 17))])]
4711 "split_di (operands+0, 1, operands+0, operands+3);
4712 split_di (operands+1, 1, operands+1, operands+4);
4713 split_di (operands+2, 1, operands+2, operands+5);")
4715 (define_insn "*adddi3_carry_rex64"
4716 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4717 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
4718 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4719 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4720 (clobber (reg:CC 17))]
4721 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4722 "adc{q}\t{%2, %0|%0, %2}"
4723 [(set_attr "type" "alu")
4724 (set_attr "pent_pair" "pu")
4725 (set_attr "mode" "DI")
4726 (set_attr "ppro_uops" "few")])
4728 (define_insn "*adddi3_cc_rex64"
4730 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4731 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4733 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4734 (plus:DI (match_dup 1) (match_dup 2)))]
4735 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4736 "add{q}\t{%2, %0|%0, %2}"
4737 [(set_attr "type" "alu")
4738 (set_attr "mode" "DI")])
4740 (define_insn "*addsi3_carry"
4741 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4742 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4743 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4744 (match_operand:SI 2 "general_operand" "ri,rm")))
4745 (clobber (reg:CC 17))]
4746 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4747 "adc{l}\t{%2, %0|%0, %2}"
4748 [(set_attr "type" "alu")
4749 (set_attr "pent_pair" "pu")
4750 (set_attr "mode" "SI")
4751 (set_attr "ppro_uops" "few")])
4753 (define_insn "*addsi3_carry_zext"
4754 [(set (match_operand:DI 0 "register_operand" "=r")
4756 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4757 (match_operand:SI 1 "nonimmediate_operand" "%0"))
4758 (match_operand:SI 2 "general_operand" "rim"))))
4759 (clobber (reg:CC 17))]
4760 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
4761 "adc{l}\t{%2, %k0|%k0, %2}"
4762 [(set_attr "type" "alu")
4763 (set_attr "pent_pair" "pu")
4764 (set_attr "mode" "SI")
4765 (set_attr "ppro_uops" "few")])
4767 (define_insn "*addsi3_cc"
4769 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
4770 (match_operand:SI 2 "general_operand" "ri,rm")]
4772 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4773 (plus:SI (match_dup 1) (match_dup 2)))]
4774 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4775 "add{l}\t{%2, %0|%0, %2}"
4776 [(set_attr "type" "alu")
4777 (set_attr "mode" "SI")])
4779 (define_insn "addqi3_cc"
4781 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
4782 (match_operand:QI 2 "general_operand" "qi,qm")]
4784 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4785 (plus:QI (match_dup 1) (match_dup 2)))]
4786 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4787 "add{b}\t{%2, %0|%0, %2}"
4788 [(set_attr "type" "alu")
4789 (set_attr "mode" "QI")])
4791 (define_expand "addsi3"
4792 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4793 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4794 (match_operand:SI 2 "general_operand" "")))
4795 (clobber (reg:CC 17))])]
4797 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
4799 (define_insn "*lea_1"
4800 [(set (match_operand:SI 0 "register_operand" "=r")
4801 (match_operand:SI 1 "address_operand" "p"))]
4803 "lea{l}\t{%a1, %0|%0, %a1}"
4804 [(set_attr "type" "lea")
4805 (set_attr "mode" "SI")])
4807 (define_insn "*lea_1_rex64"
4808 [(set (match_operand:SI 0 "register_operand" "=r")
4809 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
4811 "lea{l}\t{%a1, %0|%0, %a1}"
4812 [(set_attr "type" "lea")
4813 (set_attr "mode" "SI")])
4815 (define_insn "*lea_1_zext"
4816 [(set (match_operand:DI 0 "register_operand" "=r")
4817 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
4819 "lea{l}\t{%a1, %k0|%k0, %a1}"
4820 [(set_attr "type" "lea")
4821 (set_attr "mode" "SI")])
4823 (define_insn "*lea_2_rex64"
4824 [(set (match_operand:DI 0 "register_operand" "=r")
4825 (match_operand:DI 1 "address_operand" "p"))]
4827 "lea{q}\t{%a1, %0|%0, %a1}"
4828 [(set_attr "type" "lea")
4829 (set_attr "mode" "DI")])
4831 ;; The lea patterns for non-Pmodes needs to be matched by several
4832 ;; insns converted to real lea by splitters.
4834 (define_insn_and_split "*lea_general_1"
4835 [(set (match_operand 0 "register_operand" "=r")
4836 (plus (plus (match_operand 1 "register_operand" "r")
4837 (match_operand 2 "register_operand" "r"))
4838 (match_operand 3 "immediate_operand" "i")))]
4839 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4840 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4841 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4842 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4843 && GET_MODE (operands[0]) == GET_MODE (operands[2])
4844 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4845 || GET_MODE (operands[3]) == VOIDmode)"
4847 "&& reload_completed"
4851 operands[0] = gen_lowpart (SImode, operands[0]);
4852 operands[1] = gen_lowpart (Pmode, operands[1]);
4853 operands[2] = gen_lowpart (Pmode, operands[2]);
4854 operands[3] = gen_lowpart (Pmode, operands[3]);
4855 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
4857 if (Pmode != SImode)
4858 pat = gen_rtx_SUBREG (SImode, pat, 0);
4859 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4862 [(set_attr "type" "lea")
4863 (set_attr "mode" "SI")])
4865 (define_insn_and_split "*lea_general_1_zext"
4866 [(set (match_operand:DI 0 "register_operand" "=r")
4868 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
4869 (match_operand:SI 2 "register_operand" "r"))
4870 (match_operand:SI 3 "immediate_operand" "i"))))]
4873 "&& reload_completed"
4875 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
4877 (match_dup 3)) 0)))]
4879 operands[1] = gen_lowpart (Pmode, operands[1]);
4880 operands[2] = gen_lowpart (Pmode, operands[2]);
4881 operands[3] = gen_lowpart (Pmode, operands[3]);
4883 [(set_attr "type" "lea")
4884 (set_attr "mode" "SI")])
4886 (define_insn_and_split "*lea_general_2"
4887 [(set (match_operand 0 "register_operand" "=r")
4888 (plus (mult (match_operand 1 "register_operand" "r")
4889 (match_operand 2 "const248_operand" "i"))
4890 (match_operand 3 "nonmemory_operand" "ri")))]
4891 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4892 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4893 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4894 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4895 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4896 || GET_MODE (operands[3]) == VOIDmode)"
4898 "&& reload_completed"
4902 operands[0] = gen_lowpart (SImode, operands[0]);
4903 operands[1] = gen_lowpart (Pmode, operands[1]);
4904 operands[3] = gen_lowpart (Pmode, operands[3]);
4905 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
4907 if (Pmode != SImode)
4908 pat = gen_rtx_SUBREG (SImode, pat, 0);
4909 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4912 [(set_attr "type" "lea")
4913 (set_attr "mode" "SI")])
4915 (define_insn_and_split "*lea_general_2_zext"
4916 [(set (match_operand:DI 0 "register_operand" "=r")
4918 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4919 (match_operand:SI 2 "const248_operand" "n"))
4920 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
4923 "&& reload_completed"
4925 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
4927 (match_dup 3)) 0)))]
4929 operands[1] = gen_lowpart (Pmode, operands[1]);
4930 operands[3] = gen_lowpart (Pmode, operands[3]);
4932 [(set_attr "type" "lea")
4933 (set_attr "mode" "SI")])
4935 (define_insn_and_split "*lea_general_3"
4936 [(set (match_operand 0 "register_operand" "=r")
4937 (plus (plus (mult (match_operand 1 "register_operand" "r")
4938 (match_operand 2 "const248_operand" "i"))
4939 (match_operand 3 "register_operand" "r"))
4940 (match_operand 4 "immediate_operand" "i")))]
4941 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4942 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4943 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4944 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4945 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
4947 "&& reload_completed"
4951 operands[0] = gen_lowpart (SImode, operands[0]);
4952 operands[1] = gen_lowpart (Pmode, operands[1]);
4953 operands[3] = gen_lowpart (Pmode, operands[3]);
4954 operands[4] = gen_lowpart (Pmode, operands[4]);
4955 pat = gen_rtx_PLUS (Pmode,
4956 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
4960 if (Pmode != SImode)
4961 pat = gen_rtx_SUBREG (SImode, pat, 0);
4962 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4965 [(set_attr "type" "lea")
4966 (set_attr "mode" "SI")])
4968 (define_insn_and_split "*lea_general_3_zext"
4969 [(set (match_operand:DI 0 "register_operand" "=r")
4971 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4972 (match_operand:SI 2 "const248_operand" "n"))
4973 (match_operand:SI 3 "register_operand" "r"))
4974 (match_operand:SI 4 "immediate_operand" "i"))))]
4977 "&& reload_completed"
4979 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
4982 (match_dup 4)) 0)))]
4984 operands[1] = gen_lowpart (Pmode, operands[1]);
4985 operands[3] = gen_lowpart (Pmode, operands[3]);
4986 operands[4] = gen_lowpart (Pmode, operands[4]);
4988 [(set_attr "type" "lea")
4989 (set_attr "mode" "SI")])
4991 (define_insn "*adddi_1_rex64"
4992 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
4993 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
4994 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
4995 (clobber (reg:CC 17))]
4996 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4998 switch (get_attr_type (insn))
5001 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5002 return "lea{q}\t{%a2, %0|%0, %a2}";
5005 if (! rtx_equal_p (operands[0], operands[1]))
5007 if (operands[2] == const1_rtx)
5008 return "inc{q}\t%0";
5009 else if (operands[2] == constm1_rtx)
5010 return "dec{q}\t%0";
5015 if (! rtx_equal_p (operands[0], operands[1]))
5018 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5019 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5020 if (GET_CODE (operands[2]) == CONST_INT
5021 /* Avoid overflows. */
5022 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5023 && (INTVAL (operands[2]) == 128
5024 || (INTVAL (operands[2]) < 0
5025 && INTVAL (operands[2]) != -128)))
5027 operands[2] = GEN_INT (-INTVAL (operands[2]));
5028 return "sub{q}\t{%2, %0|%0, %2}";
5030 return "add{q}\t{%2, %0|%0, %2}";
5034 (cond [(eq_attr "alternative" "2")
5035 (const_string "lea")
5036 ; Current assemblers are broken and do not allow @GOTOFF in
5037 ; ought but a memory context.
5038 (match_operand:DI 2 "pic_symbolic_operand" "")
5039 (const_string "lea")
5040 (match_operand:DI 2 "incdec_operand" "")
5041 (const_string "incdec")
5043 (const_string "alu")))
5044 (set_attr "mode" "DI")])
5046 ;; Convert lea to the lea pattern to avoid flags dependency.
5048 [(set (match_operand:DI 0 "register_operand" "")
5049 (plus:DI (match_operand:DI 1 "register_operand" "")
5050 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5051 (clobber (reg:CC 17))]
5052 "TARGET_64BIT && reload_completed
5053 && true_regnum (operands[0]) != true_regnum (operands[1])"
5055 (plus:DI (match_dup 1)
5059 (define_insn "*adddi_2_rex64"
5062 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5063 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5065 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5066 (plus:DI (match_dup 1) (match_dup 2)))]
5067 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5068 && ix86_binary_operator_ok (PLUS, DImode, operands)
5069 /* Current assemblers are broken and do not allow @GOTOFF in
5070 ought but a memory context. */
5071 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5073 switch (get_attr_type (insn))
5076 if (! rtx_equal_p (operands[0], operands[1]))
5078 if (operands[2] == const1_rtx)
5079 return "inc{q}\t%0";
5080 else if (operands[2] == constm1_rtx)
5081 return "dec{q}\t%0";
5086 if (! rtx_equal_p (operands[0], operands[1]))
5088 /* ???? We ought to handle there the 32bit case too
5089 - do we need new constrant? */
5090 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5091 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5092 if (GET_CODE (operands[2]) == CONST_INT
5093 /* Avoid overflows. */
5094 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5095 && (INTVAL (operands[2]) == 128
5096 || (INTVAL (operands[2]) < 0
5097 && INTVAL (operands[2]) != -128)))
5099 operands[2] = GEN_INT (-INTVAL (operands[2]));
5100 return "sub{q}\t{%2, %0|%0, %2}";
5102 return "add{q}\t{%2, %0|%0, %2}";
5106 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5107 (const_string "incdec")
5108 (const_string "alu")))
5109 (set_attr "mode" "DI")])
5111 (define_insn "*adddi_3_rex64"
5113 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5114 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5115 (clobber (match_scratch:DI 0 "=r"))]
5117 && ix86_match_ccmode (insn, CCZmode)
5118 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5119 /* Current assemblers are broken and do not allow @GOTOFF in
5120 ought but a memory context. */
5121 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5123 switch (get_attr_type (insn))
5126 if (! rtx_equal_p (operands[0], operands[1]))
5128 if (operands[2] == const1_rtx)
5129 return "inc{q}\t%0";
5130 else if (operands[2] == constm1_rtx)
5131 return "dec{q}\t%0";
5136 if (! rtx_equal_p (operands[0], operands[1]))
5138 /* ???? We ought to handle there the 32bit case too
5139 - do we need new constrant? */
5140 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5141 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5142 if (GET_CODE (operands[2]) == CONST_INT
5143 /* Avoid overflows. */
5144 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5145 && (INTVAL (operands[2]) == 128
5146 || (INTVAL (operands[2]) < 0
5147 && INTVAL (operands[2]) != -128)))
5149 operands[2] = GEN_INT (-INTVAL (operands[2]));
5150 return "sub{q}\t{%2, %0|%0, %2}";
5152 return "add{q}\t{%2, %0|%0, %2}";
5156 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5157 (const_string "incdec")
5158 (const_string "alu")))
5159 (set_attr "mode" "DI")])
5161 ; For comparisons against 1, -1 and 128, we may generate better code
5162 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5163 ; is matched then. We can't accept general immediate, because for
5164 ; case of overflows, the result is messed up.
5165 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5167 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5168 ; only for comparisons not depending on it.
5169 (define_insn "*adddi_4_rex64"
5171 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5172 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5173 (clobber (match_scratch:DI 0 "=rm"))]
5175 && ix86_match_ccmode (insn, CCGCmode)"
5177 switch (get_attr_type (insn))
5180 if (operands[2] == constm1_rtx)
5181 return "inc{q}\t%0";
5182 else if (operands[2] == const1_rtx)
5183 return "dec{q}\t%0";
5188 if (! rtx_equal_p (operands[0], operands[1]))
5190 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5191 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5192 if ((INTVAL (operands[2]) == -128
5193 || (INTVAL (operands[2]) > 0
5194 && INTVAL (operands[2]) != 128))
5195 /* Avoid overflows. */
5196 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5197 return "sub{q}\t{%2, %0|%0, %2}";
5198 operands[2] = GEN_INT (-INTVAL (operands[2]));
5199 return "add{q}\t{%2, %0|%0, %2}";
5203 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5204 (const_string "incdec")
5205 (const_string "alu")))
5206 (set_attr "mode" "DI")])
5208 (define_insn "*adddi_5_rex64"
5211 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5212 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5214 (clobber (match_scratch:DI 0 "=r"))]
5216 && ix86_match_ccmode (insn, CCGOCmode)
5217 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5218 /* Current assemblers are broken and do not allow @GOTOFF in
5219 ought but a memory context. */
5220 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5222 switch (get_attr_type (insn))
5225 if (! rtx_equal_p (operands[0], operands[1]))
5227 if (operands[2] == const1_rtx)
5228 return "inc{q}\t%0";
5229 else if (operands[2] == constm1_rtx)
5230 return "dec{q}\t%0";
5235 if (! rtx_equal_p (operands[0], operands[1]))
5237 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5238 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5239 if (GET_CODE (operands[2]) == CONST_INT
5240 /* Avoid overflows. */
5241 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5242 && (INTVAL (operands[2]) == 128
5243 || (INTVAL (operands[2]) < 0
5244 && INTVAL (operands[2]) != -128)))
5246 operands[2] = GEN_INT (-INTVAL (operands[2]));
5247 return "sub{q}\t{%2, %0|%0, %2}";
5249 return "add{q}\t{%2, %0|%0, %2}";
5253 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5254 (const_string "incdec")
5255 (const_string "alu")))
5256 (set_attr "mode" "DI")])
5259 (define_insn "*addsi_1"
5260 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5261 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5262 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5263 (clobber (reg:CC 17))]
5264 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5266 switch (get_attr_type (insn))
5269 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5270 return "lea{l}\t{%a2, %0|%0, %a2}";
5273 if (! rtx_equal_p (operands[0], operands[1]))
5275 if (operands[2] == const1_rtx)
5276 return "inc{l}\t%0";
5277 else if (operands[2] == constm1_rtx)
5278 return "dec{l}\t%0";
5283 if (! rtx_equal_p (operands[0], operands[1]))
5286 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5287 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5288 if (GET_CODE (operands[2]) == CONST_INT
5289 && (INTVAL (operands[2]) == 128
5290 || (INTVAL (operands[2]) < 0
5291 && INTVAL (operands[2]) != -128)))
5293 operands[2] = GEN_INT (-INTVAL (operands[2]));
5294 return "sub{l}\t{%2, %0|%0, %2}";
5296 return "add{l}\t{%2, %0|%0, %2}";
5300 (cond [(eq_attr "alternative" "2")
5301 (const_string "lea")
5302 ; Current assemblers are broken and do not allow @GOTOFF in
5303 ; ought but a memory context.
5304 (match_operand:SI 2 "pic_symbolic_operand" "")
5305 (const_string "lea")
5306 (match_operand:SI 2 "incdec_operand" "")
5307 (const_string "incdec")
5309 (const_string "alu")))
5310 (set_attr "mode" "SI")])
5312 ;; Convert lea to the lea pattern to avoid flags dependency.
5314 [(set (match_operand 0 "register_operand" "")
5315 (plus (match_operand 1 "register_operand" "")
5316 (match_operand 2 "nonmemory_operand" "")))
5317 (clobber (reg:CC 17))]
5319 && true_regnum (operands[0]) != true_regnum (operands[1])"
5323 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5324 may confuse gen_lowpart. */
5325 if (GET_MODE (operands[0]) != Pmode)
5327 operands[1] = gen_lowpart (Pmode, operands[1]);
5328 operands[2] = gen_lowpart (Pmode, operands[2]);
5330 operands[0] = gen_lowpart (SImode, operands[0]);
5331 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5332 if (Pmode != SImode)
5333 pat = gen_rtx_SUBREG (SImode, pat, 0);
5334 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5338 ;; It may seem that nonimmediate operand is proper one for operand 1.
5339 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5340 ;; we take care in ix86_binary_operator_ok to not allow two memory
5341 ;; operands so proper swapping will be done in reload. This allow
5342 ;; patterns constructed from addsi_1 to match.
5343 (define_insn "addsi_1_zext"
5344 [(set (match_operand:DI 0 "register_operand" "=r,r")
5346 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5347 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5348 (clobber (reg:CC 17))]
5349 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5351 switch (get_attr_type (insn))
5354 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5355 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5358 if (operands[2] == const1_rtx)
5359 return "inc{l}\t%k0";
5360 else if (operands[2] == constm1_rtx)
5361 return "dec{l}\t%k0";
5366 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5367 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5368 if (GET_CODE (operands[2]) == CONST_INT
5369 && (INTVAL (operands[2]) == 128
5370 || (INTVAL (operands[2]) < 0
5371 && INTVAL (operands[2]) != -128)))
5373 operands[2] = GEN_INT (-INTVAL (operands[2]));
5374 return "sub{l}\t{%2, %k0|%k0, %2}";
5376 return "add{l}\t{%2, %k0|%k0, %2}";
5380 (cond [(eq_attr "alternative" "1")
5381 (const_string "lea")
5382 ; Current assemblers are broken and do not allow @GOTOFF in
5383 ; ought but a memory context.
5384 (match_operand:SI 2 "pic_symbolic_operand" "")
5385 (const_string "lea")
5386 (match_operand:SI 2 "incdec_operand" "")
5387 (const_string "incdec")
5389 (const_string "alu")))
5390 (set_attr "mode" "SI")])
5392 ;; Convert lea to the lea pattern to avoid flags dependency.
5394 [(set (match_operand:DI 0 "register_operand" "")
5396 (plus:SI (match_operand:SI 1 "register_operand" "")
5397 (match_operand:SI 2 "nonmemory_operand" ""))))
5398 (clobber (reg:CC 17))]
5400 && true_regnum (operands[0]) != true_regnum (operands[1])"
5402 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5404 operands[1] = gen_lowpart (Pmode, operands[1]);
5405 operands[2] = gen_lowpart (Pmode, operands[2]);
5408 (define_insn "*addsi_2"
5411 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5412 (match_operand:SI 2 "general_operand" "rmni,rni"))
5414 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5415 (plus:SI (match_dup 1) (match_dup 2)))]
5416 "ix86_match_ccmode (insn, CCGOCmode)
5417 && ix86_binary_operator_ok (PLUS, SImode, operands)
5418 /* Current assemblers are broken and do not allow @GOTOFF in
5419 ought but a memory context. */
5420 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5422 switch (get_attr_type (insn))
5425 if (! rtx_equal_p (operands[0], operands[1]))
5427 if (operands[2] == const1_rtx)
5428 return "inc{l}\t%0";
5429 else if (operands[2] == constm1_rtx)
5430 return "dec{l}\t%0";
5435 if (! rtx_equal_p (operands[0], operands[1]))
5437 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5438 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5439 if (GET_CODE (operands[2]) == CONST_INT
5440 && (INTVAL (operands[2]) == 128
5441 || (INTVAL (operands[2]) < 0
5442 && INTVAL (operands[2]) != -128)))
5444 operands[2] = GEN_INT (-INTVAL (operands[2]));
5445 return "sub{l}\t{%2, %0|%0, %2}";
5447 return "add{l}\t{%2, %0|%0, %2}";
5451 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5452 (const_string "incdec")
5453 (const_string "alu")))
5454 (set_attr "mode" "SI")])
5456 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5457 (define_insn "*addsi_2_zext"
5460 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5461 (match_operand:SI 2 "general_operand" "rmni"))
5463 (set (match_operand:DI 0 "register_operand" "=r")
5464 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5465 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5466 && ix86_binary_operator_ok (PLUS, SImode, operands)
5467 /* Current assemblers are broken and do not allow @GOTOFF in
5468 ought but a memory context. */
5469 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5471 switch (get_attr_type (insn))
5474 if (operands[2] == const1_rtx)
5475 return "inc{l}\t%k0";
5476 else if (operands[2] == constm1_rtx)
5477 return "dec{l}\t%k0";
5482 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5483 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5484 if (GET_CODE (operands[2]) == CONST_INT
5485 && (INTVAL (operands[2]) == 128
5486 || (INTVAL (operands[2]) < 0
5487 && INTVAL (operands[2]) != -128)))
5489 operands[2] = GEN_INT (-INTVAL (operands[2]));
5490 return "sub{l}\t{%2, %k0|%k0, %2}";
5492 return "add{l}\t{%2, %k0|%k0, %2}";
5496 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5497 (const_string "incdec")
5498 (const_string "alu")))
5499 (set_attr "mode" "SI")])
5501 (define_insn "*addsi_3"
5503 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5504 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5505 (clobber (match_scratch:SI 0 "=r"))]
5506 "ix86_match_ccmode (insn, CCZmode)
5507 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5508 /* Current assemblers are broken and do not allow @GOTOFF in
5509 ought but a memory context. */
5510 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5512 switch (get_attr_type (insn))
5515 if (! rtx_equal_p (operands[0], operands[1]))
5517 if (operands[2] == const1_rtx)
5518 return "inc{l}\t%0";
5519 else if (operands[2] == constm1_rtx)
5520 return "dec{l}\t%0";
5525 if (! rtx_equal_p (operands[0], operands[1]))
5527 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5528 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5529 if (GET_CODE (operands[2]) == CONST_INT
5530 && (INTVAL (operands[2]) == 128
5531 || (INTVAL (operands[2]) < 0
5532 && INTVAL (operands[2]) != -128)))
5534 operands[2] = GEN_INT (-INTVAL (operands[2]));
5535 return "sub{l}\t{%2, %0|%0, %2}";
5537 return "add{l}\t{%2, %0|%0, %2}";
5541 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5542 (const_string "incdec")
5543 (const_string "alu")))
5544 (set_attr "mode" "SI")])
5546 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5547 (define_insn "*addsi_3_zext"
5549 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5550 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5551 (set (match_operand:DI 0 "register_operand" "=r")
5552 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5553 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5554 && ix86_binary_operator_ok (PLUS, SImode, operands)
5555 /* Current assemblers are broken and do not allow @GOTOFF in
5556 ought but a memory context. */
5557 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5559 switch (get_attr_type (insn))
5562 if (operands[2] == const1_rtx)
5563 return "inc{l}\t%k0";
5564 else if (operands[2] == constm1_rtx)
5565 return "dec{l}\t%k0";
5570 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5571 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5572 if (GET_CODE (operands[2]) == CONST_INT
5573 && (INTVAL (operands[2]) == 128
5574 || (INTVAL (operands[2]) < 0
5575 && INTVAL (operands[2]) != -128)))
5577 operands[2] = GEN_INT (-INTVAL (operands[2]));
5578 return "sub{l}\t{%2, %k0|%k0, %2}";
5580 return "add{l}\t{%2, %k0|%k0, %2}";
5584 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5585 (const_string "incdec")
5586 (const_string "alu")))
5587 (set_attr "mode" "SI")])
5589 ; For comparisons agains 1, -1 and 128, we may generate better code
5590 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5591 ; is matched then. We can't accept general immediate, because for
5592 ; case of overflows, the result is messed up.
5593 ; This pattern also don't hold of 0x80000000, since the value overflows
5595 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5596 ; only for comparisons not depending on it.
5597 (define_insn "*addsi_4"
5599 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5600 (match_operand:SI 2 "const_int_operand" "n")))
5601 (clobber (match_scratch:SI 0 "=rm"))]
5602 "ix86_match_ccmode (insn, CCGCmode)
5603 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5605 switch (get_attr_type (insn))
5608 if (operands[2] == constm1_rtx)
5609 return "inc{l}\t%0";
5610 else if (operands[2] == const1_rtx)
5611 return "dec{l}\t%0";
5616 if (! rtx_equal_p (operands[0], operands[1]))
5618 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5619 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5620 if ((INTVAL (operands[2]) == -128
5621 || (INTVAL (operands[2]) > 0
5622 && INTVAL (operands[2]) != 128)))
5623 return "sub{l}\t{%2, %0|%0, %2}";
5624 operands[2] = GEN_INT (-INTVAL (operands[2]));
5625 return "add{l}\t{%2, %0|%0, %2}";
5629 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5630 (const_string "incdec")
5631 (const_string "alu")))
5632 (set_attr "mode" "SI")])
5634 (define_insn "*addsi_5"
5637 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5638 (match_operand:SI 2 "general_operand" "rmni"))
5640 (clobber (match_scratch:SI 0 "=r"))]
5641 "ix86_match_ccmode (insn, CCGOCmode)
5642 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5643 /* Current assemblers are broken and do not allow @GOTOFF in
5644 ought but a memory context. */
5645 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5647 switch (get_attr_type (insn))
5650 if (! rtx_equal_p (operands[0], operands[1]))
5652 if (operands[2] == const1_rtx)
5653 return "inc{l}\t%0";
5654 else if (operands[2] == constm1_rtx)
5655 return "dec{l}\t%0";
5660 if (! rtx_equal_p (operands[0], operands[1]))
5662 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5663 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5664 if (GET_CODE (operands[2]) == CONST_INT
5665 && (INTVAL (operands[2]) == 128
5666 || (INTVAL (operands[2]) < 0
5667 && INTVAL (operands[2]) != -128)))
5669 operands[2] = GEN_INT (-INTVAL (operands[2]));
5670 return "sub{l}\t{%2, %0|%0, %2}";
5672 return "add{l}\t{%2, %0|%0, %2}";
5676 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5677 (const_string "incdec")
5678 (const_string "alu")))
5679 (set_attr "mode" "SI")])
5681 (define_expand "addhi3"
5682 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5683 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5684 (match_operand:HI 2 "general_operand" "")))
5685 (clobber (reg:CC 17))])]
5686 "TARGET_HIMODE_MATH"
5687 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5689 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5690 ;; type optimizations enabled by define-splits. This is not important
5691 ;; for PII, and in fact harmful because of partial register stalls.
5693 (define_insn "*addhi_1_lea"
5694 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5695 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5696 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
5697 (clobber (reg:CC 17))]
5698 "!TARGET_PARTIAL_REG_STALL
5699 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5701 switch (get_attr_type (insn))
5706 if (operands[2] == const1_rtx)
5707 return "inc{w}\t%0";
5708 else if (operands[2] == constm1_rtx
5709 || (GET_CODE (operands[2]) == CONST_INT
5710 && INTVAL (operands[2]) == 65535))
5711 return "dec{w}\t%0";
5715 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5716 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5717 if (GET_CODE (operands[2]) == CONST_INT
5718 && (INTVAL (operands[2]) == 128
5719 || (INTVAL (operands[2]) < 0
5720 && INTVAL (operands[2]) != -128)))
5722 operands[2] = GEN_INT (-INTVAL (operands[2]));
5723 return "sub{w}\t{%2, %0|%0, %2}";
5725 return "add{w}\t{%2, %0|%0, %2}";
5729 (if_then_else (eq_attr "alternative" "2")
5730 (const_string "lea")
5731 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5732 (const_string "incdec")
5733 (const_string "alu"))))
5734 (set_attr "mode" "HI,HI,SI")])
5736 (define_insn "*addhi_1"
5737 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5738 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5739 (match_operand:HI 2 "general_operand" "ri,rm")))
5740 (clobber (reg:CC 17))]
5741 "TARGET_PARTIAL_REG_STALL
5742 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5744 switch (get_attr_type (insn))
5747 if (operands[2] == const1_rtx)
5748 return "inc{w}\t%0";
5749 else if (operands[2] == constm1_rtx
5750 || (GET_CODE (operands[2]) == CONST_INT
5751 && INTVAL (operands[2]) == 65535))
5752 return "dec{w}\t%0";
5756 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5757 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5758 if (GET_CODE (operands[2]) == CONST_INT
5759 && (INTVAL (operands[2]) == 128
5760 || (INTVAL (operands[2]) < 0
5761 && INTVAL (operands[2]) != -128)))
5763 operands[2] = GEN_INT (-INTVAL (operands[2]));
5764 return "sub{w}\t{%2, %0|%0, %2}";
5766 return "add{w}\t{%2, %0|%0, %2}";
5770 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5771 (const_string "incdec")
5772 (const_string "alu")))
5773 (set_attr "mode" "HI")])
5775 (define_insn "*addhi_2"
5778 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5779 (match_operand:HI 2 "general_operand" "rmni,rni"))
5781 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
5782 (plus:HI (match_dup 1) (match_dup 2)))]
5783 "ix86_match_ccmode (insn, CCGOCmode)
5784 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5786 switch (get_attr_type (insn))
5789 if (operands[2] == const1_rtx)
5790 return "inc{w}\t%0";
5791 else if (operands[2] == constm1_rtx
5792 || (GET_CODE (operands[2]) == CONST_INT
5793 && INTVAL (operands[2]) == 65535))
5794 return "dec{w}\t%0";
5798 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5799 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5800 if (GET_CODE (operands[2]) == CONST_INT
5801 && (INTVAL (operands[2]) == 128
5802 || (INTVAL (operands[2]) < 0
5803 && INTVAL (operands[2]) != -128)))
5805 operands[2] = GEN_INT (-INTVAL (operands[2]));
5806 return "sub{w}\t{%2, %0|%0, %2}";
5808 return "add{w}\t{%2, %0|%0, %2}";
5812 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5813 (const_string "incdec")
5814 (const_string "alu")))
5815 (set_attr "mode" "HI")])
5817 (define_insn "*addhi_3"
5819 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
5820 (match_operand:HI 1 "nonimmediate_operand" "%0")))
5821 (clobber (match_scratch:HI 0 "=r"))]
5822 "ix86_match_ccmode (insn, CCZmode)
5823 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5825 switch (get_attr_type (insn))
5828 if (operands[2] == const1_rtx)
5829 return "inc{w}\t%0";
5830 else if (operands[2] == constm1_rtx
5831 || (GET_CODE (operands[2]) == CONST_INT
5832 && INTVAL (operands[2]) == 65535))
5833 return "dec{w}\t%0";
5837 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5838 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5839 if (GET_CODE (operands[2]) == CONST_INT
5840 && (INTVAL (operands[2]) == 128
5841 || (INTVAL (operands[2]) < 0
5842 && INTVAL (operands[2]) != -128)))
5844 operands[2] = GEN_INT (-INTVAL (operands[2]));
5845 return "sub{w}\t{%2, %0|%0, %2}";
5847 return "add{w}\t{%2, %0|%0, %2}";
5851 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5852 (const_string "incdec")
5853 (const_string "alu")))
5854 (set_attr "mode" "HI")])
5856 ; See comments above addsi_3_imm for details.
5857 (define_insn "*addhi_4"
5859 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
5860 (match_operand:HI 2 "const_int_operand" "n")))
5861 (clobber (match_scratch:HI 0 "=rm"))]
5862 "ix86_match_ccmode (insn, CCGCmode)
5863 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
5865 switch (get_attr_type (insn))
5868 if (operands[2] == constm1_rtx
5869 || (GET_CODE (operands[2]) == CONST_INT
5870 && INTVAL (operands[2]) == 65535))
5871 return "inc{w}\t%0";
5872 else if (operands[2] == const1_rtx)
5873 return "dec{w}\t%0";
5878 if (! rtx_equal_p (operands[0], operands[1]))
5880 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5881 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5882 if ((INTVAL (operands[2]) == -128
5883 || (INTVAL (operands[2]) > 0
5884 && INTVAL (operands[2]) != 128)))
5885 return "sub{w}\t{%2, %0|%0, %2}";
5886 operands[2] = GEN_INT (-INTVAL (operands[2]));
5887 return "add{w}\t{%2, %0|%0, %2}";
5891 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5892 (const_string "incdec")
5893 (const_string "alu")))
5894 (set_attr "mode" "SI")])
5897 (define_insn "*addhi_5"
5900 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
5901 (match_operand:HI 2 "general_operand" "rmni"))
5903 (clobber (match_scratch:HI 0 "=r"))]
5904 "ix86_match_ccmode (insn, CCGOCmode)
5905 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5907 switch (get_attr_type (insn))
5910 if (operands[2] == const1_rtx)
5911 return "inc{w}\t%0";
5912 else if (operands[2] == constm1_rtx
5913 || (GET_CODE (operands[2]) == CONST_INT
5914 && INTVAL (operands[2]) == 65535))
5915 return "dec{w}\t%0";
5919 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5920 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5921 if (GET_CODE (operands[2]) == CONST_INT
5922 && (INTVAL (operands[2]) == 128
5923 || (INTVAL (operands[2]) < 0
5924 && INTVAL (operands[2]) != -128)))
5926 operands[2] = GEN_INT (-INTVAL (operands[2]));
5927 return "sub{w}\t{%2, %0|%0, %2}";
5929 return "add{w}\t{%2, %0|%0, %2}";
5933 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5934 (const_string "incdec")
5935 (const_string "alu")))
5936 (set_attr "mode" "HI")])
5938 (define_expand "addqi3"
5939 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
5940 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
5941 (match_operand:QI 2 "general_operand" "")))
5942 (clobber (reg:CC 17))])]
5943 "TARGET_QIMODE_MATH"
5944 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
5946 ;; %%% Potential partial reg stall on alternative 2. What to do?
5947 (define_insn "*addqi_1_lea"
5948 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
5949 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
5950 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
5951 (clobber (reg:CC 17))]
5952 "!TARGET_PARTIAL_REG_STALL
5953 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5955 int widen = (which_alternative == 2);
5956 switch (get_attr_type (insn))
5961 if (operands[2] == const1_rtx)
5962 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
5963 else if (operands[2] == constm1_rtx
5964 || (GET_CODE (operands[2]) == CONST_INT
5965 && INTVAL (operands[2]) == 255))
5966 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
5970 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5971 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5972 if (GET_CODE (operands[2]) == CONST_INT
5973 && (INTVAL (operands[2]) == 128
5974 || (INTVAL (operands[2]) < 0
5975 && INTVAL (operands[2]) != -128)))
5977 operands[2] = GEN_INT (-INTVAL (operands[2]));
5979 return "sub{l}\t{%2, %k0|%k0, %2}";
5981 return "sub{b}\t{%2, %0|%0, %2}";
5984 return "add{l}\t{%k2, %k0|%k0, %k2}";
5986 return "add{b}\t{%2, %0|%0, %2}";
5990 (if_then_else (eq_attr "alternative" "3")
5991 (const_string "lea")
5992 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5993 (const_string "incdec")
5994 (const_string "alu"))))
5995 (set_attr "mode" "QI,QI,SI,SI")])
5997 (define_insn "*addqi_1"
5998 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
5999 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6000 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6001 (clobber (reg:CC 17))]
6002 "TARGET_PARTIAL_REG_STALL
6003 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6005 int widen = (which_alternative == 2);
6006 switch (get_attr_type (insn))
6009 if (operands[2] == const1_rtx)
6010 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6011 else if (operands[2] == constm1_rtx
6012 || (GET_CODE (operands[2]) == CONST_INT
6013 && INTVAL (operands[2]) == 255))
6014 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6018 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6019 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6020 if (GET_CODE (operands[2]) == CONST_INT
6021 && (INTVAL (operands[2]) == 128
6022 || (INTVAL (operands[2]) < 0
6023 && INTVAL (operands[2]) != -128)))
6025 operands[2] = GEN_INT (-INTVAL (operands[2]));
6027 return "sub{l}\t{%2, %k0|%k0, %2}";
6029 return "sub{b}\t{%2, %0|%0, %2}";
6032 return "add{l}\t{%k2, %k0|%k0, %k2}";
6034 return "add{b}\t{%2, %0|%0, %2}";
6038 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6039 (const_string "incdec")
6040 (const_string "alu")))
6041 (set_attr "mode" "QI,QI,SI")])
6043 (define_insn "*addqi_2"
6046 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6047 (match_operand:QI 2 "general_operand" "qmni,qni"))
6049 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6050 (plus:QI (match_dup 1) (match_dup 2)))]
6051 "ix86_match_ccmode (insn, CCGOCmode)
6052 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6054 switch (get_attr_type (insn))
6057 if (operands[2] == const1_rtx)
6058 return "inc{b}\t%0";
6059 else if (operands[2] == constm1_rtx
6060 || (GET_CODE (operands[2]) == CONST_INT
6061 && INTVAL (operands[2]) == 255))
6062 return "dec{b}\t%0";
6066 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6067 if (GET_CODE (operands[2]) == CONST_INT
6068 && INTVAL (operands[2]) < 0)
6070 operands[2] = GEN_INT (-INTVAL (operands[2]));
6071 return "sub{b}\t{%2, %0|%0, %2}";
6073 return "add{b}\t{%2, %0|%0, %2}";
6077 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6078 (const_string "incdec")
6079 (const_string "alu")))
6080 (set_attr "mode" "QI")])
6082 (define_insn "*addqi_3"
6084 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6085 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6086 (clobber (match_scratch:QI 0 "=q"))]
6087 "ix86_match_ccmode (insn, CCZmode)
6088 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6090 switch (get_attr_type (insn))
6093 if (operands[2] == const1_rtx)
6094 return "inc{b}\t%0";
6095 else if (operands[2] == constm1_rtx
6096 || (GET_CODE (operands[2]) == CONST_INT
6097 && INTVAL (operands[2]) == 255))
6098 return "dec{b}\t%0";
6102 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6103 if (GET_CODE (operands[2]) == CONST_INT
6104 && INTVAL (operands[2]) < 0)
6106 operands[2] = GEN_INT (-INTVAL (operands[2]));
6107 return "sub{b}\t{%2, %0|%0, %2}";
6109 return "add{b}\t{%2, %0|%0, %2}";
6113 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6114 (const_string "incdec")
6115 (const_string "alu")))
6116 (set_attr "mode" "QI")])
6118 ; See comments above addsi_3_imm for details.
6119 (define_insn "*addqi_4"
6121 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6122 (match_operand:QI 2 "const_int_operand" "n")))
6123 (clobber (match_scratch:QI 0 "=qm"))]
6124 "ix86_match_ccmode (insn, CCGCmode)
6125 && (INTVAL (operands[2]) & 0xff) != 0x80"
6127 switch (get_attr_type (insn))
6130 if (operands[2] == constm1_rtx
6131 || (GET_CODE (operands[2]) == CONST_INT
6132 && INTVAL (operands[2]) == 255))
6133 return "inc{b}\t%0";
6134 else if (operands[2] == const1_rtx)
6135 return "dec{b}\t%0";
6140 if (! rtx_equal_p (operands[0], operands[1]))
6142 if (INTVAL (operands[2]) < 0)
6144 operands[2] = GEN_INT (-INTVAL (operands[2]));
6145 return "add{b}\t{%2, %0|%0, %2}";
6147 return "sub{b}\t{%2, %0|%0, %2}";
6151 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6152 (const_string "incdec")
6153 (const_string "alu")))
6154 (set_attr "mode" "QI")])
6157 (define_insn "*addqi_5"
6160 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6161 (match_operand:QI 2 "general_operand" "qmni"))
6163 (clobber (match_scratch:QI 0 "=q"))]
6164 "ix86_match_ccmode (insn, CCGOCmode)
6165 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6167 switch (get_attr_type (insn))
6170 if (operands[2] == const1_rtx)
6171 return "inc{b}\t%0";
6172 else if (operands[2] == constm1_rtx
6173 || (GET_CODE (operands[2]) == CONST_INT
6174 && INTVAL (operands[2]) == 255))
6175 return "dec{b}\t%0";
6179 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6180 if (GET_CODE (operands[2]) == CONST_INT
6181 && INTVAL (operands[2]) < 0)
6183 operands[2] = GEN_INT (-INTVAL (operands[2]));
6184 return "sub{b}\t{%2, %0|%0, %2}";
6186 return "add{b}\t{%2, %0|%0, %2}";
6190 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6191 (const_string "incdec")
6192 (const_string "alu")))
6193 (set_attr "mode" "QI")])
6196 (define_insn "addqi_ext_1"
6197 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6202 (match_operand 1 "ext_register_operand" "0")
6205 (match_operand:QI 2 "general_operand" "Qmn")))
6206 (clobber (reg:CC 17))]
6209 switch (get_attr_type (insn))
6212 if (operands[2] == const1_rtx)
6213 return "inc{b}\t%h0";
6214 else if (operands[2] == constm1_rtx
6215 || (GET_CODE (operands[2]) == CONST_INT
6216 && INTVAL (operands[2]) == 255))
6217 return "dec{b}\t%h0";
6221 return "add{b}\t{%2, %h0|%h0, %2}";
6225 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6226 (const_string "incdec")
6227 (const_string "alu")))
6228 (set_attr "mode" "QI")])
6230 (define_insn "*addqi_ext_1_rex64"
6231 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6236 (match_operand 1 "ext_register_operand" "0")
6239 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6240 (clobber (reg:CC 17))]
6243 switch (get_attr_type (insn))
6246 if (operands[2] == const1_rtx)
6247 return "inc{b}\t%h0";
6248 else if (operands[2] == constm1_rtx
6249 || (GET_CODE (operands[2]) == CONST_INT
6250 && INTVAL (operands[2]) == 255))
6251 return "dec{b}\t%h0";
6255 return "add{b}\t{%2, %h0|%h0, %2}";
6259 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6260 (const_string "incdec")
6261 (const_string "alu")))
6262 (set_attr "mode" "QI")])
6264 (define_insn "*addqi_ext_2"
6265 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6270 (match_operand 1 "ext_register_operand" "%0")
6274 (match_operand 2 "ext_register_operand" "Q")
6277 (clobber (reg:CC 17))]
6279 "add{b}\t{%h2, %h0|%h0, %h2}"
6280 [(set_attr "type" "alu")
6281 (set_attr "mode" "QI")])
6283 ;; The patterns that match these are at the end of this file.
6285 (define_expand "addxf3"
6286 [(set (match_operand:XF 0 "register_operand" "")
6287 (plus:XF (match_operand:XF 1 "register_operand" "")
6288 (match_operand:XF 2 "register_operand" "")))]
6289 "!TARGET_64BIT && TARGET_80387"
6292 (define_expand "addtf3"
6293 [(set (match_operand:TF 0 "register_operand" "")
6294 (plus:TF (match_operand:TF 1 "register_operand" "")
6295 (match_operand:TF 2 "register_operand" "")))]
6299 (define_expand "adddf3"
6300 [(set (match_operand:DF 0 "register_operand" "")
6301 (plus:DF (match_operand:DF 1 "register_operand" "")
6302 (match_operand:DF 2 "nonimmediate_operand" "")))]
6303 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6306 (define_expand "addsf3"
6307 [(set (match_operand:SF 0 "register_operand" "")
6308 (plus:SF (match_operand:SF 1 "register_operand" "")
6309 (match_operand:SF 2 "nonimmediate_operand" "")))]
6310 "TARGET_80387 || TARGET_SSE_MATH"
6313 ;; Subtract instructions
6315 ;; %%% splits for subsidi3
6317 (define_expand "subdi3"
6318 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6319 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6320 (match_operand:DI 2 "x86_64_general_operand" "")))
6321 (clobber (reg:CC 17))])]
6323 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6325 (define_insn "*subdi3_1"
6326 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6327 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6328 (match_operand:DI 2 "general_operand" "roiF,riF")))
6329 (clobber (reg:CC 17))]
6334 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6335 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6336 (match_operand:DI 2 "general_operand" "")))
6337 (clobber (reg:CC 17))]
6338 "!TARGET_64BIT && reload_completed"
6339 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6340 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6341 (parallel [(set (match_dup 3)
6342 (minus:SI (match_dup 4)
6343 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6345 (clobber (reg:CC 17))])]
6346 "split_di (operands+0, 1, operands+0, operands+3);
6347 split_di (operands+1, 1, operands+1, operands+4);
6348 split_di (operands+2, 1, operands+2, operands+5);")
6350 (define_insn "subdi3_carry_rex64"
6351 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6352 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6353 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6354 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6355 (clobber (reg:CC 17))]
6356 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6357 "sbb{q}\t{%2, %0|%0, %2}"
6358 [(set_attr "type" "alu")
6359 (set_attr "pent_pair" "pu")
6360 (set_attr "ppro_uops" "few")
6361 (set_attr "mode" "DI")])
6363 (define_insn "*subdi_1_rex64"
6364 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6365 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6366 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6367 (clobber (reg:CC 17))]
6368 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6369 "sub{q}\t{%2, %0|%0, %2}"
6370 [(set_attr "type" "alu")
6371 (set_attr "mode" "DI")])
6373 (define_insn "*subdi_2_rex64"
6376 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6377 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6379 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6380 (minus:DI (match_dup 1) (match_dup 2)))]
6381 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6382 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6383 "sub{q}\t{%2, %0|%0, %2}"
6384 [(set_attr "type" "alu")
6385 (set_attr "mode" "DI")])
6387 (define_insn "*subdi_3_rex63"
6389 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6390 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6391 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6392 (minus:DI (match_dup 1) (match_dup 2)))]
6393 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6394 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6395 "sub{q}\t{%2, %0|%0, %2}"
6396 [(set_attr "type" "alu")
6397 (set_attr "mode" "DI")])
6400 (define_insn "subsi3_carry"
6401 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6402 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6403 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6404 (match_operand:SI 2 "general_operand" "ri,rm"))))
6405 (clobber (reg:CC 17))]
6406 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6407 "sbb{l}\t{%2, %0|%0, %2}"
6408 [(set_attr "type" "alu")
6409 (set_attr "pent_pair" "pu")
6410 (set_attr "ppro_uops" "few")
6411 (set_attr "mode" "SI")])
6413 (define_insn "subsi3_carry_zext"
6414 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6416 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6417 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6418 (match_operand:SI 2 "general_operand" "ri,rm")))))
6419 (clobber (reg:CC 17))]
6420 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6421 "sbb{l}\t{%2, %k0|%k0, %2}"
6422 [(set_attr "type" "alu")
6423 (set_attr "pent_pair" "pu")
6424 (set_attr "ppro_uops" "few")
6425 (set_attr "mode" "SI")])
6427 (define_expand "subsi3"
6428 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6429 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6430 (match_operand:SI 2 "general_operand" "")))
6431 (clobber (reg:CC 17))])]
6433 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6435 (define_insn "*subsi_1"
6436 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6437 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6438 (match_operand:SI 2 "general_operand" "ri,rm")))
6439 (clobber (reg:CC 17))]
6440 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6441 "sub{l}\t{%2, %0|%0, %2}"
6442 [(set_attr "type" "alu")
6443 (set_attr "mode" "SI")])
6445 (define_insn "*subsi_1_zext"
6446 [(set (match_operand:DI 0 "register_operand" "=r")
6448 (minus:SI (match_operand:SI 1 "register_operand" "0")
6449 (match_operand:SI 2 "general_operand" "rim"))))
6450 (clobber (reg:CC 17))]
6451 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6452 "sub{l}\t{%2, %k0|%k0, %2}"
6453 [(set_attr "type" "alu")
6454 (set_attr "mode" "SI")])
6456 (define_insn "*subsi_2"
6459 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6460 (match_operand:SI 2 "general_operand" "ri,rm"))
6462 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6463 (minus:SI (match_dup 1) (match_dup 2)))]
6464 "ix86_match_ccmode (insn, CCGOCmode)
6465 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6466 "sub{l}\t{%2, %0|%0, %2}"
6467 [(set_attr "type" "alu")
6468 (set_attr "mode" "SI")])
6470 (define_insn "*subsi_2_zext"
6473 (minus:SI (match_operand:SI 1 "register_operand" "0")
6474 (match_operand:SI 2 "general_operand" "rim"))
6476 (set (match_operand:DI 0 "register_operand" "=r")
6478 (minus:SI (match_dup 1)
6480 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6481 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6482 "sub{l}\t{%2, %k0|%k0, %2}"
6483 [(set_attr "type" "alu")
6484 (set_attr "mode" "SI")])
6486 (define_insn "*subsi_3"
6488 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6489 (match_operand:SI 2 "general_operand" "ri,rm")))
6490 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6491 (minus:SI (match_dup 1) (match_dup 2)))]
6492 "ix86_match_ccmode (insn, CCmode)
6493 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6494 "sub{l}\t{%2, %0|%0, %2}"
6495 [(set_attr "type" "alu")
6496 (set_attr "mode" "SI")])
6498 (define_insn "*subsi_3_zext"
6500 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6501 (match_operand:SI 2 "general_operand" "rim")))
6502 (set (match_operand:DI 0 "register_operand" "=r")
6504 (minus:SI (match_dup 1)
6506 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6507 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6508 "sub{q}\t{%2, %0|%0, %2}"
6509 [(set_attr "type" "alu")
6510 (set_attr "mode" "DI")])
6512 (define_expand "subhi3"
6513 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6514 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6515 (match_operand:HI 2 "general_operand" "")))
6516 (clobber (reg:CC 17))])]
6517 "TARGET_HIMODE_MATH"
6518 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6520 (define_insn "*subhi_1"
6521 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6522 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6523 (match_operand:HI 2 "general_operand" "ri,rm")))
6524 (clobber (reg:CC 17))]
6525 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6526 "sub{w}\t{%2, %0|%0, %2}"
6527 [(set_attr "type" "alu")
6528 (set_attr "mode" "HI")])
6530 (define_insn "*subhi_2"
6533 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6534 (match_operand:HI 2 "general_operand" "ri,rm"))
6536 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6537 (minus:HI (match_dup 1) (match_dup 2)))]
6538 "ix86_match_ccmode (insn, CCGOCmode)
6539 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6540 "sub{w}\t{%2, %0|%0, %2}"
6541 [(set_attr "type" "alu")
6542 (set_attr "mode" "HI")])
6544 (define_insn "*subhi_3"
6546 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6547 (match_operand:HI 2 "general_operand" "ri,rm")))
6548 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6549 (minus:HI (match_dup 1) (match_dup 2)))]
6550 "ix86_match_ccmode (insn, CCmode)
6551 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6552 "sub{w}\t{%2, %0|%0, %2}"
6553 [(set_attr "type" "alu")
6554 (set_attr "mode" "HI")])
6556 (define_expand "subqi3"
6557 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6558 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6559 (match_operand:QI 2 "general_operand" "")))
6560 (clobber (reg:CC 17))])]
6561 "TARGET_QIMODE_MATH"
6562 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6564 (define_insn "*subqi_1"
6565 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6566 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6567 (match_operand:QI 2 "general_operand" "qn,qmn")))
6568 (clobber (reg:CC 17))]
6569 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6570 "sub{b}\t{%2, %0|%0, %2}"
6571 [(set_attr "type" "alu")
6572 (set_attr "mode" "QI")])
6574 (define_insn "*subqi_2"
6577 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6578 (match_operand:QI 2 "general_operand" "qi,qm"))
6580 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6581 (minus:HI (match_dup 1) (match_dup 2)))]
6582 "ix86_match_ccmode (insn, CCGOCmode)
6583 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6584 "sub{b}\t{%2, %0|%0, %2}"
6585 [(set_attr "type" "alu")
6586 (set_attr "mode" "QI")])
6588 (define_insn "*subqi_3"
6590 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6591 (match_operand:QI 2 "general_operand" "qi,qm")))
6592 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6593 (minus:HI (match_dup 1) (match_dup 2)))]
6594 "ix86_match_ccmode (insn, CCmode)
6595 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6596 "sub{b}\t{%2, %0|%0, %2}"
6597 [(set_attr "type" "alu")
6598 (set_attr "mode" "QI")])
6600 ;; The patterns that match these are at the end of this file.
6602 (define_expand "subxf3"
6603 [(set (match_operand:XF 0 "register_operand" "")
6604 (minus:XF (match_operand:XF 1 "register_operand" "")
6605 (match_operand:XF 2 "register_operand" "")))]
6606 "!TARGET_64BIT && TARGET_80387"
6609 (define_expand "subtf3"
6610 [(set (match_operand:TF 0 "register_operand" "")
6611 (minus:TF (match_operand:TF 1 "register_operand" "")
6612 (match_operand:TF 2 "register_operand" "")))]
6616 (define_expand "subdf3"
6617 [(set (match_operand:DF 0 "register_operand" "")
6618 (minus:DF (match_operand:DF 1 "register_operand" "")
6619 (match_operand:DF 2 "nonimmediate_operand" "")))]
6620 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6623 (define_expand "subsf3"
6624 [(set (match_operand:SF 0 "register_operand" "")
6625 (minus:SF (match_operand:SF 1 "register_operand" "")
6626 (match_operand:SF 2 "nonimmediate_operand" "")))]
6627 "TARGET_80387 || TARGET_SSE_MATH"
6630 ;; Multiply instructions
6632 (define_expand "muldi3"
6633 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6634 (mult:DI (match_operand:DI 1 "register_operand" "")
6635 (match_operand:DI 2 "x86_64_general_operand" "")))
6636 (clobber (reg:CC 17))])]
6640 (define_insn "*muldi3_1_rex64"
6641 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6642 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
6643 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6644 (clobber (reg:CC 17))]
6646 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6648 imul{q}\t{%2, %1, %0|%0, %1, %2}
6649 imul{q}\t{%2, %1, %0|%0, %1, %2}
6650 imul{q}\t{%2, %0|%0, %2}"
6651 [(set_attr "type" "imul")
6652 (set_attr "prefix_0f" "0,0,1")
6653 (set_attr "mode" "DI")])
6655 (define_expand "mulsi3"
6656 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6657 (mult:SI (match_operand:SI 1 "register_operand" "")
6658 (match_operand:SI 2 "general_operand" "")))
6659 (clobber (reg:CC 17))])]
6663 (define_insn "*mulsi3_1"
6664 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6665 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
6666 (match_operand:SI 2 "general_operand" "K,i,mr")))
6667 (clobber (reg:CC 17))]
6668 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6669 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
6670 ; there are two ways of writing the exact same machine instruction
6671 ; in assembly language. One, for example, is:
6675 ; while the other is:
6677 ; imul $12, %eax, %eax
6679 ; The first is simply short-hand for the latter. But, some assemblers,
6680 ; like the SCO OSR5 COFF assembler, don't handle the first form.
6682 imul{l}\t{%2, %1, %0|%0, %1, %2}
6683 imul{l}\t{%2, %1, %0|%0, %1, %2}
6684 imul{l}\t{%2, %0|%0, %2}"
6685 [(set_attr "type" "imul")
6686 (set_attr "prefix_0f" "0,0,1")
6687 (set_attr "mode" "SI")])
6689 (define_insn "*mulsi3_1_zext"
6690 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6692 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
6693 (match_operand:SI 2 "general_operand" "K,i,mr"))))
6694 (clobber (reg:CC 17))]
6696 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6697 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
6698 ; there are two ways of writing the exact same machine instruction
6699 ; in assembly language. One, for example, is:
6703 ; while the other is:
6705 ; imul $12, %eax, %eax
6707 ; The first is simply short-hand for the latter. But, some assemblers,
6708 ; like the SCO OSR5 COFF assembler, don't handle the first form.
6710 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6711 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6712 imul{l}\t{%2, %k0|%k0, %2}"
6713 [(set_attr "type" "imul")
6714 (set_attr "prefix_0f" "0,0,1")
6715 (set_attr "mode" "SI")])
6717 (define_expand "mulhi3"
6718 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6719 (mult:HI (match_operand:HI 1 "register_operand" "")
6720 (match_operand:HI 2 "general_operand" "")))
6721 (clobber (reg:CC 17))])]
6722 "TARGET_HIMODE_MATH"
6725 (define_insn "*mulhi3_1"
6726 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
6727 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
6728 (match_operand:HI 2 "general_operand" "K,i,mr")))
6729 (clobber (reg:CC 17))]
6730 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6731 ; %%% There was a note about "Assembler has weird restrictions",
6732 ; concerning alternative 1 when op1 == op0. True?
6734 imul{w}\t{%2, %1, %0|%0, %1, %2}
6735 imul{w}\t{%2, %1, %0|%0, %1, %2}
6736 imul{w}\t{%2, %0|%0, %2}"
6737 [(set_attr "type" "imul")
6738 (set_attr "prefix_0f" "0,0,1")
6739 (set_attr "mode" "HI")])
6741 (define_expand "mulqi3"
6742 [(parallel [(set (match_operand:QI 0 "register_operand" "")
6743 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
6744 (match_operand:QI 2 "register_operand" "")))
6745 (clobber (reg:CC 17))])]
6746 "TARGET_QIMODE_MATH"
6749 (define_insn "*mulqi3_1"
6750 [(set (match_operand:QI 0 "register_operand" "=a")
6751 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6752 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6753 (clobber (reg:CC 17))]
6755 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6757 [(set_attr "type" "imul")
6758 (set_attr "length_immediate" "0")
6759 (set_attr "mode" "QI")])
6761 (define_expand "umulqihi3"
6762 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6763 (mult:HI (zero_extend:HI
6764 (match_operand:QI 1 "nonimmediate_operand" ""))
6766 (match_operand:QI 2 "register_operand" ""))))
6767 (clobber (reg:CC 17))])]
6768 "TARGET_QIMODE_MATH"
6771 (define_insn "*umulqihi3_1"
6772 [(set (match_operand:HI 0 "register_operand" "=a")
6773 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
6774 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6775 (clobber (reg:CC 17))]
6777 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6779 [(set_attr "type" "imul")
6780 (set_attr "length_immediate" "0")
6781 (set_attr "mode" "QI")])
6783 (define_expand "mulqihi3"
6784 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6785 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
6786 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
6787 (clobber (reg:CC 17))])]
6788 "TARGET_QIMODE_MATH"
6791 (define_insn "*mulqihi3_insn"
6792 [(set (match_operand:HI 0 "register_operand" "=a")
6793 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
6794 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6795 (clobber (reg:CC 17))]
6797 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6799 [(set_attr "type" "imul")
6800 (set_attr "length_immediate" "0")
6801 (set_attr "mode" "QI")])
6803 (define_expand "umulditi3"
6804 [(parallel [(set (match_operand:TI 0 "register_operand" "")
6805 (mult:TI (zero_extend:TI
6806 (match_operand:DI 1 "nonimmediate_operand" ""))
6808 (match_operand:DI 2 "register_operand" ""))))
6809 (clobber (reg:CC 17))])]
6813 (define_insn "*umulditi3_insn"
6814 [(set (match_operand:TI 0 "register_operand" "=A")
6815 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
6816 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
6817 (clobber (reg:CC 17))]
6819 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6821 [(set_attr "type" "imul")
6822 (set_attr "ppro_uops" "few")
6823 (set_attr "length_immediate" "0")
6824 (set_attr "mode" "DI")])
6826 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
6827 (define_expand "umulsidi3"
6828 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6829 (mult:DI (zero_extend:DI
6830 (match_operand:SI 1 "nonimmediate_operand" ""))
6832 (match_operand:SI 2 "register_operand" ""))))
6833 (clobber (reg:CC 17))])]
6837 (define_insn "*umulsidi3_insn"
6838 [(set (match_operand:DI 0 "register_operand" "=A")
6839 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
6840 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6841 (clobber (reg:CC 17))]
6843 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6845 [(set_attr "type" "imul")
6846 (set_attr "ppro_uops" "few")
6847 (set_attr "length_immediate" "0")
6848 (set_attr "mode" "SI")])
6850 (define_expand "mulditi3"
6851 [(parallel [(set (match_operand:TI 0 "register_operand" "")
6852 (mult:TI (sign_extend:TI
6853 (match_operand:DI 1 "nonimmediate_operand" ""))
6855 (match_operand:DI 2 "register_operand" ""))))
6856 (clobber (reg:CC 17))])]
6860 (define_insn "*mulditi3_insn"
6861 [(set (match_operand:TI 0 "register_operand" "=A")
6862 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
6863 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
6864 (clobber (reg:CC 17))]
6866 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6868 [(set_attr "type" "imul")
6869 (set_attr "length_immediate" "0")
6870 (set_attr "mode" "DI")])
6872 (define_expand "mulsidi3"
6873 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6874 (mult:DI (sign_extend:DI
6875 (match_operand:SI 1 "nonimmediate_operand" ""))
6877 (match_operand:SI 2 "register_operand" ""))))
6878 (clobber (reg:CC 17))])]
6882 (define_insn "*mulsidi3_insn"
6883 [(set (match_operand:DI 0 "register_operand" "=A")
6884 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
6885 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6886 (clobber (reg:CC 17))]
6888 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6890 [(set_attr "type" "imul")
6891 (set_attr "length_immediate" "0")
6892 (set_attr "mode" "SI")])
6894 (define_expand "umuldi3_highpart"
6895 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6898 (mult:TI (zero_extend:TI
6899 (match_operand:DI 1 "nonimmediate_operand" ""))
6901 (match_operand:DI 2 "register_operand" "")))
6903 (clobber (match_scratch:DI 3 ""))
6904 (clobber (reg:CC 17))])]
6908 (define_insn "*umuldi3_highpart_rex64"
6909 [(set (match_operand:DI 0 "register_operand" "=d")
6912 (mult:TI (zero_extend:TI
6913 (match_operand:DI 1 "nonimmediate_operand" "%a"))
6915 (match_operand:DI 2 "nonimmediate_operand" "rm")))
6917 (clobber (match_scratch:DI 3 "=1"))
6918 (clobber (reg:CC 17))]
6920 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6922 [(set_attr "type" "imul")
6923 (set_attr "ppro_uops" "few")
6924 (set_attr "length_immediate" "0")
6925 (set_attr "mode" "DI")])
6927 (define_expand "umulsi3_highpart"
6928 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6931 (mult:DI (zero_extend:DI
6932 (match_operand:SI 1 "nonimmediate_operand" ""))
6934 (match_operand:SI 2 "register_operand" "")))
6936 (clobber (match_scratch:SI 3 ""))
6937 (clobber (reg:CC 17))])]
6941 (define_insn "*umulsi3_highpart_insn"
6942 [(set (match_operand:SI 0 "register_operand" "=d")
6945 (mult:DI (zero_extend:DI
6946 (match_operand:SI 1 "nonimmediate_operand" "%a"))
6948 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6950 (clobber (match_scratch:SI 3 "=1"))
6951 (clobber (reg:CC 17))]
6952 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6954 [(set_attr "type" "imul")
6955 (set_attr "ppro_uops" "few")
6956 (set_attr "length_immediate" "0")
6957 (set_attr "mode" "SI")])
6959 (define_insn "*umulsi3_highpart_zext"
6960 [(set (match_operand:DI 0 "register_operand" "=d")
6961 (zero_extend:DI (truncate:SI
6963 (mult:DI (zero_extend:DI
6964 (match_operand:SI 1 "nonimmediate_operand" "%a"))
6966 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6968 (clobber (match_scratch:SI 3 "=1"))
6969 (clobber (reg:CC 17))]
6971 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6973 [(set_attr "type" "imul")
6974 (set_attr "ppro_uops" "few")
6975 (set_attr "length_immediate" "0")
6976 (set_attr "mode" "SI")])
6978 (define_expand "smuldi3_highpart"
6979 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
6982 (mult:TI (sign_extend:TI
6983 (match_operand:DI 1 "nonimmediate_operand" ""))
6985 (match_operand:DI 2 "register_operand" "")))
6987 (clobber (match_scratch:DI 3 ""))
6988 (clobber (reg:CC 17))])]
6992 (define_insn "*smuldi3_highpart_rex64"
6993 [(set (match_operand:DI 0 "register_operand" "=d")
6996 (mult:TI (sign_extend:TI
6997 (match_operand:DI 1 "nonimmediate_operand" "%a"))
6999 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7001 (clobber (match_scratch:DI 3 "=1"))
7002 (clobber (reg:CC 17))]
7004 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7006 [(set_attr "type" "imul")
7007 (set_attr "ppro_uops" "few")
7008 (set_attr "mode" "DI")])
7010 (define_expand "smulsi3_highpart"
7011 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7014 (mult:DI (sign_extend:DI
7015 (match_operand:SI 1 "nonimmediate_operand" ""))
7017 (match_operand:SI 2 "register_operand" "")))
7019 (clobber (match_scratch:SI 3 ""))
7020 (clobber (reg:CC 17))])]
7024 (define_insn "*smulsi3_highpart_insn"
7025 [(set (match_operand:SI 0 "register_operand" "=d")
7028 (mult:DI (sign_extend:DI
7029 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7031 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7033 (clobber (match_scratch:SI 3 "=1"))
7034 (clobber (reg:CC 17))]
7035 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7037 [(set_attr "type" "imul")
7038 (set_attr "ppro_uops" "few")
7039 (set_attr "mode" "SI")])
7041 (define_insn "*smulsi3_highpart_zext"
7042 [(set (match_operand:DI 0 "register_operand" "=d")
7043 (zero_extend:DI (truncate:SI
7045 (mult:DI (sign_extend:DI
7046 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7048 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7050 (clobber (match_scratch:SI 3 "=1"))
7051 (clobber (reg:CC 17))]
7053 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7055 [(set_attr "type" "imul")
7056 (set_attr "ppro_uops" "few")
7057 (set_attr "mode" "SI")])
7059 ;; The patterns that match these are at the end of this file.
7061 (define_expand "mulxf3"
7062 [(set (match_operand:XF 0 "register_operand" "")
7063 (mult:XF (match_operand:XF 1 "register_operand" "")
7064 (match_operand:XF 2 "register_operand" "")))]
7065 "!TARGET_64BIT && TARGET_80387"
7068 (define_expand "multf3"
7069 [(set (match_operand:TF 0 "register_operand" "")
7070 (mult:TF (match_operand:TF 1 "register_operand" "")
7071 (match_operand:TF 2 "register_operand" "")))]
7075 (define_expand "muldf3"
7076 [(set (match_operand:DF 0 "register_operand" "")
7077 (mult:DF (match_operand:DF 1 "register_operand" "")
7078 (match_operand:DF 2 "nonimmediate_operand" "")))]
7079 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7082 (define_expand "mulsf3"
7083 [(set (match_operand:SF 0 "register_operand" "")
7084 (mult:SF (match_operand:SF 1 "register_operand" "")
7085 (match_operand:SF 2 "nonimmediate_operand" "")))]
7086 "TARGET_80387 || TARGET_SSE_MATH"
7089 ;; Divide instructions
7091 (define_insn "divqi3"
7092 [(set (match_operand:QI 0 "register_operand" "=a")
7093 (div:QI (match_operand:HI 1 "register_operand" "0")
7094 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7095 (clobber (reg:CC 17))]
7096 "TARGET_QIMODE_MATH"
7098 [(set_attr "type" "idiv")
7099 (set_attr "mode" "QI")
7100 (set_attr "ppro_uops" "few")])
7102 (define_insn "udivqi3"
7103 [(set (match_operand:QI 0 "register_operand" "=a")
7104 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7105 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7106 (clobber (reg:CC 17))]
7107 "TARGET_QIMODE_MATH"
7109 [(set_attr "type" "idiv")
7110 (set_attr "mode" "QI")
7111 (set_attr "ppro_uops" "few")])
7113 ;; The patterns that match these are at the end of this file.
7115 (define_expand "divxf3"
7116 [(set (match_operand:XF 0 "register_operand" "")
7117 (div:XF (match_operand:XF 1 "register_operand" "")
7118 (match_operand:XF 2 "register_operand" "")))]
7119 "!TARGET_64BIT && TARGET_80387"
7122 (define_expand "divtf3"
7123 [(set (match_operand:TF 0 "register_operand" "")
7124 (div:TF (match_operand:TF 1 "register_operand" "")
7125 (match_operand:TF 2 "register_operand" "")))]
7129 (define_expand "divdf3"
7130 [(set (match_operand:DF 0 "register_operand" "")
7131 (div:DF (match_operand:DF 1 "register_operand" "")
7132 (match_operand:DF 2 "nonimmediate_operand" "")))]
7133 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7136 (define_expand "divsf3"
7137 [(set (match_operand:SF 0 "register_operand" "")
7138 (div:SF (match_operand:SF 1 "register_operand" "")
7139 (match_operand:SF 2 "nonimmediate_operand" "")))]
7140 "TARGET_80387 || TARGET_SSE_MATH"
7143 ;; Remainder instructions.
7145 (define_expand "divmoddi4"
7146 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7147 (div:DI (match_operand:DI 1 "register_operand" "")
7148 (match_operand:DI 2 "nonimmediate_operand" "")))
7149 (set (match_operand:DI 3 "register_operand" "")
7150 (mod:DI (match_dup 1) (match_dup 2)))
7151 (clobber (reg:CC 17))])]
7155 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7156 ;; Penalize eax case sligthly because it results in worse scheduling
7158 (define_insn "*divmoddi4_nocltd_rex64"
7159 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7160 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7161 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7162 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7163 (mod:DI (match_dup 2) (match_dup 3)))
7164 (clobber (reg:CC 17))]
7165 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7167 [(set_attr "type" "multi")])
7169 (define_insn "*divmoddi4_cltd_rex64"
7170 [(set (match_operand:DI 0 "register_operand" "=a")
7171 (div:DI (match_operand:DI 2 "register_operand" "a")
7172 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7173 (set (match_operand:DI 1 "register_operand" "=&d")
7174 (mod:DI (match_dup 2) (match_dup 3)))
7175 (clobber (reg:CC 17))]
7176 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7178 [(set_attr "type" "multi")])
7180 (define_insn "*divmoddi_noext_rex64"
7181 [(set (match_operand:DI 0 "register_operand" "=a")
7182 (div:DI (match_operand:DI 1 "register_operand" "0")
7183 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7184 (set (match_operand:DI 3 "register_operand" "=d")
7185 (mod:DI (match_dup 1) (match_dup 2)))
7186 (use (match_operand:DI 4 "register_operand" "3"))
7187 (clobber (reg:CC 17))]
7190 [(set_attr "type" "idiv")
7191 (set_attr "mode" "DI")
7192 (set_attr "ppro_uops" "few")])
7195 [(set (match_operand:DI 0 "register_operand" "")
7196 (div:DI (match_operand:DI 1 "register_operand" "")
7197 (match_operand:DI 2 "nonimmediate_operand" "")))
7198 (set (match_operand:DI 3 "register_operand" "")
7199 (mod:DI (match_dup 1) (match_dup 2)))
7200 (clobber (reg:CC 17))]
7201 "TARGET_64BIT && reload_completed"
7202 [(parallel [(set (match_dup 3)
7203 (ashiftrt:DI (match_dup 4) (const_int 63)))
7204 (clobber (reg:CC 17))])
7205 (parallel [(set (match_dup 0)
7206 (div:DI (reg:DI 0) (match_dup 2)))
7208 (mod:DI (reg:DI 0) (match_dup 2)))
7210 (clobber (reg:CC 17))])]
7212 /* Avoid use of cltd in favour of a mov+shift. */
7213 if (!TARGET_USE_CLTD && !optimize_size)
7215 if (true_regnum (operands[1]))
7216 emit_move_insn (operands[0], operands[1]);
7218 emit_move_insn (operands[3], operands[1]);
7219 operands[4] = operands[3];
7223 if (true_regnum (operands[1]))
7225 operands[4] = operands[1];
7230 (define_expand "divmodsi4"
7231 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7232 (div:SI (match_operand:SI 1 "register_operand" "")
7233 (match_operand:SI 2 "nonimmediate_operand" "")))
7234 (set (match_operand:SI 3 "register_operand" "")
7235 (mod:SI (match_dup 1) (match_dup 2)))
7236 (clobber (reg:CC 17))])]
7240 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7241 ;; Penalize eax case sligthly because it results in worse scheduling
7243 (define_insn "*divmodsi4_nocltd"
7244 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7245 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7246 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7247 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7248 (mod:SI (match_dup 2) (match_dup 3)))
7249 (clobber (reg:CC 17))]
7250 "!optimize_size && !TARGET_USE_CLTD"
7252 [(set_attr "type" "multi")])
7254 (define_insn "*divmodsi4_cltd"
7255 [(set (match_operand:SI 0 "register_operand" "=a")
7256 (div:SI (match_operand:SI 2 "register_operand" "a")
7257 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7258 (set (match_operand:SI 1 "register_operand" "=&d")
7259 (mod:SI (match_dup 2) (match_dup 3)))
7260 (clobber (reg:CC 17))]
7261 "optimize_size || TARGET_USE_CLTD"
7263 [(set_attr "type" "multi")])
7265 (define_insn "*divmodsi_noext"
7266 [(set (match_operand:SI 0 "register_operand" "=a")
7267 (div:SI (match_operand:SI 1 "register_operand" "0")
7268 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7269 (set (match_operand:SI 3 "register_operand" "=d")
7270 (mod:SI (match_dup 1) (match_dup 2)))
7271 (use (match_operand:SI 4 "register_operand" "3"))
7272 (clobber (reg:CC 17))]
7275 [(set_attr "type" "idiv")
7276 (set_attr "mode" "SI")
7277 (set_attr "ppro_uops" "few")])
7280 [(set (match_operand:SI 0 "register_operand" "")
7281 (div:SI (match_operand:SI 1 "register_operand" "")
7282 (match_operand:SI 2 "nonimmediate_operand" "")))
7283 (set (match_operand:SI 3 "register_operand" "")
7284 (mod:SI (match_dup 1) (match_dup 2)))
7285 (clobber (reg:CC 17))]
7287 [(parallel [(set (match_dup 3)
7288 (ashiftrt:SI (match_dup 4) (const_int 31)))
7289 (clobber (reg:CC 17))])
7290 (parallel [(set (match_dup 0)
7291 (div:SI (reg:SI 0) (match_dup 2)))
7293 (mod:SI (reg:SI 0) (match_dup 2)))
7295 (clobber (reg:CC 17))])]
7297 /* Avoid use of cltd in favour of a mov+shift. */
7298 if (!TARGET_USE_CLTD && !optimize_size)
7300 if (true_regnum (operands[1]))
7301 emit_move_insn (operands[0], operands[1]);
7303 emit_move_insn (operands[3], operands[1]);
7304 operands[4] = operands[3];
7308 if (true_regnum (operands[1]))
7310 operands[4] = operands[1];
7314 (define_insn "divmodhi4"
7315 [(set (match_operand:HI 0 "register_operand" "=a")
7316 (div:HI (match_operand:HI 1 "register_operand" "0")
7317 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7318 (set (match_operand:HI 3 "register_operand" "=&d")
7319 (mod:HI (match_dup 1) (match_dup 2)))
7320 (clobber (reg:CC 17))]
7321 "TARGET_HIMODE_MATH"
7323 [(set_attr "type" "multi")
7324 (set_attr "length_immediate" "0")
7325 (set_attr "mode" "SI")])
7327 (define_insn "udivmoddi4"
7328 [(set (match_operand:DI 0 "register_operand" "=a")
7329 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7330 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7331 (set (match_operand:DI 3 "register_operand" "=&d")
7332 (umod:DI (match_dup 1) (match_dup 2)))
7333 (clobber (reg:CC 17))]
7335 "xor{q}\t%3, %3\;div{q}\t%2"
7336 [(set_attr "type" "multi")
7337 (set_attr "length_immediate" "0")
7338 (set_attr "mode" "DI")])
7340 (define_insn "*udivmoddi4_noext"
7341 [(set (match_operand:DI 0 "register_operand" "=a")
7342 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7343 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7344 (set (match_operand:DI 3 "register_operand" "=d")
7345 (umod:DI (match_dup 1) (match_dup 2)))
7347 (clobber (reg:CC 17))]
7350 [(set_attr "type" "idiv")
7351 (set_attr "ppro_uops" "few")
7352 (set_attr "mode" "DI")])
7355 [(set (match_operand:DI 0 "register_operand" "")
7356 (udiv:DI (match_operand:DI 1 "register_operand" "")
7357 (match_operand:DI 2 "nonimmediate_operand" "")))
7358 (set (match_operand:DI 3 "register_operand" "")
7359 (umod:DI (match_dup 1) (match_dup 2)))
7360 (clobber (reg:CC 17))]
7361 "TARGET_64BIT && reload_completed"
7362 [(set (match_dup 3) (const_int 0))
7363 (parallel [(set (match_dup 0)
7364 (udiv:DI (match_dup 1) (match_dup 2)))
7366 (umod:DI (match_dup 1) (match_dup 2)))
7368 (clobber (reg:CC 17))])]
7371 (define_insn "udivmodsi4"
7372 [(set (match_operand:SI 0 "register_operand" "=a")
7373 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7374 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7375 (set (match_operand:SI 3 "register_operand" "=&d")
7376 (umod:SI (match_dup 1) (match_dup 2)))
7377 (clobber (reg:CC 17))]
7379 "xor{l}\t%3, %3\;div{l}\t%2"
7380 [(set_attr "type" "multi")
7381 (set_attr "length_immediate" "0")
7382 (set_attr "mode" "SI")])
7384 (define_insn "*udivmodsi4_noext"
7385 [(set (match_operand:SI 0 "register_operand" "=a")
7386 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7387 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7388 (set (match_operand:SI 3 "register_operand" "=d")
7389 (umod:SI (match_dup 1) (match_dup 2)))
7391 (clobber (reg:CC 17))]
7394 [(set_attr "type" "idiv")
7395 (set_attr "ppro_uops" "few")
7396 (set_attr "mode" "SI")])
7399 [(set (match_operand:SI 0 "register_operand" "")
7400 (udiv:SI (match_operand:SI 1 "register_operand" "")
7401 (match_operand:SI 2 "nonimmediate_operand" "")))
7402 (set (match_operand:SI 3 "register_operand" "")
7403 (umod:SI (match_dup 1) (match_dup 2)))
7404 (clobber (reg:CC 17))]
7406 [(set (match_dup 3) (const_int 0))
7407 (parallel [(set (match_dup 0)
7408 (udiv:SI (match_dup 1) (match_dup 2)))
7410 (umod:SI (match_dup 1) (match_dup 2)))
7412 (clobber (reg:CC 17))])]
7415 (define_expand "udivmodhi4"
7416 [(set (match_dup 4) (const_int 0))
7417 (parallel [(set (match_operand:HI 0 "register_operand" "")
7418 (udiv:HI (match_operand:HI 1 "register_operand" "")
7419 (match_operand:HI 2 "nonimmediate_operand" "")))
7420 (set (match_operand:HI 3 "register_operand" "")
7421 (umod:HI (match_dup 1) (match_dup 2)))
7423 (clobber (reg:CC 17))])]
7424 "TARGET_HIMODE_MATH"
7425 "operands[4] = gen_reg_rtx (HImode);")
7427 (define_insn "*udivmodhi_noext"
7428 [(set (match_operand:HI 0 "register_operand" "=a")
7429 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7430 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7431 (set (match_operand:HI 3 "register_operand" "=d")
7432 (umod:HI (match_dup 1) (match_dup 2)))
7433 (use (match_operand:HI 4 "register_operand" "3"))
7434 (clobber (reg:CC 17))]
7437 [(set_attr "type" "idiv")
7438 (set_attr "mode" "HI")
7439 (set_attr "ppro_uops" "few")])
7441 ;; We can not use div/idiv for double division, because it causes
7442 ;; "division by zero" on the overflow and that's not what we expect
7443 ;; from truncate. Because true (non truncating) double division is
7444 ;; never generated, we can't create this insn anyway.
7447 ; [(set (match_operand:SI 0 "register_operand" "=a")
7449 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7451 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7452 ; (set (match_operand:SI 3 "register_operand" "=d")
7454 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7455 ; (clobber (reg:CC 17))]
7457 ; "div{l}\t{%2, %0|%0, %2}"
7458 ; [(set_attr "type" "idiv")
7459 ; (set_attr "ppro_uops" "few")])
7461 ;;- Logical AND instructions
7463 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7464 ;; Note that this excludes ah.
7466 (define_insn "*testdi_1_rex64"
7469 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7470 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7472 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7474 test{l}\t{%k1, %k0|%k0, %k1}
7475 test{l}\t{%k1, %k0|%k0, %k1}
7476 test{q}\t{%1, %0|%0, %1}
7477 test{q}\t{%1, %0|%0, %1}
7478 test{q}\t{%1, %0|%0, %1}"
7479 [(set_attr "type" "test")
7480 (set_attr "modrm" "0,1,0,1,1")
7481 (set_attr "mode" "SI,SI,DI,DI,DI")
7482 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7484 (define_insn "testsi_1"
7487 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7488 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7490 "ix86_match_ccmode (insn, CCNOmode)"
7491 "test{l}\t{%1, %0|%0, %1}"
7492 [(set_attr "type" "test")
7493 (set_attr "modrm" "0,1,1")
7494 (set_attr "mode" "SI")
7495 (set_attr "pent_pair" "uv,np,uv")])
7497 (define_expand "testsi_ccno_1"
7500 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7501 (match_operand:SI 1 "nonmemory_operand" ""))
7506 (define_insn "*testhi_1"
7508 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7509 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7511 "ix86_match_ccmode (insn, CCNOmode)"
7512 "test{w}\t{%1, %0|%0, %1}"
7513 [(set_attr "type" "test")
7514 (set_attr "modrm" "0,1,1")
7515 (set_attr "mode" "HI")
7516 (set_attr "pent_pair" "uv,np,uv")])
7518 (define_expand "testqi_ccz_1"
7520 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7521 (match_operand:QI 1 "nonmemory_operand" ""))
7526 (define_insn "*testqi_1"
7528 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7529 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7531 "ix86_match_ccmode (insn, CCNOmode)"
7533 if (which_alternative == 3)
7535 if (GET_CODE (operands[1]) == CONST_INT
7536 && (INTVAL (operands[1]) & 0xffffff00))
7537 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7538 return "test{l}\t{%1, %k0|%k0, %1}";
7540 return "test{b}\t{%1, %0|%0, %1}";
7542 [(set_attr "type" "test")
7543 (set_attr "modrm" "0,1,1,1")
7544 (set_attr "mode" "QI,QI,QI,SI")
7545 (set_attr "pent_pair" "uv,np,uv,np")])
7547 (define_expand "testqi_ext_ccno_0"
7552 (match_operand 0 "ext_register_operand" "")
7555 (match_operand 1 "const_int_operand" ""))
7560 (define_insn "*testqi_ext_0"
7565 (match_operand 0 "ext_register_operand" "Q")
7568 (match_operand 1 "const_int_operand" "n"))
7570 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
7571 && ix86_match_ccmode (insn, CCNOmode)"
7572 "test{b}\t{%1, %h0|%h0, %1}"
7573 [(set_attr "type" "test")
7574 (set_attr "mode" "QI")
7575 (set_attr "length_immediate" "1")
7576 (set_attr "pent_pair" "np")])
7578 (define_insn "*testqi_ext_1"
7583 (match_operand 0 "ext_register_operand" "Q")
7587 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
7589 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7590 "test{b}\t{%1, %h0|%h0, %1}"
7591 [(set_attr "type" "test")
7592 (set_attr "mode" "QI")])
7594 (define_insn "*testqi_ext_1_rex64"
7599 (match_operand 0 "ext_register_operand" "Q")
7603 (match_operand:QI 1 "register_operand" "Q")))
7605 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7606 "test{b}\t{%1, %h0|%h0, %1}"
7607 [(set_attr "type" "test")
7608 (set_attr "mode" "QI")])
7610 (define_insn "*testqi_ext_2"
7615 (match_operand 0 "ext_register_operand" "Q")
7619 (match_operand 1 "ext_register_operand" "Q")
7623 "ix86_match_ccmode (insn, CCNOmode)"
7624 "test{b}\t{%h1, %h0|%h0, %h1}"
7625 [(set_attr "type" "test")
7626 (set_attr "mode" "QI")])
7628 ;; Combine likes to form bit extractions for some tests. Humor it.
7629 (define_insn "*testqi_ext_3"
7631 (compare (zero_extract:SI
7632 (match_operand 0 "nonimmediate_operand" "rm")
7633 (match_operand:SI 1 "const_int_operand" "")
7634 (match_operand:SI 2 "const_int_operand" ""))
7636 "ix86_match_ccmode (insn, CCNOmode)
7637 && (GET_MODE (operands[0]) == SImode
7638 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7639 || GET_MODE (operands[0]) == HImode
7640 || GET_MODE (operands[0]) == QImode)"
7643 (define_insn "*testqi_ext_3_rex64"
7645 (compare (zero_extract:DI
7646 (match_operand 0 "nonimmediate_operand" "rm")
7647 (match_operand:DI 1 "const_int_operand" "")
7648 (match_operand:DI 2 "const_int_operand" ""))
7651 && ix86_match_ccmode (insn, CCNOmode)
7652 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
7653 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
7654 /* Ensure that resulting mask is zero or sign extended operand. */
7655 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7656 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
7657 && INTVAL (operands[1]) > 32))
7658 && (GET_MODE (operands[0]) == SImode
7659 || GET_MODE (operands[0]) == DImode
7660 || GET_MODE (operands[0]) == HImode
7661 || GET_MODE (operands[0]) == QImode)"
7666 (compare (zero_extract
7667 (match_operand 0 "nonimmediate_operand" "")
7668 (match_operand 1 "const_int_operand" "")
7669 (match_operand 2 "const_int_operand" ""))
7671 "ix86_match_ccmode (insn, CCNOmode)"
7672 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
7674 HOST_WIDE_INT len = INTVAL (operands[1]);
7675 HOST_WIDE_INT pos = INTVAL (operands[2]);
7677 enum machine_mode mode, submode;
7679 mode = GET_MODE (operands[0]);
7680 if (GET_CODE (operands[0]) == MEM)
7682 /* ??? Combine likes to put non-volatile mem extractions in QImode
7683 no matter the size of the test. So find a mode that works. */
7684 if (! MEM_VOLATILE_P (operands[0]))
7686 mode = smallest_mode_for_size (pos + len, MODE_INT);
7687 operands[0] = adjust_address (operands[0], mode, 0);
7690 else if (GET_CODE (operands[0]) == SUBREG
7691 && (submode = GET_MODE (SUBREG_REG (operands[0])),
7692 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
7693 && pos + len <= GET_MODE_BITSIZE (submode))
7695 /* Narrow a paradoxical subreg to prevent partial register stalls. */
7697 operands[0] = SUBREG_REG (operands[0]);
7699 else if (mode == HImode && pos + len <= 8)
7701 /* Small HImode tests can be converted to QImode. */
7703 operands[0] = gen_lowpart (QImode, operands[0]);
7706 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
7707 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
7709 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
7712 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
7713 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
7714 ;; this is relatively important trick.
7715 ;; Do the converison only post-reload to avoid limiting of the register class
7720 (and (match_operand 0 "register_operand" "")
7721 (match_operand 1 "const_int_operand" ""))
7723 "(!TARGET_PROMOTE_QImode || optimize_size)
7725 && QI_REG_P (operands[0])
7726 && ((ix86_match_ccmode (insn, CCZmode)
7727 && !(INTVAL (operands[1]) & ~(255 << 8)))
7728 || (ix86_match_ccmode (insn, CCNOmode)
7729 && !(INTVAL (operands[1]) & ~(127 << 8))))
7730 && GET_MODE (operands[0]) != QImode"
7733 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
7736 "operands[0] = gen_lowpart (SImode, operands[0]);
7737 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
7742 (and (match_operand 0 "nonimmediate_operand" "")
7743 (match_operand 1 "const_int_operand" ""))
7745 "(!TARGET_PROMOTE_QImode || optimize_size)
7747 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
7748 && ((ix86_match_ccmode (insn, CCZmode)
7749 && !(INTVAL (operands[1]) & ~255))
7750 || (ix86_match_ccmode (insn, CCNOmode)
7751 && !(INTVAL (operands[1]) & ~127)))
7752 && GET_MODE (operands[0]) != QImode"
7755 (and:QI (match_dup 0)
7758 "operands[0] = gen_lowpart (QImode, operands[0]);
7759 operands[1] = gen_lowpart (QImode, operands[1]);")
7762 ;; %%% This used to optimize known byte-wide and operations to memory,
7763 ;; and sometimes to QImode registers. If this is considered useful,
7764 ;; it should be done with splitters.
7766 (define_expand "anddi3"
7767 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7768 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
7769 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
7770 (clobber (reg:CC 17))]
7772 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
7774 (define_insn "*anddi_1_rex64"
7775 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
7776 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
7777 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
7778 (clobber (reg:CC 17))]
7779 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
7781 switch (get_attr_type (insn))
7785 enum machine_mode mode;
7787 if (GET_CODE (operands[2]) != CONST_INT)
7789 if (INTVAL (operands[2]) == 0xff)
7791 else if (INTVAL (operands[2]) == 0xffff)
7796 operands[1] = gen_lowpart (mode, operands[1]);
7798 return "movz{bq|x}\t{%1,%0|%0, %1}";
7800 return "movz{wq|x}\t{%1,%0|%0, %1}";
7804 if (! rtx_equal_p (operands[0], operands[1]))
7806 if (get_attr_mode (insn) == MODE_SI)
7807 return "and{l}\t{%k2, %k0|%k0, %k2}";
7809 return "and{q}\t{%2, %0|%0, %2}";
7812 [(set_attr "type" "alu,alu,alu,imovx")
7813 (set_attr "length_immediate" "*,*,*,0")
7814 (set_attr "mode" "SI,DI,DI,DI")])
7816 (define_insn "*anddi_2"
7818 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
7819 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
7821 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
7822 (and:DI (match_dup 1) (match_dup 2)))]
7823 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7824 && ix86_binary_operator_ok (AND, DImode, operands)"
7826 and{l}\t{%k2, %k0|%k0, %k2}
7827 and{q}\t{%2, %0|%0, %2}
7828 and{q}\t{%2, %0|%0, %2}"
7829 [(set_attr "type" "alu")
7830 (set_attr "mode" "SI,DI,DI")])
7832 (define_expand "andsi3"
7833 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7834 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
7835 (match_operand:SI 2 "general_operand" "")))
7836 (clobber (reg:CC 17))]
7838 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
7840 (define_insn "*andsi_1"
7841 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
7842 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
7843 (match_operand:SI 2 "general_operand" "ri,rm,L")))
7844 (clobber (reg:CC 17))]
7845 "ix86_binary_operator_ok (AND, SImode, operands)"
7847 switch (get_attr_type (insn))
7851 enum machine_mode mode;
7853 if (GET_CODE (operands[2]) != CONST_INT)
7855 if (INTVAL (operands[2]) == 0xff)
7857 else if (INTVAL (operands[2]) == 0xffff)
7862 operands[1] = gen_lowpart (mode, operands[1]);
7864 return "movz{bl|x}\t{%1,%0|%0, %1}";
7866 return "movz{wl|x}\t{%1,%0|%0, %1}";
7870 if (! rtx_equal_p (operands[0], operands[1]))
7872 return "and{l}\t{%2, %0|%0, %2}";
7875 [(set_attr "type" "alu,alu,imovx")
7876 (set_attr "length_immediate" "*,*,0")
7877 (set_attr "mode" "SI")])
7880 [(set (match_operand 0 "register_operand" "")
7882 (const_int -65536)))
7883 (clobber (reg:CC 17))]
7885 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7886 "operands[1] = gen_lowpart (HImode, operands[0]);")
7889 [(set (match_operand 0 "ext_register_operand" "")
7892 (clobber (reg:CC 17))]
7893 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
7894 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7895 "operands[1] = gen_lowpart (QImode, operands[0]);")
7898 [(set (match_operand 0 "ext_register_operand" "")
7900 (const_int -65281)))
7901 (clobber (reg:CC 17))]
7902 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
7903 [(parallel [(set (zero_extract:SI (match_dup 0)
7907 (zero_extract:SI (match_dup 0)
7910 (zero_extract:SI (match_dup 0)
7913 (clobber (reg:CC 17))])]
7914 "operands[0] = gen_lowpart (SImode, operands[0]);")
7916 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7917 (define_insn "*andsi_1_zext"
7918 [(set (match_operand:DI 0 "register_operand" "=r")
7920 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7921 (match_operand:SI 2 "general_operand" "rim"))))
7922 (clobber (reg:CC 17))]
7923 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
7924 "and{l}\t{%2, %k0|%k0, %2}"
7925 [(set_attr "type" "alu")
7926 (set_attr "mode" "SI")])
7928 (define_insn "*andsi_2"
7930 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7931 (match_operand:SI 2 "general_operand" "rim,ri"))
7933 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
7934 (and:SI (match_dup 1) (match_dup 2)))]
7935 "ix86_match_ccmode (insn, CCNOmode)
7936 && ix86_binary_operator_ok (AND, SImode, operands)"
7937 "and{l}\t{%2, %0|%0, %2}"
7938 [(set_attr "type" "alu")
7939 (set_attr "mode" "SI")])
7941 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7942 (define_insn "*andsi_2_zext"
7944 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7945 (match_operand:SI 2 "general_operand" "rim"))
7947 (set (match_operand:DI 0 "register_operand" "=r")
7948 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
7949 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7950 && ix86_binary_operator_ok (AND, SImode, operands)"
7951 "and{l}\t{%2, %k0|%k0, %2}"
7952 [(set_attr "type" "alu")
7953 (set_attr "mode" "SI")])
7955 (define_expand "andhi3"
7956 [(set (match_operand:HI 0 "nonimmediate_operand" "")
7957 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
7958 (match_operand:HI 2 "general_operand" "")))
7959 (clobber (reg:CC 17))]
7960 "TARGET_HIMODE_MATH"
7961 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
7963 (define_insn "*andhi_1"
7964 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
7965 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
7966 (match_operand:HI 2 "general_operand" "ri,rm,L")))
7967 (clobber (reg:CC 17))]
7968 "ix86_binary_operator_ok (AND, HImode, operands)"
7970 switch (get_attr_type (insn))
7973 if (GET_CODE (operands[2]) != CONST_INT)
7975 if (INTVAL (operands[2]) == 0xff)
7976 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
7980 if (! rtx_equal_p (operands[0], operands[1]))
7983 return "and{w}\t{%2, %0|%0, %2}";
7986 [(set_attr "type" "alu,alu,imovx")
7987 (set_attr "length_immediate" "*,*,0")
7988 (set_attr "mode" "HI,HI,SI")])
7990 (define_insn "*andhi_2"
7992 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
7993 (match_operand:HI 2 "general_operand" "rim,ri"))
7995 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
7996 (and:HI (match_dup 1) (match_dup 2)))]
7997 "ix86_match_ccmode (insn, CCNOmode)
7998 && ix86_binary_operator_ok (AND, HImode, operands)"
7999 "and{w}\t{%2, %0|%0, %2}"
8000 [(set_attr "type" "alu")
8001 (set_attr "mode" "HI")])
8003 (define_expand "andqi3"
8004 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8005 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8006 (match_operand:QI 2 "general_operand" "")))
8007 (clobber (reg:CC 17))]
8008 "TARGET_QIMODE_MATH"
8009 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8011 ;; %%% Potential partial reg stall on alternative 2. What to do?
8012 (define_insn "*andqi_1"
8013 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8014 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8015 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8016 (clobber (reg:CC 17))]
8017 "ix86_binary_operator_ok (AND, QImode, operands)"
8019 and{b}\t{%2, %0|%0, %2}
8020 and{b}\t{%2, %0|%0, %2}
8021 and{l}\t{%k2, %k0|%k0, %k2}"
8022 [(set_attr "type" "alu")
8023 (set_attr "mode" "QI,QI,SI")])
8025 (define_insn "*andqi_1_slp"
8026 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8027 (and:QI (match_dup 0)
8028 (match_operand:QI 1 "general_operand" "qi,qmi")))
8029 (clobber (reg:CC 17))]
8031 "and{b}\t{%1, %0|%0, %1}"
8032 [(set_attr "type" "alu1")
8033 (set_attr "mode" "QI")])
8035 (define_insn "*andqi_2"
8038 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8039 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8041 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8042 (and:QI (match_dup 1) (match_dup 2)))]
8043 "ix86_match_ccmode (insn, CCNOmode)
8044 && ix86_binary_operator_ok (AND, QImode, operands)"
8046 if (which_alternative == 2)
8048 if (GET_CODE (operands[2]) == CONST_INT
8049 && (INTVAL (operands[2]) & 0xffffff00))
8050 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8051 return "and{l}\t{%2, %k0|%k0, %2}";
8053 return "and{b}\t{%2, %0|%0, %2}";
8055 [(set_attr "type" "alu")
8056 (set_attr "mode" "QI,QI,SI")])
8058 (define_insn "*andqi_2_slp"
8061 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8062 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8064 (set (strict_low_part (match_dup 0))
8065 (and:QI (match_dup 0) (match_dup 1)))]
8066 "ix86_match_ccmode (insn, CCNOmode)"
8067 "and{b}\t{%1, %0|%0, %1}"
8068 [(set_attr "type" "alu1")
8069 (set_attr "mode" "QI")])
8071 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8072 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8073 ;; for a QImode operand, which of course failed.
8075 (define_insn "andqi_ext_0"
8076 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8081 (match_operand 1 "ext_register_operand" "0")
8084 (match_operand 2 "const_int_operand" "n")))
8085 (clobber (reg:CC 17))]
8086 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8087 "and{b}\t{%2, %h0|%h0, %2}"
8088 [(set_attr "type" "alu")
8089 (set_attr "length_immediate" "1")
8090 (set_attr "mode" "QI")])
8092 ;; Generated by peephole translating test to and. This shows up
8093 ;; often in fp comparisons.
8095 (define_insn "*andqi_ext_0_cc"
8100 (match_operand 1 "ext_register_operand" "0")
8103 (match_operand 2 "const_int_operand" "n"))
8105 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8114 "ix86_match_ccmode (insn, CCNOmode)
8115 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8116 "and{b}\t{%2, %h0|%h0, %2}"
8117 [(set_attr "type" "alu")
8118 (set_attr "length_immediate" "1")
8119 (set_attr "mode" "QI")])
8121 (define_insn "*andqi_ext_1"
8122 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8127 (match_operand 1 "ext_register_operand" "0")
8131 (match_operand:QI 2 "general_operand" "Qm"))))
8132 (clobber (reg:CC 17))]
8134 "and{b}\t{%2, %h0|%h0, %2}"
8135 [(set_attr "type" "alu")
8136 (set_attr "length_immediate" "0")
8137 (set_attr "mode" "QI")])
8139 (define_insn "*andqi_ext_1_rex64"
8140 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8145 (match_operand 1 "ext_register_operand" "0")
8149 (match_operand 2 "ext_register_operand" "Q"))))
8150 (clobber (reg:CC 17))]
8152 "and{b}\t{%2, %h0|%h0, %2}"
8153 [(set_attr "type" "alu")
8154 (set_attr "length_immediate" "0")
8155 (set_attr "mode" "QI")])
8157 (define_insn "*andqi_ext_2"
8158 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8163 (match_operand 1 "ext_register_operand" "%0")
8167 (match_operand 2 "ext_register_operand" "Q")
8170 (clobber (reg:CC 17))]
8172 "and{b}\t{%h2, %h0|%h0, %h2}"
8173 [(set_attr "type" "alu")
8174 (set_attr "length_immediate" "0")
8175 (set_attr "mode" "QI")])
8177 ;; Logical inclusive OR instructions
8179 ;; %%% This used to optimize known byte-wide and operations to memory.
8180 ;; If this is considered useful, it should be done with splitters.
8182 (define_expand "iordi3"
8183 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8184 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8185 (match_operand:DI 2 "x86_64_general_operand" "")))
8186 (clobber (reg:CC 17))]
8188 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8190 (define_insn "*iordi_1_rex64"
8191 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8192 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8193 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8194 (clobber (reg:CC 17))]
8196 && ix86_binary_operator_ok (IOR, DImode, operands)"
8197 "or{q}\t{%2, %0|%0, %2}"
8198 [(set_attr "type" "alu")
8199 (set_attr "mode" "DI")])
8201 (define_insn "*iordi_2_rex64"
8203 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8204 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8206 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8207 (ior:DI (match_dup 1) (match_dup 2)))]
8209 && ix86_match_ccmode (insn, CCNOmode)
8210 && ix86_binary_operator_ok (IOR, DImode, operands)"
8211 "or{q}\t{%2, %0|%0, %2}"
8212 [(set_attr "type" "alu")
8213 (set_attr "mode" "DI")])
8215 (define_insn "*iordi_3_rex64"
8217 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8218 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8220 (clobber (match_scratch:DI 0 "=r"))]
8222 && ix86_match_ccmode (insn, CCNOmode)
8223 && ix86_binary_operator_ok (IOR, DImode, operands)"
8224 "or{q}\t{%2, %0|%0, %2}"
8225 [(set_attr "type" "alu")
8226 (set_attr "mode" "DI")])
8229 (define_expand "iorsi3"
8230 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8231 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8232 (match_operand:SI 2 "general_operand" "")))
8233 (clobber (reg:CC 17))]
8235 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8237 (define_insn "*iorsi_1"
8238 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8239 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8240 (match_operand:SI 2 "general_operand" "ri,rmi")))
8241 (clobber (reg:CC 17))]
8242 "ix86_binary_operator_ok (IOR, SImode, operands)"
8243 "or{l}\t{%2, %0|%0, %2}"
8244 [(set_attr "type" "alu")
8245 (set_attr "mode" "SI")])
8247 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8248 (define_insn "*iorsi_1_zext"
8249 [(set (match_operand:DI 0 "register_operand" "=rm")
8251 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8252 (match_operand:SI 2 "general_operand" "rim"))))
8253 (clobber (reg:CC 17))]
8254 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8255 "or{l}\t{%2, %k0|%k0, %2}"
8256 [(set_attr "type" "alu")
8257 (set_attr "mode" "SI")])
8259 (define_insn "*iorsi_1_zext_imm"
8260 [(set (match_operand:DI 0 "register_operand" "=rm")
8261 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8262 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8263 (clobber (reg:CC 17))]
8265 "or{l}\t{%2, %k0|%k0, %2}"
8266 [(set_attr "type" "alu")
8267 (set_attr "mode" "SI")])
8269 (define_insn "*iorsi_2"
8271 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8272 (match_operand:SI 2 "general_operand" "rim,ri"))
8274 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8275 (ior:SI (match_dup 1) (match_dup 2)))]
8276 "ix86_match_ccmode (insn, CCNOmode)
8277 && ix86_binary_operator_ok (IOR, SImode, operands)"
8278 "or{l}\t{%2, %0|%0, %2}"
8279 [(set_attr "type" "alu")
8280 (set_attr "mode" "SI")])
8282 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8283 ;; ??? Special case for immediate operand is missing - it is tricky.
8284 (define_insn "*iorsi_2_zext"
8286 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8287 (match_operand:SI 2 "general_operand" "rim"))
8289 (set (match_operand:DI 0 "register_operand" "=r")
8290 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8291 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8292 && ix86_binary_operator_ok (IOR, SImode, operands)"
8293 "or{l}\t{%2, %k0|%k0, %2}"
8294 [(set_attr "type" "alu")
8295 (set_attr "mode" "SI")])
8297 (define_insn "*iorsi_2_zext_imm"
8299 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8300 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8302 (set (match_operand:DI 0 "register_operand" "=r")
8303 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8304 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8305 && ix86_binary_operator_ok (IOR, SImode, operands)"
8306 "or{l}\t{%2, %k0|%k0, %2}"
8307 [(set_attr "type" "alu")
8308 (set_attr "mode" "SI")])
8310 (define_insn "*iorsi_3"
8312 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8313 (match_operand:SI 2 "general_operand" "rim"))
8315 (clobber (match_scratch:SI 0 "=r"))]
8316 "ix86_match_ccmode (insn, CCNOmode)
8317 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8318 "or{l}\t{%2, %0|%0, %2}"
8319 [(set_attr "type" "alu")
8320 (set_attr "mode" "SI")])
8322 (define_expand "iorhi3"
8323 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8324 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8325 (match_operand:HI 2 "general_operand" "")))
8326 (clobber (reg:CC 17))]
8327 "TARGET_HIMODE_MATH"
8328 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8330 (define_insn "*iorhi_1"
8331 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8332 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8333 (match_operand:HI 2 "general_operand" "rmi,ri")))
8334 (clobber (reg:CC 17))]
8335 "ix86_binary_operator_ok (IOR, HImode, operands)"
8336 "or{w}\t{%2, %0|%0, %2}"
8337 [(set_attr "type" "alu")
8338 (set_attr "mode" "HI")])
8340 (define_insn "*iorhi_2"
8342 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8343 (match_operand:HI 2 "general_operand" "rim,ri"))
8345 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8346 (ior:HI (match_dup 1) (match_dup 2)))]
8347 "ix86_match_ccmode (insn, CCNOmode)
8348 && ix86_binary_operator_ok (IOR, HImode, operands)"
8349 "or{w}\t{%2, %0|%0, %2}"
8350 [(set_attr "type" "alu")
8351 (set_attr "mode" "HI")])
8353 (define_insn "*iorhi_3"
8355 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8356 (match_operand:HI 2 "general_operand" "rim"))
8358 (clobber (match_scratch:HI 0 "=r"))]
8359 "ix86_match_ccmode (insn, CCNOmode)
8360 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8361 "or{w}\t{%2, %0|%0, %2}"
8362 [(set_attr "type" "alu")
8363 (set_attr "mode" "HI")])
8365 (define_expand "iorqi3"
8366 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8367 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8368 (match_operand:QI 2 "general_operand" "")))
8369 (clobber (reg:CC 17))]
8370 "TARGET_QIMODE_MATH"
8371 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8373 ;; %%% Potential partial reg stall on alternative 2. What to do?
8374 (define_insn "*iorqi_1"
8375 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8376 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8377 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8378 (clobber (reg:CC 17))]
8379 "ix86_binary_operator_ok (IOR, QImode, operands)"
8381 or{b}\t{%2, %0|%0, %2}
8382 or{b}\t{%2, %0|%0, %2}
8383 or{l}\t{%k2, %k0|%k0, %k2}"
8384 [(set_attr "type" "alu")
8385 (set_attr "mode" "QI,QI,SI")])
8387 (define_insn "*iorqi_1_slp"
8388 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8389 (ior:QI (match_dup 0)
8390 (match_operand:QI 1 "general_operand" "qmi,qi")))
8391 (clobber (reg:CC 17))]
8393 "or{b}\t{%1, %0|%0, %1}"
8394 [(set_attr "type" "alu1")
8395 (set_attr "mode" "QI")])
8397 (define_insn "*iorqi_2"
8399 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8400 (match_operand:QI 2 "general_operand" "qim,qi"))
8402 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8403 (ior:QI (match_dup 1) (match_dup 2)))]
8404 "ix86_match_ccmode (insn, CCNOmode)
8405 && ix86_binary_operator_ok (IOR, QImode, operands)"
8406 "or{b}\t{%2, %0|%0, %2}"
8407 [(set_attr "type" "alu")
8408 (set_attr "mode" "QI")])
8410 (define_insn "*iorqi_2_slp"
8412 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8413 (match_operand:QI 1 "general_operand" "qim,qi"))
8415 (set (strict_low_part (match_dup 0))
8416 (ior:QI (match_dup 0) (match_dup 1)))]
8417 "ix86_match_ccmode (insn, CCNOmode)"
8418 "or{b}\t{%1, %0|%0, %1}"
8419 [(set_attr "type" "alu1")
8420 (set_attr "mode" "QI")])
8422 (define_insn "*iorqi_3"
8424 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8425 (match_operand:QI 2 "general_operand" "qim"))
8427 (clobber (match_scratch:QI 0 "=q"))]
8428 "ix86_match_ccmode (insn, CCNOmode)
8429 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8430 "or{b}\t{%2, %0|%0, %2}"
8431 [(set_attr "type" "alu")
8432 (set_attr "mode" "QI")])
8435 ;; Logical XOR instructions
8437 ;; %%% This used to optimize known byte-wide and operations to memory.
8438 ;; If this is considered useful, it should be done with splitters.
8440 (define_expand "xordi3"
8441 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8442 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8443 (match_operand:DI 2 "x86_64_general_operand" "")))
8444 (clobber (reg:CC 17))]
8446 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8448 (define_insn "*xordi_1_rex64"
8449 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8450 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8451 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8452 (clobber (reg:CC 17))]
8454 && ix86_binary_operator_ok (XOR, DImode, operands)"
8456 xor{q}\t{%2, %0|%0, %2}
8457 xor{q}\t{%2, %0|%0, %2}"
8458 [(set_attr "type" "alu")
8459 (set_attr "mode" "DI,DI")])
8461 (define_insn "*xordi_2_rex64"
8463 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8464 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8466 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8467 (xor:DI (match_dup 1) (match_dup 2)))]
8469 && ix86_match_ccmode (insn, CCNOmode)
8470 && ix86_binary_operator_ok (XOR, DImode, operands)"
8472 xor{q}\t{%2, %0|%0, %2}
8473 xor{q}\t{%2, %0|%0, %2}"
8474 [(set_attr "type" "alu")
8475 (set_attr "mode" "DI,DI")])
8477 (define_insn "*xordi_3_rex64"
8479 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8480 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8482 (clobber (match_scratch:DI 0 "=r"))]
8484 && ix86_match_ccmode (insn, CCNOmode)
8485 && ix86_binary_operator_ok (XOR, DImode, operands)"
8486 "xor{q}\t{%2, %0|%0, %2}"
8487 [(set_attr "type" "alu")
8488 (set_attr "mode" "DI")])
8490 (define_expand "xorsi3"
8491 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8492 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8493 (match_operand:SI 2 "general_operand" "")))
8494 (clobber (reg:CC 17))]
8496 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8498 (define_insn "*xorsi_1"
8499 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8500 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8501 (match_operand:SI 2 "general_operand" "ri,rm")))
8502 (clobber (reg:CC 17))]
8503 "ix86_binary_operator_ok (XOR, SImode, operands)"
8504 "xor{l}\t{%2, %0|%0, %2}"
8505 [(set_attr "type" "alu")
8506 (set_attr "mode" "SI")])
8508 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8509 ;; Add speccase for immediates
8510 (define_insn "*xorsi_1_zext"
8511 [(set (match_operand:DI 0 "register_operand" "=r")
8513 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8514 (match_operand:SI 2 "general_operand" "rim"))))
8515 (clobber (reg:CC 17))]
8516 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8517 "xor{l}\t{%2, %k0|%k0, %2}"
8518 [(set_attr "type" "alu")
8519 (set_attr "mode" "SI")])
8521 (define_insn "*xorsi_1_zext_imm"
8522 [(set (match_operand:DI 0 "register_operand" "=r")
8523 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8524 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8525 (clobber (reg:CC 17))]
8526 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8527 "xor{l}\t{%2, %k0|%k0, %2}"
8528 [(set_attr "type" "alu")
8529 (set_attr "mode" "SI")])
8531 (define_insn "*xorsi_2"
8533 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8534 (match_operand:SI 2 "general_operand" "rim,ri"))
8536 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8537 (xor:SI (match_dup 1) (match_dup 2)))]
8538 "ix86_match_ccmode (insn, CCNOmode)
8539 && ix86_binary_operator_ok (XOR, SImode, operands)"
8540 "xor{l}\t{%2, %0|%0, %2}"
8541 [(set_attr "type" "alu")
8542 (set_attr "mode" "SI")])
8544 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8545 ;; ??? Special case for immediate operand is missing - it is tricky.
8546 (define_insn "*xorsi_2_zext"
8548 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8549 (match_operand:SI 2 "general_operand" "rim"))
8551 (set (match_operand:DI 0 "register_operand" "=r")
8552 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8553 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8554 && ix86_binary_operator_ok (XOR, SImode, operands)"
8555 "xor{l}\t{%2, %k0|%k0, %2}"
8556 [(set_attr "type" "alu")
8557 (set_attr "mode" "SI")])
8559 (define_insn "*xorsi_2_zext_imm"
8561 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8562 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8564 (set (match_operand:DI 0 "register_operand" "=r")
8565 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8566 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8567 && ix86_binary_operator_ok (XOR, SImode, operands)"
8568 "xor{l}\t{%2, %k0|%k0, %2}"
8569 [(set_attr "type" "alu")
8570 (set_attr "mode" "SI")])
8572 (define_insn "*xorsi_3"
8574 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8575 (match_operand:SI 2 "general_operand" "rim"))
8577 (clobber (match_scratch:SI 0 "=r"))]
8578 "ix86_match_ccmode (insn, CCNOmode)
8579 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8580 "xor{l}\t{%2, %0|%0, %2}"
8581 [(set_attr "type" "alu")
8582 (set_attr "mode" "SI")])
8584 (define_expand "xorhi3"
8585 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8586 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8587 (match_operand:HI 2 "general_operand" "")))
8588 (clobber (reg:CC 17))]
8589 "TARGET_HIMODE_MATH"
8590 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
8592 (define_insn "*xorhi_1"
8593 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8594 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8595 (match_operand:HI 2 "general_operand" "rmi,ri")))
8596 (clobber (reg:CC 17))]
8597 "ix86_binary_operator_ok (XOR, HImode, operands)"
8598 "xor{w}\t{%2, %0|%0, %2}"
8599 [(set_attr "type" "alu")
8600 (set_attr "mode" "HI")])
8602 (define_insn "*xorhi_2"
8604 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8605 (match_operand:HI 2 "general_operand" "rim,ri"))
8607 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8608 (xor:HI (match_dup 1) (match_dup 2)))]
8609 "ix86_match_ccmode (insn, CCNOmode)
8610 && ix86_binary_operator_ok (XOR, HImode, operands)"
8611 "xor{w}\t{%2, %0|%0, %2}"
8612 [(set_attr "type" "alu")
8613 (set_attr "mode" "HI")])
8615 (define_insn "*xorhi_3"
8617 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8618 (match_operand:HI 2 "general_operand" "rim"))
8620 (clobber (match_scratch:HI 0 "=r"))]
8621 "ix86_match_ccmode (insn, CCNOmode)
8622 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8623 "xor{w}\t{%2, %0|%0, %2}"
8624 [(set_attr "type" "alu")
8625 (set_attr "mode" "HI")])
8627 (define_expand "xorqi3"
8628 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8629 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
8630 (match_operand:QI 2 "general_operand" "")))
8631 (clobber (reg:CC 17))]
8632 "TARGET_QIMODE_MATH"
8633 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
8635 ;; %%% Potential partial reg stall on alternative 2. What to do?
8636 (define_insn "*xorqi_1"
8637 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8638 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8639 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8640 (clobber (reg:CC 17))]
8641 "ix86_binary_operator_ok (XOR, QImode, operands)"
8643 xor{b}\t{%2, %0|%0, %2}
8644 xor{b}\t{%2, %0|%0, %2}
8645 xor{l}\t{%k2, %k0|%k0, %k2}"
8646 [(set_attr "type" "alu")
8647 (set_attr "mode" "QI,QI,SI")])
8649 (define_insn "*xorqi_ext_1"
8650 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8654 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8657 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8660 (clobber (reg:CC 17))]
8662 "xor{b}\t{%h2, %h0|%h0, %h2}"
8663 [(set_attr "type" "alu")
8664 (set_attr "length_immediate" "0")
8665 (set_attr "mode" "QI")])
8667 (define_insn "*xorqi_cc_1"
8670 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8671 (match_operand:QI 2 "general_operand" "qim,qi"))
8673 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8674 (xor:QI (match_dup 1) (match_dup 2)))]
8675 "ix86_match_ccmode (insn, CCNOmode)
8676 && ix86_binary_operator_ok (XOR, QImode, operands)"
8677 "xor{b}\t{%2, %0|%0, %2}"
8678 [(set_attr "type" "alu")
8679 (set_attr "mode" "QI")])
8681 (define_insn "*xorqi_cc_2"
8684 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8685 (match_operand:QI 2 "general_operand" "qim"))
8687 (clobber (match_scratch:QI 0 "=q"))]
8688 "ix86_match_ccmode (insn, CCNOmode)
8689 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8690 "xor{b}\t{%2, %0|%0, %2}"
8691 [(set_attr "type" "alu")
8692 (set_attr "mode" "QI")])
8694 (define_insn "*xorqi_cc_ext_1"
8699 (match_operand 1 "ext_register_operand" "0")
8702 (match_operand:QI 2 "general_operand" "qmn"))
8704 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
8708 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8710 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8711 "xor{b}\t{%2, %h0|%h0, %2}"
8712 [(set_attr "type" "alu")
8713 (set_attr "mode" "QI")])
8715 (define_insn "*xorqi_cc_ext_1_rex64"
8720 (match_operand 1 "ext_register_operand" "0")
8723 (match_operand:QI 2 "nonmemory_operand" "Qn"))
8725 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8729 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8731 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8732 "xor{b}\t{%2, %h0|%h0, %2}"
8733 [(set_attr "type" "alu")
8734 (set_attr "mode" "QI")])
8736 (define_expand "xorqi_cc_ext_1"
8742 (match_operand 1 "ext_register_operand" "")
8745 (match_operand:QI 2 "general_operand" ""))
8747 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
8751 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8756 ;; Negation instructions
8758 (define_expand "negdi2"
8759 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
8760 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
8761 (clobber (reg:CC 17))])]
8763 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
8765 (define_insn "*negdi2_1"
8766 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
8767 (neg:DI (match_operand:DI 1 "general_operand" "0")))
8768 (clobber (reg:CC 17))]
8770 && ix86_unary_operator_ok (NEG, DImode, operands)"
8774 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8775 (neg:DI (match_operand:DI 1 "general_operand" "")))
8776 (clobber (reg:CC 17))]
8777 "!TARGET_64BIT && reload_completed"
8780 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
8781 (set (match_dup 0) (neg:SI (match_dup 2)))])
8784 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
8787 (clobber (reg:CC 17))])
8790 (neg:SI (match_dup 1)))
8791 (clobber (reg:CC 17))])]
8792 "split_di (operands+1, 1, operands+2, operands+3);
8793 split_di (operands+0, 1, operands+0, operands+1);")
8795 (define_insn "*negdi2_1_rex64"
8796 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
8797 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
8798 (clobber (reg:CC 17))]
8799 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
8801 [(set_attr "type" "negnot")
8802 (set_attr "mode" "DI")])
8804 ;; The problem with neg is that it does not perform (compare x 0),
8805 ;; it really performs (compare 0 x), which leaves us with the zero
8806 ;; flag being the only useful item.
8808 (define_insn "*negdi2_cmpz_rex64"
8810 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
8812 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
8813 (neg:DI (match_dup 1)))]
8814 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
8816 [(set_attr "type" "negnot")
8817 (set_attr "mode" "DI")])
8820 (define_expand "negsi2"
8821 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
8822 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
8823 (clobber (reg:CC 17))])]
8825 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
8827 (define_insn "*negsi2_1"
8828 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8829 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
8830 (clobber (reg:CC 17))]
8831 "ix86_unary_operator_ok (NEG, SImode, operands)"
8833 [(set_attr "type" "negnot")
8834 (set_attr "mode" "SI")])
8836 ;; Combine is quite creative about this pattern.
8837 (define_insn "*negsi2_1_zext"
8838 [(set (match_operand:DI 0 "register_operand" "=r")
8839 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
8842 (clobber (reg:CC 17))]
8843 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
8845 [(set_attr "type" "negnot")
8846 (set_attr "mode" "SI")])
8848 ;; The problem with neg is that it does not perform (compare x 0),
8849 ;; it really performs (compare 0 x), which leaves us with the zero
8850 ;; flag being the only useful item.
8852 (define_insn "*negsi2_cmpz"
8854 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
8856 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8857 (neg:SI (match_dup 1)))]
8858 "ix86_unary_operator_ok (NEG, SImode, operands)"
8860 [(set_attr "type" "negnot")
8861 (set_attr "mode" "SI")])
8863 (define_insn "*negsi2_cmpz_zext"
8865 (compare:CCZ (lshiftrt:DI
8867 (match_operand:DI 1 "register_operand" "0")
8871 (set (match_operand:DI 0 "register_operand" "=r")
8872 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
8875 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
8877 [(set_attr "type" "negnot")
8878 (set_attr "mode" "SI")])
8880 (define_expand "neghi2"
8881 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
8882 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
8883 (clobber (reg:CC 17))])]
8884 "TARGET_HIMODE_MATH"
8885 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
8887 (define_insn "*neghi2_1"
8888 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8889 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
8890 (clobber (reg:CC 17))]
8891 "ix86_unary_operator_ok (NEG, HImode, operands)"
8893 [(set_attr "type" "negnot")
8894 (set_attr "mode" "HI")])
8896 (define_insn "*neghi2_cmpz"
8898 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
8900 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8901 (neg:HI (match_dup 1)))]
8902 "ix86_unary_operator_ok (NEG, HImode, operands)"
8904 [(set_attr "type" "negnot")
8905 (set_attr "mode" "HI")])
8907 (define_expand "negqi2"
8908 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
8909 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
8910 (clobber (reg:CC 17))])]
8911 "TARGET_QIMODE_MATH"
8912 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
8914 (define_insn "*negqi2_1"
8915 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8916 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
8917 (clobber (reg:CC 17))]
8918 "ix86_unary_operator_ok (NEG, QImode, operands)"
8920 [(set_attr "type" "negnot")
8921 (set_attr "mode" "QI")])
8923 (define_insn "*negqi2_cmpz"
8925 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
8927 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8928 (neg:QI (match_dup 1)))]
8929 "ix86_unary_operator_ok (NEG, QImode, operands)"
8931 [(set_attr "type" "negnot")
8932 (set_attr "mode" "QI")])
8934 ;; Changing of sign for FP values is doable using integer unit too.
8936 (define_expand "negsf2"
8937 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
8938 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
8939 (clobber (reg:CC 17))])]
8943 /* In case operand is in memory, we will not use SSE. */
8944 if (memory_operand (operands[0], VOIDmode)
8945 && rtx_equal_p (operands[0], operands[1]))
8946 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
8949 /* Using SSE is tricky, since we need bitwise negation of -0
8951 rtx reg = gen_reg_rtx (SFmode);
8952 rtx dest = operands[0];
8954 operands[1] = force_reg (SFmode, operands[1]);
8955 operands[0] = force_reg (SFmode, operands[0]);
8956 emit_move_insn (reg,
8957 gen_lowpart (SFmode,
8958 gen_int_mode (0x80000000, SImode)));
8959 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
8960 if (dest != operands[0])
8961 emit_move_insn (dest, operands[0]);
8965 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
8967 (define_insn "negsf2_memory"
8968 [(set (match_operand:SF 0 "memory_operand" "=m")
8969 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
8970 (clobber (reg:CC 17))]
8971 "ix86_unary_operator_ok (NEG, SFmode, operands)"
8974 (define_insn "negsf2_ifs"
8975 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
8976 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
8977 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
8978 (clobber (reg:CC 17))]
8980 && (reload_in_progress || reload_completed
8981 || (register_operand (operands[0], VOIDmode)
8982 && register_operand (operands[1], VOIDmode)))"
8986 [(set (match_operand:SF 0 "memory_operand" "")
8987 (neg:SF (match_operand:SF 1 "memory_operand" "")))
8988 (use (match_operand:SF 2 "" ""))
8989 (clobber (reg:CC 17))]
8991 [(parallel [(set (match_dup 0)
8992 (neg:SF (match_dup 1)))
8993 (clobber (reg:CC 17))])])
8996 [(set (match_operand:SF 0 "register_operand" "")
8997 (neg:SF (match_operand:SF 1 "register_operand" "")))
8998 (use (match_operand:SF 2 "" ""))
8999 (clobber (reg:CC 17))]
9000 "reload_completed && !SSE_REG_P (operands[0])"
9001 [(parallel [(set (match_dup 0)
9002 (neg:SF (match_dup 1)))
9003 (clobber (reg:CC 17))])])
9006 [(set (match_operand:SF 0 "register_operand" "")
9007 (neg:SF (match_operand:SF 1 "register_operand" "")))
9008 (use (match_operand:SF 2 "register_operand" ""))
9009 (clobber (reg:CC 17))]
9010 "reload_completed && SSE_REG_P (operands[0])"
9011 [(set (subreg:TI (match_dup 0) 0)
9012 (xor:TI (subreg:TI (match_dup 1) 0)
9013 (subreg:TI (match_dup 2) 0)))]
9015 if (operands_match_p (operands[0], operands[2]))
9019 operands[1] = operands[2];
9025 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9026 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9028 (define_insn "*negsf2_if"
9029 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9030 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9031 (clobber (reg:CC 17))]
9032 "TARGET_80387 && !TARGET_SSE
9033 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9037 [(set (match_operand:SF 0 "register_operand" "")
9038 (neg:SF (match_operand:SF 1 "register_operand" "")))
9039 (clobber (reg:CC 17))]
9040 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9042 (neg:SF (match_dup 1)))]
9046 [(set (match_operand:SF 0 "register_operand" "")
9047 (neg:SF (match_operand:SF 1 "register_operand" "")))
9048 (clobber (reg:CC 17))]
9049 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9050 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9051 (clobber (reg:CC 17))])]
9052 "operands[1] = gen_int_mode (0x80000000, SImode);
9053 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9056 [(set (match_operand 0 "memory_operand" "")
9057 (neg (match_operand 1 "memory_operand" "")))
9058 (clobber (reg:CC 17))]
9059 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9060 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9061 (clobber (reg:CC 17))])]
9063 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9065 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9068 operands[0] = adjust_address (operands[0], QImode, size - 1);
9069 operands[1] = gen_int_mode (0x80, QImode);
9072 (define_expand "negdf2"
9073 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9074 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9075 (clobber (reg:CC 17))])]
9079 /* In case operand is in memory, we will not use SSE. */
9080 if (memory_operand (operands[0], VOIDmode)
9081 && rtx_equal_p (operands[0], operands[1]))
9082 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9085 /* Using SSE is tricky, since we need bitwise negation of -0
9087 rtx reg = gen_reg_rtx (DFmode);
9088 #if HOST_BITS_PER_WIDE_INT >= 64
9089 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9091 rtx imm = immed_double_const (0, 0x80000000, DImode);
9093 rtx dest = operands[0];
9095 operands[1] = force_reg (DFmode, operands[1]);
9096 operands[0] = force_reg (DFmode, operands[0]);
9097 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9098 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9099 if (dest != operands[0])
9100 emit_move_insn (dest, operands[0]);
9104 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9106 (define_insn "negdf2_memory"
9107 [(set (match_operand:DF 0 "memory_operand" "=m")
9108 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9109 (clobber (reg:CC 17))]
9110 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9113 (define_insn "negdf2_ifs"
9114 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9115 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9116 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9117 (clobber (reg:CC 17))]
9118 "!TARGET_64BIT && TARGET_SSE2
9119 && (reload_in_progress || reload_completed
9120 || (register_operand (operands[0], VOIDmode)
9121 && register_operand (operands[1], VOIDmode)))"
9124 (define_insn "*negdf2_ifs_rex64"
9125 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9126 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9127 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9128 (clobber (reg:CC 17))]
9129 "TARGET_64BIT && TARGET_SSE2
9130 && (reload_in_progress || reload_completed
9131 || (register_operand (operands[0], VOIDmode)
9132 && register_operand (operands[1], VOIDmode)))"
9136 [(set (match_operand:DF 0 "memory_operand" "")
9137 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9138 (use (match_operand:DF 2 "" ""))
9139 (clobber (reg:CC 17))]
9141 [(parallel [(set (match_dup 0)
9142 (neg:DF (match_dup 1)))
9143 (clobber (reg:CC 17))])])
9146 [(set (match_operand:DF 0 "register_operand" "")
9147 (neg:DF (match_operand:DF 1 "register_operand" "")))
9148 (use (match_operand:DF 2 "" ""))
9149 (clobber (reg:CC 17))]
9150 "reload_completed && !SSE_REG_P (operands[0])
9151 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9152 [(parallel [(set (match_dup 0)
9153 (neg:DF (match_dup 1)))
9154 (clobber (reg:CC 17))])])
9157 [(set (match_operand:DF 0 "register_operand" "")
9158 (neg:DF (match_operand:DF 1 "register_operand" "")))
9159 (use (match_operand:DF 2 "" ""))
9160 (clobber (reg:CC 17))]
9161 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9162 [(parallel [(set (match_dup 0)
9163 (xor:DI (match_dup 1) (match_dup 2)))
9164 (clobber (reg:CC 17))])]
9165 "operands[0] = gen_lowpart (DImode, operands[0]);
9166 operands[1] = gen_lowpart (DImode, operands[1]);
9167 operands[2] = gen_lowpart (DImode, operands[2]);")
9170 [(set (match_operand:DF 0 "register_operand" "")
9171 (neg:DF (match_operand:DF 1 "register_operand" "")))
9172 (use (match_operand:DF 2 "register_operand" ""))
9173 (clobber (reg:CC 17))]
9174 "reload_completed && SSE_REG_P (operands[0])"
9175 [(set (subreg:TI (match_dup 0) 0)
9176 (xor:TI (subreg:TI (match_dup 1) 0)
9177 (subreg:TI (match_dup 2) 0)))]
9179 if (operands_match_p (operands[0], operands[2]))
9183 operands[1] = operands[2];
9188 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9189 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9191 (define_insn "*negdf2_if"
9192 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9193 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9194 (clobber (reg:CC 17))]
9195 "!TARGET_64BIT && TARGET_80387
9196 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9199 ;; FIXME: We should to allow integer registers here. Problem is that
9200 ;; we need another scratch register to get constant from.
9201 ;; Forcing constant to mem if no register available in peep2 should be
9202 ;; safe even for PIC mode, because of RIP relative addressing.
9203 (define_insn "*negdf2_if_rex64"
9204 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9205 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9206 (clobber (reg:CC 17))]
9207 "TARGET_64BIT && TARGET_80387
9208 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9212 [(set (match_operand:DF 0 "register_operand" "")
9213 (neg:DF (match_operand:DF 1 "register_operand" "")))
9214 (clobber (reg:CC 17))]
9215 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9217 (neg:DF (match_dup 1)))]
9221 [(set (match_operand:DF 0 "register_operand" "")
9222 (neg:DF (match_operand:DF 1 "register_operand" "")))
9223 (clobber (reg:CC 17))]
9224 "!TARGET_64BIT && TARGET_80387 && reload_completed
9225 && !FP_REGNO_P (REGNO (operands[0]))"
9226 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9227 (clobber (reg:CC 17))])]
9228 "operands[4] = gen_int_mode (0x80000000, SImode);
9229 split_di (operands+0, 1, operands+2, operands+3);")
9231 (define_expand "negxf2"
9232 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9233 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9234 (clobber (reg:CC 17))])]
9235 "!TARGET_64BIT && TARGET_80387"
9236 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9238 (define_expand "negtf2"
9239 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9240 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9241 (clobber (reg:CC 17))])]
9243 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9245 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9246 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9248 (define_insn "*negxf2_if"
9249 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9250 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9251 (clobber (reg:CC 17))]
9252 "!TARGET_64BIT && TARGET_80387
9253 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9257 [(set (match_operand:XF 0 "register_operand" "")
9258 (neg:XF (match_operand:XF 1 "register_operand" "")))
9259 (clobber (reg:CC 17))]
9260 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9262 (neg:XF (match_dup 1)))]
9266 [(set (match_operand:XF 0 "register_operand" "")
9267 (neg:XF (match_operand:XF 1 "register_operand" "")))
9268 (clobber (reg:CC 17))]
9269 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9270 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9271 (clobber (reg:CC 17))])]
9272 "operands[1] = GEN_INT (0x8000);
9273 operands[0] = gen_rtx_REG (SImode,
9274 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9276 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9277 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9279 (define_insn "*negtf2_if"
9280 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9281 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9282 (clobber (reg:CC 17))]
9283 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9287 [(set (match_operand:TF 0 "register_operand" "")
9288 (neg:TF (match_operand:TF 1 "register_operand" "")))
9289 (clobber (reg:CC 17))]
9290 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9292 (neg:TF (match_dup 1)))]
9296 [(set (match_operand:TF 0 "register_operand" "")
9297 (neg:TF (match_operand:TF 1 "register_operand" "")))
9298 (clobber (reg:CC 17))]
9299 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9300 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9301 (clobber (reg:CC 17))])]
9302 "operands[1] = GEN_INT (0x8000);
9303 operands[0] = gen_rtx_REG (SImode,
9304 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9306 ;; Conditionize these after reload. If they matches before reload, we
9307 ;; lose the clobber and ability to use integer instructions.
9309 (define_insn "*negsf2_1"
9310 [(set (match_operand:SF 0 "register_operand" "=f")
9311 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9312 "TARGET_80387 && reload_completed"
9314 [(set_attr "type" "fsgn")
9315 (set_attr "mode" "SF")
9316 (set_attr "ppro_uops" "few")])
9318 (define_insn "*negdf2_1"
9319 [(set (match_operand:DF 0 "register_operand" "=f")
9320 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9321 "TARGET_80387 && reload_completed"
9323 [(set_attr "type" "fsgn")
9324 (set_attr "mode" "DF")
9325 (set_attr "ppro_uops" "few")])
9327 (define_insn "*negextendsfdf2"
9328 [(set (match_operand:DF 0 "register_operand" "=f")
9329 (neg:DF (float_extend:DF
9330 (match_operand:SF 1 "register_operand" "0"))))]
9333 [(set_attr "type" "fsgn")
9334 (set_attr "mode" "DF")
9335 (set_attr "ppro_uops" "few")])
9337 (define_insn "*negxf2_1"
9338 [(set (match_operand:XF 0 "register_operand" "=f")
9339 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9340 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9342 [(set_attr "type" "fsgn")
9343 (set_attr "mode" "XF")
9344 (set_attr "ppro_uops" "few")])
9346 (define_insn "*negextenddfxf2"
9347 [(set (match_operand:XF 0 "register_operand" "=f")
9348 (neg:XF (float_extend:XF
9349 (match_operand:DF 1 "register_operand" "0"))))]
9350 "!TARGET_64BIT && TARGET_80387"
9352 [(set_attr "type" "fsgn")
9353 (set_attr "mode" "XF")
9354 (set_attr "ppro_uops" "few")])
9356 (define_insn "*negextendsfxf2"
9357 [(set (match_operand:XF 0 "register_operand" "=f")
9358 (neg:XF (float_extend:XF
9359 (match_operand:SF 1 "register_operand" "0"))))]
9360 "!TARGET_64BIT && TARGET_80387"
9362 [(set_attr "type" "fsgn")
9363 (set_attr "mode" "XF")
9364 (set_attr "ppro_uops" "few")])
9366 (define_insn "*negtf2_1"
9367 [(set (match_operand:TF 0 "register_operand" "=f")
9368 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9369 "TARGET_80387 && reload_completed"
9371 [(set_attr "type" "fsgn")
9372 (set_attr "mode" "XF")
9373 (set_attr "ppro_uops" "few")])
9375 (define_insn "*negextenddftf2"
9376 [(set (match_operand:TF 0 "register_operand" "=f")
9377 (neg:TF (float_extend:TF
9378 (match_operand:DF 1 "register_operand" "0"))))]
9381 [(set_attr "type" "fsgn")
9382 (set_attr "mode" "XF")
9383 (set_attr "ppro_uops" "few")])
9385 (define_insn "*negextendsftf2"
9386 [(set (match_operand:TF 0 "register_operand" "=f")
9387 (neg:TF (float_extend:TF
9388 (match_operand:SF 1 "register_operand" "0"))))]
9391 [(set_attr "type" "fsgn")
9392 (set_attr "mode" "XF")
9393 (set_attr "ppro_uops" "few")])
9395 ;; Absolute value instructions
9397 (define_expand "abssf2"
9398 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9399 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9400 (clobber (reg:CC 17))])]
9404 /* In case operand is in memory, we will not use SSE. */
9405 if (memory_operand (operands[0], VOIDmode)
9406 && rtx_equal_p (operands[0], operands[1]))
9407 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9410 /* Using SSE is tricky, since we need bitwise negation of -0
9412 rtx reg = gen_reg_rtx (SFmode);
9413 rtx dest = operands[0];
9415 operands[1] = force_reg (SFmode, operands[1]);
9416 operands[0] = force_reg (SFmode, operands[0]);
9417 emit_move_insn (reg,
9418 gen_lowpart (SFmode,
9419 gen_int_mode (0x80000000, SImode)));
9420 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9421 if (dest != operands[0])
9422 emit_move_insn (dest, operands[0]);
9426 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9428 (define_insn "abssf2_memory"
9429 [(set (match_operand:SF 0 "memory_operand" "=m")
9430 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9431 (clobber (reg:CC 17))]
9432 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9435 (define_insn "abssf2_ifs"
9436 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9437 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9438 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9439 (clobber (reg:CC 17))]
9441 && (reload_in_progress || reload_completed
9442 || (register_operand (operands[0], VOIDmode)
9443 && register_operand (operands[1], VOIDmode)))"
9447 [(set (match_operand:SF 0 "memory_operand" "")
9448 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9449 (use (match_operand:SF 2 "" ""))
9450 (clobber (reg:CC 17))]
9452 [(parallel [(set (match_dup 0)
9453 (abs:SF (match_dup 1)))
9454 (clobber (reg:CC 17))])])
9457 [(set (match_operand:SF 0 "register_operand" "")
9458 (abs:SF (match_operand:SF 1 "register_operand" "")))
9459 (use (match_operand:SF 2 "" ""))
9460 (clobber (reg:CC 17))]
9461 "reload_completed && !SSE_REG_P (operands[0])"
9462 [(parallel [(set (match_dup 0)
9463 (abs:SF (match_dup 1)))
9464 (clobber (reg:CC 17))])])
9467 [(set (match_operand:SF 0 "register_operand" "")
9468 (abs:SF (match_operand:SF 1 "register_operand" "")))
9469 (use (match_operand:SF 2 "register_operand" ""))
9470 (clobber (reg:CC 17))]
9471 "reload_completed && SSE_REG_P (operands[0])"
9472 [(set (subreg:TI (match_dup 0) 0)
9473 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9474 (subreg:TI (match_dup 1) 0)))])
9476 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9477 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9479 (define_insn "*abssf2_if"
9480 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9481 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9482 (clobber (reg:CC 17))]
9483 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9487 [(set (match_operand:SF 0 "register_operand" "")
9488 (abs:SF (match_operand:SF 1 "register_operand" "")))
9489 (clobber (reg:CC 17))]
9490 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9492 (abs:SF (match_dup 1)))]
9496 [(set (match_operand:SF 0 "register_operand" "")
9497 (abs:SF (match_operand:SF 1 "register_operand" "")))
9498 (clobber (reg:CC 17))]
9499 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9500 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9501 (clobber (reg:CC 17))])]
9502 "operands[1] = gen_int_mode (~0x80000000, SImode);
9503 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9506 [(set (match_operand 0 "memory_operand" "")
9507 (abs (match_operand 1 "memory_operand" "")))
9508 (clobber (reg:CC 17))]
9509 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9510 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9511 (clobber (reg:CC 17))])]
9513 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9515 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9518 operands[0] = adjust_address (operands[0], QImode, size - 1);
9519 operands[1] = gen_int_mode (~0x80, QImode);
9522 (define_expand "absdf2"
9523 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9524 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9525 (clobber (reg:CC 17))])]
9529 /* In case operand is in memory, we will not use SSE. */
9530 if (memory_operand (operands[0], VOIDmode)
9531 && rtx_equal_p (operands[0], operands[1]))
9532 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9535 /* Using SSE is tricky, since we need bitwise negation of -0
9537 rtx reg = gen_reg_rtx (DFmode);
9538 #if HOST_BITS_PER_WIDE_INT >= 64
9539 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9541 rtx imm = immed_double_const (0, 0x80000000, DImode);
9543 rtx dest = operands[0];
9545 operands[1] = force_reg (DFmode, operands[1]);
9546 operands[0] = force_reg (DFmode, operands[0]);
9547 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9548 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9549 if (dest != operands[0])
9550 emit_move_insn (dest, operands[0]);
9554 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9556 (define_insn "absdf2_memory"
9557 [(set (match_operand:DF 0 "memory_operand" "=m")
9558 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9559 (clobber (reg:CC 17))]
9560 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9563 (define_insn "absdf2_ifs"
9564 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
9565 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9566 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
9567 (clobber (reg:CC 17))]
9568 "!TARGET_64BIT && TARGET_SSE2
9569 && (reload_in_progress || reload_completed
9570 || (register_operand (operands[0], VOIDmode)
9571 && register_operand (operands[1], VOIDmode)))"
9574 (define_insn "*absdf2_ifs_rex64"
9575 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
9576 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
9577 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
9578 (clobber (reg:CC 17))]
9579 "TARGET_64BIT && TARGET_SSE2
9580 && (reload_in_progress || reload_completed
9581 || (register_operand (operands[0], VOIDmode)
9582 && register_operand (operands[1], VOIDmode)))"
9586 [(set (match_operand:DF 0 "memory_operand" "")
9587 (abs:DF (match_operand:DF 1 "memory_operand" "")))
9588 (use (match_operand:DF 2 "" ""))
9589 (clobber (reg:CC 17))]
9591 [(parallel [(set (match_dup 0)
9592 (abs:DF (match_dup 1)))
9593 (clobber (reg:CC 17))])])
9596 [(set (match_operand:DF 0 "register_operand" "")
9597 (abs:DF (match_operand:DF 1 "register_operand" "")))
9598 (use (match_operand:DF 2 "" ""))
9599 (clobber (reg:CC 17))]
9600 "reload_completed && !SSE_REG_P (operands[0])"
9601 [(parallel [(set (match_dup 0)
9602 (abs:DF (match_dup 1)))
9603 (clobber (reg:CC 17))])])
9606 [(set (match_operand:DF 0 "register_operand" "")
9607 (abs:DF (match_operand:DF 1 "register_operand" "")))
9608 (use (match_operand:DF 2 "register_operand" ""))
9609 (clobber (reg:CC 17))]
9610 "reload_completed && SSE_REG_P (operands[0])"
9611 [(set (subreg:TI (match_dup 0) 0)
9612 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9613 (subreg:TI (match_dup 1) 0)))])
9616 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9617 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9619 (define_insn "*absdf2_if"
9620 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9621 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9622 (clobber (reg:CC 17))]
9623 "!TARGET_64BIT && TARGET_80387
9624 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9627 ;; FIXME: We should to allow integer registers here. Problem is that
9628 ;; we need another scratch register to get constant from.
9629 ;; Forcing constant to mem if no register available in peep2 should be
9630 ;; safe even for PIC mode, because of RIP relative addressing.
9631 (define_insn "*absdf2_if_rex64"
9632 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9633 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9634 (clobber (reg:CC 17))]
9635 "TARGET_64BIT && TARGET_80387
9636 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9640 [(set (match_operand:DF 0 "register_operand" "")
9641 (abs:DF (match_operand:DF 1 "register_operand" "")))
9642 (clobber (reg:CC 17))]
9643 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9645 (abs:DF (match_dup 1)))]
9649 [(set (match_operand:DF 0 "register_operand" "")
9650 (abs:DF (match_operand:DF 1 "register_operand" "")))
9651 (clobber (reg:CC 17))]
9652 "!TARGET_64BIT && TARGET_80387 && reload_completed &&
9653 !FP_REGNO_P (REGNO (operands[0]))"
9654 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
9655 (clobber (reg:CC 17))])]
9656 "operands[4] = gen_int_mode (~0x80000000, SImode);
9657 split_di (operands+0, 1, operands+2, operands+3);")
9659 (define_expand "absxf2"
9660 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9661 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9662 (clobber (reg:CC 17))])]
9663 "!TARGET_64BIT && TARGET_80387"
9664 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
9666 (define_expand "abstf2"
9667 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9668 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9669 (clobber (reg:CC 17))])]
9671 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
9673 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9674 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9676 (define_insn "*absxf2_if"
9677 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9678 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9679 (clobber (reg:CC 17))]
9680 "!TARGET_64BIT && TARGET_80387
9681 && ix86_unary_operator_ok (ABS, XFmode, operands)"
9685 [(set (match_operand:XF 0 "register_operand" "")
9686 (abs:XF (match_operand:XF 1 "register_operand" "")))
9687 (clobber (reg:CC 17))]
9688 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9690 (abs:XF (match_dup 1)))]
9694 [(set (match_operand:XF 0 "register_operand" "")
9695 (abs:XF (match_operand:XF 1 "register_operand" "")))
9696 (clobber (reg:CC 17))]
9697 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9698 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9699 (clobber (reg:CC 17))])]
9700 "operands[1] = GEN_INT (~0x8000);
9701 operands[0] = gen_rtx_REG (SImode,
9702 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9704 (define_insn "*abstf2_if"
9705 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9706 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9707 (clobber (reg:CC 17))]
9708 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
9712 [(set (match_operand:TF 0 "register_operand" "")
9713 (abs:TF (match_operand:TF 1 "register_operand" "")))
9714 (clobber (reg:CC 17))]
9715 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9717 (abs:TF (match_dup 1)))]
9721 [(set (match_operand:TF 0 "register_operand" "")
9722 (abs:TF (match_operand:TF 1 "register_operand" "")))
9723 (clobber (reg:CC 17))]
9724 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9725 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9726 (clobber (reg:CC 17))])]
9727 "operands[1] = GEN_INT (~0x8000);
9728 operands[0] = gen_rtx_REG (SImode,
9729 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9731 (define_insn "*abssf2_1"
9732 [(set (match_operand:SF 0 "register_operand" "=f")
9733 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
9734 "TARGET_80387 && reload_completed"
9736 [(set_attr "type" "fsgn")
9737 (set_attr "mode" "SF")])
9739 (define_insn "*absdf2_1"
9740 [(set (match_operand:DF 0 "register_operand" "=f")
9741 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
9742 "TARGET_80387 && reload_completed"
9744 [(set_attr "type" "fsgn")
9745 (set_attr "mode" "DF")])
9747 (define_insn "*absextendsfdf2"
9748 [(set (match_operand:DF 0 "register_operand" "=f")
9749 (abs:DF (float_extend:DF
9750 (match_operand:SF 1 "register_operand" "0"))))]
9753 [(set_attr "type" "fsgn")
9754 (set_attr "mode" "DF")])
9756 (define_insn "*absxf2_1"
9757 [(set (match_operand:XF 0 "register_operand" "=f")
9758 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
9759 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9761 [(set_attr "type" "fsgn")
9762 (set_attr "mode" "DF")])
9764 (define_insn "*absextenddfxf2"
9765 [(set (match_operand:XF 0 "register_operand" "=f")
9766 (abs:XF (float_extend:XF
9767 (match_operand:DF 1 "register_operand" "0"))))]
9768 "!TARGET_64BIT && TARGET_80387"
9770 [(set_attr "type" "fsgn")
9771 (set_attr "mode" "XF")])
9773 (define_insn "*absextendsfxf2"
9774 [(set (match_operand:XF 0 "register_operand" "=f")
9775 (abs:XF (float_extend:XF
9776 (match_operand:SF 1 "register_operand" "0"))))]
9777 "!TARGET_64BIT && TARGET_80387"
9779 [(set_attr "type" "fsgn")
9780 (set_attr "mode" "XF")])
9782 (define_insn "*abstf2_1"
9783 [(set (match_operand:TF 0 "register_operand" "=f")
9784 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
9785 "TARGET_80387 && reload_completed"
9787 [(set_attr "type" "fsgn")
9788 (set_attr "mode" "DF")])
9790 (define_insn "*absextenddftf2"
9791 [(set (match_operand:TF 0 "register_operand" "=f")
9792 (abs:TF (float_extend:TF
9793 (match_operand:DF 1 "register_operand" "0"))))]
9796 [(set_attr "type" "fsgn")
9797 (set_attr "mode" "XF")])
9799 (define_insn "*absextendsftf2"
9800 [(set (match_operand:TF 0 "register_operand" "=f")
9801 (abs:TF (float_extend:TF
9802 (match_operand:SF 1 "register_operand" "0"))))]
9805 [(set_attr "type" "fsgn")
9806 (set_attr "mode" "XF")])
9808 ;; One complement instructions
9810 (define_expand "one_cmpldi2"
9811 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9812 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
9814 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
9816 (define_insn "*one_cmpldi2_1_rex64"
9817 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9818 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
9819 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
9821 [(set_attr "type" "negnot")
9822 (set_attr "mode" "DI")])
9824 (define_insn "*one_cmpldi2_2_rex64"
9826 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9828 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9829 (not:DI (match_dup 1)))]
9830 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9831 && ix86_unary_operator_ok (NOT, DImode, operands)"
9833 [(set_attr "type" "alu1")
9834 (set_attr "mode" "DI")])
9838 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
9840 (set (match_operand:DI 0 "nonimmediate_operand" "")
9841 (not:DI (match_dup 1)))]
9842 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9843 [(parallel [(set (reg:CCNO 17)
9844 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
9847 (xor:DI (match_dup 1) (const_int -1)))])]
9850 (define_expand "one_cmplsi2"
9851 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9852 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
9854 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
9856 (define_insn "*one_cmplsi2_1"
9857 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9858 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
9859 "ix86_unary_operator_ok (NOT, SImode, operands)"
9861 [(set_attr "type" "negnot")
9862 (set_attr "mode" "SI")])
9864 ;; ??? Currently never generated - xor is used instead.
9865 (define_insn "*one_cmplsi2_1_zext"
9866 [(set (match_operand:DI 0 "register_operand" "=r")
9867 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
9868 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
9870 [(set_attr "type" "negnot")
9871 (set_attr "mode" "SI")])
9873 (define_insn "*one_cmplsi2_2"
9875 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9877 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9878 (not:SI (match_dup 1)))]
9879 "ix86_match_ccmode (insn, CCNOmode)
9880 && ix86_unary_operator_ok (NOT, SImode, operands)"
9882 [(set_attr "type" "alu1")
9883 (set_attr "mode" "SI")])
9887 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
9889 (set (match_operand:SI 0 "nonimmediate_operand" "")
9890 (not:SI (match_dup 1)))]
9891 "ix86_match_ccmode (insn, CCNOmode)"
9892 [(parallel [(set (reg:CCNO 17)
9893 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
9896 (xor:SI (match_dup 1) (const_int -1)))])]
9899 ;; ??? Currently never generated - xor is used instead.
9900 (define_insn "*one_cmplsi2_2_zext"
9902 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
9904 (set (match_operand:DI 0 "register_operand" "=r")
9905 (zero_extend:DI (not:SI (match_dup 1))))]
9906 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9907 && ix86_unary_operator_ok (NOT, SImode, operands)"
9909 [(set_attr "type" "alu1")
9910 (set_attr "mode" "SI")])
9914 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
9916 (set (match_operand:DI 0 "register_operand" "")
9917 (zero_extend:DI (not:SI (match_dup 1))))]
9918 "ix86_match_ccmode (insn, CCNOmode)"
9919 [(parallel [(set (reg:CCNO 17)
9920 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
9923 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
9926 (define_expand "one_cmplhi2"
9927 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9928 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
9929 "TARGET_HIMODE_MATH"
9930 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
9932 (define_insn "*one_cmplhi2_1"
9933 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9934 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
9935 "ix86_unary_operator_ok (NOT, HImode, operands)"
9937 [(set_attr "type" "negnot")
9938 (set_attr "mode" "HI")])
9940 (define_insn "*one_cmplhi2_2"
9942 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9944 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9945 (not:HI (match_dup 1)))]
9946 "ix86_match_ccmode (insn, CCNOmode)
9947 && ix86_unary_operator_ok (NEG, HImode, operands)"
9949 [(set_attr "type" "alu1")
9950 (set_attr "mode" "HI")])
9954 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
9956 (set (match_operand:HI 0 "nonimmediate_operand" "")
9957 (not:HI (match_dup 1)))]
9958 "ix86_match_ccmode (insn, CCNOmode)"
9959 [(parallel [(set (reg:CCNO 17)
9960 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
9963 (xor:HI (match_dup 1) (const_int -1)))])]
9966 ;; %%% Potential partial reg stall on alternative 1. What to do?
9967 (define_expand "one_cmplqi2"
9968 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9969 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
9970 "TARGET_QIMODE_MATH"
9971 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
9973 (define_insn "*one_cmplqi2_1"
9974 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
9975 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
9976 "ix86_unary_operator_ok (NOT, QImode, operands)"
9980 [(set_attr "type" "negnot")
9981 (set_attr "mode" "QI,SI")])
9983 (define_insn "*one_cmplqi2_2"
9985 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9987 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9988 (not:QI (match_dup 1)))]
9989 "ix86_match_ccmode (insn, CCNOmode)
9990 && ix86_unary_operator_ok (NOT, QImode, operands)"
9992 [(set_attr "type" "alu1")
9993 (set_attr "mode" "QI")])
9997 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
9999 (set (match_operand:QI 0 "nonimmediate_operand" "")
10000 (not:QI (match_dup 1)))]
10001 "ix86_match_ccmode (insn, CCNOmode)"
10002 [(parallel [(set (reg:CCNO 17)
10003 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10006 (xor:QI (match_dup 1) (const_int -1)))])]
10009 ;; Arithmetic shift instructions
10011 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10012 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10013 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10014 ;; from the assembler input.
10016 ;; This instruction shifts the target reg/mem as usual, but instead of
10017 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10018 ;; is a left shift double, bits are taken from the high order bits of
10019 ;; reg, else if the insn is a shift right double, bits are taken from the
10020 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10021 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10023 ;; Since sh[lr]d does not change the `reg' operand, that is done
10024 ;; separately, making all shifts emit pairs of shift double and normal
10025 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10026 ;; support a 63 bit shift, each shift where the count is in a reg expands
10027 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10029 ;; If the shift count is a constant, we need never emit more than one
10030 ;; shift pair, instead using moves and sign extension for counts greater
10033 (define_expand "ashldi3"
10034 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10035 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10036 (match_operand:QI 2 "nonmemory_operand" "")))
10037 (clobber (reg:CC 17))])]
10040 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10042 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10045 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10049 (define_insn "*ashldi3_1_rex64"
10050 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10051 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10052 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10053 (clobber (reg:CC 17))]
10054 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10056 switch (get_attr_type (insn))
10059 if (operands[2] != const1_rtx)
10061 if (!rtx_equal_p (operands[0], operands[1]))
10063 return "add{q}\t{%0, %0|%0, %0}";
10066 if (GET_CODE (operands[2]) != CONST_INT
10067 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10069 operands[1] = gen_rtx_MULT (DImode, operands[1],
10070 GEN_INT (1 << INTVAL (operands[2])));
10071 return "lea{q}\t{%a1, %0|%0, %a1}";
10074 if (REG_P (operands[2]))
10075 return "sal{q}\t{%b2, %0|%0, %b2}";
10076 else if (GET_CODE (operands[2]) == CONST_INT
10077 && INTVAL (operands[2]) == 1
10078 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10079 return "sal{q}\t%0";
10081 return "sal{q}\t{%2, %0|%0, %2}";
10084 [(set (attr "type")
10085 (cond [(eq_attr "alternative" "1")
10086 (const_string "lea")
10087 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10089 (match_operand 0 "register_operand" ""))
10090 (match_operand 2 "const1_operand" ""))
10091 (const_string "alu")
10093 (const_string "ishift")))
10094 (set_attr "mode" "DI")])
10096 ;; Convert lea to the lea pattern to avoid flags dependency.
10098 [(set (match_operand:DI 0 "register_operand" "")
10099 (ashift:DI (match_operand:DI 1 "register_operand" "")
10100 (match_operand:QI 2 "immediate_operand" "")))
10101 (clobber (reg:CC 17))]
10102 "TARGET_64BIT && reload_completed
10103 && true_regnum (operands[0]) != true_regnum (operands[1])"
10104 [(set (match_dup 0)
10105 (mult:DI (match_dup 1)
10107 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10109 ;; This pattern can't accept a variable shift count, since shifts by
10110 ;; zero don't affect the flags. We assume that shifts by constant
10111 ;; zero are optimized away.
10112 (define_insn "*ashldi3_cmp_rex64"
10115 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10116 (match_operand:QI 2 "immediate_operand" "e"))
10118 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10119 (ashift:DI (match_dup 1) (match_dup 2)))]
10120 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10121 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10123 switch (get_attr_type (insn))
10126 if (operands[2] != const1_rtx)
10128 return "add{q}\t{%0, %0|%0, %0}";
10131 if (REG_P (operands[2]))
10132 return "sal{q}\t{%b2, %0|%0, %b2}";
10133 else if (GET_CODE (operands[2]) == CONST_INT
10134 && INTVAL (operands[2]) == 1
10135 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10136 return "sal{q}\t%0";
10138 return "sal{q}\t{%2, %0|%0, %2}";
10141 [(set (attr "type")
10142 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10144 (match_operand 0 "register_operand" ""))
10145 (match_operand 2 "const1_operand" ""))
10146 (const_string "alu")
10148 (const_string "ishift")))
10149 (set_attr "mode" "DI")])
10151 (define_insn "ashldi3_1"
10152 [(set (match_operand:DI 0 "register_operand" "=r")
10153 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10154 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10155 (clobber (match_scratch:SI 3 "=&r"))
10156 (clobber (reg:CC 17))]
10157 "!TARGET_64BIT && TARGET_CMOVE"
10159 [(set_attr "type" "multi")])
10161 (define_insn "*ashldi3_2"
10162 [(set (match_operand:DI 0 "register_operand" "=r")
10163 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10164 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10165 (clobber (reg:CC 17))]
10168 [(set_attr "type" "multi")])
10171 [(set (match_operand:DI 0 "register_operand" "")
10172 (ashift:DI (match_operand:DI 1 "register_operand" "")
10173 (match_operand:QI 2 "nonmemory_operand" "")))
10174 (clobber (match_scratch:SI 3 ""))
10175 (clobber (reg:CC 17))]
10176 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10178 "ix86_split_ashldi (operands, operands[3]); DONE;")
10181 [(set (match_operand:DI 0 "register_operand" "")
10182 (ashift:DI (match_operand:DI 1 "register_operand" "")
10183 (match_operand:QI 2 "nonmemory_operand" "")))
10184 (clobber (reg:CC 17))]
10185 "!TARGET_64BIT && reload_completed"
10187 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10189 (define_insn "x86_shld_1"
10190 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10191 (ior:SI (ashift:SI (match_dup 0)
10192 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10193 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10194 (minus:QI (const_int 32) (match_dup 2)))))
10195 (clobber (reg:CC 17))]
10198 shld{l}\t{%2, %1, %0|%0, %1, %2}
10199 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10200 [(set_attr "type" "ishift")
10201 (set_attr "prefix_0f" "1")
10202 (set_attr "mode" "SI")
10203 (set_attr "pent_pair" "np")
10204 (set_attr "athlon_decode" "vector")
10205 (set_attr "ppro_uops" "few")])
10207 (define_expand "x86_shift_adj_1"
10209 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10212 (set (match_operand:SI 0 "register_operand" "")
10213 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10214 (match_operand:SI 1 "register_operand" "")
10217 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10218 (match_operand:SI 3 "register_operand" "r")
10223 (define_expand "x86_shift_adj_2"
10224 [(use (match_operand:SI 0 "register_operand" ""))
10225 (use (match_operand:SI 1 "register_operand" ""))
10226 (use (match_operand:QI 2 "register_operand" ""))]
10229 rtx label = gen_label_rtx ();
10232 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10234 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10235 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10236 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10237 gen_rtx_LABEL_REF (VOIDmode, label),
10239 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10240 JUMP_LABEL (tmp) = label;
10242 emit_move_insn (operands[0], operands[1]);
10243 emit_move_insn (operands[1], const0_rtx);
10245 emit_label (label);
10246 LABEL_NUSES (label) = 1;
10251 (define_expand "ashlsi3"
10252 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10253 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10254 (match_operand:QI 2 "nonmemory_operand" "")))
10255 (clobber (reg:CC 17))]
10257 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10259 (define_insn "*ashlsi3_1"
10260 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10261 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10262 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10263 (clobber (reg:CC 17))]
10264 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10266 switch (get_attr_type (insn))
10269 if (operands[2] != const1_rtx)
10271 if (!rtx_equal_p (operands[0], operands[1]))
10273 return "add{l}\t{%0, %0|%0, %0}";
10279 if (REG_P (operands[2]))
10280 return "sal{l}\t{%b2, %0|%0, %b2}";
10281 else if (GET_CODE (operands[2]) == CONST_INT
10282 && INTVAL (operands[2]) == 1
10283 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10284 return "sal{l}\t%0";
10286 return "sal{l}\t{%2, %0|%0, %2}";
10289 [(set (attr "type")
10290 (cond [(eq_attr "alternative" "1")
10291 (const_string "lea")
10292 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10294 (match_operand 0 "register_operand" ""))
10295 (match_operand 2 "const1_operand" ""))
10296 (const_string "alu")
10298 (const_string "ishift")))
10299 (set_attr "mode" "SI")])
10301 ;; Convert lea to the lea pattern to avoid flags dependency.
10303 [(set (match_operand 0 "register_operand" "")
10304 (ashift (match_operand 1 "register_operand" "")
10305 (match_operand:QI 2 "const_int_operand" "")))
10306 (clobber (reg:CC 17))]
10308 && true_regnum (operands[0]) != true_regnum (operands[1])"
10312 operands[0] = gen_lowpart (SImode, operands[0]);
10313 operands[1] = gen_lowpart (Pmode, operands[1]);
10314 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10315 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10316 if (Pmode != SImode)
10317 pat = gen_rtx_SUBREG (SImode, pat, 0);
10318 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10322 (define_insn "*ashlsi3_1_zext"
10323 [(set (match_operand:DI 0 "register_operand" "=r,r")
10324 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10325 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10326 (clobber (reg:CC 17))]
10327 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10329 switch (get_attr_type (insn))
10332 if (operands[2] != const1_rtx)
10334 return "add{l}\t{%k0, %k0|%k0, %k0}";
10340 if (REG_P (operands[2]))
10341 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10342 else if (GET_CODE (operands[2]) == CONST_INT
10343 && INTVAL (operands[2]) == 1
10344 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10345 return "sal{l}\t%k0";
10347 return "sal{l}\t{%2, %k0|%k0, %2}";
10350 [(set (attr "type")
10351 (cond [(eq_attr "alternative" "1")
10352 (const_string "lea")
10353 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10355 (match_operand 2 "const1_operand" ""))
10356 (const_string "alu")
10358 (const_string "ishift")))
10359 (set_attr "mode" "SI")])
10361 ;; Convert lea to the lea pattern to avoid flags dependency.
10363 [(set (match_operand:DI 0 "register_operand" "")
10364 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10365 (match_operand:QI 2 "const_int_operand" ""))))
10366 (clobber (reg:CC 17))]
10368 && true_regnum (operands[0]) != true_regnum (operands[1])"
10369 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10371 operands[1] = gen_lowpart (Pmode, operands[1]);
10372 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10375 ;; This pattern can't accept a variable shift count, since shifts by
10376 ;; zero don't affect the flags. We assume that shifts by constant
10377 ;; zero are optimized away.
10378 (define_insn "*ashlsi3_cmp"
10381 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10382 (match_operand:QI 2 "immediate_operand" "I"))
10384 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10385 (ashift:SI (match_dup 1) (match_dup 2)))]
10386 "ix86_match_ccmode (insn, CCGOCmode)
10387 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10389 switch (get_attr_type (insn))
10392 if (operands[2] != const1_rtx)
10394 return "add{l}\t{%0, %0|%0, %0}";
10397 if (REG_P (operands[2]))
10398 return "sal{l}\t{%b2, %0|%0, %b2}";
10399 else if (GET_CODE (operands[2]) == CONST_INT
10400 && INTVAL (operands[2]) == 1
10401 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10402 return "sal{l}\t%0";
10404 return "sal{l}\t{%2, %0|%0, %2}";
10407 [(set (attr "type")
10408 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10410 (match_operand 0 "register_operand" ""))
10411 (match_operand 2 "const1_operand" ""))
10412 (const_string "alu")
10414 (const_string "ishift")))
10415 (set_attr "mode" "SI")])
10417 (define_insn "*ashlsi3_cmp_zext"
10420 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10421 (match_operand:QI 2 "immediate_operand" "I"))
10423 (set (match_operand:DI 0 "register_operand" "=r")
10424 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10425 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10426 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10428 switch (get_attr_type (insn))
10431 if (operands[2] != const1_rtx)
10433 return "add{l}\t{%k0, %k0|%k0, %k0}";
10436 if (REG_P (operands[2]))
10437 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10438 else if (GET_CODE (operands[2]) == CONST_INT
10439 && INTVAL (operands[2]) == 1
10440 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10441 return "sal{l}\t%k0";
10443 return "sal{l}\t{%2, %k0|%k0, %2}";
10446 [(set (attr "type")
10447 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10449 (match_operand 2 "const1_operand" ""))
10450 (const_string "alu")
10452 (const_string "ishift")))
10453 (set_attr "mode" "SI")])
10455 (define_expand "ashlhi3"
10456 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10457 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10458 (match_operand:QI 2 "nonmemory_operand" "")))
10459 (clobber (reg:CC 17))]
10460 "TARGET_HIMODE_MATH"
10461 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10463 (define_insn "*ashlhi3_1_lea"
10464 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10465 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10466 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10467 (clobber (reg:CC 17))]
10468 "!TARGET_PARTIAL_REG_STALL
10469 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10471 switch (get_attr_type (insn))
10476 if (operands[2] != const1_rtx)
10478 return "add{w}\t{%0, %0|%0, %0}";
10481 if (REG_P (operands[2]))
10482 return "sal{w}\t{%b2, %0|%0, %b2}";
10483 else if (GET_CODE (operands[2]) == CONST_INT
10484 && INTVAL (operands[2]) == 1
10485 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10486 return "sal{w}\t%0";
10488 return "sal{w}\t{%2, %0|%0, %2}";
10491 [(set (attr "type")
10492 (cond [(eq_attr "alternative" "1")
10493 (const_string "lea")
10494 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10496 (match_operand 0 "register_operand" ""))
10497 (match_operand 2 "const1_operand" ""))
10498 (const_string "alu")
10500 (const_string "ishift")))
10501 (set_attr "mode" "HI,SI")])
10503 (define_insn "*ashlhi3_1"
10504 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10505 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10506 (match_operand:QI 2 "nonmemory_operand" "cI")))
10507 (clobber (reg:CC 17))]
10508 "TARGET_PARTIAL_REG_STALL
10509 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10511 switch (get_attr_type (insn))
10514 if (operands[2] != const1_rtx)
10516 return "add{w}\t{%0, %0|%0, %0}";
10519 if (REG_P (operands[2]))
10520 return "sal{w}\t{%b2, %0|%0, %b2}";
10521 else if (GET_CODE (operands[2]) == CONST_INT
10522 && INTVAL (operands[2]) == 1
10523 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10524 return "sal{w}\t%0";
10526 return "sal{w}\t{%2, %0|%0, %2}";
10529 [(set (attr "type")
10530 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10532 (match_operand 0 "register_operand" ""))
10533 (match_operand 2 "const1_operand" ""))
10534 (const_string "alu")
10536 (const_string "ishift")))
10537 (set_attr "mode" "HI")])
10539 ;; This pattern can't accept a variable shift count, since shifts by
10540 ;; zero don't affect the flags. We assume that shifts by constant
10541 ;; zero are optimized away.
10542 (define_insn "*ashlhi3_cmp"
10545 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10546 (match_operand:QI 2 "immediate_operand" "I"))
10548 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10549 (ashift:HI (match_dup 1) (match_dup 2)))]
10550 "ix86_match_ccmode (insn, CCGOCmode)
10551 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10553 switch (get_attr_type (insn))
10556 if (operands[2] != const1_rtx)
10558 return "add{w}\t{%0, %0|%0, %0}";
10561 if (REG_P (operands[2]))
10562 return "sal{w}\t{%b2, %0|%0, %b2}";
10563 else if (GET_CODE (operands[2]) == CONST_INT
10564 && INTVAL (operands[2]) == 1
10565 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10566 return "sal{w}\t%0";
10568 return "sal{w}\t{%2, %0|%0, %2}";
10571 [(set (attr "type")
10572 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10574 (match_operand 0 "register_operand" ""))
10575 (match_operand 2 "const1_operand" ""))
10576 (const_string "alu")
10578 (const_string "ishift")))
10579 (set_attr "mode" "HI")])
10581 (define_expand "ashlqi3"
10582 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10583 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10584 (match_operand:QI 2 "nonmemory_operand" "")))
10585 (clobber (reg:CC 17))]
10586 "TARGET_QIMODE_MATH"
10587 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10589 ;; %%% Potential partial reg stall on alternative 2. What to do?
10591 (define_insn "*ashlqi3_1_lea"
10592 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10593 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
10594 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10595 (clobber (reg:CC 17))]
10596 "!TARGET_PARTIAL_REG_STALL
10597 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10599 switch (get_attr_type (insn))
10604 if (operands[2] != const1_rtx)
10606 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10607 return "add{l}\t{%k0, %k0|%k0, %k0}";
10609 return "add{b}\t{%0, %0|%0, %0}";
10612 if (REG_P (operands[2]))
10614 if (get_attr_mode (insn) == MODE_SI)
10615 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10617 return "sal{b}\t{%b2, %0|%0, %b2}";
10619 else if (GET_CODE (operands[2]) == CONST_INT
10620 && INTVAL (operands[2]) == 1
10621 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10623 if (get_attr_mode (insn) == MODE_SI)
10624 return "sal{l}\t%0";
10626 return "sal{b}\t%0";
10630 if (get_attr_mode (insn) == MODE_SI)
10631 return "sal{l}\t{%2, %k0|%k0, %2}";
10633 return "sal{b}\t{%2, %0|%0, %2}";
10637 [(set (attr "type")
10638 (cond [(eq_attr "alternative" "2")
10639 (const_string "lea")
10640 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10642 (match_operand 0 "register_operand" ""))
10643 (match_operand 2 "const1_operand" ""))
10644 (const_string "alu")
10646 (const_string "ishift")))
10647 (set_attr "mode" "QI,SI,SI")])
10649 (define_insn "*ashlqi3_1"
10650 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10651 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10652 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10653 (clobber (reg:CC 17))]
10654 "TARGET_PARTIAL_REG_STALL
10655 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10657 switch (get_attr_type (insn))
10660 if (operands[2] != const1_rtx)
10662 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10663 return "add{l}\t{%k0, %k0|%k0, %k0}";
10665 return "add{b}\t{%0, %0|%0, %0}";
10668 if (REG_P (operands[2]))
10670 if (get_attr_mode (insn) == MODE_SI)
10671 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10673 return "sal{b}\t{%b2, %0|%0, %b2}";
10675 else if (GET_CODE (operands[2]) == CONST_INT
10676 && INTVAL (operands[2]) == 1
10677 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10679 if (get_attr_mode (insn) == MODE_SI)
10680 return "sal{l}\t%0";
10682 return "sal{b}\t%0";
10686 if (get_attr_mode (insn) == MODE_SI)
10687 return "sal{l}\t{%2, %k0|%k0, %2}";
10689 return "sal{b}\t{%2, %0|%0, %2}";
10693 [(set (attr "type")
10694 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10696 (match_operand 0 "register_operand" ""))
10697 (match_operand 2 "const1_operand" ""))
10698 (const_string "alu")
10700 (const_string "ishift")))
10701 (set_attr "mode" "QI,SI")])
10703 ;; This pattern can't accept a variable shift count, since shifts by
10704 ;; zero don't affect the flags. We assume that shifts by constant
10705 ;; zero are optimized away.
10706 (define_insn "*ashlqi3_cmp"
10709 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
10710 (match_operand:QI 2 "immediate_operand" "I"))
10712 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10713 (ashift:QI (match_dup 1) (match_dup 2)))]
10714 "ix86_match_ccmode (insn, CCGOCmode)
10715 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10717 switch (get_attr_type (insn))
10720 if (operands[2] != const1_rtx)
10722 return "add{b}\t{%0, %0|%0, %0}";
10725 if (REG_P (operands[2]))
10726 return "sal{b}\t{%b2, %0|%0, %b2}";
10727 else if (GET_CODE (operands[2]) == CONST_INT
10728 && INTVAL (operands[2]) == 1
10729 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10730 return "sal{b}\t%0";
10732 return "sal{b}\t{%2, %0|%0, %2}";
10735 [(set (attr "type")
10736 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10738 (match_operand 0 "register_operand" ""))
10739 (match_operand 2 "const1_operand" ""))
10740 (const_string "alu")
10742 (const_string "ishift")))
10743 (set_attr "mode" "QI")])
10745 ;; See comment above `ashldi3' about how this works.
10747 (define_expand "ashrdi3"
10748 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10749 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
10750 (match_operand:QI 2 "nonmemory_operand" "")))
10751 (clobber (reg:CC 17))])]
10754 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10756 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
10759 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
10763 (define_insn "ashrdi3_63_rex64"
10764 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
10765 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
10766 (match_operand:DI 2 "const_int_operand" "i,i")))
10767 (clobber (reg:CC 17))]
10768 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
10769 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10772 sar{q}\t{%2, %0|%0, %2}"
10773 [(set_attr "type" "imovx,ishift")
10774 (set_attr "prefix_0f" "0,*")
10775 (set_attr "length_immediate" "0,*")
10776 (set_attr "modrm" "0,1")
10777 (set_attr "mode" "DI")])
10779 (define_insn "*ashrdi3_1_one_bit_rex64"
10780 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10781 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10782 (match_operand:QI 2 "const_int_1_operand" "")))
10783 (clobber (reg:CC 17))]
10784 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
10785 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
10787 [(set_attr "type" "ishift")
10788 (set (attr "length")
10789 (if_then_else (match_operand:DI 0 "register_operand" "")
10791 (const_string "*")))])
10793 (define_insn "*ashrdi3_1_rex64"
10794 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
10795 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
10796 (match_operand:QI 2 "nonmemory_operand" "J,c")))
10797 (clobber (reg:CC 17))]
10798 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10800 sar{q}\t{%2, %0|%0, %2}
10801 sar{q}\t{%b2, %0|%0, %b2}"
10802 [(set_attr "type" "ishift")
10803 (set_attr "mode" "DI")])
10805 ;; This pattern can't accept a variable shift count, since shifts by
10806 ;; zero don't affect the flags. We assume that shifts by constant
10807 ;; zero are optimized away.
10808 (define_insn "*ashrdi3_one_bit_cmp_rex64"
10811 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10812 (match_operand:QI 2 "const_int_1_operand" ""))
10814 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10815 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10816 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10817 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
10818 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10820 [(set_attr "type" "ishift")
10821 (set (attr "length")
10822 (if_then_else (match_operand:DI 0 "register_operand" "")
10824 (const_string "*")))])
10826 ;; This pattern can't accept a variable shift count, since shifts by
10827 ;; zero don't affect the flags. We assume that shifts by constant
10828 ;; zero are optimized away.
10829 (define_insn "*ashrdi3_cmp_rex64"
10832 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10833 (match_operand:QI 2 "const_int_operand" "n"))
10835 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10836 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10837 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10838 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10839 "sar{q}\t{%2, %0|%0, %2}"
10840 [(set_attr "type" "ishift")
10841 (set_attr "mode" "DI")])
10844 (define_insn "ashrdi3_1"
10845 [(set (match_operand:DI 0 "register_operand" "=r")
10846 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
10847 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10848 (clobber (match_scratch:SI 3 "=&r"))
10849 (clobber (reg:CC 17))]
10850 "!TARGET_64BIT && TARGET_CMOVE"
10852 [(set_attr "type" "multi")])
10854 (define_insn "*ashrdi3_2"
10855 [(set (match_operand:DI 0 "register_operand" "=r")
10856 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
10857 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10858 (clobber (reg:CC 17))]
10861 [(set_attr "type" "multi")])
10864 [(set (match_operand:DI 0 "register_operand" "")
10865 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10866 (match_operand:QI 2 "nonmemory_operand" "")))
10867 (clobber (match_scratch:SI 3 ""))
10868 (clobber (reg:CC 17))]
10869 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10871 "ix86_split_ashrdi (operands, operands[3]); DONE;")
10874 [(set (match_operand:DI 0 "register_operand" "")
10875 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10876 (match_operand:QI 2 "nonmemory_operand" "")))
10877 (clobber (reg:CC 17))]
10878 "!TARGET_64BIT && reload_completed"
10880 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
10882 (define_insn "x86_shrd_1"
10883 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10884 (ior:SI (ashiftrt:SI (match_dup 0)
10885 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10886 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
10887 (minus:QI (const_int 32) (match_dup 2)))))
10888 (clobber (reg:CC 17))]
10891 shrd{l}\t{%2, %1, %0|%0, %1, %2}
10892 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
10893 [(set_attr "type" "ishift")
10894 (set_attr "prefix_0f" "1")
10895 (set_attr "pent_pair" "np")
10896 (set_attr "ppro_uops" "few")
10897 (set_attr "mode" "SI")])
10899 (define_expand "x86_shift_adj_3"
10900 [(use (match_operand:SI 0 "register_operand" ""))
10901 (use (match_operand:SI 1 "register_operand" ""))
10902 (use (match_operand:QI 2 "register_operand" ""))]
10905 rtx label = gen_label_rtx ();
10908 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10910 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10911 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10912 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10913 gen_rtx_LABEL_REF (VOIDmode, label),
10915 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10916 JUMP_LABEL (tmp) = label;
10918 emit_move_insn (operands[0], operands[1]);
10919 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
10921 emit_label (label);
10922 LABEL_NUSES (label) = 1;
10927 (define_insn "ashrsi3_31"
10928 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
10929 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
10930 (match_operand:SI 2 "const_int_operand" "i,i")))
10931 (clobber (reg:CC 17))]
10932 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
10933 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
10936 sar{l}\t{%2, %0|%0, %2}"
10937 [(set_attr "type" "imovx,ishift")
10938 (set_attr "prefix_0f" "0,*")
10939 (set_attr "length_immediate" "0,*")
10940 (set_attr "modrm" "0,1")
10941 (set_attr "mode" "SI")])
10943 (define_insn "*ashrsi3_31_zext"
10944 [(set (match_operand:DI 0 "register_operand" "=*d,r")
10945 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
10946 (match_operand:SI 2 "const_int_operand" "i,i"))))
10947 (clobber (reg:CC 17))]
10948 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
10949 && INTVAL (operands[2]) == 31
10950 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
10953 sar{l}\t{%2, %k0|%k0, %2}"
10954 [(set_attr "type" "imovx,ishift")
10955 (set_attr "prefix_0f" "0,*")
10956 (set_attr "length_immediate" "0,*")
10957 (set_attr "modrm" "0,1")
10958 (set_attr "mode" "SI")])
10960 (define_expand "ashrsi3"
10961 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10962 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
10963 (match_operand:QI 2 "nonmemory_operand" "")))
10964 (clobber (reg:CC 17))]
10966 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
10968 (define_insn "*ashrsi3_1_one_bit"
10969 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10970 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10971 (match_operand:QI 2 "const_int_1_operand" "")))
10972 (clobber (reg:CC 17))]
10973 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
10974 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
10976 [(set_attr "type" "ishift")
10977 (set (attr "length")
10978 (if_then_else (match_operand:SI 0 "register_operand" "")
10980 (const_string "*")))])
10982 (define_insn "*ashrsi3_1_one_bit_zext"
10983 [(set (match_operand:DI 0 "register_operand" "=r")
10984 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
10985 (match_operand:QI 2 "const_int_1_operand" ""))))
10986 (clobber (reg:CC 17))]
10987 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
10988 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
10990 [(set_attr "type" "ishift")
10991 (set_attr "length" "2")])
10993 (define_insn "*ashrsi3_1"
10994 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
10995 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
10996 (match_operand:QI 2 "nonmemory_operand" "I,c")))
10997 (clobber (reg:CC 17))]
10998 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11000 sar{l}\t{%2, %0|%0, %2}
11001 sar{l}\t{%b2, %0|%0, %b2}"
11002 [(set_attr "type" "ishift")
11003 (set_attr "mode" "SI")])
11005 (define_insn "*ashrsi3_1_zext"
11006 [(set (match_operand:DI 0 "register_operand" "=r,r")
11007 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11008 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11009 (clobber (reg:CC 17))]
11010 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11012 sar{l}\t{%2, %k0|%k0, %2}
11013 sar{l}\t{%b2, %k0|%k0, %b2}"
11014 [(set_attr "type" "ishift")
11015 (set_attr "mode" "SI")])
11017 ;; This pattern can't accept a variable shift count, since shifts by
11018 ;; zero don't affect the flags. We assume that shifts by constant
11019 ;; zero are optimized away.
11020 (define_insn "*ashrsi3_one_bit_cmp"
11023 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11024 (match_operand:QI 2 "const_int_1_operand" ""))
11026 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11027 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11028 "ix86_match_ccmode (insn, CCGOCmode)
11029 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11030 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11032 [(set_attr "type" "ishift")
11033 (set (attr "length")
11034 (if_then_else (match_operand:SI 0 "register_operand" "")
11036 (const_string "*")))])
11038 (define_insn "*ashrsi3_one_bit_cmp_zext"
11041 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11042 (match_operand:QI 2 "const_int_1_operand" ""))
11044 (set (match_operand:DI 0 "register_operand" "=r")
11045 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11046 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11047 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11048 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11050 [(set_attr "type" "ishift")
11051 (set_attr "length" "2")])
11053 ;; This pattern can't accept a variable shift count, since shifts by
11054 ;; zero don't affect the flags. We assume that shifts by constant
11055 ;; zero are optimized away.
11056 (define_insn "*ashrsi3_cmp"
11059 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11060 (match_operand:QI 2 "immediate_operand" "I"))
11062 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11063 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11064 "ix86_match_ccmode (insn, CCGOCmode)
11065 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11066 "sar{l}\t{%2, %0|%0, %2}"
11067 [(set_attr "type" "ishift")
11068 (set_attr "mode" "SI")])
11070 (define_insn "*ashrsi3_cmp_zext"
11073 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11074 (match_operand:QI 2 "immediate_operand" "I"))
11076 (set (match_operand:DI 0 "register_operand" "=r")
11077 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11078 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11079 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11080 "sar{l}\t{%2, %k0|%k0, %2}"
11081 [(set_attr "type" "ishift")
11082 (set_attr "mode" "SI")])
11084 (define_expand "ashrhi3"
11085 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11086 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11087 (match_operand:QI 2 "nonmemory_operand" "")))
11088 (clobber (reg:CC 17))]
11089 "TARGET_HIMODE_MATH"
11090 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11092 (define_insn "*ashrhi3_1_one_bit"
11093 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11094 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11095 (match_operand:QI 2 "const_int_1_operand" "")))
11096 (clobber (reg:CC 17))]
11097 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11098 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11100 [(set_attr "type" "ishift")
11101 (set (attr "length")
11102 (if_then_else (match_operand 0 "register_operand" "")
11104 (const_string "*")))])
11106 (define_insn "*ashrhi3_1"
11107 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11108 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11109 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11110 (clobber (reg:CC 17))]
11111 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11113 sar{w}\t{%2, %0|%0, %2}
11114 sar{w}\t{%b2, %0|%0, %b2}"
11115 [(set_attr "type" "ishift")
11116 (set_attr "mode" "HI")])
11118 ;; This pattern can't accept a variable shift count, since shifts by
11119 ;; zero don't affect the flags. We assume that shifts by constant
11120 ;; zero are optimized away.
11121 (define_insn "*ashrhi3_one_bit_cmp"
11124 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11125 (match_operand:QI 2 "const_int_1_operand" ""))
11127 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11128 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11129 "ix86_match_ccmode (insn, CCGOCmode)
11130 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11131 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11133 [(set_attr "type" "ishift")
11134 (set (attr "length")
11135 (if_then_else (match_operand 0 "register_operand" "")
11137 (const_string "*")))])
11139 ;; This pattern can't accept a variable shift count, since shifts by
11140 ;; zero don't affect the flags. We assume that shifts by constant
11141 ;; zero are optimized away.
11142 (define_insn "*ashrhi3_cmp"
11145 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11146 (match_operand:QI 2 "immediate_operand" "I"))
11148 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11149 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11150 "ix86_match_ccmode (insn, CCGOCmode)
11151 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11152 "sar{w}\t{%2, %0|%0, %2}"
11153 [(set_attr "type" "ishift")
11154 (set_attr "mode" "HI")])
11156 (define_expand "ashrqi3"
11157 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11158 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11159 (match_operand:QI 2 "nonmemory_operand" "")))
11160 (clobber (reg:CC 17))]
11161 "TARGET_QIMODE_MATH"
11162 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11164 (define_insn "*ashrqi3_1_one_bit"
11165 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11166 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11167 (match_operand:QI 2 "const_int_1_operand" "")))
11168 (clobber (reg:CC 17))]
11169 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11170 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11172 [(set_attr "type" "ishift")
11173 (set (attr "length")
11174 (if_then_else (match_operand 0 "register_operand" "")
11176 (const_string "*")))])
11178 (define_insn "*ashrqi3_1"
11179 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11180 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11181 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11182 (clobber (reg:CC 17))]
11183 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11185 sar{b}\t{%2, %0|%0, %2}
11186 sar{b}\t{%b2, %0|%0, %b2}"
11187 [(set_attr "type" "ishift")
11188 (set_attr "mode" "QI")])
11190 ;; This pattern can't accept a variable shift count, since shifts by
11191 ;; zero don't affect the flags. We assume that shifts by constant
11192 ;; zero are optimized away.
11193 (define_insn "*ashrqi3_one_bit_cmp"
11196 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11197 (match_operand:QI 2 "const_int_1_operand" "I"))
11199 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11200 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11201 "ix86_match_ccmode (insn, CCGOCmode)
11202 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11203 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11205 [(set_attr "type" "ishift")
11206 (set (attr "length")
11207 (if_then_else (match_operand 0 "register_operand" "")
11209 (const_string "*")))])
11211 ;; This pattern can't accept a variable shift count, since shifts by
11212 ;; zero don't affect the flags. We assume that shifts by constant
11213 ;; zero are optimized away.
11214 (define_insn "*ashrqi3_cmp"
11217 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11218 (match_operand:QI 2 "immediate_operand" "I"))
11220 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11221 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11222 "ix86_match_ccmode (insn, CCGOCmode)
11223 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11224 "sar{b}\t{%2, %0|%0, %2}"
11225 [(set_attr "type" "ishift")
11226 (set_attr "mode" "QI")])
11228 ;; Logical shift instructions
11230 ;; See comment above `ashldi3' about how this works.
11232 (define_expand "lshrdi3"
11233 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11234 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11235 (match_operand:QI 2 "nonmemory_operand" "")))
11236 (clobber (reg:CC 17))])]
11239 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11241 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11244 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11248 (define_insn "*lshrdi3_1_one_bit_rex64"
11249 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11250 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11251 (match_operand:QI 2 "const_int_1_operand" "")))
11252 (clobber (reg:CC 17))]
11253 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11254 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11256 [(set_attr "type" "ishift")
11257 (set (attr "length")
11258 (if_then_else (match_operand:DI 0 "register_operand" "")
11260 (const_string "*")))])
11262 (define_insn "*lshrdi3_1_rex64"
11263 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11264 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11265 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11266 (clobber (reg:CC 17))]
11267 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11269 shr{q}\t{%2, %0|%0, %2}
11270 shr{q}\t{%b2, %0|%0, %b2}"
11271 [(set_attr "type" "ishift")
11272 (set_attr "mode" "DI")])
11274 ;; This pattern can't accept a variable shift count, since shifts by
11275 ;; zero don't affect the flags. We assume that shifts by constant
11276 ;; zero are optimized away.
11277 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11280 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11281 (match_operand:QI 2 "const_int_1_operand" ""))
11283 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11284 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11285 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11286 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11287 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11289 [(set_attr "type" "ishift")
11290 (set (attr "length")
11291 (if_then_else (match_operand:DI 0 "register_operand" "")
11293 (const_string "*")))])
11295 ;; This pattern can't accept a variable shift count, since shifts by
11296 ;; zero don't affect the flags. We assume that shifts by constant
11297 ;; zero are optimized away.
11298 (define_insn "*lshrdi3_cmp_rex64"
11301 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11302 (match_operand:QI 2 "const_int_operand" "e"))
11304 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11305 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11306 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11307 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11308 "shr{q}\t{%2, %0|%0, %2}"
11309 [(set_attr "type" "ishift")
11310 (set_attr "mode" "DI")])
11312 (define_insn "lshrdi3_1"
11313 [(set (match_operand:DI 0 "register_operand" "=r")
11314 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11315 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11316 (clobber (match_scratch:SI 3 "=&r"))
11317 (clobber (reg:CC 17))]
11318 "!TARGET_64BIT && TARGET_CMOVE"
11320 [(set_attr "type" "multi")])
11322 (define_insn "*lshrdi3_2"
11323 [(set (match_operand:DI 0 "register_operand" "=r")
11324 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11325 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11326 (clobber (reg:CC 17))]
11329 [(set_attr "type" "multi")])
11332 [(set (match_operand:DI 0 "register_operand" "")
11333 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11334 (match_operand:QI 2 "nonmemory_operand" "")))
11335 (clobber (match_scratch:SI 3 ""))
11336 (clobber (reg:CC 17))]
11337 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11339 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11342 [(set (match_operand:DI 0 "register_operand" "")
11343 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11344 (match_operand:QI 2 "nonmemory_operand" "")))
11345 (clobber (reg:CC 17))]
11346 "!TARGET_64BIT && reload_completed"
11348 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11350 (define_expand "lshrsi3"
11351 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11352 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11353 (match_operand:QI 2 "nonmemory_operand" "")))
11354 (clobber (reg:CC 17))]
11356 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11358 (define_insn "*lshrsi3_1_one_bit"
11359 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11360 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11361 (match_operand:QI 2 "const_int_1_operand" "")))
11362 (clobber (reg:CC 17))]
11363 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11364 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11366 [(set_attr "type" "ishift")
11367 (set (attr "length")
11368 (if_then_else (match_operand:SI 0 "register_operand" "")
11370 (const_string "*")))])
11372 (define_insn "*lshrsi3_1_one_bit_zext"
11373 [(set (match_operand:DI 0 "register_operand" "=r")
11374 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11375 (match_operand:QI 2 "const_int_1_operand" "")))
11376 (clobber (reg:CC 17))]
11377 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11378 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11380 [(set_attr "type" "ishift")
11381 (set_attr "length" "2")])
11383 (define_insn "*lshrsi3_1"
11384 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11385 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11386 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11387 (clobber (reg:CC 17))]
11388 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11390 shr{l}\t{%2, %0|%0, %2}
11391 shr{l}\t{%b2, %0|%0, %b2}"
11392 [(set_attr "type" "ishift")
11393 (set_attr "mode" "SI")])
11395 (define_insn "*lshrsi3_1_zext"
11396 [(set (match_operand:DI 0 "register_operand" "=r,r")
11398 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11399 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11400 (clobber (reg:CC 17))]
11401 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11403 shr{l}\t{%2, %k0|%k0, %2}
11404 shr{l}\t{%b2, %k0|%k0, %b2}"
11405 [(set_attr "type" "ishift")
11406 (set_attr "mode" "SI")])
11408 ;; This pattern can't accept a variable shift count, since shifts by
11409 ;; zero don't affect the flags. We assume that shifts by constant
11410 ;; zero are optimized away.
11411 (define_insn "*lshrsi3_one_bit_cmp"
11414 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11415 (match_operand:QI 2 "const_int_1_operand" ""))
11417 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11418 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11419 "ix86_match_ccmode (insn, CCGOCmode)
11420 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11421 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11423 [(set_attr "type" "ishift")
11424 (set (attr "length")
11425 (if_then_else (match_operand:SI 0 "register_operand" "")
11427 (const_string "*")))])
11429 (define_insn "*lshrsi3_cmp_one_bit_zext"
11432 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11433 (match_operand:QI 2 "const_int_1_operand" ""))
11435 (set (match_operand:DI 0 "register_operand" "=r")
11436 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11437 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11438 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11439 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11441 [(set_attr "type" "ishift")
11442 (set_attr "length" "2")])
11444 ;; This pattern can't accept a variable shift count, since shifts by
11445 ;; zero don't affect the flags. We assume that shifts by constant
11446 ;; zero are optimized away.
11447 (define_insn "*lshrsi3_cmp"
11450 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11451 (match_operand:QI 2 "immediate_operand" "I"))
11453 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11454 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11455 "ix86_match_ccmode (insn, CCGOCmode)
11456 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11457 "shr{l}\t{%2, %0|%0, %2}"
11458 [(set_attr "type" "ishift")
11459 (set_attr "mode" "SI")])
11461 (define_insn "*lshrsi3_cmp_zext"
11464 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11465 (match_operand:QI 2 "immediate_operand" "I"))
11467 (set (match_operand:DI 0 "register_operand" "=r")
11468 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11469 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11470 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11471 "shr{l}\t{%2, %k0|%k0, %2}"
11472 [(set_attr "type" "ishift")
11473 (set_attr "mode" "SI")])
11475 (define_expand "lshrhi3"
11476 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11477 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11478 (match_operand:QI 2 "nonmemory_operand" "")))
11479 (clobber (reg:CC 17))]
11480 "TARGET_HIMODE_MATH"
11481 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11483 (define_insn "*lshrhi3_1_one_bit"
11484 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11485 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11486 (match_operand:QI 2 "const_int_1_operand" "")))
11487 (clobber (reg:CC 17))]
11488 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11489 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11491 [(set_attr "type" "ishift")
11492 (set (attr "length")
11493 (if_then_else (match_operand 0 "register_operand" "")
11495 (const_string "*")))])
11497 (define_insn "*lshrhi3_1"
11498 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11499 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11500 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11501 (clobber (reg:CC 17))]
11502 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11504 shr{w}\t{%2, %0|%0, %2}
11505 shr{w}\t{%b2, %0|%0, %b2}"
11506 [(set_attr "type" "ishift")
11507 (set_attr "mode" "HI")])
11509 ;; This pattern can't accept a variable shift count, since shifts by
11510 ;; zero don't affect the flags. We assume that shifts by constant
11511 ;; zero are optimized away.
11512 (define_insn "*lshrhi3_one_bit_cmp"
11515 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11516 (match_operand:QI 2 "const_int_1_operand" ""))
11518 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11519 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11520 "ix86_match_ccmode (insn, CCGOCmode)
11521 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11522 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11524 [(set_attr "type" "ishift")
11525 (set (attr "length")
11526 (if_then_else (match_operand:SI 0 "register_operand" "")
11528 (const_string "*")))])
11530 ;; This pattern can't accept a variable shift count, since shifts by
11531 ;; zero don't affect the flags. We assume that shifts by constant
11532 ;; zero are optimized away.
11533 (define_insn "*lshrhi3_cmp"
11536 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11537 (match_operand:QI 2 "immediate_operand" "I"))
11539 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11540 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11541 "ix86_match_ccmode (insn, CCGOCmode)
11542 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11543 "shr{w}\t{%2, %0|%0, %2}"
11544 [(set_attr "type" "ishift")
11545 (set_attr "mode" "HI")])
11547 (define_expand "lshrqi3"
11548 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11549 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11550 (match_operand:QI 2 "nonmemory_operand" "")))
11551 (clobber (reg:CC 17))]
11552 "TARGET_QIMODE_MATH"
11553 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11555 (define_insn "*lshrqi3_1_one_bit"
11556 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11557 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11558 (match_operand:QI 2 "const_int_1_operand" "")))
11559 (clobber (reg:CC 17))]
11560 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11561 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11563 [(set_attr "type" "ishift")
11564 (set (attr "length")
11565 (if_then_else (match_operand 0 "register_operand" "")
11567 (const_string "*")))])
11569 (define_insn "*lshrqi3_1"
11570 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11571 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11572 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11573 (clobber (reg:CC 17))]
11574 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11576 shr{b}\t{%2, %0|%0, %2}
11577 shr{b}\t{%b2, %0|%0, %b2}"
11578 [(set_attr "type" "ishift")
11579 (set_attr "mode" "QI")])
11581 ;; This pattern can't accept a variable shift count, since shifts by
11582 ;; zero don't affect the flags. We assume that shifts by constant
11583 ;; zero are optimized away.
11584 (define_insn "*lshrqi2_one_bit_cmp"
11587 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11588 (match_operand:QI 2 "const_int_1_operand" ""))
11590 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11591 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11592 "ix86_match_ccmode (insn, CCGOCmode)
11593 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11594 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11596 [(set_attr "type" "ishift")
11597 (set (attr "length")
11598 (if_then_else (match_operand:SI 0 "register_operand" "")
11600 (const_string "*")))])
11602 ;; This pattern can't accept a variable shift count, since shifts by
11603 ;; zero don't affect the flags. We assume that shifts by constant
11604 ;; zero are optimized away.
11605 (define_insn "*lshrqi2_cmp"
11608 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11609 (match_operand:QI 2 "immediate_operand" "I"))
11611 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11612 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11613 "ix86_match_ccmode (insn, CCGOCmode)
11614 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11615 "shr{b}\t{%2, %0|%0, %2}"
11616 [(set_attr "type" "ishift")
11617 (set_attr "mode" "QI")])
11619 ;; Rotate instructions
11621 (define_expand "rotldi3"
11622 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11623 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
11624 (match_operand:QI 2 "nonmemory_operand" "")))
11625 (clobber (reg:CC 17))]
11627 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
11629 (define_insn "*rotlsi3_1_one_bit_rex64"
11630 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11631 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11632 (match_operand:QI 2 "const_int_1_operand" "")))
11633 (clobber (reg:CC 17))]
11634 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
11635 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11637 [(set_attr "type" "rotate")
11638 (set (attr "length")
11639 (if_then_else (match_operand:DI 0 "register_operand" "")
11641 (const_string "*")))])
11643 (define_insn "*rotldi3_1_rex64"
11644 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11645 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11646 (match_operand:QI 2 "nonmemory_operand" "e,c")))
11647 (clobber (reg:CC 17))]
11648 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
11650 rol{q}\t{%2, %0|%0, %2}
11651 rol{q}\t{%b2, %0|%0, %b2}"
11652 [(set_attr "type" "rotate")
11653 (set_attr "mode" "DI")])
11655 (define_expand "rotlsi3"
11656 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11657 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
11658 (match_operand:QI 2 "nonmemory_operand" "")))
11659 (clobber (reg:CC 17))]
11661 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
11663 (define_insn "*rotlsi3_1_one_bit"
11664 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11665 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11666 (match_operand:QI 2 "const_int_1_operand" "")))
11667 (clobber (reg:CC 17))]
11668 "ix86_binary_operator_ok (ROTATE, SImode, operands)
11669 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11671 [(set_attr "type" "rotate")
11672 (set (attr "length")
11673 (if_then_else (match_operand:SI 0 "register_operand" "")
11675 (const_string "*")))])
11677 (define_insn "*rotlsi3_1_one_bit_zext"
11678 [(set (match_operand:DI 0 "register_operand" "=r")
11680 (rotate:SI (match_operand:SI 1 "register_operand" "0")
11681 (match_operand:QI 2 "const_int_1_operand" ""))))
11682 (clobber (reg:CC 17))]
11683 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
11684 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11686 [(set_attr "type" "rotate")
11687 (set_attr "length" "2")])
11689 (define_insn "*rotlsi3_1"
11690 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11691 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11692 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11693 (clobber (reg:CC 17))]
11694 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
11696 rol{l}\t{%2, %0|%0, %2}
11697 rol{l}\t{%b2, %0|%0, %b2}"
11698 [(set_attr "type" "rotate")
11699 (set_attr "mode" "SI")])
11701 (define_insn "*rotlsi3_1_zext"
11702 [(set (match_operand:DI 0 "register_operand" "=r,r")
11704 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
11705 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11706 (clobber (reg:CC 17))]
11707 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
11709 rol{l}\t{%2, %k0|%k0, %2}
11710 rol{l}\t{%b2, %k0|%k0, %b2}"
11711 [(set_attr "type" "rotate")
11712 (set_attr "mode" "SI")])
11714 (define_expand "rotlhi3"
11715 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11716 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
11717 (match_operand:QI 2 "nonmemory_operand" "")))
11718 (clobber (reg:CC 17))]
11719 "TARGET_HIMODE_MATH"
11720 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
11722 (define_insn "*rotlhi3_1_one_bit"
11723 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11724 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11725 (match_operand:QI 2 "const_int_1_operand" "")))
11726 (clobber (reg:CC 17))]
11727 "ix86_binary_operator_ok (ROTATE, HImode, operands)
11728 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11730 [(set_attr "type" "rotate")
11731 (set (attr "length")
11732 (if_then_else (match_operand 0 "register_operand" "")
11734 (const_string "*")))])
11736 (define_insn "*rotlhi3_1"
11737 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11738 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11739 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11740 (clobber (reg:CC 17))]
11741 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
11743 rol{w}\t{%2, %0|%0, %2}
11744 rol{w}\t{%b2, %0|%0, %b2}"
11745 [(set_attr "type" "rotate")
11746 (set_attr "mode" "HI")])
11748 (define_expand "rotlqi3"
11749 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11750 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
11751 (match_operand:QI 2 "nonmemory_operand" "")))
11752 (clobber (reg:CC 17))]
11753 "TARGET_QIMODE_MATH"
11754 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
11756 (define_insn "*rotlqi3_1_one_bit"
11757 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11758 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11759 (match_operand:QI 2 "const_int_1_operand" "")))
11760 (clobber (reg:CC 17))]
11761 "ix86_binary_operator_ok (ROTATE, QImode, operands)
11762 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11764 [(set_attr "type" "rotate")
11765 (set (attr "length")
11766 (if_then_else (match_operand 0 "register_operand" "")
11768 (const_string "*")))])
11770 (define_insn "*rotlqi3_1"
11771 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11772 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11773 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11774 (clobber (reg:CC 17))]
11775 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
11777 rol{b}\t{%2, %0|%0, %2}
11778 rol{b}\t{%b2, %0|%0, %b2}"
11779 [(set_attr "type" "rotate")
11780 (set_attr "mode" "QI")])
11782 (define_expand "rotrdi3"
11783 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11784 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
11785 (match_operand:QI 2 "nonmemory_operand" "")))
11786 (clobber (reg:CC 17))]
11788 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
11790 (define_insn "*rotrdi3_1_one_bit_rex64"
11791 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11792 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11793 (match_operand:QI 2 "const_int_1_operand" "")))
11794 (clobber (reg:CC 17))]
11795 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
11796 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11798 [(set_attr "type" "rotate")
11799 (set (attr "length")
11800 (if_then_else (match_operand:DI 0 "register_operand" "")
11802 (const_string "*")))])
11804 (define_insn "*rotrdi3_1_rex64"
11805 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11806 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11807 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11808 (clobber (reg:CC 17))]
11809 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
11811 ror{q}\t{%2, %0|%0, %2}
11812 ror{q}\t{%b2, %0|%0, %b2}"
11813 [(set_attr "type" "rotate")
11814 (set_attr "mode" "DI")])
11816 (define_expand "rotrsi3"
11817 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11818 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
11819 (match_operand:QI 2 "nonmemory_operand" "")))
11820 (clobber (reg:CC 17))]
11822 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
11824 (define_insn "*rotrsi3_1_one_bit"
11825 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11826 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11827 (match_operand:QI 2 "const_int_1_operand" "")))
11828 (clobber (reg:CC 17))]
11829 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
11830 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11832 [(set_attr "type" "rotate")
11833 (set (attr "length")
11834 (if_then_else (match_operand:SI 0 "register_operand" "")
11836 (const_string "*")))])
11838 (define_insn "*rotrsi3_1_one_bit_zext"
11839 [(set (match_operand:DI 0 "register_operand" "=r")
11841 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
11842 (match_operand:QI 2 "const_int_1_operand" ""))))
11843 (clobber (reg:CC 17))]
11844 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
11845 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11847 [(set_attr "type" "rotate")
11848 (set (attr "length")
11849 (if_then_else (match_operand:SI 0 "register_operand" "")
11851 (const_string "*")))])
11853 (define_insn "*rotrsi3_1"
11854 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11855 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11856 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11857 (clobber (reg:CC 17))]
11858 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
11860 ror{l}\t{%2, %0|%0, %2}
11861 ror{l}\t{%b2, %0|%0, %b2}"
11862 [(set_attr "type" "rotate")
11863 (set_attr "mode" "SI")])
11865 (define_insn "*rotrsi3_1_zext"
11866 [(set (match_operand:DI 0 "register_operand" "=r,r")
11868 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
11869 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11870 (clobber (reg:CC 17))]
11871 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
11873 ror{l}\t{%2, %k0|%k0, %2}
11874 ror{l}\t{%b2, %k0|%k0, %b2}"
11875 [(set_attr "type" "rotate")
11876 (set_attr "mode" "SI")])
11878 (define_expand "rotrhi3"
11879 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11880 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
11881 (match_operand:QI 2 "nonmemory_operand" "")))
11882 (clobber (reg:CC 17))]
11883 "TARGET_HIMODE_MATH"
11884 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
11886 (define_insn "*rotrhi3_one_bit"
11887 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11888 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11889 (match_operand:QI 2 "const_int_1_operand" "")))
11890 (clobber (reg:CC 17))]
11891 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
11892 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11894 [(set_attr "type" "rotate")
11895 (set (attr "length")
11896 (if_then_else (match_operand 0 "register_operand" "")
11898 (const_string "*")))])
11900 (define_insn "*rotrhi3"
11901 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11902 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11903 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11904 (clobber (reg:CC 17))]
11905 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
11907 ror{w}\t{%2, %0|%0, %2}
11908 ror{w}\t{%b2, %0|%0, %b2}"
11909 [(set_attr "type" "rotate")
11910 (set_attr "mode" "HI")])
11912 (define_expand "rotrqi3"
11913 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11914 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
11915 (match_operand:QI 2 "nonmemory_operand" "")))
11916 (clobber (reg:CC 17))]
11917 "TARGET_QIMODE_MATH"
11918 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
11920 (define_insn "*rotrqi3_1_one_bit"
11921 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11922 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11923 (match_operand:QI 2 "const_int_1_operand" "")))
11924 (clobber (reg:CC 17))]
11925 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
11926 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11928 [(set_attr "type" "rotate")
11929 (set (attr "length")
11930 (if_then_else (match_operand 0 "register_operand" "")
11932 (const_string "*")))])
11934 (define_insn "*rotrqi3_1"
11935 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11936 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11937 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11938 (clobber (reg:CC 17))]
11939 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
11941 ror{b}\t{%2, %0|%0, %2}
11942 ror{b}\t{%b2, %0|%0, %b2}"
11943 [(set_attr "type" "rotate")
11944 (set_attr "mode" "QI")])
11946 ;; Bit set / bit test instructions
11948 (define_expand "extv"
11949 [(set (match_operand:SI 0 "register_operand" "")
11950 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
11951 (match_operand:SI 2 "immediate_operand" "")
11952 (match_operand:SI 3 "immediate_operand" "")))]
11955 /* Handle extractions from %ah et al. */
11956 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
11959 /* From mips.md: extract_bit_field doesn't verify that our source
11960 matches the predicate, so check it again here. */
11961 if (! register_operand (operands[1], VOIDmode))
11965 (define_expand "extzv"
11966 [(set (match_operand:SI 0 "register_operand" "")
11967 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
11968 (match_operand:SI 2 "immediate_operand" "")
11969 (match_operand:SI 3 "immediate_operand" "")))]
11972 /* Handle extractions from %ah et al. */
11973 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
11976 /* From mips.md: extract_bit_field doesn't verify that our source
11977 matches the predicate, so check it again here. */
11978 if (! register_operand (operands[1], VOIDmode))
11982 (define_expand "insv"
11983 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
11984 (match_operand:SI 1 "immediate_operand" "")
11985 (match_operand:SI 2 "immediate_operand" ""))
11986 (match_operand:SI 3 "register_operand" ""))]
11989 /* Handle extractions from %ah et al. */
11990 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
11993 /* From mips.md: insert_bit_field doesn't verify that our source
11994 matches the predicate, so check it again here. */
11995 if (! register_operand (operands[0], VOIDmode))
11999 ;; %%% bts, btr, btc, bt.
12001 ;; Store-flag instructions.
12003 ;; For all sCOND expanders, also expand the compare or test insn that
12004 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12006 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12007 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12008 ;; way, which can later delete the movzx if only QImode is needed.
12010 (define_expand "seq"
12011 [(set (match_operand:QI 0 "register_operand" "")
12012 (eq:QI (reg:CC 17) (const_int 0)))]
12014 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12016 (define_expand "sne"
12017 [(set (match_operand:QI 0 "register_operand" "")
12018 (ne:QI (reg:CC 17) (const_int 0)))]
12020 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12022 (define_expand "sgt"
12023 [(set (match_operand:QI 0 "register_operand" "")
12024 (gt:QI (reg:CC 17) (const_int 0)))]
12026 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12028 (define_expand "sgtu"
12029 [(set (match_operand:QI 0 "register_operand" "")
12030 (gtu:QI (reg:CC 17) (const_int 0)))]
12032 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12034 (define_expand "slt"
12035 [(set (match_operand:QI 0 "register_operand" "")
12036 (lt:QI (reg:CC 17) (const_int 0)))]
12038 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12040 (define_expand "sltu"
12041 [(set (match_operand:QI 0 "register_operand" "")
12042 (ltu:QI (reg:CC 17) (const_int 0)))]
12044 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12046 (define_expand "sge"
12047 [(set (match_operand:QI 0 "register_operand" "")
12048 (ge:QI (reg:CC 17) (const_int 0)))]
12050 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12052 (define_expand "sgeu"
12053 [(set (match_operand:QI 0 "register_operand" "")
12054 (geu:QI (reg:CC 17) (const_int 0)))]
12056 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12058 (define_expand "sle"
12059 [(set (match_operand:QI 0 "register_operand" "")
12060 (le:QI (reg:CC 17) (const_int 0)))]
12062 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12064 (define_expand "sleu"
12065 [(set (match_operand:QI 0 "register_operand" "")
12066 (leu:QI (reg:CC 17) (const_int 0)))]
12068 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12070 (define_expand "sunordered"
12071 [(set (match_operand:QI 0 "register_operand" "")
12072 (unordered:QI (reg:CC 17) (const_int 0)))]
12073 "TARGET_80387 || TARGET_SSE"
12074 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12076 (define_expand "sordered"
12077 [(set (match_operand:QI 0 "register_operand" "")
12078 (ordered:QI (reg:CC 17) (const_int 0)))]
12080 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12082 (define_expand "suneq"
12083 [(set (match_operand:QI 0 "register_operand" "")
12084 (uneq:QI (reg:CC 17) (const_int 0)))]
12085 "TARGET_80387 || TARGET_SSE"
12086 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12088 (define_expand "sunge"
12089 [(set (match_operand:QI 0 "register_operand" "")
12090 (unge:QI (reg:CC 17) (const_int 0)))]
12091 "TARGET_80387 || TARGET_SSE"
12092 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12094 (define_expand "sungt"
12095 [(set (match_operand:QI 0 "register_operand" "")
12096 (ungt:QI (reg:CC 17) (const_int 0)))]
12097 "TARGET_80387 || TARGET_SSE"
12098 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12100 (define_expand "sunle"
12101 [(set (match_operand:QI 0 "register_operand" "")
12102 (unle:QI (reg:CC 17) (const_int 0)))]
12103 "TARGET_80387 || TARGET_SSE"
12104 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12106 (define_expand "sunlt"
12107 [(set (match_operand:QI 0 "register_operand" "")
12108 (unlt:QI (reg:CC 17) (const_int 0)))]
12109 "TARGET_80387 || TARGET_SSE"
12110 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12112 (define_expand "sltgt"
12113 [(set (match_operand:QI 0 "register_operand" "")
12114 (ltgt:QI (reg:CC 17) (const_int 0)))]
12115 "TARGET_80387 || TARGET_SSE"
12116 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12118 (define_insn "*setcc_1"
12119 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12120 (match_operator:QI 1 "ix86_comparison_operator"
12121 [(reg 17) (const_int 0)]))]
12124 [(set_attr "type" "setcc")
12125 (set_attr "mode" "QI")])
12127 (define_insn "setcc_2"
12128 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12129 (match_operator:QI 1 "ix86_comparison_operator"
12130 [(reg 17) (const_int 0)]))]
12133 [(set_attr "type" "setcc")
12134 (set_attr "mode" "QI")])
12136 ;; In general it is not safe to assume too much about CCmode registers,
12137 ;; so simplify-rtx stops when it sees a second one. Under certain
12138 ;; conditions this is safe on x86, so help combine not create
12145 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12146 (ne:QI (match_operator 1 "ix86_comparison_operator"
12147 [(reg 17) (const_int 0)])
12150 [(set (match_dup 0) (match_dup 1))]
12152 PUT_MODE (operands[1], QImode);
12156 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12157 (ne:QI (match_operator 1 "ix86_comparison_operator"
12158 [(reg 17) (const_int 0)])
12161 [(set (match_dup 0) (match_dup 1))]
12163 PUT_MODE (operands[1], QImode);
12167 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12168 (eq:QI (match_operator 1 "ix86_comparison_operator"
12169 [(reg 17) (const_int 0)])
12172 [(set (match_dup 0) (match_dup 1))]
12174 rtx new_op1 = copy_rtx (operands[1]);
12175 operands[1] = new_op1;
12176 PUT_MODE (new_op1, QImode);
12177 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12178 GET_MODE (XEXP (new_op1, 0))));
12180 /* Make sure that (a) the CCmode we have for the flags is strong
12181 enough for the reversed compare or (b) we have a valid FP compare. */
12182 if (! ix86_comparison_operator (new_op1, VOIDmode))
12187 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12188 (eq:QI (match_operator 1 "ix86_comparison_operator"
12189 [(reg 17) (const_int 0)])
12192 [(set (match_dup 0) (match_dup 1))]
12194 rtx new_op1 = copy_rtx (operands[1]);
12195 operands[1] = new_op1;
12196 PUT_MODE (new_op1, QImode);
12197 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12198 GET_MODE (XEXP (new_op1, 0))));
12200 /* Make sure that (a) the CCmode we have for the flags is strong
12201 enough for the reversed compare or (b) we have a valid FP compare. */
12202 if (! ix86_comparison_operator (new_op1, VOIDmode))
12206 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12207 ;; subsequent logical operations are used to imitate conditional moves.
12208 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12209 ;; it directly. Futher holding this value in pseudo register might bring
12210 ;; problem in implicit normalization in spill code.
12211 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12212 ;; instructions after reload by splitting the conditional move patterns.
12214 (define_insn "*sse_setccsf"
12215 [(set (match_operand:SF 0 "register_operand" "=x")
12216 (match_operator:SF 1 "sse_comparison_operator"
12217 [(match_operand:SF 2 "register_operand" "0")
12218 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12219 "TARGET_SSE && reload_completed"
12220 "cmp%D1ss\t{%3, %0|%0, %3}"
12221 [(set_attr "type" "ssecmp")
12222 (set_attr "mode" "SF")])
12224 (define_insn "*sse_setccdf"
12225 [(set (match_operand:DF 0 "register_operand" "=Y")
12226 (match_operator:DF 1 "sse_comparison_operator"
12227 [(match_operand:DF 2 "register_operand" "0")
12228 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12229 "TARGET_SSE2 && reload_completed"
12230 "cmp%D1sd\t{%3, %0|%0, %3}"
12231 [(set_attr "type" "ssecmp")
12232 (set_attr "mode" "DF")])
12234 ;; Basic conditional jump instructions.
12235 ;; We ignore the overflow flag for signed branch instructions.
12237 ;; For all bCOND expanders, also expand the compare or test insn that
12238 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12240 (define_expand "beq"
12242 (if_then_else (match_dup 1)
12243 (label_ref (match_operand 0 "" ""))
12246 "ix86_expand_branch (EQ, operands[0]); DONE;")
12248 (define_expand "bne"
12250 (if_then_else (match_dup 1)
12251 (label_ref (match_operand 0 "" ""))
12254 "ix86_expand_branch (NE, operands[0]); DONE;")
12256 (define_expand "bgt"
12258 (if_then_else (match_dup 1)
12259 (label_ref (match_operand 0 "" ""))
12262 "ix86_expand_branch (GT, operands[0]); DONE;")
12264 (define_expand "bgtu"
12266 (if_then_else (match_dup 1)
12267 (label_ref (match_operand 0 "" ""))
12270 "ix86_expand_branch (GTU, operands[0]); DONE;")
12272 (define_expand "blt"
12274 (if_then_else (match_dup 1)
12275 (label_ref (match_operand 0 "" ""))
12278 "ix86_expand_branch (LT, operands[0]); DONE;")
12280 (define_expand "bltu"
12282 (if_then_else (match_dup 1)
12283 (label_ref (match_operand 0 "" ""))
12286 "ix86_expand_branch (LTU, operands[0]); DONE;")
12288 (define_expand "bge"
12290 (if_then_else (match_dup 1)
12291 (label_ref (match_operand 0 "" ""))
12294 "ix86_expand_branch (GE, operands[0]); DONE;")
12296 (define_expand "bgeu"
12298 (if_then_else (match_dup 1)
12299 (label_ref (match_operand 0 "" ""))
12302 "ix86_expand_branch (GEU, operands[0]); DONE;")
12304 (define_expand "ble"
12306 (if_then_else (match_dup 1)
12307 (label_ref (match_operand 0 "" ""))
12310 "ix86_expand_branch (LE, operands[0]); DONE;")
12312 (define_expand "bleu"
12314 (if_then_else (match_dup 1)
12315 (label_ref (match_operand 0 "" ""))
12318 "ix86_expand_branch (LEU, operands[0]); DONE;")
12320 (define_expand "bunordered"
12322 (if_then_else (match_dup 1)
12323 (label_ref (match_operand 0 "" ""))
12325 "TARGET_80387 || TARGET_SSE"
12326 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12328 (define_expand "bordered"
12330 (if_then_else (match_dup 1)
12331 (label_ref (match_operand 0 "" ""))
12333 "TARGET_80387 || TARGET_SSE"
12334 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12336 (define_expand "buneq"
12338 (if_then_else (match_dup 1)
12339 (label_ref (match_operand 0 "" ""))
12341 "TARGET_80387 || TARGET_SSE"
12342 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12344 (define_expand "bunge"
12346 (if_then_else (match_dup 1)
12347 (label_ref (match_operand 0 "" ""))
12349 "TARGET_80387 || TARGET_SSE"
12350 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12352 (define_expand "bungt"
12354 (if_then_else (match_dup 1)
12355 (label_ref (match_operand 0 "" ""))
12357 "TARGET_80387 || TARGET_SSE"
12358 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12360 (define_expand "bunle"
12362 (if_then_else (match_dup 1)
12363 (label_ref (match_operand 0 "" ""))
12365 "TARGET_80387 || TARGET_SSE"
12366 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12368 (define_expand "bunlt"
12370 (if_then_else (match_dup 1)
12371 (label_ref (match_operand 0 "" ""))
12373 "TARGET_80387 || TARGET_SSE"
12374 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12376 (define_expand "bltgt"
12378 (if_then_else (match_dup 1)
12379 (label_ref (match_operand 0 "" ""))
12381 "TARGET_80387 || TARGET_SSE"
12382 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12384 (define_insn "*jcc_1"
12386 (if_then_else (match_operator 1 "ix86_comparison_operator"
12387 [(reg 17) (const_int 0)])
12388 (label_ref (match_operand 0 "" ""))
12392 [(set_attr "type" "ibr")
12393 (set (attr "prefix_0f")
12394 (if_then_else (and (ge (minus (match_dup 0) (pc))
12396 (lt (minus (match_dup 0) (pc))
12401 (define_insn "*jcc_2"
12403 (if_then_else (match_operator 1 "ix86_comparison_operator"
12404 [(reg 17) (const_int 0)])
12406 (label_ref (match_operand 0 "" ""))))]
12409 [(set_attr "type" "ibr")
12410 (set (attr "prefix_0f")
12411 (if_then_else (and (ge (minus (match_dup 0) (pc))
12413 (lt (minus (match_dup 0) (pc))
12418 ;; In general it is not safe to assume too much about CCmode registers,
12419 ;; so simplify-rtx stops when it sees a second one. Under certain
12420 ;; conditions this is safe on x86, so help combine not create
12428 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
12429 [(reg 17) (const_int 0)])
12431 (label_ref (match_operand 1 "" ""))
12435 (if_then_else (match_dup 0)
12436 (label_ref (match_dup 1))
12439 PUT_MODE (operands[0], VOIDmode);
12444 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
12445 [(reg 17) (const_int 0)])
12447 (label_ref (match_operand 1 "" ""))
12451 (if_then_else (match_dup 0)
12452 (label_ref (match_dup 1))
12455 rtx new_op0 = copy_rtx (operands[0]);
12456 operands[0] = new_op0;
12457 PUT_MODE (new_op0, VOIDmode);
12458 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
12459 GET_MODE (XEXP (new_op0, 0))));
12461 /* Make sure that (a) the CCmode we have for the flags is strong
12462 enough for the reversed compare or (b) we have a valid FP compare. */
12463 if (! ix86_comparison_operator (new_op0, VOIDmode))
12467 ;; Define combination compare-and-branch fp compare instructions to use
12468 ;; during early optimization. Splitting the operation apart early makes
12469 ;; for bad code when we want to reverse the operation.
12471 (define_insn "*fp_jcc_1"
12473 (if_then_else (match_operator 0 "comparison_operator"
12474 [(match_operand 1 "register_operand" "f")
12475 (match_operand 2 "register_operand" "f")])
12476 (label_ref (match_operand 3 "" ""))
12478 (clobber (reg:CCFP 18))
12479 (clobber (reg:CCFP 17))]
12480 "TARGET_CMOVE && TARGET_80387
12481 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12482 && FLOAT_MODE_P (GET_MODE (operands[1]))
12483 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12484 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12487 (define_insn "*fp_jcc_1_sse"
12489 (if_then_else (match_operator 0 "comparison_operator"
12490 [(match_operand 1 "register_operand" "f#x,x#f")
12491 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12492 (label_ref (match_operand 3 "" ""))
12494 (clobber (reg:CCFP 18))
12495 (clobber (reg:CCFP 17))]
12497 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12498 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12499 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12502 (define_insn "*fp_jcc_1_sse_only"
12504 (if_then_else (match_operator 0 "comparison_operator"
12505 [(match_operand 1 "register_operand" "x")
12506 (match_operand 2 "nonimmediate_operand" "xm")])
12507 (label_ref (match_operand 3 "" ""))
12509 (clobber (reg:CCFP 18))
12510 (clobber (reg:CCFP 17))]
12511 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12512 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12513 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12516 (define_insn "*fp_jcc_2"
12518 (if_then_else (match_operator 0 "comparison_operator"
12519 [(match_operand 1 "register_operand" "f")
12520 (match_operand 2 "register_operand" "f")])
12522 (label_ref (match_operand 3 "" ""))))
12523 (clobber (reg:CCFP 18))
12524 (clobber (reg:CCFP 17))]
12525 "TARGET_CMOVE && TARGET_80387
12526 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12527 && FLOAT_MODE_P (GET_MODE (operands[1]))
12528 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12529 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12532 (define_insn "*fp_jcc_2_sse"
12534 (if_then_else (match_operator 0 "comparison_operator"
12535 [(match_operand 1 "register_operand" "f#x,x#f")
12536 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12538 (label_ref (match_operand 3 "" ""))))
12539 (clobber (reg:CCFP 18))
12540 (clobber (reg:CCFP 17))]
12542 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12543 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12544 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12547 (define_insn "*fp_jcc_2_sse_only"
12549 (if_then_else (match_operator 0 "comparison_operator"
12550 [(match_operand 1 "register_operand" "x")
12551 (match_operand 2 "nonimmediate_operand" "xm")])
12553 (label_ref (match_operand 3 "" ""))))
12554 (clobber (reg:CCFP 18))
12555 (clobber (reg:CCFP 17))]
12556 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12557 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12558 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12561 (define_insn "*fp_jcc_3"
12563 (if_then_else (match_operator 0 "comparison_operator"
12564 [(match_operand 1 "register_operand" "f")
12565 (match_operand 2 "nonimmediate_operand" "fm")])
12566 (label_ref (match_operand 3 "" ""))
12568 (clobber (reg:CCFP 18))
12569 (clobber (reg:CCFP 17))
12570 (clobber (match_scratch:HI 4 "=a"))]
12572 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12573 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12574 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12575 && SELECT_CC_MODE (GET_CODE (operands[0]),
12576 operands[1], operands[2]) == CCFPmode
12577 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12580 (define_insn "*fp_jcc_4"
12582 (if_then_else (match_operator 0 "comparison_operator"
12583 [(match_operand 1 "register_operand" "f")
12584 (match_operand 2 "nonimmediate_operand" "fm")])
12586 (label_ref (match_operand 3 "" ""))))
12587 (clobber (reg:CCFP 18))
12588 (clobber (reg:CCFP 17))
12589 (clobber (match_scratch:HI 4 "=a"))]
12591 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12592 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12593 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12594 && SELECT_CC_MODE (GET_CODE (operands[0]),
12595 operands[1], operands[2]) == CCFPmode
12596 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12599 (define_insn "*fp_jcc_5"
12601 (if_then_else (match_operator 0 "comparison_operator"
12602 [(match_operand 1 "register_operand" "f")
12603 (match_operand 2 "register_operand" "f")])
12604 (label_ref (match_operand 3 "" ""))
12606 (clobber (reg:CCFP 18))
12607 (clobber (reg:CCFP 17))
12608 (clobber (match_scratch:HI 4 "=a"))]
12610 && FLOAT_MODE_P (GET_MODE (operands[1]))
12611 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12612 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12615 (define_insn "*fp_jcc_6"
12617 (if_then_else (match_operator 0 "comparison_operator"
12618 [(match_operand 1 "register_operand" "f")
12619 (match_operand 2 "register_operand" "f")])
12621 (label_ref (match_operand 3 "" ""))))
12622 (clobber (reg:CCFP 18))
12623 (clobber (reg:CCFP 17))
12624 (clobber (match_scratch:HI 4 "=a"))]
12626 && FLOAT_MODE_P (GET_MODE (operands[1]))
12627 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12628 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12633 (if_then_else (match_operator 0 "comparison_operator"
12634 [(match_operand 1 "register_operand" "")
12635 (match_operand 2 "nonimmediate_operand" "")])
12636 (match_operand 3 "" "")
12637 (match_operand 4 "" "")))
12638 (clobber (reg:CCFP 18))
12639 (clobber (reg:CCFP 17))]
12643 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
12644 operands[3], operands[4], NULL_RTX);
12650 (if_then_else (match_operator 0 "comparison_operator"
12651 [(match_operand 1 "register_operand" "")
12652 (match_operand 2 "nonimmediate_operand" "")])
12653 (match_operand 3 "" "")
12654 (match_operand 4 "" "")))
12655 (clobber (reg:CCFP 18))
12656 (clobber (reg:CCFP 17))
12657 (clobber (match_scratch:HI 5 "=a"))]
12660 (if_then_else (match_dup 6)
12664 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
12665 operands[3], operands[4], operands[5]);
12669 ;; Unconditional and other jump instructions
12671 (define_insn "jump"
12673 (label_ref (match_operand 0 "" "")))]
12676 [(set_attr "type" "ibr")])
12678 (define_expand "indirect_jump"
12679 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
12683 (define_insn "*indirect_jump"
12684 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
12687 [(set_attr "type" "ibr")
12688 (set_attr "length_immediate" "0")])
12690 (define_insn "*indirect_jump_rtx64"
12691 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
12694 [(set_attr "type" "ibr")
12695 (set_attr "length_immediate" "0")])
12697 (define_expand "tablejump"
12698 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
12699 (use (label_ref (match_operand 1 "" "")))])]
12702 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
12703 relative. Convert the relative address to an absolute address. */
12707 enum rtx_code code;
12713 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
12715 else if (HAVE_AS_GOTOFF_IN_DATA)
12719 op1 = pic_offset_table_rtx;
12724 op0 = pic_offset_table_rtx;
12728 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 1,
12733 (define_insn "*tablejump_1"
12734 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
12735 (use (label_ref (match_operand 1 "" "")))]
12738 [(set_attr "type" "ibr")
12739 (set_attr "length_immediate" "0")])
12741 (define_insn "*tablejump_1_rtx64"
12742 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
12743 (use (label_ref (match_operand 1 "" "")))]
12746 [(set_attr "type" "ibr")
12747 (set_attr "length_immediate" "0")])
12749 ;; Loop instruction
12751 ;; This is all complicated by the fact that since this is a jump insn
12752 ;; we must handle our own reloads.
12754 (define_expand "doloop_end"
12755 [(use (match_operand 0 "" "")) ; loop pseudo
12756 (use (match_operand 1 "" "")) ; iterations; zero if unknown
12757 (use (match_operand 2 "" "")) ; max iterations
12758 (use (match_operand 3 "" "")) ; loop level
12759 (use (match_operand 4 "" ""))] ; label
12760 "!TARGET_64BIT && TARGET_USE_LOOP"
12763 /* Only use cloop on innermost loops. */
12764 if (INTVAL (operands[3]) > 1)
12766 if (GET_MODE (operands[0]) != SImode)
12768 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
12773 (define_insn "doloop_end_internal"
12775 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
12777 (label_ref (match_operand 0 "" ""))
12779 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
12780 (plus:SI (match_dup 1)
12782 (clobber (match_scratch:SI 3 "=X,X,r"))
12783 (clobber (reg:CC 17))]
12784 "!TARGET_64BIT && TARGET_USE_LOOP"
12786 if (which_alternative != 0)
12788 if (get_attr_length (insn) == 2)
12789 return "%+loop\t%l0";
12791 return "dec{l}\t%1\;%+jne\t%l0";
12793 [(set_attr "ppro_uops" "many")
12795 (if_then_else (and (eq_attr "alternative" "0")
12796 (and (ge (minus (match_dup 0) (pc))
12798 (lt (minus (match_dup 0) (pc))
12800 (const_string "ibr")
12801 (const_string "multi")))])
12805 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
12807 (match_operand 0 "" "")
12810 (plus:SI (match_dup 1)
12812 (clobber (match_scratch:SI 2 ""))
12813 (clobber (reg:CC 17))]
12814 "!TARGET_64BIT && TARGET_USE_LOOP
12815 && reload_completed
12816 && REGNO (operands[1]) != 2"
12817 [(parallel [(set (reg:CCZ 17)
12818 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
12820 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
12821 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
12828 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
12830 (match_operand 0 "" "")
12832 (set (match_operand:SI 2 "nonimmediate_operand" "")
12833 (plus:SI (match_dup 1)
12835 (clobber (match_scratch:SI 3 ""))
12836 (clobber (reg:CC 17))]
12837 "!TARGET_64BIT && TARGET_USE_LOOP
12838 && reload_completed
12839 && (! REG_P (operands[2])
12840 || ! rtx_equal_p (operands[1], operands[2]))"
12841 [(set (match_dup 3) (match_dup 1))
12842 (parallel [(set (reg:CCZ 17)
12843 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
12845 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
12846 (set (match_dup 2) (match_dup 3))
12847 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
12852 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
12855 [(set (reg 17) (match_operand 0 "" ""))
12856 (set (match_operand:QI 1 "register_operand" "")
12857 (match_operator:QI 2 "ix86_comparison_operator"
12858 [(reg 17) (const_int 0)]))
12859 (set (match_operand 3 "q_regs_operand" "")
12860 (zero_extend (match_dup 1)))]
12861 "(peep2_reg_dead_p (3, operands[1])
12862 || operands_match_p (operands[1], operands[3]))
12863 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
12864 [(set (match_dup 4) (match_dup 0))
12865 (set (strict_low_part (match_dup 5))
12868 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
12869 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
12870 ix86_expand_clear (operands[3]);
12873 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
12876 [(set (reg 17) (match_operand 0 "" ""))
12877 (set (match_operand:QI 1 "register_operand" "")
12878 (match_operator:QI 2 "ix86_comparison_operator"
12879 [(reg 17) (const_int 0)]))
12880 (parallel [(set (match_operand 3 "q_regs_operand" "")
12881 (zero_extend (match_dup 1)))
12882 (clobber (reg:CC 17))])]
12883 "(peep2_reg_dead_p (3, operands[1])
12884 || operands_match_p (operands[1], operands[3]))
12885 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
12886 [(set (match_dup 4) (match_dup 0))
12887 (set (strict_low_part (match_dup 5))
12890 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
12891 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
12892 ix86_expand_clear (operands[3]);
12895 ;; Call instructions.
12897 ;; The predicates normally associated with named expanders are not properly
12898 ;; checked for calls. This is a bug in the generic code, but it isn't that
12899 ;; easy to fix. Ignore it for now and be prepared to fix things up.
12901 ;; Call subroutine returning no value.
12903 (define_expand "call_pop"
12904 [(parallel [(call (match_operand:QI 0 "" "")
12905 (match_operand:SI 1 "" ""))
12907 (plus:SI (reg:SI 7)
12908 (match_operand:SI 3 "" "")))])]
12911 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3]);
12915 (define_insn "*call_pop_0"
12916 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
12917 (match_operand:SI 1 "" ""))
12918 (set (reg:SI 7) (plus:SI (reg:SI 7)
12919 (match_operand:SI 2 "immediate_operand" "")))]
12922 if (SIBLING_CALL_P (insn))
12925 return "call\t%P0";
12927 [(set_attr "type" "call")])
12929 (define_insn "*call_pop_1"
12930 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
12931 (match_operand:SI 1 "" ""))
12932 (set (reg:SI 7) (plus:SI (reg:SI 7)
12933 (match_operand:SI 2 "immediate_operand" "i")))]
12936 if (constant_call_address_operand (operands[0], Pmode))
12938 if (SIBLING_CALL_P (insn))
12941 return "call\t%P0";
12943 if (SIBLING_CALL_P (insn))
12946 return "call\t%A0";
12948 [(set_attr "type" "call")])
12950 (define_expand "call"
12951 [(call (match_operand:QI 0 "" "")
12952 (match_operand 1 "" ""))
12953 (use (match_operand 2 "" ""))]
12956 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL);
12960 (define_insn "*call_0"
12961 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
12962 (match_operand 1 "" ""))]
12965 if (SIBLING_CALL_P (insn))
12968 return "call\t%P0";
12970 [(set_attr "type" "call")])
12972 (define_insn "*call_1"
12973 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
12974 (match_operand 1 "" ""))]
12977 if (constant_call_address_operand (operands[0], QImode))
12979 if (SIBLING_CALL_P (insn))
12982 return "call\t%P0";
12984 if (SIBLING_CALL_P (insn))
12987 return "call\t%A0";
12989 [(set_attr "type" "call")])
12991 (define_insn "*call_1_rex64"
12992 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
12993 (match_operand 1 "" ""))]
12996 if (constant_call_address_operand (operands[0], QImode))
12998 if (SIBLING_CALL_P (insn))
13001 return "call\t%P0";
13003 if (SIBLING_CALL_P (insn))
13006 return "call\t%A0";
13008 [(set_attr "type" "call")])
13010 ;; Call subroutine, returning value in operand 0
13012 (define_expand "call_value_pop"
13013 [(parallel [(set (match_operand 0 "" "")
13014 (call (match_operand:QI 1 "" "")
13015 (match_operand:SI 2 "" "")))
13017 (plus:SI (reg:SI 7)
13018 (match_operand:SI 4 "" "")))])]
13021 ix86_expand_call (operands[0], operands[1], operands[2],
13022 operands[3], operands[4]);
13026 (define_expand "call_value"
13027 [(set (match_operand 0 "" "")
13028 (call (match_operand:QI 1 "" "")
13029 (match_operand:SI 2 "" "")))
13030 (use (match_operand:SI 3 "" ""))]
13031 ;; Operand 2 not used on the i386.
13034 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL);
13038 ;; Call subroutine returning any type.
13040 (define_expand "untyped_call"
13041 [(parallel [(call (match_operand 0 "" "")
13043 (match_operand 1 "" "")
13044 (match_operand 2 "" "")])]
13049 /* In order to give reg-stack an easier job in validating two
13050 coprocessor registers as containing a possible return value,
13051 simply pretend the untyped call returns a complex long double
13054 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13055 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13056 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13059 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13061 rtx set = XVECEXP (operands[2], 0, i);
13062 emit_move_insn (SET_DEST (set), SET_SRC (set));
13065 /* The optimizer does not know that the call sets the function value
13066 registers we stored in the result block. We avoid problems by
13067 claiming that all hard registers are used and clobbered at this
13069 emit_insn (gen_blockage (const0_rtx));
13074 ;; Prologue and epilogue instructions
13076 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13077 ;; all of memory. This blocks insns from being moved across this point.
13079 (define_insn "blockage"
13080 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13083 [(set_attr "length" "0")])
13085 ;; Insn emitted into the body of a function to return from a function.
13086 ;; This is only done if the function's epilogue is known to be simple.
13087 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13089 (define_expand "return"
13091 "ix86_can_use_return_insn_p ()"
13093 if (current_function_pops_args)
13095 rtx popc = GEN_INT (current_function_pops_args);
13096 emit_jump_insn (gen_return_pop_internal (popc));
13101 (define_insn "return_internal"
13105 [(set_attr "length" "1")
13106 (set_attr "length_immediate" "0")
13107 (set_attr "modrm" "0")])
13109 (define_insn "return_pop_internal"
13111 (use (match_operand:SI 0 "const_int_operand" ""))]
13114 [(set_attr "length" "3")
13115 (set_attr "length_immediate" "2")
13116 (set_attr "modrm" "0")])
13118 (define_insn "return_indirect_internal"
13120 (use (match_operand:SI 0 "register_operand" "r"))]
13123 [(set_attr "type" "ibr")
13124 (set_attr "length_immediate" "0")])
13130 [(set_attr "length" "1")
13131 (set_attr "length_immediate" "0")
13132 (set_attr "modrm" "0")
13133 (set_attr "ppro_uops" "one")])
13135 (define_expand "prologue"
13138 "ix86_expand_prologue (); DONE;")
13140 (define_expand "set_got"
13141 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13142 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13143 (clobber (reg:CC 17))])]
13147 (define_insn "*set_got_nopic"
13148 [(set (match_operand:SI 0 "register_operand" "=r")
13149 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13150 (clobber (reg:CC 17))]
13151 "!TARGET_64BIT && !flag_pic"
13152 { return output_set_got (operands[0]); }
13153 [(set_attr "type" "multi")
13154 (set_attr "length" "11")])
13156 (define_insn "*set_got_deep"
13157 [(set (match_operand:SI 0 "register_operand" "=b")
13158 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13159 (clobber (reg:CC 17))]
13160 "!TARGET_64BIT && TARGET_DEEP_BRANCH_PREDICTION"
13161 { return output_set_got (operands[0]); }
13162 [(set_attr "type" "multi")
13163 (set_attr "length" "11")])
13165 (define_insn "*set_got_nodeep"
13166 [(set (match_operand:SI 0 "register_operand" "=r")
13167 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13168 (clobber (reg:CC 17))]
13170 { return output_set_got (operands[0]); }
13171 [(set_attr "type" "multi")
13172 (set_attr "length" "12")])
13174 (define_expand "epilogue"
13177 "ix86_expand_epilogue (1); DONE;")
13179 (define_expand "sibcall_epilogue"
13182 "ix86_expand_epilogue (0); DONE;")
13184 (define_expand "eh_return"
13185 [(use (match_operand 0 "register_operand" ""))
13186 (use (match_operand 1 "register_operand" ""))]
13189 rtx tmp, sa = operands[0], ra = operands[1];
13191 /* Tricky bit: we write the address of the handler to which we will
13192 be returning into someone else's stack frame, one word below the
13193 stack address we wish to restore. */
13194 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13195 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13196 tmp = gen_rtx_MEM (Pmode, tmp);
13197 emit_move_insn (tmp, ra);
13199 if (Pmode == SImode)
13200 emit_insn (gen_eh_return_si (sa));
13202 emit_insn (gen_eh_return_di (sa));
13207 (define_insn_and_split "eh_return_si"
13208 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
13209 UNSPECV_EH_RETURN)]
13214 "ix86_expand_epilogue (2); DONE;")
13216 (define_insn_and_split "eh_return_di"
13217 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
13218 UNSPECV_EH_RETURN)]
13223 "ix86_expand_epilogue (2); DONE;")
13225 (define_insn "leave"
13226 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
13227 (set (reg:SI 6) (mem:SI (reg:SI 6)))
13228 (clobber (mem:BLK (scratch)))]
13231 [(set_attr "length_immediate" "0")
13232 (set_attr "length" "1")
13233 (set_attr "modrm" "0")
13234 (set_attr "modrm" "0")
13235 (set_attr "athlon_decode" "vector")
13236 (set_attr "ppro_uops" "few")])
13238 (define_insn "leave_rex64"
13239 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
13240 (set (reg:DI 6) (mem:DI (reg:DI 6)))
13241 (clobber (mem:BLK (scratch)))]
13244 [(set_attr "length_immediate" "0")
13245 (set_attr "length" "1")
13246 (set_attr "modrm" "0")
13247 (set_attr "modrm" "0")
13248 (set_attr "athlon_decode" "vector")
13249 (set_attr "ppro_uops" "few")])
13251 (define_expand "ffssi2"
13252 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13253 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13256 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13257 rtx in = operands[1];
13261 emit_move_insn (tmp, constm1_rtx);
13262 emit_insn (gen_ffssi_1 (out, in));
13263 emit_insn (gen_rtx_SET (VOIDmode, out,
13264 gen_rtx_IF_THEN_ELSE (SImode,
13265 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13269 emit_insn (gen_addsi3 (out, out, const1_rtx));
13270 emit_move_insn (operands[0], out);
13273 /* Pentium bsf instruction is extremly slow. The following code is
13274 recommended by the Intel Optimizing Manual as a reasonable replacement:
13278 MOV DWORD PTR [TEMP+4],ECX
13281 MOV DWORD PTR [TEMP],EAX
13282 FILD QWORD PTR [TEMP]
13283 FSTP QWORD PTR [TEMP]
13284 WAIT ; WAIT only needed for compatibility with
13285 ; earlier processors
13286 MOV ECX, DWORD PTR [TEMP+4]
13289 TEST EAX,EAX ; clear zero flag
13291 Following piece of code expand ffs to similar beast.
13294 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13296 rtx label = gen_label_rtx ();
13298 rtx mem = assign_386_stack_local (DImode, 0);
13299 rtx fptmp = gen_reg_rtx (DFmode);
13300 split_di (&mem, 1, &lo, &hi);
13302 emit_move_insn (out, const0_rtx);
13304 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label);
13306 emit_move_insn (hi, out);
13307 emit_insn (gen_subsi3 (out, out, in));
13308 emit_insn (gen_andsi3 (out, out, in));
13309 emit_move_insn (lo, out);
13310 emit_insn (gen_floatdidf2 (fptmp,mem));
13311 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13312 emit_move_insn (out, hi);
13313 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13314 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13316 emit_label (label);
13317 LABEL_NUSES (label) = 1;
13319 emit_move_insn (operands[0], out);
13323 emit_move_insn (tmp, const0_rtx);
13324 emit_insn (gen_ffssi_1 (out, in));
13325 emit_insn (gen_rtx_SET (VOIDmode,
13326 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13327 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13329 emit_insn (gen_negsi2 (tmp, tmp));
13330 emit_insn (gen_iorsi3 (out, out, tmp));
13331 emit_insn (gen_addsi3 (out, out, const1_rtx));
13332 emit_move_insn (operands[0], out);
13337 (define_insn "ffssi_1"
13339 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13341 (set (match_operand:SI 0 "register_operand" "=r")
13342 (unspec:SI [(match_dup 1)] UNSPEC_BSF))]
13344 "bsf{l}\t{%1, %0|%0, %1}"
13345 [(set_attr "prefix_0f" "1")
13346 (set_attr "ppro_uops" "few")])
13348 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13349 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13351 ;; Thread-local storage patterns for ELF.
13353 ;; Note that these code sequences must appear exactly as shown
13354 ;; in order to allow linker relaxation.
13356 (define_insn "*tls_global_dynamic_gnu"
13357 [(set (match_operand:SI 0 "register_operand" "=a")
13358 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13359 (match_operand:SI 2 "tls_symbolic_operand" "")
13360 (match_operand:SI 3 "call_insn_operand" "")]
13362 (clobber (match_scratch:SI 4 "=d"))
13363 (clobber (match_scratch:SI 5 "=c"))
13364 (clobber (reg:CC 17))]
13366 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
13367 [(set_attr "type" "multi")
13368 (set_attr "length" "12")])
13370 (define_insn "*tls_global_dynamic_sun"
13371 [(set (match_operand:SI 0 "register_operand" "=a")
13372 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13373 (match_operand:SI 2 "tls_symbolic_operand" "")
13374 (match_operand:SI 3 "call_insn_operand" "")]
13376 (clobber (match_scratch:SI 4 "=d"))
13377 (clobber (match_scratch:SI 5 "=c"))
13378 (clobber (reg:CC 17))]
13380 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
13381 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
13382 [(set_attr "type" "multi")
13383 (set_attr "length" "14")])
13385 (define_expand "tls_global_dynamic"
13386 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13389 (match_operand:SI 1 "tls_symbolic_operand" "")
13392 (clobber (match_scratch:SI 4 ""))
13393 (clobber (match_scratch:SI 5 ""))
13394 (clobber (reg:CC 17))])]
13399 operands[2] = pic_offset_table_rtx;
13400 operands[3] = ix86_tls_get_addr ();
13403 (define_insn "*tls_local_dynamic_base_gnu"
13404 [(set (match_operand:SI 0 "register_operand" "=a")
13405 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13406 (match_operand:SI 2 "call_insn_operand" "")]
13407 UNSPEC_TLS_LD_BASE))
13408 (clobber (match_scratch:SI 3 "=d"))
13409 (clobber (match_scratch:SI 4 "=c"))
13410 (clobber (reg:CC 17))]
13412 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
13413 [(set_attr "type" "multi")
13414 (set_attr "length" "11")])
13416 (define_insn "*tls_local_dynamic_base_sun"
13417 [(set (match_operand:SI 0 "register_operand" "=a")
13418 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13419 (match_operand:SI 2 "call_insn_operand" "")]
13420 UNSPEC_TLS_LD_BASE))
13421 (clobber (match_scratch:SI 3 "=d"))
13422 (clobber (match_scratch:SI 4 "=c"))
13423 (clobber (reg:CC 17))]
13425 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
13426 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
13427 [(set_attr "type" "multi")
13428 (set_attr "length" "13")])
13430 (define_expand "tls_local_dynamic_base"
13431 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13432 (unspec:SI [(match_dup 1) (match_dup 2)]
13433 UNSPEC_TLS_LD_BASE))
13434 (clobber (match_scratch:SI 3 ""))
13435 (clobber (match_scratch:SI 4 ""))
13436 (clobber (reg:CC 17))])]
13441 operands[1] = pic_offset_table_rtx;
13442 operands[2] = ix86_tls_get_addr ();
13445 ;; Local dynamic of a single variable is a lose. Show combine how
13446 ;; to convert that back to global dynamic.
13448 (define_insn_and_split "*tls_local_dynamic_once"
13449 [(set (match_operand:SI 0 "register_operand" "=a")
13450 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13451 (match_operand:SI 2 "call_insn_operand" "")]
13452 UNSPEC_TLS_LD_BASE)
13453 (const:SI (unspec:SI
13454 [(match_operand:SI 3 "tls_symbolic_operand" "")]
13456 (clobber (match_scratch:SI 4 "=d"))
13457 (clobber (match_scratch:SI 5 "=c"))
13458 (clobber (reg:CC 17))]
13462 [(parallel [(set (match_dup 0)
13463 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
13465 (clobber (match_dup 4))
13466 (clobber (match_dup 5))
13467 (clobber (reg:CC 17))])]
13470 ;; These patterns match the binary 387 instructions for addM3, subM3,
13471 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13472 ;; SFmode. The first is the normal insn, the second the same insn but
13473 ;; with one operand a conversion, and the third the same insn but with
13474 ;; the other operand a conversion. The conversion may be SFmode or
13475 ;; SImode if the target mode DFmode, but only SImode if the target mode
13478 ;; Gcc is slightly more smart about handling normal two address instructions
13479 ;; so use special patterns for add and mull.
13480 (define_insn "*fop_sf_comm_nosse"
13481 [(set (match_operand:SF 0 "register_operand" "=f")
13482 (match_operator:SF 3 "binary_fp_operator"
13483 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13484 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
13485 "TARGET_80387 && !TARGET_SSE_MATH
13486 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13487 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13488 "* return output_387_binary_op (insn, operands);"
13489 [(set (attr "type")
13490 (if_then_else (match_operand:SF 3 "mult_operator" "")
13491 (const_string "fmul")
13492 (const_string "fop")))
13493 (set_attr "mode" "SF")])
13495 (define_insn "*fop_sf_comm"
13496 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13497 (match_operator:SF 3 "binary_fp_operator"
13498 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
13499 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13500 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13501 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13502 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13503 "* return output_387_binary_op (insn, operands);"
13504 [(set (attr "type")
13505 (if_then_else (eq_attr "alternative" "1")
13506 (if_then_else (match_operand:SF 3 "mult_operator" "")
13507 (const_string "ssemul")
13508 (const_string "sseadd"))
13509 (if_then_else (match_operand:SF 3 "mult_operator" "")
13510 (const_string "fmul")
13511 (const_string "fop"))))
13512 (set_attr "mode" "SF")])
13514 (define_insn "*fop_sf_comm_sse"
13515 [(set (match_operand:SF 0 "register_operand" "=x")
13516 (match_operator:SF 3 "binary_fp_operator"
13517 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13518 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13519 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13520 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13521 "* return output_387_binary_op (insn, operands);"
13522 [(set (attr "type")
13523 (if_then_else (match_operand:SF 3 "mult_operator" "")
13524 (const_string "ssemul")
13525 (const_string "sseadd")))
13526 (set_attr "mode" "SF")])
13528 (define_insn "*fop_df_comm_nosse"
13529 [(set (match_operand:DF 0 "register_operand" "=f")
13530 (match_operator:DF 3 "binary_fp_operator"
13531 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13532 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
13533 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13534 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13535 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13536 "* return output_387_binary_op (insn, operands);"
13537 [(set (attr "type")
13538 (if_then_else (match_operand:SF 3 "mult_operator" "")
13539 (const_string "fmul")
13540 (const_string "fop")))
13541 (set_attr "mode" "DF")])
13543 (define_insn "*fop_df_comm"
13544 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13545 (match_operator:DF 3 "binary_fp_operator"
13546 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
13547 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13548 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
13549 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13550 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13551 "* return output_387_binary_op (insn, operands);"
13552 [(set (attr "type")
13553 (if_then_else (eq_attr "alternative" "1")
13554 (if_then_else (match_operand:SF 3 "mult_operator" "")
13555 (const_string "ssemul")
13556 (const_string "sseadd"))
13557 (if_then_else (match_operand:SF 3 "mult_operator" "")
13558 (const_string "fmul")
13559 (const_string "fop"))))
13560 (set_attr "mode" "DF")])
13562 (define_insn "*fop_df_comm_sse"
13563 [(set (match_operand:DF 0 "register_operand" "=Y")
13564 (match_operator:DF 3 "binary_fp_operator"
13565 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13566 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13567 "TARGET_SSE2 && TARGET_SSE_MATH
13568 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13569 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13570 "* return output_387_binary_op (insn, operands);"
13571 [(set (attr "type")
13572 (if_then_else (match_operand:SF 3 "mult_operator" "")
13573 (const_string "ssemul")
13574 (const_string "sseadd")))
13575 (set_attr "mode" "DF")])
13577 (define_insn "*fop_xf_comm"
13578 [(set (match_operand:XF 0 "register_operand" "=f")
13579 (match_operator:XF 3 "binary_fp_operator"
13580 [(match_operand:XF 1 "register_operand" "%0")
13581 (match_operand:XF 2 "register_operand" "f")]))]
13582 "!TARGET_64BIT && TARGET_80387
13583 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13584 "* return output_387_binary_op (insn, operands);"
13585 [(set (attr "type")
13586 (if_then_else (match_operand:XF 3 "mult_operator" "")
13587 (const_string "fmul")
13588 (const_string "fop")))
13589 (set_attr "mode" "XF")])
13591 (define_insn "*fop_tf_comm"
13592 [(set (match_operand:TF 0 "register_operand" "=f")
13593 (match_operator:TF 3 "binary_fp_operator"
13594 [(match_operand:TF 1 "register_operand" "%0")
13595 (match_operand:TF 2 "register_operand" "f")]))]
13596 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13597 "* return output_387_binary_op (insn, operands);"
13598 [(set (attr "type")
13599 (if_then_else (match_operand:TF 3 "mult_operator" "")
13600 (const_string "fmul")
13601 (const_string "fop")))
13602 (set_attr "mode" "XF")])
13604 (define_insn "*fop_sf_1_nosse"
13605 [(set (match_operand:SF 0 "register_operand" "=f,f")
13606 (match_operator:SF 3 "binary_fp_operator"
13607 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
13608 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
13609 "TARGET_80387 && !TARGET_SSE_MATH
13610 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13611 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13612 "* return output_387_binary_op (insn, operands);"
13613 [(set (attr "type")
13614 (cond [(match_operand:SF 3 "mult_operator" "")
13615 (const_string "fmul")
13616 (match_operand:SF 3 "div_operator" "")
13617 (const_string "fdiv")
13619 (const_string "fop")))
13620 (set_attr "mode" "SF")])
13622 (define_insn "*fop_sf_1"
13623 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
13624 (match_operator:SF 3 "binary_fp_operator"
13625 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
13626 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
13627 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13628 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13629 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13630 "* return output_387_binary_op (insn, operands);"
13631 [(set (attr "type")
13632 (cond [(and (eq_attr "alternative" "2")
13633 (match_operand:SF 3 "mult_operator" ""))
13634 (const_string "ssemul")
13635 (and (eq_attr "alternative" "2")
13636 (match_operand:SF 3 "div_operator" ""))
13637 (const_string "ssediv")
13638 (eq_attr "alternative" "2")
13639 (const_string "sseadd")
13640 (match_operand:SF 3 "mult_operator" "")
13641 (const_string "fmul")
13642 (match_operand:SF 3 "div_operator" "")
13643 (const_string "fdiv")
13645 (const_string "fop")))
13646 (set_attr "mode" "SF")])
13648 (define_insn "*fop_sf_1_sse"
13649 [(set (match_operand:SF 0 "register_operand" "=x")
13650 (match_operator:SF 3 "binary_fp_operator"
13651 [(match_operand:SF 1 "register_operand" "0")
13652 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13654 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13655 "* return output_387_binary_op (insn, operands);"
13656 [(set (attr "type")
13657 (cond [(match_operand:SF 3 "mult_operator" "")
13658 (const_string "ssemul")
13659 (match_operand:SF 3 "div_operator" "")
13660 (const_string "ssediv")
13662 (const_string "sseadd")))
13663 (set_attr "mode" "SF")])
13665 ;; ??? Add SSE splitters for these!
13666 (define_insn "*fop_sf_2"
13667 [(set (match_operand:SF 0 "register_operand" "=f,f")
13668 (match_operator:SF 3 "binary_fp_operator"
13669 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13670 (match_operand:SF 2 "register_operand" "0,0")]))]
13671 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
13672 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13673 [(set (attr "type")
13674 (cond [(match_operand:SF 3 "mult_operator" "")
13675 (const_string "fmul")
13676 (match_operand:SF 3 "div_operator" "")
13677 (const_string "fdiv")
13679 (const_string "fop")))
13680 (set_attr "fp_int_src" "true")
13681 (set_attr "ppro_uops" "many")
13682 (set_attr "mode" "SI")])
13684 (define_insn "*fop_sf_3"
13685 [(set (match_operand:SF 0 "register_operand" "=f,f")
13686 (match_operator:SF 3 "binary_fp_operator"
13687 [(match_operand:SF 1 "register_operand" "0,0")
13688 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13689 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
13690 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13691 [(set (attr "type")
13692 (cond [(match_operand:SF 3 "mult_operator" "")
13693 (const_string "fmul")
13694 (match_operand:SF 3 "div_operator" "")
13695 (const_string "fdiv")
13697 (const_string "fop")))
13698 (set_attr "fp_int_src" "true")
13699 (set_attr "ppro_uops" "many")
13700 (set_attr "mode" "SI")])
13702 (define_insn "*fop_df_1_nosse"
13703 [(set (match_operand:DF 0 "register_operand" "=f,f")
13704 (match_operator:DF 3 "binary_fp_operator"
13705 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
13706 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
13707 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13708 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13709 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13710 "* return output_387_binary_op (insn, operands);"
13711 [(set (attr "type")
13712 (cond [(match_operand:DF 3 "mult_operator" "")
13713 (const_string "fmul")
13714 (match_operand:DF 3 "div_operator" "")
13715 (const_string "fdiv")
13717 (const_string "fop")))
13718 (set_attr "mode" "DF")])
13721 (define_insn "*fop_df_1"
13722 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
13723 (match_operator:DF 3 "binary_fp_operator"
13724 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
13725 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
13726 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13727 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13728 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13729 "* return output_387_binary_op (insn, operands);"
13730 [(set (attr "type")
13731 (cond [(and (eq_attr "alternative" "2")
13732 (match_operand:SF 3 "mult_operator" ""))
13733 (const_string "ssemul")
13734 (and (eq_attr "alternative" "2")
13735 (match_operand:SF 3 "div_operator" ""))
13736 (const_string "ssediv")
13737 (eq_attr "alternative" "2")
13738 (const_string "sseadd")
13739 (match_operand:DF 3 "mult_operator" "")
13740 (const_string "fmul")
13741 (match_operand:DF 3 "div_operator" "")
13742 (const_string "fdiv")
13744 (const_string "fop")))
13745 (set_attr "mode" "DF")])
13747 (define_insn "*fop_df_1_sse"
13748 [(set (match_operand:DF 0 "register_operand" "=Y")
13749 (match_operator:DF 3 "binary_fp_operator"
13750 [(match_operand:DF 1 "register_operand" "0")
13751 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13752 "TARGET_SSE2 && TARGET_SSE_MATH
13753 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13754 "* return output_387_binary_op (insn, operands);"
13755 [(set_attr "mode" "DF")
13757 (cond [(match_operand:SF 3 "mult_operator" "")
13758 (const_string "ssemul")
13759 (match_operand:SF 3 "div_operator" "")
13760 (const_string "ssediv")
13762 (const_string "sseadd")))])
13764 ;; ??? Add SSE splitters for these!
13765 (define_insn "*fop_df_2"
13766 [(set (match_operand:DF 0 "register_operand" "=f,f")
13767 (match_operator:DF 3 "binary_fp_operator"
13768 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13769 (match_operand:DF 2 "register_operand" "0,0")]))]
13770 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
13771 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13772 [(set (attr "type")
13773 (cond [(match_operand:DF 3 "mult_operator" "")
13774 (const_string "fmul")
13775 (match_operand:DF 3 "div_operator" "")
13776 (const_string "fdiv")
13778 (const_string "fop")))
13779 (set_attr "fp_int_src" "true")
13780 (set_attr "ppro_uops" "many")
13781 (set_attr "mode" "SI")])
13783 (define_insn "*fop_df_3"
13784 [(set (match_operand:DF 0 "register_operand" "=f,f")
13785 (match_operator:DF 3 "binary_fp_operator"
13786 [(match_operand:DF 1 "register_operand" "0,0")
13787 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13788 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
13789 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13790 [(set (attr "type")
13791 (cond [(match_operand:DF 3 "mult_operator" "")
13792 (const_string "fmul")
13793 (match_operand:DF 3 "div_operator" "")
13794 (const_string "fdiv")
13796 (const_string "fop")))
13797 (set_attr "fp_int_src" "true")
13798 (set_attr "ppro_uops" "many")
13799 (set_attr "mode" "SI")])
13801 (define_insn "*fop_df_4"
13802 [(set (match_operand:DF 0 "register_operand" "=f,f")
13803 (match_operator:DF 3 "binary_fp_operator"
13804 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13805 (match_operand:DF 2 "register_operand" "0,f")]))]
13806 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13807 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13808 "* return output_387_binary_op (insn, operands);"
13809 [(set (attr "type")
13810 (cond [(match_operand:DF 3 "mult_operator" "")
13811 (const_string "fmul")
13812 (match_operand:DF 3 "div_operator" "")
13813 (const_string "fdiv")
13815 (const_string "fop")))
13816 (set_attr "mode" "SF")])
13818 (define_insn "*fop_df_5"
13819 [(set (match_operand:DF 0 "register_operand" "=f,f")
13820 (match_operator:DF 3 "binary_fp_operator"
13821 [(match_operand:DF 1 "register_operand" "0,f")
13823 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13824 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
13825 "* return output_387_binary_op (insn, operands);"
13826 [(set (attr "type")
13827 (cond [(match_operand:DF 3 "mult_operator" "")
13828 (const_string "fmul")
13829 (match_operand:DF 3 "div_operator" "")
13830 (const_string "fdiv")
13832 (const_string "fop")))
13833 (set_attr "mode" "SF")])
13835 (define_insn "*fop_xf_1"
13836 [(set (match_operand:XF 0 "register_operand" "=f,f")
13837 (match_operator:XF 3 "binary_fp_operator"
13838 [(match_operand:XF 1 "register_operand" "0,f")
13839 (match_operand:XF 2 "register_operand" "f,0")]))]
13840 "!TARGET_64BIT && TARGET_80387
13841 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13842 "* return output_387_binary_op (insn, operands);"
13843 [(set (attr "type")
13844 (cond [(match_operand:XF 3 "mult_operator" "")
13845 (const_string "fmul")
13846 (match_operand:XF 3 "div_operator" "")
13847 (const_string "fdiv")
13849 (const_string "fop")))
13850 (set_attr "mode" "XF")])
13852 (define_insn "*fop_tf_1"
13853 [(set (match_operand:TF 0 "register_operand" "=f,f")
13854 (match_operator:TF 3 "binary_fp_operator"
13855 [(match_operand:TF 1 "register_operand" "0,f")
13856 (match_operand:TF 2 "register_operand" "f,0")]))]
13858 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13859 "* return output_387_binary_op (insn, operands);"
13860 [(set (attr "type")
13861 (cond [(match_operand:TF 3 "mult_operator" "")
13862 (const_string "fmul")
13863 (match_operand:TF 3 "div_operator" "")
13864 (const_string "fdiv")
13866 (const_string "fop")))
13867 (set_attr "mode" "XF")])
13869 (define_insn "*fop_xf_2"
13870 [(set (match_operand:XF 0 "register_operand" "=f,f")
13871 (match_operator:XF 3 "binary_fp_operator"
13872 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13873 (match_operand:XF 2 "register_operand" "0,0")]))]
13874 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
13875 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13876 [(set (attr "type")
13877 (cond [(match_operand:XF 3 "mult_operator" "")
13878 (const_string "fmul")
13879 (match_operand:XF 3 "div_operator" "")
13880 (const_string "fdiv")
13882 (const_string "fop")))
13883 (set_attr "fp_int_src" "true")
13884 (set_attr "mode" "SI")
13885 (set_attr "ppro_uops" "many")])
13887 (define_insn "*fop_tf_2"
13888 [(set (match_operand:TF 0 "register_operand" "=f,f")
13889 (match_operator:TF 3 "binary_fp_operator"
13890 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13891 (match_operand:TF 2 "register_operand" "0,0")]))]
13892 "TARGET_80387 && TARGET_USE_FIOP"
13893 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13894 [(set (attr "type")
13895 (cond [(match_operand:TF 3 "mult_operator" "")
13896 (const_string "fmul")
13897 (match_operand:TF 3 "div_operator" "")
13898 (const_string "fdiv")
13900 (const_string "fop")))
13901 (set_attr "fp_int_src" "true")
13902 (set_attr "mode" "SI")
13903 (set_attr "ppro_uops" "many")])
13905 (define_insn "*fop_xf_3"
13906 [(set (match_operand:XF 0 "register_operand" "=f,f")
13907 (match_operator:XF 3 "binary_fp_operator"
13908 [(match_operand:XF 1 "register_operand" "0,0")
13909 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13910 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
13911 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13912 [(set (attr "type")
13913 (cond [(match_operand:XF 3 "mult_operator" "")
13914 (const_string "fmul")
13915 (match_operand:XF 3 "div_operator" "")
13916 (const_string "fdiv")
13918 (const_string "fop")))
13919 (set_attr "fp_int_src" "true")
13920 (set_attr "mode" "SI")
13921 (set_attr "ppro_uops" "many")])
13923 (define_insn "*fop_tf_3"
13924 [(set (match_operand:TF 0 "register_operand" "=f,f")
13925 (match_operator:TF 3 "binary_fp_operator"
13926 [(match_operand:TF 1 "register_operand" "0,0")
13927 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13928 "TARGET_80387 && TARGET_USE_FIOP"
13929 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13930 [(set (attr "type")
13931 (cond [(match_operand:TF 3 "mult_operator" "")
13932 (const_string "fmul")
13933 (match_operand:TF 3 "div_operator" "")
13934 (const_string "fdiv")
13936 (const_string "fop")))
13937 (set_attr "fp_int_src" "true")
13938 (set_attr "mode" "SI")
13939 (set_attr "ppro_uops" "many")])
13941 (define_insn "*fop_xf_4"
13942 [(set (match_operand:XF 0 "register_operand" "=f,f")
13943 (match_operator:XF 3 "binary_fp_operator"
13944 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13945 (match_operand:XF 2 "register_operand" "0,f")]))]
13946 "!TARGET_64BIT && TARGET_80387"
13947 "* return output_387_binary_op (insn, operands);"
13948 [(set (attr "type")
13949 (cond [(match_operand:XF 3 "mult_operator" "")
13950 (const_string "fmul")
13951 (match_operand:XF 3 "div_operator" "")
13952 (const_string "fdiv")
13954 (const_string "fop")))
13955 (set_attr "mode" "SF")])
13957 (define_insn "*fop_tf_4"
13958 [(set (match_operand:TF 0 "register_operand" "=f,f")
13959 (match_operator:TF 3 "binary_fp_operator"
13960 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13961 (match_operand:TF 2 "register_operand" "0,f")]))]
13963 "* return output_387_binary_op (insn, operands);"
13964 [(set (attr "type")
13965 (cond [(match_operand:TF 3 "mult_operator" "")
13966 (const_string "fmul")
13967 (match_operand:TF 3 "div_operator" "")
13968 (const_string "fdiv")
13970 (const_string "fop")))
13971 (set_attr "mode" "SF")])
13973 (define_insn "*fop_xf_5"
13974 [(set (match_operand:XF 0 "register_operand" "=f,f")
13975 (match_operator:XF 3 "binary_fp_operator"
13976 [(match_operand:XF 1 "register_operand" "0,f")
13978 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13979 "!TARGET_64BIT && TARGET_80387"
13980 "* return output_387_binary_op (insn, operands);"
13981 [(set (attr "type")
13982 (cond [(match_operand:XF 3 "mult_operator" "")
13983 (const_string "fmul")
13984 (match_operand:XF 3 "div_operator" "")
13985 (const_string "fdiv")
13987 (const_string "fop")))
13988 (set_attr "mode" "SF")])
13990 (define_insn "*fop_tf_5"
13991 [(set (match_operand:TF 0 "register_operand" "=f,f")
13992 (match_operator:TF 3 "binary_fp_operator"
13993 [(match_operand:TF 1 "register_operand" "0,f")
13995 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13997 "* return output_387_binary_op (insn, operands);"
13998 [(set (attr "type")
13999 (cond [(match_operand:TF 3 "mult_operator" "")
14000 (const_string "fmul")
14001 (match_operand:TF 3 "div_operator" "")
14002 (const_string "fdiv")
14004 (const_string "fop")))
14005 (set_attr "mode" "SF")])
14007 (define_insn "*fop_xf_6"
14008 [(set (match_operand:XF 0 "register_operand" "=f,f")
14009 (match_operator:XF 3 "binary_fp_operator"
14010 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14011 (match_operand:XF 2 "register_operand" "0,f")]))]
14012 "!TARGET_64BIT && TARGET_80387"
14013 "* return output_387_binary_op (insn, operands);"
14014 [(set (attr "type")
14015 (cond [(match_operand:XF 3 "mult_operator" "")
14016 (const_string "fmul")
14017 (match_operand:XF 3 "div_operator" "")
14018 (const_string "fdiv")
14020 (const_string "fop")))
14021 (set_attr "mode" "DF")])
14023 (define_insn "*fop_tf_6"
14024 [(set (match_operand:TF 0 "register_operand" "=f,f")
14025 (match_operator:TF 3 "binary_fp_operator"
14026 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14027 (match_operand:TF 2 "register_operand" "0,f")]))]
14029 "* return output_387_binary_op (insn, operands);"
14030 [(set (attr "type")
14031 (cond [(match_operand:TF 3 "mult_operator" "")
14032 (const_string "fmul")
14033 (match_operand:TF 3 "div_operator" "")
14034 (const_string "fdiv")
14036 (const_string "fop")))
14037 (set_attr "mode" "DF")])
14039 (define_insn "*fop_xf_7"
14040 [(set (match_operand:XF 0 "register_operand" "=f,f")
14041 (match_operator:XF 3 "binary_fp_operator"
14042 [(match_operand:XF 1 "register_operand" "0,f")
14044 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14045 "!TARGET_64BIT && TARGET_80387"
14046 "* return output_387_binary_op (insn, operands);"
14047 [(set (attr "type")
14048 (cond [(match_operand:XF 3 "mult_operator" "")
14049 (const_string "fmul")
14050 (match_operand:XF 3 "div_operator" "")
14051 (const_string "fdiv")
14053 (const_string "fop")))
14054 (set_attr "mode" "DF")])
14056 (define_insn "*fop_tf_7"
14057 [(set (match_operand:TF 0 "register_operand" "=f,f")
14058 (match_operator:TF 3 "binary_fp_operator"
14059 [(match_operand:TF 1 "register_operand" "0,f")
14061 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14063 "* return output_387_binary_op (insn, operands);"
14064 [(set (attr "type")
14065 (cond [(match_operand:TF 3 "mult_operator" "")
14066 (const_string "fmul")
14067 (match_operand:TF 3 "div_operator" "")
14068 (const_string "fdiv")
14070 (const_string "fop")))
14071 (set_attr "mode" "DF")])
14074 [(set (match_operand 0 "register_operand" "")
14075 (match_operator 3 "binary_fp_operator"
14076 [(float (match_operand:SI 1 "register_operand" ""))
14077 (match_operand 2 "register_operand" "")]))]
14078 "TARGET_80387 && reload_completed
14079 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14082 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14083 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14084 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14085 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14086 GET_MODE (operands[3]),
14089 ix86_free_from_memory (GET_MODE (operands[1]));
14094 [(set (match_operand 0 "register_operand" "")
14095 (match_operator 3 "binary_fp_operator"
14096 [(match_operand 1 "register_operand" "")
14097 (float (match_operand:SI 2 "register_operand" ""))]))]
14098 "TARGET_80387 && reload_completed
14099 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14102 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14103 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14104 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14105 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14106 GET_MODE (operands[3]),
14109 ix86_free_from_memory (GET_MODE (operands[2]));
14113 ;; FPU special functions.
14115 (define_expand "sqrtsf2"
14116 [(set (match_operand:SF 0 "register_operand" "")
14117 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14118 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
14120 if (!TARGET_SSE_MATH)
14121 operands[1] = force_reg (SFmode, operands[1]);
14124 (define_insn "sqrtsf2_1"
14125 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14126 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14127 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14128 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14131 sqrtss\t{%1, %0|%0, %1}"
14132 [(set_attr "type" "fpspc,sse")
14133 (set_attr "mode" "SF,SF")
14134 (set_attr "athlon_decode" "direct,*")])
14136 (define_insn "sqrtsf2_1_sse_only"
14137 [(set (match_operand:SF 0 "register_operand" "=x")
14138 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14139 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14140 "sqrtss\t{%1, %0|%0, %1}"
14141 [(set_attr "type" "sse")
14142 (set_attr "mode" "SF")
14143 (set_attr "athlon_decode" "*")])
14145 (define_insn "sqrtsf2_i387"
14146 [(set (match_operand:SF 0 "register_operand" "=f")
14147 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14148 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14149 && !TARGET_SSE_MATH"
14151 [(set_attr "type" "fpspc")
14152 (set_attr "mode" "SF")
14153 (set_attr "athlon_decode" "direct")])
14155 (define_expand "sqrtdf2"
14156 [(set (match_operand:DF 0 "register_operand" "")
14157 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14158 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
14159 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14161 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14162 operands[1] = force_reg (DFmode, operands[1]);
14165 (define_insn "sqrtdf2_1"
14166 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14167 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14168 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14169 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14172 sqrtsd\t{%1, %0|%0, %1}"
14173 [(set_attr "type" "fpspc,sse")
14174 (set_attr "mode" "DF,DF")
14175 (set_attr "athlon_decode" "direct,*")])
14177 (define_insn "sqrtdf2_1_sse_only"
14178 [(set (match_operand:DF 0 "register_operand" "=Y")
14179 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14180 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14181 "sqrtsd\t{%1, %0|%0, %1}"
14182 [(set_attr "type" "sse")
14183 (set_attr "mode" "DF")
14184 (set_attr "athlon_decode" "*")])
14186 (define_insn "sqrtdf2_i387"
14187 [(set (match_operand:DF 0 "register_operand" "=f")
14188 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14189 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14190 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14192 [(set_attr "type" "fpspc")
14193 (set_attr "mode" "DF")
14194 (set_attr "athlon_decode" "direct")])
14196 (define_insn "*sqrtextendsfdf2"
14197 [(set (match_operand:DF 0 "register_operand" "=f")
14198 (sqrt:DF (float_extend:DF
14199 (match_operand:SF 1 "register_operand" "0"))))]
14200 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14201 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14203 [(set_attr "type" "fpspc")
14204 (set_attr "mode" "DF")
14205 (set_attr "athlon_decode" "direct")])
14207 (define_insn "sqrtxf2"
14208 [(set (match_operand:XF 0 "register_operand" "=f")
14209 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14210 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14211 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14213 [(set_attr "type" "fpspc")
14214 (set_attr "mode" "XF")
14215 (set_attr "athlon_decode" "direct")])
14217 (define_insn "sqrttf2"
14218 [(set (match_operand:TF 0 "register_operand" "=f")
14219 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14220 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14221 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14223 [(set_attr "type" "fpspc")
14224 (set_attr "mode" "XF")
14225 (set_attr "athlon_decode" "direct")])
14227 (define_insn "*sqrtextenddfxf2"
14228 [(set (match_operand:XF 0 "register_operand" "=f")
14229 (sqrt:XF (float_extend:XF
14230 (match_operand:DF 1 "register_operand" "0"))))]
14231 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14233 [(set_attr "type" "fpspc")
14234 (set_attr "mode" "XF")
14235 (set_attr "athlon_decode" "direct")])
14237 (define_insn "*sqrtextenddftf2"
14238 [(set (match_operand:TF 0 "register_operand" "=f")
14239 (sqrt:TF (float_extend:TF
14240 (match_operand:DF 1 "register_operand" "0"))))]
14241 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14243 [(set_attr "type" "fpspc")
14244 (set_attr "mode" "XF")
14245 (set_attr "athlon_decode" "direct")])
14247 (define_insn "*sqrtextendsfxf2"
14248 [(set (match_operand:XF 0 "register_operand" "=f")
14249 (sqrt:XF (float_extend:XF
14250 (match_operand:SF 1 "register_operand" "0"))))]
14251 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14253 [(set_attr "type" "fpspc")
14254 (set_attr "mode" "XF")
14255 (set_attr "athlon_decode" "direct")])
14257 (define_insn "*sqrtextendsftf2"
14258 [(set (match_operand:TF 0 "register_operand" "=f")
14259 (sqrt:TF (float_extend:TF
14260 (match_operand:SF 1 "register_operand" "0"))))]
14261 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14263 [(set_attr "type" "fpspc")
14264 (set_attr "mode" "XF")
14265 (set_attr "athlon_decode" "direct")])
14267 (define_insn "sindf2"
14268 [(set (match_operand:DF 0 "register_operand" "=f")
14269 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14270 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14271 && flag_unsafe_math_optimizations"
14273 [(set_attr "type" "fpspc")
14274 (set_attr "mode" "DF")])
14276 (define_insn "sinsf2"
14277 [(set (match_operand:SF 0 "register_operand" "=f")
14278 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14279 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14280 && flag_unsafe_math_optimizations"
14282 [(set_attr "type" "fpspc")
14283 (set_attr "mode" "SF")])
14285 (define_insn "*sinextendsfdf2"
14286 [(set (match_operand:DF 0 "register_operand" "=f")
14287 (unspec:DF [(float_extend:DF
14288 (match_operand:SF 1 "register_operand" "0"))]
14290 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14291 && flag_unsafe_math_optimizations"
14293 [(set_attr "type" "fpspc")
14294 (set_attr "mode" "DF")])
14296 (define_insn "sinxf2"
14297 [(set (match_operand:XF 0 "register_operand" "=f")
14298 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14299 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14300 && flag_unsafe_math_optimizations"
14302 [(set_attr "type" "fpspc")
14303 (set_attr "mode" "XF")])
14305 (define_insn "sintf2"
14306 [(set (match_operand:TF 0 "register_operand" "=f")
14307 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
14308 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14309 && flag_unsafe_math_optimizations"
14311 [(set_attr "type" "fpspc")
14312 (set_attr "mode" "XF")])
14314 (define_insn "cosdf2"
14315 [(set (match_operand:DF 0 "register_operand" "=f")
14316 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14317 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14318 && flag_unsafe_math_optimizations"
14320 [(set_attr "type" "fpspc")
14321 (set_attr "mode" "DF")])
14323 (define_insn "cossf2"
14324 [(set (match_operand:SF 0 "register_operand" "=f")
14325 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14326 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14327 && flag_unsafe_math_optimizations"
14329 [(set_attr "type" "fpspc")
14330 (set_attr "mode" "SF")])
14332 (define_insn "*cosextendsfdf2"
14333 [(set (match_operand:DF 0 "register_operand" "=f")
14334 (unspec:DF [(float_extend:DF
14335 (match_operand:SF 1 "register_operand" "0"))]
14337 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14338 && flag_unsafe_math_optimizations"
14340 [(set_attr "type" "fpspc")
14341 (set_attr "mode" "DF")])
14343 (define_insn "cosxf2"
14344 [(set (match_operand:XF 0 "register_operand" "=f")
14345 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14346 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14347 && flag_unsafe_math_optimizations"
14349 [(set_attr "type" "fpspc")
14350 (set_attr "mode" "XF")])
14352 (define_insn "costf2"
14353 [(set (match_operand:TF 0 "register_operand" "=f")
14354 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
14355 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14356 && flag_unsafe_math_optimizations"
14358 [(set_attr "type" "fpspc")
14359 (set_attr "mode" "XF")])
14361 ;; Block operation instructions
14364 [(set (reg:SI 19) (const_int 0))]
14367 [(set_attr "type" "cld")])
14369 (define_expand "movstrsi"
14370 [(use (match_operand:BLK 0 "memory_operand" ""))
14371 (use (match_operand:BLK 1 "memory_operand" ""))
14372 (use (match_operand:SI 2 "nonmemory_operand" ""))
14373 (use (match_operand:SI 3 "const_int_operand" ""))]
14376 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14382 (define_expand "movstrdi"
14383 [(use (match_operand:BLK 0 "memory_operand" ""))
14384 (use (match_operand:BLK 1 "memory_operand" ""))
14385 (use (match_operand:DI 2 "nonmemory_operand" ""))
14386 (use (match_operand:DI 3 "const_int_operand" ""))]
14389 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14395 ;; Most CPUs don't like single string operations
14396 ;; Handle this case here to simplify previous expander.
14398 (define_expand "strmovdi_rex64"
14399 [(set (match_dup 2)
14400 (mem:DI (match_operand:DI 1 "register_operand" "")))
14401 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14403 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14404 (clobber (reg:CC 17))])
14405 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14406 (clobber (reg:CC 17))])]
14409 if (TARGET_SINGLE_STRINGOP || optimize_size)
14411 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14416 operands[2] = gen_reg_rtx (DImode);
14420 (define_expand "strmovsi"
14421 [(set (match_dup 2)
14422 (mem:SI (match_operand:SI 1 "register_operand" "")))
14423 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14425 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14426 (clobber (reg:CC 17))])
14427 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14428 (clobber (reg:CC 17))])]
14433 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14436 if (TARGET_SINGLE_STRINGOP || optimize_size)
14438 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14443 operands[2] = gen_reg_rtx (SImode);
14446 (define_expand "strmovsi_rex64"
14447 [(set (match_dup 2)
14448 (mem:SI (match_operand:DI 1 "register_operand" "")))
14449 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14451 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14452 (clobber (reg:CC 17))])
14453 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14454 (clobber (reg:CC 17))])]
14457 if (TARGET_SINGLE_STRINGOP || optimize_size)
14459 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14464 operands[2] = gen_reg_rtx (SImode);
14467 (define_expand "strmovhi"
14468 [(set (match_dup 2)
14469 (mem:HI (match_operand:SI 1 "register_operand" "")))
14470 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14472 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14473 (clobber (reg:CC 17))])
14474 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14475 (clobber (reg:CC 17))])]
14480 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14483 if (TARGET_SINGLE_STRINGOP || optimize_size)
14485 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14490 operands[2] = gen_reg_rtx (HImode);
14493 (define_expand "strmovhi_rex64"
14494 [(set (match_dup 2)
14495 (mem:HI (match_operand:DI 1 "register_operand" "")))
14496 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14498 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14499 (clobber (reg:CC 17))])
14500 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14501 (clobber (reg:CC 17))])]
14504 if (TARGET_SINGLE_STRINGOP || optimize_size)
14506 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14511 operands[2] = gen_reg_rtx (HImode);
14514 (define_expand "strmovqi"
14515 [(set (match_dup 2)
14516 (mem:QI (match_operand:SI 1 "register_operand" "")))
14517 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14519 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14520 (clobber (reg:CC 17))])
14521 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14522 (clobber (reg:CC 17))])]
14527 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14530 if (TARGET_SINGLE_STRINGOP || optimize_size)
14532 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14537 operands[2] = gen_reg_rtx (QImode);
14540 (define_expand "strmovqi_rex64"
14541 [(set (match_dup 2)
14542 (mem:QI (match_operand:DI 1 "register_operand" "")))
14543 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14545 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14546 (clobber (reg:CC 17))])
14547 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14548 (clobber (reg:CC 17))])]
14551 if (TARGET_SINGLE_STRINGOP || optimize_size)
14553 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14558 operands[2] = gen_reg_rtx (QImode);
14561 (define_insn "strmovdi_rex_1"
14562 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14563 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14564 (set (match_operand:DI 0 "register_operand" "=D")
14565 (plus:DI (match_dup 2)
14567 (set (match_operand:DI 1 "register_operand" "=S")
14568 (plus:DI (match_dup 3)
14571 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14573 [(set_attr "type" "str")
14574 (set_attr "mode" "DI")
14575 (set_attr "memory" "both")])
14577 (define_insn "strmovsi_1"
14578 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14579 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14580 (set (match_operand:SI 0 "register_operand" "=D")
14581 (plus:SI (match_dup 2)
14583 (set (match_operand:SI 1 "register_operand" "=S")
14584 (plus:SI (match_dup 3)
14587 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14589 [(set_attr "type" "str")
14590 (set_attr "mode" "SI")
14591 (set_attr "memory" "both")])
14593 (define_insn "strmovsi_rex_1"
14594 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
14595 (mem:SI (match_operand:DI 3 "register_operand" "1")))
14596 (set (match_operand:DI 0 "register_operand" "=D")
14597 (plus:DI (match_dup 2)
14599 (set (match_operand:DI 1 "register_operand" "=S")
14600 (plus:DI (match_dup 3)
14603 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14605 [(set_attr "type" "str")
14606 (set_attr "mode" "SI")
14607 (set_attr "memory" "both")])
14609 (define_insn "strmovhi_1"
14610 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
14611 (mem:HI (match_operand:SI 3 "register_operand" "1")))
14612 (set (match_operand:SI 0 "register_operand" "=D")
14613 (plus:SI (match_dup 2)
14615 (set (match_operand:SI 1 "register_operand" "=S")
14616 (plus:SI (match_dup 3)
14619 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14621 [(set_attr "type" "str")
14622 (set_attr "memory" "both")
14623 (set_attr "mode" "HI")])
14625 (define_insn "strmovhi_rex_1"
14626 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
14627 (mem:HI (match_operand:DI 3 "register_operand" "1")))
14628 (set (match_operand:DI 0 "register_operand" "=D")
14629 (plus:DI (match_dup 2)
14631 (set (match_operand:DI 1 "register_operand" "=S")
14632 (plus:DI (match_dup 3)
14635 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14637 [(set_attr "type" "str")
14638 (set_attr "memory" "both")
14639 (set_attr "mode" "HI")])
14641 (define_insn "strmovqi_1"
14642 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
14643 (mem:QI (match_operand:SI 3 "register_operand" "1")))
14644 (set (match_operand:SI 0 "register_operand" "=D")
14645 (plus:SI (match_dup 2)
14647 (set (match_operand:SI 1 "register_operand" "=S")
14648 (plus:SI (match_dup 3)
14651 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14653 [(set_attr "type" "str")
14654 (set_attr "memory" "both")
14655 (set_attr "mode" "QI")])
14657 (define_insn "strmovqi_rex_1"
14658 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
14659 (mem:QI (match_operand:DI 3 "register_operand" "1")))
14660 (set (match_operand:DI 0 "register_operand" "=D")
14661 (plus:DI (match_dup 2)
14663 (set (match_operand:DI 1 "register_operand" "=S")
14664 (plus:DI (match_dup 3)
14667 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14669 [(set_attr "type" "str")
14670 (set_attr "memory" "both")
14671 (set_attr "mode" "QI")])
14673 (define_insn "rep_movdi_rex64"
14674 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14675 (set (match_operand:DI 0 "register_operand" "=D")
14676 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14678 (match_operand:DI 3 "register_operand" "0")))
14679 (set (match_operand:DI 1 "register_operand" "=S")
14680 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
14681 (match_operand:DI 4 "register_operand" "1")))
14682 (set (mem:BLK (match_dup 3))
14683 (mem:BLK (match_dup 4)))
14684 (use (match_dup 5))
14687 "{rep\;movsq|rep movsq}"
14688 [(set_attr "type" "str")
14689 (set_attr "prefix_rep" "1")
14690 (set_attr "memory" "both")
14691 (set_attr "mode" "DI")])
14693 (define_insn "rep_movsi"
14694 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14695 (set (match_operand:SI 0 "register_operand" "=D")
14696 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
14698 (match_operand:SI 3 "register_operand" "0")))
14699 (set (match_operand:SI 1 "register_operand" "=S")
14700 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
14701 (match_operand:SI 4 "register_operand" "1")))
14702 (set (mem:BLK (match_dup 3))
14703 (mem:BLK (match_dup 4)))
14704 (use (match_dup 5))
14707 "{rep\;movsl|rep movsd}"
14708 [(set_attr "type" "str")
14709 (set_attr "prefix_rep" "1")
14710 (set_attr "memory" "both")
14711 (set_attr "mode" "SI")])
14713 (define_insn "rep_movsi_rex64"
14714 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14715 (set (match_operand:DI 0 "register_operand" "=D")
14716 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14718 (match_operand:DI 3 "register_operand" "0")))
14719 (set (match_operand:DI 1 "register_operand" "=S")
14720 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
14721 (match_operand:DI 4 "register_operand" "1")))
14722 (set (mem:BLK (match_dup 3))
14723 (mem:BLK (match_dup 4)))
14724 (use (match_dup 5))
14727 "{rep\;movsl|rep movsd}"
14728 [(set_attr "type" "str")
14729 (set_attr "prefix_rep" "1")
14730 (set_attr "memory" "both")
14731 (set_attr "mode" "SI")])
14733 (define_insn "rep_movqi"
14734 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14735 (set (match_operand:SI 0 "register_operand" "=D")
14736 (plus:SI (match_operand:SI 3 "register_operand" "0")
14737 (match_operand:SI 5 "register_operand" "2")))
14738 (set (match_operand:SI 1 "register_operand" "=S")
14739 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
14740 (set (mem:BLK (match_dup 3))
14741 (mem:BLK (match_dup 4)))
14742 (use (match_dup 5))
14745 "{rep\;movsb|rep movsb}"
14746 [(set_attr "type" "str")
14747 (set_attr "prefix_rep" "1")
14748 (set_attr "memory" "both")
14749 (set_attr "mode" "SI")])
14751 (define_insn "rep_movqi_rex64"
14752 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14753 (set (match_operand:DI 0 "register_operand" "=D")
14754 (plus:DI (match_operand:DI 3 "register_operand" "0")
14755 (match_operand:DI 5 "register_operand" "2")))
14756 (set (match_operand:DI 1 "register_operand" "=S")
14757 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
14758 (set (mem:BLK (match_dup 3))
14759 (mem:BLK (match_dup 4)))
14760 (use (match_dup 5))
14763 "{rep\;movsb|rep movsb}"
14764 [(set_attr "type" "str")
14765 (set_attr "prefix_rep" "1")
14766 (set_attr "memory" "both")
14767 (set_attr "mode" "SI")])
14769 (define_expand "clrstrsi"
14770 [(use (match_operand:BLK 0 "memory_operand" ""))
14771 (use (match_operand:SI 1 "nonmemory_operand" ""))
14772 (use (match_operand 2 "const_int_operand" ""))]
14775 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14781 (define_expand "clrstrdi"
14782 [(use (match_operand:BLK 0 "memory_operand" ""))
14783 (use (match_operand:DI 1 "nonmemory_operand" ""))
14784 (use (match_operand 2 "const_int_operand" ""))]
14787 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14793 ;; Most CPUs don't like single string operations
14794 ;; Handle this case here to simplify previous expander.
14796 (define_expand "strsetdi_rex64"
14797 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
14798 (match_operand:DI 1 "register_operand" ""))
14799 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14800 (clobber (reg:CC 17))])]
14803 if (TARGET_SINGLE_STRINGOP || optimize_size)
14805 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
14810 (define_expand "strsetsi"
14811 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
14812 (match_operand:SI 1 "register_operand" ""))
14813 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14814 (clobber (reg:CC 17))])]
14819 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
14822 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14824 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
14829 (define_expand "strsetsi_rex64"
14830 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
14831 (match_operand:SI 1 "register_operand" ""))
14832 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14833 (clobber (reg:CC 17))])]
14836 if (TARGET_SINGLE_STRINGOP || optimize_size)
14838 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
14843 (define_expand "strsethi"
14844 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
14845 (match_operand:HI 1 "register_operand" ""))
14846 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14847 (clobber (reg:CC 17))])]
14852 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
14855 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14857 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
14862 (define_expand "strsethi_rex64"
14863 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
14864 (match_operand:HI 1 "register_operand" ""))
14865 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14866 (clobber (reg:CC 17))])]
14869 if (TARGET_SINGLE_STRINGOP || optimize_size)
14871 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
14876 (define_expand "strsetqi"
14877 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
14878 (match_operand:QI 1 "register_operand" ""))
14879 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14880 (clobber (reg:CC 17))])]
14885 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
14888 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14890 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
14895 (define_expand "strsetqi_rex64"
14896 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
14897 (match_operand:QI 1 "register_operand" ""))
14898 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14899 (clobber (reg:CC 17))])]
14902 if (TARGET_SINGLE_STRINGOP || optimize_size)
14904 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
14909 (define_insn "strsetdi_rex_1"
14910 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
14911 (match_operand:SI 2 "register_operand" "a"))
14912 (set (match_operand:DI 0 "register_operand" "=D")
14913 (plus:DI (match_dup 1)
14916 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14918 [(set_attr "type" "str")
14919 (set_attr "memory" "store")
14920 (set_attr "mode" "DI")])
14922 (define_insn "strsetsi_1"
14923 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
14924 (match_operand:SI 2 "register_operand" "a"))
14925 (set (match_operand:SI 0 "register_operand" "=D")
14926 (plus:SI (match_dup 1)
14929 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14931 [(set_attr "type" "str")
14932 (set_attr "memory" "store")
14933 (set_attr "mode" "SI")])
14935 (define_insn "strsetsi_rex_1"
14936 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
14937 (match_operand:SI 2 "register_operand" "a"))
14938 (set (match_operand:DI 0 "register_operand" "=D")
14939 (plus:DI (match_dup 1)
14942 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14944 [(set_attr "type" "str")
14945 (set_attr "memory" "store")
14946 (set_attr "mode" "SI")])
14948 (define_insn "strsethi_1"
14949 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
14950 (match_operand:HI 2 "register_operand" "a"))
14951 (set (match_operand:SI 0 "register_operand" "=D")
14952 (plus:SI (match_dup 1)
14955 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14957 [(set_attr "type" "str")
14958 (set_attr "memory" "store")
14959 (set_attr "mode" "HI")])
14961 (define_insn "strsethi_rex_1"
14962 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
14963 (match_operand:HI 2 "register_operand" "a"))
14964 (set (match_operand:DI 0 "register_operand" "=D")
14965 (plus:DI (match_dup 1)
14968 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14970 [(set_attr "type" "str")
14971 (set_attr "memory" "store")
14972 (set_attr "mode" "HI")])
14974 (define_insn "strsetqi_1"
14975 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
14976 (match_operand:QI 2 "register_operand" "a"))
14977 (set (match_operand:SI 0 "register_operand" "=D")
14978 (plus:SI (match_dup 1)
14981 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14983 [(set_attr "type" "str")
14984 (set_attr "memory" "store")
14985 (set_attr "mode" "QI")])
14987 (define_insn "strsetqi_rex_1"
14988 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
14989 (match_operand:QI 2 "register_operand" "a"))
14990 (set (match_operand:DI 0 "register_operand" "=D")
14991 (plus:DI (match_dup 1)
14994 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14996 [(set_attr "type" "str")
14997 (set_attr "memory" "store")
14998 (set_attr "mode" "QI")])
15000 (define_insn "rep_stosdi_rex64"
15001 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15002 (set (match_operand:DI 0 "register_operand" "=D")
15003 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15005 (match_operand:DI 3 "register_operand" "0")))
15006 (set (mem:BLK (match_dup 3))
15008 (use (match_operand:DI 2 "register_operand" "a"))
15009 (use (match_dup 4))
15012 "{rep\;stosq|rep stosq}"
15013 [(set_attr "type" "str")
15014 (set_attr "prefix_rep" "1")
15015 (set_attr "memory" "store")
15016 (set_attr "mode" "DI")])
15018 (define_insn "rep_stossi"
15019 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15020 (set (match_operand:SI 0 "register_operand" "=D")
15021 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15023 (match_operand:SI 3 "register_operand" "0")))
15024 (set (mem:BLK (match_dup 3))
15026 (use (match_operand:SI 2 "register_operand" "a"))
15027 (use (match_dup 4))
15030 "{rep\;stosl|rep stosd}"
15031 [(set_attr "type" "str")
15032 (set_attr "prefix_rep" "1")
15033 (set_attr "memory" "store")
15034 (set_attr "mode" "SI")])
15036 (define_insn "rep_stossi_rex64"
15037 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15038 (set (match_operand:DI 0 "register_operand" "=D")
15039 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15041 (match_operand:DI 3 "register_operand" "0")))
15042 (set (mem:BLK (match_dup 3))
15044 (use (match_operand:SI 2 "register_operand" "a"))
15045 (use (match_dup 4))
15048 "{rep\;stosl|rep stosd}"
15049 [(set_attr "type" "str")
15050 (set_attr "prefix_rep" "1")
15051 (set_attr "memory" "store")
15052 (set_attr "mode" "SI")])
15054 (define_insn "rep_stosqi"
15055 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15056 (set (match_operand:SI 0 "register_operand" "=D")
15057 (plus:SI (match_operand:SI 3 "register_operand" "0")
15058 (match_operand:SI 4 "register_operand" "1")))
15059 (set (mem:BLK (match_dup 3))
15061 (use (match_operand:QI 2 "register_operand" "a"))
15062 (use (match_dup 4))
15065 "{rep\;stosb|rep stosb}"
15066 [(set_attr "type" "str")
15067 (set_attr "prefix_rep" "1")
15068 (set_attr "memory" "store")
15069 (set_attr "mode" "QI")])
15071 (define_insn "rep_stosqi_rex64"
15072 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15073 (set (match_operand:DI 0 "register_operand" "=D")
15074 (plus:DI (match_operand:DI 3 "register_operand" "0")
15075 (match_operand:DI 4 "register_operand" "1")))
15076 (set (mem:BLK (match_dup 3))
15078 (use (match_operand:QI 2 "register_operand" "a"))
15079 (use (match_dup 4))
15082 "{rep\;stosb|rep stosb}"
15083 [(set_attr "type" "str")
15084 (set_attr "prefix_rep" "1")
15085 (set_attr "memory" "store")
15086 (set_attr "mode" "QI")])
15088 (define_expand "cmpstrsi"
15089 [(set (match_operand:SI 0 "register_operand" "")
15090 (compare:SI (match_operand:BLK 1 "general_operand" "")
15091 (match_operand:BLK 2 "general_operand" "")))
15092 (use (match_operand 3 "general_operand" ""))
15093 (use (match_operand 4 "immediate_operand" ""))]
15096 rtx addr1, addr2, out, outlow, count, countreg, align;
15099 if (GET_CODE (out) != REG)
15100 out = gen_reg_rtx (SImode);
15102 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15103 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15105 count = operands[3];
15106 countreg = ix86_zero_extend_to_Pmode (count);
15108 /* %%% Iff we are testing strict equality, we can use known alignment
15109 to good advantage. This may be possible with combine, particularly
15110 once cc0 is dead. */
15111 align = operands[4];
15113 emit_insn (gen_cld ());
15114 if (GET_CODE (count) == CONST_INT)
15116 if (INTVAL (count) == 0)
15118 emit_move_insn (operands[0], const0_rtx);
15122 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15123 addr1, addr2, countreg));
15125 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15126 addr1, addr2, countreg));
15132 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15133 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15134 addr1, addr2, countreg));
15138 emit_insn (gen_cmpsi_1 (countreg, countreg));
15139 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15140 addr1, addr2, countreg));
15144 outlow = gen_lowpart (QImode, out);
15145 emit_insn (gen_cmpintqi (outlow));
15146 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15148 if (operands[0] != out)
15149 emit_move_insn (operands[0], out);
15154 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15156 (define_expand "cmpintqi"
15157 [(set (match_dup 1)
15158 (gtu:QI (reg:CC 17) (const_int 0)))
15160 (ltu:QI (reg:CC 17) (const_int 0)))
15161 (parallel [(set (match_operand:QI 0 "register_operand" "")
15162 (minus:QI (match_dup 1)
15164 (clobber (reg:CC 17))])]
15166 "operands[1] = gen_reg_rtx (QImode);
15167 operands[2] = gen_reg_rtx (QImode);")
15169 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15170 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15172 (define_insn "cmpstrqi_nz_1"
15174 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15175 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15176 (use (match_operand:SI 6 "register_operand" "2"))
15177 (use (match_operand:SI 3 "immediate_operand" "i"))
15179 (clobber (match_operand:SI 0 "register_operand" "=S"))
15180 (clobber (match_operand:SI 1 "register_operand" "=D"))
15181 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15184 [(set_attr "type" "str")
15185 (set_attr "mode" "QI")
15186 (set_attr "prefix_rep" "1")])
15188 (define_insn "cmpstrqi_nz_rex_1"
15190 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15191 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15192 (use (match_operand:DI 6 "register_operand" "2"))
15193 (use (match_operand:SI 3 "immediate_operand" "i"))
15195 (clobber (match_operand:DI 0 "register_operand" "=S"))
15196 (clobber (match_operand:DI 1 "register_operand" "=D"))
15197 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15200 [(set_attr "type" "str")
15201 (set_attr "mode" "QI")
15202 (set_attr "prefix_rep" "1")])
15204 ;; The same, but the count is not known to not be zero.
15206 (define_insn "cmpstrqi_1"
15208 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15210 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15211 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15213 (use (match_operand:SI 3 "immediate_operand" "i"))
15216 (clobber (match_operand:SI 0 "register_operand" "=S"))
15217 (clobber (match_operand:SI 1 "register_operand" "=D"))
15218 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15221 [(set_attr "type" "str")
15222 (set_attr "mode" "QI")
15223 (set_attr "prefix_rep" "1")])
15225 (define_insn "cmpstrqi_rex_1"
15227 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15229 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15230 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15232 (use (match_operand:SI 3 "immediate_operand" "i"))
15235 (clobber (match_operand:DI 0 "register_operand" "=S"))
15236 (clobber (match_operand:DI 1 "register_operand" "=D"))
15237 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15240 [(set_attr "type" "str")
15241 (set_attr "mode" "QI")
15242 (set_attr "prefix_rep" "1")])
15244 (define_expand "strlensi"
15245 [(set (match_operand:SI 0 "register_operand" "")
15246 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15247 (match_operand:QI 2 "immediate_operand" "")
15248 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15251 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15257 (define_expand "strlendi"
15258 [(set (match_operand:DI 0 "register_operand" "")
15259 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15260 (match_operand:QI 2 "immediate_operand" "")
15261 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15264 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15270 (define_insn "strlenqi_1"
15271 [(set (match_operand:SI 0 "register_operand" "=&c")
15272 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15273 (match_operand:QI 2 "register_operand" "a")
15274 (match_operand:SI 3 "immediate_operand" "i")
15275 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
15277 (clobber (match_operand:SI 1 "register_operand" "=D"))
15278 (clobber (reg:CC 17))]
15281 [(set_attr "type" "str")
15282 (set_attr "mode" "QI")
15283 (set_attr "prefix_rep" "1")])
15285 (define_insn "strlenqi_rex_1"
15286 [(set (match_operand:DI 0 "register_operand" "=&c")
15287 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15288 (match_operand:QI 2 "register_operand" "a")
15289 (match_operand:DI 3 "immediate_operand" "i")
15290 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
15292 (clobber (match_operand:DI 1 "register_operand" "=D"))
15293 (clobber (reg:CC 17))]
15296 [(set_attr "type" "str")
15297 (set_attr "mode" "QI")
15298 (set_attr "prefix_rep" "1")])
15300 ;; Peephole optimizations to clean up after cmpstr*. This should be
15301 ;; handled in combine, but it is not currently up to the task.
15302 ;; When used for their truth value, the cmpstr* expanders generate
15311 ;; The intermediate three instructions are unnecessary.
15313 ;; This one handles cmpstr*_nz_1...
15317 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15318 (mem:BLK (match_operand 5 "register_operand" ""))))
15319 (use (match_operand 6 "register_operand" ""))
15320 (use (match_operand:SI 3 "immediate_operand" ""))
15322 (clobber (match_operand 0 "register_operand" ""))
15323 (clobber (match_operand 1 "register_operand" ""))
15324 (clobber (match_operand 2 "register_operand" ""))])
15325 (set (match_operand:QI 7 "register_operand" "")
15326 (gtu:QI (reg:CC 17) (const_int 0)))
15327 (set (match_operand:QI 8 "register_operand" "")
15328 (ltu:QI (reg:CC 17) (const_int 0)))
15330 (compare (match_dup 7) (match_dup 8)))
15332 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15335 (compare:CC (mem:BLK (match_dup 4))
15336 (mem:BLK (match_dup 5))))
15337 (use (match_dup 6))
15338 (use (match_dup 3))
15340 (clobber (match_dup 0))
15341 (clobber (match_dup 1))
15342 (clobber (match_dup 2))])]
15345 ;; ...and this one handles cmpstr*_1.
15349 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
15351 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15352 (mem:BLK (match_operand 5 "register_operand" "")))
15354 (use (match_operand:SI 3 "immediate_operand" ""))
15357 (clobber (match_operand 0 "register_operand" ""))
15358 (clobber (match_operand 1 "register_operand" ""))
15359 (clobber (match_operand 2 "register_operand" ""))])
15360 (set (match_operand:QI 7 "register_operand" "")
15361 (gtu:QI (reg:CC 17) (const_int 0)))
15362 (set (match_operand:QI 8 "register_operand" "")
15363 (ltu:QI (reg:CC 17) (const_int 0)))
15365 (compare (match_dup 7) (match_dup 8)))
15367 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15370 (if_then_else:CC (ne (match_dup 6)
15372 (compare:CC (mem:BLK (match_dup 4))
15373 (mem:BLK (match_dup 5)))
15375 (use (match_dup 3))
15378 (clobber (match_dup 0))
15379 (clobber (match_dup 1))
15380 (clobber (match_dup 2))])]
15385 ;; Conditional move instructions.
15387 (define_expand "movdicc"
15388 [(set (match_operand:DI 0 "register_operand" "")
15389 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15390 (match_operand:DI 2 "general_operand" "")
15391 (match_operand:DI 3 "general_operand" "")))]
15393 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15395 (define_insn "x86_movdicc_0_m1_rex64"
15396 [(set (match_operand:DI 0 "register_operand" "=r")
15397 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15400 (clobber (reg:CC 17))]
15403 ; Since we don't have the proper number of operands for an alu insn,
15404 ; fill in all the blanks.
15405 [(set_attr "type" "alu")
15406 (set_attr "pent_pair" "pu")
15407 (set_attr "memory" "none")
15408 (set_attr "imm_disp" "false")
15409 (set_attr "mode" "DI")
15410 (set_attr "length_immediate" "0")])
15412 (define_insn "*movdicc_c_rex64"
15413 [(set (match_operand:DI 0 "register_operand" "=r,r")
15414 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15415 [(reg 17) (const_int 0)])
15416 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15417 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15418 "TARGET_64BIT && TARGET_CMOVE
15419 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15421 cmov%O2%C1\t{%2, %0|%0, %2}
15422 cmov%O2%c1\t{%3, %0|%0, %3}"
15423 [(set_attr "type" "icmov")
15424 (set_attr "mode" "DI")])
15426 (define_expand "movsicc"
15427 [(set (match_operand:SI 0 "register_operand" "")
15428 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15429 (match_operand:SI 2 "general_operand" "")
15430 (match_operand:SI 3 "general_operand" "")))]
15432 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15434 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15435 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15436 ;; So just document what we're doing explicitly.
15438 (define_insn "x86_movsicc_0_m1"
15439 [(set (match_operand:SI 0 "register_operand" "=r")
15440 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15443 (clobber (reg:CC 17))]
15446 ; Since we don't have the proper number of operands for an alu insn,
15447 ; fill in all the blanks.
15448 [(set_attr "type" "alu")
15449 (set_attr "pent_pair" "pu")
15450 (set_attr "memory" "none")
15451 (set_attr "imm_disp" "false")
15452 (set_attr "mode" "SI")
15453 (set_attr "length_immediate" "0")])
15455 (define_insn "*movsicc_noc"
15456 [(set (match_operand:SI 0 "register_operand" "=r,r")
15457 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15458 [(reg 17) (const_int 0)])
15459 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15460 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15462 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15464 cmov%O2%C1\t{%2, %0|%0, %2}
15465 cmov%O2%c1\t{%3, %0|%0, %3}"
15466 [(set_attr "type" "icmov")
15467 (set_attr "mode" "SI")])
15469 (define_expand "movhicc"
15470 [(set (match_operand:HI 0 "register_operand" "")
15471 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15472 (match_operand:HI 2 "nonimmediate_operand" "")
15473 (match_operand:HI 3 "nonimmediate_operand" "")))]
15474 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15475 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15477 (define_insn "*movhicc_noc"
15478 [(set (match_operand:HI 0 "register_operand" "=r,r")
15479 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15480 [(reg 17) (const_int 0)])
15481 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15482 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15484 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15486 cmov%O2%C1\t{%2, %0|%0, %2}
15487 cmov%O2%c1\t{%3, %0|%0, %3}"
15488 [(set_attr "type" "icmov")
15489 (set_attr "mode" "HI")])
15491 (define_expand "movsfcc"
15492 [(set (match_operand:SF 0 "register_operand" "")
15493 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15494 (match_operand:SF 2 "register_operand" "")
15495 (match_operand:SF 3 "register_operand" "")))]
15497 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15499 (define_insn "*movsfcc_1"
15500 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15501 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15502 [(reg 17) (const_int 0)])
15503 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15504 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15506 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15508 fcmov%F1\t{%2, %0|%0, %2}
15509 fcmov%f1\t{%3, %0|%0, %3}
15510 cmov%O2%C1\t{%2, %0|%0, %2}
15511 cmov%O2%c1\t{%3, %0|%0, %3}"
15512 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15513 (set_attr "mode" "SF,SF,SI,SI")])
15515 (define_expand "movdfcc"
15516 [(set (match_operand:DF 0 "register_operand" "")
15517 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15518 (match_operand:DF 2 "register_operand" "")
15519 (match_operand:DF 3 "register_operand" "")))]
15521 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15523 (define_insn "*movdfcc_1"
15524 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15525 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15526 [(reg 17) (const_int 0)])
15527 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15528 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15529 "!TARGET_64BIT && TARGET_CMOVE
15530 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15532 fcmov%F1\t{%2, %0|%0, %2}
15533 fcmov%f1\t{%3, %0|%0, %3}
15536 [(set_attr "type" "fcmov,fcmov,multi,multi")
15537 (set_attr "mode" "DF")])
15539 (define_insn "*movdfcc_1_rex64"
15540 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15541 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15542 [(reg 17) (const_int 0)])
15543 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15544 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15545 "TARGET_64BIT && TARGET_CMOVE
15546 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15548 fcmov%F1\t{%2, %0|%0, %2}
15549 fcmov%f1\t{%3, %0|%0, %3}
15550 cmov%O2%C1\t{%2, %0|%0, %2}
15551 cmov%O2%c1\t{%3, %0|%0, %3}"
15552 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15553 (set_attr "mode" "DF")])
15556 [(set (match_operand:DF 0 "register_operand" "")
15557 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15558 [(match_operand 4 "" "") (const_int 0)])
15559 (match_operand:DF 2 "nonimmediate_operand" "")
15560 (match_operand:DF 3 "nonimmediate_operand" "")))]
15561 "!TARGET_64BIT && !ANY_FP_REG_P (operands[0]) && reload_completed"
15562 [(set (match_dup 2)
15563 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15567 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15570 "split_di (operands+2, 1, operands+5, operands+6);
15571 split_di (operands+3, 1, operands+7, operands+8);
15572 split_di (operands, 1, operands+2, operands+3);")
15574 (define_expand "movxfcc"
15575 [(set (match_operand:XF 0 "register_operand" "")
15576 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15577 (match_operand:XF 2 "register_operand" "")
15578 (match_operand:XF 3 "register_operand" "")))]
15579 "!TARGET_64BIT && TARGET_CMOVE"
15580 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15582 (define_expand "movtfcc"
15583 [(set (match_operand:TF 0 "register_operand" "")
15584 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15585 (match_operand:TF 2 "register_operand" "")
15586 (match_operand:TF 3 "register_operand" "")))]
15588 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15590 (define_insn "*movxfcc_1"
15591 [(set (match_operand:XF 0 "register_operand" "=f,f")
15592 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
15593 [(reg 17) (const_int 0)])
15594 (match_operand:XF 2 "register_operand" "f,0")
15595 (match_operand:XF 3 "register_operand" "0,f")))]
15596 "!TARGET_64BIT && TARGET_CMOVE"
15598 fcmov%F1\t{%2, %0|%0, %2}
15599 fcmov%f1\t{%3, %0|%0, %3}"
15600 [(set_attr "type" "fcmov")
15601 (set_attr "mode" "XF")])
15603 (define_insn "*movtfcc_1"
15604 [(set (match_operand:TF 0 "register_operand" "=f,f")
15605 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
15606 [(reg 17) (const_int 0)])
15607 (match_operand:TF 2 "register_operand" "f,0")
15608 (match_operand:TF 3 "register_operand" "0,f")))]
15611 fcmov%F1\t{%2, %0|%0, %2}
15612 fcmov%f1\t{%3, %0|%0, %3}"
15613 [(set_attr "type" "fcmov")
15614 (set_attr "mode" "XF")])
15616 (define_expand "minsf3"
15618 (set (match_operand:SF 0 "register_operand" "")
15619 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15620 (match_operand:SF 2 "nonimmediate_operand" ""))
15623 (clobber (reg:CC 17))])]
15627 (define_insn "*minsf"
15628 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15629 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
15630 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15633 (clobber (reg:CC 17))]
15634 "TARGET_SSE && TARGET_IEEE_FP"
15637 (define_insn "*minsf_nonieee"
15638 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15639 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
15640 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
15643 (clobber (reg:CC 17))]
15644 "TARGET_SSE && !TARGET_IEEE_FP
15645 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
15649 [(set (match_operand:SF 0 "register_operand" "")
15650 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15651 (match_operand:SF 2 "nonimmediate_operand" ""))
15652 (match_operand:SF 3 "register_operand" "")
15653 (match_operand:SF 4 "nonimmediate_operand" "")))
15654 (clobber (reg:CC 17))]
15655 "SSE_REG_P (operands[0]) && reload_completed
15656 && ((operands_match_p (operands[1], operands[3])
15657 && operands_match_p (operands[2], operands[4]))
15658 || (operands_match_p (operands[1], operands[4])
15659 && operands_match_p (operands[2], operands[3])))"
15660 [(set (match_dup 0)
15661 (if_then_else:SF (lt (match_dup 1)
15666 ;; We can't represent the LT test directly. Do this by swapping the operands.
15669 [(set (match_operand:SF 0 "register_operand" "")
15670 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15671 (match_operand:SF 2 "register_operand" ""))
15672 (match_operand:SF 3 "register_operand" "")
15673 (match_operand:SF 4 "register_operand" "")))
15674 (clobber (reg:CC 17))]
15675 "FP_REG_P (operands[0]) && reload_completed
15676 && ((operands_match_p (operands[1], operands[3])
15677 && operands_match_p (operands[2], operands[4]))
15678 || (operands_match_p (operands[1], operands[4])
15679 && operands_match_p (operands[2], operands[3])))"
15680 [(set (reg:CCFP 17)
15681 (compare:CCFP (match_dup 2)
15684 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
15688 (define_insn "*minsf_sse"
15689 [(set (match_operand:SF 0 "register_operand" "=x")
15690 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
15691 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15694 "TARGET_SSE && reload_completed"
15695 "minss\t{%2, %0|%0, %2}"
15696 [(set_attr "type" "sse")
15697 (set_attr "mode" "SF")])
15699 (define_expand "mindf3"
15701 (set (match_operand:DF 0 "register_operand" "")
15702 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15703 (match_operand:DF 2 "nonimmediate_operand" ""))
15706 (clobber (reg:CC 17))])]
15707 "TARGET_SSE2 && TARGET_SSE_MATH"
15710 (define_insn "*mindf"
15711 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15712 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15713 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15716 (clobber (reg:CC 17))]
15717 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
15720 (define_insn "*mindf_nonieee"
15721 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15722 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
15723 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
15726 (clobber (reg:CC 17))]
15727 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
15728 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
15732 [(set (match_operand:DF 0 "register_operand" "")
15733 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15734 (match_operand:DF 2 "nonimmediate_operand" ""))
15735 (match_operand:DF 3 "register_operand" "")
15736 (match_operand:DF 4 "nonimmediate_operand" "")))
15737 (clobber (reg:CC 17))]
15738 "SSE_REG_P (operands[0]) && reload_completed
15739 && ((operands_match_p (operands[1], operands[3])
15740 && operands_match_p (operands[2], operands[4]))
15741 || (operands_match_p (operands[1], operands[4])
15742 && operands_match_p (operands[2], operands[3])))"
15743 [(set (match_dup 0)
15744 (if_then_else:DF (lt (match_dup 1)
15749 ;; We can't represent the LT test directly. Do this by swapping the operands.
15751 [(set (match_operand:DF 0 "register_operand" "")
15752 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15753 (match_operand:DF 2 "register_operand" ""))
15754 (match_operand:DF 3 "register_operand" "")
15755 (match_operand:DF 4 "register_operand" "")))
15756 (clobber (reg:CC 17))]
15757 "FP_REG_P (operands[0]) && reload_completed
15758 && ((operands_match_p (operands[1], operands[3])
15759 && operands_match_p (operands[2], operands[4]))
15760 || (operands_match_p (operands[1], operands[4])
15761 && operands_match_p (operands[2], operands[3])))"
15762 [(set (reg:CCFP 17)
15763 (compare:CCFP (match_dup 2)
15766 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
15770 (define_insn "*mindf_sse"
15771 [(set (match_operand:DF 0 "register_operand" "=Y")
15772 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
15773 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15776 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
15777 "minsd\t{%2, %0|%0, %2}"
15778 [(set_attr "type" "sse")
15779 (set_attr "mode" "DF")])
15781 (define_expand "maxsf3"
15783 (set (match_operand:SF 0 "register_operand" "")
15784 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15785 (match_operand:SF 2 "nonimmediate_operand" ""))
15788 (clobber (reg:CC 17))])]
15792 (define_insn "*maxsf"
15793 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15794 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
15795 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15798 (clobber (reg:CC 17))]
15799 "TARGET_SSE && TARGET_IEEE_FP"
15802 (define_insn "*maxsf_nonieee"
15803 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15804 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
15805 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
15808 (clobber (reg:CC 17))]
15809 "TARGET_SSE && !TARGET_IEEE_FP
15810 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
15814 [(set (match_operand:SF 0 "register_operand" "")
15815 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15816 (match_operand:SF 2 "nonimmediate_operand" ""))
15817 (match_operand:SF 3 "register_operand" "")
15818 (match_operand:SF 4 "nonimmediate_operand" "")))
15819 (clobber (reg:CC 17))]
15820 "SSE_REG_P (operands[0]) && reload_completed
15821 && ((operands_match_p (operands[1], operands[3])
15822 && operands_match_p (operands[2], operands[4]))
15823 || (operands_match_p (operands[1], operands[4])
15824 && operands_match_p (operands[2], operands[3])))"
15825 [(set (match_dup 0)
15826 (if_then_else:SF (gt (match_dup 1)
15832 [(set (match_operand:SF 0 "register_operand" "")
15833 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15834 (match_operand:SF 2 "register_operand" ""))
15835 (match_operand:SF 3 "register_operand" "")
15836 (match_operand:SF 4 "register_operand" "")))
15837 (clobber (reg:CC 17))]
15838 "FP_REG_P (operands[0]) && reload_completed
15839 && ((operands_match_p (operands[1], operands[3])
15840 && operands_match_p (operands[2], operands[4]))
15841 || (operands_match_p (operands[1], operands[4])
15842 && operands_match_p (operands[2], operands[3])))"
15843 [(set (reg:CCFP 17)
15844 (compare:CCFP (match_dup 1)
15847 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
15851 (define_insn "*maxsf_sse"
15852 [(set (match_operand:SF 0 "register_operand" "=x")
15853 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
15854 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15857 "TARGET_SSE && reload_completed"
15858 "maxss\t{%2, %0|%0, %2}"
15859 [(set_attr "type" "sse")
15860 (set_attr "mode" "SF")])
15862 (define_expand "maxdf3"
15864 (set (match_operand:DF 0 "register_operand" "")
15865 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15866 (match_operand:DF 2 "nonimmediate_operand" ""))
15869 (clobber (reg:CC 17))])]
15870 "TARGET_SSE2 && TARGET_SSE_MATH"
15873 (define_insn "*maxdf"
15874 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15875 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15876 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15879 (clobber (reg:CC 17))]
15880 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
15883 (define_insn "*maxdf_nonieee"
15884 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15885 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
15886 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
15889 (clobber (reg:CC 17))]
15890 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
15891 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
15895 [(set (match_operand:DF 0 "register_operand" "")
15896 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15897 (match_operand:DF 2 "nonimmediate_operand" ""))
15898 (match_operand:DF 3 "register_operand" "")
15899 (match_operand:DF 4 "nonimmediate_operand" "")))
15900 (clobber (reg:CC 17))]
15901 "SSE_REG_P (operands[0]) && reload_completed
15902 && ((operands_match_p (operands[1], operands[3])
15903 && operands_match_p (operands[2], operands[4]))
15904 || (operands_match_p (operands[1], operands[4])
15905 && operands_match_p (operands[2], operands[3])))"
15906 [(set (match_dup 0)
15907 (if_then_else:DF (gt (match_dup 1)
15913 [(set (match_operand:DF 0 "register_operand" "")
15914 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15915 (match_operand:DF 2 "register_operand" ""))
15916 (match_operand:DF 3 "register_operand" "")
15917 (match_operand:DF 4 "register_operand" "")))
15918 (clobber (reg:CC 17))]
15919 "FP_REG_P (operands[0]) && reload_completed
15920 && ((operands_match_p (operands[1], operands[3])
15921 && operands_match_p (operands[2], operands[4]))
15922 || (operands_match_p (operands[1], operands[4])
15923 && operands_match_p (operands[2], operands[3])))"
15924 [(set (reg:CCFP 17)
15925 (compare:CCFP (match_dup 1)
15928 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
15932 (define_insn "*maxdf_sse"
15933 [(set (match_operand:DF 0 "register_operand" "=Y")
15934 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
15935 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15938 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
15939 "maxsd\t{%2, %0|%0, %2}"
15940 [(set_attr "type" "sse")
15941 (set_attr "mode" "DF")])
15943 ;; Misc patterns (?)
15945 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
15946 ;; Otherwise there will be nothing to keep
15948 ;; [(set (reg ebp) (reg esp))]
15949 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
15950 ;; (clobber (eflags)]
15951 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
15953 ;; in proper program order.
15954 (define_expand "pro_epilogue_adjust_stack"
15955 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
15956 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
15957 (match_operand:SI 2 "immediate_operand" "i,i")))
15958 (clobber (reg:CC 17))
15959 (clobber (mem:BLK (scratch)))])]
15964 emit_insn (gen_pro_epilogue_adjust_stack_rex64
15965 (operands[0], operands[1], operands[2]));
15970 (define_insn "*pro_epilogue_adjust_stack_1"
15971 [(set (match_operand:SI 0 "register_operand" "=r,r")
15972 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
15973 (match_operand:SI 2 "immediate_operand" "i,i")))
15974 (clobber (reg:CC 17))
15975 (clobber (mem:BLK (scratch)))]
15978 switch (get_attr_type (insn))
15981 return "mov{l}\t{%1, %0|%0, %1}";
15984 if (GET_CODE (operands[2]) == CONST_INT
15985 && (INTVAL (operands[2]) == 128
15986 || (INTVAL (operands[2]) < 0
15987 && INTVAL (operands[2]) != -128)))
15989 operands[2] = GEN_INT (-INTVAL (operands[2]));
15990 return "sub{l}\t{%2, %0|%0, %2}";
15992 return "add{l}\t{%2, %0|%0, %2}";
15995 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
15996 return "lea{l}\t{%a2, %0|%0, %a2}";
16002 [(set (attr "type")
16003 (cond [(eq_attr "alternative" "0")
16004 (const_string "alu")
16005 (match_operand:SI 2 "const0_operand" "")
16006 (const_string "imov")
16008 (const_string "lea")))
16009 (set_attr "mode" "SI")])
16011 (define_insn "pro_epilogue_adjust_stack_rex64"
16012 [(set (match_operand:DI 0 "register_operand" "=r,r")
16013 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16014 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16015 (clobber (reg:CC 17))
16016 (clobber (mem:BLK (scratch)))]
16019 switch (get_attr_type (insn))
16022 return "mov{q}\t{%1, %0|%0, %1}";
16025 if (GET_CODE (operands[2]) == CONST_INT
16026 && (INTVAL (operands[2]) == 128
16027 || (INTVAL (operands[2]) < 0
16028 && INTVAL (operands[2]) != -128)))
16030 operands[2] = GEN_INT (-INTVAL (operands[2]));
16031 return "sub{q}\t{%2, %0|%0, %2}";
16033 return "add{q}\t{%2, %0|%0, %2}";
16036 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16037 return "lea{q}\t{%a2, %0|%0, %a2}";
16043 [(set (attr "type")
16044 (cond [(eq_attr "alternative" "0")
16045 (const_string "alu")
16046 (match_operand:DI 2 "const0_operand" "")
16047 (const_string "imov")
16049 (const_string "lea")))
16050 (set_attr "mode" "DI")])
16053 ;; Placeholder for the conditional moves. This one is split either to SSE
16054 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16055 ;; fact is that compares supported by the cmp??ss instructions are exactly
16056 ;; swapped of those supported by cmove sequence.
16057 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16058 ;; supported by i387 comparisons and we do need to emit two conditional moves
16061 (define_insn "sse_movsfcc"
16062 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16063 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16064 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16065 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16066 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16067 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16068 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16069 (clobber (reg:CC 17))]
16071 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16072 && (!TARGET_IEEE_FP
16073 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16076 (define_insn "sse_movsfcc_eq"
16077 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16078 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16079 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16080 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16081 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16082 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16083 (clobber (reg:CC 17))]
16085 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16088 (define_insn "sse_movdfcc"
16089 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
16090 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16091 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
16092 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
16093 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
16094 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
16095 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16096 (clobber (reg:CC 17))]
16098 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16099 && (!TARGET_IEEE_FP
16100 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16103 (define_insn "sse_movdfcc_eq"
16104 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
16105 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
16106 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
16107 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
16108 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
16109 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16110 (clobber (reg:CC 17))]
16112 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16115 ;; For non-sse moves just expand the usual cmove sequence.
16117 [(set (match_operand 0 "register_operand" "")
16118 (if_then_else (match_operator 1 "comparison_operator"
16119 [(match_operand 4 "nonimmediate_operand" "")
16120 (match_operand 5 "register_operand" "")])
16121 (match_operand 2 "nonimmediate_operand" "")
16122 (match_operand 3 "nonimmediate_operand" "")))
16123 (clobber (match_operand 6 "" ""))
16124 (clobber (reg:CC 17))]
16125 "!SSE_REG_P (operands[0]) && reload_completed
16126 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16129 ix86_compare_op0 = operands[5];
16130 ix86_compare_op1 = operands[4];
16131 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16132 VOIDmode, operands[5], operands[4]);
16133 ix86_expand_fp_movcc (operands);
16137 ;; Split SSE based conditional move into seqence:
16138 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16139 ;; and op2, op0 - zero op2 if comparison was false
16140 ;; nand op0, op3 - load op3 to op0 if comparison was false
16141 ;; or op2, op0 - get the non-zero one into the result.
16143 [(set (match_operand 0 "register_operand" "")
16144 (if_then_else (match_operator 1 "sse_comparison_operator"
16145 [(match_operand 4 "register_operand" "")
16146 (match_operand 5 "nonimmediate_operand" "")])
16147 (match_operand 2 "register_operand" "")
16148 (match_operand 3 "register_operand" "")))
16149 (clobber (match_operand 6 "" ""))
16150 (clobber (reg:CC 17))]
16151 "SSE_REG_P (operands[0]) && reload_completed"
16152 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16153 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16154 (subreg:TI (match_dup 4) 0)))
16155 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16156 (subreg:TI (match_dup 3) 0)))
16157 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16158 (subreg:TI (match_dup 7) 0)))]
16160 /* If op2 == op3, op3 will be clobbered before it is used.
16161 This should be optimized out though. */
16162 if (operands_match_p (operands[2], operands[3]))
16164 PUT_MODE (operands[1], GET_MODE (operands[0]));
16165 if (operands_match_p (operands[0], operands[4]))
16166 operands[6] = operands[4], operands[7] = operands[2];
16168 operands[6] = operands[2], operands[7] = operands[4];
16171 ;; Special case of conditional move we can handle effectivly.
16172 ;; Do not brother with the integer/floating point case, since these are
16173 ;; bot considerably slower, unlike in the generic case.
16174 (define_insn "*sse_movsfcc_const0_1"
16175 [(set (match_operand:SF 0 "register_operand" "=&x")
16176 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16177 [(match_operand:SF 4 "register_operand" "0")
16178 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16179 (match_operand:SF 2 "register_operand" "x")
16180 (match_operand:SF 3 "const0_operand" "X")))]
16184 (define_insn "*sse_movsfcc_const0_2"
16185 [(set (match_operand:SF 0 "register_operand" "=&x")
16186 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16187 [(match_operand:SF 4 "register_operand" "0")
16188 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16189 (match_operand:SF 2 "const0_operand" "X")
16190 (match_operand:SF 3 "register_operand" "x")))]
16194 (define_insn "*sse_movsfcc_const0_3"
16195 [(set (match_operand:SF 0 "register_operand" "=&x")
16196 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16197 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16198 (match_operand:SF 5 "register_operand" "0")])
16199 (match_operand:SF 2 "register_operand" "x")
16200 (match_operand:SF 3 "const0_operand" "X")))]
16204 (define_insn "*sse_movsfcc_const0_4"
16205 [(set (match_operand:SF 0 "register_operand" "=&x")
16206 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16207 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16208 (match_operand:SF 5 "register_operand" "0")])
16209 (match_operand:SF 2 "const0_operand" "X")
16210 (match_operand:SF 3 "register_operand" "x")))]
16214 (define_insn "*sse_movdfcc_const0_1"
16215 [(set (match_operand:DF 0 "register_operand" "=&Y")
16216 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16217 [(match_operand:DF 4 "register_operand" "0")
16218 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
16219 (match_operand:DF 2 "register_operand" "Y")
16220 (match_operand:DF 3 "const0_operand" "X")))]
16224 (define_insn "*sse_movdfcc_const0_2"
16225 [(set (match_operand:DF 0 "register_operand" "=&Y")
16226 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16227 [(match_operand:DF 4 "register_operand" "0")
16228 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
16229 (match_operand:DF 2 "const0_operand" "X")
16230 (match_operand:DF 3 "register_operand" "Y")))]
16234 (define_insn "*sse_movdfcc_const0_3"
16235 [(set (match_operand:DF 0 "register_operand" "=&Y")
16236 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16237 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
16238 (match_operand:DF 5 "register_operand" "0")])
16239 (match_operand:DF 2 "register_operand" "Y")
16240 (match_operand:DF 3 "const0_operand" "X")))]
16244 (define_insn "*sse_movdfcc_const0_4"
16245 [(set (match_operand:DF 0 "register_operand" "=&Y")
16246 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16247 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
16248 (match_operand:DF 5 "register_operand" "0")])
16249 (match_operand:DF 2 "const0_operand" "X")
16250 (match_operand:DF 3 "register_operand" "Y")))]
16255 [(set (match_operand 0 "register_operand" "")
16256 (if_then_else (match_operator 1 "comparison_operator"
16257 [(match_operand 4 "register_operand" "")
16258 (match_operand 5 "nonimmediate_operand" "")])
16259 (match_operand 2 "nonmemory_operand" "")
16260 (match_operand 3 "nonmemory_operand" "")))]
16261 "SSE_REG_P (operands[0]) && reload_completed
16262 && (const0_operand (operands[2], GET_MODE (operands[0]))
16263 || const0_operand (operands[3], GET_MODE (operands[0])))"
16264 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16265 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16266 (subreg:TI (match_dup 7) 0)))]
16268 PUT_MODE (operands[1], GET_MODE (operands[0]));
16269 if (!sse_comparison_operator (operands[1], VOIDmode))
16271 rtx tmp = operands[5];
16272 operands[5] = operands[4];
16274 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16276 if (const0_operand (operands[2], GET_MODE (operands[0])))
16278 operands[7] = operands[3];
16279 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16284 operands[7] = operands[2];
16285 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16289 (define_expand "allocate_stack_worker"
16290 [(match_operand:SI 0 "register_operand" "")]
16291 "TARGET_STACK_PROBE"
16294 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16296 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16300 (define_insn "allocate_stack_worker_1"
16301 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16302 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16303 (clobber (match_dup 0))
16304 (clobber (reg:CC 17))]
16305 "!TARGET_64BIT && TARGET_STACK_PROBE"
16307 [(set_attr "type" "multi")
16308 (set_attr "length" "5")])
16310 (define_insn "allocate_stack_worker_rex64"
16311 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16312 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16313 (clobber (match_dup 0))
16314 (clobber (reg:CC 17))]
16315 "TARGET_64BIT && TARGET_STACK_PROBE"
16317 [(set_attr "type" "multi")
16318 (set_attr "length" "5")])
16320 (define_expand "allocate_stack"
16321 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16322 (minus:SI (reg:SI 7)
16323 (match_operand:SI 1 "general_operand" "")))
16324 (clobber (reg:CC 17))])
16325 (parallel [(set (reg:SI 7)
16326 (minus:SI (reg:SI 7) (match_dup 1)))
16327 (clobber (reg:CC 17))])]
16328 "TARGET_STACK_PROBE"
16330 #ifdef CHECK_STACK_LIMIT
16331 if (GET_CODE (operands[1]) == CONST_INT
16332 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16333 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16337 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16340 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16344 (define_expand "builtin_setjmp_receiver"
16345 [(label_ref (match_operand 0 "" ""))]
16346 "!TARGET_64BIT && flag_pic"
16348 emit_insn (gen_set_got (pic_offset_table_rtx));
16352 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16355 [(set (match_operand 0 "register_operand" "")
16356 (match_operator 3 "promotable_binary_operator"
16357 [(match_operand 1 "register_operand" "")
16358 (match_operand 2 "aligned_operand" "")]))
16359 (clobber (reg:CC 17))]
16360 "! TARGET_PARTIAL_REG_STALL && reload_completed
16361 && ((GET_MODE (operands[0]) == HImode
16362 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
16363 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16364 || (GET_MODE (operands[0]) == QImode
16365 && (TARGET_PROMOTE_QImode || optimize_size)))"
16366 [(parallel [(set (match_dup 0)
16367 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16368 (clobber (reg:CC 17))])]
16369 "operands[0] = gen_lowpart (SImode, operands[0]);
16370 operands[1] = gen_lowpart (SImode, operands[1]);
16371 if (GET_CODE (operands[3]) != ASHIFT)
16372 operands[2] = gen_lowpart (SImode, operands[2]);
16373 PUT_MODE (operands[3], SImode);")
16377 (compare (and (match_operand 1 "aligned_operand" "")
16378 (match_operand 2 "const_int_operand" ""))
16380 (set (match_operand 0 "register_operand" "")
16381 (and (match_dup 1) (match_dup 2)))]
16382 "! TARGET_PARTIAL_REG_STALL && reload_completed
16383 && ix86_match_ccmode (insn, CCNOmode)
16384 && (GET_MODE (operands[0]) == HImode
16385 || (GET_MODE (operands[0]) == QImode
16386 && (TARGET_PROMOTE_QImode || optimize_size)))"
16387 [(parallel [(set (reg:CCNO 17)
16388 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16391 (and:SI (match_dup 1) (match_dup 2)))])]
16393 = gen_int_mode (INTVAL (operands[2])
16394 & GET_MODE_MASK (GET_MODE (operands[0])),
16396 operands[0] = gen_lowpart (SImode, operands[0]);
16397 operands[1] = gen_lowpart (SImode, operands[1]);")
16401 (compare (and (match_operand 0 "aligned_operand" "")
16402 (match_operand 1 "const_int_operand" ""))
16404 "! TARGET_PARTIAL_REG_STALL && reload_completed
16405 && ix86_match_ccmode (insn, CCNOmode)
16406 && (GET_MODE (operands[0]) == HImode
16407 || (GET_MODE (operands[0]) == QImode
16408 && (TARGET_PROMOTE_QImode || optimize_size)))"
16409 [(set (reg:CCNO 17)
16410 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16413 = gen_int_mode (INTVAL (operands[1])
16414 & GET_MODE_MASK (GET_MODE (operands[0])),
16416 operands[0] = gen_lowpart (SImode, operands[0]);")
16419 [(set (match_operand 0 "register_operand" "")
16420 (neg (match_operand 1 "register_operand" "")))
16421 (clobber (reg:CC 17))]
16422 "! TARGET_PARTIAL_REG_STALL && reload_completed
16423 && (GET_MODE (operands[0]) == HImode
16424 || (GET_MODE (operands[0]) == QImode
16425 && (TARGET_PROMOTE_QImode || optimize_size)))"
16426 [(parallel [(set (match_dup 0)
16427 (neg:SI (match_dup 1)))
16428 (clobber (reg:CC 17))])]
16429 "operands[0] = gen_lowpart (SImode, operands[0]);
16430 operands[1] = gen_lowpart (SImode, operands[1]);")
16433 [(set (match_operand 0 "register_operand" "")
16434 (not (match_operand 1 "register_operand" "")))]
16435 "! TARGET_PARTIAL_REG_STALL && reload_completed
16436 && (GET_MODE (operands[0]) == HImode
16437 || (GET_MODE (operands[0]) == QImode
16438 && (TARGET_PROMOTE_QImode || optimize_size)))"
16439 [(set (match_dup 0)
16440 (not:SI (match_dup 1)))]
16441 "operands[0] = gen_lowpart (SImode, operands[0]);
16442 operands[1] = gen_lowpart (SImode, operands[1]);")
16445 [(set (match_operand 0 "register_operand" "")
16446 (if_then_else (match_operator 1 "comparison_operator"
16447 [(reg 17) (const_int 0)])
16448 (match_operand 2 "register_operand" "")
16449 (match_operand 3 "register_operand" "")))]
16450 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16451 && (GET_MODE (operands[0]) == HImode
16452 || (GET_MODE (operands[0]) == QImode
16453 && (TARGET_PROMOTE_QImode || optimize_size)))"
16454 [(set (match_dup 0)
16455 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16456 "operands[0] = gen_lowpart (SImode, operands[0]);
16457 operands[2] = gen_lowpart (SImode, operands[2]);
16458 operands[3] = gen_lowpart (SImode, operands[3]);")
16461 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16462 ;; transform a complex memory operation into two memory to register operations.
16464 ;; Don't push memory operands
16466 [(set (match_operand:SI 0 "push_operand" "")
16467 (match_operand:SI 1 "memory_operand" ""))
16468 (match_scratch:SI 2 "r")]
16469 "! optimize_size && ! TARGET_PUSH_MEMORY"
16470 [(set (match_dup 2) (match_dup 1))
16471 (set (match_dup 0) (match_dup 2))]
16475 [(set (match_operand:DI 0 "push_operand" "")
16476 (match_operand:DI 1 "memory_operand" ""))
16477 (match_scratch:DI 2 "r")]
16478 "! optimize_size && ! TARGET_PUSH_MEMORY"
16479 [(set (match_dup 2) (match_dup 1))
16480 (set (match_dup 0) (match_dup 2))]
16483 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16486 [(set (match_operand:SF 0 "push_operand" "")
16487 (match_operand:SF 1 "memory_operand" ""))
16488 (match_scratch:SF 2 "r")]
16489 "! optimize_size && ! TARGET_PUSH_MEMORY"
16490 [(set (match_dup 2) (match_dup 1))
16491 (set (match_dup 0) (match_dup 2))]
16495 [(set (match_operand:HI 0 "push_operand" "")
16496 (match_operand:HI 1 "memory_operand" ""))
16497 (match_scratch:HI 2 "r")]
16498 "! optimize_size && ! TARGET_PUSH_MEMORY"
16499 [(set (match_dup 2) (match_dup 1))
16500 (set (match_dup 0) (match_dup 2))]
16504 [(set (match_operand:QI 0 "push_operand" "")
16505 (match_operand:QI 1 "memory_operand" ""))
16506 (match_scratch:QI 2 "q")]
16507 "! optimize_size && ! TARGET_PUSH_MEMORY"
16508 [(set (match_dup 2) (match_dup 1))
16509 (set (match_dup 0) (match_dup 2))]
16512 ;; Don't move an immediate directly to memory when the instruction
16515 [(match_scratch:SI 1 "r")
16516 (set (match_operand:SI 0 "memory_operand" "")
16519 && ! TARGET_USE_MOV0
16520 && TARGET_SPLIT_LONG_MOVES
16521 && get_attr_length (insn) >= ix86_cost->large_insn
16522 && peep2_regno_dead_p (0, FLAGS_REG)"
16523 [(parallel [(set (match_dup 1) (const_int 0))
16524 (clobber (reg:CC 17))])
16525 (set (match_dup 0) (match_dup 1))]
16529 [(match_scratch:HI 1 "r")
16530 (set (match_operand:HI 0 "memory_operand" "")
16533 && ! TARGET_USE_MOV0
16534 && TARGET_SPLIT_LONG_MOVES
16535 && get_attr_length (insn) >= ix86_cost->large_insn
16536 && peep2_regno_dead_p (0, FLAGS_REG)"
16537 [(parallel [(set (match_dup 2) (const_int 0))
16538 (clobber (reg:CC 17))])
16539 (set (match_dup 0) (match_dup 1))]
16540 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16543 [(match_scratch:QI 1 "q")
16544 (set (match_operand:QI 0 "memory_operand" "")
16547 && ! TARGET_USE_MOV0
16548 && TARGET_SPLIT_LONG_MOVES
16549 && get_attr_length (insn) >= ix86_cost->large_insn
16550 && peep2_regno_dead_p (0, FLAGS_REG)"
16551 [(parallel [(set (match_dup 2) (const_int 0))
16552 (clobber (reg:CC 17))])
16553 (set (match_dup 0) (match_dup 1))]
16554 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16557 [(match_scratch:SI 2 "r")
16558 (set (match_operand:SI 0 "memory_operand" "")
16559 (match_operand:SI 1 "immediate_operand" ""))]
16561 && get_attr_length (insn) >= ix86_cost->large_insn
16562 && TARGET_SPLIT_LONG_MOVES"
16563 [(set (match_dup 2) (match_dup 1))
16564 (set (match_dup 0) (match_dup 2))]
16568 [(match_scratch:HI 2 "r")
16569 (set (match_operand:HI 0 "memory_operand" "")
16570 (match_operand:HI 1 "immediate_operand" ""))]
16571 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16572 && TARGET_SPLIT_LONG_MOVES"
16573 [(set (match_dup 2) (match_dup 1))
16574 (set (match_dup 0) (match_dup 2))]
16578 [(match_scratch:QI 2 "q")
16579 (set (match_operand:QI 0 "memory_operand" "")
16580 (match_operand:QI 1 "immediate_operand" ""))]
16581 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16582 && TARGET_SPLIT_LONG_MOVES"
16583 [(set (match_dup 2) (match_dup 1))
16584 (set (match_dup 0) (match_dup 2))]
16587 ;; Don't compare memory with zero, load and use a test instead.
16590 (compare (match_operand:SI 0 "memory_operand" "")
16592 (match_scratch:SI 3 "r")]
16593 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
16594 [(set (match_dup 3) (match_dup 0))
16595 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
16598 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16599 ;; Don't split NOTs with a displacement operand, because resulting XOR
16600 ;; will not be pariable anyway.
16602 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
16603 ;; represented using a modRM byte. The XOR replacement is long decoded,
16604 ;; so this split helps here as well.
16606 ;; Note: Can't do this as a regular split because we can't get proper
16607 ;; lifetime information then.
16610 [(set (match_operand:SI 0 "nonimmediate_operand" "")
16611 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
16613 && peep2_regno_dead_p (0, FLAGS_REG)
16614 && ((TARGET_PENTIUM
16615 && (GET_CODE (operands[0]) != MEM
16616 || !memory_displacement_operand (operands[0], SImode)))
16617 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
16618 [(parallel [(set (match_dup 0)
16619 (xor:SI (match_dup 1) (const_int -1)))
16620 (clobber (reg:CC 17))])]
16624 [(set (match_operand:HI 0 "nonimmediate_operand" "")
16625 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
16627 && peep2_regno_dead_p (0, FLAGS_REG)
16628 && ((TARGET_PENTIUM
16629 && (GET_CODE (operands[0]) != MEM
16630 || !memory_displacement_operand (operands[0], HImode)))
16631 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
16632 [(parallel [(set (match_dup 0)
16633 (xor:HI (match_dup 1) (const_int -1)))
16634 (clobber (reg:CC 17))])]
16638 [(set (match_operand:QI 0 "nonimmediate_operand" "")
16639 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
16641 && peep2_regno_dead_p (0, FLAGS_REG)
16642 && ((TARGET_PENTIUM
16643 && (GET_CODE (operands[0]) != MEM
16644 || !memory_displacement_operand (operands[0], QImode)))
16645 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
16646 [(parallel [(set (match_dup 0)
16647 (xor:QI (match_dup 1) (const_int -1)))
16648 (clobber (reg:CC 17))])]
16651 ;; Non pairable "test imm, reg" instructions can be translated to
16652 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
16653 ;; byte opcode instead of two, have a short form for byte operands),
16654 ;; so do it for other CPUs as well. Given that the value was dead,
16655 ;; this should not create any new dependencies. Pass on the sub-word
16656 ;; versions if we're concerned about partial register stalls.
16660 (compare (and:SI (match_operand:SI 0 "register_operand" "")
16661 (match_operand:SI 1 "immediate_operand" ""))
16663 "ix86_match_ccmode (insn, CCNOmode)
16664 && (true_regnum (operands[0]) != 0
16665 || (GET_CODE (operands[1]) == CONST_INT
16666 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
16667 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16669 [(set (reg:CCNO 17)
16670 (compare:CCNO (and:SI (match_dup 0)
16674 (and:SI (match_dup 0) (match_dup 1)))])]
16677 ;; We don't need to handle HImode case, because it will be promoted to SImode
16678 ;; on ! TARGET_PARTIAL_REG_STALL
16682 (compare (and:QI (match_operand:QI 0 "register_operand" "")
16683 (match_operand:QI 1 "immediate_operand" ""))
16685 "! TARGET_PARTIAL_REG_STALL
16686 && ix86_match_ccmode (insn, CCNOmode)
16687 && true_regnum (operands[0]) != 0
16688 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16690 [(set (reg:CCNO 17)
16691 (compare:CCNO (and:QI (match_dup 0)
16695 (and:QI (match_dup 0) (match_dup 1)))])]
16703 (match_operand 0 "ext_register_operand" "")
16706 (match_operand 1 "const_int_operand" ""))
16708 "! TARGET_PARTIAL_REG_STALL
16709 && ix86_match_ccmode (insn, CCNOmode)
16710 && true_regnum (operands[0]) != 0
16711 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16712 [(parallel [(set (reg:CCNO 17)
16721 (set (zero_extract:SI (match_dup 0)
16732 ;; Don't do logical operations with memory inputs.
16734 [(match_scratch:SI 2 "r")
16735 (parallel [(set (match_operand:SI 0 "register_operand" "")
16736 (match_operator:SI 3 "arith_or_logical_operator"
16738 (match_operand:SI 1 "memory_operand" "")]))
16739 (clobber (reg:CC 17))])]
16740 "! optimize_size && ! TARGET_READ_MODIFY"
16741 [(set (match_dup 2) (match_dup 1))
16742 (parallel [(set (match_dup 0)
16743 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
16744 (clobber (reg:CC 17))])]
16748 [(match_scratch:SI 2 "r")
16749 (parallel [(set (match_operand:SI 0 "register_operand" "")
16750 (match_operator:SI 3 "arith_or_logical_operator"
16751 [(match_operand:SI 1 "memory_operand" "")
16753 (clobber (reg:CC 17))])]
16754 "! optimize_size && ! TARGET_READ_MODIFY"
16755 [(set (match_dup 2) (match_dup 1))
16756 (parallel [(set (match_dup 0)
16757 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
16758 (clobber (reg:CC 17))])]
16761 ; Don't do logical operations with memory outputs
16763 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
16764 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
16765 ; the same decoder scheduling characteristics as the original.
16768 [(match_scratch:SI 2 "r")
16769 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16770 (match_operator:SI 3 "arith_or_logical_operator"
16772 (match_operand:SI 1 "nonmemory_operand" "")]))
16773 (clobber (reg:CC 17))])]
16774 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16775 [(set (match_dup 2) (match_dup 0))
16776 (parallel [(set (match_dup 2)
16777 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
16778 (clobber (reg:CC 17))])
16779 (set (match_dup 0) (match_dup 2))]
16783 [(match_scratch:SI 2 "r")
16784 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16785 (match_operator:SI 3 "arith_or_logical_operator"
16786 [(match_operand:SI 1 "nonmemory_operand" "")
16788 (clobber (reg:CC 17))])]
16789 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16790 [(set (match_dup 2) (match_dup 0))
16791 (parallel [(set (match_dup 2)
16792 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16793 (clobber (reg:CC 17))])
16794 (set (match_dup 0) (match_dup 2))]
16797 ;; Attempt to always use XOR for zeroing registers.
16799 [(set (match_operand 0 "register_operand" "")
16801 "(GET_MODE (operands[0]) == QImode
16802 || GET_MODE (operands[0]) == HImode
16803 || GET_MODE (operands[0]) == SImode
16804 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16805 && (! TARGET_USE_MOV0 || optimize_size)
16806 && peep2_regno_dead_p (0, FLAGS_REG)"
16807 [(parallel [(set (match_dup 0) (const_int 0))
16808 (clobber (reg:CC 17))])]
16809 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16810 true_regnum (operands[0]));")
16813 [(set (strict_low_part (match_operand 0 "register_operand" ""))
16815 "(GET_MODE (operands[0]) == QImode
16816 || GET_MODE (operands[0]) == HImode)
16817 && (! TARGET_USE_MOV0 || optimize_size)
16818 && peep2_regno_dead_p (0, FLAGS_REG)"
16819 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
16820 (clobber (reg:CC 17))])])
16822 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
16824 [(set (match_operand 0 "register_operand" "")
16826 "(GET_MODE (operands[0]) == HImode
16827 || GET_MODE (operands[0]) == SImode
16828 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16829 && (optimize_size || TARGET_PENTIUM)
16830 && peep2_regno_dead_p (0, FLAGS_REG)"
16831 [(parallel [(set (match_dup 0) (const_int -1))
16832 (clobber (reg:CC 17))])]
16833 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16834 true_regnum (operands[0]));")
16836 ;; Attempt to convert simple leas to adds. These can be created by
16839 [(set (match_operand:SI 0 "register_operand" "")
16840 (plus:SI (match_dup 0)
16841 (match_operand:SI 1 "nonmemory_operand" "")))]
16842 "peep2_regno_dead_p (0, FLAGS_REG)"
16843 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
16844 (clobber (reg:CC 17))])]
16848 [(set (match_operand:SI 0 "register_operand" "")
16849 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
16850 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
16851 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
16852 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
16853 (clobber (reg:CC 17))])]
16854 "operands[2] = gen_lowpart (SImode, operands[2]);")
16857 [(set (match_operand:DI 0 "register_operand" "")
16858 (plus:DI (match_dup 0)
16859 (match_operand:DI 1 "x86_64_general_operand" "")))]
16860 "peep2_regno_dead_p (0, FLAGS_REG)"
16861 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
16862 (clobber (reg:CC 17))])]
16866 [(set (match_operand:SI 0 "register_operand" "")
16867 (mult:SI (match_dup 0)
16868 (match_operand:SI 1 "const_int_operand" "")))]
16869 "exact_log2 (INTVAL (operands[1])) >= 0
16870 && peep2_regno_dead_p (0, FLAGS_REG)"
16871 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16872 (clobber (reg:CC 17))])]
16873 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16876 [(set (match_operand:DI 0 "register_operand" "")
16877 (mult:DI (match_dup 0)
16878 (match_operand:DI 1 "const_int_operand" "")))]
16879 "exact_log2 (INTVAL (operands[1])) >= 0
16880 && peep2_regno_dead_p (0, FLAGS_REG)"
16881 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
16882 (clobber (reg:CC 17))])]
16883 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16886 [(set (match_operand:SI 0 "register_operand" "")
16887 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
16888 (match_operand:DI 2 "const_int_operand" "")) 0))]
16889 "exact_log2 (INTVAL (operands[1])) >= 0
16890 && REGNO (operands[0]) == REGNO (operands[1])
16891 && peep2_regno_dead_p (0, FLAGS_REG)"
16892 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16893 (clobber (reg:CC 17))])]
16894 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
16896 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
16897 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
16898 ;; many CPUs it is also faster, since special hardware to avoid esp
16899 ;; dependencies is present.
16901 ;; While some of these conversions may be done using splitters, we use peepholes
16902 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
16904 ;; Convert prologue esp subtractions to push.
16905 ;; We need register to push. In order to keep verify_flow_info happy we have
16907 ;; - use scratch and clobber it in order to avoid dependencies
16908 ;; - use already live register
16909 ;; We can't use the second way right now, since there is no reliable way how to
16910 ;; verify that given register is live. First choice will also most likely in
16911 ;; fewer dependencies. On the place of esp adjustments it is very likely that
16912 ;; call clobbered registers are dead. We may want to use base pointer as an
16913 ;; alternative when no register is available later.
16916 [(match_scratch:SI 0 "r")
16917 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
16918 (clobber (reg:CC 17))
16919 (clobber (mem:BLK (scratch)))])]
16920 "optimize_size || !TARGET_SUB_ESP_4"
16921 [(clobber (match_dup 0))
16922 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16923 (clobber (mem:BLK (scratch)))])])
16926 [(match_scratch:SI 0 "r")
16927 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
16928 (clobber (reg:CC 17))
16929 (clobber (mem:BLK (scratch)))])]
16930 "optimize_size || !TARGET_SUB_ESP_8"
16931 [(clobber (match_dup 0))
16932 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16933 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16934 (clobber (mem:BLK (scratch)))])])
16936 ;; Convert esp subtractions to push.
16938 [(match_scratch:SI 0 "r")
16939 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
16940 (clobber (reg:CC 17))])]
16941 "optimize_size || !TARGET_SUB_ESP_4"
16942 [(clobber (match_dup 0))
16943 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
16946 [(match_scratch:SI 0 "r")
16947 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
16948 (clobber (reg:CC 17))])]
16949 "optimize_size || !TARGET_SUB_ESP_8"
16950 [(clobber (match_dup 0))
16951 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16952 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
16954 ;; Convert epilogue deallocator to pop.
16956 [(match_scratch:SI 0 "r")
16957 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16958 (clobber (reg:CC 17))
16959 (clobber (mem:BLK (scratch)))])]
16960 "optimize_size || !TARGET_ADD_ESP_4"
16961 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16962 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16963 (clobber (mem:BLK (scratch)))])]
16966 ;; Two pops case is tricky, since pop causes dependency on destination register.
16967 ;; We use two registers if available.
16969 [(match_scratch:SI 0 "r")
16970 (match_scratch:SI 1 "r")
16971 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
16972 (clobber (reg:CC 17))
16973 (clobber (mem:BLK (scratch)))])]
16974 "optimize_size || !TARGET_ADD_ESP_8"
16975 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16976 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16977 (clobber (mem:BLK (scratch)))])
16978 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
16979 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
16983 [(match_scratch:SI 0 "r")
16984 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
16985 (clobber (reg:CC 17))
16986 (clobber (mem:BLK (scratch)))])]
16988 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16989 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16990 (clobber (mem:BLK (scratch)))])
16991 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16992 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
16995 ;; Convert esp additions to pop.
16997 [(match_scratch:SI 0 "r")
16998 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16999 (clobber (reg:CC 17))])]
17001 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17002 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17005 ;; Two pops case is tricky, since pop causes dependency on destination register.
17006 ;; We use two registers if available.
17008 [(match_scratch:SI 0 "r")
17009 (match_scratch:SI 1 "r")
17010 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17011 (clobber (reg:CC 17))])]
17013 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17014 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17015 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17016 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17020 [(match_scratch:SI 0 "r")
17021 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17022 (clobber (reg:CC 17))])]
17024 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17025 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17026 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17027 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17030 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17031 ;; required and register dies.
17034 (compare (match_operand:SI 0 "register_operand" "")
17035 (match_operand:SI 1 "incdec_operand" "")))]
17036 "ix86_match_ccmode (insn, CCGCmode)
17037 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17038 [(parallel [(set (reg:CCGC 17)
17039 (compare:CCGC (match_dup 0)
17041 (clobber (match_dup 0))])]
17046 (compare (match_operand:HI 0 "register_operand" "")
17047 (match_operand:HI 1 "incdec_operand" "")))]
17048 "ix86_match_ccmode (insn, CCGCmode)
17049 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17050 [(parallel [(set (reg:CCGC 17)
17051 (compare:CCGC (match_dup 0)
17053 (clobber (match_dup 0))])]
17058 (compare (match_operand:QI 0 "register_operand" "")
17059 (match_operand:QI 1 "incdec_operand" "")))]
17060 "ix86_match_ccmode (insn, CCGCmode)
17061 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17062 [(parallel [(set (reg:CCGC 17)
17063 (compare:CCGC (match_dup 0)
17065 (clobber (match_dup 0))])]
17068 ;; Convert compares with 128 to shorter add -128
17071 (compare (match_operand:SI 0 "register_operand" "")
17073 "ix86_match_ccmode (insn, CCGCmode)
17074 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17075 [(parallel [(set (reg:CCGC 17)
17076 (compare:CCGC (match_dup 0)
17078 (clobber (match_dup 0))])]
17083 (compare (match_operand:HI 0 "register_operand" "")
17085 "ix86_match_ccmode (insn, CCGCmode)
17086 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17087 [(parallel [(set (reg:CCGC 17)
17088 (compare:CCGC (match_dup 0)
17090 (clobber (match_dup 0))])]
17094 [(match_scratch:DI 0 "r")
17095 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17096 (clobber (reg:CC 17))
17097 (clobber (mem:BLK (scratch)))])]
17098 "optimize_size || !TARGET_SUB_ESP_4"
17099 [(clobber (match_dup 0))
17100 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17101 (clobber (mem:BLK (scratch)))])])
17104 [(match_scratch:DI 0 "r")
17105 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17106 (clobber (reg:CC 17))
17107 (clobber (mem:BLK (scratch)))])]
17108 "optimize_size || !TARGET_SUB_ESP_8"
17109 [(clobber (match_dup 0))
17110 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17111 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17112 (clobber (mem:BLK (scratch)))])])
17114 ;; Convert esp subtractions to push.
17116 [(match_scratch:DI 0 "r")
17117 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17118 (clobber (reg:CC 17))])]
17119 "optimize_size || !TARGET_SUB_ESP_4"
17120 [(clobber (match_dup 0))
17121 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17124 [(match_scratch:DI 0 "r")
17125 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17126 (clobber (reg:CC 17))])]
17127 "optimize_size || !TARGET_SUB_ESP_8"
17128 [(clobber (match_dup 0))
17129 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17130 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17132 ;; Convert epilogue deallocator to pop.
17134 [(match_scratch:DI 0 "r")
17135 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17136 (clobber (reg:CC 17))
17137 (clobber (mem:BLK (scratch)))])]
17138 "optimize_size || !TARGET_ADD_ESP_4"
17139 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17140 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17141 (clobber (mem:BLK (scratch)))])]
17144 ;; Two pops case is tricky, since pop causes dependency on destination register.
17145 ;; We use two registers if available.
17147 [(match_scratch:DI 0 "r")
17148 (match_scratch:DI 1 "r")
17149 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17150 (clobber (reg:CC 17))
17151 (clobber (mem:BLK (scratch)))])]
17152 "optimize_size || !TARGET_ADD_ESP_8"
17153 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17154 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17155 (clobber (mem:BLK (scratch)))])
17156 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17157 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17161 [(match_scratch:DI 0 "r")
17162 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17163 (clobber (reg:CC 17))
17164 (clobber (mem:BLK (scratch)))])]
17166 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17167 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17168 (clobber (mem:BLK (scratch)))])
17169 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17170 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17173 ;; Convert esp additions to pop.
17175 [(match_scratch:DI 0 "r")
17176 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17177 (clobber (reg:CC 17))])]
17179 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17180 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17183 ;; Two pops case is tricky, since pop causes dependency on destination register.
17184 ;; We use two registers if available.
17186 [(match_scratch:DI 0 "r")
17187 (match_scratch:DI 1 "r")
17188 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17189 (clobber (reg:CC 17))])]
17191 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17192 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17193 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17194 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17198 [(match_scratch:DI 0 "r")
17199 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17200 (clobber (reg:CC 17))])]
17202 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17203 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17204 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17205 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17208 ;; Call-value patterns last so that the wildcard operand does not
17209 ;; disrupt insn-recog's switch tables.
17211 (define_insn "*call_value_pop_0"
17212 [(set (match_operand 0 "" "")
17213 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17214 (match_operand:SI 2 "" "")))
17215 (set (reg:SI 7) (plus:SI (reg:SI 7)
17216 (match_operand:SI 3 "immediate_operand" "")))]
17219 if (SIBLING_CALL_P (insn))
17222 return "call\t%P1";
17224 [(set_attr "type" "callv")])
17226 (define_insn "*call_value_pop_1"
17227 [(set (match_operand 0 "" "")
17228 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17229 (match_operand:SI 2 "" "")))
17230 (set (reg:SI 7) (plus:SI (reg:SI 7)
17231 (match_operand:SI 3 "immediate_operand" "i")))]
17234 if (constant_call_address_operand (operands[1], QImode))
17236 if (SIBLING_CALL_P (insn))
17239 return "call\t%P1";
17241 if (SIBLING_CALL_P (insn))
17244 return "call\t%A1";
17246 [(set_attr "type" "callv")])
17248 (define_insn "*call_value_0"
17249 [(set (match_operand 0 "" "")
17250 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17251 (match_operand:SI 2 "" "")))]
17254 if (SIBLING_CALL_P (insn))
17257 return "call\t%P1";
17259 [(set_attr "type" "callv")])
17261 (define_insn "*call_value_0_rex64"
17262 [(set (match_operand 0 "" "")
17263 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17264 (match_operand:DI 2 "const_int_operand" "")))]
17267 if (SIBLING_CALL_P (insn))
17270 return "call\t%P1";
17272 [(set_attr "type" "callv")])
17274 (define_insn "*call_value_1"
17275 [(set (match_operand 0 "" "")
17276 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17277 (match_operand:SI 2 "" "")))]
17280 if (constant_call_address_operand (operands[1], QImode))
17282 if (SIBLING_CALL_P (insn))
17285 return "call\t%P1";
17287 if (SIBLING_CALL_P (insn))
17288 return "jmp\t%*%1";
17290 return "call\t%*%1";
17292 [(set_attr "type" "callv")])
17294 (define_insn "*call_value_1_rex64"
17295 [(set (match_operand 0 "" "")
17296 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17297 (match_operand:DI 2 "" "")))]
17300 if (constant_call_address_operand (operands[1], QImode))
17302 if (SIBLING_CALL_P (insn))
17305 return "call\t%P1";
17307 if (SIBLING_CALL_P (insn))
17310 return "call\t%A1";
17312 [(set_attr "type" "callv")])
17314 (define_insn "trap"
17315 [(trap_if (const_int 1) (const_int 5))]
17319 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17320 ;;; for the sake of bounds checking. By emitting bounds checks as
17321 ;;; conditional traps rather than as conditional jumps around
17322 ;;; unconditional traps we avoid introducing spurious basic-block
17323 ;;; boundaries and facilitate elimination of redundant checks. In
17324 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17327 ;;; FIXME: Static branch prediction rules for ix86 are such that
17328 ;;; forward conditional branches predict as untaken. As implemented
17329 ;;; below, pseudo conditional traps violate that rule. We should use
17330 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17331 ;;; section loaded at the end of the text segment and branch forward
17332 ;;; there on bounds-failure, and then jump back immediately (in case
17333 ;;; the system chooses to ignore bounds violations, or to report
17334 ;;; violations and continue execution).
17336 (define_expand "conditional_trap"
17337 [(trap_if (match_operator 0 "comparison_operator"
17338 [(match_dup 2) (const_int 0)])
17339 (match_operand 1 "const_int_operand" ""))]
17342 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17343 ix86_expand_compare (GET_CODE (operands[0]),
17349 (define_insn "*conditional_trap_1"
17350 [(trap_if (match_operator 0 "comparison_operator"
17351 [(reg 17) (const_int 0)])
17352 (match_operand 1 "const_int_operand" ""))]
17355 operands[2] = gen_label_rtx ();
17356 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
17357 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
17358 CODE_LABEL_NUMBER (operands[2]));
17362 ;; Pentium III SIMD instructions.
17364 ;; Moves for SSE/MMX regs.
17366 (define_insn "movv4sf_internal"
17367 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17368 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x"))]
17370 ;; @@@ let's try to use movaps here.
17371 "movaps\t{%1, %0|%0, %1}"
17372 [(set_attr "type" "ssemov")
17373 (set_attr "mode" "V4SF")])
17375 (define_insn "movv4si_internal"
17376 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17377 (match_operand:V4SI 1 "nonimmediate_operand" "xm,x"))]
17379 ;; @@@ let's try to use movaps here.
17380 "movaps\t{%1, %0|%0, %1}"
17381 [(set_attr "type" "ssemov")
17382 (set_attr "mode" "V4SF")])
17384 (define_insn "movv8qi_internal"
17385 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17386 (match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
17388 "movq\t{%1, %0|%0, %1}"
17389 [(set_attr "type" "mmxmov")
17390 (set_attr "mode" "DI")])
17392 (define_insn "movv4hi_internal"
17393 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17394 (match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
17396 "movq\t{%1, %0|%0, %1}"
17397 [(set_attr "type" "mmxmov")
17398 (set_attr "mode" "DI")])
17400 (define_insn "movv2si_internal"
17401 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17402 (match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
17404 "movq\t{%1, %0|%0, %1}"
17405 [(set_attr "type" "mmxcvt")
17406 (set_attr "mode" "DI")])
17408 (define_insn "movv2sf_internal"
17409 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
17410 (match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
17412 "movq\\t{%1, %0|%0, %1}"
17413 [(set_attr "type" "mmxcvt")
17414 (set_attr "mode" "DI")])
17416 (define_expand "movti"
17417 [(set (match_operand:TI 0 "general_operand" "")
17418 (match_operand:TI 1 "general_operand" ""))]
17419 "TARGET_SSE || TARGET_64BIT"
17422 ix86_expand_move (TImode, operands);
17424 ix86_expand_vector_move (TImode, operands);
17428 (define_insn "movv2df_internal"
17429 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
17430 (match_operand:V2DF 1 "general_operand" "xm,x"))]
17432 ;; @@@ let's try to use movaps here.
17433 "movapd\t{%1, %0|%0, %1}"
17434 [(set_attr "type" "ssemov")
17435 (set_attr "mode" "V2DF")])
17437 (define_insn "movv8hi_internal"
17438 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
17439 (match_operand:V8HI 1 "general_operand" "xm,x"))]
17441 ;; @@@ let's try to use movaps here.
17442 "movaps\t{%1, %0|%0, %1}"
17443 [(set_attr "type" "ssemov")
17444 (set_attr "mode" "V4SF")])
17446 (define_insn "movv16qi_internal"
17447 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
17448 (match_operand:V16QI 1 "general_operand" "xm,x"))]
17450 ;; @@@ let's try to use movaps here.
17451 "movaps\t{%1, %0|%0, %1}"
17452 [(set_attr "type" "ssemov")
17453 (set_attr "mode" "V4SF")])
17455 (define_expand "movv2df"
17456 [(set (match_operand:V2DF 0 "general_operand" "")
17457 (match_operand:V2DF 1 "general_operand" ""))]
17460 ix86_expand_vector_move (V2DFmode, operands);
17464 (define_expand "movv8hi"
17465 [(set (match_operand:V8HI 0 "general_operand" "")
17466 (match_operand:V8HI 1 "general_operand" ""))]
17469 ix86_expand_vector_move (V8HImode, operands);
17473 (define_expand "movv16qi"
17474 [(set (match_operand:V16QI 0 "general_operand" "")
17475 (match_operand:V16QI 1 "general_operand" ""))]
17478 ix86_expand_vector_move (V16QImode, operands);
17482 (define_expand "movv4sf"
17483 [(set (match_operand:V4SF 0 "general_operand" "")
17484 (match_operand:V4SF 1 "general_operand" ""))]
17487 ix86_expand_vector_move (V4SFmode, operands);
17491 (define_expand "movv4si"
17492 [(set (match_operand:V4SI 0 "general_operand" "")
17493 (match_operand:V4SI 1 "general_operand" ""))]
17496 ix86_expand_vector_move (V4SImode, operands);
17500 (define_expand "movv2si"
17501 [(set (match_operand:V2SI 0 "general_operand" "")
17502 (match_operand:V2SI 1 "general_operand" ""))]
17505 ix86_expand_vector_move (V2SImode, operands);
17509 (define_expand "movv4hi"
17510 [(set (match_operand:V4HI 0 "general_operand" "")
17511 (match_operand:V4HI 1 "general_operand" ""))]
17514 ix86_expand_vector_move (V4HImode, operands);
17518 (define_expand "movv8qi"
17519 [(set (match_operand:V8QI 0 "general_operand" "")
17520 (match_operand:V8QI 1 "general_operand" ""))]
17523 ix86_expand_vector_move (V8QImode, operands);
17527 (define_expand "movv2sf"
17528 [(set (match_operand:V2SF 0 "general_operand" "")
17529 (match_operand:V2SF 1 "general_operand" ""))]
17532 ix86_expand_vector_move (V2SFmode, operands);
17536 (define_insn_and_split "*pushti"
17537 [(set (match_operand:TI 0 "push_operand" "=<")
17538 (match_operand:TI 1 "nonmemory_operand" "x"))]
17542 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17543 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17545 [(set_attr "type" "multi")])
17547 (define_insn_and_split "*pushv2df"
17548 [(set (match_operand:V2DF 0 "push_operand" "=<")
17549 (match_operand:V2DF 1 "nonmemory_operand" "x"))]
17553 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17554 (set (mem:V2DF (reg:SI 7)) (match_dup 1))]
17556 [(set_attr "type" "multi")])
17558 (define_insn_and_split "*pushv8hi"
17559 [(set (match_operand:V8HI 0 "push_operand" "=<")
17560 (match_operand:V8HI 1 "nonmemory_operand" "x"))]
17564 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17565 (set (mem:V8HI (reg:SI 7)) (match_dup 1))]
17567 [(set_attr "type" "multi")])
17569 (define_insn_and_split "*pushv16qi"
17570 [(set (match_operand:V16QI 0 "push_operand" "=<")
17571 (match_operand:V16QI 1 "nonmemory_operand" "x"))]
17575 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17576 (set (mem:V16QI (reg:SI 7)) (match_dup 1))]
17578 [(set_attr "type" "multi")])
17580 (define_insn_and_split "*pushv4sf"
17581 [(set (match_operand:V4SF 0 "push_operand" "=<")
17582 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
17586 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17587 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
17589 [(set_attr "type" "multi")])
17591 (define_insn_and_split "*pushv4si"
17592 [(set (match_operand:V4SI 0 "push_operand" "=<")
17593 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
17597 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17598 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
17600 [(set_attr "type" "multi")])
17602 (define_insn_and_split "*pushv2si"
17603 [(set (match_operand:V2SI 0 "push_operand" "=<")
17604 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
17608 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17609 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
17611 [(set_attr "type" "mmx")])
17613 (define_insn_and_split "*pushv4hi"
17614 [(set (match_operand:V4HI 0 "push_operand" "=<")
17615 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
17619 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17620 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
17622 [(set_attr "type" "mmx")])
17624 (define_insn_and_split "*pushv8qi"
17625 [(set (match_operand:V8QI 0 "push_operand" "=<")
17626 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
17630 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17631 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
17633 [(set_attr "type" "mmx")])
17635 (define_insn_and_split "*pushv2sf"
17636 [(set (match_operand:V2SF 0 "push_operand" "=<")
17637 (match_operand:V2SF 1 "nonmemory_operand" "y"))]
17641 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17642 (set (mem:V2SF (reg:SI 7)) (match_dup 1))]
17644 [(set_attr "type" "mmx")])
17646 (define_insn "movti_internal"
17647 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
17648 (match_operand:TI 1 "general_operand" "O,xm,x"))]
17649 "TARGET_SSE && !TARGET_64BIT"
17652 movaps\t{%1, %0|%0, %1}
17653 movaps\t{%1, %0|%0, %1}"
17654 [(set_attr "type" "ssemov,ssemov,ssemov")
17655 (set_attr "mode" "V4SF")])
17657 (define_insn "*movti_rex64"
17658 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
17659 (match_operand:TI 1 "general_operand" "riFo,riF,O,x,m"))]
17661 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17666 movaps\\t{%1, %0|%0, %1}
17667 movaps\\t{%1, %0|%0, %1}"
17668 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
17669 (set_attr "mode" "V4SF")])
17672 [(set (match_operand:TI 0 "nonimmediate_operand" "")
17673 (match_operand:TI 1 "general_operand" ""))]
17674 "reload_completed && !SSE_REG_P (operands[0])
17675 && !SSE_REG_P (operands[1])"
17677 "ix86_split_long_move (operands); DONE;")
17679 ;; These two patterns are useful for specifying exactly whether to use
17680 ;; movaps or movups
17681 (define_insn "sse_movaps"
17682 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17683 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
17687 movaps\t{%1, %0|%0, %1}
17688 movaps\t{%1, %0|%0, %1}"
17689 [(set_attr "type" "ssemov,ssemov")
17690 (set_attr "mode" "V4SF")])
17692 (define_insn "sse_movups"
17693 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17694 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
17698 movups\t{%1, %0|%0, %1}
17699 movups\t{%1, %0|%0, %1}"
17700 [(set_attr "type" "ssecvt,ssecvt")
17701 (set_attr "mode" "V4SF")])
17704 ;; SSE Strange Moves.
17706 (define_insn "sse_movmskps"
17707 [(set (match_operand:SI 0 "register_operand" "=r")
17708 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
17711 "movmskps\t{%1, %0|%0, %1}"
17712 [(set_attr "type" "ssecvt")
17713 (set_attr "mode" "V4SF")])
17715 (define_insn "mmx_pmovmskb"
17716 [(set (match_operand:SI 0 "register_operand" "=r")
17717 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
17719 "TARGET_SSE || TARGET_3DNOW_A"
17720 "pmovmskb\t{%1, %0|%0, %1}"
17721 [(set_attr "type" "ssecvt")
17722 (set_attr "mode" "V4SF")])
17725 (define_insn "mmx_maskmovq"
17726 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17727 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17728 (match_operand:V8QI 2 "register_operand" "y")]
17730 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
17731 ;; @@@ check ordering of operands in intel/nonintel syntax
17732 "maskmovq\t{%2, %1|%1, %2}"
17733 [(set_attr "type" "mmxcvt")
17734 (set_attr "mode" "DI")])
17736 (define_insn "mmx_maskmovq_rex"
17737 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
17738 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17739 (match_operand:V8QI 2 "register_operand" "y")]
17741 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
17742 ;; @@@ check ordering of operands in intel/nonintel syntax
17743 "maskmovq\t{%2, %1|%1, %2}"
17744 [(set_attr "type" "mmxcvt")
17745 (set_attr "mode" "DI")])
17747 (define_insn "sse_movntv4sf"
17748 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17749 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
17752 "movntps\t{%1, %0|%0, %1}"
17753 [(set_attr "type" "ssemov")
17754 (set_attr "mode" "V4SF")])
17756 (define_insn "sse_movntdi"
17757 [(set (match_operand:DI 0 "memory_operand" "=m")
17758 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
17760 "TARGET_SSE || TARGET_3DNOW_A"
17761 "movntq\t{%1, %0|%0, %1}"
17762 [(set_attr "type" "mmxmov")
17763 (set_attr "mode" "DI")])
17765 (define_insn "sse_movhlps"
17766 [(set (match_operand:V4SF 0 "register_operand" "=x")
17768 (match_operand:V4SF 1 "register_operand" "0")
17769 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17770 (parallel [(const_int 2)
17776 "movhlps\t{%2, %0|%0, %2}"
17777 [(set_attr "type" "ssecvt")
17778 (set_attr "mode" "V4SF")])
17780 (define_insn "sse_movlhps"
17781 [(set (match_operand:V4SF 0 "register_operand" "=x")
17783 (match_operand:V4SF 1 "register_operand" "0")
17784 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17785 (parallel [(const_int 2)
17791 "movlhps\t{%2, %0|%0, %2}"
17792 [(set_attr "type" "ssecvt")
17793 (set_attr "mode" "V4SF")])
17795 (define_insn "sse_movhps"
17796 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17798 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17799 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17802 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17803 "movhps\t{%2, %0|%0, %2}"
17804 [(set_attr "type" "ssecvt")
17805 (set_attr "mode" "V4SF")])
17807 (define_insn "sse_movlps"
17808 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17810 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17811 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17814 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17815 "movlps\t{%2, %0|%0, %2}"
17816 [(set_attr "type" "ssecvt")
17817 (set_attr "mode" "V4SF")])
17819 (define_insn "sse_loadss"
17820 [(set (match_operand:V4SF 0 "register_operand" "=x")
17822 (match_operand:V4SF 1 "memory_operand" "m")
17823 (vec_duplicate:V4SF (float:SF (const_int 0)))
17826 "movss\t{%1, %0|%0, %1}"
17827 [(set_attr "type" "ssemov")
17828 (set_attr "mode" "SF")])
17830 (define_insn "sse_movss"
17831 [(set (match_operand:V4SF 0 "register_operand" "=x")
17833 (match_operand:V4SF 1 "register_operand" "0")
17834 (match_operand:V4SF 2 "register_operand" "x")
17837 "movss\t{%2, %0|%0, %2}"
17838 [(set_attr "type" "ssemov")
17839 (set_attr "mode" "SF")])
17841 (define_insn "sse_storess"
17842 [(set (match_operand:SF 0 "memory_operand" "=m")
17844 (match_operand:V4SF 1 "register_operand" "x")
17845 (parallel [(const_int 0)])))]
17847 "movss\t{%1, %0|%0, %1}"
17848 [(set_attr "type" "ssemov")
17849 (set_attr "mode" "SF")])
17851 (define_insn "sse_shufps"
17852 [(set (match_operand:V4SF 0 "register_operand" "=x")
17853 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
17854 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
17855 (match_operand:SI 3 "immediate_operand" "i")]
17858 ;; @@@ check operand order for intel/nonintel syntax
17859 "shufps\t{%3, %2, %0|%0, %2, %3}"
17860 [(set_attr "type" "ssecvt")
17861 (set_attr "mode" "V4SF")])
17866 (define_insn "addv4sf3"
17867 [(set (match_operand:V4SF 0 "register_operand" "=x")
17868 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17869 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17871 "addps\t{%2, %0|%0, %2}"
17872 [(set_attr "type" "sseadd")
17873 (set_attr "mode" "V4SF")])
17875 (define_insn "vmaddv4sf3"
17876 [(set (match_operand:V4SF 0 "register_operand" "=x")
17878 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17879 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17883 "addss\t{%2, %0|%0, %2}"
17884 [(set_attr "type" "sseadd")
17885 (set_attr "mode" "SF")])
17887 (define_insn "subv4sf3"
17888 [(set (match_operand:V4SF 0 "register_operand" "=x")
17889 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17890 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17892 "subps\t{%2, %0|%0, %2}"
17893 [(set_attr "type" "sseadd")
17894 (set_attr "mode" "V4SF")])
17896 (define_insn "vmsubv4sf3"
17897 [(set (match_operand:V4SF 0 "register_operand" "=x")
17899 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17900 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17904 "subss\t{%2, %0|%0, %2}"
17905 [(set_attr "type" "sseadd")
17906 (set_attr "mode" "SF")])
17908 (define_insn "mulv4sf3"
17909 [(set (match_operand:V4SF 0 "register_operand" "=x")
17910 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17911 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17913 "mulps\t{%2, %0|%0, %2}"
17914 [(set_attr "type" "ssemul")
17915 (set_attr "mode" "V4SF")])
17917 (define_insn "vmmulv4sf3"
17918 [(set (match_operand:V4SF 0 "register_operand" "=x")
17920 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17921 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17925 "mulss\t{%2, %0|%0, %2}"
17926 [(set_attr "type" "ssemul")
17927 (set_attr "mode" "SF")])
17929 (define_insn "divv4sf3"
17930 [(set (match_operand:V4SF 0 "register_operand" "=x")
17931 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17932 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17934 "divps\t{%2, %0|%0, %2}"
17935 [(set_attr "type" "ssediv")
17936 (set_attr "mode" "V4SF")])
17938 (define_insn "vmdivv4sf3"
17939 [(set (match_operand:V4SF 0 "register_operand" "=x")
17941 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17942 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17946 "divss\t{%2, %0|%0, %2}"
17947 [(set_attr "type" "ssediv")
17948 (set_attr "mode" "SF")])
17951 ;; SSE square root/reciprocal
17953 (define_insn "rcpv4sf2"
17954 [(set (match_operand:V4SF 0 "register_operand" "=x")
17956 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
17958 "rcpps\t{%1, %0|%0, %1}"
17959 [(set_attr "type" "sse")
17960 (set_attr "mode" "V4SF")])
17962 (define_insn "vmrcpv4sf2"
17963 [(set (match_operand:V4SF 0 "register_operand" "=x")
17965 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
17967 (match_operand:V4SF 2 "register_operand" "0")
17970 "rcpss\t{%1, %0|%0, %1}"
17971 [(set_attr "type" "sse")
17972 (set_attr "mode" "SF")])
17974 (define_insn "rsqrtv4sf2"
17975 [(set (match_operand:V4SF 0 "register_operand" "=x")
17977 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
17979 "rsqrtps\t{%1, %0|%0, %1}"
17980 [(set_attr "type" "sse")
17981 (set_attr "mode" "V4SF")])
17983 (define_insn "vmrsqrtv4sf2"
17984 [(set (match_operand:V4SF 0 "register_operand" "=x")
17986 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
17988 (match_operand:V4SF 2 "register_operand" "0")
17991 "rsqrtss\t{%1, %0|%0, %1}"
17992 [(set_attr "type" "sse")
17993 (set_attr "mode" "SF")])
17995 (define_insn "sqrtv4sf2"
17996 [(set (match_operand:V4SF 0 "register_operand" "=x")
17997 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
17999 "sqrtps\t{%1, %0|%0, %1}"
18000 [(set_attr "type" "sse")
18001 (set_attr "mode" "V4SF")])
18003 (define_insn "vmsqrtv4sf2"
18004 [(set (match_operand:V4SF 0 "register_operand" "=x")
18006 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18007 (match_operand:V4SF 2 "register_operand" "0")
18010 "sqrtss\t{%1, %0|%0, %1}"
18011 [(set_attr "type" "sse")
18012 (set_attr "mode" "SF")])
18014 ;; SSE logical operations.
18016 ;; These are not called andti3 etc. because we really really don't want
18017 ;; the compiler to widen DImode ands to TImode ands and then try to move
18018 ;; into DImode subregs of SSE registers, and them together, and move out
18019 ;; of DImode subregs again!
18021 (define_insn "*sse_andti3_df_1"
18022 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18023 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18024 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18026 "andpd\t{%2, %0|%0, %2}"
18027 [(set_attr "type" "sselog")
18028 (set_attr "mode" "V2DF")])
18030 (define_insn "*sse_andti3_df_2"
18031 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18032 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18033 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18035 "andpd\t{%2, %0|%0, %2}"
18036 [(set_attr "type" "sselog")
18037 (set_attr "mode" "V2DF")])
18039 (define_insn "*sse_andti3_sf_1"
18040 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18041 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18042 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18044 "andps\t{%2, %0|%0, %2}"
18045 [(set_attr "type" "sselog")
18046 (set_attr "mode" "V4SF")])
18048 (define_insn "*sse_andti3_sf_2"
18049 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18050 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18051 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18053 "andps\t{%2, %0|%0, %2}"
18054 [(set_attr "type" "sselog")
18055 (set_attr "mode" "V4SF")])
18057 (define_insn "sse_andti3"
18058 [(set (match_operand:TI 0 "register_operand" "=x")
18059 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18060 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18061 "TARGET_SSE && !TARGET_SSE2
18062 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18063 "andps\t{%2, %0|%0, %2}"
18064 [(set_attr "type" "sselog")
18065 (set_attr "mode" "V4SF")])
18067 (define_insn "sse2_andti3"
18068 [(set (match_operand:TI 0 "register_operand" "=x")
18069 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18070 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18072 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18073 "pand\t{%2, %0|%0, %2}"
18074 [(set_attr "type" "sselog")
18075 (set_attr "mode" "TI")])
18077 (define_insn "sse2_andv2di3"
18078 [(set (match_operand:V2DI 0 "register_operand" "=x")
18079 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18080 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18082 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18083 "pand\t{%2, %0|%0, %2}"
18084 [(set_attr "type" "sselog")
18085 (set_attr "mode" "TI")])
18087 (define_insn "*sse_nandti3_df"
18088 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18089 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18090 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18092 "andnpd\t{%2, %0|%0, %2}"
18093 [(set_attr "type" "sselog")
18094 (set_attr "mode" "V2DF")])
18096 (define_insn "*sse_nandti3_sf"
18097 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18098 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18099 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18101 "andnps\t{%2, %0|%0, %2}"
18102 [(set_attr "type" "sselog")
18103 (set_attr "mode" "V4SF")])
18105 (define_insn "sse_nandti3"
18106 [(set (match_operand:TI 0 "register_operand" "=x")
18107 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18108 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18109 "TARGET_SSE && !TARGET_SSE2"
18110 "andnps\t{%2, %0|%0, %2}"
18111 [(set_attr "type" "sselog")
18112 (set_attr "mode" "V4SF")])
18114 (define_insn "sse2_nandti3"
18115 [(set (match_operand:TI 0 "register_operand" "=x")
18116 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18117 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18119 "pandn\t{%2, %0|%0, %2}"
18120 [(set_attr "type" "sselog")
18121 (set_attr "mode" "TI")])
18123 (define_insn "sse2_nandv2di3"
18124 [(set (match_operand:V2DI 0 "register_operand" "=x")
18125 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0"))
18126 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18128 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18129 "pandn\t{%2, %0|%0, %2}"
18130 [(set_attr "type" "sselog")
18131 (set_attr "mode" "TI")])
18133 (define_insn "*sse_iorti3_df_1"
18134 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18135 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18136 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18138 "orpd\t{%2, %0|%0, %2}"
18139 [(set_attr "type" "sselog")
18140 (set_attr "mode" "V2DF")])
18142 (define_insn "*sse_iorti3_df_2"
18143 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18144 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18145 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18147 "orpd\t{%2, %0|%0, %2}"
18148 [(set_attr "type" "sselog")
18149 (set_attr "mode" "V2DF")])
18151 (define_insn "*sse_iorti3_sf_1"
18152 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18153 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18154 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18156 "orps\t{%2, %0|%0, %2}"
18157 [(set_attr "type" "sselog")
18158 (set_attr "mode" "V4SF")])
18160 (define_insn "*sse_iorti3_sf_2"
18161 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18162 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18163 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18165 "orps\t{%2, %0|%0, %2}"
18166 [(set_attr "type" "sselog")
18167 (set_attr "mode" "V4SF")])
18169 (define_insn "sse_iorti3"
18170 [(set (match_operand:TI 0 "register_operand" "=x")
18171 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18172 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18173 "TARGET_SSE && !TARGET_SSE2
18174 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18175 "orps\t{%2, %0|%0, %2}"
18176 [(set_attr "type" "sselog")
18177 (set_attr "mode" "V4SF")])
18179 (define_insn "sse2_iorti3"
18180 [(set (match_operand:TI 0 "register_operand" "=x")
18181 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18182 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18184 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18185 "por\t{%2, %0|%0, %2}"
18186 [(set_attr "type" "sselog")
18187 (set_attr "mode" "TI")])
18189 (define_insn "sse2_iorv2di3"
18190 [(set (match_operand:V2DI 0 "register_operand" "=x")
18191 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18192 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18194 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18195 "por\t{%2, %0|%0, %2}"
18196 [(set_attr "type" "sselog")
18197 (set_attr "mode" "TI")])
18199 (define_insn "*sse_xorti3_df_1"
18200 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18201 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18202 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18204 "xorpd\t{%2, %0|%0, %2}"
18205 [(set_attr "type" "sselog")
18206 (set_attr "mode" "V2DF")])
18208 (define_insn "*sse_xorti3_df_2"
18209 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18210 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18211 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18213 "xorpd\t{%2, %0|%0, %2}"
18214 [(set_attr "type" "sselog")
18215 (set_attr "mode" "V2DF")])
18217 (define_insn "*sse_xorti3_sf_1"
18218 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18219 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18220 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18222 "xorps\t{%2, %0|%0, %2}"
18223 [(set_attr "type" "sselog")
18224 (set_attr "mode" "V4SF")])
18226 (define_insn "*sse_xorti3_sf_2"
18227 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18228 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18229 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18231 "xorps\t{%2, %0|%0, %2}"
18232 [(set_attr "type" "sselog")
18233 (set_attr "mode" "V4SF")])
18235 (define_insn "sse_xorti3"
18236 [(set (match_operand:TI 0 "register_operand" "=x")
18237 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18238 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18239 "TARGET_SSE && !TARGET_SSE2
18240 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18241 "xorps\t{%2, %0|%0, %2}"
18242 [(set_attr "type" "sselog")
18243 (set_attr "mode" "V4SF")])
18245 (define_insn "sse2_xorti3"
18246 [(set (match_operand:TI 0 "register_operand" "=x")
18247 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18248 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18250 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18251 "pxor\t{%2, %0|%0, %2}"
18252 [(set_attr "type" "sselog")
18253 (set_attr "mode" "TI")])
18255 (define_insn "sse2_xorv2di3"
18256 [(set (match_operand:V2DI 0 "register_operand" "=x")
18257 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18258 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18260 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18261 "pxor\t{%2, %0|%0, %2}"
18262 [(set_attr "type" "sselog")
18263 (set_attr "mode" "TI")])
18265 ;; Use xor, but don't show input operands so they aren't live before
18267 (define_insn "sse_clrv4sf"
18268 [(set (match_operand:V4SF 0 "register_operand" "=x")
18269 (unspec:V4SF [(const_int 0)] UNSPEC_NOP))]
18271 "xorps\t{%0, %0|%0, %0}"
18272 [(set_attr "type" "sselog")
18273 (set_attr "memory" "none")
18274 (set_attr "mode" "V4SF")])
18276 ;; SSE mask-generating compares
18278 (define_insn "maskcmpv4sf3"
18279 [(set (match_operand:V4SI 0 "register_operand" "=x")
18280 (match_operator:V4SI 3 "sse_comparison_operator"
18281 [(match_operand:V4SF 1 "register_operand" "0")
18282 (match_operand:V4SF 2 "register_operand" "x")]))]
18284 "cmp%D3ps\t{%2, %0|%0, %2}"
18285 [(set_attr "type" "ssecmp")
18286 (set_attr "mode" "V4SF")])
18288 (define_insn "maskncmpv4sf3"
18289 [(set (match_operand:V4SI 0 "register_operand" "=x")
18291 (match_operator:V4SI 3 "sse_comparison_operator"
18292 [(match_operand:V4SF 1 "register_operand" "0")
18293 (match_operand:V4SF 2 "register_operand" "x")])))]
18296 if (GET_CODE (operands[3]) == UNORDERED)
18297 return "cmpordps\t{%2, %0|%0, %2}";
18299 return "cmpn%D3ps\t{%2, %0|%0, %2}";
18301 [(set_attr "type" "ssecmp")
18302 (set_attr "mode" "V4SF")])
18304 (define_insn "vmmaskcmpv4sf3"
18305 [(set (match_operand:V4SI 0 "register_operand" "=x")
18307 (match_operator:V4SI 3 "sse_comparison_operator"
18308 [(match_operand:V4SF 1 "register_operand" "0")
18309 (match_operand:V4SF 2 "register_operand" "x")])
18313 "cmp%D3ss\t{%2, %0|%0, %2}"
18314 [(set_attr "type" "ssecmp")
18315 (set_attr "mode" "SF")])
18317 (define_insn "vmmaskncmpv4sf3"
18318 [(set (match_operand:V4SI 0 "register_operand" "=x")
18321 (match_operator:V4SI 3 "sse_comparison_operator"
18322 [(match_operand:V4SF 1 "register_operand" "0")
18323 (match_operand:V4SF 2 "register_operand" "x")]))
18324 (subreg:V4SI (match_dup 1) 0)
18328 if (GET_CODE (operands[3]) == UNORDERED)
18329 return "cmpordss\t{%2, %0|%0, %2}";
18331 return "cmpn%D3ss\t{%2, %0|%0, %2}";
18333 [(set_attr "type" "ssecmp")
18334 (set_attr "mode" "SF")])
18336 (define_insn "sse_comi"
18337 [(set (reg:CCFP 17)
18338 (match_operator:CCFP 2 "sse_comparison_operator"
18340 (match_operand:V4SF 0 "register_operand" "x")
18341 (parallel [(const_int 0)]))
18343 (match_operand:V4SF 1 "register_operand" "x")
18344 (parallel [(const_int 0)]))]))]
18346 "comiss\t{%1, %0|%0, %1}"
18347 [(set_attr "type" "ssecmp")
18348 (set_attr "mode" "SF")])
18350 (define_insn "sse_ucomi"
18351 [(set (reg:CCFPU 17)
18352 (match_operator:CCFPU 2 "sse_comparison_operator"
18354 (match_operand:V4SF 0 "register_operand" "x")
18355 (parallel [(const_int 0)]))
18357 (match_operand:V4SF 1 "register_operand" "x")
18358 (parallel [(const_int 0)]))]))]
18360 "ucomiss\t{%1, %0|%0, %1}"
18361 [(set_attr "type" "ssecmp")
18362 (set_attr "mode" "SF")])
18367 (define_insn "sse_unpckhps"
18368 [(set (match_operand:V4SF 0 "register_operand" "=x")
18370 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18371 (parallel [(const_int 2)
18375 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18376 (parallel [(const_int 0)
18382 "unpckhps\t{%2, %0|%0, %2}"
18383 [(set_attr "type" "ssecvt")
18384 (set_attr "mode" "V4SF")])
18386 (define_insn "sse_unpcklps"
18387 [(set (match_operand:V4SF 0 "register_operand" "=x")
18389 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18390 (parallel [(const_int 0)
18394 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18395 (parallel [(const_int 2)
18401 "unpcklps\t{%2, %0|%0, %2}"
18402 [(set_attr "type" "ssecvt")
18403 (set_attr "mode" "V4SF")])
18408 (define_insn "smaxv4sf3"
18409 [(set (match_operand:V4SF 0 "register_operand" "=x")
18410 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18411 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18413 "maxps\t{%2, %0|%0, %2}"
18414 [(set_attr "type" "sse")
18415 (set_attr "mode" "V4SF")])
18417 (define_insn "vmsmaxv4sf3"
18418 [(set (match_operand:V4SF 0 "register_operand" "=x")
18420 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18421 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18425 "maxss\t{%2, %0|%0, %2}"
18426 [(set_attr "type" "sse")
18427 (set_attr "mode" "SF")])
18429 (define_insn "sminv4sf3"
18430 [(set (match_operand:V4SF 0 "register_operand" "=x")
18431 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18432 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18434 "minps\t{%2, %0|%0, %2}"
18435 [(set_attr "type" "sse")
18436 (set_attr "mode" "V4SF")])
18438 (define_insn "vmsminv4sf3"
18439 [(set (match_operand:V4SF 0 "register_operand" "=x")
18441 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18442 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18446 "minss\t{%2, %0|%0, %2}"
18447 [(set_attr "type" "sse")
18448 (set_attr "mode" "SF")])
18451 ;; SSE <-> integer/MMX conversions
18453 (define_insn "cvtpi2ps"
18454 [(set (match_operand:V4SF 0 "register_operand" "=x")
18456 (match_operand:V4SF 1 "register_operand" "0")
18457 (vec_duplicate:V4SF
18458 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
18461 "cvtpi2ps\t{%2, %0|%0, %2}"
18462 [(set_attr "type" "ssecvt")
18463 (set_attr "mode" "V4SF")])
18465 (define_insn "cvtps2pi"
18466 [(set (match_operand:V2SI 0 "register_operand" "=y")
18468 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18469 (parallel [(const_int 0) (const_int 1)])))]
18471 "cvtps2pi\t{%1, %0|%0, %1}"
18472 [(set_attr "type" "ssecvt")
18473 (set_attr "mode" "V4SF")])
18475 (define_insn "cvttps2pi"
18476 [(set (match_operand:V2SI 0 "register_operand" "=y")
18478 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18480 (parallel [(const_int 0) (const_int 1)])))]
18482 "cvttps2pi\t{%1, %0|%0, %1}"
18483 [(set_attr "type" "ssecvt")
18484 (set_attr "mode" "SF")])
18486 (define_insn "cvtsi2ss"
18487 [(set (match_operand:V4SF 0 "register_operand" "=x")
18489 (match_operand:V4SF 1 "register_operand" "0")
18490 (vec_duplicate:V4SF
18491 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
18494 "cvtsi2ss\t{%2, %0|%0, %2}"
18495 [(set_attr "type" "ssecvt")
18496 (set_attr "mode" "SF")])
18498 (define_insn "cvtss2si"
18499 [(set (match_operand:SI 0 "register_operand" "=r")
18501 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18502 (parallel [(const_int 0)])))]
18504 "cvtss2si\t{%1, %0|%0, %1}"
18505 [(set_attr "type" "ssecvt")
18506 (set_attr "mode" "SF")])
18508 (define_insn "cvttss2si"
18509 [(set (match_operand:SI 0 "register_operand" "=r")
18511 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18513 (parallel [(const_int 0)])))]
18515 "cvttss2si\t{%1, %0|%0, %1}"
18516 [(set_attr "type" "ssecvt")
18517 (set_attr "mode" "SF")])
18524 (define_insn "addv8qi3"
18525 [(set (match_operand:V8QI 0 "register_operand" "=y")
18526 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18527 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18529 "paddb\t{%2, %0|%0, %2}"
18530 [(set_attr "type" "mmxadd")
18531 (set_attr "mode" "DI")])
18533 (define_insn "addv4hi3"
18534 [(set (match_operand:V4HI 0 "register_operand" "=y")
18535 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18536 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18538 "paddw\t{%2, %0|%0, %2}"
18539 [(set_attr "type" "mmxadd")
18540 (set_attr "mode" "DI")])
18542 (define_insn "addv2si3"
18543 [(set (match_operand:V2SI 0 "register_operand" "=y")
18544 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18545 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18547 "paddd\t{%2, %0|%0, %2}"
18548 [(set_attr "type" "mmxadd")
18549 (set_attr "mode" "DI")])
18551 (define_insn "ssaddv8qi3"
18552 [(set (match_operand:V8QI 0 "register_operand" "=y")
18553 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18554 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18556 "paddsb\t{%2, %0|%0, %2}"
18557 [(set_attr "type" "mmxadd")
18558 (set_attr "mode" "DI")])
18560 (define_insn "ssaddv4hi3"
18561 [(set (match_operand:V4HI 0 "register_operand" "=y")
18562 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18563 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18565 "paddsw\t{%2, %0|%0, %2}"
18566 [(set_attr "type" "mmxadd")
18567 (set_attr "mode" "DI")])
18569 (define_insn "usaddv8qi3"
18570 [(set (match_operand:V8QI 0 "register_operand" "=y")
18571 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18572 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18574 "paddusb\t{%2, %0|%0, %2}"
18575 [(set_attr "type" "mmxadd")
18576 (set_attr "mode" "DI")])
18578 (define_insn "usaddv4hi3"
18579 [(set (match_operand:V4HI 0 "register_operand" "=y")
18580 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18581 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18583 "paddusw\t{%2, %0|%0, %2}"
18584 [(set_attr "type" "mmxadd")
18585 (set_attr "mode" "DI")])
18587 (define_insn "subv8qi3"
18588 [(set (match_operand:V8QI 0 "register_operand" "=y")
18589 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18590 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18592 "psubb\t{%2, %0|%0, %2}"
18593 [(set_attr "type" "mmxadd")
18594 (set_attr "mode" "DI")])
18596 (define_insn "subv4hi3"
18597 [(set (match_operand:V4HI 0 "register_operand" "=y")
18598 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18599 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18601 "psubw\t{%2, %0|%0, %2}"
18602 [(set_attr "type" "mmxadd")
18603 (set_attr "mode" "DI")])
18605 (define_insn "subv2si3"
18606 [(set (match_operand:V2SI 0 "register_operand" "=y")
18607 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18608 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18610 "psubd\t{%2, %0|%0, %2}"
18611 [(set_attr "type" "mmxadd")
18612 (set_attr "mode" "DI")])
18614 (define_insn "sssubv8qi3"
18615 [(set (match_operand:V8QI 0 "register_operand" "=y")
18616 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18617 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18619 "psubsb\t{%2, %0|%0, %2}"
18620 [(set_attr "type" "mmxadd")
18621 (set_attr "mode" "DI")])
18623 (define_insn "sssubv4hi3"
18624 [(set (match_operand:V4HI 0 "register_operand" "=y")
18625 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18626 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18628 "psubsw\t{%2, %0|%0, %2}"
18629 [(set_attr "type" "mmxadd")
18630 (set_attr "mode" "DI")])
18632 (define_insn "ussubv8qi3"
18633 [(set (match_operand:V8QI 0 "register_operand" "=y")
18634 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18635 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18637 "psubusb\t{%2, %0|%0, %2}"
18638 [(set_attr "type" "mmxadd")
18639 (set_attr "mode" "DI")])
18641 (define_insn "ussubv4hi3"
18642 [(set (match_operand:V4HI 0 "register_operand" "=y")
18643 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18644 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18646 "psubusw\t{%2, %0|%0, %2}"
18647 [(set_attr "type" "mmxadd")
18648 (set_attr "mode" "DI")])
18650 (define_insn "mulv4hi3"
18651 [(set (match_operand:V4HI 0 "register_operand" "=y")
18652 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
18653 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18655 "pmullw\t{%2, %0|%0, %2}"
18656 [(set_attr "type" "mmxmul")
18657 (set_attr "mode" "DI")])
18659 (define_insn "smulv4hi3_highpart"
18660 [(set (match_operand:V4HI 0 "register_operand" "=y")
18663 (mult:V4SI (sign_extend:V4SI
18664 (match_operand:V4HI 1 "register_operand" "0"))
18666 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18669 "pmulhw\t{%2, %0|%0, %2}"
18670 [(set_attr "type" "mmxmul")
18671 (set_attr "mode" "DI")])
18673 (define_insn "umulv4hi3_highpart"
18674 [(set (match_operand:V4HI 0 "register_operand" "=y")
18677 (mult:V4SI (zero_extend:V4SI
18678 (match_operand:V4HI 1 "register_operand" "0"))
18680 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18682 "TARGET_SSE || TARGET_3DNOW_A"
18683 "pmulhuw\t{%2, %0|%0, %2}"
18684 [(set_attr "type" "mmxmul")
18685 (set_attr "mode" "DI")])
18687 (define_insn "mmx_pmaddwd"
18688 [(set (match_operand:V2SI 0 "register_operand" "=y")
18692 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
18693 (parallel [(const_int 0) (const_int 2)])))
18695 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18696 (parallel [(const_int 0) (const_int 2)]))))
18698 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
18699 (parallel [(const_int 1)
18701 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
18702 (parallel [(const_int 1)
18703 (const_int 3)]))))))]
18705 "pmaddwd\t{%2, %0|%0, %2}"
18706 [(set_attr "type" "mmxmul")
18707 (set_attr "mode" "DI")])
18710 ;; MMX logical operations
18711 ;; Note we don't want to declare these as regular iordi3 insns to prevent
18712 ;; normal code that also wants to use the FPU from getting broken.
18713 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
18714 (define_insn "mmx_iordi3"
18715 [(set (match_operand:DI 0 "register_operand" "=y")
18717 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18718 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
18721 "por\t{%2, %0|%0, %2}"
18722 [(set_attr "type" "mmxadd")
18723 (set_attr "mode" "DI")])
18725 (define_insn "mmx_xordi3"
18726 [(set (match_operand:DI 0 "register_operand" "=y")
18728 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18729 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
18732 "pxor\t{%2, %0|%0, %2}"
18733 [(set_attr "type" "mmxadd")
18734 (set_attr "mode" "DI")
18735 (set_attr "memory" "none")])
18737 ;; Same as pxor, but don't show input operands so that we don't think
18739 (define_insn "mmx_clrdi"
18740 [(set (match_operand:DI 0 "register_operand" "=y")
18741 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
18743 "pxor\t{%0, %0|%0, %0}"
18744 [(set_attr "type" "mmxadd")
18745 (set_attr "mode" "DI")
18746 (set_attr "memory" "none")])
18748 (define_insn "mmx_anddi3"
18749 [(set (match_operand:DI 0 "register_operand" "=y")
18751 [(and:DI (match_operand:DI 1 "register_operand" "0")
18752 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
18755 "pand\t{%2, %0|%0, %2}"
18756 [(set_attr "type" "mmxadd")
18757 (set_attr "mode" "DI")])
18759 (define_insn "mmx_nanddi3"
18760 [(set (match_operand:DI 0 "register_operand" "=y")
18762 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
18763 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
18766 "pandn\t{%2, %0|%0, %2}"
18767 [(set_attr "type" "mmxadd")
18768 (set_attr "mode" "DI")])
18771 ;; MMX unsigned averages/sum of absolute differences
18773 (define_insn "mmx_uavgv8qi3"
18774 [(set (match_operand:V8QI 0 "register_operand" "=y")
18776 (plus:V8QI (plus:V8QI
18777 (match_operand:V8QI 1 "register_operand" "0")
18778 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18779 (const_vector:V8QI [(const_int 1)
18788 "TARGET_SSE || TARGET_3DNOW_A"
18789 "pavgb\t{%2, %0|%0, %2}"
18790 [(set_attr "type" "mmxshft")
18791 (set_attr "mode" "DI")])
18793 (define_insn "mmx_uavgv4hi3"
18794 [(set (match_operand:V4HI 0 "register_operand" "=y")
18796 (plus:V4HI (plus:V4HI
18797 (match_operand:V4HI 1 "register_operand" "0")
18798 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18799 (const_vector:V4HI [(const_int 1)
18804 "TARGET_SSE || TARGET_3DNOW_A"
18805 "pavgw\t{%2, %0|%0, %2}"
18806 [(set_attr "type" "mmxshft")
18807 (set_attr "mode" "DI")])
18809 (define_insn "mmx_psadbw"
18810 [(set (match_operand:DI 0 "register_operand" "=y")
18811 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
18812 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
18814 "TARGET_SSE || TARGET_3DNOW_A"
18815 "psadbw\t{%2, %0|%0, %2}"
18816 [(set_attr "type" "mmxshft")
18817 (set_attr "mode" "DI")])
18820 ;; MMX insert/extract/shuffle
18822 (define_insn "mmx_pinsrw"
18823 [(set (match_operand:V4HI 0 "register_operand" "=y")
18824 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
18825 (vec_duplicate:V4HI
18826 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
18827 (match_operand:SI 3 "immediate_operand" "i")))]
18828 "TARGET_SSE || TARGET_3DNOW_A"
18829 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
18830 [(set_attr "type" "mmxcvt")
18831 (set_attr "mode" "DI")])
18833 (define_insn "mmx_pextrw"
18834 [(set (match_operand:SI 0 "register_operand" "=r")
18835 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
18837 [(match_operand:SI 2 "immediate_operand" "i")]))))]
18838 "TARGET_SSE || TARGET_3DNOW_A"
18839 "pextrw\t{%2, %1, %0|%0, %1, %2}"
18840 [(set_attr "type" "mmxcvt")
18841 (set_attr "mode" "DI")])
18843 (define_insn "mmx_pshufw"
18844 [(set (match_operand:V4HI 0 "register_operand" "=y")
18845 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
18846 (match_operand:SI 2 "immediate_operand" "i")]
18848 "TARGET_SSE || TARGET_3DNOW_A"
18849 "pshufw\t{%2, %1, %0|%0, %1, %2}"
18850 [(set_attr "type" "mmxcvt")
18851 (set_attr "mode" "DI")])
18854 ;; MMX mask-generating comparisons
18856 (define_insn "eqv8qi3"
18857 [(set (match_operand:V8QI 0 "register_operand" "=y")
18858 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
18859 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18861 "pcmpeqb\t{%2, %0|%0, %2}"
18862 [(set_attr "type" "mmxcmp")
18863 (set_attr "mode" "DI")])
18865 (define_insn "eqv4hi3"
18866 [(set (match_operand:V4HI 0 "register_operand" "=y")
18867 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
18868 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18870 "pcmpeqw\t{%2, %0|%0, %2}"
18871 [(set_attr "type" "mmxcmp")
18872 (set_attr "mode" "DI")])
18874 (define_insn "eqv2si3"
18875 [(set (match_operand:V2SI 0 "register_operand" "=y")
18876 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
18877 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18879 "pcmpeqd\t{%2, %0|%0, %2}"
18880 [(set_attr "type" "mmxcmp")
18881 (set_attr "mode" "DI")])
18883 (define_insn "gtv8qi3"
18884 [(set (match_operand:V8QI 0 "register_operand" "=y")
18885 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
18886 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18888 "pcmpgtb\t{%2, %0|%0, %2}"
18889 [(set_attr "type" "mmxcmp")
18890 (set_attr "mode" "DI")])
18892 (define_insn "gtv4hi3"
18893 [(set (match_operand:V4HI 0 "register_operand" "=y")
18894 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18895 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18897 "pcmpgtw\t{%2, %0|%0, %2}"
18898 [(set_attr "type" "mmxcmp")
18899 (set_attr "mode" "DI")])
18901 (define_insn "gtv2si3"
18902 [(set (match_operand:V2SI 0 "register_operand" "=y")
18903 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18904 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18906 "pcmpgtd\t{%2, %0|%0, %2}"
18907 [(set_attr "type" "mmxcmp")
18908 (set_attr "mode" "DI")])
18911 ;; MMX max/min insns
18913 (define_insn "umaxv8qi3"
18914 [(set (match_operand:V8QI 0 "register_operand" "=y")
18915 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
18916 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18917 "TARGET_SSE || TARGET_3DNOW_A"
18918 "pmaxub\t{%2, %0|%0, %2}"
18919 [(set_attr "type" "mmxadd")
18920 (set_attr "mode" "DI")])
18922 (define_insn "smaxv4hi3"
18923 [(set (match_operand:V4HI 0 "register_operand" "=y")
18924 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
18925 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18926 "TARGET_SSE || TARGET_3DNOW_A"
18927 "pmaxsw\t{%2, %0|%0, %2}"
18928 [(set_attr "type" "mmxadd")
18929 (set_attr "mode" "DI")])
18931 (define_insn "uminv8qi3"
18932 [(set (match_operand:V8QI 0 "register_operand" "=y")
18933 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
18934 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18935 "TARGET_SSE || TARGET_3DNOW_A"
18936 "pminub\t{%2, %0|%0, %2}"
18937 [(set_attr "type" "mmxadd")
18938 (set_attr "mode" "DI")])
18940 (define_insn "sminv4hi3"
18941 [(set (match_operand:V4HI 0 "register_operand" "=y")
18942 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
18943 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18944 "TARGET_SSE || TARGET_3DNOW_A"
18945 "pminsw\t{%2, %0|%0, %2}"
18946 [(set_attr "type" "mmxadd")
18947 (set_attr "mode" "DI")])
18952 (define_insn "ashrv4hi3"
18953 [(set (match_operand:V4HI 0 "register_operand" "=y")
18954 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18955 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18957 "psraw\t{%2, %0|%0, %2}"
18958 [(set_attr "type" "mmxshft")
18959 (set_attr "mode" "DI")])
18961 (define_insn "ashrv2si3"
18962 [(set (match_operand:V2SI 0 "register_operand" "=y")
18963 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18964 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18966 "psrad\t{%2, %0|%0, %2}"
18967 [(set_attr "type" "mmxshft")
18968 (set_attr "mode" "DI")])
18970 (define_insn "lshrv4hi3"
18971 [(set (match_operand:V4HI 0 "register_operand" "=y")
18972 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18973 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18975 "psrlw\t{%2, %0|%0, %2}"
18976 [(set_attr "type" "mmxshft")
18977 (set_attr "mode" "DI")])
18979 (define_insn "lshrv2si3"
18980 [(set (match_operand:V2SI 0 "register_operand" "=y")
18981 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18982 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18984 "psrld\t{%2, %0|%0, %2}"
18985 [(set_attr "type" "mmxshft")
18986 (set_attr "mode" "DI")])
18988 ;; See logical MMX insns.
18989 (define_insn "mmx_lshrdi3"
18990 [(set (match_operand:DI 0 "register_operand" "=y")
18992 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
18993 (match_operand:DI 2 "nonmemory_operand" "yi"))]
18996 "psrlq\t{%2, %0|%0, %2}"
18997 [(set_attr "type" "mmxshft")
18998 (set_attr "mode" "DI")])
19000 (define_insn "ashlv4hi3"
19001 [(set (match_operand:V4HI 0 "register_operand" "=y")
19002 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
19003 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19005 "psllw\t{%2, %0|%0, %2}"
19006 [(set_attr "type" "mmxshft")
19007 (set_attr "mode" "DI")])
19009 (define_insn "ashlv2si3"
19010 [(set (match_operand:V2SI 0 "register_operand" "=y")
19011 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
19012 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19014 "pslld\t{%2, %0|%0, %2}"
19015 [(set_attr "type" "mmxshft")
19016 (set_attr "mode" "DI")])
19018 ;; See logical MMX insns.
19019 (define_insn "mmx_ashldi3"
19020 [(set (match_operand:DI 0 "register_operand" "=y")
19022 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
19023 (match_operand:DI 2 "nonmemory_operand" "yi"))]
19026 "psllq\t{%2, %0|%0, %2}"
19027 [(set_attr "type" "mmxshft")
19028 (set_attr "mode" "DI")])
19031 ;; MMX pack/unpack insns.
19033 (define_insn "mmx_packsswb"
19034 [(set (match_operand:V8QI 0 "register_operand" "=y")
19036 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19037 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19039 "packsswb\t{%2, %0|%0, %2}"
19040 [(set_attr "type" "mmxshft")
19041 (set_attr "mode" "DI")])
19043 (define_insn "mmx_packssdw"
19044 [(set (match_operand:V4HI 0 "register_operand" "=y")
19046 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
19047 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
19049 "packssdw\t{%2, %0|%0, %2}"
19050 [(set_attr "type" "mmxshft")
19051 (set_attr "mode" "DI")])
19053 (define_insn "mmx_packuswb"
19054 [(set (match_operand:V8QI 0 "register_operand" "=y")
19056 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19057 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19059 "packuswb\t{%2, %0|%0, %2}"
19060 [(set_attr "type" "mmxshft")
19061 (set_attr "mode" "DI")])
19063 (define_insn "mmx_punpckhbw"
19064 [(set (match_operand:V8QI 0 "register_operand" "=y")
19066 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19067 (parallel [(const_int 4)
19075 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19076 (parallel [(const_int 0)
19086 "punpckhbw\t{%2, %0|%0, %2}"
19087 [(set_attr "type" "mmxcvt")
19088 (set_attr "mode" "DI")])
19090 (define_insn "mmx_punpckhwd"
19091 [(set (match_operand:V4HI 0 "register_operand" "=y")
19093 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19094 (parallel [(const_int 0)
19098 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19099 (parallel [(const_int 2)
19105 "punpckhwd\t{%2, %0|%0, %2}"
19106 [(set_attr "type" "mmxcvt")
19107 (set_attr "mode" "DI")])
19109 (define_insn "mmx_punpckhdq"
19110 [(set (match_operand:V2SI 0 "register_operand" "=y")
19112 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19113 (parallel [(const_int 0)
19115 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19116 (parallel [(const_int 1)
19120 "punpckhdq\t{%2, %0|%0, %2}"
19121 [(set_attr "type" "mmxcvt")
19122 (set_attr "mode" "DI")])
19124 (define_insn "mmx_punpcklbw"
19125 [(set (match_operand:V8QI 0 "register_operand" "=y")
19127 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19128 (parallel [(const_int 0)
19136 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19137 (parallel [(const_int 4)
19147 "punpcklbw\t{%2, %0|%0, %2}"
19148 [(set_attr "type" "mmxcvt")
19149 (set_attr "mode" "DI")])
19151 (define_insn "mmx_punpcklwd"
19152 [(set (match_operand:V4HI 0 "register_operand" "=y")
19154 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19155 (parallel [(const_int 2)
19159 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19160 (parallel [(const_int 0)
19166 "punpcklwd\t{%2, %0|%0, %2}"
19167 [(set_attr "type" "mmxcvt")
19168 (set_attr "mode" "DI")])
19170 (define_insn "mmx_punpckldq"
19171 [(set (match_operand:V2SI 0 "register_operand" "=y")
19173 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19174 (parallel [(const_int 1)
19176 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19177 (parallel [(const_int 0)
19181 "punpckldq\t{%2, %0|%0, %2}"
19182 [(set_attr "type" "mmxcvt")
19183 (set_attr "mode" "DI")])
19186 ;; Miscellaneous stuff
19188 (define_insn "emms"
19189 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
19190 (clobber (reg:XF 8))
19191 (clobber (reg:XF 9))
19192 (clobber (reg:XF 10))
19193 (clobber (reg:XF 11))
19194 (clobber (reg:XF 12))
19195 (clobber (reg:XF 13))
19196 (clobber (reg:XF 14))
19197 (clobber (reg:XF 15))
19198 (clobber (reg:DI 29))
19199 (clobber (reg:DI 30))
19200 (clobber (reg:DI 31))
19201 (clobber (reg:DI 32))
19202 (clobber (reg:DI 33))
19203 (clobber (reg:DI 34))
19204 (clobber (reg:DI 35))
19205 (clobber (reg:DI 36))]
19208 [(set_attr "type" "mmx")
19209 (set_attr "memory" "unknown")])
19211 (define_insn "ldmxcsr"
19212 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
19216 [(set_attr "type" "mmx")
19217 (set_attr "memory" "load")])
19219 (define_insn "stmxcsr"
19220 [(set (match_operand:SI 0 "memory_operand" "=m")
19221 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
19224 [(set_attr "type" "mmx")
19225 (set_attr "memory" "store")])
19227 (define_expand "sfence"
19228 [(set (match_dup 0)
19229 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
19230 "TARGET_SSE || TARGET_3DNOW_A"
19232 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19233 MEM_VOLATILE_P (operands[0]) = 1;
19236 (define_insn "*sfence_insn"
19237 [(set (match_operand:BLK 0 "" "")
19238 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
19239 "TARGET_SSE || TARGET_3DNOW_A"
19241 [(set_attr "type" "sse")
19242 (set_attr "memory" "unknown")])
19244 (define_expand "sse_prologue_save"
19245 [(parallel [(set (match_operand:BLK 0 "" "")
19246 (unspec:BLK [(reg:DI 21)
19253 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
19254 (use (match_operand:DI 1 "register_operand" ""))
19255 (use (match_operand:DI 2 "immediate_operand" ""))
19256 (use (label_ref:DI (match_operand 3 "" "")))])]
19260 (define_insn "*sse_prologue_save_insn"
19261 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
19262 (match_operand:DI 4 "const_int_operand" "n")))
19263 (unspec:BLK [(reg:DI 21)
19270 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
19271 (use (match_operand:DI 1 "register_operand" "r"))
19272 (use (match_operand:DI 2 "const_int_operand" "i"))
19273 (use (label_ref:DI (match_operand 3 "" "X")))]
19275 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
19276 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
19280 operands[0] = gen_rtx_MEM (Pmode,
19281 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
19282 output_asm_insn (\"jmp\\t%A1\", operands);
19283 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
19285 operands[4] = adjust_address (operands[0], DImode, i*16);
19286 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
19287 PUT_MODE (operands[4], TImode);
19288 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
19289 output_asm_insn (\"rex\", operands);
19290 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
19292 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
19293 CODE_LABEL_NUMBER (operands[3]));
19297 [(set_attr "type" "other")
19298 (set_attr "length_immediate" "0")
19299 (set_attr "length_address" "0")
19300 (set_attr "length" "135")
19301 (set_attr "memory" "store")
19302 (set_attr "modrm" "0")
19303 (set_attr "mode" "DI")])
19305 ;; 3Dnow! instructions
19307 (define_insn "addv2sf3"
19308 [(set (match_operand:V2SF 0 "register_operand" "=y")
19309 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19310 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19312 "pfadd\\t{%2, %0|%0, %2}"
19313 [(set_attr "type" "mmxadd")
19314 (set_attr "mode" "V2SF")])
19316 (define_insn "subv2sf3"
19317 [(set (match_operand:V2SF 0 "register_operand" "=y")
19318 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19319 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19321 "pfsub\\t{%2, %0|%0, %2}"
19322 [(set_attr "type" "mmxadd")
19323 (set_attr "mode" "V2SF")])
19325 (define_insn "subrv2sf3"
19326 [(set (match_operand:V2SF 0 "register_operand" "=y")
19327 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
19328 (match_operand:V2SF 1 "register_operand" "0")))]
19330 "pfsubr\\t{%2, %0|%0, %2}"
19331 [(set_attr "type" "mmxadd")
19332 (set_attr "mode" "V2SF")])
19334 (define_insn "gtv2sf3"
19335 [(set (match_operand:V2SI 0 "register_operand" "=y")
19336 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
19337 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19339 "pfcmpgt\\t{%2, %0|%0, %2}"
19340 [(set_attr "type" "mmxcmp")
19341 (set_attr "mode" "V2SF")])
19343 (define_insn "gev2sf3"
19344 [(set (match_operand:V2SI 0 "register_operand" "=y")
19345 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
19346 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19348 "pfcmpge\\t{%2, %0|%0, %2}"
19349 [(set_attr "type" "mmxcmp")
19350 (set_attr "mode" "V2SF")])
19352 (define_insn "eqv2sf3"
19353 [(set (match_operand:V2SI 0 "register_operand" "=y")
19354 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
19355 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19357 "pfcmpeq\\t{%2, %0|%0, %2}"
19358 [(set_attr "type" "mmxcmp")
19359 (set_attr "mode" "V2SF")])
19361 (define_insn "pfmaxv2sf3"
19362 [(set (match_operand:V2SF 0 "register_operand" "=y")
19363 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
19364 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19366 "pfmax\\t{%2, %0|%0, %2}"
19367 [(set_attr "type" "mmxadd")
19368 (set_attr "mode" "V2SF")])
19370 (define_insn "pfminv2sf3"
19371 [(set (match_operand:V2SF 0 "register_operand" "=y")
19372 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
19373 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19375 "pfmin\\t{%2, %0|%0, %2}"
19376 [(set_attr "type" "mmxadd")
19377 (set_attr "mode" "V2SF")])
19379 (define_insn "mulv2sf3"
19380 [(set (match_operand:V2SF 0 "register_operand" "=y")
19381 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
19382 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19384 "pfmul\\t{%2, %0|%0, %2}"
19385 [(set_attr "type" "mmxmul")
19386 (set_attr "mode" "V2SF")])
19388 (define_insn "femms"
19389 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
19390 (clobber (reg:XF 8))
19391 (clobber (reg:XF 9))
19392 (clobber (reg:XF 10))
19393 (clobber (reg:XF 11))
19394 (clobber (reg:XF 12))
19395 (clobber (reg:XF 13))
19396 (clobber (reg:XF 14))
19397 (clobber (reg:XF 15))
19398 (clobber (reg:DI 29))
19399 (clobber (reg:DI 30))
19400 (clobber (reg:DI 31))
19401 (clobber (reg:DI 32))
19402 (clobber (reg:DI 33))
19403 (clobber (reg:DI 34))
19404 (clobber (reg:DI 35))
19405 (clobber (reg:DI 36))]
19408 [(set_attr "type" "mmx")])
19410 (define_insn "pf2id"
19411 [(set (match_operand:V2SI 0 "register_operand" "=y")
19412 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
19414 "pf2id\\t{%1, %0|%0, %1}"
19415 [(set_attr "type" "mmxcvt")
19416 (set_attr "mode" "V2SF")])
19418 (define_insn "pf2iw"
19419 [(set (match_operand:V2SI 0 "register_operand" "=y")
19422 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
19424 "pf2iw\\t{%1, %0|%0, %1}"
19425 [(set_attr "type" "mmxcvt")
19426 (set_attr "mode" "V2SF")])
19428 (define_insn "pfacc"
19429 [(set (match_operand:V2SF 0 "register_operand" "=y")
19432 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19433 (parallel [(const_int 0)]))
19434 (vec_select:SF (match_dup 1)
19435 (parallel [(const_int 1)])))
19437 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19438 (parallel [(const_int 0)]))
19439 (vec_select:SF (match_dup 2)
19440 (parallel [(const_int 1)])))))]
19442 "pfacc\\t{%2, %0|%0, %2}"
19443 [(set_attr "type" "mmxadd")
19444 (set_attr "mode" "V2SF")])
19446 (define_insn "pfnacc"
19447 [(set (match_operand:V2SF 0 "register_operand" "=y")
19450 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19451 (parallel [(const_int 0)]))
19452 (vec_select:SF (match_dup 1)
19453 (parallel [(const_int 1)])))
19455 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19456 (parallel [(const_int 0)]))
19457 (vec_select:SF (match_dup 2)
19458 (parallel [(const_int 1)])))))]
19460 "pfnacc\\t{%2, %0|%0, %2}"
19461 [(set_attr "type" "mmxadd")
19462 (set_attr "mode" "V2SF")])
19464 (define_insn "pfpnacc"
19465 [(set (match_operand:V2SF 0 "register_operand" "=y")
19468 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19469 (parallel [(const_int 0)]))
19470 (vec_select:SF (match_dup 1)
19471 (parallel [(const_int 1)])))
19473 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19474 (parallel [(const_int 0)]))
19475 (vec_select:SF (match_dup 2)
19476 (parallel [(const_int 1)])))))]
19478 "pfpnacc\\t{%2, %0|%0, %2}"
19479 [(set_attr "type" "mmxadd")
19480 (set_attr "mode" "V2SF")])
19482 (define_insn "pi2fw"
19483 [(set (match_operand:V2SF 0 "register_operand" "=y")
19488 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19489 (parallel [(const_int 0)]))))
19492 (vec_select:SI (match_dup 1)
19493 (parallel [(const_int 1)])))))))]
19495 "pi2fw\\t{%1, %0|%0, %1}"
19496 [(set_attr "type" "mmxcvt")
19497 (set_attr "mode" "V2SF")])
19499 (define_insn "floatv2si2"
19500 [(set (match_operand:V2SF 0 "register_operand" "=y")
19501 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
19503 "pi2fd\\t{%1, %0|%0, %1}"
19504 [(set_attr "type" "mmxcvt")
19505 (set_attr "mode" "V2SF")])
19507 ;; This insn is identical to pavgb in operation, but the opcode is
19508 ;; different. To avoid accidentally matching pavgb, use an unspec.
19510 (define_insn "pavgusb"
19511 [(set (match_operand:V8QI 0 "register_operand" "=y")
19513 [(match_operand:V8QI 1 "register_operand" "0")
19514 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
19517 "pavgusb\\t{%2, %0|%0, %2}"
19518 [(set_attr "type" "mmxshft")
19519 (set_attr "mode" "TI")])
19521 ;; 3DNow reciprical and sqrt
19523 (define_insn "pfrcpv2sf2"
19524 [(set (match_operand:V2SF 0 "register_operand" "=y")
19525 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
19528 "pfrcp\\t{%1, %0|%0, %1}"
19529 [(set_attr "type" "mmx")
19530 (set_attr "mode" "TI")])
19532 (define_insn "pfrcpit1v2sf3"
19533 [(set (match_operand:V2SF 0 "register_operand" "=y")
19534 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19535 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19538 "pfrcpit1\\t{%2, %0|%0, %2}"
19539 [(set_attr "type" "mmx")
19540 (set_attr "mode" "TI")])
19542 (define_insn "pfrcpit2v2sf3"
19543 [(set (match_operand:V2SF 0 "register_operand" "=y")
19544 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19545 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19548 "pfrcpit2\\t{%2, %0|%0, %2}"
19549 [(set_attr "type" "mmx")
19550 (set_attr "mode" "TI")])
19552 (define_insn "pfrsqrtv2sf2"
19553 [(set (match_operand:V2SF 0 "register_operand" "=y")
19554 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
19557 "pfrsqrt\\t{%1, %0|%0, %1}"
19558 [(set_attr "type" "mmx")
19559 (set_attr "mode" "TI")])
19561 (define_insn "pfrsqit1v2sf3"
19562 [(set (match_operand:V2SF 0 "register_operand" "=y")
19563 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19564 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19567 "pfrsqit1\\t{%2, %0|%0, %2}"
19568 [(set_attr "type" "mmx")
19569 (set_attr "mode" "TI")])
19571 (define_insn "pmulhrwv4hi3"
19572 [(set (match_operand:V4HI 0 "register_operand" "=y")
19578 (match_operand:V4HI 1 "register_operand" "0"))
19580 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19581 (const_vector:V4SI [(const_int 32768)
19584 (const_int 32768)]))
19587 "pmulhrw\\t{%2, %0|%0, %2}"
19588 [(set_attr "type" "mmxmul")
19589 (set_attr "mode" "TI")])
19591 (define_insn "pswapdv2si2"
19592 [(set (match_operand:V2SI 0 "register_operand" "=y")
19593 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19594 (parallel [(const_int 1) (const_int 0)])))]
19596 "pswapd\\t{%1, %0|%0, %1}"
19597 [(set_attr "type" "mmxcvt")
19598 (set_attr "mode" "TI")])
19600 (define_insn "pswapdv2sf2"
19601 [(set (match_operand:V2SF 0 "register_operand" "=y")
19602 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
19603 (parallel [(const_int 1) (const_int 0)])))]
19605 "pswapd\\t{%1, %0|%0, %1}"
19606 [(set_attr "type" "mmxcvt")
19607 (set_attr "mode" "TI")])
19609 (define_expand "prefetch"
19610 [(prefetch (match_operand:SI 0 "address_operand" "")
19611 (match_operand:SI 1 "const_int_operand" "")
19612 (match_operand:SI 2 "const_int_operand" ""))]
19613 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
19615 int rw = INTVAL (operands[1]);
19616 int locality = INTVAL (operands[2]);
19618 if (rw != 0 && rw != 1)
19620 if (locality < 0 || locality > 3)
19623 /* Use 3dNOW prefetch in case we are asking for write prefetch not
19624 suported by SSE counterpart or the SSE prefetch is not available
19625 (K6 machines). Otherwise use SSE prefetch as it allows specifying
19627 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
19628 operands[2] = GEN_INT (3);
19630 operands[1] = const0_rtx;
19633 (define_insn "*prefetch_sse"
19634 [(prefetch (match_operand:SI 0 "address_operand" "p")
19636 (match_operand:SI 1 "const_int_operand" ""))]
19637 "TARGET_PREFETCH_SSE"
19639 static const char * const patterns[4] = {
19640 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
19643 int locality = INTVAL (operands[1]);
19644 if (locality < 0 || locality > 3)
19647 return patterns[locality];
19649 [(set_attr "type" "sse")
19650 (set_attr "memory" "none")])
19652 (define_insn "*prefetch_3dnow"
19653 [(prefetch (match_operand:SI 0 "address_operand" "p")
19654 (match_operand:SI 1 "const_int_operand" "n")
19658 if (INTVAL (operands[1]) == 0)
19659 return "prefetch\t%a0";
19661 return "prefetchw\t%a0";
19663 [(set_attr "type" "mmx")
19664 (set_attr "memory" "none")])
19668 (define_insn "addv2df3"
19669 [(set (match_operand:V2DF 0 "register_operand" "=x")
19670 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
19671 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19673 "addpd\t{%2, %0|%0, %2}"
19674 [(set_attr "type" "sseadd")
19675 (set_attr "mode" "V2DF")])
19677 (define_insn "vmaddv2df3"
19678 [(set (match_operand:V2DF 0 "register_operand" "=x")
19679 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
19680 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
19684 "addsd\t{%2, %0|%0, %2}"
19685 [(set_attr "type" "sseadd")
19686 (set_attr "mode" "DF")])
19688 (define_insn "subv2df3"
19689 [(set (match_operand:V2DF 0 "register_operand" "=x")
19690 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
19691 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19693 "subpd\t{%2, %0|%0, %2}"
19694 [(set_attr "type" "sseadd")
19695 (set_attr "mode" "V2DF")])
19697 (define_insn "vmsubv2df3"
19698 [(set (match_operand:V2DF 0 "register_operand" "=x")
19699 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
19700 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
19704 "subsd\t{%2, %0|%0, %2}"
19705 [(set_attr "type" "sseadd")
19706 (set_attr "mode" "DF")])
19708 (define_insn "mulv2df3"
19709 [(set (match_operand:V2DF 0 "register_operand" "=x")
19710 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
19711 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19713 "mulpd\t{%2, %0|%0, %2}"
19714 [(set_attr "type" "ssemul")
19715 (set_attr "mode" "V2DF")])
19717 (define_insn "vmmulv2df3"
19718 [(set (match_operand:V2DF 0 "register_operand" "=x")
19719 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
19720 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
19724 "mulsd\t{%2, %0|%0, %2}"
19725 [(set_attr "type" "ssemul")
19726 (set_attr "mode" "DF")])
19728 (define_insn "divv2df3"
19729 [(set (match_operand:V2DF 0 "register_operand" "=x")
19730 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
19731 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19733 "divpd\t{%2, %0|%0, %2}"
19734 [(set_attr "type" "ssediv")
19735 (set_attr "mode" "V2DF")])
19737 (define_insn "vmdivv2df3"
19738 [(set (match_operand:V2DF 0 "register_operand" "=x")
19739 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
19740 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
19744 "divsd\t{%2, %0|%0, %2}"
19745 [(set_attr "type" "ssediv")
19746 (set_attr "mode" "DF")])
19750 (define_insn "smaxv2df3"
19751 [(set (match_operand:V2DF 0 "register_operand" "=x")
19752 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
19753 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19755 "maxpd\t{%2, %0|%0, %2}"
19756 [(set_attr "type" "sseadd")
19757 (set_attr "mode" "V2DF")])
19759 (define_insn "vmsmaxv2df3"
19760 [(set (match_operand:V2DF 0 "register_operand" "=x")
19761 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
19762 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
19766 "maxsd\t{%2, %0|%0, %2}"
19767 [(set_attr "type" "sseadd")
19768 (set_attr "mode" "DF")])
19770 (define_insn "sminv2df3"
19771 [(set (match_operand:V2DF 0 "register_operand" "=x")
19772 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
19773 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19775 "minpd\t{%2, %0|%0, %2}"
19776 [(set_attr "type" "sseadd")
19777 (set_attr "mode" "V2DF")])
19779 (define_insn "vmsminv2df3"
19780 [(set (match_operand:V2DF 0 "register_operand" "=x")
19781 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
19782 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
19786 "minsd\t{%2, %0|%0, %2}"
19787 [(set_attr "type" "sseadd")
19788 (set_attr "mode" "DF")])
19790 (define_insn "sse2_anddf3"
19791 [(set (match_operand:V2DF 0 "register_operand" "=x")
19792 (subreg:V2DF (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
19793 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
19795 "andpd\t{%2, %0|%0, %2}"
19796 [(set_attr "type" "sselog")
19797 (set_attr "mode" "V2DF")])
19799 (define_insn "sse2_nanddf3"
19800 [(set (match_operand:V2DF 0 "register_operand" "=x")
19801 (subreg:V2DF (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "0") 0))
19802 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
19804 "andnpd\t{%2, %0|%0, %2}"
19805 [(set_attr "type" "sselog")
19806 (set_attr "mode" "V2DF")])
19808 (define_insn "sse2_iordf3"
19809 [(set (match_operand:V2DF 0 "register_operand" "=x")
19810 (subreg:V2DF (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
19811 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
19813 "orpd\t{%2, %0|%0, %2}"
19814 [(set_attr "type" "sselog")
19815 (set_attr "mode" "V2DF")])
19817 (define_insn "sse2_xordf3"
19818 [(set (match_operand:V2DF 0 "register_operand" "=x")
19819 (subreg:V2DF (xor:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
19820 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
19822 "xorpd\t{%2, %0|%0, %2}"
19823 [(set_attr "type" "sselog")
19824 (set_attr "mode" "V2DF")])
19825 ;; SSE2 square root. There doesn't appear to be an extension for the
19826 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
19828 (define_insn "sqrtv2df2"
19829 [(set (match_operand:V2DF 0 "register_operand" "=x")
19830 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
19832 "sqrtpd\t{%1, %0|%0, %1}"
19833 [(set_attr "type" "sse")
19834 (set_attr "mode" "V2DF")])
19836 (define_insn "vmsqrtv2df2"
19837 [(set (match_operand:V2DF 0 "register_operand" "=x")
19838 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
19839 (match_operand:V2DF 2 "register_operand" "0")
19842 "sqrtsd\t{%1, %0|%0, %1}"
19843 [(set_attr "type" "sse")
19844 (set_attr "mode" "SF")])
19846 ;; SSE mask-generating compares
19848 (define_insn "maskcmpv2df3"
19849 [(set (match_operand:V2DI 0 "register_operand" "=x")
19850 (match_operator:V2DI 3 "sse_comparison_operator"
19851 [(match_operand:V2DF 1 "register_operand" "0")
19852 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
19854 "cmp%D3pd\t{%2, %0|%0, %2}"
19855 [(set_attr "type" "ssecmp")
19856 (set_attr "mode" "V2DF")])
19858 (define_insn "maskncmpv2df3"
19859 [(set (match_operand:V2DI 0 "register_operand" "=x")
19861 (match_operator:V2DI 3 "sse_comparison_operator"
19862 [(match_operand:V2DF 1 "register_operand" "0")
19863 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
19865 "cmpn%D3pd\t{%2, %0|%0, %2}"
19866 [(set_attr "type" "ssecmp")
19867 (set_attr "mode" "V2DF")])
19869 (define_insn "vmmaskcmpv2df3"
19870 [(set (match_operand:V2DI 0 "register_operand" "=x")
19872 (match_operator:V2DI 3 "sse_comparison_operator"
19873 [(match_operand:V2DF 1 "register_operand" "0")
19874 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
19878 "cmp%D3sd\t{%2, %0|%0, %2}"
19879 [(set_attr "type" "ssecmp")
19880 (set_attr "mode" "DF")])
19882 (define_insn "vmmaskncmpv2df3"
19883 [(set (match_operand:V2DI 0 "register_operand" "=x")
19886 (match_operator:V2DI 3 "sse_comparison_operator"
19887 [(match_operand:V2DF 1 "register_operand" "0")
19888 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
19889 (subreg:V2DI (match_dup 1) 0)
19892 "cmp%D3sd\t{%2, %0|%0, %2}"
19893 [(set_attr "type" "ssecmp")
19894 (set_attr "mode" "DF")])
19896 (define_insn "sse2_comi"
19897 [(set (reg:CCFP 17)
19898 (match_operator:CCFP 2 "sse_comparison_operator"
19900 (match_operand:V2DF 0 "register_operand" "x")
19901 (parallel [(const_int 0)]))
19903 (match_operand:V2DF 1 "register_operand" "x")
19904 (parallel [(const_int 0)]))]))]
19906 "comisd\t{%1, %0|%0, %1}"
19907 [(set_attr "type" "ssecmp")
19908 (set_attr "mode" "DF")])
19910 (define_insn "sse2_ucomi"
19911 [(set (reg:CCFPU 17)
19912 (match_operator:CCFPU 2 "sse_comparison_operator"
19914 (match_operand:V2DF 0 "register_operand" "x")
19915 (parallel [(const_int 0)]))
19917 (match_operand:V2DF 1 "register_operand" "x")
19918 (parallel [(const_int 0)]))]))]
19920 "ucomisd\t{%1, %0|%0, %1}"
19921 [(set_attr "type" "ssecmp")
19922 (set_attr "mode" "DF")])
19924 ;; SSE Strange Moves.
19926 (define_insn "sse2_movmskpd"
19927 [(set (match_operand:SI 0 "register_operand" "=r")
19928 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
19931 "movmskpd\t{%1, %0|%0, %1}"
19932 [(set_attr "type" "ssecvt")
19933 (set_attr "mode" "V2DF")])
19935 (define_insn "sse2_pmovmskb"
19936 [(set (match_operand:SI 0 "register_operand" "=r")
19937 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
19940 "pmovmskb\t{%1, %0|%0, %1}"
19941 [(set_attr "type" "ssecvt")
19942 (set_attr "mode" "V2DF")])
19944 (define_insn "sse2_maskmovdqu"
19945 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
19946 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
19947 (match_operand:V16QI 2 "register_operand" "x")]
19950 ;; @@@ check ordering of operands in intel/nonintel syntax
19951 "maskmovdqu\t{%2, %1|%1, %2}"
19952 [(set_attr "type" "ssecvt")
19953 (set_attr "mode" "TI")])
19955 (define_insn "sse2_movntv2df"
19956 [(set (match_operand:V2DF 0 "memory_operand" "=m")
19957 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
19960 "movntpd\t{%1, %0|%0, %1}"
19961 [(set_attr "type" "ssecvt")
19962 (set_attr "mode" "V2DF")])
19964 (define_insn "sse2_movntv2di"
19965 [(set (match_operand:V2DI 0 "memory_operand" "=m")
19966 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
19969 "movntdq\t{%1, %0|%0, %1}"
19970 [(set_attr "type" "ssecvt")
19971 (set_attr "mode" "TI")])
19973 (define_insn "sse2_movntsi"
19974 [(set (match_operand:SI 0 "memory_operand" "=m")
19975 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
19978 "movnti\t{%1, %0|%0, %1}"
19979 [(set_attr "type" "ssecvt")
19980 (set_attr "mode" "V2DF")])
19982 ;; SSE <-> integer/MMX conversions
19984 ;; Conversions between SI and SF
19986 (define_insn "cvtdq2ps"
19987 [(set (match_operand:V4SF 0 "register_operand" "=x")
19988 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
19990 "cvtdq2ps\t{%1, %0|%0, %1}"
19991 [(set_attr "type" "ssecvt")
19992 (set_attr "mode" "V2DF")])
19994 (define_insn "cvtps2dq"
19995 [(set (match_operand:V4SI 0 "register_operand" "=x")
19996 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
19998 "cvtps2dq\t{%1, %0|%0, %1}"
19999 [(set_attr "type" "ssecvt")
20000 (set_attr "mode" "TI")])
20002 (define_insn "cvttps2dq"
20003 [(set (match_operand:V4SI 0 "register_operand" "=x")
20004 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20007 "cvttps2dq\t{%1, %0|%0, %1}"
20008 [(set_attr "type" "ssecvt")
20009 (set_attr "mode" "TI")])
20011 ;; Conversions between SI and DF
20013 (define_insn "cvtdq2pd"
20014 [(set (match_operand:V2DF 0 "register_operand" "=x")
20015 (float:V2DF (vec_select:V2SI
20016 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
20019 (const_int 1)]))))]
20021 "cvtdq2pd\t{%1, %0|%0, %1}"
20022 [(set_attr "type" "ssecvt")
20023 (set_attr "mode" "V2DF")])
20025 (define_insn "cvtpd2dq"
20026 [(set (match_operand:V4SI 0 "register_operand" "=x")
20028 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
20029 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20031 "cvtpd2dq\t{%1, %0|%0, %1}"
20032 [(set_attr "type" "ssecvt")
20033 (set_attr "mode" "TI")])
20035 (define_insn "cvttpd2dq"
20036 [(set (match_operand:V4SI 0 "register_operand" "=x")
20038 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20040 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20042 "cvttpd2dq\t{%1, %0|%0, %1}"
20043 [(set_attr "type" "ssecvt")
20044 (set_attr "mode" "TI")])
20046 (define_insn "cvtpd2pi"
20047 [(set (match_operand:V2SI 0 "register_operand" "=y")
20048 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
20050 "cvtpd2pi\t{%1, %0|%0, %1}"
20051 [(set_attr "type" "ssecvt")
20052 (set_attr "mode" "TI")])
20054 (define_insn "cvttpd2pi"
20055 [(set (match_operand:V2SI 0 "register_operand" "=y")
20056 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20059 "cvttpd2pi\t{%1, %0|%0, %1}"
20060 [(set_attr "type" "ssecvt")
20061 (set_attr "mode" "TI")])
20063 (define_insn "cvtpi2pd"
20064 [(set (match_operand:V2DF 0 "register_operand" "=x")
20065 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
20067 "cvtpi2pd\t{%1, %0|%0, %1}"
20068 [(set_attr "type" "ssecvt")
20069 (set_attr "mode" "TI")])
20071 ;; Conversions between SI and DF
20073 (define_insn "cvtsd2si"
20074 [(set (match_operand:SI 0 "register_operand" "=r")
20075 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20076 (parallel [(const_int 0)]))))]
20078 "cvtsd2si\t{%1, %0|%0, %1}"
20079 [(set_attr "type" "ssecvt")
20080 (set_attr "mode" "SI")])
20082 (define_insn "cvttsd2si"
20083 [(set (match_operand:SI 0 "register_operand" "=r")
20084 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20085 (parallel [(const_int 0)]))] UNSPEC_FIX))]
20087 "cvttsd2si\t{%1, %0|%0, %1}"
20088 [(set_attr "type" "ssecvt")
20089 (set_attr "mode" "SI")])
20091 (define_insn "cvtsi2sd"
20092 [(set (match_operand:V2DF 0 "register_operand" "=x")
20093 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20094 (vec_duplicate:V2DF
20096 (match_operand:SI 2 "nonimmediate_operand" "rm")))
20099 "cvtsd2si\t{%2, %0|%0, %2}"
20100 [(set_attr "type" "ssecvt")
20101 (set_attr "mode" "DF")])
20103 ;; Conversions between SF and DF
20105 (define_insn "cvtsd2ss"
20106 [(set (match_operand:V4SF 0 "register_operand" "=x")
20107 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
20108 (vec_duplicate:V4SF
20109 (float_truncate:V2SF
20110 (match_operand:V2DF 2 "register_operand" "xm")))
20113 "cvtsd2ss\t{%2, %0|%0, %2}"
20114 [(set_attr "type" "ssecvt")
20115 (set_attr "mode" "SF")])
20117 (define_insn "cvtss2sd"
20118 [(set (match_operand:V2DF 0 "register_operand" "=x")
20119 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20122 (match_operand:V4SF 2 "register_operand" "xm")
20123 (parallel [(const_int 0)
20127 "cvtss2sd\t{%2, %0|%0, %2}"
20128 [(set_attr "type" "ssecvt")
20129 (set_attr "mode" "DF")])
20131 (define_insn "cvtpd2ps"
20132 [(set (match_operand:V4SF 0 "register_operand" "=x")
20135 (subreg:V2SI (float_truncate:V2SF
20136 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
20137 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
20139 "cvtpd2ps\t{%1, %0|%0, %1}"
20140 [(set_attr "type" "ssecvt")
20141 (set_attr "mode" "V4SF")])
20143 (define_insn "cvtps2pd"
20144 [(set (match_operand:V2DF 0 "register_operand" "=x")
20146 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
20147 (parallel [(const_int 0)
20148 (const_int 1)]))))]
20150 "cvtps2pd\t{%1, %0|%0, %1}"
20151 [(set_attr "type" "ssecvt")
20152 (set_attr "mode" "V2DF")])
20154 ;; SSE2 variants of MMX insns
20158 (define_insn "addv16qi3"
20159 [(set (match_operand:V16QI 0 "register_operand" "=x")
20160 (plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20161 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20163 "paddb\t{%2, %0|%0, %2}"
20164 [(set_attr "type" "sseiadd")
20165 (set_attr "mode" "TI")])
20167 (define_insn "addv8hi3"
20168 [(set (match_operand:V8HI 0 "register_operand" "=x")
20169 (plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20170 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20172 "paddw\t{%2, %0|%0, %2}"
20173 [(set_attr "type" "sseiadd")
20174 (set_attr "mode" "TI")])
20176 (define_insn "addv4si3"
20177 [(set (match_operand:V4SI 0 "register_operand" "=x")
20178 (plus:V4SI (match_operand:V4SI 1 "register_operand" "0")
20179 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20181 "paddd\t{%2, %0|%0, %2}"
20182 [(set_attr "type" "sseiadd")
20183 (set_attr "mode" "TI")])
20185 (define_insn "addv2di3"
20186 [(set (match_operand:V2DI 0 "register_operand" "=x")
20187 (plus:V2DI (match_operand:V2DI 1 "register_operand" "0")
20188 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20190 "paddq\t{%2, %0|%0, %2}"
20191 [(set_attr "type" "sseiadd")
20192 (set_attr "mode" "TI")])
20194 (define_insn "ssaddv16qi3"
20195 [(set (match_operand:V16QI 0 "register_operand" "=x")
20196 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20197 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20199 "paddsb\t{%2, %0|%0, %2}"
20200 [(set_attr "type" "sseiadd")
20201 (set_attr "mode" "TI")])
20203 (define_insn "ssaddv8hi3"
20204 [(set (match_operand:V8HI 0 "register_operand" "=x")
20205 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20206 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20208 "paddsw\t{%2, %0|%0, %2}"
20209 [(set_attr "type" "sseiadd")
20210 (set_attr "mode" "TI")])
20212 (define_insn "usaddv16qi3"
20213 [(set (match_operand:V16QI 0 "register_operand" "=x")
20214 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20215 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20217 "paddusb\t{%2, %0|%0, %2}"
20218 [(set_attr "type" "sseiadd")
20219 (set_attr "mode" "TI")])
20221 (define_insn "usaddv8hi3"
20222 [(set (match_operand:V8HI 0 "register_operand" "=x")
20223 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20224 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20226 "paddusw\t{%2, %0|%0, %2}"
20227 [(set_attr "type" "sseiadd")
20228 (set_attr "mode" "TI")])
20230 (define_insn "subv16qi3"
20231 [(set (match_operand:V16QI 0 "register_operand" "=x")
20232 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20233 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20235 "psubb\t{%2, %0|%0, %2}"
20236 [(set_attr "type" "sseiadd")
20237 (set_attr "mode" "TI")])
20239 (define_insn "subv8hi3"
20240 [(set (match_operand:V8HI 0 "register_operand" "=x")
20241 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20242 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20244 "psubw\t{%2, %0|%0, %2}"
20245 [(set_attr "type" "sseiadd")
20246 (set_attr "mode" "TI")])
20248 (define_insn "subv4si3"
20249 [(set (match_operand:V4SI 0 "register_operand" "=x")
20250 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
20251 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20253 "psubd\t{%2, %0|%0, %2}"
20254 [(set_attr "type" "sseiadd")
20255 (set_attr "mode" "TI")])
20257 (define_insn "subv2di3"
20258 [(set (match_operand:V2DI 0 "register_operand" "=x")
20259 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
20260 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20262 "psubq\t{%2, %0|%0, %2}"
20263 [(set_attr "type" "sseiadd")
20264 (set_attr "mode" "TI")])
20266 (define_insn "sssubv16qi3"
20267 [(set (match_operand:V16QI 0 "register_operand" "=x")
20268 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20269 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20271 "psubsb\t{%2, %0|%0, %2}"
20272 [(set_attr "type" "sseiadd")
20273 (set_attr "mode" "TI")])
20275 (define_insn "sssubv8hi3"
20276 [(set (match_operand:V8HI 0 "register_operand" "=x")
20277 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20278 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20280 "psubsw\t{%2, %0|%0, %2}"
20281 [(set_attr "type" "sseiadd")
20282 (set_attr "mode" "TI")])
20284 (define_insn "ussubv16qi3"
20285 [(set (match_operand:V16QI 0 "register_operand" "=x")
20286 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20287 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20289 "psubusb\t{%2, %0|%0, %2}"
20290 [(set_attr "type" "sseiadd")
20291 (set_attr "mode" "TI")])
20293 (define_insn "ussubv8hi3"
20294 [(set (match_operand:V8HI 0 "register_operand" "=x")
20295 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20296 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20298 "psubusw\t{%2, %0|%0, %2}"
20299 [(set_attr "type" "sseiadd")
20300 (set_attr "mode" "TI")])
20302 (define_insn "mulv8hi3"
20303 [(set (match_operand:V8HI 0 "register_operand" "=x")
20304 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
20305 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20307 "pmullw\t{%2, %0|%0, %2}"
20308 [(set_attr "type" "sseimul")
20309 (set_attr "mode" "TI")])
20311 (define_insn "smulv8hi3_highpart"
20312 [(set (match_operand:V8HI 0 "register_operand" "=x")
20315 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
20316 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
20319 "pmulhw\t{%2, %0|%0, %2}"
20320 [(set_attr "type" "sseimul")
20321 (set_attr "mode" "TI")])
20323 (define_insn "umulv8hi3_highpart"
20324 [(set (match_operand:V8HI 0 "register_operand" "=x")
20327 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
20328 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
20331 "pmulhuw\t{%2, %0|%0, %2}"
20332 [(set_attr "type" "sseimul")
20333 (set_attr "mode" "TI")])
20335 (define_insn "sse2_umulsidi3"
20336 [(set (match_operand:DI 0 "register_operand" "=y")
20337 (mult:DI (zero_extend:DI (vec_select:SI
20338 (match_operand:V2SI 1 "register_operand" "0")
20339 (parallel [(const_int 0)])))
20340 (zero_extend:DI (vec_select:SI
20341 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
20342 (parallel [(const_int 0)])))))]
20344 "pmuludq\t{%2, %0|%0, %2}"
20345 [(set_attr "type" "sseimul")
20346 (set_attr "mode" "TI")])
20348 (define_insn "sse2_umulv2siv2di3"
20349 [(set (match_operand:V2DI 0 "register_operand" "=y")
20350 (mult:V2DI (zero_extend:V2DI
20352 (match_operand:V4SI 1 "register_operand" "0")
20353 (parallel [(const_int 0) (const_int 2)])))
20356 (match_operand:V4SI 2 "nonimmediate_operand" "ym")
20357 (parallel [(const_int 0) (const_int 2)])))))]
20359 "pmuludq\t{%2, %0|%0, %2}"
20360 [(set_attr "type" "sseimul")
20361 (set_attr "mode" "TI")])
20363 (define_insn "sse2_pmaddwd"
20364 [(set (match_operand:V4SI 0 "register_operand" "=x")
20367 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
20368 (parallel [(const_int 0)
20372 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
20373 (parallel [(const_int 0)
20378 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
20379 (parallel [(const_int 1)
20383 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
20384 (parallel [(const_int 1)
20387 (const_int 7)]))))))]
20389 "pmaddwd\t{%2, %0|%0, %2}"
20390 [(set_attr "type" "sseiadd")
20391 (set_attr "mode" "TI")])
20393 ;; Same as pxor, but don't show input operands so that we don't think
20395 (define_insn "sse2_clrti"
20396 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
20398 "pxor\t{%0, %0|%0, %0}"
20399 [(set_attr "type" "sseiadd")
20400 (set_attr "memory" "none")
20401 (set_attr "mode" "TI")])
20403 ;; MMX unsigned averages/sum of absolute differences
20405 (define_insn "sse2_uavgv16qi3"
20406 [(set (match_operand:V16QI 0 "register_operand" "=x")
20408 (plus:V16QI (plus:V16QI
20409 (match_operand:V16QI 1 "register_operand" "0")
20410 (match_operand:V16QI 2 "nonimmediate_operand" "ym"))
20411 (const_vector:V16QI [(const_int 1) (const_int 1)
20412 (const_int 1) (const_int 1)
20413 (const_int 1) (const_int 1)
20414 (const_int 1) (const_int 1)
20415 (const_int 1) (const_int 1)
20416 (const_int 1) (const_int 1)
20417 (const_int 1) (const_int 1)
20418 (const_int 1) (const_int 1)]))
20421 "pavgb\t{%2, %0|%0, %2}"
20422 [(set_attr "type" "sseiadd")
20423 (set_attr "mode" "TI")])
20425 (define_insn "sse2_uavgv8hi3"
20426 [(set (match_operand:V8HI 0 "register_operand" "=x")
20428 (plus:V8HI (plus:V8HI
20429 (match_operand:V8HI 1 "register_operand" "0")
20430 (match_operand:V8HI 2 "nonimmediate_operand" "ym"))
20431 (const_vector:V8HI [(const_int 1) (const_int 1)
20432 (const_int 1) (const_int 1)
20433 (const_int 1) (const_int 1)
20434 (const_int 1) (const_int 1)]))
20437 "pavgw\t{%2, %0|%0, %2}"
20438 [(set_attr "type" "sseiadd")
20439 (set_attr "mode" "TI")])
20441 ;; @@@ this isn't the right representation.
20442 (define_insn "sse2_psadbw"
20443 [(set (match_operand:V2DI 0 "register_operand" "=x")
20444 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
20445 (match_operand:V16QI 2 "nonimmediate_operand" "ym")]
20448 "psadbw\t{%2, %0|%0, %2}"
20449 [(set_attr "type" "sseiadd")
20450 (set_attr "mode" "TI")])
20453 ;; MMX insert/extract/shuffle
20455 (define_insn "sse2_pinsrw"
20456 [(set (match_operand:V8HI 0 "register_operand" "=x")
20457 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
20458 (vec_duplicate:V8HI
20459 (match_operand:SI 2 "nonimmediate_operand" "rm"))
20460 (match_operand:SI 3 "immediate_operand" "i")))]
20462 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20463 [(set_attr "type" "ssecvt")
20464 (set_attr "mode" "TI")])
20466 (define_insn "sse2_pextrw"
20467 [(set (match_operand:SI 0 "register_operand" "=r")
20469 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
20471 [(match_operand:SI 2 "immediate_operand" "i")]))))]
20473 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20474 [(set_attr "type" "ssecvt")
20475 (set_attr "mode" "TI")])
20477 (define_insn "sse2_pshufd"
20478 [(set (match_operand:V4SI 0 "register_operand" "=x")
20479 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
20480 (match_operand:SI 2 "immediate_operand" "i")]
20483 "pshufd\t{%2, %1, %0|%0, %1, %2}"
20484 [(set_attr "type" "ssecvt")
20485 (set_attr "mode" "TI")])
20487 (define_insn "sse2_pshuflw"
20488 [(set (match_operand:V8HI 0 "register_operand" "=x")
20489 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
20490 (match_operand:SI 2 "immediate_operand" "i")]
20493 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
20494 [(set_attr "type" "ssecvt")
20495 (set_attr "mode" "TI")])
20497 (define_insn "sse2_pshufhw"
20498 [(set (match_operand:V8HI 0 "register_operand" "=x")
20499 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
20500 (match_operand:SI 2 "immediate_operand" "i")]
20503 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
20504 [(set_attr "type" "ssecvt")
20505 (set_attr "mode" "TI")])
20507 ;; MMX mask-generating comparisons
20509 (define_insn "eqv16qi3"
20510 [(set (match_operand:V16QI 0 "register_operand" "=x")
20511 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
20512 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20514 "pcmpeqb\t{%2, %0|%0, %2}"
20515 [(set_attr "type" "ssecmp")
20516 (set_attr "mode" "TI")])
20518 (define_insn "eqv8hi3"
20519 [(set (match_operand:V8HI 0 "register_operand" "=x")
20520 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
20521 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20523 "pcmpeqw\t{%2, %0|%0, %2}"
20524 [(set_attr "type" "ssecmp")
20525 (set_attr "mode" "TI")])
20527 (define_insn "eqv4si3"
20528 [(set (match_operand:V4SI 0 "register_operand" "=x")
20529 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
20530 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20532 "pcmpeqd\t{%2, %0|%0, %2}"
20533 [(set_attr "type" "ssecmp")
20534 (set_attr "mode" "TI")])
20536 (define_insn "gtv16qi3"
20537 [(set (match_operand:V16QI 0 "register_operand" "=x")
20538 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
20539 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20541 "pcmpgtb\t{%2, %0|%0, %2}"
20542 [(set_attr "type" "ssecmp")
20543 (set_attr "mode" "TI")])
20545 (define_insn "gtv8hi3"
20546 [(set (match_operand:V8HI 0 "register_operand" "=x")
20547 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
20548 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20550 "pcmpgtw\t{%2, %0|%0, %2}"
20551 [(set_attr "type" "ssecmp")
20552 (set_attr "mode" "TI")])
20554 (define_insn "gtv4si3"
20555 [(set (match_operand:V4SI 0 "register_operand" "=x")
20556 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
20557 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20559 "pcmpgtd\t{%2, %0|%0, %2}"
20560 [(set_attr "type" "ssecmp")
20561 (set_attr "mode" "TI")])
20564 ;; MMX max/min insns
20566 (define_insn "umaxv16qi3"
20567 [(set (match_operand:V16QI 0 "register_operand" "=x")
20568 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
20569 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20571 "pmaxub\t{%2, %0|%0, %2}"
20572 [(set_attr "type" "sseiadd")
20573 (set_attr "mode" "TI")])
20575 (define_insn "smaxv8hi3"
20576 [(set (match_operand:V8HI 0 "register_operand" "=x")
20577 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
20578 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20580 "pmaxsw\t{%2, %0|%0, %2}"
20581 [(set_attr "type" "sseiadd")
20582 (set_attr "mode" "TI")])
20584 (define_insn "uminv16qi3"
20585 [(set (match_operand:V16QI 0 "register_operand" "=x")
20586 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
20587 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20589 "pminub\t{%2, %0|%0, %2}"
20590 [(set_attr "type" "sseiadd")
20591 (set_attr "mode" "TI")])
20593 (define_insn "sminv8hi3"
20594 [(set (match_operand:V8HI 0 "register_operand" "=x")
20595 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
20596 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20598 "pminsw\t{%2, %0|%0, %2}"
20599 [(set_attr "type" "sseiadd")
20600 (set_attr "mode" "TI")])
20605 (define_insn "ashrv8hi3"
20606 [(set (match_operand:V8HI 0 "register_operand" "=x")
20607 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
20608 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20610 "psraw\t{%2, %0|%0, %2}"
20611 [(set_attr "type" "sseishft")
20612 (set_attr "mode" "TI")])
20614 (define_insn "ashrv4si3"
20615 [(set (match_operand:V4SI 0 "register_operand" "=x")
20616 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
20617 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20619 "psrad\t{%2, %0|%0, %2}"
20620 [(set_attr "type" "sseishft")
20621 (set_attr "mode" "TI")])
20623 (define_insn "lshrv8hi3"
20624 [(set (match_operand:V8HI 0 "register_operand" "=x")
20625 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
20626 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20628 "psrlw\t{%2, %0|%0, %2}"
20629 [(set_attr "type" "sseishft")
20630 (set_attr "mode" "TI")])
20632 (define_insn "lshrv4si3"
20633 [(set (match_operand:V4SI 0 "register_operand" "=x")
20634 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
20635 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20637 "psrld\t{%2, %0|%0, %2}"
20638 [(set_attr "type" "sseishft")
20639 (set_attr "mode" "TI")])
20641 (define_insn "lshrv2di3"
20642 [(set (match_operand:V2DI 0 "register_operand" "=x")
20643 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
20644 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20646 "psrlq\t{%2, %0|%0, %2}"
20647 [(set_attr "type" "sseishft")
20648 (set_attr "mode" "TI")])
20650 (define_insn "ashlv8hi3"
20651 [(set (match_operand:V8HI 0 "register_operand" "=x")
20652 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
20653 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20655 "psllw\t{%2, %0|%0, %2}"
20656 [(set_attr "type" "sseishft")
20657 (set_attr "mode" "TI")])
20659 (define_insn "ashlv4si3"
20660 [(set (match_operand:V4SI 0 "register_operand" "=x")
20661 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
20662 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20664 "pslld\t{%2, %0|%0, %2}"
20665 [(set_attr "type" "sseishft")
20666 (set_attr "mode" "TI")])
20668 (define_insn "ashlv2di3"
20669 [(set (match_operand:V2DI 0 "register_operand" "=x")
20670 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
20671 (match_operand:SI 2 "nonmemory_operand" "ri")))]
20673 "psllq\t{%2, %0|%0, %2}"
20674 [(set_attr "type" "sseishft")
20675 (set_attr "mode" "TI")])
20677 (define_insn "ashrv8hi3_ti"
20678 [(set (match_operand:V8HI 0 "register_operand" "=x")
20679 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
20680 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20682 "psraw\t{%2, %0|%0, %2}"
20683 [(set_attr "type" "sseishft")
20684 (set_attr "mode" "TI")])
20686 (define_insn "ashrv4si3_ti"
20687 [(set (match_operand:V4SI 0 "register_operand" "=x")
20688 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
20689 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20691 "psrad\t{%2, %0|%0, %2}"
20692 [(set_attr "type" "sseishft")
20693 (set_attr "mode" "TI")])
20695 (define_insn "lshrv8hi3_ti"
20696 [(set (match_operand:V8HI 0 "register_operand" "=x")
20697 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
20698 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20700 "psrlw\t{%2, %0|%0, %2}"
20701 [(set_attr "type" "sseishft")
20702 (set_attr "mode" "TI")])
20704 (define_insn "lshrv4si3_ti"
20705 [(set (match_operand:V4SI 0 "register_operand" "=x")
20706 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
20707 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20709 "psrld\t{%2, %0|%0, %2}"
20710 [(set_attr "type" "sseishft")
20711 (set_attr "mode" "TI")])
20713 (define_insn "lshrv2di3_ti"
20714 [(set (match_operand:V2DI 0 "register_operand" "=x")
20715 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
20716 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20718 "psrlq\t{%2, %0|%0, %2}"
20719 [(set_attr "type" "sseishft")
20720 (set_attr "mode" "TI")])
20722 (define_insn "ashlv8hi3_ti"
20723 [(set (match_operand:V8HI 0 "register_operand" "=x")
20724 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
20725 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20727 "psllw\t{%2, %0|%0, %2}"
20728 [(set_attr "type" "sseishft")
20729 (set_attr "mode" "TI")])
20731 (define_insn "ashlv4si3_ti"
20732 [(set (match_operand:V4SI 0 "register_operand" "=x")
20733 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
20734 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20736 "pslld\t{%2, %0|%0, %2}"
20737 [(set_attr "type" "sseishft")
20738 (set_attr "mode" "TI")])
20740 (define_insn "ashlv2di3_ti"
20741 [(set (match_operand:V2DI 0 "register_operand" "=x")
20742 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
20743 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
20745 "psllq\t{%2, %0|%0, %2}"
20746 [(set_attr "type" "sseishft")
20747 (set_attr "mode" "TI")])
20749 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
20750 ;; we wouldn't need here it since we never generate TImode arithmetic.
20752 ;; There has to be some kind of prize for the weirdest new instruction...
20753 (define_insn "sse2_ashlti3"
20754 [(set (match_operand:TI 0 "register_operand" "=x")
20756 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
20757 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
20758 (const_int 8)))] UNSPEC_NOP))]
20760 "pslldq\t{%2, %0|%0, %2}"
20761 [(set_attr "type" "sseishft")
20762 (set_attr "mode" "TI")])
20764 (define_insn "sse2_lshrti3"
20765 [(set (match_operand:TI 0 "register_operand" "=x")
20767 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
20768 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
20769 (const_int 8)))] UNSPEC_NOP))]
20771 "pslrdq\t{%2, %0|%0, %2}"
20772 [(set_attr "type" "sseishft")
20773 (set_attr "mode" "TI")])
20777 (define_insn "sse2_unpckhpd"
20778 [(set (match_operand:V2DF 0 "register_operand" "=x")
20780 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
20781 (parallel [(const_int 1)]))
20782 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
20783 (parallel [(const_int 0)]))))]
20785 "unpckhpd\t{%2, %0|%0, %2}"
20786 [(set_attr "type" "ssecvt")
20787 (set_attr "mode" "TI")])
20789 (define_insn "sse2_unpcklpd"
20790 [(set (match_operand:V2DF 0 "register_operand" "=x")
20792 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
20793 (parallel [(const_int 0)]))
20794 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
20795 (parallel [(const_int 1)]))))]
20797 "unpcklpd\t{%2, %0|%0, %2}"
20798 [(set_attr "type" "ssecvt")
20799 (set_attr "mode" "TI")])
20801 ;; MMX pack/unpack insns.
20803 (define_insn "sse2_packsswb"
20804 [(set (match_operand:V16QI 0 "register_operand" "=x")
20806 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
20807 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
20809 "packsswb\t{%2, %0|%0, %2}"
20810 [(set_attr "type" "ssecvt")
20811 (set_attr "mode" "TI")])
20813 (define_insn "sse2_packssdw"
20814 [(set (match_operand:V8HI 0 "register_operand" "=x")
20816 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
20817 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
20819 "packssdw\t{%2, %0|%0, %2}"
20820 [(set_attr "type" "ssecvt")
20821 (set_attr "mode" "TI")])
20823 (define_insn "sse2_packuswb"
20824 [(set (match_operand:V16QI 0 "register_operand" "=x")
20826 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
20827 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
20829 "packuswb\t{%2, %0|%0, %2}"
20830 [(set_attr "type" "ssecvt")
20831 (set_attr "mode" "TI")])
20833 (define_insn "sse2_punpckhbw"
20834 [(set (match_operand:V16QI 0 "register_operand" "=x")
20836 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
20837 (parallel [(const_int 8) (const_int 0)
20838 (const_int 9) (const_int 1)
20839 (const_int 10) (const_int 2)
20840 (const_int 11) (const_int 3)
20841 (const_int 12) (const_int 4)
20842 (const_int 13) (const_int 5)
20843 (const_int 14) (const_int 6)
20844 (const_int 15) (const_int 7)]))
20845 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
20846 (parallel [(const_int 0) (const_int 8)
20847 (const_int 1) (const_int 9)
20848 (const_int 2) (const_int 10)
20849 (const_int 3) (const_int 11)
20850 (const_int 4) (const_int 12)
20851 (const_int 5) (const_int 13)
20852 (const_int 6) (const_int 14)
20853 (const_int 7) (const_int 15)]))
20854 (const_int 21845)))]
20856 "punpckhbw\t{%2, %0|%0, %2}"
20857 [(set_attr "type" "ssecvt")
20858 (set_attr "mode" "TI")])
20860 (define_insn "sse2_punpckhwd"
20861 [(set (match_operand:V8HI 0 "register_operand" "=x")
20863 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
20864 (parallel [(const_int 4) (const_int 0)
20865 (const_int 5) (const_int 1)
20866 (const_int 6) (const_int 2)
20867 (const_int 7) (const_int 3)]))
20868 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
20869 (parallel [(const_int 0) (const_int 4)
20870 (const_int 1) (const_int 5)
20871 (const_int 2) (const_int 6)
20872 (const_int 3) (const_int 7)]))
20875 "punpckhwd\t{%2, %0|%0, %2}"
20876 [(set_attr "type" "ssecvt")
20877 (set_attr "mode" "TI")])
20879 (define_insn "sse2_punpckhdq"
20880 [(set (match_operand:V4SI 0 "register_operand" "=x")
20882 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
20883 (parallel [(const_int 2) (const_int 0)
20884 (const_int 3) (const_int 1)]))
20885 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
20886 (parallel [(const_int 0) (const_int 2)
20887 (const_int 1) (const_int 3)]))
20890 "punpckhdq\t{%2, %0|%0, %2}"
20891 [(set_attr "type" "ssecvt")
20892 (set_attr "mode" "TI")])
20894 (define_insn "sse2_punpcklbw"
20895 [(set (match_operand:V16QI 0 "register_operand" "=x")
20897 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
20898 (parallel [(const_int 0) (const_int 8)
20899 (const_int 1) (const_int 9)
20900 (const_int 2) (const_int 10)
20901 (const_int 3) (const_int 11)
20902 (const_int 4) (const_int 12)
20903 (const_int 5) (const_int 13)
20904 (const_int 6) (const_int 14)
20905 (const_int 7) (const_int 15)]))
20906 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
20907 (parallel [(const_int 8) (const_int 0)
20908 (const_int 9) (const_int 1)
20909 (const_int 10) (const_int 2)
20910 (const_int 11) (const_int 3)
20911 (const_int 12) (const_int 4)
20912 (const_int 13) (const_int 5)
20913 (const_int 14) (const_int 6)
20914 (const_int 15) (const_int 7)]))
20915 (const_int 21845)))]
20917 "punpcklbw\t{%2, %0|%0, %2}"
20918 [(set_attr "type" "ssecvt")
20919 (set_attr "mode" "TI")])
20921 (define_insn "sse2_punpcklwd"
20922 [(set (match_operand:V8HI 0 "register_operand" "=x")
20924 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
20925 (parallel [(const_int 0) (const_int 4)
20926 (const_int 1) (const_int 5)
20927 (const_int 2) (const_int 6)
20928 (const_int 3) (const_int 7)]))
20929 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
20930 (parallel [(const_int 4) (const_int 0)
20931 (const_int 5) (const_int 1)
20932 (const_int 6) (const_int 2)
20933 (const_int 7) (const_int 3)]))
20936 "punpcklwd\t{%2, %0|%0, %2}"
20937 [(set_attr "type" "ssecvt")
20938 (set_attr "mode" "TI")])
20940 (define_insn "sse2_punpckldq"
20941 [(set (match_operand:V4SI 0 "register_operand" "=x")
20943 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
20944 (parallel [(const_int 0) (const_int 2)
20945 (const_int 1) (const_int 3)]))
20946 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
20947 (parallel [(const_int 2) (const_int 0)
20948 (const_int 3) (const_int 1)]))
20951 "punpckldq\t{%2, %0|%0, %2}"
20952 [(set_attr "type" "ssecvt")
20953 (set_attr "mode" "TI")])
20957 (define_insn "sse2_movapd"
20958 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
20959 (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
20963 movapd\t{%1, %0|%0, %1}
20964 movapd\t{%1, %0|%0, %1}"
20965 [(set_attr "type" "ssemov")
20966 (set_attr "mode" "V2DF")])
20968 (define_insn "sse2_movupd"
20969 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
20970 (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
20974 movupd\t{%1, %0|%0, %1}
20975 movupd\t{%1, %0|%0, %1}"
20976 [(set_attr "type" "ssecvt")
20977 (set_attr "mode" "V2DF")])
20979 (define_insn "sse2_movdqa"
20980 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
20981 (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
20985 movdqa\t{%1, %0|%0, %1}
20986 movdqa\t{%1, %0|%0, %1}"
20987 [(set_attr "type" "ssemov")
20988 (set_attr "mode" "TI")])
20990 (define_insn "sse2_movdqu"
20991 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
20992 (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
20996 movdqu\t{%1, %0|%0, %1}
20997 movdqu\t{%1, %0|%0, %1}"
20998 [(set_attr "type" "ssecvt")
20999 (set_attr "mode" "TI")])
21001 (define_insn "sse2_movdq2q"
21002 [(set (match_operand:DI 0 "nonimmediate_operand" "=y")
21003 (vec_select:DI (match_operand:V2DI 1 "general_operand" "x")
21004 (parallel [(const_int 0)])))]
21006 "movdq2q\t{%1, %0|%0, %1}"
21007 [(set_attr "type" "ssecvt")
21008 (set_attr "mode" "TI")])
21010 (define_insn "sse2_movq2dq"
21011 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x")
21012 (vec_concat:V2DI (match_operand:DI 1 "general_operand" "y")
21013 (const_vector:DI [(const_int 0)])))]
21015 "movq2dq\t{%1, %0|%0, %1}"
21016 [(set_attr "type" "ssecvt")
21017 (set_attr "mode" "TI")])
21019 (define_insn "sse2_movhpd"
21020 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21022 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21023 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21025 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21026 "movhpd\t{%2, %0|%0, %2}"
21027 [(set_attr "type" "ssecvt")
21028 (set_attr "mode" "V2DF")])
21030 (define_insn "sse2_movlpd"
21031 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21033 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21034 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21036 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21037 "movlpd\t{%2, %0|%0, %2}"
21038 [(set_attr "type" "ssecvt")
21039 (set_attr "mode" "V2DF")])
21041 (define_insn "sse2_loadsd"
21042 [(set (match_operand:V2DF 0 "register_operand" "=x")
21044 (match_operand:DF 1 "memory_operand" "m")
21045 (vec_duplicate:DF (float:DF (const_int 0)))
21048 "movsd\t{%1, %0|%0, %1}"
21049 [(set_attr "type" "ssecvt")
21050 (set_attr "mode" "DF")])
21052 (define_insn "sse2_movsd"
21053 [(set (match_operand:V2DF 0 "register_operand" "=x")
21055 (match_operand:V2DF 1 "register_operand" "0")
21056 (match_operand:V2DF 2 "register_operand" "x")
21059 "movsd\t{%2, %0|%0, %2}"
21060 [(set_attr "type" "ssecvt")
21061 (set_attr "mode" "DF")])
21063 (define_insn "sse2_storesd"
21064 [(set (match_operand:DF 0 "memory_operand" "=m")
21066 (match_operand:V2DF 1 "register_operand" "x")
21067 (parallel [(const_int 0)])))]
21069 "movsd\t{%1, %0|%0, %1}"
21070 [(set_attr "type" "ssecvt")
21071 (set_attr "mode" "DF")])
21073 (define_insn "sse2_shufpd"
21074 [(set (match_operand:V2DF 0 "register_operand" "=x")
21075 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
21076 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
21077 (match_operand:SI 3 "immediate_operand" "i")]
21080 ;; @@@ check operand order for intel/nonintel syntax
21081 "shufpd\t{%3, %2, %0|%0, %2, %3}"
21082 [(set_attr "type" "ssecvt")
21083 (set_attr "mode" "V2DF")])
21085 (define_insn "sse2_clflush"
21086 [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")]
21090 [(set_attr "type" "sse")
21091 (set_attr "memory" "unknown")])
21093 (define_expand "sse2_mfence"
21094 [(set (match_dup 0)
21095 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
21098 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21099 MEM_VOLATILE_P (operands[0]) = 1;
21102 (define_insn "*mfence_insn"
21103 [(set (match_operand:BLK 0 "" "")
21104 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
21107 [(set_attr "type" "sse")
21108 (set_attr "memory" "unknown")])
21110 (define_expand "sse2_lfence"
21111 [(set (match_dup 0)
21112 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
21115 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21116 MEM_VOLATILE_P (operands[0]) = 1;
21119 (define_insn "*lfence_insn"
21120 [(set (match_operand:BLK 0 "" "")
21121 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
21124 [(set_attr "type" "sse")
21125 (set_attr "memory" "unknown")])