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* config/i386/netbsd-elf.h (TARGET_OS_CPP_BUILTINS): Define.
[official-gcc.git] / gcc / config / i386 / i386.h
blob970dfdfdf61608f96cbf18e4671ed4a9b4bfa084
1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
38
39 #ifndef HALF_PIC_P
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) (X)
48 #define HALF_PIC_FINISH(STREAM)
49 #endif
50
51 /* Define the specific costs for a given cpu */
52
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
91 operations. */
92 };
93
94 extern const struct processor_costs *ix86_cost;
95
96 /* Run-time compilation parameters selecting different hardware subsets. */
97
98 extern int target_flags;
99
100 /* Macros used in the machine description to test the flags. */
101
102 /* configure can arrange to make this 2, to force a 486. */
103
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
106 #endif
107
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
140
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
145
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 #else
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
197 #else
198 #define TARGET_64BIT 0
199 #endif
200 #endif
201
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
209
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern const int x86_arch_always_fancy_math_387;
226 extern int x86_prefetch_sse;
227
228 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
229 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
230 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
231 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
232 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
233 /* For sane SSE instruction set generation we need fcomi instruction. It is
234 safe to enable all CMOVE instructions. */
235 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
236 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
237 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
238 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
239 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
240 #define TARGET_MOVX (x86_movx & CPUMASK)
241 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
242 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
243 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
244 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
245 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
246 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
247 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
248 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
249 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
250 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
251 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
252 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
253 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
254 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
255 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
256 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
257 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
258 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
259 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
260 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
261 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
262 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
263 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
264 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
265 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
266
267 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
268
269 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
270 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
271
272 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
273
274 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
275 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
276 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
277 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
278 && (ix86_fpmath & FPMATH_387))
279 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
280 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
281 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
282
283 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
284
285 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
286 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
287
288 /* WARNING: Do not mark empty strings for translation, as calling
289 gettext on an empty string does NOT return an empty
290 string. */
291
292
293 #define TARGET_SWITCHES \
294 { { "80387", MASK_80387, N_("Use hardware fp") }, \
295 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
296 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
297 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
298 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
299 { "386", 0, "" /*Deprecated.*/}, \
300 { "486", 0, "" /*Deprecated.*/}, \
301 { "pentium", 0, "" /*Deprecated.*/}, \
302 { "pentiumpro", 0, "" /*Deprecated.*/}, \
303 { "intel-syntax", 0, "" /*Deprecated.*/}, \
304 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
305 { "rtd", MASK_RTD, \
306 N_("Alternate calling convention") }, \
307 { "no-rtd", -MASK_RTD, \
308 N_("Use normal calling convention") }, \
309 { "align-double", MASK_ALIGN_DOUBLE, \
310 N_("Align some doubles on dword boundary") }, \
311 { "no-align-double", -MASK_ALIGN_DOUBLE, \
312 N_("Align doubles on word boundary") }, \
313 { "svr3-shlib", MASK_SVR3_SHLIB, \
314 N_("Uninitialized locals in .bss") }, \
315 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
316 N_("Uninitialized locals in .data") }, \
317 { "ieee-fp", MASK_IEEE_FP, \
318 N_("Use IEEE math for fp comparisons") }, \
319 { "no-ieee-fp", -MASK_IEEE_FP, \
320 N_("Do not use IEEE math for fp comparisons") }, \
321 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
322 N_("Return values of functions in FPU registers") }, \
323 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
324 N_("Do not return values of functions in FPU registers")}, \
325 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
326 N_("Do not generate sin, cos, sqrt for FPU") }, \
327 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
328 N_("Generate sin, cos, sqrt for FPU")}, \
329 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
330 N_("Omit the frame pointer in leaf functions") }, \
331 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
332 { "stack-arg-probe", MASK_STACK_PROBE, \
333 N_("Enable stack probing") }, \
334 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
335 { "windows", 0, 0 /* undocumented */ }, \
336 { "dll", 0, 0 /* undocumented */ }, \
337 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
338 N_("Align destination of the string operations") }, \
339 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
340 N_("Do not align destination of the string operations") }, \
341 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
342 N_("Inline all known string operations") }, \
343 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
344 N_("Do not inline all known string operations") }, \
345 { "push-args", -MASK_NO_PUSH_ARGS, \
346 N_("Use push instructions to save outgoing arguments") }, \
347 { "no-push-args", MASK_NO_PUSH_ARGS, \
348 N_("Do not use push instructions to save outgoing arguments") }, \
349 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
350 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
351 N_("Use push instructions to save outgoing arguments") }, \
352 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
353 N_("Do not use push instructions to save outgoing arguments") }, \
354 { "mmx", MASK_MMX | MASK_MMX_SET, \
355 N_("Support MMX built-in functions") }, \
356 { "no-mmx", -MASK_MMX, \
357 N_("Do not support MMX built-in functions") }, \
358 { "no-mmx", MASK_MMX_SET, "" }, \
359 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
360 N_("Support 3DNow! built-in functions") }, \
361 { "no-3dnow", -MASK_3DNOW, "" }, \
362 { "no-3dnow", MASK_3DNOW_SET, \
363 N_("Do not support 3DNow! built-in functions") }, \
364 { "sse", MASK_SSE | MASK_SSE_SET, \
365 N_("Support MMX and SSE built-in functions and code generation") }, \
366 { "no-sse", -MASK_SSE, "" }, \
367 { "no-sse", MASK_SSE_SET, \
368 N_("Do not support MMX and SSE built-in functions and code generation") },\
369 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
370 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
371 { "no-sse2", -MASK_SSE2, "" }, \
372 { "no-sse2", MASK_SSE2_SET, \
373 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
374 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
375 N_("sizeof(long double) is 16") }, \
376 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
377 N_("sizeof(long double) is 12") }, \
378 { "64", MASK_64BIT, \
379 N_("Generate 64bit x86-64 code") }, \
380 { "32", -MASK_64BIT, \
381 N_("Generate 32bit i386 code") }, \
382 { "red-zone", -MASK_NO_RED_ZONE, \
383 N_("Use red-zone in the x86-64 code") }, \
384 { "no-red-zone", MASK_NO_RED_ZONE, \
385 N_("Do not use red-zone in the x86-64 code") }, \
386 SUBTARGET_SWITCHES \
387 { "", TARGET_DEFAULT, 0 }}
388
389 #ifdef TARGET_64BIT_DEFAULT
390 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
391 #else
392 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
393 #endif
394
395 /* This macro is similar to `TARGET_SWITCHES' but defines names of
396 command options that have values. Its definition is an
397 initializer with a subgrouping for each command option.
398
399 Each subgrouping contains a string constant, that defines the
400 fixed part of the option name, and the address of a variable. The
401 variable, type `char *', is set to the variable part of the given
402 option if the fixed part matches. The actual option name is made
403 by appending `-m' to the specified name. */
404 #define TARGET_OPTIONS \
405 { { "cpu=", &ix86_cpu_string, \
406 N_("Schedule code for given CPU")}, \
407 { "fpmath=", &ix86_fpmath_string, \
408 N_("Generate floating point mathematics using given instruction set")},\
409 { "arch=", &ix86_arch_string, \
410 N_("Generate code for given CPU")}, \
411 { "regparm=", &ix86_regparm_string, \
412 N_("Number of registers used to pass integer arguments") }, \
413 { "align-loops=", &ix86_align_loops_string, \
414 N_("Loop code aligned to this power of 2") }, \
415 { "align-jumps=", &ix86_align_jumps_string, \
416 N_("Jump targets are aligned to this power of 2") }, \
417 { "align-functions=", &ix86_align_funcs_string, \
418 N_("Function starts are aligned to this power of 2") }, \
419 { "preferred-stack-boundary=", \
420 &ix86_preferred_stack_boundary_string, \
421 N_("Attempt to keep stack aligned to this power of 2") }, \
422 { "branch-cost=", &ix86_branch_cost_string, \
423 N_("Branches are this expensive (1-5, arbitrary units)") }, \
424 { "cmodel=", &ix86_cmodel_string, \
425 N_("Use given x86-64 code model") }, \
426 { "debug-arg", &ix86_debug_arg_string, \
427 "" /* Undocumented. */ }, \
428 { "debug-addr", &ix86_debug_addr_string, \
429 "" /* Undocumented. */ }, \
430 { "asm=", &ix86_asm_string, \
431 N_("Use given assembler dialect") }, \
432 { "tls-dialect=", &ix86_tls_dialect_string, \
433 N_("Use given thread-local storage dialect") }, \
434 SUBTARGET_OPTIONS \
435 }
436
437 /* Sometimes certain combinations of command options do not make
438 sense on a particular target machine. You can define a macro
439 `OVERRIDE_OPTIONS' to take account of this. This macro, if
440 defined, is executed once just after all the command options have
441 been parsed.
442
443 Don't use this macro to turn on various extra optimizations for
444 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
445
446 #define OVERRIDE_OPTIONS override_options ()
447
448 /* These are meant to be redefined in the host dependent files */
449 #define SUBTARGET_SWITCHES
450 #define SUBTARGET_OPTIONS
451
452 /* Define this to change the optimizations performed by default. */
453 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
454 optimization_options ((LEVEL), (SIZE))
455
456 /* Specs for the compiler proper */
457
458 #ifndef CC1_CPU_SPEC
459 #define CC1_CPU_SPEC "\
460 %{!mcpu*: \
461 %{m386:-mcpu=i386 \
462 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
463 %{m486:-mcpu=i486 \
464 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
465 %{mpentium:-mcpu=pentium \
466 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
467 %{mpentiumpro:-mcpu=pentiumpro \
468 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
469 %{mintel-syntax:-masm=intel \
470 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
471 %{mno-intel-syntax:-masm=att \
472 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
473 #endif
474 \f
475 #define TARGET_CPU_DEFAULT_i386 0
476 #define TARGET_CPU_DEFAULT_i486 1
477 #define TARGET_CPU_DEFAULT_pentium 2
478 #define TARGET_CPU_DEFAULT_pentium_mmx 3
479 #define TARGET_CPU_DEFAULT_pentiumpro 4
480 #define TARGET_CPU_DEFAULT_pentium2 5
481 #define TARGET_CPU_DEFAULT_pentium3 6
482 #define TARGET_CPU_DEFAULT_pentium4 7
483 #define TARGET_CPU_DEFAULT_k6 8
484 #define TARGET_CPU_DEFAULT_k6_2 9
485 #define TARGET_CPU_DEFAULT_k6_3 10
486 #define TARGET_CPU_DEFAULT_athlon 11
487 #define TARGET_CPU_DEFAULT_athlon_sse 12
488
489 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
490 "pentiumpro", "pentium2", "pentium3", \
491 "pentium4", "k6", "k6-2", "k6-3",\
492 "athlon", "athlon-4"}
493 #ifndef CPP_CPU_DEFAULT_SPEC
494 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
495 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
496 #endif
497 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
498 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
499 #endif
500 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
501 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
502 #endif
503 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
504 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
505 #endif
506 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
507 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
508 -D__tune_pentium2__"
509 #endif
510 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
511 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
512 -D__tune_pentium2__ -D__tune_pentium3__"
513 #endif
514 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
515 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
516 #endif
517 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
518 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
519 #endif
520 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
521 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
522 #endif
523 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
524 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
525 #endif
526 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
527 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
528 #endif
529 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
530 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
531 #endif
532 #ifndef CPP_CPU_DEFAULT_SPEC
533 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
534 #endif
535 #endif /* CPP_CPU_DEFAULT_SPEC */
536
537 #define CPP_CPU32_SPEC \
538 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
539 -D__i386__"
540
541 #define CPP_CPU64_SPEC \
542 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__"
543
544 #define CPP_CPUCOMMON_SPEC "\
545 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
546 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
547 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
548 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
549 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
550 -D__pentium__mmx__ \
551 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
552 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
553 -D__pentiumpro -D__pentiumpro__ \
554 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
555 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
556 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
557 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
558 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
559 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
560 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
561 %{!mcpu*:-D__tune_athlon__ }}\
562 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
563 -D__athlon_sse__ \
564 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
565 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
566 %{m386|mcpu=i386:-D__tune_i386__ }\
567 %{m486|mcpu=i486:-D__tune_i486__ }\
568 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
569 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
570 -D__tune_pentiumpro__ }\
571 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
572 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
573 -D__tune_athlon__ }\
574 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
575 -D__tune_athlon_sse__ }\
576 %{mcpu=pentium4:-D__tune_pentium4__ }\
577 %{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
578 -D__SSE__ }\
579 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
580 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
581 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
582 %{march=k6-2|march=k6-3\
583 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
584 |march=athlon-mp: -D__3dNOW__ }\
585 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
586 |march=athlon-mp: -D__3dNOW_A__ }\
587 %{msse2: -D__SSE2__ }\
588 %{march=pentium4: -D__SSE2__ }\
589 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
590
591 #ifndef CPP_CPU_SPEC
592 #ifdef TARGET_BI_ARCH
593 #ifdef TARGET_64BIT_DEFAULT
594 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
595 #else
596 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
597 #endif
598 #else
599 #ifdef TARGET_64BIT_DEFAULT
600 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
601 #else
602 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
603 #endif
604 #endif
605 #endif
606
607 #ifndef CC1_SPEC
608 #define CC1_SPEC "%(cc1_cpu) "
609 #endif
610
611 /* This macro defines names of additional specifications to put in the
612 specs that can be used in various specifications like CC1_SPEC. Its
613 definition is an initializer with a subgrouping for each command option.
614
615 Each subgrouping contains a string constant, that defines the
616 specification name, and a string constant that used by the GNU CC driver
617 program.
618
619 Do not define this macro if it does not need to do anything. */
620
621 #ifndef SUBTARGET_EXTRA_SPECS
622 #define SUBTARGET_EXTRA_SPECS
623 #endif
624
625 #define EXTRA_SPECS \
626 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
627 { "cpp_cpu", CPP_CPU_SPEC }, \
628 { "cpp_cpu32", CPP_CPU32_SPEC }, \
629 { "cpp_cpu64", CPP_CPU64_SPEC }, \
630 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
631 { "cc1_cpu", CC1_CPU_SPEC }, \
632 SUBTARGET_EXTRA_SPECS
633 \f
634 /* target machine storage layout */
635
636 /* Define for XFmode or TFmode extended real floating point support.
637 The XFmode is specified by i386 ABI, while TFmode may be faster
638 due to alignment and simplifications in the address calculations.
639 */
640 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
641 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
642 #ifdef __x86_64__
643 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
644 #else
645 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
646 #endif
647 /* Tell real.c that this is the 80-bit Intel extended float format
648 packaged in a 128-bit or 96bit entity. */
649 #define INTEL_EXTENDED_IEEE_FORMAT 1
650
651
652 #define SHORT_TYPE_SIZE 16
653 #define INT_TYPE_SIZE 32
654 #define FLOAT_TYPE_SIZE 32
655 #define LONG_TYPE_SIZE BITS_PER_WORD
656 #define MAX_WCHAR_TYPE_SIZE 32
657 #define DOUBLE_TYPE_SIZE 64
658 #define LONG_LONG_TYPE_SIZE 64
659
660 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
661 #define MAX_BITS_PER_WORD 64
662 #define MAX_LONG_TYPE_SIZE 64
663 #else
664 #define MAX_BITS_PER_WORD 32
665 #define MAX_LONG_TYPE_SIZE 32
666 #endif
667
668 /* Define this if most significant byte of a word is the lowest numbered. */
669 /* That is true on the 80386. */
670
671 #define BITS_BIG_ENDIAN 0
672
673 /* Define this if most significant byte of a word is the lowest numbered. */
674 /* That is not true on the 80386. */
675 #define BYTES_BIG_ENDIAN 0
676
677 /* Define this if most significant word of a multiword number is the lowest
678 numbered. */
679 /* Not true for 80386 */
680 #define WORDS_BIG_ENDIAN 0
681
682 /* Width of a word, in units (bytes). */
683 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
684 #define MIN_UNITS_PER_WORD 4
685
686 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
687 #define PARM_BOUNDARY BITS_PER_WORD
688
689 /* Boundary (in *bits*) on which stack pointer should be aligned. */
690 #define STACK_BOUNDARY BITS_PER_WORD
691
692 /* Boundary (in *bits*) on which the stack pointer preferrs to be
693 aligned; the compiler cannot rely on having this alignment. */
694 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
695
696 /* As of July 2001, many runtimes to not align the stack properly when
697 entering main. This causes expand_main_function to forcably align
698 the stack, which results in aligned frames for functions called from
699 main, though it does nothing for the alignment of main itself. */
700 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
701 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
702
703 /* Allocation boundary for the code of a function. */
704 #define FUNCTION_BOUNDARY 16
705
706 /* Alignment of field after `int : 0' in a structure. */
707
708 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
709
710 /* Minimum size in bits of the largest boundary to which any
711 and all fundamental data types supported by the hardware
712 might need to be aligned. No data type wants to be aligned
713 rounder than this.
714
715 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
716 and Pentium Pro XFmode values at 128 bit boundaries. */
717
718 #define BIGGEST_ALIGNMENT 128
719
720 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
721 #define ALIGN_MODE_128(MODE) \
722 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
723 || (MODE) == V4SFmode || (MODE) == V4SImode)
724
725 /* The published ABIs say that doubles should be aligned on word
726 boundaries, so lower the aligment for structure fields unless
727 -malign-double is set. */
728 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
729 constant. Use the smaller value in that context. */
730 #ifndef IN_TARGET_LIBS
731 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
732 #else
733 #define BIGGEST_FIELD_ALIGNMENT 32
734 #endif
735
736 /* If defined, a C expression to compute the alignment given to a
737 constant that is being placed in memory. EXP is the constant
738 and ALIGN is the alignment that the object would ordinarily have.
739 The value of this macro is used instead of that alignment to align
740 the object.
741
742 If this macro is not defined, then ALIGN is used.
743
744 The typical use of this macro is to increase alignment for string
745 constants to be word aligned so that `strcpy' calls that copy
746 constants can be done inline. */
747
748 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
749
750 /* If defined, a C expression to compute the alignment for a static
751 variable. TYPE is the data type, and ALIGN is the alignment that
752 the object would ordinarily have. The value of this macro is used
753 instead of that alignment to align the object.
754
755 If this macro is not defined, then ALIGN is used.
756
757 One use of this macro is to increase alignment of medium-size
758 data to make it all fit in fewer cache lines. Another is to
759 cause character arrays to be word-aligned so that `strcpy' calls
760 that copy constants to character arrays can be done inline. */
761
762 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
763
764 /* If defined, a C expression to compute the alignment for a local
765 variable. TYPE is the data type, and ALIGN is the alignment that
766 the object would ordinarily have. The value of this macro is used
767 instead of that alignment to align the object.
768
769 If this macro is not defined, then ALIGN is used.
770
771 One use of this macro is to increase alignment of medium-size
772 data to make it all fit in fewer cache lines. */
773
774 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
775
776 /* If defined, a C expression that gives the alignment boundary, in
777 bits, of an argument with the specified mode and type. If it is
778 not defined, `PARM_BOUNDARY' is used for all arguments. */
779
780 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
781 ix86_function_arg_boundary ((MODE), (TYPE))
782
783 /* Set this non-zero if move instructions will actually fail to work
784 when given unaligned data. */
785 #define STRICT_ALIGNMENT 0
786
787 /* If bit field type is int, don't let it cross an int,
788 and give entire struct the alignment of an int. */
789 /* Required on the 386 since it doesn't have bitfield insns. */
790 #define PCC_BITFIELD_TYPE_MATTERS 1
791 \f
792 /* Standard register usage. */
793
794 /* This processor has special stack-like registers. See reg-stack.c
795 for details. */
796
797 #define STACK_REGS
798 #define IS_STACK_MODE(MODE) \
799 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
800 || (MODE) == TFmode)
801
802 /* Number of actual hardware registers.
803 The hardware registers are assigned numbers for the compiler
804 from 0 to just below FIRST_PSEUDO_REGISTER.
805 All registers that the compiler knows about must be given numbers,
806 even those that are not normally considered general registers.
807
808 In the 80386 we give the 8 general purpose registers the numbers 0-7.
809 We number the floating point registers 8-15.
810 Note that registers 0-7 can be accessed as a short or int,
811 while only 0-3 may be used with byte `mov' instructions.
812
813 Reg 16 does not correspond to any hardware register, but instead
814 appears in the RTL as an argument pointer prior to reload, and is
815 eliminated during reloading in favor of either the stack or frame
816 pointer. */
817
818 #define FIRST_PSEUDO_REGISTER 53
819
820 /* Number of hardware registers that go into the DWARF-2 unwind info.
821 If not defined, equals FIRST_PSEUDO_REGISTER. */
822
823 #define DWARF_FRAME_REGISTERS 17
824
825 /* 1 for registers that have pervasive standard uses
826 and are not available for the register allocator.
827 On the 80386, the stack pointer is such, as is the arg pointer.
828
829 The value is an mask - bit 1 is set for fixed registers
830 for 32bit target, while 2 is set for fixed registers for 64bit.
831 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
832 */
833 #define FIXED_REGISTERS \
834 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
835 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
836 /*arg,flags,fpsr,dir,frame*/ \
837 3, 3, 3, 3, 3, \
838 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
839 0, 0, 0, 0, 0, 0, 0, 0, \
840 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
841 0, 0, 0, 0, 0, 0, 0, 0, \
842 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
843 1, 1, 1, 1, 1, 1, 1, 1, \
844 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
845 1, 1, 1, 1, 1, 1, 1, 1}
846
847
848 /* 1 for registers not available across function calls.
849 These must include the FIXED_REGISTERS and also any
850 registers that can be used without being saved.
851 The latter must include the registers where values are returned
852 and the register where structure-value addresses are passed.
853 Aside from that, you can include as many other registers as you like.
854
855 The value is an mask - bit 1 is set for call used
856 for 32bit target, while 2 is set for call used for 64bit.
857 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
858 */
859 #define CALL_USED_REGISTERS \
860 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
861 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
862 /*arg,flags,fpsr,dir,frame*/ \
863 3, 3, 3, 3, 3, \
864 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
865 3, 3, 3, 3, 3, 3, 3, 3, \
866 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
867 3, 3, 3, 3, 3, 3, 3, 3, \
868 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
869 3, 3, 3, 3, 1, 1, 1, 1, \
870 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
871 3, 3, 3, 3, 3, 3, 3, 3} \
872
873 /* Order in which to allocate registers. Each register must be
874 listed once, even those in FIXED_REGISTERS. List frame pointer
875 late and fixed registers last. Note that, in general, we prefer
876 registers listed in CALL_USED_REGISTERS, keeping the others
877 available for storage of persistent values.
878
879 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
880 so this is just empty initializer for array. */
881
882 #define REG_ALLOC_ORDER \
883 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
884 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
885 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
886 48, 49, 50, 51, 52 }
887
888 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
889 to be rearranged based on a particular function. When using sse math,
890 we want to allocase SSE before x87 registers and vice vera. */
891
892 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
893
894
895 /* Macro to conditionally modify fixed_regs/call_used_regs. */
896 #define CONDITIONAL_REGISTER_USAGE \
897 do { \
898 int i; \
899 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
900 { \
901 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
902 call_used_regs[i] = (call_used_regs[i] \
903 & (TARGET_64BIT ? 2 : 1)) != 0; \
904 } \
905 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
906 { \
907 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
908 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
909 } \
910 if (! TARGET_MMX) \
911 { \
912 int i; \
913 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
914 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
915 fixed_regs[i] = call_used_regs[i] = 1; \
916 } \
917 if (! TARGET_SSE) \
918 { \
919 int i; \
920 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
921 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
922 fixed_regs[i] = call_used_regs[i] = 1; \
923 } \
924 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
925 { \
926 int i; \
927 HARD_REG_SET x; \
928 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
929 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
930 if (TEST_HARD_REG_BIT (x, i)) \
931 fixed_regs[i] = call_used_regs[i] = 1; \
932 } \
933 } while (0)
934
935 /* Return number of consecutive hard regs needed starting at reg REGNO
936 to hold something of mode MODE.
937 This is ordinarily the length in words of a value of mode MODE
938 but can be less for certain modes in special long registers.
939
940 Actually there are no two word move instructions for consecutive
941 registers. And only registers 0-3 may have mov byte instructions
942 applied to them.
943 */
944
945 #define HARD_REGNO_NREGS(REGNO, MODE) \
946 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
947 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
948 : ((MODE) == TFmode \
949 ? (TARGET_64BIT ? 2 : 3) \
950 : (MODE) == TCmode \
951 ? (TARGET_64BIT ? 4 : 6) \
952 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
953
954 #define VALID_SSE2_REG_MODE(MODE) \
955 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
956 || (MODE) == V2DImode)
957
958 #define VALID_SSE_REG_MODE(MODE) \
959 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
960 || (MODE) == SFmode \
961 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
962 || VALID_SSE2_REG_MODE (MODE) \
963 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
964
965 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
966 ((MODE) == V2SFmode || (MODE) == SFmode)
967
968 #define VALID_MMX_REG_MODE(MODE) \
969 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
970 || (MODE) == V2SImode || (MODE) == SImode)
971
972 #define VECTOR_MODE_SUPPORTED_P(MODE) \
973 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
974 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
975 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
976
977 #define VALID_FP_MODE_P(MODE) \
978 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
979 || (!TARGET_64BIT && (MODE) == XFmode) \
980 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
981 || (!TARGET_64BIT && (MODE) == XCmode))
982
983 #define VALID_INT_MODE_P(MODE) \
984 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
985 || (MODE) == DImode \
986 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
987 || (MODE) == CDImode \
988 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
989
990 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
991
992 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
993 ix86_hard_regno_mode_ok ((REGNO), (MODE))
994
995 /* Value is 1 if it is a good idea to tie two pseudo registers
996 when one has mode MODE1 and one has mode MODE2.
997 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
998 for any hard reg, then this must be 0 for correct output. */
999
1000 #define MODES_TIEABLE_P(MODE1, MODE2) \
1001 ((MODE1) == (MODE2) \
1002 || (((MODE1) == HImode || (MODE1) == SImode \
1003 || ((MODE1) == QImode \
1004 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1005 || ((MODE1) == DImode && TARGET_64BIT)) \
1006 && ((MODE2) == HImode || (MODE2) == SImode \
1007 || ((MODE1) == QImode \
1008 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1009 || ((MODE2) == DImode && TARGET_64BIT))))
1010
1011
1012 /* Specify the modes required to caller save a given hard regno.
1013 We do this on i386 to prevent flags from being saved at all.
1014
1015 Kill any attempts to combine saving of modes. */
1016
1017 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1018 (CC_REGNO_P (REGNO) ? VOIDmode \
1019 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1020 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1021 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1022 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1023 : (MODE))
1024 /* Specify the registers used for certain standard purposes.
1025 The values of these macros are register numbers. */
1026
1027 /* on the 386 the pc register is %eip, and is not usable as a general
1028 register. The ordinary mov instructions won't work */
1029 /* #define PC_REGNUM */
1030
1031 /* Register to use for pushing function arguments. */
1032 #define STACK_POINTER_REGNUM 7
1033
1034 /* Base register for access to local variables of the function. */
1035 #define HARD_FRAME_POINTER_REGNUM 6
1036
1037 /* Base register for access to local variables of the function. */
1038 #define FRAME_POINTER_REGNUM 20
1039
1040 /* First floating point reg */
1041 #define FIRST_FLOAT_REG 8
1042
1043 /* First & last stack-like regs */
1044 #define FIRST_STACK_REG FIRST_FLOAT_REG
1045 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1046
1047 #define FLAGS_REG 17
1048 #define FPSR_REG 18
1049 #define DIRFLAG_REG 19
1050
1051 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1052 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1053
1054 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1055 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1056
1057 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1058 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1059
1060 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1061 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1062
1063 /* Value should be nonzero if functions must have frame pointers.
1064 Zero means the frame pointer need not be set up (and parms
1065 may be accessed via the stack pointer) in functions that seem suitable.
1066 This is computed in `reload', in reload1.c. */
1067 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1068
1069 /* Override this in other tm.h files to cope with various OS losage
1070 requiring a frame pointer. */
1071 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1072 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1073 #endif
1074
1075 /* Make sure we can access arbitrary call frames. */
1076 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1077
1078 /* Base register for access to arguments of the function. */
1079 #define ARG_POINTER_REGNUM 16
1080
1081 /* Register in which static-chain is passed to a function.
1082 We do use ECX as static chain register for 32 bit ABI. On the
1083 64bit ABI, ECX is an argument register, so we use R10 instead. */
1084 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1085
1086 /* Register to hold the addressing base for position independent
1087 code access to data items. We don't use PIC pointer for 64bit
1088 mode. Define the regnum to dummy value to prevent gcc from
1089 pessimizing code dealing with EBX. */
1090 #define PIC_OFFSET_TABLE_REGNUM \
1091 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3)
1092
1093 /* Register in which address to store a structure value
1094 arrives in the function. On the 386, the prologue
1095 copies this from the stack to register %eax. */
1096 #define STRUCT_VALUE_INCOMING 0
1097
1098 /* Place in which caller passes the structure value address.
1099 0 means push the value on the stack like an argument. */
1100 #define STRUCT_VALUE 0
1101
1102 /* A C expression which can inhibit the returning of certain function
1103 values in registers, based on the type of value. A nonzero value
1104 says to return the function value in memory, just as large
1105 structures are always returned. Here TYPE will be a C expression
1106 of type `tree', representing the data type of the value.
1107
1108 Note that values of mode `BLKmode' must be explicitly handled by
1109 this macro. Also, the option `-fpcc-struct-return' takes effect
1110 regardless of this macro. On most systems, it is possible to
1111 leave the macro undefined; this causes a default definition to be
1112 used, whose value is the constant 1 for `BLKmode' values, and 0
1113 otherwise.
1114
1115 Do not use this macro to indicate that structures and unions
1116 should always be returned in memory. You should instead use
1117 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1118
1119 #define RETURN_IN_MEMORY(TYPE) \
1120 ix86_return_in_memory (TYPE)
1121
1122 \f
1123 /* Define the classes of registers for register constraints in the
1124 machine description. Also define ranges of constants.
1125
1126 One of the classes must always be named ALL_REGS and include all hard regs.
1127 If there is more than one class, another class must be named NO_REGS
1128 and contain no registers.
1129
1130 The name GENERAL_REGS must be the name of a class (or an alias for
1131 another name such as ALL_REGS). This is the class of registers
1132 that is allowed by "g" or "r" in a register constraint.
1133 Also, registers outside this class are allocated only when
1134 instructions express preferences for them.
1135
1136 The classes must be numbered in nondecreasing order; that is,
1137 a larger-numbered class must never be contained completely
1138 in a smaller-numbered class.
1139
1140 For any two classes, it is very desirable that there be another
1141 class that represents their union.
1142
1143 It might seem that class BREG is unnecessary, since no useful 386
1144 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1145 and the "b" register constraint is useful in asms for syscalls.
1146
1147 The flags and fpsr registers are in no class. */
1148
1149 enum reg_class
1150 {
1151 NO_REGS,
1152 AREG, DREG, CREG, BREG, SIREG, DIREG,
1153 AD_REGS, /* %eax/%edx for DImode */
1154 Q_REGS, /* %eax %ebx %ecx %edx */
1155 NON_Q_REGS, /* %esi %edi %ebp %esp */
1156 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1157 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1158 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1159 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1160 FLOAT_REGS,
1161 SSE_REGS,
1162 MMX_REGS,
1163 FP_TOP_SSE_REGS,
1164 FP_SECOND_SSE_REGS,
1165 FLOAT_SSE_REGS,
1166 FLOAT_INT_REGS,
1167 INT_SSE_REGS,
1168 FLOAT_INT_SSE_REGS,
1169 ALL_REGS, LIM_REG_CLASSES
1170 };
1171
1172 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1173
1174 #define INTEGER_CLASS_P(CLASS) \
1175 reg_class_subset_p ((CLASS), GENERAL_REGS)
1176 #define FLOAT_CLASS_P(CLASS) \
1177 reg_class_subset_p ((CLASS), FLOAT_REGS)
1178 #define SSE_CLASS_P(CLASS) \
1179 reg_class_subset_p ((CLASS), SSE_REGS)
1180 #define MMX_CLASS_P(CLASS) \
1181 reg_class_subset_p ((CLASS), MMX_REGS)
1182 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1183 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1184 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1185 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1186 #define MAYBE_SSE_CLASS_P(CLASS) \
1187 reg_classes_intersect_p (SSE_REGS, (CLASS))
1188 #define MAYBE_MMX_CLASS_P(CLASS) \
1189 reg_classes_intersect_p (MMX_REGS, (CLASS))
1190
1191 #define Q_CLASS_P(CLASS) \
1192 reg_class_subset_p ((CLASS), Q_REGS)
1193
1194 /* Give names of register classes as strings for dump file. */
1195
1196 #define REG_CLASS_NAMES \
1197 { "NO_REGS", \
1198 "AREG", "DREG", "CREG", "BREG", \
1199 "SIREG", "DIREG", \
1200 "AD_REGS", \
1201 "Q_REGS", "NON_Q_REGS", \
1202 "INDEX_REGS", \
1203 "LEGACY_REGS", \
1204 "GENERAL_REGS", \
1205 "FP_TOP_REG", "FP_SECOND_REG", \
1206 "FLOAT_REGS", \
1207 "SSE_REGS", \
1208 "MMX_REGS", \
1209 "FP_TOP_SSE_REGS", \
1210 "FP_SECOND_SSE_REGS", \
1211 "FLOAT_SSE_REGS", \
1212 "FLOAT_INT_REGS", \
1213 "INT_SSE_REGS", \
1214 "FLOAT_INT_SSE_REGS", \
1215 "ALL_REGS" }
1216
1217 /* Define which registers fit in which classes.
1218 This is an initializer for a vector of HARD_REG_SET
1219 of length N_REG_CLASSES. */
1220
1221 #define REG_CLASS_CONTENTS \
1222 { { 0x00, 0x0 }, \
1223 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1224 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1225 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1226 { 0x03, 0x0 }, /* AD_REGS */ \
1227 { 0x0f, 0x0 }, /* Q_REGS */ \
1228 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1229 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1230 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1231 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1232 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1233 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1234 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1235 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1236 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1237 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1238 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1239 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1240 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1241 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1242 { 0xffffffff,0x1fffff } \
1243 }
1244
1245 /* The same information, inverted:
1246 Return the class number of the smallest class containing
1247 reg number REGNO. This could be a conditional expression
1248 or could index an array. */
1249
1250 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1251
1252 /* When defined, the compiler allows registers explicitly used in the
1253 rtl to be used as spill registers but prevents the compiler from
1254 extending the lifetime of these registers. */
1255
1256 #define SMALL_REGISTER_CLASSES 1
1257
1258 #define QI_REG_P(X) \
1259 (REG_P (X) && REGNO (X) < 4)
1260
1261 #define GENERAL_REGNO_P(N) \
1262 ((N) < 8 || REX_INT_REGNO_P (N))
1263
1264 #define GENERAL_REG_P(X) \
1265 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1266
1267 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1268
1269 #define NON_QI_REG_P(X) \
1270 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1271
1272 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1273 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1274
1275 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1276 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1277 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1278 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1279
1280 #define SSE_REGNO_P(N) \
1281 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1282 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1283
1284 #define SSE_REGNO(N) \
1285 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1286 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1287
1288 #define SSE_FLOAT_MODE_P(MODE) \
1289 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1290
1291 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1292 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1293
1294 #define STACK_REG_P(XOP) \
1295 (REG_P (XOP) && \
1296 REGNO (XOP) >= FIRST_STACK_REG && \
1297 REGNO (XOP) <= LAST_STACK_REG)
1298
1299 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1300
1301 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1302
1303 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1304 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1305
1306 /* Indicate whether hard register numbered REG_NO should be converted
1307 to SSA form. */
1308 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1309 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1310
1311 /* The class value for index registers, and the one for base regs. */
1312
1313 #define INDEX_REG_CLASS INDEX_REGS
1314 #define BASE_REG_CLASS GENERAL_REGS
1315
1316 /* Get reg_class from a letter such as appears in the machine description. */
1317
1318 #define REG_CLASS_FROM_LETTER(C) \
1319 ((C) == 'r' ? GENERAL_REGS : \
1320 (C) == 'R' ? LEGACY_REGS : \
1321 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1322 (C) == 'Q' ? Q_REGS : \
1323 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1324 ? FLOAT_REGS \
1325 : NO_REGS) : \
1326 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1327 ? FP_TOP_REG \
1328 : NO_REGS) : \
1329 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1330 ? FP_SECOND_REG \
1331 : NO_REGS) : \
1332 (C) == 'a' ? AREG : \
1333 (C) == 'b' ? BREG : \
1334 (C) == 'c' ? CREG : \
1335 (C) == 'd' ? DREG : \
1336 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1337 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1338 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1339 (C) == 'A' ? AD_REGS : \
1340 (C) == 'D' ? DIREG : \
1341 (C) == 'S' ? SIREG : NO_REGS)
1342
1343 /* The letters I, J, K, L and M in a register constraint string
1344 can be used to stand for particular ranges of immediate operands.
1345 This macro defines what the ranges are.
1346 C is the letter, and VALUE is a constant value.
1347 Return 1 if VALUE is in the range specified by C.
1348
1349 I is for non-DImode shifts.
1350 J is for DImode shifts.
1351 K is for signed imm8 operands.
1352 L is for andsi as zero-extending move.
1353 M is for shifts that can be executed by the "lea" opcode.
1354 N is for immedaite operands for out/in instructions (0-255)
1355 */
1356
1357 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1358 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1359 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1360 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1361 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1362 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1363 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1364 : 0)
1365
1366 /* Similar, but for floating constants, and defining letters G and H.
1367 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1368 TARGET_387 isn't set, because the stack register converter may need to
1369 load 0.0 into the function value register. */
1370
1371 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1372 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1373 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1374
1375 /* A C expression that defines the optional machine-dependent
1376 constraint letters that can be used to segregate specific types of
1377 operands, usually memory references, for the target machine. Any
1378 letter that is not elsewhere defined and not matched by
1379 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1380 be defined.
1381
1382 If it is required for a particular target machine, it should
1383 return 1 if VALUE corresponds to the operand type represented by
1384 the constraint letter C. If C is not defined as an extra
1385 constraint, the value returned should be 0 regardless of VALUE. */
1386
1387 #define EXTRA_CONSTRAINT(VALUE, C) \
1388 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1389 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1390 : 0)
1391
1392 /* Place additional restrictions on the register class to use when it
1393 is necessary to be able to hold a value of mode MODE in a reload
1394 register for which class CLASS would ordinarily be used. */
1395
1396 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1397 ((MODE) == QImode && !TARGET_64BIT \
1398 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1399 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1400 ? Q_REGS : (CLASS))
1401
1402 /* Given an rtx X being reloaded into a reg required to be
1403 in class CLASS, return the class of reg to actually use.
1404 In general this is just CLASS; but on some machines
1405 in some cases it is preferable to use a more restrictive class.
1406 On the 80386 series, we prevent floating constants from being
1407 reloaded into floating registers (since no move-insn can do that)
1408 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1409
1410 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1411 QImode must go into class Q_REGS.
1412 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1413 movdf to do mem-to-mem moves through integer regs. */
1414
1415 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1416 ix86_preferred_reload_class ((X), (CLASS))
1417
1418 /* If we are copying between general and FP registers, we need a memory
1419 location. The same is true for SSE and MMX registers. */
1420 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1421 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1422
1423 /* QImode spills from non-QI registers need a scratch. This does not
1424 happen often -- the only example so far requires an uninitialized
1425 pseudo. */
1426
1427 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1428 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1429 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1430 ? Q_REGS : NO_REGS)
1431
1432 /* Return the maximum number of consecutive registers
1433 needed to represent mode MODE in a register of class CLASS. */
1434 /* On the 80386, this is the size of MODE in words,
1435 except in the FP regs, where a single reg is always enough.
1436 The TFmodes are really just 80bit values, so we use only 3 registers
1437 to hold them, instead of 4, as the size would suggest.
1438 */
1439 #define CLASS_MAX_NREGS(CLASS, MODE) \
1440 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1441 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1442 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1443 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1444
1445 /* A C expression whose value is nonzero if pseudos that have been
1446 assigned to registers of class CLASS would likely be spilled
1447 because registers of CLASS are needed for spill registers.
1448
1449 The default value of this macro returns 1 if CLASS has exactly one
1450 register and zero otherwise. On most machines, this default
1451 should be used. Only define this macro to some other expression
1452 if pseudo allocated by `local-alloc.c' end up in memory because
1453 their hard registers were needed for spill registers. If this
1454 macro returns nonzero for those classes, those pseudos will only
1455 be allocated by `global.c', which knows how to reallocate the
1456 pseudo to another register. If there would not be another
1457 register available for reallocation, you should not change the
1458 definition of this macro since the only effect of such a
1459 definition would be to slow down register allocation. */
1460
1461 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1462 (((CLASS) == AREG) \
1463 || ((CLASS) == DREG) \
1464 || ((CLASS) == CREG) \
1465 || ((CLASS) == BREG) \
1466 || ((CLASS) == AD_REGS) \
1467 || ((CLASS) == SIREG) \
1468 || ((CLASS) == DIREG))
1469
1470 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1471 to automatically clobber for all asms.
1472
1473 We do this in the new i386 backend to maintain source compatibility
1474 with the old cc0-based compiler. */
1475
1476 #define MD_ASM_CLOBBERS(CLOBBERS) \
1477 do { \
1478 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1479 (CLOBBERS)); \
1480 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1481 (CLOBBERS)); \
1482 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1483 (CLOBBERS)); \
1484 } while (0)
1485 \f
1486 /* Stack layout; function entry, exit and calling. */
1487
1488 /* Define this if pushing a word on the stack
1489 makes the stack pointer a smaller address. */
1490 #define STACK_GROWS_DOWNWARD
1491
1492 /* Define this if the nominal address of the stack frame
1493 is at the high-address end of the local variables;
1494 that is, each additional local variable allocated
1495 goes at a more negative offset in the frame. */
1496 #define FRAME_GROWS_DOWNWARD
1497
1498 /* Offset within stack frame to start allocating local variables at.
1499 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1500 first local allocated. Otherwise, it is the offset to the BEGINNING
1501 of the first local allocated. */
1502 #define STARTING_FRAME_OFFSET 0
1503
1504 /* If we generate an insn to push BYTES bytes,
1505 this says how many the stack pointer really advances by.
1506 On 386 pushw decrements by exactly 2 no matter what the position was.
1507 On the 386 there is no pushb; we use pushw instead, and this
1508 has the effect of rounding up to 2.
1509
1510 For 64bit ABI we round up to 8 bytes.
1511 */
1512
1513 #define PUSH_ROUNDING(BYTES) \
1514 (TARGET_64BIT \
1515 ? (((BYTES) + 7) & (-8)) \
1516 : (((BYTES) + 1) & (-2)))
1517
1518 /* If defined, the maximum amount of space required for outgoing arguments will
1519 be computed and placed into the variable
1520 `current_function_outgoing_args_size'. No space will be pushed onto the
1521 stack for each call; instead, the function prologue should increase the stack
1522 frame size by this amount. */
1523
1524 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1525
1526 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1527 instructions to pass outgoing arguments. */
1528
1529 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1530
1531 /* Offset of first parameter from the argument pointer register value. */
1532 #define FIRST_PARM_OFFSET(FNDECL) 0
1533
1534 /* Define this macro if functions should assume that stack space has been
1535 allocated for arguments even when their values are passed in registers.
1536
1537 The value of this macro is the size, in bytes, of the area reserved for
1538 arguments passed in registers for the function represented by FNDECL.
1539
1540 This space can be allocated by the caller, or be a part of the
1541 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1542 which. */
1543 #define REG_PARM_STACK_SPACE(FNDECL) 0
1544
1545 /* Define as a C expression that evaluates to nonzero if we do not know how
1546 to pass TYPE solely in registers. The file expr.h defines a
1547 definition that is usually appropriate, refer to expr.h for additional
1548 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1549 computed in the stack and then loaded into a register. */
1550 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1551 ((TYPE) != 0 \
1552 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1553 || TREE_ADDRESSABLE (TYPE) \
1554 || ((MODE) == TImode) \
1555 || ((MODE) == BLKmode \
1556 && ! ((TYPE) != 0 \
1557 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1558 && 0 == (int_size_in_bytes (TYPE) \
1559 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1560 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1561 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1562
1563 /* Value is the number of bytes of arguments automatically
1564 popped when returning from a subroutine call.
1565 FUNDECL is the declaration node of the function (as a tree),
1566 FUNTYPE is the data type of the function (as a tree),
1567 or for a library call it is an identifier node for the subroutine name.
1568 SIZE is the number of bytes of arguments passed on the stack.
1569
1570 On the 80386, the RTD insn may be used to pop them if the number
1571 of args is fixed, but if the number is variable then the caller
1572 must pop them all. RTD can't be used for library calls now
1573 because the library is compiled with the Unix compiler.
1574 Use of RTD is a selectable option, since it is incompatible with
1575 standard Unix calling sequences. If the option is not selected,
1576 the caller must always pop the args.
1577
1578 The attribute stdcall is equivalent to RTD on a per module basis. */
1579
1580 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1581 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1582
1583 /* Define how to find the value returned by a function.
1584 VALTYPE is the data type of the value (as a tree).
1585 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1586 otherwise, FUNC is 0. */
1587 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1588 ix86_function_value (VALTYPE)
1589
1590 #define FUNCTION_VALUE_REGNO_P(N) \
1591 ix86_function_value_regno_p (N)
1592
1593 /* Define how to find the value returned by a library function
1594 assuming the value has mode MODE. */
1595
1596 #define LIBCALL_VALUE(MODE) \
1597 ix86_libcall_value (MODE)
1598
1599 /* Define the size of the result block used for communication between
1600 untyped_call and untyped_return. The block contains a DImode value
1601 followed by the block used by fnsave and frstor. */
1602
1603 #define APPLY_RESULT_SIZE (8+108)
1604
1605 /* 1 if N is a possible register number for function argument passing. */
1606 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1607
1608 /* Define a data type for recording info about an argument list
1609 during the scan of that argument list. This data type should
1610 hold all necessary information about the function itself
1611 and about the args processed so far, enough to enable macros
1612 such as FUNCTION_ARG to determine where the next arg should go. */
1613
1614 typedef struct ix86_args {
1615 int words; /* # words passed so far */
1616 int nregs; /* # registers available for passing */
1617 int regno; /* next available register number */
1618 int sse_words; /* # sse words passed so far */
1619 int sse_nregs; /* # sse registers available for passing */
1620 int sse_regno; /* next available sse register number */
1621 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1622 } CUMULATIVE_ARGS;
1623
1624 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1625 for a call to a function whose data type is FNTYPE.
1626 For a library call, FNTYPE is 0. */
1627
1628 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1629 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1630
1631 /* Update the data in CUM to advance over an argument
1632 of mode MODE and data type TYPE.
1633 (TYPE is null for libcalls where that information may not be available.) */
1634
1635 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1636 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1637
1638 /* Define where to put the arguments to a function.
1639 Value is zero to push the argument on the stack,
1640 or a hard register in which to store the argument.
1641
1642 MODE is the argument's machine mode.
1643 TYPE is the data type of the argument (as a tree).
1644 This is null for libcalls where that information may
1645 not be available.
1646 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1647 the preceding args and about the function being called.
1648 NAMED is nonzero if this argument is a named parameter
1649 (otherwise it is an extra parameter matching an ellipsis). */
1650
1651 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1652 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1653
1654 /* For an arg passed partly in registers and partly in memory,
1655 this is the number of registers used.
1656 For args passed entirely in registers or entirely in memory, zero. */
1657
1658 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1659
1660 /* If PIC, we cannot make sibling calls to global functions
1661 because the PLT requires %ebx live.
1662 If we are returning floats on the register stack, we cannot make
1663 sibling calls to functions that return floats. (The stack adjust
1664 instruction will wind up after the sibcall jump, and not be executed.) */
1665 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1666 ((DECL) \
1667 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1668 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1669 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1670 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1671
1672 /* Perform any needed actions needed for a function that is receiving a
1673 variable number of arguments.
1674
1675 CUM is as above.
1676
1677 MODE and TYPE are the mode and type of the current parameter.
1678
1679 PRETEND_SIZE is a variable that should be set to the amount of stack
1680 that must be pushed by the prolog to pretend that our caller pushed
1681 it.
1682
1683 Normally, this macro will push all remaining incoming registers on the
1684 stack and set PRETEND_SIZE to the length of the registers pushed. */
1685
1686 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1687 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1688 (NO_RTL))
1689
1690 /* Define the `__builtin_va_list' type for the ABI. */
1691 #define BUILD_VA_LIST_TYPE(VALIST) \
1692 ((VALIST) = ix86_build_va_list ())
1693
1694 /* Implement `va_start' for varargs and stdarg. */
1695 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1696 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1697
1698 /* Implement `va_arg'. */
1699 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1700 ix86_va_arg ((VALIST), (TYPE))
1701
1702 /* This macro is invoked at the end of compilation. It is used here to
1703 output code for -fpic that will load the return address into %ebx. */
1704
1705 #undef ASM_FILE_END
1706 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1707
1708 /* Output assembler code to FILE to increment profiler label # LABELNO
1709 for profiling a function entry. */
1710
1711 #define FUNCTION_PROFILER(FILE, LABELNO) \
1712 do { \
1713 if (flag_pic) \
1714 { \
1715 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1716 LPREFIX, (LABELNO)); \
1717 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1718 } \
1719 else \
1720 { \
1721 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1722 fprintf ((FILE), "\tcall\t_mcount\n"); \
1723 } \
1724 } while (0)
1725
1726 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1727 the stack pointer does not matter. The value is tested only in
1728 functions that have frame pointers.
1729 No definition is equivalent to always zero. */
1730 /* Note on the 386 it might be more efficient not to define this since
1731 we have to restore it ourselves from the frame pointer, in order to
1732 use pop */
1733
1734 #define EXIT_IGNORE_STACK 1
1735
1736 /* Output assembler code for a block containing the constant parts
1737 of a trampoline, leaving space for the variable parts. */
1738
1739 /* On the 386, the trampoline contains two instructions:
1740 mov #STATIC,ecx
1741 jmp FUNCTION
1742 The trampoline is generated entirely at runtime. The operand of JMP
1743 is the address of FUNCTION relative to the instruction following the
1744 JMP (which is 5 bytes long). */
1745
1746 /* Length in units of the trampoline for entering a nested function. */
1747
1748 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1749
1750 /* Emit RTL insns to initialize the variable parts of a trampoline.
1751 FNADDR is an RTX for the address of the function's pure code.
1752 CXT is an RTX for the static chain value for the function. */
1753
1754 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1755 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1756 \f
1757 /* Definitions for register eliminations.
1758
1759 This is an array of structures. Each structure initializes one pair
1760 of eliminable registers. The "from" register number is given first,
1761 followed by "to". Eliminations of the same "from" register are listed
1762 in order of preference.
1763
1764 There are two registers that can always be eliminated on the i386.
1765 The frame pointer and the arg pointer can be replaced by either the
1766 hard frame pointer or to the stack pointer, depending upon the
1767 circumstances. The hard frame pointer is not used before reload and
1768 so it is not eligible for elimination. */
1769
1770 #define ELIMINABLE_REGS \
1771 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1772 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1773 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1774 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1775
1776 /* Given FROM and TO register numbers, say whether this elimination is
1777 allowed. Frame pointer elimination is automatically handled.
1778
1779 All other eliminations are valid. */
1780
1781 #define CAN_ELIMINATE(FROM, TO) \
1782 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1783
1784 /* Define the offset between two registers, one to be eliminated, and the other
1785 its replacement, at the start of a routine. */
1786
1787 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1788 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1789 \f
1790 /* Addressing modes, and classification of registers for them. */
1791
1792 /* #define HAVE_POST_INCREMENT 0 */
1793 /* #define HAVE_POST_DECREMENT 0 */
1794
1795 /* #define HAVE_PRE_DECREMENT 0 */
1796 /* #define HAVE_PRE_INCREMENT 0 */
1797
1798 /* Macros to check register numbers against specific register classes. */
1799
1800 /* These assume that REGNO is a hard or pseudo reg number.
1801 They give nonzero only if REGNO is a hard reg of the suitable class
1802 or a pseudo reg currently allocated to a suitable hard reg.
1803 Since they use reg_renumber, they are safe only once reg_renumber
1804 has been allocated, which happens in local-alloc.c. */
1805
1806 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1807 ((REGNO) < STACK_POINTER_REGNUM \
1808 || (REGNO >= FIRST_REX_INT_REG \
1809 && (REGNO) <= LAST_REX_INT_REG) \
1810 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1811 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1812 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1813
1814 #define REGNO_OK_FOR_BASE_P(REGNO) \
1815 ((REGNO) <= STACK_POINTER_REGNUM \
1816 || (REGNO) == ARG_POINTER_REGNUM \
1817 || (REGNO) == FRAME_POINTER_REGNUM \
1818 || (REGNO >= FIRST_REX_INT_REG \
1819 && (REGNO) <= LAST_REX_INT_REG) \
1820 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1821 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1822 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1823
1824 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1825 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1826 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1827 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1828
1829 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1830 and check its validity for a certain class.
1831 We have two alternate definitions for each of them.
1832 The usual definition accepts all pseudo regs; the other rejects
1833 them unless they have been allocated suitable hard regs.
1834 The symbol REG_OK_STRICT causes the latter definition to be used.
1835
1836 Most source files want to accept pseudo regs in the hope that
1837 they will get allocated to the class that the insn wants them to be in.
1838 Source files for reload pass need to be strict.
1839 After reload, it makes no difference, since pseudo regs have
1840 been eliminated by then. */
1841
1842
1843 /* Non strict versions, pseudos are ok */
1844 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1845 (REGNO (X) < STACK_POINTER_REGNUM \
1846 || (REGNO (X) >= FIRST_REX_INT_REG \
1847 && REGNO (X) <= LAST_REX_INT_REG) \
1848 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1849
1850 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1851 (REGNO (X) <= STACK_POINTER_REGNUM \
1852 || REGNO (X) == ARG_POINTER_REGNUM \
1853 || REGNO (X) == FRAME_POINTER_REGNUM \
1854 || (REGNO (X) >= FIRST_REX_INT_REG \
1855 && REGNO (X) <= LAST_REX_INT_REG) \
1856 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1857
1858 /* Strict versions, hard registers only */
1859 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1860 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1861
1862 #ifndef REG_OK_STRICT
1863 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1864 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1865
1866 #else
1867 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1868 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1869 #endif
1870
1871 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1872 that is a valid memory address for an instruction.
1873 The MODE argument is the machine mode for the MEM expression
1874 that wants to use this address.
1875
1876 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1877 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1878
1879 See legitimize_pic_address in i386.c for details as to what
1880 constitutes a legitimate address when -fpic is used. */
1881
1882 #define MAX_REGS_PER_ADDRESS 2
1883
1884 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1885
1886 /* Nonzero if the constant value X is a legitimate general operand.
1887 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1888
1889 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1890
1891 #ifdef REG_OK_STRICT
1892 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1893 do { \
1894 if (legitimate_address_p ((MODE), (X), 1)) \
1895 goto ADDR; \
1896 } while (0)
1897
1898 #else
1899 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1900 do { \
1901 if (legitimate_address_p ((MODE), (X), 0)) \
1902 goto ADDR; \
1903 } while (0)
1904
1905 #endif
1906
1907 /* If defined, a C expression to determine the base term of address X.
1908 This macro is used in only one place: `find_base_term' in alias.c.
1909
1910 It is always safe for this macro to not be defined. It exists so
1911 that alias analysis can understand machine-dependent addresses.
1912
1913 The typical use of this macro is to handle addresses containing
1914 a label_ref or symbol_ref within an UNSPEC. */
1915
1916 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1917
1918 /* Try machine-dependent ways of modifying an illegitimate address
1919 to be legitimate. If we find one, return the new, valid address.
1920 This macro is used in only one place: `memory_address' in explow.c.
1921
1922 OLDX is the address as it was before break_out_memory_refs was called.
1923 In some cases it is useful to look at this to decide what needs to be done.
1924
1925 MODE and WIN are passed so that this macro can use
1926 GO_IF_LEGITIMATE_ADDRESS.
1927
1928 It is always safe for this macro to do nothing. It exists to recognize
1929 opportunities to optimize the output.
1930
1931 For the 80386, we handle X+REG by loading X into a register R and
1932 using R+REG. R will go in a general reg and indexing will be used.
1933 However, if REG is a broken-out memory address or multiplication,
1934 nothing needs to be done because REG can certainly go in a general reg.
1935
1936 When -fpic is used, special handling is needed for symbolic references.
1937 See comments by legitimize_pic_address in i386.c for details. */
1938
1939 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1940 do { \
1941 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1942 if (memory_address_p ((MODE), (X))) \
1943 goto WIN; \
1944 } while (0)
1945
1946 #define REWRITE_ADDRESS(X) rewrite_address (X)
1947
1948 /* Nonzero if the constant value X is a legitimate general operand
1949 when generating PIC code. It is given that flag_pic is on and
1950 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1951
1952 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1953
1954 #define SYMBOLIC_CONST(X) \
1955 (GET_CODE (X) == SYMBOL_REF \
1956 || GET_CODE (X) == LABEL_REF \
1957 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1958
1959 /* Go to LABEL if ADDR (a legitimate address expression)
1960 has an effect that depends on the machine mode it is used for.
1961 On the 80386, only postdecrement and postincrement address depend thus
1962 (the amount of decrement or increment being the length of the operand). */
1963 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1964 do { \
1965 if (GET_CODE (ADDR) == POST_INC \
1966 || GET_CODE (ADDR) == POST_DEC) \
1967 goto LABEL; \
1968 } while (0)
1969 \f
1970 /* Codes for all the SSE/MMX builtins. */
1971 enum ix86_builtins
1972 {
1973 IX86_BUILTIN_ADDPS,
1974 IX86_BUILTIN_ADDSS,
1975 IX86_BUILTIN_DIVPS,
1976 IX86_BUILTIN_DIVSS,
1977 IX86_BUILTIN_MULPS,
1978 IX86_BUILTIN_MULSS,
1979 IX86_BUILTIN_SUBPS,
1980 IX86_BUILTIN_SUBSS,
1981
1982 IX86_BUILTIN_CMPEQPS,
1983 IX86_BUILTIN_CMPLTPS,
1984 IX86_BUILTIN_CMPLEPS,
1985 IX86_BUILTIN_CMPGTPS,
1986 IX86_BUILTIN_CMPGEPS,
1987 IX86_BUILTIN_CMPNEQPS,
1988 IX86_BUILTIN_CMPNLTPS,
1989 IX86_BUILTIN_CMPNLEPS,
1990 IX86_BUILTIN_CMPNGTPS,
1991 IX86_BUILTIN_CMPNGEPS,
1992 IX86_BUILTIN_CMPORDPS,
1993 IX86_BUILTIN_CMPUNORDPS,
1994 IX86_BUILTIN_CMPNEPS,
1995 IX86_BUILTIN_CMPEQSS,
1996 IX86_BUILTIN_CMPLTSS,
1997 IX86_BUILTIN_CMPLESS,
1998 IX86_BUILTIN_CMPGTSS,
1999 IX86_BUILTIN_CMPGESS,
2000 IX86_BUILTIN_CMPNEQSS,
2001 IX86_BUILTIN_CMPNLTSS,
2002 IX86_BUILTIN_CMPNLESS,
2003 IX86_BUILTIN_CMPNGTSS,
2004 IX86_BUILTIN_CMPNGESS,
2005 IX86_BUILTIN_CMPORDSS,
2006 IX86_BUILTIN_CMPUNORDSS,
2007 IX86_BUILTIN_CMPNESS,
2008
2009 IX86_BUILTIN_COMIEQSS,
2010 IX86_BUILTIN_COMILTSS,
2011 IX86_BUILTIN_COMILESS,
2012 IX86_BUILTIN_COMIGTSS,
2013 IX86_BUILTIN_COMIGESS,
2014 IX86_BUILTIN_COMINEQSS,
2015 IX86_BUILTIN_UCOMIEQSS,
2016 IX86_BUILTIN_UCOMILTSS,
2017 IX86_BUILTIN_UCOMILESS,
2018 IX86_BUILTIN_UCOMIGTSS,
2019 IX86_BUILTIN_UCOMIGESS,
2020 IX86_BUILTIN_UCOMINEQSS,
2021
2022 IX86_BUILTIN_CVTPI2PS,
2023 IX86_BUILTIN_CVTPS2PI,
2024 IX86_BUILTIN_CVTSI2SS,
2025 IX86_BUILTIN_CVTSS2SI,
2026 IX86_BUILTIN_CVTTPS2PI,
2027 IX86_BUILTIN_CVTTSS2SI,
2028
2029 IX86_BUILTIN_MAXPS,
2030 IX86_BUILTIN_MAXSS,
2031 IX86_BUILTIN_MINPS,
2032 IX86_BUILTIN_MINSS,
2033
2034 IX86_BUILTIN_LOADAPS,
2035 IX86_BUILTIN_LOADUPS,
2036 IX86_BUILTIN_STOREAPS,
2037 IX86_BUILTIN_STOREUPS,
2038 IX86_BUILTIN_LOADSS,
2039 IX86_BUILTIN_STORESS,
2040 IX86_BUILTIN_MOVSS,
2041
2042 IX86_BUILTIN_MOVHLPS,
2043 IX86_BUILTIN_MOVLHPS,
2044 IX86_BUILTIN_LOADHPS,
2045 IX86_BUILTIN_LOADLPS,
2046 IX86_BUILTIN_STOREHPS,
2047 IX86_BUILTIN_STORELPS,
2048
2049 IX86_BUILTIN_MASKMOVQ,
2050 IX86_BUILTIN_MOVMSKPS,
2051 IX86_BUILTIN_PMOVMSKB,
2052
2053 IX86_BUILTIN_MOVNTPS,
2054 IX86_BUILTIN_MOVNTQ,
2055
2056 IX86_BUILTIN_PACKSSWB,
2057 IX86_BUILTIN_PACKSSDW,
2058 IX86_BUILTIN_PACKUSWB,
2059
2060 IX86_BUILTIN_PADDB,
2061 IX86_BUILTIN_PADDW,
2062 IX86_BUILTIN_PADDD,
2063 IX86_BUILTIN_PADDSB,
2064 IX86_BUILTIN_PADDSW,
2065 IX86_BUILTIN_PADDUSB,
2066 IX86_BUILTIN_PADDUSW,
2067 IX86_BUILTIN_PSUBB,
2068 IX86_BUILTIN_PSUBW,
2069 IX86_BUILTIN_PSUBD,
2070 IX86_BUILTIN_PSUBSB,
2071 IX86_BUILTIN_PSUBSW,
2072 IX86_BUILTIN_PSUBUSB,
2073 IX86_BUILTIN_PSUBUSW,
2074
2075 IX86_BUILTIN_PAND,
2076 IX86_BUILTIN_PANDN,
2077 IX86_BUILTIN_POR,
2078 IX86_BUILTIN_PXOR,
2079
2080 IX86_BUILTIN_PAVGB,
2081 IX86_BUILTIN_PAVGW,
2082
2083 IX86_BUILTIN_PCMPEQB,
2084 IX86_BUILTIN_PCMPEQW,
2085 IX86_BUILTIN_PCMPEQD,
2086 IX86_BUILTIN_PCMPGTB,
2087 IX86_BUILTIN_PCMPGTW,
2088 IX86_BUILTIN_PCMPGTD,
2089
2090 IX86_BUILTIN_PEXTRW,
2091 IX86_BUILTIN_PINSRW,
2092
2093 IX86_BUILTIN_PMADDWD,
2094
2095 IX86_BUILTIN_PMAXSW,
2096 IX86_BUILTIN_PMAXUB,
2097 IX86_BUILTIN_PMINSW,
2098 IX86_BUILTIN_PMINUB,
2099
2100 IX86_BUILTIN_PMULHUW,
2101 IX86_BUILTIN_PMULHW,
2102 IX86_BUILTIN_PMULLW,
2103
2104 IX86_BUILTIN_PSADBW,
2105 IX86_BUILTIN_PSHUFW,
2106
2107 IX86_BUILTIN_PSLLW,
2108 IX86_BUILTIN_PSLLD,
2109 IX86_BUILTIN_PSLLQ,
2110 IX86_BUILTIN_PSRAW,
2111 IX86_BUILTIN_PSRAD,
2112 IX86_BUILTIN_PSRLW,
2113 IX86_BUILTIN_PSRLD,
2114 IX86_BUILTIN_PSRLQ,
2115 IX86_BUILTIN_PSLLWI,
2116 IX86_BUILTIN_PSLLDI,
2117 IX86_BUILTIN_PSLLQI,
2118 IX86_BUILTIN_PSRAWI,
2119 IX86_BUILTIN_PSRADI,
2120 IX86_BUILTIN_PSRLWI,
2121 IX86_BUILTIN_PSRLDI,
2122 IX86_BUILTIN_PSRLQI,
2123
2124 IX86_BUILTIN_PUNPCKHBW,
2125 IX86_BUILTIN_PUNPCKHWD,
2126 IX86_BUILTIN_PUNPCKHDQ,
2127 IX86_BUILTIN_PUNPCKLBW,
2128 IX86_BUILTIN_PUNPCKLWD,
2129 IX86_BUILTIN_PUNPCKLDQ,
2130
2131 IX86_BUILTIN_SHUFPS,
2132
2133 IX86_BUILTIN_RCPPS,
2134 IX86_BUILTIN_RCPSS,
2135 IX86_BUILTIN_RSQRTPS,
2136 IX86_BUILTIN_RSQRTSS,
2137 IX86_BUILTIN_SQRTPS,
2138 IX86_BUILTIN_SQRTSS,
2139
2140 IX86_BUILTIN_UNPCKHPS,
2141 IX86_BUILTIN_UNPCKLPS,
2142
2143 IX86_BUILTIN_ANDPS,
2144 IX86_BUILTIN_ANDNPS,
2145 IX86_BUILTIN_ORPS,
2146 IX86_BUILTIN_XORPS,
2147
2148 IX86_BUILTIN_EMMS,
2149 IX86_BUILTIN_LDMXCSR,
2150 IX86_BUILTIN_STMXCSR,
2151 IX86_BUILTIN_SFENCE,
2152
2153 /* 3DNow! Original */
2154 IX86_BUILTIN_FEMMS,
2155 IX86_BUILTIN_PAVGUSB,
2156 IX86_BUILTIN_PF2ID,
2157 IX86_BUILTIN_PFACC,
2158 IX86_BUILTIN_PFADD,
2159 IX86_BUILTIN_PFCMPEQ,
2160 IX86_BUILTIN_PFCMPGE,
2161 IX86_BUILTIN_PFCMPGT,
2162 IX86_BUILTIN_PFMAX,
2163 IX86_BUILTIN_PFMIN,
2164 IX86_BUILTIN_PFMUL,
2165 IX86_BUILTIN_PFRCP,
2166 IX86_BUILTIN_PFRCPIT1,
2167 IX86_BUILTIN_PFRCPIT2,
2168 IX86_BUILTIN_PFRSQIT1,
2169 IX86_BUILTIN_PFRSQRT,
2170 IX86_BUILTIN_PFSUB,
2171 IX86_BUILTIN_PFSUBR,
2172 IX86_BUILTIN_PI2FD,
2173 IX86_BUILTIN_PMULHRW,
2174
2175 /* 3DNow! Athlon Extensions */
2176 IX86_BUILTIN_PF2IW,
2177 IX86_BUILTIN_PFNACC,
2178 IX86_BUILTIN_PFPNACC,
2179 IX86_BUILTIN_PI2FW,
2180 IX86_BUILTIN_PSWAPDSI,
2181 IX86_BUILTIN_PSWAPDSF,
2182
2183 IX86_BUILTIN_SSE_ZERO,
2184 IX86_BUILTIN_MMX_ZERO,
2185
2186 /* SSE2 */
2187 IX86_BUILTIN_ADDPD,
2188 IX86_BUILTIN_ADDSD,
2189 IX86_BUILTIN_DIVPD,
2190 IX86_BUILTIN_DIVSD,
2191 IX86_BUILTIN_MULPD,
2192 IX86_BUILTIN_MULSD,
2193 IX86_BUILTIN_SUBPD,
2194 IX86_BUILTIN_SUBSD,
2195
2196 IX86_BUILTIN_CMPEQPD,
2197 IX86_BUILTIN_CMPLTPD,
2198 IX86_BUILTIN_CMPLEPD,
2199 IX86_BUILTIN_CMPGTPD,
2200 IX86_BUILTIN_CMPGEPD,
2201 IX86_BUILTIN_CMPNEQPD,
2202 IX86_BUILTIN_CMPNLTPD,
2203 IX86_BUILTIN_CMPNLEPD,
2204 IX86_BUILTIN_CMPNGTPD,
2205 IX86_BUILTIN_CMPNGEPD,
2206 IX86_BUILTIN_CMPORDPD,
2207 IX86_BUILTIN_CMPUNORDPD,
2208 IX86_BUILTIN_CMPNEPD,
2209 IX86_BUILTIN_CMPEQSD,
2210 IX86_BUILTIN_CMPLTSD,
2211 IX86_BUILTIN_CMPLESD,
2212 IX86_BUILTIN_CMPGTSD,
2213 IX86_BUILTIN_CMPGESD,
2214 IX86_BUILTIN_CMPNEQSD,
2215 IX86_BUILTIN_CMPNLTSD,
2216 IX86_BUILTIN_CMPNLESD,
2217 IX86_BUILTIN_CMPNGTSD,
2218 IX86_BUILTIN_CMPNGESD,
2219 IX86_BUILTIN_CMPORDSD,
2220 IX86_BUILTIN_CMPUNORDSD,
2221 IX86_BUILTIN_CMPNESD,
2222
2223 IX86_BUILTIN_COMIEQSD,
2224 IX86_BUILTIN_COMILTSD,
2225 IX86_BUILTIN_COMILESD,
2226 IX86_BUILTIN_COMIGTSD,
2227 IX86_BUILTIN_COMIGESD,
2228 IX86_BUILTIN_COMINEQSD,
2229 IX86_BUILTIN_UCOMIEQSD,
2230 IX86_BUILTIN_UCOMILTSD,
2231 IX86_BUILTIN_UCOMILESD,
2232 IX86_BUILTIN_UCOMIGTSD,
2233 IX86_BUILTIN_UCOMIGESD,
2234 IX86_BUILTIN_UCOMINEQSD,
2235
2236 IX86_BUILTIN_MAXPD,
2237 IX86_BUILTIN_MAXSD,
2238 IX86_BUILTIN_MINPD,
2239 IX86_BUILTIN_MINSD,
2240
2241 IX86_BUILTIN_ANDPD,
2242 IX86_BUILTIN_ANDNPD,
2243 IX86_BUILTIN_ORPD,
2244 IX86_BUILTIN_XORPD,
2245
2246 IX86_BUILTIN_SQRTPD,
2247 IX86_BUILTIN_SQRTSD,
2248
2249 IX86_BUILTIN_UNPCKHPD,
2250 IX86_BUILTIN_UNPCKLPD,
2251
2252 IX86_BUILTIN_SHUFPD,
2253
2254 IX86_BUILTIN_LOADAPD,
2255 IX86_BUILTIN_LOADUPD,
2256 IX86_BUILTIN_STOREAPD,
2257 IX86_BUILTIN_STOREUPD,
2258 IX86_BUILTIN_LOADSD,
2259 IX86_BUILTIN_STORESD,
2260 IX86_BUILTIN_MOVSD,
2261
2262 IX86_BUILTIN_LOADHPD,
2263 IX86_BUILTIN_LOADLPD,
2264 IX86_BUILTIN_STOREHPD,
2265 IX86_BUILTIN_STORELPD,
2266
2267 IX86_BUILTIN_CVTDQ2PD,
2268 IX86_BUILTIN_CVTDQ2PS,
2269
2270 IX86_BUILTIN_CVTPD2DQ,
2271 IX86_BUILTIN_CVTPD2PI,
2272 IX86_BUILTIN_CVTPD2PS,
2273 IX86_BUILTIN_CVTTPD2DQ,
2274 IX86_BUILTIN_CVTTPD2PI,
2275
2276 IX86_BUILTIN_CVTPI2PD,
2277 IX86_BUILTIN_CVTSI2SD,
2278
2279 IX86_BUILTIN_CVTSD2SI,
2280 IX86_BUILTIN_CVTSD2SS,
2281 IX86_BUILTIN_CVTSS2SD,
2282 IX86_BUILTIN_CVTTSD2SI,
2283
2284 IX86_BUILTIN_CVTPS2DQ,
2285 IX86_BUILTIN_CVTPS2PD,
2286 IX86_BUILTIN_CVTTPS2DQ,
2287
2288 IX86_BUILTIN_MOVNTI,
2289 IX86_BUILTIN_MOVNTPD,
2290 IX86_BUILTIN_MOVNTDQ,
2291
2292 IX86_BUILTIN_SETPD1,
2293 IX86_BUILTIN_SETPD,
2294 IX86_BUILTIN_CLRPD,
2295 IX86_BUILTIN_SETRPD,
2296 IX86_BUILTIN_LOADPD1,
2297 IX86_BUILTIN_LOADRPD,
2298 IX86_BUILTIN_STOREPD1,
2299 IX86_BUILTIN_STORERPD,
2300
2301 /* SSE2 MMX */
2302 IX86_BUILTIN_MASKMOVDQU,
2303 IX86_BUILTIN_MOVMSKPD,
2304 IX86_BUILTIN_PMOVMSKB128,
2305 IX86_BUILTIN_MOVQ2DQ,
2306
2307 IX86_BUILTIN_PACKSSWB128,
2308 IX86_BUILTIN_PACKSSDW128,
2309 IX86_BUILTIN_PACKUSWB128,
2310
2311 IX86_BUILTIN_PADDB128,
2312 IX86_BUILTIN_PADDW128,
2313 IX86_BUILTIN_PADDD128,
2314 IX86_BUILTIN_PADDQ128,
2315 IX86_BUILTIN_PADDSB128,
2316 IX86_BUILTIN_PADDSW128,
2317 IX86_BUILTIN_PADDUSB128,
2318 IX86_BUILTIN_PADDUSW128,
2319 IX86_BUILTIN_PSUBB128,
2320 IX86_BUILTIN_PSUBW128,
2321 IX86_BUILTIN_PSUBD128,
2322 IX86_BUILTIN_PSUBQ128,
2323 IX86_BUILTIN_PSUBSB128,
2324 IX86_BUILTIN_PSUBSW128,
2325 IX86_BUILTIN_PSUBUSB128,
2326 IX86_BUILTIN_PSUBUSW128,
2327
2328 IX86_BUILTIN_PAND128,
2329 IX86_BUILTIN_PANDN128,
2330 IX86_BUILTIN_POR128,
2331 IX86_BUILTIN_PXOR128,
2332
2333 IX86_BUILTIN_PAVGB128,
2334 IX86_BUILTIN_PAVGW128,
2335
2336 IX86_BUILTIN_PCMPEQB128,
2337 IX86_BUILTIN_PCMPEQW128,
2338 IX86_BUILTIN_PCMPEQD128,
2339 IX86_BUILTIN_PCMPGTB128,
2340 IX86_BUILTIN_PCMPGTW128,
2341 IX86_BUILTIN_PCMPGTD128,
2342
2343 IX86_BUILTIN_PEXTRW128,
2344 IX86_BUILTIN_PINSRW128,
2345
2346 IX86_BUILTIN_PMADDWD128,
2347
2348 IX86_BUILTIN_PMAXSW128,
2349 IX86_BUILTIN_PMAXUB128,
2350 IX86_BUILTIN_PMINSW128,
2351 IX86_BUILTIN_PMINUB128,
2352
2353 IX86_BUILTIN_PMULUDQ,
2354 IX86_BUILTIN_PMULUDQ128,
2355 IX86_BUILTIN_PMULHUW128,
2356 IX86_BUILTIN_PMULHW128,
2357 IX86_BUILTIN_PMULLW128,
2358
2359 IX86_BUILTIN_PSADBW128,
2360 IX86_BUILTIN_PSHUFHW,
2361 IX86_BUILTIN_PSHUFLW,
2362 IX86_BUILTIN_PSHUFD,
2363
2364 IX86_BUILTIN_PSLLW128,
2365 IX86_BUILTIN_PSLLD128,
2366 IX86_BUILTIN_PSLLQ128,
2367 IX86_BUILTIN_PSRAW128,
2368 IX86_BUILTIN_PSRAD128,
2369 IX86_BUILTIN_PSRLW128,
2370 IX86_BUILTIN_PSRLD128,
2371 IX86_BUILTIN_PSRLQ128,
2372 IX86_BUILTIN_PSLLWI128,
2373 IX86_BUILTIN_PSLLDI128,
2374 IX86_BUILTIN_PSLLQI128,
2375 IX86_BUILTIN_PSRAWI128,
2376 IX86_BUILTIN_PSRADI128,
2377 IX86_BUILTIN_PSRLWI128,
2378 IX86_BUILTIN_PSRLDI128,
2379 IX86_BUILTIN_PSRLQI128,
2380
2381 IX86_BUILTIN_PUNPCKHBW128,
2382 IX86_BUILTIN_PUNPCKHWD128,
2383 IX86_BUILTIN_PUNPCKHDQ128,
2384 IX86_BUILTIN_PUNPCKLBW128,
2385 IX86_BUILTIN_PUNPCKLWD128,
2386 IX86_BUILTIN_PUNPCKLDQ128,
2387
2388 IX86_BUILTIN_CLFLUSH,
2389 IX86_BUILTIN_MFENCE,
2390 IX86_BUILTIN_LFENCE,
2391
2392 IX86_BUILTIN_MAX
2393 };
2394 \f
2395 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
2396 #define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding
2397
2398 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2399 do { \
2400 const char *xname = (NAME); \
2401 if (xname[0] == '%') \
2402 xname += 2; \
2403 if (xname[0] == '*') \
2404 xname += 1; \
2405 else \
2406 fputs (user_label_prefix, FILE); \
2407 fputs (xname, FILE); \
2408 } while (0)
2409 \f
2410 /* Max number of args passed in registers. If this is more than 3, we will
2411 have problems with ebx (register #4), since it is a caller save register and
2412 is also used as the pic register in ELF. So for now, don't allow more than
2413 3 registers to be passed in registers. */
2414
2415 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2416
2417 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2418
2419 \f
2420 /* Specify the machine mode that this machine uses
2421 for the index in the tablejump instruction. */
2422 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2423
2424 /* Define as C expression which evaluates to nonzero if the tablejump
2425 instruction expects the table to contain offsets from the address of the
2426 table.
2427 Do not define this if the table should contain absolute addresses. */
2428 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2429
2430 /* Define this as 1 if `char' should by default be signed; else as 0. */
2431 #define DEFAULT_SIGNED_CHAR 1
2432
2433 /* Number of bytes moved into a data cache for a single prefetch operation. */
2434 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2435
2436 /* Number of prefetch operations that can be done in parallel. */
2437 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2438
2439 /* Max number of bytes we can move from memory to memory
2440 in one reasonably fast instruction. */
2441 #define MOVE_MAX 16
2442
2443 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2444 move efficiently, as opposed to MOVE_MAX which is the maximum
2445 number of bytes we can move with a single instruction. */
2446 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2447
2448 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2449 move-instruction pairs, we will do a movstr or libcall instead.
2450 Increasing the value will always make code faster, but eventually
2451 incurs high cost in increased code size.
2452
2453 If you don't define this, a reasonable default is used. */
2454
2455 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2456
2457 /* Define if shifts truncate the shift count
2458 which implies one can omit a sign-extension or zero-extension
2459 of a shift count. */
2460 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2461
2462 /* #define SHIFT_COUNT_TRUNCATED */
2463
2464 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2465 is done just by pretending it is already truncated. */
2466 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2467
2468 /* We assume that the store-condition-codes instructions store 0 for false
2469 and some other value for true. This is the value stored for true. */
2470
2471 #define STORE_FLAG_VALUE 1
2472
2473 /* When a prototype says `char' or `short', really pass an `int'.
2474 (The 386 can't easily push less than an int.) */
2475
2476 #define PROMOTE_PROTOTYPES 1
2477
2478 /* A macro to update M and UNSIGNEDP when an object whose type is
2479 TYPE and which has the specified mode and signedness is to be
2480 stored in a register. This macro is only called when TYPE is a
2481 scalar type.
2482
2483 On i386 it is sometimes useful to promote HImode and QImode
2484 quantities to SImode. The choice depends on target type. */
2485
2486 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2487 do { \
2488 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2489 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2490 (MODE) = SImode; \
2491 } while (0)
2492
2493 /* Specify the machine mode that pointers have.
2494 After generation of rtl, the compiler makes no further distinction
2495 between pointers and any other objects of this machine mode. */
2496 #define Pmode (TARGET_64BIT ? DImode : SImode)
2497
2498 /* A function address in a call instruction
2499 is a byte address (for indexing purposes)
2500 so give the MEM rtx a byte's mode. */
2501 #define FUNCTION_MODE QImode
2502 \f
2503 /* A part of a C `switch' statement that describes the relative costs
2504 of constant RTL expressions. It must contain `case' labels for
2505 expression codes `const_int', `const', `symbol_ref', `label_ref'
2506 and `const_double'. Each case must ultimately reach a `return'
2507 statement to return the relative cost of the use of that kind of
2508 constant value in an expression. The cost may depend on the
2509 precise value of the constant, which is available for examination
2510 in X, and the rtx code of the expression in which it is contained,
2511 found in OUTER_CODE.
2512
2513 CODE is the expression code--redundant, since it can be obtained
2514 with `GET_CODE (X)'. */
2515
2516 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2517 case CONST_INT: \
2518 case CONST: \
2519 case LABEL_REF: \
2520 case SYMBOL_REF: \
2521 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2522 return 3; \
2523 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2524 return 2; \
2525 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2526 \
2527 case CONST_DOUBLE: \
2528 if (GET_MODE (RTX) == VOIDmode) \
2529 return 0; \
2530 switch (standard_80387_constant_p (RTX)) \
2531 { \
2532 case 1: /* 0.0 */ \
2533 return 1; \
2534 case 2: /* 1.0 */ \
2535 return 2; \
2536 default: \
2537 /* Start with (MEM (SYMBOL_REF)), since that's where \
2538 it'll probably end up. Add a penalty for size. */ \
2539 return (COSTS_N_INSNS (1) + (flag_pic != 0) \
2540 + (GET_MODE (RTX) == SFmode ? 0 \
2541 : GET_MODE (RTX) == DFmode ? 1 : 2)); \
2542 }
2543
2544 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2545 #define TOPLEVEL_COSTS_N_INSNS(N) \
2546 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2547
2548 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2549 This can be used, for example, to indicate how costly a multiply
2550 instruction is. In writing this macro, you can use the construct
2551 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2552 instructions. OUTER_CODE is the code of the expression in which X
2553 is contained.
2554
2555 This macro is optional; do not define it if the default cost
2556 assumptions are adequate for the target machine. */
2557
2558 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2559 case ZERO_EXTEND: \
2560 /* The zero extensions is often completely free on x86_64, so make \
2561 it as cheap as possible. */ \
2562 if (TARGET_64BIT && GET_MODE (X) == DImode \
2563 && GET_MODE (XEXP (X, 0)) == SImode) \
2564 { \
2565 total = 1; goto egress_rtx_costs; \
2566 } \
2567 else \
2568 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2569 ix86_cost->add : ix86_cost->movzx); \
2570 break; \
2571 case SIGN_EXTEND: \
2572 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2573 break; \
2574 case ASHIFT: \
2575 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2576 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2577 { \
2578 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2579 if (value == 1) \
2580 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2581 if ((value == 2 || value == 3) \
2582 && !TARGET_DECOMPOSE_LEA \
2583 && ix86_cost->lea <= ix86_cost->shift_const) \
2584 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2585 } \
2586 /* fall through */ \
2587 \
2588 case ROTATE: \
2589 case ASHIFTRT: \
2590 case LSHIFTRT: \
2591 case ROTATERT: \
2592 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2593 { \
2594 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2595 { \
2596 if (INTVAL (XEXP (X, 1)) > 32) \
2597 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2598 else \
2599 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2600 } \
2601 else \
2602 { \
2603 if (GET_CODE (XEXP (X, 1)) == AND) \
2604 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2605 else \
2606 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2607 } \
2608 } \
2609 else \
2610 { \
2611 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2612 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2613 else \
2614 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2615 } \
2616 break; \
2617 \
2618 case MULT: \
2619 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2620 { \
2621 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2622 int nbits = 0; \
2623 \
2624 while (value != 0) \
2625 { \
2626 nbits++; \
2627 value >>= 1; \
2628 } \
2629 \
2630 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2631 + nbits * ix86_cost->mult_bit); \
2632 } \
2633 else /* This is arbitrary */ \
2634 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2635 + 7 * ix86_cost->mult_bit); \
2636 \
2637 case DIV: \
2638 case UDIV: \
2639 case MOD: \
2640 case UMOD: \
2641 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2642 \
2643 case PLUS: \
2644 if (!TARGET_DECOMPOSE_LEA \
2645 && INTEGRAL_MODE_P (GET_MODE (X)) \
2646 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2647 { \
2648 if (GET_CODE (XEXP (X, 0)) == PLUS \
2649 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2650 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2651 && CONSTANT_P (XEXP (X, 1))) \
2652 { \
2653 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2654 if (val == 2 || val == 4 || val == 8) \
2655 { \
2656 return (COSTS_N_INSNS (ix86_cost->lea) \
2657 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2658 (OUTER_CODE)) \
2659 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2660 (OUTER_CODE)) \
2661 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2662 } \
2663 } \
2664 else if (GET_CODE (XEXP (X, 0)) == MULT \
2665 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2666 { \
2667 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2668 if (val == 2 || val == 4 || val == 8) \
2669 { \
2670 return (COSTS_N_INSNS (ix86_cost->lea) \
2671 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2672 (OUTER_CODE)) \
2673 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2674 } \
2675 } \
2676 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2677 { \
2678 return (COSTS_N_INSNS (ix86_cost->lea) \
2679 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2680 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2681 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2682 } \
2683 } \
2684 \
2685 /* fall through */ \
2686 case AND: \
2687 case IOR: \
2688 case XOR: \
2689 case MINUS: \
2690 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2691 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2692 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2693 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2694 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2695 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2696 \
2697 /* fall through */ \
2698 case NEG: \
2699 case NOT: \
2700 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2701 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2702 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2703 \
2704 case FLOAT_EXTEND: \
2705 TOPLEVEL_COSTS_N_INSNS (0); \
2706 \
2707 egress_rtx_costs: \
2708 break;
2709
2710
2711 /* An expression giving the cost of an addressing mode that contains
2712 ADDRESS. If not defined, the cost is computed from the ADDRESS
2713 expression and the `CONST_COSTS' values.
2714
2715 For most CISC machines, the default cost is a good approximation
2716 of the true cost of the addressing mode. However, on RISC
2717 machines, all instructions normally have the same length and
2718 execution time. Hence all addresses will have equal costs.
2719
2720 In cases where more than one form of an address is known, the form
2721 with the lowest cost will be used. If multiple forms have the
2722 same, lowest, cost, the one that is the most complex will be used.
2723
2724 For example, suppose an address that is equal to the sum of a
2725 register and a constant is used twice in the same basic block.
2726 When this macro is not defined, the address will be computed in a
2727 register and memory references will be indirect through that
2728 register. On machines where the cost of the addressing mode
2729 containing the sum is no higher than that of a simple indirect
2730 reference, this will produce an additional instruction and
2731 possibly require an additional register. Proper specification of
2732 this macro eliminates this overhead for such machines.
2733
2734 Similar use of this macro is made in strength reduction of loops.
2735
2736 ADDRESS need not be valid as an address. In such a case, the cost
2737 is not relevant and can be any value; invalid addresses need not be
2738 assigned a different cost.
2739
2740 On machines where an address involving more than one register is as
2741 cheap as an address computation involving only one register,
2742 defining `ADDRESS_COST' to reflect this can cause two registers to
2743 be live over a region of code where only one would have been if
2744 `ADDRESS_COST' were not defined in that manner. This effect should
2745 be considered in the definition of this macro. Equivalent costs
2746 should probably only be given to addresses with different numbers
2747 of registers on machines with lots of registers.
2748
2749 This macro will normally either not be defined or be defined as a
2750 constant.
2751
2752 For i386, it is better to use a complex address than let gcc copy
2753 the address into a reg and make a new pseudo. But not if the address
2754 requires to two regs - that would mean more pseudos with longer
2755 lifetimes. */
2756
2757 #define ADDRESS_COST(RTX) \
2758 ix86_address_cost (RTX)
2759
2760 /* A C expression for the cost of moving data from a register in class FROM to
2761 one in class TO. The classes are expressed using the enumeration values
2762 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2763 interpreted relative to that.
2764
2765 It is not required that the cost always equal 2 when FROM is the same as TO;
2766 on some machines it is expensive to move between registers if they are not
2767 general registers. */
2768
2769 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2770 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2771
2772 /* A C expression for the cost of moving data of mode M between a
2773 register and memory. A value of 2 is the default; this cost is
2774 relative to those in `REGISTER_MOVE_COST'.
2775
2776 If moving between registers and memory is more expensive than
2777 between two registers, you should define this macro to express the
2778 relative cost. */
2779
2780 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2781 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2782
2783 /* A C expression for the cost of a branch instruction. A value of 1
2784 is the default; other values are interpreted relative to that. */
2785
2786 #define BRANCH_COST ix86_branch_cost
2787
2788 /* Define this macro as a C expression which is nonzero if accessing
2789 less than a word of memory (i.e. a `char' or a `short') is no
2790 faster than accessing a word of memory, i.e., if such access
2791 require more than one instruction or if there is no difference in
2792 cost between byte and (aligned) word loads.
2793
2794 When this macro is not defined, the compiler will access a field by
2795 finding the smallest containing object; when it is defined, a
2796 fullword load will be used if alignment permits. Unless bytes
2797 accesses are faster than word accesses, using word accesses is
2798 preferable since it may eliminate subsequent memory access if
2799 subsequent accesses occur to other fields in the same word of the
2800 structure, but to different bytes. */
2801
2802 #define SLOW_BYTE_ACCESS 0
2803
2804 /* Nonzero if access to memory by shorts is slow and undesirable. */
2805 #define SLOW_SHORT_ACCESS 0
2806
2807 /* Define this macro to be the value 1 if unaligned accesses have a
2808 cost many times greater than aligned accesses, for example if they
2809 are emulated in a trap handler.
2810
2811 When this macro is non-zero, the compiler will act as if
2812 `STRICT_ALIGNMENT' were non-zero when generating code for block
2813 moves. This can cause significantly more instructions to be
2814 produced. Therefore, do not set this macro non-zero if unaligned
2815 accesses only add a cycle or two to the time for a memory access.
2816
2817 If the value of this macro is always zero, it need not be defined. */
2818
2819 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2820
2821 /* Define this macro to inhibit strength reduction of memory
2822 addresses. (On some machines, such strength reduction seems to do
2823 harm rather than good.) */
2824
2825 /* #define DONT_REDUCE_ADDR */
2826
2827 /* Define this macro if it is as good or better to call a constant
2828 function address than to call an address kept in a register.
2829
2830 Desirable on the 386 because a CALL with a constant address is
2831 faster than one with a register address. */
2832
2833 #define NO_FUNCTION_CSE
2834
2835 /* Define this macro if it is as good or better for a function to call
2836 itself with an explicit address than to call an address kept in a
2837 register. */
2838
2839 #define NO_RECURSIVE_FUNCTION_CSE
2840 \f
2841 /* Add any extra modes needed to represent the condition code.
2842
2843 For the i386, we need separate modes when floating-point
2844 equality comparisons are being done.
2845
2846 Add CCNO to indicate comparisons against zero that requires
2847 Overflow flag to be unset. Sign bit test is used instead and
2848 thus can be used to form "a&b>0" type of tests.
2849
2850 Add CCGC to indicate comparisons agains zero that allows
2851 unspecified garbage in the Carry flag. This mode is used
2852 by inc/dec instructions.
2853
2854 Add CCGOC to indicate comparisons agains zero that allows
2855 unspecified garbage in the Carry and Overflow flag. This
2856 mode is used to simulate comparisons of (a-b) and (a+b)
2857 against zero using sub/cmp/add operations.
2858
2859 Add CCZ to indicate that only the Zero flag is valid. */
2860
2861 #define EXTRA_CC_MODES \
2862 CC (CCGCmode, "CCGC") \
2863 CC (CCGOCmode, "CCGOC") \
2864 CC (CCNOmode, "CCNO") \
2865 CC (CCZmode, "CCZ") \
2866 CC (CCFPmode, "CCFP") \
2867 CC (CCFPUmode, "CCFPU")
2868
2869 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2870 return the mode to be used for the comparison.
2871
2872 For floating-point equality comparisons, CCFPEQmode should be used.
2873 VOIDmode should be used in all other cases.
2874
2875 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2876 possible, to allow for more combinations. */
2877
2878 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2879
2880 /* Return non-zero if MODE implies a floating point inequality can be
2881 reversed. */
2882
2883 #define REVERSIBLE_CC_MODE(MODE) 1
2884
2885 /* A C expression whose value is reversed condition code of the CODE for
2886 comparison done in CC_MODE mode. */
2887 #define REVERSE_CONDITION(CODE, MODE) \
2888 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2889 : reverse_condition_maybe_unordered (CODE))
2890
2891 \f
2892 /* Control the assembler format that we output, to the extent
2893 this does not vary between assemblers. */
2894
2895 /* How to refer to registers in assembler output.
2896 This sequence is indexed by compiler's hard-register-number (see above). */
2897
2898 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2899 For non floating point regs, the following are the HImode names.
2900
2901 For float regs, the stack top is sometimes referred to as "%st(0)"
2902 instead of just "%st". PRINT_REG handles this with the "y" code. */
2903
2904 #undef HI_REGISTER_NAMES
2905 #define HI_REGISTER_NAMES \
2906 {"ax","dx","cx","bx","si","di","bp","sp", \
2907 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2908 "flags","fpsr", "dirflag", "frame", \
2909 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2910 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2911 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2912 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2913
2914 #define REGISTER_NAMES HI_REGISTER_NAMES
2915
2916 /* Table of additional register names to use in user input. */
2917
2918 #define ADDITIONAL_REGISTER_NAMES \
2919 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2920 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2921 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2922 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2923 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2924 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2925 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2926 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2927
2928 /* Note we are omitting these since currently I don't know how
2929 to get gcc to use these, since they want the same but different
2930 number as al, and ax.
2931 */
2932
2933 #define QI_REGISTER_NAMES \
2934 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2935
2936 /* These parallel the array above, and can be used to access bits 8:15
2937 of regs 0 through 3. */
2938
2939 #define QI_HIGH_REGISTER_NAMES \
2940 {"ah", "dh", "ch", "bh", }
2941
2942 /* How to renumber registers for dbx and gdb. */
2943
2944 #define DBX_REGISTER_NUMBER(N) \
2945 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2946
2947 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2948 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2949 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2950
2951 /* Before the prologue, RA is at 0(%esp). */
2952 #define INCOMING_RETURN_ADDR_RTX \
2953 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2954
2955 /* After the prologue, RA is at -4(AP) in the current frame. */
2956 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2957 ((COUNT) == 0 \
2958 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2959 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2960
2961 /* PC is dbx register 8; let's use that column for RA. */
2962 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2963
2964 /* Before the prologue, the top of the frame is at 4(%esp). */
2965 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2966
2967 /* Describe how we implement __builtin_eh_return. */
2968 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2969 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2970
2971
2972 /* Select a format to encode pointers in exception handling data. CODE
2973 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2974 true if the symbol may be affected by dynamic relocations.
2975
2976 ??? All x86 object file formats are capable of representing this.
2977 After all, the relocation needed is the same as for the call insn.
2978 Whether or not a particular assembler allows us to enter such, I
2979 guess we'll have to see. */
2980 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2981 (flag_pic \
2982 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2983 : DW_EH_PE_absptr)
2984
2985 /* This is how to output the definition of a user-level label named NAME,
2986 such as the label on a static function or variable NAME. */
2987
2988 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2989 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2990
2991 /* Store in OUTPUT a string (made with alloca) containing
2992 an assembler-name for a local static variable named NAME.
2993 LABELNO is an integer which is different for each call. */
2994
2995 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2996 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2997 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2998
2999 /* This is how to output an insn to push a register on the stack.
3000 It need not be very fast code. */
3001
3002 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
3003 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
3004
3005 /* This is how to output an insn to pop a register from the stack.
3006 It need not be very fast code. */
3007
3008 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
3009 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
3010
3011 /* This is how to output an element of a case-vector that is absolute. */
3012
3013 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
3014 ix86_output_addr_vec_elt ((FILE), (VALUE))
3015
3016 /* This is how to output an element of a case-vector that is relative. */
3017
3018 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3019 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
3020
3021 /* Under some conditions we need jump tables in the text section, because
3022 the assembler cannot handle label differences between sections. */
3023
3024 #define JUMP_TABLES_IN_TEXT_SECTION \
3025 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
3026
3027 /* A C statement that outputs an address constant appropriate to
3028 for DWARF debugging. */
3029
3030 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
3031 i386_dwarf_output_addr_const ((FILE), (X))
3032
3033 /* Either simplify a location expression, or return the original. */
3034
3035 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
3036 i386_simplify_dwarf_addr (X)
3037
3038 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
3039 and switch back. For x86 we do this only to save a few bytes that
3040 would otherwise be unused in the text section. */
3041 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3042 asm (SECTION_OP "\n\t" \
3043 "call " USER_LABEL_PREFIX #FUNC "\n" \
3044 TEXT_SECTION_ASM_OP);
3045 \f
3046 /* Print operand X (an rtx) in assembler syntax to file FILE.
3047 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3048 Effect of various CODE letters is described in i386.c near
3049 print_operand function. */
3050
3051 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
3052 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
3053
3054 /* Print the name of a register based on its machine mode and number.
3055 If CODE is 'w', pretend the mode is HImode.
3056 If CODE is 'b', pretend the mode is QImode.
3057 If CODE is 'k', pretend the mode is SImode.
3058 If CODE is 'q', pretend the mode is DImode.
3059 If CODE is 'h', pretend the reg is the `high' byte register.
3060 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
3061
3062 #define PRINT_REG(X, CODE, FILE) \
3063 print_reg ((X), (CODE), (FILE))
3064
3065 #define PRINT_OPERAND(FILE, X, CODE) \
3066 print_operand ((FILE), (X), (CODE))
3067
3068 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3069 print_operand_address ((FILE), (ADDR))
3070
3071 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
3072 do { \
3073 if (! output_addr_const_extra (FILE, (X))) \
3074 goto FAIL; \
3075 } while (0);
3076
3077 /* Print the name of a register for based on its machine mode and number.
3078 This macro is used to print debugging output.
3079 This macro is different from PRINT_REG in that it may be used in
3080 programs that are not linked with aux-output.o. */
3081
3082 #define DEBUG_PRINT_REG(X, CODE, FILE) \
3083 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
3084 static const char * const qi_name[] = QI_REGISTER_NAMES; \
3085 fprintf ((FILE), "%d ", REGNO (X)); \
3086 if (REGNO (X) == FLAGS_REG) \
3087 { fputs ("flags", (FILE)); break; } \
3088 if (REGNO (X) == DIRFLAG_REG) \
3089 { fputs ("dirflag", (FILE)); break; } \
3090 if (REGNO (X) == FPSR_REG) \
3091 { fputs ("fpsr", (FILE)); break; } \
3092 if (REGNO (X) == ARG_POINTER_REGNUM) \
3093 { fputs ("argp", (FILE)); break; } \
3094 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3095 { fputs ("frame", (FILE)); break; } \
3096 if (STACK_TOP_P (X)) \
3097 { fputs ("st(0)", (FILE)); break; } \
3098 if (FP_REG_P (X)) \
3099 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
3100 if (REX_INT_REG_P (X)) \
3101 { \
3102 switch (GET_MODE_SIZE (GET_MODE (X))) \
3103 { \
3104 default: \
3105 case 8: \
3106 fprintf ((FILE), "r%i", REGNO (X) \
3107 - FIRST_REX_INT_REG + 8); \
3108 break; \
3109 case 4: \
3110 fprintf ((FILE), "r%id", REGNO (X) \
3111 - FIRST_REX_INT_REG + 8); \
3112 break; \
3113 case 2: \
3114 fprintf ((FILE), "r%iw", REGNO (X) \
3115 - FIRST_REX_INT_REG + 8); \
3116 break; \
3117 case 1: \
3118 fprintf ((FILE), "r%ib", REGNO (X) \
3119 - FIRST_REX_INT_REG + 8); \
3120 break; \
3121 } \
3122 break; \
3123 } \
3124 switch (GET_MODE_SIZE (GET_MODE (X))) \
3125 { \
3126 case 8: \
3127 fputs ("r", (FILE)); \
3128 fputs (hi_name[REGNO (X)], (FILE)); \
3129 break; \
3130 default: \
3131 fputs ("e", (FILE)); \
3132 case 2: \
3133 fputs (hi_name[REGNO (X)], (FILE)); \
3134 break; \
3135 case 1: \
3136 fputs (qi_name[REGNO (X)], (FILE)); \
3137 break; \
3138 } \
3139 } while (0)
3140
3141 /* a letter which is not needed by the normal asm syntax, which
3142 we can use for operand syntax in the extended asm */
3143
3144 #define ASM_OPERAND_LETTER '#'
3145 #define RET return ""
3146 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3147 \f
3148 /* Define the codes that are matched by predicates in i386.c. */
3149
3150 #define PREDICATE_CODES \
3151 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3152 SYMBOL_REF, LABEL_REF, CONST}}, \
3153 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3154 SYMBOL_REF, LABEL_REF, CONST}}, \
3155 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3156 SYMBOL_REF, LABEL_REF, CONST}}, \
3157 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3158 SYMBOL_REF, LABEL_REF, CONST}}, \
3159 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3160 SYMBOL_REF, LABEL_REF, CONST}}, \
3161 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3162 SYMBOL_REF, LABEL_REF, CONST}}, \
3163 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3164 SYMBOL_REF, LABEL_REF}}, \
3165 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3166 {"const_int_1_operand", {CONST_INT}}, \
3167 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3168 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3169 LABEL_REF, SUBREG, REG, MEM}}, \
3170 {"pic_symbolic_operand", {CONST}}, \
3171 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3172 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3173 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3174 {"const1_operand", {CONST_INT}}, \
3175 {"const248_operand", {CONST_INT}}, \
3176 {"incdec_operand", {CONST_INT}}, \
3177 {"mmx_reg_operand", {REG}}, \
3178 {"reg_no_sp_operand", {SUBREG, REG}}, \
3179 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3180 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3181 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3182 {"q_regs_operand", {SUBREG, REG}}, \
3183 {"non_q_regs_operand", {SUBREG, REG}}, \
3184 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3185 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3186 GE, UNGE, LTGT, UNEQ}}, \
3187 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3188 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3189 }}, \
3190 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3191 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3192 UNGE, UNGT, LTGT, UNEQ }}, \
3193 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3194 {"ext_register_operand", {SUBREG, REG}}, \
3195 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3196 {"mult_operator", {MULT}}, \
3197 {"div_operator", {DIV}}, \
3198 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3199 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3200 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3201 LSHIFTRT, ROTATERT}}, \
3202 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3203 {"memory_displacement_operand", {MEM}}, \
3204 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3205 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3206 {"long_memory_operand", {MEM}}, \
3207 {"tls_symbolic_operand", {SYMBOL_REF}}, \
3208 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3209 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3210 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
3211 {"local_exec_symbolic_operand", {SYMBOL_REF}},
3212
3213 /* A list of predicates that do special things with modes, and so
3214 should not elicit warnings for VOIDmode match_operand. */
3215
3216 #define SPECIAL_MODE_PREDICATES \
3217 "ext_register_operand",
3218 \f
3219 /* Which processor to schedule for. The cpu attribute defines a list that
3220 mirrors this list, so changes to i386.md must be made at the same time. */
3221
3222 enum processor_type
3223 {
3224 PROCESSOR_I386, /* 80386 */
3225 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
3226 PROCESSOR_PENTIUM,
3227 PROCESSOR_PENTIUMPRO,
3228 PROCESSOR_K6,
3229 PROCESSOR_ATHLON,
3230 PROCESSOR_PENTIUM4,
3231 PROCESSOR_max
3232 };
3233
3234 extern enum processor_type ix86_cpu;
3235 extern const char *ix86_cpu_string;
3236
3237 extern enum processor_type ix86_arch;
3238 extern const char *ix86_arch_string;
3239
3240 enum fpmath_unit
3241 {
3242 FPMATH_387 = 1,
3243 FPMATH_SSE = 2
3244 };
3245
3246 extern enum fpmath_unit ix86_fpmath;
3247 extern const char *ix86_fpmath_string;
3248
3249 enum tls_dialect
3250 {
3251 TLS_DIALECT_GNU,
3252 TLS_DIALECT_SUN
3253 };
3254
3255 extern enum tls_dialect ix86_tls_dialect;
3256 extern const char *ix86_tls_dialect_string;
3257
3258 enum cmodel {
3259 CM_32, /* The traditional 32-bit ABI. */
3260 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
3261 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
3262 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
3263 CM_LARGE, /* No assumptions. */
3264 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
3265 };
3266
3267 extern enum cmodel ix86_cmodel;
3268 extern const char *ix86_cmodel_string;
3269
3270 /* Size of the RED_ZONE area. */
3271 #define RED_ZONE_SIZE 128
3272 /* Reserved area of the red zone for temporaries. */
3273 #define RED_ZONE_RESERVE 8
3274
3275 enum asm_dialect {
3276 ASM_ATT,
3277 ASM_INTEL
3278 };
3279
3280 extern const char *ix86_asm_string;
3281 extern enum asm_dialect ix86_asm_dialect;
3282
3283 extern int ix86_regparm;
3284 extern const char *ix86_regparm_string;
3285
3286 extern int ix86_preferred_stack_boundary;
3287 extern const char *ix86_preferred_stack_boundary_string;
3288
3289 extern int ix86_branch_cost;
3290 extern const char *ix86_branch_cost_string;
3291
3292 extern const char *ix86_debug_arg_string;
3293 extern const char *ix86_debug_addr_string;
3294
3295 /* Obsoleted by -f options. Remove before 3.2 ships. */
3296 extern const char *ix86_align_loops_string;
3297 extern const char *ix86_align_jumps_string;
3298 extern const char *ix86_align_funcs_string;
3299
3300 /* Smallest class containing REGNO. */
3301 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
3302
3303 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3304 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3305 \f
3306 /* To properly truncate FP values into integers, we need to set i387 control
3307 word. We can't emit proper mode switching code before reload, as spills
3308 generated by reload may truncate values incorrectly, but we still can avoid
3309 redundant computation of new control word by the mode switching pass.
3310 The fldcw instructions are still emitted redundantly, but this is probably
3311 not going to be noticeable problem, as most CPUs do have fast path for
3312 the sequence.
3313
3314 The machinery is to emit simple truncation instructions and split them
3315 before reload to instructions having USEs of two memory locations that
3316 are filled by this code to old and new control word.
3317
3318 Post-reload pass may be later used to eliminate the redundant fildcw if
3319 needed. */
3320
3321 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3322
3323 /* Define this macro if the port needs extra instructions inserted
3324 for mode switching in an optimizing compilation. */
3325
3326 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3327
3328 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3329 initializer for an array of integers. Each initializer element N
3330 refers to an entity that needs mode switching, and specifies the
3331 number of different modes that might need to be set for this
3332 entity. The position of the initializer in the initializer -
3333 starting counting at zero - determines the integer that is used to
3334 refer to the mode-switched entity in question. */
3335
3336 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3337
3338 /* ENTITY is an integer specifying a mode-switched entity. If
3339 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3340 return an integer value not larger than the corresponding element
3341 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3342 must be switched into prior to the execution of INSN. */
3343
3344 #define MODE_NEEDED(ENTITY, I) \
3345 (GET_CODE (I) == CALL_INSN \
3346 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3347 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3348 ? FP_CW_UNINITIALIZED \
3349 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3350 ? FP_CW_ANY \
3351 : FP_CW_STORED)
3352
3353 /* This macro specifies the order in which modes for ENTITY are
3354 processed. 0 is the highest priority. */
3355
3356 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3357
3358 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3359 is the set of hard registers live at the point where the insn(s)
3360 are to be inserted. */
3361
3362 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3363 ((MODE) == FP_CW_STORED \
3364 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3365 assign_386_stack_local (HImode, 2)), 0\
3366 : 0)
3367 \f
3368 /* Avoid renaming of stack registers, as doing so in combination with
3369 scheduling just increases amount of live registers at time and in
3370 the turn amount of fxch instructions needed.
3371
3372 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3373
3374 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3375 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3376
3377 \f
3378 /*
3379 Local variables:
3380 version-control: t
3381 End:
3382 */
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