| blob | f2e6957169deae4f2ea0887518289ba523a787db |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
89 #ifndef CHECK_STACK_LIMIT
90 #define CHECK_STACK_LIMIT (-1)
91 #endif
93 /* Return index of given mode in mult and division cost tables. */
94 #define MODE_INDEX(mode) \
95 ((mode) == QImode ? 0 \
96 : (mode) == HImode ? 1 \
97 : (mode) == SImode ? 2 \
98 : (mode) == DImode ? 3 \
99 : 4)
101 /* Processor costs (relative to an add) */
102 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
103 #define COSTS_N_BYTES(N) ((N) * 2)
105 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
114 const
137 in QImode, HImode and SImode.
138 Relative to reg-reg move (2). */
142 in SFmode, DFmode and XFmode */
144 in SFmode, DFmode and XFmode */
147 in SImode and DImode */
149 in SImode and DImode */
152 in SImode, DImode and TImode */
154 in SImode, DImode and TImode */
167 ix86_size_memcpy,
168 ix86_size_memset,
180 };
182 /* Processor costs (relative to an add) */
185 DUMMY_STRINGOP_ALGS};
188 DUMMY_STRINGOP_ALGS};
190 static const
213 in QImode, HImode and SImode.
214 Relative to reg-reg move (2). */
218 in SFmode, DFmode and XFmode */
220 in SFmode, DFmode and XFmode */
223 in SImode and DImode */
225 in SImode and DImode */
228 in SImode, DImode and TImode */
230 in SImode, DImode and TImode */
243 i386_memcpy,
244 i386_memset,
256 };
260 DUMMY_STRINGOP_ALGS};
263 DUMMY_STRINGOP_ALGS};
265 static const
288 in QImode, HImode and SImode.
289 Relative to reg-reg move (2). */
293 in SFmode, DFmode and XFmode */
295 in SFmode, DFmode and XFmode */
298 in SImode and DImode */
300 in SImode and DImode */
303 in SImode, DImode and TImode */
305 in SImode, DImode and TImode */
308 shared for code and data, so 4kB is
309 not really precise. */
320 i486_memcpy,
321 i486_memset,
333 };
337 DUMMY_STRINGOP_ALGS};
340 DUMMY_STRINGOP_ALGS};
342 static const
365 in QImode, HImode and SImode.
366 Relative to reg-reg move (2). */
370 in SFmode, DFmode and XFmode */
372 in SFmode, DFmode and XFmode */
375 in SImode and DImode */
377 in SImode and DImode */
380 in SImode, DImode and TImode */
382 in SImode, DImode and TImode */
395 pentium_memcpy,
396 pentium_memset,
408 };
410 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
411 (we ensure the alignment). For small blocks inline loop is still a
412 noticeable win, for bigger blocks either rep movsl or rep movsb is
413 way to go. Rep movsb has apparently more expensive startup time in CPU,
414 but after 4K the difference is down in the noise. */
419 DUMMY_STRINGOP_ALGS};
424 DUMMY_STRINGOP_ALGS};
425 static const
448 in QImode, HImode and SImode.
449 Relative to reg-reg move (2). */
453 in SFmode, DFmode and XFmode */
455 in SFmode, DFmode and XFmode */
458 in SImode and DImode */
460 in SImode and DImode */
463 in SImode, DImode and TImode */
465 in SImode, DImode and TImode */
478 pentiumpro_memcpy,
479 pentiumpro_memset,
491 };
495 DUMMY_STRINGOP_ALGS};
498 DUMMY_STRINGOP_ALGS};
499 static const
522 in QImode, HImode and SImode.
523 Relative to reg-reg move (2). */
527 in SFmode, DFmode and XFmode */
529 in SFmode, DFmode and XFmode */
533 in SImode and DImode */
535 in SImode and DImode */
538 in SImode, DImode and TImode */
540 in SImode, DImode and TImode */
553 geode_memcpy,
554 geode_memset,
566 };
570 DUMMY_STRINGOP_ALGS};
573 DUMMY_STRINGOP_ALGS};
574 static const
597 in QImode, HImode and SImode.
598 Relative to reg-reg move (2). */
602 in SFmode, DFmode and XFmode */
604 in SFmode, DFmode and XFmode */
607 in SImode and DImode */
609 in SImode and DImode */
612 in SImode, DImode and TImode */
614 in SImode, DImode and TImode */
618 have integrated l2 cache, but
619 optimizing for k6 is not important
620 enough to worry about that. */
630 k6_memcpy,
631 k6_memset,
643 };
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
650 DUMMY_STRINGOP_ALGS};
653 DUMMY_STRINGOP_ALGS};
654 static const
677 in QImode, HImode and SImode.
678 Relative to reg-reg move (2). */
682 in SFmode, DFmode and XFmode */
684 in SFmode, DFmode and XFmode */
687 in SImode and DImode */
689 in SImode and DImode */
692 in SImode, DImode and TImode */
694 in SImode, DImode and TImode */
707 athlon_memcpy,
708 athlon_memset,
720 };
722 /* K8 has optimized REP instruction for medium sized blocks, but for very
723 small blocks it is better to use loop. For large blocks, libcall can
724 do nontemporary accesses and beat inline considerably. */
735 static const
758 in QImode, HImode and SImode.
759 Relative to reg-reg move (2). */
763 in SFmode, DFmode and XFmode */
765 in SFmode, DFmode and XFmode */
768 in SImode and DImode */
770 in SImode and DImode */
773 in SImode, DImode and TImode */
775 in SImode, DImode and TImode */
780 /* New AMD processors never drop prefetches; if they cannot be performed
781 immediately, they are queued. We set number of simultaneous prefetches
782 to a large constant to reflect this (it probably is not a good idea not
783 to limit number of prefetches at all, as their execution also takes some
784 time). */
794 k8_memcpy,
795 k8_memset,
807 };
809 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
810 very small blocks it is better to use loop. For large blocks, libcall can
811 do nontemporary accesses and beat inline considerably. */
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
849 in SFmode, DFmode and XFmode */
851 in SFmode, DFmode and XFmode */
854 in SImode and DImode */
856 in SImode and DImode */
859 in SImode, DImode and TImode */
861 in SImode, DImode and TImode */
863 /* On K8:
864 MOVD reg64, xmmreg Double FSTORE 4
865 MOVD reg32, xmmreg Double FSTORE 4
866 On AMDFAM10:
867 MOVD reg64, xmmreg Double FADD 3
868 1/1 1/1
869 MOVD reg32, xmmreg Double FADD 3
870 1/1 1/1 */
874 /* New AMD processors never drop prefetches; if they cannot be performed
875 immediately, they are queued. We set number of simultaneous prefetches
876 to a large constant to reflect this (it probably is not a good idea not
877 to limit number of prefetches at all, as their execution also takes some
878 time). */
888 amdfam10_memcpy,
889 amdfam10_memset,
901 };
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
939 in QImode, HImode and SImode.
940 Relative to reg-reg move (2). */
944 in SFmode, DFmode and XFmode */
946 in SFmode, DFmode and XFmode */
949 in SImode and DImode */
951 in SImode and DImode */
954 in SImode, DImode and TImode */
956 in SImode, DImode and TImode */
958 /* On K8:
959 MOVD reg64, xmmreg Double FSTORE 4
960 MOVD reg32, xmmreg Double FSTORE 4
961 On AMDFAM10:
962 MOVD reg64, xmmreg Double FADD 3
963 1/1 1/1
964 MOVD reg32, xmmreg Double FADD 3
965 1/1 1/1 */
969 /* New AMD processors never drop prefetches; if they cannot be performed
970 immediately, they are queued. We set number of simultaneous prefetches
971 to a large constant to reflect this (it probably is not a good idea not
972 to limit number of prefetches at all, as their execution also takes some
973 time). */
983 bdver1_memcpy,
984 bdver1_memset,
996 };
998 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
999 very small blocks it is better to use loop. For large blocks, libcall
1000 can do nontemporary accesses and beat inline considerably. */
1035 in QImode, HImode and SImode.
1036 Relative to reg-reg move (2). */
1040 in SFmode, DFmode and XFmode */
1042 in SFmode, DFmode and XFmode */
1045 in SImode and DImode */
1047 in SImode and DImode */
1050 in SImode, DImode and TImode */
1052 in SImode, DImode and TImode */
1054 /* On K8:
1055 MOVD reg64, xmmreg Double FSTORE 4
1056 MOVD reg32, xmmreg Double FSTORE 4
1057 On AMDFAM10:
1058 MOVD reg64, xmmreg Double FADD 3
1059 1/1 1/1
1060 MOVD reg32, xmmreg Double FADD 3
1061 1/1 1/1 */
1065 /* New AMD processors never drop prefetches; if they cannot be performed
1066 immediately, they are queued. We set number of simultaneous prefetches
1067 to a large constant to reflect this (it probably is not a good idea not
1068 to limit number of prefetches at all, as their execution also takes some
1069 time). */
1079 bdver2_memcpy,
1080 bdver2_memset,
1092 };
1095 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1096 very small blocks it is better to use loop. For large blocks, libcall
1097 can do nontemporary accesses and beat inline considerably. */
1130 in QImode, HImode and SImode.
1131 Relative to reg-reg move (2). */
1135 in SFmode, DFmode and XFmode */
1137 in SFmode, DFmode and XFmode */
1140 in SImode and DImode */
1142 in SImode and DImode */
1145 in SImode, DImode and TImode */
1147 in SImode, DImode and TImode */
1152 /* New AMD processors never drop prefetches; if they cannot be performed
1153 immediately, they are queued. We set number of simultaneous prefetches
1154 to a large constant to reflect this (it probably is not a good idea not
1155 to limit number of prefetches at all, as their execution also takes some
1156 time). */
1166 bdver3_memcpy,
1167 bdver3_memset,
1179 };
1181 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1182 very small blocks it is better to use loop. For large blocks, libcall
1183 can do nontemporary accesses and beat inline considerably. */
1216 in QImode, HImode and SImode.
1217 Relative to reg-reg move (2). */
1221 in SFmode, DFmode and XFmode */
1223 in SFmode, DFmode and XFmode */
1226 in SImode and DImode */
1228 in SImode and DImode */
1231 in SImode, DImode and TImode */
1233 in SImode, DImode and TImode */
1238 /* New AMD processors never drop prefetches; if they cannot be performed
1239 immediately, they are queued. We set number of simultaneous prefetches
1240 to a large constant to reflect this (it probably is not a good idea not
1241 to limit number of prefetches at all, as their execution also takes some
1242 time). */
1252 bdver4_memcpy,
1253 bdver4_memset,
1265 };
1267 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1268 very small blocks it is better to use loop. For large blocks, libcall can
1269 do nontemporary accesses and beat inline considerably. */
1302 in QImode, HImode and SImode.
1303 Relative to reg-reg move (2). */
1307 in SFmode, DFmode and XFmode */
1309 in SFmode, DFmode and XFmode */
1312 in SImode and DImode */
1314 in SImode and DImode */
1317 in SImode, DImode and TImode */
1319 in SImode, DImode and TImode */
1321 /* On K8:
1322 MOVD reg64, xmmreg Double FSTORE 4
1323 MOVD reg32, xmmreg Double FSTORE 4
1324 On AMDFAM10:
1325 MOVD reg64, xmmreg Double FADD 3
1326 1/1 1/1
1327 MOVD reg32, xmmreg Double FADD 3
1328 1/1 1/1 */
1341 btver1_memcpy,
1342 btver1_memset,
1354 };
1388 in QImode, HImode and SImode.
1389 Relative to reg-reg move (2). */
1393 in SFmode, DFmode and XFmode */
1395 in SFmode, DFmode and XFmode */
1398 in SImode and DImode */
1400 in SImode and DImode */
1403 in SImode, DImode and TImode */
1405 in SImode, DImode and TImode */
1407 /* On K8:
1408 MOVD reg64, xmmreg Double FSTORE 4
1409 MOVD reg32, xmmreg Double FSTORE 4
1410 On AMDFAM10:
1411 MOVD reg64, xmmreg Double FADD 3
1412 1/1 1/1
1413 MOVD reg32, xmmreg Double FADD 3
1414 1/1 1/1 */
1426 btver2_memcpy,
1427 btver2_memset,
1439 };
1443 DUMMY_STRINGOP_ALGS};
1447 DUMMY_STRINGOP_ALGS};
1449 static const
1472 in QImode, HImode and SImode.
1473 Relative to reg-reg move (2). */
1477 in SFmode, DFmode and XFmode */
1479 in SFmode, DFmode and XFmode */
1482 in SImode and DImode */
1484 in SImode and DImode */
1487 in SImode, DImode and TImode */
1489 in SImode, DImode and TImode */
1502 pentium4_memcpy,
1503 pentium4_memset,
1515 };
1528 static const
1551 in QImode, HImode and SImode.
1552 Relative to reg-reg move (2). */
1556 in SFmode, DFmode and XFmode */
1558 in SFmode, DFmode and XFmode */
1561 in SImode and DImode */
1563 in SImode and DImode */
1566 in SImode, DImode and TImode */
1568 in SImode, DImode and TImode */
1581 nocona_memcpy,
1582 nocona_memset,
1594 };
1605 static const
1628 in QImode, HImode and SImode.
1629 Relative to reg-reg move (2). */
1633 in SFmode, DFmode and XFmode */
1635 in SFmode, DFmode and XFmode */
1638 in SImode and DImode */
1640 in SImode and DImode */
1643 in SImode, DImode and TImode */
1645 in SImode, DImode and TImode */
1658 atom_memcpy,
1659 atom_memset,
1671 };
1682 static const
1705 in QImode, HImode and SImode.
1706 Relative to reg-reg move (2). */
1710 in SFmode, DFmode and XFmode */
1712 in SFmode, DFmode and XFmode */
1715 in SImode and DImode */
1717 in SImode and DImode */
1720 in SImode, DImode and TImode */
1722 in SImode, DImode and TImode */
1735 slm_memcpy,
1736 slm_memset,
1748 };
1759 static const
1782 in QImode, HImode and SImode.
1783 Relative to reg-reg move (2). */
1787 in SFmode, DFmode and XFmode */
1789 in SFmode, DFmode and XFmode */
1792 in SImode and DImode */
1794 in SImode and DImode */
1797 in SImode, DImode and TImode */
1799 in SImode, DImode and TImode */
1812 intel_memcpy,
1813 intel_memset,
1825 };
1827 /* Generic should produce code tuned for Core-i7 (and newer chips)
1828 and btver1 (and newer chips). */
1840 static const
1843 /* On all chips taken into consideration lea is 2 cycles and more. With
1844 this cost however our current implementation of synth_mult results in
1845 use of unnecessary temporary registers causing regression on several
1846 SPECfp benchmarks. */
1867 in QImode, HImode and SImode.
1868 Relative to reg-reg move (2). */
1872 in SFmode, DFmode and XFmode */
1874 in SFmode, DFmode and XFmode */
1877 in SImode and DImode */
1879 in SImode and DImode */
1882 in SImode, DImode and TImode */
1884 in SImode, DImode and TImode */
1890 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1891 value is increased to perhaps more appropriate value of 5. */
1899 generic_memcpy,
1900 generic_memset,
1912 };
1914 /* core_cost should produce code tuned for Core familly of CPUs. */
1927 static const
1930 /* On all chips taken into consideration lea is 2 cycles and more. With
1931 this cost however our current implementation of synth_mult results in
1932 use of unnecessary temporary registers causing regression on several
1933 SPECfp benchmarks. */
1954 in QImode, HImode and SImode.
1955 Relative to reg-reg move (2). */
1959 in SFmode, DFmode and XFmode */
1961 in SFmode, DFmode and XFmode */
1964 in SImode and DImode */
1966 in SImode and DImode */
1969 in SImode, DImode and TImode */
1971 in SImode, DImode and TImode */
1977 /* FIXME perhaps more appropriate value is 5. */
1985 core_memcpy,
1986 core_memset,
1998 };
2001 /* Set by -mtune. */
2004 /* Set by -mtune or -Os. */
2007 /* Processor feature/optimization bitmasks. */
2008 #define m_386 (1<<PROCESSOR_I386)
2009 #define m_486 (1<<PROCESSOR_I486)
2010 #define m_PENT (1<<PROCESSOR_PENTIUM)
2011 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2012 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2013 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2014 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2015 #define m_CORE2 (1<<PROCESSOR_CORE2)
2016 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2017 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2018 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2019 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2020 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2021 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2022 #define m_INTEL (1<<PROCESSOR_INTEL)
2024 #define m_GEODE (1<<PROCESSOR_GEODE)
2025 #define m_K6 (1<<PROCESSOR_K6)
2026 #define m_K6_GEODE (m_K6 | m_GEODE)
2027 #define m_K8 (1<<PROCESSOR_K8)
2028 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2029 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2030 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2031 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2032 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2033 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2034 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2035 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2036 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2037 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2038 #define m_BTVER (m_BTVER1 | m_BTVER2)
2039 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2041 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2044 #undef DEF_TUNE
2045 #define DEF_TUNE(tune, name, selector) name,
2047 #undef DEF_TUNE
2048 };
2050 /* Feature tests against the various tunings. */
2053 /* Feature tests against the various tunings used to create ix86_tune_features
2054 based on the processor mask. */
2056 #undef DEF_TUNE
2057 #define DEF_TUNE(tune, name, selector) selector,
2059 #undef DEF_TUNE
2060 };
2062 /* Feature tests against the various architecture variations. */
2065 /* Feature tests against the various architecture variations, used to create
2066 ix86_arch_features based on the processor mask. */
2068 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2071 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2074 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2077 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2080 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2082 };
2084 /* In case the average insn count for single function invocation is
2085 lower than this constant, emit fast (but longer) prologue and
2086 epilogue code. */
2087 #define FAST_PROLOGUE_INSN_COUNT 20
2089 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2094 /* Array of the smallest class containing reg number REGNO, indexed by
2095 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2098 {
2099 /* ax, dx, cx, bx */
2101 /* si, di, bp, sp */
2103 /* FP registers */
2106 /* arg pointer */
2107 NON_Q_REGS,
2108 /* flags, fpsr, fpcr, frame */
2110 /* SSE registers */
2113 /* MMX registers */
2116 /* REX registers */
2119 /* SSE REX registers */
2122 /* AVX-512 SSE registers */
2127 /* Mask registers. */
2130 };
2132 /* The "default" register map used in 32bit mode. */
2135 {
2146 };
2148 /* The "default" register map used in 64bit mode. */
2151 {
2162 };
2164 /* Define the register numbers to be used in Dwarf debugging information.
2165 The SVR4 reference port C compiler uses the following register numbers
2166 in its Dwarf output code:
2167 0 for %eax (gcc regno = 0)
2168 1 for %ecx (gcc regno = 2)
2169 2 for %edx (gcc regno = 1)
2170 3 for %ebx (gcc regno = 3)
2171 4 for %esp (gcc regno = 7)
2172 5 for %ebp (gcc regno = 6)
2173 6 for %esi (gcc regno = 4)
2174 7 for %edi (gcc regno = 5)
2175 The following three DWARF register numbers are never generated by
2176 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2177 believes these numbers have these meanings.
2178 8 for %eip (no gcc equivalent)
2179 9 for %eflags (gcc regno = 17)
2180 10 for %trapno (no gcc equivalent)
2181 It is not at all clear how we should number the FP stack registers
2182 for the x86 architecture. If the version of SDB on x86/svr4 were
2183 a bit less brain dead with respect to floating-point then we would
2184 have a precedent to follow with respect to DWARF register numbers
2185 for x86 FP registers, but the SDB on x86/svr4 is so completely
2186 broken with respect to FP registers that it is hardly worth thinking
2187 of it as something to strive for compatibility with.
2188 The version of x86/svr4 SDB I have at the moment does (partially)
2189 seem to believe that DWARF register number 11 is associated with
2190 the x86 register %st(0), but that's about all. Higher DWARF
2191 register numbers don't seem to be associated with anything in
2192 particular, and even for DWARF regno 11, SDB only seems to under-
2193 stand that it should say that a variable lives in %st(0) (when
2194 asked via an `=' command) if we said it was in DWARF regno 11,
2195 but SDB still prints garbage when asked for the value of the
2196 variable in question (via a `/' command).
2197 (Also note that the labels SDB prints for various FP stack regs
2198 when doing an `x' command are all wrong.)
2199 Note that these problems generally don't affect the native SVR4
2200 C compiler because it doesn't allow the use of -O with -g and
2201 because when it is *not* optimizing, it allocates a memory
2202 location for each floating-point variable, and the memory
2203 location is what gets described in the DWARF AT_location
2204 attribute for the variable in question.
2205 Regardless of the severe mental illness of the x86/svr4 SDB, we
2206 do something sensible here and we use the following DWARF
2207 register numbers. Note that these are all stack-top-relative
2208 numbers.
2209 11 for %st(0) (gcc regno = 8)
2210 12 for %st(1) (gcc regno = 9)
2211 13 for %st(2) (gcc regno = 10)
2212 14 for %st(3) (gcc regno = 11)
2213 15 for %st(4) (gcc regno = 12)
2214 16 for %st(5) (gcc regno = 13)
2215 17 for %st(6) (gcc regno = 14)
2216 18 for %st(7) (gcc regno = 15)
2217 */
2219 {
2230 };
2232 /* Define parameter passing and return registers. */
2235 {
2237 };
2240 {
2242 };
2245 {
2247 };
2249 /* Additional registers that are clobbered by SYSV calls. */
2252 {
2257 };
2259 /* Define the structure for the machine field in struct function. */
2264 rtx rtl;
2266 };
2268 /* Structure describing stack frame layout.
2269 Stack grows downward:
2271 [arguments]
2272 <- ARG_POINTER
2273 saved pc
2275 saved static chain if ix86_static_chain_on_stack
2277 saved frame pointer if frame_pointer_needed
2278 <- HARD_FRAME_POINTER
2279 [saved regs]
2280 <- regs_save_offset
2281 [padding0]
2283 [saved SSE regs]
2284 <- sse_regs_save_offset
2285 [padding1] |
2286 | <- FRAME_POINTER
2287 [va_arg registers] |
2288 |
2289 [frame] |
2290 |
2291 [padding2] | = to_allocate
2292 <- STACK_POINTER
2293 */
2294 struct ix86_frame
2295 {
2302 /* The offsets relative to ARG_POINTER. */
2303 HOST_WIDE_INT frame_pointer_offset;
2304 HOST_WIDE_INT hard_frame_pointer_offset;
2305 HOST_WIDE_INT stack_pointer_offset;
2306 HOST_WIDE_INT hfp_save_offset;
2307 HOST_WIDE_INT reg_save_offset;
2308 HOST_WIDE_INT sse_reg_save_offset;
2310 /* When save_regs_using_mov is set, emit prologue using
2311 move instead of push instructions. */
2313 };
2315 /* Which cpu are we scheduling for. */
2318 /* Which cpu are we optimizing for. */
2321 /* Which instruction set architecture to use. */
2324 /* True if processor has SSE prefetch instruction. */
2327 /* -mstackrealign option */
2344 /* Preferred alignment for stack boundary in bits. */
2347 /* Alignment for incoming stack boundary in bits specified at
2348 command line. */
2351 /* Default alignment for incoming stack boundary in bits. */
2354 /* Alignment for incoming stack boundary in bits. */
2357 /* Calling abi specific va_list type nodes. */
2361 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2365 /* Fence to use after loop using movnt. */
2366 tree x86_mfence;
2368 /* Register class used for passing given 64bit part of the argument.
2369 These represent classes as documented by the PS ABI, with the exception
2370 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2371 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2373 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2374 whenever possible (upper half does contain padding). */
2375 enum x86_64_reg_class
2376 {
2377 X86_64_NO_CLASS,
2378 X86_64_INTEGER_CLASS,
2379 X86_64_INTEGERSI_CLASS,
2380 X86_64_SSE_CLASS,
2381 X86_64_SSESF_CLASS,
2382 X86_64_SSEDF_CLASS,
2383 X86_64_SSEUP_CLASS,
2384 X86_64_X87_CLASS,
2385 X86_64_X87UP_CLASS,
2386 X86_64_COMPLEX_X87_CLASS,
2387 X86_64_MEMORY_CLASS
2388 };
2390 #define MAX_CLASSES 8
2392 /* Table of constants used by fldpi, fldln2, etc.... */
2396 \f
2401 const_tree);
2413 enum ix86_function_specific_strings
2414 {
2415 IX86_FUNCTION_SPECIFIC_ARCH,
2416 IX86_FUNCTION_SPECIFIC_TUNE,
2417 IX86_FUNCTION_SPECIFIC_MAX
2418 };
2439 \f
2440 #ifndef SUBTARGET32_DEFAULT_CPU
2442 #endif
2444 /* Whether -mtune= or -march= were specified */
2448 /* Vectorization library interface and handlers. */
2454 /* Processor target table, indexed by processor number */
2455 struct ptt
2456 {
2464 };
2466 /* This table must be in sync with enum processor_type in i386.h. */
2468 {
2494 };
2495 \f
2496 static bool
2498 {
2500 }
2502 static unsigned int
2504 {
2507 /* vzeroupper instructions are inserted immediately after reload to
2508 account for possible spills from 256bit registers. The pass
2509 reuses mode switching infrastructure by re-running mode insertion
2510 pass, so disable entities that have already been processed. */
2516 /* Call optimize_mode_switching. */
2519 }
2524 {
2536 };
2539 {
2543 {}
2545 /* opt_pass methods: */
2553 rtl_opt_pass *
2555 {
2557 }
2559 /* Return true if a red-zone is in use. */
2563 {
2565 }
2566 \f
2567 /* Return a string that documents the current -m options. The caller is
2568 responsible for freeing the string. */
2574 {
2575 struct ix86_target_opts
2576 {
2579 };
2581 /* This table is ordered so that options like -msse4.2 that imply
2582 preceding options while match those first. */
2584 {
2626 };
2628 /* Flag options. */
2630 {
2659 };
2676 /* Add -march= option. */
2678 {
2681 }
2683 /* Add -mtune= option. */
2685 {
2688 }
2690 /* Add -m32/-m64/-mx32. */
2692 {
2695 else
2697 isa &= ~ (OPTION_MASK_ISA_64BIT
2698 | OPTION_MASK_ABI_64
2700 }
2701 else
2705 /* Pick out the options in isa options. */
2707 {
2709 {
2712 }
2713 }
2716 {
2719 isa);
2720 }
2722 /* Add flag options. */
2724 {
2726 {
2729 }
2730 }
2733 {
2736 }
2738 /* Add -fpmath= option. */
2740 {
2743 {
2758 }
2759 }
2761 /* Any options? */
2767 /* Size the string. */
2771 {
2776 }
2778 /* Build the string. */
2783 {
2790 {
2792 line_len++;
2795 {
2799 }
2800 }
2804 {
2808 }
2809 }
2815 }
2817 /* Return true, if profiling code should be emitted before
2818 prologue. Otherwise it returns false.
2819 Note: For x86 with "hotfix" it is sorried. */
2820 static bool
2822 {
2824 }
2826 /* Function that is callable from the debugger to print the current
2827 options. */
2828 void ATTRIBUTE_UNUSED
2830 {
2836 {
2839 }
2840 else
2844 }
2847 #define DEF_ENUM
2848 #define DEF_ALG(alg, name) #name,
2850 #undef DEF_ENUM
2851 #undef DEF_ALG
2852 };
2854 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2855 The string is of the following form (or comma separated list of it):
2857 strategy_alg:max_size:[align|noalign]
2859 where the full size range for the strategy is either [0, max_size] or
2860 [min_size, max_size], in which min_size is the max_size + 1 of the
2861 preceding range. The last size range must have max_size == -1.
2863 Examples:
2865 1.
2866 -mmemcpy-strategy=libcall:-1:noalign
2868 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2871 2.
2872 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2874 This is to tell the compiler to use the following strategy for memset
2875 1) when the expected size is between [1, 16], use rep_8byte strategy;
2876 2) when the size is between [17, 2048], use vector_loop;
2877 3) when the size is > 2048, use libcall. */
2879 struct stringop_size_range
2880 {
2882 stringop_alg alg;
2884 };
2886 static void
2888 {
2896 else
2901 do
2902 {
2912 {
2916 }
2919 {
2923 }
2930 {
2932 alg_name,
2935 }
2943 else
2944 {
2948 }
2949 n++;
2951 }
2955 {
2960 }
2963 {
2967 }
2969 /* Now override the default algs array. */
2971 {
2977 }
2978 }
2980 \f
2981 /* parse -mtune-ctrl= option. When DUMP is true,
2982 print the features that are explicitly set. */
2984 static void
2986 {
2994 do
2995 {
3002 {
3003 curr_feature_string++;
3005 }
3007 {
3009 {
3015 }
3016 }
3021 }
3024 }
3026 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3027 processor type. */
3029 static void
3031 {
3036 {
3039 else
3041 }
3044 {
3049 }
3052 }
3055 /* Override various settings based on options. If MAIN_ARGS_P, the
3056 options are from the command line, otherwise they are from
3057 attributes. */
3059 static void
3063 {
3071 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3072 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3073 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3074 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3075 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3076 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3077 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3078 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3079 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3080 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3081 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3082 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3083 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3084 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3085 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3086 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3087 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3088 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3089 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3090 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3091 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3092 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3093 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3094 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3095 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3096 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3097 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3098 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3099 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3100 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3101 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3102 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3103 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3104 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3105 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3106 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3107 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3108 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3109 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3110 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3111 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3112 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3113 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3114 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3115 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3116 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3118 #define PTA_CORE2 \
3119 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3120 | PTA_CX16 | PTA_FXSR)
3121 #define PTA_NEHALEM \
3122 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3123 #define PTA_WESTMERE \
3124 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3125 #define PTA_SANDYBRIDGE \
3126 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3127 #define PTA_IVYBRIDGE \
3128 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3129 #define PTA_HASWELL \
3130 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3131 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE)
3132 #define PTA_BROADWELL \
3133 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3134 #define PTA_BONNELL \
3135 (PTA_CORE2 | PTA_MOVBE)
3136 #define PTA_SILVERMONT \
3137 (PTA_WESTMERE | PTA_MOVBE)
3139 /* if this reaches 64, need to widen struct pta flags below */
3141 static struct pta
3142 {
3147 }
3149 {
3183 PTA_SANDYBRIDGE},
3185 PTA_SANDYBRIDGE},
3187 PTA_IVYBRIDGE},
3189 PTA_IVYBRIDGE},
3279 PTA_64BIT
3281 };
3283 /* -mrecip options. */
3284 static struct
3285 {
3288 }
3290 {
3297 };
3301 /* Set up prefix/suffix so the error messages refer to either the command
3302 line argument, or the attribute(target). */
3304 {
3308 }
3309 else
3310 {
3314 }
3316 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3317 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3320 #ifdef TARGET_BI_ARCH
3321 else
3322 {
3323 #if TARGET_BI_ARCH == 1
3324 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3325 is on and OPTION_MASK_ABI_X32 is off. We turn off
3326 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3327 -mx32. */
3330 #else
3331 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3332 on and OPTION_MASK_ABI_64 is off. We turn off
3333 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3334 -m64. */
3337 #endif
3338 }
3339 #endif
3342 {
3343 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3344 OPTION_MASK_ABI_64 for TARGET_X32. */
3347 }
3350 | OPTION_MASK_ABI_X32
3353 {
3354 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3355 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3358 }
3360 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3361 SUBTARGET_OVERRIDE_OPTIONS;
3362 #endif
3364 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3365 SUBSUBTARGET_OVERRIDE_OPTIONS;
3366 #endif
3368 /* -fPIC is the default for x86_64. */
3372 /* Need to check -mtune=generic first. */
3374 {
3375 /* As special support for cross compilers we read -mtune=native
3376 as -mtune=generic. With native compilers we won't see the
3377 -mtune=native, as it was changed by the driver. */
3379 {
3381 }
3386 }
3387 else
3388 {
3392 {
3393 opts->x_ix86_tune_string
3396 }
3398 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3399 or defaulted. We need to use a sensible tune option. */
3401 {
3403 }
3404 }
3408 {
3409 /* rep; movq isn't available in 32-bit code. */
3412 }
3415 opts->x_ix86_arch_string
3418 else
3422 {
3430 }
3431 else
3438 /* For targets using ms ABI enable ms-extensions, if not
3439 explicit turned off. For non-ms ABI we turn off this
3440 option. */
3445 {
3447 {
3491 {
3494 }
3502 }
3503 }
3504 else
3505 {
3506 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3507 use of rip-relative addressing. This eliminates fixups that
3508 would otherwise be needed if this object is to be placed in a
3509 DLL, and is essentially just as efficient as direct addressing. */
3515 else
3517 }
3519 {
3522 }
3530 {
3533 /* Default cpu tuning to the architecture. */
3678 }
3696 {
3700 {
3702 {
3704 {
3712 }
3713 else
3716 }
3717 }
3718 /* Intel CPUs have always interpreted SSE prefetch instructions as
3719 NOPs; so, we can enable SSE prefetch instructions even when
3720 -mtune (rather than -march) points us to a processor that has them.
3721 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3722 higher processors. */
3727 }
3735 #ifndef USE_IX86_FRAME_POINTER
3736 #define USE_IX86_FRAME_POINTER 0
3737 #endif
3739 #ifndef USE_X86_64_FRAME_POINTER
3740 #define USE_X86_64_FRAME_POINTER 0
3741 #endif
3743 /* Set the default values for switches whose default depends on TARGET_64BIT
3744 in case they weren't overwritten by command line options. */
3746 {
3754 opts->x_flag_unwind_tables
3758 }
3759 else
3760 {
3762 opts->x_flag_omit_frame_pointer
3768 }
3773 else
3776 /* Arrange to set up i386_stack_locals for all functions. */
3779 /* Validate -mregparm= value. */
3781 {
3785 {
3789 }
3790 }
3794 /* Default align_* from the processor table. */
3796 {
3799 }
3801 {
3804 }
3806 {
3808 }
3810 /* Provide default for -mbranch-cost= value. */
3815 {
3816 opts->x_target_flags
3819 /* Enable by default the SSE and MMX builtins. Do allow the user to
3820 explicitly disable any of these. In particular, disabling SSE and
3821 MMX for kernel code is extremely useful. */
3823 opts->x_ix86_isa_flags
3830 }
3831 else
3832 {
3833 opts->x_target_flags
3837 opts->x_ix86_isa_flags
3840 /* i386 ABI does not specify red zone. It still makes sense to use it
3841 when programmer takes care to stack from being destroyed. */
3844 }
3846 /* Keep nonleaf frame pointers. */
3852 /* If we're doing fast math, we don't care about comparison order
3853 wrt NaNs. This lets us use a shorter comparison sequence. */
3857 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3858 since the insns won't need emulation. */
3862 /* Likewise, if the target doesn't have a 387, or we've specified
3863 software floating point, don't use 387 inline intrinsics. */
3867 /* Turn on MMX builtins for -msse. */
3869 opts->x_ix86_isa_flags
3872 /* Enable SSE prefetch. */
3877 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3880 opts->x_ix86_isa_flags
3883 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3886 opts->x_ix86_isa_flags
3889 /* Enable lzcnt instruction for -mabm. */
3891 opts->x_ix86_isa_flags
3894 /* Validate -mpreferred-stack-boundary= value or default it to
3895 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3898 {
3905 {
3909 else
3912 }
3913 else
3914 ix86_preferred_stack_boundary
3916 }
3918 /* Set the default value for -mstackrealign. */
3924 /* Validate -mincoming-stack-boundary= value or default it to
3925 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3928 {
3935 else
3936 {
3937 ix86_user_incoming_stack_boundary
3939 ix86_incoming_stack_boundary
3941 }
3942 }
3944 /* Accept -msseregparm only if at least SSE support is enabled. */
3950 {
3952 {
3954 {
3957 }
3960 {
3963 }
3964 }
3965 }
3966 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3967 fpmath=387. The second is however default at many targets since the
3968 extra 80bit precision of temporaries is considered to be part of ABI.
3969 Overwrite the default at least for -ffast-math.
3970 TODO: -mfpmath=both seems to produce same performing code with bit
3971 smaller binaries. It is however not clear if register allocation is
3972 ready for this setting.
3973 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3974 codegen. We may switch to 387 with -ffast-math for size optimized
3975 functions. */
3979 else
3982 /* If the i387 is disabled, then do not return values in it. */
3986 /* Use external vectorized library in vectorizing intrinsics. */
3989 {
4000 }
4007 /* If stack probes are required, the space used for large function
4008 arguments on the stack must also be probed, so enable
4009 -maccumulate-outgoing-args so this happens in the prologue. */
4012 {
4017 }
4019 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4020 {
4026 }
4028 /* When scheduling description is not available, disable scheduler pass
4029 so it won't slow down the compilation and make x87 code slower. */
4050 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4052 && HAVE_prefetch
4057 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4058 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4063 {
4066 {
4068 ix86_gen_tls_local_dynamic_base_64
4070 }
4071 else
4072 {
4074 ix86_gen_tls_local_dynamic_base_64
4076 }
4077 }
4078 else
4082 {
4092 }
4093 else
4094 {
4104 }
4106 #ifdef USE_IX86_CLD
4107 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4110 #endif
4113 {
4118 }
4120 {
4124 }
4126 {
4127 #if defined(PROFILE_BEFORE_PROLOGUE)
4129 #else
4131 #endif
4132 }
4134 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4135 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4136 AVX unaligned load/store. */
4138 {
4148 /* Enable 128-bit AVX instruction generation
4149 for the auto-vectorizer. */
4153 }
4156 {
4163 {
4166 {
4168 q++;
4169 }
4170 else
4175 else
4176 {
4179 {
4182 }
4185 {
4189 }
4190 }
4195 else
4197 }
4198 }
4205 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4206 for 64-bit Bionic. */
4211 ? MASK_LONG_DOUBLE_128
4214 /* Only one of them can be active. */
4218 /* Save the initial options in case the user does function specific
4219 options. */
4221 target_option_default_node = target_option_current_node
4224 /* Handle stack protector */
4226 opts->x_ix86_stack_protector_guard
4229 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4231 {
4235 }
4238 {
4242 }
4243 }
4245 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4247 static void
4249 {
4251 static struct register_pass_info insert_vzeroupper_info
4254 };
4259 /* This needs to be done at start up. It's convenient to do it here. */
4261 }
4263 /* Update register usage after having seen the compiler flags. */
4265 static void
4267 {
4271 /* The PIC register, if it exists, is fixed. */
4276 /* For 32-bit targets, squash the REX registers. */
4278 {
4285 }
4287 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4295 {
4296 /* Set/reset conditionally defined registers from
4297 CALL_USED_REGISTERS initializer. */
4301 /* Calculate registers of CLOBBERED_REGS register set
4302 as call used registers from GENERAL_REGS register set. */
4306 }
4308 /* If MMX is disabled, squash the registers. */
4314 /* If SSE is disabled, squash the registers. */
4320 /* If the FPU is disabled, squash the registers. */
4326 /* If AVX512F is disabled, squash the registers. */
4328 {
4334 }
4335 }
4337 \f
4338 /* Save the current options */
4340 static void
4343 {
4378 /* The fields are char but the variables are not; make sure the
4379 values fit in the fields. */
4384 }
4386 /* Restore the current options */
4388 static void
4391 {
4397 /* We don't change -fPIC. */
4434 /* Recreate the arch feature tests if the arch changed */
4436 {
4441 }
4443 /* Recreate the tune optimization tests */
4446 }
4448 /* Print the current options */
4450 static void
4453 {
4471 {
4474 }
4475 }
4477 \f
4478 /* Inner function to process the attribute((target(...))), take an argument and
4479 set the current options from the argument. If we have a list, recursively go
4480 over the list. */
4482 static bool
4487 {
4491 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4492 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4493 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4494 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4495 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4497 enum ix86_opt_type
4498 {
4499 ix86_opt_unknown,
4500 ix86_opt_yes,
4501 ix86_opt_no,
4502 ix86_opt_str,
4503 ix86_opt_enum,
4504 ix86_opt_isa
4505 };
4507 static const struct
4508 {
4515 /* isa options */
4558 /* enum options */
4561 /* string options */
4565 /* flag options */
4567 OPT_mcld,
4568 MASK_CLD),
4571 OPT_mfancy_math_387,
4572 MASK_NO_FANCY_MATH_387),
4575 OPT_mieee_fp,
4576 MASK_IEEE_FP),
4579 OPT_minline_all_stringops,
4580 MASK_INLINE_ALL_STRINGOPS),
4583 OPT_minline_stringops_dynamically,
4584 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4587 OPT_mno_align_stringops,
4588 MASK_NO_ALIGN_STRINGOPS),
4591 OPT_mrecip,
4592 MASK_RECIP),
4594 };
4596 /* If this is a list, recurse to get the options. */
4598 {
4605 enum_opts_set))
4609 }
4612 {
4615 }
4617 /* Handle multiple arguments separated by commas. */
4621 {
4635 {
4639 }
4640 else
4641 {
4644 }
4646 /* Recognize no-xxx. */
4648 {
4652 }
4653 else
4656 /* Find the option. */
4660 {
4668 {
4673 }
4674 }
4676 /* Process the option. */
4678 {
4681 }
4684 {
4690 }
4693 {
4699 else
4701 }
4704 {
4706 {
4709 }
4710 else
4712 }
4715 {
4723 global_dc);
4724 else
4725 {
4728 }
4729 }
4731 else
4733 }
4736 }
4738 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4740 tree
4744 {
4759 /* Process each of the options on the chain. */
4764 /* If the changed options are different from the default, rerun
4765 ix86_option_override_internal, and then save the options away.
4766 The string options are are attribute options, and will be undone
4767 when we copy the save structure. */
4773 {
4774 /* If we are using the default tune= or arch=, undo the string assigned,
4775 and use the default. */
4786 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4791 {
4794 }
4796 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4799 /* Add any builtin functions with the new isa if any. */
4802 /* Save the current options unless we are validating options for
4803 #pragma. */
4810 /* Free up memory allocated to hold the strings */
4813 }
4816 }
4818 /* Hook to validate attribute((target("string"))). */
4820 static bool
4823 tree args,
4825 {
4830 /* attribute((target("default"))) does nothing, beyond
4831 affecting multi-versioning. */
4840 /* Get the optimization options of the current function. */
4846 /* Init func_options. */
4854 /* Initialize func_options to the default before its target options can
4855 be set. */
4868 {
4873 }
4876 }
4878 \f
4879 /* Hook to determine if one function can safely inline another. */
4881 static bool
4883 {
4888 /* If callee has no option attributes, then it is ok to inline. */
4892 /* If caller has no option attributes, but callee does then it is not ok to
4893 inline. */
4897 else
4898 {
4902 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4903 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4904 function. */
4909 /* See if we have the same non-isa options. */
4913 /* See if arch, tune, etc. are the same. */
4926 else
4928 }
4931 }
4933 \f
4934 /* Remember the last target of ix86_set_current_function. */
4937 /* Invalidate ix86_previous_fndecl cache. */
4938 void
4940 {
4942 }
4944 /* Establish appropriate back-end context for processing the function
4945 FNDECL. The argument might be NULL to indicate processing at top
4946 level, outside of any function scope. */
4947 static void
4949 {
4950 /* Only change the context if the function changes. This hook is called
4951 several times in the course of compiling a function, and we don't want to
4952 slow things down too much or call target_reinit when it isn't safe. */
4954 {
4955 tree old_tree = (ix86_previous_fndecl
4959 tree new_tree = (fndecl
4965 ;
4968 {
4973 else
4976 }
4979 {
4987 else
4990 }
4991 }
4992 }
4994 \f
4995 /* Return true if this goes in large data/bss. */
4997 static bool
4999 {
5003 /* Functions are never large data. */
5008 {
5014 }
5015 else
5016 {
5019 /* If this is an incomplete type with size 0, then we can't put it
5020 in data because it might be too big when completed. */
5023 }
5026 }
5028 /* Switch to the appropriate section for output of DECL.
5029 DECL is either a `VAR_DECL' node or a constant of some sort.
5030 RELOC indicates whether forming the initial value of DECL requires
5031 link-time relocations. */
5036 {
5039 {
5043 {
5077 /* We don't split these for medium model. Place them into
5078 default sections and hope for best. */
5080 }
5082 {
5083 /* We might get called with string constants, but get_named_section
5084 doesn't like them as they are not DECLs. Also, we need to set
5085 flags in that case. */
5089 }
5090 }
5092 }
5094 /* Select a set of attributes for section NAME based on the properties
5095 of DECL and whether or not RELOC indicates that DECL's initializer
5096 might contain runtime relocations. */
5098 static unsigned int ATTRIBUTE_UNUSED
5100 {
5114 }
5116 /* Build up a unique section name, expressed as a
5117 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5118 RELOC indicates whether the initial value of EXP requires
5119 link-time relocations. */
5121 static void ATTRIBUTE_UNUSED
5123 {
5126 {
5128 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5132 {
5156 /* We don't split these for medium model. Place them into
5157 default sections and hope for best. */
5159 }
5161 {
5168 /* If we're using one_only, then there needs to be a .gnu.linkonce
5169 prefix to the section name. */
5176 }
5177 }
5179 }
5181 #ifdef COMMON_ASM_OP
5182 /* This says how to output assembler code to declare an
5183 uninitialized external linkage data object.
5185 For medium model x86-64 we need to use .largecomm opcode for
5186 large objects. */
5187 void
5191 {
5195 else
5200 }
5201 #endif
5203 /* Utility function for targets to use in implementing
5204 ASM_OUTPUT_ALIGNED_BSS. */
5206 void
5210 {
5214 else
5217 #ifdef ASM_DECLARE_OBJECT_NAME
5220 #else
5221 /* Standard thing is just output label for the object. */
5225 }
5226 \f
5227 /* Decide whether we must probe the stack before any space allocation
5228 on this target. It's essentially TARGET_STACK_PROBE except when
5229 -fstack-check causes the stack to be already probed differently. */
5231 bool
5233 {
5234 /* Do not probe the stack twice if static stack checking is enabled. */
5239 }
5240 \f
5241 /* Decide whether we can make a sibling call to a function. DECL is the
5242 declaration of the function being targeted by the call and EXP is the
5243 CALL_EXPR representing the call. */
5245 static bool
5247 {
5251 /* If we are generating position-independent code, we cannot sibcall
5252 optimize any indirect call, or a direct call to a global function,
5253 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5255 && !TARGET_64BIT
5256 && flag_pic
5260 /* If we need to align the outgoing stack, then sibcalling would
5261 unalign the stack, which may break the called function. */
5267 {
5270 }
5271 else
5272 {
5273 /* We're looking at the CALL_EXPR, we need the type of the function. */
5278 }
5280 /* Check that the return value locations are the same. Like
5281 if we are returning floats on the 80387 register stack, we cannot
5282 make a sibcall from a function that doesn't return a float to a
5283 function that does or, conversely, from a function that does return
5284 a float to a function that doesn't; the necessary stack adjustment
5285 would not be executed. This is also the place we notice
5286 differences in the return value ABI. Note that it is ok for one
5287 of the functions to have void return type as long as the return
5288 value of the other is passed in a register. */
5293 {
5296 }
5298 ;
5303 {
5304 /* The SYSV ABI has more call-clobbered registers;
5305 disallow sibcalls from MS to SYSV. */
5309 }
5310 else
5311 {
5312 /* If this call is indirect, we'll need to be able to use a
5313 call-clobbered register for the address of the target function.
5314 Make sure that all such registers are not used for passing
5315 parameters. Note that DLLIMPORT functions are indirect. */
5318 {
5320 {
5321 /* ??? Need to count the actual number of registers to be used,
5322 not the possible number of registers. Fix later. */
5324 }
5325 }
5326 }
5328 /* Otherwise okay. That also includes certain types of indirect calls. */
5330 }
5332 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5333 and "sseregparm" calling convention attributes;
5334 arguments as in struct attribute_spec.handler. */
5336 static tree
5338 tree args,
5341 {
5346 {
5348 name);
5351 }
5353 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5355 {
5356 tree cst;
5359 {
5361 }
5364 {
5366 }
5370 {
5373 name);
5375 }
5377 {
5381 }
5384 }
5387 {
5388 /* Do not warn when emulating the MS ABI. */
5393 name);
5396 }
5398 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5400 {
5402 {
5404 }
5406 {
5408 }
5410 {
5412 }
5414 {
5416 }
5417 }
5419 /* Can combine stdcall with fastcall (redundant), regparm and
5420 sseregparm. */
5422 {
5424 {
5426 }
5428 {
5430 }
5432 {
5434 }
5435 }
5437 /* Can combine cdecl with regparm and sseregparm. */
5439 {
5441 {
5443 }
5445 {
5447 }
5449 {
5451 }
5452 }
5454 {
5457 name);
5459 {
5461 }
5463 {
5465 }
5467 {
5469 }
5470 }
5472 /* Can combine sseregparm with all attributes. */
5475 }
5477 /* The transactional memory builtins are implicitly regparm or fastcall
5478 depending on the ABI. Override the generic do-nothing attribute that
5479 these builtins were declared with, and replace it with one of the two
5480 attributes that we expect elsewhere. */
5482 static tree
5484 tree args ATTRIBUTE_UNUSED,
5486 {
5487 tree alt;
5489 /* In no case do we want to add the placeholder attribute. */
5492 /* The 64-bit ABI is unchanged for transactional memory. */
5496 /* ??? Is there a better way to validate 32-bit windows? We have
5497 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5500 else
5501 {
5504 }
5508 }
5510 /* This function determines from TYPE the calling-convention. */
5512 unsigned int
5514 {
5517 tree attrs;
5524 {
5534 /* Regparam isn't allowed for thiscall and fastcall. */
5536 {
5541 }
5545 }
5552 || is_stdarg
5558 }
5560 /* Return 0 if the attributes for two types are incompatible, 1 if they
5561 are compatible, and 2 if they are nearly compatible (which causes a
5562 warning to be generated). */
5564 static int
5566 {
5582 }
5583 \f
5584 /* Return the regparm value for a function with the indicated TYPE and DECL.
5585 DECL may be NULL when calling function indirectly
5586 or considering a libcall. */
5588 static int
5590 {
5591 tree attr;
5602 {
5605 {
5608 }
5609 }
5615 /* Use register calling convention for local functions when possible. */
5618 /* Caller and callee must agree on the calling convention, so
5619 checking here just optimize means that with
5620 __attribute__((optimize (...))) caller could use regparm convention
5621 and callee not, or vice versa. Instead look at whether the callee
5622 is optimized or not. */
5625 {
5626 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5629 {
5632 /* Make sure no regparm register is taken by a
5633 fixed register variable. */
5638 /* We don't want to use regparm(3) for nested functions as
5639 these use a static chain pointer in the third argument. */
5643 /* In 32-bit mode save a register for the split stack. */
5647 /* Each fixed register usage increases register pressure,
5648 so less registers should be used for argument passing.
5649 This functionality can be overriden by an explicit
5650 regparm value. */
5653 globals++;
5655 local_regparm
5660 }
5661 }
5664 }
5666 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5667 DFmode (2) arguments in SSE registers for a function with the
5668 indicated TYPE and DECL. DECL may be NULL when calling function
5669 indirectly or considering a libcall. Otherwise return 0. */
5671 static int
5673 {
5676 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5677 by the sseregparm attribute. */
5680 {
5682 {
5684 {
5688 else
5691 }
5693 }
5696 }
5698 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5699 (and DFmode for SSE2) arguments in SSE registers. */
5702 {
5703 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5707 }
5710 }
5712 /* Return true if EAX is live at the start of the function. Used by
5713 ix86_expand_prologue to determine if we need special help before
5714 calling allocate_stack_worker. */
5716 static bool
5718 {
5719 /* Cheat. Don't bother working forward from ix86_function_regparm
5720 to the function type to whether an actual argument is located in
5721 eax. Instead just look at cfg info, which is still close enough
5722 to correct at this point. This gives false positives for broken
5723 functions that might use uninitialized data that happens to be
5724 allocated in eax, but who cares? */
5726 }
5728 static bool
5730 {
5731 tree attr;
5734 {
5740 /* For 32-bit MS-ABI the default is to keep aggregate
5741 return pointer. */
5744 }
5746 }
5748 /* Value is the number of bytes of arguments automatically
5749 popped when returning from a subroutine call.
5750 FUNDECL is the declaration node of the function (as a tree),
5751 FUNTYPE is the data type of the function (as a tree),
5752 or for a library call it is an identifier node for the subroutine name.
5753 SIZE is the number of bytes of arguments passed on the stack.
5755 On the 80386, the RTD insn may be used to pop them if the number
5756 of args is fixed, but if the number is variable then the caller
5757 must pop them all. RTD can't be used for library calls now
5758 because the library is compiled with the Unix compiler.
5759 Use of RTD is a selectable option, since it is incompatible with
5760 standard Unix calling sequences. If the option is not selected,
5761 the caller must always pop the args.
5763 The attribute stdcall is equivalent to RTD on a per module basis. */
5765 static int
5767 {
5770 /* None of the 64-bit ABIs pop arguments. */
5781 /* Lose any fake structure return argument if it is passed on the stack. */
5784 {
5788 }
5791 }
5793 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5795 static bool
5797 {
5798 /* Check operand constraints in case hard registers were propagated
5799 into insn pattern. This check prevents combine pass from
5800 generating insn patterns with invalid hard register operands.
5801 These invalid insns can eventually confuse reload to error out
5802 with a spill failure. See also PRs 46829 and 46843. */
5804 {
5811 {
5819 /* For pre-AVX disallow unaligned loads/stores where the
5820 instructions don't support it. */
5824 {
5828 }
5830 /* A unary operator may be accepted by the predicate, but it
5831 is irrelevant for matching constraints. */
5836 {
5844 }
5851 /* Operand has no constraints, anything is OK. */
5855 {
5858 && operands_match_p
5862 {
5865 }
5866 }
5870 }
5871 }
5874 }
5875 \f
5876 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5878 static unsigned HOST_WIDE_INT
5880 {
5884 }
5885 \f
5886 /* Argument support functions. */
5888 /* Return true when register may be used to pass function parameters. */
5889 bool
5891 {
5896 {
5900 else
5906 }
5912 /* TODO: The function should depend on current function ABI but
5913 builtins.c would need updating then. Therefore we use the
5914 default ABI. */
5916 /* RAX is used as hidden argument to va_arg functions. */
5922 else
5929 }
5931 /* Return if we do not know how to pass TYPE solely in registers. */
5933 static bool
5935 {
5939 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5940 The layout_type routine is crafty and tries to trick us into passing
5941 currently unsupported vector types on the stack by using TImode. */
5944 }
5946 /* It returns the size, in bytes, of the area reserved for arguments passed
5947 in registers for the function represented by fndecl dependent to the used
5948 abi format. */
5949 int
5951 {
5955 else
5960 }
5962 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5963 call abi used. */
5964 enum calling_abi
5966 {
5968 {
5971 {
5974 }
5978 }
5980 }
5982 /* We add this as a workaround in order to use libc_has_function
5983 hook in i386.md. */
5984 bool
5986 {
5988 }
5990 static bool
5992 {
5994 {
5998 else
6000 }
6002 }
6004 static enum calling_abi
6006 {
6010 }
6012 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6013 call abi used. */
6014 enum calling_abi
6016 {
6020 }
6022 /* Write the extra assembler code needed to declare a function properly. */
6024 void
6026 tree decl)
6027 {
6031 {
6037 }
6039 #ifdef SUBTARGET_ASM_UNWIND_INIT
6041 #endif
6045 /* Output magic byte marker, if hot-patch attribute is set. */
6047 {
6049 {
6050 /* leaq [%rsp + 0], %rsp */
6053 }
6054 else
6055 {
6056 /* movl.s %edi, %edi
6057 push %ebp
6058 movl.s %esp, %ebp */
6061 }
6062 }
6063 }
6065 /* regclass.c */
6068 /* Implementation of call abi switching target hook. Specific to FNDECL
6069 the specific call register sets are set. See also
6070 ix86_conditional_register_usage for more details. */
6071 void
6073 {
6076 else
6078 }
6080 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6081 expensive re-initialization of init_regs each time we switch function context
6082 since this is needed only during RTL expansion. */
6083 static void
6085 {
6089 }
6091 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6092 for a call to a function whose data type is FNTYPE.
6093 For a library call, FNTYPE is 0. */
6095 void
6099 tree fndecl,
6101 {
6107 {
6110 }
6111 else
6112 {
6115 }
6119 /* Set up the number of registers to use for passing arguments. */
6122 {
6124 ? X86_64_REGPARM_MAX
6126 }
6128 {
6131 {
6133 ? X86_64_SSE_REGPARM_MAX
6135 }
6136 }
6144 /* Because type might mismatch in between caller and callee, we need to
6145 use actual type of function for local calls.
6146 FIXME: cgraph_analyze can be told to actually record if function uses
6147 va_start so for local functions maybe_vaarg can be made aggressive
6148 helping K&R code.
6149 FIXME: once typesytem is fixed, we won't need this code anymore. */
6157 {
6158 /* If there are variable arguments, then we won't pass anything
6159 in registers in 32-bit mode. */
6161 {
6170 }
6172 /* Use ecx and edx registers if function has fastcall attribute,
6173 else look for regparm information. */
6175 {
6178 {
6181 }
6183 {
6186 }
6187 else
6189 }
6191 /* Set up the number of SSE registers used for passing SFmode
6192 and DFmode arguments. Warn for mismatching ABI. */
6194 }
6195 }
6197 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6198 But in the case of vector types, it is some vector mode.
6200 When we have only some of our vector isa extensions enabled, then there
6201 are some modes for which vector_mode_supported_p is false. For these
6202 modes, the generic vector support in gcc will choose some non-vector mode
6203 in order to implement the type. By computing the natural mode, we'll
6204 select the proper ABI location for the operand and not depend on whatever
6205 the middle-end decides to do with these vector types.
6207 The midde-end can't deal with the vector types > 16 bytes. In this
6208 case, we return the original mode and warn ABI change if CUM isn't
6209 NULL.
6211 If INT_RETURN is true, warn ABI change if the vector mode isn't
6212 available for function return value. */
6214 static enum machine_mode
6217 {
6221 {
6224 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6226 {
6231 else
6234 /* Get the mode which has this inner mode and number of units. */
6238 {
6240 {
6245 {
6249 }
6251 {
6255 }
6258 }
6260 {
6265 {
6269 }
6271 {
6275 }
6278 }
6281 {
6286 {
6290 }
6292 {
6296 }
6297 }
6299 {
6304 {
6308 }
6310 {
6314 }
6315 }
6317 }
6320 }
6321 }
6324 }
6326 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6327 this may not agree with the mode that the type system has chosen for the
6328 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6329 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6331 static rtx
6334 {
6335 rtx tmp;
6339 else
6340 {
6344 }
6347 }
6349 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6350 of this code is to classify each 8bytes of incoming argument by the register
6351 class and assign registers accordingly. */
6353 /* Return the union class of CLASS1 and CLASS2.
6354 See the x86-64 PS ABI for details. */
6356 static enum x86_64_reg_class
6358 {
6359 /* Rule #1: If both classes are equal, this is the resulting class. */
6363 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6364 the other class. */
6370 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6374 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6382 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6383 MEMORY is used. */
6392 /* Rule #6: Otherwise class SSE is used. */
6394 }
6396 /* Classify the argument of type TYPE and mode MODE.
6397 CLASSES will be filled by the register class used to pass each word
6398 of the operand. The number of words is returned. In case the parameter
6399 should be passed in memory, 0 is returned. As a special case for zero
6400 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6402 BIT_OFFSET is used internally for handling records and specifies offset
6403 of the offset in bits modulo 512 to avoid overflow cases.
6405 See the x86-64 PS ABI for details.
6406 */
6408 static int
6411 {
6412 HOST_WIDE_INT bytes =
6414 int words
6417 /* Variable sized entities are always passed/returned in memory. */
6426 {
6428 tree field;
6431 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6438 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6439 signalize memory class, so handle it as special case. */
6441 {
6444 }
6446 /* Classify each field of record and merge classes. */
6448 {
6450 /* And now merge the fields of structure. */
6452 {
6454 {
6460 /* Bitfields are always classified as integer. Handle them
6461 early, since later code would consider them to be
6462 misaligned integers. */
6464 {
6473 }
6474 else
6475 {
6480 /* Flexible array member is ignored. */
6487 {
6491 {
6494 "the ABI of passing struct with"
6495 " a flexible array member has"
6497 }
6499 }
6501 subclasses,
6511 }
6512 }
6513 }
6517 /* Arrays are handled as small records. */
6518 {
6525 /* The partial classes are now full classes. */
6536 }
6539 /* Unions are similar to RECORD_TYPE but offset is always 0.
6540 */
6542 {
6544 {
6552 bit_offset);
6557 }
6558 }
6563 }
6566 {
6567 /* When size > 16 bytes, if the first one isn't
6568 X86_64_SSE_CLASS or any other ones aren't
6569 X86_64_SSEUP_CLASS, everything should be passed in
6570 memory. */
6577 }
6579 /* Final merger cleanup. */
6581 {
6582 /* If one class is MEMORY, everything should be passed in
6583 memory. */
6587 /* The X86_64_SSEUP_CLASS should be always preceded by
6588 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6592 {
6593 /* The first one should never be X86_64_SSEUP_CLASS. */
6596 }
6598 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6599 everything should be passed in memory. */
6602 {
6605 /* The first one should never be X86_64_X87UP_CLASS. */
6608 {
6611 "the ABI of passing union with long double"
6613 }
6615 }
6616 }
6618 }
6620 /* Compute alignment needed. We align all types to natural boundaries with
6621 exception of XFmode that is aligned to 64bits. */
6623 {
6632 /* Misaligned fields are always returned in memory. */
6635 }
6637 /* for V1xx modes, just use the base mode */
6642 /* Classification of atomic types. */
6644 {
6660 {
6663 /* Analyze last 128 bits only. */
6667 {
6670 }
6672 {
6675 }
6677 {
6681 }
6683 {
6686 }
6687 else
6689 }
6696 /* OImode shouldn't be used directly. */
6703 else
6721 else
6722 {
6726 {
6729 "the ABI of passing structure with complex float"
6731 }
6734 }
6743 /* This modes is larger than 16 bytes. */
6801 else
6805 }
6806 }
6808 /* Examine the argument and return set number of register required in each
6809 class. Return true iff parameter should be passed in memory. */
6811 static bool
6814 {
6825 {
6846 }
6849 }
6851 /* Construct container for the argument used by GCC interface. See
6852 FUNCTION_ARG for the detailed description. */
6854 static rtx
6858 {
6859 /* The following variables hold the static issued_error state. */
6873 rtx ret;
6884 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6885 some less clueful developer tries to use floating-point anyway. */
6887 {
6889 {
6891 {
6894 }
6895 }
6897 {
6900 }
6902 }
6904 /* Likewise, error if the ABI requires us to return values in the
6905 x87 registers and the user specified -mno-80387. */
6911 {
6913 {
6916 }
6918 }
6920 /* First construct simple cases. Avoid SCmode, since we want to use
6921 single register to pass this type. */
6924 {
6939 /* Zero sized array, struct or class. */
6943 }
6982 /* Otherwise figure out the entries of the PARALLEL. */
6984 {
6988 {
6993 /* Merge TImodes on aligned occasions here too. */
6995 tmpmode
6999 else
7001 /* We've requested 24 bytes we
7002 don't have mode for. Use DImode. */
7009 intreg++;
7017 sse_regno++;
7025 sse_regno++;
7030 {
7036 {
7038 i++;
7039 }
7040 else
7065 }
7071 sse_regno++;
7075 }
7076 }
7078 /* Empty aligned struct, union or class. */
7086 }
7088 /* Update the data in CUM to advance over an argument of mode MODE
7089 and data type TYPE. (TYPE is null for libcalls where that information
7090 may not be available.) */
7092 static void
7095 HOST_WIDE_INT words)
7096 {
7098 {
7105 /* FALLTHRU */
7116 {
7119 }
7123 /* OImode shouldn't be used directly. */
7132 /* FALLTHRU */
7154 {
7159 {
7162 }
7163 }
7173 {
7178 {
7181 }
7182 }
7184 }
7185 }
7187 static void
7190 {
7193 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7200 {
7205 }
7206 else
7207 {
7211 }
7212 }
7214 static void
7216 HOST_WIDE_INT words)
7217 {
7218 /* Otherwise, this should be passed indirect. */
7223 {
7226 }
7227 }
7229 /* Update the data in CUM to advance over an argument of mode MODE and
7230 data type TYPE. (TYPE is null for libcalls where that information
7231 may not be available.) */
7233 static void
7236 {
7242 else
7253 else
7255 }
7257 /* Define where to put the arguments to a function.
7258 Value is zero to push the argument on the stack,
7259 or a hard register in which to store the argument.
7261 MODE is the argument's machine mode.
7262 TYPE is the data type of the argument (as a tree).
7263 This is null for libcalls where that information may
7264 not be available.
7265 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7266 the preceding args and about the function being called.
7267 NAMED is nonzero if this argument is a named parameter
7268 (otherwise it is an extra parameter matching an ellipsis). */
7270 static rtx
7274 {
7275 /* Avoid the AL settings for the Unix64 ABI. */
7280 {
7287 /* FALLTHRU */
7293 {
7296 /* Fastcall allocates the first two DWORD (SImode) or
7297 smaller arguments to ECX and EDX if it isn't an
7298 aggregate type . */
7300 {
7306 /* ECX not EAX is the first allocated register. */
7309 }
7311 }
7320 /* FALLTHRU */
7322 /* In 32bit, we pass TImode in xmm registers. */
7330 {
7334 }
7339 /* OImode and XImode shouldn't be used directly. */
7355 {
7359 }
7369 {
7373 }
7375 }
7378 }
7380 static rtx
7383 {
7384 /* Handle a hidden AL argument containing number of registers
7385 for varargs x86-64 functions. */
7389 ? X86_64_SSE_REGPARM_MAX
7394 {
7410 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7414 }
7420 }
7422 static rtx
7425 HOST_WIDE_INT bytes)
7426 {
7429 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7430 We use value of -2 to specify that current function call is MSABI. */
7434 /* If we've run out of registers, it goes on the stack. */
7440 /* Only floating point modes are passed in anything but integer regs. */
7442 {
7445 else
7446 {
7449 /* Unnamed floating parameters are passed in both the
7450 SSE and integer registers. */
7456 }
7457 }
7458 /* Handle aggregated types passed in register. */
7460 {
7465 }
7468 }
7470 /* Return where to put the arguments to a function.
7471 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7473 MODE is the argument's machine mode. TYPE is the data type of the
7474 argument. It is null for libcalls where that information may not be
7475 available. CUM gives information about the preceding args and about
7476 the function being called. NAMED is nonzero if this argument is a
7477 named parameter (otherwise it is an extra parameter matching an
7478 ellipsis). */
7480 static rtx
7483 {
7487 rtx arg;
7491 else
7495 /* To simplify the code below, represent vector types with a vector mode
7496 even if MMX/SSE are not active. */
7504 else
7508 }
7510 /* A C expression that indicates when an argument must be passed by
7511 reference. If nonzero for an argument, a copy of that argument is
7512 made in memory and a pointer to the argument is passed instead of
7513 the argument itself. The pointer is passed in whatever way is
7514 appropriate for passing a pointer to that type. */
7516 static bool
7519 {
7522 /* See Windows x64 Software Convention. */
7524 {
7527 {
7528 /* Arrays are passed by reference. */
7533 {
7534 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7535 are passed by reference. */
7537 }
7538 }
7540 /* __m128 is passed by reference. */
7546 }
7547 }
7552 }
7554 /* Return true when TYPE should be 128bit aligned for 32bit argument
7555 passing ABI. XXX: This function is obsolete and is only used for
7556 checking psABI compatibility with previous versions of GCC. */
7558 static bool
7560 {
7572 {
7573 /* Walk the aggregates recursively. */
7575 {
7579 {
7580 tree field;
7582 /* Walk all the structure fields. */
7584 {
7588 }
7590 }
7593 /* Just for use if some languages passes arrays by value. */
7600 }
7601 }
7603 }
7605 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7606 XXX: This function is obsolete and is only used for checking psABI
7607 compatibility with previous versions of GCC. */
7609 static unsigned int
7612 {
7613 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7614 natural boundaries. */
7616 {
7617 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7618 make an exception for SSE modes since these require 128bit
7619 alignment.
7621 The handling here differs from field_alignment. ICC aligns MMX
7622 arguments to 4 byte boundaries, while structure fields are aligned
7623 to 8 byte boundaries. */
7625 {
7628 }
7629 else
7630 {
7633 }
7634 }
7638 }
7640 /* Return true when TYPE should be 128bit aligned for 32bit argument
7641 passing ABI. */
7643 static bool
7645 {
7655 {
7656 /* Walk the aggregates recursively. */
7658 {
7662 {
7663 tree field;
7665 /* Walk all the structure fields. */
7667 field;
7669 {
7673 }
7675 }
7678 /* Just for use if some languages passes arrays by value. */
7685 }
7686 }
7687 else
7691 }
7693 /* Gives the alignment boundary, in bits, of an argument with the
7694 specified mode and type. */
7696 static unsigned int
7698 {
7701 {
7702 /* Since the main variant type is used for call, we convert it to
7703 the main variant type. */
7706 }
7707 else
7711 else
7712 {
7717 {
7718 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7720 {
7723 }
7729 }
7732 && !warned
7734 saved_align))
7735 {
7738 "The ABI for passing parameters with %d-byte"
7741 }
7742 }
7745 }
7747 /* Return true if N is a possible register number of function value. */
7749 static bool
7751 {
7753 {
7761 /* Complex values are returned in %st(0)/%st(1) pair. */
7764 /* TODO: The function should depend on current function ABI but
7765 builtins.c would need updating then. Therefore we use the
7766 default ABI. */
7771 /* Complex values are returned in %xmm0/%xmm1 pair. */
7780 }
7783 }
7785 /* Define how to find the value returned by a function.
7786 VALTYPE is the data type of the value (as a tree).
7787 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7788 otherwise, FUNC is 0. */
7790 static rtx
7793 {
7796 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7797 we normally prevent this case when mmx is not available. However
7798 some ABIs may require the result to be returned like DImode. */
7802 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7803 we prevent this case when sse is not available. However some ABIs
7804 may require the result to be returned like integer TImode. */
7809 /* 32-byte vector modes in %ymm0. */
7813 /* 64-byte vector modes in %zmm0. */
7817 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7820 else
7821 /* Most things go in %eax. */
7824 /* Override FP return register with %xmm0 for local functions when
7825 SSE math is enabled or for functions with sseregparm attribute. */
7827 {
7832 }
7834 /* OImode shouldn't be used directly. */
7838 }
7840 static rtx
7842 const_tree valtype)
7843 {
7844 rtx ret;
7846 /* Handle libcalls, which don't provide a type node. */
7848 {
7852 {
7871 }
7874 }
7876 {
7877 /* Pointers are always returned in word_mode. */
7879 }
7885 /* For zero sized structures, construct_container returns NULL, but we
7886 need to keep rest of compiler happy by returning meaningful value. */
7891 }
7893 static rtx
7895 const_tree valtype)
7896 {
7900 {
7902 {
7921 }
7922 }
7924 }
7926 static rtx
7929 {
7941 else
7943 }
7945 static rtx
7948 {
7954 }
7956 /* Pointer function arguments and return values are promoted to
7957 word_mode. */
7959 static enum machine_mode
7963 {
7965 {
7968 }
7970 for_return);
7971 }
7973 /* Return true if a structure, union or array with MODE containing FIELD
7974 should be accessed using BLKmode. */
7976 static bool
7978 {
7979 /* Union with XFmode must be in BLKmode. */
7983 }
7985 rtx
7987 {
7989 }
7991 /* Return true iff type is returned in memory. */
7993 static bool
7995 {
7996 #ifdef SUBTARGET_RETURN_IN_MEMORY
7998 #else
8000 HOST_WIDE_INT size;
8003 {
8005 {
8008 /* __m128 is returned in xmm0. */
8017 /* Otherwise, the size must be exactly in [1248]. */
8019 }
8020 else
8021 {
8026 }
8027 }
8028 else
8029 {
8039 {
8040 /* User-created vectors small enough to fit in EAX. */
8044 /* Unless ABI prescibes otherwise,
8045 MMX/3dNow values are returned in MM0 if available. */
8050 /* SSE values are returned in XMM0 if available. */
8054 /* AVX values are returned in YMM0 if available. */
8058 /* AVX512F values are returned in ZMM0 if available. */
8061 }
8069 /* OImode shouldn't be used directly. */
8073 }
8074 #endif
8075 }
8077 \f
8078 /* Create the va_list data type. */
8080 /* Returns the calling convention specific va_list date type.
8081 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8083 static tree
8085 {
8088 /* For i386 we use plain pointer to argument area. */
8098 unsigned_type_node);
8101 unsigned_type_node);
8104 ptr_type_node);
8107 ptr_type_node);
8126 /* The correct type is an array type of one element. */
8128 }
8130 /* Setup the builtin va_list data type and for 64-bit the additional
8131 calling convention specific va_list data types. */
8133 static tree
8135 {
8138 /* Initialize abi specific va_list builtin types. */
8140 {
8141 tree t;
8143 {
8148 }
8149 else
8150 {
8155 }
8157 {
8162 }
8163 else
8164 {
8169 }
8170 }
8173 }
8175 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8177 static void
8179 {
8181 alias_set_type set;
8184 /* GPR size of varargs save area. */
8187 else
8190 /* FPR size of varargs save area. We don't need it if we don't pass
8191 anything in SSE registers. */
8194 else
8208 {
8216 }
8219 {
8223 /* Now emit code to save SSE registers. The AX parameter contains number
8224 of SSE parameter registers used to call this function, though all we
8225 actually check here is the zero/non-zero status. */
8230 label));
8232 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8233 we used movdqa (i.e. TImode) instead? Perhaps even better would
8234 be if we could determine the real mode of the data, via a hook
8235 into pass_stdarg. Ignore all that for now. */
8245 {
8254 }
8257 }
8258 }
8260 static void
8262 {
8266 /* Reset to zero, as there might be a sysv vaarg used
8267 before. */
8272 {
8283 }
8284 }
8286 static void
8290 {
8292 CUMULATIVE_ARGS next_cum;
8293 tree fntype;
8295 /* This argument doesn't appear to be used anymore. Which is good,
8296 because the old code here didn't suppress rtl generation. */
8304 /* For varargs, we do not want to skip the dummy va_dcl argument.
8305 For stdargs, we do want to skip the last named argument. */
8313 else
8315 }
8317 /* Checks if TYPE is of kind va_list char *. */
8319 static bool
8321 {
8322 tree canonic;
8324 /* For 32-bit it is always true. */
8330 }
8332 /* Implement va_start. */
8334 static void
8336 {
8340 tree type;
8341 rtx ovf_rtx;
8345 {
8348 /* When we are splitting the stack, we can't refer to the stack
8349 arguments using internal_arg_pointer, because they may be on
8350 the old stack. The split stack prologue will arrange to
8351 leave a pointer to the old stack arguments in a scratch
8352 register, which we here copy to a pseudo-register. The split
8353 stack prologue can't set the pseudo-register directly because
8354 it (the prologue) runs before any registers have been saved. */
8358 {
8372 }
8373 }
8375 /* Only 64bit target needs something special. */
8377 {
8380 else
8381 {
8390 }
8392 }
8401 /* The following should be folded into the MEM_REF offset. */
8411 /* Count number of gp and fp argument registers used. */
8417 {
8423 }
8426 {
8432 }
8434 /* Find the overflow area. */
8438 else
8448 {
8449 /* Find the register save area.
8450 Prologue of the function save it right above stack frame. */
8458 }
8459 }
8461 /* Implement va_arg. */
8463 static tree
8466 {
8473 rtx container;
8475 tree ptrtype;
8479 /* Only 64bit target needs something special. */
8503 {
8516 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8518 {
8521 }
8529 }
8531 /* Pull the value out of the saved registers. */
8536 {
8550 /* In case we are passing structure, verify that it is consecutive block
8551 on the register save area. If not we need to do moves. */
8553 {
8554 /* Verify that all registers are strictly consecutive */
8556 {
8560 {
8565 }
8566 }
8567 else
8568 {
8572 {
8577 }
8578 }
8579 }
8581 {
8584 }
8585 else
8586 {
8589 }
8591 /* First ensure that we fit completely in registers. */
8593 {
8600 }
8602 {
8610 }
8612 /* Compute index to start of area used for integer regs. */
8614 {
8615 /* int_addr = gpr + sav; */
8618 }
8620 {
8621 /* sse_addr = fpr + sav; */
8624 }
8626 {
8630 /* addr = &temp; */
8635 {
8639 tree piece_type;
8640 tree addr_type;
8641 tree daddr_type;
8650 {
8655 }
8659 else
8666 {
8669 }
8670 else
8671 {
8674 }
8681 {
8686 }
8687 else
8688 {
8689 tree copy
8694 }
8696 }
8697 }
8700 {
8704 }
8707 {
8711 }
8716 }
8718 /* ... otherwise out of the overflow area. */
8720 /* When we align parameter on stack for caller, if the parameter
8721 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8722 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8723 here with caller. */
8728 /* Care for on-stack alignment if needed. */
8731 else
8732 {
8737 }
8754 }
8755 \f
8756 /* Return true if OPNUM's MEM should be matched
8757 in movabs* patterns. */
8759 bool
8761 {
8773 }
8774 \f
8775 /* Initialize the table of extra 80387 mathematical constants. */
8777 static void
8779 {
8781 {
8787 };
8791 {
8793 /* Ensure each constant is rounded to XFmode precision. */
8796 }
8799 }
8801 /* Return non-zero if the constant is something that
8802 can be loaded with a special instruction. */
8804 int
8806 {
8809 REAL_VALUE_TYPE r;
8821 /* For XFmode constants, try to find a special 80387 instruction when
8822 optimizing for size or on those CPUs that benefit from them. */
8825 {
8834 }
8836 /* Load of the constant -0.0 or -1.0 will be split as
8837 fldz;fchs or fld1;fchs sequence. */
8844 }
8846 /* Return the opcode of the special instruction to be used to load
8847 the constant X. */
8851 {
8853 {
8873 }
8874 }
8876 /* Return the CONST_DOUBLE representing the 80387 constant that is
8877 loaded by the specified special instruction. The argument IDX
8878 matches the return value from standard_80387_constant_p. */
8880 rtx
8882 {
8889 {
8900 }
8903 XFmode);
8904 }
8906 /* Return 1 if X is all 0s and 2 if x is all 1s
8907 in supported SSE/AVX vector mode. */
8909 int
8911 {
8918 {
8939 }
8942 }
8944 /* Return the opcode of the special instruction to be used to load
8945 the constant X. */
8949 {
8951 {
8954 {
8976 }
8985 else
8990 }
8992 }
8994 /* Returns true if OP contains a symbol reference */
8996 bool
8998 {
9007 {
9009 {
9015 }
9019 }
9022 }
9024 /* Return true if it is appropriate to emit `ret' instructions in the
9025 body of a function. Do this only if the epilogue is simple, needing a
9026 couple of insns. Prior to reloading, we can't tell how many registers
9027 must be saved, so return false then. Return false if there is no frame
9028 marker to de-allocate. */
9030 bool
9032 {
9038 /* Don't allow more than 32k pop, since that's all we can do
9039 with one instruction. */
9046 }
9047 \f
9048 /* Value should be nonzero if functions must have frame pointers.
9049 Zero means the frame pointer need not be set up (and parms may
9050 be accessed via the stack pointer) in functions that seem suitable. */
9052 static bool
9054 {
9055 /* If we accessed previous frames, then the generated code expects
9056 to be able to access the saved ebp value in our frame. */
9060 /* Several x86 os'es need a frame pointer for other reasons,
9061 usually pertaining to setjmp. */
9065 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9069 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9070 allocation is 4GB. */
9074 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9075 turns off the frame pointer by default. Turn it back on now if
9076 we've not got a leaf function. */
9086 }
9088 /* Record that the current function accesses previous call frames. */
9090 void
9092 {
9094 }
9095 \f
9096 #ifndef USE_HIDDEN_LINKONCE
9097 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9098 # define USE_HIDDEN_LINKONCE 1
9099 # else
9100 # define USE_HIDDEN_LINKONCE 0
9101 # endif
9102 #endif
9106 /* Fills in the label name that should be used for a pc thunk for
9107 the given register. */
9109 static void
9111 {
9116 else
9118 }
9121 /* This function generates code for -fpic that loads %ebx with
9122 the return address of the caller and then returns. */
9124 static void
9126 {
9131 {
9133 tree decl;
9149 #if TARGET_MACHO
9151 {
9160 }
9161 else
9162 #endif
9164 {
9175 }
9176 else
9177 {
9180 }
9186 /* Make sure unwind info is emitted for the thunk if needed. */
9189 /* Pad stack IP move with 4 instructions (two NOPs count
9190 as one instruction). */
9192 {
9197 }
9208 }
9212 }
9214 /* Emit code for the SET_GOT patterns. */
9218 {
9224 {
9225 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9230 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9231 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9232 an unadorned address. */
9237 }
9242 {
9244 /* We don't need a pic base, we're not producing pic. */
9251 }
9252 else
9253 {
9262 #if TARGET_MACHO
9263 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9264 This is what will be referenced by the Mach-O PIC subsystem. */
9268 /* When we are restoring the pic base at the site of a nonlocal label,
9269 and we decided to emit the pic base above, we will still output a
9270 local label used for calculating the correction offset (even though
9271 the offset will be 0 in that case). */
9275 #endif
9276 }
9282 }
9284 /* Generate an "push" pattern for input ARG. */
9286 static rtx
9288 {
9301 stack_pointer_rtx)),
9302 arg);
9303 }
9305 /* Generate an "pop" pattern for input ARG. */
9307 static rtx
9309 {
9314 arg,
9317 stack_pointer_rtx)));
9318 }
9320 /* Return >= 0 if there is an unused call-clobbered register available
9321 for the entire function. */
9323 static unsigned int
9325 {
9329 {
9331 /* Can't use the same register for both PIC and DRAP. */
9334 else
9339 }
9342 }
9344 /* Return TRUE if we need to save REGNO. */
9346 static bool
9348 {
9359 {
9362 {
9368 }
9369 }
9380 }
9382 /* Return number of saved general prupose registers. */
9384 static int
9386 {
9392 nregs ++;
9394 }
9396 /* Return number of saved SSE registrers. */
9398 static int
9400 {
9408 nregs ++;
9410 }
9412 /* Given FROM and TO register numbers, say whether this elimination is
9413 allowed. If stack alignment is needed, we can only replace argument
9414 pointer with hard frame pointer, or replace frame pointer with stack
9415 pointer. Otherwise, frame pointer elimination is automatically
9416 handled and all other eliminations are valid. */
9418 static bool
9420 {
9426 else
9428 }
9430 /* Return the offset between two registers, one to be eliminated, and the other
9431 its replacement, at the start of a routine. */
9433 HOST_WIDE_INT
9435 {
9444 else
9445 {
9453 }
9454 }
9456 /* In a dynamically-aligned function, we can't know the offset from
9457 stack pointer to frame pointer, so we must ensure that setjmp
9458 eliminates fp against the hard fp (%ebp) rather than trying to
9459 index from %esp up to the top of the frame across a gap that is
9460 of unknown (at compile-time) size. */
9461 static rtx
9463 {
9465 }
9467 /* When using -fsplit-stack, the allocation routines set a field in
9468 the TCB to the bottom of the stack plus this much space, measured
9469 in bytes. */
9471 #define SPLIT_STACK_AVAILABLE 256
9473 /* Fill structure ix86_frame about frame of currently computed function. */
9475 static void
9477 {
9479 HOST_WIDE_INT offset;
9482 HOST_WIDE_INT to_allocate;
9490 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9491 function prologues and leaf. */
9495 {
9500 }
9506 /* For SEH we have to limit the amount of code movement into the prologue.
9507 At present we do this via a BLOCKAGE, at which point there's very little
9508 scheduling that can be done, which means that there's very little point
9509 in doing anything except PUSHs. */
9513 /* During reload iteration the amount of registers saved can change.
9514 Recompute the value as needed. Do not recompute when amount of registers
9515 didn't change as reload does multiple calls to the function and does not
9516 expect the decision to change within single iteration. */
9519 {
9525 /* The fast prologue uses move instead of push to save registers. This
9526 is significantly longer, but also executes faster as modern hardware
9527 can execute the moves in parallel, but can't do that for push/pop.
9529 Be careful about choosing what prologue to emit: When function takes
9530 many instructions to execute we may use slow version as well as in
9531 case function is known to be outside hot spot (this is known with
9532 feedback only). Weight the size of function by number of registers
9533 to save as it is cheap to use one or two push instructions but very
9534 slow to use many of them. */
9538 || (flag_branch_probabilities
9541 else
9544 }
9546 frame->save_regs_using_mov
9548 /* If static stack checking is enabled and done with probes,
9549 the registers need to be saved before allocating the frame. */
9552 /* Skip return address. */
9555 /* Skip pushed static chain. */
9559 /* Skip saved base pointer. */
9564 /* The traditional frame pointer location is at the top of the frame. */
9567 /* Register save area */
9571 /* On SEH target, registers are pushed just before the frame pointer
9572 location. */
9576 /* Align and set SSE register save area. */
9578 {
9579 /* The only ABI that has saved SSE registers (Win64) also has a
9580 16-byte aligned default stack, and thus we don't need to be
9581 within the re-aligned local stack frame to save them. */
9585 }
9588 /* The re-aligned stack starts here. Values before this point are not
9589 directly comparable with values below this point. In order to make
9590 sure that no value happens to be the same before and after, force
9591 the alignment computation below to add a non-zero value. */
9595 /* Va-arg area */
9599 /* Align start of frame for local function. */
9608 /* Frame pointer points here. */
9613 /* Add outgoing arguments area. Can be skipped if we eliminated
9614 all the function calls as dead code.
9615 Skipping is however impossible when function calls alloca. Alloca
9616 expander assumes that last crtl->outgoing_args_size
9617 of stack frame are unused. */
9621 {
9624 }
9625 else
9628 /* Align stack boundary. Only needed if we're calling another function
9629 or using alloca. */
9634 /* We've reached end of stack frame. */
9637 /* Size prologue needs to allocate. */
9648 {
9654 }
9655 else
9659 /* The SEH frame pointer location is near the bottom of the frame.
9660 This is enforced by the fact that the difference between the
9661 stack pointer and the frame pointer is limited to 240 bytes in
9662 the unwind data structure. */
9664 {
9665 HOST_WIDE_INT diff;
9667 /* If we can leave the frame pointer where it is, do so. Also, returns
9668 the establisher frame for __builtin_frame_address (0). */
9673 {
9674 /* Ideally we'd determine what portion of the local stack frame
9675 (within the constraint of the lowest 240) is most heavily used.
9676 But without that complication, simply bias the frame pointer
9677 by 128 bytes so as to maximize the amount of the local stack
9678 frame that is addressable with 8-bit offsets. */
9680 }
9681 }
9682 }
9684 /* This is semi-inlined memory_address_length, but simplified
9685 since we know that we're always dealing with reg+offset, and
9686 to avoid having to create and discard all that rtl. */
9690 {
9694 {
9695 /* EBP and R13 cannot be encoded without an offset. */
9697 }
9701 /* ESP and R12 must be encoded with a SIB byte. */
9703 len++;
9706 }
9708 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9709 The valid base registers are taken from CFUN->MACHINE->FS. */
9711 static rtx
9713 {
9719 {
9720 /* Choose the base register most likely to allow the most scheduling
9721 opportunities. Generally FP is valid throughout the function,
9722 while DRAP must be reloaded within the epilogue. But choose either
9723 over the SP due to increased encoding size. */
9726 {
9729 }
9731 {
9734 }
9736 {
9739 }
9740 }
9741 else
9742 {
9743 HOST_WIDE_INT toffset;
9746 /* Choose the base register with the smallest address encoding.
9747 With a tie, choose FP > DRAP > SP. */
9749 {
9753 }
9755 {
9759 {
9763 }
9764 }
9766 {
9770 {
9774 }
9775 }
9776 }
9780 }
9782 /* Emit code to save registers in the prologue. */
9784 static void
9786 {
9788 rtx insn;
9792 {
9795 }
9796 }
9798 /* Emit a single register save at CFA - CFA_OFFSET. */
9800 static void
9802 HOST_WIDE_INT cfa_offset)
9803 {
9811 /* For SSE saves, we need to indicate the 128-bit alignment. */
9822 /* When saving registers into a re-aligned local stack frame, avoid
9823 any tricky guessing by dwarf2out. */
9825 {
9829 {
9830 /* A bit of a hack. We force the DRAP register to be saved in
9831 the re-aligned stack frame, which provides us with a copy
9832 of the CFA that will last past the prologue. Install it. */
9838 }
9839 else
9840 {
9841 /* The frame pointer is a stable reference within the
9842 aligned frame. Use it. */
9849 }
9850 }
9852 /* The memory may not be relative to the current CFA register,
9853 which means that we may need to generate a new pattern for
9854 use by the unwind info. */
9856 {
9861 }
9862 }
9864 /* Emit code to save registers using MOV insns.
9865 First register is stored at CFA - CFA_OFFSET. */
9866 static void
9868 {
9873 {
9876 }
9877 }
9879 /* Emit code to save SSE registers using MOV insns.
9880 First register is stored at CFA - CFA_OFFSET. */
9881 static void
9883 {
9888 {
9891 }
9892 }
9896 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9897 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9898 Don't add the note if the previously saved value will be left untouched
9899 within stack red-zone till return, as unwinders can find the same value
9900 in the register and on the stack. */
9902 static void
9904 {
9910 {
9913 }
9914 else
9915 queued_cfa_restores
9917 }
9919 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9921 static void
9923 {
9924 rtx last;
9928 ;
9933 }
9935 /* Expand prologue or epilogue stack adjustment.
9936 The pattern exist to put a dependency on all ebp-based memory accesses.
9937 STYLE should be negative if instructions should be marked as frame related,
9938 zero if %r11 register is live and cannot be freely used and positive
9939 otherwise. */
9941 static void
9944 {
9946 rtx insn;
9953 else
9954 {
9955 rtx tmp;
9956 /* r11 is used by indirect sibcall return as well, set before the
9957 epilogue and used after the epilogue. */
9960 else
9961 {
9965 }
9971 }
9978 {
9979 rtx r;
9989 }
9991 {
9994 {
9998 }
9999 }
10002 {
10007 {
10010 }
10012 {
10015 }
10016 else
10017 {
10018 /* Else there are two possibilities: SP itself, which we set
10019 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10020 taken care of this by hand along the eh_return path. */
10023 }
10027 }
10028 }
10030 /* Find an available register to be used as dynamic realign argument
10031 pointer regsiter. Such a register will be written in prologue and
10032 used in begin of body, so it must not be
10033 1. parameter passing register.
10034 2. GOT pointer.
10035 We reuse static-chain register if it is available. Otherwise, we
10036 use DI for i386 and R13 for x86-64. We chose R13 since it has
10037 shorter encoding.
10039 Return: the regno of chosen register. */
10041 static unsigned int
10043 {
10047 {
10048 /* Use R13 for nested function or function need static chain.
10049 Since function with tail call may use any caller-saved
10050 registers in epilogue, DRAP must not use caller-saved
10051 register in such case. */
10056 }
10057 else
10058 {
10059 /* Use DI for nested function or function need static chain.
10060 Since function with tail call may use any caller-saved
10061 registers in epilogue, DRAP must not use caller-saved
10062 register in such case. */
10066 /* Reuse static chain register if it isn't used for parameter
10067 passing. */
10069 {
10073 }
10075 }
10076 }
10078 /* Return minimum incoming stack alignment. */
10080 static unsigned int
10082 {
10085 /* Prefer the one specified at command line. */
10088 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10089 if -mstackrealign is used, it isn't used for sibcall check and
10090 estimated stack alignment is 128bit. */
10092 && !TARGET_64BIT
10093 && ix86_force_align_arg_pointer
10096 else
10099 /* Incoming stack alignment can be changed on individual functions
10100 via force_align_arg_pointer attribute. We use the smallest
10101 incoming stack boundary. */
10107 /* The incoming stack frame has to be aligned at least at
10108 parm_stack_boundary. */
10112 /* Stack at entrance of main is aligned by runtime. We use the
10113 smallest incoming stack boundary. */
10121 }
10123 /* Update incoming stack boundary and estimated stack alignment. */
10125 static void
10127 {
10128 ix86_incoming_stack_boundary
10131 /* x86_64 vararg needs 16byte stack alignment for register save
10132 area. */
10137 }
10139 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10140 needed or an rtx for DRAP otherwise. */
10142 static rtx
10144 {
10149 {
10150 /* Assign DRAP to vDRAP and returns vDRAP */
10152 rtx drap_vreg;
10153 rtx arg_ptr;
10166 {
10169 }
10171 }
10172 else
10174 }
10176 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10178 static rtx
10180 {
10182 }
10185 rtx reg;
10187 };
10189 /* Return a short-lived scratch register for use on function entry.
10190 In 32-bit mode, it is valid only after the registers are saved
10191 in the prologue. This register must be released by means of
10192 release_scratch_register_on_entry once it is dead. */
10194 static void
10196 {
10202 {
10203 /* We always use R11 in 64-bit mode. */
10205 }
10206 else
10207 {
10209 bool fastcall_p
10211 bool thiscall_p
10215 int drap_regno
10218 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10219 for the static chain register. */
10223 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10224 for the static chain register. */
10229 /* ecx is the static chain register. */
10231 && !static_chain_p
10236 /* esi is the static chain register. */
10242 else
10243 {
10246 }
10247 }
10251 {
10254 }
10255 }
10257 /* Release a scratch register obtained from the preceding function. */
10259 static void
10261 {
10263 {
10267 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10273 }
10274 }
10276 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10278 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10280 static void
10282 {
10283 /* We skip the probe for the first interval + a small dope of 4 words and
10284 probe that many bytes past the specified size to maintain a protection
10285 area at the botton of the stack. */
10289 /* See if we have a constant small number of probes to generate. If so,
10290 that's the easy case. The run-time loop is made up of 11 insns in the
10291 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10292 for n # of intervals. */
10294 {
10298 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10299 values of N from 1 until it exceeds SIZE. If only one probe is
10300 needed, this will not generate any code. Then adjust and probe
10301 to PROBE_INTERVAL + SIZE. */
10303 {
10305 {
10308 }
10309 else
10316 }
10320 else
10328 /* Adjust back to account for the additional first interval. */
10332 }
10334 /* Otherwise, do the same as above, but in a loop. Note that we must be
10335 extra careful with variables wrapping around because we might be at
10336 the very top (or the very bottom) of the address space and we have
10337 to be able to handle this case properly; in particular, we use an
10338 equality test for the loop condition. */
10339 else
10340 {
10341 HOST_WIDE_INT rounded_size;
10347 /* Step 1: round SIZE to the previous multiple of the interval. */
10352 /* Step 2: compute initial and final value of the loop counter. */
10354 /* SP = SP_0 + PROBE_INTERVAL. */
10359 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10363 stack_pointer_rtx)));
10366 /* Step 3: the loop
10368 while (SP != LAST_ADDR)
10369 {
10370 SP = SP + PROBE_INTERVAL
10371 probe at SP
10372 }
10374 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10375 values of N from 1 until it is equal to ROUNDED_SIZE. */
10380 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10381 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10384 {
10389 }
10391 /* Adjust back to account for the additional first interval. */
10397 }
10401 /* Even if the stack pointer isn't the CFA register, we need to correctly
10402 describe the adjustments made to it, in particular differentiate the
10403 frame-related ones from the frame-unrelated ones. */
10405 {
10418 }
10420 /* Make sure nothing is scheduled before we are done. */
10422 }
10424 /* Adjust the stack pointer up to REG while probing it. */
10428 {
10438 /* Jump to END_LAB if SP == LAST_ADDR. */
10446 /* SP = SP + PROBE_INTERVAL. */
10450 /* Probe at SP. */
10461 }
10463 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10464 inclusive. These are offsets from the current stack pointer. */
10466 static void
10468 {
10469 /* See if we have a constant small number of probes to generate. If so,
10470 that's the easy case. The run-time loop is made up of 7 insns in the
10471 generic case while the compile-time loop is made up of n insns for n #
10472 of intervals. */
10474 {
10475 HOST_WIDE_INT i;
10477 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10478 it exceeds SIZE. If only one probe is needed, this will not
10479 generate any code. Then probe at FIRST + SIZE. */
10486 }
10488 /* Otherwise, do the same as above, but in a loop. Note that we must be
10489 extra careful with variables wrapping around because we might be at
10490 the very top (or the very bottom) of the address space and we have
10491 to be able to handle this case properly; in particular, we use an
10492 equality test for the loop condition. */
10493 else
10494 {
10501 /* Step 1: round SIZE to the previous multiple of the interval. */
10506 /* Step 2: compute initial and final value of the loop counter. */
10508 /* TEST_OFFSET = FIRST. */
10511 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10515 /* Step 3: the loop
10517 while (TEST_ADDR != LAST_ADDR)
10518 {
10519 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10520 probe at TEST_ADDR
10521 }
10523 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10524 until it is equal to ROUNDED_SIZE. */
10529 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10530 that SIZE is equal to ROUNDED_SIZE. */
10535 stack_pointer_rtx,
10540 }
10542 /* Make sure nothing is scheduled before we are done. */
10544 }
10546 /* Probe a range of stack addresses from REG to END, inclusive. These are
10547 offsets from the current stack pointer. */
10551 {
10561 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10569 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10573 /* Probe at TEST_ADDR. */
10586 }
10588 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10589 to be generated in correct form. */
10590 static void
10592 {
10593 /* Check if stack realign is really needed after reload, and
10594 stores result in cfun */
10595 unsigned int incoming_stack_boundary
10604 {
10605 /* After stack_realign_needed is finalized, we can't no longer
10606 change it. */
10609 }
10611 /* If the only reason for frame_pointer_needed is that we conservatively
10612 assumed stack realignment might be needed, but in the end nothing that
10613 needed the stack alignment had been spilled, clear frame_pointer_needed
10614 and say we don't need stack realignment. */
10616 && frame_pointer_needed
10618 && flag_omit_frame_pointer
10620 && !ix86_current_function_calls_tls_descriptor
10629 {
10631 basic_block bb;
10638 HARD_FRAME_POINTER_REGNUM);
10640 {
10641 rtx insn;
10645 set_up_by_prologue))
10646 {
10650 }
10651 }
10653 /* If drap has been set, but it actually isn't live at the start
10654 of the function, there is no reason to set it up. */
10656 {
10659 {
10662 }
10663 }
10664 else
10679 }
10683 }
10685 /* Expand the prologue into a bunch of separate insns. */
10687 void
10689 {
10694 HOST_WIDE_INT allocate;
10700 /* DRAP should not coexist with stack_realign_fp */
10705 /* Initialize CFA state for before the prologue. */
10709 /* Track SP offset to the CFA. We continue tracking this after we've
10710 swapped the CFA register away from SP. In the case of re-alignment
10711 this is fudged; we're interested to offsets within the local frame. */
10718 {
10719 /* We should have already generated an error for any use of
10720 ms_hook on a nested function. */
10723 /* Check if profiling is active and we shall use profiling before
10724 prologue variant. If so sorry. */
10729 /* In ix86_asm_output_function_label we emitted:
10730 8b ff movl.s %edi,%edi
10731 55 push %ebp
10732 8b ec movl.s %esp,%ebp
10734 This matches the hookable function prologue in Win32 API
10735 functions in Microsoft Windows XP Service Pack 2 and newer.
10736 Wine uses this to enable Windows apps to hook the Win32 API
10737 functions provided by Wine.
10739 What that means is that we've already set up the frame pointer. */
10743 {
10746 /* We've decided to use the frame pointer already set up.
10747 Describe this to the unwinder by pretending that both
10748 push and mov insns happen right here.
10750 Putting the unwind info here at the end of the ms_hook
10751 is done so that we can make absolutely certain we get
10752 the required byte sequence at the start of the function,
10753 rather than relying on an assembler that can produce
10754 the exact encoding required.
10756 However it does mean (in the unpatched case) that we have
10757 a 1 insn window where the asynchronous unwind info is
10758 incorrect. However, if we placed the unwind info at
10759 its correct location we would have incorrect unwind info
10760 in the patched case. Which is probably all moot since
10761 I don't expect Wine generates dwarf2 unwind info for the
10762 system libraries that use this feature. */
10768 stack_pointer_rtx);
10776 /* Note that gen_push incremented m->fs.cfa_offset, even
10777 though we didn't emit the push insn here. */
10781 }
10782 else
10783 {
10784 /* The frame pointer is not needed so pop %ebp again.
10785 This leaves us with a pristine state. */
10787 }
10788 }
10790 /* The first insn of a function that accepts its static chain on the
10791 stack is to push the register that would be filled in by a direct
10792 call. This insn will be skipped by the trampoline. */
10794 {
10798 /* We don't want to interpret this push insn as a register save,
10799 only as a stack adjustment. The real copy of the register as
10800 a save will be done later, if needed. */
10805 }
10807 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10808 of DRAP is needed and stack realignment is really needed after reload */
10810 {
10813 /* Only need to push parameter pointer reg if it is caller saved. */
10815 {
10816 /* Push arg pointer reg */
10819 }
10821 /* Grab the argument pointer. */
10828 /* Align the stack. */
10830 stack_pointer_rtx,
10834 /* Replicate the return address on the stack so that return
10835 address can be reached via (argp - 1) slot. This is needed
10836 to implement macro RETURN_ADDR_RTX and intrinsic function
10837 expand_builtin_return_addr etc. */
10843 /* For the purposes of frame and register save area addressing,
10844 we've started over with a new frame. */
10847 }
10853 {
10854 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10855 slower on all targets. Also sdb doesn't like it. */
10859 /* Push registers now, before setting the frame pointer
10860 on SEH target. */
10862 && TARGET_SEH
10864 {
10868 }
10871 {
10879 }
10880 }
10883 {
10884 /* If saving registers via PUSH, do so now. */
10886 {
10890 }
10892 /* When using red zone we may start register saving before allocating
10893 the stack frame saving one cycle of the prologue. However, avoid
10894 doing this if we have to probe the stack; at least on x86_64 the
10895 stack probe can turn into a call that clobbers a red zone location. */
10897 && (! TARGET_STACK_PROBE
10899 {
10902 }
10903 }
10906 {
10910 /* The computation of the size of the re-aligned stack frame means
10911 that we must allocate the size of the register save area before
10912 performing the actual alignment. Otherwise we cannot guarantee
10913 that there's enough storage above the realignment point. */
10920 /* Align the stack. */
10922 stack_pointer_rtx,
10925 /* For the purposes of register save area addressing, the stack
10926 pointer is no longer valid. As for the value of sp_offset,
10927 see ix86_compute_frame_layout, which we need to match in order
10928 to pass verification of stack_pointer_offset at the end. */
10931 }
10936 {
10937 /* We start to count from ARG_POINTER. */
10940 /* If it was realigned, take into account the fake frame. */
10942 {
10949 /* This over-estimates by 1 minimal-stack-alignment-unit but
10950 mitigates that by counting in the new return address slot. */
10951 current_function_dynamic_stack_size
10953 }
10956 }
10958 /* On SEH target with very large frame size, allocate an area to save
10959 SSE registers (as the very large allocation won't be described). */
10963 {
10964 HOST_WIDE_INT sse_size =
10969 /* No need to do stack checking as the area will be immediately
10970 written. */
10977 }
10979 /* The stack has already been decremented by the instruction calling us
10980 so probe if the size is non-negative to preserve the protection area. */
10982 {
10983 /* We expect the registers to be saved when probes are used. */
10987 {
10990 {
10993 }
10994 }
10995 else
10996 {
11003 {
11005 {
11008 }
11009 else
11011 }
11012 else
11013 {
11015 {
11019 }
11020 else
11022 }
11023 }
11024 }
11027 ;
11030 {
11034 }
11035 else
11036 {
11048 {
11051 /* Note that SEH directives need to continue tracking the stack
11052 pointer even after the frame pointer has been set up. */
11054 {
11058 }
11059 }
11062 {
11067 {
11071 }
11072 }
11077 /* Use the fact that AX still contains ALLOCATE. */
11079 ? gen_pro_epilogue_adjust_stack_di_sub
11086 {
11094 }
11097 /* Use stack_pointer_rtx for relative addressing so that code
11098 works for realigned stack, too. */
11100 {
11107 }
11109 {
11114 }
11115 }
11118 /* If we havn't already set up the frame pointer, do so now. */
11120 {
11132 }
11140 /* We don't use pic-register for pe-coff target. */
11142 && !TARGET_PECOFF
11145 {
11152 }
11155 {
11157 {
11159 {
11169 label));
11173 }
11174 else
11176 }
11177 else
11178 {
11182 }
11183 }
11185 /* In the pic_reg_used case, make sure that the got load isn't deleted
11186 when mcount needs it. Blockage to avoid call movement across mcount
11187 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11188 note. */
11193 {
11194 /* vDRAP is setup but after reload it turns out stack realign
11195 isn't necessary, here we will emit prologue to setup DRAP
11196 without stack realign adjustment */
11199 }
11201 /* Prevent instructions from being scheduled into register save push
11202 sequence when access to the redzone area is done through frame pointer.
11203 The offset between the frame pointer and the stack pointer is calculated
11204 relative to the value of the stack pointer at the end of the function
11205 prologue, and moving instructions that access redzone area via frame
11206 pointer inside push sequence violates this assumption. */
11210 /* Emit cld instruction if stringops are used in the function. */
11214 /* SEH requires that the prologue end within 256 bytes of the start of
11215 the function. Prevent instruction schedules that would extend that.
11216 Further, prevent alloca modifications to the stack pointer from being
11217 combined with prologue modifications. */
11220 }
11222 /* Emit code to restore REG using a POP insn. */
11224 static void
11226 {
11235 {
11236 /* Previously we'd represented the CFA as an expression
11237 like *(%ebp - 8). We've just popped that value from
11238 the stack, which means we need to reset the CFA to
11239 the drap register. This will remain until we restore
11240 the stack pointer. */
11244 /* This means that the DRAP register is valid for addressing too. */
11247 }
11250 {
11257 }
11259 /* When the frame pointer is the CFA, and we pop it, we are
11260 swapping back to the stack pointer as the CFA. This happens
11261 for stack frames that don't allocate other data, so we assume
11262 the stack pointer is now pointing at the return address, i.e.
11263 the function entry state, which makes the offset be 1 word. */
11265 {
11268 {
11276 }
11277 }
11278 }
11280 /* Emit code to restore saved registers using POP insns. */
11282 static void
11284 {
11290 }
11292 /* Emit code and notes for the LEAVE instruction. */
11294 static void
11296 {
11308 {
11316 }
11319 }
11321 /* Emit code to restore saved registers using MOV insns.
11322 First register is restored from CFA - CFA_OFFSET. */
11323 static void
11326 {
11332 {
11341 {
11342 /* Previously we'd represented the CFA as an expression
11343 like *(%ebp - 8). We've just popped that value from
11344 the stack, which means we need to reset the CFA to
11345 the drap register. This will remain until we restore
11346 the stack pointer. */
11350 /* This means that the DRAP register is valid for addressing. */
11352 }
11353 else
11357 }
11358 }
11360 /* Emit code to restore saved registers using MOV insns.
11361 First register is restored from CFA - CFA_OFFSET. */
11362 static void
11365 {
11370 {
11372 rtx mem;
11382 }
11383 }
11385 /* Restore function stack, frame, and registers. */
11387 void
11389 {
11405 /* The FP must be valid if the frame pointer is present. */
11410 /* We must have *some* valid pointer to the stack frame. */
11413 /* The DRAP is never valid at this point. */
11416 /* See the comment about red zone and frame
11417 pointer usage in ix86_expand_prologue. */
11424 /* Determine the CFA offset of the end of the red-zone. */
11427 {
11428 /* The red-zone begins below the return address. */
11431 /* When the register save area is in the aligned portion of
11432 the stack, determine the maximum runtime displacement that
11433 matches up with the aligned frame. */
11437 }
11439 /* Special care must be taken for the normal return case of a function
11440 using eh_return: the eax and edx registers are marked as saved, but
11441 not restored along this path. Adjust the save location to match. */
11445 /* EH_RETURN requires the use of moves to function properly. */
11448 /* SEH requires the use of pops to identify the epilogue. */
11451 /* If we're only restoring one register and sp is not valid then
11452 using a move instruction to restore the register since it's
11453 less work than reloading sp and popping the register. */
11466 && TARGET_USE_LEAVE
11470 else
11474 {
11475 /* Ensure that the entire register save area is addressable via
11476 the stack pointer, if we will restore via sp. */
11481 {
11485 style,
11487 }
11488 }
11490 /* If there are any SSE registers to restore, then we have to do it
11491 via moves, since there's obviously no pop for SSE regs. */
11497 {
11498 rtx t;
11503 /* eh_return epilogues need %ecx added to the stack pointer. */
11505 {
11508 /* Stack align doesn't work with eh_return. */
11510 /* Neither does regparm nested functions. */
11514 {
11522 /* Note that we use SA as a temporary CFA, as the return
11523 address is at the proper place relative to it. We
11524 pretend this happens at the FP restore insn because
11525 prior to this insn the FP would be stored at the wrong
11526 offset relative to SA, and after this insn we have no
11527 other reasonable register to use for the CFA. We don't
11528 bother resetting the CFA to the SP for the duration of
11529 the return insn. */
11542 }
11543 else
11544 {
11552 {
11556 UNITS_PER_WORD));
11558 }
11559 }
11562 }
11563 }
11564 else
11565 {
11566 /* SEH requires that the function end with (1) a stack adjustment
11567 if necessary, (2) a sequence of pops, and (3) a return or
11568 jump instruction. Prevent insns from the function body from
11569 being scheduled into this sequence. */
11571 {
11572 /* Prevent a catch region from being adjacent to the standard
11573 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11574 several other flags that would be interesting to test are
11575 not yet set up. */
11578 else
11580 }
11582 /* First step is to deallocate the stack frame so that we can
11583 pop the registers. Also do it on SEH target for very large
11584 frame as the emitted instructions aren't allowed by the ABI in
11585 epilogues. */
11587 || (TARGET_SEH
11590 {
11595 }
11597 {
11601 style,
11603 }
11606 }
11608 /* If we used a stack pointer and haven't already got rid of it,
11609 then do so now. */
11611 {
11612 /* If the stack pointer is valid and pointing at the frame
11613 pointer store address, then we only need a pop. */
11616 /* Leave results in shorter dependency chains on CPUs that are
11617 able to grok it fast. */
11622 else
11623 {
11625 hard_frame_pointer_rtx,
11628 }
11629 }
11632 {
11634 rtx insn;
11660 }
11662 /* At this point the stack pointer must be valid, and we must have
11663 restored all of the registers. We may not have deallocated the
11664 entire stack frame. We've delayed this until now because it may
11665 be possible to merge the local stack deallocation with the
11666 deallocation forced by ix86_static_chain_on_stack. */
11671 {
11675 }
11676 else
11679 /* Sibcall epilogues don't want a return instruction. */
11681 {
11684 }
11687 {
11690 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11691 address, do explicit add, and jump indirectly to the caller. */
11694 {
11696 rtx insn;
11698 /* There is no "pascal" calling convention in any 64bit ABI. */
11715 }
11716 else
11718 }
11719 else
11722 /* Restore the state back to the state from the prologue,
11723 so that it's correct for the next epilogue. */
11725 }
11727 /* Reset from the function's potential modifications. */
11729 static void
11731 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11732 {
11735 #if TARGET_MACHO
11736 /* Mach-O doesn't support labels at the end of objects, so if
11737 it looks like we might want one, insert a NOP. */
11738 {
11744 {
11745 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11746 notes only, instead set their CODE_LABEL_NUMBER to -1,
11747 otherwise there would be code generation differences
11748 in between -g and -g0. */
11752 }
11762 }
11763 #endif
11765 }
11767 /* Return a scratch register to use in the split stack prologue. The
11768 split stack prologue is used for -fsplit-stack. It is the first
11769 instructions in the function, even before the regular prologue.
11770 The scratch register can be any caller-saved register which is not
11771 used for parameters or for the static chain. */
11773 static unsigned int
11775 {
11778 else
11779 {
11792 {
11794 {
11798 }
11800 }
11802 {
11806 }
11808 {
11811 else
11812 {
11814 {
11818 }
11820 }
11821 }
11822 else
11823 {
11824 /* FIXME: We could make this work by pushing a register
11825 around the addition and comparison. */
11828 }
11829 }
11830 }
11832 /* A SYMBOL_REF for the function which allocates new stackspace for
11833 -fsplit-stack. */
11837 /* A SYMBOL_REF for the more stack function when using the large
11838 model. */
11842 /* Handle -fsplit-stack. These are the first instructions in the
11843 function, even before the regular prologue. */
11845 void
11847 {
11849 HOST_WIDE_INT allocate;
11854 rtx fn;
11862 /* This is the label we will branch to if we have enough stack
11863 space. We expect the basic block reordering pass to reverse this
11864 branch if optimizing, so that we branch in the unlikely case. */
11867 /* We need to compare the stack pointer minus the frame size with
11868 the stack boundary in the TCB. The stack boundary always gives
11869 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11870 can compare directly. Otherwise we need to do an addition. */
11873 UNSPEC_STACK_CHECK);
11878 else
11879 {
11881 rtx offset;
11883 /* We need a scratch register to hold the stack pointer minus
11884 the required frame size. Since this is the very start of the
11885 function, the scratch register can be any caller-saved
11886 register which is not used for parameters. */
11893 {
11894 /* We don't use ix86_gen_add3 in this case because it will
11895 want to split to lea, but when not optimizing the insn
11896 will not be split after this point. */
11899 offset)));
11900 }
11901 else
11902 {
11905 stack_pointer_rtx));
11906 }
11908 }
11914 /* Mark the jump as very likely to be taken. */
11922 /* Get more stack space. We pass in the desired stack space and the
11923 size of the arguments to copy to the new stack. In 32-bit mode
11924 we push the parameters; __morestack will return on a new stack
11925 anyhow. In 64-bit mode we pass the parameters in r10 and
11926 r11. */
11931 {
11937 /* If this function uses a static chain, it will be in %r10.
11938 Preserve it across the call to __morestack. */
11940 {
11941 rtx rax;
11946 }
11950 {
11951 HOST_WIDE_INT argval;
11954 /* When using the large model we need to load the address
11955 into a register, and we've run out of registers. So we
11956 switch to a different calling convention, and we call a
11957 different function: __morestack_large. We pass the
11958 argument size in the upper 32 bits of r10 and pass the
11959 frame size in the lower 32 bits. */
11964 split_stack_fn_large =
11968 {
11978 UNSPEC_GOT);
11984 }
11985 else
11992 }
11993 else
11994 {
11998 }
12001 }
12002 else
12003 {
12006 }
12012 /* In order to make call/return prediction work right, we now need
12013 to execute a return instruction. See
12014 libgcc/config/i386/morestack.S for the details on how this works.
12016 For flow purposes gcc must not see this as a return
12017 instruction--we need control flow to continue at the subsequent
12018 label. Therefore, we use an unspec. */
12022 /* If we are in 64-bit mode and this function uses a static chain,
12023 we saved %r10 in %rax before calling _morestack. */
12028 /* If this function calls va_start, we need to store a pointer to
12029 the arguments on the old stack, because they may not have been
12030 all copied to the new stack. At this point the old stack can be
12031 found at the frame pointer value used by __morestack, because
12032 __morestack has set that up before calling back to us. Here we
12033 store that pointer in a scratch register, and in
12034 ix86_expand_prologue we store the scratch register in a stack
12035 slot. */
12037 {
12039 rtx frame_reg;
12046 /* 64-bit:
12047 fp -> old fp value
12048 return address within this function
12049 return address of caller of this function
12050 stack arguments
12051 So we add three words to get to the stack arguments.
12053 32-bit:
12054 fp -> old fp value
12055 return address within this function
12056 first argument to __morestack
12057 second argument to __morestack
12058 return address of caller of this function
12059 stack arguments
12060 So we add five words to get to the stack arguments.
12061 */
12072 }
12077 /* If this function calls va_start, we now have to set the scratch
12078 register for the case where we do not call __morestack. In this
12079 case we need to set it based on the stack pointer. */
12081 {
12088 }
12089 }
12091 /* We may have to tell the dataflow pass that the split stack prologue
12092 is initializing a scratch register. */
12094 static void
12096 {
12098 {
12101 }
12102 }
12103 \f
12104 /* Extract the parts of an RTL expression that is a valid memory address
12105 for an instruction. Return 0 if the structure of the address is
12106 grossly off. Return -1 if the address contains ASHIFT, so it is not
12107 strictly valid, but still used for computing length of lea instruction. */
12109 int
12111 {
12116 rtx tmp;
12120 /* Allow zero-extended SImode addresses,
12121 they will be emitted with addr32 prefix. */
12123 {
12126 {
12130 }
12133 {
12140 }
12141 }
12143 /* Allow SImode subregs of DImode addresses,
12144 they will be emitted with addr32 prefix. */
12146 {
12149 {
12153 }
12154 }
12159 {
12162 else
12164 }
12166 {
12171 do
12172 {
12177 }
12184 {
12187 {
12212 /* FALLTHRU */
12216 && TARGET_TLS_DIRECT_SEG_REFS
12219 else
12226 /* FALLTHRU */
12233 else
12248 }
12249 }
12250 }
12252 {
12255 }
12257 {
12258 /* We're called for lea too, which implements ashift on occasion. */
12268 }
12269 else
12273 {
12275 ;
12278 ;
12279 else
12281 }
12283 /* Extract the integral value of scale. */
12285 {
12289 }
12294 /* Avoid useless 0 displacement. */
12298 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12303 {
12304 rtx tmp;
12307 }
12309 /* Special case: %ebp cannot be encoded as a base without a displacement.
12310 Similarly %r13. */
12312 && base_reg
12321 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12322 Avoid this by transforming to [%esi+0].
12323 Reload calls address legitimization without cfun defined, so we need
12324 to test cfun for being non-NULL. */
12330 /* Special case: encode reg+reg instead of reg*2. */
12334 /* Special case: scaling cannot be encoded without base or displacement. */
12345 }
12346 \f
12347 /* Return cost of the memory address x.
12348 For i386, it is better to use a complex address than let gcc copy
12349 the address into a reg and make a new pseudo. But not if the address
12350 requires to two regs - that would mean more pseudos with longer
12351 lifetimes. */
12352 static int
12354 addr_space_t as ATTRIBUTE_UNUSED,
12356 {
12368 /* Attempt to minimize number of registers in the address. */
12374 cost++;
12381 cost++;
12383 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12384 since it's predecode logic can't detect the length of instructions
12385 and it degenerates to vector decoded. Increase cost of such
12386 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12387 to split such addresses or even refuse such addresses at all.
12389 Following addressing modes are affected:
12390 [base+scale*index]
12391 [scale*index+disp]
12392 [base+index]
12394 The first and last case may be avoidable by explicitly coding the zero in
12395 memory address, but I don't have AMD-K6 machine handy to check this
12396 theory. */
12405 }
12406 \f
12407 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12408 this is used for to form addresses to local data when -fPIC is in
12409 use. */
12411 static bool
12413 {
12416 }
12418 /* Determine if a given RTX is a valid constant. We already know this
12419 satisfies CONSTANT_P. */
12421 static bool
12423 {
12425 {
12430 {
12434 }
12439 /* Only some unspecs are valid as "constants". */
12442 {
12458 }
12460 /* We must have drilled down to a symbol. */
12465 /* FALLTHRU */
12468 /* TLS symbols are never valid. */
12472 /* DLLIMPORT symbols are never valid. */
12477 #if TARGET_MACHO
12478 /* mdynamic-no-pic */
12481 #endif
12497 }
12499 /* Otherwise we handle everything else in the move patterns. */
12501 }
12503 /* Determine if it's legal to put X into the constant pool. This
12504 is not possible for the address of thread-local symbols, which
12505 is checked above. */
12507 static bool
12509 {
12510 /* We can always put integral constants and vectors in memory. */
12512 {
12520 }
12522 }
12524 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12525 otherwise zero. */
12527 static bool
12529 {
12535 }
12538 /* Nonzero if the constant value X is a legitimate general operand
12539 when generating PIC code. It is given that flag_pic is on and
12540 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12542 bool
12544 {
12545 rtx inner;
12548 {
12555 /* Only some unspecs are valid as "constants". */
12558 {
12571 }
12572 /* FALLTHRU */
12580 }
12581 }
12583 /* Determine if a given CONST RTX is a valid memory displacement
12584 in PIC mode. */
12586 bool
12588 {
12591 /* In 64bit mode we can allow direct addresses of symbols and labels
12592 when they are not dynamic symbols. */
12594 {
12598 {
12622 /* FALLTHRU */
12625 /* TLS references should always be enclosed in UNSPEC.
12626 The dllimported symbol needs always to be resolved. */
12632 {
12640 /* Function-symbols need to be resolved only for
12641 large-model.
12642 For the small-model we don't need to resolve anything
12643 here. */
12648 /* Non-external symbols don't need to be resolved for
12649 large, and medium-model. */
12654 }
12663 }
12664 }
12670 {
12671 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12672 of GOT tables. We should not need these anyway. */
12684 }
12688 {
12693 }
12702 {
12706 /* We need to check for both symbols and labels because VxWorks loads
12707 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12708 details. */
12712 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12713 While ABI specify also 32bit relocation but we don't produce it in
12714 small PIC model at all. */
12736 }
12739 }
12741 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12742 replace the input X, or the original X if no replacement is called for.
12743 The output parameter *WIN is 1 if the calling macro should goto WIN,
12744 0 if it should not. */
12746 bool
12751 {
12752 /* Reload can generate:
12754 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12755 (reg:DI 97))
12756 (reg:DI 2 cx))
12758 This RTX is rejected from ix86_legitimate_address_p due to
12759 non-strictness of base register 97. Following this rejection,
12760 reload pushes all three components into separate registers,
12761 creating invalid memory address RTX.
12763 Following code reloads only the invalid part of the
12764 memory address RTX. */
12770 {
12776 {
12781 }
12785 {
12790 }
12794 }
12797 }
12799 /* Determine if op is suitable RTX for an address register.
12800 Return naked register if a register or a register subreg is
12801 found, otherwise return NULL_RTX. */
12803 static rtx
12805 {
12808 /* Only SImode or DImode registers can form the address. */
12815 {
12823 /* Don't allow SUBREGs that span more than a word. It can
12824 lead to spill failures when the register is one word out
12825 of a two word structure. */
12829 /* Allow only SUBREGs of non-eliminable hard registers. */
12832 }
12834 /* Op is not a register. */
12836 }
12838 /* Recognizes RTL expressions that are valid memory addresses for an
12839 instruction. The MODE argument is the machine mode for the MEM
12840 expression that wants to use this address.
12842 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12843 convert common non-canonical forms to canonical form so that they will
12844 be recognized. */
12846 static bool
12849 {
12852 HOST_WIDE_INT scale;
12856 /* Decomposition failed. */
12865 /* Validate base register. */
12867 {
12875 /* Base is not valid. */
12877 }
12879 /* Validate index register. */
12881 {
12889 /* Index is not valid. */
12891 }
12893 /* Index and base should have the same mode. */
12898 /* Address override works only on the (%reg) part of %fs:(%reg). */
12904 /* Validate scale factor. */
12906 {
12908 /* Scale without index. */
12912 /* Scale is not a valid multiplier. */
12914 }
12916 /* Validate displacement. */
12918 {
12923 {
12924 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12925 used. While ABI specify also 32bit relocations, we don't produce
12926 them at all and use IP relative instead. */
12933 /* 64bit address unspec. */
12953 /* Invalid address unspec. */
12955 }
12958 && (flag_pic
12959 || (TARGET_MACHO
12960 #if TARGET_MACHO
12961 && MACHOPIC_INDIRECT
12963 #endif
12964 )))
12965 {
12967 is_legitimate_pic:
12969 {
12970 /* foo@dtpoff(%rX) is ok. */
12977 /* Non-constant pic memory reference. */
12979 }
12982 /* Displacement is an invalid pic construct. */
12984 #if TARGET_MACHO
12987 /* displacment must be referenced via non_lazy_pointer */
12989 #endif
12991 /* This code used to verify that a symbolic pic displacement
12992 includes the pic_offset_table_rtx register.
12994 While this is good idea, unfortunately these constructs may
12995 be created by "adds using lea" optimization for incorrect
12996 code like:
12998 int a;
12999 int foo(int i)
13000 {
13001 return *(&a+i);
13002 }
13004 This code is nonsensical, but results in addressing
13005 GOT table with pic_offset_table_rtx base. We can't
13006 just refuse it easily, since it gets matched by
13007 "addsi3" pattern, that later gets split to lea in the
13008 case output register differs from input. While this
13009 can be handled by separate addsi pattern for this case
13010 that never results in lea, this seems to be easier and
13011 correct fix for crash to disable this test. */
13012 }
13019 /* Displacement is not constant. */
13023 /* Displacement is out of range. */
13025 /* In x32 mode, constant addresses are sign extended to 64bit, so
13026 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13031 }
13033 /* Everything looks valid. */
13035 }
13037 /* Determine if a given RTX is a valid constant address. */
13039 bool
13041 {
13043 }
13044 \f
13045 /* Return a unique alias set for the GOT. */
13047 static alias_set_type
13049 {
13054 }
13056 /* Return a legitimate reference for ORIG (an address) using the
13057 register REG. If REG is 0, a new pseudo is generated.
13059 There are two types of references that must be handled:
13061 1. Global data references must load the address from the GOT, via
13062 the PIC reg. An insn is emitted to do this load, and the reg is
13063 returned.
13065 2. Static data references, constant pool addresses, and code labels
13066 compute the address as an offset from the GOT, whose base is in
13067 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13068 differentiate them from global data objects. The returned
13069 address is the PIC reg + an unspec constant.
13071 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13072 reg also appears in the address. */
13074 static rtx
13076 {
13080 #if TARGET_MACHO
13082 {
13085 /* Use the generic Mach-O PIC machinery. */
13087 }
13088 #endif
13091 {
13095 }
13101 {
13102 rtx tmpreg;
13103 /* This symbol may be referenced via a displacement from the PIC
13104 base address (@GOTOFF). */
13111 {
13113 UNSPEC_GOTOFF);
13115 }
13116 else
13121 else
13126 {
13130 }
13131 else
13133 }
13135 {
13136 /* This symbol may be referenced via a displacement from the PIC
13137 base address (@GOTOFF). */
13144 {
13146 UNSPEC_GOTOFF);
13148 }
13149 else
13155 {
13158 }
13159 }
13161 /* We can't use @GOTOFF for text labels on VxWorks;
13162 see gotoff_operand. */
13164 {
13169 /* For x64 PE-COFF there is no GOT table. So we use address
13170 directly. */
13172 {
13180 }
13182 {
13190 /* Use directly gen_movsi, otherwise the address is loaded
13191 into register for CSE. We don't want to CSE this addresses,
13192 instead we CSE addresses from the GOT table, so skip this. */
13195 }
13196 else
13197 {
13198 /* This symbol must be referenced via a load from the
13199 Global Offset Table (@GOT). */
13215 }
13216 }
13217 else
13218 {
13221 {
13223 {
13226 }
13227 else
13229 }
13231 {
13234 /* We must match stuff we generate before. Assume the only
13235 unspecs that can get here are ours. Not that we could do
13236 anything with them anyway.... */
13242 }
13244 {
13247 /* Check first to see if this is a constant offset from a @GOTOFF
13248 symbol reference. */
13251 {
13253 {
13257 UNSPEC_GOTOFF);
13263 {
13266 }
13267 }
13268 else
13269 {
13272 {
13276 }
13277 }
13278 }
13279 else
13280 {
13283 new_rtx
13287 {
13290 {
13293 new_rtx
13295 }
13296 else
13298 }
13299 else
13300 {
13303 {
13306 }
13308 }
13309 }
13310 }
13311 }
13313 }
13314 \f
13315 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13317 static rtx
13319 {
13323 {
13328 }
13334 }
13336 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13340 static rtx
13342 {
13344 {
13350 }
13353 {
13355 UNSPEC_PLTOFF);
13358 }
13361 }
13363 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13367 rtx
13369 {
13371 {
13372 ix86_tls_module_base_symbol
13377 }
13380 }
13382 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13383 false if we expect this to be used for a memory address and true if
13384 we expect to load the address into a register. */
13386 static rtx
13388 {
13394 /* Fall back to global dynamic model if tool chain cannot support local
13395 dynamic. */
13402 {
13407 {
13410 else
13411 {
13414 }
13415 }
13418 {
13421 else
13431 }
13432 else
13433 {
13437 {
13439 rtx insns;
13442 emit_call_insn
13452 }
13453 else
13455 }
13462 {
13465 else
13466 {
13469 }
13470 }
13473 {
13478 else
13484 }
13485 else
13486 {
13490 {
13495 emit_call_insn
13500 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13501 share the LD_BASE result with other LD model accesses. */
13503 UNSPEC_TLS_LD_BASE);
13507 }
13508 else
13510 }
13518 {
13525 }
13530 {
13532 {
13533 /* The Sun linker took the AMD64 TLS spec literally
13534 and can only handle %rax as destination of the
13535 initial executable code sequence. */
13540 }
13542 /* Generate DImode references to avoid %fs:(%reg32)
13543 problems and linker IE->LE relaxation bug. */
13547 }
13549 {
13554 }
13556 {
13560 }
13561 else
13562 {
13565 }
13575 {
13580 }
13581 else
13582 {
13586 }
13596 {
13600 }
13601 else
13602 {
13606 }
13611 }
13614 }
13616 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13617 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13618 unique refptr-DECL symbol corresponding to symbol DECL. */
13621 htab_t dllimport_map;
13623 static tree
13625 {
13632 tree to;
13633 rtx rtl;
13660 else
13673 {
13675 #ifdef SUB_TARGET_RECORD_STUB
13677 #endif
13678 }
13687 }
13689 /* Expand SYMBOL into its corresponding far-addresse symbol.
13690 WANT_REG is true if we require the result be a register. */
13692 static rtx
13694 {
13695 tree imp_decl;
13696 rtx x;
13705 }
13707 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13708 true if we require the result be a register. */
13710 static rtx
13712 {
13713 tree imp_decl;
13714 rtx x;
13723 }
13725 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13726 is true if we require the result be a register. */
13728 static rtx
13730 {
13735 {
13742 {
13745 }
13746 }
13762 {
13765 }
13767 }
13769 /* Try machine-dependent ways of modifying an illegitimate address
13770 to be legitimate. If we find one, return the new, valid address.
13771 This macro is used in only one place: `memory_address' in explow.c.
13773 OLDX is the address as it was before break_out_memory_refs was called.
13774 In some cases it is useful to look at this to decide what needs to be done.
13776 It is always safe for this macro to do nothing. It exists to recognize
13777 opportunities to optimize the output.
13779 For the 80386, we handle X+REG by loading X into a register R and
13780 using R+REG. R will go in a general reg and indexing will be used.
13781 However, if REG is a broken-out memory address or multiplication,
13782 nothing needs to be done because REG can certainly go in a general reg.
13784 When -fpic is used, special handling is needed for symbolic references.
13785 See comments by legitimize_pic_address in i386.c for details. */
13787 static rtx
13790 {
13801 {
13805 }
13808 {
13812 }
13817 #if TARGET_MACHO
13820 #endif
13822 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13826 {
13831 }
13834 {
13835 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13840 {
13846 }
13851 {
13857 }
13859 /* Put multiply first if it isn't already. */
13861 {
13866 }
13868 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13869 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13870 created by virtual register instantiation, register elimination, and
13871 similar optimizations. */
13873 {
13879 }
13881 /* Canonicalize
13882 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13883 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13888 {
13889 rtx constant;
13893 {
13896 }
13898 {
13901 }
13902 else
13906 {
13913 }
13914 }
13920 {
13923 }
13926 {
13929 }
13937 {
13940 }
13946 {
13950 {
13953 }
13957 }
13960 {
13964 {
13967 }
13971 }
13972 }
13975 }
13976 \f
13977 /* Print an integer constant expression in assembler syntax. Addition
13978 and subtraction are the only arithmetic that may appear in these
13979 expressions. FILE is the stdio stream to write to, X is the rtx, and
13980 CODE is the operand print code from the output string. */
13982 static void
13984 {
13988 {
13997 else
13998 {
14001 /* Mark the decl as referenced so that cgraph will
14002 output the function. */
14006 #if TARGET_MACHO
14010 #endif
14012 }
14020 /* FALLTHRU */
14031 /* This used to output parentheses around the expression,
14032 but that does not work on the 386 (either ATT or BSD assembler). */
14038 {
14039 /* We can use %d if the number is <32 bits and positive. */
14044 else
14046 }
14047 else
14048 /* We can't handle floating point constants;
14049 TARGET_PRINT_OPERAND must handle them. */
14054 /* Some assemblers need integer constants to appear first. */
14056 {
14060 }
14061 else
14062 {
14067 }
14082 {
14086 }
14091 {
14110 /* FIXME: This might be @TPOFF in Sun ld too. */
14119 else
14129 else
14135 #if TARGET_MACHO
14140 #endif
14144 }
14149 }
14150 }
14152 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14153 We need to emit DTP-relative relocations. */
14155 static void ATTRIBUTE_UNUSED
14157 {
14162 {
14170 }
14171 }
14173 /* Return true if X is a representation of the PIC register. This copes
14174 with calls from ix86_find_base_term, where the register might have
14175 been replaced by a cselib value. */
14177 static bool
14179 {
14183 else
14185 }
14187 /* Helper function for ix86_delegitimize_address.
14188 Attempt to delegitimize TLS local-exec accesses. */
14190 static rtx
14192 {
14217 {
14222 }
14228 }
14230 /* In the name of slightly smaller debug output, and to cater to
14231 general assembler lossage, recognize PIC+GOTOFF and turn it back
14232 into a direct symbol reference.
14234 On Darwin, this is necessary to avoid a crash, because Darwin
14235 has a different PIC label for each routine but the DWARF debugging
14236 information is not associated with any particular routine, so it's
14237 necessary to remove references to the PIC label from RTL stored by
14238 the DWARF output code. */
14240 static rtx
14242 {
14244 /* addend is NULL or some rtx if x is something+GOTOFF where
14245 something doesn't include the PIC register. */
14247 /* reg_addend is NULL or a multiple of some register. */
14249 /* const_addend is NULL or a const_int. */
14251 /* This is the result, or NULL. */
14260 {
14267 {
14273 }
14280 {
14283 {
14288 }
14290 }
14295 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14296 and -mcmodel=medium -fpic. */
14297 }
14304 /* %ebx + GOT/GOTOFF */
14305 ;
14307 {
14308 /* %ebx + %reg * scale + GOT/GOTOFF */
14314 else
14315 {
14318 }
14319 }
14320 else
14326 {
14329 }
14350 {
14351 /* If the rest of original X doesn't involve the PIC register, add
14352 addend and subtract pic_offset_table_rtx. This can happen e.g.
14353 for code like:
14354 leal (%ebx, %ecx, 4), %ecx
14355 ...
14356 movl foo@GOTOFF(%ecx), %edx
14357 in which case we return (%ecx - %ebx) + foo. */
14360 pic_offset_table_rtx),
14361 result);
14362 else
14364 }
14366 {
14370 }
14372 }
14374 /* If X is a machine specific address (i.e. a symbol or label being
14375 referenced as a displacement from the GOT implemented using an
14376 UNSPEC), then return the base term. Otherwise return X. */
14378 rtx
14380 {
14381 rtx term;
14384 {
14398 }
14401 }
14402 \f
14403 static void
14406 {
14410 {
14413 }
14418 {
14421 {
14440 }
14444 {
14463 }
14470 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14471 Those same assemblers have the same but opposite lossage on cmov. */
14474 else
14479 {
14492 }
14499 else
14504 {
14517 }
14524 else
14534 else
14545 }
14547 }
14549 /* Print the name of register X to FILE based on its machine mode and number.
14550 If CODE is 'w', pretend the mode is HImode.
14551 If CODE is 'b', pretend the mode is QImode.
14552 If CODE is 'k', pretend the mode is SImode.
14553 If CODE is 'q', pretend the mode is DImode.
14554 If CODE is 'x', pretend the mode is V4SFmode.
14555 If CODE is 't', pretend the mode is V8SFmode.
14556 If CODE is 'g', pretend the mode is V16SFmode.
14557 If CODE is 'h', pretend the reg is the 'high' byte register.
14558 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14559 If CODE is 'd', duplicate the operand for AVX instruction.
14560 */
14562 void
14564 {
14573 {
14577 }
14604 else
14607 /* Irritatingly, AMD extended registers use different naming convention
14608 from the normal registers: "r%d[bwd]" */
14610 {
14615 {
14629 /* no suffix */
14634 }
14636 }
14640 {
14643 {
14646 }
14647 /* FALLTHRU */
14653 /* FALLTHRU */
14656 normal:
14671 {
14676 }
14679 {
14684 }
14688 }
14692 {
14695 else
14697 }
14698 }
14700 /* Locate some local-dynamic symbol still in use by this function
14701 so that we can print its name in some tls_local_dynamic_base
14702 pattern. */
14704 static int
14706 {
14711 {
14714 }
14717 }
14721 {
14722 rtx insn;
14733 }
14735 /* Meaning of CODE:
14736 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14737 C -- print opcode suffix for set/cmov insn.
14738 c -- like C, but print reversed condition
14739 F,f -- likewise, but for floating-point.
14740 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14741 otherwise nothing
14742 R -- print embeded rounding and sae.
14743 r -- print only sae.
14744 z -- print the opcode suffix for the size of the current operand.
14745 Z -- likewise, with special suffixes for x87 instructions.
14746 * -- print a star (in certain assembler syntax)
14747 A -- print an absolute memory reference.
14748 E -- print address with DImode register names if TARGET_64BIT.
14749 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14750 s -- print a shift double count, followed by the assemblers argument
14751 delimiter.
14752 b -- print the QImode name of the register for the indicated operand.
14753 %b0 would print %al if operands[0] is reg 0.
14754 w -- likewise, print the HImode name of the register.
14755 k -- likewise, print the SImode name of the register.
14756 q -- likewise, print the DImode name of the register.
14757 x -- likewise, print the V4SFmode name of the register.
14758 t -- likewise, print the V8SFmode name of the register.
14759 g -- likewise, print the V16SFmode name of the register.
14760 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14761 y -- print "st(0)" instead of "st" as a register.
14762 d -- print duplicated register operand for AVX instruction.
14763 D -- print condition for SSE cmp instruction.
14764 P -- if PIC, print an @PLT suffix.
14765 p -- print raw symbol name.
14766 X -- don't print any sort of PIC '@' suffix for a symbol.
14767 & -- print some in-use local-dynamic symbol name.
14768 H -- print a memory address offset by 8; used for sse high-parts
14769 Y -- print condition for XOP pcom* instruction.
14770 + -- print a branch hint as 'cs' or 'ds' prefix
14771 ; -- print a semicolon (after prefixes due to bug in older gas).
14772 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14773 @ -- print a segment register of thread base pointer load
14774 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14775 */
14777 void
14779 {
14781 {
14783 {
14786 {
14792 /* Intel syntax. For absolute addresses, registers should not
14793 be surrounded by braces. */
14795 {
14800 }
14805 }
14811 /* Wrap address in an UNSPEC to declare special handling. */
14849 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14854 {
14868 output_operand_lossage
14871 }
14874 #endif
14879 {
14880 /* Opcodes don't get size suffixes if using Intel opcodes. */
14885 {
14903 output_operand_lossage
14906 }
14907 }
14910 warning
14912 /* FALLTHRU */
14915 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14920 {
14922 {
14924 #ifdef HAVE_AS_IX86_FILDS
14926 #endif
14934 #ifdef HAVE_AS_IX86_FILDQ
14936 #else
14938 #endif
14943 }
14944 }
14946 {
14947 /* 387 opcodes don't get size suffixes
14948 if the operands are registers. */
14953 {
14969 }
14970 }
14971 else
14972 {
14973 output_operand_lossage
14976 }
14978 output_operand_lossage
14999 {
15002 }
15007 {
15058 }
15062 /* Little bit of braindamage here. The SSE compare instructions
15063 does use completely different names for the comparisons that the
15064 fp conditional moves. */
15066 {
15069 {
15072 }
15078 {
15081 }
15087 {
15090 }
15099 {
15102 }
15108 {
15111 }
15117 {
15120 }
15131 }
15136 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15139 #endif
15144 {
15148 }
15152 file);
15157 {
15161 }
15162 /* It doesn't actually matter what mode we use here, as we're
15163 only going to use this for printing. */
15165 /* Output 'qword ptr' for intel assembler dialect. */
15174 #ifdef HAVE_AS_IX86_HLE
15176 #else
15178 #endif
15180 #ifdef HAVE_AS_IX86_HLE
15182 #else
15184 #endif
15185 /* We do not want to print value of the operand. */
15214 {
15229 }
15242 {
15247 else
15250 }
15253 {
15254 rtx x;
15263 {
15268 {
15270 bool cputaken
15273 /* Emit hints only in the case default branch prediction
15274 heuristics would fail. */
15276 {
15277 /* We use 3e (DS) prefix for taken branches and
15278 2e (CS) prefix for not taken branches. */
15281 else
15283 }
15284 }
15285 }
15287 }
15290 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15292 #endif
15299 /* The kernel uses a different segment register for performance
15300 reasons; a system call would not have to trash the userspace
15301 segment register, which would be expensive. */
15304 else
15319 }
15320 }
15326 {
15327 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15330 {
15333 {
15342 else
15349 }
15351 /* Check for explicit size override (codes 'b', 'w', 'k',
15352 'q' and 'x') */
15366 }
15369 /* Avoid (%rip) for call operands. */
15375 else
15377 }
15380 {
15381 REAL_VALUE_TYPE r;
15389 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15393 else
15395 }
15398 {
15399 REAL_VALUE_TYPE r;
15408 }
15410 /* These float cases don't actually occur as immediate operands. */
15412 {
15417 }
15419 else
15420 {
15421 /* We have patterns that allow zero sets of memory, for instance.
15422 In 64-bit mode, we should probably support all 8-byte vectors,
15423 since we can in fact encode that into an immediate. */
15425 {
15428 }
15431 {
15433 {
15436 }
15439 {
15442 else
15444 }
15445 }
15450 else
15452 }
15453 }
15455 static bool
15457 {
15460 }
15461 \f
15462 /* Print a memory operand whose address is ADDR. */
15464 static void
15466 {
15475 {
15482 }
15484 {
15488 }
15489 else
15500 {
15511 }
15513 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15515 {
15527 }
15529 {
15530 /* Displacement only requires special attention. */
15533 {
15537 }
15540 else
15542 }
15543 else
15544 {
15545 /* Print SImode register names to force addr32 prefix. */
15547 {
15548 #ifdef ENABLE_CHECKING
15551 {
15562 }
15563 #endif
15566 }
15568 && TARGET_X32
15569 && disp
15572 {
15573 /* X32 runs in 64-bit mode, where displacement, DISP, in
15574 address DISP(%r64), is encoded as 32-bit immediate sign-
15575 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15576 address is %r64 + 0xffffffffbffffd00. When %r64 <
15577 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15578 which is invalid for x32. The correct address is %r64
15579 - 0x40000300 == 0xf7ffdd64. To properly encode
15580 -0x40000300(%r64) for x32, we zero-extend negative
15581 displacement by forcing addr32 prefix which truncates
15582 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15583 zero-extend all negative displacements, including -1(%rsp).
15584 However, for small negative displacements, sign-extension
15585 won't cause overflow. We only zero-extend negative
15586 displacements if they < -16*1024*1024, which is also used
15587 to check legitimate address displacements for PIC. */
15589 }
15592 {
15594 {
15599 else
15601 }
15607 {
15612 }
15614 }
15615 else
15616 {
15620 {
15621 /* Pull out the offset of a symbol; print any symbol itself. */
15625 {
15629 }
15637 else
15639 }
15643 {
15646 {
15650 }
15651 }
15654 else
15658 {
15663 }
15665 }
15666 }
15667 }
15669 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15671 static bool
15673 {
15674 rtx op;
15681 {
15684 /* FIXME: This might be @TPOFF in Sun ld. */
15695 else
15707 else
15714 #if TARGET_MACHO
15720 #endif
15723 {
15728 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15730 #else
15732 #endif
15735 }
15740 }
15743 }
15744 \f
15745 /* Split one or more double-mode RTL references into pairs of half-mode
15746 references. The RTL can be REG, offsettable MEM, integer constant, or
15747 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15748 split and "num" is its length. lo_half and hi_half are output arrays
15749 that parallel "operands". */
15751 void
15754 {
15759 {
15768 }
15773 {
15776 /* simplify_subreg refuse to split volatile memory addresses,
15777 but we still have to handle it. */
15779 {
15782 }
15783 else
15784 {
15791 }
15792 }
15793 }
15794 \f
15795 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15796 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15797 is the expression of the binary operation. The output may either be
15798 emitted here, or returned to the caller, like all output_* functions.
15800 There is no guarantee that the operands are the same mode, as they
15801 might be within FLOAT or FLOAT_EXTEND expressions. */
15803 #ifndef SYSV386_COMPAT
15804 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15805 wants to fix the assemblers because that causes incompatibility
15806 with gcc. No-one wants to fix gcc because that causes
15807 incompatibility with assemblers... You can use the option of
15808 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15809 #define SYSV386_COMPAT 1
15810 #endif
15814 {
15820 #ifdef ENABLE_CHECKING
15821 /* Even if we do not want to check the inputs, this documents input
15822 constraints. Which helps in understanding the following code. */
15832 else
15834 #endif
15837 {
15842 else
15851 else
15860 else
15869 else
15876 }
15879 {
15881 {
15885 else
15887 }
15888 else
15889 {
15893 else
15895 }
15897 }
15901 {
15905 {
15909 }
15911 /* know operands[0] == operands[1]. */
15914 {
15917 }
15920 {
15922 /* How is it that we are storing to a dead operand[2]?
15923 Well, presumably operands[1] is dead too. We can't
15924 store the result to st(0) as st(0) gets popped on this
15925 instruction. Instead store to operands[2] (which I
15926 think has to be st(1)). st(1) will be popped later.
15927 gcc <= 2.8.1 didn't have this check and generated
15928 assembly code that the Unixware assembler rejected. */
15930 else
15933 }
15937 else
15944 {
15947 }
15950 {
15953 }
15956 {
15957 #if SYSV386_COMPAT
15958 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15959 derived assemblers, confusingly reverse the direction of
15960 the operation for fsub{r} and fdiv{r} when the
15961 destination register is not st(0). The Intel assembler
15962 doesn't have this brain damage. Read !SYSV386_COMPAT to
15963 figure out what the hardware really does. */
15966 else
15968 #else
15970 /* As above for fmul/fadd, we can't store to st(0). */
15972 else
15974 #endif
15976 }
15979 {
15980 #if SYSV386_COMPAT
15983 else
15985 #else
15988 else
15990 #endif
15992 }
15995 {
15998 else
16001 }
16003 {
16004 #if SYSV386_COMPAT
16006 #else
16008 #endif
16009 }
16010 else
16011 {
16012 #if SYSV386_COMPAT
16014 #else
16016 #endif
16017 }
16022 }
16026 }
16028 /* Check if a 256bit AVX register is referenced inside of EXP. */
16030 static int
16032 {
16043 }
16045 /* Return needed mode for entity in optimize_mode_switching pass. */
16047 static int
16049 {
16051 {
16052 rtx link;
16054 /* Needed mode is set to AVX_U128_CLEAN if there are
16055 no 256bit modes used in function arguments. */
16057 link;
16059 {
16061 {
16066 }
16067 }
16070 }
16072 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16073 changes state only when a 256bit register is written to, but we need
16074 to prevent the compiler from moving optimal insertion point above
16075 eventual read from 256bit register. */
16080 }
16082 /* Return mode that i387 must be switched into
16083 prior to the execution of insn. */
16085 static int
16087 {
16090 /* The mode UNINITIALIZED is used to store control word after a
16091 function call or ASM pattern. The mode ANY specify that function
16092 has no requirements on the control word and make no changes in the
16093 bits we are interested in. */
16107 {
16130 }
16133 }
16135 /* Return mode that entity must be switched into
16136 prior to the execution of insn. */
16138 int
16140 {
16142 {
16152 }
16154 }
16156 /* Check if a 256bit AVX register is referenced in stores. */
16158 static void
16160 {
16162 {
16165 }
16166 }
16168 /* Calculate mode of upper 128bit AVX registers after the insn. */
16170 static int
16172 {
16179 /* We know that state is clean after CALL insn if there are no
16180 256bit registers used in the function return register. */
16182 {
16187 }
16189 /* Otherwise, return current mode. Remember that if insn
16190 references AVX 256bit registers, the mode was already changed
16191 to DIRTY from MODE_NEEDED. */
16193 }
16195 /* Return the mode that an insn results in. */
16197 int
16199 {
16201 {
16211 }
16212 }
16214 static int
16216 {
16217 tree arg;
16219 /* Entry mode is set to AVX_U128_DIRTY if there are
16220 256bit modes used in function arguments. */
16223 {
16228 }
16231 }
16233 /* Return a mode that ENTITY is assumed to be
16234 switched to at function entry. */
16236 int
16238 {
16240 {
16250 }
16251 }
16253 static int
16255 {
16258 /* Exit mode is set to AVX_U128_DIRTY if there are
16259 256bit modes used in the function return register. */
16264 }
16266 /* Return a mode that ENTITY is assumed to be
16267 switched to at function exit. */
16269 int
16271 {
16273 {
16283 }
16284 }
16286 /* Output code to initialize control word copies used by trunc?f?i and
16287 rounding patterns. CURRENT_MODE is set to current control word,
16288 while NEW_MODE is set to new control word. */
16290 static void
16292 {
16294 rtx new_mode;
16305 {
16307 {
16309 /* round toward zero (truncate) */
16315 /* round down toward -oo */
16322 /* round up toward +oo */
16329 /* mask precision exception for nearbyint() */
16336 }
16337 }
16338 else
16339 {
16341 {
16343 /* round toward zero (truncate) */
16349 /* round down toward -oo */
16355 /* round up toward +oo */
16361 /* mask precision exception for nearbyint() */
16368 }
16369 }
16375 }
16377 /* Emit vzeroupper. */
16379 void
16381 {
16384 /* Cancel automatic vzeroupper insertion if there are
16385 live call-saved SSE registers at the insertion point. */
16397 }
16399 /* Generate one or more insns to set ENTITY to MODE. */
16401 void
16403 {
16405 {
16420 }
16421 }
16423 /* Output code for INSN to convert a float to a signed int. OPERANDS
16424 are the insn operands. The output may be [HSD]Imode and the input
16425 operand may be [SDX]Fmode. */
16429 {
16434 /* Jump through a hoop or two for DImode, since the hardware has no
16435 non-popping instruction. We used to do this a different way, but
16436 that was somewhat fragile and broke with post-reload splitters. */
16446 else
16447 {
16452 else
16456 }
16459 }
16461 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16462 have the values zero or one, indicates the ffreep insn's operand
16463 from the OPERANDS array. */
16467 {
16469 #ifdef HAVE_AS_IX86_FFREEP
16471 #else
16472 {
16482 }
16483 #endif
16486 }
16489 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16490 should be used. UNORDERED_P is true when fucom should be used. */
16494 {
16500 {
16503 }
16504 else
16505 {
16508 }
16511 {
16515 else
16517 else
16520 else
16522 }
16529 {
16531 {
16534 }
16535 else
16537 }
16540 && stack_top_dies
16543 {
16544 /* If both the top of the 387 stack dies, and the other operand
16545 is also a stack register that dies, then this must be a
16546 `fcompp' float compare */
16549 {
16550 /* There is no double popping fcomi variant. Fortunately,
16551 eflags is immune from the fstp's cc clobbering. */
16554 else
16557 }
16558 else
16559 {
16562 else
16564 }
16565 }
16566 else
16567 {
16568 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16571 {
16579 NULL,
16580 NULL,
16587 NULL,
16588 NULL,
16589 NULL,
16590 NULL
16591 };
16606 }
16607 }
16609 void
16611 {
16614 #ifdef ASM_QUAD
16617 #else
16619 #endif
16622 }
16624 void
16626 {
16629 #ifdef ASM_QUAD
16632 #else
16634 #endif
16635 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16641 #if TARGET_MACHO
16643 {
16647 }
16648 #endif
16649 else
16652 }
16653 \f
16654 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16655 for the target. */
16657 void
16659 {
16660 rtx tmp;
16662 /* We play register width games, which are only valid after reload. */
16665 /* Avoid HImode and its attendant prefix byte. */
16670 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16672 {
16675 }
16678 }
16680 /* X is an unchanging MEM. If it is a constant pool reference, return
16681 the constant pool rtx, else NULL. */
16683 rtx
16685 {
16692 }
16694 void
16696 {
16704 {
16705 rtx tmp;
16709 {
16715 }
16718 }
16722 {
16725 rtx tmp;
16730 else
16734 {
16741 }
16742 }
16746 {
16748 {
16749 #if TARGET_MACHO
16750 /* dynamic-no-pic */
16752 {
16753 rtx temp = ((reload_in_progress
16761 }
16763 {
16767 }
16770 else
16771 {
16779 }
16780 /* dynamic-no-pic */
16781 #endif
16782 }
16783 else
16784 {
16788 {
16794 }
16795 }
16796 }
16797 else
16798 {
16809 /* Force large constants in 64bit compilation into register
16810 to get them CSEed. */
16822 {
16823 /* If we are loading a floating point constant to a register,
16824 force the value to memory now, since we'll get better code
16825 out the back end. */
16829 {
16834 }
16835 }
16836 }
16839 }
16841 void
16843 {
16850 /* Force constants other than zero into memory. We do not know how
16851 the instructions used to build constants modify the upper 64 bits
16852 of the register, once we have that information we may be able
16853 to handle some of them more efficiently. */
16862 /* We need to check memory alignment for SSE mode since attribute
16863 can make operands unaligned. */
16868 {
16871 /* ix86_expand_vector_move_misalign() does not like constants ... */
16877 /* ... nor both arguments in memory. */
16885 }
16887 /* Make operand1 a register if it isn't already. */
16891 {
16894 }
16897 }
16899 /* Split 32-byte AVX unaligned load and store if needed. */
16901 static void
16903 {
16904 rtx m;
16911 {
16932 }
16935 {
16937 {
16944 }
16945 /* Normal *mov<mode>_internal pattern will handle
16946 unaligned loads just fine if misaligned_operand
16947 is true, and without the UNSPEC it can be combined
16948 with arithmetic instructions. */
16951 else
16953 }
16955 {
16957 {
16962 }
16963 else
16965 }
16966 else
16968 }
16970 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16971 straight to ix86_expand_vector_move. */
16972 /* Code generation for scalar reg-reg moves of single and double precision data:
16973 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16974 movaps reg, reg
16975 else
16976 movss reg, reg
16977 if (x86_sse_partial_reg_dependency == true)
16978 movapd reg, reg
16979 else
16980 movsd reg, reg
16982 Code generation for scalar loads of double precision data:
16983 if (x86_sse_split_regs == true)
16984 movlpd mem, reg (gas syntax)
16985 else
16986 movsd mem, reg
16988 Code generation for unaligned packed loads of single precision data
16989 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16990 if (x86_sse_unaligned_move_optimal)
16991 movups mem, reg
16993 if (x86_sse_partial_reg_dependency == true)
16994 {
16995 xorps reg, reg
16996 movlps mem, reg
16997 movhps mem+8, reg
16998 }
16999 else
17000 {
17001 movlps mem, reg
17002 movhps mem+8, reg
17003 }
17005 Code generation for unaligned packed loads of double precision data
17006 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17007 if (x86_sse_unaligned_move_optimal)
17008 movupd mem, reg
17010 if (x86_sse_split_regs == true)
17011 {
17012 movlpd mem, reg
17013 movhpd mem+8, reg
17014 }
17015 else
17016 {
17017 movsd mem, reg
17018 movhpd mem+8, reg
17019 }
17020 */
17022 void
17024 {
17033 {
17035 {
17039 {
17041 {
17044 }
17045 else
17047 }
17049 /* FALLTHRU */
17053 {
17068 }
17074 else
17082 }
17085 }
17089 {
17091 {
17095 {
17097 {
17100 }
17101 else
17103 }
17105 /* FALLTHRU */
17115 }
17118 }
17121 {
17122 /* Normal *mov<mode>_internal pattern will handle
17123 unaligned loads just fine if misaligned_operand
17124 is true, and without the UNSPEC it can be combined
17125 with arithmetic instructions. */
17131 /* ??? If we have typed data, then it would appear that using
17132 movdqu is the only way to get unaligned data loaded with
17133 integer type. */
17135 {
17137 {
17140 }
17142 /* We will eventually emit movups based on insn attributes. */
17146 }
17148 {
17149 rtx zero;
17152 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17153 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17155 {
17156 /* We will eventually emit movups based on insn attributes. */
17159 }
17161 /* When SSE registers are split into halves, we can avoid
17162 writing to the top half twice. */
17164 {
17167 }
17168 else
17169 {
17170 /* ??? Not sure about the best option for the Intel chips.
17171 The following would seem to satisfy; the register is
17172 entirely cleared, breaking the dependency chain. We
17173 then store to the upper half, with a dependency depth
17174 of one. A rumor has it that Intel recommends two movsd
17175 followed by an unpacklpd, but this is unconfirmed. And
17176 given that the dependency depth of the unpacklpd would
17177 still be one, I'm not sure why this would be better. */
17179 }
17185 }
17186 else
17187 {
17188 rtx t;
17191 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17192 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17194 {
17196 {
17199 }
17206 }
17210 else
17215 else
17224 }
17225 }
17227 {
17229 {
17232 /* We will eventually emit movups based on insn attributes. */
17234 }
17236 {
17238 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17239 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17241 /* We will eventually emit movups based on insn attributes. */
17243 else
17244 {
17249 }
17250 }
17251 else
17252 {
17257 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17258 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17260 {
17263 }
17264 else
17265 {
17270 }
17271 }
17272 }
17273 else
17275 }
17277 /* Helper function of ix86_fixup_binary_operands to canonicalize
17278 operand order. Returns true if the operands should be swapped. */
17280 static bool
17282 rtx operands[])
17283 {
17288 /* If the operation is not commutative, we can't do anything. */
17292 /* Highest priority is that src1 should match dst. */
17298 /* Next highest priority is that immediate constants come second. */
17304 /* Lowest priority is that memory references should come second. */
17311 }
17314 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17315 destination to use for the operation. If different from the true
17316 destination in operands[0], a copy operation will be required. */
17318 rtx
17320 rtx operands[])
17321 {
17326 /* Canonicalize operand order. */
17328 {
17329 rtx temp;
17331 /* It is invalid to swap operands of different modes. */
17337 }
17339 /* Both source operands cannot be in memory. */
17341 {
17342 /* Optimization: Only read from memory once. */
17344 {
17347 }
17350 else
17352 }
17354 /* If the destination is memory, and we do not have matching source
17355 operands, do things in registers. */
17359 /* Source 1 cannot be a constant. */
17363 /* Source 1 cannot be a non-matching memory. */
17367 /* Improve address combine. */
17376 }
17378 /* Similarly, but assume that the destination has already been
17379 set up properly. */
17381 void
17384 {
17387 }
17389 /* Attempt to expand a binary operator. Make the expansion closer to the
17390 actual machine, then just general_operand, which will allow 3 separate
17391 memory references (one output, two input) in a single insn. */
17393 void
17395 rtx operands[])
17396 {
17403 /* Emit the instruction. */
17407 {
17408 /* Reload doesn't know about the flags register, and doesn't know that
17409 it doesn't want to clobber it. We can only do this with PLUS. */
17412 }
17416 {
17417 /* This is going to be an LEA; avoid splitting it later. */
17419 }
17420 else
17421 {
17424 }
17426 /* Fix up the destination if needed. */
17429 }
17431 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17432 the given OPERANDS. */
17434 void
17436 rtx operands[])
17437 {
17440 {
17443 }
17445 {
17448 }
17449 /* Optimize (__m128i) d | (__m128i) e and similar code
17450 when d and e are float vectors into float vector logical
17451 insn. In C/C++ without using intrinsics there is no other way
17452 to express vector logical operation on float vectors than
17453 to cast them temporarily to integer vectors. */
17455 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17464 {
17465 rtx dst;
17467 {
17474 {
17477 }
17478 else
17479 {
17484 }
17495 }
17496 }
17505 }
17507 /* Return TRUE or FALSE depending on whether the binary operator meets the
17508 appropriate constraints. */
17510 bool
17513 {
17518 /* Both source operands cannot be in memory. */
17522 /* Canonicalize operand order for commutative operators. */
17524 {
17528 }
17530 /* If the destination is memory, we must have a matching source operand. */
17534 /* Source 1 cannot be a constant. */
17538 /* Source 1 cannot be a non-matching memory. */
17540 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17548 }
17550 /* Attempt to expand a unary operator. Make the expansion closer to the
17551 actual machine, then just general_operand, which will allow 2 separate
17552 memory references (one output, one input) in a single insn. */
17554 void
17556 rtx operands[])
17557 {
17564 /* If the destination is memory, and we do not have matching source
17565 operands, do things in registers. */
17568 {
17571 else
17573 }
17575 /* When source operand is memory, destination must match. */
17579 /* Emit the instruction. */
17583 {
17584 /* Reload doesn't know about the flags register, and doesn't know that
17585 it doesn't want to clobber it. */
17588 }
17589 else
17590 {
17593 }
17595 /* Fix up the destination if needed. */
17598 }
17600 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17601 divisor are within the range [0-255]. */
17603 void
17606 {
17615 {
17628 }
17635 /* Use 8bit unsigned divimod if dividend and divisor are within
17636 the range [0-255]. */
17645 pc_rtx);
17650 /* Generate original signed/unsigned divimod. */
17655 /* Branch to the end. */
17659 /* Generate 8bit unsigned divide. */
17661 /* Don't use operands[0] for result of 8bit divide since not all
17662 registers support QImode ZERO_EXTRACT. */
17669 {
17672 }
17673 else
17674 {
17677 }
17679 /* Extract remainder from AH. */
17683 else
17684 {
17685 /* Need a new scratch register since the old one has result
17686 of 8bit divide. */
17690 }
17693 /* Zero extend quotient from AL. */
17699 }
17701 /* Whether it is OK to emit CFI directives when emitting asm code. */
17703 bool
17705 {
17707 }
17709 #define LEA_MAX_STALL (3)
17710 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17712 /* Increase given DISTANCE in half-cycles according to
17713 dependencies between PREV and NEXT instructions.
17714 Add 1 half-cycle if there is no dependency and
17715 go to next cycle if there is some dependecy. */
17717 static unsigned int
17719 {
17736 }
17738 /* Function checks if instruction INSN defines register number
17739 REGNO1 or REGNO2. */
17741 static bool
17743 rtx insn)
17744 {
17752 {
17754 }
17757 }
17759 /* Function checks if instruction INSN uses register number
17760 REGNO as a part of address expression. */
17762 static bool
17764 {
17772 }
17774 /* Search backward for non-agu definition of register number REGNO1
17775 or register number REGNO2 in basic block starting from instruction
17776 START up to head of basic block or instruction INSN.
17778 Function puts true value into *FOUND var if definition was found
17779 and false otherwise.
17781 Distance in half-cycles between START and found instruction or head
17782 of BB is added to DISTANCE and returned. */
17784 static int
17788 {
17798 {
17800 {
17803 {
17806 {
17809 }
17810 }
17813 }
17818 }
17821 }
17823 /* Search backward for non-agu definition of register number REGNO1
17824 or register number REGNO2 in INSN's basic block until
17825 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17826 2. Reach neighbour BBs boundary, or
17827 3. Reach agu definition.
17828 Returns the distance between the non-agu definition point and INSN.
17829 If no definition point, returns -1. */
17831 static int
17833 rtx insn)
17834 {
17845 {
17846 edge e;
17847 edge_iterator ei;
17852 {
17855 }
17861 else
17862 {
17867 {
17868 int bb_dist
17874 {
17881 }
17882 }
17885 }
17886 }
17888 /* get_attr_type may modify recog data. We want to make sure
17889 that recog data is valid for instruction INSN, on which
17890 distance_non_agu_define is called. INSN is unchanged here. */
17897 }
17899 /* Return the distance in half-cycles between INSN and the next
17900 insn that uses register number REGNO in memory address added
17901 to DISTANCE. Return -1 if REGNO0 is set.
17903 Put true value into *FOUND if register usage was found and
17904 false otherwise.
17905 Put true value into *REDEFINED if register redefinition was
17906 found and false otherwise. */
17908 static int
17912 {
17921 {
17924 /* If insn and start belong to the same bb, set prev to insn,
17925 so the call to increase_distance will increase the distance
17926 between insns by 1. */
17928 }
17933 {
17935 {
17938 {
17939 /* Return DISTANCE if OP0 is used in memory
17940 address in NEXT. */
17943 }
17946 {
17947 /* Return -1 if OP0 is set in NEXT. */
17950 }
17953 }
17959 }
17962 }
17964 /* Return the distance between INSN and the next insn that uses
17965 register number REGNO0 in memory address. Return -1 if no such
17966 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17968 static int
17970 {
17982 {
17983 edge e;
17984 edge_iterator ei;
17989 {
17992 }
17998 else
17999 {
18005 {
18006 int bb_dist
18011 {
18018 }
18019 }
18022 }
18023 }
18029 }
18031 /* Define this macro to tune LEA priority vs ADD, it take effect when
18032 there is a dilemma of choicing LEA or ADD
18033 Negative value: ADD is more preferred than LEA
18034 Zero: Netrual
18035 Positive value: LEA is more preferred than ADD*/
18036 #define IX86_LEA_PRIORITY 0
18038 /* Return true if usage of lea INSN has performance advantage
18039 over a sequence of instructions. Instructions sequence has
18040 SPLIT_COST cycles higher latency than lea latency. */
18042 static bool
18045 {
18048 /* For Silvermont if using a 2-source or 3-source LEA for
18049 non-destructive destination purposes, or due to wanting
18050 ability to use SCALE, the use of LEA is justified. */
18052 {
18060 }
18066 {
18067 /* If there is no non AGU operand definition, no AGU
18068 operand usage and split cost is 0 then both lea
18069 and non lea variants have same priority. Currently
18070 we prefer lea for 64 bit code and non lea on 32 bit
18071 code. */
18074 else
18076 }
18078 /* With longer definitions distance lea is more preferable.
18079 Here we change it to take into account splitting cost and
18080 lea priority. */
18083 /* If there is no use in memory addess then we just check
18084 that split cost exceeds AGU stall. */
18088 /* If this insn has both backward non-agu dependence and forward
18089 agu dependence, the one with short distance takes effect. */
18091 }
18093 /* Return true if it is legal to clobber flags by INSN and
18094 false otherwise. */
18096 static bool
18098 {
18101 bitmap live;
18104 {
18106 {
18113 }
18119 }
18123 }
18125 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18126 move and add to avoid AGU stalls. */
18128 bool
18130 {
18133 /* Check if we need to optimize. */
18137 /* Check it is correct to split here. */
18145 /* We need to split only adds with non destructive
18146 destination operand. */
18149 else
18151 }
18153 /* Return true if we should emit lea instruction instead of mov
18154 instruction. */
18156 bool
18158 {
18161 /* Check if we need to optimize. */
18165 /* Use lea for reg to reg moves only. */
18173 }
18175 /* Return true if we need to split lea into a sequence of
18176 instructions to avoid AGU stalls. */
18178 bool
18180 {
18186 /* Check we need to optimize. */
18190 /* The "at least two components" test below might not catch simple
18191 move or zero extension insns if parts.base is non-NULL and parts.disp
18192 is const0_rtx as the only components in the address, e.g. if the
18193 register is %rbp or %r13. As this test is much cheaper and moves or
18194 zero extensions are the common case, do this check first. */
18200 /* Check if it is OK to split here. */
18207 /* There should be at least two components in the address. */
18212 /* We should not split into add if non legitimate pic
18213 operand is used as displacement. */
18228 /* Compute how many cycles we will add to execution time
18229 if split lea into a sequence of instructions. */
18231 {
18232 /* Have to use mov instruction if non desctructive
18233 destination form is used. */
18237 /* Have to add index to base if both exist. */
18241 /* Have to use shift and adds if scale is 2 or greater. */
18243 {
18248 else
18250 }
18252 /* Have to use add instruction with immediate if
18253 disp is non zero. */
18257 /* Subtract the price of lea. */
18259 }
18263 }
18265 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18266 matches destination. RTX includes clobber of FLAGS_REG. */
18268 static void
18271 {
18278 }
18280 /* Return true if regno1 def is nearest to the insn. */
18282 static bool
18284 {
18291 {
18293 {
18296 }
18302 }
18304 /* None of the regs is defined in the bb. */
18306 }
18308 /* Split lea instructions into a sequence of instructions
18309 which are executed on ALU to avoid AGU stalls.
18310 It is assumed that it is allowed to clobber flags register
18311 at lea position. */
18313 void
18315 {
18331 {
18334 }
18337 {
18340 }
18346 {
18347 /* Case r1 = r1 + ... */
18349 {
18350 /* If we have a case r1 = r1 + C * r2 then we
18351 should use multiplication which is very
18352 expensive. Assume cost model is wrong if we
18353 have such case here. */
18358 }
18359 else
18360 {
18361 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18365 /* Use shift for scaling. */
18374 }
18375 }
18377 {
18380 }
18381 else
18382 {
18384 {
18387 }
18389 {
18392 }
18393 else
18394 {
18399 else
18400 {
18401 rtx tmp1;
18403 /* Find better operand for SET instruction, depending
18404 on which definition is farther from the insn. */
18407 else
18417 }
18420 }
18424 }
18425 }
18427 /* Return true if it is ok to optimize an ADD operation to LEA
18428 operation to avoid flag register consumation. For most processors,
18429 ADD is faster than LEA. For the processors like BONNELL, if the
18430 destination register of LEA holds an actual address which will be
18431 used soon, LEA is better and otherwise ADD is better. */
18433 bool
18435 {
18440 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18448 }
18450 /* Return true if destination reg of SET_BODY is shift count of
18451 USE_BODY. */
18453 static bool
18455 {
18456 rtx set_dest;
18457 rtx shift_rtx;
18460 /* Retrieve destination of SET_BODY. */
18462 {
18471 use_body))
18476 }
18478 /* Retrieve shift count of USE_BODY. */
18480 {
18492 }
18500 {
18503 /* Return true if shift count is dest of SET_BODY. */
18505 {
18506 /* Add check since it can be invoked before register
18507 allocation in pre-reload schedule. */
18513 }
18514 }
18517 }
18519 /* Return true if destination reg of SET_INSN is shift count of
18520 USE_INSN. */
18522 bool
18524 {
18527 }
18529 /* Return TRUE or FALSE depending on whether the unary operator meets the
18530 appropriate constraints. */
18532 bool
18536 {
18537 /* If one of operands is memory, source and destination must match. */
18543 }
18545 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18546 are ok, keeping in mind the possible movddup alternative. */
18548 bool
18550 {
18556 }
18558 /* Post-reload splitter for converting an SF or DFmode value in an
18559 SSE register into an unsigned SImode. */
18561 void
18563 {
18574 /* Load up the value into the low element. We must ensure that the other
18575 elements are valid floats -- zero is the easiest such value. */
18577 {
18580 else
18582 }
18583 else
18584 {
18589 else
18591 }
18611 else
18616 }
18618 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18619 Expects the 64-bit DImode to be supplied in a pair of integral
18620 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18621 -mfpmath=sse, !optimize_size only. */
18623 void
18625 {
18629 rtx x;
18635 {
18638 }
18639 else
18640 {
18644 }
18652 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18655 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18656 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18657 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18658 (0x1.0p84 + double(fp_value_hi_xmm)).
18659 Note these exponents differ by 32. */
18663 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18664 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18673 /* Add the upper and lower DFmode values together. */
18676 else
18677 {
18681 }
18684 }
18686 /* Not used, but eases macroization of patterns. */
18687 void
18689 rtx input ATTRIBUTE_UNUSED)
18690 {
18692 }
18694 /* Convert an unsigned SImode value into a DFmode. Only currently used
18695 for SSE, but applicable anywhere. */
18697 void
18699 {
18700 REAL_VALUE_TYPE TWO31r;
18715 }
18717 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18718 32-bit mode; otherwise we have a direct convert instruction. */
18720 void
18722 {
18723 REAL_VALUE_TYPE TWO32r;
18741 }
18743 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18744 For x86_32, -mfpmath=sse, !optimize_size only. */
18745 void
18747 {
18748 REAL_VALUE_TYPE ONE16r;
18767 }
18769 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18770 a vector of unsigned ints VAL to vector of floats TARGET. */
18772 void
18774 {
18776 REAL_VALUE_TYPE TWO16r;
18783 else
18788 OPTAB_DIRECT);
18799 OPTAB_DIRECT);
18801 OPTAB_DIRECT);
18804 }
18806 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18807 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18808 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18809 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18811 rtx
18813 {
18814 REAL_VALUE_TYPE TWO31r;
18829 {
18835 }
18844 OPTAB_DIRECT);
18845 else
18846 {
18852 OPTAB_DIRECT);
18853 }
18856 }
18858 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18859 then replicate the value for all elements of the vector
18860 register. */
18862 rtx
18864 {
18866 rtvec v;
18870 {
18903 }
18904 }
18906 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18907 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18908 for an SSE register. If VECT is true, then replicate the mask for
18909 all elements of the vector register. If INVERT is true, then create
18910 a mask excluding the sign bit. */
18912 rtx
18914 {
18918 rtx v;
18919 rtx mask;
18921 /* Find the sign bit, sign extended to 2*HWI. */
18923 {
18947 else
18955 {
18958 }
18959 else
18960 {
18961 rtvec vec;
18967 {
18970 }
18971 else
18981 }
18986 }
18991 /* Force this value into the low part of a fp vector constant. */
19000 }
19002 /* Generate code for floating point ABS or NEG. */
19004 void
19006 rtx operands[])
19007 {
19018 {
19024 }
19026 /* NEG and ABS performed with SSE use bitwise mask operations.
19027 Create the appropriate mask now. */
19030 else
19040 {
19042 rtvec par;
19047 else
19048 {
19051 }
19053 }
19054 else
19056 }
19058 /* Expand a copysign operation. Special case operand 0 being a constant. */
19060 void
19062 {
19076 else
19080 {
19087 {
19090 else
19091 {
19095 }
19096 }
19106 else
19110 }
19111 else
19112 {
19122 else
19126 }
19127 }
19129 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19130 be a constant, and so has already been expanded into a vector constant. */
19132 void
19134 {
19150 {
19153 }
19154 }
19156 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19157 so we have to do two masks. */
19159 void
19161 {
19176 {
19177 /* Shouldn't happen often (it's useless, obviously), but when it does
19178 we'd generate incorrect code if we continue below. */
19181 }
19184 {
19195 }
19196 else
19197 {
19199 {
19201 }
19203 {
19207 }
19211 {
19214 }
19216 {
19221 }
19223 }
19227 }
19229 /* Return TRUE or FALSE depending on whether the first SET in INSN
19230 has source and destination with matching CC modes, and that the
19231 CC mode is at least as constrained as REQ_MODE. */
19233 bool
19235 {
19236 rtx set;
19247 {
19257 /* FALLTHRU */
19261 /* FALLTHRU */
19265 /* FALLTHRU */
19279 }
19282 }
19284 /* Generate insn patterns to do an integer compare of OPERANDS. */
19286 static rtx
19288 {
19295 /* This is very simple, but making the interface the same as in the
19296 FP case makes the rest of the code easier. */
19300 /* Return the test that should be put into the flags user, i.e.
19301 the bcc, scc, or cmov instruction. */
19303 }
19305 /* Figure out whether to use ordered or unordered fp comparisons.
19306 Return the appropriate mode to use. */
19308 enum machine_mode
19310 {
19311 /* ??? In order to make all comparisons reversible, we do all comparisons
19312 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19313 all forms trapping and nontrapping comparisons, we can make inequality
19314 comparisons trapping again, since it results in better code when using
19315 FCOM based compares. */
19317 }
19319 enum machine_mode
19321 {
19325 {
19328 }
19331 {
19332 /* Only zero flag is needed. */
19336 /* Codes needing carry flag. */
19339 /* Detect overflow checks. They need just the carry flag. */
19343 else
19348 /* Codes possibly doable only with sign flag when
19349 comparing against zero. */
19354 else
19355 /* For other cases Carry flag is not required. */
19357 /* Codes doable only with sign flag when comparing
19358 against zero, but we miss jump instruction for it
19359 so we need to use relational tests against overflow
19360 that thus needs to be zero. */
19365 else
19367 /* strcmp pattern do (use flags) and combine may ask us for proper
19368 mode. */
19373 }
19374 }
19376 /* Return the fixed registers used for condition codes. */
19378 static bool
19380 {
19384 }
19386 /* If two condition code modes are compatible, return a condition code
19387 mode which is compatible with both. Otherwise, return
19388 VOIDmode. */
19390 static enum machine_mode
19392 {
19409 {
19423 {
19437 }
19441 /* These are only compatible with themselves, which we already
19442 checked above. */
19444 }
19445 }
19448 /* Return a comparison we can do and that it is equivalent to
19449 swap_condition (code) apart possibly from orderedness.
19450 But, never change orderedness if TARGET_IEEE_FP, returning
19451 UNKNOWN in that case if necessary. */
19453 static enum rtx_code
19455 {
19457 {
19468 }
19469 }
19471 /* Return cost of comparison CODE using the best strategy for performance.
19472 All following functions do use number of instructions as a cost metrics.
19473 In future this should be tweaked to compute bytes for optimize_size and
19474 take into account performance of various instructions on various CPUs. */
19476 static int
19478 {
19481 /* The cost of code using bit-twiddling on %ah. */
19483 {
19506 }
19509 {
19516 }
19517 }
19519 /* Return strategy to use for floating-point. We assume that fcomi is always
19520 preferrable where available, since that is also true when looking at size
19521 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19523 enum ix86_fpcmp_strategy
19525 {
19526 /* Do fcomi/sahf based test when profitable. */
19535 }
19537 /* Swap, force into registers, or otherwise massage the two operands
19538 to a fp comparison. The operands are updated in place; the new
19539 comparison code is returned. */
19541 static enum rtx_code
19543 {
19549 /* All of the unordered compare instructions only work on registers.
19550 The same is true of the fcomi compare instructions. The XFmode
19551 compare instructions require registers except when comparing
19552 against zero or when converting operand 1 from fixed point to
19553 floating point. */
19562 {
19565 }
19566 else
19567 {
19568 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19569 things around if they appear profitable, otherwise force op0
19570 into a register. */
19576 {
19579 {
19580 rtx tmp;
19583 }
19584 }
19590 {
19595 {
19598 }
19599 else
19601 }
19602 }
19604 /* Try to rearrange the comparison to make it cheaper. */
19608 {
19609 rtx tmp;
19614 }
19619 }
19621 /* Convert comparison codes we use to represent FP comparison to integer
19622 code that will result in proper branch. Return UNKNOWN if no such code
19623 is available. */
19625 enum rtx_code
19627 {
19629 {
19652 }
19653 }
19655 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19657 static rtx
19659 {
19666 /* Do fcomi/sahf based test when profitable. */
19668 {
19673 tmp);
19681 tmp);
19690 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19697 /* In the unordered case, we have to check C2 for NaN's, which
19698 doesn't happen to work out to anything nice combination-wise.
19699 So do some bit twiddling on the value we've got in AH to come
19700 up with an appropriate set of condition codes. */
19704 {
19708 {
19711 }
19712 else
19713 {
19719 }
19724 {
19729 }
19730 else
19731 {
19734 }
19739 {
19742 }
19743 else
19744 {
19748 }
19753 {
19759 }
19760 else
19761 {
19764 }
19769 {
19774 }
19775 else
19776 {
19779 }
19784 {
19789 }
19790 else
19791 {
19794 }
19808 }
19813 }
19815 /* Return the test that should be put into the flags user, i.e.
19816 the bcc, scc, or cmov instruction. */
19819 const0_rtx);
19820 }
19822 static rtx
19824 {
19825 rtx ret;
19831 {
19834 }
19835 else
19839 }
19841 void
19843 {
19845 rtx tmp;
19848 {
19855 simple:
19859 pc_rtx);
19867 /* Expand DImode branch into multiple compare+branch. */
19868 {
19874 {
19877 }
19884 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19885 avoid two branches. This costs one extra insn, so disable when
19886 optimizing for size. */
19891 {
19909 }
19911 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19912 op1 is a constant and the low word is zero, then we can just
19913 examine the high word. Similarly for low word -1 and
19914 less-or-equal-than or greater-than. */
19918 {
19921 {
19924 }
19928 {
19931 }
19935 }
19937 /* Otherwise, we need two or three jumps. */
19946 {
19960 }
19962 /*
19963 * a < b =>
19964 * if (hi(a) < hi(b)) goto true;
19965 * if (hi(a) > hi(b)) goto false;
19966 * if (lo(a) < lo(b)) goto true;
19967 * false:
19968 */
19980 }
19985 }
19986 }
19988 /* Split branch based on floating point condition. */
19989 void
19992 {
19993 rtx condition;
19994 rtx i;
19997 {
20002 }
20005 tmp);
20013 }
20015 void
20017 {
20018 rtx ret;
20025 }
20027 /* Expand comparison setting or clearing carry flag. Return true when
20028 successful and set pop for the operation. */
20029 static bool
20031 {
20035 /* Do not handle double-mode compares that go through special path. */
20040 {
20045 /* Shortcut: following common codes never translate
20046 into carry flag compares. */
20051 /* These comparisons require zero flag; swap operands so they won't. */
20054 {
20059 }
20061 /* Try to expand the comparison and verify that we end up with
20062 carry flag based comparison. This fails to be true only when
20063 we decide to expand comparison using arithmetic that is not
20064 too common scenario. */
20073 else
20082 }
20088 {
20093 /* Convert a==0 into (unsigned)a<1. */
20102 /* Convert a>b into b<a or a>=b-1. */
20106 {
20108 /* Bail out on overflow. We still can swap operands but that
20109 would force loading of the constant into register. */
20114 }
20115 else
20116 {
20121 }
20124 /* Convert a>=0 into (unsigned)a<0x80000000. */
20142 }
20143 /* Swapping operands may cause constant to appear as first operand. */
20145 {
20149 }
20153 }
20155 bool
20157 {
20181 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20182 HImode insns, we'd be swallowed in word prefix ops. */
20188 {
20192 HOST_WIDE_INT diff;
20195 /* Sign bit compares are better done using shifts than we do by using
20196 sbb. */
20199 {
20200 /* Detect overlap between destination and compare sources. */
20204 {
20205 rtx flags;
20214 {
20216 compare_code
20218 }
20220 /* To simplify rest of code, restrict to the GEU case. */
20222 {
20228 }
20229 else
20230 {
20233 reverse_condition_maybe_unordered
20235 else
20238 }
20247 else
20250 }
20251 else
20252 {
20255 else
20256 {
20261 }
20263 }
20266 {
20267 /*
20268 * cmpl op0,op1
20269 * sbbl dest,dest
20270 * [addl dest, ct]
20271 *
20272 * Size 5 - 8.
20273 */
20278 }
20280 {
20281 /*
20282 * cmpl op0,op1
20283 * sbbl dest,dest
20284 * orl $ct, dest
20285 *
20286 * Size 8.
20287 */
20291 }
20293 {
20294 /*
20295 * cmpl op0,op1
20296 * sbbl dest,dest
20297 * notl dest
20298 * [addl dest, cf]
20299 *
20300 * Size 8 - 11.
20301 */
20307 }
20308 else
20309 {
20310 /*
20311 * cmpl op0,op1
20312 * sbbl dest,dest
20313 * [notl dest]
20314 * andl cf - ct, dest
20315 * [addl dest, ct]
20316 *
20317 * Size 8 - 11.
20318 */
20321 {
20325 }
20335 }
20341 }
20344 {
20347 HOST_WIDE_INT tmp;
20352 {
20355 /* We may be reversing unordered compare to normal compare, that
20356 is not valid in general (we may convert non-trapping condition
20357 to trapping one), however on i386 we currently emit all
20358 comparisons unordered. */
20361 }
20362 else
20363 {
20366 }
20367 }
20372 {
20377 {
20382 }
20383 }
20385 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20389 {
20390 /* If lea code below could be used, only optimize
20391 if it results in a 2 insn sequence. */
20397 {
20398 /*
20399 * notl op1 (if necessary)
20400 * sarl $31, op1
20401 * orl cf, op1
20402 */
20404 {
20408 }
20419 }
20420 }
20428 {
20429 /*
20430 * xorl dest,dest
20431 * cmpl op1,op2
20432 * setcc dest
20433 * lea cf(dest*(ct-cf)),dest
20434 *
20435 * Size 14.
20436 *
20437 * This also catches the degenerate setcc-only case.
20438 */
20440 rtx tmp;
20446 /* On x86_64 the lea instruction operates on Pmode, so we need
20447 to get arithmetics done in proper mode to match. */
20450 else
20451 {
20452 rtx out1;
20455 nops++;
20457 {
20459 nops++;
20460 }
20461 }
20463 {
20465 nops++;
20466 }
20468 {
20471 else
20473 }
20478 }
20480 /*
20481 * General case: Jumpful:
20482 * xorl dest,dest cmpl op1, op2
20483 * cmpl op1, op2 movl ct, dest
20484 * setcc dest jcc 1f
20485 * decl dest movl cf, dest
20486 * andl (cf-ct),dest 1:
20487 * addl ct,dest
20488 *
20489 * Size 20. Size 14.
20490 *
20491 * This is reasonably steep, but branch mispredict costs are
20492 * high on modern cpus, so consider failing only if optimizing
20493 * for space.
20494 */
20499 {
20501 {
20508 {
20511 /* We may be reversing unordered compare to normal compare,
20512 that is not valid in general (we may convert non-trapping
20513 condition to trapping one), however on i386 we currently
20514 emit all comparisons unordered. */
20516 }
20517 else
20518 {
20522 }
20523 }
20526 {
20527 /* notl op1 (if needed)
20528 sarl $31, op1
20529 andl (cf-ct), op1
20530 addl ct, op1
20532 For x < 0 (resp. x <= -1) there will be no notl,
20533 so if possible swap the constants to get rid of the
20534 complement.
20535 True/false will be -1/0 while code below (store flag
20536 followed by decrement) is 0/-1, so the constants need
20537 to be exchanged once more. */
20540 {
20543 }
20544 else
20545 {
20549 }
20552 }
20553 else
20554 {
20558 constm1_rtx,
20560 }
20572 }
20573 }
20576 {
20577 /* Try a few things more with specific constants and a variable. */
20579 optab op;
20585 /* If one of the two operands is an interesting constant, load a
20586 constant with the above and mask it in with a logical operation. */
20589 {
20595 else
20597 }
20599 {
20605 else
20607 }
20608 else
20615 /* Recurse to get the constant loaded. */
20619 /* Mask in the interesting variable. */
20621 OPTAB_WIDEN);
20626 }
20628 /*
20629 * For comparison with above,
20630 *
20631 * movl cf,dest
20632 * movl ct,tmp
20633 * cmpl op1,op2
20634 * cmovcc tmp,dest
20635 *
20636 * Size 15.
20637 */
20659 }
20661 /* Swap, force into registers, or otherwise massage the two operands
20662 to an sse comparison with a mask result. Thus we differ a bit from
20663 ix86_prepare_fp_compare_args which expects to produce a flags result.
20665 The DEST operand exists to help determine whether to commute commutative
20666 operators. The POP0/POP1 operands are updated in place. The new
20667 comparison code is returned, or UNKNOWN if not implementable. */
20669 static enum rtx_code
20672 {
20673 rtx tmp;
20676 {
20679 /* AVX supports all the needed comparisons. */
20682 /* We have no LTGT as an operator. We could implement it with
20683 NE & ORDERED, but this requires an extra temporary. It's
20684 not clear that it's worth it. */
20691 /* These are supported directly. */
20698 /* AVX has 3 operand comparisons, no need to swap anything. */
20701 /* For commutative operators, try to canonicalize the destination
20702 operand to be first in the comparison - this helps reload to
20703 avoid extra moves. */
20706 /* FALLTHRU */
20712 /* These are not supported directly before AVX, and furthermore
20713 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20714 comparison operands to transform into something that is
20715 supported. */
20724 }
20727 }
20729 /* Detect conditional moves that exactly match min/max operational
20730 semantics. Note that this is IEEE safe, as long as we don't
20731 interchange the operands.
20733 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20734 and TRUE if the operation is successful and instructions are emitted. */
20736 static bool
20739 {
20742 rtx tmp;
20745 ;
20747 {
20751 }
20752 else
20759 else
20764 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20765 but MODE may be a vector mode and thus not appropriate. */
20767 {
20769 rtvec v;
20774 }
20775 else
20776 {
20779 }
20783 }
20785 /* Expand an sse vector comparison. Return the register with the result. */
20787 static rtx
20790 {
20794 /* In general case result of comparison can differ from operands' type. */
20797 /* In AVX512F the result of comparison is an integer mask. */
20799 rtx x;
20802 {
20807 }
20808 else
20821 /* Compare patterns for int modes are unspec in AVX512F only. */
20823 {
20827 {
20836 }
20839 {
20842 }
20843 }
20847 {
20850 }
20851 else
20855 }
20857 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20858 operations. This is used for both scalar and vector conditional moves. */
20860 static void
20862 {
20866 /* In AVX512F the result of comparison is an integer mask. */
20874 {
20876 }
20879 {
20883 }
20886 {
20891 }
20894 {
20898 }
20901 {
20909 op_true,
20910 op_false)));
20911 }
20912 else
20913 {
20923 {
20937 {
20944 }
20959 {
20966 }
20984 }
20987 {
20991 }
20992 else
20993 {
20999 else
21011 }
21012 }
21013 }
21015 /* Expand a floating-point conditional move. Return true if successful. */
21017 bool
21019 {
21027 {
21030 /* Since we've no cmove for sse registers, don't force bad register
21031 allocation just to gain access to it. Deny movcc when the
21032 comparison mode doesn't match the move mode. */
21051 }
21058 /* The floating point conditional move instructions don't directly
21059 support conditions resulting from a signed integer comparison. */
21063 {
21068 }
21075 }
21077 /* Expand a floating-point vector conditional move; a vcond operation
21078 rather than a movcc operation. */
21080 bool
21082 {
21084 rtx cmp;
21089 {
21090 rtx temp;
21092 {
21109 }
21111 OPTAB_DIRECT);
21114 }
21124 }
21126 /* Expand a signed/unsigned integral vector conditional move. */
21128 bool
21130 {
21140 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21141 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21150 {
21154 {
21160 }
21163 {
21169 }
21170 }
21179 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21183 ;
21184 else
21185 {
21186 /* Canonicalize the comparison to EQ, GT, GTU. */
21188 {
21205 /* FALLTHRU */
21215 }
21217 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21219 {
21221 {
21223 /* SSE4.1 supports EQ. */
21230 /* SSE4.2 supports GT/GTU. */
21237 }
21238 }
21240 /* Unsigned parallel compare is not supported by the hardware.
21241 Play some tricks to turn this into a signed comparison
21242 against 0. */
21244 {
21248 {
21255 {
21260 {
21269 }
21270 /* Subtract (-(INT MAX) - 1) from both operands to make
21271 them signed. */
21282 }
21289 /* Perform a parallel unsigned saturating subtraction. */
21302 }
21303 }
21304 }
21306 /* Allow the comparison to be done in one mode, but the movcc to
21307 happen in another mode. */
21309 {
21312 }
21313 else
21314 {
21320 }
21325 }
21327 static bool
21329 {
21332 {
21336 op1));
21341 op1));
21353 }
21354 }
21356 /* Expand a variable vector permutation. */
21358 void
21360 {
21371 /* Number of elements in the vector. */
21380 {
21382 {
21383 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21384 an constant shuffle operand. With a tiny bit of effort we can
21385 use VPERMD instead. A re-interpretation stall for V4DFmode is
21386 unfortunate but there's no avoiding it.
21387 Similarly for V16HImode we don't have instructions for variable
21388 shuffling, while for V32QImode we can use after preparing suitable
21389 masks vpshufb; vpshufb; vpermq; vpor. */
21392 {
21396 }
21397 else
21398 {
21402 }
21405 /* Replicate the low bits of the V4DImode mask into V8SImode:
21406 mask = { A B C D }
21407 t1 = { A A B B C C D D }. */
21415 else
21418 /* Multiply the shuffle indicies by two. */
21420 OPTAB_DIRECT);
21422 /* Add one to the odd shuffle indicies:
21423 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21425 {
21428 }
21432 OPTAB_DIRECT);
21434 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21439 }
21442 {
21444 /* The VPERMD and VPERMPS instructions already properly ignore
21445 the high bits of the shuffle elements. No need for us to
21446 perform an AND ourselves. */
21448 {
21453 }
21454 else
21455 {
21461 }
21468 else
21469 {
21475 }
21479 /* By combining the two 128-bit input vectors into one 256-bit
21480 input vector, we can use VPERMD and VPERMPS for the full
21481 two-operand shuffle. */
21513 /* From mask create two adjusted masks, which contain the same
21514 bits as mask in the low 7 bits of each vector element.
21515 The first mask will have the most significant bit clear
21516 if it requests element from the same 128-bit lane
21517 and MSB set if it requests element from the other 128-bit lane.
21518 The second mask will have the opposite values of the MSB,
21519 and additionally will have its 128-bit lanes swapped.
21520 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21521 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21522 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21523 stands for other 12 bytes. */
21524 /* The bit whether element is from the same lane or the other
21525 lane is bit 4, so shift it up by 3 to the MSB position. */
21529 /* Clear MSB bits from the mask just in case it had them set. */
21531 /* After this t1 will have MSB set for elements from other lane. */
21533 /* Clear bits other than MSB. */
21535 /* Or in the lower bits from mask into t3. */
21537 /* And invert MSB bits in t1, so MSB is set for elements from the same
21538 lane. */
21540 /* Swap 128-bit lanes in t3. */
21545 /* And or in the lower bits from mask into t1. */
21548 {
21549 /* Each of these shuffles will put 0s in places where
21550 element from the other 128-bit lane is needed, otherwise
21551 will shuffle in the requested value. */
21555 /* For t3 the 128-bit lanes are swapped again. */
21560 /* And oring both together leads to the result. */
21567 }
21570 /* Similarly to the above one_operand_shuffle code,
21571 just for repeated twice for each operand. merge_two:
21572 code will merge the two results together. */
21596 }
21597 }
21600 {
21601 /* The XOP VPPERM insn supports three inputs. By ignoring the
21602 one_operand_shuffle special case, we avoid creating another
21603 set of constant vectors in memory. */
21606 /* mask = mask & {2*w-1, ...} */
21608 }
21609 else
21610 {
21611 /* mask = mask & {w-1, ...} */
21613 }
21621 /* For non-QImode operations, convert the word permutation control
21622 into a byte permutation control. */
21624 {
21629 /* Convert mask to vector of chars. */
21632 /* Replicate each of the input bytes into byte positions:
21633 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21634 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21635 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21642 else
21645 /* Convert it into the byte positions by doing
21646 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21652 }
21654 /* The actual shuffle operations all operate on V16QImode. */
21659 {
21666 }
21668 {
21675 }
21676 else
21677 {
21681 /* Shuffle the two input vectors independently. */
21687 merge_two:
21688 /* Then merge them together. The key is whether any given control
21689 element contained a bit set that indicates the second word. */
21693 {
21694 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21695 more shuffle to convert the V2DI input mask into a V4SI
21696 input mask. At which point the masking that expand_int_vcond
21697 will work as desired. */
21705 }
21727 }
21728 }
21730 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21731 true if we should do zero extension, else sign extension. HIGH_P is
21732 true if we want the N/2 high elements, else the low elements. */
21734 void
21736 {
21738 rtx tmp;
21741 {
21747 {
21751 else
21754 extract
21760 else
21763 extract
21769 else
21772 extract
21778 else
21781 extract
21787 else
21790 extract
21796 else
21802 else
21808 else
21813 }
21816 {
21819 }
21821 {
21822 /* Shift higher 8 bytes to lower 8 bytes. */
21827 }
21828 else
21832 }
21833 else
21834 {
21838 {
21842 else
21848 else
21854 else
21859 }
21863 else
21870 }
21871 }
21873 /* Expand conditional increment or decrement using adb/sbb instructions.
21874 The default case using setcc followed by the conditional move can be
21875 done by generic code. */
21876 bool
21878 {
21880 rtx flags;
21882 rtx compare_op;
21900 {
21903 }
21906 {
21910 reverse_condition_maybe_unordered
21912 else
21914 }
21918 /* Construct either adc or sbb insn. */
21920 {
21922 {
21937 }
21938 }
21939 else
21940 {
21942 {
21957 }
21958 }
21962 }
21965 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21966 but works for floating pointer parameters and nonoffsetable memories.
21967 For pushes, it returns just stack offsets; the values will be saved
21968 in the right order. Maximally three parts are generated. */
21970 static int
21972 {
21977 else
21983 /* Optimize constant pool reference to immediates. This is used by fp
21984 moves, that force all constants to memory to allow combining. */
21986 {
21990 }
21993 {
21994 /* The only non-offsetable memories we handle are pushes. */
22003 }
22006 {
22008 /* Caution: if we looked through a constant pool memory above,
22009 the operand may actually have a different mode now. That's
22010 ok, since we want to pun this all the way back to an integer. */
22014 }
22017 {
22020 else
22021 {
22025 {
22029 }
22031 {
22036 }
22038 {
22039 REAL_VALUE_TYPE r;
22044 {
22051 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22052 long double may not be 80-bit. */
22061 }
22064 }
22065 else
22067 }
22068 }
22069 else
22070 {
22074 {
22077 {
22081 }
22083 {
22087 }
22089 {
22090 REAL_VALUE_TYPE r;
22096 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22099 = gen_int_mode
22102 DImode);
22103 else
22110 = gen_int_mode
22113 DImode);
22114 else
22116 }
22117 else
22119 }
22120 }
22123 }
22125 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22126 Return false when normal moves are needed; true when all required
22127 insns have been emitted. Operands 2-4 contain the input values
22128 int the correct order; operands 5-7 contain the output values. */
22130 void
22132 {
22140 /* The DFmode expanders may ask us to move double.
22141 For 64bit target this is single move. By hiding the fact
22142 here we simplify i386.md splitters. */
22144 {
22145 /* Optimize constant pool reference to immediates. This is used by
22146 fp moves, that force all constants to memory to allow combining. */
22153 {
22156 }
22157 else
22162 }
22164 /* The only non-offsettable memory we handle is push. */
22167 else
22174 /* When emitting push, take care for source operands on the stack. */
22177 {
22180 /* Compensate for the stack decrement by 4. */
22185 /* src_base refers to the stack pointer and is
22186 automatically decreased by emitted push. */
22190 }
22192 /* We need to do copy in the right order in case an address register
22193 of the source overlaps the destination. */
22195 {
22196 rtx tmp;
22199 {
22203 collisions++;
22204 }
22206 /* Collision in the middle part can be handled by reordering. */
22208 {
22211 }
22215 {
22217 {
22220 }
22221 else
22222 {
22225 }
22226 }
22228 /* If there are more collisions, we can't handle it by reordering.
22229 Do an lea to the last part and use only one colliding move. */
22231 {
22232 rtx base;
22238 /* Handle the case when the last part isn't valid for lea.
22239 Happens in 64-bit mode storing the 12-byte XFmode. */
22246 {
22249 }
22250 }
22251 }
22254 {
22256 {
22258 {
22263 }
22265 {
22268 }
22269 }
22270 else
22271 {
22272 /* In 64bit mode we don't have 32bit push available. In case this is
22273 register, it is OK - we will just use larger counterpart. We also
22274 retype memory - these comes from attempt to avoid REX prefix on
22275 moving of second half of TFmode value. */
22277 {
22279 {
22290 }
22294 }
22295 }
22299 }
22301 /* Choose correct order to not overwrite the source before it is copied. */
22311 {
22313 {
22316 }
22317 }
22318 else
22319 {
22321 {
22324 }
22325 }
22327 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22329 {
22338 }
22344 }
22346 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22347 left shift by a constant, either using a single shift or
22348 a sequence of add instructions. */
22350 static void
22352 {
22358 {
22362 }
22363 else
22364 {
22367 }
22368 }
22370 void
22372 {
22381 {
22386 {
22392 }
22393 else
22394 {
22402 }
22404 }
22411 {
22412 /* Assuming we've chosen a QImode capable registers, then 1 << N
22413 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22415 {
22431 }
22433 /* Otherwise, we can get the same results by manually performing
22434 a bit extract operation on bit 5/6, and then performing the two
22435 shifts. The two methods of getting 0/1 into low/high are exactly
22436 the same size. Avoiding the shift in the bit extract case helps
22437 pentium4 a bit; no one else seems to care much either way. */
22438 else
22439 {
22444 HOST_WIDE_INT bits;
22445 rtx x;
22448 {
22454 }
22455 else
22456 {
22462 }
22466 else
22474 }
22479 }
22482 {
22483 /* For -1 << N, we can avoid the shld instruction, because we
22484 know that we're shifting 0...31/63 ones into a -1. */
22488 else
22490 }
22491 else
22492 {
22500 }
22505 {
22511 }
22512 else
22513 {
22518 }
22519 }
22521 void
22523 {
22533 {
22538 {
22544 }
22546 {
22555 }
22556 else
22557 {
22565 }
22566 }
22567 else
22568 {
22580 {
22588 scratch));
22589 }
22590 else
22591 {
22596 }
22597 }
22598 }
22600 void
22602 {
22612 {
22617 {
22624 }
22625 else
22626 {
22634 }
22635 }
22636 else
22637 {
22649 {
22655 scratch));
22656 }
22657 else
22658 {
22663 }
22664 }
22665 }
22667 /* Predict just emitted jump instruction to be taken with probability PROB. */
22668 static void
22670 {
22674 }
22676 /* Helper function for the string operations below. Dest VARIABLE whether
22677 it is aligned to VALUE bytes. If true, jump to the label. */
22678 static rtx
22680 {
22685 else
22691 else
22694 }
22696 /* Adjust COUNTER by the VALUE. */
22697 static void
22699 {
22704 }
22706 /* Zero extend possibly SImode EXP to Pmode register. */
22707 rtx
22709 {
22711 }
22713 /* Divide COUNTREG by SCALE. */
22714 static rtx
22716 {
22717 rtx sc;
22729 }
22731 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22732 DImode for constant loop counts. */
22734 static enum machine_mode
22736 {
22744 }
22746 /* Copy the address to a Pmode register. This is used for x32 to
22747 truncate DImode TLS address to a SImode register. */
22749 static rtx
22751 {
22754 else
22755 {
22758 }
22759 }
22761 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22762 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22763 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22764 memory by VALUE (supposed to be in MODE).
22766 The size is rounded down to whole number of chunk size moved at once.
22767 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22770 static void
22775 {
22781 rtx size;
22790 /* Those two should combine. */
22792 {
22796 }
22803 /* This assert could be relaxed - in this case we'll need to compute
22804 smallest power of two, containing in PIECE_SIZE_N and pass it to
22805 offset_address. */
22811 {
22815 /* When unrolling for chips that reorder memory reads and writes,
22816 we can save registers by using single temporary.
22817 Also using 4 temporaries is overkill in 32bit mode. */
22819 {
22821 {
22823 {
22824 destmem =
22826 srcmem =
22828 }
22830 }
22831 }
22832 else
22833 {
22837 {
22840 {
22841 srcmem =
22843 }
22845 }
22847 {
22849 {
22850 destmem =
22852 }
22854 }
22855 }
22856 }
22857 else
22859 {
22861 destmem =
22864 }
22874 {
22880 else
22882 }
22883 else
22891 {
22896 }
22898 }
22900 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22901 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22902 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22903 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22904 ORIG_VALUE is the original value passed to memset to fill the memory with.
22905 Other arguments have same meaning as for previous function. */
22907 static void
22910 rtx count,
22912 {
22913 rtx destexp;
22914 rtx srcexp;
22915 rtx countreg;
22916 HOST_WIDE_INT rounded_count;
22918 /* If possible, it is shorter to use rep movs.
22919 TODO: Maybe it is better to move this logic to decide_alg. */
22930 {
22934 }
22935 else
22938 {
22943 }
22948 {
22951 }
22952 else
22953 {
22957 {
22961 }
22962 else
22965 {
22970 }
22971 else
22972 {
22975 }
22978 }
22979 }
22981 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
22982 DESTMEM.
22983 SRC is passed by pointer to be updated on return.
22984 Return value is updated DST. */
22985 static rtx
22987 HOST_WIDE_INT size_to_move)
22988 {
22994 /* Find the widest mode in which we could perform moves.
22995 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
22996 it until move of such size is supported. */
23001 {
23005 }
23007 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23008 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23010 {
23015 {
23019 }
23020 }
23026 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23030 {
23031 /* We move from memory to memory, so we'll need to do it via
23032 a temporary register. */
23043 piece_size);
23045 piece_size);
23046 }
23048 /* Update DST and SRC rtx. */
23051 }
23053 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23054 static void
23057 {
23060 {
23065 /* For now MAX_SIZE should be a power of 2. This assert could be
23066 relaxed, but it'll require a bit more complicated epilogue
23067 expanding. */
23070 {
23073 }
23075 }
23077 {
23083 }
23085 /* When there are stringops, we can cheaply increase dest and src pointers.
23086 Otherwise we save code size by maintaining offset (zero is readily
23087 available from preceding rep operation) and using x86 addressing modes.
23088 */
23090 {
23092 {
23099 }
23101 {
23108 }
23110 {
23117 }
23118 }
23119 else
23120 {
23122 rtx tmp;
23125 {
23136 }
23138 {
23151 }
23153 {
23162 }
23163 }
23164 }
23166 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23167 with value PROMOTED_VAL.
23168 SRC is passed by pointer to be updated on return.
23169 Return value is updated DST. */
23170 static rtx
23172 HOST_WIDE_INT size_to_move)
23173 {
23179 /* Find the widest mode in which we could perform moves.
23180 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23181 it until move of such size is supported. */
23186 {
23189 }
23196 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23200 {
23202 {
23205 piece_size);
23207 }
23215 piece_size);
23216 }
23218 /* Update DST rtx. */
23220 }
23221 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23222 static void
23225 {
23226 count =
23232 }
23234 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23235 static void
23238 {
23239 rtx dest;
23242 {
23247 /* For now MAX_SIZE should be a power of 2. This assert could be
23248 relaxed, but it'll require a bit more complicated epilogue
23249 expanding. */
23252 {
23254 {
23257 else
23259 }
23260 }
23262 }
23264 {
23267 }
23269 {
23272 {
23277 }
23278 else
23279 {
23288 }
23291 }
23293 {
23296 {
23299 }
23300 else
23301 {
23306 }
23309 }
23311 {
23317 }
23319 {
23325 }
23327 {
23333 }
23334 }
23336 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23337 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23338 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23339 ignored.
23340 Return value is updated DESTMEM. */
23341 static rtx
23346 {
23349 {
23351 {
23354 {
23357 else
23359 }
23360 else
23366 }
23367 }
23369 }
23371 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23372 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23373 and jump to DONE_LABEL. */
23374 static void
23380 {
23383 rtx modesize;
23386 /* If we do not have vector value to copy, we must reduce size. */
23388 {
23390 {
23395 }
23396 else
23398 }
23399 else
23400 {
23401 /* Choose appropriate vector mode. */
23407 }
23412 {
23415 else
23416 {
23419 }
23421 }
23427 {
23431 }
23433 {
23436 else
23437 {
23440 }
23442 }
23448 }
23450 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23451 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23452 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23453 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23454 DONE_LABEL is a label after the whole copying sequence. The label is created
23455 on demand if *DONE_LABEL is NULL.
23456 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23457 bounds after the initial copies.
23459 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23460 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23461 we will dispatch to a library call for large blocks.
23463 In pseudocode we do:
23465 if (COUNT < SIZE)
23466 {
23467 Assume that SIZE is 4. Bigger sizes are handled analogously
23468 if (COUNT & 4)
23469 {
23470 copy 4 bytes from SRCPTR to DESTPTR
23471 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23472 goto done_label
23473 }
23474 if (!COUNT)
23475 goto done_label;
23476 copy 1 byte from SRCPTR to DESTPTR
23477 if (COUNT & 2)
23478 {
23479 copy 2 bytes from SRCPTR to DESTPTR
23480 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23481 }
23482 }
23483 else
23484 {
23485 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23486 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23488 OLD_DESPTR = DESTPTR;
23489 Align DESTPTR up to DESIRED_ALIGN
23490 SRCPTR += DESTPTR - OLD_DESTPTR
23491 COUNT -= DEST_PTR - OLD_DESTPTR
23492 if (DYNAMIC_CHECK)
23493 Round COUNT down to multiple of SIZE
23494 << optional caller supplied zero size guard is here >>
23495 << optional caller suppplied dynamic check is here >>
23496 << caller supplied main copy loop is here >>
23497 }
23498 done_label:
23499 */
23500 static void
23513 {
23516 rtx modesize;
23518 rtx mode_value;
23520 /* Chose proper value to copy. */
23523 else
23527 /* See if block is big or small, handle small blocks. */
23529 {
23540 /* Handle sizes > 3. */
23547 /* Nothing to copy? Jump to DONE_LABEL if so */
23551 /* Do a byte copy. */
23555 else
23556 {
23559 }
23561 /* Handle sizes 2 and 3. */
23568 else
23569 {
23574 }
23580 }
23581 else
23585 /* Start memcpy for COUNT >= SIZE. */
23587 {
23590 }
23592 /* Copy first desired_align bytes. */
23598 {
23601 else
23602 {
23605 }
23608 }
23611 /* Copy last SIZE bytes. */
23618 else
23619 {
23625 }
23627 {
23631 else
23632 {
23635 }
23636 }
23638 /* Align destination. */
23640 {
23644 /* Align destptr up, place it to new register. */
23651 /* See how many bytes we skipped. */
23655 /* Adjust srcptr and count. */
23661 /* We copied at most size + prolog_size. */
23664 else
23667 /* Our loops always round down the bock size, but for dispatch to library
23668 we need precise value. */
23672 }
23673 else
23674 {
23676 /* Decrease count, so we won't end up copying last word twice. */
23680 else
23684 }
23685 }
23688 /* This function is like the previous one, except here we know how many bytes
23689 need to be copied. That allows us to update alignment not only of DST, which
23690 is returned, but also of SRC, which is passed as a pointer for that
23691 reason. */
23692 static rtx
23697 {
23705 {
23709 }
23714 {
23716 {
23718 {
23721 else
23723 }
23724 else
23727 }
23728 }
23735 {
23741 {
23744 {
23748 }
23753 }
23757 }
23760 }
23762 /* Return true if ALG can be used in current context.
23763 Assume we expand memset if MEMSET is true. */
23764 static bool
23766 {
23771 /* Algorithms using the rep prefix want at least edi and ecx;
23772 additionally, memset wants eax and memcpy wants esi. Don't
23773 consider such algorithms if the user has appropriated those
23774 registers for their own purposes. */
23781 }
23783 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23784 static enum stringop_alg
23788 {
23799 /* Even if the string operation call is cold, we still might spend a lot
23800 of time processing large blocks. */
23806 else
23812 else
23815 /* See maximal size for user defined algorithm. */
23817 {
23824 }
23826 /* If expected size is not known but max size is small enough
23827 so inline version is a win, set expected size into
23828 the range. */
23833 /* If user specified the algorithm, honnor it if possible. */
23837 /* rep; movq or rep; movl is the smallest variant. */
23839 {
23844 else
23847 }
23848 /* Very tiny blocks are best handled via the loop, REP is expensive to
23849 setup. */
23853 {
23857 {
23858 /* We get here if the algorithms that were not libcall-based
23859 were rep-prefix based and we are unable to use rep prefixes
23860 based on global register usage. Break out of the loop and
23861 use the heuristic below. */
23865 {
23869 {
23872 }
23873 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23874 last non-libcall inline algorithm. */
23876 {
23877 /* When the current size is best to be copied by a libcall,
23878 but we are still forced to inline, run the heuristic below
23879 that will pick code for medium sized blocks. */
23881 {
23884 }
23886 }
23888 {
23891 }
23892 }
23893 }
23894 }
23895 /* When asked to inline the call anyway, try to pick meaningful choice.
23896 We look for maximal size of block that is faster to copy by hand and
23897 take blocks of at most of that size guessing that average size will
23898 be roughly half of the block.
23900 If this turns out to be bad, we might simply specify the preferred
23901 choice in ix86_costs. */
23905 {
23908 /* If there aren't any usable algorithms, then recursing on
23909 smaller sizes isn't going to find anything. Just return the
23910 simple byte-at-a-time copy loop. */
23912 {
23913 /* Pick something reasonable. */
23917 }
23927 }
23930 }
23932 /* Decide on alignment. We know that the operand is already aligned to ALIGN
23933 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
23934 static int
23939 {
23950 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
23951 copying whole cacheline at once. */
23964 }
23967 /* Helper function for memcpy. For QImode value 0xXY produce
23968 0xXYXYXYXY of wide specified by MODE. This is essentially
23969 a * 0x10101010, but we can do slightly better than
23970 synth_mult by unwinding the sequence by hand on CPUs with
23971 slow multiply. */
23972 static rtx
23974 {
23976 rtx tmp;
23983 {
23991 }
24000 nops--;
24005 {
24009 OPTAB_DIRECT);
24010 }
24011 else
24012 {
24018 else
24020 else
24021 {
24024 reg =
24026 }
24036 }
24037 }
24039 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24040 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24041 alignment from ALIGN to DESIRED_ALIGN. */
24042 static rtx
24045 {
24046 rtx promoted_val;
24055 else
24059 }
24061 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24062 operations when profitable. The code depends upon architecture, block size
24063 and alignment, but always has one of the following overall structures:
24065 Aligned move sequence:
24067 1) Prologue guard: Conditional that jumps up to epilogues for small
24068 blocks that can be handled by epilogue alone. This is faster
24069 but also needed for correctness, since prologue assume the block
24070 is larger than the desired alignment.
24072 Optional dynamic check for size and libcall for large
24073 blocks is emitted here too, with -minline-stringops-dynamically.
24075 2) Prologue: copy first few bytes in order to get destination
24076 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24077 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24078 copied. We emit either a jump tree on power of two sized
24079 blocks, or a byte loop.
24081 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24082 with specified algorithm.
24084 4) Epilogue: code copying tail of the block that is too small to be
24085 handled by main body (or up to size guarded by prologue guard).
24087 Misaligned move sequence
24089 1) missaligned move prologue/epilogue containing:
24090 a) Prologue handling small memory blocks and jumping to done_label
24091 (skipped if blocks are known to be large enough)
24092 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24093 needed by single possibly misaligned move
24094 (skipped if alignment is not needed)
24095 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24097 2) Zero size guard dispatching to done_label, if needed
24099 3) dispatch to library call, if needed,
24101 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24102 with specified algorithm. */
24103 bool
24109 {
24110 rtx destreg;
24113 rtx tmp;
24129 /* TODO: Once value ranges are available, fill in proper data. */
24137 /* i386 can do misaligned access on reasonably increased cost. */
24141 /* ALIGN is the minimum of destination and source alignment, but we care here
24142 just about destination alignment. */
24150 else
24151 {
24160 }
24162 /* Make sure we don't need to care about overflow later on. */
24166 /* Step 0: Decide on preferred algorithm, desired alignment and
24167 size of chunks to be copied by main loop. */
24169 issetmem,
24176 /* For now vector-version of memset is generated only for memory zeroing, as
24177 creating of promoted vector value is very cheap in this case. */
24190 {
24209 /* Find the widest supported mode. */
24215 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24216 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24218 {
24223 }
24235 }
24243 /* Step 1: Prologue guard. */
24245 /* Alignment code needs count to be in register. */
24247 {
24250 {
24251 align_bytes
24255 else
24257 }
24260 }
24263 /* Misaligned move sequences handle both prologue and epilogue at once.
24264 Default code generation results in a smaller code for large alignments
24265 and also avoids redundant job when sizes are known precisely. */
24266 misaligned_prologue_used
24267 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24273 /* Do the cheap promotion to allow better CSE across the
24274 main loop and epilogue (ie one load of the big constant in the
24275 front of all code.
24276 For now the misaligned move sequences do not have fast path
24277 without broadcasting. */
24279 {
24281 {
24287 }
24288 else
24289 {
24292 }
24293 }
24294 /* Misaligned move sequences handles both prologues and epilogues at once.
24295 Default code generation results in smaller code for large alignments and
24296 also avoids redundant job when sizes are known precisely. */
24298 {
24299 /* Misaligned move prologue handled small blocks by itself. */
24300 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24305 desired_align < align
24314 {
24315 /* It is possible that we copied enough so the main loop will not
24316 execute. */
24326 else
24328 }
24329 }
24330 /* Ensure that alignment prologue won't copy past end of block. */
24332 {
24334 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24335 Make sure it is power of 2. */
24338 /* To improve performance of small blocks, we jump around the VAL
24339 promoting mode. This mean that if the promoted VAL is not constant,
24340 we might not use it in the epilogue and have to use byte
24341 loop variant. */
24346 {
24347 /* If main algorithm works on QImode, no epilogue is needed.
24348 For small sizes just don't align anything. */
24351 else
24353 }
24356 {
24363 else
24365 }
24366 }
24368 /* Emit code to decide on runtime whether library call or inline should be
24369 used. */
24371 {
24373 {
24375 {
24379 }
24380 }
24381 else
24382 {
24391 else
24395 }
24396 }
24398 /* Step 2: Alignment prologue. */
24399 /* Do the expensive promotion once we branched off the small blocks. */
24405 {
24407 {
24408 /* Except for the first move in prologue, we no longer know
24409 constant offset in aliasing info. It don't seems to worth
24410 the pain to maintain it for the first move, so throw away
24411 the info early. */
24418 issetmem);
24419 /* At most desired_align - align bytes are copied. */
24422 else
24424 }
24425 else
24426 {
24427 /* If we know how many bytes need to be stored before dst is
24428 sufficiently aligned, maintain aliasing info accurately. */
24430 srcreg,
24431 promoted_val,
24432 vec_promoted_val,
24433 desired_align,
24434 align_bytes,
24435 issetmem);
24442 }
24444 && !min_size
24449 {
24450 /* It is possible that we copied enough so the main loop will not
24451 execute. */
24461 else
24463 }
24464 }
24466 {
24473 }
24477 /* Step 3: Main loop. */
24480 {
24503 }
24504 /* Adjust properly the offset of src and dest memory for aliasing. */
24506 {
24512 }
24513 else
24514 {
24518 }
24520 /* Step 4: Epilogue to copy the remaining bytes. */
24521 epilogue:
24523 {
24524 /* When the main loop is done, COUNT_EXP might hold original count,
24525 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24526 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24527 bytes. Compensate if needed. */
24530 {
24531 tmp =
24534 OPTAB_DIRECT);
24537 }
24540 }
24543 {
24546 epilogue_size_needed);
24547 else
24548 {
24552 epilogue_size_needed);
24553 else
24555 epilogue_size_needed);
24556 }
24557 }
24561 }
24564 /* Expand the appropriate insns for doing strlen if not just doing
24565 repnz; scasb
24567 out = result, initialized with the start address
24568 align_rtx = alignment of the address.
24569 scratch = scratch register, initialized with the startaddress when
24570 not aligned, otherwise undefined
24572 This is just the body. It needs the initializations mentioned above and
24573 some address computing at the end. These things are done in i386.md. */
24575 static void
24577 {
24579 rtx tmp;
24584 rtx mem;
24587 rtx cmp;
24593 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24595 /* Is there a known alignment and is it less than 4? */
24597 {
24600 /* Is there a known alignment and is it not 2? */
24602 {
24606 /* Leave just the 3 lower bits. */
24616 }
24617 else
24618 {
24619 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24620 check if is aligned to 4 - byte. */
24627 }
24631 /* Now compare the bytes. */
24633 /* Compare the first n unaligned byte on a byte per byte basis. */
24637 /* Increment the address. */
24640 /* Not needed with an alignment of 2 */
24642 {
24646 end_0_label);
24651 }
24654 end_0_label);
24657 }
24659 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24660 align this loop. It gives only huge programs, but does not help to
24661 speed up. */
24668 /* This formula yields a nonzero result iff one of the bytes is zero.
24669 This saves three branches inside loop and many cycles. */
24677 align_4_label);
24680 {
24686 /* If zero is not in the first two bytes, move two bytes forward. */
24692 reg,
24693 tmpreg)));
24694 /* Emit lea manually to avoid clobbering of flags. */
24702 reg2,
24703 out)));
24704 }
24705 else
24706 {
24708 /* Is zero in the first two bytes? */
24715 pc_rtx);
24719 /* Not in the first two. Move two bytes forward. */
24725 }
24727 /* Avoid branch in fixing the byte. */
24735 }
24737 /* Expand strlen. */
24739 bool
24741 {
24744 /* The generic case of strlen expander is long. Avoid it's
24745 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24748 && !TARGET_INLINE_ALL_STRINGOPS
24758 {
24759 /* Well it seems that some optimizer does not combine a call like
24760 foo(strlen(bar), strlen(bar));
24761 when the move and the subtraction is done here. It does calculate
24762 the length just once when these instructions are done inside of
24763 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24764 often used and I use one fewer register for the lifetime of
24765 output_strlen_unroll() this is better. */
24771 /* strlensi_unroll_1 returns the address of the zero at the end of
24772 the string, like memchr(), so compute the length by subtracting
24773 the start address. */
24775 }
24776 else
24777 {
24778 rtx unspec;
24780 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24793 /* If .md starts supporting :P, this can be done in .md. */
24799 }
24801 }
24803 /* For given symbol (function) construct code to compute address of it's PLT
24804 entry in large x86-64 PIC model. */
24805 static rtx
24807 {
24820 }
24822 rtx
24824 rtx callarg2,
24826 {
24827 unsigned int const cregs_size
24838 {
24839 #if TARGET_MACHO
24842 #endif
24843 }
24844 else
24845 {
24846 /* Static functions and indirect calls don't need the pic register. */
24848 && (!TARGET_64BIT
24854 }
24857 {
24861 }
24864 && !TARGET_PECOFF
24872 {
24875 }
24883 {
24887 }
24891 {
24895 UNSPEC_MS_TO_SYSV_CALL);
24898 {
24904 }
24905 }
24914 }
24916 /* Output the assembly for a call instruction. */
24920 {
24926 {
24929 /* SEH epilogue detection requires the indirect branch case
24930 to include REX.W. */
24933 else
24938 }
24940 /* SEH unwinding can require an extra nop to be emitted in several
24941 circumstances. Determine if we have one of those. */
24943 {
24944 rtx i;
24947 {
24948 /* If we get to another real insn, we don't need the nop. */
24952 /* If we get to the epilogue note, prevent a catch region from
24953 being adjacent to the standard epilogue sequence. If non-
24954 call-exceptions, we'll have done this during epilogue emission. */
24956 && !flag_non_call_exceptions
24958 {
24961 }
24962 }
24964 /* If we didn't find a real insn following the call, prevent the
24965 unwinder from looking into the next function. */
24968 }
24972 else
24981 }
24982 \f
24983 /* Clear stack slot assignments remembered from previous functions.
24984 This is called from INIT_EXPANDERS once before RTL is emitted for each
24985 function. */
24989 {
24997 }
24999 /* Return a MEM corresponding to a stack slot with mode MODE.
25000 Allocate a new slot if necessary.
25002 The RTL for a function can have several slots available: N is
25003 which slot to use. */
25005 rtx
25007 {
25024 }
25026 static void
25028 {
25034 }
25035 \f
25036 /* Check whether x86 address PARTS is a pc-relative address. */
25038 static bool
25040 {
25048 {
25050 {
25067 }
25068 }
25070 }
25072 /* Calculate the length of the memory address in the instruction encoding.
25073 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25074 or other prefixes. We never generate addr32 prefix for LEA insn. */
25076 int
25078 {
25095 /* If this is not LEA instruction, add the length of addr32 prefix. */
25100 len++;
25114 /* Rule of thumb:
25115 - esp as the base always wants an index,
25116 - ebp as the base always wants a displacement,
25117 - r12 as the base always wants an index,
25118 - r13 as the base always wants a displacement. */
25120 /* Register Indirect. */
25122 {
25123 /* esp (for its index) and ebp (for its displacement) need
25124 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25125 code. */
25132 len++;
25133 }
25135 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25136 is not disp32, but disp32(%rip), so for disp32
25137 SIB byte is needed, unless print_operand_address
25138 optimizes it into disp32(%rip) or (%rip) is implied
25139 by UNSPEC. */
25141 {
25144 len++;
25145 }
25146 else
25147 {
25148 /* Find the length of the displacement constant. */
25150 {
25153 else
25155 }
25156 /* ebp always wants a displacement. Similarly r13. */
25158 len++;
25160 /* An index requires the two-byte modrm form.... */
25162 /* ...like esp (or r12), which always wants an index. */
25166 len++;
25167 }
25170 }
25172 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25173 is set, expect that insn have 8bit immediate alternative. */
25174 int
25176 {
25182 {
25187 {
25190 {
25202 }
25204 {
25207 }
25208 }
25210 {
25220 /* Immediates for DImode instructions are encoded
25221 as 32bit sign extended values. */
25227 }
25228 }
25230 }
25232 /* Compute default value for "length_address" attribute. */
25233 int
25235 {
25239 {
25250 }
25255 {
25258 {
25263 constraints++;
25266 ;
25267 /* Skip ignored operands. */
25270 }
25272 }
25274 }
25276 /* Compute default value for "length_vex" attribute. It includes
25277 2 or 3 byte VEX prefix and 1 opcode byte. */
25279 int
25281 {
25284 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25285 byte VEX prefix. */
25289 /* We can always use 2 byte VEX prefix in 32bit. */
25297 {
25298 /* REX.W bit uses 3 byte VEX prefix. */
25302 }
25303 else
25304 {
25305 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25309 }
25312 }
25313 \f
25314 /* Return the maximum number of instructions a cpu can issue. */
25316 static int
25318 {
25320 {
25351 }
25352 }
25354 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25355 by DEP_INSN and nothing set by DEP_INSN. */
25357 static bool
25359 {
25362 /* Simplify the test for uninteresting insns. */
25370 {
25373 }
25378 {
25381 }
25382 else
25388 /* This test is true if the dependent insn reads the flags but
25389 not any other potentially set register. */
25397 }
25399 /* Return true iff USE_INSN has a memory address with operands set by
25400 SET_INSN. */
25402 bool
25404 {
25409 {
25412 }
25414 }
25416 /* Helper function for exact_store_load_dependency.
25417 Return true if addr is found in insn. */
25418 static bool
25420 {
25427 {
25433 CASE_CONST_ANY:
25442 }
25446 {
25448 {
25458 }
25459 }
25461 }
25463 /* Return true if there exists exact dependency for store & load, i.e.
25464 the same memory address is used in them. */
25465 static bool
25467 {
25481 }
25483 static int
25485 {
25491 /* Anti and output dependencies have zero cost on all CPUs. */
25497 /* If we can't recognize the insns, we can't really do anything. */
25505 {
25507 /* Address Generation Interlock adds a cycle of latency. */
25509 {
25520 }
25524 /* ??? Compares pair with jump/setcc. */
25528 /* Floating point stores require value to be ready one cycle earlier. */
25536 /* INT->FP conversion is expensive. */
25540 /* There is one cycle extra latency between an FP op and a store. */
25550 /* Show ability of reorder buffer to hide latency of load by executing
25551 in parallel with previous instruction in case
25552 previous instruction is not needed to compute the address. */
25555 {
25556 /* Claim moves to take one cycle, as core can issue one load
25557 at time and the next load can start cycle later. */
25562 cost--;
25563 }
25567 /* The esp dependency is resolved before
25568 the instruction is really finished. */
25573 /* INT->FP conversion is expensive. */
25579 /* Show ability of reorder buffer to hide latency of load by executing
25580 in parallel with previous instruction in case
25581 previous instruction is not needed to compute the address. */
25584 {
25585 /* Claim moves to take one cycle, as core can issue one load
25586 at time and the next load can start cycle later. */
25592 else
25594 }
25605 /* Stack engine allows to execute push&pop instructions in parall. */
25609 /* FALLTHRU */
25615 /* Show ability of reorder buffer to hide latency of load by executing
25616 in parallel with previous instruction in case
25617 previous instruction is not needed to compute the address. */
25620 {
25624 /* Because of the difference between the length of integer and
25625 floating unit pipeline preparation stages, the memory operands
25626 for floating point are cheaper.
25628 ??? For Athlon it the difference is most probably 2. */
25631 else
25636 else
25638 }
25645 /* Stack engine allows to execute push&pop instructions in parall. */
25652 /* Show ability of reorder buffer to hide latency of load by executing
25653 in parallel with previous instruction in case
25654 previous instruction is not needed to compute the address. */
25657 {
25660 else
25662 }
25670 /* Increase cost of integer loads. */
25673 {
25676 {
25679 else
25680 {
25681 /* Increase cost of ld/st for short int types only
25682 because of store forwarding issue. */
25686 {
25687 /* Increase cost of store/load insn if exact
25688 dependence exists and it is load insn. */
25693 }
25694 }
25695 }
25696 }
25700 }
25703 }
25705 /* How many alternative schedules to try. This should be as wide as the
25706 scheduling freedom in the DFA, but no wider. Making this value too
25707 large results extra work for the scheduler. */
25709 static int
25711 {
25713 {
25725 /* We use lookahead value 4 for BD both before and after reload
25726 schedules. Plan is to have value 8 included for O3. */
25736 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25737 as many instructions can be executed on a cycle, i.e.,
25738 issue_rate. I wonder why tuning for many CPUs does not do this. */
25741 /* Don't use lookahead for pre-reload schedule to save compile time. */
25746 }
25747 }
25749 /* Return true if target platform supports macro-fusion. */
25751 static bool
25753 {
25755 }
25757 /* Check whether current microarchitecture support macro fusion
25758 for insn pair "CONDGEN + CONDJMP". Refer to
25759 "Intel Architectures Optimization Reference Manual". */
25761 static bool
25763 {
25782 else
25783 {
25788 {
25792 else
25794 }
25795 }
25802 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25803 supported. */
25810 /* No fusion for RIP-relative address. */
25817 ix86_address parts;
25823 }
25828 /* Check whether conditional jump use Sign or Overflow Flags. */
25836 /* Return true for TYPE_TEST and TYPE_ICMP. */
25841 /* The following is the case that macro-fusion for alu + jmp. */
25845 /* No fusion for alu op with memory destination operand. */
25850 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25851 supported. */
25860 }
25862 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25863 execution. It is applied if
25864 (1) IMUL instruction is on the top of list;
25865 (2) There exists the only producer of independent IMUL instruction in
25866 ready list.
25867 Return index of IMUL producer if it was found and -1 otherwise. */
25868 static int
25870 {
25872 sd_iterator_def sd_it;
25873 dep_t dep;
25880 /* Check that IMUL instruction is on the top of ready list. */
25889 /* Search for producer of independent IMUL instruction. */
25891 {
25895 /* Skip IMUL instruction. */
25905 {
25906 rtx con;
25917 {
25918 sd_iterator_def sd_it1;
25919 dep_t dep1;
25920 /* Check if there is no other dependee for IMUL. */
25923 {
25924 rtx pro;
25930 }
25933 }
25934 }
25937 }
25939 }
25941 /* Try to find the best candidate on the top of ready list if two insns
25942 have the same priority - candidate is best if its dependees were
25943 scheduled earlier. Applied for Silvermont only.
25944 Return true if top 2 insns must be interchanged. */
25945 static bool
25947 {
25950 rtx set;
25951 sd_iterator_def sd_it;
25952 dep_t dep;
25955 #define INSN_TICK(INSN) (HID (INSN)->tick)
25976 {
25979 /* Determine winner more precise. */
25981 {
25982 rtx pro;
25988 }
25990 {
25991 rtx pro;
25997 }
26000 {
26001 /* Determine winner - load must win. */
26007 }
26009 }
26011 #undef INSN_TICK
26012 }
26014 /* Perform possible reodering of ready list for Atom/Silvermont only.
26015 Return issue rate. */
26016 static int
26019 {
26023 rtx insn;
26026 /* Set up issue rate. */
26029 /* Do reodering for BONNELL/SILVERMONT only. */
26033 /* Nothing to do if ready list contains only 1 instruction. */
26037 /* Do reodering for post-reload scheduler only. */
26042 {
26047 /* Put IMUL producer (ready[index]) at the top of ready list. */
26053 }
26055 {
26059 /* Swap 2 top elements of ready list. */
26063 }
26065 }
26067 static bool
26070 /* Returns true if lhs of insn is HW function argument register and set up
26071 is_spilled to true if it is likely spilled HW register. */
26072 static bool
26074 {
26075 rtx dst;
26079 /* Call instructions are not movable, ignore it. */
26090 {
26091 /* Is it likely spilled HW register? */
26096 }
26098 }
26100 /* Add output dependencies for chain of function adjacent arguments if only
26101 there is a move to likely spilled HW register. Return first argument
26102 if at least one dependence was added or NULL otherwise. */
26103 static rtx
26105 {
26106 rtx insn;
26113 /* Find nearest to call argument passing instruction. */
26115 {
26124 }
26128 {
26135 {
26138 }
26140 {
26141 /* Add output depdendence between two function arguments if chain
26142 of output arguments contains likely spilled HW registers. */
26146 }
26147 else
26149 }
26153 }
26155 /* Add output or anti dependency from insn to first_arg to restrict its code
26156 motion. */
26157 static void
26159 {
26160 rtx set;
26161 rtx tmp;
26168 {
26169 /* Add output dependency to the first function argument. */
26172 }
26173 /* Add anti dependency. */
26175 }
26177 /* Avoid cross block motion of function argument through adding dependency
26178 from the first non-jump instruction in bb. */
26179 static void
26181 {
26185 {
26187 {
26190 {
26193 }
26194 }
26198 }
26199 }
26201 /* Hook for pre-reload schedule - avoid motion of function arguments
26202 passed in likely spilled HW registers. */
26203 static void
26205 {
26206 rtx insn;
26214 {
26217 {
26218 /* Add dependee for first argument to predecessors if only
26219 region contains more than one block. */
26223 /* Skip trivial regions and region head blocks that can have
26224 predecessors outside of region. */
26226 {
26227 edge e;
26228 edge_iterator ei;
26229 /* Assume that region is SCC, i.e. all immediate predecessors
26230 of non-head block are in the same region. */
26232 {
26233 /* Avoid creating of loop-carried dependencies through
26234 using topological odering in region. */
26237 }
26238 }
26242 }
26243 }
26246 }
26248 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26249 HW registers to maximum, to schedule them at soon as possible. These are
26250 moves from function argument registers at the top of the function entry
26251 and moves from function return value registers after call. */
26252 static int
26254 {
26255 rtx set;
26265 {
26272 }
26275 }
26277 /* Model decoder of Core 2/i7.
26278 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26279 track the instruction fetch block boundaries and make sure that long
26280 (9+ bytes) instructions are assigned to D0. */
26282 /* Maximum length of an insn that can be handled by
26283 a secondary decoder unit. '8' for Core 2/i7. */
26286 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26287 '16' for Core 2/i7. */
26290 /* Maximum number of instructions decoder can handle per cycle.
26291 '6' for Core 2/i7. */
26295 ix86_first_cycle_multipass_data_t;
26297 const_ix86_first_cycle_multipass_data_t;
26299 /* A variable to store target state across calls to max_issue within
26300 one cycle. */
26304 /* Initialize DATA. */
26305 static void
26307 {
26308 ix86_first_cycle_multipass_data_t data
26315 }
26317 /* Advancing the cycle; reset ifetch block counts. */
26318 static void
26320 {
26327 }
26331 /* Filter out insns from ready_try that the core will not be able to issue
26332 on current cycle due to decoder. */
26333 static void
26334 core2i7_first_cycle_multipass_filter_ready_try
26337 {
26339 {
26340 rtx insn;
26350 (!first_cycle_insn_p
26352 /* ... or it would not fit into the ifetch block ... */
26354 /* ... or the decoder is full already ... */
26356 /* ... mask the insn out. */
26357 {
26362 }
26363 }
26364 }
26366 /* Prepare for a new round of multipass lookahead scheduling. */
26367 static void
26370 {
26371 ix86_first_cycle_multipass_data_t data
26373 const_ix86_first_cycle_multipass_data_t prev_data
26376 /* Restore the state from the end of the previous round. */
26380 /* Filter instructions that cannot be issued on current cycle due to
26381 decoder restrictions. */
26383 first_cycle_insn_p);
26384 }
26386 /* INSN is being issued in current solution. Account for its impact on
26387 the decoder model. */
26388 static void
26391 {
26392 ix86_first_cycle_multipass_data_t data
26394 const_ix86_first_cycle_multipass_data_t prev_data
26404 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26406 {
26409 }
26411 {
26415 }
26418 /* Filter out insns from ready_try that the core will not be able to issue
26419 on current cycle due to decoder. */
26422 }
26424 /* Revert the effect on ready_try. */
26425 static void
26429 {
26430 const_ix86_first_cycle_multipass_data_t data
26433 sbitmap_iterator sbi;
26437 {
26439 }
26440 }
26442 /* Save the result of multipass lookahead scheduling for the next round. */
26443 static void
26445 {
26446 const_ix86_first_cycle_multipass_data_t data
26448 ix86_first_cycle_multipass_data_t next_data
26452 {
26455 }
26456 }
26458 /* Deallocate target data. */
26459 static void
26461 {
26462 ix86_first_cycle_multipass_data_t data
26466 {
26470 }
26471 }
26473 /* Prepare for scheduling pass. */
26474 static void
26478 {
26479 /* Install scheduling hooks for current CPU. Some of these hooks are used
26480 in time-critical parts of the scheduler, so we only set them up when
26481 they are actually used. */
26483 {
26488 /* Do not perform multipass scheduling for pre-reload schedule
26489 to save compile time. */
26491 {
26507 /* Set decoder parameters. */
26512 }
26513 /* ... Fall through ... */
26523 }
26524 }
26526 \f
26527 /* Compute the alignment given to a constant that is being placed in memory.
26528 EXP is the constant and ALIGN is the alignment that the object would
26529 ordinarily have.
26530 The value of this function is used instead of that alignment to align
26531 the object. */
26533 int
26535 {
26538 {
26543 }
26549 }
26551 /* Compute the alignment for a static variable.
26552 TYPE is the data type, and ALIGN is the alignment that
26553 the object would ordinarily have. The value of this function is used
26554 instead of that alignment to align the object. */
26556 int
26558 {
26559 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26560 for symbols from other compilation units or symbols that don't need
26561 to bind locally. In order to preserve some ABI compatibility with
26562 those compilers, ensure we don't decrease alignment from what we
26563 used to assume. */
26565 int max_align_compat
26568 /* A data structure, equal or greater than the size of a cache line
26569 (64 bytes in the Pentium 4 and other recent Intel processors, including
26570 processors based on Intel Core microarchitecture) should be aligned
26571 so that its base address is a multiple of a cache line size. */
26573 int max_align
26583 {
26592 }
26594 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26595 to 16byte boundary. */
26597 {
26604 }
26610 {
26615 }
26617 {
26624 }
26629 {
26634 }
26637 {
26642 }
26645 }
26647 /* Compute the alignment for a local variable or a stack slot. EXP is
26648 the data type or decl itself, MODE is the widest mode available and
26649 ALIGN is the alignment that the object would ordinarily have. The
26650 value of this macro is used instead of that alignment to align the
26651 object. */
26653 unsigned int
26656 {
26660 {
26663 }
26664 else
26665 {
26668 }
26670 /* Don't do dynamic stack realignment for long long objects with
26671 -mpreferred-stack-boundary=2. */
26680 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26681 register in MODE. We will return the largest alignment of XF
26682 and DF. */
26684 {
26688 }
26690 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26691 to 16byte boundary. Exact wording is:
26693 An array uses the same alignment as its elements, except that a local or
26694 global array variable of length at least 16 bytes or
26695 a C99 variable-length array variable always has alignment of at least 16 bytes.
26697 This was added to allow use of aligned SSE instructions at arrays. This
26698 rule is meant for static storage (where compiler can not do the analysis
26699 by itself). We follow it for automatic variables only when convenient.
26700 We fully control everything in the function compiled and functions from
26701 other unit can not rely on the alignment.
26703 Exclude va_list type. It is the common case of local array where
26704 we can not benefit from the alignment.
26706 TODO: Probably one should optimize for size only when var is not escaping. */
26709 {
26719 }
26721 {
26726 }
26728 {
26734 }
26739 {
26744 }
26747 {
26753 }
26755 }
26757 /* Compute the minimum required alignment for dynamic stack realignment
26758 purposes for a local variable, parameter or a stack slot. EXP is
26759 the data type or decl itself, MODE is its mode and ALIGN is the
26760 alignment that the object would ordinarily have. */
26762 unsigned int
26765 {
26769 {
26772 }
26773 else
26774 {
26777 }
26782 /* Don't do dynamic stack realignment for long long objects with
26783 -mpreferred-stack-boundary=2. */
26790 }
26791 \f
26792 /* Find a location for the static chain incoming to a nested function.
26793 This is a register, unless all free registers are used by arguments. */
26795 static rtx
26797 {
26804 {
26805 /* We always use R10 in 64-bit mode. */
26807 }
26808 else
26809 {
26810 tree fntype;
26813 /* By default in 32-bit mode we use ECX to pass the static chain. */
26819 {
26820 /* Fastcall functions use ecx/edx for arguments, which leaves
26821 us with EAX for the static chain.
26822 Thiscall functions use ecx for arguments, which also
26823 leaves us with EAX for the static chain. */
26825 }
26827 {
26828 /* Thiscall functions use ecx for arguments, which leaves
26829 us with EAX and EDX for the static chain.
26830 We are using for abi-compatibility EAX. */
26832 }
26834 {
26835 /* For regparm 3, we have no free call-clobbered registers in
26836 which to store the static chain. In order to implement this,
26837 we have the trampoline push the static chain to the stack.
26838 However, we can't push a value below the return address when
26839 we call the nested function directly, so we have to use an
26840 alternate entry point. For this we use ESI, and have the
26841 alternate entry point push ESI, so that things appear the
26842 same once we're executing the nested function. */
26844 {
26850 }
26852 }
26853 }
26856 }
26858 /* Emit RTL insns to initialize the variable parts of a trampoline.
26859 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26860 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26861 to be passed to the target function. */
26863 static void
26865 {
26873 {
26876 /* Load the function address to r11. Try to load address using
26877 the shorter movl instead of movabs. We may want to support
26878 movq for kernel mode, but kernel does not use trampolines at
26879 the moment. FNADDR is a 32bit address and may not be in
26880 DImode when ptr_mode == SImode. Always use movl in this
26881 case. */
26884 {
26893 }
26894 else
26895 {
26902 }
26904 /* Load static chain using movabs to r10. Use the shorter movl
26905 instead of movabs when ptr_mode == SImode. */
26907 {
26910 }
26911 else
26912 {
26915 }
26924 /* Jump to r11; the last (unused) byte is a nop, only there to
26925 pad the write out to a single 32-bit store. */
26929 }
26930 else
26931 {
26934 /* Depending on the static chain location, either load a register
26935 with a constant, or push the constant to the stack. All of the
26936 instructions are the same size. */
26939 {
26941 {
26948 }
26949 }
26950 else
26965 /* Compute offset from the end of the jmp to the target function.
26966 In the case in which the trampoline stores the static chain on
26967 the stack, we need to skip the first insn which pushes the
26968 (call-saved) register static chain; this push is 1 byte. */
26975 }
26979 #ifdef HAVE_ENABLE_EXECUTE_STACK
26980 #ifdef CHECK_EXECUTE_STACK_ENABLED
26982 #endif
26985 #endif
26986 }
26987 \f
26988 /* The following file contains several enumerations and data structures
26989 built from the definitions in i386-builtin-types.def. */
26993 /* Table for the ix86 builtin non-function types. */
26996 /* Retrieve an element from the above table, building some of
26997 the types lazily. */
26999 static tree
27001 {
27013 {
27021 }
27022 else
27023 {
27029 else
27037 }
27041 }
27043 /* Table for the ix86 builtin function types. */
27046 /* Retrieve an element from the above table, building some of
27047 the types lazily. */
27049 static tree
27051 {
27052 tree type;
27061 {
27069 {
27072 }
27075 }
27076 else
27077 {
27083 }
27087 }
27090 /* Codes for all the SSE/MMX builtins. */
27091 enum ix86_builtins
27092 {
27093 IX86_BUILTIN_ADDPS,
27094 IX86_BUILTIN_ADDSS,
27095 IX86_BUILTIN_DIVPS,
27096 IX86_BUILTIN_DIVSS,
27097 IX86_BUILTIN_MULPS,
27098 IX86_BUILTIN_MULSS,
27099 IX86_BUILTIN_SUBPS,
27100 IX86_BUILTIN_SUBSS,
27102 IX86_BUILTIN_CMPEQPS,
27103 IX86_BUILTIN_CMPLTPS,
27104 IX86_BUILTIN_CMPLEPS,
27105 IX86_BUILTIN_CMPGTPS,
27106 IX86_BUILTIN_CMPGEPS,
27107 IX86_BUILTIN_CMPNEQPS,
27108 IX86_BUILTIN_CMPNLTPS,
27109 IX86_BUILTIN_CMPNLEPS,
27110 IX86_BUILTIN_CMPNGTPS,
27111 IX86_BUILTIN_CMPNGEPS,
27112 IX86_BUILTIN_CMPORDPS,
27113 IX86_BUILTIN_CMPUNORDPS,
27114 IX86_BUILTIN_CMPEQSS,
27115 IX86_BUILTIN_CMPLTSS,
27116 IX86_BUILTIN_CMPLESS,
27117 IX86_BUILTIN_CMPNEQSS,
27118 IX86_BUILTIN_CMPNLTSS,
27119 IX86_BUILTIN_CMPNLESS,
27120 IX86_BUILTIN_CMPORDSS,
27121 IX86_BUILTIN_CMPUNORDSS,
27123 IX86_BUILTIN_COMIEQSS,
27124 IX86_BUILTIN_COMILTSS,
27125 IX86_BUILTIN_COMILESS,
27126 IX86_BUILTIN_COMIGTSS,
27127 IX86_BUILTIN_COMIGESS,
27128 IX86_BUILTIN_COMINEQSS,
27129 IX86_BUILTIN_UCOMIEQSS,
27130 IX86_BUILTIN_UCOMILTSS,
27131 IX86_BUILTIN_UCOMILESS,
27132 IX86_BUILTIN_UCOMIGTSS,
27133 IX86_BUILTIN_UCOMIGESS,
27134 IX86_BUILTIN_UCOMINEQSS,
27136 IX86_BUILTIN_CVTPI2PS,
27137 IX86_BUILTIN_CVTPS2PI,
27138 IX86_BUILTIN_CVTSI2SS,
27139 IX86_BUILTIN_CVTSI642SS,
27140 IX86_BUILTIN_CVTSS2SI,
27141 IX86_BUILTIN_CVTSS2SI64,
27142 IX86_BUILTIN_CVTTPS2PI,
27143 IX86_BUILTIN_CVTTSS2SI,
27144 IX86_BUILTIN_CVTTSS2SI64,
27146 IX86_BUILTIN_MAXPS,
27147 IX86_BUILTIN_MAXSS,
27148 IX86_BUILTIN_MINPS,
27149 IX86_BUILTIN_MINSS,
27151 IX86_BUILTIN_LOADUPS,
27152 IX86_BUILTIN_STOREUPS,
27153 IX86_BUILTIN_MOVSS,
27155 IX86_BUILTIN_MOVHLPS,
27156 IX86_BUILTIN_MOVLHPS,
27157 IX86_BUILTIN_LOADHPS,
27158 IX86_BUILTIN_LOADLPS,
27159 IX86_BUILTIN_STOREHPS,
27160 IX86_BUILTIN_STORELPS,
27162 IX86_BUILTIN_MASKMOVQ,
27163 IX86_BUILTIN_MOVMSKPS,
27164 IX86_BUILTIN_PMOVMSKB,
27166 IX86_BUILTIN_MOVNTPS,
27167 IX86_BUILTIN_MOVNTQ,
27169 IX86_BUILTIN_LOADDQU,
27170 IX86_BUILTIN_STOREDQU,
27172 IX86_BUILTIN_PACKSSWB,
27173 IX86_BUILTIN_PACKSSDW,
27174 IX86_BUILTIN_PACKUSWB,
27176 IX86_BUILTIN_PADDB,
27177 IX86_BUILTIN_PADDW,
27178 IX86_BUILTIN_PADDD,
27179 IX86_BUILTIN_PADDQ,
27180 IX86_BUILTIN_PADDSB,
27181 IX86_BUILTIN_PADDSW,
27182 IX86_BUILTIN_PADDUSB,
27183 IX86_BUILTIN_PADDUSW,
27184 IX86_BUILTIN_PSUBB,
27185 IX86_BUILTIN_PSUBW,
27186 IX86_BUILTIN_PSUBD,
27187 IX86_BUILTIN_PSUBQ,
27188 IX86_BUILTIN_PSUBSB,
27189 IX86_BUILTIN_PSUBSW,
27190 IX86_BUILTIN_PSUBUSB,
27191 IX86_BUILTIN_PSUBUSW,
27193 IX86_BUILTIN_PAND,
27194 IX86_BUILTIN_PANDN,
27195 IX86_BUILTIN_POR,
27196 IX86_BUILTIN_PXOR,
27198 IX86_BUILTIN_PAVGB,
27199 IX86_BUILTIN_PAVGW,
27201 IX86_BUILTIN_PCMPEQB,
27202 IX86_BUILTIN_PCMPEQW,
27203 IX86_BUILTIN_PCMPEQD,
27204 IX86_BUILTIN_PCMPGTB,
27205 IX86_BUILTIN_PCMPGTW,
27206 IX86_BUILTIN_PCMPGTD,
27208 IX86_BUILTIN_PMADDWD,
27210 IX86_BUILTIN_PMAXSW,
27211 IX86_BUILTIN_PMAXUB,
27212 IX86_BUILTIN_PMINSW,
27213 IX86_BUILTIN_PMINUB,
27215 IX86_BUILTIN_PMULHUW,
27216 IX86_BUILTIN_PMULHW,
27217 IX86_BUILTIN_PMULLW,
27219 IX86_BUILTIN_PSADBW,
27220 IX86_BUILTIN_PSHUFW,
27222 IX86_BUILTIN_PSLLW,
27223 IX86_BUILTIN_PSLLD,
27224 IX86_BUILTIN_PSLLQ,
27225 IX86_BUILTIN_PSRAW,
27226 IX86_BUILTIN_PSRAD,
27227 IX86_BUILTIN_PSRLW,
27228 IX86_BUILTIN_PSRLD,
27229 IX86_BUILTIN_PSRLQ,
27230 IX86_BUILTIN_PSLLWI,
27231 IX86_BUILTIN_PSLLDI,
27232 IX86_BUILTIN_PSLLQI,
27233 IX86_BUILTIN_PSRAWI,
27234 IX86_BUILTIN_PSRADI,
27235 IX86_BUILTIN_PSRLWI,
27236 IX86_BUILTIN_PSRLDI,
27237 IX86_BUILTIN_PSRLQI,
27239 IX86_BUILTIN_PUNPCKHBW,
27240 IX86_BUILTIN_PUNPCKHWD,
27241 IX86_BUILTIN_PUNPCKHDQ,
27242 IX86_BUILTIN_PUNPCKLBW,
27243 IX86_BUILTIN_PUNPCKLWD,
27244 IX86_BUILTIN_PUNPCKLDQ,
27246 IX86_BUILTIN_SHUFPS,
27248 IX86_BUILTIN_RCPPS,
27249 IX86_BUILTIN_RCPSS,
27250 IX86_BUILTIN_RSQRTPS,
27251 IX86_BUILTIN_RSQRTPS_NR,
27252 IX86_BUILTIN_RSQRTSS,
27253 IX86_BUILTIN_RSQRTF,
27254 IX86_BUILTIN_SQRTPS,
27255 IX86_BUILTIN_SQRTPS_NR,
27256 IX86_BUILTIN_SQRTSS,
27258 IX86_BUILTIN_UNPCKHPS,
27259 IX86_BUILTIN_UNPCKLPS,
27261 IX86_BUILTIN_ANDPS,
27262 IX86_BUILTIN_ANDNPS,
27263 IX86_BUILTIN_ORPS,
27264 IX86_BUILTIN_XORPS,
27266 IX86_BUILTIN_EMMS,
27267 IX86_BUILTIN_LDMXCSR,
27268 IX86_BUILTIN_STMXCSR,
27269 IX86_BUILTIN_SFENCE,
27271 IX86_BUILTIN_FXSAVE,
27272 IX86_BUILTIN_FXRSTOR,
27273 IX86_BUILTIN_FXSAVE64,
27274 IX86_BUILTIN_FXRSTOR64,
27276 IX86_BUILTIN_XSAVE,
27277 IX86_BUILTIN_XRSTOR,
27278 IX86_BUILTIN_XSAVE64,
27279 IX86_BUILTIN_XRSTOR64,
27281 IX86_BUILTIN_XSAVEOPT,
27282 IX86_BUILTIN_XSAVEOPT64,
27284 /* 3DNow! Original */
27285 IX86_BUILTIN_FEMMS,
27286 IX86_BUILTIN_PAVGUSB,
27287 IX86_BUILTIN_PF2ID,
27288 IX86_BUILTIN_PFACC,
27289 IX86_BUILTIN_PFADD,
27290 IX86_BUILTIN_PFCMPEQ,
27291 IX86_BUILTIN_PFCMPGE,
27292 IX86_BUILTIN_PFCMPGT,
27293 IX86_BUILTIN_PFMAX,
27294 IX86_BUILTIN_PFMIN,
27295 IX86_BUILTIN_PFMUL,
27296 IX86_BUILTIN_PFRCP,
27297 IX86_BUILTIN_PFRCPIT1,
27298 IX86_BUILTIN_PFRCPIT2,
27299 IX86_BUILTIN_PFRSQIT1,
27300 IX86_BUILTIN_PFRSQRT,
27301 IX86_BUILTIN_PFSUB,
27302 IX86_BUILTIN_PFSUBR,
27303 IX86_BUILTIN_PI2FD,
27304 IX86_BUILTIN_PMULHRW,
27306 /* 3DNow! Athlon Extensions */
27307 IX86_BUILTIN_PF2IW,
27308 IX86_BUILTIN_PFNACC,
27309 IX86_BUILTIN_PFPNACC,
27310 IX86_BUILTIN_PI2FW,
27311 IX86_BUILTIN_PSWAPDSI,
27312 IX86_BUILTIN_PSWAPDSF,
27314 /* SSE2 */
27315 IX86_BUILTIN_ADDPD,
27316 IX86_BUILTIN_ADDSD,
27317 IX86_BUILTIN_DIVPD,
27318 IX86_BUILTIN_DIVSD,
27319 IX86_BUILTIN_MULPD,
27320 IX86_BUILTIN_MULSD,
27321 IX86_BUILTIN_SUBPD,
27322 IX86_BUILTIN_SUBSD,
27324 IX86_BUILTIN_CMPEQPD,
27325 IX86_BUILTIN_CMPLTPD,
27326 IX86_BUILTIN_CMPLEPD,
27327 IX86_BUILTIN_CMPGTPD,
27328 IX86_BUILTIN_CMPGEPD,
27329 IX86_BUILTIN_CMPNEQPD,
27330 IX86_BUILTIN_CMPNLTPD,
27331 IX86_BUILTIN_CMPNLEPD,
27332 IX86_BUILTIN_CMPNGTPD,
27333 IX86_BUILTIN_CMPNGEPD,
27334 IX86_BUILTIN_CMPORDPD,
27335 IX86_BUILTIN_CMPUNORDPD,
27336 IX86_BUILTIN_CMPEQSD,
27337 IX86_BUILTIN_CMPLTSD,
27338 IX86_BUILTIN_CMPLESD,
27339 IX86_BUILTIN_CMPNEQSD,
27340 IX86_BUILTIN_CMPNLTSD,
27341 IX86_BUILTIN_CMPNLESD,
27342 IX86_BUILTIN_CMPORDSD,
27343 IX86_BUILTIN_CMPUNORDSD,
27345 IX86_BUILTIN_COMIEQSD,
27346 IX86_BUILTIN_COMILTSD,
27347 IX86_BUILTIN_COMILESD,
27348 IX86_BUILTIN_COMIGTSD,
27349 IX86_BUILTIN_COMIGESD,
27350 IX86_BUILTIN_COMINEQSD,
27351 IX86_BUILTIN_UCOMIEQSD,
27352 IX86_BUILTIN_UCOMILTSD,
27353 IX86_BUILTIN_UCOMILESD,
27354 IX86_BUILTIN_UCOMIGTSD,
27355 IX86_BUILTIN_UCOMIGESD,
27356 IX86_BUILTIN_UCOMINEQSD,
27358 IX86_BUILTIN_MAXPD,
27359 IX86_BUILTIN_MAXSD,
27360 IX86_BUILTIN_MINPD,
27361 IX86_BUILTIN_MINSD,
27363 IX86_BUILTIN_ANDPD,
27364 IX86_BUILTIN_ANDNPD,
27365 IX86_BUILTIN_ORPD,
27366 IX86_BUILTIN_XORPD,
27368 IX86_BUILTIN_SQRTPD,
27369 IX86_BUILTIN_SQRTSD,
27371 IX86_BUILTIN_UNPCKHPD,
27372 IX86_BUILTIN_UNPCKLPD,
27374 IX86_BUILTIN_SHUFPD,
27376 IX86_BUILTIN_LOADUPD,
27377 IX86_BUILTIN_STOREUPD,
27378 IX86_BUILTIN_MOVSD,
27380 IX86_BUILTIN_LOADHPD,
27381 IX86_BUILTIN_LOADLPD,
27383 IX86_BUILTIN_CVTDQ2PD,
27384 IX86_BUILTIN_CVTDQ2PS,
27386 IX86_BUILTIN_CVTPD2DQ,
27387 IX86_BUILTIN_CVTPD2PI,
27388 IX86_BUILTIN_CVTPD2PS,
27389 IX86_BUILTIN_CVTTPD2DQ,
27390 IX86_BUILTIN_CVTTPD2PI,
27392 IX86_BUILTIN_CVTPI2PD,
27393 IX86_BUILTIN_CVTSI2SD,
27394 IX86_BUILTIN_CVTSI642SD,
27396 IX86_BUILTIN_CVTSD2SI,
27397 IX86_BUILTIN_CVTSD2SI64,
27398 IX86_BUILTIN_CVTSD2SS,
27399 IX86_BUILTIN_CVTSS2SD,
27400 IX86_BUILTIN_CVTTSD2SI,
27401 IX86_BUILTIN_CVTTSD2SI64,
27403 IX86_BUILTIN_CVTPS2DQ,
27404 IX86_BUILTIN_CVTPS2PD,
27405 IX86_BUILTIN_CVTTPS2DQ,
27407 IX86_BUILTIN_MOVNTI,
27408 IX86_BUILTIN_MOVNTI64,
27409 IX86_BUILTIN_MOVNTPD,
27410 IX86_BUILTIN_MOVNTDQ,
27412 IX86_BUILTIN_MOVQ128,
27414 /* SSE2 MMX */
27415 IX86_BUILTIN_MASKMOVDQU,
27416 IX86_BUILTIN_MOVMSKPD,
27417 IX86_BUILTIN_PMOVMSKB128,
27419 IX86_BUILTIN_PACKSSWB128,
27420 IX86_BUILTIN_PACKSSDW128,
27421 IX86_BUILTIN_PACKUSWB128,
27423 IX86_BUILTIN_PADDB128,
27424 IX86_BUILTIN_PADDW128,
27425 IX86_BUILTIN_PADDD128,
27426 IX86_BUILTIN_PADDQ128,
27427 IX86_BUILTIN_PADDSB128,
27428 IX86_BUILTIN_PADDSW128,
27429 IX86_BUILTIN_PADDUSB128,
27430 IX86_BUILTIN_PADDUSW128,
27431 IX86_BUILTIN_PSUBB128,
27432 IX86_BUILTIN_PSUBW128,
27433 IX86_BUILTIN_PSUBD128,
27434 IX86_BUILTIN_PSUBQ128,
27435 IX86_BUILTIN_PSUBSB128,
27436 IX86_BUILTIN_PSUBSW128,
27437 IX86_BUILTIN_PSUBUSB128,
27438 IX86_BUILTIN_PSUBUSW128,
27440 IX86_BUILTIN_PAND128,
27441 IX86_BUILTIN_PANDN128,
27442 IX86_BUILTIN_POR128,
27443 IX86_BUILTIN_PXOR128,
27445 IX86_BUILTIN_PAVGB128,
27446 IX86_BUILTIN_PAVGW128,
27448 IX86_BUILTIN_PCMPEQB128,
27449 IX86_BUILTIN_PCMPEQW128,
27450 IX86_BUILTIN_PCMPEQD128,
27451 IX86_BUILTIN_PCMPGTB128,
27452 IX86_BUILTIN_PCMPGTW128,
27453 IX86_BUILTIN_PCMPGTD128,
27455 IX86_BUILTIN_PMADDWD128,
27457 IX86_BUILTIN_PMAXSW128,
27458 IX86_BUILTIN_PMAXUB128,
27459 IX86_BUILTIN_PMINSW128,
27460 IX86_BUILTIN_PMINUB128,
27462 IX86_BUILTIN_PMULUDQ,
27463 IX86_BUILTIN_PMULUDQ128,
27464 IX86_BUILTIN_PMULHUW128,
27465 IX86_BUILTIN_PMULHW128,
27466 IX86_BUILTIN_PMULLW128,
27468 IX86_BUILTIN_PSADBW128,
27469 IX86_BUILTIN_PSHUFHW,
27470 IX86_BUILTIN_PSHUFLW,
27471 IX86_BUILTIN_PSHUFD,
27473 IX86_BUILTIN_PSLLDQI128,
27474 IX86_BUILTIN_PSLLWI128,
27475 IX86_BUILTIN_PSLLDI128,
27476 IX86_BUILTIN_PSLLQI128,
27477 IX86_BUILTIN_PSRAWI128,
27478 IX86_BUILTIN_PSRADI128,
27479 IX86_BUILTIN_PSRLDQI128,
27480 IX86_BUILTIN_PSRLWI128,
27481 IX86_BUILTIN_PSRLDI128,
27482 IX86_BUILTIN_PSRLQI128,
27484 IX86_BUILTIN_PSLLDQ128,
27485 IX86_BUILTIN_PSLLW128,
27486 IX86_BUILTIN_PSLLD128,
27487 IX86_BUILTIN_PSLLQ128,
27488 IX86_BUILTIN_PSRAW128,
27489 IX86_BUILTIN_PSRAD128,
27490 IX86_BUILTIN_PSRLW128,
27491 IX86_BUILTIN_PSRLD128,
27492 IX86_BUILTIN_PSRLQ128,
27494 IX86_BUILTIN_PUNPCKHBW128,
27495 IX86_BUILTIN_PUNPCKHWD128,
27496 IX86_BUILTIN_PUNPCKHDQ128,
27497 IX86_BUILTIN_PUNPCKHQDQ128,
27498 IX86_BUILTIN_PUNPCKLBW128,
27499 IX86_BUILTIN_PUNPCKLWD128,
27500 IX86_BUILTIN_PUNPCKLDQ128,
27501 IX86_BUILTIN_PUNPCKLQDQ128,
27503 IX86_BUILTIN_CLFLUSH,
27504 IX86_BUILTIN_MFENCE,
27505 IX86_BUILTIN_LFENCE,
27506 IX86_BUILTIN_PAUSE,
27508 IX86_BUILTIN_FNSTENV,
27509 IX86_BUILTIN_FLDENV,
27510 IX86_BUILTIN_FNSTSW,
27511 IX86_BUILTIN_FNCLEX,
27513 IX86_BUILTIN_BSRSI,
27514 IX86_BUILTIN_BSRDI,
27515 IX86_BUILTIN_RDPMC,
27516 IX86_BUILTIN_RDTSC,
27517 IX86_BUILTIN_RDTSCP,
27518 IX86_BUILTIN_ROLQI,
27519 IX86_BUILTIN_ROLHI,
27520 IX86_BUILTIN_RORQI,
27521 IX86_BUILTIN_RORHI,
27523 /* SSE3. */
27524 IX86_BUILTIN_ADDSUBPS,
27525 IX86_BUILTIN_HADDPS,
27526 IX86_BUILTIN_HSUBPS,
27527 IX86_BUILTIN_MOVSHDUP,
27528 IX86_BUILTIN_MOVSLDUP,
27529 IX86_BUILTIN_ADDSUBPD,
27530 IX86_BUILTIN_HADDPD,
27531 IX86_BUILTIN_HSUBPD,
27532 IX86_BUILTIN_LDDQU,
27534 IX86_BUILTIN_MONITOR,
27535 IX86_BUILTIN_MWAIT,
27537 /* SSSE3. */
27538 IX86_BUILTIN_PHADDW,
27539 IX86_BUILTIN_PHADDD,
27540 IX86_BUILTIN_PHADDSW,
27541 IX86_BUILTIN_PHSUBW,
27542 IX86_BUILTIN_PHSUBD,
27543 IX86_BUILTIN_PHSUBSW,
27544 IX86_BUILTIN_PMADDUBSW,
27545 IX86_BUILTIN_PMULHRSW,
27546 IX86_BUILTIN_PSHUFB,
27547 IX86_BUILTIN_PSIGNB,
27548 IX86_BUILTIN_PSIGNW,
27549 IX86_BUILTIN_PSIGND,
27550 IX86_BUILTIN_PALIGNR,
27551 IX86_BUILTIN_PABSB,
27552 IX86_BUILTIN_PABSW,
27553 IX86_BUILTIN_PABSD,
27555 IX86_BUILTIN_PHADDW128,
27556 IX86_BUILTIN_PHADDD128,
27557 IX86_BUILTIN_PHADDSW128,
27558 IX86_BUILTIN_PHSUBW128,
27559 IX86_BUILTIN_PHSUBD128,
27560 IX86_BUILTIN_PHSUBSW128,
27561 IX86_BUILTIN_PMADDUBSW128,
27562 IX86_BUILTIN_PMULHRSW128,
27563 IX86_BUILTIN_PSHUFB128,
27564 IX86_BUILTIN_PSIGNB128,
27565 IX86_BUILTIN_PSIGNW128,
27566 IX86_BUILTIN_PSIGND128,
27567 IX86_BUILTIN_PALIGNR128,
27568 IX86_BUILTIN_PABSB128,
27569 IX86_BUILTIN_PABSW128,
27570 IX86_BUILTIN_PABSD128,
27572 /* AMDFAM10 - SSE4A New Instructions. */
27573 IX86_BUILTIN_MOVNTSD,
27574 IX86_BUILTIN_MOVNTSS,
27575 IX86_BUILTIN_EXTRQI,
27576 IX86_BUILTIN_EXTRQ,
27577 IX86_BUILTIN_INSERTQI,
27578 IX86_BUILTIN_INSERTQ,
27580 /* SSE4.1. */
27581 IX86_BUILTIN_BLENDPD,
27582 IX86_BUILTIN_BLENDPS,
27583 IX86_BUILTIN_BLENDVPD,
27584 IX86_BUILTIN_BLENDVPS,
27585 IX86_BUILTIN_PBLENDVB128,
27586 IX86_BUILTIN_PBLENDW128,
27588 IX86_BUILTIN_DPPD,
27589 IX86_BUILTIN_DPPS,
27591 IX86_BUILTIN_INSERTPS128,
27593 IX86_BUILTIN_MOVNTDQA,
27594 IX86_BUILTIN_MPSADBW128,
27595 IX86_BUILTIN_PACKUSDW128,
27596 IX86_BUILTIN_PCMPEQQ,
27597 IX86_BUILTIN_PHMINPOSUW128,
27599 IX86_BUILTIN_PMAXSB128,
27600 IX86_BUILTIN_PMAXSD128,
27601 IX86_BUILTIN_PMAXUD128,
27602 IX86_BUILTIN_PMAXUW128,
27604 IX86_BUILTIN_PMINSB128,
27605 IX86_BUILTIN_PMINSD128,
27606 IX86_BUILTIN_PMINUD128,
27607 IX86_BUILTIN_PMINUW128,
27609 IX86_BUILTIN_PMOVSXBW128,
27610 IX86_BUILTIN_PMOVSXBD128,
27611 IX86_BUILTIN_PMOVSXBQ128,
27612 IX86_BUILTIN_PMOVSXWD128,
27613 IX86_BUILTIN_PMOVSXWQ128,
27614 IX86_BUILTIN_PMOVSXDQ128,
27616 IX86_BUILTIN_PMOVZXBW128,
27617 IX86_BUILTIN_PMOVZXBD128,
27618 IX86_BUILTIN_PMOVZXBQ128,
27619 IX86_BUILTIN_PMOVZXWD128,
27620 IX86_BUILTIN_PMOVZXWQ128,
27621 IX86_BUILTIN_PMOVZXDQ128,
27623 IX86_BUILTIN_PMULDQ128,
27624 IX86_BUILTIN_PMULLD128,
27626 IX86_BUILTIN_ROUNDSD,
27627 IX86_BUILTIN_ROUNDSS,
27629 IX86_BUILTIN_ROUNDPD,
27630 IX86_BUILTIN_ROUNDPS,
27632 IX86_BUILTIN_FLOORPD,
27633 IX86_BUILTIN_CEILPD,
27634 IX86_BUILTIN_TRUNCPD,
27635 IX86_BUILTIN_RINTPD,
27636 IX86_BUILTIN_ROUNDPD_AZ,
27638 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27639 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27640 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27642 IX86_BUILTIN_FLOORPS,
27643 IX86_BUILTIN_CEILPS,
27644 IX86_BUILTIN_TRUNCPS,
27645 IX86_BUILTIN_RINTPS,
27646 IX86_BUILTIN_ROUNDPS_AZ,
27648 IX86_BUILTIN_FLOORPS_SFIX,
27649 IX86_BUILTIN_CEILPS_SFIX,
27650 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27652 IX86_BUILTIN_PTESTZ,
27653 IX86_BUILTIN_PTESTC,
27654 IX86_BUILTIN_PTESTNZC,
27656 IX86_BUILTIN_VEC_INIT_V2SI,
27657 IX86_BUILTIN_VEC_INIT_V4HI,
27658 IX86_BUILTIN_VEC_INIT_V8QI,
27659 IX86_BUILTIN_VEC_EXT_V2DF,
27660 IX86_BUILTIN_VEC_EXT_V2DI,
27661 IX86_BUILTIN_VEC_EXT_V4SF,
27662 IX86_BUILTIN_VEC_EXT_V4SI,
27663 IX86_BUILTIN_VEC_EXT_V8HI,
27664 IX86_BUILTIN_VEC_EXT_V2SI,
27665 IX86_BUILTIN_VEC_EXT_V4HI,
27666 IX86_BUILTIN_VEC_EXT_V16QI,
27667 IX86_BUILTIN_VEC_SET_V2DI,
27668 IX86_BUILTIN_VEC_SET_V4SF,
27669 IX86_BUILTIN_VEC_SET_V4SI,
27670 IX86_BUILTIN_VEC_SET_V8HI,
27671 IX86_BUILTIN_VEC_SET_V4HI,
27672 IX86_BUILTIN_VEC_SET_V16QI,
27674 IX86_BUILTIN_VEC_PACK_SFIX,
27675 IX86_BUILTIN_VEC_PACK_SFIX256,
27677 /* SSE4.2. */
27678 IX86_BUILTIN_CRC32QI,
27679 IX86_BUILTIN_CRC32HI,
27680 IX86_BUILTIN_CRC32SI,
27681 IX86_BUILTIN_CRC32DI,
27683 IX86_BUILTIN_PCMPESTRI128,
27684 IX86_BUILTIN_PCMPESTRM128,
27685 IX86_BUILTIN_PCMPESTRA128,
27686 IX86_BUILTIN_PCMPESTRC128,
27687 IX86_BUILTIN_PCMPESTRO128,
27688 IX86_BUILTIN_PCMPESTRS128,
27689 IX86_BUILTIN_PCMPESTRZ128,
27690 IX86_BUILTIN_PCMPISTRI128,
27691 IX86_BUILTIN_PCMPISTRM128,
27692 IX86_BUILTIN_PCMPISTRA128,
27693 IX86_BUILTIN_PCMPISTRC128,
27694 IX86_BUILTIN_PCMPISTRO128,
27695 IX86_BUILTIN_PCMPISTRS128,
27696 IX86_BUILTIN_PCMPISTRZ128,
27698 IX86_BUILTIN_PCMPGTQ,
27700 /* AES instructions */
27701 IX86_BUILTIN_AESENC128,
27702 IX86_BUILTIN_AESENCLAST128,
27703 IX86_BUILTIN_AESDEC128,
27704 IX86_BUILTIN_AESDECLAST128,
27705 IX86_BUILTIN_AESIMC128,
27706 IX86_BUILTIN_AESKEYGENASSIST128,
27708 /* PCLMUL instruction */
27709 IX86_BUILTIN_PCLMULQDQ128,
27711 /* AVX */
27712 IX86_BUILTIN_ADDPD256,
27713 IX86_BUILTIN_ADDPS256,
27714 IX86_BUILTIN_ADDSUBPD256,
27715 IX86_BUILTIN_ADDSUBPS256,
27716 IX86_BUILTIN_ANDPD256,
27717 IX86_BUILTIN_ANDPS256,
27718 IX86_BUILTIN_ANDNPD256,
27719 IX86_BUILTIN_ANDNPS256,
27720 IX86_BUILTIN_BLENDPD256,
27721 IX86_BUILTIN_BLENDPS256,
27722 IX86_BUILTIN_BLENDVPD256,
27723 IX86_BUILTIN_BLENDVPS256,
27724 IX86_BUILTIN_DIVPD256,
27725 IX86_BUILTIN_DIVPS256,
27726 IX86_BUILTIN_DPPS256,
27727 IX86_BUILTIN_HADDPD256,
27728 IX86_BUILTIN_HADDPS256,
27729 IX86_BUILTIN_HSUBPD256,
27730 IX86_BUILTIN_HSUBPS256,
27731 IX86_BUILTIN_MAXPD256,
27732 IX86_BUILTIN_MAXPS256,
27733 IX86_BUILTIN_MINPD256,
27734 IX86_BUILTIN_MINPS256,
27735 IX86_BUILTIN_MULPD256,
27736 IX86_BUILTIN_MULPS256,
27737 IX86_BUILTIN_ORPD256,
27738 IX86_BUILTIN_ORPS256,
27739 IX86_BUILTIN_SHUFPD256,
27740 IX86_BUILTIN_SHUFPS256,
27741 IX86_BUILTIN_SUBPD256,
27742 IX86_BUILTIN_SUBPS256,
27743 IX86_BUILTIN_XORPD256,
27744 IX86_BUILTIN_XORPS256,
27745 IX86_BUILTIN_CMPSD,
27746 IX86_BUILTIN_CMPSS,
27747 IX86_BUILTIN_CMPPD,
27748 IX86_BUILTIN_CMPPS,
27749 IX86_BUILTIN_CMPPD256,
27750 IX86_BUILTIN_CMPPS256,
27751 IX86_BUILTIN_CVTDQ2PD256,
27752 IX86_BUILTIN_CVTDQ2PS256,
27753 IX86_BUILTIN_CVTPD2PS256,
27754 IX86_BUILTIN_CVTPS2DQ256,
27755 IX86_BUILTIN_CVTPS2PD256,
27756 IX86_BUILTIN_CVTTPD2DQ256,
27757 IX86_BUILTIN_CVTPD2DQ256,
27758 IX86_BUILTIN_CVTTPS2DQ256,
27759 IX86_BUILTIN_EXTRACTF128PD256,
27760 IX86_BUILTIN_EXTRACTF128PS256,
27761 IX86_BUILTIN_EXTRACTF128SI256,
27762 IX86_BUILTIN_VZEROALL,
27763 IX86_BUILTIN_VZEROUPPER,
27764 IX86_BUILTIN_VPERMILVARPD,
27765 IX86_BUILTIN_VPERMILVARPS,
27766 IX86_BUILTIN_VPERMILVARPD256,
27767 IX86_BUILTIN_VPERMILVARPS256,
27768 IX86_BUILTIN_VPERMILPD,
27769 IX86_BUILTIN_VPERMILPS,
27770 IX86_BUILTIN_VPERMILPD256,
27771 IX86_BUILTIN_VPERMILPS256,
27772 IX86_BUILTIN_VPERMIL2PD,
27773 IX86_BUILTIN_VPERMIL2PS,
27774 IX86_BUILTIN_VPERMIL2PD256,
27775 IX86_BUILTIN_VPERMIL2PS256,
27776 IX86_BUILTIN_VPERM2F128PD256,
27777 IX86_BUILTIN_VPERM2F128PS256,
27778 IX86_BUILTIN_VPERM2F128SI256,
27779 IX86_BUILTIN_VBROADCASTSS,
27780 IX86_BUILTIN_VBROADCASTSD256,
27781 IX86_BUILTIN_VBROADCASTSS256,
27782 IX86_BUILTIN_VBROADCASTPD256,
27783 IX86_BUILTIN_VBROADCASTPS256,
27784 IX86_BUILTIN_VINSERTF128PD256,
27785 IX86_BUILTIN_VINSERTF128PS256,
27786 IX86_BUILTIN_VINSERTF128SI256,
27787 IX86_BUILTIN_LOADUPD256,
27788 IX86_BUILTIN_LOADUPS256,
27789 IX86_BUILTIN_STOREUPD256,
27790 IX86_BUILTIN_STOREUPS256,
27791 IX86_BUILTIN_LDDQU256,
27792 IX86_BUILTIN_MOVNTDQ256,
27793 IX86_BUILTIN_MOVNTPD256,
27794 IX86_BUILTIN_MOVNTPS256,
27795 IX86_BUILTIN_LOADDQU256,
27796 IX86_BUILTIN_STOREDQU256,
27797 IX86_BUILTIN_MASKLOADPD,
27798 IX86_BUILTIN_MASKLOADPS,
27799 IX86_BUILTIN_MASKSTOREPD,
27800 IX86_BUILTIN_MASKSTOREPS,
27801 IX86_BUILTIN_MASKLOADPD256,
27802 IX86_BUILTIN_MASKLOADPS256,
27803 IX86_BUILTIN_MASKSTOREPD256,
27804 IX86_BUILTIN_MASKSTOREPS256,
27805 IX86_BUILTIN_MOVSHDUP256,
27806 IX86_BUILTIN_MOVSLDUP256,
27807 IX86_BUILTIN_MOVDDUP256,
27809 IX86_BUILTIN_SQRTPD256,
27810 IX86_BUILTIN_SQRTPS256,
27811 IX86_BUILTIN_SQRTPS_NR256,
27812 IX86_BUILTIN_RSQRTPS256,
27813 IX86_BUILTIN_RSQRTPS_NR256,
27815 IX86_BUILTIN_RCPPS256,
27817 IX86_BUILTIN_ROUNDPD256,
27818 IX86_BUILTIN_ROUNDPS256,
27820 IX86_BUILTIN_FLOORPD256,
27821 IX86_BUILTIN_CEILPD256,
27822 IX86_BUILTIN_TRUNCPD256,
27823 IX86_BUILTIN_RINTPD256,
27824 IX86_BUILTIN_ROUNDPD_AZ256,
27826 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27827 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27828 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27830 IX86_BUILTIN_FLOORPS256,
27831 IX86_BUILTIN_CEILPS256,
27832 IX86_BUILTIN_TRUNCPS256,
27833 IX86_BUILTIN_RINTPS256,
27834 IX86_BUILTIN_ROUNDPS_AZ256,
27836 IX86_BUILTIN_FLOORPS_SFIX256,
27837 IX86_BUILTIN_CEILPS_SFIX256,
27838 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27840 IX86_BUILTIN_UNPCKHPD256,
27841 IX86_BUILTIN_UNPCKLPD256,
27842 IX86_BUILTIN_UNPCKHPS256,
27843 IX86_BUILTIN_UNPCKLPS256,
27845 IX86_BUILTIN_SI256_SI,
27846 IX86_BUILTIN_PS256_PS,
27847 IX86_BUILTIN_PD256_PD,
27848 IX86_BUILTIN_SI_SI256,
27849 IX86_BUILTIN_PS_PS256,
27850 IX86_BUILTIN_PD_PD256,
27852 IX86_BUILTIN_VTESTZPD,
27853 IX86_BUILTIN_VTESTCPD,
27854 IX86_BUILTIN_VTESTNZCPD,
27855 IX86_BUILTIN_VTESTZPS,
27856 IX86_BUILTIN_VTESTCPS,
27857 IX86_BUILTIN_VTESTNZCPS,
27858 IX86_BUILTIN_VTESTZPD256,
27859 IX86_BUILTIN_VTESTCPD256,
27860 IX86_BUILTIN_VTESTNZCPD256,
27861 IX86_BUILTIN_VTESTZPS256,
27862 IX86_BUILTIN_VTESTCPS256,
27863 IX86_BUILTIN_VTESTNZCPS256,
27864 IX86_BUILTIN_PTESTZ256,
27865 IX86_BUILTIN_PTESTC256,
27866 IX86_BUILTIN_PTESTNZC256,
27868 IX86_BUILTIN_MOVMSKPD256,
27869 IX86_BUILTIN_MOVMSKPS256,
27871 /* AVX2 */
27872 IX86_BUILTIN_MPSADBW256,
27873 IX86_BUILTIN_PABSB256,
27874 IX86_BUILTIN_PABSW256,
27875 IX86_BUILTIN_PABSD256,
27876 IX86_BUILTIN_PACKSSDW256,
27877 IX86_BUILTIN_PACKSSWB256,
27878 IX86_BUILTIN_PACKUSDW256,
27879 IX86_BUILTIN_PACKUSWB256,
27880 IX86_BUILTIN_PADDB256,
27881 IX86_BUILTIN_PADDW256,
27882 IX86_BUILTIN_PADDD256,
27883 IX86_BUILTIN_PADDQ256,
27884 IX86_BUILTIN_PADDSB256,
27885 IX86_BUILTIN_PADDSW256,
27886 IX86_BUILTIN_PADDUSB256,
27887 IX86_BUILTIN_PADDUSW256,
27888 IX86_BUILTIN_PALIGNR256,
27889 IX86_BUILTIN_AND256I,
27890 IX86_BUILTIN_ANDNOT256I,
27891 IX86_BUILTIN_PAVGB256,
27892 IX86_BUILTIN_PAVGW256,
27893 IX86_BUILTIN_PBLENDVB256,
27894 IX86_BUILTIN_PBLENDVW256,
27895 IX86_BUILTIN_PCMPEQB256,
27896 IX86_BUILTIN_PCMPEQW256,
27897 IX86_BUILTIN_PCMPEQD256,
27898 IX86_BUILTIN_PCMPEQQ256,
27899 IX86_BUILTIN_PCMPGTB256,
27900 IX86_BUILTIN_PCMPGTW256,
27901 IX86_BUILTIN_PCMPGTD256,
27902 IX86_BUILTIN_PCMPGTQ256,
27903 IX86_BUILTIN_PHADDW256,
27904 IX86_BUILTIN_PHADDD256,
27905 IX86_BUILTIN_PHADDSW256,
27906 IX86_BUILTIN_PHSUBW256,
27907 IX86_BUILTIN_PHSUBD256,
27908 IX86_BUILTIN_PHSUBSW256,
27909 IX86_BUILTIN_PMADDUBSW256,
27910 IX86_BUILTIN_PMADDWD256,
27911 IX86_BUILTIN_PMAXSB256,
27912 IX86_BUILTIN_PMAXSW256,
27913 IX86_BUILTIN_PMAXSD256,
27914 IX86_BUILTIN_PMAXUB256,
27915 IX86_BUILTIN_PMAXUW256,
27916 IX86_BUILTIN_PMAXUD256,
27917 IX86_BUILTIN_PMINSB256,
27918 IX86_BUILTIN_PMINSW256,
27919 IX86_BUILTIN_PMINSD256,
27920 IX86_BUILTIN_PMINUB256,
27921 IX86_BUILTIN_PMINUW256,
27922 IX86_BUILTIN_PMINUD256,
27923 IX86_BUILTIN_PMOVMSKB256,
27924 IX86_BUILTIN_PMOVSXBW256,
27925 IX86_BUILTIN_PMOVSXBD256,
27926 IX86_BUILTIN_PMOVSXBQ256,
27927 IX86_BUILTIN_PMOVSXWD256,
27928 IX86_BUILTIN_PMOVSXWQ256,
27929 IX86_BUILTIN_PMOVSXDQ256,
27930 IX86_BUILTIN_PMOVZXBW256,
27931 IX86_BUILTIN_PMOVZXBD256,
27932 IX86_BUILTIN_PMOVZXBQ256,
27933 IX86_BUILTIN_PMOVZXWD256,
27934 IX86_BUILTIN_PMOVZXWQ256,
27935 IX86_BUILTIN_PMOVZXDQ256,
27936 IX86_BUILTIN_PMULDQ256,
27937 IX86_BUILTIN_PMULHRSW256,
27938 IX86_BUILTIN_PMULHUW256,
27939 IX86_BUILTIN_PMULHW256,
27940 IX86_BUILTIN_PMULLW256,
27941 IX86_BUILTIN_PMULLD256,
27942 IX86_BUILTIN_PMULUDQ256,
27943 IX86_BUILTIN_POR256,
27944 IX86_BUILTIN_PSADBW256,
27945 IX86_BUILTIN_PSHUFB256,
27946 IX86_BUILTIN_PSHUFD256,
27947 IX86_BUILTIN_PSHUFHW256,
27948 IX86_BUILTIN_PSHUFLW256,
27949 IX86_BUILTIN_PSIGNB256,
27950 IX86_BUILTIN_PSIGNW256,
27951 IX86_BUILTIN_PSIGND256,
27952 IX86_BUILTIN_PSLLDQI256,
27953 IX86_BUILTIN_PSLLWI256,
27954 IX86_BUILTIN_PSLLW256,
27955 IX86_BUILTIN_PSLLDI256,
27956 IX86_BUILTIN_PSLLD256,
27957 IX86_BUILTIN_PSLLQI256,
27958 IX86_BUILTIN_PSLLQ256,
27959 IX86_BUILTIN_PSRAWI256,
27960 IX86_BUILTIN_PSRAW256,
27961 IX86_BUILTIN_PSRADI256,
27962 IX86_BUILTIN_PSRAD256,
27963 IX86_BUILTIN_PSRLDQI256,
27964 IX86_BUILTIN_PSRLWI256,
27965 IX86_BUILTIN_PSRLW256,
27966 IX86_BUILTIN_PSRLDI256,
27967 IX86_BUILTIN_PSRLD256,
27968 IX86_BUILTIN_PSRLQI256,
27969 IX86_BUILTIN_PSRLQ256,
27970 IX86_BUILTIN_PSUBB256,
27971 IX86_BUILTIN_PSUBW256,
27972 IX86_BUILTIN_PSUBD256,
27973 IX86_BUILTIN_PSUBQ256,
27974 IX86_BUILTIN_PSUBSB256,
27975 IX86_BUILTIN_PSUBSW256,
27976 IX86_BUILTIN_PSUBUSB256,
27977 IX86_BUILTIN_PSUBUSW256,
27978 IX86_BUILTIN_PUNPCKHBW256,
27979 IX86_BUILTIN_PUNPCKHWD256,
27980 IX86_BUILTIN_PUNPCKHDQ256,
27981 IX86_BUILTIN_PUNPCKHQDQ256,
27982 IX86_BUILTIN_PUNPCKLBW256,
27983 IX86_BUILTIN_PUNPCKLWD256,
27984 IX86_BUILTIN_PUNPCKLDQ256,
27985 IX86_BUILTIN_PUNPCKLQDQ256,
27986 IX86_BUILTIN_PXOR256,
27987 IX86_BUILTIN_MOVNTDQA256,
27988 IX86_BUILTIN_VBROADCASTSS_PS,
27989 IX86_BUILTIN_VBROADCASTSS_PS256,
27990 IX86_BUILTIN_VBROADCASTSD_PD256,
27991 IX86_BUILTIN_VBROADCASTSI256,
27992 IX86_BUILTIN_PBLENDD256,
27993 IX86_BUILTIN_PBLENDD128,
27994 IX86_BUILTIN_PBROADCASTB256,
27995 IX86_BUILTIN_PBROADCASTW256,
27996 IX86_BUILTIN_PBROADCASTD256,
27997 IX86_BUILTIN_PBROADCASTQ256,
27998 IX86_BUILTIN_PBROADCASTB128,
27999 IX86_BUILTIN_PBROADCASTW128,
28000 IX86_BUILTIN_PBROADCASTD128,
28001 IX86_BUILTIN_PBROADCASTQ128,
28002 IX86_BUILTIN_VPERMVARSI256,
28003 IX86_BUILTIN_VPERMDF256,
28004 IX86_BUILTIN_VPERMVARSF256,
28005 IX86_BUILTIN_VPERMDI256,
28006 IX86_BUILTIN_VPERMTI256,
28007 IX86_BUILTIN_VEXTRACT128I256,
28008 IX86_BUILTIN_VINSERT128I256,
28009 IX86_BUILTIN_MASKLOADD,
28010 IX86_BUILTIN_MASKLOADQ,
28011 IX86_BUILTIN_MASKLOADD256,
28012 IX86_BUILTIN_MASKLOADQ256,
28013 IX86_BUILTIN_MASKSTORED,
28014 IX86_BUILTIN_MASKSTOREQ,
28015 IX86_BUILTIN_MASKSTORED256,
28016 IX86_BUILTIN_MASKSTOREQ256,
28017 IX86_BUILTIN_PSLLVV4DI,
28018 IX86_BUILTIN_PSLLVV2DI,
28019 IX86_BUILTIN_PSLLVV8SI,
28020 IX86_BUILTIN_PSLLVV4SI,
28021 IX86_BUILTIN_PSRAVV8SI,
28022 IX86_BUILTIN_PSRAVV4SI,
28023 IX86_BUILTIN_PSRLVV4DI,
28024 IX86_BUILTIN_PSRLVV2DI,
28025 IX86_BUILTIN_PSRLVV8SI,
28026 IX86_BUILTIN_PSRLVV4SI,
28028 IX86_BUILTIN_GATHERSIV2DF,
28029 IX86_BUILTIN_GATHERSIV4DF,
28030 IX86_BUILTIN_GATHERDIV2DF,
28031 IX86_BUILTIN_GATHERDIV4DF,
28032 IX86_BUILTIN_GATHERSIV4SF,
28033 IX86_BUILTIN_GATHERSIV8SF,
28034 IX86_BUILTIN_GATHERDIV4SF,
28035 IX86_BUILTIN_GATHERDIV8SF,
28036 IX86_BUILTIN_GATHERSIV2DI,
28037 IX86_BUILTIN_GATHERSIV4DI,
28038 IX86_BUILTIN_GATHERDIV2DI,
28039 IX86_BUILTIN_GATHERDIV4DI,
28040 IX86_BUILTIN_GATHERSIV4SI,
28041 IX86_BUILTIN_GATHERSIV8SI,
28042 IX86_BUILTIN_GATHERDIV4SI,
28043 IX86_BUILTIN_GATHERDIV8SI,
28045 /* AVX512F */
28046 IX86_BUILTIN_ADDPD512,
28047 IX86_BUILTIN_ADDPS512,
28048 IX86_BUILTIN_ADDSD_ROUND,
28049 IX86_BUILTIN_ADDSS_ROUND,
28050 IX86_BUILTIN_ALIGND512,
28051 IX86_BUILTIN_ALIGNQ512,
28052 IX86_BUILTIN_BLENDMD512,
28053 IX86_BUILTIN_BLENDMPD512,
28054 IX86_BUILTIN_BLENDMPS512,
28055 IX86_BUILTIN_BLENDMQ512,
28056 IX86_BUILTIN_BROADCASTF32X4_512,
28057 IX86_BUILTIN_BROADCASTF64X4_512,
28058 IX86_BUILTIN_BROADCASTI32X4_512,
28059 IX86_BUILTIN_BROADCASTI64X4_512,
28060 IX86_BUILTIN_BROADCASTSD512,
28061 IX86_BUILTIN_BROADCASTSS512,
28062 IX86_BUILTIN_CMPD512,
28063 IX86_BUILTIN_CMPPD512,
28064 IX86_BUILTIN_CMPPS512,
28065 IX86_BUILTIN_CMPQ512,
28066 IX86_BUILTIN_CMPSD_MASK,
28067 IX86_BUILTIN_CMPSS_MASK,
28068 IX86_BUILTIN_COMIDF,
28069 IX86_BUILTIN_COMISF,
28070 IX86_BUILTIN_COMPRESSPD512,
28071 IX86_BUILTIN_COMPRESSPDSTORE512,
28072 IX86_BUILTIN_COMPRESSPS512,
28073 IX86_BUILTIN_COMPRESSPSSTORE512,
28074 IX86_BUILTIN_CVTDQ2PD512,
28075 IX86_BUILTIN_CVTDQ2PS512,
28076 IX86_BUILTIN_CVTPD2DQ512,
28077 IX86_BUILTIN_CVTPD2PS512,
28078 IX86_BUILTIN_CVTPD2UDQ512,
28079 IX86_BUILTIN_CVTPH2PS512,
28080 IX86_BUILTIN_CVTPS2DQ512,
28081 IX86_BUILTIN_CVTPS2PD512,
28082 IX86_BUILTIN_CVTPS2PH512,
28083 IX86_BUILTIN_CVTPS2UDQ512,
28084 IX86_BUILTIN_CVTSD2SS_ROUND,
28085 IX86_BUILTIN_CVTSI2SD64,
28086 IX86_BUILTIN_CVTSI2SS32,
28087 IX86_BUILTIN_CVTSI2SS64,
28088 IX86_BUILTIN_CVTSS2SD_ROUND,
28089 IX86_BUILTIN_CVTTPD2DQ512,
28090 IX86_BUILTIN_CVTTPD2UDQ512,
28091 IX86_BUILTIN_CVTTPS2DQ512,
28092 IX86_BUILTIN_CVTTPS2UDQ512,
28093 IX86_BUILTIN_CVTUDQ2PD512,
28094 IX86_BUILTIN_CVTUDQ2PS512,
28095 IX86_BUILTIN_CVTUSI2SD32,
28096 IX86_BUILTIN_CVTUSI2SD64,
28097 IX86_BUILTIN_CVTUSI2SS32,
28098 IX86_BUILTIN_CVTUSI2SS64,
28099 IX86_BUILTIN_DIVPD512,
28100 IX86_BUILTIN_DIVPS512,
28101 IX86_BUILTIN_DIVSD_ROUND,
28102 IX86_BUILTIN_DIVSS_ROUND,
28103 IX86_BUILTIN_EXPANDPD512,
28104 IX86_BUILTIN_EXPANDPD512Z,
28105 IX86_BUILTIN_EXPANDPDLOAD512,
28106 IX86_BUILTIN_EXPANDPDLOAD512Z,
28107 IX86_BUILTIN_EXPANDPS512,
28108 IX86_BUILTIN_EXPANDPS512Z,
28109 IX86_BUILTIN_EXPANDPSLOAD512,
28110 IX86_BUILTIN_EXPANDPSLOAD512Z,
28111 IX86_BUILTIN_EXTRACTF32X4,
28112 IX86_BUILTIN_EXTRACTF64X4,
28113 IX86_BUILTIN_EXTRACTI32X4,
28114 IX86_BUILTIN_EXTRACTI64X4,
28115 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28116 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28117 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28118 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28119 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28120 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28121 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28122 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28123 IX86_BUILTIN_GETEXPPD512,
28124 IX86_BUILTIN_GETEXPPS512,
28125 IX86_BUILTIN_GETEXPSD128,
28126 IX86_BUILTIN_GETEXPSS128,
28127 IX86_BUILTIN_GETMANTPD512,
28128 IX86_BUILTIN_GETMANTPS512,
28129 IX86_BUILTIN_GETMANTSD128,
28130 IX86_BUILTIN_GETMANTSS128,
28131 IX86_BUILTIN_INSERTF32X4,
28132 IX86_BUILTIN_INSERTF64X4,
28133 IX86_BUILTIN_INSERTI32X4,
28134 IX86_BUILTIN_INSERTI64X4,
28135 IX86_BUILTIN_LOADAPD512,
28136 IX86_BUILTIN_LOADAPS512,
28137 IX86_BUILTIN_LOADDQUDI512,
28138 IX86_BUILTIN_LOADDQUSI512,
28139 IX86_BUILTIN_LOADUPD512,
28140 IX86_BUILTIN_LOADUPS512,
28141 IX86_BUILTIN_MAXPD512,
28142 IX86_BUILTIN_MAXPS512,
28143 IX86_BUILTIN_MAXSD_ROUND,
28144 IX86_BUILTIN_MAXSS_ROUND,
28145 IX86_BUILTIN_MINPD512,
28146 IX86_BUILTIN_MINPS512,
28147 IX86_BUILTIN_MINSD_ROUND,
28148 IX86_BUILTIN_MINSS_ROUND,
28149 IX86_BUILTIN_MOVAPD512,
28150 IX86_BUILTIN_MOVAPS512,
28151 IX86_BUILTIN_MOVDDUP512,
28152 IX86_BUILTIN_MOVDQA32LOAD512,
28153 IX86_BUILTIN_MOVDQA32STORE512,
28154 IX86_BUILTIN_MOVDQA32_512,
28155 IX86_BUILTIN_MOVDQA64LOAD512,
28156 IX86_BUILTIN_MOVDQA64STORE512,
28157 IX86_BUILTIN_MOVDQA64_512,
28158 IX86_BUILTIN_MOVNTDQ512,
28159 IX86_BUILTIN_MOVNTDQA512,
28160 IX86_BUILTIN_MOVNTPD512,
28161 IX86_BUILTIN_MOVNTPS512,
28162 IX86_BUILTIN_MOVSHDUP512,
28163 IX86_BUILTIN_MOVSLDUP512,
28164 IX86_BUILTIN_MULPD512,
28165 IX86_BUILTIN_MULPS512,
28166 IX86_BUILTIN_MULSD_ROUND,
28167 IX86_BUILTIN_MULSS_ROUND,
28168 IX86_BUILTIN_PABSD512,
28169 IX86_BUILTIN_PABSQ512,
28170 IX86_BUILTIN_PADDD512,
28171 IX86_BUILTIN_PADDQ512,
28172 IX86_BUILTIN_PANDD512,
28173 IX86_BUILTIN_PANDND512,
28174 IX86_BUILTIN_PANDNQ512,
28175 IX86_BUILTIN_PANDQ512,
28176 IX86_BUILTIN_PBROADCASTD512,
28177 IX86_BUILTIN_PBROADCASTD512_GPR,
28178 IX86_BUILTIN_PBROADCASTMB512,
28179 IX86_BUILTIN_PBROADCASTMW512,
28180 IX86_BUILTIN_PBROADCASTQ512,
28181 IX86_BUILTIN_PBROADCASTQ512_GPR,
28182 IX86_BUILTIN_PBROADCASTQ512_MEM,
28183 IX86_BUILTIN_PCMPEQD512_MASK,
28184 IX86_BUILTIN_PCMPEQQ512_MASK,
28185 IX86_BUILTIN_PCMPGTD512_MASK,
28186 IX86_BUILTIN_PCMPGTQ512_MASK,
28187 IX86_BUILTIN_PCOMPRESSD512,
28188 IX86_BUILTIN_PCOMPRESSDSTORE512,
28189 IX86_BUILTIN_PCOMPRESSQ512,
28190 IX86_BUILTIN_PCOMPRESSQSTORE512,
28191 IX86_BUILTIN_PEXPANDD512,
28192 IX86_BUILTIN_PEXPANDD512Z,
28193 IX86_BUILTIN_PEXPANDDLOAD512,
28194 IX86_BUILTIN_PEXPANDDLOAD512Z,
28195 IX86_BUILTIN_PEXPANDQ512,
28196 IX86_BUILTIN_PEXPANDQ512Z,
28197 IX86_BUILTIN_PEXPANDQLOAD512,
28198 IX86_BUILTIN_PEXPANDQLOAD512Z,
28199 IX86_BUILTIN_PMAXSD512,
28200 IX86_BUILTIN_PMAXSQ512,
28201 IX86_BUILTIN_PMAXUD512,
28202 IX86_BUILTIN_PMAXUQ512,
28203 IX86_BUILTIN_PMINSD512,
28204 IX86_BUILTIN_PMINSQ512,
28205 IX86_BUILTIN_PMINUD512,
28206 IX86_BUILTIN_PMINUQ512,
28207 IX86_BUILTIN_PMOVDB512,
28208 IX86_BUILTIN_PMOVDB512_MEM,
28209 IX86_BUILTIN_PMOVDW512,
28210 IX86_BUILTIN_PMOVDW512_MEM,
28211 IX86_BUILTIN_PMOVQB512,
28212 IX86_BUILTIN_PMOVQB512_MEM,
28213 IX86_BUILTIN_PMOVQD512,
28214 IX86_BUILTIN_PMOVQD512_MEM,
28215 IX86_BUILTIN_PMOVQW512,
28216 IX86_BUILTIN_PMOVQW512_MEM,
28217 IX86_BUILTIN_PMOVSDB512,
28218 IX86_BUILTIN_PMOVSDB512_MEM,
28219 IX86_BUILTIN_PMOVSDW512,
28220 IX86_BUILTIN_PMOVSDW512_MEM,
28221 IX86_BUILTIN_PMOVSQB512,
28222 IX86_BUILTIN_PMOVSQB512_MEM,
28223 IX86_BUILTIN_PMOVSQD512,
28224 IX86_BUILTIN_PMOVSQD512_MEM,
28225 IX86_BUILTIN_PMOVSQW512,
28226 IX86_BUILTIN_PMOVSQW512_MEM,
28227 IX86_BUILTIN_PMOVSXBD512,
28228 IX86_BUILTIN_PMOVSXBQ512,
28229 IX86_BUILTIN_PMOVSXDQ512,
28230 IX86_BUILTIN_PMOVSXWD512,
28231 IX86_BUILTIN_PMOVSXWQ512,
28232 IX86_BUILTIN_PMOVUSDB512,
28233 IX86_BUILTIN_PMOVUSDB512_MEM,
28234 IX86_BUILTIN_PMOVUSDW512,
28235 IX86_BUILTIN_PMOVUSDW512_MEM,
28236 IX86_BUILTIN_PMOVUSQB512,
28237 IX86_BUILTIN_PMOVUSQB512_MEM,
28238 IX86_BUILTIN_PMOVUSQD512,
28239 IX86_BUILTIN_PMOVUSQD512_MEM,
28240 IX86_BUILTIN_PMOVUSQW512,
28241 IX86_BUILTIN_PMOVUSQW512_MEM,
28242 IX86_BUILTIN_PMOVZXBD512,
28243 IX86_BUILTIN_PMOVZXBQ512,
28244 IX86_BUILTIN_PMOVZXDQ512,
28245 IX86_BUILTIN_PMOVZXWD512,
28246 IX86_BUILTIN_PMOVZXWQ512,
28247 IX86_BUILTIN_PMULDQ512,
28248 IX86_BUILTIN_PMULLD512,
28249 IX86_BUILTIN_PMULUDQ512,
28250 IX86_BUILTIN_PORD512,
28251 IX86_BUILTIN_PORQ512,
28252 IX86_BUILTIN_PROLD512,
28253 IX86_BUILTIN_PROLQ512,
28254 IX86_BUILTIN_PROLVD512,
28255 IX86_BUILTIN_PROLVQ512,
28256 IX86_BUILTIN_PRORD512,
28257 IX86_BUILTIN_PRORQ512,
28258 IX86_BUILTIN_PRORVD512,
28259 IX86_BUILTIN_PRORVQ512,
28260 IX86_BUILTIN_PSHUFD512,
28261 IX86_BUILTIN_PSLLD512,
28262 IX86_BUILTIN_PSLLDI512,
28263 IX86_BUILTIN_PSLLQ512,
28264 IX86_BUILTIN_PSLLQI512,
28265 IX86_BUILTIN_PSLLVV16SI,
28266 IX86_BUILTIN_PSLLVV8DI,
28267 IX86_BUILTIN_PSRAD512,
28268 IX86_BUILTIN_PSRADI512,
28269 IX86_BUILTIN_PSRAQ512,
28270 IX86_BUILTIN_PSRAQI512,
28271 IX86_BUILTIN_PSRAVV16SI,
28272 IX86_BUILTIN_PSRAVV8DI,
28273 IX86_BUILTIN_PSRLD512,
28274 IX86_BUILTIN_PSRLDI512,
28275 IX86_BUILTIN_PSRLQ512,
28276 IX86_BUILTIN_PSRLQI512,
28277 IX86_BUILTIN_PSRLVV16SI,
28278 IX86_BUILTIN_PSRLVV8DI,
28279 IX86_BUILTIN_PSUBD512,
28280 IX86_BUILTIN_PSUBQ512,
28281 IX86_BUILTIN_PTESTMD512,
28282 IX86_BUILTIN_PTESTMQ512,
28283 IX86_BUILTIN_PTESTNMD512,
28284 IX86_BUILTIN_PTESTNMQ512,
28285 IX86_BUILTIN_PUNPCKHDQ512,
28286 IX86_BUILTIN_PUNPCKHQDQ512,
28287 IX86_BUILTIN_PUNPCKLDQ512,
28288 IX86_BUILTIN_PUNPCKLQDQ512,
28289 IX86_BUILTIN_PXORD512,
28290 IX86_BUILTIN_PXORQ512,
28291 IX86_BUILTIN_RCP14PD512,
28292 IX86_BUILTIN_RCP14PS512,
28293 IX86_BUILTIN_RCP14SD,
28294 IX86_BUILTIN_RCP14SS,
28295 IX86_BUILTIN_RNDSCALEPD,
28296 IX86_BUILTIN_RNDSCALEPS,
28297 IX86_BUILTIN_RNDSCALESD,
28298 IX86_BUILTIN_RNDSCALESS,
28299 IX86_BUILTIN_RSQRT14PD512,
28300 IX86_BUILTIN_RSQRT14PS512,
28301 IX86_BUILTIN_RSQRT14SD,
28302 IX86_BUILTIN_RSQRT14SS,
28303 IX86_BUILTIN_SCALEFPD512,
28304 IX86_BUILTIN_SCALEFPS512,
28305 IX86_BUILTIN_SCALEFSD,
28306 IX86_BUILTIN_SCALEFSS,
28307 IX86_BUILTIN_SHUFPD512,
28308 IX86_BUILTIN_SHUFPS512,
28309 IX86_BUILTIN_SHUF_F32x4,
28310 IX86_BUILTIN_SHUF_F64x2,
28311 IX86_BUILTIN_SHUF_I32x4,
28312 IX86_BUILTIN_SHUF_I64x2,
28313 IX86_BUILTIN_SQRTPD512,
28314 IX86_BUILTIN_SQRTPD512_MASK,
28315 IX86_BUILTIN_SQRTPS512_MASK,
28316 IX86_BUILTIN_SQRTPS_NR512,
28317 IX86_BUILTIN_SQRTSD_ROUND,
28318 IX86_BUILTIN_SQRTSS_ROUND,
28319 IX86_BUILTIN_STOREAPD512,
28320 IX86_BUILTIN_STOREAPS512,
28321 IX86_BUILTIN_STOREDQUDI512,
28322 IX86_BUILTIN_STOREDQUSI512,
28323 IX86_BUILTIN_STOREUPD512,
28324 IX86_BUILTIN_STOREUPS512,
28325 IX86_BUILTIN_SUBPD512,
28326 IX86_BUILTIN_SUBPS512,
28327 IX86_BUILTIN_SUBSD_ROUND,
28328 IX86_BUILTIN_SUBSS_ROUND,
28329 IX86_BUILTIN_UCMPD512,
28330 IX86_BUILTIN_UCMPQ512,
28331 IX86_BUILTIN_UNPCKHPD512,
28332 IX86_BUILTIN_UNPCKHPS512,
28333 IX86_BUILTIN_UNPCKLPD512,
28334 IX86_BUILTIN_UNPCKLPS512,
28335 IX86_BUILTIN_VCVTSD2SI32,
28336 IX86_BUILTIN_VCVTSD2SI64,
28337 IX86_BUILTIN_VCVTSD2USI32,
28338 IX86_BUILTIN_VCVTSD2USI64,
28339 IX86_BUILTIN_VCVTSS2SI32,
28340 IX86_BUILTIN_VCVTSS2SI64,
28341 IX86_BUILTIN_VCVTSS2USI32,
28342 IX86_BUILTIN_VCVTSS2USI64,
28343 IX86_BUILTIN_VCVTTSD2SI32,
28344 IX86_BUILTIN_VCVTTSD2SI64,
28345 IX86_BUILTIN_VCVTTSD2USI32,
28346 IX86_BUILTIN_VCVTTSD2USI64,
28347 IX86_BUILTIN_VCVTTSS2SI32,
28348 IX86_BUILTIN_VCVTTSS2SI64,
28349 IX86_BUILTIN_VCVTTSS2USI32,
28350 IX86_BUILTIN_VCVTTSS2USI64,
28351 IX86_BUILTIN_VFMADDPD512_MASK,
28352 IX86_BUILTIN_VFMADDPD512_MASK3,
28353 IX86_BUILTIN_VFMADDPD512_MASKZ,
28354 IX86_BUILTIN_VFMADDPS512_MASK,
28355 IX86_BUILTIN_VFMADDPS512_MASK3,
28356 IX86_BUILTIN_VFMADDPS512_MASKZ,
28357 IX86_BUILTIN_VFMADDSD3_ROUND,
28358 IX86_BUILTIN_VFMADDSS3_ROUND,
28359 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28360 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28361 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28362 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28363 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28364 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28365 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28366 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28367 IX86_BUILTIN_VFMSUBPD512_MASK3,
28368 IX86_BUILTIN_VFMSUBPS512_MASK3,
28369 IX86_BUILTIN_VFMSUBSD3_MASK3,
28370 IX86_BUILTIN_VFMSUBSS3_MASK3,
28371 IX86_BUILTIN_VFNMADDPD512_MASK,
28372 IX86_BUILTIN_VFNMADDPS512_MASK,
28373 IX86_BUILTIN_VFNMSUBPD512_MASK,
28374 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28375 IX86_BUILTIN_VFNMSUBPS512_MASK,
28376 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28377 IX86_BUILTIN_VPCLZCNTD512,
28378 IX86_BUILTIN_VPCLZCNTQ512,
28379 IX86_BUILTIN_VPCONFLICTD512,
28380 IX86_BUILTIN_VPCONFLICTQ512,
28381 IX86_BUILTIN_VPERMDF512,
28382 IX86_BUILTIN_VPERMDI512,
28383 IX86_BUILTIN_VPERMI2VARD512,
28384 IX86_BUILTIN_VPERMI2VARPD512,
28385 IX86_BUILTIN_VPERMI2VARPS512,
28386 IX86_BUILTIN_VPERMI2VARQ512,
28387 IX86_BUILTIN_VPERMILPD512,
28388 IX86_BUILTIN_VPERMILPS512,
28389 IX86_BUILTIN_VPERMILVARPD512,
28390 IX86_BUILTIN_VPERMILVARPS512,
28391 IX86_BUILTIN_VPERMT2VARD512,
28392 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28393 IX86_BUILTIN_VPERMT2VARPD512,
28394 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28395 IX86_BUILTIN_VPERMT2VARPS512,
28396 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28397 IX86_BUILTIN_VPERMT2VARQ512,
28398 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28399 IX86_BUILTIN_VPERMVARDF512,
28400 IX86_BUILTIN_VPERMVARDI512,
28401 IX86_BUILTIN_VPERMVARSF512,
28402 IX86_BUILTIN_VPERMVARSI512,
28403 IX86_BUILTIN_VTERNLOGD512_MASK,
28404 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28405 IX86_BUILTIN_VTERNLOGQ512_MASK,
28406 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28408 /* Mask arithmetic operations */
28409 IX86_BUILTIN_KAND16,
28410 IX86_BUILTIN_KANDN16,
28411 IX86_BUILTIN_KNOT16,
28412 IX86_BUILTIN_KOR16,
28413 IX86_BUILTIN_KORTESTC16,
28414 IX86_BUILTIN_KORTESTZ16,
28415 IX86_BUILTIN_KUNPCKBW,
28416 IX86_BUILTIN_KXNOR16,
28417 IX86_BUILTIN_KXOR16,
28418 IX86_BUILTIN_KMOV16,
28420 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28421 where all operands are 32-byte or 64-byte wide respectively. */
28422 IX86_BUILTIN_GATHERALTSIV4DF,
28423 IX86_BUILTIN_GATHERALTDIV8SF,
28424 IX86_BUILTIN_GATHERALTSIV4DI,
28425 IX86_BUILTIN_GATHERALTDIV8SI,
28426 IX86_BUILTIN_GATHER3ALTDIV16SF,
28427 IX86_BUILTIN_GATHER3ALTDIV16SI,
28428 IX86_BUILTIN_GATHER3ALTSIV8DF,
28429 IX86_BUILTIN_GATHER3ALTSIV8DI,
28430 IX86_BUILTIN_GATHER3DIV16SF,
28431 IX86_BUILTIN_GATHER3DIV16SI,
28432 IX86_BUILTIN_GATHER3DIV8DF,
28433 IX86_BUILTIN_GATHER3DIV8DI,
28434 IX86_BUILTIN_GATHER3SIV16SF,
28435 IX86_BUILTIN_GATHER3SIV16SI,
28436 IX86_BUILTIN_GATHER3SIV8DF,
28437 IX86_BUILTIN_GATHER3SIV8DI,
28438 IX86_BUILTIN_SCATTERDIV16SF,
28439 IX86_BUILTIN_SCATTERDIV16SI,
28440 IX86_BUILTIN_SCATTERDIV8DF,
28441 IX86_BUILTIN_SCATTERDIV8DI,
28442 IX86_BUILTIN_SCATTERSIV16SF,
28443 IX86_BUILTIN_SCATTERSIV16SI,
28444 IX86_BUILTIN_SCATTERSIV8DF,
28445 IX86_BUILTIN_SCATTERSIV8DI,
28447 /* AVX512PF */
28448 IX86_BUILTIN_GATHERPFQPD,
28449 IX86_BUILTIN_GATHERPFDPS,
28450 IX86_BUILTIN_GATHERPFDPD,
28451 IX86_BUILTIN_GATHERPFQPS,
28452 IX86_BUILTIN_SCATTERPFDPD,
28453 IX86_BUILTIN_SCATTERPFDPS,
28454 IX86_BUILTIN_SCATTERPFQPD,
28455 IX86_BUILTIN_SCATTERPFQPS,
28457 /* AVX-512ER */
28458 IX86_BUILTIN_EXP2PD_MASK,
28459 IX86_BUILTIN_EXP2PS_MASK,
28460 IX86_BUILTIN_EXP2PS,
28461 IX86_BUILTIN_RCP28PD,
28462 IX86_BUILTIN_RCP28PS,
28463 IX86_BUILTIN_RCP28SD,
28464 IX86_BUILTIN_RCP28SS,
28465 IX86_BUILTIN_RSQRT28PD,
28466 IX86_BUILTIN_RSQRT28PS,
28467 IX86_BUILTIN_RSQRT28SD,
28468 IX86_BUILTIN_RSQRT28SS,
28470 /* SHA builtins. */
28471 IX86_BUILTIN_SHA1MSG1,
28472 IX86_BUILTIN_SHA1MSG2,
28473 IX86_BUILTIN_SHA1NEXTE,
28474 IX86_BUILTIN_SHA1RNDS4,
28475 IX86_BUILTIN_SHA256MSG1,
28476 IX86_BUILTIN_SHA256MSG2,
28477 IX86_BUILTIN_SHA256RNDS2,
28479 /* TFmode support builtins. */
28480 IX86_BUILTIN_INFQ,
28481 IX86_BUILTIN_HUGE_VALQ,
28482 IX86_BUILTIN_FABSQ,
28483 IX86_BUILTIN_COPYSIGNQ,
28485 /* Vectorizer support builtins. */
28486 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28487 IX86_BUILTIN_CPYSGNPS,
28488 IX86_BUILTIN_CPYSGNPD,
28489 IX86_BUILTIN_CPYSGNPS256,
28490 IX86_BUILTIN_CPYSGNPS512,
28491 IX86_BUILTIN_CPYSGNPD256,
28492 IX86_BUILTIN_CPYSGNPD512,
28493 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28494 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28497 /* FMA4 instructions. */
28498 IX86_BUILTIN_VFMADDSS,
28499 IX86_BUILTIN_VFMADDSD,
28500 IX86_BUILTIN_VFMADDPS,
28501 IX86_BUILTIN_VFMADDPD,
28502 IX86_BUILTIN_VFMADDPS256,
28503 IX86_BUILTIN_VFMADDPD256,
28504 IX86_BUILTIN_VFMADDSUBPS,
28505 IX86_BUILTIN_VFMADDSUBPD,
28506 IX86_BUILTIN_VFMADDSUBPS256,
28507 IX86_BUILTIN_VFMADDSUBPD256,
28509 /* FMA3 instructions. */
28510 IX86_BUILTIN_VFMADDSS3,
28511 IX86_BUILTIN_VFMADDSD3,
28513 /* XOP instructions. */
28514 IX86_BUILTIN_VPCMOV,
28515 IX86_BUILTIN_VPCMOV_V2DI,
28516 IX86_BUILTIN_VPCMOV_V4SI,
28517 IX86_BUILTIN_VPCMOV_V8HI,
28518 IX86_BUILTIN_VPCMOV_V16QI,
28519 IX86_BUILTIN_VPCMOV_V4SF,
28520 IX86_BUILTIN_VPCMOV_V2DF,
28521 IX86_BUILTIN_VPCMOV256,
28522 IX86_BUILTIN_VPCMOV_V4DI256,
28523 IX86_BUILTIN_VPCMOV_V8SI256,
28524 IX86_BUILTIN_VPCMOV_V16HI256,
28525 IX86_BUILTIN_VPCMOV_V32QI256,
28526 IX86_BUILTIN_VPCMOV_V8SF256,
28527 IX86_BUILTIN_VPCMOV_V4DF256,
28529 IX86_BUILTIN_VPPERM,
28531 IX86_BUILTIN_VPMACSSWW,
28532 IX86_BUILTIN_VPMACSWW,
28533 IX86_BUILTIN_VPMACSSWD,
28534 IX86_BUILTIN_VPMACSWD,
28535 IX86_BUILTIN_VPMACSSDD,
28536 IX86_BUILTIN_VPMACSDD,
28537 IX86_BUILTIN_VPMACSSDQL,
28538 IX86_BUILTIN_VPMACSSDQH,
28539 IX86_BUILTIN_VPMACSDQL,
28540 IX86_BUILTIN_VPMACSDQH,
28541 IX86_BUILTIN_VPMADCSSWD,
28542 IX86_BUILTIN_VPMADCSWD,
28544 IX86_BUILTIN_VPHADDBW,
28545 IX86_BUILTIN_VPHADDBD,
28546 IX86_BUILTIN_VPHADDBQ,
28547 IX86_BUILTIN_VPHADDWD,
28548 IX86_BUILTIN_VPHADDWQ,
28549 IX86_BUILTIN_VPHADDDQ,
28550 IX86_BUILTIN_VPHADDUBW,
28551 IX86_BUILTIN_VPHADDUBD,
28552 IX86_BUILTIN_VPHADDUBQ,
28553 IX86_BUILTIN_VPHADDUWD,
28554 IX86_BUILTIN_VPHADDUWQ,
28555 IX86_BUILTIN_VPHADDUDQ,
28556 IX86_BUILTIN_VPHSUBBW,
28557 IX86_BUILTIN_VPHSUBWD,
28558 IX86_BUILTIN_VPHSUBDQ,
28560 IX86_BUILTIN_VPROTB,
28561 IX86_BUILTIN_VPROTW,
28562 IX86_BUILTIN_VPROTD,
28563 IX86_BUILTIN_VPROTQ,
28564 IX86_BUILTIN_VPROTB_IMM,
28565 IX86_BUILTIN_VPROTW_IMM,
28566 IX86_BUILTIN_VPROTD_IMM,
28567 IX86_BUILTIN_VPROTQ_IMM,
28569 IX86_BUILTIN_VPSHLB,
28570 IX86_BUILTIN_VPSHLW,
28571 IX86_BUILTIN_VPSHLD,
28572 IX86_BUILTIN_VPSHLQ,
28573 IX86_BUILTIN_VPSHAB,
28574 IX86_BUILTIN_VPSHAW,
28575 IX86_BUILTIN_VPSHAD,
28576 IX86_BUILTIN_VPSHAQ,
28578 IX86_BUILTIN_VFRCZSS,
28579 IX86_BUILTIN_VFRCZSD,
28580 IX86_BUILTIN_VFRCZPS,
28581 IX86_BUILTIN_VFRCZPD,
28582 IX86_BUILTIN_VFRCZPS256,
28583 IX86_BUILTIN_VFRCZPD256,
28585 IX86_BUILTIN_VPCOMEQUB,
28586 IX86_BUILTIN_VPCOMNEUB,
28587 IX86_BUILTIN_VPCOMLTUB,
28588 IX86_BUILTIN_VPCOMLEUB,
28589 IX86_BUILTIN_VPCOMGTUB,
28590 IX86_BUILTIN_VPCOMGEUB,
28591 IX86_BUILTIN_VPCOMFALSEUB,
28592 IX86_BUILTIN_VPCOMTRUEUB,
28594 IX86_BUILTIN_VPCOMEQUW,
28595 IX86_BUILTIN_VPCOMNEUW,
28596 IX86_BUILTIN_VPCOMLTUW,
28597 IX86_BUILTIN_VPCOMLEUW,
28598 IX86_BUILTIN_VPCOMGTUW,
28599 IX86_BUILTIN_VPCOMGEUW,
28600 IX86_BUILTIN_VPCOMFALSEUW,
28601 IX86_BUILTIN_VPCOMTRUEUW,
28603 IX86_BUILTIN_VPCOMEQUD,
28604 IX86_BUILTIN_VPCOMNEUD,
28605 IX86_BUILTIN_VPCOMLTUD,
28606 IX86_BUILTIN_VPCOMLEUD,
28607 IX86_BUILTIN_VPCOMGTUD,
28608 IX86_BUILTIN_VPCOMGEUD,
28609 IX86_BUILTIN_VPCOMFALSEUD,
28610 IX86_BUILTIN_VPCOMTRUEUD,
28612 IX86_BUILTIN_VPCOMEQUQ,
28613 IX86_BUILTIN_VPCOMNEUQ,
28614 IX86_BUILTIN_VPCOMLTUQ,
28615 IX86_BUILTIN_VPCOMLEUQ,
28616 IX86_BUILTIN_VPCOMGTUQ,
28617 IX86_BUILTIN_VPCOMGEUQ,
28618 IX86_BUILTIN_VPCOMFALSEUQ,
28619 IX86_BUILTIN_VPCOMTRUEUQ,
28621 IX86_BUILTIN_VPCOMEQB,
28622 IX86_BUILTIN_VPCOMNEB,
28623 IX86_BUILTIN_VPCOMLTB,
28624 IX86_BUILTIN_VPCOMLEB,
28625 IX86_BUILTIN_VPCOMGTB,
28626 IX86_BUILTIN_VPCOMGEB,
28627 IX86_BUILTIN_VPCOMFALSEB,
28628 IX86_BUILTIN_VPCOMTRUEB,
28630 IX86_BUILTIN_VPCOMEQW,
28631 IX86_BUILTIN_VPCOMNEW,
28632 IX86_BUILTIN_VPCOMLTW,
28633 IX86_BUILTIN_VPCOMLEW,
28634 IX86_BUILTIN_VPCOMGTW,
28635 IX86_BUILTIN_VPCOMGEW,
28636 IX86_BUILTIN_VPCOMFALSEW,
28637 IX86_BUILTIN_VPCOMTRUEW,
28639 IX86_BUILTIN_VPCOMEQD,
28640 IX86_BUILTIN_VPCOMNED,
28641 IX86_BUILTIN_VPCOMLTD,
28642 IX86_BUILTIN_VPCOMLED,
28643 IX86_BUILTIN_VPCOMGTD,
28644 IX86_BUILTIN_VPCOMGED,
28645 IX86_BUILTIN_VPCOMFALSED,
28646 IX86_BUILTIN_VPCOMTRUED,
28648 IX86_BUILTIN_VPCOMEQQ,
28649 IX86_BUILTIN_VPCOMNEQ,
28650 IX86_BUILTIN_VPCOMLTQ,
28651 IX86_BUILTIN_VPCOMLEQ,
28652 IX86_BUILTIN_VPCOMGTQ,
28653 IX86_BUILTIN_VPCOMGEQ,
28654 IX86_BUILTIN_VPCOMFALSEQ,
28655 IX86_BUILTIN_VPCOMTRUEQ,
28657 /* LWP instructions. */
28658 IX86_BUILTIN_LLWPCB,
28659 IX86_BUILTIN_SLWPCB,
28660 IX86_BUILTIN_LWPVAL32,
28661 IX86_BUILTIN_LWPVAL64,
28662 IX86_BUILTIN_LWPINS32,
28663 IX86_BUILTIN_LWPINS64,
28665 IX86_BUILTIN_CLZS,
28667 /* RTM */
28668 IX86_BUILTIN_XBEGIN,
28669 IX86_BUILTIN_XEND,
28670 IX86_BUILTIN_XABORT,
28671 IX86_BUILTIN_XTEST,
28673 /* BMI instructions. */
28674 IX86_BUILTIN_BEXTR32,
28675 IX86_BUILTIN_BEXTR64,
28676 IX86_BUILTIN_CTZS,
28678 /* TBM instructions. */
28679 IX86_BUILTIN_BEXTRI32,
28680 IX86_BUILTIN_BEXTRI64,
28682 /* BMI2 instructions. */
28683 IX86_BUILTIN_BZHI32,
28684 IX86_BUILTIN_BZHI64,
28685 IX86_BUILTIN_PDEP32,
28686 IX86_BUILTIN_PDEP64,
28687 IX86_BUILTIN_PEXT32,
28688 IX86_BUILTIN_PEXT64,
28690 /* ADX instructions. */
28691 IX86_BUILTIN_ADDCARRYX32,
28692 IX86_BUILTIN_ADDCARRYX64,
28694 /* FSGSBASE instructions. */
28695 IX86_BUILTIN_RDFSBASE32,
28696 IX86_BUILTIN_RDFSBASE64,
28697 IX86_BUILTIN_RDGSBASE32,
28698 IX86_BUILTIN_RDGSBASE64,
28699 IX86_BUILTIN_WRFSBASE32,
28700 IX86_BUILTIN_WRFSBASE64,
28701 IX86_BUILTIN_WRGSBASE32,
28702 IX86_BUILTIN_WRGSBASE64,
28704 /* RDRND instructions. */
28705 IX86_BUILTIN_RDRAND16_STEP,
28706 IX86_BUILTIN_RDRAND32_STEP,
28707 IX86_BUILTIN_RDRAND64_STEP,
28709 /* RDSEED instructions. */
28710 IX86_BUILTIN_RDSEED16_STEP,
28711 IX86_BUILTIN_RDSEED32_STEP,
28712 IX86_BUILTIN_RDSEED64_STEP,
28714 /* F16C instructions. */
28715 IX86_BUILTIN_CVTPH2PS,
28716 IX86_BUILTIN_CVTPH2PS256,
28717 IX86_BUILTIN_CVTPS2PH,
28718 IX86_BUILTIN_CVTPS2PH256,
28720 /* CFString built-in for darwin */
28721 IX86_BUILTIN_CFSTRING,
28723 /* Builtins to get CPU type and supported features. */
28724 IX86_BUILTIN_CPU_INIT,
28725 IX86_BUILTIN_CPU_IS,
28726 IX86_BUILTIN_CPU_SUPPORTS,
28728 /* Read/write FLAGS register built-ins. */
28729 IX86_BUILTIN_READ_FLAGS,
28730 IX86_BUILTIN_WRITE_FLAGS,
28732 IX86_BUILTIN_MAX
28733 };
28735 /* Table for the ix86 builtin decls. */
28738 /* Table of all of the builtin functions that are possible with different ISA's
28739 but are waiting to be built until a function is declared to use that
28740 ISA. */
28747 };
28752 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28753 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28754 function decl in the ix86_builtins array. Returns the function decl or
28755 NULL_TREE, if the builtin was not added.
28757 If the front end has a special hook for builtin functions, delay adding
28758 builtin functions that aren't in the current ISA until the ISA is changed
28759 with function specific optimization. Doing so, can save about 300K for the
28760 default compiler. When the builtin is expanded, check at that time whether
28761 it is valid.
28763 If the front end doesn't have a special hook, record all builtins, even if
28764 it isn't an instruction set in the current ISA in case the user uses
28765 function specific options for a different ISA, so that we don't get scope
28766 errors if a builtin is added in the middle of a function scope. */
28772 {
28776 {
28785 {
28791 }
28792 else
28793 {
28799 }
28800 }
28803 }
28805 /* Like def_builtin, but also marks the function decl "const". */
28810 {
28814 else
28818 }
28820 /* Add any new builtin functions for a given ISA that may not have been
28821 declared. This saves a bit of space compared to adding all of the
28822 declarations to the tree, even if we didn't use them. */
28824 static void
28826 {
28830 {
28833 {
28836 /* Don't define the builtin again. */
28842 NULL_TREE);
28847 }
28848 }
28849 }
28851 /* Bits for builtin_description.flag. */
28853 /* Set when we don't support the comparison natively, and should
28854 swap_comparison in order to support it. */
28855 #define BUILTIN_DESC_SWAP_OPERANDS 1
28857 struct builtin_description
28858 {
28865 };
28868 {
28869 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28870 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28871 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28872 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28873 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28874 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28875 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28876 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28878 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28879 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28880 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28881 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
28887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
28888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
28889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
28890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
28891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
28892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
28893 };
28896 {
28897 /* SSE4.2 */
28898 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
28899 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
28900 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
28901 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
28902 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
28903 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
28904 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
28905 };
28908 {
28909 /* SSE4.2 */
28910 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
28911 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
28912 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
28913 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
28914 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
28915 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
28916 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
28917 };
28919 /* Special builtins with variable number of arguments. */
28921 {
28922 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
28923 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
28924 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
28926 /* 80387 (for use internally for atomic compound assignment). */
28927 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
28928 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
28929 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
28930 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
28932 /* MMX */
28933 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28935 /* 3DNow! */
28936 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28938 /* FXSR, XSAVE and XSAVEOPT */
28939 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
28940 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
28941 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28942 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28943 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28945 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28946 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28947 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28948 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28949 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28951 /* SSE */
28952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
28956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28957 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28958 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28959 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28961 /* SSE or 3DNow!A */
28962 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28963 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
28965 /* SSE2 */
28966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
28970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
28972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
28973 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
28974 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
28975 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
28977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
28978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
28980 /* SSE3 */
28981 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
28983 /* SSE4.1 */
28984 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
28986 /* SSE4A */
28987 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28988 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28990 /* AVX */
28991 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
28992 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
28994 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
28995 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
28996 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
28997 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
28998 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29000 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29002 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29003 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29004 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29009 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29013 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29015 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29017 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29018 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29019 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29021 /* AVX2 */
29022 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29023 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29024 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29025 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29026 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29027 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29028 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29029 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29030 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29032 /* AVX512F */
29033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29081 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29082 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29083 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29084 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29085 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29086 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29088 /* FSGSBASE */
29089 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29090 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29091 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29092 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29093 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29094 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29095 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29096 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29098 /* RTM */
29099 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29100 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29101 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29102 };
29104 /* Builtins with variable number of arguments. */
29106 {
29107 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29108 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29109 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29110 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29111 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29112 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29113 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29115 /* MMX */
29116 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29117 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29118 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29136 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29158 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29161 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29162 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29163 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29168 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29170 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29174 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29175 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29176 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29177 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29179 /* 3DNow! */
29180 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29181 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29182 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29183 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29185 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29186 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29187 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29188 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29189 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29190 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29191 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29192 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29193 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29194 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29195 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29196 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29197 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29198 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29199 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29201 /* 3DNow!A */
29202 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29203 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29204 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29205 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29206 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29207 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29209 /* SSE */
29210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29212 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29214 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29216 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29218 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29220 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29221 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29225 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29226 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29227 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29228 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29231 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29255 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29256 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29260 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29261 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29262 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29263 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29265 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29267 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29268 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29269 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29270 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29271 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29275 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29277 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29279 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29280 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29283 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29284 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29286 /* SSE MMX or 3Dnow!A */
29287 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29288 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29289 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29291 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29292 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29293 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29294 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29296 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29297 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29299 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29301 /* SSE2 */
29302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29308 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29320 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29321 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29325 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29327 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29328 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29329 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29330 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29358 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29362 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29364 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29365 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29367 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29370 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29371 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29373 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29375 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29376 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29377 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29378 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29379 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29380 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29381 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29382 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29393 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29394 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29396 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29398 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29399 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29411 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29412 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29413 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29416 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29417 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29418 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29419 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29420 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29422 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29423 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29429 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29433 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29438 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29443 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29444 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29445 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29448 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29451 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29452 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29454 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29455 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29458 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29459 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29460 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29461 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29469 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29471 /* SSE2 MMX */
29472 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29473 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29475 /* SSE3 */
29476 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29477 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29479 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29480 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29481 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29482 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29483 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29484 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29486 /* SSSE3 */
29487 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29488 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29490 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29504 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29505 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29508 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29509 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29510 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29513 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29514 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29515 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29516 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29517 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29519 /* SSSE3. */
29520 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29521 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29523 /* SSE4.1 */
29524 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29525 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29543 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29550 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29553 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29556 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29557 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29558 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29559 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29560 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29562 /* SSE4.1 */
29563 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29564 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29565 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29566 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29569 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29570 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29571 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29573 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29574 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29576 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29577 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29579 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29580 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29581 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29582 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29584 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29585 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29587 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29588 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29590 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29591 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29592 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29594 /* SSE4.2 */
29595 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29596 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29597 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29598 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29599 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29601 /* SSE4A */
29602 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29603 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29604 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29605 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29607 /* AES */
29608 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29609 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29611 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29612 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29613 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29614 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29616 /* PCLMUL */
29617 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29619 /* AVX */
29620 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29621 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29624 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29625 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29628 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29634 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29635 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29636 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29637 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29638 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29639 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29640 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29641 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29642 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29643 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29644 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29645 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29668 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29669 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29670 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29673 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29675 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29691 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29693 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29695 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29707 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29708 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29721 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29722 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29732 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29733 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29734 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29755 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29756 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29758 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29760 /* AVX2 */
29761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29762 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29763 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29764 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29769 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29770 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29771 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29772 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29778 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29800 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29801 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29802 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29803 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29804 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29805 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29806 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29807 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29808 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29809 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29810 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29811 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29822 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29824 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29825 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29826 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29827 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29828 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29829 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29830 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29831 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29832 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29833 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29834 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29835 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29836 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29837 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29839 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29842 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29843 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29844 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29845 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29846 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29847 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29848 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29849 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29850 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29851 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29852 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29853 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29854 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29855 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29856 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29857 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29858 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29859 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29860 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29861 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29862 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29872 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29875 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29908 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29910 /* BMI */
29911 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29912 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29913 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29915 /* TBM */
29916 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29917 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29919 /* F16C */
29920 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
29921 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
29922 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
29923 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
29925 /* BMI2 */
29926 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29927 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29928 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29929 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29930 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29931 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29933 /* AVX512F */
29934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
29935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
29936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
29942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
29943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
29944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
29945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
29947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
29948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
29952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
29954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
29959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
29960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
29961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
29962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
29963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
29964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
29965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
29966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
29982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
29983 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
29984 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
29985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
29986 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
29987 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
29988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
29989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
29990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
29991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
29992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30095 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30096 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30097 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30098 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30130 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30135 /* Mask arithmetic operations */
30136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30147 /* SHA */
30148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30152 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30155 };
30157 /* Builtins with rounding support. */
30159 {
30160 /* AVX512F */
30161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30180 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30182 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30189 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30191 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30241 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30243 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30245 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30247 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30249 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30251 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30253 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30255 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30281 /* AVX512ER */
30282 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30283 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30284 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30285 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30286 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30287 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30288 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30289 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30290 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30291 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30292 };
30294 /* FMA4 and XOP. */
30295 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30296 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30297 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30298 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30299 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30300 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30301 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30302 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30303 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30304 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30305 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30306 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30307 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30308 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30309 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30310 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30311 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30312 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30313 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30314 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30315 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30316 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30317 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30318 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30319 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30320 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30321 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30322 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30323 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30324 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30325 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30326 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30327 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30328 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30329 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30330 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30331 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30332 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30333 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30334 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30335 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30336 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30337 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30338 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30339 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30340 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30341 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30342 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30343 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30344 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30345 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30346 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30349 {
30390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30548 };
30549 \f
30550 /* TM vector builtins. */
30552 /* Reuse the existing x86-specific `struct builtin_description' cause
30553 we're lazy. Add casts to make them fit. */
30555 {
30556 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30557 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30558 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30559 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30560 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30561 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30562 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30564 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30565 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30566 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30567 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30568 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30569 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30570 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30572 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30573 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30574 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30575 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30576 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30577 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30578 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30580 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30581 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30582 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30583 };
30585 /* TM callbacks. */
30587 /* Return the builtin decl needed to load a vector of TYPE. */
30589 static tree
30591 {
30593 {
30595 {
30602 }
30603 }
30605 }
30607 /* Return the builtin decl needed to store a vector of TYPE. */
30609 static tree
30611 {
30613 {
30615 {
30622 }
30623 }
30625 }
30626 \f
30627 /* Initialize the transactional memory vector load/store builtins. */
30629 static void
30631 {
30635 tree decl;
30642 /* If there are no builtins defined, we must be compiling in a
30643 language without trans-mem support. */
30647 /* Use whatever attributes a normal TM load has. */
30651 /* Use whatever attributes a normal TM store has. */
30655 /* Use whatever attributes a normal TM log has. */
30663 {
30667 {
30675 {
30678 }
30680 {
30683 }
30684 else
30685 {
30688 }
30690 /* The builtin without the prefix for
30691 calling it directly. */
30693 attrs);
30694 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30695 set the TYPE_ATTRIBUTES. */
30699 }
30700 }
30701 }
30703 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30704 in the current target ISA to allow the user to compile particular modules
30705 with different target specific options that differ from the command line
30706 options. */
30707 static void
30709 {
30714 /* Add all special builtins with variable number of operands. */
30718 {
30724 }
30726 /* Add all builtins with variable number of operands. */
30730 {
30736 }
30738 /* Add all builtins with rounding. */
30742 {
30748 }
30750 /* pcmpestr[im] insns. */
30754 {
30757 else
30760 }
30762 /* pcmpistr[im] insns. */
30766 {
30769 else
30772 }
30774 /* comi/ucomi insns. */
30776 {
30779 else
30782 }
30784 /* SSE */
30790 /* SSE or 3DNow!A */
30793 IX86_BUILTIN_MASKMOVQ);
30795 /* SSE2 */
30804 /* SSE3. */
30810 /* AES */
30824 /* PCLMUL */
30828 /* RDRND */
30835 IX86_BUILTIN_RDRAND64_STEP);
30837 /* AVX2 */
30839 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30840 IX86_BUILTIN_GATHERSIV2DF);
30843 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30844 IX86_BUILTIN_GATHERSIV4DF);
30847 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30848 IX86_BUILTIN_GATHERDIV2DF);
30851 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30852 IX86_BUILTIN_GATHERDIV4DF);
30855 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30856 IX86_BUILTIN_GATHERSIV4SF);
30859 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30860 IX86_BUILTIN_GATHERSIV8SF);
30863 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30864 IX86_BUILTIN_GATHERDIV4SF);
30867 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30868 IX86_BUILTIN_GATHERDIV8SF);
30871 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30872 IX86_BUILTIN_GATHERSIV2DI);
30875 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
30876 IX86_BUILTIN_GATHERSIV4DI);
30879 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
30880 IX86_BUILTIN_GATHERDIV2DI);
30883 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
30884 IX86_BUILTIN_GATHERDIV4DI);
30887 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
30888 IX86_BUILTIN_GATHERSIV4SI);
30891 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
30892 IX86_BUILTIN_GATHERSIV8SI);
30895 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
30896 IX86_BUILTIN_GATHERDIV4SI);
30899 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
30900 IX86_BUILTIN_GATHERDIV8SI);
30903 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
30904 IX86_BUILTIN_GATHERALTSIV4DF);
30907 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
30908 IX86_BUILTIN_GATHERALTDIV8SF);
30911 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
30912 IX86_BUILTIN_GATHERALTSIV4DI);
30915 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
30916 IX86_BUILTIN_GATHERALTDIV8SI);
30918 /* AVX512F */
30920 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
30921 IX86_BUILTIN_GATHER3SIV16SF);
30924 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
30925 IX86_BUILTIN_GATHER3SIV8DF);
30928 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
30929 IX86_BUILTIN_GATHER3DIV16SF);
30932 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
30933 IX86_BUILTIN_GATHER3DIV8DF);
30936 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
30937 IX86_BUILTIN_GATHER3SIV16SI);
30940 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
30941 IX86_BUILTIN_GATHER3SIV8DI);
30944 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
30945 IX86_BUILTIN_GATHER3DIV16SI);
30948 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
30949 IX86_BUILTIN_GATHER3DIV8DI);
30952 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
30953 IX86_BUILTIN_GATHER3ALTSIV8DF);
30956 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
30957 IX86_BUILTIN_GATHER3ALTDIV16SF);
30960 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
30961 IX86_BUILTIN_GATHER3ALTSIV8DI);
30964 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
30965 IX86_BUILTIN_GATHER3ALTDIV16SI);
30968 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
30969 IX86_BUILTIN_SCATTERSIV16SF);
30972 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
30973 IX86_BUILTIN_SCATTERSIV8DF);
30976 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
30977 IX86_BUILTIN_SCATTERDIV16SF);
30980 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
30981 IX86_BUILTIN_SCATTERDIV8DF);
30984 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
30985 IX86_BUILTIN_SCATTERSIV16SI);
30988 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
30989 IX86_BUILTIN_SCATTERSIV8DI);
30992 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
30993 IX86_BUILTIN_SCATTERDIV16SI);
30996 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
30997 IX86_BUILTIN_SCATTERDIV8DI);
30999 /* AVX512PF */
31001 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31002 IX86_BUILTIN_GATHERPFDPD);
31004 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31005 IX86_BUILTIN_GATHERPFDPS);
31007 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31008 IX86_BUILTIN_GATHERPFQPD);
31010 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31011 IX86_BUILTIN_GATHERPFQPS);
31013 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31014 IX86_BUILTIN_SCATTERPFDPD);
31016 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31017 IX86_BUILTIN_SCATTERPFDPS);
31019 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31020 IX86_BUILTIN_SCATTERPFQPD);
31022 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31023 IX86_BUILTIN_SCATTERPFQPS);
31025 /* SHA */
31041 /* RTM. */
31045 /* MMX access to the vec_init patterns. */
31050 V4HI_FTYPE_HI_HI_HI_HI,
31051 IX86_BUILTIN_VEC_INIT_V4HI);
31054 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31055 IX86_BUILTIN_VEC_INIT_V8QI);
31057 /* Access to the vec_extract patterns. */
31079 /* Access to the vec_set patterns. */
31100 /* RDSEED */
31109 /* ADCX */
31114 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31115 IX86_BUILTIN_ADDCARRYX64);
31117 /* Read/write FLAGS. */
31128 /* Add FMA4 multi-arg argument instructions */
31130 {
31136 }
31137 }
31139 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31140 to return a pointer to VERSION_DECL if the outcome of the expression
31141 formed by PREDICATE_CHAIN is true. This function will be called during
31142 version dispatch to decide which function version to execute. It returns
31143 the basic block at the end, to which more conditions can be added. */
31145 static basic_block
31148 {
31149 gimple return_stmt;
31151 gimple convert_stmt;
31152 gimple call_cond_stmt;
31153 gimple if_else_stmt;
31159 gimple_seq gseq;
31176 {
31184 }
31187 {
31202 else
31203 {
31204 gimple assign_stmt;
31205 /* Use MIN_EXPR to check if any integer is zero?.
31206 and_expr_var = min_expr <cond_var, and_expr_var> */
31214 }
31215 }
31218 integer_zero_node,
31248 }
31250 /* This parses the attribute arguments to target in DECL and determines
31251 the right builtin to use to match the platform specification.
31252 It returns the priority value for this version decl. If PREDICATE_LIST
31253 is not NULL, it stores the list of cpu features that need to be checked
31254 before dispatching this function. */
31256 static unsigned int
31258 {
31259 tree attrs;
31261 tree target_node;
31268 /* Priority of i386 features, greater value is higher priority. This is
31269 used to decide the order in which function dispatch must happen. For
31270 instance, a version specialized for SSE4.2 should be checked for dispatch
31271 before a version for SSE3, as SSE4.2 implies SSE3. */
31272 enum feature_priority
31273 {
31275 P_MMX,
31276 P_SSE,
31277 P_SSE2,
31278 P_SSE3,
31279 P_SSSE3,
31280 P_PROC_SSSE3,
31281 P_SSE4_A,
31282 P_PROC_SSE4_A,
31283 P_SSE4_1,
31284 P_SSE4_2,
31285 P_PROC_SSE4_2,
31286 P_POPCNT,
31287 P_AVX,
31288 P_PROC_AVX,
31289 P_FMA4,
31290 P_XOP,
31291 P_PROC_XOP,
31292 P_FMA,
31293 P_PROC_FMA,
31294 P_AVX2,
31295 P_PROC_AVX2
31296 };
31300 /* These are the target attribute strings for which a dispatcher is
31301 available, from fold_builtin_cpu. */
31303 static struct _feature_list
31304 {
31307 }
31309 {
31324 };
31327 static unsigned int NUM_FEATURES
31343 /* Return priority zero for default function. */
31347 /* Handle arch= if specified. For priority, set it to be 1 more than
31348 the best instruction set the processor can handle. For instance, if
31349 there is a version for atom and a version for ssse3 (the highest ISA
31350 priority for atom), the atom version must be checked for dispatch
31351 before the ssse3 version. */
31353 {
31363 {
31365 {
31373 else
31374 /* We translate "arch=corei7" and "arch=nehalem" to
31375 "corei7" so that it will be mapped to M_INTEL_COREI7
31376 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31383 else
31390 else
31430 }
31431 }
31436 {
31440 }
31443 {
31445 /* For a C string literal the length includes the trailing NULL. */
31448 predicate_chain);
31449 }
31450 }
31452 /* Process feature name. */
31459 {
31460 /* Do not process "arch=" */
31462 {
31465 }
31467 {
31469 {
31471 {
31476 predicate_chain);
31477 }
31478 /* Find the maximum priority feature. */
31483 }
31484 }
31486 {
31490 }
31492 }
31496 {
31499 attrs_str);
31501 }
31503 {
31506 }
31509 }
31511 /* This compares the priority of target features in function DECL1
31512 and DECL2. It returns positive value if DECL1 is higher priority,
31513 negative value if DECL2 is higher priority and 0 if they are the
31514 same. */
31516 static int
31518 {
31523 }
31525 /* V1 and V2 point to function versions with different priorities
31526 based on the target ISA. This function compares their priorities. */
31528 static int
31530 {
31532 {
31533 tree version_decl;
31534 tree predicate_chain;
31541 }
31543 /* This function generates the dispatch function for
31544 multi-versioned functions. DISPATCH_DECL is the function which will
31545 contain the dispatch logic. FNDECLS are the function choices for
31546 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31547 in DISPATCH_DECL in which the dispatch code is generated. */
31549 static int
31553 {
31554 tree default_decl;
31555 gimple ifunc_cpu_init_stmt;
31556 gimple_seq gseq;
31558 tree ele;
31564 struct _function_version_info
31565 {
31566 tree version_decl;
31567 tree predicate_chain;
31575 /*fndecls_p is actually a vector. */
31578 /* At least one more version other than the default. */
31585 /* The first version in the vector is the default decl. */
31591 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31592 constructors, so explicity call __builtin_cpu_init here. */
31603 {
31607 /* Get attribute string, parse it and find the right predicate decl.
31608 The predicate function could be a lengthy combination of many
31609 features, like arch-type and various isa-variants. */
31620 actual_versions++;
31621 }
31623 /* Sort the versions according to descending order of dispatch priority. The
31624 priority is based on the ISA. This is not a perfect solution. There
31625 could still be ambiguity. If more than one function version is suitable
31626 to execute, which one should be dispatched? In future, allow the user
31627 to specify a dispatch priority next to the version. */
31637 /* dispatch default version at the end. */
31643 }
31645 /* Comparator function to be used in qsort routine to sort attribute
31646 specification strings to "target". */
31648 static int
31650 {
31654 }
31656 /* ARGLIST is the argument to target attribute. This function tokenizes
31657 the comma separated arguments, sorts them and returns a string which
31658 is a unique identifier for the comma separated arguments. It also
31659 replaces non-identifier characters "=,-" with "_". */
31663 {
31664 tree arg;
31673 {
31678 argnum++;
31681 argnum++;
31682 }
31687 {
31693 }
31695 /* Replace "=,-" with "_". */
31708 {
31710 i++;
31712 }
31719 {
31724 }
31729 }
31731 /* This function changes the assembler name for functions that are
31732 versions. If DECL is a function version and has a "target"
31733 attribute, it appends the attribute string to its assembler name. */
31735 static tree
31737 {
31738 tree version_attr;
31746 "Function versions cannot be marked as gnu_inline,"
31755 /* target attribute string cannot be NULL. */
31759 version_string
31770 /* Allow assembler name to be modified if already set. */
31778 }
31780 /* This function returns true if FN1 and FN2 are versions of the same function,
31781 that is, the target strings of the function decls are different. This assumes
31782 that FN1 and FN2 have the same signature. */
31784 static bool
31786 {
31798 /* At least one function decl should have the target attribute specified. */
31802 /* Diagnose missing target attribute if one of the decls is already
31803 multi-versioned. */
31805 {
31807 {
31809 {
31814 }
31817 fn2);
31820 /* Prevent diagnosing of the same error multiple times. */
31825 }
31827 }
31832 /* The sorted target strings must be different for fn1 and fn2
31833 to be versions. */
31836 else
31843 }
31845 static tree
31847 {
31848 /* For function version, add the target suffix to the assembler name. */
31852 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31854 #endif
31857 }
31859 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31860 is true, append the full path name of the source file. */
31864 {
31872 /* Get a unique name that can be used globally without any chances
31873 of collision at link time. */
31883 /* Use '.' to concatenate names as it is demangler friendly. */
31886 suffix);
31887 else
31891 }
31893 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
31895 /* Make a dispatcher declaration for the multi-versioned function DECL.
31896 Calls to DECL function will be replaced with calls to the dispatcher
31897 by the front-end. Return the decl created. */
31899 static tree
31901 {
31902 tree func_decl;
31922 /* Mark this func as external, the resolver will flip it again if
31923 it gets generated. */
31925 /* This will be of type IFUNCs have to be externally visible. */
31929 }
31931 #endif
31933 /* Returns true if decl is multi-versioned and DECL is the default function,
31934 that is it is not tagged with target specific optimization. */
31936 static bool
31938 {
31947 }
31949 /* Make a dispatcher declaration for the multi-versioned function DECL.
31950 Calls to DECL function will be replaced with calls to the dispatcher
31951 by the front-end. Returns the decl of the dispatcher function. */
31953 static tree
31955 {
31977 /* Find the default version and make it the first node. */
31979 /* Go to the beginning of the chain. */
31984 {
31989 }
31991 /* If there is no default node, just return NULL. */
31995 /* Make default info the first node. */
31997 {
32004 }
32008 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32010 {
32015 /* Right now, the dispatching is done via ifunc. */
32021 dispatcher_version_info
32026 /* Set the dispatcher for all the versions. */
32029 {
32032 }
32033 }
32034 else
32035 #endif
32036 {
32038 "multiversioning needs ifunc which is not supported "
32040 }
32043 }
32045 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32046 it to CHAIN. */
32048 static tree
32050 {
32051 tree attr_name;
32052 tree attr_arg_name;
32053 tree attr_args;
32054 tree attr;
32061 }
32063 /* Make the resolver function decl to dispatch the versions of
32064 a multi-versioned function, DEFAULT_DECL. Create an
32065 empty basic block in the resolver and store the pointer in
32066 EMPTY_BB. Return the decl of the resolver function. */
32068 static tree
32072 {
32077 /* IFUNC's have to be globally visible. So, if the default_decl is
32078 not, then the name of the IFUNC should be made unique. */
32082 /* Append the filename to the resolver function if the versions are
32083 not externally visible. This is because the resolver function has
32084 to be externally visible for the loader to find it. So, appending
32085 the filename will prevent conflicts with a resolver function from
32086 another module which is based on the same version name. */
32089 /* The resolver function should return a (void *). */
32100 /* IFUNC resolvers have to be externally visible. */
32104 /* Resolver is not external, body is generated. */
32114 {
32115 /* In this case, each translation unit with a call to this
32116 versioned function will put out a resolver. Ensure it
32117 is comdat to keep just one copy. */
32120 }
32121 /* Build result decl and add to function_decl. */
32137 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32141 /* Create the alias for dispatch to resolver here. */
32142 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32146 }
32148 /* Generate the dispatching code body to dispatch multi-versioned function
32149 DECL. The target hook is called to process the "target" attributes and
32150 provide the code to dispatch the right function at run-time. NODE points
32151 to the dispatcher decl whose body will be created. */
32153 static tree
32155 {
32156 tree resolver_decl;
32157 basic_block empty_bb;
32158 tree default_ver_decl;
32174 /* The first version in the chain corresponds to the default version. */
32177 /* node is going to be an alias, so remove the finalized bit. */
32191 {
32193 /* Check for virtual functions here again, as by this time it should
32194 have been determined if this function needs a vtable index or
32195 not. This happens for methods in derived classes that override
32196 virtual methods in base classes but are not explicitly marked as
32197 virtual. */
32202 }
32208 }
32209 /* This builds the processor_model struct type defined in
32210 libgcc/config/i386/cpuinfo.c */
32212 static tree
32214 {
32221 /* The first 3 fields are unsigned int. */
32223 {
32229 }
32231 /* The last field is an array of unsigned integers of size one. */
32242 }
32244 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32246 static tree
32248 {
32249 tree new_decl;
32252 VAR_DECL,
32254 type);
32267 }
32269 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32270 into an integer defined in libgcc/config/i386/cpuinfo.c */
32272 static tree
32274 {
32280 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32281 enum processor_features
32282 {
32284 F_MMX,
32285 F_POPCNT,
32286 F_SSE,
32287 F_SSE2,
32288 F_SSE3,
32289 F_SSSE3,
32290 F_SSE4_1,
32291 F_SSE4_2,
32292 F_AVX,
32293 F_AVX2,
32294 F_SSE4_A,
32295 F_FMA4,
32296 F_XOP,
32297 F_FMA,
32298 F_MAX
32299 };
32301 /* These are the values for vendor types and cpu types and subtypes
32302 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32303 the corresponding start value. */
32304 enum processor_model
32305 {
32307 M_AMD,
32308 M_CPU_TYPE_START,
32309 M_INTEL_BONNELL,
32310 M_INTEL_CORE2,
32311 M_INTEL_COREI7,
32312 M_AMDFAM10H,
32313 M_AMDFAM15H,
32314 M_INTEL_SILVERMONT,
32315 M_AMD_BTVER1,
32316 M_AMD_BTVER2,
32317 M_CPU_SUBTYPE_START,
32318 M_INTEL_COREI7_NEHALEM,
32319 M_INTEL_COREI7_WESTMERE,
32320 M_INTEL_COREI7_SANDYBRIDGE,
32321 M_AMDFAM10H_BARCELONA,
32322 M_AMDFAM10H_SHANGHAI,
32323 M_AMDFAM10H_ISTANBUL,
32324 M_AMDFAM15H_BDVER1,
32325 M_AMDFAM15H_BDVER2,
32326 M_AMDFAM15H_BDVER3,
32327 M_AMDFAM15H_BDVER4,
32328 M_INTEL_COREI7_IVYBRIDGE,
32329 M_INTEL_COREI7_HASWELL
32330 };
32332 static struct _arch_names_table
32333 {
32336 }
32338 {
32363 };
32365 static struct _isa_names_table
32366 {
32369 }
32371 {
32387 };
32401 {
32402 /* *args must be a expr that can contain other EXPRS leading to a
32403 STRING_CST. */
32405 {
32408 }
32410 }
32415 {
32416 tree ref;
32417 tree field;
32418 tree final;
32421 unsigned int NUM_ARCH_NAMES
32430 {
32434 }
32439 /* CPU types are stored in the next field. */
32442 {
32445 }
32447 /* CPU subtypes are stored in the next field. */
32449 {
32452 }
32454 /* Get the appropriate field in __cpu_model. */
32458 /* Check the value. */
32462 }
32464 {
32465 tree ref;
32466 tree array_elt;
32467 tree field;
32468 tree final;
32471 unsigned int NUM_ISA_NAMES
32480 {
32484 }
32487 /* Get the last field, which is __cpu_features. */
32491 /* Get the appropriate field: __cpu_model.__cpu_features */
32495 /* Access the 0th element of __cpu_features array. */
32500 /* Return __cpu_model.__cpu_features[0] & field_val */
32504 }
32506 }
32508 static tree
32511 {
32513 {
32518 {
32521 }
32522 }
32524 #ifdef SUBTARGET_FOLD_BUILTIN
32526 #endif
32529 }
32531 /* Make builtins to detect cpu type and features supported. NAME is
32532 the builtin name, CODE is the builtin code, and FTYPE is the function
32533 type of the builtin. */
32535 static void
32538 {
32539 tree decl;
32540 tree type;
32548 }
32550 /* Make builtins to get CPU type and features supported. The created
32551 builtins are :
32553 __builtin_cpu_init (), to detect cpu type and features,
32554 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32555 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32556 */
32558 static void
32560 {
32567 }
32569 /* Internal method for ix86_init_builtins. */
32571 static void
32573 {
32585 sysv_va_ref =
32588 fnvoid_va_end_ms =
32590 fnvoid_va_start_ms =
32592 fnvoid_va_end_sysv =
32594 fnvoid_va_start_sysv =
32596 NULL_TREE);
32597 fnvoid_va_copy_ms =
32599 NULL_TREE);
32600 fnvoid_va_copy_sysv =
32616 }
32618 static void
32620 {
32623 /* The __float80 type. */
32626 {
32627 /* The __float80 type. */
32632 }
32635 /* The __float128 type. */
32641 /* This macro is built by i386-builtin-types.awk. */
32642 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32643 }
32645 static void
32647 {
32648 tree t;
32652 /* Builtins to get CPU type and features. */
32655 /* TFmode support builtins. */
32661 /* We will expand them to normal call if SSE isn't available since
32662 they are used by libgcc. */
32681 #ifdef SUBTARGET_INIT_BUILTINS
32682 SUBTARGET_INIT_BUILTINS;
32683 #endif
32684 }
32686 /* Return the ix86 builtin for CODE. */
32688 static tree
32690 {
32695 }
32697 /* Errors in the source file can cause expand_expr to return const0_rtx
32698 where we expect a vector. To avoid crashing, use one of the vector
32699 clear instructions. */
32700 static rtx
32702 {
32706 }
32708 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32710 static rtx
32712 {
32713 rtx pat;
32733 {
32737 }
32751 }
32753 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32755 static rtx
32759 {
32760 rtx pat;
32768 rtx op;
32775 {
32855 }
32865 {
32872 {
32874 {
32877 {
32895 xop_rotl:
32897 {
32900 gcc_checking_assert
32902 }
32903 else
32904 {
32905 gcc_checking_assert
32916 }
32920 }
32921 }
32922 }
32923 else
32924 {
32925 non_constant:
32929 /* If we aren't optimizing, only allow one memory operand to be
32930 generated. */
32932 num_memory++;
32940 }
32944 }
32947 {
32958 else
32959 {
32965 }
32978 }
32985 }
32987 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
32988 insns with vec_merge. */
32990 static rtx
32992 rtx target)
32993 {
32994 rtx pat;
33021 }
33023 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33025 static rtx
33028 {
33029 rtx pat;
33034 rtx op2;
33045 /* Swap operands if we have a comparison that isn't available in
33046 hardware. */
33048 {
33053 }
33073 }
33075 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33077 static rtx
33079 rtx target)
33080 {
33081 rtx pat;
33095 /* Swap operands if we have a comparison that isn't available in
33096 hardware. */
33098 {
33102 }
33123 const0_rtx)));
33126 }
33128 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33130 static rtx
33132 rtx target)
33133 {
33134 rtx pat;
33159 }
33161 static rtx
33164 {
33165 rtx pat;
33170 rtx op2;
33197 }
33199 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33201 static rtx
33203 rtx target)
33204 {
33205 rtx pat;
33238 const0_rtx)));
33241 }
33243 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33245 static rtx
33248 {
33249 rtx pat;
33287 {
33290 }
33293 {
33302 }
33304 {
33313 }
33314 else
33315 {
33322 }
33330 {
33335 emit_insn
33339 FLAGS_REG),
33340 const0_rtx)));
33342 }
33343 else
33345 }
33348 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33350 static rtx
33353 {
33354 rtx pat;
33382 {
33385 }
33388 {
33397 }
33399 {
33408 }
33409 else
33410 {
33417 }
33425 {
33430 emit_insn
33434 FLAGS_REG),
33435 const0_rtx)));
33437 }
33438 else
33440 }
33442 /* Subroutine of ix86_expand_builtin to take care of insns with
33443 variable number of operands. */
33445 static rtx
33448 {
33454 struct
33455 {
33456 rtx op;
33468 {
33916 }
33921 {
33924 }
33927 {
33934 }
33935 else
33936 {
33939 }
33942 {
33949 {
33950 /* SIMD shift insns take either an 8-bit immediate or
33951 register as count. But builtin functions take int as
33952 count. If count doesn't match, we put it in register. */
33954 {
33958 }
33959 }
33962 {
33965 {
34041 {
34045 {
34048 }
34054 }
34056 }
34057 }
34058 else
34059 {
34063 /* If we aren't optimizing, only allow one memory operand to
34064 be generated. */
34066 num_memory++;
34069 {
34072 }
34073 else
34074 {
34077 }
34078 }
34082 }
34085 {
34110 }
34117 }
34119 /* Transform pattern of following layout:
34120 (parallel [
34121 set (A B)
34122 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34123 ])
34124 into:
34125 (set (A B))
34127 Or:
34128 (parallel [ A B
34129 ...
34130 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34131 ...
34132 ])
34133 into:
34134 (parallel [ A B ... ]) */
34136 static rtx
34138 {
34145 {
34154 }
34155 else
34156 {
34162 {
34167 }
34169 /* No more than 1 occurence was removed. */
34173 }
34174 }
34176 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34177 with rounding. */
34178 static rtx
34181 {
34198 /* See avxintrin.h for values. */
34200 {
34204 };
34206 {
34211 };
34214 {
34217 }
34219 {
34222 }
34225 {
34228 }
34251 ? CODE_FOR_sse_ucomi_round
34258 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34260 {
34266 }
34267 else
34268 {
34271 }
34277 set_dst,
34278 const0_rtx)));
34281 }
34283 static rtx
34286 {
34287 rtx pat;
34289 struct
34290 {
34291 rtx op;
34301 {
34378 }
34388 {
34395 {
34397 {
34399 {
34415 }
34416 }
34417 }
34419 {
34421 {
34424 }
34426 /* If there is no rounding use normal version of the pattern. */
34429 }
34430 else
34431 {
34436 {
34439 }
34440 else
34441 {
34444 }
34445 }
34449 }
34452 {
34477 }
34487 }
34489 /* Subroutine of ix86_expand_builtin to take care of special insns
34490 with variable number of operands. */
34492 static rtx
34495 {
34496 tree arg;
34500 struct
34501 {
34502 rtx op;
34512 {
34551 {
34559 }
34578 /* Reserve memory operand for target. */
34581 {
34582 /* These builtins and instructions require the memory
34583 to be properly aligned. */
34602 }
34627 {
34628 /* These builtins and instructions require the memory
34629 to be properly aligned. */
34638 }
34639 /* FALLTHRU */
34657 /* Reserve memory operand for target. */
34670 {
34671 /* These builtins and instructions require the memory
34672 to be properly aligned. */
34681 }
34694 }
34699 {
34704 {
34707 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34708 on it. Try to improve it using get_pointer_alignment,
34709 and if the special builtin is one that requires strict
34710 mode alignment, also from it's GET_MODE_ALIGNMENT.
34711 Failure to do so could lead to ix86_legitimate_combined_insn
34712 rejecting all changes to such insns. */
34718 }
34719 else
34722 }
34723 else
34724 {
34731 }
34734 {
34743 {
34745 {
34751 else
34754 }
34755 }
34756 else
34757 {
34759 {
34760 /* This must be the memory operand. */
34763 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34764 on it. Try to improve it using get_pointer_alignment,
34765 and if the special builtin is one that requires strict
34766 mode alignment, also from it's GET_MODE_ALIGNMENT.
34767 Failure to do so could lead to ix86_legitimate_combined_insn
34768 rejecting all changes to such insns. */
34774 }
34775 else
34776 {
34777 /* This must be register. */
34783 else
34784 {
34787 }
34788 }
34789 }
34793 }
34796 {
34811 }
34817 }
34819 /* Return the integer constant in ARG. Constrain it to be in the range
34820 of the subparts of VEC_TYPE; issue an error if not. */
34822 static int
34824 {
34829 {
34832 }
34835 }
34837 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34838 ix86_expand_vector_init. We DO have language-level syntax for this, in
34839 the form of (type){ init-list }. Except that since we can't place emms
34840 instructions from inside the compiler, we can't allow the use of MMX
34841 registers unless the user explicitly asks for it. So we do *not* define
34842 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34843 we have builtins invoked by mmintrin.h that gives us license to emit
34844 these sorts of instructions. */
34846 static rtx
34848 {
34858 {
34861 }
34868 }
34870 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34871 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
34872 had a language-level syntax for referencing vector elements. */
34874 static rtx
34876 {
34880 rtx op0;
34900 }
34902 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34903 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
34904 a language-level syntax for referencing vector elements. */
34906 static rtx
34908 {
34932 /* OP0 is the source of these builtin functions and shouldn't be
34933 modified. Create a copy, use it and return it as target. */
34939 }
34941 /* Expand an expression EXP that calls a built-in function,
34942 with result going to TARGET if that's convenient
34943 (and in mode MODE if that's convenient).
34944 SUBTARGET may be used as the target for computing one of EXP's operands.
34945 IGNORE is nonzero if the value is to be ignored. */
34947 static rtx
34950 {
34960 /* For CPU builtins that can be folded, fold first and expand the fold. */
34962 {
34964 {
34965 /* Make it call __cpu_indicator_init in libgcc. */
34971 }
34974 {
34979 }
34980 }
34982 /* Determine whether the builtin function is available under the current ISA.
34983 Originally the builtin was not created if it wasn't applicable to the
34984 current ISA based on the command line switches. With function specific
34985 options, we need to check in the context of the function making the call
34986 whether it is supported. */
34989 {
34995 else
34996 {
35000 }
35002 }
35005 {
35009 ? CODE_FOR_mmx_maskmovq
35011 /* Note the arg order is different from the operand order. */
35112 {
35113 REAL_VALUE_TYPE inf;
35114 rtx tmp;
35126 }
35136 {
35142 insn = (TARGET_64BIT
35146 }
35148 {
35149 insn = (TARGET_64BIT
35153 }
35154 else
35155 {
35158 insn = (TARGET_64BIT
35166 {
35169 }
35171 }
35174 {
35175 /* mode is VOIDmode if __builtin_rd* has been called
35176 without lhs. */
35180 }
35183 {
35188 }
35202 {
35227 }
35233 {
35236 }
35256 {
35259 }
35265 {
35269 {
35290 }
35295 }
35296 else
35297 {
35299 {
35311 }
35313 }
35343 ? CODE_FOR_tbm_bextri_si
35346 {
35349 }
35350 else
35351 {
35360 }
35376 rdrand_step:
35383 {
35386 }
35392 /* Emit SImode conditional move. */
35394 {
35397 }
35400 else
35407 const0_rtx);
35426 rdseed_step:
35433 {
35436 }
35442 const0_rtx);
35460 addcarryx:
35468 /* Generate CF from input operand. */
35473 /* Gen ADCX instruction to compute X+Y+CF. */
35488 /* Store the result. */
35491 {
35494 }
35497 /* Return current CF value. */
35539 kortest:
35553 /* Emit kortest. */
35555 /* And use setcc to return result from flags. */
35706 gather_gen:
35707 rtx half;
35720 /* Note the arg order is different from the operand order. */
35731 else
35735 {
35757 else
35764 {
35769 }
35776 else
35783 {
35788 }
35792 }
35794 /* Force memory operand only with base register here. But we
35795 don't want to do it on memory operand for other builtin
35796 functions. */
35806 {
35809 }
35810 else
35811 {
35814 }
35816 {
35819 }
35821 /* Optimize. If mask is known to have all high bits set,
35822 replace op0 with pc_rtx to signal that the instruction
35823 overwrites the whole destination and doesn't use its
35824 previous contents. */
35826 {
35828 {
35831 }
35833 {
35836 {
35840 negative++;
35843 negative++;
35844 }
35847 }
35850 {
35851 /* Recognize also when mask is like:
35852 __v2df src = _mm_setzero_pd ();
35853 __v2df mask = _mm_cmpeq_pd (src, src);
35854 or
35855 __v8sf src = _mm256_setzero_ps ();
35856 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
35857 as that is a cheaper way to load all ones into
35858 a register than having to load a constant from
35859 memory. */
35862 {
35867 {
35874 /* FALLTHRU */
35884 }
35885 }
35886 }
35887 }
35895 {
35919 }
35922 scatter_gen:
35938 /* Force memory operand only with base register here. But we
35939 don't want to do it on memory operand for other builtin
35940 functions. */
35947 {
35950 }
35951 else
35952 {
35955 }
35964 {
35967 }
35976 vec_prefetch_gen:
35994 {
35997 }
35999 {
36002 }
36007 /* Force memory operand only with base register here. But we
36008 don't want to do it on memory operand for other builtin
36009 functions. */
36016 {
36019 }
36022 {
36025 }
36041 {
36044 }
36050 }
36063 {
36067 /* Emit a normal call if SSE isn't available. */
36071 }
36100 }
36102 /* This returns the target-specific builtin with code CODE if
36103 current_function_decl has visibility on this builtin, which is checked
36104 using isa flags. Returns NULL_TREE otherwise. */
36107 {
36111 /* Determine the isa flags of current_function_decl. */
36123 else
36125 }
36127 /* Returns a function decl for a vectorized version of the builtin function
36128 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36129 if it is not available. */
36131 static tree
36133 tree type_in)
36134 {
36150 {
36153 {
36160 }
36165 {
36168 }
36173 {
36180 }
36186 /* The round insn does not trap on denormals. */
36191 {
36198 }
36204 /* The round insn does not trap on denormals. */
36209 {
36214 }
36220 /* The round insn does not trap on denormals. */
36225 {
36232 }
36238 /* The round insn does not trap on denormals. */
36243 {
36248 }
36255 {
36260 }
36267 {
36272 }
36278 /* The round insn does not trap on denormals. */
36283 {
36290 }
36296 /* The round insn does not trap on denormals. */
36301 {
36306 }
36311 {
36318 }
36323 {
36330 }
36334 /* The round insn does not trap on denormals. */
36339 {
36344 }
36348 /* The round insn does not trap on denormals. */
36353 {
36358 }
36362 /* The round insn does not trap on denormals. */
36367 {
36372 }
36376 /* The round insn does not trap on denormals. */
36381 {
36386 }
36390 /* The round insn does not trap on denormals. */
36395 {
36400 }
36404 /* The round insn does not trap on denormals. */
36409 {
36414 }
36418 /* The round insn does not trap on denormals. */
36423 {
36428 }
36432 /* The round insn does not trap on denormals. */
36437 {
36442 }
36446 /* The round insn does not trap on denormals. */
36451 {
36456 }
36460 /* The round insn does not trap on denormals. */
36465 {
36470 }
36475 {
36480 }
36485 {
36490 }
36495 }
36497 /* Dispatch to a handler for a vectorization library. */
36500 type_in);
36503 }
36505 /* Handler for an SVML-style interface to
36506 a library with vectorized intrinsics. */
36508 static tree
36510 {
36518 /* The SVML is suitable for unsafe math only. */
36531 {
36578 }
36587 {
36590 }
36591 else
36594 /* Convert to uppercase. */
36599 args;
36601 arity++;
36605 else
36608 /* Build a function declaration for the vectorized function. */
36617 }
36619 /* Handler for an ACML-style interface to
36620 a library with vectorized intrinsics. */
36622 static tree
36624 {
36632 /* The ACML is 64bits only and suitable for unsafe math only as
36633 it does not correctly support parts of IEEE with the required
36634 precision such as denormals. */
36648 {
36678 }
36685 args;
36687 arity++;
36691 else
36694 /* Build a function declaration for the vectorized function. */
36703 }
36705 /* Returns a decl of a function that implements gather load with
36706 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36707 Return NULL_TREE if it is not available. */
36709 static tree
36712 {
36728 /* v*gather* insn sign extends index to pointer mode. */
36740 {
36768 else
36774 else
36780 else
36786 else
36791 }
36794 }
36796 /* Returns a code for a target-specific builtin that implements
36797 reciprocal of the function, or NULL_TREE if not available. */
36799 static tree
36802 {
36809 /* Machine dependent builtins. */
36811 {
36812 /* Vectorized version of sqrt to rsqrt conversion. */
36821 }
36822 else
36823 /* Normal builtins. */
36825 {
36826 /* Sqrt to rsqrt conversion. */
36832 }
36833 }
36834 \f
36835 /* Helper for avx_vpermilps256_operand et al. This is also used by
36836 the expansion functions to turn the parallel back into a mask.
36837 The return value is 0 for no match and the imm8+1 for a match. */
36839 int
36841 {
36849 /* Validate that all of the elements are constants, and not totally
36850 out of range. Copy the data into an integral array to make the
36851 subsequent checks easier. */
36853 {
36863 }
36866 {
36868 /* In the 512-bit DFmode case, we can only move elements within
36869 a 128-bit lane. First fill the second part of the mask,
36870 then fallthru. */
36872 {
36876 }
36878 {
36882 }
36883 /* FALLTHRU */
36886 /* In the 256-bit DFmode case, we can only move elements within
36887 a 128-bit lane. */
36889 {
36893 }
36895 {
36899 }
36903 /* In 512 bit SFmode case, permutation in the upper 256 bits
36904 must mirror the permutation in the lower 256-bits. */
36908 /* FALLTHRU */
36911 /* In 256 bit SFmode case, we have full freedom of
36912 movement within the low 128-bit lane, but the high 128-bit
36913 lane must mirror the exact same pattern. */
36918 /* FALLTHRU */
36922 /* In the 128-bit case, we've full freedom in the placement of
36923 the elements from the source operand. */
36930 }
36932 /* Make sure success has a non-zero value by adding one. */
36934 }
36936 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
36937 the expansion functions to turn the parallel back into a mask.
36938 The return value is 0 for no match and the imm8+1 for a match. */
36940 int
36942 {
36950 /* Validate that all of the elements are constants, and not totally
36951 out of range. Copy the data into an integral array to make the
36952 subsequent checks easier. */
36954 {
36964 }
36966 /* Validate that the halves of the permute are halves. */
36974 /* Reconstruct the mask. */
36976 {
36982 }
36984 /* Make sure success has a non-zero value by adding one. */
36986 }
36987 \f
36988 /* Return a register priority for hard reg REGNO. */
36989 static int
36991 {
36992 /* ebp and r13 as the base always wants a displacement, r12 as the
36993 base always wants an index. So discourage their usage in an
36994 address. */
36999 /* New x86-64 int registers result in bigger code size. Discourage
37000 them. */
37003 /* New x86-64 SSE registers result in bigger code size. Discourage
37004 them. */
37007 /* Usage of AX register results in smaller code. Prefer it. */
37011 }
37013 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37015 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37016 QImode must go into class Q_REGS.
37017 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37018 movdf to do mem-to-mem moves through integer regs. */
37020 static reg_class_t
37022 {
37025 /* We're only allowed to return a subclass of CLASS. Many of the
37026 following checks fail for NO_REGS, so eliminate that early. */
37030 /* All classes can load zeros. */
37034 /* Force constants into memory if we are loading a (nonzero) constant into
37035 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37036 instructions to load from a constant. */
37043 /* Prefer SSE regs only, if we can use them for math. */
37047 /* Floating-point constants need more complex checks. */
37049 {
37050 /* General regs can load everything. */
37054 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37055 zero above. We only want to wind up preferring 80387 registers if
37056 we plan on doing computation with them. */
37059 {
37060 /* Limit class to non-sse. */
37069 }
37072 }
37074 /* Generally when we see PLUS here, it's the function invariant
37075 (plus soft-fp const_int). Which can only be computed into general
37076 regs. */
37080 /* QImode constants are easy to load, but non-constant QImode data
37081 must go into Q_REGS. */
37083 {
37089 }
37092 }
37094 /* Discourage putting floating-point values in SSE registers unless
37095 SSE math is being used, and likewise for the 387 registers. */
37096 static reg_class_t
37098 {
37101 /* Restrict the output reload class to the register bank that we are doing
37102 math on. If we would like not to return a subset of CLASS, reject this
37103 alternative: if reload cannot do this, it will still use its choice. */
37109 {
37114 else
37116 }
37119 }
37121 static reg_class_t
37124 {
37125 /* Double-word spills from general registers to non-offsettable memory
37126 references (zero-extended addresses) require special handling. */
37132 {
37134 ? CODE_FOR_reload_noff_load
37136 /* Add the cost of moving address to a temporary. */
37140 }
37142 /* QImode spills from non-QI registers require
37143 intermediate register on 32bit targets. */
37149 {
37154 else
37160 /* Return Q_REGS if the operand is in memory. */
37163 }
37165 /* This condition handles corner case where an expression involving
37166 pointers gets vectorized. We're trying to use the address of a
37167 stack slot as a vector initializer.
37169 (set (reg:V2DI 74 [ vect_cst_.2 ])
37170 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37172 Eventually frame gets turned into sp+offset like this:
37174 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37175 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37176 (const_int 392 [0x188]))))
37178 That later gets turned into:
37180 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37181 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37182 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37184 We'll have the following reload recorded:
37186 Reload 0: reload_in (DI) =
37187 (plus:DI (reg/f:DI 7 sp)
37188 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37189 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37190 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37191 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37192 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37193 reload_reg_rtx: (reg:V2DI 22 xmm1)
37195 Which isn't going to work since SSE instructions can't handle scalar
37196 additions. Returning GENERAL_REGS forces the addition into integer
37197 register and reload can handle subsequent reloads without problems. */
37205 }
37207 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37209 static bool
37211 {
37213 {
37228 }
37231 }
37233 /* If we are copying between general and FP registers, we need a memory
37234 location. The same is true for SSE and MMX registers.
37236 To optimize register_move_cost performance, allow inline variant.
37238 The macro can't work reliably when one of the CLASSES is class containing
37239 registers from multiple units (SSE, MMX, integer). We avoid this by never
37240 combining those units in single alternative in the machine description.
37241 Ensure that this constraint holds to avoid unexpected surprises.
37243 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37244 enforce these sanity checks. */
37249 {
37258 {
37261 }
37266 /* ??? This is a lie. We do have moves between mmx/general, and for
37267 mmx/sse2. But by saying we need secondary memory we discourage the
37268 register allocator from using the mmx registers unless needed. */
37273 {
37274 /* SSE1 doesn't have any direct moves from other classes. */
37278 /* If the target says that inter-unit moves are more expensive
37279 than moving through memory, then don't generate them. */
37284 /* Between SSE and general, we have moves no larger than word size. */
37287 }
37290 }
37292 bool
37295 {
37297 }
37299 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37301 On the 80386, this is the size of MODE in words,
37302 except in the FP regs, where a single reg is always enough. */
37304 static unsigned char
37306 {
37308 {
37313 else
37315 }
37316 else
37317 {
37320 else
37322 }
37323 }
37325 /* Return true if the registers in CLASS cannot represent the change from
37326 modes FROM to TO. */
37328 bool
37331 {
37335 /* x87 registers can't do subreg at all, as all values are reformatted
37336 to extended precision. */
37341 {
37342 /* Vector registers do not support QI or HImode loads. If we don't
37343 disallow a change to these modes, reload will assume it's ok to
37344 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37345 the vec_dupv4hi pattern. */
37349 /* Vector registers do not support subreg with nonzero offsets, which
37350 are otherwise valid for integer registers. Since we can't see
37351 whether we have a nonzero offset from here, prohibit all
37352 nonparadoxical subregs changing size. */
37355 }
37358 }
37360 /* Return the cost of moving data of mode M between a
37361 register and memory. A value of 2 is the default; this cost is
37362 relative to those in `REGISTER_MOVE_COST'.
37364 This function is used extensively by register_move_cost that is used to
37365 build tables at startup. Make it inline in this case.
37366 When IN is 2, return maximum of in and out move cost.
37368 If moving between registers and memory is more expensive than
37369 between two registers, you should define this macro to express the
37370 relative cost.
37372 Model also increased moving costs of QImode registers in non
37373 Q_REGS classes.
37374 */
37378 {
37381 {
37384 {
37396 }
37400 }
37402 {
37405 {
37417 }
37421 }
37423 {
37426 {
37435 }
37439 }
37441 {
37444 {
37450 else
37455 }
37456 else
37457 {
37462 else
37464 }
37471 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37478 else
37482 }
37483 }
37485 static int
37488 {
37490 }
37493 /* Return the cost of moving data from a register in class CLASS1 to
37494 one in class CLASS2.
37496 It is not required that the cost always equal 2 when FROM is the same as TO;
37497 on some machines it is expensive to move between registers if they are not
37498 general registers. */
37500 static int
37502 reg_class_t class2_i)
37503 {
37507 /* In case we require secondary memory, compute cost of the store followed
37508 by load. In order to avoid bad register allocation choices, we need
37509 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37512 {
37518 /* In case of copying from general_purpose_register we may emit multiple
37519 stores followed by single load causing memory size mismatch stall.
37520 Count this as arbitrarily high cost of 20. */
37525 /* In the case of FP/MMX moves, the registers actually overlap, and we
37526 have to switch modes in order to treat them differently. */
37532 }
37534 /* Moves between SSE/MMX and integer unit are expensive. */
37538 /* ??? By keeping returned value relatively high, we limit the number
37539 of moves between integer and MMX/SSE registers for all targets.
37540 Additionally, high value prevents problem with x86_modes_tieable_p(),
37541 where integer modes in MMX/SSE registers are not tieable
37542 because of missing QImode and HImode moves to, from or between
37543 MMX/SSE registers. */
37553 }
37555 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37556 MODE. */
37558 bool
37560 {
37561 /* Flags and only flags can only hold CCmode values. */
37573 {
37574 /* We implement the move patterns for all vector modes into and
37575 out of SSE registers, even when no operation instructions
37576 are available. */
37578 /* For AVX-512 we allow, regardless of regno:
37579 - XI mode
37580 - any of 512-bit wide vector mode
37581 - any scalar mode. */
37588 /* xmm16-xmm31 are only available for AVX-512. */
37592 /* OImode and AVX modes are available only when AVX is enabled. */
37599 }
37601 {
37602 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37603 so if the register is available at all, then we can move data of
37604 the given mode into or out of it. */
37607 }
37610 {
37611 /* Take care for QImode values - they can be in non-QI regs,
37612 but then they do cause partial register stalls. */
37617 /* LRA checks if the hard register is OK for the given mode.
37618 QImode values can live in non-QI regs, so we allow all
37619 registers here. */
37623 }
37624 /* We handle both integer and floats in the general purpose registers. */
37631 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37632 on to use that value in smaller contexts, this can easily force a
37633 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37634 supporting DImode, allow it. */
37639 }
37641 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37642 tieable integer mode. */
37644 static bool
37646 {
37648 {
37661 }
37662 }
37664 /* Return true if MODE1 is accessible in a register that can hold MODE2
37665 without copying. That is, all register classes that can hold MODE2
37666 can also hold MODE1. */
37668 bool
37670 {
37678 /* MODE2 being XFmode implies fp stack or general regs, which means we
37679 can tie any smaller floating point modes to it. Note that we do not
37680 tie this with TFmode. */
37684 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37685 that we can tie it with SFmode. */
37689 /* If MODE2 is only appropriate for an SSE register, then tie with
37690 any other mode acceptable to SSE registers. */
37700 /* If MODE2 is appropriate for an MMX register, then tie
37701 with any other mode acceptable to MMX registers. */
37708 }
37710 /* Return the cost of moving between two registers of mode MODE. */
37712 static int
37714 {
37718 {
37750 }
37752 /* Return the cost of moving between two registers of mode MODE,
37753 assuming that the move will be in pieces of at most UNITS bytes. */
37755 }
37757 /* Compute a (partial) cost for rtx X. Return true if the complete
37758 cost has been computed, and false if subexpressions should be
37759 scanned. In either case, *TOTAL contains the cost result. */
37761 static bool
37764 {
37765 rtx mask;
37772 {
37776 {
37779 }
37791 && (!TARGET_64BIT
37796 else
37802 {
37805 }
37807 {
37817 }
37819 {
37822 {
37831 }
37832 }
37833 /* Fall back to (MEM (SYMBOL_REF)), since that's where
37834 it'll probably end up. Add a penalty for size. */
37841 /* The zero extensions is often completely free on x86_64, so make
37842 it as cheap as possible. */
37848 else
37860 {
37863 {
37866 }
37869 {
37872 }
37873 }
37874 /* FALLTHRU */
37881 {
37882 /* ??? Should be SSE vector operation cost. */
37883 /* At least for published AMD latencies, this really is the same
37884 as the latency for a simple fpu operation like fabs. */
37885 /* V*QImode is emulated with 1-11 insns. */
37887 {
37890 {
37891 /* For XOP we use vpshab, which requires a broadcast of the
37892 value to the variable shift insn. For constants this
37893 means a V16Q const in mem; even when we can perform the
37894 shift with one insn set the cost to prefer paddb. */
37896 {
37901 }
37903 }
37907 }
37908 else
37910 }
37912 {
37914 {
37917 else
37919 }
37920 else
37921 {
37924 else
37926 }
37927 }
37928 else
37929 {
37934 {
37935 /* Return the cost after shift-and truncation. */
37938 }
37939 else
37941 }
37945 {
37946 rtx sub;
37951 /* ??? SSE scalar/vector cost should be used here. */
37952 /* ??? Bald assumption that fma has the same cost as fmul. */
37956 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
37967 }
37971 {
37972 /* ??? SSE scalar cost should be used here. */
37975 }
37977 {
37980 }
37982 {
37983 /* ??? SSE vector cost should be used here. */
37986 }
37988 {
37989 /* V*QImode is emulated with 7-13 insns. */
37991 {
37998 }
37999 /* V*DImode is emulated with 5-8 insns. */
38001 {
38004 else
38006 }
38007 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38008 insns, including two PMULUDQ. */
38011 else
38014 }
38015 else
38016 {
38021 {
38024 nbits++;
38025 }
38026 else
38027 /* This is arbitrary. */
38030 /* Compute costs correctly for widening multiplication. */
38034 {
38041 {
38045 else
38047 }
38051 }
38059 }
38066 /* ??? SSE cost should be used here. */
38071 /* ??? SSE vector cost should be used here. */
38073 else
38080 {
38085 {
38088 {
38096 }
38097 }
38100 {
38103 {
38109 }
38110 }
38112 {
38120 }
38121 }
38122 /* FALLTHRU */
38126 {
38127 /* ??? SSE cost should be used here. */
38130 }
38132 {
38135 }
38137 {
38138 /* ??? SSE vector cost should be used here. */
38141 }
38142 /* FALLTHRU */
38149 {
38156 }
38157 /* FALLTHRU */
38161 {
38162 /* ??? SSE cost should be used here. */
38165 }
38167 {
38170 }
38172 {
38173 /* ??? SSE vector cost should be used here. */
38176 }
38177 /* FALLTHRU */
38181 {
38182 /* ??? Should be SSE vector operation cost. */
38183 /* At least for published AMD latencies, this really is the same
38184 as the latency for a simple fpu operation like fabs. */
38186 }
38189 else
38198 {
38199 /* This kind of construct is implemented using test[bwl].
38200 Treat it as if we had an AND. */
38205 }
38215 /* ??? SSE cost should be used here. */
38220 /* ??? SSE vector cost should be used here. */
38226 /* ??? SSE cost should be used here. */
38231 /* ??? SSE vector cost should be used here. */
38243 /* ??? Assume all of these vector manipulation patterns are
38244 recognizable. In which case they all pretty much have the
38245 same cost. */
38250 /* This is masked instruction, assume the same cost,
38251 as nonmasked variant. */
38254 else
38260 }
38261 }
38263 #if TARGET_MACHO
38267 /* Given a symbol name and its associated stub, write out the
38268 definition of the stub. */
38270 void
38272 {
38277 /* For 64-bit we shouldn't get here. */
38280 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38297 else
38304 {
38306 }
38308 {
38309 /* PIC stub. */
38310 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38316 }
38317 else
38320 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38321 it needs no stub-binding-helper. */
38328 {
38331 }
38332 else
38337 /* N.B. Keep the correspondence of these
38338 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38339 old-pic/new-pic/non-pic stubs; altering this will break
38340 compatibility with existing dylibs. */
38342 {
38343 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38345 }
38346 else
38347 /* 16-byte -mdynamic-no-pic stub. */
38353 }
38356 /* Order the registers for register allocator. */
38358 void
38360 {
38364 /* First allocate the local general purpose registers. */
38369 /* Global general purpose registers. */
38374 /* x87 registers come first in case we are doing FP math
38375 using them. */
38380 /* SSE registers. */
38386 /* Extended REX SSE registers. */
38390 /* Mask register. */
38394 /* x87 registers. */
38402 /* Initialize the rest of array as we do not allocate some registers
38403 at all. */
38406 }
38408 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38409 in struct attribute_spec handler. */
38410 static tree
38412 tree args,
38415 {
38420 {
38422 name);
38425 }
38427 {
38429 name);
38432 }
38434 {
38435 tree cst;
38439 {
38442 name);
38444 }
38447 {
38450 name);
38452 }
38455 }
38458 }
38460 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38461 struct attribute_spec.handler. */
38462 static tree
38464 tree args ATTRIBUTE_UNUSED,
38466 {
38471 {
38473 name);
38476 }
38478 /* Can combine regparm with all attributes but fastcall. */
38480 {
38482 {
38484 }
38487 }
38489 {
38491 {
38493 }
38496 }
38499 }
38501 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38502 struct attribute_spec.handler. */
38503 static tree
38505 tree args ATTRIBUTE_UNUSED,
38507 {
38510 {
38513 }
38514 else
38518 {
38520 name);
38522 }
38528 {
38530 name);
38532 }
38535 }
38537 static tree
38539 tree args ATTRIBUTE_UNUSED,
38541 {
38543 {
38545 name);
38547 }
38549 }
38551 static bool
38553 {
38557 }
38559 /* Returns an expression indicating where the this parameter is
38560 located on entry to the FUNCTION. */
38562 static rtx
38564 {
38570 {
38575 else
38578 }
38583 {
38590 {
38595 }
38596 else
38597 {
38600 {
38606 }
38607 }
38609 }
38613 }
38615 /* Determine whether x86_output_mi_thunk can succeed. */
38617 static bool
38619 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
38621 {
38622 /* 64-bit can handle anything. */
38626 /* For 32-bit, everything's fine if we have one free register. */
38630 /* Need a free register for vcall_offset. */
38634 /* Need a free register for GOT references. */
38638 /* Otherwise ok. */
38640 }
38642 /* Output the assembler code for a thunk function. THUNK_DECL is the
38643 declaration for the thunk function itself, FUNCTION is the decl for
38644 the target function. DELTA is an immediate constant offset to be
38645 added to THIS. If VCALL_OFFSET is nonzero, the word at
38646 *(*this + vcall_offset) should be added to THIS. */
38648 static void
38652 {
38659 else
38660 {
38666 else
38668 }
38672 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38673 pull it in now and let DELTA benefit. */
38677 {
38678 /* Put the this parameter into %eax. */
38681 }
38682 else
38685 /* Adjust the this parameter by a fixed constant. */
38687 {
38692 {
38694 {
38698 }
38699 }
38702 }
38704 /* Adjust the this parameter by a value stored in the vtable. */
38706 {
38716 /* Adjust the this parameter. */
38720 {
38724 }
38731 vcall_mem));
38732 else
38734 }
38736 /* If necessary, drop THIS back to its stack slot. */
38742 {
38745 ;
38746 else
38747 {
38751 }
38752 }
38753 else
38754 {
38756 ;
38757 #if TARGET_MACHO
38759 {
38762 }
38764 else
38765 {
38773 }
38774 }
38776 /* Our sibling call patterns do not allow memories, because we have no
38777 predicate that can distinguish between frame and non-frame memory.
38778 For our purposes here, we can get away with (ab)using a jump pattern,
38779 because we're going to do no optimization. */
38782 else
38783 {
38789 {
38795 }
38801 }
38804 /* Emit just enough of rest_of_compilation to get the insns emitted.
38805 Note that use_thunk calls assemble_start_function et al. */
38811 }
38813 static void
38815 {
38819 #if TARGET_MACHO
38821 #endif
38828 }
38830 int
38832 {
38844 }
38846 /* Output assembler code to FILE to increment profiler label # LABELNO
38847 for profiling a function entry. */
38848 void
38850 {
38855 {
38856 #ifndef NO_PROFILE_COUNTERS
38858 #endif
38862 else
38864 }
38866 {
38867 #ifndef NO_PROFILE_COUNTERS
38870 #endif
38872 }
38873 else
38874 {
38875 #ifndef NO_PROFILE_COUNTERS
38878 #endif
38880 }
38881 }
38883 /* We don't have exact information about the insn sizes, but we may assume
38884 quite safely that we are informed about all 1 byte insns and memory
38885 address sizes. This is enough to eliminate unnecessary padding in
38886 99% of cases. */
38888 static int
38890 {
38896 /* Discard alignments we've emit and jump instructions. */
38901 /* Important case - calls are always 5 bytes.
38902 It is common to have many calls in the row. */
38911 /* For normal instructions we rely on get_attr_length being exact,
38912 with a few exceptions. */
38914 {
38918 {
38928 /* Otherwise trust get_attr_length. */
38930 }
38935 }
38938 else
38940 }
38942 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
38944 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
38945 window. */
38947 static void
38949 {
38954 /* Look for all minimal intervals of instructions containing 4 jumps.
38955 The intervals are bounded by START and INSN. NBYTES is the total
38956 size of instructions in the interval including INSN and not including
38957 START. When the NBYTES is smaller than 16 bytes, it is possible
38958 that the end of START and INSN ends up in the same 16byte page.
38960 The smallest offset in the page INSN can start is the case where START
38961 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
38962 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
38964 Don't consider asm goto as jump, while it can contain a jump, it doesn't
38965 have to, control transfer to label(s) can be performed through other
38966 means, and also we estimate minimum length of all asm stmts as 0. */
38968 {
38972 {
38978 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
38979 already in the current 16 byte page, because otherwise
38980 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
38981 bytes to reach 16 byte boundary. */
38989 {
38991 {
38996 else
38999 }
39000 }
39002 }
39011 njumps++;
39012 else
39016 {
39021 else
39024 }
39031 {
39038 }
39039 }
39040 }
39041 #endif
39043 /* AMD Athlon works faster
39044 when RET is not destination of conditional jump or directly preceded
39045 by other jump instruction. We avoid the penalty by inserting NOP just
39046 before the RET instructions in such cases. */
39047 static void
39049 {
39050 edge e;
39051 edge_iterator ei;
39054 {
39057 rtx prev;
39067 {
39068 edge e;
39069 edge_iterator ei;
39074 {
39077 }
39078 }
39080 {
39086 /* Empty functions get branch mispredict even when
39087 the jump destination is not visible to us. */
39090 }
39092 {
39095 }
39096 }
39097 }
39099 /* Count the minimum number of instructions in BB. Return 4 if the
39100 number of instructions >= 4. */
39102 static int
39104 {
39105 rtx insn;
39108 /* Count number of instructions in this block. Return 4 if the number
39109 of instructions >= 4. */
39111 {
39112 /* Only happen in exit blocks. */
39120 {
39121 insn_count++;
39124 }
39125 }
39128 }
39131 /* Count the minimum number of instructions in code path in BB.
39132 Return 4 if the number of instructions >= 4. */
39134 static int
39136 {
39137 edge e;
39138 edge_iterator ei;
39141 /* Only bother counting instructions along paths with no
39142 more than 2 basic blocks between entry and exit. Given
39143 that BB has an edge to exit, determine if a predecessor
39144 of BB has an edge from entry. If so, compute the number
39145 of instructions in the predecessor block. If there
39146 happen to be multiple such blocks, compute the minimum. */
39149 {
39150 edge prev_e;
39151 edge_iterator prev_ei;
39154 {
39157 }
39159 {
39161 {
39166 }
39167 }
39168 }
39174 }
39176 /* Pad short function to 4 instructions. */
39178 static void
39180 {
39181 edge e;
39182 edge_iterator ei;
39185 {
39188 {
39191 /* Pad short function. */
39193 {
39196 /* Find epilogue. */
39205 /* Two NOPs count as one instruction. */
39208 }
39209 }
39210 }
39211 }
39213 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39214 the epilogue, the Windows system unwinder will apply epilogue logic and
39215 produce incorrect offsets. This can be avoided by adding a nop between
39216 the last insn that can throw and the first insn of the epilogue. */
39218 static void
39220 {
39221 edge e;
39222 edge_iterator ei;
39225 {
39228 /* Find the beginning of the epilogue. */
39235 /* We only care about preceding insns that can throw. */
39240 /* Do not separate calls from their debug information. */
39246 else
39250 }
39251 }
39253 /* Implement machine specific optimizations. We implement padding of returns
39254 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39255 static void
39257 {
39258 /* We are freeing block_for_insn in the toplev to keep compatibility
39259 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39266 {
39271 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39274 #endif
39275 }
39276 }
39278 /* Return nonzero when QImode register that must be represented via REX prefix
39279 is used. */
39280 bool
39282 {
39290 }
39292 /* Return nonzero when P points to register encoded via REX prefix.
39293 Called via for_each_rtx. */
39294 static int
39296 {
39302 }
39304 /* Return true when INSN mentions register that must be encoded using REX
39305 prefix. */
39306 bool
39308 {
39311 }
39313 /* If profitable, negate (without causing overflow) integer constant
39314 of mode MODE at location LOC. Return true in this case. */
39315 bool
39317 {
39318 HOST_WIDE_INT val;
39324 {
39326 /* DImode x86_64 constants must fit in 32 bits. */
39339 }
39341 /* Avoid overflows. */
39347 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39348 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39351 {
39354 }
39357 }
39359 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39360 optabs would emit if we didn't have TFmode patterns. */
39362 void
39364 {
39398 }
39399 \f
39400 /* AVX512F does support 64-byte integer vector operations,
39401 thus the longest vector we are faced with is V64QImode. */
39402 #define MAX_VECT_LEN 64
39404 struct expand_vec_perm_d
39405 {
39412 };
39418 /* Get a vector mode of the same size as the original but with elements
39419 twice as wide. This is only guaranteed to apply to integral vectors. */
39423 {
39424 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39429 }
39431 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39432 fill target with val via vec_duplicate. */
39434 static bool
39436 {
39440 /* First attempt to recognize VAL as-is. */
39444 {
39445 rtx seq;
39446 /* If that fails, force VAL into a register. */
39457 }
39459 }
39461 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39462 with all elements equal to VAR. Return true if successful. */
39464 static bool
39467 {
39471 {
39476 /* FALLTHRU */
39496 {
39497 rtx x;
39504 }
39514 {
39518 permute:
39526 /* Extend to SImode using a paradoxical SUBREG. */
39530 /* Insert the SImode value as low element of a V4SImode vector. */
39539 }
39547 widen:
39548 /* Replicate the value once into the next wider mode and recurse. */
39549 {
39551 rtx x;
39568 }
39572 {
39581 }
39586 }
39587 }
39589 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39590 whose ONE_VAR element is VAR, and other elements are zero. Return true
39591 if successful. */
39593 static bool
39596 {
39598 rtx new_target;
39603 {
39605 /* For SSE4.1, we normally use vector set. But if the second
39606 element is zero and inter-unit moves are OK, we use movq
39607 instead. */
39609 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39631 /* Use ix86_expand_vector_set in 64bit mode only. */
39636 }
39639 {
39644 }
39647 {
39652 /* FALLTHRU */
39667 else
39674 {
39675 /* We need to shuffle the value to the correct position, so
39676 create a new pseudo to store the intermediate result. */
39678 /* With SSE2, we can use the integer shuffle insns. */
39680 {
39682 const1_rtx,
39689 }
39691 /* Otherwise convert the intermediate result to V4SFmode and
39692 use the SSE1 shuffle instructions. */
39694 {
39697 }
39698 else
39702 const1_rtx,
39711 }
39726 widen:
39730 /* Zero extend the variable element to SImode and recurse. */
39743 }
39744 }
39746 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39747 consisting of the values in VALS. It is known that all elements
39748 except ONE_VAR are constants. Return true if successful. */
39750 static bool
39753 {
39763 {
39768 /* For the two element vectors, it's just as easy to use
39769 the general case. */
39773 /* Use ix86_expand_vector_set in 64bit mode only. */
39795 widen:
39796 /* There's no way to set one QImode entry easily. Combine
39797 the variable value with its adjacent constant value, and
39798 promote to an HImode set. */
39801 {
39806 }
39807 else
39808 {
39811 }
39825 }
39830 }
39832 /* A subroutine of ix86_expand_vector_init_general. Use vector
39833 concatenate to handle the most general case: all values variable,
39834 and none identical. */
39836 static void
39839 {
39842 rtvec v;
39846 {
39849 {
39894 }
39907 {
39922 }
39927 {
39946 }
39951 {
39964 }
39967 half:
39968 /* FIXME: We process inputs backward to help RA. PR 36222. */
39972 {
39977 }
39981 {
39985 {
39989 }
39992 {
39996 }
39999 }
40001 {
40004 {
40008 }
40011 }
40012 else
40018 }
40019 }
40021 /* A subroutine of ix86_expand_vector_init_general. Use vector
40022 interleave to handle the most general case: all values variable,
40023 and none identical. */
40025 static void
40028 {
40037 {
40058 }
40061 {
40062 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40066 /* Insert the SImode value as low element of V4SImode vector. */
40070 op0),
40072 const1_rtx);
40075 /* Cast the V4SImode vector back to a vector in orignal mode. */
40079 /* Load even elements into the second position. */
40083 const1_rtx));
40085 /* Cast vector to FIRST_IMODE vector. */
40088 }
40090 /* Interleave low FIRST_IMODE vectors. */
40092 {
40096 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40099 }
40101 /* Interleave low SECOND_IMODE vectors. */
40103 {
40106 {
40111 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40112 vector. */
40115 }
40118 /* FALLTHRU */
40125 /* Cast the SECOND_IMODE vector back to a vector on original
40126 mode. */
40133 }
40134 }
40136 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40137 all values variable, and none identical. */
40139 static void
40142 {
40148 {
40153 /* FALLTHRU */
40181 half:
40198 /* FALLTHRU */
40204 /* Don't use ix86_expand_vector_init_interleave if we can't
40205 move from GPR to SSE register directly. */
40221 }
40223 {
40235 {
40239 {
40245 else
40246 {
40251 }
40252 }
40255 }
40260 {
40266 }
40268 {
40274 }
40275 else
40277 }
40278 }
40280 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40281 instructions unless MMX_OK is true. */
40283 void
40285 {
40292 rtx x;
40295 {
40305 }
40307 /* Constants are best loaded from the constant pool. */
40309 {
40312 }
40314 /* If all values are identical, broadcast the value. */
40320 /* Values where only one field is non-constant are best loaded from
40321 the pool and overwritten via move later. */
40323 {
40327 one_var))
40332 }
40335 }
40337 void
40339 {
40344 rtx tmp;
40346 = {
40353 };
40355 = {
40362 };
40366 {
40370 {
40375 else
40379 }
40391 else
40397 {
40400 /* For the two element vectors, we implement a VEC_CONCAT with
40401 the extraction of the other element. */
40408 else
40413 }
40422 {
40428 /* tmp = target = A B C D */
40430 /* target = A A B B */
40432 /* target = X A B B */
40434 /* target = A X C D */
40441 /* tmp = target = A B C D */
40443 /* tmp = X B C D */
40445 /* target = A B X D */
40452 /* tmp = target = A B C D */
40454 /* tmp = X B C D */
40456 /* target = A B X D */
40464 }
40472 /* Element 0 handled by vec_merge below. */
40474 {
40477 }
40480 {
40481 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40482 store into element 0, then shuffle them back. */
40499 }
40500 else
40501 {
40502 /* For SSE1, we have to reuse the V4SF code. */
40506 }
40559 half:
40560 /* Compute offset. */
40566 /* Extract the half. */
40570 /* Put val in tmp at elt. */
40573 /* Put it back. */
40579 }
40582 {
40586 }
40587 else
40588 {
40597 }
40598 }
40600 void
40602 {
40606 rtx tmp;
40609 {
40614 /* FALLTHRU */
40627 {
40647 }
40659 {
40661 {
40681 }
40685 }
40686 else
40687 {
40688 /* For SSE1, we have to reuse the V4SF code. */
40692 }
40708 {
40712 else
40716 }
40721 {
40725 else
40729 }
40734 {
40738 else
40742 }
40747 {
40751 else
40755 }
40760 {
40764 else
40768 }
40773 {
40777 else
40781 }
40788 else
40797 else
40806 else
40815 else
40821 /* ??? Could extract the appropriate HImode element and shift. */
40824 }
40827 {
40831 /* Let the rtl optimizers know about the zero extension performed. */
40833 {
40836 }
40839 }
40840 else
40841 {
40848 }
40849 }
40851 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
40852 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
40853 The upper bits of DEST are undefined, though they shouldn't cause
40854 exceptions (some bits from src or all zeros are ok). */
40856 static void
40858 {
40861 {
40865 else
40883 else
40890 else
40898 {
40903 const1_rtx);
40904 }
40905 else
40906 {
40910 }
40930 else
40952 }
40956 }
40958 /* Expand a vector reduction. FN is the binary pattern to reduce;
40959 DEST is the destination; IN is the input vector. */
40961 void
40963 {
40968 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
40972 {
40975 }
40980 {
40985 else
40989 }
40990 }
40991 \f
40992 /* Target hook for scalar_mode_supported_p. */
40993 static bool
40995 {
41000 else
41002 }
41004 /* Implements target hook vector_mode_supported_p. */
41005 static bool
41007 {
41021 }
41023 /* Target hook for c_mode_for_suffix. */
41024 static enum machine_mode
41026 {
41033 }
41035 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41037 We do this in the new i386 backend to maintain source compatibility
41038 with the old cc0-based compiler. */
41040 static tree
41042 tree inputs ATTRIBUTE_UNUSED,
41043 tree clobbers)
41044 {
41046 clobbers);
41048 clobbers);
41050 }
41052 /* Implements target vector targetm.asm.encode_section_info. */
41054 static void ATTRIBUTE_UNUSED
41056 {
41063 }
41065 /* Worker function for REVERSE_CONDITION. */
41067 enum rtx_code
41069 {
41073 }
41075 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41076 to OPERANDS[0]. */
41080 {
41082 {
41085 {
41089 }
41093 }
41095 {
41099 else
41100 {
41101 /* There is no non-popping store to memory for XFmode.
41102 So if we need one, follow the store with a load. */
41105 else
41107 }
41108 }
41109 else
41111 }
41113 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41114 FP status register is set. */
41116 void
41118 {
41120 rtx temp;
41125 {
41130 }
41131 else
41132 {
41137 }
41141 pc_rtx);
41146 }
41148 /* Output code to perform a log1p XFmode calculation. */
41151 {
41157 rtx test;
41163 XFmode));
41177 }
41179 /* Emit code for round calculation. */
41181 {
41188 rtx insn;
41193 {
41205 }
41208 {
41229 }
41237 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41239 /* scratch = fxam(op1) */
41242 UNSPEC_FXAM)));
41243 /* e1 = fabs(op1) */
41246 /* e2 = e1 + 0.5 */
41251 /* res = floor(e2) */
41253 {
41258 }
41259 else
41263 {
41266 {
41273 UNSPEC_TRUNC_NOOP)));
41274 }
41290 }
41292 /* flags = signbit(a) */
41295 /* if (flags) then res = -res */
41299 pc_rtx);
41310 }
41312 /* Output code to perform a Newton-Rhapson approximation of a single precision
41313 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41316 {
41324 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41328 /* x0 = rcp(b) estimate */
41332 UNSPEC_RCP14)));
41333 else
41336 UNSPEC_RCP)));
41338 /* e0 = x0 * b */
41342 /* e0 = x0 * e0 */
41346 /* e1 = x0 + x0 */
41350 /* x1 = e1 - e0 */
41354 /* res = a * x1 */
41357 }
41359 /* Output code to perform a Newton-Rhapson approximation of a
41360 single precision floating point [reciprocal] square root. */
41364 {
41366 REAL_VALUE_TYPE r;
41383 {
41386 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41389 }
41391 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41392 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41396 /* x0 = rsqrt(a) estimate */
41399 unspec)));
41401 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41403 {
41411 /* Handle masked compare. */
41413 {
41415 /* Imm value 0x4 corresponds to not-equal comparison. */
41418 }
41419 else
41420 {
41426 }
41427 }
41429 /* e0 = x0 * a */
41432 /* e1 = e0 * x0 */
41436 /* e2 = e1 - 3. */
41443 /* e3 = -.5 * x0 */
41446 else
41447 /* e3 = -.5 * e0 */
41450 /* ret = e2 * e3 */
41453 }
41455 #ifdef TARGET_SOLARIS
41456 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41458 static void
41460 tree decl)
41461 {
41462 /* With Binutils 2.15, the "@unwind" marker must be specified on
41463 every occurrence of the ".eh_frame" section, not just the first
41464 one. */
41467 {
41471 }
41473 #ifndef USE_GAS
41475 {
41478 }
41479 #endif
41482 }
41485 /* Return the mangling of TYPE if it is an extended fundamental type. */
41489 {
41497 {
41499 /* __float128 is "g". */
41502 /* "long double" or __float80 is "e". */
41506 }
41507 }
41509 /* For 32-bit code we can save PIC register setup by using
41510 __stack_chk_fail_local hidden function instead of calling
41511 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41512 register, so it is better to call __stack_chk_fail directly. */
41514 static tree ATTRIBUTE_UNUSED
41516 {
41517 return TARGET_64BIT
41520 }
41522 /* Select a format to encode pointers in exception handling data. CODE
41523 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41524 true if the symbol may be affected by dynamic relocations.
41526 ??? All x86 object file formats are capable of representing this.
41527 After all, the relocation needed is the same as for the call insn.
41528 Whether or not a particular assembler allows us to enter such, I
41529 guess we'll have to see. */
41530 int
41532 {
41534 {
41541 }
41546 }
41547 \f
41548 /* Expand copysign from SIGN to the positive value ABS_VALUE
41549 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41550 the sign-bit. */
41551 static void
41553 {
41557 {
41564 else
41569 {
41570 /* We need to generate a scalar mode mask in this case. */
41575 }
41576 }
41577 else
41583 }
41585 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41586 mask for masking out the sign-bit is stored in *SMASK, if that is
41587 non-null. */
41588 static rtx
41590 {
41599 else
41603 {
41604 /* We need to generate a scalar mode mask in this case. */
41609 }
41617 }
41619 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41620 swapping the operands if SWAP_OPERANDS is true. The expanded
41621 code is a forward jump to a newly created label in case the
41622 comparison is true. The generated label rtx is returned. */
41623 static rtx
41626 {
41631 {
41635 }
41648 }
41650 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41651 using comparison code CODE. Operands are swapped for the comparison if
41652 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41653 static rtx
41656 {
41662 {
41666 }
41673 }
41675 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41676 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41677 static rtx
41679 {
41680 REAL_VALUE_TYPE TWO52r;
41681 rtx TWO52;
41688 }
41690 /* Expand SSE sequence for computing lround from OP1 storing
41691 into OP0. */
41692 void
41694 {
41695 /* C code for the stuff we're doing below:
41696 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41697 return (long)tmp;
41698 */
41702 rtx adj;
41704 /* load nextafter (0.5, 0.0) */
41709 /* adj = copysign (0.5, op1) */
41713 /* adj = op1 + adj */
41716 /* op0 = (imode)adj */
41718 }
41720 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41721 into OPERAND0. */
41722 void
41724 {
41725 /* C code for the stuff we're doing below (for do_floor):
41726 xi = (long)op1;
41727 xi -= (double)xi > op1 ? 1 : 0;
41728 return xi;
41729 */
41734 /* reg = (long)op1 */
41738 /* freg = (double)reg */
41742 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41753 }
41755 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41756 result in OPERAND0. */
41757 void
41759 {
41760 /* C code for the stuff we're doing below:
41761 xa = fabs (operand1);
41762 if (!isless (xa, 2**52))
41763 return operand1;
41764 xa = xa + 2**52 - 2**52;
41765 return copysign (xa, operand1);
41766 */
41773 /* xa = abs (operand1) */
41776 /* if (!isless (xa, TWO52)) goto label; */
41789 }
41791 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41792 into OPERAND0. */
41793 void
41795 {
41796 /* C code for the stuff we expand below.
41797 double xa = fabs (x), x2;
41798 if (!isless (xa, TWO52))
41799 return x;
41800 xa = xa + TWO52 - TWO52;
41801 x2 = copysign (xa, x);
41802 Compensate. Floor:
41803 if (x2 > x)
41804 x2 -= 1;
41805 Compensate. Ceil:
41806 if (x2 < x)
41807 x2 -= -1;
41808 return x2;
41809 */
41815 /* Temporary for holding the result, initialized to the input
41816 operand to ease control flow. */
41820 /* xa = abs (operand1) */
41823 /* if (!isless (xa, TWO52)) goto label; */
41826 /* xa = xa + TWO52 - TWO52; */
41830 /* xa = copysign (xa, operand1) */
41833 /* generate 1.0 or -1.0 */
41838 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41842 /* We always need to subtract here to preserve signed zero. */
41851 }
41853 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41854 into OPERAND0. */
41855 void
41857 {
41858 /* C code for the stuff we expand below.
41859 double xa = fabs (x), x2;
41860 if (!isless (xa, TWO52))
41861 return x;
41862 x2 = (double)(long)x;
41863 Compensate. Floor:
41864 if (x2 > x)
41865 x2 -= 1;
41866 Compensate. Ceil:
41867 if (x2 < x)
41868 x2 += 1;
41869 if (HONOR_SIGNED_ZEROS (mode))
41870 return copysign (x2, x);
41871 return x2;
41872 */
41878 /* Temporary for holding the result, initialized to the input
41879 operand to ease control flow. */
41883 /* xa = abs (operand1) */
41886 /* if (!isless (xa, TWO52)) goto label; */
41889 /* xa = (double)(long)x */
41894 /* generate 1.0 */
41897 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41912 }
41914 /* Expand SSE sequence for computing round from OPERAND1 storing
41915 into OPERAND0. Sequence that works without relying on DImode truncation
41916 via cvttsd2siq that is only available on 64bit targets. */
41917 void
41919 {
41920 /* C code for the stuff we expand below.
41921 double xa = fabs (x), xa2, x2;
41922 if (!isless (xa, TWO52))
41923 return x;
41924 Using the absolute value and copying back sign makes
41925 -0.0 -> -0.0 correct.
41926 xa2 = xa + TWO52 - TWO52;
41927 Compensate.
41928 dxa = xa2 - xa;
41929 if (dxa <= -0.5)
41930 xa2 += 1;
41931 else if (dxa > 0.5)
41932 xa2 -= 1;
41933 x2 = copysign (xa2, x);
41934 return x2;
41935 */
41941 /* Temporary for holding the result, initialized to the input
41942 operand to ease control flow. */
41946 /* xa = abs (operand1) */
41949 /* if (!isless (xa, TWO52)) goto label; */
41952 /* xa2 = xa + TWO52 - TWO52; */
41956 /* dxa = xa2 - xa; */
41959 /* generate 0.5, 1.0 and -0.5 */
41965 /* Compensate. */
41967 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
41972 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
41978 /* res = copysign (xa2, operand1) */
41985 }
41987 /* Expand SSE sequence for computing trunc from OPERAND1 storing
41988 into OPERAND0. */
41989 void
41991 {
41992 /* C code for SSE variant we expand below.
41993 double xa = fabs (x), x2;
41994 if (!isless (xa, TWO52))
41995 return x;
41996 x2 = (double)(long)x;
41997 if (HONOR_SIGNED_ZEROS (mode))
41998 return copysign (x2, x);
41999 return x2;
42000 */
42006 /* Temporary for holding the result, initialized to the input
42007 operand to ease control flow. */
42011 /* xa = abs (operand1) */
42014 /* if (!isless (xa, TWO52)) goto label; */
42017 /* x = (double)(long)x */
42029 }
42031 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42032 into OPERAND0. */
42033 void
42035 {
42039 /* C code for SSE variant we expand below.
42040 double xa = fabs (x), x2;
42041 if (!isless (xa, TWO52))
42042 return x;
42043 xa2 = xa + TWO52 - TWO52;
42044 Compensate:
42045 if (xa2 > xa)
42046 xa2 -= 1.0;
42047 x2 = copysign (xa2, x);
42048 return x2;
42049 */
42053 /* Temporary for holding the result, initialized to the input
42054 operand to ease control flow. */
42058 /* xa = abs (operand1) */
42061 /* if (!isless (xa, TWO52)) goto label; */
42064 /* res = xa + TWO52 - TWO52; */
42069 /* generate 1.0 */
42072 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42080 /* res = copysign (res, operand1) */
42087 }
42089 /* Expand SSE sequence for computing round from OPERAND1 storing
42090 into OPERAND0. */
42091 void
42093 {
42094 /* C code for the stuff we're doing below:
42095 double xa = fabs (x);
42096 if (!isless (xa, TWO52))
42097 return x;
42098 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42099 return copysign (xa, x);
42100 */
42106 /* Temporary for holding the result, initialized to the input
42107 operand to ease control flow. */
42115 /* load nextafter (0.5, 0.0) */
42120 /* xa = xa + 0.5 */
42124 /* xa = (double)(int64_t)xa */
42129 /* res = copysign (xa, operand1) */
42136 }
42138 /* Expand SSE sequence for computing round
42139 from OP1 storing into OP0 using sse4 round insn. */
42140 void
42142 {
42151 {
42162 }
42164 /* round (a) = trunc (a + copysign (0.5, a)) */
42166 /* load nextafter (0.5, 0.0) */
42172 /* e1 = copysign (0.5, op1) */
42176 /* e2 = op1 + e1 */
42179 /* res = trunc (e2) */
42184 }
42185 \f
42187 /* Table of valid machine attributes. */
42189 {
42190 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42191 affects_type_identity } */
42192 /* Stdcall attribute says callee is responsible for popping arguments
42193 if they are not variable. */
42196 /* Fastcall attribute says callee is responsible for popping arguments
42197 if they are not variable. */
42200 /* Thiscall attribute says callee is responsible for popping arguments
42201 if they are not variable. */
42204 /* Cdecl attribute says the callee is a normal C declaration */
42207 /* Regparm attribute specifies how many integer arguments are to be
42208 passed in registers. */
42211 /* Sseregparm attribute says we are using x86_64 calling conventions
42212 for FP arguments. */
42215 /* The transactional memory builtins are implicitly regparm or fastcall
42216 depending on the ABI. Override the generic do-nothing attribute that
42217 these builtins were declared with. */
42220 /* force_align_arg_pointer says this function realigns the stack at entry. */
42223 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42228 #endif
42233 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42234 SUBTARGET_ATTRIBUTE_TABLE,
42235 #endif
42236 /* ms_abi and sysv_abi calling convention function attributes. */
42243 /* End element. */
42245 };
42247 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42248 static int
42250 tree vectype,
42252 {
42256 {
42301 }
42302 }
42304 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42305 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42306 insn every time. */
42310 /* Initialize vselect_insn. */
42312 static void
42314 {
42316 rtx x;
42327 }
42329 /* Construct (set target (vec_select op0 (parallel perm))) and
42330 return true if that's a valid instruction in the active ISA. */
42332 static bool
42335 {
42361 }
42363 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42365 static bool
42369 {
42371 rtx x;
42386 }
42388 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42389 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42391 static bool
42393 {
42402 ;
42404 ;
42406 ;
42407 else
42410 /* This is a blend, not a permute. Elements must stay in their
42411 respective lanes. */
42413 {
42417 }
42422 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42423 decision should be extracted elsewhere, so that we only try that
42424 sequence once all budget==3 options have been tried. */
42431 {
42455 /* See if bytes move in pairs so we can use pblendw with
42456 an immediate argument, rather than pblendvb with a vector
42457 argument. */
42460 {
42461 use_pblendvb:
42465 finish_pblendvb:
42471 else
42476 }
42481 /* FALLTHRU */
42483 do_subreg:
42490 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42494 /* See if bytes move in quadruplets. If yes, vpblendd
42495 with immediate can be used. */
42500 {
42501 /* See if bytes move the same in both lanes. If yes,
42502 vpblendw with immediate can be used. */
42507 /* Use vpblendw. */
42512 }
42514 /* Use vpblendd. */
42521 /* See if words move in pairs. If yes, vpblendd can be used. */
42526 {
42527 /* See if words move the same in both lanes. If not,
42528 vpblendvb must be used. */
42531 {
42532 /* Use vpblendvb. */
42542 }
42544 /* Use vpblendw. */
42548 }
42550 /* Use vpblendd. */
42557 /* Use vpblendd. */
42565 }
42567 /* This matches five different patterns with the different modes. */
42575 }
42577 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42578 in terms of the variable form of vpermilps.
42580 Note that we will have already failed the immediate input vpermilps,
42581 which requires that the high and low part shuffle be identical; the
42582 variable form doesn't require that. */
42584 static bool
42586 {
42593 /* We can only permute within the 128-bit lane. */
42595 {
42599 }
42605 {
42608 /* Within each 128-bit lane, the elements of op0 are numbered
42609 from 0 and the elements of op1 are numbered from 4. */
42616 }
42623 }
42625 /* Return true if permutation D can be performed as VMODE permutation
42626 instead. */
42628 static bool
42630 {
42645 else
42651 }
42653 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42654 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42656 static bool
42658 {
42667 {
42669 {
42672 {
42676 /* Use vperm2i128 insn. The pattern uses
42677 V4DImode instead of V2TImode. */
42690 }
42692 }
42693 }
42694 else
42695 {
42697 {
42700 }
42702 {
42706 /* V4DImode should be already handled through
42707 expand_vselect by vpermq instruction. */
42714 {
42715 /* First see if vpermq can be used for
42716 V8SImode/V16HImode/V32QImode. */
42718 {
42726 {
42730 }
42732 }
42734 /* Next see if vpermd can be used. */
42737 }
42738 /* Or if vpermps can be used. */
42743 {
42744 /* vpshufb only works intra lanes, it is not
42745 possible to shuffle bytes in between the lanes. */
42749 }
42750 }
42751 else
42753 }
42761 else
42762 {
42768 else
42772 {
42776 }
42777 }
42788 {
42795 else
42797 }
42798 else
42799 {
42802 }
42807 }
42809 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
42810 in a single instruction. */
42812 static bool
42814 {
42818 /* Check plain VEC_SELECT first, because AVX has instructions that could
42819 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
42820 input where SEL+CONCAT may not. */
42822 {
42828 {
42834 }
42837 {
42841 }
42843 {
42844 /* Use vpbroadcast{b,w,d}. */
42847 {
42866 /* For other modes prefer other shuffles this function creates. */
42868 }
42870 {
42874 }
42875 }
42880 /* There are plenty of patterns in sse.md that are written for
42881 SEL+CONCAT and are not replicated for a single op. Perhaps
42882 that should be changed, to avoid the nastiness here. */
42884 /* Recognize interleave style patterns, which means incrementing
42885 every other permutation operand. */
42887 {
42890 }
42895 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
42897 {
42899 {
42904 }
42909 }
42910 }
42912 /* Finally, try the fully general two operand permute. */
42917 /* Recognize interleave style patterns with reversed operands. */
42919 {
42921 {
42925 else
42928 }
42933 }
42935 /* Try the SSE4.1 blend variable merge instructions. */
42939 /* Try one of the AVX vpermil variable permutations. */
42943 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
42944 vpshufb, vpermd, vpermps or vpermq variable permutation. */
42948 /* Try the AVX512F vpermi2 instructions. */
42962 }
42964 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42965 in terms of a pair of pshuflw + pshufhw instructions. */
42967 static bool
42969 {
42977 /* The two permutations only operate in 64-bit lanes. */
42988 /* Emit the pshuflw. */
42995 /* Emit the pshufhw. */
43003 }
43005 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43006 the permutation using the SSSE3 palignr instruction. This succeeds
43007 when all of the elements in PERM fit within one vector and we merely
43008 need to shift them down so that a single vector permutation has a
43009 chance to succeed. */
43011 static bool
43013 {
43020 /* Even with AVX, palignr only operates on 128-bit vectors. */
43026 {
43032 }
43036 /* Given that we have SSSE3, we know we'll be able to implement the
43037 single operand permutation after the palignr with pshufb. */
43052 {
43057 }
43059 /* Test for the degenerate case where the alignment by itself
43060 produces the desired permutation. */
43062 {
43065 }
43071 }
43075 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43076 a two vector permutation into a single vector permutation by using
43077 an interleave operation to merge the vectors. */
43079 static bool
43081 {
43086 rtx seq;
43090 {
43093 }
43095 {
43098 /* For 32-byte modes allow even d->one_operand_p.
43099 The lack of cross-lane shuffling in some instructions
43100 might prevent a single insn shuffle. */
43103 /* If expand_vec_perm_interleave3 can expand this into
43104 a 3 insn sequence, give up and let it be expanded as
43105 3 insn sequence. While that is one insn longer,
43106 it doesn't need a memory operand and in the common
43107 case that both interleave low and high permutations
43108 with the same operands are adjacent needs 4 insns
43109 for both after CSE. */
43112 }
43113 else
43116 /* Examine from whence the elements come. */
43125 {
43128 /* Split the two input vectors into 4 halves. */
43134 /* If the elements from the low halves use interleave low, and similarly
43135 for interleave high. If the elements are from mis-matched halves, we
43136 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43138 {
43139 /* punpckl* */
43141 {
43146 }
43149 }
43151 {
43152 /* punpckh* */
43154 {
43159 }
43162 }
43164 {
43165 /* shufps */
43167 {
43172 }
43174 {
43175 /* shufpd */
43180 }
43181 }
43183 {
43184 /* shufps */
43186 {
43191 }
43193 {
43194 /* shufpd */
43199 }
43200 }
43201 else
43203 }
43204 else
43205 {
43210 /* Split the two input vectors into 8 quarters. */
43216 {
43219 }
43222 {
43226 }
43228 {
43231 }
43234 {
43236 {
43237 /* Attempt to increase the likelihood that dfinal
43238 shuffle will be intra-lane. */
43242 }
43244 /* vperm2f128 or vperm2i128. */
43246 {
43251 }
43256 {
43260 {
43263 }
43264 }
43265 }
43270 {
43271 /* vpunpckl* */
43273 {
43282 }
43283 }
43286 {
43287 /* vpunpckh* */
43289 {
43298 }
43299 }
43300 else
43302 }
43304 /* Use the remapping array set up above to move the elements from their
43305 swizzled locations into their final destinations. */
43308 {
43311 /* If same_halves is true, both halves of the remapped vector are the
43312 same. Avoid cross-lane accesses if possible. */
43314 {
43317 }
43318 else
43320 }
43322 {
43325 }
43329 /* Test if the final remap can be done with a single insn. For V4SFmode or
43330 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43343 {
43346 }
43353 }
43355 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43356 a single vector cross-lane permutation into vpermq followed
43357 by any of the single insn permutations. */
43359 static bool
43361 {
43375 {
43378 }
43381 {
43386 }
43399 {
43406 }
43413 {
43418 ;
43421 else
43423 }
43432 }
43434 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43435 a vector permutation using two instructions, vperm2f128 resp.
43436 vperm2i128 followed by any single in-lane permutation. */
43438 static bool
43440 {
43454 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43455 immediate. For perm < 16 the second permutation uses
43456 d->op0 as first operand, for perm >= 16 it uses d->op1
43457 as first operand. The second operand is the result of
43458 vperm2[fi]128. */
43460 {
43461 /* Ignore permutations which do not move anything cross-lane. */
43463 {
43464 /* The second shuffle for e.g. V4DFmode has
43465 0123 and ABCD operands.
43466 Ignore AB23, as 23 is already in the second lane
43467 of the first operand. */
43469 /* And 01CD, as 01 is in the first lane of the first
43470 operand. */
43472 /* And 4567, as then the vperm2[fi]128 doesn't change
43473 anything on the original 4567 second operand. */
43475 }
43476 else
43477 {
43478 /* The second shuffle for e.g. V4DFmode has
43479 4567 and ABCD operands.
43480 Ignore AB67, as 67 is already in the second lane
43481 of the first operand. */
43483 /* And 45CD, as 45 is in the first lane of the first
43484 operand. */
43486 /* And 0123, as then the vperm2[fi]128 doesn't change
43487 anything on the original 0123 first operand. */
43489 }
43492 {
43498 else
43500 }
43503 {
43507 }
43508 else
43512 {
43516 /* Found a usable second shuffle. dfirst will be
43517 vperm2f128 on d->op0 and d->op1. */
43528 /* And dsecond is some single insn shuffle, taking
43529 d->op0 and result of vperm2f128 (if perm < 16) or
43530 d->op1 and result of vperm2f128 (otherwise). */
43539 }
43541 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43544 }
43547 }
43549 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43550 a two vector permutation using 2 intra-lane interleave insns
43551 and cross-lane shuffle for 32-byte vectors. */
43553 static bool
43555 {
43562 ;
43564 ;
43565 else
43580 {
43584 else
43590 else
43596 else
43602 else
43608 else
43614 else
43619 }
43623 }
43625 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43626 a single vector permutation using a single intra-lane vector
43627 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43628 the non-swapped and swapped vectors together. */
43630 static bool
43632 {
43635 rtx seq;
43640 || TARGET_AVX2
43649 {
43656 }
43691 }
43693 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43694 permutation using two vperm2f128, followed by a vshufpd insn blending
43695 the two vectors together. */
43697 static bool
43699 {
43742 }
43744 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
43745 permutation with two pshufb insns and an ior. We should have already
43746 failed all two instruction sequences. */
43748 static bool
43750 {
43764 /* Generate two permutation masks. If the required element is within
43765 the given vector it is shuffled into the proper lane. If the required
43766 element is in the other vector, force a zero into the lane by setting
43767 bit 7 in the permutation mask. */
43770 {
43777 {
43780 }
43781 }
43805 }
43807 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
43808 with two vpshufb insns, vpermq and vpor. We should have already failed
43809 all two or three instruction sequences. */
43811 static bool
43813 {
43828 /* Generate two permutation masks. If the required element is within
43829 the same lane, it is shuffled in. If the required element from the
43830 other lane, force a zero by setting bit 7 in the permutation mask.
43831 In the other mask the mask has non-negative elements if element
43832 is requested from the other lane, but also moved to the other lane,
43833 so that the result of vpshufb can have the two V2TImode halves
43834 swapped. */
43837 {
43842 {
43845 }
43846 }
43855 /* Swap the 128-byte lanes of h into hp. */
43859 const1_rtx));
43876 }
43878 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
43879 and extract-odd permutations of two V32QImode and V16QImode operand
43880 with two vpshufb insns, vpor and vpermq. We should have already
43881 failed all two or three instruction sequences. */
43883 static bool
43885 {
43904 /* Generate two permutation masks. In the first permutation mask
43905 the first quarter will contain indexes for the first half
43906 of the op0, the second quarter will contain bit 7 set, third quarter
43907 will contain indexes for the second half of the op0 and the
43908 last quarter bit 7 set. In the second permutation mask
43909 the first quarter will contain bit 7 set, the second quarter
43910 indexes for the first half of the op1, the third quarter bit 7 set
43911 and last quarter indexes for the second half of the op1.
43912 I.e. the first mask e.g. for V32QImode extract even will be:
43913 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
43914 (all values masked with 0xf except for -128) and second mask
43915 for extract even will be
43916 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
43919 {
43925 {
43928 }
43929 }
43948 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
43956 }
43958 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
43959 and extract-odd permutations. */
43961 static bool
43963 {
43967 {
43974 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
43978 /* Now an unpck[lh]pd will produce the result required. */
43981 else
43987 {
43996 /* Shuffle within the 128-bit lanes to produce:
43997 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44001 /* Shuffle the lanes around to produce:
44002 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44006 /* Shuffle within the 128-bit lanes to produce:
44007 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44010 /* Shuffle within the 128-bit lanes to produce:
44011 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44014 /* Shuffle the lanes around to produce:
44015 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44018 }
44025 /* These are always directly implementable by expand_vec_perm_1. */
44031 else
44032 {
44035 /* We need 2*log2(N)-1 operations to achieve odd/even
44036 with interleave. */
44045 else
44048 }
44054 else
44055 {
44069 else
44072 }
44081 {
44086 else
44091 {
44096 }
44098 }
44106 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44110 /* Now an vpunpck[lh]qdq will produce the result required. */
44113 else
44120 {
44125 else
44130 {
44135 }
44137 }
44148 /* Shuffle the lanes around into
44149 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44157 /* Swap the 2nd and 3rd position in each lane into
44158 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44164 /* Now an vpunpck[lh]qdq will produce
44165 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44169 else
44178 }
44181 }
44183 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44184 extract-even and extract-odd permutations. */
44186 static bool
44188 {
44200 }
44202 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44203 permutations. We assume that expand_vec_perm_1 has already failed. */
44205 static bool
44207 {
44215 {
44218 /* These are special-cased in sse.md so that we can optionally
44219 use the vbroadcast instruction. They expand to two insns
44220 if the input happens to be in a register. */
44227 /* These are always implementable using standard shuffle patterns. */
44232 /* These can be implemented via interleave. We save one insn by
44233 stopping once we have promoted to V4SImode and then use pshufd. */
44236 do
44237 {
44238 rtx dest;
44244 {
44248 }
44255 }
44270 /* For AVX2 broadcasts of the first element vpbroadcast* or
44271 vpermq should be used by expand_vec_perm_1. */
44277 }
44278 }
44280 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44281 broadcast permutations. */
44283 static bool
44285 {
44297 }
44299 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44300 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44301 all the shorter instruction sequences. */
44303 static bool
44305 {
44321 /* Generate 4 permutation masks. If the required element is within
44322 the same lane, it is shuffled in. If the required element from the
44323 other lane, force a zero by setting bit 7 in the permutation mask.
44324 In the other mask the mask has non-negative elements if element
44325 is requested from the other lane, but also moved to the other lane,
44326 so that the result of vpshufb can have the two V2TImode halves
44327 swapped. */
44330 {
44335 }
44341 {
44349 }
44352 {
44354 {
44357 }
44364 }
44366 /* Swap the 128-byte lanes of h[X]. */
44368 {
44374 const1_rtx));
44376 }
44379 {
44381 {
44384 }
44390 }
44393 {
44395 {
44399 }
44402 }
44412 }
44414 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44415 With all of the interface bits taken care of, perform the expansion
44416 in D and return true on success. */
44418 static bool
44420 {
44421 /* Try a single instruction expansion. */
44425 /* Try sequences of two instructions. */
44445 /* Try sequences of three instructions. */
44459 /* Try sequences of four instructions. */
44467 /* ??? Look for narrow permutations whose element orderings would
44468 allow the promotion to a wider mode. */
44470 /* ??? Look for sequences of interleave or a wider permute that place
44471 the data into the correct lanes for a half-vector shuffle like
44472 pshuf[lh]w or vpermilps. */
44474 /* ??? Look for sequences of interleave that produce the desired results.
44475 The combinatorics of punpck[lh] get pretty ugly... */
44480 /* Even longer sequences. */
44485 }
44487 /* If a permutation only uses one operand, make it clear. Returns true
44488 if the permutation references both operands. */
44490 static bool
44492 {
44500 {
44506 {
44509 }
44510 /* The elements of PERM do not suggest that only the first operand
44511 is used, but both operands are identical. Allow easier matching
44512 of the permutation by folding the permutation into the single
44513 input vector. */
44514 /* FALLTHRU */
44525 }
44528 }
44530 bool
44532 {
44537 rtx sel;
44554 {
44559 }
44566 /* If the selector says both arguments are needed, but the operands are the
44567 same, the above tried to expand with one_operand_p and flattened selector.
44568 If that didn't work, retry without one_operand_p; we succeeded with that
44569 during testing. */
44571 {
44575 }
44578 }
44580 /* Implement targetm.vectorize.vec_perm_const_ok. */
44582 static bool
44585 {
44594 /* Given sufficient ISA support we can just return true here
44595 for selected vector modes. */
44598 /* All implementable with a single vpermi2 insn. */
44601 {
44602 /* All implementable with a single vpperm insn. */
44605 /* All implementable with 2 pshufb + 1 ior. */
44608 /* All implementable with shufpd or unpck[lh]pd. */
44611 }
44613 /* Extract the values from the vector CST into the permutation
44614 array in D. */
44617 {
44621 }
44623 /* For all elements from second vector, fold the elements to first. */
44628 /* Check whether the mask can be applied to the vector type. */
44631 /* Implementable with shufps or pshufd. */
44635 /* Otherwise we have to go through the motions and see if we can
44636 figure out how to generate the requested permutation. */
44647 }
44649 void
44651 {
44666 /* We'll either be able to implement the permutation directly... */
44670 /* ... or we use the special-case patterns. */
44672 }
44674 static void
44676 {
44691 {
44694 }
44696 /* Note that for AVX this isn't one instruction. */
44699 }
44702 /* Expand a vector operation CODE for a V*QImode in terms of the
44703 same operation on V*HImode. */
44705 void
44707 {
44719 {
44732 }
44736 {
44738 /* Unpack data such that we've got a source byte in each low byte of
44739 each word. We don't care what goes into the high byte of each word.
44740 Rather than trying to get zero in there, most convenient is to let
44741 it be a copy of the low byte. */
44746 /* FALLTHRU */
44758 /* FALLTHRU */
44768 }
44770 /* Perform the operation. */
44777 /* Merge the data back into the right place. */
44787 {
44788 /* For SSE2, we used an full interleave, so the desired
44789 results are in the even elements. */
44792 }
44793 else
44794 {
44795 /* For AVX, the interleave used above was not cross-lane. So the
44796 extraction is evens but with the second and third quarter swapped.
44797 Happily, that is even one insn shorter than even extraction. */
44800 }
44807 }
44809 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
44810 if op is CONST_VECTOR with all odd elements equal to their
44811 preceding element. */
44813 static bool
44815 {
44825 }
44827 void
44830 {
44833 rtx x;
44841 /* We only play even/odd games with vectors of SImode. */
44844 /* If we're looking for the odd results, shift those members down to
44845 the even slots. For some cpus this is faster than a PSHUFD. */
44847 {
44848 /* For XOP use vpmacsdqh, but only for smult, as it is only
44849 signed. */
44851 {
44855 }
44866 }
44869 {
44872 else
44874 }
44876 {
44879 else
44881 }
44886 else
44887 {
44890 /* The easiest way to implement this without PMULDQ is to go through
44891 the motions as if we are performing a full 64-bit multiply. With
44892 the exception that we need to do less shuffling of the elements. */
44894 /* Compute the sign-extension, aka highparts, of the two operands. */
44900 /* Multiply LO(A) * HI(B), and vice-versa. */
44906 /* Multiply LO(A) * LO(B). */
44910 /* Combine and shift the highparts into place. */
44915 /* Combine high and low parts. */
44918 }
44920 }
44922 void
44925 {
44931 {
44936 {
44937 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
44938 shuffle the elements once so that all elements are in the right
44939 place for immediate use: { A C B D }. */
44944 }
44945 else
44946 {
44947 /* Put the elements into place for the multiply. */
44951 }
44956 /* Shuffle the elements between the lanes. After this we
44957 have { A B E F | C D G H } for each operand. */
44967 /* Shuffle the elements within the lanes. After this we
44968 have { A A B B | C C D D } or { E E F F | G G H H }. */
45006 }
45007 }
45009 void
45011 {
45021 /* Move the results in element 2 down to element 1; we don't care
45022 what goes in elements 2 and 3. Then we can merge the parts
45023 back together with an interleave.
45025 Note that two other sequences were tried:
45026 (1) Use interleaves at the start instead of psrldq, which allows
45027 us to use a single shufps to merge things back at the end.
45028 (2) Use shufps here to combine the two vectors, then pshufd to
45029 put the elements in the correct order.
45030 In both cases the cost of the reformatting stall was too high
45031 and the overall sequence slower. */
45042 }
45044 void
45046 {
45051 {
45052 /* op1: A,B,C,D, op2: E,F,G,H */
45061 /* t1: B,A,D,C */
45068 /* t2: (B*E),(A*F),(D*G),(C*H) */
45071 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45074 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45077 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
45079 }
45080 else
45081 {
45086 {
45089 }
45091 {
45094 }
45096 {
45099 }
45100 else
45104 /* Multiply low parts. */
45108 /* Shift input vectors right 32 bits so we can multiply high parts. */
45113 /* Multiply high parts by low parts. */
45119 /* Combine and shift the highparts back. */
45123 /* Combine high and low parts. */
45125 }
45129 }
45131 /* Calculate integer abs() using only SSE2 instructions. */
45133 void
45135 {
45140 {
45141 /* For 32-bit signed integer X, the best way to calculate the absolute
45142 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45154 /* For 16-bit signed integer X, the best way to calculate the absolute
45155 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45163 /* For 8-bit signed integer X, the best way to calculate the absolute
45164 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45165 as SSE2 provides the PMINUB insn. */
45175 }
45179 }
45181 /* Expand an insert into a vector register through pinsr insn.
45182 Return true if successful. */
45184 bool
45186 {
45194 {
45197 }
45203 {
45208 {
45215 {
45247 }
45261 }
45265 }
45266 }
45267 \f
45268 /* This function returns the calling abi specific va_list type node.
45269 It returns the FNDECL specific va_list type. */
45271 static tree
45273 {
45280 else
45282 }
45284 /* Returns the canonical va_list type specified by TYPE. If there
45285 is no valid TYPE provided, it return NULL_TREE. */
45287 static tree
45289 {
45292 /* Resolve references and pointers to va_list type. */
45301 {
45306 {
45307 /* If va_list is an array type, the argument may have decayed
45308 to a pointer type, e.g. by being passed to another function.
45309 In that case, unwrap both types so that we can compare the
45310 underlying records. */
45313 {
45316 }
45317 }
45324 {
45325 /* If va_list is an array type, the argument may have decayed
45326 to a pointer type, e.g. by being passed to another function.
45327 In that case, unwrap both types so that we can compare the
45328 underlying records. */
45331 {
45334 }
45335 }
45342 {
45343 /* If va_list is an array type, the argument may have decayed
45344 to a pointer type, e.g. by being passed to another function.
45345 In that case, unwrap both types so that we can compare the
45346 underlying records. */
45349 {
45352 }
45353 }
45357 }
45359 }
45361 /* Iterate through the target-specific builtin types for va_list.
45362 IDX denotes the iterator, *PTREE is set to the result type of
45363 the va_list builtin, and *PNAME to its internal type.
45364 Returns zero if there is no element for this index, otherwise
45365 IDX should be increased upon the next call.
45366 Note, do not iterate a base builtin's name like __builtin_va_list.
45367 Used from c_common_nodes_and_builtins. */
45369 static int
45371 {
45373 {
45375 {
45388 }
45389 }
45392 }
45394 #undef TARGET_SCHED_DISPATCH
45395 #define TARGET_SCHED_DISPATCH has_dispatch
45396 #undef TARGET_SCHED_DISPATCH_DO
45397 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45398 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45399 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45400 #undef TARGET_SCHED_REORDER
45401 #define TARGET_SCHED_REORDER ix86_sched_reorder
45402 #undef TARGET_SCHED_ADJUST_PRIORITY
45403 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45404 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45405 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45406 ix86_dependencies_evaluation_hook
45408 /* The size of the dispatch window is the total number of bytes of
45409 object code allowed in a window. */
45410 #define DISPATCH_WINDOW_SIZE 16
45412 /* Number of dispatch windows considered for scheduling. */
45413 #define MAX_DISPATCH_WINDOWS 3
45415 /* Maximum number of instructions in a window. */
45416 #define MAX_INSN 4
45418 /* Maximum number of immediate operands in a window. */
45419 #define MAX_IMM 4
45421 /* Maximum number of immediate bits allowed in a window. */
45422 #define MAX_IMM_SIZE 128
45424 /* Maximum number of 32 bit immediates allowed in a window. */
45425 #define MAX_IMM_32 4
45427 /* Maximum number of 64 bit immediates allowed in a window. */
45428 #define MAX_IMM_64 2
45430 /* Maximum total of loads or prefetches allowed in a window. */
45431 #define MAX_LOAD 2
45433 /* Maximum total of stores allowed in a window. */
45434 #define MAX_STORE 1
45436 #undef BIG
45437 #define BIG 100
45440 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45443 disp_load,
45444 disp_store,
45445 disp_load_store,
45446 disp_prefetch,
45447 disp_imm,
45448 disp_imm_32,
45449 disp_imm_64,
45450 disp_branch,
45451 disp_cmp,
45452 disp_jcc,
45453 disp_last
45454 };
45456 /* Number of allowable groups in a dispatch window. It is an array
45457 indexed by dispatch_group enum. 100 is used as a big number,
45458 because the number of these kind of operations does not have any
45459 effect in dispatch window, but we need them for other reasons in
45460 the table. */
45463 };
45469 };
45471 /* Instruction path. */
45477 last_path
45478 };
45480 /* sched_insn_info defines a window to the instructions scheduled in
45481 the basic block. It contains a pointer to the insn_info table and
45482 the instruction scheduled.
45484 Windows are allocated for each basic block and are linked
45485 together. */
45487 rtx insn;
45494 /* Linked list of dispatch windows. This is a two way list of
45495 dispatch windows of a basic block. It contains information about
45496 the number of uops in the window and the total number of
45497 instructions and of bytes in the object code for this dispatch
45498 window. */
45516 /* Immediate valuse used in an insn. */
45518 {
45527 /* Get dispatch group of insn. */
45529 static enum dispatch_group
45531 {
45547 }
45549 /* Return true if insn is a compare instruction. */
45551 static bool
45553 {
45561 }
45563 /* Return true if a dispatch violation encountered. */
45565 static bool
45567 {
45571 }
45573 /* Return true if insn is a branch instruction. */
45575 static bool
45577 {
45579 }
45581 /* Return true if insn is a prefetch instruction. */
45583 static bool
45585 {
45587 }
45589 /* This function initializes a dispatch window and the list container holding a
45590 pointer to the window. */
45592 static void
45594 {
45600 else
45618 {
45624 }
45626 }
45628 /* This function allocates and initializes a dispatch window and the
45629 list container holding a pointer to the window. */
45633 {
45638 }
45640 /* This routine initializes the dispatch scheduling information. It
45641 initiates building dispatch scheduler tables and constructs the
45642 first dispatch window. */
45644 static void
45646 {
45647 /* Allocate a dispatch list and a window. */
45652 }
45654 /* This function returns true if a branch is detected. End of a basic block
45655 does not have to be a branch, but here we assume only branches end a
45656 window. */
45658 static bool
45660 {
45662 }
45664 /* This function is called when the end of a window processing is reached. */
45666 static void
45668 {
45671 {
45676 }
45678 }
45680 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45681 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45682 for 48 bytes of instructions. Note that these windows are not dispatch
45683 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45687 {
45689 {
45694 }
45700 }
45702 /* Increment the number of immediate operands of an instruction. */
45704 static int
45706 {
45711 {
45718 else
45729 {
45732 }
45737 }
45740 }
45742 /* Compute number of immediate operands of an instruction. */
45744 static void
45746 {
45749 }
45751 /* Return total size of immediate operands of an instruction along with number
45752 of corresponding immediate-operands. It initializes its parameters to zero
45753 befor calling FIND_CONSTANT.
45754 INSN is the input instruction. IMM is the total of immediates.
45755 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
45756 bit immediates. */
45758 static int
45760 {
45768 }
45770 /* This function indicates if an operand of an instruction is an
45771 immediate. */
45773 static bool
45775 {
45784 }
45786 /* Return single or double path for instructions. */
45788 static enum insn_path
45790 {
45800 }
45802 /* Return insn dispatch group. */
45804 static enum dispatch_group
45806 {
45824 }
45826 /* Count number of GROUP restricted instructions in a dispatch
45827 window WINDOW_LIST. */
45829 static int
45831 {
45842 {
45861 }
45874 }
45876 /* This function returns true if insn satisfies dispatch rules on the
45877 last window scheduled. */
45879 static bool
45881 {
45889 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
45890 instructions should be given the lowest priority in the
45891 scheduling process in Haifa scheduler to make sure they will be
45892 scheduled in the same dispatch window as the reference to them. */
45896 /* Check nonrestricted. */
45900 /* Get last dispatch window. */
45905 {
45910 /* Window 1 is full. Go for next window. */
45912 }
45919 /* See if it fits in the first window. */
45921 {
45922 /* The first widow should have only single and double path
45923 uops. */
45929 }
45931 }
45933 /* Add an instruction INSN with NUM_UOPS micro-operations to the
45934 dispatch window WINDOW_LIST. */
45936 static void
45938 {
45956 /* Initialize window with new instruction. */
45977 {
45980 }
45981 }
45983 /* Adds a scheduled instruction, INSN, to the current dispatch window.
45984 If the total bytes of instructions or the number of instructions in
45985 the window exceed allowable, it allocates a new window. */
45987 static void
45989 {
46012 /* Get the last dispatch window. */
46020 else
46023 /* If current window is full, get a new window.
46024 Window number zero is full, if MAX_INSN uops are scheduled in it.
46025 Window number one is full, if window zero's bytes plus window
46026 one's bytes is 32, or if the bytes of the new instruction added
46027 to the total makes it greater than 48, or it has already MAX_INSN
46028 instructions in it. */
46037 {
46040 }
46043 {
46047 {
46050 }
46051 }
46053 {
46058 {
46061 }
46064 }
46065 else
46069 {
46070 /* End of basic block is reached do end-basic-block process. */
46073 }
46074 }
46076 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46078 DEBUG_FUNCTION static void
46080 {
46086 else
46100 {
46103 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46109 }
46110 }
46112 /* Print to stdout a dispatch window. */
46114 DEBUG_FUNCTION void
46116 {
46118 }
46120 /* Print INSN dispatch information to FILE. */
46122 DEBUG_FUNCTION static void
46124 {
46147 }
46149 /* Print to STDERR the status of the ready list with respect to
46150 dispatch windows. */
46152 DEBUG_FUNCTION void
46154 {
46162 }
46164 /* This routine is the driver of the dispatch scheduler. */
46166 static void
46168 {
46173 }
46175 /* Return TRUE if Dispatch Scheduling is supported. */
46177 static bool
46179 {
46183 {
46199 }
46202 }
46204 /* Implementation of reassociation_width target hook used by
46205 reassoc phase to identify parallelism level in reassociated
46206 tree. Statements tree_code is passed in OPC. Arguments type
46207 is passed in MODE.
46209 Currently parallel reassociation is enabled for Atom
46210 processors only and we set reassociation width to be 2
46211 because Atom may issue up to 2 instructions per cycle.
46213 Return value should be fixed if parallel reassociation is
46214 enabled for other processors. */
46216 static int
46219 {
46228 }
46230 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46231 place emms and femms instructions. */
46233 static enum machine_mode
46235 {
46240 {
46257 else
46269 /* FALLTHRU */
46273 }
46274 }
46276 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46277 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46278 256bit and 128bit vectors. */
46280 static unsigned int
46282 {
46285 }
46287 \f
46289 /* Return class of registers which could be used for pseudo of MODE
46290 and of class RCLASS for spilling instead of memory. Return NO_REGS
46291 if it is not possible or non-profitable. */
46292 static reg_class_t
46294 {
46300 }
46302 /* Implement targetm.vectorize.init_cost. */
46306 {
46310 }
46312 /* Implement targetm.vectorize.add_stmt_cost. */
46314 static unsigned
46318 {
46325 /* Statements in an inner loop relative to the loop being
46326 vectorized are weighted more heavily. The value here is
46327 arbitrary and could potentially be improved with analysis. */
46335 }
46337 /* Implement targetm.vectorize.finish_cost. */
46339 static void
46342 {
46347 }
46349 /* Implement targetm.vectorize.destroy_cost_data. */
46351 static void
46353 {
46355 }
46357 /* Validate target specific memory model bits in VAL. */
46359 static unsigned HOST_WIDE_INT
46361 {
46368 {
46372 }
46375 {
46379 }
46381 {
46385 }
46387 }
46389 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46390 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46391 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46392 or number of vecsize_mangle variants that should be emitted. */
46394 static int
46398 {
46405 {
46409 }
46414 {
46421 /* case SCmode: */
46422 /* case DCmode: */
46428 }
46430 tree t;
46434 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46436 {
46443 /* case SCmode: */
46444 /* case DCmode: */
46450 }
46453 {
46454 /* Parse here processor clause. If not present, default to 'b'. */
46456 }
46458 {
46459 /* If the function isn't exported, we can pick up just one ISA
46460 for the clones. */
46465 else
46468 }
46469 else
46470 {
46473 }
46475 {
46488 }
46490 {
46493 else
46498 }
46500 }
46502 /* Add target attribute to SIMD clone NODE if needed. */
46504 static void
46506 {
46510 {
46525 }
46535 }
46537 /* If SIMD clone NODE can't be used in a vectorized loop
46538 in current function, return -1, otherwise return a badness of using it
46539 (0 if it is most desirable from vecsize_mangle point of view, 1
46540 slightly less desirable, etc.). */
46542 static int
46544 {
46546 {
46564 }
46565 }
46567 /* This function gives out the number of memory references.
46568 This value determines the unrolling factor for
46569 bdver3 and bdver4 architectures. */
46571 static int
46573 {
46575 {
46584 else
46586 }
46588 }
46590 /* This function adjusts the unroll factor based on
46591 the hardware capabilities. For ex, bdver3 has
46592 a loop buffer which makes unrolling of smaller
46593 loops less important. This function decides the
46594 unroll factor using number of memory references
46595 (value 32 is used) as a heuristic. */
46597 static unsigned
46599 {
46601 rtx insn;
46608 /* Count the number of memory references within the loop body. */
46611 {
46615 }
46622 }
46625 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46627 static bool
46629 {
46630 /* For x87 floating point with standard excess precision handling,
46631 there is no adddf3 pattern (since x87 floating point only has
46632 XFmode operations) so the default hook implementation gets this
46633 wrong. */
46635 }
46637 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46639 static void
46641 {
46646 {
46661 hold_fnclex);
46675 }
46677 {
46686 mxcsr_orig_var,
46696 ldmxcsr_hold_call);
46699 else
46704 ldmxcsr_clear_call);
46705 else
46709 stxmcsr_update_call);
46711 {
46717 exceptions_assign);
46718 }
46719 else
46724 ldmxcsr_update_call);
46725 }
46726 tree atomic_feraiseexcept
46731 atomic_feraiseexcept_call);
46732 }
46734 /* Initialize the GCC target structure. */
46735 #undef TARGET_RETURN_IN_MEMORY
46736 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
46738 #undef TARGET_LEGITIMIZE_ADDRESS
46739 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
46741 #undef TARGET_ATTRIBUTE_TABLE
46742 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
46743 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
46744 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
46745 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46746 # undef TARGET_MERGE_DECL_ATTRIBUTES
46747 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
46748 #endif
46750 #undef TARGET_COMP_TYPE_ATTRIBUTES
46751 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
46753 #undef TARGET_INIT_BUILTINS
46754 #define TARGET_INIT_BUILTINS ix86_init_builtins
46755 #undef TARGET_BUILTIN_DECL
46756 #define TARGET_BUILTIN_DECL ix86_builtin_decl
46757 #undef TARGET_EXPAND_BUILTIN
46758 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
46760 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
46761 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
46762 ix86_builtin_vectorized_function
46764 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
46765 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
46767 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
46768 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
46770 #undef TARGET_VECTORIZE_BUILTIN_GATHER
46771 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
46773 #undef TARGET_BUILTIN_RECIPROCAL
46774 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
46776 #undef TARGET_ASM_FUNCTION_EPILOGUE
46777 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
46779 #undef TARGET_ENCODE_SECTION_INFO
46780 #ifndef SUBTARGET_ENCODE_SECTION_INFO
46781 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
46782 #else
46783 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
46784 #endif
46786 #undef TARGET_ASM_OPEN_PAREN
46788 #undef TARGET_ASM_CLOSE_PAREN
46791 #undef TARGET_ASM_BYTE_OP
46792 #define TARGET_ASM_BYTE_OP ASM_BYTE
46794 #undef TARGET_ASM_ALIGNED_HI_OP
46795 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
46796 #undef TARGET_ASM_ALIGNED_SI_OP
46797 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
46798 #ifdef ASM_QUAD
46799 #undef TARGET_ASM_ALIGNED_DI_OP
46800 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
46801 #endif
46803 #undef TARGET_PROFILE_BEFORE_PROLOGUE
46804 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
46806 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
46807 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
46809 #undef TARGET_ASM_UNALIGNED_HI_OP
46810 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
46811 #undef TARGET_ASM_UNALIGNED_SI_OP
46812 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
46813 #undef TARGET_ASM_UNALIGNED_DI_OP
46814 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
46816 #undef TARGET_PRINT_OPERAND
46817 #define TARGET_PRINT_OPERAND ix86_print_operand
46818 #undef TARGET_PRINT_OPERAND_ADDRESS
46819 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
46820 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
46821 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
46822 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
46823 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
46825 #undef TARGET_SCHED_INIT_GLOBAL
46826 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
46827 #undef TARGET_SCHED_ADJUST_COST
46828 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
46829 #undef TARGET_SCHED_ISSUE_RATE
46830 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
46831 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
46832 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
46833 ia32_multipass_dfa_lookahead
46834 #undef TARGET_SCHED_MACRO_FUSION_P
46835 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
46836 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
46837 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
46839 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
46840 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
46842 #undef TARGET_MEMMODEL_CHECK
46843 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
46845 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
46846 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
46848 #ifdef HAVE_AS_TLS
46849 #undef TARGET_HAVE_TLS
46850 #define TARGET_HAVE_TLS true
46851 #endif
46852 #undef TARGET_CANNOT_FORCE_CONST_MEM
46853 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
46854 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
46855 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
46857 #undef TARGET_DELEGITIMIZE_ADDRESS
46858 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
46860 #undef TARGET_MS_BITFIELD_LAYOUT_P
46861 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
46863 #if TARGET_MACHO
46864 #undef TARGET_BINDS_LOCAL_P
46865 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
46866 #endif
46867 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46868 #undef TARGET_BINDS_LOCAL_P
46869 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
46870 #endif
46872 #undef TARGET_ASM_OUTPUT_MI_THUNK
46873 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
46874 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
46875 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
46877 #undef TARGET_ASM_FILE_START
46878 #define TARGET_ASM_FILE_START x86_file_start
46880 #undef TARGET_OPTION_OVERRIDE
46881 #define TARGET_OPTION_OVERRIDE ix86_option_override
46883 #undef TARGET_REGISTER_MOVE_COST
46884 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
46885 #undef TARGET_MEMORY_MOVE_COST
46886 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
46887 #undef TARGET_RTX_COSTS
46888 #define TARGET_RTX_COSTS ix86_rtx_costs
46889 #undef TARGET_ADDRESS_COST
46890 #define TARGET_ADDRESS_COST ix86_address_cost
46892 #undef TARGET_FIXED_CONDITION_CODE_REGS
46893 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
46894 #undef TARGET_CC_MODES_COMPATIBLE
46895 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
46897 #undef TARGET_MACHINE_DEPENDENT_REORG
46898 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
46900 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
46901 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
46903 #undef TARGET_BUILD_BUILTIN_VA_LIST
46904 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
46906 #undef TARGET_FOLD_BUILTIN
46907 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
46909 #undef TARGET_COMPARE_VERSION_PRIORITY
46910 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
46912 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
46913 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
46914 ix86_generate_version_dispatcher_body
46916 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
46917 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
46918 ix86_get_function_versions_dispatcher
46920 #undef TARGET_ENUM_VA_LIST_P
46921 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
46923 #undef TARGET_FN_ABI_VA_LIST
46924 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
46926 #undef TARGET_CANONICAL_VA_LIST_TYPE
46927 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
46929 #undef TARGET_EXPAND_BUILTIN_VA_START
46930 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
46932 #undef TARGET_MD_ASM_CLOBBERS
46933 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
46935 #undef TARGET_PROMOTE_PROTOTYPES
46936 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
46937 #undef TARGET_SETUP_INCOMING_VARARGS
46938 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
46939 #undef TARGET_MUST_PASS_IN_STACK
46940 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
46941 #undef TARGET_FUNCTION_ARG_ADVANCE
46942 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
46943 #undef TARGET_FUNCTION_ARG
46944 #define TARGET_FUNCTION_ARG ix86_function_arg
46945 #undef TARGET_FUNCTION_ARG_BOUNDARY
46946 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
46947 #undef TARGET_PASS_BY_REFERENCE
46948 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
46949 #undef TARGET_INTERNAL_ARG_POINTER
46950 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
46951 #undef TARGET_UPDATE_STACK_BOUNDARY
46952 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
46953 #undef TARGET_GET_DRAP_RTX
46954 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
46955 #undef TARGET_STRICT_ARGUMENT_NAMING
46956 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
46957 #undef TARGET_STATIC_CHAIN
46958 #define TARGET_STATIC_CHAIN ix86_static_chain
46959 #undef TARGET_TRAMPOLINE_INIT
46960 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
46961 #undef TARGET_RETURN_POPS_ARGS
46962 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
46964 #undef TARGET_LEGITIMATE_COMBINED_INSN
46965 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
46967 #undef TARGET_ASAN_SHADOW_OFFSET
46968 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
46970 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
46971 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
46973 #undef TARGET_SCALAR_MODE_SUPPORTED_P
46974 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
46976 #undef TARGET_VECTOR_MODE_SUPPORTED_P
46977 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
46979 #undef TARGET_C_MODE_FOR_SUFFIX
46980 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
46982 #ifdef HAVE_AS_TLS
46983 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
46984 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
46985 #endif
46987 #ifdef SUBTARGET_INSERT_ATTRIBUTES
46988 #undef TARGET_INSERT_ATTRIBUTES
46989 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
46990 #endif
46992 #undef TARGET_MANGLE_TYPE
46993 #define TARGET_MANGLE_TYPE ix86_mangle_type
46995 #if !TARGET_MACHO
46996 #undef TARGET_STACK_PROTECT_FAIL
46997 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
46998 #endif
47000 #undef TARGET_FUNCTION_VALUE
47001 #define TARGET_FUNCTION_VALUE ix86_function_value
47003 #undef TARGET_FUNCTION_VALUE_REGNO_P
47004 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47006 #undef TARGET_PROMOTE_FUNCTION_MODE
47007 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47009 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47010 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47012 #undef TARGET_INSTANTIATE_DECLS
47013 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47015 #undef TARGET_SECONDARY_RELOAD
47016 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47018 #undef TARGET_CLASS_MAX_NREGS
47019 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47021 #undef TARGET_PREFERRED_RELOAD_CLASS
47022 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47023 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47024 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47025 #undef TARGET_CLASS_LIKELY_SPILLED_P
47026 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47028 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47029 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47030 ix86_builtin_vectorization_cost
47031 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47032 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47033 ix86_vectorize_vec_perm_const_ok
47034 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47035 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47036 ix86_preferred_simd_mode
47037 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47038 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47039 ix86_autovectorize_vector_sizes
47040 #undef TARGET_VECTORIZE_INIT_COST
47041 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47042 #undef TARGET_VECTORIZE_ADD_STMT_COST
47043 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47044 #undef TARGET_VECTORIZE_FINISH_COST
47045 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47046 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47047 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47049 #undef TARGET_SET_CURRENT_FUNCTION
47050 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47052 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47053 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47055 #undef TARGET_OPTION_SAVE
47056 #define TARGET_OPTION_SAVE ix86_function_specific_save
47058 #undef TARGET_OPTION_RESTORE
47059 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47061 #undef TARGET_OPTION_PRINT
47062 #define TARGET_OPTION_PRINT ix86_function_specific_print
47064 #undef TARGET_OPTION_FUNCTION_VERSIONS
47065 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47067 #undef TARGET_CAN_INLINE_P
47068 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47070 #undef TARGET_EXPAND_TO_RTL_HOOK
47071 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47073 #undef TARGET_LEGITIMATE_ADDRESS_P
47074 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47076 #undef TARGET_LRA_P
47077 #define TARGET_LRA_P hook_bool_void_true
47079 #undef TARGET_REGISTER_PRIORITY
47080 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47082 #undef TARGET_REGISTER_USAGE_LEVELING_P
47083 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47085 #undef TARGET_LEGITIMATE_CONSTANT_P
47086 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47088 #undef TARGET_FRAME_POINTER_REQUIRED
47089 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47091 #undef TARGET_CAN_ELIMINATE
47092 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47094 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47095 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47097 #undef TARGET_ASM_CODE_END
47098 #define TARGET_ASM_CODE_END ix86_code_end
47100 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47101 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47103 #if TARGET_MACHO
47104 #undef TARGET_INIT_LIBFUNCS
47105 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47106 #endif
47108 #undef TARGET_LOOP_UNROLL_ADJUST
47109 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47111 #undef TARGET_SPILL_CLASS
47112 #define TARGET_SPILL_CLASS ix86_spill_class
47114 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47115 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47116 ix86_simd_clone_compute_vecsize_and_simdlen
47118 #undef TARGET_SIMD_CLONE_ADJUST
47119 #define TARGET_SIMD_CLONE_ADJUST \
47120 ix86_simd_clone_adjust
47122 #undef TARGET_SIMD_CLONE_USABLE
47123 #define TARGET_SIMD_CLONE_USABLE \
47124 ix86_simd_clone_usable
47126 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47127 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47128 ix86_float_exceptions_rounding_supported_p
47131 \f