1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 88, 89, 92, 93, 1994 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "insn-flags.h"
27 #include "insn-codes.h"
28 #include "insn-config.h"
33 static void store_fixed_bit_field
PROTO((rtx
, int, int, int, rtx
, int));
34 static void store_split_bit_field
PROTO((rtx
, int, int, rtx
, int));
35 static rtx extract_fixed_bit_field
PROTO((enum machine_mode
, rtx
, int,
36 int, int, rtx
, int, int));
37 static rtx mask_rtx
PROTO((enum machine_mode
, int,
39 static rtx lshift_value
PROTO((enum machine_mode
, rtx
,
41 static rtx extract_split_bit_field
PROTO((rtx
, int, int, int, int));
43 #define CEIL(x,y) (((x) + (y) - 1) / (y))
45 /* Non-zero means divides or modulus operations are relatively cheap for
46 powers of two, so don't use branches; emit the operation instead.
47 Usually, this will mean that the MD file will emit non-branch
50 static int sdiv_pow2_cheap
, smod_pow2_cheap
;
52 #ifndef SLOW_UNALIGNED_ACCESS
53 #define SLOW_UNALIGNED_ACCESS STRICT_ALIGNMENT
56 /* For compilers that support multiple targets with different word sizes,
57 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
58 is the H8/300(H) compiler. */
60 #ifndef MAX_BITS_PER_WORD
61 #define MAX_BITS_PER_WORD BITS_PER_WORD
64 /* Cost of various pieces of RTL. */
65 static int add_cost
, negate_cost
, zero_cost
;
66 static int shift_cost
[MAX_BITS_PER_WORD
];
67 static int shiftadd_cost
[MAX_BITS_PER_WORD
];
68 static int shiftsub_cost
[MAX_BITS_PER_WORD
];
74 /* This is "some random pseudo register" for purposes of calling recog
75 to see what insns exist. */
76 rtx reg
= gen_rtx (REG
, word_mode
, 10000);
77 rtx shift_insn
, shiftadd_insn
, shiftsub_insn
;
83 /* Since we are on the permanent obstack, we must be sure we save this
84 spot AFTER we call start_sequence, since it will reuse the rtl it
87 free_point
= (char *) oballoc (0);
89 zero_cost
= rtx_cost (const0_rtx
, 0);
90 add_cost
= rtx_cost (gen_rtx (PLUS
, word_mode
, reg
, reg
), SET
);
92 shift_insn
= emit_insn (gen_rtx (SET
, VOIDmode
, reg
,
93 gen_rtx (ASHIFT
, word_mode
, reg
,
96 shiftadd_insn
= emit_insn (gen_rtx (SET
, VOIDmode
, reg
,
97 gen_rtx (PLUS
, word_mode
,
98 gen_rtx (MULT
, word_mode
,
102 shiftsub_insn
= emit_insn (gen_rtx (SET
, VOIDmode
, reg
,
103 gen_rtx (MINUS
, word_mode
,
104 gen_rtx (MULT
, word_mode
,
111 shiftadd_cost
[0] = shiftsub_cost
[0] = add_cost
;
113 for (m
= 1; m
< BITS_PER_WORD
; m
++)
115 shift_cost
[m
] = shiftadd_cost
[m
] = shiftsub_cost
[m
] = 32000;
117 XEXP (SET_SRC (PATTERN (shift_insn
)), 1) = GEN_INT (m
);
118 if (recog (PATTERN (shift_insn
), shift_insn
, &dummy
) >= 0)
119 shift_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shift_insn
)), SET
);
121 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn
)), 0), 1)
122 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
123 if (recog (PATTERN (shiftadd_insn
), shiftadd_insn
, &dummy
) >= 0)
124 shiftadd_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn
)), SET
);
126 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn
)), 0), 1)
127 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
128 if (recog (PATTERN (shiftsub_insn
), shiftsub_insn
, &dummy
) >= 0)
129 shiftsub_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn
)), SET
);
132 negate_cost
= rtx_cost (gen_rtx (NEG
, word_mode
, reg
), SET
);
135 = (rtx_cost (gen_rtx (DIV
, word_mode
, reg
, GEN_INT (32)), SET
)
138 = (rtx_cost (gen_rtx (MOD
, word_mode
, reg
, GEN_INT (32)), SET
)
141 /* Free the objects we just allocated. */
146 /* Return an rtx representing minus the value of X.
147 MODE is the intended mode of the result,
148 useful if X is a CONST_INT. */
152 enum machine_mode mode
;
155 if (GET_CODE (x
) == CONST_INT
)
157 HOST_WIDE_INT val
= - INTVAL (x
);
158 if (GET_MODE_BITSIZE (mode
) < HOST_BITS_PER_WIDE_INT
)
160 /* Sign extend the value from the bits that are significant. */
161 if (val
& ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
162 val
|= (HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (mode
);
164 val
&= ((HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (mode
)) - 1;
166 return GEN_INT (val
);
169 return expand_unop (GET_MODE (x
), neg_optab
, x
, NULL_RTX
, 0);
172 /* Generate code to store value from rtx VALUE
173 into a bit-field within structure STR_RTX
174 containing BITSIZE bits starting at bit BITNUM.
175 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
176 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
177 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
179 /* ??? Note that there are two different ideas here for how
180 to determine the size to count bits within, for a register.
181 One is BITS_PER_WORD, and the other is the size of operand 3
182 of the insv pattern. (The latter assumes that an n-bit machine
183 will be able to insert bit fields up to n bits wide.)
184 It isn't certain that either of these is right.
185 extract_bit_field has the same quandary. */
188 store_bit_field (str_rtx
, bitsize
, bitnum
, fieldmode
, value
, align
, total_size
)
190 register int bitsize
;
192 enum machine_mode fieldmode
;
197 int unit
= (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
198 register int offset
= bitnum
/ unit
;
199 register int bitpos
= bitnum
% unit
;
200 register rtx op0
= str_rtx
;
202 if (GET_CODE (str_rtx
) == MEM
&& ! MEM_IN_STRUCT_P (str_rtx
))
205 /* Discount the part of the structure before the desired byte.
206 We need to know how many bytes are safe to reference after it. */
208 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
209 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
211 while (GET_CODE (op0
) == SUBREG
)
213 /* The following line once was done only if WORDS_BIG_ENDIAN,
214 but I think that is a mistake. WORDS_BIG_ENDIAN is
215 meaningful at a much higher level; when structures are copied
216 between memory and regs, the higher-numbered regs
217 always get higher addresses. */
218 offset
+= SUBREG_WORD (op0
);
219 /* We used to adjust BITPOS here, but now we do the whole adjustment
220 right after the loop. */
221 op0
= SUBREG_REG (op0
);
225 /* If OP0 is a register, BITPOS must count within a word.
226 But as we have it, it counts within whatever size OP0 now has.
227 On a bigendian machine, these are not the same, so convert. */
228 if (GET_CODE (op0
) != MEM
&& unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
229 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
232 value
= protect_from_queue (value
, 0);
235 value
= force_not_mem (value
);
237 /* Note that the adjustment of BITPOS above has no effect on whether
238 BITPOS is 0 in a REG bigger than a word. */
239 if (GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
240 && (GET_CODE (op0
) != MEM
241 || ! SLOW_UNALIGNED_ACCESS
242 || (offset
* BITS_PER_UNIT
% bitsize
== 0
243 && align
% GET_MODE_SIZE (fieldmode
) == 0))
244 && bitpos
== 0 && bitsize
== GET_MODE_BITSIZE (fieldmode
))
246 /* Storing in a full-word or multi-word field in a register
247 can be done with just SUBREG. */
248 if (GET_MODE (op0
) != fieldmode
)
250 if (GET_CODE (op0
) == REG
)
251 op0
= gen_rtx (SUBREG
, fieldmode
, op0
, offset
);
253 op0
= change_address (op0
, fieldmode
,
254 plus_constant (XEXP (op0
, 0), offset
));
256 emit_move_insn (op0
, value
);
260 /* Storing an lsb-aligned field in a register
261 can be done with a movestrict instruction. */
263 if (GET_CODE (op0
) != MEM
265 && bitpos
+ bitsize
== unit
269 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
270 && (GET_MODE (op0
) == fieldmode
271 || (movstrict_optab
->handlers
[(int) fieldmode
].insn_code
272 != CODE_FOR_nothing
)))
274 /* Get appropriate low part of the value being stored. */
275 if (GET_CODE (value
) == CONST_INT
|| GET_CODE (value
) == REG
)
276 value
= gen_lowpart (fieldmode
, value
);
277 else if (!(GET_CODE (value
) == SYMBOL_REF
278 || GET_CODE (value
) == LABEL_REF
279 || GET_CODE (value
) == CONST
))
280 value
= convert_to_mode (fieldmode
, value
, 0);
282 if (GET_MODE (op0
) == fieldmode
)
283 emit_move_insn (op0
, value
);
286 int icode
= movstrict_optab
->handlers
[(int) fieldmode
].insn_code
;
287 if(! (*insn_operand_predicate
[icode
][1]) (value
, fieldmode
))
288 value
= copy_to_mode_reg (fieldmode
, value
);
289 emit_insn (GEN_FCN (icode
)
290 (gen_rtx (SUBREG
, fieldmode
, op0
, offset
), value
));
295 /* Handle fields bigger than a word. */
297 if (bitsize
> BITS_PER_WORD
)
299 /* Here we transfer the words of the field
300 in the order least significant first.
301 This is because the most significant word is the one which may
302 be less than full. */
304 int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
307 /* This is the mode we must force value to, so that there will be enough
308 subwords to extract. Note that fieldmode will often (always?) be
309 VOIDmode, because that is what store_field uses to indicate that this
310 is a bit field, but passing VOIDmode to operand_subword_force will
311 result in an abort. */
312 fieldmode
= mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
, 0);
314 for (i
= 0; i
< nwords
; i
++)
316 /* If I is 0, use the low-order word in both field and target;
317 if I is 1, use the next to lowest word; and so on. */
318 int wordnum
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
319 int bit_offset
= (WORDS_BIG_ENDIAN
320 ? MAX (bitsize
- (i
+ 1) * BITS_PER_WORD
, 0)
321 : i
* BITS_PER_WORD
);
322 store_bit_field (op0
, MIN (BITS_PER_WORD
,
323 bitsize
- i
* BITS_PER_WORD
),
324 bitnum
+ bit_offset
, word_mode
,
325 operand_subword_force (value
, wordnum
,
326 (GET_MODE (value
) == VOIDmode
328 : GET_MODE (value
))),
334 /* From here on we can assume that the field to be stored in is
335 a full-word (whatever type that is), since it is shorter than a word. */
337 /* OFFSET is the number of words or bytes (UNIT says which)
338 from STR_RTX to the first word or byte containing part of the field. */
340 if (GET_CODE (op0
) == REG
)
343 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
344 op0
= gen_rtx (SUBREG
, TYPE_MODE (type_for_size (BITS_PER_WORD
, 0)),
350 op0
= protect_from_queue (op0
, 1);
353 /* If VALUE is a floating-point mode, access it as an integer of the
354 corresponding size. This can occur on a machine with 64 bit registers
355 that uses SFmode for float. This can also occur for unaligned float
357 if (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
)
359 if (GET_CODE (value
) != REG
)
360 value
= copy_to_reg (value
);
361 value
= gen_rtx (SUBREG
, word_mode
, value
, 0);
364 /* Now OFFSET is nonzero only if OP0 is memory
365 and is therefore always measured in bytes. */
369 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
370 /* Ensure insv's size is wide enough for this field. */
371 && (GET_MODE_BITSIZE (insn_operand_mode
[(int) CODE_FOR_insv
][3])
374 int xbitpos
= bitpos
;
377 rtx last
= get_last_insn ();
379 enum machine_mode maxmode
380 = insn_operand_mode
[(int) CODE_FOR_insv
][3];
382 int save_volatile_ok
= volatile_ok
;
385 /* If this machine's insv can only insert into a register, or if we
386 are to force MEMs into a register, copy OP0 into a register and
387 save it back later. */
388 if (GET_CODE (op0
) == MEM
390 || ! ((*insn_operand_predicate
[(int) CODE_FOR_insv
][0])
394 enum machine_mode bestmode
;
396 /* Get the mode to use for inserting into this field. If OP0 is
397 BLKmode, get the smallest mode consistent with the alignment. If
398 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
399 mode. Otherwise, use the smallest mode containing the field. */
401 if (GET_MODE (op0
) == BLKmode
402 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
404 = get_best_mode (bitsize
, bitnum
, align
* BITS_PER_UNIT
, maxmode
,
405 MEM_VOLATILE_P (op0
));
407 bestmode
= GET_MODE (op0
);
409 if (bestmode
== VOIDmode
410 || (STRICT_ALIGNMENT
&& GET_MODE_SIZE (bestmode
) > align
))
413 /* Adjust address to point to the containing unit of that mode. */
414 unit
= GET_MODE_BITSIZE (bestmode
);
415 /* Compute offset as multiple of this unit, counting in bytes. */
416 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
417 bitpos
= bitnum
% unit
;
418 op0
= change_address (op0
, bestmode
,
419 plus_constant (XEXP (op0
, 0), offset
));
421 /* Fetch that unit, store the bitfield in it, then store the unit. */
422 tempreg
= copy_to_reg (op0
);
423 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, value
,
425 emit_move_insn (op0
, tempreg
);
428 volatile_ok
= save_volatile_ok
;
430 /* Add OFFSET into OP0's address. */
431 if (GET_CODE (xop0
) == MEM
)
432 xop0
= change_address (xop0
, byte_mode
,
433 plus_constant (XEXP (xop0
, 0), offset
));
435 /* If xop0 is a register, we need it in MAXMODE
436 to make it acceptable to the format of insv. */
437 if (GET_CODE (xop0
) == SUBREG
)
438 /* We can't just change the mode, because this might clobber op0,
439 and we will need the original value of op0 if insv fails. */
440 xop0
= gen_rtx (SUBREG
, maxmode
, SUBREG_REG (xop0
), SUBREG_WORD (xop0
));
441 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
442 xop0
= gen_rtx (SUBREG
, maxmode
, xop0
, 0);
444 /* On big-endian machines, we count bits from the most significant.
445 If the bit field insn does not, we must invert. */
447 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
448 xbitpos
= unit
- bitsize
- xbitpos
;
450 /* We have been counting XBITPOS within UNIT.
451 Count instead within the size of the register. */
453 if (GET_CODE (xop0
) != MEM
)
454 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
456 unit
= GET_MODE_BITSIZE (maxmode
);
458 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
460 if (GET_MODE (value
) != maxmode
)
462 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
464 /* Optimization: Don't bother really extending VALUE
465 if it has all the bits we will actually use. However,
466 if we must narrow it, be sure we do it correctly. */
468 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
470 /* Avoid making subreg of a subreg, or of a mem. */
471 if (GET_CODE (value1
) != REG
)
472 value1
= copy_to_reg (value1
);
473 value1
= gen_rtx (SUBREG
, maxmode
, value1
, 0);
476 value1
= gen_lowpart (maxmode
, value1
);
478 else if (!CONSTANT_P (value
))
479 /* Parse phase is supposed to make VALUE's data type
480 match that of the component reference, which is a type
481 at least as wide as the field; so VALUE should have
482 a mode that corresponds to that type. */
486 /* If this machine's insv insists on a register,
487 get VALUE1 into a register. */
488 if (! ((*insn_operand_predicate
[(int) CODE_FOR_insv
][3])
490 value1
= force_reg (maxmode
, value1
);
492 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
497 delete_insns_since (last
);
498 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, align
);
504 /* Insv is not available; store using shifts and boolean ops. */
505 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, align
);
509 /* Use shifts and boolean operations to store VALUE
510 into a bit field of width BITSIZE
511 in a memory location specified by OP0 except offset by OFFSET bytes.
512 (OFFSET must be 0 if OP0 is a register.)
513 The field starts at position BITPOS within the byte.
514 (If OP0 is a register, it may be a full word or a narrower mode,
515 but BITPOS still counts within a full word,
516 which is significant on bigendian machines.)
517 STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
519 Note that protect_from_queue has already been done on OP0 and VALUE. */
522 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, struct_align
)
524 register int offset
, bitsize
, bitpos
;
528 register enum machine_mode mode
;
529 int total_bits
= BITS_PER_WORD
;
534 /* There is a case not handled here:
535 a structure with a known alignment of just a halfword
536 and a field split across two aligned halfwords within the structure.
537 Or likewise a structure with a known alignment of just a byte
538 and a field split across two bytes.
539 Such cases are not supposed to be able to occur. */
541 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
545 /* Special treatment for a bit field split across two registers. */
546 if (bitsize
+ bitpos
> BITS_PER_WORD
)
548 store_split_bit_field (op0
, bitsize
, bitpos
,
549 value
, BITS_PER_WORD
);
555 /* Get the proper mode to use for this field. We want a mode that
556 includes the entire field. If such a mode would be larger than
557 a word, we won't be doing the extraction the normal way. */
559 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
560 struct_align
* BITS_PER_UNIT
, word_mode
,
561 GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
));
563 if (mode
== VOIDmode
)
565 /* The only way this should occur is if the field spans word
567 store_split_bit_field (op0
,
568 bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
569 value
, struct_align
);
573 total_bits
= GET_MODE_BITSIZE (mode
);
575 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
576 be be in the range 0 to total_bits-1, and put any excess bytes in
578 if (bitpos
>= total_bits
)
580 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
581 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
585 /* Get ref to an aligned byte, halfword, or word containing the field.
586 Adjust BITPOS to be position within a word,
587 and OFFSET to be the offset of that word.
588 Then alter OP0 to refer to that word. */
589 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
590 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
591 op0
= change_address (op0
, mode
,
592 plus_constant (XEXP (op0
, 0), offset
));
595 mode
= GET_MODE (op0
);
597 /* Now MODE is either some integral mode for a MEM as OP0,
598 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
599 The bit field is contained entirely within OP0.
600 BITPOS is the starting bit number within OP0.
601 (OP0's mode may actually be narrower than MODE.) */
604 /* BITPOS is the distance between our msb
605 and that of the containing datum.
606 Convert it to the distance from the lsb. */
608 bitpos
= total_bits
- bitsize
- bitpos
;
610 /* Now BITPOS is always the distance between our lsb
613 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
614 we must first convert its mode to MODE. */
616 if (GET_CODE (value
) == CONST_INT
)
618 register HOST_WIDE_INT v
= INTVAL (value
);
620 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
621 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
625 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
626 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
627 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
630 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
634 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
635 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
637 if (GET_MODE (value
) != mode
)
639 if ((GET_CODE (value
) == REG
|| GET_CODE (value
) == SUBREG
)
640 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
641 value
= gen_lowpart (mode
, value
);
643 value
= convert_to_mode (mode
, value
, 1);
647 value
= expand_binop (mode
, and_optab
, value
,
648 mask_rtx (mode
, 0, bitsize
, 0),
649 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
651 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
652 build_int_2 (bitpos
, 0), NULL_RTX
, 1);
655 /* Now clear the chosen bits in OP0,
656 except that if VALUE is -1 we need not bother. */
658 subtarget
= (GET_CODE (op0
) == REG
|| ! flag_force_mem
) ? op0
: 0;
662 temp
= expand_binop (mode
, and_optab
, op0
,
663 mask_rtx (mode
, bitpos
, bitsize
, 1),
664 subtarget
, 1, OPTAB_LIB_WIDEN
);
670 /* Now logical-or VALUE into OP0, unless it is zero. */
673 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
674 subtarget
, 1, OPTAB_LIB_WIDEN
);
676 emit_move_insn (op0
, temp
);
679 /* Store a bit field that is split across multiple accessible memory objects.
681 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
682 BITSIZE is the field width; BITPOS the position of its first bit
684 VALUE is the value to store.
685 ALIGN is the known alignment of OP0, measured in bytes.
686 This is also the size of the memory objects to be used.
688 This does not yet handle fields wider than BITS_PER_WORD. */
691 store_split_bit_field (op0
, bitsize
, bitpos
, value
, align
)
697 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
699 int unit
= MIN (align
* BITS_PER_UNIT
, BITS_PER_WORD
);
702 /* If VALUE is a constant other than a CONST_INT, get it into a register in
703 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
704 that VALUE might be a floating-point constant. */
705 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
707 rtx word
= gen_lowpart_common (word_mode
, value
);
709 if (word
&& (value
!= word
))
712 value
= gen_lowpart_common (word_mode
,
713 force_reg (GET_MODE (value
), value
));
716 while (bitsdone
< bitsize
)
723 offset
= (bitpos
+ bitsdone
) / unit
;
724 thispos
= (bitpos
+ bitsdone
) % unit
;
726 /* THISSIZE must not overrun a word boundary. Otherwise,
727 store_fixed_bit_field will call us again, and we will mutually
729 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
730 thissize
= MIN (thissize
, unit
- thispos
);
733 /* Fetch successively less significant portions. */
734 if (GET_CODE (value
) == CONST_INT
)
735 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
736 >> (bitsize
- bitsdone
- thissize
))
737 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
740 /* The args are chosen so that the last part
743 /* If the value isn't in memory, then it must be right aligned
744 if a register, so skip past the padding on the left. If it
745 is in memory, then there is no padding on the left. */
746 if (GET_CODE (value
) != MEM
)
747 bit_offset
= BITS_PER_WORD
- bitsize
;
748 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
749 bit_offset
+ bitsdone
,
753 /* Fetch successively more significant portions. */
754 if (GET_CODE (value
) == CONST_INT
)
755 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
)) >> bitsdone
)
756 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
758 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
759 bitsdone
, NULL_RTX
, 1, align
);
762 /* If OP0 is a register, then handle OFFSET here.
764 When handling multiword bitfields, extract_bit_field may pass
765 down a word_mode SUBREG of a larger REG for a bitfield that actually
766 crosses a word boundary. Thus, for a SUBREG, we must find
767 the current word starting from the base register. */
768 if (GET_CODE (op0
) == SUBREG
)
770 word
= operand_subword (SUBREG_REG (op0
),
771 SUBREG_WORD (op0
) + offset
, 1,
772 GET_MODE (SUBREG_REG (op0
)));
775 else if (GET_CODE (op0
) == REG
)
777 word
= operand_subword (op0
, offset
, 1, GET_MODE (op0
));
786 /* OFFSET is in UNITs, and UNIT is in bits.
787 store_fixed_bit_field wants offset in bytes. */
788 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
,
789 thissize
, thispos
, part
, align
);
790 bitsdone
+= thissize
;
794 /* Generate code to extract a byte-field from STR_RTX
795 containing BITSIZE bits, starting at BITNUM,
796 and put it in TARGET if possible (if TARGET is nonzero).
797 Regardless of TARGET, we return the rtx for where the value is placed.
800 STR_RTX is the structure containing the byte (a REG or MEM).
801 UNSIGNEDP is nonzero if this is an unsigned bit field.
802 MODE is the natural mode of the field value once extracted.
803 TMODE is the mode the caller would like the value to have;
804 but the value may be returned with type MODE instead.
806 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
807 TOTAL_SIZE is the size in bytes of the containing structure,
810 If a TARGET is specified and we can store in it at no extra cost,
811 we do so, and return TARGET.
812 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
813 if they are equally easy. */
816 extract_bit_field (str_rtx
, bitsize
, bitnum
, unsignedp
,
817 target
, mode
, tmode
, align
, total_size
)
819 register int bitsize
;
823 enum machine_mode mode
, tmode
;
827 int unit
= (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
828 register int offset
= bitnum
/ unit
;
829 register int bitpos
= bitnum
% unit
;
830 register rtx op0
= str_rtx
;
831 rtx spec_target
= target
;
832 rtx spec_target_subreg
= 0;
834 if (GET_CODE (str_rtx
) == MEM
&& ! MEM_IN_STRUCT_P (str_rtx
))
837 /* Discount the part of the structure before the desired byte.
838 We need to know how many bytes are safe to reference after it. */
840 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
841 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
843 if (tmode
== VOIDmode
)
845 while (GET_CODE (op0
) == SUBREG
)
847 offset
+= SUBREG_WORD (op0
);
848 op0
= SUBREG_REG (op0
);
852 /* If OP0 is a register, BITPOS must count within a word.
853 But as we have it, it counts within whatever size OP0 now has.
854 On a bigendian machine, these are not the same, so convert. */
855 if (GET_CODE (op0
) != MEM
&& unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
856 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
859 /* Extracting a full-word or multi-word value
860 from a structure in a register or aligned memory.
861 This can be done with just SUBREG.
862 So too extracting a subword value in
863 the least significant part of the register. */
865 if ((GET_CODE (op0
) == REG
866 || (GET_CODE (op0
) == MEM
867 && (! SLOW_UNALIGNED_ACCESS
868 || (offset
* BITS_PER_UNIT
% bitsize
== 0
869 && align
* BITS_PER_UNIT
% bitsize
== 0))))
870 && ((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
871 && bitpos
% BITS_PER_WORD
== 0)
872 || (mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0) != BLKmode
874 && bitpos
+ bitsize
== BITS_PER_WORD
880 enum machine_mode mode1
881 = mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0);
883 if (mode1
!= GET_MODE (op0
))
885 if (GET_CODE (op0
) == REG
)
886 op0
= gen_rtx (SUBREG
, mode1
, op0
, offset
);
888 op0
= change_address (op0
, mode1
,
889 plus_constant (XEXP (op0
, 0), offset
));
892 return convert_to_mode (tmode
, op0
, unsignedp
);
896 /* Handle fields bigger than a word. */
898 if (bitsize
> BITS_PER_WORD
)
900 /* Here we transfer the words of the field
901 in the order least significant first.
902 This is because the most significant word is the one which may
903 be less than full. */
905 int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
908 if (target
== 0 || GET_CODE (target
) != REG
)
909 target
= gen_reg_rtx (mode
);
911 for (i
= 0; i
< nwords
; i
++)
913 /* If I is 0, use the low-order word in both field and target;
914 if I is 1, use the next to lowest word; and so on. */
915 int wordnum
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
916 int bit_offset
= (WORDS_BIG_ENDIAN
917 ? MAX (0, bitsize
- (i
+ 1) * BITS_PER_WORD
)
918 : i
* BITS_PER_WORD
);
919 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
921 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
922 bitsize
- i
* BITS_PER_WORD
),
924 1, target_part
, mode
, word_mode
,
927 if (target_part
== 0)
930 if (result_part
!= target_part
)
931 emit_move_insn (target_part
, result_part
);
936 /* Signed bit field: sign-extend with two arithmetic shifts. */
937 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
938 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
940 return expand_shift (RSHIFT_EXPR
, mode
, target
,
941 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
945 /* From here on we know the desired field is smaller than a word
946 so we can assume it is an integer. So we can safely extract it as one
947 size of integer, if necessary, and then truncate or extend
948 to the size that is wanted. */
950 /* OFFSET is the number of words or bytes (UNIT says which)
951 from STR_RTX to the first word or byte containing part of the field. */
953 if (GET_CODE (op0
) == REG
)
956 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
957 op0
= gen_rtx (SUBREG
, TYPE_MODE (type_for_size (BITS_PER_WORD
, 0)),
963 op0
= protect_from_queue (str_rtx
, 1);
966 /* Now OFFSET is nonzero only for memory operands. */
972 && (GET_MODE_BITSIZE (insn_operand_mode
[(int) CODE_FOR_extzv
][0])
975 int xbitpos
= bitpos
, xoffset
= offset
;
976 rtx bitsize_rtx
, bitpos_rtx
;
977 rtx last
= get_last_insn();
979 rtx xtarget
= target
;
980 rtx xspec_target
= spec_target
;
981 rtx xspec_target_subreg
= spec_target_subreg
;
983 enum machine_mode maxmode
984 = insn_operand_mode
[(int) CODE_FOR_extzv
][0];
986 if (GET_CODE (xop0
) == MEM
)
988 int save_volatile_ok
= volatile_ok
;
991 /* Is the memory operand acceptable? */
993 || ! ((*insn_operand_predicate
[(int) CODE_FOR_extzv
][1])
994 (xop0
, GET_MODE (xop0
))))
996 /* No, load into a reg and extract from there. */
997 enum machine_mode bestmode
;
999 /* Get the mode to use for inserting into this field. If
1000 OP0 is BLKmode, get the smallest mode consistent with the
1001 alignment. If OP0 is a non-BLKmode object that is no
1002 wider than MAXMODE, use its mode. Otherwise, use the
1003 smallest mode containing the field. */
1005 if (GET_MODE (xop0
) == BLKmode
1006 || (GET_MODE_SIZE (GET_MODE (op0
))
1007 > GET_MODE_SIZE (maxmode
)))
1008 bestmode
= get_best_mode (bitsize
, bitnum
,
1009 align
* BITS_PER_UNIT
, maxmode
,
1010 MEM_VOLATILE_P (xop0
));
1012 bestmode
= GET_MODE (xop0
);
1014 if (bestmode
== VOIDmode
1015 || (STRICT_ALIGNMENT
&& GET_MODE_SIZE (bestmode
) > align
))
1018 /* Compute offset as multiple of this unit,
1019 counting in bytes. */
1020 unit
= GET_MODE_BITSIZE (bestmode
);
1021 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1022 xbitpos
= bitnum
% unit
;
1023 xop0
= change_address (xop0
, bestmode
,
1024 plus_constant (XEXP (xop0
, 0),
1026 /* Fetch it to a register in that size. */
1027 xop0
= force_reg (bestmode
, xop0
);
1029 /* XBITPOS counts within UNIT, which is what is expected. */
1032 /* Get ref to first byte containing part of the field. */
1033 xop0
= change_address (xop0
, byte_mode
,
1034 plus_constant (XEXP (xop0
, 0), xoffset
));
1036 volatile_ok
= save_volatile_ok
;
1039 /* If op0 is a register, we need it in MAXMODE (which is usually
1040 SImode). to make it acceptable to the format of extzv. */
1041 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1043 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1044 xop0
= gen_rtx (SUBREG
, maxmode
, xop0
, 0);
1046 /* On big-endian machines, we count bits from the most significant.
1047 If the bit field insn does not, we must invert. */
1048 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1049 xbitpos
= unit
- bitsize
- xbitpos
;
1051 /* Now convert from counting within UNIT to counting in MAXMODE. */
1053 if (GET_CODE (xop0
) != MEM
)
1054 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1056 unit
= GET_MODE_BITSIZE (maxmode
);
1059 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1060 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1062 if (GET_MODE (xtarget
) != maxmode
)
1064 if (GET_CODE (xtarget
) == REG
)
1066 int wider
= (GET_MODE_SIZE (maxmode
)
1067 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1068 xtarget
= gen_lowpart (maxmode
, xtarget
);
1070 xspec_target_subreg
= xtarget
;
1073 xtarget
= gen_reg_rtx (maxmode
);
1076 /* If this machine's extzv insists on a register target,
1077 make sure we have one. */
1078 if (! ((*insn_operand_predicate
[(int) CODE_FOR_extzv
][0])
1079 (xtarget
, maxmode
)))
1080 xtarget
= gen_reg_rtx (maxmode
);
1082 bitsize_rtx
= GEN_INT (bitsize
);
1083 bitpos_rtx
= GEN_INT (xbitpos
);
1085 pat
= gen_extzv (protect_from_queue (xtarget
, 1),
1086 xop0
, bitsize_rtx
, bitpos_rtx
);
1091 spec_target
= xspec_target
;
1092 spec_target_subreg
= xspec_target_subreg
;
1096 delete_insns_since (last
);
1097 target
= extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
,
1098 bitpos
, target
, 1, align
);
1104 target
= extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
, bitpos
,
1111 && (GET_MODE_BITSIZE (insn_operand_mode
[(int) CODE_FOR_extv
][0])
1114 int xbitpos
= bitpos
, xoffset
= offset
;
1115 rtx bitsize_rtx
, bitpos_rtx
;
1116 rtx last
= get_last_insn();
1117 rtx xop0
= op0
, xtarget
= target
;
1118 rtx xspec_target
= spec_target
;
1119 rtx xspec_target_subreg
= spec_target_subreg
;
1121 enum machine_mode maxmode
1122 = insn_operand_mode
[(int) CODE_FOR_extv
][0];
1124 if (GET_CODE (xop0
) == MEM
)
1126 /* Is the memory operand acceptable? */
1127 if (! ((*insn_operand_predicate
[(int) CODE_FOR_extv
][1])
1128 (xop0
, GET_MODE (xop0
))))
1130 /* No, load into a reg and extract from there. */
1131 enum machine_mode bestmode
;
1133 /* Get the mode to use for inserting into this field. If
1134 OP0 is BLKmode, get the smallest mode consistent with the
1135 alignment. If OP0 is a non-BLKmode object that is no
1136 wider than MAXMODE, use its mode. Otherwise, use the
1137 smallest mode containing the field. */
1139 if (GET_MODE (xop0
) == BLKmode
1140 || (GET_MODE_SIZE (GET_MODE (op0
))
1141 > GET_MODE_SIZE (maxmode
)))
1142 bestmode
= get_best_mode (bitsize
, bitnum
,
1143 align
* BITS_PER_UNIT
, maxmode
,
1144 MEM_VOLATILE_P (xop0
));
1146 bestmode
= GET_MODE (xop0
);
1148 if (bestmode
== VOIDmode
1149 || (STRICT_ALIGNMENT
&& GET_MODE_SIZE (bestmode
) > align
))
1152 /* Compute offset as multiple of this unit,
1153 counting in bytes. */
1154 unit
= GET_MODE_BITSIZE (bestmode
);
1155 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1156 xbitpos
= bitnum
% unit
;
1157 xop0
= change_address (xop0
, bestmode
,
1158 plus_constant (XEXP (xop0
, 0),
1160 /* Fetch it to a register in that size. */
1161 xop0
= force_reg (bestmode
, xop0
);
1163 /* XBITPOS counts within UNIT, which is what is expected. */
1166 /* Get ref to first byte containing part of the field. */
1167 xop0
= change_address (xop0
, byte_mode
,
1168 plus_constant (XEXP (xop0
, 0), xoffset
));
1171 /* If op0 is a register, we need it in MAXMODE (which is usually
1172 SImode) to make it acceptable to the format of extv. */
1173 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1175 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1176 xop0
= gen_rtx (SUBREG
, maxmode
, xop0
, 0);
1178 /* On big-endian machines, we count bits from the most significant.
1179 If the bit field insn does not, we must invert. */
1180 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1181 xbitpos
= unit
- bitsize
- xbitpos
;
1183 /* XBITPOS counts within a size of UNIT.
1184 Adjust to count within a size of MAXMODE. */
1186 if (GET_CODE (xop0
) != MEM
)
1187 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1189 unit
= GET_MODE_BITSIZE (maxmode
);
1192 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1193 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1195 if (GET_MODE (xtarget
) != maxmode
)
1197 if (GET_CODE (xtarget
) == REG
)
1199 int wider
= (GET_MODE_SIZE (maxmode
)
1200 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1201 xtarget
= gen_lowpart (maxmode
, xtarget
);
1203 xspec_target_subreg
= xtarget
;
1206 xtarget
= gen_reg_rtx (maxmode
);
1209 /* If this machine's extv insists on a register target,
1210 make sure we have one. */
1211 if (! ((*insn_operand_predicate
[(int) CODE_FOR_extv
][0])
1212 (xtarget
, maxmode
)))
1213 xtarget
= gen_reg_rtx (maxmode
);
1215 bitsize_rtx
= GEN_INT (bitsize
);
1216 bitpos_rtx
= GEN_INT (xbitpos
);
1218 pat
= gen_extv (protect_from_queue (xtarget
, 1),
1219 xop0
, bitsize_rtx
, bitpos_rtx
);
1224 spec_target
= xspec_target
;
1225 spec_target_subreg
= xspec_target_subreg
;
1229 delete_insns_since (last
);
1230 target
= extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
,
1231 bitpos
, target
, 0, align
);
1237 target
= extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
, bitpos
,
1240 if (target
== spec_target
)
1242 if (target
== spec_target_subreg
)
1244 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1246 /* If the target mode is floating-point, first convert to the
1247 integer mode of that size and then access it as a floating-point
1248 value via a SUBREG. */
1249 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1251 target
= convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode
),
1254 if (GET_CODE (target
) != REG
)
1255 target
= copy_to_reg (target
);
1256 return gen_rtx (SUBREG
, tmode
, target
, 0);
1259 return convert_to_mode (tmode
, target
, unsignedp
);
1264 /* Extract a bit field using shifts and boolean operations
1265 Returns an rtx to represent the value.
1266 OP0 addresses a register (word) or memory (byte).
1267 BITPOS says which bit within the word or byte the bit field starts in.
1268 OFFSET says how many bytes farther the bit field starts;
1269 it is 0 if OP0 is a register.
1270 BITSIZE says how many bits long the bit field is.
1271 (If OP0 is a register, it may be narrower than a full word,
1272 but BITPOS still counts within a full word,
1273 which is significant on bigendian machines.)
1275 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1276 If TARGET is nonzero, attempts to store the value there
1277 and return TARGET, but this is not guaranteed.
1278 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1280 ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1283 extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
, bitpos
,
1284 target
, unsignedp
, align
)
1285 enum machine_mode tmode
;
1286 register rtx op0
, target
;
1287 register int offset
, bitsize
, bitpos
;
1291 int total_bits
= BITS_PER_WORD
;
1292 enum machine_mode mode
;
1294 if (GET_CODE (op0
) == SUBREG
|| GET_CODE (op0
) == REG
)
1296 /* Special treatment for a bit field split across two registers. */
1297 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1298 return extract_split_bit_field (op0
, bitsize
, bitpos
,
1303 /* Get the proper mode to use for this field. We want a mode that
1304 includes the entire field. If such a mode would be larger than
1305 a word, we won't be doing the extraction the normal way. */
1307 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1308 align
* BITS_PER_UNIT
, word_mode
,
1309 GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
));
1311 if (mode
== VOIDmode
)
1312 /* The only way this should occur is if the field spans word
1314 return extract_split_bit_field (op0
, bitsize
,
1315 bitpos
+ offset
* BITS_PER_UNIT
,
1318 total_bits
= GET_MODE_BITSIZE (mode
);
1320 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1321 be be in the range 0 to total_bits-1, and put any excess bytes in
1323 if (bitpos
>= total_bits
)
1325 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1326 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1330 /* Get ref to an aligned byte, halfword, or word containing the field.
1331 Adjust BITPOS to be position within a word,
1332 and OFFSET to be the offset of that word.
1333 Then alter OP0 to refer to that word. */
1334 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1335 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1336 op0
= change_address (op0
, mode
,
1337 plus_constant (XEXP (op0
, 0), offset
));
1340 mode
= GET_MODE (op0
);
1342 #if BYTES_BIG_ENDIAN
1343 /* BITPOS is the distance between our msb and that of OP0.
1344 Convert it to the distance from the lsb. */
1346 bitpos
= total_bits
- bitsize
- bitpos
;
1348 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1349 We have reduced the big-endian case to the little-endian case. */
1355 /* If the field does not already start at the lsb,
1356 shift it so it does. */
1357 tree amount
= build_int_2 (bitpos
, 0);
1358 /* Maybe propagate the target for the shift. */
1359 /* But not if we will return it--could confuse integrate.c. */
1360 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1361 && !REG_FUNCTION_VALUE_P (target
)
1363 if (tmode
!= mode
) subtarget
= 0;
1364 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1366 /* Convert the value to the desired mode. */
1368 op0
= convert_to_mode (tmode
, op0
, 1);
1370 /* Unless the msb of the field used to be the msb when we shifted,
1371 mask out the upper bits. */
1373 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
1375 #ifdef SLOW_ZERO_EXTEND
1376 /* Always generate an `and' if
1377 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1378 will combine fruitfully with the zero-extend. */
1383 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1384 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1385 target
, 1, OPTAB_LIB_WIDEN
);
1389 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1390 then arithmetic-shift its lsb to the lsb of the word. */
1391 op0
= force_reg (mode
, op0
);
1395 /* Find the narrowest integer mode that contains the field. */
1397 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1398 mode
= GET_MODE_WIDER_MODE (mode
))
1399 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1401 op0
= convert_to_mode (mode
, op0
, 0);
1405 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1407 tree amount
= build_int_2 (GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
), 0);
1408 /* Maybe propagate the target for the shift. */
1409 /* But not if we will return the result--could confuse integrate.c. */
1410 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1411 && ! REG_FUNCTION_VALUE_P (target
)
1413 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1416 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1417 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1421 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1422 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1423 complement of that if COMPLEMENT. The mask is truncated if
1424 necessary to the width of mode MODE. */
1427 mask_rtx (mode
, bitpos
, bitsize
, complement
)
1428 enum machine_mode mode
;
1429 int bitpos
, bitsize
, complement
;
1431 HOST_WIDE_INT masklow
, maskhigh
;
1433 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1434 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1438 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1439 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1440 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1442 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1445 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1447 if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1448 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1449 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1455 maskhigh
= ~maskhigh
;
1459 return immed_double_const (masklow
, maskhigh
, mode
);
1462 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1463 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1466 lshift_value (mode
, value
, bitpos
, bitsize
)
1467 enum machine_mode mode
;
1469 int bitpos
, bitsize
;
1471 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1472 HOST_WIDE_INT low
, high
;
1474 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1475 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1477 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1480 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1485 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1488 return immed_double_const (low
, high
, mode
);
1491 /* Extract a bit field that is split across two words
1492 and return an RTX for the result.
1494 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1495 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1496 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1498 ALIGN is the known alignment of OP0, measured in bytes.
1499 This is also the size of the memory objects to be used. */
1502 extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
, align
)
1504 int bitsize
, bitpos
, unsignedp
, align
;
1506 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1508 int unit
= MIN (align
* BITS_PER_UNIT
, BITS_PER_WORD
);
1513 while (bitsdone
< bitsize
)
1520 offset
= (bitpos
+ bitsdone
) / unit
;
1521 thispos
= (bitpos
+ bitsdone
) % unit
;
1523 /* THISSIZE must not overrun a word boundary. Otherwise,
1524 extract_fixed_bit_field will call us again, and we will mutually
1526 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1527 thissize
= MIN (thissize
, unit
- thispos
);
1529 /* If OP0 is a register, then handle OFFSET here.
1531 When handling multiword bitfields, extract_bit_field may pass
1532 down a word_mode SUBREG of a larger REG for a bitfield that actually
1533 crosses a word boundary. Thus, for a SUBREG, we must find
1534 the current word starting from the base register. */
1535 if (GET_CODE (op0
) == SUBREG
)
1537 word
= operand_subword_force (SUBREG_REG (op0
),
1538 SUBREG_WORD (op0
) + offset
,
1539 GET_MODE (SUBREG_REG (op0
)));
1542 else if (GET_CODE (op0
) == REG
)
1544 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1553 /* Extract the parts in bit-counting order,
1554 whose meaning is determined by BYTES_PER_UNIT.
1555 OFFSET is in UNITs, and UNIT is in bits.
1556 extract_fixed_bit_field wants offset in bytes. */
1557 part
= extract_fixed_bit_field (word_mode
, word
,
1558 offset
* unit
/ BITS_PER_UNIT
,
1559 thissize
, thispos
, 0, 1, align
);
1560 bitsdone
+= thissize
;
1562 /* Shift this part into place for the result. */
1563 #if BYTES_BIG_ENDIAN
1564 if (bitsize
!= bitsdone
)
1565 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1566 build_int_2 (bitsize
- bitsdone
, 0), 0, 1);
1568 if (bitsdone
!= thissize
)
1569 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1570 build_int_2 (bitsdone
- thissize
, 0), 0, 1);
1576 /* Combine the parts with bitwise or. This works
1577 because we extracted each part as an unsigned bit field. */
1578 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1584 /* Unsigned bit field: we are done. */
1587 /* Signed bit field: sign-extend with two arithmetic shifts. */
1588 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1589 build_int_2 (BITS_PER_WORD
- bitsize
, 0),
1591 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1592 build_int_2 (BITS_PER_WORD
- bitsize
, 0), NULL_RTX
, 0);
1595 /* Add INC into TARGET. */
1598 expand_inc (target
, inc
)
1601 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
1603 target
, 0, OPTAB_LIB_WIDEN
);
1604 if (value
!= target
)
1605 emit_move_insn (target
, value
);
1608 /* Subtract DEC from TARGET. */
1611 expand_dec (target
, dec
)
1614 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
1616 target
, 0, OPTAB_LIB_WIDEN
);
1617 if (value
!= target
)
1618 emit_move_insn (target
, value
);
1621 /* Output a shift instruction for expression code CODE,
1622 with SHIFTED being the rtx for the value to shift,
1623 and AMOUNT the tree for the amount to shift by.
1624 Store the result in the rtx TARGET, if that is convenient.
1625 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1626 Return the rtx for where the value is. */
1629 expand_shift (code
, mode
, shifted
, amount
, target
, unsignedp
)
1630 enum tree_code code
;
1631 register enum machine_mode mode
;
1634 register rtx target
;
1637 register rtx op1
, temp
= 0;
1638 register int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
1639 register int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
1642 /* Previously detected shift-counts computed by NEGATE_EXPR
1643 and shifted in the other direction; but that does not work
1646 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
1648 #if SHIFT_COUNT_TRUNCATED
1649 if (SHIFT_COUNT_TRUNCATED
1650 && GET_CODE (op1
) == CONST_INT
1651 && (unsigned HOST_WIDE_INT
) INTVAL (op1
) >= GET_MODE_BITSIZE (mode
))
1652 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
1653 % GET_MODE_BITSIZE (mode
));
1656 if (op1
== const0_rtx
)
1659 for (try = 0; temp
== 0 && try < 3; try++)
1661 enum optab_methods methods
;
1664 methods
= OPTAB_DIRECT
;
1666 methods
= OPTAB_WIDEN
;
1668 methods
= OPTAB_LIB_WIDEN
;
1672 /* Widening does not work for rotation. */
1673 if (methods
== OPTAB_WIDEN
)
1675 else if (methods
== OPTAB_LIB_WIDEN
)
1677 /* If we are rotating by a constant that is valid and
1678 we have been unable to open-code this by a rotation,
1679 do it as the IOR of two shifts. I.e., to rotate A
1680 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1681 where C is the bitsize of A.
1683 It is theoretically possible that the target machine might
1684 not be able to perform either shift and hence we would
1685 be making two libcalls rather than just the one for the
1686 shift (similarly if IOR could not be done). We will allow
1687 this extremely unlikely lossage to avoid complicating the
1690 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) > 0
1691 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
1693 rtx subtarget
= target
== shifted
? 0 : target
;
1696 = build_int_2 (GET_MODE_BITSIZE (mode
) - INTVAL (op1
), 0);
1698 shifted
= force_reg (mode
, shifted
);
1700 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
1701 mode
, shifted
, amount
, subtarget
, 1);
1702 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
1703 mode
, shifted
, other_amount
, 0, 1);
1704 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
1705 unsignedp
, methods
);
1708 methods
= OPTAB_LIB
;
1711 temp
= expand_binop (mode
,
1712 left
? rotl_optab
: rotr_optab
,
1713 shifted
, op1
, target
, unsignedp
, methods
);
1715 /* If we don't have the rotate, but we are rotating by a constant
1716 that is in range, try a rotate in the opposite direction. */
1718 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
1719 && INTVAL (op1
) > 0 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
1720 temp
= expand_binop (mode
,
1721 left
? rotr_optab
: rotl_optab
,
1723 GEN_INT (GET_MODE_BITSIZE (mode
)
1725 target
, unsignedp
, methods
);
1728 temp
= expand_binop (mode
,
1729 left
? ashl_optab
: lshr_optab
,
1730 shifted
, op1
, target
, unsignedp
, methods
);
1732 /* Do arithmetic shifts.
1733 Also, if we are going to widen the operand, we can just as well
1734 use an arithmetic right-shift instead of a logical one. */
1735 if (temp
== 0 && ! rotate
1736 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
1738 enum optab_methods methods1
= methods
;
1740 /* If trying to widen a log shift to an arithmetic shift,
1741 don't accept an arithmetic shift of the same size. */
1743 methods1
= OPTAB_MUST_WIDEN
;
1745 /* Arithmetic shift */
1747 temp
= expand_binop (mode
,
1748 left
? ashl_optab
: ashr_optab
,
1749 shifted
, op1
, target
, unsignedp
, methods1
);
1753 /* We can do a logical (unsigned) right shift with a bit-field
1754 extract insn. But first check if one of the above methods worked. */
1758 if (unsignedp
&& code
== RSHIFT_EXPR
&& ! BITS_BIG_ENDIAN
&& HAVE_extzv
)
1760 enum machine_mode output_mode
1761 = insn_operand_mode
[(int) CODE_FOR_extzv
][0];
1763 if ((methods
== OPTAB_DIRECT
&& mode
== output_mode
)
1764 || (methods
== OPTAB_WIDEN
1765 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (output_mode
)))
1767 rtx shifted1
= convert_modes (output_mode
, mode
,
1768 protect_from_queue (shifted
, 0),
1770 enum machine_mode length_mode
1771 = insn_operand_mode
[(int) CODE_FOR_extzv
][2];
1772 enum machine_mode pos_mode
1773 = insn_operand_mode
[(int) CODE_FOR_extzv
][3];
1775 rtx last
= get_last_insn ();
1781 target1
= protect_from_queue (target
, 1);
1783 /* We define extract insns as having OUTPUT_MODE in a register
1784 and the mode of operand 1 in memory. Since we want
1785 OUTPUT_MODE, we will always force the operand into a
1786 register. At some point we might want to support MEM
1788 shifted1
= force_reg (output_mode
, shifted1
);
1790 /* If we don't have or cannot use a suggested target,
1791 make a place for the result, in the proper mode. */
1792 if (methods
== OPTAB_WIDEN
|| target1
== 0
1793 || ! ((*insn_operand_predicate
[(int) CODE_FOR_extzv
][0])
1794 (target1
, output_mode
)))
1795 target1
= gen_reg_rtx (output_mode
);
1797 xop1
= protect_from_queue (xop1
, 0);
1798 xop1
= convert_modes (pos_mode
, TYPE_MODE (TREE_TYPE (amount
)),
1799 xop1
, TREE_UNSIGNED (TREE_TYPE (amount
)));
1801 /* If this machine's extzv insists on a register for
1802 operand 3 (position), arrange for that. */
1803 if (! ((*insn_operand_predicate
[(int) CODE_FOR_extzv
][3])
1805 xop1
= force_reg (pos_mode
, xop1
);
1807 /* WIDTH gets the width of the bit field to extract:
1808 wordsize minus # bits to shift by. */
1809 if (GET_CODE (xop1
) == CONST_INT
)
1810 width
= GEN_INT (GET_MODE_BITSIZE (mode
) - INTVAL (op1
));
1813 /* Now get the width in the proper mode. */
1814 op1
= protect_from_queue (op1
, 0);
1815 width
= convert_to_mode (length_mode
, op1
,
1816 TREE_UNSIGNED (TREE_TYPE (amount
)));
1818 width
= expand_binop (length_mode
, sub_optab
,
1819 GEN_INT (GET_MODE_BITSIZE (mode
)),
1820 width
, NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
1823 /* If this machine's extzv insists on a register for
1824 operand 2 (length), arrange for that. */
1825 if (! ((*insn_operand_predicate
[(int) CODE_FOR_extzv
][2])
1826 (width
, length_mode
)))
1827 width
= force_reg (length_mode
, width
);
1829 /* Now extract with WIDTH, omitting OP1 least sig bits. */
1830 pat
= gen_extzv (target1
, shifted1
, width
, xop1
);
1834 temp
= convert_to_mode (mode
, target1
, 1);
1837 delete_insns_since (last
);
1840 /* Can also do logical shift with signed bit-field extract
1841 followed by inserting the bit-field at a different position.
1842 That strategy is not yet implemented. */
1844 #endif /* HAVE_extzv */
1852 enum alg_code
{ alg_zero
, alg_m
, alg_shift
,
1853 alg_add_t_m2
, alg_sub_t_m2
,
1854 alg_add_factor
, alg_sub_factor
,
1855 alg_add_t2_m
, alg_sub_t2_m
,
1856 alg_add
, alg_subtract
, alg_factor
, alg_shiftop
};
1858 /* This structure records a sequence of operations.
1859 `ops' is the number of operations recorded.
1860 `cost' is their total cost.
1861 The operations are stored in `op' and the corresponding
1862 logarithms of the integer coefficients in `log'.
1864 These are the operations:
1865 alg_zero total := 0;
1866 alg_m total := multiplicand;
1867 alg_shift total := total * coeff
1868 alg_add_t_m2 total := total + multiplicand * coeff;
1869 alg_sub_t_m2 total := total - multiplicand * coeff;
1870 alg_add_factor total := total * coeff + total;
1871 alg_sub_factor total := total * coeff - total;
1872 alg_add_t2_m total := total * coeff + multiplicand;
1873 alg_sub_t2_m total := total * coeff - multiplicand;
1875 The first operand must be either alg_zero or alg_m. */
1881 /* The size of the OP and LOG fields are not directly related to the
1882 word size, but the worst-case algorithms will be if we have few
1883 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
1884 In that case we will generate shift-by-2, add, shift-by-2, add,...,
1885 in total wordsize operations. */
1886 enum alg_code op
[MAX_BITS_PER_WORD
];
1887 char log
[MAX_BITS_PER_WORD
];
1890 /* Compute and return the best algorithm for multiplying by T.
1891 The algorithm must cost less than cost_limit
1892 If retval.cost >= COST_LIMIT, no algorithm was found and all
1893 other field of the returned struct are undefined. */
1896 synth_mult (alg_out
, t
, cost_limit
)
1897 struct algorithm
*alg_out
;
1898 unsigned HOST_WIDE_INT t
;
1902 struct algorithm
*alg_in
, *best_alg
;
1904 unsigned HOST_WIDE_INT q
;
1906 /* Indicate that no algorithm is yet found. If no algorithm
1907 is found, this value will be returned and indicate failure. */
1908 alg_out
->cost
= cost_limit
;
1910 if (cost_limit
<= 0)
1913 /* t == 1 can be done in zero cost. */
1918 alg_out
->op
[0] = alg_m
;
1922 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
1926 if (zero_cost
>= cost_limit
)
1931 alg_out
->cost
= zero_cost
;
1932 alg_out
->op
[0] = alg_zero
;
1937 /* We'll be needing a couple extra algorithm structures now. */
1939 alg_in
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
1940 best_alg
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
1942 /* If we have a group of zero bits at the low-order part of T, try
1943 multiplying by the remaining bits and then doing a shift. */
1947 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
1949 cost
= shift_cost
[m
];
1950 synth_mult (alg_in
, q
, cost_limit
- cost
);
1952 cost
+= alg_in
->cost
;
1953 if (cost
< cost_limit
)
1955 struct algorithm
*x
;
1956 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
1957 best_alg
->log
[best_alg
->ops
] = m
;
1958 best_alg
->op
[best_alg
->ops
] = alg_shift
;
1963 /* If we have an odd number, add or subtract one. */
1966 unsigned HOST_WIDE_INT w
;
1968 for (w
= 1; (w
& t
) != 0; w
<<= 1)
1971 /* Reject the case where t is 3.
1972 Thus we prefer addition in that case. */
1975 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
1978 synth_mult (alg_in
, t
+ 1, cost_limit
- cost
);
1980 cost
+= alg_in
->cost
;
1981 if (cost
< cost_limit
)
1983 struct algorithm
*x
;
1984 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
1985 best_alg
->log
[best_alg
->ops
] = 0;
1986 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
1992 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
1995 synth_mult (alg_in
, t
- 1, cost_limit
- cost
);
1997 cost
+= alg_in
->cost
;
1998 if (cost
< cost_limit
)
2000 struct algorithm
*x
;
2001 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2002 best_alg
->log
[best_alg
->ops
] = 0;
2003 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2009 /* Look for factors of t of the form
2010 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2011 If we find such a factor, we can multiply by t using an algorithm that
2012 multiplies by q, shift the result by m and add/subtract it to itself.
2014 We search for large factors first and loop down, even if large factors
2015 are less probable than small; if we find a large factor we will find a
2016 good sequence quickly, and therefore be able to prune (by decreasing
2017 COST_LIMIT) the search. */
2019 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2021 unsigned HOST_WIDE_INT d
;
2023 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2024 if (t
% d
== 0 && t
> d
)
2026 cost
= MIN (shiftadd_cost
[m
], add_cost
+ shift_cost
[m
]);
2027 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2029 cost
+= alg_in
->cost
;
2030 if (cost
< cost_limit
)
2032 struct algorithm
*x
;
2033 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2034 best_alg
->log
[best_alg
->ops
] = m
;
2035 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2038 /* Other factors will have been taken care of in the recursion. */
2042 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2043 if (t
% d
== 0 && t
> d
)
2045 cost
= MIN (shiftsub_cost
[m
], add_cost
+ shift_cost
[m
]);
2046 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2048 cost
+= alg_in
->cost
;
2049 if (cost
< cost_limit
)
2051 struct algorithm
*x
;
2052 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2053 best_alg
->log
[best_alg
->ops
] = m
;
2054 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2061 /* Try shift-and-add (load effective address) instructions,
2062 i.e. do a*3, a*5, a*9. */
2070 cost
= shiftadd_cost
[m
];
2071 synth_mult (alg_in
, (t
- 1) >> m
, cost_limit
- cost
);
2073 cost
+= alg_in
->cost
;
2074 if (cost
< cost_limit
)
2076 struct algorithm
*x
;
2077 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2078 best_alg
->log
[best_alg
->ops
] = m
;
2079 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2089 cost
= shiftsub_cost
[m
];
2090 synth_mult (alg_in
, (t
+ 1) >> m
, cost_limit
- cost
);
2092 cost
+= alg_in
->cost
;
2093 if (cost
< cost_limit
)
2095 struct algorithm
*x
;
2096 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2097 best_alg
->log
[best_alg
->ops
] = m
;
2098 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2104 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2105 we have not found any algorithm. */
2106 if (cost_limit
== alg_out
->cost
)
2109 /* If we are getting a too long sequence for `struct algorithm'
2110 to record, make this search fail. */
2111 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2114 /* Copy the algorithm from temporary space to the space at alg_out.
2115 We avoid using structure assignment because the majority of
2116 best_alg is normally undefined, and this is a critical function. */
2117 alg_out
->ops
= best_alg
->ops
+ 1;
2118 alg_out
->cost
= cost_limit
;
2119 bcopy (best_alg
->op
, alg_out
->op
, alg_out
->ops
* sizeof *alg_out
->op
);
2120 bcopy (best_alg
->log
, alg_out
->log
, alg_out
->ops
* sizeof *alg_out
->log
);
2123 /* Perform a multiplication and return an rtx for the result.
2124 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2125 TARGET is a suggestion for where to store the result (an rtx).
2127 We check specially for a constant integer as OP1.
2128 If you want this check for OP0 as well, then before calling
2129 you should swap the two operands if OP0 would be constant. */
2132 expand_mult (mode
, op0
, op1
, target
, unsignedp
)
2133 enum machine_mode mode
;
2134 register rtx op0
, op1
, target
;
2137 rtx const_op1
= op1
;
2139 /* If we are multiplying in DImode, it may still be a win
2140 to try to work with shifts and adds. */
2141 if (GET_CODE (op1
) == CONST_DOUBLE
2142 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
2143 && HOST_BITS_PER_INT
<= BITS_PER_WORD
)
2145 if ((CONST_DOUBLE_HIGH (op1
) == 0 && CONST_DOUBLE_LOW (op1
) >= 0)
2146 || (CONST_DOUBLE_HIGH (op1
) == -1 && CONST_DOUBLE_LOW (op1
) < 0))
2147 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2150 /* We used to test optimize here, on the grounds that it's better to
2151 produce a smaller program when -O is not used.
2152 But this causes such a terrible slowdown sometimes
2153 that it seems better to use synth_mult always. */
2155 if (GET_CODE (const_op1
) == CONST_INT
)
2157 struct algorithm alg
;
2158 struct algorithm neg_alg
;
2160 HOST_WIDE_INT val
= INTVAL (op1
);
2161 HOST_WIDE_INT val_so_far
;
2165 /* Try to do the computation two ways: multiply by the negative of OP1
2166 and then negate, or do the multiplication directly. The latter is
2167 usually faster for positive numbers and the former for negative
2168 numbers, but the opposite can be faster if the original value
2169 has a factor of 2**m +/- 1, while the negated value does not or
2172 mult_cost
= rtx_cost (gen_rtx (MULT
, mode
, op0
, op1
), SET
);
2173 mult_cost
= MIN (12 * add_cost
, mult_cost
);
2175 synth_mult (&alg
, val
, mult_cost
);
2176 synth_mult (&neg_alg
, - val
,
2177 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - negate_cost
);
2179 if (neg_alg
.cost
+ negate_cost
< alg
.cost
)
2180 alg
= neg_alg
, negate
= 1;
2182 if (alg
.cost
< mult_cost
)
2184 /* We found something cheaper than a multiply insn. */
2188 op0
= protect_from_queue (op0
, 0);
2190 /* Avoid referencing memory over and over.
2191 For speed, but also for correctness when mem is volatile. */
2192 if (GET_CODE (op0
) == MEM
)
2193 op0
= force_reg (mode
, op0
);
2195 /* ACCUM starts out either as OP0 or as a zero, depending on
2196 the first operation. */
2198 if (alg
.op
[0] == alg_zero
)
2200 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2203 else if (alg
.op
[0] == alg_m
)
2205 accum
= copy_to_mode_reg (mode
, op0
);
2211 for (opno
= 1; opno
< alg
.ops
; opno
++)
2213 int log
= alg
.log
[opno
];
2214 int preserve
= preserve_subexpressions_p ();
2215 rtx shift_subtarget
= preserve
? 0 : accum
;
2216 rtx add_target
= opno
== alg
.ops
- 1 && target
!= 0 ? target
: 0;
2217 rtx accum_target
= preserve
? 0 : accum
;
2219 switch (alg
.op
[opno
])
2222 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2223 build_int_2 (log
, 0), NULL_RTX
, 0);
2228 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2229 build_int_2 (log
, 0), NULL_RTX
, 0);
2230 accum
= force_operand (gen_rtx (PLUS
, mode
, accum
, tem
),
2231 add_target
? add_target
: accum_target
);
2232 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2236 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2237 build_int_2 (log
, 0), NULL_RTX
, 0);
2238 accum
= force_operand (gen_rtx (MINUS
, mode
, accum
, tem
),
2239 add_target
? add_target
: accum_target
);
2240 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2244 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2245 build_int_2 (log
, 0), shift_subtarget
,
2247 accum
= force_operand (gen_rtx (PLUS
, mode
, accum
, op0
),
2248 add_target
? add_target
: accum_target
);
2249 val_so_far
= (val_so_far
<< log
) + 1;
2253 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2254 build_int_2 (log
, 0), shift_subtarget
,
2256 accum
= force_operand (gen_rtx (MINUS
, mode
, accum
, op0
),
2257 add_target
? add_target
: accum_target
);
2258 val_so_far
= (val_so_far
<< log
) - 1;
2261 case alg_add_factor
:
2262 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2263 build_int_2 (log
, 0), NULL_RTX
, 0);
2264 accum
= force_operand (gen_rtx (PLUS
, mode
, accum
, tem
),
2265 add_target
? add_target
: accum_target
);
2266 val_so_far
+= val_so_far
<< log
;
2269 case alg_sub_factor
:
2270 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2271 build_int_2 (log
, 0), NULL_RTX
, 0);
2272 accum
= force_operand (gen_rtx (MINUS
, mode
, tem
, accum
),
2273 (add_target
? add_target
2274 : preserve
? 0 : tem
));
2275 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2282 /* Write a REG_EQUAL note on the last insn so that we can cse
2283 multiplication sequences. */
2285 insn
= get_last_insn ();
2287 = gen_rtx (EXPR_LIST
, REG_EQUAL
,
2288 gen_rtx (MULT
, mode
, op0
, GEN_INT (val_so_far
)),
2294 val_so_far
= - val_so_far
;
2295 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2298 if (val
!= val_so_far
)
2305 /* This used to use umul_optab if unsigned, but for non-widening multiply
2306 there is no difference between signed and unsigned. */
2307 op0
= expand_binop (mode
, smul_optab
,
2308 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
2314 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2315 if that is convenient, and returning where the result is.
2316 You may request either the quotient or the remainder as the result;
2317 specify REM_FLAG nonzero to get the remainder.
2319 CODE is the expression code for which kind of division this is;
2320 it controls how rounding is done. MODE is the machine mode to use.
2321 UNSIGNEDP nonzero means do unsigned division. */
2323 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2324 and then correct it by or'ing in missing high bits
2325 if result of ANDI is nonzero.
2326 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2327 This could optimize to a bfexts instruction.
2328 But C doesn't use these operations, so their optimizations are
2332 expand_divmod (rem_flag
, code
, mode
, op0
, op1
, target
, unsignedp
)
2334 enum tree_code code
;
2335 enum machine_mode mode
;
2336 register rtx op0
, op1
, target
;
2339 register rtx result
= 0;
2340 enum machine_mode compute_mode
;
2343 int can_clobber_op0
;
2344 int mod_insn_no_good
= 0;
2345 rtx adjusted_op0
= op0
;
2346 optab optab1
, optab2
;
2348 /* We shouldn't be called with op1 == const1_rtx, but some of the
2349 code below will malfunction if we are, so check here and handle
2350 the special case if so. */
2351 if (op1
== const1_rtx
)
2352 return rem_flag
? const0_rtx
: op0
;
2355 /* Don't use the function value register as a target
2356 since we have to read it as well as write it,
2357 and function-inlining gets confused by this. */
2358 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
2359 /* Don't clobber an operand while doing a multi-step calculation. */
2361 && (reg_mentioned_p (target
, op0
)
2362 || (GET_CODE (op0
) == MEM
&& GET_CODE (target
) == MEM
)))
2363 || reg_mentioned_p (target
, op1
)
2364 || (GET_CODE (op1
) == MEM
&& GET_CODE (target
) == MEM
)))
2367 /* See if we are dividing by 2**log, and hence will do it by shifting,
2368 which is really floor-division, or if we will really do a divide,
2369 and we assume that is trunc-division.
2371 We must correct the dividend by adding or subtracting something
2372 based on the divisor, in order to do the kind of rounding specified
2373 by CODE. The correction depends on what kind of rounding is actually
2374 available, and that depends on whether we will shift or divide.
2376 In many of these cases it is possible to perform the operation by a
2377 clever series of logical operations (shifts and/or exclusive-ors).
2378 Although avoiding the jump has the advantage that it extends the basic
2379 block and allows further optimization, the branch-free code is normally
2380 at least one instruction longer in the (most common) case where the
2381 dividend is non-negative. Performance measurements of the two
2382 alternatives show that the branch-free code is slightly faster on the
2383 IBM ROMP but slower on CISC processors (significantly slower on the
2384 VAX). Accordingly, the jump code has been retained when BRANCH_COST
2387 On machines where the jump code is slower, the cost of a DIV or MOD
2388 operation can be set small (less than twice that of an addition); in
2389 that case, we pretend that we don't have a power of two and perform
2390 a normal division or modulus operation. */
2392 if (GET_CODE (op1
) == CONST_INT
2393 && ! ((code
== TRUNC_MOD_EXPR
|| code
== TRUNC_DIV_EXPR
)
2395 && (rem_flag
? smod_pow2_cheap
: sdiv_pow2_cheap
)))
2396 log
= exact_log2 (INTVAL (op1
));
2398 /* Get the mode in which to perform this computation. Normally it will
2399 be MODE, but sometimes we can't do the desired operation in MODE.
2400 If so, pick a wider mode in which we can do the operation. Convert
2401 to that mode at the start to avoid repeated conversions.
2403 First see what operations we need. These depend on the expression
2404 we are evaluating. (We assume that divxx3 insns exist under the
2405 same conditions that modxx3 insns and that these insns don't normally
2406 fail. If these assumptions are not correct, we may generate less
2407 efficient code in some cases.)
2409 Then see if we find a mode in which we can open-code that operation
2410 (either a division, modulus, or shift). Finally, check for the smallest
2411 mode for which we can do the operation with a library call. */
2413 optab1
= (log
>= 0 ? (unsignedp
? lshr_optab
: ashr_optab
)
2414 : (unsignedp
? udiv_optab
: sdiv_optab
));
2415 optab2
= (log
>= 0 ? optab1
: (unsignedp
? udivmod_optab
: sdivmod_optab
));
2417 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
2418 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
2419 if (optab1
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
2420 || optab2
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
)
2423 if (compute_mode
== VOIDmode
)
2424 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
2425 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
2426 if (optab1
->handlers
[(int) compute_mode
].libfunc
2427 || optab2
->handlers
[(int) compute_mode
].libfunc
)
2430 /* If we still couldn't find a mode, use MODE, but we'll probably abort
2432 if (compute_mode
== VOIDmode
)
2433 compute_mode
= mode
;
2435 size
= GET_MODE_BITSIZE (compute_mode
);
2437 /* If OP0 is a register that is used as the target, we can modify
2438 it in place; otherwise, we have to ensure we copy OP0 before
2440 can_clobber_op0
= (GET_CODE (op0
) == REG
&& op0
== target
);
2442 /* Now convert to the best mode to use. Normally show we made a copy of OP0
2443 and hence we can clobber it (we cannot use a SUBREG to widen
2444 something), but check that the conversion wasn't a no-op due to
2446 if (compute_mode
!= mode
)
2448 adjusted_op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
2449 can_clobber_op0
= ! (GET_CODE (op0
) == SUBREG
2450 && SUBREG_REG (op0
) == adjusted_op0
);
2452 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
2455 /* If we are computing the remainder and one of the operands is a volatile
2456 MEM, copy it into a register. */
2458 if (rem_flag
&& GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
))
2459 adjusted_op0
= op0
= force_reg (compute_mode
, op0
), can_clobber_op0
= 1;
2460 if (rem_flag
&& GET_CODE (op1
) == MEM
&& MEM_VOLATILE_P (op1
))
2461 op1
= force_reg (compute_mode
, op1
);
2463 /* If we are computing the remainder, op0 will be needed later to calculate
2464 X - Y * (X / Y), therefore cannot be clobbered. */
2466 can_clobber_op0
= 0;
2468 /* See if we will need to modify ADJUSTED_OP0. Note that this code
2469 must agree with that in the switch below. */
2470 if (((code
== TRUNC_MOD_EXPR
|| code
== TRUNC_DIV_EXPR
)
2471 && log
>= 0 && ! unsignedp
)
2472 || ((code
== FLOOR_MOD_EXPR
|| code
== FLOOR_DIV_EXPR
)
2473 && log
< 0 && ! unsignedp
)
2474 || code
== CEIL_MOD_EXPR
|| code
== CEIL_DIV_EXPR
2475 || code
== ROUND_MOD_EXPR
|| code
== ROUND_DIV_EXPR
)
2477 /* If we want the remainder, we may need to use OP0, so make sure
2478 it and ADJUSTED_OP0 are in different registers. We force OP0
2479 to a register in case it has any queued subexpressions, because
2480 emit_cmp_insn will call emit_queue.
2482 If we don't want the remainder, we aren't going to use OP0 anymore.
2483 However, if we cannot clobber OP0 (and hence ADJUSTED_OP0), we must
2484 make a copy of it, hopefully to TARGET.
2486 This code is somewhat tricky. Note that if REM_FLAG is nonzero,
2487 CAN_CLOBBER_OP0 will be zero and we know that OP0 cannot
2491 op0
= force_reg (compute_mode
, op0
);
2493 if (! can_clobber_op0
)
2495 if (target
&& GET_MODE (target
) == compute_mode
)
2496 adjusted_op0
= target
;
2499 adjusted_op0
= copy_to_suggested_reg (op0
, adjusted_op0
,
2504 /* Adjust ADJUSTED_OP0 as described above. Unless CAN_CLOBBER_OP0
2505 is now non-zero, OP0 will retain it's original value. */
2509 case TRUNC_MOD_EXPR
:
2510 case TRUNC_DIV_EXPR
:
2511 if (log
>= 0 && ! unsignedp
)
2513 /* Here we need to add OP1-1 if OP0 is negative, 0 otherwise.
2514 This can be computed without jumps by arithmetically shifting
2515 OP0 right LOG-1 places and then shifting right logically
2516 SIZE-LOG bits. The resulting value is unconditionally added
2519 If OP0 cannot be modified in place, copy it, possibly to
2520 TARGET. Note that we will have previously only allowed
2521 it to be modified in place if it is a register, so that
2522 after this `if', ADJUSTED_OP0 is known to be a
2524 if (log
== 1 || BRANCH_COST
>= 3)
2528 temp
= expand_shift (RSHIFT_EXPR
, compute_mode
, adjusted_op0
,
2529 build_int_2 (log
- 1, 0), NULL_RTX
, 0);
2531 /* We cannot allow TEMP to be ADJUSTED_OP0 here. */
2532 temp
= expand_shift (RSHIFT_EXPR
, compute_mode
, temp
,
2533 build_int_2 (size
- log
, 0),
2534 temp
!= adjusted_op0
? temp
: NULL_RTX
, 1);
2536 adjusted_op0
= expand_binop (compute_mode
, add_optab
,
2537 adjusted_op0
, temp
, adjusted_op0
,
2538 0, OPTAB_LIB_WIDEN
);
2542 rtx label
= gen_label_rtx ();
2544 emit_cmp_insn (adjusted_op0
, const0_rtx
, GE
,
2545 NULL_RTX
, compute_mode
, 0, 0);
2546 emit_jump_insn (gen_bge (label
));
2547 expand_inc (adjusted_op0
, plus_constant (op1
, -1));
2550 mod_insn_no_good
= 1;
2554 case FLOOR_DIV_EXPR
:
2555 case FLOOR_MOD_EXPR
:
2556 if (log
< 0 && ! unsignedp
)
2558 rtx label
= gen_label_rtx ();
2560 emit_cmp_insn (adjusted_op0
, const0_rtx
, GE
,
2561 NULL_RTX
, compute_mode
, 0, 0);
2562 emit_jump_insn (gen_bge (label
));
2563 expand_dec (adjusted_op0
, op1
);
2564 expand_inc (adjusted_op0
, const1_rtx
);
2566 mod_insn_no_good
= 1;
2577 label
= gen_label_rtx ();
2578 emit_cmp_insn (adjusted_op0
, const0_rtx
, LE
,
2579 NULL_RTX
, compute_mode
, 0, 0);
2580 emit_jump_insn (gen_ble (label
));
2582 expand_inc (adjusted_op0
, op1
);
2583 expand_dec (adjusted_op0
, const1_rtx
);
2588 adjusted_op0
= expand_binop (compute_mode
, add_optab
,
2589 adjusted_op0
, plus_constant (op1
, -1),
2590 adjusted_op0
, 0, OPTAB_LIB_WIDEN
);
2592 mod_insn_no_good
= 1;
2595 case ROUND_DIV_EXPR
:
2596 case ROUND_MOD_EXPR
:
2599 op1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op1
,
2600 integer_one_node
, NULL_RTX
, 0);
2603 if (BRANCH_COST
>= 2)
2605 /* Negate OP1 if OP0 < 0. Do this by computing a temporary
2606 that has all bits equal to the sign bit and exclusive
2607 or-ing it with OP1. */
2608 rtx temp
= expand_shift (RSHIFT_EXPR
, compute_mode
,
2610 build_int_2 (size
- 1, 0),
2612 op1
= expand_binop (compute_mode
, xor_optab
, op1
, temp
, op1
,
2613 unsignedp
, OPTAB_LIB_WIDEN
);
2617 rtx label
= gen_label_rtx ();
2618 emit_cmp_insn (adjusted_op0
, const0_rtx
, GE
, NULL_RTX
,
2619 compute_mode
, 0, 0);
2620 emit_jump_insn (gen_bge (label
));
2621 expand_unop (compute_mode
, neg_optab
, op1
, op1
, 0);
2625 expand_inc (adjusted_op0
, op1
);
2628 expand_inc (adjusted_op0
, GEN_INT (((HOST_WIDE_INT
) 1 << log
) / 2));
2630 mod_insn_no_good
= 1;
2634 if (rem_flag
&& !mod_insn_no_good
)
2636 /* Try to produce the remainder directly */
2638 result
= expand_binop (compute_mode
, and_optab
, adjusted_op0
,
2639 GEN_INT (((HOST_WIDE_INT
) 1 << log
) - 1),
2640 target
, 1, OPTAB_LIB_WIDEN
);
2643 /* See if we can do remainder without a library call. */
2644 result
= sign_expand_binop (mode
, umod_optab
, smod_optab
,
2645 adjusted_op0
, op1
, target
,
2646 unsignedp
, OPTAB_WIDEN
);
2649 /* No luck there. Can we do remainder and divide at once
2650 without a library call? */
2651 result
= gen_reg_rtx (compute_mode
);
2652 if (! expand_twoval_binop (unsignedp
2653 ? udivmod_optab
: sdivmod_optab
,
2655 NULL_RTX
, result
, unsignedp
))
2662 return gen_lowpart (mode
, result
);
2664 /* Produce the quotient. */
2666 result
= expand_shift (RSHIFT_EXPR
, compute_mode
, adjusted_op0
,
2667 build_int_2 (log
, 0), target
, unsignedp
);
2668 else if (rem_flag
&& !mod_insn_no_good
)
2669 /* If producing quotient in order to subtract for remainder,
2670 and a remainder subroutine would be ok,
2671 don't use a divide subroutine. */
2672 result
= sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
2673 adjusted_op0
, op1
, NULL_RTX
, unsignedp
,
2677 /* Try a quotient insn, but not a library call. */
2678 result
= sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
2680 rem_flag
? NULL_RTX
: target
,
2681 unsignedp
, OPTAB_WIDEN
);
2684 /* No luck there. Try a quotient-and-remainder insn,
2685 keeping the quotient alone. */
2686 result
= gen_reg_rtx (compute_mode
);
2687 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
2689 result
, NULL_RTX
, unsignedp
))
2693 /* If still no luck, use a library call. */
2695 result
= sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
2697 rem_flag
? NULL_RTX
: target
,
2698 unsignedp
, OPTAB_LIB_WIDEN
);
2701 /* If we really want the remainder, get it by subtraction. */
2705 /* No divide instruction either. Use library for remainder. */
2706 result
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
2708 unsignedp
, OPTAB_LIB_WIDEN
);
2711 /* We divided. Now finish doing X - Y * (X / Y). */
2712 result
= expand_mult (compute_mode
, result
, op1
, target
, unsignedp
);
2713 if (! result
) abort ();
2714 result
= expand_binop (compute_mode
, sub_optab
, op0
,
2715 result
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
2722 return gen_lowpart (mode
, result
);
2725 /* Return a tree node with data type TYPE, describing the value of X.
2726 Usually this is an RTL_EXPR, if there is no obvious better choice.
2727 X may be an expression, however we only support those expressions
2728 generated by loop.c. */
2737 switch (GET_CODE (x
))
2740 t
= build_int_2 (INTVAL (x
),
2741 TREE_UNSIGNED (type
) || INTVAL (x
) >= 0 ? 0 : -1);
2742 TREE_TYPE (t
) = type
;
2746 if (GET_MODE (x
) == VOIDmode
)
2748 t
= build_int_2 (CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
2749 TREE_TYPE (t
) = type
;
2755 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2756 t
= build_real (type
, d
);
2762 return fold (build (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
2763 make_tree (type
, XEXP (x
, 1))));
2766 return fold (build (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
2767 make_tree (type
, XEXP (x
, 1))));
2770 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
2773 return fold (build (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
2774 make_tree (type
, XEXP (x
, 1))));
2777 return fold (build (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
2778 make_tree (type
, XEXP (x
, 1))));
2781 return fold (convert (type
,
2782 build (RSHIFT_EXPR
, unsigned_type (type
),
2783 make_tree (unsigned_type (type
),
2785 make_tree (type
, XEXP (x
, 1)))));
2788 return fold (convert (type
,
2789 build (RSHIFT_EXPR
, signed_type (type
),
2790 make_tree (signed_type (type
), XEXP (x
, 0)),
2791 make_tree (type
, XEXP (x
, 1)))));
2794 if (TREE_CODE (type
) != REAL_TYPE
)
2795 t
= signed_type (type
);
2799 return fold (convert (type
,
2800 build (TRUNC_DIV_EXPR
, t
,
2801 make_tree (t
, XEXP (x
, 0)),
2802 make_tree (t
, XEXP (x
, 1)))));
2804 t
= unsigned_type (type
);
2805 return fold (convert (type
,
2806 build (TRUNC_DIV_EXPR
, t
,
2807 make_tree (t
, XEXP (x
, 0)),
2808 make_tree (t
, XEXP (x
, 1)))));
2810 t
= make_node (RTL_EXPR
);
2811 TREE_TYPE (t
) = type
;
2812 RTL_EXPR_RTL (t
) = x
;
2813 /* There are no insns to be output
2814 when this rtl_expr is used. */
2815 RTL_EXPR_SEQUENCE (t
) = 0;
2820 /* Return an rtx representing the value of X * MULT + ADD.
2821 TARGET is a suggestion for where to store the result (an rtx).
2822 MODE is the machine mode for the computation.
2823 X and MULT must have mode MODE. ADD may have a different mode.
2824 So can X (defaults to same as MODE).
2825 UNSIGNEDP is non-zero to do unsigned multiplication.
2826 This may emit insns. */
2829 expand_mult_add (x
, target
, mult
, add
, mode
, unsignedp
)
2830 rtx x
, target
, mult
, add
;
2831 enum machine_mode mode
;
2834 tree type
= type_for_mode (mode
, unsignedp
);
2835 tree add_type
= (GET_MODE (add
) == VOIDmode
2836 ? type
: type_for_mode (GET_MODE (add
), unsignedp
));
2837 tree result
= fold (build (PLUS_EXPR
, type
,
2838 fold (build (MULT_EXPR
, type
,
2839 make_tree (type
, x
),
2840 make_tree (type
, mult
))),
2841 make_tree (add_type
, add
)));
2843 return expand_expr (result
, target
, VOIDmode
, 0);
2846 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
2847 and returning TARGET.
2849 If TARGET is 0, a pseudo-register or constant is returned. */
2852 expand_and (op0
, op1
, target
)
2853 rtx op0
, op1
, target
;
2855 enum machine_mode mode
= VOIDmode
;
2858 if (GET_MODE (op0
) != VOIDmode
)
2859 mode
= GET_MODE (op0
);
2860 else if (GET_MODE (op1
) != VOIDmode
)
2861 mode
= GET_MODE (op1
);
2863 if (mode
!= VOIDmode
)
2864 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
2865 else if (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) == CONST_INT
)
2866 tem
= GEN_INT (INTVAL (op0
) & INTVAL (op1
));
2872 else if (tem
!= target
)
2873 emit_move_insn (target
, tem
);
2877 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
2878 and storing in TARGET. Normally return TARGET.
2879 Return 0 if that cannot be done.
2881 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
2882 it is VOIDmode, they cannot both be CONST_INT.
2884 UNSIGNEDP is for the case where we have to widen the operands
2885 to perform the operation. It says to use zero-extension.
2887 NORMALIZEP is 1 if we should convert the result to be either zero
2888 or one one. Normalize is -1 if we should convert the result to be
2889 either zero or -1. If NORMALIZEP is zero, the result will be left
2890 "raw" out of the scc insn. */
2893 emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
2897 enum machine_mode mode
;
2902 enum insn_code icode
;
2903 enum machine_mode compare_mode
;
2904 enum machine_mode target_mode
= GET_MODE (target
);
2907 rtx pattern
, comparison
;
2909 if (mode
== VOIDmode
)
2910 mode
= GET_MODE (op0
);
2912 /* If one operand is constant, make it the second one. Only do this
2913 if the other operand is not constant as well. */
2915 if ((CONSTANT_P (op0
) && ! CONSTANT_P (op1
))
2916 || (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) != CONST_INT
))
2921 code
= swap_condition (code
);
2924 /* For some comparisons with 1 and -1, we can convert this to
2925 comparisons with zero. This will often produce more opportunities for
2926 store-flag insns. */
2931 if (op1
== const1_rtx
)
2932 op1
= const0_rtx
, code
= LE
;
2935 if (op1
== constm1_rtx
)
2936 op1
= const0_rtx
, code
= LT
;
2939 if (op1
== const1_rtx
)
2940 op1
= const0_rtx
, code
= GT
;
2943 if (op1
== constm1_rtx
)
2944 op1
= const0_rtx
, code
= GE
;
2947 if (op1
== const1_rtx
)
2948 op1
= const0_rtx
, code
= NE
;
2951 if (op1
== const1_rtx
)
2952 op1
= const0_rtx
, code
= EQ
;
2956 /* From now on, we won't change CODE, so set ICODE now. */
2957 icode
= setcc_gen_code
[(int) code
];
2959 /* If this is A < 0 or A >= 0, we can do this by taking the ones
2960 complement of A (for GE) and shifting the sign bit to the low bit. */
2961 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
2962 && GET_MODE_CLASS (mode
) == MODE_INT
2963 && (normalizep
|| STORE_FLAG_VALUE
== 1
2964 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2965 && (STORE_FLAG_VALUE
2966 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
2970 /* If the result is to be wider than OP0, it is best to convert it
2971 first. If it is to be narrower, it is *incorrect* to convert it
2973 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
2975 op0
= protect_from_queue (op0
, 0);
2976 op0
= convert_modes (target_mode
, mode
, op0
, 0);
2980 if (target_mode
!= mode
)
2984 op0
= expand_unop (mode
, one_cmpl_optab
, op0
, subtarget
, 0);
2986 if (normalizep
|| STORE_FLAG_VALUE
== 1)
2987 /* If we are supposed to produce a 0/1 value, we want to do
2988 a logical shift from the sign bit to the low-order bit; for
2989 a -1/0 value, we do an arithmetic shift. */
2990 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2991 size_int (GET_MODE_BITSIZE (mode
) - 1),
2992 subtarget
, normalizep
!= -1);
2994 if (mode
!= target_mode
)
2995 op0
= convert_modes (target_mode
, mode
, op0
, 0);
3000 if (icode
!= CODE_FOR_nothing
)
3002 /* We think we may be able to do this with a scc insn. Emit the
3003 comparison and then the scc insn.
3005 compare_from_rtx may call emit_queue, which would be deleted below
3006 if the scc insn fails. So call it ourselves before setting LAST. */
3009 last
= get_last_insn ();
3012 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
, 0);
3013 if (GET_CODE (comparison
) == CONST_INT
)
3014 return (comparison
== const0_rtx
? const0_rtx
3015 : normalizep
== 1 ? const1_rtx
3016 : normalizep
== -1 ? constm1_rtx
3019 /* If the code of COMPARISON doesn't match CODE, something is
3020 wrong; we can no longer be sure that we have the operation.
3021 We could handle this case, but it should not happen. */
3023 if (GET_CODE (comparison
) != code
)
3026 /* Get a reference to the target in the proper mode for this insn. */
3027 compare_mode
= insn_operand_mode
[(int) icode
][0];
3029 if (preserve_subexpressions_p ()
3030 || ! (*insn_operand_predicate
[(int) icode
][0]) (subtarget
, compare_mode
))
3031 subtarget
= gen_reg_rtx (compare_mode
);
3033 pattern
= GEN_FCN (icode
) (subtarget
);
3036 emit_insn (pattern
);
3038 /* If we are converting to a wider mode, first convert to
3039 TARGET_MODE, then normalize. This produces better combining
3040 opportunities on machines that have a SIGN_EXTRACT when we are
3041 testing a single bit. This mostly benefits the 68k.
3043 If STORE_FLAG_VALUE does not have the sign bit set when
3044 interpreted in COMPARE_MODE, we can do this conversion as
3045 unsigned, which is usually more efficient. */
3046 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
3048 convert_move (target
, subtarget
,
3049 (GET_MODE_BITSIZE (compare_mode
)
3050 <= HOST_BITS_PER_WIDE_INT
)
3051 && 0 == (STORE_FLAG_VALUE
3052 & ((HOST_WIDE_INT
) 1
3053 << (GET_MODE_BITSIZE (compare_mode
) -1))));
3055 compare_mode
= target_mode
;
3060 /* If we want to keep subexpressions around, don't reuse our
3063 if (preserve_subexpressions_p ())
3066 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
3067 we don't have to do anything. */
3068 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
3070 else if (normalizep
== - STORE_FLAG_VALUE
)
3071 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
3073 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
3074 makes it hard to use a value of just the sign bit due to
3075 ANSI integer constant typing rules. */
3076 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
3077 && (STORE_FLAG_VALUE
3078 & ((HOST_WIDE_INT
) 1
3079 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
3080 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
3081 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
3082 subtarget
, normalizep
== 1);
3083 else if (STORE_FLAG_VALUE
& 1)
3085 op0
= expand_and (op0
, const1_rtx
, subtarget
);
3086 if (normalizep
== -1)
3087 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
3092 /* If we were converting to a smaller mode, do the
3094 if (target_mode
!= compare_mode
)
3096 convert_move (target
, op0
, 0);
3105 delete_insns_since (last
);
3107 subtarget
= target_mode
== mode
? target
: 0;
3109 /* If we reached here, we can't do this with a scc insn. However, there
3110 are some comparisons that can be done directly. For example, if
3111 this is an equality comparison of integers, we can try to exclusive-or
3112 (or subtract) the two operands and use a recursive call to try the
3113 comparison with zero. Don't do any of these cases if branches are
3117 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
3118 && op1
!= const0_rtx
)
3120 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
3124 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
3127 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
3128 mode
, unsignedp
, normalizep
);
3130 delete_insns_since (last
);
3134 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
3135 the constant zero. Reject all other comparisons at this point. Only
3136 do LE and GT if branches are expensive since they are expensive on
3137 2-operand machines. */
3139 if (BRANCH_COST
== 0
3140 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
3141 || (code
!= EQ
&& code
!= NE
3142 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
3145 /* See what we need to return. We can only return a 1, -1, or the
3148 if (normalizep
== 0)
3150 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
3151 normalizep
= STORE_FLAG_VALUE
;
3153 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3154 && (STORE_FLAG_VALUE
3155 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
3161 /* Try to put the result of the comparison in the sign bit. Assume we can't
3162 do the necessary operation below. */
3166 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
3167 the sign bit set. */
3171 /* This is destructive, so SUBTARGET can't be OP0. */
3172 if (rtx_equal_p (subtarget
, op0
))
3175 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
3178 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
3182 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
3183 number of bits in the mode of OP0, minus one. */
3187 if (rtx_equal_p (subtarget
, op0
))
3190 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3191 size_int (GET_MODE_BITSIZE (mode
) - 1),
3193 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
3197 if (code
== EQ
|| code
== NE
)
3199 /* For EQ or NE, one way to do the comparison is to apply an operation
3200 that converts the operand into a positive number if it is non-zero
3201 or zero if it was originally zero. Then, for EQ, we subtract 1 and
3202 for NE we negate. This puts the result in the sign bit. Then we
3203 normalize with a shift, if needed.
3205 Two operations that can do the above actions are ABS and FFS, so try
3206 them. If that doesn't work, and MODE is smaller than a full word,
3207 we can use zero-extension to the wider mode (an unsigned conversion)
3208 as the operation. */
3210 if (abs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3211 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
3212 else if (ffs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3213 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
3214 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3216 op0
= protect_from_queue (op0
, 0);
3217 tem
= convert_modes (word_mode
, mode
, op0
, 1);
3224 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
3227 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
3230 /* If we couldn't do it that way, for NE we can "or" the two's complement
3231 of the value with itself. For EQ, we take the one's complement of
3232 that "or", which is an extra insn, so we only handle EQ if branches
3235 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
3237 if (rtx_equal_p (subtarget
, op0
))
3240 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
3241 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
3244 if (tem
&& code
== EQ
)
3245 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
3249 if (tem
&& normalizep
)
3250 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
3251 size_int (GET_MODE_BITSIZE (mode
) - 1),
3252 tem
, normalizep
== 1);
3254 if (tem
&& GET_MODE (tem
) != target_mode
)
3256 convert_move (target
, tem
, 0);
3261 delete_insns_since (last
);
3265 emit_jump_insn ((*bcc_gen_fctn
[(int) code
]) (label
));
3266 emit_move_insn (target
, const1_rtx
);