1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
45 Here is block diagram of LRA passes:
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56 | Remove |----> ------------>| register | |
57 | scratches | ^ | displacements | |
58 ----------- | ---------------- |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
80 -------------------------
82 To speed up the process:
83 o We process only insns affected by changes on previous
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
98 o data used for assigning (preferred hard regs, costs etc).
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
105 #include "coretypes.h"
107 #include "hard-reg-set.h"
111 #include "insn-config.h"
112 #include "insn-codes.h"
115 #include "addresses.h"
117 #include "function.h"
126 #include "emit-rtl.h"
131 #include "dominance.h"
134 #include "cfgbuild.h"
135 #include "basic-block.h"
137 #include "tree-pass.h"
141 #include "alloc-pool.h"
145 /* Dump bitmap SET with TITLE and BB INDEX. */
147 lra_dump_bitmap_with_title (const char *title
, bitmap set
, int index
)
152 static const int max_nums_on_line
= 10;
154 if (bitmap_empty_p (set
))
156 fprintf (lra_dump_file
, " %s %d:", title
, index
);
157 fprintf (lra_dump_file
, "\n");
158 count
= max_nums_on_line
+ 1;
159 EXECUTE_IF_SET_IN_BITMAP (set
, 0, i
, bi
)
161 if (count
> max_nums_on_line
)
163 fprintf (lra_dump_file
, "\n ");
166 fprintf (lra_dump_file
, " %4u", i
);
169 fprintf (lra_dump_file
, "\n");
172 /* Hard registers currently not available for allocation. It can
173 changed after some hard registers become not eliminable. */
174 HARD_REG_SET lra_no_alloc_regs
;
176 static int get_new_reg_value (void);
177 static void expand_reg_info (void);
178 static void invalidate_insn_recog_data (int);
179 static int get_insn_freq (rtx_insn
*);
180 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
,
183 /* Expand all regno related info needed for LRA. */
185 expand_reg_data (int old
)
189 ira_expand_reg_equiv ();
190 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
191 lra_change_class (i
, ALL_REGS
, " Set", true);
194 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
195 or of VOIDmode, use MD_MODE for the new reg. Initialize its
196 register class to RCLASS. Print message about assigning class
197 RCLASS containing new register name TITLE unless it is NULL. Use
198 attributes of ORIGINAL if it is a register. The created register
199 will have unique held value. */
201 lra_create_new_reg_with_unique_value (machine_mode md_mode
, rtx original
,
202 enum reg_class rclass
, const char *title
)
207 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
209 lra_assert (mode
!= VOIDmode
);
210 new_reg
= gen_reg_rtx (mode
);
211 if (original
== NULL_RTX
|| ! REG_P (original
))
213 if (lra_dump_file
!= NULL
)
214 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
218 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
219 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
220 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
221 REG_POINTER (new_reg
) = REG_POINTER (original
);
222 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
223 if (lra_dump_file
!= NULL
)
224 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
225 REGNO (new_reg
), REGNO (original
));
227 if (lra_dump_file
!= NULL
)
230 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
231 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
232 title
, REGNO (new_reg
));
233 fprintf (lra_dump_file
, "\n");
235 expand_reg_data (max_reg_num ());
236 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
240 /* Analogous to the previous function but also inherits value of
243 lra_create_new_reg (machine_mode md_mode
, rtx original
,
244 enum reg_class rclass
, const char *title
)
249 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
250 if (original
!= NULL_RTX
&& REG_P (original
))
251 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
255 /* Set up for REGNO unique hold value. */
257 lra_set_regno_unique_value (int regno
)
259 lra_reg_info
[regno
].val
= get_new_reg_value ();
262 /* Invalidate INSN related info used by LRA. The info should never be
265 lra_invalidate_insn_data (rtx_insn
*insn
)
267 lra_invalidate_insn_regno_info (insn
);
268 invalidate_insn_recog_data (INSN_UID (insn
));
271 /* Mark INSN deleted and invalidate the insn related info used by
274 lra_set_insn_deleted (rtx_insn
*insn
)
276 lra_invalidate_insn_data (insn
);
277 SET_INSN_DELETED (insn
);
280 /* Delete an unneeded INSN and any previous insns who sole purpose is
281 loading data that is dead in INSN. */
283 lra_delete_dead_insn (rtx_insn
*insn
)
285 rtx_insn
*prev
= prev_real_insn (insn
);
288 /* If the previous insn sets a register that dies in our insn,
290 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
291 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
292 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
293 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
294 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
295 lra_delete_dead_insn (prev
);
297 lra_set_insn_deleted (insn
);
300 /* Emit insn x = y + z. Return NULL if we failed to do it.
301 Otherwise, return the insn. We don't use gen_add3_insn as it might
304 emit_add3_insn (rtx x
, rtx y
, rtx z
)
308 last
= get_last_insn ();
310 if (have_addptr3_insn (x
, y
, z
))
312 rtx_insn
*insn
= gen_addptr3_insn (x
, y
, z
);
314 /* If the target provides an "addptr" pattern it hopefully does
315 for a reason. So falling back to the normal add would be
317 lra_assert (insn
!= NULL_RTX
);
322 rtx_insn
*insn
= emit_insn (gen_rtx_SET (x
, gen_rtx_PLUS (GET_MODE (y
),
324 if (recog_memoized (insn
) < 0)
326 delete_insns_since (last
);
332 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
335 emit_add2_insn (rtx x
, rtx y
)
337 rtx_insn
*insn
= emit_add3_insn (x
, x
, y
);
338 if (insn
== NULL_RTX
)
340 insn
= gen_add2_insn (x
, y
);
341 if (insn
!= NULL_RTX
)
347 /* Target checks operands through operand predicates to recognize an
348 insn. We should have a special precaution to generate add insns
349 which are frequent results of elimination.
351 Emit insns for x = y + z. X can be used to store intermediate
352 values and should be not in Y and Z when we use X to store an
353 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
354 + disp] where base and index are registers, disp and scale are
355 constants. Y should contain base if it is present, Z should
356 contain disp if any. index[*scale] can be part of Y or Z. */
358 lra_emit_add (rtx x
, rtx y
, rtx z
)
362 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
365 rtx_insn
*add3_insn
= emit_add3_insn (x
, y
, z
);
366 old
= max_reg_num ();
367 if (add3_insn
!= NULL
)
371 disp
= a2
= NULL_RTX
;
372 if (GET_CODE (y
) == PLUS
)
386 index_scale
= scale
= NULL_RTX
;
387 if (GET_CODE (a1
) == MULT
)
390 index
= XEXP (a1
, 0);
391 scale
= XEXP (a1
, 1);
394 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
397 index
= XEXP (a2
, 0);
398 scale
= XEXP (a2
, 1);
406 if (! (REG_P (base
) || GET_CODE (base
) == SUBREG
)
407 || (index
!= NULL_RTX
408 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
409 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
410 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
412 /* Probably we have no 3 op add. Last chance is to use 2-op
413 add insn. To succeed, don't move Z to X as an address
414 segment always comes in Y. Otherwise, we might fail when
415 adding the address segment to register. */
416 lra_assert (x
!= y
&& x
!= z
);
417 emit_move_insn (x
, y
);
418 rtx_insn
*insn
= emit_add2_insn (x
, z
);
419 lra_assert (insn
!= NULL_RTX
);
423 if (index_scale
== NULL_RTX
)
425 if (disp
== NULL_RTX
)
427 /* Generate x = index_scale; x = x + base. */
428 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
429 emit_move_insn (x
, index_scale
);
430 rtx_insn
*insn
= emit_add2_insn (x
, base
);
431 lra_assert (insn
!= NULL_RTX
);
433 else if (scale
== NULL_RTX
)
435 /* Try x = base + disp. */
436 lra_assert (base
!= NULL_RTX
);
437 last
= get_last_insn ();
438 rtx_insn
*move_insn
=
439 emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
), base
, disp
));
440 if (recog_memoized (move_insn
) < 0)
442 delete_insns_since (last
);
443 /* Generate x = disp; x = x + base. */
444 emit_move_insn (x
, disp
);
445 rtx_insn
*add2_insn
= emit_add2_insn (x
, base
);
446 lra_assert (add2_insn
!= NULL_RTX
);
448 /* Generate x = x + index. */
449 if (index
!= NULL_RTX
)
451 rtx_insn
*insn
= emit_add2_insn (x
, index
);
452 lra_assert (insn
!= NULL_RTX
);
457 /* Try x = index_scale; x = x + disp; x = x + base. */
458 last
= get_last_insn ();
459 rtx_insn
*move_insn
= emit_move_insn (x
, index_scale
);
461 if (recog_memoized (move_insn
) >= 0)
463 rtx_insn
*insn
= emit_add2_insn (x
, disp
);
464 if (insn
!= NULL_RTX
)
466 insn
= emit_add2_insn (x
, base
);
467 if (insn
!= NULL_RTX
)
473 delete_insns_since (last
);
474 /* Generate x = disp; x = x + base; x = x + index_scale. */
475 emit_move_insn (x
, disp
);
476 rtx_insn
*insn
= emit_add2_insn (x
, base
);
477 lra_assert (insn
!= NULL_RTX
);
478 insn
= emit_add2_insn (x
, index_scale
);
479 lra_assert (insn
!= NULL_RTX
);
484 /* Functions emit_... can create pseudos -- so expand the pseudo
486 if (old
!= max_reg_num ())
487 expand_reg_data (old
);
490 /* The number of emitted reload insns so far. */
491 int lra_curr_reload_num
;
493 /* Emit x := y, processing special case when y = u + v or y = u + v *
494 scale + w through emit_add (Y can be an address which is base +
495 index reg * scale + displacement in general case). X may be used
496 as intermediate result therefore it should be not in Y. */
498 lra_emit_move (rtx x
, rtx y
)
502 if (GET_CODE (y
) != PLUS
)
504 if (rtx_equal_p (x
, y
))
506 old
= max_reg_num ();
507 emit_move_insn (x
, y
);
509 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
510 /* Function emit_move can create pseudos -- so expand the pseudo
512 if (old
!= max_reg_num ())
513 expand_reg_data (old
);
516 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
519 /* Update insn operands which are duplication of operands whose
520 numbers are in array of NOPS (with end marker -1). The insn is
521 represented by its LRA internal representation ID. */
523 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
526 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
528 for (i
= 0; i
< static_id
->n_dups
; i
++)
529 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
530 if (static_id
->dup_num
[i
] == nop
)
531 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
536 /* This page contains code dealing with info about registers in the
539 /* Pools for insn reg info. */
540 pool_allocator
<lra_insn_reg
> lra_insn_reg::pool ("insn regs", 100);
542 /* Create LRA insn related info about a reference to REGNO in INSN with
543 TYPE (in/out/inout), biggest reference mode MODE, flag that it is
544 reference through subreg (SUBREG_P), flag that is early clobbered
545 in the insn (EARLY_CLOBBER), and reference to the next insn reg
547 static struct lra_insn_reg
*
548 new_insn_reg (rtx_insn
*insn
, int regno
, enum op_type type
,
550 bool subreg_p
, bool early_clobber
, struct lra_insn_reg
*next
)
552 lra_insn_reg
*ir
= new lra_insn_reg ();
554 ir
->biggest_mode
= mode
;
555 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (lra_reg_info
[regno
].biggest_mode
)
556 && NONDEBUG_INSN_P (insn
))
557 lra_reg_info
[regno
].biggest_mode
= mode
;
558 ir
->subreg_p
= subreg_p
;
559 ir
->early_clobber
= early_clobber
;
565 /* Free insn reg info list IR. */
567 free_insn_regs (struct lra_insn_reg
*ir
)
569 struct lra_insn_reg
*next_ir
;
571 for (; ir
!= NULL
; ir
= next_ir
)
578 /* Finish pool for insn reg info. */
580 finish_insn_regs (void)
582 lra_insn_reg::pool
.release ();
587 /* This page contains code dealing LRA insn info (or in other words
588 LRA internal insn representation). */
590 /* Map INSN_CODE -> the static insn data. This info is valid during
591 all translation unit. */
592 struct lra_static_insn_data
*insn_code_data
[LAST_INSN_CODE
];
594 /* Debug insns are represented as a special insn with one input
595 operand which is RTL expression in var_location. */
597 /* The following data are used as static insn operand data for all
598 debug insns. If structure lra_operand_data is changed, the
599 initializer should be changed too. */
600 static struct lra_operand_data debug_operand_data
=
602 NULL
, /* alternative */
603 VOIDmode
, /* We are not interesting in the operand mode. */
608 /* The following data are used as static insn data for all debug
609 insns. If structure lra_static_insn_data is changed, the
610 initializer should be changed too. */
611 static struct lra_static_insn_data debug_insn_static_data
=
614 0, /* Duplication operands #. */
615 -1, /* Commutative operand #. */
616 1, /* Operands #. There is only one operand which is debug RTL
618 0, /* Duplications #. */
619 0, /* Alternatives #. We are not interesting in alternatives
620 because we does not proceed debug_insns for reloads. */
621 NULL
, /* Hard registers referenced in machine description. */
622 NULL
/* Descriptions of operands in alternatives. */
625 /* Called once per compiler work to initialize some LRA data related
628 init_insn_code_data_once (void)
630 memset (insn_code_data
, 0, sizeof (insn_code_data
));
633 /* Called once per compiler work to finalize some LRA data related to
636 finish_insn_code_data_once (void)
640 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
642 if (insn_code_data
[i
] != NULL
)
643 free (insn_code_data
[i
]);
647 /* Return static insn data, allocate and setup if necessary. Although
648 dup_num is static data (it depends only on icode), to set it up we
649 need to extract insn first. So recog_data should be valid for
650 normal insn (ICODE >= 0) before the call. */
651 static struct lra_static_insn_data
*
652 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
654 struct lra_static_insn_data
*data
;
657 lra_assert (icode
< LAST_INSN_CODE
);
658 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
660 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
661 n_bytes
= sizeof (struct lra_static_insn_data
)
662 + sizeof (struct lra_operand_data
) * nop
663 + sizeof (int) * ndup
;
664 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
665 data
->operand_alternative
= NULL
;
666 data
->n_operands
= nop
;
668 data
->n_alternatives
= nalt
;
669 data
->operand
= ((struct lra_operand_data
*)
670 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
671 data
->dup_num
= ((int *) ((char *) data
->operand
672 + sizeof (struct lra_operand_data
) * nop
));
677 insn_code_data
[icode
] = data
;
678 for (i
= 0; i
< nop
; i
++)
680 data
->operand
[i
].constraint
681 = insn_data
[icode
].operand
[i
].constraint
;
682 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
683 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
684 data
->operand
[i
].is_operator
685 = insn_data
[icode
].operand
[i
].is_operator
;
686 data
->operand
[i
].type
687 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
688 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
690 data
->operand
[i
].is_address
= false;
692 for (i
= 0; i
< ndup
; i
++)
693 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
698 /* The current length of the following array. */
699 int lra_insn_recog_data_len
;
701 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
702 lra_insn_recog_data_t
*lra_insn_recog_data
;
704 /* Initialize LRA data about insns. */
706 init_insn_recog_data (void)
708 lra_insn_recog_data_len
= 0;
709 lra_insn_recog_data
= NULL
;
712 /* Expand, if necessary, LRA data about insns. */
714 check_and_expand_insn_recog_data (int index
)
718 if (lra_insn_recog_data_len
> index
)
720 old
= lra_insn_recog_data_len
;
721 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
722 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
724 lra_insn_recog_data_len
);
725 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
726 lra_insn_recog_data
[i
] = NULL
;
729 /* Finish LRA DATA about insn. */
731 free_insn_recog_data (lra_insn_recog_data_t data
)
733 if (data
->operand_loc
!= NULL
)
734 free (data
->operand_loc
);
735 if (data
->dup_loc
!= NULL
)
736 free (data
->dup_loc
);
737 if (data
->arg_hard_regs
!= NULL
)
738 free (data
->arg_hard_regs
);
739 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
741 if (data
->insn_static_data
->operand_alternative
!= NULL
)
742 free (const_cast <operand_alternative
*>
743 (data
->insn_static_data
->operand_alternative
));
744 free_insn_regs (data
->insn_static_data
->hard_regs
);
745 free (data
->insn_static_data
);
747 free_insn_regs (data
->regs
);
752 /* Finish LRA data about all insns. */
754 finish_insn_recog_data (void)
757 lra_insn_recog_data_t data
;
759 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
760 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
761 free_insn_recog_data (data
);
763 lra_copy::pool
.release ();
764 lra_insn_reg::pool
.release ();
765 free (lra_insn_recog_data
);
768 /* Setup info about operands in alternatives of LRA DATA of insn. */
770 setup_operand_alternative (lra_insn_recog_data_t data
,
771 const operand_alternative
*op_alt
)
774 int icode
= data
->icode
;
775 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
777 static_data
->commutative
= -1;
778 nop
= static_data
->n_operands
;
779 nalt
= static_data
->n_alternatives
;
780 static_data
->operand_alternative
= op_alt
;
781 for (i
= 0; i
< nop
; i
++)
783 static_data
->operand
[i
].early_clobber
= false;
784 static_data
->operand
[i
].is_address
= false;
785 if (static_data
->operand
[i
].constraint
[0] == '%')
787 /* We currently only support one commutative pair of operands. */
788 if (static_data
->commutative
< 0)
789 static_data
->commutative
= i
;
791 lra_assert (icode
< 0); /* Asm */
792 /* The last operand should not be marked commutative. */
793 lra_assert (i
!= nop
- 1);
796 for (j
= 0; j
< nalt
; j
++)
797 for (i
= 0; i
< nop
; i
++, op_alt
++)
799 static_data
->operand
[i
].early_clobber
|= op_alt
->earlyclobber
;
800 static_data
->operand
[i
].is_address
|= op_alt
->is_address
;
804 /* Recursively process X and collect info about registers, which are
805 not the insn operands, in X with TYPE (in/out/inout) and flag that
806 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
807 to LIST. X is a part of insn given by DATA. Return the result
809 static struct lra_insn_reg
*
810 collect_non_operand_hard_regs (rtx
*x
, lra_insn_recog_data_t data
,
811 struct lra_insn_reg
*list
,
812 enum op_type type
, bool early_clobber
)
814 int i
, j
, regno
, last
;
817 struct lra_insn_reg
*curr
;
819 enum rtx_code code
= GET_CODE (op
);
820 const char *fmt
= GET_RTX_FORMAT (code
);
822 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
823 if (x
== data
->operand_loc
[i
])
824 /* It is an operand loc. Stop here. */
826 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
827 if (x
== data
->dup_loc
[i
])
828 /* It is a dup loc. Stop here. */
830 mode
= GET_MODE (op
);
834 op
= SUBREG_REG (op
);
835 code
= GET_CODE (op
);
836 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (op
)))
838 mode
= GET_MODE (op
);
839 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
845 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
847 /* Process all regs even unallocatable ones as we need info
848 about all regs for rematerialization pass. */
849 for (last
= regno
+ hard_regno_nregs
[regno
][mode
];
853 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
854 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
855 && curr
->biggest_mode
== mode
)
857 if (curr
->type
!= type
)
858 curr
->type
= OP_INOUT
;
859 if (curr
->early_clobber
!= early_clobber
)
860 curr
->early_clobber
= true;
865 /* This is a new hard regno or the info can not be
866 integrated into the found structure. */
870 /* This clobber is to inform popping floating
872 && ! (FIRST_STACK_REG
<= regno
873 && regno
<= LAST_STACK_REG
));
875 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
876 early_clobber
, list
);
884 list
= collect_non_operand_hard_regs (&SET_DEST (op
), data
,
885 list
, OP_OUT
, false);
886 list
= collect_non_operand_hard_regs (&SET_SRC (op
), data
,
890 /* We treat clobber of non-operand hard registers as early
891 clobber (the behavior is expected from asm). */
892 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
895 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
896 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
897 list
, OP_INOUT
, false);
899 case PRE_MODIFY
: case POST_MODIFY
:
900 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
901 list
, OP_INOUT
, false);
902 list
= collect_non_operand_hard_regs (&XEXP (op
, 1), data
,
906 fmt
= GET_RTX_FORMAT (code
);
907 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
910 list
= collect_non_operand_hard_regs (&XEXP (op
, i
), data
,
912 else if (fmt
[i
] == 'E')
913 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
914 list
= collect_non_operand_hard_regs (&XVECEXP (op
, i
, j
), data
,
921 /* Set up and return info about INSN. Set up the info if it is not set up
923 lra_insn_recog_data_t
924 lra_set_insn_recog_data (rtx_insn
*insn
)
926 lra_insn_recog_data_t data
;
929 unsigned int uid
= INSN_UID (insn
);
930 struct lra_static_insn_data
*insn_static_data
;
932 check_and_expand_insn_recog_data (uid
);
933 if (DEBUG_INSN_P (insn
))
937 icode
= INSN_CODE (insn
);
939 /* It might be a new simple insn which is not recognized yet. */
940 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
942 data
= XNEW (struct lra_insn_recog_data
);
943 lra_insn_recog_data
[uid
] = data
;
945 data
->used_insn_alternative
= -1;
948 if (DEBUG_INSN_P (insn
))
950 data
->insn_static_data
= &debug_insn_static_data
;
951 data
->dup_loc
= NULL
;
952 data
->arg_hard_regs
= NULL
;
953 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
954 data
->operand_loc
= XNEWVEC (rtx
*, 1);
955 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
961 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
962 const char *constraints
[MAX_RECOG_OPERANDS
];
964 nop
= asm_noperands (PATTERN (insn
));
965 data
->operand_loc
= data
->dup_loc
= NULL
;
969 /* It is a special insn like USE or CLOBBER. We should
970 recognize any regular insn otherwise LRA can do nothing
972 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
973 || GET_CODE (PATTERN (insn
)) == CLOBBER
974 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
975 data
->insn_static_data
= insn_static_data
976 = get_static_insn_data (-1, 0, 0, nalt
);
980 /* expand_asm_operands makes sure there aren't too many
982 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
984 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
985 /* Now get the operand values and constraints out of the
987 decode_asm_operands (PATTERN (insn
), NULL
,
989 constraints
, operand_mode
, NULL
);
992 const char *p
= recog_data
.constraints
[0];
994 for (p
= constraints
[0]; *p
; p
++)
997 data
->insn_static_data
= insn_static_data
998 = get_static_insn_data (-1, nop
, 0, nalt
);
999 for (i
= 0; i
< nop
; i
++)
1001 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
1002 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
1003 insn_static_data
->operand
[i
].strict_low
= false;
1004 insn_static_data
->operand
[i
].is_operator
= false;
1005 insn_static_data
->operand
[i
].is_address
= false;
1008 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1009 insn_static_data
->operand
[i
].type
1010 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1011 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1013 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
1016 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
,
1018 preprocess_constraints (nop
, nalt
, constraints
, op_alt
);
1019 setup_operand_alternative (data
, op_alt
);
1024 insn_extract (insn
);
1025 data
->insn_static_data
= insn_static_data
1026 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1027 insn_data
[icode
].n_dups
,
1028 insn_data
[icode
].n_alternatives
);
1029 n
= insn_static_data
->n_operands
;
1034 locs
= XNEWVEC (rtx
*, n
);
1035 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1037 data
->operand_loc
= locs
;
1038 n
= insn_static_data
->n_dups
;
1043 locs
= XNEWVEC (rtx
*, n
);
1044 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1046 data
->dup_loc
= locs
;
1047 data
->preferred_alternatives
= get_preferred_alternatives (insn
);
1048 const operand_alternative
*op_alt
= preprocess_insn_constraints (icode
);
1049 if (!insn_static_data
->operand_alternative
)
1050 setup_operand_alternative (data
, op_alt
);
1051 else if (op_alt
!= insn_static_data
->operand_alternative
)
1052 insn_static_data
->operand_alternative
= op_alt
;
1054 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1055 insn_static_data
->hard_regs
= NULL
;
1057 insn_static_data
->hard_regs
1058 = collect_non_operand_hard_regs (&PATTERN (insn
), data
,
1059 NULL
, OP_IN
, false);
1060 data
->arg_hard_regs
= NULL
;
1064 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1067 /* Finding implicit hard register usage. We believe it will be
1068 not changed whatever transformations are used. Call insns
1069 are such example. */
1070 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1072 link
= XEXP (link
, 1))
1073 if (GET_CODE (XEXP (link
, 0)) == USE
1074 && REG_P (XEXP (XEXP (link
, 0), 0)))
1076 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1077 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1078 /* It is an argument register. */
1079 for (i
= REG_NREGS (XEXP (XEXP (link
, 0), 0)) - 1; i
>= 0; i
--)
1080 arg_hard_regs
[n_hard_regs
++] = regno
+ i
;
1082 if (n_hard_regs
!= 0)
1084 arg_hard_regs
[n_hard_regs
++] = -1;
1085 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1086 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1087 sizeof (int) * n_hard_regs
);
1090 /* Some output operand can be recognized only from the context not
1091 from the constraints which are empty in this case. Call insn may
1092 contain a hard register in set destination with empty constraint
1093 and extract_insn treats them as an input. */
1094 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1098 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1100 /* ??? Should we treat 'X' the same way. It looks to me that
1101 'X' means anything and empty constraint means we do not
1103 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1104 || operand
->is_operator
)
1106 pat
= PATTERN (insn
);
1107 if (GET_CODE (pat
) == SET
)
1109 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1112 else if (GET_CODE (pat
) == PARALLEL
)
1114 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1116 set
= XVECEXP (PATTERN (insn
), 0, j
);
1117 if (GET_CODE (set
) == SET
1118 && &SET_DEST (set
) == data
->operand_loc
[i
])
1126 operand
->type
= OP_OUT
;
1131 /* Return info about insn give by UID. The info should be already set
1133 static lra_insn_recog_data_t
1134 get_insn_recog_data_by_uid (int uid
)
1136 lra_insn_recog_data_t data
;
1138 data
= lra_insn_recog_data
[uid
];
1139 lra_assert (data
!= NULL
);
1143 /* Invalidate all info about insn given by its UID. */
1145 invalidate_insn_recog_data (int uid
)
1147 lra_insn_recog_data_t data
;
1149 data
= lra_insn_recog_data
[uid
];
1150 lra_assert (data
!= NULL
);
1151 free_insn_recog_data (data
);
1152 lra_insn_recog_data
[uid
] = NULL
;
1155 /* Update all the insn info about INSN. It is usually called when
1156 something in the insn was changed. Return the updated info. */
1157 lra_insn_recog_data_t
1158 lra_update_insn_recog_data (rtx_insn
*insn
)
1160 lra_insn_recog_data_t data
;
1162 unsigned int uid
= INSN_UID (insn
);
1163 struct lra_static_insn_data
*insn_static_data
;
1164 HOST_WIDE_INT sp_offset
= 0;
1166 check_and_expand_insn_recog_data (uid
);
1167 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1168 && data
->icode
!= INSN_CODE (insn
))
1170 sp_offset
= data
->sp_offset
;
1171 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1172 invalidate_insn_recog_data (uid
);
1177 data
= lra_get_insn_recog_data (insn
);
1178 /* Initiate or restore SP offset. */
1179 data
->sp_offset
= sp_offset
;
1182 insn_static_data
= data
->insn_static_data
;
1183 data
->used_insn_alternative
= -1;
1184 if (DEBUG_INSN_P (insn
))
1186 if (data
->icode
< 0)
1189 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1190 const char *constraints
[MAX_RECOG_OPERANDS
];
1192 nop
= asm_noperands (PATTERN (insn
));
1195 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1196 /* Now get the operand values and constraints out of the
1198 decode_asm_operands (PATTERN (insn
), NULL
,
1200 constraints
, operand_mode
, NULL
);
1201 #ifdef ENABLE_CHECKING
1205 for (i
= 0; i
< nop
; i
++)
1207 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1208 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1209 && ! insn_static_data
->operand
[i
].is_operator
);
1213 #ifdef ENABLE_CHECKING
1217 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1219 (insn_static_data
->operand
[i
].type
1220 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1221 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1228 insn_extract (insn
);
1229 n
= insn_static_data
->n_operands
;
1231 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1232 n
= insn_static_data
->n_dups
;
1234 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1235 lra_assert (check_bool_attrs (insn
));
1240 /* Set up that INSN is using alternative ALT now. */
1242 lra_set_used_insn_alternative (rtx_insn
*insn
, int alt
)
1244 lra_insn_recog_data_t data
;
1246 data
= lra_get_insn_recog_data (insn
);
1247 data
->used_insn_alternative
= alt
;
1250 /* Set up that insn with UID is using alternative ALT now. The insn
1251 info should be already set up. */
1253 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1255 lra_insn_recog_data_t data
;
1257 check_and_expand_insn_recog_data (uid
);
1258 data
= lra_insn_recog_data
[uid
];
1259 lra_assert (data
!= NULL
);
1260 data
->used_insn_alternative
= alt
;
1265 /* This page contains code dealing with common register info and
1268 /* The size of the following array. */
1269 static int reg_info_size
;
1270 /* Common info about each register. */
1271 struct lra_reg
*lra_reg_info
;
1273 /* Last register value. */
1274 static int last_reg_value
;
1276 /* Return new register value. */
1278 get_new_reg_value (void)
1280 return ++last_reg_value
;
1283 /* Pools for copies. */
1284 pool_allocator
<lra_copy
> lra_copy::pool ("lra copies", 100);
1286 /* Vec referring to pseudo copies. */
1287 static vec
<lra_copy_t
> copy_vec
;
1289 /* Initialize I-th element of lra_reg_info. */
1291 initialize_lra_reg_info_element (int i
)
1293 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1295 lra_reg_info
[i
].no_stack_p
= false;
1297 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1298 CLEAR_HARD_REG_SET (lra_reg_info
[i
].actual_call_used_reg_set
);
1299 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1300 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1301 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1302 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1303 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1304 lra_reg_info
[i
].live_ranges
= NULL
;
1305 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1306 lra_reg_info
[i
].last_reload
= 0;
1307 lra_reg_info
[i
].restore_regno
= -1;
1308 lra_reg_info
[i
].val
= get_new_reg_value ();
1309 lra_reg_info
[i
].offset
= 0;
1310 lra_reg_info
[i
].copies
= NULL
;
1313 /* Initialize common reg info and copies. */
1315 init_reg_info (void)
1320 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1321 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1322 for (i
= 0; i
< reg_info_size
; i
++)
1323 initialize_lra_reg_info_element (i
);
1324 copy_vec
.create (100);
1328 /* Finish common reg info and copies. */
1330 finish_reg_info (void)
1334 for (i
= 0; i
< reg_info_size
; i
++)
1335 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1336 free (lra_reg_info
);
1340 /* Expand common reg info if it is necessary. */
1342 expand_reg_info (void)
1344 int i
, old
= reg_info_size
;
1346 if (reg_info_size
> max_reg_num ())
1348 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1349 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1350 for (i
= old
; i
< reg_info_size
; i
++)
1351 initialize_lra_reg_info_element (i
);
1354 /* Free all copies. */
1356 lra_free_copies (void)
1360 while (copy_vec
.length () != 0)
1362 cp
= copy_vec
.pop ();
1363 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1368 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1369 frequency is FREQ. */
1371 lra_create_copy (int regno1
, int regno2
, int freq
)
1376 lra_assert (regno1
!= regno2
);
1377 regno1_dest_p
= true;
1378 if (regno1
> regno2
)
1380 std::swap (regno1
, regno2
);
1381 regno1_dest_p
= false;
1383 cp
= new lra_copy ();
1384 copy_vec
.safe_push (cp
);
1385 cp
->regno1_dest_p
= regno1_dest_p
;
1387 cp
->regno1
= regno1
;
1388 cp
->regno2
= regno2
;
1389 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1390 lra_reg_info
[regno1
].copies
= cp
;
1391 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1392 lra_reg_info
[regno2
].copies
= cp
;
1393 if (lra_dump_file
!= NULL
)
1394 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1395 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1398 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1401 lra_get_copy (int n
)
1403 if (n
>= (int) copy_vec
.length ())
1410 /* This page contains code dealing with info about registers in
1413 /* Process X of insn UID recursively and add info (operand type is
1414 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1415 about registers in X to the insn DATA. */
1417 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
, int uid
,
1418 enum op_type type
, bool early_clobber
)
1425 struct lra_insn_reg
*curr
;
1427 code
= GET_CODE (x
);
1428 mode
= GET_MODE (x
);
1430 if (GET_CODE (x
) == SUBREG
)
1433 code
= GET_CODE (x
);
1434 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
)))
1436 mode
= GET_MODE (x
);
1437 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
1444 /* Process all regs even unallocatable ones as we need info about
1445 all regs for rematerialization pass. */
1447 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, uid
))
1449 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1450 early_clobber
, data
->regs
);
1455 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1456 if (curr
->regno
== regno
)
1458 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1459 /* The info can not be integrated into the found
1461 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1462 subreg_p
, early_clobber
,
1466 if (curr
->type
!= type
)
1467 curr
->type
= OP_INOUT
;
1468 if (curr
->early_clobber
!= early_clobber
)
1469 curr
->early_clobber
= true;
1480 add_regs_to_insn_regno_info (data
, SET_DEST (x
), uid
, OP_OUT
, false);
1481 add_regs_to_insn_regno_info (data
, SET_SRC (x
), uid
, OP_IN
, false);
1484 /* We treat clobber of non-operand hard registers as early
1485 clobber (the behavior is expected from asm). */
1486 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_OUT
, true);
1488 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1489 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1491 case PRE_MODIFY
: case POST_MODIFY
:
1492 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1493 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), uid
, OP_IN
, false);
1496 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1497 /* Some targets place small structures in registers for return
1498 values of functions, and those registers are wrapped in
1499 PARALLEL that we may see as the destination of a SET. Here
1502 (call_insn 13 12 14 2 (set (parallel:BLK [
1503 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1505 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1506 (const_int 8 [0x8]))
1508 (call (mem:QI (symbol_ref:DI (... */
1510 fmt
= GET_RTX_FORMAT (code
);
1511 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1514 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), uid
, type
, false);
1515 else if (fmt
[i
] == 'E')
1517 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1518 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), uid
,
1525 /* Return execution frequency of INSN. */
1527 get_insn_freq (rtx_insn
*insn
)
1529 basic_block bb
= BLOCK_FOR_INSN (insn
);
1531 gcc_checking_assert (bb
!= NULL
);
1532 return REG_FREQ_FROM_BB (bb
);
1535 /* Invalidate all reg info of INSN with DATA and execution frequency
1536 FREQ. Update common info about the invalidated registers. */
1538 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx_insn
*insn
,
1544 struct lra_insn_reg
*ir
, *next_ir
;
1546 uid
= INSN_UID (insn
);
1547 debug_p
= DEBUG_INSN_P (insn
);
1548 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1553 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1554 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1556 lra_reg_info
[i
].nrefs
--;
1557 lra_reg_info
[i
].freq
-= freq
;
1558 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1564 /* Invalidate all reg info of INSN. Update common info about the
1565 invalidated registers. */
1567 lra_invalidate_insn_regno_info (rtx_insn
*insn
)
1569 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1570 get_insn_freq (insn
));
1573 /* Update common reg info from reg info of insn given by its DATA and
1574 execution frequency FREQ. */
1576 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1579 struct lra_insn_reg
*ir
;
1581 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1582 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1584 lra_reg_info
[i
].nrefs
++;
1585 lra_reg_info
[i
].freq
+= freq
;
1589 /* Set up insn reg info of INSN. Update common reg info from reg info
1592 lra_update_insn_regno_info (rtx_insn
*insn
)
1595 lra_insn_recog_data_t data
;
1596 struct lra_static_insn_data
*static_data
;
1600 if (! INSN_P (insn
))
1602 data
= lra_get_insn_recog_data (insn
);
1603 static_data
= data
->insn_static_data
;
1604 freq
= get_insn_freq (insn
);
1605 invalidate_insn_data_regno_info (data
, insn
, freq
);
1606 uid
= INSN_UID (insn
);
1607 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1608 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], uid
,
1609 static_data
->operand
[i
].type
,
1610 static_data
->operand
[i
].early_clobber
);
1611 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1612 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), uid
,
1613 code
== USE
? OP_IN
: OP_OUT
, false);
1615 /* On some targets call insns can refer to pseudos in memory in
1616 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1617 consider their occurrences in calls for different
1618 transformations (e.g. inheritance) with given pseudos. */
1619 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1621 link
= XEXP (link
, 1))
1622 if (((code
= GET_CODE (XEXP (link
, 0))) == USE
|| code
== CLOBBER
)
1623 && MEM_P (XEXP (XEXP (link
, 0), 0)))
1624 add_regs_to_insn_regno_info (data
, XEXP (XEXP (link
, 0), 0), uid
,
1625 code
== USE
? OP_IN
: OP_OUT
, false);
1626 if (NONDEBUG_INSN_P (insn
))
1627 setup_insn_reg_info (data
, freq
);
1630 /* Return reg info of insn given by it UID. */
1631 struct lra_insn_reg
*
1632 lra_get_insn_regs (int uid
)
1634 lra_insn_recog_data_t data
;
1636 data
= get_insn_recog_data_by_uid (uid
);
1642 /* This page contains code dealing with stack of the insns which
1643 should be processed by the next constraint pass. */
1645 /* Bitmap used to put an insn on the stack only in one exemplar. */
1646 static sbitmap lra_constraint_insn_stack_bitmap
;
1648 /* The stack itself. */
1649 vec
<rtx_insn
*> lra_constraint_insn_stack
;
1651 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1652 info for INSN, otherwise only update it if INSN is not already on the
1655 lra_push_insn_1 (rtx_insn
*insn
, bool always_update
)
1657 unsigned int uid
= INSN_UID (insn
);
1659 lra_update_insn_regno_info (insn
);
1660 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1661 lra_constraint_insn_stack_bitmap
=
1662 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1663 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1665 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1666 if (! always_update
)
1667 lra_update_insn_regno_info (insn
);
1668 lra_constraint_insn_stack
.safe_push (insn
);
1671 /* Put INSN on the stack. */
1673 lra_push_insn (rtx_insn
*insn
)
1675 lra_push_insn_1 (insn
, false);
1678 /* Put INSN on the stack and update its reg info. */
1680 lra_push_insn_and_update_insn_regno_info (rtx_insn
*insn
)
1682 lra_push_insn_1 (insn
, true);
1685 /* Put insn with UID on the stack. */
1687 lra_push_insn_by_uid (unsigned int uid
)
1689 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1692 /* Take the last-inserted insns off the stack and return it. */
1696 rtx_insn
*insn
= lra_constraint_insn_stack
.pop ();
1697 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1701 /* Return the current size of the insn stack. */
1703 lra_insn_stack_length (void)
1705 return lra_constraint_insn_stack
.length ();
1708 /* Push insns FROM to TO (excluding it) going in reverse order. */
1710 push_insns (rtx_insn
*from
, rtx_insn
*to
)
1714 if (from
== NULL_RTX
)
1716 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1718 lra_push_insn (insn
);
1721 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1722 taken from the next BB insn after LAST or zero if there in such
1725 setup_sp_offset (rtx_insn
*from
, rtx_insn
*last
)
1727 rtx_insn
*before
= next_nonnote_insn_bb (last
);
1728 HOST_WIDE_INT offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1729 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1731 for (rtx_insn
*insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1732 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1735 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1736 insns onto the stack. Print about emitting the insns with
1739 lra_process_new_insns (rtx_insn
*insn
, rtx_insn
*before
, rtx_insn
*after
,
1744 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1746 if (lra_dump_file
!= NULL
)
1748 dump_insn_slim (lra_dump_file
, insn
);
1749 if (before
!= NULL_RTX
)
1751 fprintf (lra_dump_file
," %s before:\n", title
);
1752 dump_rtl_slim (lra_dump_file
, before
, NULL
, -1, 0);
1754 if (after
!= NULL_RTX
)
1756 fprintf (lra_dump_file
, " %s after:\n", title
);
1757 dump_rtl_slim (lra_dump_file
, after
, NULL
, -1, 0);
1759 fprintf (lra_dump_file
, "\n");
1761 if (before
!= NULL_RTX
)
1763 emit_insn_before (before
, insn
);
1764 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1765 setup_sp_offset (before
, PREV_INSN (insn
));
1767 if (after
!= NULL_RTX
)
1769 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1771 emit_insn_after (after
, insn
);
1772 push_insns (last
, insn
);
1773 setup_sp_offset (after
, last
);
1779 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1780 register NEW_REG. Return true if any change was made. */
1782 lra_substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
1785 bool result
= false;
1793 code
= GET_CODE (x
);
1794 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
1796 machine_mode mode
= GET_MODE (*loc
);
1797 machine_mode inner_mode
= GET_MODE (new_reg
);
1799 if (mode
!= inner_mode
1800 && ! (CONST_INT_P (new_reg
) && SCALAR_INT_MODE_P (mode
)))
1802 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
1803 || ! SCALAR_INT_MODE_P (inner_mode
))
1804 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
1806 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
1812 /* Scan all the operand sub-expressions. */
1813 fmt
= GET_RTX_FORMAT (code
);
1814 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1818 if (lra_substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
1821 else if (fmt
[i
] == 'E')
1823 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1824 if (lra_substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
1831 /* Call lra_substitute_pseudo within an insn. This won't update the insn ptr,
1832 just the contents of the insn. */
1834 lra_substitute_pseudo_within_insn (rtx_insn
*insn
, int old_regno
, rtx new_reg
)
1837 return lra_substitute_pseudo (&loc
, old_regno
, new_reg
);
1842 /* This page contains code dealing with scratches (changing them onto
1843 pseudos and restoring them from the pseudos).
1845 We change scratches into pseudos at the beginning of LRA to
1846 simplify dealing with them (conflicts, hard register assignments).
1848 If the pseudo denoting scratch was spilled it means that we do need
1849 a hard register for it. Such pseudos are transformed back to
1850 scratches at the end of LRA. */
1852 /* Description of location of a former scratch operand. */
1855 rtx_insn
*insn
; /* Insn where the scratch was. */
1856 int nop
; /* Number of the operand which was a scratch. */
1859 typedef struct sloc
*sloc_t
;
1861 /* Locations of the former scratches. */
1862 static vec
<sloc_t
> scratches
;
1864 /* Bitmap of scratch regnos. */
1865 static bitmap_head scratch_bitmap
;
1867 /* Bitmap of scratch operands. */
1868 static bitmap_head scratch_operand_bitmap
;
1870 /* Return true if pseudo REGNO is made of SCRATCH. */
1872 lra_former_scratch_p (int regno
)
1874 return bitmap_bit_p (&scratch_bitmap
, regno
);
1877 /* Return true if the operand NOP of INSN is a former scratch. */
1879 lra_former_scratch_operand_p (rtx_insn
*insn
, int nop
)
1881 return bitmap_bit_p (&scratch_operand_bitmap
,
1882 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
1885 /* Register operand NOP in INSN as a former scratch. It will be
1886 changed to scratch back, if it is necessary, at the LRA end. */
1888 lra_register_new_scratch_op (rtx_insn
*insn
, int nop
)
1890 lra_insn_recog_data_t id
= lra_get_insn_recog_data (insn
);
1891 rtx op
= *id
->operand_loc
[nop
];
1892 sloc_t loc
= XNEW (struct sloc
);
1893 lra_assert (REG_P (op
));
1896 scratches
.safe_push (loc
);
1897 bitmap_set_bit (&scratch_bitmap
, REGNO (op
));
1898 bitmap_set_bit (&scratch_operand_bitmap
,
1899 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
);
1900 add_reg_note (insn
, REG_UNUSED
, op
);
1903 /* Change scratches onto pseudos and save their location. */
1905 remove_scratches (void)
1908 bool insn_changed_p
;
1912 lra_insn_recog_data_t id
;
1913 struct lra_static_insn_data
*static_id
;
1915 scratches
.create (get_max_uid ());
1916 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
1917 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
1918 FOR_EACH_BB_FN (bb
, cfun
)
1919 FOR_BB_INSNS (bb
, insn
)
1922 id
= lra_get_insn_recog_data (insn
);
1923 static_id
= id
->insn_static_data
;
1924 insn_changed_p
= false;
1925 for (i
= 0; i
< static_id
->n_operands
; i
++)
1926 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
1927 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
1929 insn_changed_p
= true;
1930 *id
->operand_loc
[i
] = reg
1931 = lra_create_new_reg (static_id
->operand
[i
].mode
,
1932 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
1933 lra_register_new_scratch_op (insn
, i
);
1934 if (lra_dump_file
!= NULL
)
1935 fprintf (lra_dump_file
,
1936 "Removing SCRATCH in insn #%u (nop %d)\n",
1937 INSN_UID (insn
), i
);
1940 /* Because we might use DF right after caller-saves sub-pass
1941 we need to keep DF info up to date. */
1942 df_insn_rescan (insn
);
1946 /* Changes pseudos created by function remove_scratches onto scratches. */
1948 restore_scratches (void)
1953 rtx_insn
*last
= NULL
;
1954 lra_insn_recog_data_t id
= NULL
;
1956 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1958 if (last
!= loc
->insn
)
1961 id
= lra_get_insn_recog_data (last
);
1963 if (REG_P (*id
->operand_loc
[loc
->nop
])
1964 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
1965 >= FIRST_PSEUDO_REGISTER
)
1966 && lra_get_regno_hard_regno (regno
) < 0)
1968 /* It should be only case when scratch register with chosen
1969 constraint 'X' did not get memory or hard register. */
1970 lra_assert (lra_former_scratch_p (regno
));
1971 *id
->operand_loc
[loc
->nop
]
1972 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
1973 lra_update_dup (id
, loc
->nop
);
1974 if (lra_dump_file
!= NULL
)
1975 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
1976 INSN_UID (loc
->insn
), loc
->nop
);
1979 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1981 scratches
.release ();
1982 bitmap_clear (&scratch_bitmap
);
1983 bitmap_clear (&scratch_operand_bitmap
);
1988 #ifdef ENABLE_CHECKING
1990 /* Function checks RTL for correctness. If FINAL_P is true, it is
1991 done at the end of LRA and the check is more rigorous. */
1993 check_rtl (bool final_p
)
1998 lra_assert (! final_p
|| reload_completed
);
1999 FOR_EACH_BB_FN (bb
, cfun
)
2000 FOR_BB_INSNS (bb
, insn
)
2001 if (NONDEBUG_INSN_P (insn
)
2002 && GET_CODE (PATTERN (insn
)) != USE
2003 && GET_CODE (PATTERN (insn
)) != CLOBBER
2004 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
2008 #ifdef ENABLED_CHECKING
2009 extract_constrain_insn (insn
);
2013 /* LRA code is based on assumption that all addresses can be
2014 correctly decomposed. LRA can generate reloads for
2015 decomposable addresses. The decomposition code checks the
2016 correctness of the addresses. So we don't need to check
2017 the addresses here. Don't call insn_invalid_p here, it can
2018 change the code at this stage. */
2019 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
2020 fatal_insn_not_found (insn
);
2023 #endif /* #ifdef ENABLE_CHECKING */
2025 /* Determine if the current function has an exception receiver block
2026 that reaches the exit block via non-exceptional edges */
2028 has_nonexceptional_receiver (void)
2032 basic_block
*tos
, *worklist
, bb
;
2034 /* If we're not optimizing, then just err on the safe side. */
2038 /* First determine which blocks can reach exit via normal paths. */
2039 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
2041 FOR_EACH_BB_FN (bb
, cfun
)
2042 bb
->flags
&= ~BB_REACHABLE
;
2044 /* Place the exit block on our worklist. */
2045 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
2046 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
2048 /* Iterate: find everything reachable from what we've already seen. */
2049 while (tos
!= worklist
)
2053 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
2054 if (e
->flags
& EDGE_ABNORMAL
)
2061 basic_block src
= e
->src
;
2063 if (!(src
->flags
& BB_REACHABLE
))
2065 src
->flags
|= BB_REACHABLE
;
2071 /* No exceptional block reached exit unexceptionally. */
2077 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2079 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
2081 enum rtx_code code
= GET_CODE (x
);
2085 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
2087 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
2091 /* Scan all X sub-expressions. */
2092 fmt
= GET_RTX_FORMAT (code
);
2093 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2096 add_auto_inc_notes (insn
, XEXP (x
, i
));
2097 else if (fmt
[i
] == 'E')
2098 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2099 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2105 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2106 We change pseudos by hard registers without notification of DF and
2107 that can make the notes obsolete. DF-infrastructure does not deal
2108 with REG_INC notes -- so we should regenerate them here. */
2110 update_inc_notes (void)
2116 FOR_EACH_BB_FN (bb
, cfun
)
2117 FOR_BB_INSNS (bb
, insn
)
2118 if (NONDEBUG_INSN_P (insn
))
2120 pnote
= ®_NOTES (insn
);
2123 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2124 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2125 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2126 *pnote
= XEXP (*pnote
, 1);
2128 pnote
= &XEXP (*pnote
, 1);
2131 add_auto_inc_notes (insn
, PATTERN (insn
));
2136 /* Set to 1 while in lra. */
2137 int lra_in_progress
;
2139 /* Start of pseudo regnos before the LRA. */
2140 int lra_new_regno_start
;
2142 /* Start of reload pseudo regnos before the new spill pass. */
2143 int lra_constraint_new_regno_start
;
2145 /* Avoid spilling pseudos with regno more than the following value if
2147 int lra_bad_spill_regno_start
;
2149 /* Inheritance pseudo regnos before the new spill pass. */
2150 bitmap_head lra_inheritance_pseudos
;
2152 /* Split regnos before the new spill pass. */
2153 bitmap_head lra_split_regs
;
2155 /* Reload pseudo regnos before the new assignmnet pass which still can
2156 be spilled after the assinment pass as memory is also accepted in
2157 insns for the reload pseudos. */
2158 bitmap_head lra_optional_reload_pseudos
;
2160 /* Pseudo regnos used for subreg reloads before the new assignment
2161 pass. Such pseudos still can be spilled after the assinment
2163 bitmap_head lra_subreg_reload_pseudos
;
2165 /* File used for output of LRA debug information. */
2166 FILE *lra_dump_file
;
2168 /* True if we should try spill into registers of different classes
2169 instead of memory. */
2170 bool lra_reg_spill_p
;
2172 /* Set up value LRA_REG_SPILL_P. */
2174 setup_reg_spill_flag (void)
2178 if (targetm
.spill_class
!= NULL
)
2179 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2180 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2181 if (targetm
.spill_class ((enum reg_class
) cl
,
2182 (machine_mode
) mode
) != NO_REGS
)
2184 lra_reg_spill_p
= true;
2187 lra_reg_spill_p
= false;
2190 /* True if the current function is too big to use regular algorithms
2191 in LRA. In other words, we should use simpler and faster algorithms
2192 in LRA. It also means we should not worry about generation code
2193 for caller saves. The value is set up in IRA. */
2196 /* Major LRA entry function. F is a file should be used to dump LRA
2202 bool live_p
, scratch_p
, inserted_p
;
2206 timevar_push (TV_LRA
);
2208 /* Make sure that the last insn is a note. Some subsequent passes
2210 emit_note (NOTE_INSN_DELETED
);
2212 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2217 init_insn_recog_data ();
2219 #ifdef ENABLE_CHECKING
2220 /* Some quick check on RTL generated by previous passes. */
2224 lra_in_progress
= 1;
2226 lra_live_range_iter
= lra_coalesce_iter
= lra_constraint_iter
= 0;
2227 lra_assignment_iter
= lra_assignment_iter_after_spill
= 0;
2228 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2229 lra_rematerialization_iter
= 0;
2231 setup_reg_spill_flag ();
2233 /* Function remove_scratches can creates new pseudos for clobbers --
2234 so set up lra_constraint_new_regno_start before its call to
2235 permit changing reg classes for pseudos created by this
2237 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2238 lra_bad_spill_regno_start
= INT_MAX
;
2239 remove_scratches ();
2240 scratch_p
= lra_constraint_new_regno_start
!= max_reg_num ();
2242 /* A function that has a non-local label that can reach the exit
2243 block via non-exceptional paths must save all call-saved
2245 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2246 crtl
->saves_all_registers
= 1;
2248 if (crtl
->saves_all_registers
)
2249 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2250 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2251 df_set_regs_ever_live (i
, true);
2253 /* We don't DF from now and avoid its using because it is to
2254 expensive when a lot of RTL changes are made. */
2255 df_set_flags (DF_NO_INSN_RESCAN
);
2256 lra_constraint_insn_stack
.create (get_max_uid ());
2257 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2258 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2259 lra_live_ranges_init ();
2260 lra_constraints_init ();
2261 lra_curr_reload_num
= 0;
2262 push_insns (get_last_insn (), NULL
);
2263 /* It is needed for the 1st coalescing. */
2264 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2265 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2266 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2267 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2269 if (get_frame_size () != 0 && crtl
->stack_alignment_needed
)
2270 /* If we have a stack frame, we must align it now. The stack size
2271 may be a part of the offset computation for register
2273 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2279 /* We should try to assign hard registers to scratches even
2280 if there were no RTL transformations in
2282 if (! lra_constraints (lra_constraint_iter
== 0)
2283 && (lra_constraint_iter
> 1
2284 || (! scratch_p
&& ! caller_save_needed
)))
2286 /* Constraint transformations may result in that eliminable
2287 hard regs become uneliminable and pseudos which use them
2288 should be spilled. It is better to do it before pseudo
2291 For example, rs6000 can make
2292 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2293 to use a constant pool. */
2294 lra_eliminate (false, false);
2295 /* Do inheritance only for regular algorithms. */
2301 lra_clear_live_ranges ();
2302 /* As a side-effect of lra_create_live_ranges, we calculate
2303 actual_call_used_reg_set, which is needed during
2305 lra_create_live_ranges (true, true);
2311 lra_clear_live_ranges ();
2312 /* We need live ranges for lra_assign -- so build them. But
2313 don't remove dead insns or change global live info as we
2314 can undo inheritance transformations after inheritance
2315 pseudo assigning. */
2316 lra_create_live_ranges (true, false);
2318 /* If we don't spill non-reload and non-inheritance pseudos,
2319 there is no sense to run memory-memory move coalescing.
2320 If inheritance pseudos were spilled, the memory-memory
2321 moves involving them will be removed by pass undoing
2327 bool spill_p
= !lra_assign ();
2329 if (lra_undo_inheritance ())
2335 lra_create_live_ranges (true, true);
2338 if (lra_coalesce ())
2342 lra_clear_live_ranges ();
2345 /* Don't clear optional reloads bitmap until all constraints are
2346 satisfied as we need to differ them from regular reloads. */
2347 bitmap_clear (&lra_optional_reload_pseudos
);
2348 bitmap_clear (&lra_subreg_reload_pseudos
);
2349 bitmap_clear (&lra_inheritance_pseudos
);
2350 bitmap_clear (&lra_split_regs
);
2353 /* We need full live info for spilling pseudos into
2354 registers instead of memory. */
2355 lra_create_live_ranges (lra_reg_spill_p
, true);
2358 /* We should check necessity for spilling here as the above live
2359 range pass can remove spilled pseudos. */
2360 if (! lra_need_for_spills_p ())
2362 /* Now we know what pseudos should be spilled. Try to
2363 rematerialize them first. */
2366 /* We need full live info -- see the comment above. */
2367 lra_create_live_ranges (lra_reg_spill_p
, true);
2369 if (! lra_need_for_spills_p ())
2373 /* Assignment of stack slots changes elimination offsets for
2374 some eliminations. So update the offsets here. */
2375 lra_eliminate (false, false);
2376 lra_constraint_new_regno_start
= max_reg_num ();
2377 if (lra_bad_spill_regno_start
== INT_MAX
2378 && lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
2379 && lra_rematerialization_iter
> LRA_MAX_REMATERIALIZATION_PASSES
)
2380 /* After switching off inheritance and rematerialization
2381 passes, avoid spilling reload pseudos will be created to
2382 prevent LRA cycling in some complicated cases. */
2383 lra_bad_spill_regno_start
= lra_constraint_new_regno_start
;
2384 lra_assignment_iter_after_spill
= 0;
2386 restore_scratches ();
2387 lra_eliminate (true, false);
2388 lra_final_code_change ();
2389 lra_in_progress
= 0;
2391 lra_clear_live_ranges ();
2392 lra_live_ranges_finish ();
2393 lra_constraints_finish ();
2395 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2396 lra_constraint_insn_stack
.release ();
2397 finish_insn_recog_data ();
2398 regstat_free_n_sets_and_refs ();
2400 reload_completed
= 1;
2401 update_inc_notes ();
2403 inserted_p
= fixup_abnormal_edges ();
2405 /* We've possibly turned single trapping insn into multiple ones. */
2406 if (cfun
->can_throw_non_call_exceptions
)
2409 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2410 bitmap_ones (blocks
);
2411 find_many_sub_basic_blocks (blocks
);
2412 sbitmap_free (blocks
);
2416 commit_edge_insertions ();
2418 /* Replacing pseudos with their memory equivalents might have
2419 created shared rtx. Subsequent passes would get confused
2420 by this, so unshare everything here. */
2421 unshare_all_rtl_again (get_insns ());
2423 #ifdef ENABLE_CHECKING
2427 timevar_pop (TV_LRA
);
2430 /* Called once per compiler to initialize LRA data once. */
2432 lra_init_once (void)
2434 init_insn_code_data_once ();
2437 /* Called once per compiler to finish LRA data which are initialize
2440 lra_finish_once (void)
2442 finish_insn_code_data_once ();