1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts
;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges
;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras
;
118 /* Number of instructions combined in this function. */
120 static int combine_successes
;
122 /* Totals over entire compilation. */
124 static int total_attempts
, total_merges
, total_extras
, total_successes
;
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid
;
135 static int max_uid_cuid
;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
143 BITS_PER_WORD would invoke undefined behavior. Work around it. */
145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
146 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno
;
153 /* Record last point of death of (hard or pseudo) register n. */
156 /* Record last point of modification of (hard or pseudo) register n. */
159 /* The next group of fields allows the recording of the last value assigned
160 to (hard or pseudo) register n. We use this information to see if an
161 operation being processed is redundant given a prior operation performed
162 on the register. For example, an `and' with a constant is redundant if
163 all the zero bits are already known to be turned off.
165 We use an approach similar to that used by cse, but change it in the
168 (1) We do not want to reinitialize at each label.
169 (2) It is useful, but not critical, to know the actual value assigned
170 to a register. Often just its form is helpful.
172 Therefore, we maintain the following fields:
174 last_set_value the last value assigned
175 last_set_label records the value of label_tick when the
176 register was assigned
177 last_set_table_tick records the value of label_tick when a
178 value using the register is assigned
179 last_set_invalid set to nonzero when it is not valid
180 to use the value of this register in some
183 To understand the usage of these tables, it is important to understand
184 the distinction between the value in last_set_value being valid and
185 the register being validly contained in some other expression in the
188 (The next two parameters are out of date).
190 reg_stat[i].last_set_value is valid if it is nonzero, and either
191 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
193 Register I may validly appear in any expression returned for the value
194 of another register if reg_n_sets[i] is 1. It may also appear in the
195 value for register J if reg_stat[j].last_set_invalid is zero, or
196 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
198 If an expression is found in the table containing a register which may
199 not validly appear in an expression, the register is replaced by
200 something that won't match, (clobber (const_int 0)). */
202 /* Record last value assigned to (hard or pseudo) register n. */
206 /* Record the value of label_tick when an expression involving register n
207 is placed in last_set_value. */
209 int last_set_table_tick
;
211 /* Record the value of label_tick when the value for register n is placed in
216 /* These fields are maintained in parallel with last_set_value and are
217 used to store the mode in which the register was last set, the bits
218 that were known to be zero when it was last set, and the number of
219 sign bits copies it was known to have when it was last set. */
221 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
222 char last_set_sign_bit_copies
;
223 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
225 /* Set nonzero if references to register n in expressions should not be
226 used. last_set_invalid is set nonzero when this register is being
227 assigned to and last_set_table_tick == label_tick. */
229 char last_set_invalid
;
231 /* Some registers that are set more than once and used in more than one
232 basic block are nevertheless always set in similar ways. For example,
233 a QImode register may be loaded from memory in two places on a machine
234 where byte loads zero extend.
236 We record in the following fields if a register has some leading bits
237 that are always equal to the sign bit, and what we know about the
238 nonzero bits of a register, specifically which bits are known to be
241 If an entry is zero, it means that we don't know anything special. */
243 unsigned char sign_bit_copies
;
245 unsigned HOST_WIDE_INT nonzero_bits
;
248 static struct reg_stat
*reg_stat
;
250 /* Record the cuid of the last insn that invalidated memory
251 (anything that writes memory, and subroutine calls, but not pushes). */
253 static int mem_last_set
;
255 /* Record the cuid of the last CALL_INSN
256 so we can tell whether a potential combination crosses any calls. */
258 static int last_call_cuid
;
260 /* When `subst' is called, this is the insn that is being modified
261 (by combining in a previous insn). The PATTERN of this insn
262 is still the old pattern partially modified and it should not be
263 looked at, but this may be used to examine the successors of the insn
264 to judge whether a simplification is valid. */
266 static rtx subst_insn
;
268 /* This is the lowest CUID that `subst' is currently dealing with.
269 get_last_value will not return a value if the register was set at or
270 after this CUID. If not for this mechanism, we could get confused if
271 I2 or I1 in try_combine were an insn that used the old value of a register
272 to obtain a new value. In that case, we might erroneously get the
273 new value of the register when we wanted the old one. */
275 static int subst_low_cuid
;
277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 must consider all these registers to be always live. */
280 static HARD_REG_SET newpat_used_regs
;
282 /* This is an insn to which a LOG_LINKS entry has been added. If this
283 insn is the earlier than I2 or I3, combine should rescan starting at
286 static rtx added_links_insn
;
288 /* Basic block in which we are performing combines. */
289 static basic_block this_basic_block
;
291 /* A bitmap indicating which blocks had registers go dead at entry.
292 After combine, we'll need to re-do global life analysis with
293 those blocks as starting points. */
294 static sbitmap refresh_blocks
;
296 /* The following array records the insn_rtx_cost for every insn
297 in the instruction stream. */
299 static int *uid_insn_cost
;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int last_insn_cost
;
305 /* Incremented for each label. */
307 static int label_tick
;
309 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
310 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
312 static enum machine_mode nonzero_bits_mode
;
314 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
315 be safely used. It is zero while computing them and after combine has
316 completed. This former test prevents propagating values based on
317 previously set values, which can be incorrect if a variable is modified
320 static int nonzero_sign_valid
;
323 /* Record one modification to rtl structure
324 to be undone by storing old_contents into *where.
325 is_int is 1 if the contents are an int. */
331 union {rtx r
; int i
;} old_contents
;
332 union {rtx
*r
; int *i
;} where
;
335 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
336 num_undo says how many are currently recorded.
338 other_insn is nonzero if we have modified some other insn in the process
339 of working on subst_insn. It must be verified too. */
348 static struct undobuf undobuf
;
350 /* Number of times the pseudo being substituted for
351 was found and replaced. */
353 static int n_occurrences
;
355 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
357 unsigned HOST_WIDE_INT
,
358 unsigned HOST_WIDE_INT
*);
359 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
361 unsigned int, unsigned int *);
362 static void do_SUBST (rtx
*, rtx
);
363 static void do_SUBST_INT (int *, int);
364 static void init_reg_last (void);
365 static void setup_incoming_promotions (void);
366 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
367 static int cant_combine_insn_p (rtx
);
368 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
369 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
370 static int contains_muldiv (rtx
);
371 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
372 static void undo_all (void);
373 static void undo_commit (void);
374 static rtx
*find_split_point (rtx
*, rtx
);
375 static rtx
subst (rtx
, rtx
, rtx
, int, int);
376 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
377 static rtx
simplify_if_then_else (rtx
);
378 static rtx
simplify_set (rtx
);
379 static rtx
simplify_logical (rtx
);
380 static rtx
expand_compound_operation (rtx
);
381 static rtx
expand_field_assignment (rtx
);
382 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
383 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
384 static rtx
extract_left_shift (rtx
, int);
385 static rtx
make_compound_operation (rtx
, enum rtx_code
);
386 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
387 unsigned HOST_WIDE_INT
*);
388 static rtx
force_to_mode (rtx
, enum machine_mode
,
389 unsigned HOST_WIDE_INT
, rtx
, int);
390 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
391 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
392 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
393 static rtx
make_field_assignment (rtx
);
394 static rtx
apply_distributive_law (rtx
);
395 static rtx
distribute_and_simplify_rtx (rtx
, int);
396 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
397 unsigned HOST_WIDE_INT
);
398 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
399 HOST_WIDE_INT
, enum machine_mode
, int *);
400 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
402 static int recog_for_combine (rtx
*, rtx
, rtx
*);
403 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
404 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
405 static void update_table_tick (rtx
);
406 static void record_value_for_reg (rtx
, rtx
, rtx
);
407 static void check_promoted_subreg (rtx
, rtx
);
408 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
409 static void record_dead_and_set_regs (rtx
);
410 static int get_last_value_validate (rtx
*, rtx
, int, int);
411 static rtx
get_last_value (rtx
);
412 static int use_crosses_set_p (rtx
, int);
413 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
414 static int reg_dead_at_p (rtx
, rtx
);
415 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
416 static int reg_bitfield_target_p (rtx
, rtx
);
417 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
418 static void distribute_links (rtx
);
419 static void mark_used_regs_combine (rtx
);
420 static int insn_cuid (rtx
);
421 static void record_promoted_value (rtx
, rtx
);
422 static int unmentioned_reg_p_1 (rtx
*, void *);
423 static bool unmentioned_reg_p (rtx
, rtx
);
426 /* It is not safe to use ordinary gen_lowpart in combine.
427 See comments in gen_lowpart_for_combine. */
428 #undef RTL_HOOKS_GEN_LOWPART
429 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
431 /* Our implementation of gen_lowpart never emits a new pseudo. */
432 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
433 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
435 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
436 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
438 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
439 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
441 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
444 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
445 insn. The substitution can be undone by undo_all. If INTO is already
446 set to NEWVAL, do not record this change. Because computing NEWVAL might
447 also call SUBST, we have to compute it before we put anything into
451 do_SUBST (rtx
*into
, rtx newval
)
456 if (oldval
== newval
)
459 /* We'd like to catch as many invalid transformations here as
460 possible. Unfortunately, there are way too many mode changes
461 that are perfectly valid, so we'd waste too much effort for
462 little gain doing the checks here. Focus on catching invalid
463 transformations involving integer constants. */
464 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
465 && GET_CODE (newval
) == CONST_INT
)
467 /* Sanity check that we're replacing oldval with a CONST_INT
468 that is a valid sign-extension for the original mode. */
469 gcc_assert (INTVAL (newval
)
470 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
472 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
473 CONST_INT is not valid, because after the replacement, the
474 original mode would be gone. Unfortunately, we can't tell
475 when do_SUBST is called to replace the operand thereof, so we
476 perform this test on oldval instead, checking whether an
477 invalid replacement took place before we got here. */
478 gcc_assert (!(GET_CODE (oldval
) == SUBREG
479 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
480 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
481 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
485 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
487 buf
= xmalloc (sizeof (struct undo
));
491 buf
->old_contents
.r
= oldval
;
494 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
497 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
499 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
500 for the value of a HOST_WIDE_INT value (including CONST_INT) is
504 do_SUBST_INT (int *into
, int newval
)
509 if (oldval
== newval
)
513 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
515 buf
= xmalloc (sizeof (struct undo
));
519 buf
->old_contents
.i
= oldval
;
522 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
525 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
527 /* Subroutine of try_combine. Determine whether the combine replacement
528 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
529 that the original instruction sequence I1, I2 and I3. Note that I1
530 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
531 costs of all instructions can be estimated, and the replacements are
532 more expensive than the original sequence. */
535 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
537 int i1_cost
, i2_cost
, i3_cost
;
538 int new_i2_cost
, new_i3_cost
;
539 int old_cost
, new_cost
;
541 /* Lookup the original insn_rtx_costs. */
542 i2_cost
= INSN_UID (i2
) <= last_insn_cost
543 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
544 i3_cost
= INSN_UID (i3
) <= last_insn_cost
545 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
549 i1_cost
= INSN_UID (i1
) <= last_insn_cost
550 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
551 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
552 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
556 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
560 /* Calculate the replacement insn_rtx_costs. */
561 new_i3_cost
= insn_rtx_cost (newpat
);
564 new_i2_cost
= insn_rtx_cost (newi2pat
);
565 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
566 ? new_i2_cost
+ new_i3_cost
: 0;
570 new_cost
= new_i3_cost
;
574 if (undobuf
.other_insn
)
576 int old_other_cost
, new_other_cost
;
578 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
579 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
580 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
581 if (old_other_cost
> 0 && new_other_cost
> 0)
583 old_cost
+= old_other_cost
;
584 new_cost
+= new_other_cost
;
590 /* Disallow this recombination if both new_cost and old_cost are
591 greater than zero, and new_cost is greater than old cost. */
593 && new_cost
> old_cost
)
600 "rejecting combination of insns %d, %d and %d\n",
601 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
602 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
603 i1_cost
, i2_cost
, i3_cost
, old_cost
);
608 "rejecting combination of insns %d and %d\n",
609 INSN_UID (i2
), INSN_UID (i3
));
610 fprintf (dump_file
, "original costs %d + %d = %d\n",
611 i2_cost
, i3_cost
, old_cost
);
616 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
617 new_i2_cost
, new_i3_cost
, new_cost
);
620 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
626 /* Update the uid_insn_cost array with the replacement costs. */
627 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
628 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
630 uid_insn_cost
[INSN_UID (i1
)] = 0;
635 /* Main entry point for combiner. F is the first insn of the function.
636 NREGS is the first unused pseudo-reg number.
638 Return nonzero if the combiner has turned an indirect jump
639 instruction into a direct jump. */
641 combine_instructions (rtx f
, unsigned int nregs
)
649 rtx links
, nextlinks
;
650 sbitmap_iterator sbi
;
652 int new_direct_jump_p
= 0;
654 combine_attempts
= 0;
657 combine_successes
= 0;
659 combine_max_regno
= nregs
;
661 rtl_hooks
= combine_rtl_hooks
;
663 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
665 init_recog_no_volatile ();
667 /* Compute maximum uid value so uid_cuid can be allocated. */
669 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
670 if (INSN_UID (insn
) > i
)
673 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
676 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
678 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
679 problems when, for example, we have j <<= 1 in a loop. */
681 nonzero_sign_valid
= 0;
683 /* Compute the mapping from uids to cuids.
684 Cuids are numbers assigned to insns, like uids,
685 except that cuids increase monotonically through the code.
687 Scan all SETs and see if we can deduce anything about what
688 bits are known to be zero for some registers and how many copies
689 of the sign bit are known to exist for those registers.
691 Also set any known values so that we can use it while searching
692 for what bits are known to be set. */
696 setup_incoming_promotions ();
698 refresh_blocks
= sbitmap_alloc (last_basic_block
);
699 sbitmap_zero (refresh_blocks
);
701 /* Allocate array of current insn_rtx_costs. */
702 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
703 last_insn_cost
= max_uid_cuid
;
705 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
707 uid_cuid
[INSN_UID (insn
)] = ++i
;
713 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
715 record_dead_and_set_regs (insn
);
718 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
719 if (REG_NOTE_KIND (links
) == REG_INC
)
720 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
724 /* Record the current insn_rtx_cost of this instruction. */
725 if (NONJUMP_INSN_P (insn
))
726 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
728 fprintf(dump_file
, "insn_cost %d: %d\n",
729 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
736 nonzero_sign_valid
= 1;
738 /* Now scan all the insns in forward order. */
744 setup_incoming_promotions ();
746 FOR_EACH_BB (this_basic_block
)
748 for (insn
= BB_HEAD (this_basic_block
);
749 insn
!= NEXT_INSN (BB_END (this_basic_block
));
750 insn
= next
? next
: NEXT_INSN (insn
))
757 else if (INSN_P (insn
))
759 /* See if we know about function return values before this
760 insn based upon SUBREG flags. */
761 check_promoted_subreg (insn
, PATTERN (insn
));
763 /* Try this insn with each insn it links back to. */
765 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
766 if ((next
= try_combine (insn
, XEXP (links
, 0),
767 NULL_RTX
, &new_direct_jump_p
)) != 0)
770 /* Try each sequence of three linked insns ending with this one. */
772 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
774 rtx link
= XEXP (links
, 0);
776 /* If the linked insn has been replaced by a note, then there
777 is no point in pursuing this chain any further. */
781 for (nextlinks
= LOG_LINKS (link
);
783 nextlinks
= XEXP (nextlinks
, 1))
784 if ((next
= try_combine (insn
, link
,
786 &new_direct_jump_p
)) != 0)
791 /* Try to combine a jump insn that uses CC0
792 with a preceding insn that sets CC0, and maybe with its
793 logical predecessor as well.
794 This is how we make decrement-and-branch insns.
795 We need this special code because data flow connections
796 via CC0 do not get entered in LOG_LINKS. */
799 && (prev
= prev_nonnote_insn (insn
)) != 0
800 && NONJUMP_INSN_P (prev
)
801 && sets_cc0_p (PATTERN (prev
)))
803 if ((next
= try_combine (insn
, prev
,
804 NULL_RTX
, &new_direct_jump_p
)) != 0)
807 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
808 nextlinks
= XEXP (nextlinks
, 1))
809 if ((next
= try_combine (insn
, prev
,
811 &new_direct_jump_p
)) != 0)
815 /* Do the same for an insn that explicitly references CC0. */
816 if (NONJUMP_INSN_P (insn
)
817 && (prev
= prev_nonnote_insn (insn
)) != 0
818 && NONJUMP_INSN_P (prev
)
819 && sets_cc0_p (PATTERN (prev
))
820 && GET_CODE (PATTERN (insn
)) == SET
821 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
823 if ((next
= try_combine (insn
, prev
,
824 NULL_RTX
, &new_direct_jump_p
)) != 0)
827 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
828 nextlinks
= XEXP (nextlinks
, 1))
829 if ((next
= try_combine (insn
, prev
,
831 &new_direct_jump_p
)) != 0)
835 /* Finally, see if any of the insns that this insn links to
836 explicitly references CC0. If so, try this insn, that insn,
837 and its predecessor if it sets CC0. */
838 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
839 if (NONJUMP_INSN_P (XEXP (links
, 0))
840 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
841 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
842 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
843 && NONJUMP_INSN_P (prev
)
844 && sets_cc0_p (PATTERN (prev
))
845 && (next
= try_combine (insn
, XEXP (links
, 0),
846 prev
, &new_direct_jump_p
)) != 0)
850 /* Try combining an insn with two different insns whose results it
852 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
853 for (nextlinks
= XEXP (links
, 1); nextlinks
;
854 nextlinks
= XEXP (nextlinks
, 1))
855 if ((next
= try_combine (insn
, XEXP (links
, 0),
857 &new_direct_jump_p
)) != 0)
860 /* Try this insn with each REG_EQUAL note it links back to. */
861 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
864 rtx temp
= XEXP (links
, 0);
865 if ((set
= single_set (temp
)) != 0
866 && (note
= find_reg_equal_equiv_note (temp
)) != 0
867 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
868 /* Avoid using a register that may already been marked
869 dead by an earlier instruction. */
870 && ! unmentioned_reg_p (note
, SET_SRC (set
))
871 && (GET_MODE (note
) == VOIDmode
872 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
873 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
875 /* Temporarily replace the set's source with the
876 contents of the REG_EQUAL note. The insn will
877 be deleted or recognized by try_combine. */
878 rtx orig
= SET_SRC (set
);
879 SET_SRC (set
) = note
;
880 next
= try_combine (insn
, temp
, NULL_RTX
,
884 SET_SRC (set
) = orig
;
889 record_dead_and_set_regs (insn
);
898 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, j
, sbi
)
899 BASIC_BLOCK (j
)->flags
|= BB_DIRTY
;
900 new_direct_jump_p
|= purge_all_dead_edges ();
901 delete_noop_moves ();
903 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
904 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
905 | PROP_KILL_DEAD_CODE
);
908 sbitmap_free (refresh_blocks
);
909 free (uid_insn_cost
);
914 struct undo
*undo
, *next
;
915 for (undo
= undobuf
.frees
; undo
; undo
= next
)
923 total_attempts
+= combine_attempts
;
924 total_merges
+= combine_merges
;
925 total_extras
+= combine_extras
;
926 total_successes
+= combine_successes
;
928 nonzero_sign_valid
= 0;
929 rtl_hooks
= general_rtl_hooks
;
931 /* Make recognizer allow volatile MEMs again. */
934 return new_direct_jump_p
;
937 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
943 for (i
= 0; i
< combine_max_regno
; i
++)
944 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
947 /* Set up any promoted values for incoming argument registers. */
950 setup_incoming_promotions (void)
954 enum machine_mode mode
;
956 rtx first
= get_insns ();
958 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
960 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
961 /* Check whether this register can hold an incoming pointer
962 argument. FUNCTION_ARG_REGNO_P tests outgoing register
963 numbers, so translate if necessary due to register windows. */
964 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
965 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
968 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
971 gen_rtx_CLOBBER (mode
, const0_rtx
)));
976 /* Called via note_stores. If X is a pseudo that is narrower than
977 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
979 If we are setting only a portion of X and we can't figure out what
980 portion, assume all bits will be used since we don't know what will
983 Similarly, set how many bits of X are known to be copies of the sign bit
984 at all locations in the function. This is the smallest number implied
988 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
989 void *data ATTRIBUTE_UNUSED
)
994 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
995 /* If this register is undefined at the start of the file, we can't
996 say what its contents were. */
998 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
, REGNO (x
))
999 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1001 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1003 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1004 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1008 /* If this is a complex assignment, see if we can convert it into a
1009 simple assignment. */
1010 set
= expand_field_assignment (set
);
1012 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1013 set what we know about X. */
1015 if (SET_DEST (set
) == x
1016 || (GET_CODE (SET_DEST (set
)) == SUBREG
1017 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1018 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1019 && SUBREG_REG (SET_DEST (set
)) == x
))
1021 rtx src
= SET_SRC (set
);
1023 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1024 /* If X is narrower than a word and SRC is a non-negative
1025 constant that would appear negative in the mode of X,
1026 sign-extend it for use in reg_stat[].nonzero_bits because some
1027 machines (maybe most) will actually do the sign-extension
1028 and this is the conservative approach.
1030 ??? For 2.5, try to tighten up the MD files in this regard
1031 instead of this kludge. */
1033 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1034 && GET_CODE (src
) == CONST_INT
1036 && 0 != (INTVAL (src
)
1037 & ((HOST_WIDE_INT
) 1
1038 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1039 src
= GEN_INT (INTVAL (src
)
1040 | ((HOST_WIDE_INT
) (-1)
1041 << GET_MODE_BITSIZE (GET_MODE (x
))));
1044 /* Don't call nonzero_bits if it cannot change anything. */
1045 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1046 reg_stat
[REGNO (x
)].nonzero_bits
1047 |= nonzero_bits (src
, nonzero_bits_mode
);
1048 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1049 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1050 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1051 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1055 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1056 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1061 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1062 insns that were previously combined into I3 or that will be combined
1063 into the merger of INSN and I3.
1065 Return 0 if the combination is not allowed for any reason.
1067 If the combination is allowed, *PDEST will be set to the single
1068 destination of INSN and *PSRC to the single source, and this function
1072 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1073 rtx
*pdest
, rtx
*psrc
)
1076 rtx set
= 0, src
, dest
;
1081 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1082 && next_active_insn (succ
) == i3
)
1083 : next_active_insn (insn
) == i3
);
1085 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1086 or a PARALLEL consisting of such a SET and CLOBBERs.
1088 If INSN has CLOBBER parallel parts, ignore them for our processing.
1089 By definition, these happen during the execution of the insn. When it
1090 is merged with another insn, all bets are off. If they are, in fact,
1091 needed and aren't also supplied in I3, they may be added by
1092 recog_for_combine. Otherwise, it won't match.
1094 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1097 Get the source and destination of INSN. If more than one, can't
1100 if (GET_CODE (PATTERN (insn
)) == SET
)
1101 set
= PATTERN (insn
);
1102 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1103 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1105 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1107 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1110 switch (GET_CODE (elt
))
1112 /* This is important to combine floating point insns
1113 for the SH4 port. */
1115 /* Combining an isolated USE doesn't make sense.
1116 We depend here on combinable_i3pat to reject them. */
1117 /* The code below this loop only verifies that the inputs of
1118 the SET in INSN do not change. We call reg_set_between_p
1119 to verify that the REG in the USE does not change between
1121 If the USE in INSN was for a pseudo register, the matching
1122 insn pattern will likely match any register; combining this
1123 with any other USE would only be safe if we knew that the
1124 used registers have identical values, or if there was
1125 something to tell them apart, e.g. different modes. For
1126 now, we forgo such complicated tests and simply disallow
1127 combining of USES of pseudo registers with any other USE. */
1128 if (REG_P (XEXP (elt
, 0))
1129 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1131 rtx i3pat
= PATTERN (i3
);
1132 int i
= XVECLEN (i3pat
, 0) - 1;
1133 unsigned int regno
= REGNO (XEXP (elt
, 0));
1137 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1139 if (GET_CODE (i3elt
) == USE
1140 && REG_P (XEXP (i3elt
, 0))
1141 && (REGNO (XEXP (i3elt
, 0)) == regno
1142 ? reg_set_between_p (XEXP (elt
, 0),
1143 PREV_INSN (insn
), i3
)
1144 : regno
>= FIRST_PSEUDO_REGISTER
))
1151 /* We can ignore CLOBBERs. */
1156 /* Ignore SETs whose result isn't used but not those that
1157 have side-effects. */
1158 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1159 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1160 || INTVAL (XEXP (note
, 0)) <= 0)
1161 && ! side_effects_p (elt
))
1164 /* If we have already found a SET, this is a second one and
1165 so we cannot combine with this insn. */
1173 /* Anything else means we can't combine. */
1179 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1180 so don't do anything with it. */
1181 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1190 set
= expand_field_assignment (set
);
1191 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1193 /* Don't eliminate a store in the stack pointer. */
1194 if (dest
== stack_pointer_rtx
1195 /* Don't combine with an insn that sets a register to itself if it has
1196 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1197 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1198 /* Can't merge an ASM_OPERANDS. */
1199 || GET_CODE (src
) == ASM_OPERANDS
1200 /* Can't merge a function call. */
1201 || GET_CODE (src
) == CALL
1202 /* Don't eliminate a function call argument. */
1204 && (find_reg_fusage (i3
, USE
, dest
)
1206 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1207 && global_regs
[REGNO (dest
)])))
1208 /* Don't substitute into an incremented register. */
1209 || FIND_REG_INC_NOTE (i3
, dest
)
1210 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1211 /* Don't substitute into a non-local goto, this confuses CFG. */
1212 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1214 /* Don't combine the end of a libcall into anything. */
1215 /* ??? This gives worse code, and appears to be unnecessary, since no
1216 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1217 use REG_RETVAL notes for noconflict blocks, but other code here
1218 makes sure that those insns don't disappear. */
1219 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1221 /* Make sure that DEST is not used after SUCC but before I3. */
1222 || (succ
&& ! all_adjacent
1223 && reg_used_between_p (dest
, succ
, i3
))
1224 /* Make sure that the value that is to be substituted for the register
1225 does not use any registers whose values alter in between. However,
1226 If the insns are adjacent, a use can't cross a set even though we
1227 think it might (this can happen for a sequence of insns each setting
1228 the same destination; last_set of that register might point to
1229 a NOTE). If INSN has a REG_EQUIV note, the register is always
1230 equivalent to the memory so the substitution is valid even if there
1231 are intervening stores. Also, don't move a volatile asm or
1232 UNSPEC_VOLATILE across any other insns. */
1235 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1236 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1237 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1238 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1239 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1240 better register allocation by not doing the combine. */
1241 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1242 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1243 /* Don't combine across a CALL_INSN, because that would possibly
1244 change whether the life span of some REGs crosses calls or not,
1245 and it is a pain to update that information.
1246 Exception: if source is a constant, moving it later can't hurt.
1247 Accept that special case, because it helps -fforce-addr a lot. */
1248 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1251 /* DEST must either be a REG or CC0. */
1254 /* If register alignment is being enforced for multi-word items in all
1255 cases except for parameters, it is possible to have a register copy
1256 insn referencing a hard register that is not allowed to contain the
1257 mode being copied and which would not be valid as an operand of most
1258 insns. Eliminate this problem by not combining with such an insn.
1260 Also, on some machines we don't want to extend the life of a hard
1264 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1265 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1266 /* Don't extend the life of a hard register unless it is
1267 user variable (if we have few registers) or it can't
1268 fit into the desired register (meaning something special
1270 Also avoid substituting a return register into I3, because
1271 reload can't handle a conflict with constraints of other
1273 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1274 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1277 else if (GET_CODE (dest
) != CC0
)
1281 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1282 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1283 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1285 /* Don't substitute for a register intended as a clobberable
1287 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1288 if (rtx_equal_p (reg
, dest
))
1291 /* If the clobber represents an earlyclobber operand, we must not
1292 substitute an expression containing the clobbered register.
1293 As we do not analyze the constraint strings here, we have to
1294 make the conservative assumption. However, if the register is
1295 a fixed hard reg, the clobber cannot represent any operand;
1296 we leave it up to the machine description to either accept or
1297 reject use-and-clobber patterns. */
1299 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1300 || !fixed_regs
[REGNO (reg
)])
1301 if (reg_overlap_mentioned_p (reg
, src
))
1305 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1306 or not), reject, unless nothing volatile comes between it and I3 */
1308 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1310 /* Make sure succ doesn't contain a volatile reference. */
1311 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1314 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1315 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1319 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1320 to be an explicit register variable, and was chosen for a reason. */
1322 if (GET_CODE (src
) == ASM_OPERANDS
1323 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1326 /* If there are any volatile insns between INSN and I3, reject, because
1327 they might affect machine state. */
1329 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1330 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1333 /* If INSN contains an autoincrement or autodecrement, make sure that
1334 register is not used between there and I3, and not already used in
1335 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1336 Also insist that I3 not be a jump; if it were one
1337 and the incremented register were spilled, we would lose. */
1340 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1341 if (REG_NOTE_KIND (link
) == REG_INC
1343 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1344 || (pred
!= NULL_RTX
1345 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1346 || (succ
!= NULL_RTX
1347 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1348 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1353 /* Don't combine an insn that follows a CC0-setting insn.
1354 An insn that uses CC0 must not be separated from the one that sets it.
1355 We do, however, allow I2 to follow a CC0-setting insn if that insn
1356 is passed as I1; in that case it will be deleted also.
1357 We also allow combining in this case if all the insns are adjacent
1358 because that would leave the two CC0 insns adjacent as well.
1359 It would be more logical to test whether CC0 occurs inside I1 or I2,
1360 but that would be much slower, and this ought to be equivalent. */
1362 p
= prev_nonnote_insn (insn
);
1363 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1368 /* If we get here, we have passed all the tests and the combination is
1377 /* LOC is the location within I3 that contains its pattern or the component
1378 of a PARALLEL of the pattern. We validate that it is valid for combining.
1380 One problem is if I3 modifies its output, as opposed to replacing it
1381 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1382 so would produce an insn that is not equivalent to the original insns.
1386 (set (reg:DI 101) (reg:DI 100))
1387 (set (subreg:SI (reg:DI 101) 0) <foo>)
1389 This is NOT equivalent to:
1391 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1392 (set (reg:DI 101) (reg:DI 100))])
1394 Not only does this modify 100 (in which case it might still be valid
1395 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1397 We can also run into a problem if I2 sets a register that I1
1398 uses and I1 gets directly substituted into I3 (not via I2). In that
1399 case, we would be getting the wrong value of I2DEST into I3, so we
1400 must reject the combination. This case occurs when I2 and I1 both
1401 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1402 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1403 of a SET must prevent combination from occurring.
1405 Before doing the above check, we first try to expand a field assignment
1406 into a set of logical operations.
1408 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1409 we place a register that is both set and used within I3. If more than one
1410 such register is detected, we fail.
1412 Return 1 if the combination is valid, zero otherwise. */
1415 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1416 int i1_not_in_src
, rtx
*pi3dest_killed
)
1420 if (GET_CODE (x
) == SET
)
1423 rtx dest
= SET_DEST (set
);
1424 rtx src
= SET_SRC (set
);
1425 rtx inner_dest
= dest
;
1427 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1428 || GET_CODE (inner_dest
) == SUBREG
1429 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1430 inner_dest
= XEXP (inner_dest
, 0);
1432 /* Check for the case where I3 modifies its output, as discussed
1433 above. We don't want to prevent pseudos from being combined
1434 into the address of a MEM, so only prevent the combination if
1435 i1 or i2 set the same MEM. */
1436 if ((inner_dest
!= dest
&&
1437 (!MEM_P (inner_dest
)
1438 || rtx_equal_p (i2dest
, inner_dest
)
1439 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1440 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1441 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1443 /* This is the same test done in can_combine_p except we can't test
1444 all_adjacent; we don't have to, since this instruction will stay
1445 in place, thus we are not considering increasing the lifetime of
1448 Also, if this insn sets a function argument, combining it with
1449 something that might need a spill could clobber a previous
1450 function argument; the all_adjacent test in can_combine_p also
1451 checks this; here, we do a more specific test for this case. */
1453 || (REG_P (inner_dest
)
1454 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1455 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1456 GET_MODE (inner_dest
))))
1457 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1460 /* If DEST is used in I3, it is being killed in this insn,
1461 so record that for later.
1462 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1463 STACK_POINTER_REGNUM, since these are always considered to be
1464 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1465 if (pi3dest_killed
&& REG_P (dest
)
1466 && reg_referenced_p (dest
, PATTERN (i3
))
1467 && REGNO (dest
) != FRAME_POINTER_REGNUM
1468 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1469 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1471 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1472 && (REGNO (dest
) != ARG_POINTER_REGNUM
1473 || ! fixed_regs
[REGNO (dest
)])
1475 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1477 if (*pi3dest_killed
)
1480 *pi3dest_killed
= dest
;
1484 else if (GET_CODE (x
) == PARALLEL
)
1488 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1489 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1490 i1_not_in_src
, pi3dest_killed
))
1497 /* Return 1 if X is an arithmetic expression that contains a multiplication
1498 and division. We don't count multiplications by powers of two here. */
1501 contains_muldiv (rtx x
)
1503 switch (GET_CODE (x
))
1505 case MOD
: case DIV
: case UMOD
: case UDIV
:
1509 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1510 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1513 return contains_muldiv (XEXP (x
, 0))
1514 || contains_muldiv (XEXP (x
, 1));
1517 return contains_muldiv (XEXP (x
, 0));
1523 /* Determine whether INSN can be used in a combination. Return nonzero if
1524 not. This is used in try_combine to detect early some cases where we
1525 can't perform combinations. */
1528 cant_combine_insn_p (rtx insn
)
1533 /* If this isn't really an insn, we can't do anything.
1534 This can occur when flow deletes an insn that it has merged into an
1535 auto-increment address. */
1536 if (! INSN_P (insn
))
1539 /* Never combine loads and stores involving hard regs that are likely
1540 to be spilled. The register allocator can usually handle such
1541 reg-reg moves by tying. If we allow the combiner to make
1542 substitutions of likely-spilled regs, reload might die.
1543 As an exception, we allow combinations involving fixed regs; these are
1544 not available to the register allocator so there's no risk involved. */
1546 set
= single_set (insn
);
1549 src
= SET_SRC (set
);
1550 dest
= SET_DEST (set
);
1551 if (GET_CODE (src
) == SUBREG
)
1552 src
= SUBREG_REG (src
);
1553 if (GET_CODE (dest
) == SUBREG
)
1554 dest
= SUBREG_REG (dest
);
1555 if (REG_P (src
) && REG_P (dest
)
1556 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1557 && ! fixed_regs
[REGNO (src
)]
1558 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1559 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1560 && ! fixed_regs
[REGNO (dest
)]
1561 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1567 struct likely_spilled_retval_info
1569 unsigned regno
, nregs
;
1573 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1574 hard registers that are known to be written to / clobbered in full. */
1576 likely_spilled_retval_1 (rtx x
, rtx set
, void *data
)
1578 struct likely_spilled_retval_info
*info
= data
;
1579 unsigned regno
, nregs
;
1582 if (!REG_P (XEXP (set
, 0)))
1585 if (regno
>= info
->regno
+ info
->nregs
)
1587 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1588 if (regno
+ nregs
<= info
->regno
)
1590 new_mask
= (2U << (nregs
- 1)) - 1;
1591 if (regno
< info
->regno
)
1592 new_mask
>>= info
->regno
- regno
;
1594 new_mask
<<= regno
- info
->regno
;
1595 info
->mask
&= new_mask
;
1598 /* Return nonzero iff part of the return value is live during INSN, and
1599 it is likely spilled. This can happen when more than one insn is needed
1600 to copy the return value, e.g. when we consider to combine into the
1601 second copy insn for a complex value. */
1604 likely_spilled_retval_p (rtx insn
)
1606 rtx use
= BB_END (this_basic_block
);
1608 unsigned regno
, nregs
;
1609 /* We assume here that no machine mode needs more than
1610 32 hard registers when the value overlaps with a register
1611 for which FUNCTION_VALUE_REGNO_P is true. */
1613 struct likely_spilled_retval_info info
;
1615 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
1617 reg
= XEXP (PATTERN (use
), 0);
1618 if (!REG_P (reg
) || !FUNCTION_VALUE_REGNO_P (REGNO (reg
)))
1620 regno
= REGNO (reg
);
1621 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1624 mask
= (2U << (nregs
- 1)) - 1;
1626 /* Disregard parts of the return value that are set later. */
1630 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
1631 note_stores (PATTERN (insn
), likely_spilled_retval_1
, &info
);
1634 /* Check if any of the (probably) live return value registers is
1639 if ((mask
& 1 << nregs
)
1640 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno
+ nregs
)))
1646 /* Adjust INSN after we made a change to its destination.
1648 Changing the destination can invalidate notes that say something about
1649 the results of the insn and a LOG_LINK pointing to the insn. */
1652 adjust_for_new_dest (rtx insn
)
1656 /* For notes, be conservative and simply remove them. */
1657 loc
= ®_NOTES (insn
);
1660 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1661 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1662 *loc
= XEXP (*loc
, 1);
1664 loc
= &XEXP (*loc
, 1);
1667 /* The new insn will have a destination that was previously the destination
1668 of an insn just above it. Call distribute_links to make a LOG_LINK from
1669 the next use of that destination. */
1670 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1673 /* Return TRUE if combine can reuse reg X in mode MODE.
1674 ADDED_SETS is nonzero if the original set is still required. */
1676 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
1684 /* Allow hard registers if the new mode is legal, and occupies no more
1685 registers than the old mode. */
1686 if (regno
< FIRST_PSEUDO_REGISTER
)
1687 return (HARD_REGNO_MODE_OK (regno
, mode
)
1688 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
1689 >= hard_regno_nregs
[regno
][mode
]));
1691 /* Or a pseudo that is only used once. */
1692 return (REG_N_SETS (regno
) == 1 && !added_sets
1693 && !REG_USERVAR_P (x
));
1696 /* Try to combine the insns I1 and I2 into I3.
1697 Here I1 and I2 appear earlier than I3.
1698 I1 can be zero; then we combine just I2 into I3.
1700 If we are combining three insns and the resulting insn is not recognized,
1701 try splitting it into two insns. If that happens, I2 and I3 are retained
1702 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1705 Return 0 if the combination does not work. Then nothing is changed.
1706 If we did the combination, return the insn at which combine should
1709 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1710 new direct jump instruction. */
1713 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1715 /* New patterns for I3 and I2, respectively. */
1716 rtx newpat
, newi2pat
= 0;
1717 rtvec newpat_vec_with_clobbers
= 0;
1718 int substed_i2
= 0, substed_i1
= 0;
1719 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1720 int added_sets_1
, added_sets_2
;
1721 /* Total number of SETs to put into I3. */
1723 /* Nonzero if I2's body now appears in I3. */
1725 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1726 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1727 /* Contains I3 if the destination of I3 is used in its source, which means
1728 that the old life of I3 is being killed. If that usage is placed into
1729 I2 and not in I3, a REG_DEAD note must be made. */
1730 rtx i3dest_killed
= 0;
1731 /* SET_DEST and SET_SRC of I2 and I1. */
1732 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1733 /* PATTERN (I2), or a copy of it in certain cases. */
1735 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1736 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1737 int i2dest_killed
= 0, i1dest_killed
= 0;
1738 int i1_feeds_i3
= 0;
1739 /* Notes that must be added to REG_NOTES in I3 and I2. */
1740 rtx new_i3_notes
, new_i2_notes
;
1741 /* Notes that we substituted I3 into I2 instead of the normal case. */
1742 int i3_subst_into_i2
= 0;
1743 /* Notes that I1, I2 or I3 is a MULT operation. */
1752 /* Exit early if one of the insns involved can't be used for
1754 if (cant_combine_insn_p (i3
)
1755 || cant_combine_insn_p (i2
)
1756 || (i1
&& cant_combine_insn_p (i1
))
1757 || likely_spilled_retval_p (i3
)
1758 /* We also can't do anything if I3 has a
1759 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1762 /* ??? This gives worse code, and appears to be unnecessary, since no
1763 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1764 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1770 undobuf
.other_insn
= 0;
1772 /* Reset the hard register usage information. */
1773 CLEAR_HARD_REG_SET (newpat_used_regs
);
1775 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1776 code below, set I1 to be the earlier of the two insns. */
1777 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1778 temp
= i1
, i1
= i2
, i2
= temp
;
1780 added_links_insn
= 0;
1782 /* First check for one important special-case that the code below will
1783 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1784 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1785 we may be able to replace that destination with the destination of I3.
1786 This occurs in the common code where we compute both a quotient and
1787 remainder into a structure, in which case we want to do the computation
1788 directly into the structure to avoid register-register copies.
1790 Note that this case handles both multiple sets in I2 and also
1791 cases where I2 has a number of CLOBBER or PARALLELs.
1793 We make very conservative checks below and only try to handle the
1794 most common cases of this. For example, we only handle the case
1795 where I2 and I3 are adjacent to avoid making difficult register
1798 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1799 && REG_P (SET_SRC (PATTERN (i3
)))
1800 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1801 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1802 && GET_CODE (PATTERN (i2
)) == PARALLEL
1803 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1804 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1805 below would need to check what is inside (and reg_overlap_mentioned_p
1806 doesn't support those codes anyway). Don't allow those destinations;
1807 the resulting insn isn't likely to be recognized anyway. */
1808 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1809 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1810 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1811 SET_DEST (PATTERN (i3
)))
1812 && next_real_insn (i2
) == i3
)
1814 rtx p2
= PATTERN (i2
);
1816 /* Make sure that the destination of I3,
1817 which we are going to substitute into one output of I2,
1818 is not used within another output of I2. We must avoid making this:
1819 (parallel [(set (mem (reg 69)) ...)
1820 (set (reg 69) ...)])
1821 which is not well-defined as to order of actions.
1822 (Besides, reload can't handle output reloads for this.)
1824 The problem can also happen if the dest of I3 is a memory ref,
1825 if another dest in I2 is an indirect memory ref. */
1826 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1827 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1828 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1829 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1830 SET_DEST (XVECEXP (p2
, 0, i
))))
1833 if (i
== XVECLEN (p2
, 0))
1834 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1835 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1836 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1837 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1842 subst_low_cuid
= INSN_CUID (i2
);
1844 added_sets_2
= added_sets_1
= 0;
1845 i2dest
= SET_SRC (PATTERN (i3
));
1846 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
1848 /* Replace the dest in I2 with our dest and make the resulting
1849 insn the new pattern for I3. Then skip to where we
1850 validate the pattern. Everything was set up above. */
1851 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1852 SET_DEST (PATTERN (i3
)));
1855 i3_subst_into_i2
= 1;
1856 goto validate_replacement
;
1860 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1861 one of those words to another constant, merge them by making a new
1864 && (temp
= single_set (i2
)) != 0
1865 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1866 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1867 && REG_P (SET_DEST (temp
))
1868 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1869 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1870 && GET_CODE (PATTERN (i3
)) == SET
1871 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1872 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1873 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1874 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1875 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1877 HOST_WIDE_INT lo
, hi
;
1879 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1880 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1883 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1884 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1887 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1889 /* We don't handle the case of the target word being wider
1890 than a host wide int. */
1891 gcc_assert (HOST_BITS_PER_WIDE_INT
>= BITS_PER_WORD
);
1893 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1894 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1895 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1897 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1898 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1899 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1901 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1902 >> (HOST_BITS_PER_WIDE_INT
- 1));
1904 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1905 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1906 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1907 (INTVAL (SET_SRC (PATTERN (i3
)))));
1909 hi
= lo
< 0 ? -1 : 0;
1912 /* We don't handle the case of the higher word not fitting
1913 entirely in either hi or lo. */
1918 subst_low_cuid
= INSN_CUID (i2
);
1919 added_sets_2
= added_sets_1
= 0;
1920 i2dest
= SET_DEST (temp
);
1921 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
1923 SUBST (SET_SRC (temp
),
1924 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1926 newpat
= PATTERN (i2
);
1927 goto validate_replacement
;
1931 /* If we have no I1 and I2 looks like:
1932 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1934 make up a dummy I1 that is
1937 (set (reg:CC X) (compare:CC Y (const_int 0)))
1939 (We can ignore any trailing CLOBBERs.)
1941 This undoes a previous combination and allows us to match a branch-and-
1944 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1945 && XVECLEN (PATTERN (i2
), 0) >= 2
1946 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1947 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1949 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1950 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1951 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1952 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
1953 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1954 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1956 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1957 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1962 /* We make I1 with the same INSN_UID as I2. This gives it
1963 the same INSN_CUID for value tracking. Our fake I1 will
1964 never appear in the insn stream so giving it the same INSN_UID
1965 as I2 will not cause a problem. */
1967 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1968 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1969 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1972 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1973 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1974 SET_DEST (PATTERN (i1
)));
1979 /* Verify that I2 and I1 are valid for combining. */
1980 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1981 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1987 /* Record whether I2DEST is used in I2SRC and similarly for the other
1988 cases. Knowing this will help in register status updating below. */
1989 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1990 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1991 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1992 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
1993 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
1995 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1997 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1999 /* Ensure that I3's pattern can be the destination of combines. */
2000 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
2001 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
2008 /* See if any of the insns is a MULT operation. Unless one is, we will
2009 reject a combination that is, since it must be slower. Be conservative
2011 if (GET_CODE (i2src
) == MULT
2012 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2013 || (GET_CODE (PATTERN (i3
)) == SET
2014 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2017 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2018 We used to do this EXCEPT in one case: I3 has a post-inc in an
2019 output operand. However, that exception can give rise to insns like
2021 which is a famous insn on the PDP-11 where the value of r3 used as the
2022 source was model-dependent. Avoid this sort of thing. */
2025 if (!(GET_CODE (PATTERN (i3
)) == SET
2026 && REG_P (SET_SRC (PATTERN (i3
)))
2027 && MEM_P (SET_DEST (PATTERN (i3
)))
2028 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2029 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2030 /* It's not the exception. */
2033 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2034 if (REG_NOTE_KIND (link
) == REG_INC
2035 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2037 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2044 /* See if the SETs in I1 or I2 need to be kept around in the merged
2045 instruction: whenever the value set there is still needed past I3.
2046 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2048 For the SET in I1, we have two cases: If I1 and I2 independently
2049 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2050 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2051 in I1 needs to be kept around unless I1DEST dies or is set in either
2052 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2053 I1DEST. If so, we know I1 feeds into I2. */
2055 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
2058 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
2059 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
2061 /* If the set in I2 needs to be kept around, we must make a copy of
2062 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2063 PATTERN (I2), we are only substituting for the original I1DEST, not into
2064 an already-substituted copy. This also prevents making self-referential
2065 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2068 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
2069 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
2073 i2pat
= copy_rtx (i2pat
);
2077 /* Substitute in the latest insn for the regs set by the earlier ones. */
2079 maxreg
= max_reg_num ();
2083 /* It is possible that the source of I2 or I1 may be performing an
2084 unneeded operation, such as a ZERO_EXTEND of something that is known
2085 to have the high part zero. Handle that case by letting subst look at
2086 the innermost one of them.
2088 Another way to do this would be to have a function that tries to
2089 simplify a single insn instead of merging two or more insns. We don't
2090 do this because of the potential of infinite loops and because
2091 of the potential extra memory required. However, doing it the way
2092 we are is a bit of a kludge and doesn't catch all cases.
2094 But only do this if -fexpensive-optimizations since it slows things down
2095 and doesn't usually win. */
2097 if (flag_expensive_optimizations
)
2099 /* Pass pc_rtx so no substitutions are done, just simplifications. */
2102 subst_low_cuid
= INSN_CUID (i1
);
2103 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
2107 subst_low_cuid
= INSN_CUID (i2
);
2108 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
2113 /* Many machines that don't use CC0 have insns that can both perform an
2114 arithmetic operation and set the condition code. These operations will
2115 be represented as a PARALLEL with the first element of the vector
2116 being a COMPARE of an arithmetic operation with the constant zero.
2117 The second element of the vector will set some pseudo to the result
2118 of the same arithmetic operation. If we simplify the COMPARE, we won't
2119 match such a pattern and so will generate an extra insn. Here we test
2120 for this case, where both the comparison and the operation result are
2121 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2122 I2SRC. Later we will make the PARALLEL that contains I2. */
2124 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2125 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2126 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2127 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2129 #ifdef SELECT_CC_MODE
2131 enum machine_mode compare_mode
;
2134 newpat
= PATTERN (i3
);
2135 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2139 #ifdef SELECT_CC_MODE
2140 /* See if a COMPARE with the operand we substituted in should be done
2141 with the mode that is currently being used. If not, do the same
2142 processing we do in `subst' for a SET; namely, if the destination
2143 is used only once, try to replace it with a register of the proper
2144 mode and also replace the COMPARE. */
2145 if (undobuf
.other_insn
== 0
2146 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2147 &undobuf
.other_insn
))
2148 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2150 != GET_MODE (SET_DEST (newpat
))))
2152 if (can_change_dest_mode(SET_DEST (newpat
), added_sets_2
,
2155 unsigned int regno
= REGNO (SET_DEST (newpat
));
2156 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
2158 if (regno
>= FIRST_PSEUDO_REGISTER
)
2159 SUBST (regno_reg_rtx
[regno
], new_dest
);
2161 SUBST (SET_DEST (newpat
), new_dest
);
2162 SUBST (XEXP (*cc_use
, 0), new_dest
);
2163 SUBST (SET_SRC (newpat
),
2164 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2167 undobuf
.other_insn
= 0;
2174 n_occurrences
= 0; /* `subst' counts here */
2176 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2177 need to make a unique copy of I2SRC each time we substitute it
2178 to avoid self-referential rtl. */
2180 subst_low_cuid
= INSN_CUID (i2
);
2181 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2182 ! i1_feeds_i3
&& i1dest_in_i1src
);
2185 /* Record whether i2's body now appears within i3's body. */
2186 i2_is_used
= n_occurrences
;
2189 /* If we already got a failure, don't try to do more. Otherwise,
2190 try to substitute in I1 if we have it. */
2192 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2194 /* Before we can do this substitution, we must redo the test done
2195 above (see detailed comments there) that ensures that I1DEST
2196 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2198 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2206 subst_low_cuid
= INSN_CUID (i1
);
2207 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2211 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2212 to count all the ways that I2SRC and I1SRC can be used. */
2213 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2214 && i2_is_used
+ added_sets_2
> 1)
2215 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2216 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2218 /* Fail if we tried to make a new register. */
2219 || max_reg_num () != maxreg
2220 /* Fail if we couldn't do something and have a CLOBBER. */
2221 || GET_CODE (newpat
) == CLOBBER
2222 /* Fail if this new pattern is a MULT and we didn't have one before
2223 at the outer level. */
2224 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2231 /* If the actions of the earlier insns must be kept
2232 in addition to substituting them into the latest one,
2233 we must make a new PARALLEL for the latest insn
2234 to hold additional the SETs. */
2236 if (added_sets_1
|| added_sets_2
)
2240 if (GET_CODE (newpat
) == PARALLEL
)
2242 rtvec old
= XVEC (newpat
, 0);
2243 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2244 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2245 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2246 sizeof (old
->elem
[0]) * old
->num_elem
);
2251 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2252 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2253 XVECEXP (newpat
, 0, 0) = old
;
2257 XVECEXP (newpat
, 0, --total_sets
)
2258 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2259 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2263 /* If there is no I1, use I2's body as is. We used to also not do
2264 the subst call below if I2 was substituted into I3,
2265 but that could lose a simplification. */
2267 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2269 /* See comment where i2pat is assigned. */
2270 XVECEXP (newpat
, 0, --total_sets
)
2271 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2275 /* We come here when we are replacing a destination in I2 with the
2276 destination of I3. */
2277 validate_replacement
:
2279 /* Note which hard regs this insn has as inputs. */
2280 mark_used_regs_combine (newpat
);
2282 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2283 consider splitting this pattern, we might need these clobbers. */
2284 if (i1
&& GET_CODE (newpat
) == PARALLEL
2285 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
2287 int len
= XVECLEN (newpat
, 0);
2289 newpat_vec_with_clobbers
= rtvec_alloc (len
);
2290 for (i
= 0; i
< len
; i
++)
2291 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
2294 /* Is the result of combination a valid instruction? */
2295 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2297 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2298 the second SET's destination is a register that is unused and isn't
2299 marked as an instruction that might trap in an EH region. In that case,
2300 we just need the first SET. This can occur when simplifying a divmod
2301 insn. We *must* test for this case here because the code below that
2302 splits two independent SETs doesn't handle this case correctly when it
2303 updates the register status.
2305 It's pointless doing this if we originally had two sets, one from
2306 i3, and one from i2. Combining then splitting the parallel results
2307 in the original i2 again plus an invalid insn (which we delete).
2308 The net effect is only to move instructions around, which makes
2309 debug info less accurate.
2311 Also check the case where the first SET's destination is unused.
2312 That would not cause incorrect code, but does cause an unneeded
2315 if (insn_code_number
< 0
2316 && !(added_sets_2
&& i1
== 0)
2317 && GET_CODE (newpat
) == PARALLEL
2318 && XVECLEN (newpat
, 0) == 2
2319 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2320 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2321 && asm_noperands (newpat
) < 0)
2323 rtx set0
= XVECEXP (newpat
, 0, 0);
2324 rtx set1
= XVECEXP (newpat
, 0, 1);
2327 if (((REG_P (SET_DEST (set1
))
2328 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2329 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2330 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2331 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2332 || INTVAL (XEXP (note
, 0)) <= 0)
2333 && ! side_effects_p (SET_SRC (set1
)))
2336 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2339 else if (((REG_P (SET_DEST (set0
))
2340 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2341 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2342 && find_reg_note (i3
, REG_UNUSED
,
2343 SUBREG_REG (SET_DEST (set0
)))))
2344 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2345 || INTVAL (XEXP (note
, 0)) <= 0)
2346 && ! side_effects_p (SET_SRC (set0
)))
2349 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2351 if (insn_code_number
>= 0)
2353 /* If we will be able to accept this, we have made a
2354 change to the destination of I3. This requires us to
2355 do a few adjustments. */
2357 PATTERN (i3
) = newpat
;
2358 adjust_for_new_dest (i3
);
2363 /* If we were combining three insns and the result is a simple SET
2364 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2365 insns. There are two ways to do this. It can be split using a
2366 machine-specific method (like when you have an addition of a large
2367 constant) or by combine in the function find_split_point. */
2369 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2370 && asm_noperands (newpat
) < 0)
2372 rtx m_split
, *split
;
2373 rtx ni2dest
= i2dest
;
2375 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2376 use I2DEST as a scratch register will help. In the latter case,
2377 convert I2DEST to the mode of the source of NEWPAT if we can. */
2379 m_split
= split_insns (newpat
, i3
);
2381 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2382 inputs of NEWPAT. */
2384 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2385 possible to try that as a scratch reg. This would require adding
2386 more code to make it work though. */
2388 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2390 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
2391 /* If I2DEST is a hard register or the only use of a pseudo,
2392 we can change its mode. */
2393 if (new_mode
!= GET_MODE (i2dest
)
2394 && new_mode
!= VOIDmode
2395 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
2396 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2399 m_split
= split_insns (gen_rtx_PARALLEL
2401 gen_rtvec (2, newpat
,
2402 gen_rtx_CLOBBER (VOIDmode
,
2405 /* If the split with the mode-changed register didn't work, try
2406 the original register. */
2407 if (! m_split
&& ni2dest
!= i2dest
)
2410 m_split
= split_insns (gen_rtx_PARALLEL
2412 gen_rtvec (2, newpat
,
2413 gen_rtx_CLOBBER (VOIDmode
,
2419 /* If recog_for_combine has discarded clobbers, try to use them
2420 again for the split. */
2421 if (m_split
== 0 && newpat_vec_with_clobbers
)
2423 = split_insns (gen_rtx_PARALLEL (VOIDmode
,
2424 newpat_vec_with_clobbers
), i3
);
2426 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2428 m_split
= PATTERN (m_split
);
2429 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2430 if (insn_code_number
>= 0)
2433 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2434 && (next_real_insn (i2
) == i3
2435 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2438 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2439 newi2pat
= PATTERN (m_split
);
2441 i3set
= single_set (NEXT_INSN (m_split
));
2442 i2set
= single_set (m_split
);
2444 /* In case we changed the mode of I2DEST, replace it in the
2445 pseudo-register table here. We can't do it above in case this
2446 code doesn't get executed and we do a split the other way. */
2448 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2449 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2451 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2453 /* If I2 or I3 has multiple SETs, we won't know how to track
2454 register status, so don't use these insns. If I2's destination
2455 is used between I2 and I3, we also can't use these insns. */
2457 if (i2_code_number
>= 0 && i2set
&& i3set
2458 && (next_real_insn (i2
) == i3
2459 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2460 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2462 if (insn_code_number
>= 0)
2465 /* It is possible that both insns now set the destination of I3.
2466 If so, we must show an extra use of it. */
2468 if (insn_code_number
>= 0)
2470 rtx new_i3_dest
= SET_DEST (i3set
);
2471 rtx new_i2_dest
= SET_DEST (i2set
);
2473 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2474 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2475 || GET_CODE (new_i3_dest
) == SUBREG
)
2476 new_i3_dest
= XEXP (new_i3_dest
, 0);
2478 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2479 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2480 || GET_CODE (new_i2_dest
) == SUBREG
)
2481 new_i2_dest
= XEXP (new_i2_dest
, 0);
2483 if (REG_P (new_i3_dest
)
2484 && REG_P (new_i2_dest
)
2485 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2486 REG_N_SETS (REGNO (new_i2_dest
))++;
2490 /* If we can split it and use I2DEST, go ahead and see if that
2491 helps things be recognized. Verify that none of the registers
2492 are set between I2 and I3. */
2493 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2497 /* We need I2DEST in the proper mode. If it is a hard register
2498 or the only use of a pseudo, we can change its mode.
2499 Make sure we don't change a hard register to have a mode that
2500 isn't valid for it, or change the number of registers. */
2501 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2502 || GET_MODE (*split
) == VOIDmode
2503 || can_change_dest_mode (i2dest
, added_sets_2
,
2505 && (next_real_insn (i2
) == i3
2506 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2507 /* We can't overwrite I2DEST if its value is still used by
2509 && ! reg_referenced_p (i2dest
, newpat
))
2511 rtx newdest
= i2dest
;
2512 enum rtx_code split_code
= GET_CODE (*split
);
2513 enum machine_mode split_mode
= GET_MODE (*split
);
2515 /* Get NEWDEST as a register in the proper mode. We have already
2516 validated that we can do this. */
2517 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2519 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2521 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2522 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2525 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2526 an ASHIFT. This can occur if it was inside a PLUS and hence
2527 appeared to be a memory address. This is a kludge. */
2528 if (split_code
== MULT
2529 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2530 && INTVAL (XEXP (*split
, 1)) > 0
2531 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2533 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2534 XEXP (*split
, 0), GEN_INT (i
)));
2535 /* Update split_code because we may not have a multiply
2537 split_code
= GET_CODE (*split
);
2540 #ifdef INSN_SCHEDULING
2541 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2542 be written as a ZERO_EXTEND. */
2543 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2545 #ifdef LOAD_EXTEND_OP
2546 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2547 what it really is. */
2548 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2550 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2551 SUBREG_REG (*split
)));
2554 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2555 SUBREG_REG (*split
)));
2559 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2560 SUBST (*split
, newdest
);
2561 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2563 /* recog_for_combine might have added CLOBBERs to newi2pat.
2564 Make sure NEWPAT does not depend on the clobbered regs. */
2565 if (GET_CODE (newi2pat
) == PARALLEL
)
2566 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
2567 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
2569 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
2570 if (reg_overlap_mentioned_p (reg
, newpat
))
2577 /* If the split point was a MULT and we didn't have one before,
2578 don't use one now. */
2579 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2580 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2584 /* Check for a case where we loaded from memory in a narrow mode and
2585 then sign extended it, but we need both registers. In that case,
2586 we have a PARALLEL with both loads from the same memory location.
2587 We can split this into a load from memory followed by a register-register
2588 copy. This saves at least one insn, more if register allocation can
2591 We cannot do this if the destination of the first assignment is a
2592 condition code register or cc0. We eliminate this case by making sure
2593 the SET_DEST and SET_SRC have the same mode.
2595 We cannot do this if the destination of the second assignment is
2596 a register that we have already assumed is zero-extended. Similarly
2597 for a SUBREG of such a register. */
2599 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2600 && GET_CODE (newpat
) == PARALLEL
2601 && XVECLEN (newpat
, 0) == 2
2602 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2603 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2604 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2605 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2606 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2607 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2608 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2609 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2611 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2612 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2613 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2615 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2616 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2617 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2618 && (reg_stat
[REGNO (temp
)].nonzero_bits
2619 != GET_MODE_MASK (word_mode
))))
2620 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2621 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2623 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2624 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2625 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2626 && (reg_stat
[REGNO (temp
)].nonzero_bits
2627 != GET_MODE_MASK (word_mode
)))))
2628 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2629 SET_SRC (XVECEXP (newpat
, 0, 1)))
2630 && ! find_reg_note (i3
, REG_UNUSED
,
2631 SET_DEST (XVECEXP (newpat
, 0, 0))))
2635 newi2pat
= XVECEXP (newpat
, 0, 0);
2636 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2637 newpat
= XVECEXP (newpat
, 0, 1);
2638 SUBST (SET_SRC (newpat
),
2639 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2640 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2642 if (i2_code_number
>= 0)
2643 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2645 if (insn_code_number
>= 0)
2649 /* Similarly, check for a case where we have a PARALLEL of two independent
2650 SETs but we started with three insns. In this case, we can do the sets
2651 as two separate insns. This case occurs when some SET allows two
2652 other insns to combine, but the destination of that SET is still live. */
2654 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2655 && GET_CODE (newpat
) == PARALLEL
2656 && XVECLEN (newpat
, 0) == 2
2657 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2658 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2659 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2660 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2661 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2662 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2663 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2665 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2666 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2667 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2668 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2669 XVECEXP (newpat
, 0, 0))
2670 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2671 XVECEXP (newpat
, 0, 1))
2672 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2673 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2675 /* Normally, it doesn't matter which of the two is done first,
2676 but it does if one references cc0. In that case, it has to
2679 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2681 newi2pat
= XVECEXP (newpat
, 0, 0);
2682 newpat
= XVECEXP (newpat
, 0, 1);
2687 newi2pat
= XVECEXP (newpat
, 0, 1);
2688 newpat
= XVECEXP (newpat
, 0, 0);
2691 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2693 if (i2_code_number
>= 0)
2694 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2697 /* If it still isn't recognized, fail and change things back the way they
2699 if ((insn_code_number
< 0
2700 /* Is the result a reasonable ASM_OPERANDS? */
2701 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2707 /* If we had to change another insn, make sure it is valid also. */
2708 if (undobuf
.other_insn
)
2710 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2711 rtx new_other_notes
;
2714 CLEAR_HARD_REG_SET (newpat_used_regs
);
2716 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2719 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2725 PATTERN (undobuf
.other_insn
) = other_pat
;
2727 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2728 are still valid. Then add any non-duplicate notes added by
2729 recog_for_combine. */
2730 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2732 next
= XEXP (note
, 1);
2734 if (REG_NOTE_KIND (note
) == REG_UNUSED
2735 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2737 if (REG_P (XEXP (note
, 0)))
2738 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2740 remove_note (undobuf
.other_insn
, note
);
2744 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2745 if (REG_P (XEXP (note
, 0)))
2746 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2748 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2749 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2752 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2753 they are adjacent to each other or not. */
2755 rtx p
= prev_nonnote_insn (i3
);
2756 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2757 && sets_cc0_p (newi2pat
))
2765 /* Only allow this combination if insn_rtx_costs reports that the
2766 replacement instructions are cheaper than the originals. */
2767 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
2773 /* We now know that we can do this combination. Merge the insns and
2774 update the status of registers and LOG_LINKS. */
2782 /* I3 now uses what used to be its destination and which is now
2783 I2's destination. This requires us to do a few adjustments. */
2784 PATTERN (i3
) = newpat
;
2785 adjust_for_new_dest (i3
);
2787 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2790 However, some later insn might be using I2's dest and have
2791 a LOG_LINK pointing at I3. We must remove this link.
2792 The simplest way to remove the link is to point it at I1,
2793 which we know will be a NOTE. */
2795 /* newi2pat is usually a SET here; however, recog_for_combine might
2796 have added some clobbers. */
2797 if (GET_CODE (newi2pat
) == PARALLEL
)
2798 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
2800 ni2dest
= SET_DEST (newi2pat
);
2802 for (insn
= NEXT_INSN (i3
);
2803 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2804 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2805 insn
= NEXT_INSN (insn
))
2807 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2809 for (link
= LOG_LINKS (insn
); link
;
2810 link
= XEXP (link
, 1))
2811 if (XEXP (link
, 0) == i3
)
2812 XEXP (link
, 0) = i1
;
2820 rtx i3notes
, i2notes
, i1notes
= 0;
2821 rtx i3links
, i2links
, i1links
= 0;
2824 /* Compute which registers we expect to eliminate. newi2pat may be setting
2825 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2826 same as i3dest, in which case newi2pat may be setting i1dest. */
2827 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2828 || i2dest_in_i2src
|| i2dest_in_i1src
2831 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2832 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2836 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2838 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2839 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2841 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2843 /* Ensure that we do not have something that should not be shared but
2844 occurs multiple times in the new insns. Check this by first
2845 resetting all the `used' flags and then copying anything is shared. */
2847 reset_used_flags (i3notes
);
2848 reset_used_flags (i2notes
);
2849 reset_used_flags (i1notes
);
2850 reset_used_flags (newpat
);
2851 reset_used_flags (newi2pat
);
2852 if (undobuf
.other_insn
)
2853 reset_used_flags (PATTERN (undobuf
.other_insn
));
2855 i3notes
= copy_rtx_if_shared (i3notes
);
2856 i2notes
= copy_rtx_if_shared (i2notes
);
2857 i1notes
= copy_rtx_if_shared (i1notes
);
2858 newpat
= copy_rtx_if_shared (newpat
);
2859 newi2pat
= copy_rtx_if_shared (newi2pat
);
2860 if (undobuf
.other_insn
)
2861 reset_used_flags (PATTERN (undobuf
.other_insn
));
2863 INSN_CODE (i3
) = insn_code_number
;
2864 PATTERN (i3
) = newpat
;
2866 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
2868 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2870 reset_used_flags (call_usage
);
2871 call_usage
= copy_rtx (call_usage
);
2874 replace_rtx (call_usage
, i2dest
, i2src
);
2877 replace_rtx (call_usage
, i1dest
, i1src
);
2879 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2882 if (undobuf
.other_insn
)
2883 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2885 /* We had one special case above where I2 had more than one set and
2886 we replaced a destination of one of those sets with the destination
2887 of I3. In that case, we have to update LOG_LINKS of insns later
2888 in this basic block. Note that this (expensive) case is rare.
2890 Also, in this case, we must pretend that all REG_NOTEs for I2
2891 actually came from I3, so that REG_UNUSED notes from I2 will be
2892 properly handled. */
2894 if (i3_subst_into_i2
)
2896 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2897 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2898 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
2899 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2900 && ! find_reg_note (i2
, REG_UNUSED
,
2901 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2902 for (temp
= NEXT_INSN (i2
);
2903 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2904 || BB_HEAD (this_basic_block
) != temp
);
2905 temp
= NEXT_INSN (temp
))
2906 if (temp
!= i3
&& INSN_P (temp
))
2907 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2908 if (XEXP (link
, 0) == i2
)
2909 XEXP (link
, 0) = i3
;
2914 while (XEXP (link
, 1))
2915 link
= XEXP (link
, 1);
2916 XEXP (link
, 1) = i2notes
;
2930 INSN_CODE (i2
) = i2_code_number
;
2931 PATTERN (i2
) = newi2pat
;
2934 SET_INSN_DELETED (i2
);
2940 SET_INSN_DELETED (i1
);
2943 /* Get death notes for everything that is now used in either I3 or
2944 I2 and used to die in a previous insn. If we built two new
2945 patterns, move from I1 to I2 then I2 to I3 so that we get the
2946 proper movement on registers that I2 modifies. */
2950 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2951 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2954 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2957 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2959 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2962 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2965 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2968 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2971 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2972 know these are REG_UNUSED and want them to go to the desired insn,
2973 so we always pass it as i3. We have not counted the notes in
2974 reg_n_deaths yet, so we need to do so now. */
2976 if (newi2pat
&& new_i2_notes
)
2978 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2979 if (REG_P (XEXP (temp
, 0)))
2980 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2982 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2987 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2988 if (REG_P (XEXP (temp
, 0)))
2989 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2991 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2994 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2995 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2996 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2997 in that case, it might delete I2. Similarly for I2 and I1.
2998 Show an additional death due to the REG_DEAD note we make here. If
2999 we discard it in distribute_notes, we will decrement it again. */
3003 if (REG_P (i3dest_killed
))
3004 REG_N_DEATHS (REGNO (i3dest_killed
))++;
3006 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
3007 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3009 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
3011 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3013 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3017 if (i2dest_in_i2src
)
3020 REG_N_DEATHS (REGNO (i2dest
))++;
3022 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3023 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3024 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3026 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3027 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3028 NULL_RTX
, NULL_RTX
);
3031 if (i1dest_in_i1src
)
3034 REG_N_DEATHS (REGNO (i1dest
))++;
3036 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3037 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3038 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3040 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3041 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3042 NULL_RTX
, NULL_RTX
);
3045 distribute_links (i3links
);
3046 distribute_links (i2links
);
3047 distribute_links (i1links
);
3052 rtx i2_insn
= 0, i2_val
= 0, set
;
3054 /* The insn that used to set this register doesn't exist, and
3055 this life of the register may not exist either. See if one of
3056 I3's links points to an insn that sets I2DEST. If it does,
3057 that is now the last known value for I2DEST. If we don't update
3058 this and I2 set the register to a value that depended on its old
3059 contents, we will get confused. If this insn is used, thing
3060 will be set correctly in combine_instructions. */
3062 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3063 if ((set
= single_set (XEXP (link
, 0))) != 0
3064 && rtx_equal_p (i2dest
, SET_DEST (set
)))
3065 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
3067 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
3069 /* If the reg formerly set in I2 died only once and that was in I3,
3070 zero its use count so it won't make `reload' do any work. */
3072 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
3073 && ! i2dest_in_i2src
)
3075 regno
= REGNO (i2dest
);
3076 REG_N_SETS (regno
)--;
3080 if (i1
&& REG_P (i1dest
))
3083 rtx i1_insn
= 0, i1_val
= 0, set
;
3085 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3086 if ((set
= single_set (XEXP (link
, 0))) != 0
3087 && rtx_equal_p (i1dest
, SET_DEST (set
)))
3088 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
3090 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
3092 regno
= REGNO (i1dest
);
3093 if (! added_sets_1
&& ! i1dest_in_i1src
)
3094 REG_N_SETS (regno
)--;
3097 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3098 been made to this insn. The order of
3099 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3100 can affect nonzero_bits of newpat */
3102 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
3103 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
3105 /* Set new_direct_jump_p if a new return or simple jump instruction
3108 If I3 is now an unconditional jump, ensure that it has a
3109 BARRIER following it since it may have initially been a
3110 conditional jump. It may also be the last nonnote insn. */
3112 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
3114 *new_direct_jump_p
= 1;
3115 mark_jump_label (PATTERN (i3
), i3
, 0);
3117 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
3118 || !BARRIER_P (temp
))
3119 emit_barrier_after (i3
);
3122 if (undobuf
.other_insn
!= NULL_RTX
3123 && (returnjump_p (undobuf
.other_insn
)
3124 || any_uncondjump_p (undobuf
.other_insn
)))
3126 *new_direct_jump_p
= 1;
3128 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
3129 || !BARRIER_P (temp
))
3130 emit_barrier_after (undobuf
.other_insn
);
3133 /* An NOOP jump does not need barrier, but it does need cleaning up
3135 if (GET_CODE (newpat
) == SET
3136 && SET_SRC (newpat
) == pc_rtx
3137 && SET_DEST (newpat
) == pc_rtx
)
3138 *new_direct_jump_p
= 1;
3141 combine_successes
++;
3144 if (added_links_insn
3145 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
3146 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
3147 return added_links_insn
;
3149 return newi2pat
? i2
: i3
;
3152 /* Undo all the modifications recorded in undobuf. */
3157 struct undo
*undo
, *next
;
3159 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3163 *undo
->where
.i
= undo
->old_contents
.i
;
3165 *undo
->where
.r
= undo
->old_contents
.r
;
3167 undo
->next
= undobuf
.frees
;
3168 undobuf
.frees
= undo
;
3174 /* We've committed to accepting the changes we made. Move all
3175 of the undos to the free list. */
3180 struct undo
*undo
, *next
;
3182 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3185 undo
->next
= undobuf
.frees
;
3186 undobuf
.frees
= undo
;
3192 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3193 where we have an arithmetic expression and return that point. LOC will
3196 try_combine will call this function to see if an insn can be split into
3200 find_split_point (rtx
*loc
, rtx insn
)
3203 enum rtx_code code
= GET_CODE (x
);
3205 unsigned HOST_WIDE_INT len
= 0;
3206 HOST_WIDE_INT pos
= 0;
3208 rtx inner
= NULL_RTX
;
3210 /* First special-case some codes. */
3214 #ifdef INSN_SCHEDULING
3215 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3217 if (MEM_P (SUBREG_REG (x
)))
3220 return find_split_point (&SUBREG_REG (x
), insn
);
3224 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3225 using LO_SUM and HIGH. */
3226 if (GET_CODE (XEXP (x
, 0)) == CONST
3227 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3230 gen_rtx_LO_SUM (Pmode
,
3231 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3233 return &XEXP (XEXP (x
, 0), 0);
3237 /* If we have a PLUS whose second operand is a constant and the
3238 address is not valid, perhaps will can split it up using
3239 the machine-specific way to split large constants. We use
3240 the first pseudo-reg (one of the virtual regs) as a placeholder;
3241 it will not remain in the result. */
3242 if (GET_CODE (XEXP (x
, 0)) == PLUS
3243 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3244 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3246 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3247 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3250 /* This should have produced two insns, each of which sets our
3251 placeholder. If the source of the second is a valid address,
3252 we can make put both sources together and make a split point
3256 && NEXT_INSN (seq
) != NULL_RTX
3257 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3258 && NONJUMP_INSN_P (seq
)
3259 && GET_CODE (PATTERN (seq
)) == SET
3260 && SET_DEST (PATTERN (seq
)) == reg
3261 && ! reg_mentioned_p (reg
,
3262 SET_SRC (PATTERN (seq
)))
3263 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3264 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3265 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3266 && memory_address_p (GET_MODE (x
),
3267 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3269 rtx src1
= SET_SRC (PATTERN (seq
));
3270 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3272 /* Replace the placeholder in SRC2 with SRC1. If we can
3273 find where in SRC2 it was placed, that can become our
3274 split point and we can replace this address with SRC2.
3275 Just try two obvious places. */
3277 src2
= replace_rtx (src2
, reg
, src1
);
3279 if (XEXP (src2
, 0) == src1
)
3280 split
= &XEXP (src2
, 0);
3281 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3282 && XEXP (XEXP (src2
, 0), 0) == src1
)
3283 split
= &XEXP (XEXP (src2
, 0), 0);
3287 SUBST (XEXP (x
, 0), src2
);
3292 /* If that didn't work, perhaps the first operand is complex and
3293 needs to be computed separately, so make a split point there.
3294 This will occur on machines that just support REG + CONST
3295 and have a constant moved through some previous computation. */
3297 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3298 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3299 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3300 return &XEXP (XEXP (x
, 0), 0);
3306 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3307 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3308 we need to put the operand into a register. So split at that
3311 if (SET_DEST (x
) == cc0_rtx
3312 && GET_CODE (SET_SRC (x
)) != COMPARE
3313 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3314 && !OBJECT_P (SET_SRC (x
))
3315 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3316 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3317 return &SET_SRC (x
);
3320 /* See if we can split SET_SRC as it stands. */
3321 split
= find_split_point (&SET_SRC (x
), insn
);
3322 if (split
&& split
!= &SET_SRC (x
))
3325 /* See if we can split SET_DEST as it stands. */
3326 split
= find_split_point (&SET_DEST (x
), insn
);
3327 if (split
&& split
!= &SET_DEST (x
))
3330 /* See if this is a bitfield assignment with everything constant. If
3331 so, this is an IOR of an AND, so split it into that. */
3332 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3333 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3334 <= HOST_BITS_PER_WIDE_INT
)
3335 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3336 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3337 && GET_CODE (SET_SRC (x
)) == CONST_INT
3338 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3339 + INTVAL (XEXP (SET_DEST (x
), 2)))
3340 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3341 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3343 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3344 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3345 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3346 rtx dest
= XEXP (SET_DEST (x
), 0);
3347 enum machine_mode mode
= GET_MODE (dest
);
3348 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3350 if (BITS_BIG_ENDIAN
)
3351 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3355 simplify_gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3358 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
3360 simplify_gen_binary (IOR
, mode
,
3361 simplify_gen_binary (AND
, mode
,
3363 GEN_INT (src
<< pos
)));
3366 SUBST (SET_DEST (x
), dest
);
3368 split
= find_split_point (&SET_SRC (x
), insn
);
3369 if (split
&& split
!= &SET_SRC (x
))
3373 /* Otherwise, see if this is an operation that we can split into two.
3374 If so, try to split that. */
3375 code
= GET_CODE (SET_SRC (x
));
3380 /* If we are AND'ing with a large constant that is only a single
3381 bit and the result is only being used in a context where we
3382 need to know if it is zero or nonzero, replace it with a bit
3383 extraction. This will avoid the large constant, which might
3384 have taken more than one insn to make. If the constant were
3385 not a valid argument to the AND but took only one insn to make,
3386 this is no worse, but if it took more than one insn, it will
3389 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3390 && REG_P (XEXP (SET_SRC (x
), 0))
3391 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3392 && REG_P (SET_DEST (x
))
3393 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3394 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3395 && XEXP (*split
, 0) == SET_DEST (x
)
3396 && XEXP (*split
, 1) == const0_rtx
)
3398 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3399 XEXP (SET_SRC (x
), 0),
3400 pos
, NULL_RTX
, 1, 1, 0, 0);
3401 if (extraction
!= 0)
3403 SUBST (SET_SRC (x
), extraction
);
3404 return find_split_point (loc
, insn
);
3410 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3411 is known to be on, this can be converted into a NEG of a shift. */
3412 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3413 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3414 && 1 <= (pos
= exact_log2
3415 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3416 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3418 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3422 gen_rtx_LSHIFTRT (mode
,
3423 XEXP (SET_SRC (x
), 0),
3426 split
= find_split_point (&SET_SRC (x
), insn
);
3427 if (split
&& split
!= &SET_SRC (x
))
3433 inner
= XEXP (SET_SRC (x
), 0);
3435 /* We can't optimize if either mode is a partial integer
3436 mode as we don't know how many bits are significant
3438 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3439 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3443 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3449 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3450 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3452 inner
= XEXP (SET_SRC (x
), 0);
3453 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3454 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3456 if (BITS_BIG_ENDIAN
)
3457 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3458 unsignedp
= (code
== ZERO_EXTRACT
);
3466 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3468 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3470 /* For unsigned, we have a choice of a shift followed by an
3471 AND or two shifts. Use two shifts for field sizes where the
3472 constant might be too large. We assume here that we can
3473 always at least get 8-bit constants in an AND insn, which is
3474 true for every current RISC. */
3476 if (unsignedp
&& len
<= 8)
3481 (mode
, gen_lowpart (mode
, inner
),
3483 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3485 split
= find_split_point (&SET_SRC (x
), insn
);
3486 if (split
&& split
!= &SET_SRC (x
))
3493 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3494 gen_rtx_ASHIFT (mode
,
3495 gen_lowpart (mode
, inner
),
3496 GEN_INT (GET_MODE_BITSIZE (mode
)
3498 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3500 split
= find_split_point (&SET_SRC (x
), insn
);
3501 if (split
&& split
!= &SET_SRC (x
))
3506 /* See if this is a simple operation with a constant as the second
3507 operand. It might be that this constant is out of range and hence
3508 could be used as a split point. */
3509 if (BINARY_P (SET_SRC (x
))
3510 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3511 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3512 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3513 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3514 return &XEXP (SET_SRC (x
), 1);
3516 /* Finally, see if this is a simple operation with its first operand
3517 not in a register. The operation might require this operand in a
3518 register, so return it as a split point. We can always do this
3519 because if the first operand were another operation, we would have
3520 already found it as a split point. */
3521 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3522 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3523 return &XEXP (SET_SRC (x
), 0);
3529 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3530 it is better to write this as (not (ior A B)) so we can split it.
3531 Similarly for IOR. */
3532 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3535 gen_rtx_NOT (GET_MODE (x
),
3536 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3538 XEXP (XEXP (x
, 0), 0),
3539 XEXP (XEXP (x
, 1), 0))));
3540 return find_split_point (loc
, insn
);
3543 /* Many RISC machines have a large set of logical insns. If the
3544 second operand is a NOT, put it first so we will try to split the
3545 other operand first. */
3546 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3548 rtx tem
= XEXP (x
, 0);
3549 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3550 SUBST (XEXP (x
, 1), tem
);
3558 /* Otherwise, select our actions depending on our rtx class. */
3559 switch (GET_RTX_CLASS (code
))
3561 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3563 split
= find_split_point (&XEXP (x
, 2), insn
);
3566 /* ... fall through ... */
3568 case RTX_COMM_ARITH
:
3570 case RTX_COMM_COMPARE
:
3571 split
= find_split_point (&XEXP (x
, 1), insn
);
3574 /* ... fall through ... */
3576 /* Some machines have (and (shift ...) ...) insns. If X is not
3577 an AND, but XEXP (X, 0) is, use it as our split point. */
3578 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3579 return &XEXP (x
, 0);
3581 split
= find_split_point (&XEXP (x
, 0), insn
);
3587 /* Otherwise, we don't have a split point. */
3592 /* Throughout X, replace FROM with TO, and return the result.
3593 The result is TO if X is FROM;
3594 otherwise the result is X, but its contents may have been modified.
3595 If they were modified, a record was made in undobuf so that
3596 undo_all will (among other things) return X to its original state.
3598 If the number of changes necessary is too much to record to undo,
3599 the excess changes are not made, so the result is invalid.
3600 The changes already made can still be undone.
3601 undobuf.num_undo is incremented for such changes, so by testing that
3602 the caller can tell whether the result is valid.
3604 `n_occurrences' is incremented each time FROM is replaced.
3606 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3608 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3609 by copying if `n_occurrences' is nonzero. */
3612 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3614 enum rtx_code code
= GET_CODE (x
);
3615 enum machine_mode op0_mode
= VOIDmode
;
3620 /* Two expressions are equal if they are identical copies of a shared
3621 RTX or if they are both registers with the same register number
3624 #define COMBINE_RTX_EQUAL_P(X,Y) \
3626 || (REG_P (X) && REG_P (Y) \
3627 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3629 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3632 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3635 /* If X and FROM are the same register but different modes, they will
3636 not have been seen as equal above. However, flow.c will make a
3637 LOG_LINKS entry for that case. If we do nothing, we will try to
3638 rerecognize our original insn and, when it succeeds, we will
3639 delete the feeding insn, which is incorrect.
3641 So force this insn not to match in this (rare) case. */
3642 if (! in_dest
&& code
== REG
&& REG_P (from
)
3643 && REGNO (x
) == REGNO (from
))
3644 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3646 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3647 of which may contain things that can be combined. */
3648 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3651 /* It is possible to have a subexpression appear twice in the insn.
3652 Suppose that FROM is a register that appears within TO.
3653 Then, after that subexpression has been scanned once by `subst',
3654 the second time it is scanned, TO may be found. If we were
3655 to scan TO here, we would find FROM within it and create a
3656 self-referent rtl structure which is completely wrong. */
3657 if (COMBINE_RTX_EQUAL_P (x
, to
))
3660 /* Parallel asm_operands need special attention because all of the
3661 inputs are shared across the arms. Furthermore, unsharing the
3662 rtl results in recognition failures. Failure to handle this case
3663 specially can result in circular rtl.
3665 Solve this by doing a normal pass across the first entry of the
3666 parallel, and only processing the SET_DESTs of the subsequent
3669 if (code
== PARALLEL
3670 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3671 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3673 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3675 /* If this substitution failed, this whole thing fails. */
3676 if (GET_CODE (new) == CLOBBER
3677 && XEXP (new, 0) == const0_rtx
)
3680 SUBST (XVECEXP (x
, 0, 0), new);
3682 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3684 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3687 && GET_CODE (dest
) != CC0
3688 && GET_CODE (dest
) != PC
)
3690 new = subst (dest
, from
, to
, 0, unique_copy
);
3692 /* If this substitution failed, this whole thing fails. */
3693 if (GET_CODE (new) == CLOBBER
3694 && XEXP (new, 0) == const0_rtx
)
3697 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3703 len
= GET_RTX_LENGTH (code
);
3704 fmt
= GET_RTX_FORMAT (code
);
3706 /* We don't need to process a SET_DEST that is a register, CC0,
3707 or PC, so set up to skip this common case. All other cases
3708 where we want to suppress replacing something inside a
3709 SET_SRC are handled via the IN_DEST operand. */
3711 && (REG_P (SET_DEST (x
))
3712 || GET_CODE (SET_DEST (x
)) == CC0
3713 || GET_CODE (SET_DEST (x
)) == PC
))
3716 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3719 op0_mode
= GET_MODE (XEXP (x
, 0));
3721 for (i
= 0; i
< len
; i
++)
3726 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3728 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3730 new = (unique_copy
&& n_occurrences
3731 ? copy_rtx (to
) : to
);
3736 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3739 /* If this substitution failed, this whole thing
3741 if (GET_CODE (new) == CLOBBER
3742 && XEXP (new, 0) == const0_rtx
)
3746 SUBST (XVECEXP (x
, i
, j
), new);
3749 else if (fmt
[i
] == 'e')
3751 /* If this is a register being set, ignore it. */
3755 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
3757 || code
== STRICT_LOW_PART
))
3760 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3762 /* In general, don't install a subreg involving two
3763 modes not tieable. It can worsen register
3764 allocation, and can even make invalid reload
3765 insns, since the reg inside may need to be copied
3766 from in the outside mode, and that may be invalid
3767 if it is an fp reg copied in integer mode.
3769 We allow two exceptions to this: It is valid if
3770 it is inside another SUBREG and the mode of that
3771 SUBREG and the mode of the inside of TO is
3772 tieable and it is valid if X is a SET that copies
3775 if (GET_CODE (to
) == SUBREG
3776 && ! MODES_TIEABLE_P (GET_MODE (to
),
3777 GET_MODE (SUBREG_REG (to
)))
3778 && ! (code
== SUBREG
3779 && MODES_TIEABLE_P (GET_MODE (x
),
3780 GET_MODE (SUBREG_REG (to
))))
3782 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3785 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3787 #ifdef CANNOT_CHANGE_MODE_CLASS
3790 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3791 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3794 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3797 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3801 /* If we are in a SET_DEST, suppress most cases unless we
3802 have gone inside a MEM, in which case we want to
3803 simplify the address. We assume here that things that
3804 are actually part of the destination have their inner
3805 parts in the first expression. This is true for SUBREG,
3806 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3807 things aside from REG and MEM that should appear in a
3809 new = subst (XEXP (x
, i
), from
, to
,
3811 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3812 || code
== ZERO_EXTRACT
))
3814 && i
== 0), unique_copy
);
3816 /* If we found that we will have to reject this combination,
3817 indicate that by returning the CLOBBER ourselves, rather than
3818 an expression containing it. This will speed things up as
3819 well as prevent accidents where two CLOBBERs are considered
3820 to be equal, thus producing an incorrect simplification. */
3822 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3825 if (GET_CODE (x
) == SUBREG
3826 && (GET_CODE (new) == CONST_INT
3827 || GET_CODE (new) == CONST_DOUBLE
))
3829 enum machine_mode mode
= GET_MODE (x
);
3831 x
= simplify_subreg (GET_MODE (x
), new,
3832 GET_MODE (SUBREG_REG (x
)),
3835 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3837 else if (GET_CODE (new) == CONST_INT
3838 && GET_CODE (x
) == ZERO_EXTEND
)
3840 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3841 new, GET_MODE (XEXP (x
, 0)));
3845 SUBST (XEXP (x
, i
), new);
3850 /* Try to simplify X. If the simplification changed the code, it is likely
3851 that further simplification will help, so loop, but limit the number
3852 of repetitions that will be performed. */
3854 for (i
= 0; i
< 4; i
++)
3856 /* If X is sufficiently simple, don't bother trying to do anything
3858 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3859 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3861 if (GET_CODE (x
) == code
)
3864 code
= GET_CODE (x
);
3866 /* We no longer know the original mode of operand 0 since we
3867 have changed the form of X) */
3868 op0_mode
= VOIDmode
;
3874 /* Simplify X, a piece of RTL. We just operate on the expression at the
3875 outer level; call `subst' to simplify recursively. Return the new
3878 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3879 if we are inside a SET_DEST. */
3882 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3884 enum rtx_code code
= GET_CODE (x
);
3885 enum machine_mode mode
= GET_MODE (x
);
3890 /* If this is a commutative operation, put a constant last and a complex
3891 expression first. We don't need to do this for comparisons here. */
3892 if (COMMUTATIVE_ARITH_P (x
)
3893 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3896 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3897 SUBST (XEXP (x
, 1), temp
);
3900 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3901 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3902 things. Check for cases where both arms are testing the same
3905 Don't do anything if all operands are very simple. */
3908 && ((!OBJECT_P (XEXP (x
, 0))
3909 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3910 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3911 || (!OBJECT_P (XEXP (x
, 1))
3912 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3913 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3915 && (!OBJECT_P (XEXP (x
, 0))
3916 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3917 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3919 rtx cond
, true_rtx
, false_rtx
;
3921 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3923 /* If everything is a comparison, what we have is highly unlikely
3924 to be simpler, so don't use it. */
3925 && ! (COMPARISON_P (x
)
3926 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3928 rtx cop1
= const0_rtx
;
3929 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3931 if (cond_code
== NE
&& COMPARISON_P (cond
))
3934 /* Simplify the alternative arms; this may collapse the true and
3935 false arms to store-flag values. Be careful to use copy_rtx
3936 here since true_rtx or false_rtx might share RTL with x as a
3937 result of the if_then_else_cond call above. */
3938 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3939 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3941 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3942 is unlikely to be simpler. */
3943 if (general_operand (true_rtx
, VOIDmode
)
3944 && general_operand (false_rtx
, VOIDmode
))
3946 enum rtx_code reversed
;
3948 /* Restarting if we generate a store-flag expression will cause
3949 us to loop. Just drop through in this case. */
3951 /* If the result values are STORE_FLAG_VALUE and zero, we can
3952 just make the comparison operation. */
3953 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3954 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
3956 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3957 && ((reversed
= reversed_comparison_code_parts
3958 (cond_code
, cond
, cop1
, NULL
))
3960 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
3963 /* Likewise, we can make the negate of a comparison operation
3964 if the result values are - STORE_FLAG_VALUE and zero. */
3965 else if (GET_CODE (true_rtx
) == CONST_INT
3966 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3967 && false_rtx
== const0_rtx
)
3968 x
= simplify_gen_unary (NEG
, mode
,
3969 simplify_gen_relational (cond_code
,
3973 else if (GET_CODE (false_rtx
) == CONST_INT
3974 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3975 && true_rtx
== const0_rtx
3976 && ((reversed
= reversed_comparison_code_parts
3977 (cond_code
, cond
, cop1
, NULL
))
3979 x
= simplify_gen_unary (NEG
, mode
,
3980 simplify_gen_relational (reversed
,
3985 return gen_rtx_IF_THEN_ELSE (mode
,
3986 simplify_gen_relational (cond_code
,
3991 true_rtx
, false_rtx
);
3993 code
= GET_CODE (x
);
3994 op0_mode
= VOIDmode
;
3999 /* Try to fold this expression in case we have constants that weren't
4002 switch (GET_RTX_CLASS (code
))
4005 if (op0_mode
== VOIDmode
)
4006 op0_mode
= GET_MODE (XEXP (x
, 0));
4007 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
4010 case RTX_COMM_COMPARE
:
4012 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
4013 if (cmp_mode
== VOIDmode
)
4015 cmp_mode
= GET_MODE (XEXP (x
, 1));
4016 if (cmp_mode
== VOIDmode
)
4017 cmp_mode
= op0_mode
;
4019 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
4020 XEXP (x
, 0), XEXP (x
, 1));
4023 case RTX_COMM_ARITH
:
4025 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4027 case RTX_BITFIELD_OPS
:
4029 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
4030 XEXP (x
, 1), XEXP (x
, 2));
4039 code
= GET_CODE (temp
);
4040 op0_mode
= VOIDmode
;
4041 mode
= GET_MODE (temp
);
4044 /* First see if we can apply the inverse distributive law. */
4045 if (code
== PLUS
|| code
== MINUS
4046 || code
== AND
|| code
== IOR
|| code
== XOR
)
4048 x
= apply_distributive_law (x
);
4049 code
= GET_CODE (x
);
4050 op0_mode
= VOIDmode
;
4053 /* If CODE is an associative operation not otherwise handled, see if we
4054 can associate some operands. This can win if they are constants or
4055 if they are logically related (i.e. (a & b) & a). */
4056 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
4057 || code
== AND
|| code
== IOR
|| code
== XOR
4058 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
4059 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
4060 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
4062 if (GET_CODE (XEXP (x
, 0)) == code
)
4064 rtx other
= XEXP (XEXP (x
, 0), 0);
4065 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
4066 rtx inner_op1
= XEXP (x
, 1);
4069 /* Make sure we pass the constant operand if any as the second
4070 one if this is a commutative operation. */
4071 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
4073 rtx tem
= inner_op0
;
4074 inner_op0
= inner_op1
;
4077 inner
= simplify_binary_operation (code
== MINUS
? PLUS
4078 : code
== DIV
? MULT
4080 mode
, inner_op0
, inner_op1
);
4082 /* For commutative operations, try the other pair if that one
4084 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
4086 other
= XEXP (XEXP (x
, 0), 1);
4087 inner
= simplify_binary_operation (code
, mode
,
4088 XEXP (XEXP (x
, 0), 0),
4093 return simplify_gen_binary (code
, mode
, other
, inner
);
4097 /* A little bit of algebraic simplification here. */
4101 /* Ensure that our address has any ASHIFTs converted to MULT in case
4102 address-recognizing predicates are called later. */
4103 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
4104 SUBST (XEXP (x
, 0), temp
);
4108 if (op0_mode
== VOIDmode
)
4109 op0_mode
= GET_MODE (SUBREG_REG (x
));
4111 /* See if this can be moved to simplify_subreg. */
4112 if (CONSTANT_P (SUBREG_REG (x
))
4113 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
4114 /* Don't call gen_lowpart if the inner mode
4115 is VOIDmode and we cannot simplify it, as SUBREG without
4116 inner mode is invalid. */
4117 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
4118 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
4119 return gen_lowpart (mode
, SUBREG_REG (x
));
4121 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
4125 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4131 /* Don't change the mode of the MEM if that would change the meaning
4133 if (MEM_P (SUBREG_REG (x
))
4134 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4135 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4136 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4138 /* Note that we cannot do any narrowing for non-constants since
4139 we might have been counting on using the fact that some bits were
4140 zero. We now do this in the SET. */
4145 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4146 && subreg_lowpart_p (XEXP (x
, 0))
4147 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
4148 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
4149 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
4150 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
4152 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
4154 x
= gen_rtx_ROTATE (inner_mode
,
4155 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
4157 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
4158 return gen_lowpart (mode
, x
);
4161 /* Apply De Morgan's laws to reduce number of patterns for machines
4162 with negating logical insns (and-not, nand, etc.). If result has
4163 only one NOT, put it first, since that is how the patterns are
4166 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
4168 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4169 enum machine_mode op_mode
;
4171 op_mode
= GET_MODE (in1
);
4172 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4174 op_mode
= GET_MODE (in2
);
4175 if (op_mode
== VOIDmode
)
4177 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4179 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4182 in2
= in1
; in1
= tem
;
4185 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4191 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4192 if (GET_CODE (XEXP (x
, 0)) == XOR
4193 && XEXP (XEXP (x
, 0), 1) == const1_rtx
4194 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4195 return simplify_gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4198 temp
= expand_compound_operation (XEXP (x
, 0));
4200 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4201 replaced by (lshiftrt X C). This will convert
4202 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4204 if (GET_CODE (temp
) == ASHIFTRT
4205 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4206 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4207 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4208 INTVAL (XEXP (temp
, 1)));
4210 /* If X has only a single bit that might be nonzero, say, bit I, convert
4211 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4212 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4213 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4214 or a SUBREG of one since we'd be making the expression more
4215 complex if it was just a register. */
4218 && ! (GET_CODE (temp
) == SUBREG
4219 && REG_P (SUBREG_REG (temp
)))
4220 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4222 rtx temp1
= simplify_shift_const
4223 (NULL_RTX
, ASHIFTRT
, mode
,
4224 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4225 GET_MODE_BITSIZE (mode
) - 1 - i
),
4226 GET_MODE_BITSIZE (mode
) - 1 - i
);
4228 /* If all we did was surround TEMP with the two shifts, we
4229 haven't improved anything, so don't use it. Otherwise,
4230 we are better off with TEMP1. */
4231 if (GET_CODE (temp1
) != ASHIFTRT
4232 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4233 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4239 /* We can't handle truncation to a partial integer mode here
4240 because we don't know the real bitsize of the partial
4242 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4245 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4246 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4247 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4249 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4250 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4252 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4253 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4254 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4255 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4256 return XEXP (XEXP (x
, 0), 0);
4258 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4259 (OP:SI foo:SI) if OP is NEG or ABS. */
4260 if ((GET_CODE (XEXP (x
, 0)) == ABS
4261 || GET_CODE (XEXP (x
, 0)) == NEG
)
4262 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4263 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4264 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4265 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4266 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4268 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4270 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4271 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4272 && subreg_lowpart_p (XEXP (x
, 0)))
4273 return SUBREG_REG (XEXP (x
, 0));
4275 /* If we know that the value is already truncated, we can
4276 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4277 is nonzero for the corresponding modes. But don't do this
4278 for an (LSHIFTRT (MULT ...)) since this will cause problems
4279 with the umulXi3_highpart patterns. */
4280 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4281 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4282 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4283 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4284 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4285 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4286 return gen_lowpart (mode
, XEXP (x
, 0));
4288 /* A truncate of a comparison can be replaced with a subreg if
4289 STORE_FLAG_VALUE permits. This is like the previous test,
4290 but it works even if the comparison is done in a mode larger
4291 than HOST_BITS_PER_WIDE_INT. */
4292 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4293 && COMPARISON_P (XEXP (x
, 0))
4294 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4295 return gen_lowpart (mode
, XEXP (x
, 0));
4297 /* Similarly, a truncate of a register whose value is a
4298 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4300 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4301 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4302 && (temp
= get_last_value (XEXP (x
, 0)))
4303 && COMPARISON_P (temp
))
4304 return gen_lowpart (mode
, XEXP (x
, 0));
4308 case FLOAT_TRUNCATE
:
4309 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4310 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4311 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4312 return XEXP (XEXP (x
, 0), 0);
4314 /* (float_truncate:SF (float_truncate:DF foo:XF))
4315 = (float_truncate:SF foo:XF).
4316 This may eliminate double rounding, so it is unsafe.
4318 (float_truncate:SF (float_extend:XF foo:DF))
4319 = (float_truncate:SF foo:DF).
4321 (float_truncate:DF (float_extend:XF foo:SF))
4322 = (float_extend:SF foo:DF). */
4323 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4324 && flag_unsafe_math_optimizations
)
4325 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4326 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4328 > GET_MODE_SIZE (mode
)
4329 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4331 XEXP (XEXP (x
, 0), 0), mode
);
4333 /* (float_truncate (float x)) is (float x) */
4334 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4335 && (flag_unsafe_math_optimizations
4336 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4337 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4338 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4339 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4340 return simplify_gen_unary (FLOAT
, mode
,
4341 XEXP (XEXP (x
, 0), 0),
4342 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4344 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4345 (OP:SF foo:SF) if OP is NEG or ABS. */
4346 if ((GET_CODE (XEXP (x
, 0)) == ABS
4347 || GET_CODE (XEXP (x
, 0)) == NEG
)
4348 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4349 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4350 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4351 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4353 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4354 is (float_truncate:SF x). */
4355 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4356 && subreg_lowpart_p (XEXP (x
, 0))
4357 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4358 return SUBREG_REG (XEXP (x
, 0));
4361 /* (float_extend (float_extend x)) is (float_extend x)
4363 (float_extend (float x)) is (float x) assuming that double
4364 rounding can't happen.
4366 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4367 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4368 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4369 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4370 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4371 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4372 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4373 XEXP (XEXP (x
, 0), 0),
4374 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4379 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4380 using cc0, in which case we want to leave it as a COMPARE
4381 so we can distinguish it from a register-register-copy. */
4382 if (XEXP (x
, 1) == const0_rtx
)
4385 /* x - 0 is the same as x unless x's mode has signed zeros and
4386 allows rounding towards -infinity. Under those conditions,
4388 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4389 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4390 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4396 /* (const (const X)) can become (const X). Do it this way rather than
4397 returning the inner CONST since CONST can be shared with a
4399 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4400 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4405 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4406 can add in an offset. find_split_point will split this address up
4407 again if it doesn't match. */
4408 if (GET_CODE (XEXP (x
, 0)) == HIGH
4409 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4415 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4417 if (GET_CODE (XEXP (x
, 0)) == MULT
4418 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4422 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4423 in2
= XEXP (XEXP (x
, 0), 1);
4424 return simplify_gen_binary (MINUS
, mode
, XEXP (x
, 1),
4425 simplify_gen_binary (MULT
, mode
,
4429 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4430 outermost. That's because that's the way indexed addresses are
4431 supposed to appear. This code used to check many more cases, but
4432 they are now checked elsewhere. */
4433 if (GET_CODE (XEXP (x
, 0)) == PLUS
4434 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4435 return simplify_gen_binary (PLUS
, mode
,
4436 simplify_gen_binary (PLUS
, mode
,
4437 XEXP (XEXP (x
, 0), 0),
4439 XEXP (XEXP (x
, 0), 1));
4441 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4442 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4443 bit-field and can be replaced by either a sign_extend or a
4444 sign_extract. The `and' may be a zero_extend and the two
4445 <c>, -<c> constants may be reversed. */
4446 if (GET_CODE (XEXP (x
, 0)) == XOR
4447 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4448 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4449 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4450 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4451 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4452 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4453 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4454 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4455 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4456 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4457 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4458 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4459 == (unsigned int) i
+ 1))))
4460 return simplify_shift_const
4461 (NULL_RTX
, ASHIFTRT
, mode
,
4462 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4463 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4464 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4465 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4467 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4468 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4469 is 1. This produces better code than the alternative immediately
4471 if (COMPARISON_P (XEXP (x
, 0))
4472 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4473 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4474 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
)))
4476 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4478 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4479 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4480 the bitsize of the mode - 1. This allows simplification of
4481 "a = (b & 8) == 0;" */
4482 if (XEXP (x
, 1) == constm1_rtx
4483 && !REG_P (XEXP (x
, 0))
4484 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4485 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4486 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4487 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4488 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4489 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4490 GET_MODE_BITSIZE (mode
) - 1),
4491 GET_MODE_BITSIZE (mode
) - 1);
4493 /* If we are adding two things that have no bits in common, convert
4494 the addition into an IOR. This will often be further simplified,
4495 for example in cases like ((a & 1) + (a & 2)), which can
4498 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4499 && (nonzero_bits (XEXP (x
, 0), mode
)
4500 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4502 /* Try to simplify the expression further. */
4503 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4504 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4506 /* If we could, great. If not, do not go ahead with the IOR
4507 replacement, since PLUS appears in many special purpose
4508 address arithmetic instructions. */
4509 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4515 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4516 by reversing the comparison code if valid. */
4517 if (STORE_FLAG_VALUE
== 1
4518 && XEXP (x
, 0) == const1_rtx
4519 && COMPARISON_P (XEXP (x
, 1))
4520 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
)))
4523 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4524 (and <foo> (const_int pow2-1)) */
4525 if (GET_CODE (XEXP (x
, 1)) == AND
4526 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4527 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4528 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4529 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4530 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4532 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4534 if (GET_CODE (XEXP (x
, 1)) == MULT
4535 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4539 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4540 in2
= XEXP (XEXP (x
, 1), 1);
4541 return simplify_gen_binary (PLUS
, mode
,
4542 simplify_gen_binary (MULT
, mode
,
4547 /* Canonicalize (minus (neg A) (mult B C)) to
4548 (minus (mult (neg B) C) A). */
4549 if (GET_CODE (XEXP (x
, 1)) == MULT
4550 && GET_CODE (XEXP (x
, 0)) == NEG
)
4554 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4555 in2
= XEXP (XEXP (x
, 1), 1);
4556 return simplify_gen_binary (MINUS
, mode
,
4557 simplify_gen_binary (MULT
, mode
,
4559 XEXP (XEXP (x
, 0), 0));
4562 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4564 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4565 return simplify_gen_binary (MINUS
, mode
,
4566 simplify_gen_binary (MINUS
, mode
,
4568 XEXP (XEXP (x
, 1), 0)),
4569 XEXP (XEXP (x
, 1), 1));
4573 /* If we have (mult (plus A B) C), apply the distributive law and then
4574 the inverse distributive law to see if things simplify. This
4575 occurs mostly in addresses, often when unrolling loops. */
4577 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4579 rtx result
= distribute_and_simplify_rtx (x
, 0);
4584 /* Try simplify a*(b/c) as (a*b)/c. */
4585 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4586 && GET_CODE (XEXP (x
, 0)) == DIV
)
4588 rtx tem
= simplify_binary_operation (MULT
, mode
,
4589 XEXP (XEXP (x
, 0), 0),
4592 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4597 /* If this is a divide by a power of two, treat it as a shift if
4598 its first operand is a shift. */
4599 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4600 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4601 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4602 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4603 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4604 || GET_CODE (XEXP (x
, 0)) == ROTATE
4605 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4606 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4610 case GT
: case GTU
: case GE
: case GEU
:
4611 case LT
: case LTU
: case LE
: case LEU
:
4612 case UNEQ
: case LTGT
:
4613 case UNGT
: case UNGE
:
4614 case UNLT
: case UNLE
:
4615 case UNORDERED
: case ORDERED
:
4616 /* If the first operand is a condition code, we can't do anything
4618 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4619 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4620 && ! CC0_P (XEXP (x
, 0))))
4622 rtx op0
= XEXP (x
, 0);
4623 rtx op1
= XEXP (x
, 1);
4624 enum rtx_code new_code
;
4626 if (GET_CODE (op0
) == COMPARE
)
4627 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4629 /* Simplify our comparison, if possible. */
4630 new_code
= simplify_comparison (code
, &op0
, &op1
);
4632 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4633 if only the low-order bit is possibly nonzero in X (such as when
4634 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4635 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4636 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4639 Remove any ZERO_EXTRACT we made when thinking this was a
4640 comparison. It may now be simpler to use, e.g., an AND. If a
4641 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4642 the call to make_compound_operation in the SET case. */
4644 if (STORE_FLAG_VALUE
== 1
4645 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4646 && op1
== const0_rtx
4647 && mode
== GET_MODE (op0
)
4648 && nonzero_bits (op0
, mode
) == 1)
4649 return gen_lowpart (mode
,
4650 expand_compound_operation (op0
));
4652 else if (STORE_FLAG_VALUE
== 1
4653 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4654 && op1
== const0_rtx
4655 && mode
== GET_MODE (op0
)
4656 && (num_sign_bit_copies (op0
, mode
)
4657 == GET_MODE_BITSIZE (mode
)))
4659 op0
= expand_compound_operation (op0
);
4660 return simplify_gen_unary (NEG
, mode
,
4661 gen_lowpart (mode
, op0
),
4665 else if (STORE_FLAG_VALUE
== 1
4666 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4667 && op1
== const0_rtx
4668 && mode
== GET_MODE (op0
)
4669 && nonzero_bits (op0
, mode
) == 1)
4671 op0
= expand_compound_operation (op0
);
4672 return simplify_gen_binary (XOR
, mode
,
4673 gen_lowpart (mode
, op0
),
4677 else if (STORE_FLAG_VALUE
== 1
4678 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4679 && op1
== const0_rtx
4680 && mode
== GET_MODE (op0
)
4681 && (num_sign_bit_copies (op0
, mode
)
4682 == GET_MODE_BITSIZE (mode
)))
4684 op0
= expand_compound_operation (op0
);
4685 return plus_constant (gen_lowpart (mode
, op0
), 1);
4688 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4690 if (STORE_FLAG_VALUE
== -1
4691 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4692 && op1
== const0_rtx
4693 && (num_sign_bit_copies (op0
, mode
)
4694 == GET_MODE_BITSIZE (mode
)))
4695 return gen_lowpart (mode
,
4696 expand_compound_operation (op0
));
4698 else if (STORE_FLAG_VALUE
== -1
4699 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4700 && op1
== const0_rtx
4701 && mode
== GET_MODE (op0
)
4702 && nonzero_bits (op0
, mode
) == 1)
4704 op0
= expand_compound_operation (op0
);
4705 return simplify_gen_unary (NEG
, mode
,
4706 gen_lowpart (mode
, op0
),
4710 else if (STORE_FLAG_VALUE
== -1
4711 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4712 && op1
== const0_rtx
4713 && mode
== GET_MODE (op0
)
4714 && (num_sign_bit_copies (op0
, mode
)
4715 == GET_MODE_BITSIZE (mode
)))
4717 op0
= expand_compound_operation (op0
);
4718 return simplify_gen_unary (NOT
, mode
,
4719 gen_lowpart (mode
, op0
),
4723 /* If X is 0/1, (eq X 0) is X-1. */
4724 else if (STORE_FLAG_VALUE
== -1
4725 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4726 && op1
== const0_rtx
4727 && mode
== GET_MODE (op0
)
4728 && nonzero_bits (op0
, mode
) == 1)
4730 op0
= expand_compound_operation (op0
);
4731 return plus_constant (gen_lowpart (mode
, op0
), -1);
4734 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4735 one bit that might be nonzero, we can convert (ne x 0) to
4736 (ashift x c) where C puts the bit in the sign bit. Remove any
4737 AND with STORE_FLAG_VALUE when we are done, since we are only
4738 going to test the sign bit. */
4739 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4740 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4741 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4742 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4743 && op1
== const0_rtx
4744 && mode
== GET_MODE (op0
)
4745 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4747 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4748 expand_compound_operation (op0
),
4749 GET_MODE_BITSIZE (mode
) - 1 - i
);
4750 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4756 /* If the code changed, return a whole new comparison. */
4757 if (new_code
!= code
)
4758 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4760 /* Otherwise, keep this operation, but maybe change its operands.
4761 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4762 SUBST (XEXP (x
, 0), op0
);
4763 SUBST (XEXP (x
, 1), op1
);
4768 return simplify_if_then_else (x
);
4774 /* If we are processing SET_DEST, we are done. */
4778 return expand_compound_operation (x
);
4781 return simplify_set (x
);
4786 return simplify_logical (x
);
4789 /* (abs (neg <foo>)) -> (abs <foo>) */
4790 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4791 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4793 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4795 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4798 /* If operand is something known to be positive, ignore the ABS. */
4799 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4800 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4801 <= HOST_BITS_PER_WIDE_INT
)
4802 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4803 & ((HOST_WIDE_INT
) 1
4804 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4808 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4809 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4810 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4815 /* (ffs (*_extend <X>)) = (ffs <X>) */
4816 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4817 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4818 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4823 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4824 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4825 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4829 /* (float (sign_extend <X>)) = (float <X>). */
4830 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4831 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4839 /* If this is a shift by a constant amount, simplify it. */
4840 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4841 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4842 INTVAL (XEXP (x
, 1)));
4844 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4846 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4848 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4855 rtx op0
= XEXP (x
, 0);
4856 rtx op1
= XEXP (x
, 1);
4859 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4860 len
= XVECLEN (op1
, 0);
4862 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4863 && GET_CODE (op0
) == VEC_CONCAT
)
4865 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4867 /* Try to find the element in the VEC_CONCAT. */
4870 if (GET_MODE (op0
) == GET_MODE (x
))
4872 if (GET_CODE (op0
) == VEC_CONCAT
)
4874 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4875 if (offset
< op0_size
)
4876 op0
= XEXP (op0
, 0);
4880 op0
= XEXP (op0
, 1);
4898 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4901 simplify_if_then_else (rtx x
)
4903 enum machine_mode mode
= GET_MODE (x
);
4904 rtx cond
= XEXP (x
, 0);
4905 rtx true_rtx
= XEXP (x
, 1);
4906 rtx false_rtx
= XEXP (x
, 2);
4907 enum rtx_code true_code
= GET_CODE (cond
);
4908 int comparison_p
= COMPARISON_P (cond
);
4911 enum rtx_code false_code
;
4914 /* Simplify storing of the truth value. */
4915 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4916 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
4917 XEXP (cond
, 0), XEXP (cond
, 1));
4919 /* Also when the truth value has to be reversed. */
4921 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4922 && (reversed
= reversed_comparison (cond
, mode
)))
4925 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4926 in it is being compared against certain values. Get the true and false
4927 comparisons and see if that says anything about the value of each arm. */
4930 && ((false_code
= reversed_comparison_code (cond
, NULL
))
4932 && REG_P (XEXP (cond
, 0)))
4935 rtx from
= XEXP (cond
, 0);
4936 rtx true_val
= XEXP (cond
, 1);
4937 rtx false_val
= true_val
;
4940 /* If FALSE_CODE is EQ, swap the codes and arms. */
4942 if (false_code
== EQ
)
4944 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4945 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4948 /* If we are comparing against zero and the expression being tested has
4949 only a single bit that might be nonzero, that is its value when it is
4950 not equal to zero. Similarly if it is known to be -1 or 0. */
4952 if (true_code
== EQ
&& true_val
== const0_rtx
4953 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4954 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4955 else if (true_code
== EQ
&& true_val
== const0_rtx
4956 && (num_sign_bit_copies (from
, GET_MODE (from
))
4957 == GET_MODE_BITSIZE (GET_MODE (from
))))
4958 false_code
= EQ
, false_val
= constm1_rtx
;
4960 /* Now simplify an arm if we know the value of the register in the
4961 branch and it is used in the arm. Be careful due to the potential
4962 of locally-shared RTL. */
4964 if (reg_mentioned_p (from
, true_rtx
))
4965 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4967 pc_rtx
, pc_rtx
, 0, 0);
4968 if (reg_mentioned_p (from
, false_rtx
))
4969 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4971 pc_rtx
, pc_rtx
, 0, 0);
4973 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4974 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4976 true_rtx
= XEXP (x
, 1);
4977 false_rtx
= XEXP (x
, 2);
4978 true_code
= GET_CODE (cond
);
4981 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4982 reversed, do so to avoid needing two sets of patterns for
4983 subtract-and-branch insns. Similarly if we have a constant in the true
4984 arm, the false arm is the same as the first operand of the comparison, or
4985 the false arm is more complicated than the true arm. */
4988 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
4989 && (true_rtx
== pc_rtx
4990 || (CONSTANT_P (true_rtx
)
4991 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4992 || true_rtx
== const0_rtx
4993 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4994 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4995 && !OBJECT_P (false_rtx
))
4996 || reg_mentioned_p (true_rtx
, false_rtx
)
4997 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4999 true_code
= reversed_comparison_code (cond
, NULL
);
5000 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5001 SUBST (XEXP (x
, 1), false_rtx
);
5002 SUBST (XEXP (x
, 2), true_rtx
);
5004 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5007 /* It is possible that the conditional has been simplified out. */
5008 true_code
= GET_CODE (cond
);
5009 comparison_p
= COMPARISON_P (cond
);
5012 /* If the two arms are identical, we don't need the comparison. */
5014 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5017 /* Convert a == b ? b : a to "a". */
5018 if (true_code
== EQ
&& ! side_effects_p (cond
)
5019 && !HONOR_NANS (mode
)
5020 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5021 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5023 else if (true_code
== NE
&& ! side_effects_p (cond
)
5024 && !HONOR_NANS (mode
)
5025 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5026 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5029 /* Look for cases where we have (abs x) or (neg (abs X)). */
5031 if (GET_MODE_CLASS (mode
) == MODE_INT
5032 && GET_CODE (false_rtx
) == NEG
5033 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5035 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5036 && ! side_effects_p (true_rtx
))
5041 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5045 simplify_gen_unary (NEG
, mode
,
5046 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5052 /* Look for MIN or MAX. */
5054 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5056 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5057 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5058 && ! side_effects_p (cond
))
5063 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5066 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
5069 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
5072 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
5077 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5078 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5079 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5080 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5081 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5082 neither 1 or -1, but it isn't worth checking for. */
5084 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5086 && GET_MODE_CLASS (mode
) == MODE_INT
5087 && ! side_effects_p (x
))
5089 rtx t
= make_compound_operation (true_rtx
, SET
);
5090 rtx f
= make_compound_operation (false_rtx
, SET
);
5091 rtx cond_op0
= XEXP (cond
, 0);
5092 rtx cond_op1
= XEXP (cond
, 1);
5093 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
5094 enum machine_mode m
= mode
;
5095 rtx z
= 0, c1
= NULL_RTX
;
5097 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
5098 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
5099 || GET_CODE (t
) == ASHIFT
5100 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
5101 && rtx_equal_p (XEXP (t
, 0), f
))
5102 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
5104 /* If an identity-zero op is commutative, check whether there
5105 would be a match if we swapped the operands. */
5106 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
5107 || GET_CODE (t
) == XOR
)
5108 && rtx_equal_p (XEXP (t
, 1), f
))
5109 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
5110 else if (GET_CODE (t
) == SIGN_EXTEND
5111 && (GET_CODE (XEXP (t
, 0)) == PLUS
5112 || GET_CODE (XEXP (t
, 0)) == MINUS
5113 || GET_CODE (XEXP (t
, 0)) == IOR
5114 || GET_CODE (XEXP (t
, 0)) == XOR
5115 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5116 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5117 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5118 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5119 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5120 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5121 && (num_sign_bit_copies (f
, GET_MODE (f
))
5123 (GET_MODE_BITSIZE (mode
)
5124 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5126 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5127 extend_op
= SIGN_EXTEND
;
5128 m
= GET_MODE (XEXP (t
, 0));
5130 else if (GET_CODE (t
) == SIGN_EXTEND
5131 && (GET_CODE (XEXP (t
, 0)) == PLUS
5132 || GET_CODE (XEXP (t
, 0)) == IOR
5133 || GET_CODE (XEXP (t
, 0)) == XOR
)
5134 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5135 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5136 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5137 && (num_sign_bit_copies (f
, GET_MODE (f
))
5139 (GET_MODE_BITSIZE (mode
)
5140 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5142 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5143 extend_op
= SIGN_EXTEND
;
5144 m
= GET_MODE (XEXP (t
, 0));
5146 else if (GET_CODE (t
) == ZERO_EXTEND
5147 && (GET_CODE (XEXP (t
, 0)) == PLUS
5148 || GET_CODE (XEXP (t
, 0)) == MINUS
5149 || GET_CODE (XEXP (t
, 0)) == IOR
5150 || GET_CODE (XEXP (t
, 0)) == XOR
5151 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5152 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5153 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5154 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5155 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5156 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5157 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5158 && ((nonzero_bits (f
, GET_MODE (f
))
5159 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5162 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5163 extend_op
= ZERO_EXTEND
;
5164 m
= GET_MODE (XEXP (t
, 0));
5166 else if (GET_CODE (t
) == ZERO_EXTEND
5167 && (GET_CODE (XEXP (t
, 0)) == PLUS
5168 || GET_CODE (XEXP (t
, 0)) == IOR
5169 || GET_CODE (XEXP (t
, 0)) == XOR
)
5170 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5171 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5172 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5173 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5174 && ((nonzero_bits (f
, GET_MODE (f
))
5175 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5178 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5179 extend_op
= ZERO_EXTEND
;
5180 m
= GET_MODE (XEXP (t
, 0));
5185 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5186 cond_op0
, cond_op1
),
5187 pc_rtx
, pc_rtx
, 0, 0);
5188 temp
= simplify_gen_binary (MULT
, m
, temp
,
5189 simplify_gen_binary (MULT
, m
, c1
,
5191 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5192 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5194 if (extend_op
!= UNKNOWN
)
5195 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5201 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5202 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5203 negation of a single bit, we can convert this operation to a shift. We
5204 can actually do this more generally, but it doesn't seem worth it. */
5206 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5207 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5208 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5209 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5210 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5211 == GET_MODE_BITSIZE (mode
))
5212 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5214 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5215 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5217 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5218 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5219 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5220 && GET_MODE (XEXP (cond
, 0)) == mode
5221 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5222 == nonzero_bits (XEXP (cond
, 0), mode
)
5223 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5224 return XEXP (cond
, 0);
5229 /* Simplify X, a SET expression. Return the new expression. */
5232 simplify_set (rtx x
)
5234 rtx src
= SET_SRC (x
);
5235 rtx dest
= SET_DEST (x
);
5236 enum machine_mode mode
5237 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5241 /* (set (pc) (return)) gets written as (return). */
5242 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5245 /* Now that we know for sure which bits of SRC we are using, see if we can
5246 simplify the expression for the object knowing that we only need the
5249 if (GET_MODE_CLASS (mode
) == MODE_INT
5250 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5252 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5253 SUBST (SET_SRC (x
), src
);
5256 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5257 the comparison result and try to simplify it unless we already have used
5258 undobuf.other_insn. */
5259 if ((GET_MODE_CLASS (mode
) == MODE_CC
5260 || GET_CODE (src
) == COMPARE
5262 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5263 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5264 && COMPARISON_P (*cc_use
)
5265 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5267 enum rtx_code old_code
= GET_CODE (*cc_use
);
5268 enum rtx_code new_code
;
5270 int other_changed
= 0;
5271 enum machine_mode compare_mode
= GET_MODE (dest
);
5273 if (GET_CODE (src
) == COMPARE
)
5274 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5276 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5278 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5281 new_code
= old_code
;
5282 else if (!CONSTANT_P (tmp
))
5284 new_code
= GET_CODE (tmp
);
5285 op0
= XEXP (tmp
, 0);
5286 op1
= XEXP (tmp
, 1);
5290 rtx pat
= PATTERN (other_insn
);
5291 undobuf
.other_insn
= other_insn
;
5292 SUBST (*cc_use
, tmp
);
5294 /* Attempt to simplify CC user. */
5295 if (GET_CODE (pat
) == SET
)
5297 rtx
new = simplify_rtx (SET_SRC (pat
));
5298 if (new != NULL_RTX
)
5299 SUBST (SET_SRC (pat
), new);
5302 /* Convert X into a no-op move. */
5303 SUBST (SET_DEST (x
), pc_rtx
);
5304 SUBST (SET_SRC (x
), pc_rtx
);
5308 /* Simplify our comparison, if possible. */
5309 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5311 #ifdef SELECT_CC_MODE
5312 /* If this machine has CC modes other than CCmode, check to see if we
5313 need to use a different CC mode here. */
5314 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5315 compare_mode
= GET_MODE (op0
);
5317 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5320 /* If the mode changed, we have to change SET_DEST, the mode in the
5321 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5322 a hard register, just build new versions with the proper mode. If it
5323 is a pseudo, we lose unless it is only time we set the pseudo, in
5324 which case we can safely change its mode. */
5325 if (compare_mode
!= GET_MODE (dest
))
5327 if (can_change_dest_mode (dest
, 0, compare_mode
))
5329 unsigned int regno
= REGNO (dest
);
5330 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5332 if (regno
>= FIRST_PSEUDO_REGISTER
)
5333 SUBST (regno_reg_rtx
[regno
], new_dest
);
5335 SUBST (SET_DEST (x
), new_dest
);
5336 SUBST (XEXP (*cc_use
, 0), new_dest
);
5343 #endif /* SELECT_CC_MODE */
5345 /* If the code changed, we have to build a new comparison in
5346 undobuf.other_insn. */
5347 if (new_code
!= old_code
)
5349 int other_changed_previously
= other_changed
;
5350 unsigned HOST_WIDE_INT mask
;
5352 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5356 /* If the only change we made was to change an EQ into an NE or
5357 vice versa, OP0 has only one bit that might be nonzero, and OP1
5358 is zero, check if changing the user of the condition code will
5359 produce a valid insn. If it won't, we can keep the original code
5360 in that insn by surrounding our operation with an XOR. */
5362 if (((old_code
== NE
&& new_code
== EQ
)
5363 || (old_code
== EQ
&& new_code
== NE
))
5364 && ! other_changed_previously
&& op1
== const0_rtx
5365 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5366 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5368 rtx pat
= PATTERN (other_insn
), note
= 0;
5370 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5371 && ! check_asm_operands (pat
)))
5373 PUT_CODE (*cc_use
, old_code
);
5376 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5377 op0
, GEN_INT (mask
));
5383 undobuf
.other_insn
= other_insn
;
5386 /* If we are now comparing against zero, change our source if
5387 needed. If we do not use cc0, we always have a COMPARE. */
5388 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5390 SUBST (SET_SRC (x
), op0
);
5396 /* Otherwise, if we didn't previously have a COMPARE in the
5397 correct mode, we need one. */
5398 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5400 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5403 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
5405 SUBST(SET_SRC (x
), op0
);
5410 /* Otherwise, update the COMPARE if needed. */
5411 SUBST (XEXP (src
, 0), op0
);
5412 SUBST (XEXP (src
, 1), op1
);
5417 /* Get SET_SRC in a form where we have placed back any
5418 compound expressions. Then do the checks below. */
5419 src
= make_compound_operation (src
, SET
);
5420 SUBST (SET_SRC (x
), src
);
5423 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5424 and X being a REG or (subreg (reg)), we may be able to convert this to
5425 (set (subreg:m2 x) (op)).
5427 We can always do this if M1 is narrower than M2 because that means that
5428 we only care about the low bits of the result.
5430 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5431 perform a narrower operation than requested since the high-order bits will
5432 be undefined. On machine where it is defined, this transformation is safe
5433 as long as M1 and M2 have the same number of words. */
5435 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5436 && !OBJECT_P (SUBREG_REG (src
))
5437 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5439 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5440 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5441 #ifndef WORD_REGISTER_OPERATIONS
5442 && (GET_MODE_SIZE (GET_MODE (src
))
5443 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5445 #ifdef CANNOT_CHANGE_MODE_CLASS
5446 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5447 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5448 GET_MODE (SUBREG_REG (src
)),
5452 || (GET_CODE (dest
) == SUBREG
5453 && REG_P (SUBREG_REG (dest
)))))
5455 SUBST (SET_DEST (x
),
5456 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5458 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5460 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5464 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5467 && GET_CODE (src
) == SUBREG
5468 && subreg_lowpart_p (src
)
5469 && (GET_MODE_BITSIZE (GET_MODE (src
))
5470 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5472 rtx inner
= SUBREG_REG (src
);
5473 enum machine_mode inner_mode
= GET_MODE (inner
);
5475 /* Here we make sure that we don't have a sign bit on. */
5476 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5477 && (nonzero_bits (inner
, inner_mode
)
5478 < ((unsigned HOST_WIDE_INT
) 1
5479 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5481 SUBST (SET_SRC (x
), inner
);
5487 #ifdef LOAD_EXTEND_OP
5488 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5489 would require a paradoxical subreg. Replace the subreg with a
5490 zero_extend to avoid the reload that would otherwise be required. */
5492 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5493 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5494 && SUBREG_BYTE (src
) == 0
5495 && (GET_MODE_SIZE (GET_MODE (src
))
5496 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5497 && MEM_P (SUBREG_REG (src
)))
5500 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5501 GET_MODE (src
), SUBREG_REG (src
)));
5507 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5508 are comparing an item known to be 0 or -1 against 0, use a logical
5509 operation instead. Check for one of the arms being an IOR of the other
5510 arm with some value. We compute three terms to be IOR'ed together. In
5511 practice, at most two will be nonzero. Then we do the IOR's. */
5513 if (GET_CODE (dest
) != PC
5514 && GET_CODE (src
) == IF_THEN_ELSE
5515 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5516 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5517 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5518 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5519 #ifdef HAVE_conditional_move
5520 && ! can_conditionally_move_p (GET_MODE (src
))
5522 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5523 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5524 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5525 && ! side_effects_p (src
))
5527 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5528 ? XEXP (src
, 1) : XEXP (src
, 2));
5529 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5530 ? XEXP (src
, 2) : XEXP (src
, 1));
5531 rtx term1
= const0_rtx
, term2
, term3
;
5533 if (GET_CODE (true_rtx
) == IOR
5534 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5535 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5536 else if (GET_CODE (true_rtx
) == IOR
5537 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5538 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5539 else if (GET_CODE (false_rtx
) == IOR
5540 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5541 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5542 else if (GET_CODE (false_rtx
) == IOR
5543 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5544 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5546 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5547 XEXP (XEXP (src
, 0), 0), true_rtx
);
5548 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5549 simplify_gen_unary (NOT
, GET_MODE (src
),
5550 XEXP (XEXP (src
, 0), 0),
5555 simplify_gen_binary (IOR
, GET_MODE (src
),
5556 simplify_gen_binary (IOR
, GET_MODE (src
),
5563 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5564 whole thing fail. */
5565 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5567 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5570 /* Convert this into a field assignment operation, if possible. */
5571 return make_field_assignment (x
);
5574 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5578 simplify_logical (rtx x
)
5580 enum machine_mode mode
= GET_MODE (x
);
5581 rtx op0
= XEXP (x
, 0);
5582 rtx op1
= XEXP (x
, 1);
5585 switch (GET_CODE (x
))
5588 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5589 insn (and may simplify more). */
5590 if (GET_CODE (op0
) == XOR
5591 && rtx_equal_p (XEXP (op0
, 0), op1
)
5592 && ! side_effects_p (op1
))
5593 x
= simplify_gen_binary (AND
, mode
,
5594 simplify_gen_unary (NOT
, mode
,
5595 XEXP (op0
, 1), mode
),
5598 if (GET_CODE (op0
) == XOR
5599 && rtx_equal_p (XEXP (op0
, 1), op1
)
5600 && ! side_effects_p (op1
))
5601 x
= simplify_gen_binary (AND
, mode
,
5602 simplify_gen_unary (NOT
, mode
,
5603 XEXP (op0
, 0), mode
),
5606 /* Similarly for (~(A ^ B)) & A. */
5607 if (GET_CODE (op0
) == NOT
5608 && GET_CODE (XEXP (op0
, 0)) == XOR
5609 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5610 && ! side_effects_p (op1
))
5611 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5613 if (GET_CODE (op0
) == NOT
5614 && GET_CODE (XEXP (op0
, 0)) == XOR
5615 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5616 && ! side_effects_p (op1
))
5617 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5619 /* We can call simplify_and_const_int only if we don't lose
5620 any (sign) bits when converting INTVAL (op1) to
5621 "unsigned HOST_WIDE_INT". */
5622 if (GET_CODE (op1
) == CONST_INT
5623 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5624 || INTVAL (op1
) > 0))
5626 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5628 /* If we have (ior (and (X C1) C2)) and the next restart would be
5629 the last, simplify this by making C1 as small as possible
5630 and then exit. Only do this if C1 actually changes: for now
5631 this only saves memory but, should this transformation be
5632 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5633 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5634 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5635 && GET_CODE (op1
) == CONST_INT
5636 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5637 return simplify_gen_binary (IOR
, mode
,
5639 (AND
, mode
, XEXP (op0
, 0),
5640 GEN_INT (INTVAL (XEXP (op0
, 1))
5641 & ~INTVAL (op1
))), op1
);
5643 if (GET_CODE (x
) != AND
)
5650 /* Convert (A | B) & A to A. */
5651 if (GET_CODE (op0
) == IOR
5652 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5653 || rtx_equal_p (XEXP (op0
, 1), op1
))
5654 && ! side_effects_p (XEXP (op0
, 0))
5655 && ! side_effects_p (XEXP (op0
, 1)))
5658 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5659 apply the distributive law and then the inverse distributive
5660 law to see if things simplify. */
5661 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5663 rtx result
= distribute_and_simplify_rtx (x
, 0);
5667 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5669 rtx result
= distribute_and_simplify_rtx (x
, 1);
5676 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5677 if (GET_CODE (op1
) == CONST_INT
5678 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5679 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5682 /* Convert (A & B) | A to A. */
5683 if (GET_CODE (op0
) == AND
5684 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5685 || rtx_equal_p (XEXP (op0
, 1), op1
))
5686 && ! side_effects_p (XEXP (op0
, 0))
5687 && ! side_effects_p (XEXP (op0
, 1)))
5690 /* If we have (ior (and A B) C), apply the distributive law and then
5691 the inverse distributive law to see if things simplify. */
5693 if (GET_CODE (op0
) == AND
)
5695 rtx result
= distribute_and_simplify_rtx (x
, 0);
5700 if (GET_CODE (op1
) == AND
)
5702 rtx result
= distribute_and_simplify_rtx (x
, 1);
5707 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5708 mode size to (rotate A CX). */
5710 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5711 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5712 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5713 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5714 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5715 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5716 == GET_MODE_BITSIZE (mode
)))
5717 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5718 (GET_CODE (op0
) == ASHIFT
5719 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5721 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5722 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5723 does not affect any of the bits in OP1, it can really be done
5724 as a PLUS and we can associate. We do this by seeing if OP1
5725 can be safely shifted left C bits. */
5726 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5727 && GET_CODE (XEXP (op0
, 0)) == PLUS
5728 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5729 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5730 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5732 int count
= INTVAL (XEXP (op0
, 1));
5733 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5735 if (mask
>> count
== INTVAL (op1
)
5736 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5738 SUBST (XEXP (XEXP (op0
, 0), 1),
5739 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5746 /* If we are XORing two things that have no bits in common,
5747 convert them into an IOR. This helps to detect rotation encoded
5748 using those methods and possibly other simplifications. */
5750 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5751 && (nonzero_bits (op0
, mode
)
5752 & nonzero_bits (op1
, mode
)) == 0)
5753 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
5755 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5756 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5759 int num_negated
= 0;
5761 if (GET_CODE (op0
) == NOT
)
5762 num_negated
++, op0
= XEXP (op0
, 0);
5763 if (GET_CODE (op1
) == NOT
)
5764 num_negated
++, op1
= XEXP (op1
, 0);
5766 if (num_negated
== 2)
5768 SUBST (XEXP (x
, 0), op0
);
5769 SUBST (XEXP (x
, 1), op1
);
5771 else if (num_negated
== 1)
5773 simplify_gen_unary (NOT
, mode
,
5774 simplify_gen_binary (XOR
, mode
, op0
, op1
),
5778 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5779 correspond to a machine insn or result in further simplifications
5780 if B is a constant. */
5782 if (GET_CODE (op0
) == AND
5783 && rtx_equal_p (XEXP (op0
, 1), op1
)
5784 && ! side_effects_p (op1
))
5785 return simplify_gen_binary (AND
, mode
,
5786 simplify_gen_unary (NOT
, mode
,
5787 XEXP (op0
, 0), mode
),
5790 else if (GET_CODE (op0
) == AND
5791 && rtx_equal_p (XEXP (op0
, 0), op1
)
5792 && ! side_effects_p (op1
))
5793 return simplify_gen_binary (AND
, mode
,
5794 simplify_gen_unary (NOT
, mode
,
5795 XEXP (op0
, 1), mode
),
5798 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5799 comparison if STORE_FLAG_VALUE is 1. */
5800 if (STORE_FLAG_VALUE
== 1
5801 && op1
== const1_rtx
5802 && COMPARISON_P (op0
)
5803 && (reversed
= reversed_comparison (op0
, mode
)))
5806 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5807 is (lt foo (const_int 0)), so we can perform the above
5808 simplification if STORE_FLAG_VALUE is 1. */
5810 if (STORE_FLAG_VALUE
== 1
5811 && op1
== const1_rtx
5812 && GET_CODE (op0
) == LSHIFTRT
5813 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5814 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5815 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5817 /* (xor (comparison foo bar) (const_int sign-bit))
5818 when STORE_FLAG_VALUE is the sign bit. */
5819 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5820 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5821 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5822 && op1
== const_true_rtx
5823 && COMPARISON_P (op0
)
5824 && (reversed
= reversed_comparison (op0
, mode
)))
5836 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5837 operations" because they can be replaced with two more basic operations.
5838 ZERO_EXTEND is also considered "compound" because it can be replaced with
5839 an AND operation, which is simpler, though only one operation.
5841 The function expand_compound_operation is called with an rtx expression
5842 and will convert it to the appropriate shifts and AND operations,
5843 simplifying at each stage.
5845 The function make_compound_operation is called to convert an expression
5846 consisting of shifts and ANDs into the equivalent compound expression.
5847 It is the inverse of this function, loosely speaking. */
5850 expand_compound_operation (rtx x
)
5852 unsigned HOST_WIDE_INT pos
= 0, len
;
5854 unsigned int modewidth
;
5857 switch (GET_CODE (x
))
5862 /* We can't necessarily use a const_int for a multiword mode;
5863 it depends on implicitly extending the value.
5864 Since we don't know the right way to extend it,
5865 we can't tell whether the implicit way is right.
5867 Even for a mode that is no wider than a const_int,
5868 we can't win, because we need to sign extend one of its bits through
5869 the rest of it, and we don't know which bit. */
5870 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5873 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5874 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5875 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5876 reloaded. If not for that, MEM's would very rarely be safe.
5878 Reject MODEs bigger than a word, because we might not be able
5879 to reference a two-register group starting with an arbitrary register
5880 (and currently gen_lowpart might crash for a SUBREG). */
5882 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5885 /* Reject MODEs that aren't scalar integers because turning vector
5886 or complex modes into shifts causes problems. */
5888 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5891 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5892 /* If the inner object has VOIDmode (the only way this can happen
5893 is if it is an ASM_OPERANDS), we can't do anything since we don't
5894 know how much masking to do. */
5903 /* ... fall through ... */
5906 /* If the operand is a CLOBBER, just return it. */
5907 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5910 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5911 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5912 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5915 /* Reject MODEs that aren't scalar integers because turning vector
5916 or complex modes into shifts causes problems. */
5918 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5921 len
= INTVAL (XEXP (x
, 1));
5922 pos
= INTVAL (XEXP (x
, 2));
5924 /* If this goes outside the object being extracted, replace the object
5925 with a (use (mem ...)) construct that only combine understands
5926 and is used only for this purpose. */
5927 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5928 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5930 if (BITS_BIG_ENDIAN
)
5931 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5938 /* Convert sign extension to zero extension, if we know that the high
5939 bit is not set, as this is easier to optimize. It will be converted
5940 back to cheaper alternative in make_extraction. */
5941 if (GET_CODE (x
) == SIGN_EXTEND
5942 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5943 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5944 & ~(((unsigned HOST_WIDE_INT
)
5945 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5949 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5950 rtx temp2
= expand_compound_operation (temp
);
5952 /* Make sure this is a profitable operation. */
5953 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5955 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5961 /* We can optimize some special cases of ZERO_EXTEND. */
5962 if (GET_CODE (x
) == ZERO_EXTEND
)
5964 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5965 know that the last value didn't have any inappropriate bits
5967 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5968 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5969 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5970 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5971 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5972 return XEXP (XEXP (x
, 0), 0);
5974 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5975 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5976 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5977 && subreg_lowpart_p (XEXP (x
, 0))
5978 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5979 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5980 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5981 return SUBREG_REG (XEXP (x
, 0));
5983 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5984 is a comparison and STORE_FLAG_VALUE permits. This is like
5985 the first case, but it works even when GET_MODE (x) is larger
5986 than HOST_WIDE_INT. */
5987 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5988 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5989 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5990 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5991 <= HOST_BITS_PER_WIDE_INT
)
5992 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5993 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5994 return XEXP (XEXP (x
, 0), 0);
5996 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5997 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5998 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5999 && subreg_lowpart_p (XEXP (x
, 0))
6000 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6001 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6002 <= HOST_BITS_PER_WIDE_INT
)
6003 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6004 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6005 return SUBREG_REG (XEXP (x
, 0));
6009 /* If we reach here, we want to return a pair of shifts. The inner
6010 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6011 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6012 logical depending on the value of UNSIGNEDP.
6014 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6015 converted into an AND of a shift.
6017 We must check for the case where the left shift would have a negative
6018 count. This can happen in a case like (x >> 31) & 255 on machines
6019 that can't shift by a constant. On those machines, we would first
6020 combine the shift with the AND to produce a variable-position
6021 extraction. Then the constant of 31 would be substituted in to produce
6022 a such a position. */
6024 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6025 if (modewidth
+ len
>= pos
)
6026 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6028 simplify_shift_const (NULL_RTX
, ASHIFT
,
6031 modewidth
- pos
- len
),
6034 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6035 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6036 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6039 ((HOST_WIDE_INT
) 1 << len
) - 1);
6041 /* Any other cases we can't handle. */
6044 /* If we couldn't do this for some reason, return the original
6046 if (GET_CODE (tem
) == CLOBBER
)
6052 /* X is a SET which contains an assignment of one object into
6053 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6054 or certain SUBREGS). If possible, convert it into a series of
6057 We half-heartedly support variable positions, but do not at all
6058 support variable lengths. */
6061 expand_field_assignment (rtx x
)
6064 rtx pos
; /* Always counts from low bit. */
6066 rtx mask
, cleared
, masked
;
6067 enum machine_mode compute_mode
;
6069 /* Loop until we find something we can't simplify. */
6072 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6073 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6075 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6076 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6077 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6079 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6080 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
6082 inner
= XEXP (SET_DEST (x
), 0);
6083 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6084 pos
= XEXP (SET_DEST (x
), 2);
6086 /* If the position is constant and spans the width of INNER,
6087 surround INNER with a USE to indicate this. */
6088 if (GET_CODE (pos
) == CONST_INT
6089 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6090 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
6092 if (BITS_BIG_ENDIAN
)
6094 if (GET_CODE (pos
) == CONST_INT
)
6095 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6097 else if (GET_CODE (pos
) == MINUS
6098 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
6099 && (INTVAL (XEXP (pos
, 1))
6100 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6101 /* If position is ADJUST - X, new position is X. */
6102 pos
= XEXP (pos
, 0);
6104 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6105 GEN_INT (GET_MODE_BITSIZE (
6112 /* A SUBREG between two modes that occupy the same numbers of words
6113 can be done by moving the SUBREG to the source. */
6114 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6115 /* We need SUBREGs to compute nonzero_bits properly. */
6116 && nonzero_sign_valid
6117 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6118 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6119 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6120 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6122 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6124 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6131 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6132 inner
= SUBREG_REG (inner
);
6134 compute_mode
= GET_MODE (inner
);
6136 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6137 if (! SCALAR_INT_MODE_P (compute_mode
))
6139 enum machine_mode imode
;
6141 /* Don't do anything for vector or complex integral types. */
6142 if (! FLOAT_MODE_P (compute_mode
))
6145 /* Try to find an integral mode to pun with. */
6146 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6147 if (imode
== BLKmode
)
6150 compute_mode
= imode
;
6151 inner
= gen_lowpart (imode
, inner
);
6154 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6155 if (len
>= HOST_BITS_PER_WIDE_INT
)
6158 /* Now compute the equivalent expression. Make a copy of INNER
6159 for the SET_DEST in case it is a MEM into which we will substitute;
6160 we don't want shared RTL in that case. */
6161 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6162 cleared
= simplify_gen_binary (AND
, compute_mode
,
6163 simplify_gen_unary (NOT
, compute_mode
,
6164 simplify_gen_binary (ASHIFT
,
6169 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6170 simplify_gen_binary (
6172 gen_lowpart (compute_mode
, SET_SRC (x
)),
6176 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6177 simplify_gen_binary (IOR
, compute_mode
,
6184 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6185 it is an RTX that represents a variable starting position; otherwise,
6186 POS is the (constant) starting bit position (counted from the LSB).
6188 INNER may be a USE. This will occur when we started with a bitfield
6189 that went outside the boundary of the object in memory, which is
6190 allowed on most machines. To isolate this case, we produce a USE
6191 whose mode is wide enough and surround the MEM with it. The only
6192 code that understands the USE is this routine. If it is not removed,
6193 it will cause the resulting insn not to match.
6195 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6198 IN_DEST is nonzero if this is a reference in the destination of a
6199 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6200 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6203 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6204 ZERO_EXTRACT should be built even for bits starting at bit 0.
6206 MODE is the desired mode of the result (if IN_DEST == 0).
6208 The result is an RTX for the extraction or NULL_RTX if the target
6212 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6213 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6214 int in_dest
, int in_compare
)
6216 /* This mode describes the size of the storage area
6217 to fetch the overall value from. Within that, we
6218 ignore the POS lowest bits, etc. */
6219 enum machine_mode is_mode
= GET_MODE (inner
);
6220 enum machine_mode inner_mode
;
6221 enum machine_mode wanted_inner_mode
= byte_mode
;
6222 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6223 enum machine_mode pos_mode
= word_mode
;
6224 enum machine_mode extraction_mode
= word_mode
;
6225 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6228 rtx orig_pos_rtx
= pos_rtx
;
6229 HOST_WIDE_INT orig_pos
;
6231 /* Get some information about INNER and get the innermost object. */
6232 if (GET_CODE (inner
) == USE
)
6233 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6234 /* We don't need to adjust the position because we set up the USE
6235 to pretend that it was a full-word object. */
6236 spans_byte
= 1, inner
= XEXP (inner
, 0);
6237 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6239 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6240 consider just the QI as the memory to extract from.
6241 The subreg adds or removes high bits; its mode is
6242 irrelevant to the meaning of this extraction,
6243 since POS and LEN count from the lsb. */
6244 if (MEM_P (SUBREG_REG (inner
)))
6245 is_mode
= GET_MODE (SUBREG_REG (inner
));
6246 inner
= SUBREG_REG (inner
);
6248 else if (GET_CODE (inner
) == ASHIFT
6249 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6250 && pos_rtx
== 0 && pos
== 0
6251 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6253 /* We're extracting the least significant bits of an rtx
6254 (ashift X (const_int C)), where LEN > C. Extract the
6255 least significant (LEN - C) bits of X, giving an rtx
6256 whose mode is MODE, then shift it left C times. */
6257 new = make_extraction (mode
, XEXP (inner
, 0),
6258 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6259 unsignedp
, in_dest
, in_compare
);
6261 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6264 inner_mode
= GET_MODE (inner
);
6266 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6267 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6269 /* See if this can be done without an extraction. We never can if the
6270 width of the field is not the same as that of some integer mode. For
6271 registers, we can only avoid the extraction if the position is at the
6272 low-order bit and this is either not in the destination or we have the
6273 appropriate STRICT_LOW_PART operation available.
6275 For MEM, we can avoid an extract if the field starts on an appropriate
6276 boundary and we can change the mode of the memory reference. However,
6277 we cannot directly access the MEM if we have a USE and the underlying
6278 MEM is not TMODE. This combination means that MEM was being used in a
6279 context where bits outside its mode were being referenced; that is only
6280 valid in bit-field insns. */
6282 if (tmode
!= BLKmode
6283 && ! (spans_byte
&& inner_mode
!= tmode
)
6284 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6288 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6289 || (MEM_P (inner
) && pos_rtx
== 0
6291 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6292 : BITS_PER_UNIT
)) == 0
6293 /* We can't do this if we are widening INNER_MODE (it
6294 may not be aligned, for one thing). */
6295 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6296 && (inner_mode
== tmode
6297 || (! mode_dependent_address_p (XEXP (inner
, 0))
6298 && ! MEM_VOLATILE_P (inner
))))))
6300 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6301 field. If the original and current mode are the same, we need not
6302 adjust the offset. Otherwise, we do if bytes big endian.
6304 If INNER is not a MEM, get a piece consisting of just the field
6305 of interest (in this case POS % BITS_PER_WORD must be 0). */
6309 HOST_WIDE_INT offset
;
6311 /* POS counts from lsb, but make OFFSET count in memory order. */
6312 if (BYTES_BIG_ENDIAN
)
6313 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6315 offset
= pos
/ BITS_PER_UNIT
;
6317 new = adjust_address_nv (inner
, tmode
, offset
);
6319 else if (REG_P (inner
))
6321 if (tmode
!= inner_mode
)
6323 /* We can't call gen_lowpart in a DEST since we
6324 always want a SUBREG (see below) and it would sometimes
6325 return a new hard register. */
6328 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6330 if (WORDS_BIG_ENDIAN
6331 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6332 final_word
= ((GET_MODE_SIZE (inner_mode
)
6333 - GET_MODE_SIZE (tmode
))
6334 / UNITS_PER_WORD
) - final_word
;
6336 final_word
*= UNITS_PER_WORD
;
6337 if (BYTES_BIG_ENDIAN
&&
6338 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6339 final_word
+= (GET_MODE_SIZE (inner_mode
)
6340 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6342 /* Avoid creating invalid subregs, for example when
6343 simplifying (x>>32)&255. */
6344 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
6347 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6350 new = gen_lowpart (tmode
, inner
);
6356 new = force_to_mode (inner
, tmode
,
6357 len
>= HOST_BITS_PER_WIDE_INT
6358 ? ~(unsigned HOST_WIDE_INT
) 0
6359 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6362 /* If this extraction is going into the destination of a SET,
6363 make a STRICT_LOW_PART unless we made a MEM. */
6366 return (MEM_P (new) ? new
6367 : (GET_CODE (new) != SUBREG
6368 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6369 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6374 if (GET_CODE (new) == CONST_INT
)
6375 return gen_int_mode (INTVAL (new), mode
);
6377 /* If we know that no extraneous bits are set, and that the high
6378 bit is not set, convert the extraction to the cheaper of
6379 sign and zero extension, that are equivalent in these cases. */
6380 if (flag_expensive_optimizations
6381 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6382 && ((nonzero_bits (new, tmode
)
6383 & ~(((unsigned HOST_WIDE_INT
)
6384 GET_MODE_MASK (tmode
))
6388 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6389 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6391 /* Prefer ZERO_EXTENSION, since it gives more information to
6393 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6398 /* Otherwise, sign- or zero-extend unless we already are in the
6401 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6405 /* Unless this is a COMPARE or we have a funny memory reference,
6406 don't do anything with zero-extending field extracts starting at
6407 the low-order bit since they are simple AND operations. */
6408 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6409 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6412 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6413 we would be spanning bytes or if the position is not a constant and the
6414 length is not 1. In all other cases, we would only be going outside
6415 our object in cases when an original shift would have been
6417 if (! spans_byte
&& MEM_P (inner
)
6418 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6419 || (pos_rtx
!= 0 && len
!= 1)))
6422 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6423 and the mode for the result. */
6424 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6426 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6427 pos_mode
= mode_for_extraction (EP_insv
, 2);
6428 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6431 if (! in_dest
&& unsignedp
6432 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6434 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6435 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6436 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6439 if (! in_dest
&& ! unsignedp
6440 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6442 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6443 pos_mode
= mode_for_extraction (EP_extv
, 3);
6444 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6447 /* Never narrow an object, since that might not be safe. */
6449 if (mode
!= VOIDmode
6450 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6451 extraction_mode
= mode
;
6453 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6454 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6455 pos_mode
= GET_MODE (pos_rtx
);
6457 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6458 if we have to change the mode of memory and cannot, the desired mode is
6461 wanted_inner_mode
= wanted_inner_reg_mode
;
6462 else if (inner_mode
!= wanted_inner_mode
6463 && (mode_dependent_address_p (XEXP (inner
, 0))
6464 || MEM_VOLATILE_P (inner
)))
6465 wanted_inner_mode
= extraction_mode
;
6469 if (BITS_BIG_ENDIAN
)
6471 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6472 BITS_BIG_ENDIAN style. If position is constant, compute new
6473 position. Otherwise, build subtraction.
6474 Note that POS is relative to the mode of the original argument.
6475 If it's a MEM we need to recompute POS relative to that.
6476 However, if we're extracting from (or inserting into) a register,
6477 we want to recompute POS relative to wanted_inner_mode. */
6478 int width
= (MEM_P (inner
)
6479 ? GET_MODE_BITSIZE (is_mode
)
6480 : GET_MODE_BITSIZE (wanted_inner_mode
));
6483 pos
= width
- len
- pos
;
6486 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6487 /* POS may be less than 0 now, but we check for that below.
6488 Note that it can only be less than 0 if !MEM_P (inner). */
6491 /* If INNER has a wider mode, make it smaller. If this is a constant
6492 extract, try to adjust the byte to point to the byte containing
6494 if (wanted_inner_mode
!= VOIDmode
6495 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6497 && (inner_mode
== wanted_inner_mode
6498 || (! mode_dependent_address_p (XEXP (inner
, 0))
6499 && ! MEM_VOLATILE_P (inner
))))))
6503 /* The computations below will be correct if the machine is big
6504 endian in both bits and bytes or little endian in bits and bytes.
6505 If it is mixed, we must adjust. */
6507 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6508 adjust OFFSET to compensate. */
6509 if (BYTES_BIG_ENDIAN
6511 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6512 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6514 /* If this is a constant position, we can move to the desired byte.
6515 Be careful not to go beyond the original object. */
6518 enum machine_mode bfmode
= smallest_mode_for_size (len
, MODE_INT
);
6519 offset
+= pos
/ GET_MODE_BITSIZE (bfmode
);
6520 pos
%= GET_MODE_BITSIZE (bfmode
);
6523 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6525 && is_mode
!= wanted_inner_mode
)
6526 offset
= (GET_MODE_SIZE (is_mode
)
6527 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6529 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6530 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6533 /* If INNER is not memory, we can always get it into the proper mode. If we
6534 are changing its mode, POS must be a constant and smaller than the size
6536 else if (!MEM_P (inner
))
6538 if (GET_MODE (inner
) != wanted_inner_mode
6540 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6543 inner
= force_to_mode (inner
, wanted_inner_mode
,
6545 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6546 ? ~(unsigned HOST_WIDE_INT
) 0
6547 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6552 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6553 have to zero extend. Otherwise, we can just use a SUBREG. */
6555 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6557 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6559 /* If we know that no extraneous bits are set, and that the high
6560 bit is not set, convert extraction to cheaper one - either
6561 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6563 if (flag_expensive_optimizations
6564 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6565 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6566 & ~(((unsigned HOST_WIDE_INT
)
6567 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6571 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6573 /* Prefer ZERO_EXTENSION, since it gives more information to
6575 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6580 else if (pos_rtx
!= 0
6581 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6582 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6584 /* Make POS_RTX unless we already have it and it is correct. If we don't
6585 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6587 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6588 pos_rtx
= orig_pos_rtx
;
6590 else if (pos_rtx
== 0)
6591 pos_rtx
= GEN_INT (pos
);
6593 /* Make the required operation. See if we can use existing rtx. */
6594 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6595 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6597 new = gen_lowpart (mode
, new);
6602 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6603 with any other operations in X. Return X without that shift if so. */
6606 extract_left_shift (rtx x
, int count
)
6608 enum rtx_code code
= GET_CODE (x
);
6609 enum machine_mode mode
= GET_MODE (x
);
6615 /* This is the shift itself. If it is wide enough, we will return
6616 either the value being shifted if the shift count is equal to
6617 COUNT or a shift for the difference. */
6618 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6619 && INTVAL (XEXP (x
, 1)) >= count
)
6620 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6621 INTVAL (XEXP (x
, 1)) - count
);
6625 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6626 return simplify_gen_unary (code
, mode
, tem
, mode
);
6630 case PLUS
: case IOR
: case XOR
: case AND
:
6631 /* If we can safely shift this constant and we find the inner shift,
6632 make a new operation. */
6633 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6634 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6635 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6636 return simplify_gen_binary (code
, mode
, tem
,
6637 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6648 /* Look at the expression rooted at X. Look for expressions
6649 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6650 Form these expressions.
6652 Return the new rtx, usually just X.
6654 Also, for machines like the VAX that don't have logical shift insns,
6655 try to convert logical to arithmetic shift operations in cases where
6656 they are equivalent. This undoes the canonicalizations to logical
6657 shifts done elsewhere.
6659 We try, as much as possible, to re-use rtl expressions to save memory.
6661 IN_CODE says what kind of expression we are processing. Normally, it is
6662 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6663 being kludges), it is MEM. When processing the arguments of a comparison
6664 or a COMPARE against zero, it is COMPARE. */
6667 make_compound_operation (rtx x
, enum rtx_code in_code
)
6669 enum rtx_code code
= GET_CODE (x
);
6670 enum machine_mode mode
= GET_MODE (x
);
6671 int mode_width
= GET_MODE_BITSIZE (mode
);
6673 enum rtx_code next_code
;
6679 /* Select the code to be used in recursive calls. Once we are inside an
6680 address, we stay there. If we have a comparison, set to COMPARE,
6681 but once inside, go back to our default of SET. */
6683 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6684 : ((code
== COMPARE
|| COMPARISON_P (x
))
6685 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6686 : in_code
== COMPARE
? SET
: in_code
);
6688 /* Process depending on the code of this operation. If NEW is set
6689 nonzero, it will be returned. */
6694 /* Convert shifts by constants into multiplications if inside
6696 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6697 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6698 && INTVAL (XEXP (x
, 1)) >= 0)
6700 new = make_compound_operation (XEXP (x
, 0), next_code
);
6701 new = gen_rtx_MULT (mode
, new,
6702 GEN_INT ((HOST_WIDE_INT
) 1
6703 << INTVAL (XEXP (x
, 1))));
6708 /* If the second operand is not a constant, we can't do anything
6710 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6713 /* If the constant is a power of two minus one and the first operand
6714 is a logical right shift, make an extraction. */
6715 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6716 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6718 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6719 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6720 0, in_code
== COMPARE
);
6723 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6724 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6725 && subreg_lowpart_p (XEXP (x
, 0))
6726 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6727 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6729 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6731 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6732 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6733 0, in_code
== COMPARE
);
6735 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6736 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6737 || GET_CODE (XEXP (x
, 0)) == IOR
)
6738 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6739 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6740 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6742 /* Apply the distributive law, and then try to make extractions. */
6743 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6744 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6746 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6748 new = make_compound_operation (new, in_code
);
6751 /* If we are have (and (rotate X C) M) and C is larger than the number
6752 of bits in M, this is an extraction. */
6754 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6755 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6756 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6757 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6759 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6760 new = make_extraction (mode
, new,
6761 (GET_MODE_BITSIZE (mode
)
6762 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6763 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6766 /* On machines without logical shifts, if the operand of the AND is
6767 a logical shift and our mask turns off all the propagated sign
6768 bits, we can replace the logical shift with an arithmetic shift. */
6769 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6770 && !have_insn_for (LSHIFTRT
, mode
)
6771 && have_insn_for (ASHIFTRT
, mode
)
6772 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6773 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6774 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6775 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6777 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6779 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6780 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6782 gen_rtx_ASHIFTRT (mode
,
6783 make_compound_operation
6784 (XEXP (XEXP (x
, 0), 0), next_code
),
6785 XEXP (XEXP (x
, 0), 1)));
6788 /* If the constant is one less than a power of two, this might be
6789 representable by an extraction even if no shift is present.
6790 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6791 we are in a COMPARE. */
6792 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6793 new = make_extraction (mode
,
6794 make_compound_operation (XEXP (x
, 0),
6796 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6798 /* If we are in a comparison and this is an AND with a power of two,
6799 convert this into the appropriate bit extract. */
6800 else if (in_code
== COMPARE
6801 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6802 new = make_extraction (mode
,
6803 make_compound_operation (XEXP (x
, 0),
6805 i
, NULL_RTX
, 1, 1, 0, 1);
6810 /* If the sign bit is known to be zero, replace this with an
6811 arithmetic shift. */
6812 if (have_insn_for (ASHIFTRT
, mode
)
6813 && ! have_insn_for (LSHIFTRT
, mode
)
6814 && mode_width
<= HOST_BITS_PER_WIDE_INT
6815 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6817 new = gen_rtx_ASHIFTRT (mode
,
6818 make_compound_operation (XEXP (x
, 0),
6824 /* ... fall through ... */
6830 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6831 this is a SIGN_EXTRACT. */
6832 if (GET_CODE (rhs
) == CONST_INT
6833 && GET_CODE (lhs
) == ASHIFT
6834 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6835 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6837 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6838 new = make_extraction (mode
, new,
6839 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6840 NULL_RTX
, mode_width
- INTVAL (rhs
),
6841 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6845 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6846 If so, try to merge the shifts into a SIGN_EXTEND. We could
6847 also do this for some cases of SIGN_EXTRACT, but it doesn't
6848 seem worth the effort; the case checked for occurs on Alpha. */
6851 && ! (GET_CODE (lhs
) == SUBREG
6852 && (OBJECT_P (SUBREG_REG (lhs
))))
6853 && GET_CODE (rhs
) == CONST_INT
6854 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6855 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6856 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6857 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6858 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6863 /* Call ourselves recursively on the inner expression. If we are
6864 narrowing the object and it has a different RTL code from
6865 what it originally did, do this SUBREG as a force_to_mode. */
6867 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6871 simplified
= simplify_subreg (GET_MODE (x
), tem
, GET_MODE (tem
),
6877 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6878 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6879 && subreg_lowpart_p (x
))
6881 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6884 /* If we have something other than a SUBREG, we might have
6885 done an expansion, so rerun ourselves. */
6886 if (GET_CODE (newer
) != SUBREG
)
6887 newer
= make_compound_operation (newer
, in_code
);
6903 x
= gen_lowpart (mode
, new);
6904 code
= GET_CODE (x
);
6907 /* Now recursively process each operand of this operation. */
6908 fmt
= GET_RTX_FORMAT (code
);
6909 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6912 new = make_compound_operation (XEXP (x
, i
), next_code
);
6913 SUBST (XEXP (x
, i
), new);
6919 /* Given M see if it is a value that would select a field of bits
6920 within an item, but not the entire word. Return -1 if not.
6921 Otherwise, return the starting position of the field, where 0 is the
6924 *PLEN is set to the length of the field. */
6927 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6929 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6930 int pos
= exact_log2 (m
& -m
);
6934 /* Now shift off the low-order zero bits and see if we have a
6935 power of two minus 1. */
6936 len
= exact_log2 ((m
>> pos
) + 1);
6945 /* See if X can be simplified knowing that we will only refer to it in
6946 MODE and will only refer to those bits that are nonzero in MASK.
6947 If other bits are being computed or if masking operations are done
6948 that select a superset of the bits in MASK, they can sometimes be
6951 Return a possibly simplified expression, but always convert X to
6952 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6954 Also, if REG is nonzero and X is a register equal in value to REG,
6957 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6958 are all off in X. This is used when X will be complemented, by either
6959 NOT, NEG, or XOR. */
6962 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6963 rtx reg
, int just_select
)
6965 enum rtx_code code
= GET_CODE (x
);
6966 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6967 enum machine_mode op_mode
;
6968 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6971 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6972 code below will do the wrong thing since the mode of such an
6973 expression is VOIDmode.
6975 Also do nothing if X is a CLOBBER; this can happen if X was
6976 the return value from a call to gen_lowpart. */
6977 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6980 /* We want to perform the operation is its present mode unless we know
6981 that the operation is valid in MODE, in which case we do the operation
6983 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6984 && have_insn_for (code
, mode
))
6985 ? mode
: GET_MODE (x
));
6987 /* It is not valid to do a right-shift in a narrower mode
6988 than the one it came in with. */
6989 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6990 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6991 op_mode
= GET_MODE (x
);
6993 /* Truncate MASK to fit OP_MODE. */
6995 mask
&= GET_MODE_MASK (op_mode
);
6997 /* When we have an arithmetic operation, or a shift whose count we
6998 do not know, we need to assume that all bits up to the highest-order
6999 bit in MASK will be needed. This is how we form such a mask. */
7000 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7001 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7003 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7006 /* Determine what bits of X are guaranteed to be (non)zero. */
7007 nonzero
= nonzero_bits (x
, mode
);
7009 /* If none of the bits in X are needed, return a zero. */
7010 if (! just_select
&& (nonzero
& mask
) == 0)
7013 /* If X is a CONST_INT, return a new one. Do this here since the
7014 test below will fail. */
7015 if (GET_CODE (x
) == CONST_INT
)
7017 if (SCALAR_INT_MODE_P (mode
))
7018 return gen_int_mode (INTVAL (x
) & mask
, mode
);
7021 x
= GEN_INT (INTVAL (x
) & mask
);
7022 return gen_lowpart_common (mode
, x
);
7026 /* If X is narrower than MODE and we want all the bits in X's mode, just
7027 get X in the proper mode. */
7028 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
7029 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
7030 return gen_lowpart (mode
, x
);
7035 /* If X is a (clobber (const_int)), return it since we know we are
7036 generating something that won't match. */
7040 /* X is a (use (mem ..)) that was made from a bit-field extraction that
7041 spanned the boundary of the MEM. If we are now masking so it is
7042 within that boundary, we don't need the USE any more. */
7043 if (! BITS_BIG_ENDIAN
7044 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7045 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7052 x
= expand_compound_operation (x
);
7053 if (GET_CODE (x
) != code
)
7054 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7058 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
7059 || rtx_equal_p (reg
, get_last_value (x
))))
7064 if (subreg_lowpart_p (x
)
7065 /* We can ignore the effect of this SUBREG if it narrows the mode or
7066 if the constant masks to zero all the bits the mode doesn't
7068 && ((GET_MODE_SIZE (GET_MODE (x
))
7069 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7071 & GET_MODE_MASK (GET_MODE (x
))
7072 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
7073 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
7077 /* If this is an AND with a constant, convert it into an AND
7078 whose constant is the AND of that constant with MASK. If it
7079 remains an AND of MASK, delete it since it is redundant. */
7081 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7083 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
7084 mask
& INTVAL (XEXP (x
, 1)));
7086 /* If X is still an AND, see if it is an AND with a mask that
7087 is just some low-order bits. If so, and it is MASK, we don't
7090 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7091 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7095 /* If it remains an AND, try making another AND with the bits
7096 in the mode mask that aren't in MASK turned on. If the
7097 constant in the AND is wide enough, this might make a
7098 cheaper constant. */
7100 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7101 && GET_MODE_MASK (GET_MODE (x
)) != mask
7102 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7104 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7105 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7106 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7109 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7110 number, sign extend it. */
7111 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7112 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7113 cval
|= (HOST_WIDE_INT
) -1 << width
;
7115 y
= simplify_gen_binary (AND
, GET_MODE (x
),
7116 XEXP (x
, 0), GEN_INT (cval
));
7117 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7127 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7128 low-order bits (as in an alignment operation) and FOO is already
7129 aligned to that boundary, mask C1 to that boundary as well.
7130 This may eliminate that PLUS and, later, the AND. */
7133 unsigned int width
= GET_MODE_BITSIZE (mode
);
7134 unsigned HOST_WIDE_INT smask
= mask
;
7136 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7137 number, sign extend it. */
7139 if (width
< HOST_BITS_PER_WIDE_INT
7140 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7141 smask
|= (HOST_WIDE_INT
) -1 << width
;
7143 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7144 && exact_log2 (- smask
) >= 0
7145 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7146 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7147 return force_to_mode (plus_constant (XEXP (x
, 0),
7148 (INTVAL (XEXP (x
, 1)) & smask
)),
7149 mode
, smask
, reg
, next_select
);
7152 /* ... fall through ... */
7155 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7156 most significant bit in MASK since carries from those bits will
7157 affect the bits we are interested in. */
7162 /* If X is (minus C Y) where C's least set bit is larger than any bit
7163 in the mask, then we may replace with (neg Y). */
7164 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7165 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7166 & -INTVAL (XEXP (x
, 0))))
7169 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7171 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7174 /* Similarly, if C contains every bit in the fuller_mask, then we may
7175 replace with (not Y). */
7176 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7177 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7178 == INTVAL (XEXP (x
, 0))))
7180 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7181 XEXP (x
, 1), GET_MODE (x
));
7182 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7190 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7191 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7192 operation which may be a bitfield extraction. Ensure that the
7193 constant we form is not wider than the mode of X. */
7195 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7196 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7197 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7198 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7199 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7200 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7201 + floor_log2 (INTVAL (XEXP (x
, 1))))
7202 < GET_MODE_BITSIZE (GET_MODE (x
)))
7203 && (INTVAL (XEXP (x
, 1))
7204 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7206 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7207 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7208 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7209 XEXP (XEXP (x
, 0), 0), temp
);
7210 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7211 XEXP (XEXP (x
, 0), 1));
7212 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7216 /* For most binary operations, just propagate into the operation and
7217 change the mode if we have an operation of that mode. */
7219 op0
= gen_lowpart (op_mode
,
7220 force_to_mode (XEXP (x
, 0), mode
, mask
,
7222 op1
= gen_lowpart (op_mode
,
7223 force_to_mode (XEXP (x
, 1), mode
, mask
,
7226 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7227 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7231 /* For left shifts, do the same, but just for the first operand.
7232 However, we cannot do anything with shifts where we cannot
7233 guarantee that the counts are smaller than the size of the mode
7234 because such a count will have a different meaning in a
7237 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7238 && INTVAL (XEXP (x
, 1)) >= 0
7239 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7240 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7241 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7242 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7245 /* If the shift count is a constant and we can do arithmetic in
7246 the mode of the shift, refine which bits we need. Otherwise, use the
7247 conservative form of the mask. */
7248 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7249 && INTVAL (XEXP (x
, 1)) >= 0
7250 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7251 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7252 mask
>>= INTVAL (XEXP (x
, 1));
7256 op0
= gen_lowpart (op_mode
,
7257 force_to_mode (XEXP (x
, 0), op_mode
,
7258 mask
, reg
, next_select
));
7260 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7261 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7265 /* Here we can only do something if the shift count is a constant,
7266 this shift constant is valid for the host, and we can do arithmetic
7269 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7270 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7271 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7273 rtx inner
= XEXP (x
, 0);
7274 unsigned HOST_WIDE_INT inner_mask
;
7276 /* Select the mask of the bits we need for the shift operand. */
7277 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7279 /* We can only change the mode of the shift if we can do arithmetic
7280 in the mode of the shift and INNER_MASK is no wider than the
7281 width of X's mode. */
7282 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7283 op_mode
= GET_MODE (x
);
7285 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7287 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7288 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7291 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7292 shift and AND produces only copies of the sign bit (C2 is one less
7293 than a power of two), we can do this with just a shift. */
7295 if (GET_CODE (x
) == LSHIFTRT
7296 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7297 /* The shift puts one of the sign bit copies in the least significant
7299 && ((INTVAL (XEXP (x
, 1))
7300 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7301 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7302 && exact_log2 (mask
+ 1) >= 0
7303 /* Number of bits left after the shift must be more than the mask
7305 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7306 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7307 /* Must be more sign bit copies than the mask needs. */
7308 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7309 >= exact_log2 (mask
+ 1)))
7310 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7311 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7312 - exact_log2 (mask
+ 1)));
7317 /* If we are just looking for the sign bit, we don't need this shift at
7318 all, even if it has a variable count. */
7319 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7320 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7321 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7322 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7324 /* If this is a shift by a constant, get a mask that contains those bits
7325 that are not copies of the sign bit. We then have two cases: If
7326 MASK only includes those bits, this can be a logical shift, which may
7327 allow simplifications. If MASK is a single-bit field not within
7328 those bits, we are requesting a copy of the sign bit and hence can
7329 shift the sign bit to the appropriate location. */
7331 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7332 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7336 /* If the considered data is wider than HOST_WIDE_INT, we can't
7337 represent a mask for all its bits in a single scalar.
7338 But we only care about the lower bits, so calculate these. */
7340 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7342 nonzero
= ~(HOST_WIDE_INT
) 0;
7344 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7345 is the number of bits a full-width mask would have set.
7346 We need only shift if these are fewer than nonzero can
7347 hold. If not, we must keep all bits set in nonzero. */
7349 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7350 < HOST_BITS_PER_WIDE_INT
)
7351 nonzero
>>= INTVAL (XEXP (x
, 1))
7352 + HOST_BITS_PER_WIDE_INT
7353 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7357 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7358 nonzero
>>= INTVAL (XEXP (x
, 1));
7361 if ((mask
& ~nonzero
) == 0
7362 || (i
= exact_log2 (mask
)) >= 0)
7364 x
= simplify_shift_const
7365 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7366 i
< 0 ? INTVAL (XEXP (x
, 1))
7367 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7369 if (GET_CODE (x
) != ASHIFTRT
)
7370 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7374 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7375 even if the shift count isn't a constant. */
7377 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7378 XEXP (x
, 0), XEXP (x
, 1));
7382 /* If this is a zero- or sign-extension operation that just affects bits
7383 we don't care about, remove it. Be sure the call above returned
7384 something that is still a shift. */
7386 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7387 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7388 && INTVAL (XEXP (x
, 1)) >= 0
7389 && (INTVAL (XEXP (x
, 1))
7390 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7391 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7392 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7393 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7400 /* If the shift count is constant and we can do computations
7401 in the mode of X, compute where the bits we care about are.
7402 Otherwise, we can't do anything. Don't change the mode of
7403 the shift or propagate MODE into the shift, though. */
7404 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7405 && INTVAL (XEXP (x
, 1)) >= 0)
7407 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7408 GET_MODE (x
), GEN_INT (mask
),
7410 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7412 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7413 INTVAL (temp
), reg
, next_select
));
7418 /* If we just want the low-order bit, the NEG isn't needed since it
7419 won't change the low-order bit. */
7421 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7423 /* We need any bits less significant than the most significant bit in
7424 MASK since carries from those bits will affect the bits we are
7430 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7431 same as the XOR case above. Ensure that the constant we form is not
7432 wider than the mode of X. */
7434 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7435 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7436 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7437 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7438 < GET_MODE_BITSIZE (GET_MODE (x
)))
7439 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7441 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7443 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7444 XEXP (XEXP (x
, 0), 0), temp
);
7445 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7446 temp
, XEXP (XEXP (x
, 0), 1));
7448 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7451 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7452 use the full mask inside the NOT. */
7456 op0
= gen_lowpart (op_mode
,
7457 force_to_mode (XEXP (x
, 0), mode
, mask
,
7459 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7460 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7464 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7465 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7466 which is equal to STORE_FLAG_VALUE. */
7467 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7468 && GET_MODE (XEXP (x
, 0)) == mode
7469 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7470 && (nonzero_bits (XEXP (x
, 0), mode
)
7471 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7472 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7477 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7478 written in a narrower mode. We play it safe and do not do so. */
7481 gen_lowpart (GET_MODE (x
),
7482 force_to_mode (XEXP (x
, 1), mode
,
7483 mask
, reg
, next_select
)));
7485 gen_lowpart (GET_MODE (x
),
7486 force_to_mode (XEXP (x
, 2), mode
,
7487 mask
, reg
, next_select
)));
7494 /* Ensure we return a value of the proper mode. */
7495 return gen_lowpart (mode
, x
);
7498 /* Return nonzero if X is an expression that has one of two values depending on
7499 whether some other value is zero or nonzero. In that case, we return the
7500 value that is being tested, *PTRUE is set to the value if the rtx being
7501 returned has a nonzero value, and *PFALSE is set to the other alternative.
7503 If we return zero, we set *PTRUE and *PFALSE to X. */
7506 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7508 enum machine_mode mode
= GET_MODE (x
);
7509 enum rtx_code code
= GET_CODE (x
);
7510 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7511 unsigned HOST_WIDE_INT nz
;
7513 /* If we are comparing a value against zero, we are done. */
7514 if ((code
== NE
|| code
== EQ
)
7515 && XEXP (x
, 1) == const0_rtx
)
7517 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7518 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7522 /* If this is a unary operation whose operand has one of two values, apply
7523 our opcode to compute those values. */
7524 else if (UNARY_P (x
)
7525 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7527 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7528 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7529 GET_MODE (XEXP (x
, 0)));
7533 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7534 make can't possibly match and would suppress other optimizations. */
7535 else if (code
== COMPARE
)
7538 /* If this is a binary operation, see if either side has only one of two
7539 values. If either one does or if both do and they are conditional on
7540 the same value, compute the new true and false values. */
7541 else if (BINARY_P (x
))
7543 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7544 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7546 if ((cond0
!= 0 || cond1
!= 0)
7547 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7549 /* If if_then_else_cond returned zero, then true/false are the
7550 same rtl. We must copy one of them to prevent invalid rtl
7553 true0
= copy_rtx (true0
);
7554 else if (cond1
== 0)
7555 true1
= copy_rtx (true1
);
7557 if (COMPARISON_P (x
))
7559 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7561 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7566 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7567 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7570 return cond0
? cond0
: cond1
;
7573 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7574 operands is zero when the other is nonzero, and vice-versa,
7575 and STORE_FLAG_VALUE is 1 or -1. */
7577 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7578 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7580 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7582 rtx op0
= XEXP (XEXP (x
, 0), 1);
7583 rtx op1
= XEXP (XEXP (x
, 1), 1);
7585 cond0
= XEXP (XEXP (x
, 0), 0);
7586 cond1
= XEXP (XEXP (x
, 1), 0);
7588 if (COMPARISON_P (cond0
)
7589 && COMPARISON_P (cond1
)
7590 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7591 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7592 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7593 || ((swap_condition (GET_CODE (cond0
))
7594 == reversed_comparison_code (cond1
, NULL
))
7595 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7596 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7597 && ! side_effects_p (x
))
7599 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7600 *pfalse
= simplify_gen_binary (MULT
, mode
,
7602 ? simplify_gen_unary (NEG
, mode
,
7610 /* Similarly for MULT, AND and UMIN, except that for these the result
7612 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7613 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7614 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7616 cond0
= XEXP (XEXP (x
, 0), 0);
7617 cond1
= XEXP (XEXP (x
, 1), 0);
7619 if (COMPARISON_P (cond0
)
7620 && COMPARISON_P (cond1
)
7621 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7622 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7623 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7624 || ((swap_condition (GET_CODE (cond0
))
7625 == reversed_comparison_code (cond1
, NULL
))
7626 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7627 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7628 && ! side_effects_p (x
))
7630 *ptrue
= *pfalse
= const0_rtx
;
7636 else if (code
== IF_THEN_ELSE
)
7638 /* If we have IF_THEN_ELSE already, extract the condition and
7639 canonicalize it if it is NE or EQ. */
7640 cond0
= XEXP (x
, 0);
7641 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7642 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7643 return XEXP (cond0
, 0);
7644 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7646 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7647 return XEXP (cond0
, 0);
7653 /* If X is a SUBREG, we can narrow both the true and false values
7654 if the inner expression, if there is a condition. */
7655 else if (code
== SUBREG
7656 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7659 true0
= simplify_gen_subreg (mode
, true0
,
7660 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7661 false0
= simplify_gen_subreg (mode
, false0
,
7662 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7663 if (true0
&& false0
)
7671 /* If X is a constant, this isn't special and will cause confusions
7672 if we treat it as such. Likewise if it is equivalent to a constant. */
7673 else if (CONSTANT_P (x
)
7674 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7677 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7678 will be least confusing to the rest of the compiler. */
7679 else if (mode
== BImode
)
7681 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7685 /* If X is known to be either 0 or -1, those are the true and
7686 false values when testing X. */
7687 else if (x
== constm1_rtx
|| x
== const0_rtx
7688 || (mode
!= VOIDmode
7689 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7691 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7695 /* Likewise for 0 or a single bit. */
7696 else if (SCALAR_INT_MODE_P (mode
)
7697 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7698 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7700 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7704 /* Otherwise fail; show no condition with true and false values the same. */
7705 *ptrue
= *pfalse
= x
;
7709 /* Return the value of expression X given the fact that condition COND
7710 is known to be true when applied to REG as its first operand and VAL
7711 as its second. X is known to not be shared and so can be modified in
7714 We only handle the simplest cases, and specifically those cases that
7715 arise with IF_THEN_ELSE expressions. */
7718 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7720 enum rtx_code code
= GET_CODE (x
);
7725 if (side_effects_p (x
))
7728 /* If either operand of the condition is a floating point value,
7729 then we have to avoid collapsing an EQ comparison. */
7731 && rtx_equal_p (x
, reg
)
7732 && ! FLOAT_MODE_P (GET_MODE (x
))
7733 && ! FLOAT_MODE_P (GET_MODE (val
)))
7736 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7739 /* If X is (abs REG) and we know something about REG's relationship
7740 with zero, we may be able to simplify this. */
7742 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7745 case GE
: case GT
: case EQ
:
7748 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7750 GET_MODE (XEXP (x
, 0)));
7755 /* The only other cases we handle are MIN, MAX, and comparisons if the
7756 operands are the same as REG and VAL. */
7758 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7760 if (rtx_equal_p (XEXP (x
, 0), val
))
7761 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7763 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7765 if (COMPARISON_P (x
))
7767 if (comparison_dominates_p (cond
, code
))
7768 return const_true_rtx
;
7770 code
= reversed_comparison_code (x
, NULL
);
7772 && comparison_dominates_p (cond
, code
))
7777 else if (code
== SMAX
|| code
== SMIN
7778 || code
== UMIN
|| code
== UMAX
)
7780 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7782 /* Do not reverse the condition when it is NE or EQ.
7783 This is because we cannot conclude anything about
7784 the value of 'SMAX (x, y)' when x is not equal to y,
7785 but we can when x equals y. */
7786 if ((code
== SMAX
|| code
== UMAX
)
7787 && ! (cond
== EQ
|| cond
== NE
))
7788 cond
= reverse_condition (cond
);
7793 return unsignedp
? x
: XEXP (x
, 1);
7795 return unsignedp
? x
: XEXP (x
, 0);
7797 return unsignedp
? XEXP (x
, 1) : x
;
7799 return unsignedp
? XEXP (x
, 0) : x
;
7806 else if (code
== SUBREG
)
7808 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7809 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7811 if (SUBREG_REG (x
) != r
)
7813 /* We must simplify subreg here, before we lose track of the
7814 original inner_mode. */
7815 new = simplify_subreg (GET_MODE (x
), r
,
7816 inner_mode
, SUBREG_BYTE (x
));
7820 SUBST (SUBREG_REG (x
), r
);
7825 /* We don't have to handle SIGN_EXTEND here, because even in the
7826 case of replacing something with a modeless CONST_INT, a
7827 CONST_INT is already (supposed to be) a valid sign extension for
7828 its narrower mode, which implies it's already properly
7829 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7830 story is different. */
7831 else if (code
== ZERO_EXTEND
)
7833 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7834 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7836 if (XEXP (x
, 0) != r
)
7838 /* We must simplify the zero_extend here, before we lose
7839 track of the original inner_mode. */
7840 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7845 SUBST (XEXP (x
, 0), r
);
7851 fmt
= GET_RTX_FORMAT (code
);
7852 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7855 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7856 else if (fmt
[i
] == 'E')
7857 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7858 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7865 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7866 assignment as a field assignment. */
7869 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7871 if (x
== y
|| rtx_equal_p (x
, y
))
7874 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7877 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7878 Note that all SUBREGs of MEM are paradoxical; otherwise they
7879 would have been rewritten. */
7880 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7881 && MEM_P (SUBREG_REG (y
))
7882 && rtx_equal_p (SUBREG_REG (y
),
7883 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7886 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7887 && MEM_P (SUBREG_REG (x
))
7888 && rtx_equal_p (SUBREG_REG (x
),
7889 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7892 /* We used to see if get_last_value of X and Y were the same but that's
7893 not correct. In one direction, we'll cause the assignment to have
7894 the wrong destination and in the case, we'll import a register into this
7895 insn that might have already have been dead. So fail if none of the
7896 above cases are true. */
7900 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7901 Return that assignment if so.
7903 We only handle the most common cases. */
7906 make_field_assignment (rtx x
)
7908 rtx dest
= SET_DEST (x
);
7909 rtx src
= SET_SRC (x
);
7914 unsigned HOST_WIDE_INT len
;
7916 enum machine_mode mode
;
7918 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7919 a clear of a one-bit field. We will have changed it to
7920 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7923 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7924 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7925 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7926 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7928 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7931 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7935 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7936 && subreg_lowpart_p (XEXP (src
, 0))
7937 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7938 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7939 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7940 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7941 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7942 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7944 assign
= make_extraction (VOIDmode
, dest
, 0,
7945 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7948 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7952 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7954 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7955 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7956 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7958 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7961 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7965 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7966 SRC is an AND with all bits of that field set, then we can discard
7968 if (GET_CODE (dest
) == ZERO_EXTRACT
7969 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
7970 && GET_CODE (src
) == AND
7971 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
7973 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
7974 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
7975 unsigned HOST_WIDE_INT ze_mask
;
7977 if (width
>= HOST_BITS_PER_WIDE_INT
)
7980 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
7982 /* Complete overlap. We can remove the source AND. */
7983 if ((and_mask
& ze_mask
) == ze_mask
)
7984 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
7986 /* Partial overlap. We can reduce the source AND. */
7987 if ((and_mask
& ze_mask
) != and_mask
)
7989 mode
= GET_MODE (src
);
7990 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
7991 gen_int_mode (and_mask
& ze_mask
, mode
));
7992 return gen_rtx_SET (VOIDmode
, dest
, src
);
7996 /* The other case we handle is assignments into a constant-position
7997 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7998 a mask that has all one bits except for a group of zero bits and
7999 OTHER is known to have zeros where C1 has ones, this is such an
8000 assignment. Compute the position and length from C1. Shift OTHER
8001 to the appropriate position, force it to the required mode, and
8002 make the extraction. Check for the AND in both operands. */
8004 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
8007 rhs
= expand_compound_operation (XEXP (src
, 0));
8008 lhs
= expand_compound_operation (XEXP (src
, 1));
8010 if (GET_CODE (rhs
) == AND
8011 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
8012 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
8013 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
8014 else if (GET_CODE (lhs
) == AND
8015 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
8016 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
8017 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
8021 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
8022 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
8023 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
8024 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
8027 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
8031 /* The mode to use for the source is the mode of the assignment, or of
8032 what is inside a possible STRICT_LOW_PART. */
8033 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
8034 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
8036 /* Shift OTHER right POS places and make it the source, restricting it
8037 to the proper length and mode. */
8039 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
8040 GET_MODE (src
), other
, pos
),
8042 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
8043 ? ~(unsigned HOST_WIDE_INT
) 0
8044 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
8047 /* If SRC is masked by an AND that does not make a difference in
8048 the value being stored, strip it. */
8049 if (GET_CODE (assign
) == ZERO_EXTRACT
8050 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
8051 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
8052 && GET_CODE (src
) == AND
8053 && GET_CODE (XEXP (src
, 1)) == CONST_INT
8054 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
8055 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
8056 src
= XEXP (src
, 0);
8058 return gen_rtx_SET (VOIDmode
, assign
, src
);
8061 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8065 apply_distributive_law (rtx x
)
8067 enum rtx_code code
= GET_CODE (x
);
8068 enum rtx_code inner_code
;
8069 rtx lhs
, rhs
, other
;
8072 /* Distributivity is not true for floating point as it can change the
8073 value. So we don't do it unless -funsafe-math-optimizations. */
8074 if (FLOAT_MODE_P (GET_MODE (x
))
8075 && ! flag_unsafe_math_optimizations
)
8078 /* The outer operation can only be one of the following: */
8079 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
8080 && code
!= PLUS
&& code
!= MINUS
)
8086 /* If either operand is a primitive we can't do anything, so get out
8088 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
8091 lhs
= expand_compound_operation (lhs
);
8092 rhs
= expand_compound_operation (rhs
);
8093 inner_code
= GET_CODE (lhs
);
8094 if (inner_code
!= GET_CODE (rhs
))
8097 /* See if the inner and outer operations distribute. */
8104 /* These all distribute except over PLUS. */
8105 if (code
== PLUS
|| code
== MINUS
)
8110 if (code
!= PLUS
&& code
!= MINUS
)
8115 /* This is also a multiply, so it distributes over everything. */
8119 /* Non-paradoxical SUBREGs distributes over all operations, provided
8120 the inner modes and byte offsets are the same, this is an extraction
8121 of a low-order part, we don't convert an fp operation to int or
8122 vice versa, and we would not be converting a single-word
8123 operation into a multi-word operation. The latter test is not
8124 required, but it prevents generating unneeded multi-word operations.
8125 Some of the previous tests are redundant given the latter test, but
8126 are retained because they are required for correctness.
8128 We produce the result slightly differently in this case. */
8130 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8131 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8132 || ! subreg_lowpart_p (lhs
)
8133 || (GET_MODE_CLASS (GET_MODE (lhs
))
8134 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8135 || (GET_MODE_SIZE (GET_MODE (lhs
))
8136 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8137 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
8140 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8141 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8142 return gen_lowpart (GET_MODE (x
), tem
);
8148 /* Set LHS and RHS to the inner operands (A and B in the example
8149 above) and set OTHER to the common operand (C in the example).
8150 There is only one way to do this unless the inner operation is
8152 if (COMMUTATIVE_ARITH_P (lhs
)
8153 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8154 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8155 else if (COMMUTATIVE_ARITH_P (lhs
)
8156 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8157 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8158 else if (COMMUTATIVE_ARITH_P (lhs
)
8159 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8160 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8161 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8162 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8166 /* Form the new inner operation, seeing if it simplifies first. */
8167 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8169 /* There is one exception to the general way of distributing:
8170 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8171 if (code
== XOR
&& inner_code
== IOR
)
8174 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8177 /* We may be able to continuing distributing the result, so call
8178 ourselves recursively on the inner operation before forming the
8179 outer operation, which we return. */
8180 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8181 apply_distributive_law (tem
), other
);
8184 /* See if X is of the form (* (+ A B) C), and if so convert to
8185 (+ (* A C) (* B C)) and try to simplify.
8187 Most of the time, this results in no change. However, if some of
8188 the operands are the same or inverses of each other, simplifications
8191 For example, (and (ior A B) (not B)) can occur as the result of
8192 expanding a bit field assignment. When we apply the distributive
8193 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8194 which then simplifies to (and (A (not B))).
8196 Note that no checks happen on the validity of applying the inverse
8197 distributive law. This is pointless since we can do it in the
8198 few places where this routine is called.
8200 N is the index of the term that is decomposed (the arithmetic operation,
8201 i.e. (+ A B) in the first example above). !N is the index of the term that
8202 is distributed, i.e. of C in the first example above. */
8204 distribute_and_simplify_rtx (rtx x
, int n
)
8206 enum machine_mode mode
;
8207 enum rtx_code outer_code
, inner_code
;
8208 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8210 decomposed
= XEXP (x
, n
);
8211 if (!ARITHMETIC_P (decomposed
))
8214 mode
= GET_MODE (x
);
8215 outer_code
= GET_CODE (x
);
8216 distributed
= XEXP (x
, !n
);
8218 inner_code
= GET_CODE (decomposed
);
8219 inner_op0
= XEXP (decomposed
, 0);
8220 inner_op1
= XEXP (decomposed
, 1);
8222 /* Special case (and (xor B C) (not A)), which is equivalent to
8223 (xor (ior A B) (ior A C)) */
8224 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8226 distributed
= XEXP (distributed
, 0);
8232 /* Distribute the second term. */
8233 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8234 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8238 /* Distribute the first term. */
8239 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8240 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8243 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8245 if (GET_CODE (tmp
) != outer_code
8246 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
8252 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8255 Return an equivalent form, if different from X. Otherwise, return X. If
8256 X is zero, we are to always construct the equivalent form. */
8259 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8260 unsigned HOST_WIDE_INT constop
)
8262 unsigned HOST_WIDE_INT nonzero
;
8265 /* Simplify VAROP knowing that we will be only looking at some of the
8268 Note by passing in CONSTOP, we guarantee that the bits not set in
8269 CONSTOP are not significant and will never be examined. We must
8270 ensure that is the case by explicitly masking out those bits
8271 before returning. */
8272 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8274 /* If VAROP is a CLOBBER, we will fail so return it. */
8275 if (GET_CODE (varop
) == CLOBBER
)
8278 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8279 to VAROP and return the new constant. */
8280 if (GET_CODE (varop
) == CONST_INT
)
8281 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8283 /* See what bits may be nonzero in VAROP. Unlike the general case of
8284 a call to nonzero_bits, here we don't care about bits outside
8287 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8289 /* Turn off all bits in the constant that are known to already be zero.
8290 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8291 which is tested below. */
8295 /* If we don't have any bits left, return zero. */
8299 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8300 a power of two, we can replace this with an ASHIFT. */
8301 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8302 && (i
= exact_log2 (constop
)) >= 0)
8303 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8305 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8306 or XOR, then try to apply the distributive law. This may eliminate
8307 operations if either branch can be simplified because of the AND.
8308 It may also make some cases more complex, but those cases probably
8309 won't match a pattern either with or without this. */
8311 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8315 apply_distributive_law
8316 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8317 simplify_and_const_int (NULL_RTX
,
8321 simplify_and_const_int (NULL_RTX
,
8326 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8327 the AND and see if one of the operands simplifies to zero. If so, we
8328 may eliminate it. */
8330 if (GET_CODE (varop
) == PLUS
8331 && exact_log2 (constop
+ 1) >= 0)
8335 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8336 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8337 if (o0
== const0_rtx
)
8339 if (o1
== const0_rtx
)
8343 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8344 if we already had one (just check for the simplest cases). */
8345 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8346 && GET_MODE (XEXP (x
, 0)) == mode
8347 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8348 varop
= XEXP (x
, 0);
8350 varop
= gen_lowpart (mode
, varop
);
8352 /* If we can't make the SUBREG, try to return what we were given. */
8353 if (GET_CODE (varop
) == CLOBBER
)
8354 return x
? x
: varop
;
8356 /* If we are only masking insignificant bits, return VAROP. */
8357 if (constop
== nonzero
)
8361 /* Otherwise, return an AND. */
8362 constop
= trunc_int_for_mode (constop
, mode
);
8363 /* See how much, if any, of X we can use. */
8364 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8365 x
= simplify_gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8369 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8370 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8371 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8373 SUBST (XEXP (x
, 0), varop
);
8380 /* Given a REG, X, compute which bits in X can be nonzero.
8381 We don't care about bits outside of those defined in MODE.
8383 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8384 a shift, AND, or zero_extract, we can do better. */
8387 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8388 rtx known_x ATTRIBUTE_UNUSED
,
8389 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8390 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8391 unsigned HOST_WIDE_INT
*nonzero
)
8395 /* If X is a register whose nonzero bits value is current, use it.
8396 Otherwise, if X is a register whose value we can find, use that
8397 value. Otherwise, use the previously-computed global nonzero bits
8398 for this register. */
8400 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8401 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8402 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8403 && GET_MODE_CLASS (mode
) == MODE_INT
))
8404 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8405 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8406 && REG_N_SETS (REGNO (x
)) == 1
8407 && ! REGNO_REG_SET_P
8408 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8410 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8412 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8416 tem
= get_last_value (x
);
8420 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8421 /* If X is narrower than MODE and TEM is a non-negative
8422 constant that would appear negative in the mode of X,
8423 sign-extend it for use in reg_nonzero_bits because some
8424 machines (maybe most) will actually do the sign-extension
8425 and this is the conservative approach.
8427 ??? For 2.5, try to tighten up the MD files in this regard
8428 instead of this kludge. */
8430 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8431 && GET_CODE (tem
) == CONST_INT
8433 && 0 != (INTVAL (tem
)
8434 & ((HOST_WIDE_INT
) 1
8435 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8436 tem
= GEN_INT (INTVAL (tem
)
8437 | ((HOST_WIDE_INT
) (-1)
8438 << GET_MODE_BITSIZE (GET_MODE (x
))));
8442 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8444 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8446 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8447 /* We don't know anything about the upper bits. */
8448 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8455 /* Return the number of bits at the high-order end of X that are known to
8456 be equal to the sign bit. X will be used in mode MODE; if MODE is
8457 VOIDmode, X will be used in its own mode. The returned value will always
8458 be between 1 and the number of bits in MODE. */
8461 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8462 rtx known_x ATTRIBUTE_UNUSED
,
8463 enum machine_mode known_mode
8465 unsigned int known_ret ATTRIBUTE_UNUSED
,
8466 unsigned int *result
)
8470 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8471 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8472 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8473 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8474 && REG_N_SETS (REGNO (x
)) == 1
8475 && ! REGNO_REG_SET_P
8476 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8478 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8480 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8484 tem
= get_last_value (x
);
8488 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8489 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8490 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8495 /* Return the number of "extended" bits there are in X, when interpreted
8496 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8497 unsigned quantities, this is the number of high-order zero bits.
8498 For signed quantities, this is the number of copies of the sign bit
8499 minus 1. In both case, this function returns the number of "spare"
8500 bits. For example, if two quantities for which this function returns
8501 at least 1 are added, the addition is known not to overflow.
8503 This function will always return 0 unless called during combine, which
8504 implies that it must be called from a define_split. */
8507 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8509 if (nonzero_sign_valid
== 0)
8513 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8514 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8515 - floor_log2 (nonzero_bits (x
, mode
)))
8517 : num_sign_bit_copies (x
, mode
) - 1);
8520 /* This function is called from `simplify_shift_const' to merge two
8521 outer operations. Specifically, we have already found that we need
8522 to perform operation *POP0 with constant *PCONST0 at the outermost
8523 position. We would now like to also perform OP1 with constant CONST1
8524 (with *POP0 being done last).
8526 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8527 the resulting operation. *PCOMP_P is set to 1 if we would need to
8528 complement the innermost operand, otherwise it is unchanged.
8530 MODE is the mode in which the operation will be done. No bits outside
8531 the width of this mode matter. It is assumed that the width of this mode
8532 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8534 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8535 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8536 result is simply *PCONST0.
8538 If the resulting operation cannot be expressed as one operation, we
8539 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8542 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8544 enum rtx_code op0
= *pop0
;
8545 HOST_WIDE_INT const0
= *pconst0
;
8547 const0
&= GET_MODE_MASK (mode
);
8548 const1
&= GET_MODE_MASK (mode
);
8550 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8554 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8557 if (op1
== UNKNOWN
|| op0
== SET
)
8560 else if (op0
== UNKNOWN
)
8561 op0
= op1
, const0
= const1
;
8563 else if (op0
== op1
)
8587 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8588 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8591 /* If the two constants aren't the same, we can't do anything. The
8592 remaining six cases can all be done. */
8593 else if (const0
!= const1
)
8601 /* (a & b) | b == b */
8603 else /* op1 == XOR */
8604 /* (a ^ b) | b == a | b */
8610 /* (a & b) ^ b == (~a) & b */
8611 op0
= AND
, *pcomp_p
= 1;
8612 else /* op1 == IOR */
8613 /* (a | b) ^ b == a & ~b */
8614 op0
= AND
, const0
= ~const0
;
8619 /* (a | b) & b == b */
8621 else /* op1 == XOR */
8622 /* (a ^ b) & b) == (~a) & b */
8629 /* Check for NO-OP cases. */
8630 const0
&= GET_MODE_MASK (mode
);
8632 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8634 else if (const0
== 0 && op0
== AND
)
8636 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8640 /* ??? Slightly redundant with the above mask, but not entirely.
8641 Moving this above means we'd have to sign-extend the mode mask
8642 for the final test. */
8643 const0
= trunc_int_for_mode (const0
, mode
);
8651 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8652 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8653 that we started with.
8655 The shift is normally computed in the widest mode we find in VAROP, as
8656 long as it isn't a different number of words than RESULT_MODE. Exceptions
8657 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8660 simplify_shift_const (rtx x
, enum rtx_code code
,
8661 enum machine_mode result_mode
, rtx varop
,
8664 enum rtx_code orig_code
= code
;
8667 enum machine_mode mode
= result_mode
;
8668 enum machine_mode shift_mode
, tmode
;
8669 unsigned int mode_words
8670 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8671 /* We form (outer_op (code varop count) (outer_const)). */
8672 enum rtx_code outer_op
= UNKNOWN
;
8673 HOST_WIDE_INT outer_const
= 0;
8675 int complement_p
= 0;
8678 /* Make sure and truncate the "natural" shift on the way in. We don't
8679 want to do this inside the loop as it makes it more difficult to
8681 if (SHIFT_COUNT_TRUNCATED
)
8682 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8684 /* If we were given an invalid count, don't do anything except exactly
8685 what was requested. */
8687 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8692 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8697 /* Unless one of the branches of the `if' in this loop does a `continue',
8698 we will `break' the loop after the `if'. */
8702 /* If we have an operand of (clobber (const_int 0)), just return that
8704 if (GET_CODE (varop
) == CLOBBER
)
8707 /* If we discovered we had to complement VAROP, leave. Making a NOT
8708 here would cause an infinite loop. */
8712 /* Convert ROTATERT to ROTATE. */
8713 if (code
== ROTATERT
)
8715 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8717 if (VECTOR_MODE_P (result_mode
))
8718 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8720 count
= bitsize
- count
;
8723 /* We need to determine what mode we will do the shift in. If the
8724 shift is a right shift or a ROTATE, we must always do it in the mode
8725 it was originally done in. Otherwise, we can do it in MODE, the
8726 widest mode encountered. */
8728 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8729 ? result_mode
: mode
);
8731 /* Handle cases where the count is greater than the size of the mode
8732 minus 1. For ASHIFT, use the size minus one as the count (this can
8733 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8734 take the count modulo the size. For other shifts, the result is
8737 Since these shifts are being produced by the compiler by combining
8738 multiple operations, each of which are defined, we know what the
8739 result is supposed to be. */
8741 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8743 if (code
== ASHIFTRT
)
8744 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8745 else if (code
== ROTATE
|| code
== ROTATERT
)
8746 count
%= GET_MODE_BITSIZE (shift_mode
);
8749 /* We can't simply return zero because there may be an
8757 /* An arithmetic right shift of a quantity known to be -1 or 0
8759 if (code
== ASHIFTRT
8760 && (num_sign_bit_copies (varop
, shift_mode
)
8761 == GET_MODE_BITSIZE (shift_mode
)))
8767 /* If we are doing an arithmetic right shift and discarding all but
8768 the sign bit copies, this is equivalent to doing a shift by the
8769 bitsize minus one. Convert it into that shift because it will often
8770 allow other simplifications. */
8772 if (code
== ASHIFTRT
8773 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8774 >= GET_MODE_BITSIZE (shift_mode
)))
8775 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8777 /* We simplify the tests below and elsewhere by converting
8778 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8779 `make_compound_operation' will convert it to an ASHIFTRT for
8780 those machines (such as VAX) that don't have an LSHIFTRT. */
8781 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8783 && ((nonzero_bits (varop
, shift_mode
)
8784 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8788 if (code
== LSHIFTRT
8789 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8790 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8793 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8794 && !((nonzero_bits (varop
, shift_mode
) << count
)
8795 & GET_MODE_MASK (shift_mode
)))
8798 switch (GET_CODE (varop
))
8804 new = expand_compound_operation (varop
);
8813 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8814 minus the width of a smaller mode, we can do this with a
8815 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8816 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8817 && ! mode_dependent_address_p (XEXP (varop
, 0))
8818 && ! MEM_VOLATILE_P (varop
)
8819 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8820 MODE_INT
, 1)) != BLKmode
)
8822 new = adjust_address_nv (varop
, tmode
,
8823 BYTES_BIG_ENDIAN
? 0
8824 : count
/ BITS_PER_UNIT
);
8826 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8827 : ZERO_EXTEND
, mode
, new);
8834 /* Similar to the case above, except that we can only do this if
8835 the resulting mode is the same as that of the underlying
8836 MEM and adjust the address depending on the *bits* endianness
8837 because of the way that bit-field extract insns are defined. */
8838 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8839 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8840 MODE_INT
, 1)) != BLKmode
8841 && tmode
== GET_MODE (XEXP (varop
, 0)))
8843 if (BITS_BIG_ENDIAN
)
8844 new = XEXP (varop
, 0);
8847 new = copy_rtx (XEXP (varop
, 0));
8848 SUBST (XEXP (new, 0),
8849 plus_constant (XEXP (new, 0),
8850 count
/ BITS_PER_UNIT
));
8853 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8854 : ZERO_EXTEND
, mode
, new);
8861 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8862 the same number of words as what we've seen so far. Then store
8863 the widest mode in MODE. */
8864 if (subreg_lowpart_p (varop
)
8865 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8866 > GET_MODE_SIZE (GET_MODE (varop
)))
8867 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8868 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8871 varop
= SUBREG_REG (varop
);
8872 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8873 mode
= GET_MODE (varop
);
8879 /* Some machines use MULT instead of ASHIFT because MULT
8880 is cheaper. But it is still better on those machines to
8881 merge two shifts into one. */
8882 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8883 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8886 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
8888 GEN_INT (exact_log2 (
8889 INTVAL (XEXP (varop
, 1)))));
8895 /* Similar, for when divides are cheaper. */
8896 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8897 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8900 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
8902 GEN_INT (exact_log2 (
8903 INTVAL (XEXP (varop
, 1)))));
8909 /* If we are extracting just the sign bit of an arithmetic
8910 right shift, that shift is not needed. However, the sign
8911 bit of a wider mode may be different from what would be
8912 interpreted as the sign bit in a narrower mode, so, if
8913 the result is narrower, don't discard the shift. */
8914 if (code
== LSHIFTRT
8915 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8916 && (GET_MODE_BITSIZE (result_mode
)
8917 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8919 varop
= XEXP (varop
, 0);
8923 /* ... fall through ... */
8928 /* Here we have two nested shifts. The result is usually the
8929 AND of a new shift with a mask. We compute the result below. */
8930 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8931 && INTVAL (XEXP (varop
, 1)) >= 0
8932 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8933 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8934 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8936 enum rtx_code first_code
= GET_CODE (varop
);
8937 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8938 unsigned HOST_WIDE_INT mask
;
8941 /* We have one common special case. We can't do any merging if
8942 the inner code is an ASHIFTRT of a smaller mode. However, if
8943 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8944 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8945 we can convert it to
8946 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8947 This simplifies certain SIGN_EXTEND operations. */
8948 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8949 && count
== (unsigned int)
8950 (GET_MODE_BITSIZE (result_mode
)
8951 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8953 /* C3 has the low-order C1 bits zero. */
8955 mask
= (GET_MODE_MASK (mode
)
8956 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8958 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8959 XEXP (varop
, 0), mask
);
8960 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8962 count
= first_count
;
8967 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8968 than C1 high-order bits equal to the sign bit, we can convert
8969 this to either an ASHIFT or an ASHIFTRT depending on the
8972 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8974 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8975 && GET_MODE (varop
) == shift_mode
8976 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8979 varop
= XEXP (varop
, 0);
8981 signed_count
= count
- first_count
;
8982 if (signed_count
< 0)
8983 count
= -signed_count
, code
= ASHIFT
;
8985 count
= signed_count
;
8990 /* There are some cases we can't do. If CODE is ASHIFTRT,
8991 we can only do this if FIRST_CODE is also ASHIFTRT.
8993 We can't do the case when CODE is ROTATE and FIRST_CODE is
8996 If the mode of this shift is not the mode of the outer shift,
8997 we can't do this if either shift is a right shift or ROTATE.
8999 Finally, we can't do any of these if the mode is too wide
9000 unless the codes are the same.
9002 Handle the case where the shift codes are the same
9005 if (code
== first_code
)
9007 if (GET_MODE (varop
) != result_mode
9008 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9012 count
+= first_count
;
9013 varop
= XEXP (varop
, 0);
9017 if (code
== ASHIFTRT
9018 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9019 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9020 || (GET_MODE (varop
) != result_mode
9021 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9022 || first_code
== ROTATE
9023 || code
== ROTATE
)))
9026 /* To compute the mask to apply after the shift, shift the
9027 nonzero bits of the inner shift the same way the
9028 outer shift will. */
9030 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9033 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9036 /* Give up if we can't compute an outer operation to use. */
9038 || GET_CODE (mask_rtx
) != CONST_INT
9039 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9041 result_mode
, &complement_p
))
9044 /* If the shifts are in the same direction, we add the
9045 counts. Otherwise, we subtract them. */
9046 signed_count
= count
;
9047 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9048 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9049 signed_count
+= first_count
;
9051 signed_count
-= first_count
;
9053 /* If COUNT is positive, the new shift is usually CODE,
9054 except for the two exceptions below, in which case it is
9055 FIRST_CODE. If the count is negative, FIRST_CODE should
9057 if (signed_count
> 0
9058 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9059 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9060 code
= first_code
, count
= signed_count
;
9061 else if (signed_count
< 0)
9062 code
= first_code
, count
= -signed_count
;
9064 count
= signed_count
;
9066 varop
= XEXP (varop
, 0);
9070 /* If we have (A << B << C) for any shift, we can convert this to
9071 (A << C << B). This wins if A is a constant. Only try this if
9072 B is not a constant. */
9074 else if (GET_CODE (varop
) == code
9075 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9077 = simplify_binary_operation (code
, mode
,
9081 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9088 /* Make this fit the case below. */
9089 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9090 GEN_INT (GET_MODE_MASK (mode
)));
9096 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9097 with C the size of VAROP - 1 and the shift is logical if
9098 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9099 we have an (le X 0) operation. If we have an arithmetic shift
9100 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9101 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9103 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9104 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9105 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9106 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9107 && count
== (unsigned int)
9108 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9109 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9112 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9115 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9116 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9121 /* If we have (shift (logical)), move the logical to the outside
9122 to allow it to possibly combine with another logical and the
9123 shift to combine with another shift. This also canonicalizes to
9124 what a ZERO_EXTRACT looks like. Also, some machines have
9125 (and (shift)) insns. */
9127 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9128 /* We can't do this if we have (ashiftrt (xor)) and the
9129 constant has its sign bit set in shift_mode. */
9130 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9131 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9133 && (new = simplify_binary_operation (code
, result_mode
,
9135 GEN_INT (count
))) != 0
9136 && GET_CODE (new) == CONST_INT
9137 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9138 INTVAL (new), result_mode
, &complement_p
))
9140 varop
= XEXP (varop
, 0);
9144 /* If we can't do that, try to simplify the shift in each arm of the
9145 logical expression, make a new logical expression, and apply
9146 the inverse distributive law. This also can't be done
9147 for some (ashiftrt (xor)). */
9148 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9149 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9150 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9153 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9154 XEXP (varop
, 0), count
);
9155 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9156 XEXP (varop
, 1), count
);
9158 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9160 varop
= apply_distributive_law (varop
);
9168 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9169 says that the sign bit can be tested, FOO has mode MODE, C is
9170 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9171 that may be nonzero. */
9172 if (code
== LSHIFTRT
9173 && XEXP (varop
, 1) == const0_rtx
9174 && GET_MODE (XEXP (varop
, 0)) == result_mode
9175 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9176 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9177 && ((STORE_FLAG_VALUE
9178 & ((HOST_WIDE_INT
) 1
9179 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9180 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9181 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9182 (HOST_WIDE_INT
) 1, result_mode
,
9185 varop
= XEXP (varop
, 0);
9192 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9193 than the number of bits in the mode is equivalent to A. */
9194 if (code
== LSHIFTRT
9195 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9196 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9198 varop
= XEXP (varop
, 0);
9203 /* NEG commutes with ASHIFT since it is multiplication. Move the
9204 NEG outside to allow shifts to combine. */
9206 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9207 (HOST_WIDE_INT
) 0, result_mode
,
9210 varop
= XEXP (varop
, 0);
9216 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9217 is one less than the number of bits in the mode is
9218 equivalent to (xor A 1). */
9219 if (code
== LSHIFTRT
9220 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9221 && XEXP (varop
, 1) == constm1_rtx
9222 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9223 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9224 (HOST_WIDE_INT
) 1, result_mode
,
9228 varop
= XEXP (varop
, 0);
9232 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9233 that might be nonzero in BAR are those being shifted out and those
9234 bits are known zero in FOO, we can replace the PLUS with FOO.
9235 Similarly in the other operand order. This code occurs when
9236 we are computing the size of a variable-size array. */
9238 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9239 && count
< HOST_BITS_PER_WIDE_INT
9240 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9241 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9242 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9244 varop
= XEXP (varop
, 0);
9247 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9248 && count
< HOST_BITS_PER_WIDE_INT
9249 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9250 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9252 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9253 & nonzero_bits (XEXP (varop
, 1),
9256 varop
= XEXP (varop
, 1);
9260 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9262 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9263 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9265 GEN_INT (count
))) != 0
9266 && GET_CODE (new) == CONST_INT
9267 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9268 INTVAL (new), result_mode
, &complement_p
))
9270 varop
= XEXP (varop
, 0);
9274 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9275 signbit', and attempt to change the PLUS to an XOR and move it to
9276 the outer operation as is done above in the AND/IOR/XOR case
9277 leg for shift(logical). See details in logical handling above
9278 for reasoning in doing so. */
9279 if (code
== LSHIFTRT
9280 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9281 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9282 && (new = simplify_binary_operation (code
, result_mode
,
9284 GEN_INT (count
))) != 0
9285 && GET_CODE (new) == CONST_INT
9286 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9287 INTVAL (new), result_mode
, &complement_p
))
9289 varop
= XEXP (varop
, 0);
9296 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9297 with C the size of VAROP - 1 and the shift is logical if
9298 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9299 we have a (gt X 0) operation. If the shift is arithmetic with
9300 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9301 we have a (neg (gt X 0)) operation. */
9303 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9304 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9305 && count
== (unsigned int)
9306 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9307 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9308 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9309 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9311 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9314 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9317 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9318 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9325 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9326 if the truncate does not affect the value. */
9327 if (code
== LSHIFTRT
9328 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9329 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9330 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9331 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9332 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9334 rtx varop_inner
= XEXP (varop
, 0);
9337 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9338 XEXP (varop_inner
, 0),
9340 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9341 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9354 /* We need to determine what mode to do the shift in. If the shift is
9355 a right shift or ROTATE, we must always do it in the mode it was
9356 originally done in. Otherwise, we can do it in MODE, the widest mode
9357 encountered. The code we care about is that of the shift that will
9358 actually be done, not the shift that was originally requested. */
9360 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9361 ? result_mode
: mode
);
9363 /* We have now finished analyzing the shift. The result should be
9364 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9365 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9366 to the result of the shift. OUTER_CONST is the relevant constant,
9367 but we must turn off all bits turned off in the shift.
9369 If we were passed a value for X, see if we can use any pieces of
9370 it. If not, make new rtx. */
9372 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9373 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9374 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9375 const_rtx
= XEXP (x
, 1);
9377 const_rtx
= GEN_INT (count
);
9379 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9380 && GET_MODE (XEXP (x
, 0)) == shift_mode
9381 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9382 varop
= XEXP (x
, 0);
9383 else if (GET_MODE (varop
) != shift_mode
)
9384 varop
= gen_lowpart (shift_mode
, varop
);
9386 /* If we can't make the SUBREG, try to return what we were given. */
9387 if (GET_CODE (varop
) == CLOBBER
)
9388 return x
? x
: varop
;
9390 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9394 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9396 /* If we have an outer operation and we just made a shift, it is
9397 possible that we could have simplified the shift were it not
9398 for the outer operation. So try to do the simplification
9401 if (outer_op
!= UNKNOWN
&& GET_CODE (x
) == code
9402 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9403 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9404 INTVAL (XEXP (x
, 1)));
9406 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9407 turn off all the bits that the shift would have turned off. */
9408 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9409 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9410 GET_MODE_MASK (result_mode
) >> orig_count
);
9412 /* Do the remainder of the processing in RESULT_MODE. */
9413 x
= gen_lowpart (result_mode
, x
);
9415 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9418 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9420 if (outer_op
!= UNKNOWN
)
9422 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9423 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9425 if (outer_op
== AND
)
9426 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9427 else if (outer_op
== SET
)
9428 /* This means that we have determined that the result is
9429 equivalent to a constant. This should be rare. */
9430 x
= GEN_INT (outer_const
);
9431 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9432 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9434 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9435 GEN_INT (outer_const
));
9441 /* Like recog, but we receive the address of a pointer to a new pattern.
9442 We try to match the rtx that the pointer points to.
9443 If that fails, we may try to modify or replace the pattern,
9444 storing the replacement into the same pointer object.
9446 Modifications include deletion or addition of CLOBBERs.
9448 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9449 the CLOBBERs are placed.
9451 The value is the final insn code from the pattern ultimately matched,
9455 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9458 int insn_code_number
;
9459 int num_clobbers_to_add
= 0;
9462 rtx old_notes
, old_pat
;
9464 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9465 we use to indicate that something didn't match. If we find such a
9466 thing, force rejection. */
9467 if (GET_CODE (pat
) == PARALLEL
)
9468 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9469 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9470 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9473 old_pat
= PATTERN (insn
);
9474 old_notes
= REG_NOTES (insn
);
9475 PATTERN (insn
) = pat
;
9476 REG_NOTES (insn
) = 0;
9478 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9480 /* If it isn't, there is the possibility that we previously had an insn
9481 that clobbered some register as a side effect, but the combined
9482 insn doesn't need to do that. So try once more without the clobbers
9483 unless this represents an ASM insn. */
9485 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9486 && GET_CODE (pat
) == PARALLEL
)
9490 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9491 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9494 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9498 SUBST_INT (XVECLEN (pat
, 0), pos
);
9501 pat
= XVECEXP (pat
, 0, 0);
9503 PATTERN (insn
) = pat
;
9504 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9506 PATTERN (insn
) = old_pat
;
9507 REG_NOTES (insn
) = old_notes
;
9509 /* Recognize all noop sets, these will be killed by followup pass. */
9510 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9511 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9513 /* If we had any clobbers to add, make a new pattern than contains
9514 them. Then check to make sure that all of them are dead. */
9515 if (num_clobbers_to_add
)
9517 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9518 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9520 + num_clobbers_to_add
)
9521 : num_clobbers_to_add
+ 1));
9523 if (GET_CODE (pat
) == PARALLEL
)
9524 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9525 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9527 XVECEXP (newpat
, 0, 0) = pat
;
9529 add_clobbers (newpat
, insn_code_number
);
9531 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9532 i
< XVECLEN (newpat
, 0); i
++)
9534 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9535 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9537 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9538 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9546 return insn_code_number
;
9549 /* Like gen_lowpart_general but for use by combine. In combine it
9550 is not possible to create any new pseudoregs. However, it is
9551 safe to create invalid memory addresses, because combine will
9552 try to recognize them and all they will do is make the combine
9555 If for some reason this cannot do its job, an rtx
9556 (clobber (const_int 0)) is returned.
9557 An insn containing that will not be recognized. */
9560 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9562 enum machine_mode imode
= GET_MODE (x
);
9563 unsigned int osize
= GET_MODE_SIZE (omode
);
9564 unsigned int isize
= GET_MODE_SIZE (imode
);
9570 /* Return identity if this is a CONST or symbolic reference. */
9572 && (GET_CODE (x
) == CONST
9573 || GET_CODE (x
) == SYMBOL_REF
9574 || GET_CODE (x
) == LABEL_REF
))
9577 /* We can only support MODE being wider than a word if X is a
9578 constant integer or has a mode the same size. */
9579 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9580 && ! ((imode
== VOIDmode
9581 && (GET_CODE (x
) == CONST_INT
9582 || GET_CODE (x
) == CONST_DOUBLE
))
9586 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9587 won't know what to do. So we will strip off the SUBREG here and
9588 process normally. */
9589 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9593 /* For use in case we fall down into the address adjustments
9594 further below, we need to adjust the known mode and size of
9595 x; imode and isize, since we just adjusted x. */
9596 imode
= GET_MODE (x
);
9601 isize
= GET_MODE_SIZE (imode
);
9604 result
= gen_lowpart_common (omode
, x
);
9606 #ifdef CANNOT_CHANGE_MODE_CLASS
9607 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9608 record_subregs_of_mode (result
);
9618 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9620 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9623 /* If we want to refer to something bigger than the original memref,
9624 generate a paradoxical subreg instead. That will force a reload
9625 of the original memref X. */
9627 return gen_rtx_SUBREG (omode
, x
, 0);
9629 if (WORDS_BIG_ENDIAN
)
9630 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9632 /* Adjust the address so that the address-after-the-data is
9634 if (BYTES_BIG_ENDIAN
)
9635 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9637 return adjust_address_nv (x
, omode
, offset
);
9640 /* If X is a comparison operator, rewrite it in a new mode. This
9641 probably won't match, but may allow further simplifications. */
9642 else if (COMPARISON_P (x
))
9643 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9645 /* If we couldn't simplify X any other way, just enclose it in a
9646 SUBREG. Normally, this SUBREG won't match, but some patterns may
9647 include an explicit SUBREG or we may simplify it further in combine. */
9653 offset
= subreg_lowpart_offset (omode
, imode
);
9654 if (imode
== VOIDmode
)
9656 imode
= int_mode_for_mode (omode
);
9657 x
= gen_lowpart_common (imode
, x
);
9661 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9667 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9670 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9671 comparison code that will be tested.
9673 The result is a possibly different comparison code to use. *POP0 and
9674 *POP1 may be updated.
9676 It is possible that we might detect that a comparison is either always
9677 true or always false. However, we do not perform general constant
9678 folding in combine, so this knowledge isn't useful. Such tautologies
9679 should have been detected earlier. Hence we ignore all such cases. */
9681 static enum rtx_code
9682 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9688 enum machine_mode mode
, tmode
;
9690 /* Try a few ways of applying the same transformation to both operands. */
9693 #ifndef WORD_REGISTER_OPERATIONS
9694 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9695 so check specially. */
9696 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9697 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9698 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9699 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9700 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9701 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9702 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9703 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9704 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9705 && XEXP (op0
, 1) == XEXP (op1
, 1)
9706 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9707 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9708 && (INTVAL (XEXP (op0
, 1))
9709 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9711 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9713 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9714 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9718 /* If both operands are the same constant shift, see if we can ignore the
9719 shift. We can if the shift is a rotate or if the bits shifted out of
9720 this shift are known to be zero for both inputs and if the type of
9721 comparison is compatible with the shift. */
9722 if (GET_CODE (op0
) == GET_CODE (op1
)
9723 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9724 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9725 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9726 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9727 || (GET_CODE (op0
) == ASHIFTRT
9728 && (code
!= GTU
&& code
!= LTU
9729 && code
!= GEU
&& code
!= LEU
)))
9730 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9731 && INTVAL (XEXP (op0
, 1)) >= 0
9732 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9733 && XEXP (op0
, 1) == XEXP (op1
, 1))
9735 enum machine_mode mode
= GET_MODE (op0
);
9736 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9737 int shift_count
= INTVAL (XEXP (op0
, 1));
9739 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9740 mask
&= (mask
>> shift_count
) << shift_count
;
9741 else if (GET_CODE (op0
) == ASHIFT
)
9742 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9744 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9745 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9746 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9751 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9752 SUBREGs are of the same mode, and, in both cases, the AND would
9753 be redundant if the comparison was done in the narrower mode,
9754 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9755 and the operand's possibly nonzero bits are 0xffffff01; in that case
9756 if we only care about QImode, we don't need the AND). This case
9757 occurs if the output mode of an scc insn is not SImode and
9758 STORE_FLAG_VALUE == 1 (e.g., the 386).
9760 Similarly, check for a case where the AND's are ZERO_EXTEND
9761 operations from some narrower mode even though a SUBREG is not
9764 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9765 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9766 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9768 rtx inner_op0
= XEXP (op0
, 0);
9769 rtx inner_op1
= XEXP (op1
, 0);
9770 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9771 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9774 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9775 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9776 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9777 && (GET_MODE (SUBREG_REG (inner_op0
))
9778 == GET_MODE (SUBREG_REG (inner_op1
)))
9779 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9780 <= HOST_BITS_PER_WIDE_INT
)
9781 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9782 GET_MODE (SUBREG_REG (inner_op0
)))))
9783 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9784 GET_MODE (SUBREG_REG (inner_op1
))))))
9786 op0
= SUBREG_REG (inner_op0
);
9787 op1
= SUBREG_REG (inner_op1
);
9789 /* The resulting comparison is always unsigned since we masked
9790 off the original sign bit. */
9791 code
= unsigned_condition (code
);
9797 for (tmode
= GET_CLASS_NARROWEST_MODE
9798 (GET_MODE_CLASS (GET_MODE (op0
)));
9799 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9800 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9802 op0
= gen_lowpart (tmode
, inner_op0
);
9803 op1
= gen_lowpart (tmode
, inner_op1
);
9804 code
= unsigned_condition (code
);
9813 /* If both operands are NOT, we can strip off the outer operation
9814 and adjust the comparison code for swapped operands; similarly for
9815 NEG, except that this must be an equality comparison. */
9816 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9817 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9818 && (code
== EQ
|| code
== NE
)))
9819 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9825 /* If the first operand is a constant, swap the operands and adjust the
9826 comparison code appropriately, but don't do this if the second operand
9827 is already a constant integer. */
9828 if (swap_commutative_operands_p (op0
, op1
))
9830 tem
= op0
, op0
= op1
, op1
= tem
;
9831 code
= swap_condition (code
);
9834 /* We now enter a loop during which we will try to simplify the comparison.
9835 For the most part, we only are concerned with comparisons with zero,
9836 but some things may really be comparisons with zero but not start
9837 out looking that way. */
9839 while (GET_CODE (op1
) == CONST_INT
)
9841 enum machine_mode mode
= GET_MODE (op0
);
9842 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9843 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9844 int equality_comparison_p
;
9845 int sign_bit_comparison_p
;
9846 int unsigned_comparison_p
;
9847 HOST_WIDE_INT const_op
;
9849 /* We only want to handle integral modes. This catches VOIDmode,
9850 CCmode, and the floating-point modes. An exception is that we
9851 can handle VOIDmode if OP0 is a COMPARE or a comparison
9854 if (GET_MODE_CLASS (mode
) != MODE_INT
9855 && ! (mode
== VOIDmode
9856 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9859 /* Get the constant we are comparing against and turn off all bits
9860 not on in our mode. */
9861 const_op
= INTVAL (op1
);
9862 if (mode
!= VOIDmode
)
9863 const_op
= trunc_int_for_mode (const_op
, mode
);
9864 op1
= GEN_INT (const_op
);
9866 /* If we are comparing against a constant power of two and the value
9867 being compared can only have that single bit nonzero (e.g., it was
9868 `and'ed with that bit), we can replace this with a comparison
9871 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9872 || code
== LT
|| code
== LTU
)
9873 && mode_width
<= HOST_BITS_PER_WIDE_INT
9874 && exact_log2 (const_op
) >= 0
9875 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9877 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9878 op1
= const0_rtx
, const_op
= 0;
9881 /* Similarly, if we are comparing a value known to be either -1 or
9882 0 with -1, change it to the opposite comparison against zero. */
9885 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9886 || code
== GEU
|| code
== LTU
)
9887 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9889 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9890 op1
= const0_rtx
, const_op
= 0;
9893 /* Do some canonicalizations based on the comparison code. We prefer
9894 comparisons against zero and then prefer equality comparisons.
9895 If we can reduce the size of a constant, we will do that too. */
9900 /* < C is equivalent to <= (C - 1) */
9904 op1
= GEN_INT (const_op
);
9906 /* ... fall through to LE case below. */
9912 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9916 op1
= GEN_INT (const_op
);
9920 /* If we are doing a <= 0 comparison on a value known to have
9921 a zero sign bit, we can replace this with == 0. */
9922 else if (const_op
== 0
9923 && mode_width
<= HOST_BITS_PER_WIDE_INT
9924 && (nonzero_bits (op0
, mode
)
9925 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9930 /* >= C is equivalent to > (C - 1). */
9934 op1
= GEN_INT (const_op
);
9936 /* ... fall through to GT below. */
9942 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9946 op1
= GEN_INT (const_op
);
9950 /* If we are doing a > 0 comparison on a value known to have
9951 a zero sign bit, we can replace this with != 0. */
9952 else if (const_op
== 0
9953 && mode_width
<= HOST_BITS_PER_WIDE_INT
9954 && (nonzero_bits (op0
, mode
)
9955 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9960 /* < C is equivalent to <= (C - 1). */
9964 op1
= GEN_INT (const_op
);
9966 /* ... fall through ... */
9969 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9970 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9971 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9973 const_op
= 0, op1
= const0_rtx
;
9981 /* unsigned <= 0 is equivalent to == 0 */
9985 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9986 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9987 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9989 const_op
= 0, op1
= const0_rtx
;
9995 /* >= C is equivalent to > (C - 1). */
9999 op1
= GEN_INT (const_op
);
10001 /* ... fall through ... */
10004 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10005 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10006 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10008 const_op
= 0, op1
= const0_rtx
;
10016 /* unsigned > 0 is equivalent to != 0 */
10020 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10021 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10022 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10024 const_op
= 0, op1
= const0_rtx
;
10033 /* Compute some predicates to simplify code below. */
10035 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10036 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10037 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10040 /* If this is a sign bit comparison and we can do arithmetic in
10041 MODE, say that we will only be needing the sign bit of OP0. */
10042 if (sign_bit_comparison_p
10043 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10044 op0
= force_to_mode (op0
, mode
,
10046 << (GET_MODE_BITSIZE (mode
) - 1)),
10049 /* Now try cases based on the opcode of OP0. If none of the cases
10050 does a "continue", we exit this loop immediately after the
10053 switch (GET_CODE (op0
))
10056 /* If we are extracting a single bit from a variable position in
10057 a constant that has only a single bit set and are comparing it
10058 with zero, we can convert this into an equality comparison
10059 between the position and the location of the single bit. */
10060 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10061 have already reduced the shift count modulo the word size. */
10062 if (!SHIFT_COUNT_TRUNCATED
10063 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10064 && XEXP (op0
, 1) == const1_rtx
10065 && equality_comparison_p
&& const_op
== 0
10066 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10068 if (BITS_BIG_ENDIAN
)
10070 enum machine_mode new_mode
10071 = mode_for_extraction (EP_extzv
, 1);
10072 if (new_mode
== MAX_MACHINE_MODE
)
10073 i
= BITS_PER_WORD
- 1 - i
;
10077 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10081 op0
= XEXP (op0
, 2);
10085 /* Result is nonzero iff shift count is equal to I. */
10086 code
= reverse_condition (code
);
10090 /* ... fall through ... */
10093 tem
= expand_compound_operation (op0
);
10102 /* If testing for equality, we can take the NOT of the constant. */
10103 if (equality_comparison_p
10104 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10106 op0
= XEXP (op0
, 0);
10111 /* If just looking at the sign bit, reverse the sense of the
10113 if (sign_bit_comparison_p
)
10115 op0
= XEXP (op0
, 0);
10116 code
= (code
== GE
? LT
: GE
);
10122 /* If testing for equality, we can take the NEG of the constant. */
10123 if (equality_comparison_p
10124 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10126 op0
= XEXP (op0
, 0);
10131 /* The remaining cases only apply to comparisons with zero. */
10135 /* When X is ABS or is known positive,
10136 (neg X) is < 0 if and only if X != 0. */
10138 if (sign_bit_comparison_p
10139 && (GET_CODE (XEXP (op0
, 0)) == ABS
10140 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10141 && (nonzero_bits (XEXP (op0
, 0), mode
)
10142 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10144 op0
= XEXP (op0
, 0);
10145 code
= (code
== LT
? NE
: EQ
);
10149 /* If we have NEG of something whose two high-order bits are the
10150 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10151 if (num_sign_bit_copies (op0
, mode
) >= 2)
10153 op0
= XEXP (op0
, 0);
10154 code
= swap_condition (code
);
10160 /* If we are testing equality and our count is a constant, we
10161 can perform the inverse operation on our RHS. */
10162 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10163 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10164 op1
, XEXP (op0
, 1))) != 0)
10166 op0
= XEXP (op0
, 0);
10171 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10172 a particular bit. Convert it to an AND of a constant of that
10173 bit. This will be converted into a ZERO_EXTRACT. */
10174 if (const_op
== 0 && sign_bit_comparison_p
10175 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10176 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10178 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10181 - INTVAL (XEXP (op0
, 1)))));
10182 code
= (code
== LT
? NE
: EQ
);
10186 /* Fall through. */
10189 /* ABS is ignorable inside an equality comparison with zero. */
10190 if (const_op
== 0 && equality_comparison_p
)
10192 op0
= XEXP (op0
, 0);
10198 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10199 (compare FOO CONST) if CONST fits in FOO's mode and we
10200 are either testing inequality or have an unsigned
10201 comparison with ZERO_EXTEND or a signed comparison with
10202 SIGN_EXTEND. But don't do it if we don't have a compare
10203 insn of the given mode, since we'd have to revert it
10204 later on, and then we wouldn't know whether to sign- or
10206 mode
= GET_MODE (XEXP (op0
, 0));
10207 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10208 && ! unsigned_comparison_p
10209 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10210 && ((unsigned HOST_WIDE_INT
) const_op
10211 < (((unsigned HOST_WIDE_INT
) 1
10212 << (GET_MODE_BITSIZE (mode
) - 1))))
10213 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10215 op0
= XEXP (op0
, 0);
10221 /* Check for the case where we are comparing A - C1 with C2, that is
10223 (subreg:MODE (plus (A) (-C1))) op (C2)
10225 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10226 comparison in the wider mode. One of the following two conditions
10227 must be true in order for this to be valid:
10229 1. The mode extension results in the same bit pattern being added
10230 on both sides and the comparison is equality or unsigned. As
10231 C2 has been truncated to fit in MODE, the pattern can only be
10234 2. The mode extension results in the sign bit being copied on
10237 The difficulty here is that we have predicates for A but not for
10238 (A - C1) so we need to check that C1 is within proper bounds so
10239 as to perturbate A as little as possible. */
10241 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10242 && subreg_lowpart_p (op0
)
10243 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10244 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10245 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10247 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10248 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10249 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10252 && (unsigned HOST_WIDE_INT
) c1
10253 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10254 && (equality_comparison_p
|| unsigned_comparison_p
)
10255 /* (A - C1) zero-extends if it is positive and sign-extends
10256 if it is negative, C2 both zero- and sign-extends. */
10257 && ((0 == (nonzero_bits (a
, inner_mode
)
10258 & ~GET_MODE_MASK (mode
))
10260 /* (A - C1) sign-extends if it is positive and 1-extends
10261 if it is negative, C2 both sign- and 1-extends. */
10262 || (num_sign_bit_copies (a
, inner_mode
)
10263 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10266 || ((unsigned HOST_WIDE_INT
) c1
10267 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10268 /* (A - C1) always sign-extends, like C2. */
10269 && num_sign_bit_copies (a
, inner_mode
)
10270 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10271 - (mode_width
- 1))))
10273 op0
= SUBREG_REG (op0
);
10278 /* If the inner mode is narrower and we are extracting the low part,
10279 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10280 if (subreg_lowpart_p (op0
)
10281 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10282 /* Fall through */ ;
10286 /* ... fall through ... */
10289 mode
= GET_MODE (XEXP (op0
, 0));
10290 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10291 && (unsigned_comparison_p
|| equality_comparison_p
)
10292 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10293 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10294 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10296 op0
= XEXP (op0
, 0);
10302 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10303 this for equality comparisons due to pathological cases involving
10305 if (equality_comparison_p
10306 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10307 op1
, XEXP (op0
, 1))))
10309 op0
= XEXP (op0
, 0);
10314 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10315 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10316 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10318 op0
= XEXP (XEXP (op0
, 0), 0);
10319 code
= (code
== LT
? EQ
: NE
);
10325 /* We used to optimize signed comparisons against zero, but that
10326 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10327 arrive here as equality comparisons, or (GEU, LTU) are
10328 optimized away. No need to special-case them. */
10330 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10331 (eq B (minus A C)), whichever simplifies. We can only do
10332 this for equality comparisons due to pathological cases involving
10334 if (equality_comparison_p
10335 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10336 XEXP (op0
, 1), op1
)))
10338 op0
= XEXP (op0
, 0);
10343 if (equality_comparison_p
10344 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10345 XEXP (op0
, 0), op1
)))
10347 op0
= XEXP (op0
, 1);
10352 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10353 of bits in X minus 1, is one iff X > 0. */
10354 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10355 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10356 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10358 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10360 op0
= XEXP (op0
, 1);
10361 code
= (code
== GE
? LE
: GT
);
10367 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10368 if C is zero or B is a constant. */
10369 if (equality_comparison_p
10370 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10371 XEXP (op0
, 1), op1
)))
10373 op0
= XEXP (op0
, 0);
10380 case UNEQ
: case LTGT
:
10381 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10382 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10383 case UNORDERED
: case ORDERED
:
10384 /* We can't do anything if OP0 is a condition code value, rather
10385 than an actual data value. */
10387 || CC0_P (XEXP (op0
, 0))
10388 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10391 /* Get the two operands being compared. */
10392 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10393 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10395 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10397 /* Check for the cases where we simply want the result of the
10398 earlier test or the opposite of that result. */
10399 if (code
== NE
|| code
== EQ
10400 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10401 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10402 && (STORE_FLAG_VALUE
10403 & (((HOST_WIDE_INT
) 1
10404 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10405 && (code
== LT
|| code
== GE
)))
10407 enum rtx_code new_code
;
10408 if (code
== LT
|| code
== NE
)
10409 new_code
= GET_CODE (op0
);
10411 new_code
= reversed_comparison_code (op0
, NULL
);
10413 if (new_code
!= UNKNOWN
)
10424 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10426 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10427 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10428 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10430 op0
= XEXP (op0
, 1);
10431 code
= (code
== GE
? GT
: LE
);
10437 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10438 will be converted to a ZERO_EXTRACT later. */
10439 if (const_op
== 0 && equality_comparison_p
10440 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10441 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10443 op0
= simplify_and_const_int
10444 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10446 XEXP (XEXP (op0
, 0), 1)),
10447 (HOST_WIDE_INT
) 1);
10451 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10452 zero and X is a comparison and C1 and C2 describe only bits set
10453 in STORE_FLAG_VALUE, we can compare with X. */
10454 if (const_op
== 0 && equality_comparison_p
10455 && mode_width
<= HOST_BITS_PER_WIDE_INT
10456 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10457 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10458 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10459 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10460 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10462 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10463 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10464 if ((~STORE_FLAG_VALUE
& mask
) == 0
10465 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10466 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10467 && COMPARISON_P (tem
))))
10469 op0
= XEXP (XEXP (op0
, 0), 0);
10474 /* If we are doing an equality comparison of an AND of a bit equal
10475 to the sign bit, replace this with a LT or GE comparison of
10476 the underlying value. */
10477 if (equality_comparison_p
10479 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10480 && mode_width
<= HOST_BITS_PER_WIDE_INT
10481 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10482 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10484 op0
= XEXP (op0
, 0);
10485 code
= (code
== EQ
? GE
: LT
);
10489 /* If this AND operation is really a ZERO_EXTEND from a narrower
10490 mode, the constant fits within that mode, and this is either an
10491 equality or unsigned comparison, try to do this comparison in
10492 the narrower mode. */
10493 if ((equality_comparison_p
|| unsigned_comparison_p
)
10494 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10495 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10496 & GET_MODE_MASK (mode
))
10498 && const_op
>> i
== 0
10499 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10501 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10505 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10506 fits in both M1 and M2 and the SUBREG is either paradoxical
10507 or represents the low part, permute the SUBREG and the AND
10509 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10511 unsigned HOST_WIDE_INT c1
;
10512 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10513 /* Require an integral mode, to avoid creating something like
10515 if (SCALAR_INT_MODE_P (tmode
)
10516 /* It is unsafe to commute the AND into the SUBREG if the
10517 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10518 not defined. As originally written the upper bits
10519 have a defined value due to the AND operation.
10520 However, if we commute the AND inside the SUBREG then
10521 they no longer have defined values and the meaning of
10522 the code has been changed. */
10524 #ifdef WORD_REGISTER_OPERATIONS
10525 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10526 && mode_width
<= BITS_PER_WORD
)
10528 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10529 && subreg_lowpart_p (XEXP (op0
, 0))))
10530 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10531 && mode_width
<= HOST_BITS_PER_WIDE_INT
10532 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10533 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10534 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10536 && c1
!= GET_MODE_MASK (tmode
))
10538 op0
= simplify_gen_binary (AND
, tmode
,
10539 SUBREG_REG (XEXP (op0
, 0)),
10540 gen_int_mode (c1
, tmode
));
10541 op0
= gen_lowpart (mode
, op0
);
10546 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10547 if (const_op
== 0 && equality_comparison_p
10548 && XEXP (op0
, 1) == const1_rtx
10549 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10551 op0
= simplify_and_const_int
10552 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10553 code
= (code
== NE
? EQ
: NE
);
10557 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10558 (eq (and (lshiftrt X) 1) 0).
10559 Also handle the case where (not X) is expressed using xor. */
10560 if (const_op
== 0 && equality_comparison_p
10561 && XEXP (op0
, 1) == const1_rtx
10562 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10564 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10565 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10567 if (GET_CODE (shift_op
) == NOT
10568 || (GET_CODE (shift_op
) == XOR
10569 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10570 && GET_CODE (shift_count
) == CONST_INT
10571 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10572 && (INTVAL (XEXP (shift_op
, 1))
10573 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10575 op0
= simplify_and_const_int
10577 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10578 (HOST_WIDE_INT
) 1);
10579 code
= (code
== NE
? EQ
: NE
);
10586 /* If we have (compare (ashift FOO N) (const_int C)) and
10587 the high order N bits of FOO (N+1 if an inequality comparison)
10588 are known to be zero, we can do this by comparing FOO with C
10589 shifted right N bits so long as the low-order N bits of C are
10591 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10592 && INTVAL (XEXP (op0
, 1)) >= 0
10593 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10594 < HOST_BITS_PER_WIDE_INT
)
10596 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10597 && mode_width
<= HOST_BITS_PER_WIDE_INT
10598 && (nonzero_bits (XEXP (op0
, 0), mode
)
10599 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10600 + ! equality_comparison_p
))) == 0)
10602 /* We must perform a logical shift, not an arithmetic one,
10603 as we want the top N bits of C to be zero. */
10604 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10606 temp
>>= INTVAL (XEXP (op0
, 1));
10607 op1
= gen_int_mode (temp
, mode
);
10608 op0
= XEXP (op0
, 0);
10612 /* If we are doing a sign bit comparison, it means we are testing
10613 a particular bit. Convert it to the appropriate AND. */
10614 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10615 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10617 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10620 - INTVAL (XEXP (op0
, 1)))));
10621 code
= (code
== LT
? NE
: EQ
);
10625 /* If this an equality comparison with zero and we are shifting
10626 the low bit to the sign bit, we can convert this to an AND of the
10628 if (const_op
== 0 && equality_comparison_p
10629 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10630 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10633 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10634 (HOST_WIDE_INT
) 1);
10640 /* If this is an equality comparison with zero, we can do this
10641 as a logical shift, which might be much simpler. */
10642 if (equality_comparison_p
&& const_op
== 0
10643 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10645 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10647 INTVAL (XEXP (op0
, 1)));
10651 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10652 do the comparison in a narrower mode. */
10653 if (! unsigned_comparison_p
10654 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10655 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10656 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10657 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10658 MODE_INT
, 1)) != BLKmode
10659 && (((unsigned HOST_WIDE_INT
) const_op
10660 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10661 <= GET_MODE_MASK (tmode
)))
10663 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10667 /* Likewise if OP0 is a PLUS of a sign extension with a
10668 constant, which is usually represented with the PLUS
10669 between the shifts. */
10670 if (! unsigned_comparison_p
10671 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10672 && GET_CODE (XEXP (op0
, 0)) == PLUS
10673 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10674 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10675 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10676 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10677 MODE_INT
, 1)) != BLKmode
10678 && (((unsigned HOST_WIDE_INT
) const_op
10679 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10680 <= GET_MODE_MASK (tmode
)))
10682 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10683 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10684 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
10685 add_const
, XEXP (op0
, 1));
10687 op0
= simplify_gen_binary (PLUS
, tmode
,
10688 gen_lowpart (tmode
, inner
),
10693 /* ... fall through ... */
10695 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10696 the low order N bits of FOO are known to be zero, we can do this
10697 by comparing FOO with C shifted left N bits so long as no
10698 overflow occurs. */
10699 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10700 && INTVAL (XEXP (op0
, 1)) >= 0
10701 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10702 && mode_width
<= HOST_BITS_PER_WIDE_INT
10703 && (nonzero_bits (XEXP (op0
, 0), mode
)
10704 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10705 && (((unsigned HOST_WIDE_INT
) const_op
10706 + (GET_CODE (op0
) != LSHIFTRT
10707 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10710 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10712 /* If the shift was logical, then we must make the condition
10714 if (GET_CODE (op0
) == LSHIFTRT
)
10715 code
= unsigned_condition (code
);
10717 const_op
<<= INTVAL (XEXP (op0
, 1));
10718 op1
= GEN_INT (const_op
);
10719 op0
= XEXP (op0
, 0);
10723 /* If we are using this shift to extract just the sign bit, we
10724 can replace this with an LT or GE comparison. */
10726 && (equality_comparison_p
|| sign_bit_comparison_p
)
10727 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10728 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10731 op0
= XEXP (op0
, 0);
10732 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10744 /* Now make any compound operations involved in this comparison. Then,
10745 check for an outmost SUBREG on OP0 that is not doing anything or is
10746 paradoxical. The latter transformation must only be performed when
10747 it is known that the "extra" bits will be the same in op0 and op1 or
10748 that they don't matter. There are three cases to consider:
10750 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10751 care bits and we can assume they have any convenient value. So
10752 making the transformation is safe.
10754 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10755 In this case the upper bits of op0 are undefined. We should not make
10756 the simplification in that case as we do not know the contents of
10759 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10760 UNKNOWN. In that case we know those bits are zeros or ones. We must
10761 also be sure that they are the same as the upper bits of op1.
10763 We can never remove a SUBREG for a non-equality comparison because
10764 the sign bit is in a different place in the underlying object. */
10766 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10767 op1
= make_compound_operation (op1
, SET
);
10769 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10770 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10771 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10772 && (code
== NE
|| code
== EQ
))
10774 if (GET_MODE_SIZE (GET_MODE (op0
))
10775 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10777 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10779 if (REG_P (SUBREG_REG (op0
)))
10781 op0
= SUBREG_REG (op0
);
10782 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10785 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10786 <= HOST_BITS_PER_WIDE_INT
)
10787 && (nonzero_bits (SUBREG_REG (op0
),
10788 GET_MODE (SUBREG_REG (op0
)))
10789 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10791 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10793 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10794 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10795 op0
= SUBREG_REG (op0
), op1
= tem
;
10799 /* We now do the opposite procedure: Some machines don't have compare
10800 insns in all modes. If OP0's mode is an integer mode smaller than a
10801 word and we can't do a compare in that mode, see if there is a larger
10802 mode for which we can do the compare. There are a number of cases in
10803 which we can use the wider mode. */
10805 mode
= GET_MODE (op0
);
10806 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10807 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10808 && ! have_insn_for (COMPARE
, mode
))
10809 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10811 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10812 tmode
= GET_MODE_WIDER_MODE (tmode
))
10813 if (have_insn_for (COMPARE
, tmode
))
10817 /* If the only nonzero bits in OP0 and OP1 are those in the
10818 narrower mode and this is an equality or unsigned comparison,
10819 we can use the wider mode. Similarly for sign-extended
10820 values, in which case it is true for all comparisons. */
10821 zero_extended
= ((code
== EQ
|| code
== NE
10822 || code
== GEU
|| code
== GTU
10823 || code
== LEU
|| code
== LTU
)
10824 && (nonzero_bits (op0
, tmode
)
10825 & ~GET_MODE_MASK (mode
)) == 0
10826 && ((GET_CODE (op1
) == CONST_INT
10827 || (nonzero_bits (op1
, tmode
)
10828 & ~GET_MODE_MASK (mode
)) == 0)));
10831 || ((num_sign_bit_copies (op0
, tmode
)
10832 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10833 - GET_MODE_BITSIZE (mode
)))
10834 && (num_sign_bit_copies (op1
, tmode
)
10835 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10836 - GET_MODE_BITSIZE (mode
)))))
10838 /* If OP0 is an AND and we don't have an AND in MODE either,
10839 make a new AND in the proper mode. */
10840 if (GET_CODE (op0
) == AND
10841 && !have_insn_for (AND
, mode
))
10842 op0
= simplify_gen_binary (AND
, tmode
,
10843 gen_lowpart (tmode
,
10845 gen_lowpart (tmode
,
10848 op0
= gen_lowpart (tmode
, op0
);
10849 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10850 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10851 op1
= gen_lowpart (tmode
, op1
);
10855 /* If this is a test for negative, we can make an explicit
10856 test of the sign bit. */
10858 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10859 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10861 op0
= simplify_gen_binary (AND
, tmode
,
10862 gen_lowpart (tmode
, op0
),
10863 GEN_INT ((HOST_WIDE_INT
) 1
10864 << (GET_MODE_BITSIZE (mode
)
10866 code
= (code
== LT
) ? NE
: EQ
;
10871 #ifdef CANONICALIZE_COMPARISON
10872 /* If this machine only supports a subset of valid comparisons, see if we
10873 can convert an unsupported one into a supported one. */
10874 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10883 /* Utility function for record_value_for_reg. Count number of
10888 enum rtx_code code
= GET_CODE (x
);
10892 if (GET_RTX_CLASS (code
) == '2'
10893 || GET_RTX_CLASS (code
) == 'c')
10895 rtx x0
= XEXP (x
, 0);
10896 rtx x1
= XEXP (x
, 1);
10899 return 1 + 2 * count_rtxs (x0
);
10901 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
10902 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
10903 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10904 return 2 + 2 * count_rtxs (x0
)
10905 + count_rtxs (x
== XEXP (x1
, 0)
10906 ? XEXP (x1
, 1) : XEXP (x1
, 0));
10908 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
10909 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
10910 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10911 return 2 + 2 * count_rtxs (x1
)
10912 + count_rtxs (x
== XEXP (x0
, 0)
10913 ? XEXP (x0
, 1) : XEXP (x0
, 0));
10916 fmt
= GET_RTX_FORMAT (code
);
10917 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10919 ret
+= count_rtxs (XEXP (x
, i
));
10924 /* Utility function for following routine. Called when X is part of a value
10925 being stored into last_set_value. Sets last_set_table_tick
10926 for each register mentioned. Similar to mention_regs in cse.c */
10929 update_table_tick (rtx x
)
10931 enum rtx_code code
= GET_CODE (x
);
10932 const char *fmt
= GET_RTX_FORMAT (code
);
10937 unsigned int regno
= REGNO (x
);
10938 unsigned int endregno
10939 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10940 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10943 for (r
= regno
; r
< endregno
; r
++)
10944 reg_stat
[r
].last_set_table_tick
= label_tick
;
10949 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10950 /* Note that we can't have an "E" in values stored; see
10951 get_last_value_validate. */
10954 /* Check for identical subexpressions. If x contains
10955 identical subexpression we only have to traverse one of
10957 if (i
== 0 && ARITHMETIC_P (x
))
10959 /* Note that at this point x1 has already been
10961 rtx x0
= XEXP (x
, 0);
10962 rtx x1
= XEXP (x
, 1);
10964 /* If x0 and x1 are identical then there is no need to
10969 /* If x0 is identical to a subexpression of x1 then while
10970 processing x1, x0 has already been processed. Thus we
10971 are done with x. */
10972 if (ARITHMETIC_P (x1
)
10973 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10976 /* If x1 is identical to a subexpression of x0 then we
10977 still have to process the rest of x0. */
10978 if (ARITHMETIC_P (x0
)
10979 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10981 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10986 update_table_tick (XEXP (x
, i
));
10990 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10991 are saying that the register is clobbered and we no longer know its
10992 value. If INSN is zero, don't update reg_stat[].last_set; this is
10993 only permitted with VALUE also zero and is used to invalidate the
10997 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10999 unsigned int regno
= REGNO (reg
);
11000 unsigned int endregno
11001 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11002 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
11005 /* If VALUE contains REG and we have a previous value for REG, substitute
11006 the previous value. */
11007 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11011 /* Set things up so get_last_value is allowed to see anything set up to
11013 subst_low_cuid
= INSN_CUID (insn
);
11014 tem
= get_last_value (reg
);
11016 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11017 it isn't going to be useful and will take a lot of time to process,
11018 so just use the CLOBBER. */
11022 if (ARITHMETIC_P (tem
)
11023 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11024 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11025 tem
= XEXP (tem
, 0);
11026 else if (count_occurrences (value
, reg
, 1) >= 2)
11028 /* If there are two or more occurrences of REG in VALUE,
11029 prevent the value from growing too much. */
11030 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
11031 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
11034 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11038 /* For each register modified, show we don't know its value, that
11039 we don't know about its bitwise content, that its value has been
11040 updated, and that we don't know the location of the death of the
11042 for (i
= regno
; i
< endregno
; i
++)
11045 reg_stat
[i
].last_set
= insn
;
11047 reg_stat
[i
].last_set_value
= 0;
11048 reg_stat
[i
].last_set_mode
= 0;
11049 reg_stat
[i
].last_set_nonzero_bits
= 0;
11050 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11051 reg_stat
[i
].last_death
= 0;
11054 /* Mark registers that are being referenced in this value. */
11056 update_table_tick (value
);
11058 /* Now update the status of each register being set.
11059 If someone is using this register in this block, set this register
11060 to invalid since we will get confused between the two lives in this
11061 basic block. This makes using this register always invalid. In cse, we
11062 scan the table to invalidate all entries using this register, but this
11063 is too much work for us. */
11065 for (i
= regno
; i
< endregno
; i
++)
11067 reg_stat
[i
].last_set_label
= label_tick
;
11068 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
11069 reg_stat
[i
].last_set_invalid
= 1;
11071 reg_stat
[i
].last_set_invalid
= 0;
11074 /* The value being assigned might refer to X (like in "x++;"). In that
11075 case, we must replace it with (clobber (const_int 0)) to prevent
11077 if (value
&& ! get_last_value_validate (&value
, insn
,
11078 reg_stat
[regno
].last_set_label
, 0))
11080 value
= copy_rtx (value
);
11081 if (! get_last_value_validate (&value
, insn
,
11082 reg_stat
[regno
].last_set_label
, 1))
11086 /* For the main register being modified, update the value, the mode, the
11087 nonzero bits, and the number of sign bit copies. */
11089 reg_stat
[regno
].last_set_value
= value
;
11093 enum machine_mode mode
= GET_MODE (reg
);
11094 subst_low_cuid
= INSN_CUID (insn
);
11095 reg_stat
[regno
].last_set_mode
= mode
;
11096 if (GET_MODE_CLASS (mode
) == MODE_INT
11097 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11098 mode
= nonzero_bits_mode
;
11099 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11100 reg_stat
[regno
].last_set_sign_bit_copies
11101 = num_sign_bit_copies (value
, GET_MODE (reg
));
11105 /* Called via note_stores from record_dead_and_set_regs to handle one
11106 SET or CLOBBER in an insn. DATA is the instruction in which the
11107 set is occurring. */
11110 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11112 rtx record_dead_insn
= (rtx
) data
;
11114 if (GET_CODE (dest
) == SUBREG
)
11115 dest
= SUBREG_REG (dest
);
11119 /* If we are setting the whole register, we know its value. Otherwise
11120 show that we don't know the value. We can handle SUBREG in
11122 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11123 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11124 else if (GET_CODE (setter
) == SET
11125 && GET_CODE (SET_DEST (setter
)) == SUBREG
11126 && SUBREG_REG (SET_DEST (setter
)) == dest
11127 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11128 && subreg_lowpart_p (SET_DEST (setter
)))
11129 record_value_for_reg (dest
, record_dead_insn
,
11130 gen_lowpart (GET_MODE (dest
),
11131 SET_SRC (setter
)));
11133 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11135 else if (MEM_P (dest
)
11136 /* Ignore pushes, they clobber nothing. */
11137 && ! push_operand (dest
, GET_MODE (dest
)))
11138 mem_last_set
= INSN_CUID (record_dead_insn
);
11141 /* Update the records of when each REG was most recently set or killed
11142 for the things done by INSN. This is the last thing done in processing
11143 INSN in the combiner loop.
11145 We update reg_stat[], in particular fields last_set, last_set_value,
11146 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11147 last_death, and also the similar information mem_last_set (which insn
11148 most recently modified memory) and last_call_cuid (which insn was the
11149 most recent subroutine call). */
11152 record_dead_and_set_regs (rtx insn
)
11157 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11159 if (REG_NOTE_KIND (link
) == REG_DEAD
11160 && REG_P (XEXP (link
, 0)))
11162 unsigned int regno
= REGNO (XEXP (link
, 0));
11163 unsigned int endregno
11164 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11165 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11168 for (i
= regno
; i
< endregno
; i
++)
11169 reg_stat
[i
].last_death
= insn
;
11171 else if (REG_NOTE_KIND (link
) == REG_INC
)
11172 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11177 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11178 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11180 reg_stat
[i
].last_set_value
= 0;
11181 reg_stat
[i
].last_set_mode
= 0;
11182 reg_stat
[i
].last_set_nonzero_bits
= 0;
11183 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11184 reg_stat
[i
].last_death
= 0;
11187 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11189 /* Don't bother recording what this insn does. It might set the
11190 return value register, but we can't combine into a call
11191 pattern anyway, so there's no point trying (and it may cause
11192 a crash, if e.g. we wind up asking for last_set_value of a
11193 SUBREG of the return value register). */
11197 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11200 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11201 register present in the SUBREG, so for each such SUBREG go back and
11202 adjust nonzero and sign bit information of the registers that are
11203 known to have some zero/sign bits set.
11205 This is needed because when combine blows the SUBREGs away, the
11206 information on zero/sign bits is lost and further combines can be
11207 missed because of that. */
11210 record_promoted_value (rtx insn
, rtx subreg
)
11213 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11214 enum machine_mode mode
= GET_MODE (subreg
);
11216 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11219 for (links
= LOG_LINKS (insn
); links
;)
11221 insn
= XEXP (links
, 0);
11222 set
= single_set (insn
);
11224 if (! set
|| !REG_P (SET_DEST (set
))
11225 || REGNO (SET_DEST (set
)) != regno
11226 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11228 links
= XEXP (links
, 1);
11232 if (reg_stat
[regno
].last_set
== insn
)
11234 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11235 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11238 if (REG_P (SET_SRC (set
)))
11240 regno
= REGNO (SET_SRC (set
));
11241 links
= LOG_LINKS (insn
);
11248 /* Scan X for promoted SUBREGs. For each one found,
11249 note what it implies to the registers used in it. */
11252 check_promoted_subreg (rtx insn
, rtx x
)
11254 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11255 && REG_P (SUBREG_REG (x
)))
11256 record_promoted_value (insn
, x
);
11259 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11262 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11266 check_promoted_subreg (insn
, XEXP (x
, i
));
11270 if (XVEC (x
, i
) != 0)
11271 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11272 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11278 /* Utility routine for the following function. Verify that all the registers
11279 mentioned in *LOC are valid when *LOC was part of a value set when
11280 label_tick == TICK. Return 0 if some are not.
11282 If REPLACE is nonzero, replace the invalid reference with
11283 (clobber (const_int 0)) and return 1. This replacement is useful because
11284 we often can get useful information about the form of a value (e.g., if
11285 it was produced by a shift that always produces -1 or 0) even though
11286 we don't know exactly what registers it was produced from. */
11289 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11292 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11293 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11298 unsigned int regno
= REGNO (x
);
11299 unsigned int endregno
11300 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11301 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11304 for (j
= regno
; j
< endregno
; j
++)
11305 if (reg_stat
[j
].last_set_invalid
11306 /* If this is a pseudo-register that was only set once and not
11307 live at the beginning of the function, it is always valid. */
11308 || (! (regno
>= FIRST_PSEUDO_REGISTER
11309 && REG_N_SETS (regno
) == 1
11310 && (! REGNO_REG_SET_P
11311 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11313 && reg_stat
[j
].last_set_label
> tick
))
11316 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11322 /* If this is a memory reference, make sure that there were
11323 no stores after it that might have clobbered the value. We don't
11324 have alias info, so we assume any store invalidates it. */
11325 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11326 && INSN_CUID (insn
) <= mem_last_set
)
11329 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11333 for (i
= 0; i
< len
; i
++)
11337 /* Check for identical subexpressions. If x contains
11338 identical subexpression we only have to traverse one of
11340 if (i
== 1 && ARITHMETIC_P (x
))
11342 /* Note that at this point x0 has already been checked
11343 and found valid. */
11344 rtx x0
= XEXP (x
, 0);
11345 rtx x1
= XEXP (x
, 1);
11347 /* If x0 and x1 are identical then x is also valid. */
11351 /* If x1 is identical to a subexpression of x0 then
11352 while checking x0, x1 has already been checked. Thus
11353 it is valid and so as x. */
11354 if (ARITHMETIC_P (x0
)
11355 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11358 /* If x0 is identical to a subexpression of x1 then x is
11359 valid iff the rest of x1 is valid. */
11360 if (ARITHMETIC_P (x1
)
11361 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11363 get_last_value_validate (&XEXP (x1
,
11364 x0
== XEXP (x1
, 0) ? 1 : 0),
11365 insn
, tick
, replace
);
11368 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11372 /* Don't bother with these. They shouldn't occur anyway. */
11373 else if (fmt
[i
] == 'E')
11377 /* If we haven't found a reason for it to be invalid, it is valid. */
11381 /* Get the last value assigned to X, if known. Some registers
11382 in the value may be replaced with (clobber (const_int 0)) if their value
11383 is known longer known reliably. */
11386 get_last_value (rtx x
)
11388 unsigned int regno
;
11391 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11392 then convert it to the desired mode. If this is a paradoxical SUBREG,
11393 we cannot predict what values the "extra" bits might have. */
11394 if (GET_CODE (x
) == SUBREG
11395 && subreg_lowpart_p (x
)
11396 && (GET_MODE_SIZE (GET_MODE (x
))
11397 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11398 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11399 return gen_lowpart (GET_MODE (x
), value
);
11405 value
= reg_stat
[regno
].last_set_value
;
11407 /* If we don't have a value, or if it isn't for this basic block and
11408 it's either a hard register, set more than once, or it's a live
11409 at the beginning of the function, return 0.
11411 Because if it's not live at the beginning of the function then the reg
11412 is always set before being used (is never used without being set).
11413 And, if it's set only once, and it's always set before use, then all
11414 uses must have the same last value, even if it's not from this basic
11418 || (reg_stat
[regno
].last_set_label
!= label_tick
11419 && (regno
< FIRST_PSEUDO_REGISTER
11420 || REG_N_SETS (regno
) != 1
11421 || (REGNO_REG_SET_P
11422 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11426 /* If the value was set in a later insn than the ones we are processing,
11427 we can't use it even if the register was only set once. */
11428 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11431 /* If the value has all its registers valid, return it. */
11432 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11433 reg_stat
[regno
].last_set_label
, 0))
11436 /* Otherwise, make a copy and replace any invalid register with
11437 (clobber (const_int 0)). If that fails for some reason, return 0. */
11439 value
= copy_rtx (value
);
11440 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11441 reg_stat
[regno
].last_set_label
, 1))
11447 /* Return nonzero if expression X refers to a REG or to memory
11448 that is set in an instruction more recent than FROM_CUID. */
11451 use_crosses_set_p (rtx x
, int from_cuid
)
11455 enum rtx_code code
= GET_CODE (x
);
11459 unsigned int regno
= REGNO (x
);
11460 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11461 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11463 #ifdef PUSH_ROUNDING
11464 /* Don't allow uses of the stack pointer to be moved,
11465 because we don't know whether the move crosses a push insn. */
11466 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11469 for (; regno
< endreg
; regno
++)
11470 if (reg_stat
[regno
].last_set
11471 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11476 if (code
== MEM
&& mem_last_set
> from_cuid
)
11479 fmt
= GET_RTX_FORMAT (code
);
11481 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11486 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11487 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11490 else if (fmt
[i
] == 'e'
11491 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11497 /* Define three variables used for communication between the following
11500 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11501 static int reg_dead_flag
;
11503 /* Function called via note_stores from reg_dead_at_p.
11505 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11506 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11509 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11511 unsigned int regno
, endregno
;
11516 regno
= REGNO (dest
);
11517 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11518 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11520 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11521 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11524 /* Return nonzero if REG is known to be dead at INSN.
11526 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11527 referencing REG, it is dead. If we hit a SET referencing REG, it is
11528 live. Otherwise, see if it is live or dead at the start of the basic
11529 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11530 must be assumed to be always live. */
11533 reg_dead_at_p (rtx reg
, rtx insn
)
11538 /* Set variables for reg_dead_at_p_1. */
11539 reg_dead_regno
= REGNO (reg
);
11540 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11541 ? hard_regno_nregs
[reg_dead_regno
]
11547 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11548 we allow the machine description to decide whether use-and-clobber
11549 patterns are OK. */
11550 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11552 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11553 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11557 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11558 beginning of function. */
11559 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11560 insn
= prev_nonnote_insn (insn
))
11562 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11564 return reg_dead_flag
== 1 ? 1 : 0;
11566 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11570 /* Get the basic block that we were in. */
11572 block
= ENTRY_BLOCK_PTR
->next_bb
;
11575 FOR_EACH_BB (block
)
11576 if (insn
== BB_HEAD (block
))
11579 if (block
== EXIT_BLOCK_PTR
)
11583 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11584 if (REGNO_REG_SET_P (block
->il
.rtl
->global_live_at_start
, i
))
11590 /* Note hard registers in X that are used. This code is similar to
11591 that in flow.c, but much simpler since we don't care about pseudos. */
11594 mark_used_regs_combine (rtx x
)
11596 RTX_CODE code
= GET_CODE (x
);
11597 unsigned int regno
;
11610 case ADDR_DIFF_VEC
:
11613 /* CC0 must die in the insn after it is set, so we don't need to take
11614 special note of it here. */
11620 /* If we are clobbering a MEM, mark any hard registers inside the
11621 address as used. */
11622 if (MEM_P (XEXP (x
, 0)))
11623 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11628 /* A hard reg in a wide mode may really be multiple registers.
11629 If so, mark all of them just like the first. */
11630 if (regno
< FIRST_PSEUDO_REGISTER
)
11632 unsigned int endregno
, r
;
11634 /* None of this applies to the stack, frame or arg pointers. */
11635 if (regno
== STACK_POINTER_REGNUM
11636 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11637 || regno
== HARD_FRAME_POINTER_REGNUM
11639 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11640 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11642 || regno
== FRAME_POINTER_REGNUM
)
11645 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11646 for (r
= regno
; r
< endregno
; r
++)
11647 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11653 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11655 rtx testreg
= SET_DEST (x
);
11657 while (GET_CODE (testreg
) == SUBREG
11658 || GET_CODE (testreg
) == ZERO_EXTRACT
11659 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11660 testreg
= XEXP (testreg
, 0);
11662 if (MEM_P (testreg
))
11663 mark_used_regs_combine (XEXP (testreg
, 0));
11665 mark_used_regs_combine (SET_SRC (x
));
11673 /* Recursively scan the operands of this expression. */
11676 const char *fmt
= GET_RTX_FORMAT (code
);
11678 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11681 mark_used_regs_combine (XEXP (x
, i
));
11682 else if (fmt
[i
] == 'E')
11686 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11687 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11693 /* Remove register number REGNO from the dead registers list of INSN.
11695 Return the note used to record the death, if there was one. */
11698 remove_death (unsigned int regno
, rtx insn
)
11700 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11704 REG_N_DEATHS (regno
)--;
11705 remove_note (insn
, note
);
11711 /* For each register (hardware or pseudo) used within expression X, if its
11712 death is in an instruction with cuid between FROM_CUID (inclusive) and
11713 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11714 list headed by PNOTES.
11716 That said, don't move registers killed by maybe_kill_insn.
11718 This is done when X is being merged by combination into TO_INSN. These
11719 notes will then be distributed as needed. */
11722 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11727 enum rtx_code code
= GET_CODE (x
);
11731 unsigned int regno
= REGNO (x
);
11732 rtx where_dead
= reg_stat
[regno
].last_death
;
11733 rtx before_dead
, after_dead
;
11735 /* Don't move the register if it gets killed in between from and to. */
11736 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11737 && ! reg_referenced_p (x
, maybe_kill_insn
))
11740 /* WHERE_DEAD could be a USE insn made by combine, so first we
11741 make sure that we have insns with valid INSN_CUID values. */
11742 before_dead
= where_dead
;
11743 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11744 before_dead
= PREV_INSN (before_dead
);
11746 after_dead
= where_dead
;
11747 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11748 after_dead
= NEXT_INSN (after_dead
);
11750 if (before_dead
&& after_dead
11751 && INSN_CUID (before_dead
) >= from_cuid
11752 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11753 || (where_dead
!= after_dead
11754 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11756 rtx note
= remove_death (regno
, where_dead
);
11758 /* It is possible for the call above to return 0. This can occur
11759 when last_death points to I2 or I1 that we combined with.
11760 In that case make a new note.
11762 We must also check for the case where X is a hard register
11763 and NOTE is a death note for a range of hard registers
11764 including X. In that case, we must put REG_DEAD notes for
11765 the remaining registers in place of NOTE. */
11767 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11768 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11769 > GET_MODE_SIZE (GET_MODE (x
))))
11771 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11772 unsigned int deadend
11773 = (deadregno
+ hard_regno_nregs
[deadregno
]
11774 [GET_MODE (XEXP (note
, 0))]);
11775 unsigned int ourend
11776 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11779 for (i
= deadregno
; i
< deadend
; i
++)
11780 if (i
< regno
|| i
>= ourend
)
11781 REG_NOTES (where_dead
)
11782 = gen_rtx_EXPR_LIST (REG_DEAD
,
11784 REG_NOTES (where_dead
));
11787 /* If we didn't find any note, or if we found a REG_DEAD note that
11788 covers only part of the given reg, and we have a multi-reg hard
11789 register, then to be safe we must check for REG_DEAD notes
11790 for each register other than the first. They could have
11791 their own REG_DEAD notes lying around. */
11792 else if ((note
== 0
11794 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11795 < GET_MODE_SIZE (GET_MODE (x
)))))
11796 && regno
< FIRST_PSEUDO_REGISTER
11797 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11799 unsigned int ourend
11800 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11801 unsigned int i
, offset
;
11805 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11809 for (i
= regno
+ offset
; i
< ourend
; i
++)
11810 move_deaths (regno_reg_rtx
[i
],
11811 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11814 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11816 XEXP (note
, 1) = *pnotes
;
11820 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11822 REG_N_DEATHS (regno
)++;
11828 else if (GET_CODE (x
) == SET
)
11830 rtx dest
= SET_DEST (x
);
11832 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11834 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11835 that accesses one word of a multi-word item, some
11836 piece of everything register in the expression is used by
11837 this insn, so remove any old death. */
11838 /* ??? So why do we test for equality of the sizes? */
11840 if (GET_CODE (dest
) == ZERO_EXTRACT
11841 || GET_CODE (dest
) == STRICT_LOW_PART
11842 || (GET_CODE (dest
) == SUBREG
11843 && (((GET_MODE_SIZE (GET_MODE (dest
))
11844 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11845 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11846 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11848 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11852 /* If this is some other SUBREG, we know it replaces the entire
11853 value, so use that as the destination. */
11854 if (GET_CODE (dest
) == SUBREG
)
11855 dest
= SUBREG_REG (dest
);
11857 /* If this is a MEM, adjust deaths of anything used in the address.
11858 For a REG (the only other possibility), the entire value is
11859 being replaced so the old value is not used in this insn. */
11862 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11867 else if (GET_CODE (x
) == CLOBBER
)
11870 len
= GET_RTX_LENGTH (code
);
11871 fmt
= GET_RTX_FORMAT (code
);
11873 for (i
= 0; i
< len
; i
++)
11878 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11879 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11882 else if (fmt
[i
] == 'e')
11883 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11887 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11888 pattern of an insn. X must be a REG. */
11891 reg_bitfield_target_p (rtx x
, rtx body
)
11895 if (GET_CODE (body
) == SET
)
11897 rtx dest
= SET_DEST (body
);
11899 unsigned int regno
, tregno
, endregno
, endtregno
;
11901 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11902 target
= XEXP (dest
, 0);
11903 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11904 target
= SUBREG_REG (XEXP (dest
, 0));
11908 if (GET_CODE (target
) == SUBREG
)
11909 target
= SUBREG_REG (target
);
11911 if (!REG_P (target
))
11914 tregno
= REGNO (target
), regno
= REGNO (x
);
11915 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11916 return target
== x
;
11918 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11919 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11921 return endregno
> tregno
&& regno
< endtregno
;
11924 else if (GET_CODE (body
) == PARALLEL
)
11925 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11926 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11932 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11933 as appropriate. I3 and I2 are the insns resulting from the combination
11934 insns including FROM (I2 may be zero).
11936 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11937 not need REG_DEAD notes because they are being substituted for. This
11938 saves searching in the most common cases.
11940 Each note in the list is either ignored or placed on some insns, depending
11941 on the type of note. */
11944 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
11947 rtx note
, next_note
;
11950 for (note
= notes
; note
; note
= next_note
)
11952 rtx place
= 0, place2
= 0;
11954 /* If this NOTE references a pseudo register, ensure it references
11955 the latest copy of that register. */
11956 if (XEXP (note
, 0) && REG_P (XEXP (note
, 0))
11957 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11958 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11960 next_note
= XEXP (note
, 1);
11961 switch (REG_NOTE_KIND (note
))
11965 /* Doesn't matter much where we put this, as long as it's somewhere.
11966 It is preferable to keep these notes on branches, which is most
11967 likely to be i3. */
11971 case REG_VALUE_PROFILE
:
11972 /* Just get rid of this note, as it is unused later anyway. */
11975 case REG_NON_LOCAL_GOTO
:
11980 gcc_assert (i2
&& JUMP_P (i2
));
11985 case REG_EH_REGION
:
11986 /* These notes must remain with the call or trapping instruction. */
11989 else if (i2
&& CALL_P (i2
))
11993 gcc_assert (flag_non_call_exceptions
);
11994 if (may_trap_p (i3
))
11996 else if (i2
&& may_trap_p (i2
))
11998 /* ??? Otherwise assume we've combined things such that we
11999 can now prove that the instructions can't trap. Drop the
12000 note in this case. */
12006 /* These notes must remain with the call. It should not be
12007 possible for both I2 and I3 to be a call. */
12012 gcc_assert (i2
&& CALL_P (i2
));
12018 /* Any clobbers for i3 may still exist, and so we must process
12019 REG_UNUSED notes from that insn.
12021 Any clobbers from i2 or i1 can only exist if they were added by
12022 recog_for_combine. In that case, recog_for_combine created the
12023 necessary REG_UNUSED notes. Trying to keep any original
12024 REG_UNUSED notes from these insns can cause incorrect output
12025 if it is for the same register as the original i3 dest.
12026 In that case, we will notice that the register is set in i3,
12027 and then add a REG_UNUSED note for the destination of i3, which
12028 is wrong. However, it is possible to have REG_UNUSED notes from
12029 i2 or i1 for register which were both used and clobbered, so
12030 we keep notes from i2 or i1 if they will turn into REG_DEAD
12033 /* If this register is set or clobbered in I3, put the note there
12034 unless there is one already. */
12035 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12037 if (from_insn
!= i3
)
12040 if (! (REG_P (XEXP (note
, 0))
12041 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12042 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12045 /* Otherwise, if this register is used by I3, then this register
12046 now dies here, so we must put a REG_DEAD note here unless there
12048 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12049 && ! (REG_P (XEXP (note
, 0))
12050 ? find_regno_note (i3
, REG_DEAD
,
12051 REGNO (XEXP (note
, 0)))
12052 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12054 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12062 /* These notes say something about results of an insn. We can
12063 only support them if they used to be on I3 in which case they
12064 remain on I3. Otherwise they are ignored.
12066 If the note refers to an expression that is not a constant, we
12067 must also ignore the note since we cannot tell whether the
12068 equivalence is still true. It might be possible to do
12069 slightly better than this (we only have a problem if I2DEST
12070 or I1DEST is present in the expression), but it doesn't
12071 seem worth the trouble. */
12073 if (from_insn
== i3
12074 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12079 case REG_NO_CONFLICT
:
12080 /* These notes say something about how a register is used. They must
12081 be present on any use of the register in I2 or I3. */
12082 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12085 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12095 /* This can show up in several ways -- either directly in the
12096 pattern, or hidden off in the constant pool with (or without?)
12097 a REG_EQUAL note. */
12098 /* ??? Ignore the without-reg_equal-note problem for now. */
12099 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12100 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12101 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12102 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12106 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12107 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12108 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12109 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12117 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12118 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12119 if (place
&& JUMP_P (place
))
12121 rtx label
= JUMP_LABEL (place
);
12124 JUMP_LABEL (place
) = XEXP (note
, 0);
12127 gcc_assert (label
== XEXP (note
, 0));
12128 if (LABEL_P (label
))
12129 LABEL_NUSES (label
)--;
12133 if (place2
&& JUMP_P (place2
))
12135 rtx label
= JUMP_LABEL (place2
);
12138 JUMP_LABEL (place2
) = XEXP (note
, 0);
12141 gcc_assert (label
== XEXP (note
, 0));
12142 if (LABEL_P (label
))
12143 LABEL_NUSES (label
)--;
12150 /* This note says something about the value of a register prior
12151 to the execution of an insn. It is too much trouble to see
12152 if the note is still correct in all situations. It is better
12153 to simply delete it. */
12157 /* If the insn previously containing this note still exists,
12158 put it back where it was. Otherwise move it to the previous
12159 insn. Adjust the corresponding REG_LIBCALL note. */
12160 if (!NOTE_P (from_insn
))
12164 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12165 place
= prev_real_insn (from_insn
);
12167 XEXP (tem
, 0) = place
;
12168 /* If we're deleting the last remaining instruction of a
12169 libcall sequence, don't add the notes. */
12170 else if (XEXP (note
, 0) == from_insn
)
12172 /* Don't add the dangling REG_RETVAL note. */
12179 /* This is handled similarly to REG_RETVAL. */
12180 if (!NOTE_P (from_insn
))
12184 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12185 place
= next_real_insn (from_insn
);
12187 XEXP (tem
, 0) = place
;
12188 /* If we're deleting the last remaining instruction of a
12189 libcall sequence, don't add the notes. */
12190 else if (XEXP (note
, 0) == from_insn
)
12192 /* Don't add the dangling REG_LIBCALL note. */
12199 /* If the register is used as an input in I3, it dies there.
12200 Similarly for I2, if it is nonzero and adjacent to I3.
12202 If the register is not used as an input in either I3 or I2
12203 and it is not one of the registers we were supposed to eliminate,
12204 there are two possibilities. We might have a non-adjacent I2
12205 or we might have somehow eliminated an additional register
12206 from a computation. For example, we might have had A & B where
12207 we discover that B will always be zero. In this case we will
12208 eliminate the reference to A.
12210 In both cases, we must search to see if we can find a previous
12211 use of A and put the death note there. */
12214 && CALL_P (from_insn
)
12215 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12217 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12219 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12220 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12224 && (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12225 || rtx_equal_p (XEXP (note
, 0), elim_i1
)))
12230 basic_block bb
= this_basic_block
;
12232 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12234 if (! INSN_P (tem
))
12236 if (tem
== BB_HEAD (bb
))
12241 /* If the register is being set at TEM, see if that is all
12242 TEM is doing. If so, delete TEM. Otherwise, make this
12243 into a REG_UNUSED note instead. Don't delete sets to
12244 global register vars. */
12245 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12246 || !global_regs
[REGNO (XEXP (note
, 0))])
12247 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12249 rtx set
= single_set (tem
);
12250 rtx inner_dest
= 0;
12252 rtx cc0_setter
= NULL_RTX
;
12256 for (inner_dest
= SET_DEST (set
);
12257 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12258 || GET_CODE (inner_dest
) == SUBREG
12259 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12260 inner_dest
= XEXP (inner_dest
, 0))
12263 /* Verify that it was the set, and not a clobber that
12264 modified the register.
12266 CC0 targets must be careful to maintain setter/user
12267 pairs. If we cannot delete the setter due to side
12268 effects, mark the user with an UNUSED note instead
12271 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12272 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12274 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12275 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12276 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12280 /* Move the notes and links of TEM elsewhere.
12281 This might delete other dead insns recursively.
12282 First set the pattern to something that won't use
12284 rtx old_notes
= REG_NOTES (tem
);
12286 PATTERN (tem
) = pc_rtx
;
12287 REG_NOTES (tem
) = NULL
;
12289 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
12290 NULL_RTX
, NULL_RTX
);
12291 distribute_links (LOG_LINKS (tem
));
12293 SET_INSN_DELETED (tem
);
12296 /* Delete the setter too. */
12299 PATTERN (cc0_setter
) = pc_rtx
;
12300 old_notes
= REG_NOTES (cc0_setter
);
12301 REG_NOTES (cc0_setter
) = NULL
;
12303 distribute_notes (old_notes
, cc0_setter
,
12304 cc0_setter
, NULL_RTX
,
12305 NULL_RTX
, NULL_RTX
);
12306 distribute_links (LOG_LINKS (cc0_setter
));
12308 SET_INSN_DELETED (cc0_setter
);
12314 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12316 /* If there isn't already a REG_UNUSED note, put one
12317 here. Do not place a REG_DEAD note, even if
12318 the register is also used here; that would not
12319 match the algorithm used in lifetime analysis
12320 and can cause the consistency check in the
12321 scheduler to fail. */
12322 if (! find_regno_note (tem
, REG_UNUSED
,
12323 REGNO (XEXP (note
, 0))))
12328 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12330 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12334 /* If we are doing a 3->2 combination, and we have a
12335 register which formerly died in i3 and was not used
12336 by i2, which now no longer dies in i3 and is used in
12337 i2 but does not die in i2, and place is between i2
12338 and i3, then we may need to move a link from place to
12340 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12341 && INSN_CUID (place
) > INSN_CUID (i2
)
12343 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12344 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12346 rtx links
= LOG_LINKS (place
);
12347 LOG_LINKS (place
) = 0;
12348 distribute_links (links
);
12353 if (tem
== BB_HEAD (bb
))
12357 /* We haven't found an insn for the death note and it
12358 is still a REG_DEAD note, but we have hit the beginning
12359 of the block. If the existing life info says the reg
12360 was dead, there's nothing left to do. Otherwise, we'll
12361 need to do a global life update after combine. */
12362 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12363 && REGNO_REG_SET_P (bb
->il
.rtl
->global_live_at_start
,
12364 REGNO (XEXP (note
, 0))))
12365 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12368 /* If the register is set or already dead at PLACE, we needn't do
12369 anything with this note if it is still a REG_DEAD note.
12370 We check here if it is set at all, not if is it totally replaced,
12371 which is what `dead_or_set_p' checks, so also check for it being
12374 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12376 unsigned int regno
= REGNO (XEXP (note
, 0));
12378 /* Similarly, if the instruction on which we want to place
12379 the note is a noop, we'll need do a global live update
12380 after we remove them in delete_noop_moves. */
12381 if (noop_move_p (place
))
12382 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12384 if (dead_or_set_p (place
, XEXP (note
, 0))
12385 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12387 /* Unless the register previously died in PLACE, clear
12388 last_death. [I no longer understand why this is
12390 if (reg_stat
[regno
].last_death
!= place
)
12391 reg_stat
[regno
].last_death
= 0;
12395 reg_stat
[regno
].last_death
= place
;
12397 /* If this is a death note for a hard reg that is occupying
12398 multiple registers, ensure that we are still using all
12399 parts of the object. If we find a piece of the object
12400 that is unused, we must arrange for an appropriate REG_DEAD
12401 note to be added for it. However, we can't just emit a USE
12402 and tag the note to it, since the register might actually
12403 be dead; so we recourse, and the recursive call then finds
12404 the previous insn that used this register. */
12406 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12407 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12409 unsigned int endregno
12410 = regno
+ hard_regno_nregs
[regno
]
12411 [GET_MODE (XEXP (note
, 0))];
12415 for (i
= regno
; i
< endregno
; i
++)
12416 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12417 && ! find_regno_fusage (place
, USE
, i
))
12418 || dead_or_set_regno_p (place
, i
))
12423 /* Put only REG_DEAD notes for pieces that are
12424 not already dead or set. */
12426 for (i
= regno
; i
< endregno
;
12427 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12429 rtx piece
= regno_reg_rtx
[i
];
12430 basic_block bb
= this_basic_block
;
12432 if (! dead_or_set_p (place
, piece
)
12433 && ! reg_bitfield_target_p (piece
,
12437 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12439 distribute_notes (new_note
, place
, place
,
12440 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12442 else if (! refers_to_regno_p (i
, i
+ 1,
12443 PATTERN (place
), 0)
12444 && ! find_regno_fusage (place
, USE
, i
))
12445 for (tem
= PREV_INSN (place
); ;
12446 tem
= PREV_INSN (tem
))
12448 if (! INSN_P (tem
))
12450 if (tem
== BB_HEAD (bb
))
12452 SET_BIT (refresh_blocks
,
12453 this_basic_block
->index
);
12458 if (dead_or_set_p (tem
, piece
)
12459 || reg_bitfield_target_p (piece
,
12463 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12478 /* Any other notes should not be present at this point in the
12480 gcc_unreachable ();
12485 XEXP (note
, 1) = REG_NOTES (place
);
12486 REG_NOTES (place
) = note
;
12488 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12489 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12490 && REG_P (XEXP (note
, 0)))
12491 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12495 if ((REG_NOTE_KIND (note
) == REG_DEAD
12496 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12497 && REG_P (XEXP (note
, 0)))
12498 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12500 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12501 REG_NOTE_KIND (note
),
12503 REG_NOTES (place2
));
12508 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12509 I3, I2, and I1 to new locations. This is also called to add a link
12510 pointing at I3 when I3's destination is changed. */
12513 distribute_links (rtx links
)
12515 rtx link
, next_link
;
12517 for (link
= links
; link
; link
= next_link
)
12523 next_link
= XEXP (link
, 1);
12525 /* If the insn that this link points to is a NOTE or isn't a single
12526 set, ignore it. In the latter case, it isn't clear what we
12527 can do other than ignore the link, since we can't tell which
12528 register it was for. Such links wouldn't be used by combine
12531 It is not possible for the destination of the target of the link to
12532 have been changed by combine. The only potential of this is if we
12533 replace I3, I2, and I1 by I3 and I2. But in that case the
12534 destination of I2 also remains unchanged. */
12536 if (NOTE_P (XEXP (link
, 0))
12537 || (set
= single_set (XEXP (link
, 0))) == 0)
12540 reg
= SET_DEST (set
);
12541 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12542 || GET_CODE (reg
) == STRICT_LOW_PART
)
12543 reg
= XEXP (reg
, 0);
12545 /* A LOG_LINK is defined as being placed on the first insn that uses
12546 a register and points to the insn that sets the register. Start
12547 searching at the next insn after the target of the link and stop
12548 when we reach a set of the register or the end of the basic block.
12550 Note that this correctly handles the link that used to point from
12551 I3 to I2. Also note that not much searching is typically done here
12552 since most links don't point very far away. */
12554 for (insn
= NEXT_INSN (XEXP (link
, 0));
12555 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12556 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12557 insn
= NEXT_INSN (insn
))
12558 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12560 if (reg_referenced_p (reg
, PATTERN (insn
)))
12564 else if (CALL_P (insn
)
12565 && find_reg_fusage (insn
, USE
, reg
))
12570 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12573 /* If we found a place to put the link, place it there unless there
12574 is already a link to the same insn as LINK at that point. */
12580 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12581 if (XEXP (link2
, 0) == XEXP (link
, 0))
12586 XEXP (link
, 1) = LOG_LINKS (place
);
12587 LOG_LINKS (place
) = link
;
12589 /* Set added_links_insn to the earliest insn we added a
12591 if (added_links_insn
== 0
12592 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12593 added_links_insn
= place
;
12599 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12600 Check whether the expression pointer to by LOC is a register or
12601 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12602 Otherwise return zero. */
12605 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12610 && (REG_P (x
) || MEM_P (x
))
12611 && ! reg_mentioned_p (x
, (rtx
) expr
))
12616 /* Check for any register or memory mentioned in EQUIV that is not
12617 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12618 of EXPR where some registers may have been replaced by constants. */
12621 unmentioned_reg_p (rtx equiv
, rtx expr
)
12623 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12626 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12629 insn_cuid (rtx insn
)
12631 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12632 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12633 insn
= NEXT_INSN (insn
);
12635 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12637 return INSN_CUID (insn
);
12641 dump_combine_stats (FILE *file
)
12645 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12646 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12650 dump_combine_total_stats (FILE *file
)
12654 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12655 total_attempts
, total_merges
, total_extras
, total_successes
);
12660 gate_handle_combine (void)
12662 return (optimize
> 0);
12665 /* Try combining insns through substitution. */
12667 rest_of_handle_combine (void)
12669 int rebuild_jump_labels_after_combine
12670 = combine_instructions (get_insns (), max_reg_num ());
12672 /* Combining insns may have turned an indirect jump into a
12673 direct jump. Rebuild the JUMP_LABEL fields of jumping
12675 if (rebuild_jump_labels_after_combine
)
12677 timevar_push (TV_JUMP
);
12678 rebuild_jump_labels (get_insns ());
12679 timevar_pop (TV_JUMP
);
12681 delete_dead_jumptables ();
12682 cleanup_cfg (CLEANUP_EXPENSIVE
| CLEANUP_UPDATE_LIFE
);
12686 struct tree_opt_pass pass_combine
=
12688 "combine", /* name */
12689 gate_handle_combine
, /* gate */
12690 rest_of_handle_combine
, /* execute */
12693 0, /* static_pass_number */
12694 TV_COMBINE
, /* tv_id */
12695 0, /* properties_required */
12696 0, /* properties_provided */
12697 0, /* properties_destroyed */
12698 0, /* todo_flags_start */
12700 TODO_ggc_collect
, /* todo_flags_finish */