1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* Basic block in which we are performing combines. */
306 static basic_block this_basic_block
;
307 static bool optimize_this_for_speed_p
;
310 /* Length of the currently allocated uid_insn_cost array. */
312 static int max_uid_known
;
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
317 static int *uid_insn_cost
;
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
325 struct insn_link
*next
;
328 static struct insn_link
**uid_log_links
;
331 insn_uid_check (const_rtx insn
)
333 int uid
= INSN_UID (insn
);
334 gcc_checking_assert (uid
<= max_uid_known
);
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
346 static struct obstack insn_link_obstack
;
348 /* Allocate a link. */
350 static inline struct insn_link
*
351 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
354 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
355 sizeof (struct insn_link
));
362 /* Incremented for each basic block. */
364 static int label_tick
;
366 /* Reset to label_tick for each extended basic block in scanning order. */
368 static int label_tick_ebb_start
;
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
373 static machine_mode nonzero_bits_mode
;
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
381 static int nonzero_sign_valid
;
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
387 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
393 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
394 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
407 rtx_insn
*other_insn
;
410 static struct undobuf undobuf
;
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
415 static int n_occurrences
;
417 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
419 unsigned HOST_WIDE_INT
,
420 unsigned HOST_WIDE_INT
*);
421 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
423 unsigned int, unsigned int *);
424 static void do_SUBST (rtx
*, rtx
);
425 static void do_SUBST_INT (int *, int);
426 static void init_reg_last (void);
427 static void setup_incoming_promotions (rtx_insn
*);
428 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
429 static int cant_combine_insn_p (rtx_insn
*);
430 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
431 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
432 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
433 static int contains_muldiv (rtx
);
434 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
436 static void undo_all (void);
437 static void undo_commit (void);
438 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
439 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
440 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
441 static rtx
simplify_if_then_else (rtx
);
442 static rtx
simplify_set (rtx
);
443 static rtx
simplify_logical (rtx
);
444 static rtx
expand_compound_operation (rtx
);
445 static const_rtx
expand_field_assignment (const_rtx
);
446 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
447 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
448 static rtx
extract_left_shift (rtx
, int);
449 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
450 unsigned HOST_WIDE_INT
*);
451 static rtx
canon_reg_for_combine (rtx
, rtx
);
452 static rtx
force_to_mode (rtx
, machine_mode
,
453 unsigned HOST_WIDE_INT
, int);
454 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
455 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
456 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
457 static rtx
make_field_assignment (rtx
);
458 static rtx
apply_distributive_law (rtx
);
459 static rtx
distribute_and_simplify_rtx (rtx
, int);
460 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
461 unsigned HOST_WIDE_INT
);
462 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
463 unsigned HOST_WIDE_INT
);
464 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
465 HOST_WIDE_INT
, machine_mode
, int *);
466 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
467 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
469 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
470 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
471 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
473 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
474 static void update_table_tick (rtx
);
475 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
476 static void check_promoted_subreg (rtx_insn
*, rtx
);
477 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
478 static void record_dead_and_set_regs (rtx_insn
*);
479 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
480 static rtx
get_last_value (const_rtx
);
481 static int use_crosses_set_p (const_rtx
, int);
482 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
483 static int reg_dead_at_p (rtx
, rtx_insn
*);
484 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
485 static int reg_bitfield_target_p (rtx
, rtx
);
486 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
487 static void distribute_links (struct insn_link
*);
488 static void mark_used_regs_combine (rtx
);
489 static void record_promoted_value (rtx_insn
*, rtx
);
490 static bool unmentioned_reg_p (rtx
, rtx
);
491 static void record_truncated_values (rtx
*, void *);
492 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
493 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
514 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
520 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
521 bool op0_preserve_value
)
523 int code_int
= (int)*code
;
524 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
525 *code
= (enum rtx_code
)code_int
;
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
535 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
540 ret
= split_insns (pattern
, insn
);
541 nregs
= max_reg_num ();
542 if (nregs
> reg_stat
.length ())
543 reg_stat
.safe_grow_cleared (nregs
);
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
554 find_single_use_1 (rtx dest
, rtx
*loc
)
557 enum rtx_code code
= GET_CODE (x
);
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
577 if (GET_CODE (SET_DEST (x
)) != CC0
578 && GET_CODE (SET_DEST (x
)) != PC
579 && !REG_P (SET_DEST (x
))
580 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
581 && REG_P (SUBREG_REG (SET_DEST (x
)))
582 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
583 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
584 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
585 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_rtx_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_rtx_costs. */
892 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
895 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
896 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
897 ? new_i2_cost
+ new_i3_cost
: 0;
901 new_cost
= new_i3_cost
;
905 if (undobuf
.other_insn
)
907 int old_other_cost
, new_other_cost
;
909 old_other_cost
= INSN_COST (undobuf
.other_insn
);
910 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
911 if (old_other_cost
> 0 && new_other_cost
> 0)
913 old_cost
+= old_other_cost
;
914 new_cost
+= new_other_cost
;
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
922 int reject
= old_cost
> 0 && new_cost
> old_cost
;
926 fprintf (dump_file
, "%s combination of insns ",
927 reject
? "rejecting" : "allowing");
929 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
930 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
931 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
932 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
934 fprintf (dump_file
, "original costs ");
936 fprintf (dump_file
, "%d + ", i0_cost
);
937 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
938 fprintf (dump_file
, "%d + ", i1_cost
);
939 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
942 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
943 new_i2_cost
, new_i3_cost
, new_cost
);
945 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
951 /* Update the uid_insn_cost array with the replacement costs. */
952 INSN_COST (i2
) = new_i2_cost
;
953 INSN_COST (i3
) = new_i3_cost
;
965 /* Delete any insns that copy a register to itself. */
968 delete_noop_moves (void)
970 rtx_insn
*insn
, *next
;
973 FOR_EACH_BB_FN (bb
, cfun
)
975 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
977 next
= NEXT_INSN (insn
);
978 if (INSN_P (insn
) && noop_move_p (insn
))
981 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
983 delete_insn_and_edges (insn
);
990 /* Return false if we do not want to (or cannot) combine DEF. */
992 can_combine_def_p (df_ref def
)
994 /* Do not consider if it is pre/post modification in MEM. */
995 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
998 unsigned int regno
= DF_REF_REGNO (def
);
1000 /* Do not combine frame pointer adjustments. */
1001 if ((regno
== FRAME_POINTER_REGNUM
1002 && (!reload_completed
|| frame_pointer_needed
))
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 && regno
== HARD_FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1007 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1013 /* Return false if we do not want to (or cannot) combine USE. */
1015 can_combine_use_p (df_ref use
)
1017 /* Do not consider the usage of the stack pointer by function call. */
1018 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1024 /* Fill in log links field for all insns. */
1027 create_log_links (void)
1030 rtx_insn
**next_use
;
1034 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1045 FOR_EACH_BB_FN (bb
, cfun
)
1047 FOR_BB_INSNS_REVERSE (bb
, insn
)
1049 if (!NONDEBUG_INSN_P (insn
))
1052 /* Log links are created only once. */
1053 gcc_assert (!LOG_LINKS (insn
));
1055 FOR_EACH_INSN_DEF (def
, insn
)
1057 unsigned int regno
= DF_REF_REGNO (def
);
1060 if (!next_use
[regno
])
1063 if (!can_combine_def_p (def
))
1066 use_insn
= next_use
[regno
];
1067 next_use
[regno
] = NULL
;
1069 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1079 if (regno
< FIRST_PSEUDO_REGISTER
1080 && asm_noperands (PATTERN (use_insn
)) >= 0)
1083 /* Don't add duplicate links between instructions. */
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, use_insn
)
1086 if (insn
== links
->insn
&& regno
== links
->regno
)
1090 LOG_LINKS (use_insn
)
1091 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1094 FOR_EACH_INSN_USE (use
, insn
)
1095 if (can_combine_use_p (use
))
1096 next_use
[DF_REF_REGNO (use
)] = insn
;
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1111 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1113 struct insn_link
*links
;
1114 FOR_EACH_LOG_LINK (links
, b
)
1115 if (links
->insn
== a
)
1117 if (HAVE_cc0
&& sets_cc0_p (a
))
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1128 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1130 rtx_insn
*insn
, *next
;
1132 struct insn_link
*links
, *nextlinks
;
1134 basic_block last_bb
;
1136 int new_direct_jump_p
= 0;
1138 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1139 first
= NEXT_INSN (first
);
1143 combine_attempts
= 0;
1146 combine_successes
= 0;
1148 rtl_hooks
= combine_rtl_hooks
;
1150 reg_stat
.safe_grow_cleared (nregs
);
1152 init_recog_no_volatile ();
1154 /* Allocate array for insn info. */
1155 max_uid_known
= get_max_uid ();
1156 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1157 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1158 gcc_obstack_init (&insn_link_obstack
);
1160 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1165 nonzero_sign_valid
= 0;
1166 label_tick
= label_tick_ebb_start
= 1;
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1175 setup_incoming_promotions (first
);
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1178 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1180 create_log_links ();
1181 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1183 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1188 if (!single_pred_p (this_basic_block
)
1189 || single_pred (this_basic_block
) != last_bb
)
1190 label_tick_ebb_start
= label_tick
;
1191 last_bb
= this_basic_block
;
1193 FOR_BB_INSNS (this_basic_block
, insn
)
1194 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1198 subst_low_luid
= DF_INSN_LUID (insn
);
1201 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1203 record_dead_and_set_regs (insn
);
1206 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1207 if (REG_NOTE_KIND (links
) == REG_INC
)
1208 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1211 /* Record the current insn_rtx_cost of this instruction. */
1212 if (NONJUMP_INSN_P (insn
))
1213 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1214 optimize_this_for_speed_p
);
1217 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1218 dump_insn_slim (dump_file
, insn
);
1223 nonzero_sign_valid
= 1;
1225 /* Now scan all the insns in forward order. */
1226 label_tick
= label_tick_ebb_start
= 1;
1228 setup_incoming_promotions (first
);
1229 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1230 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1232 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1234 rtx_insn
*last_combined_insn
= NULL
;
1235 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1240 if (!single_pred_p (this_basic_block
)
1241 || single_pred (this_basic_block
) != last_bb
)
1242 label_tick_ebb_start
= label_tick
;
1243 last_bb
= this_basic_block
;
1245 rtl_profile_for_bb (this_basic_block
);
1246 for (insn
= BB_HEAD (this_basic_block
);
1247 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1248 insn
= next
? next
: NEXT_INSN (insn
))
1251 if (!NONDEBUG_INSN_P (insn
))
1254 while (last_combined_insn
1255 && (!NONDEBUG_INSN_P (last_combined_insn
)
1256 || last_combined_insn
->deleted ()))
1257 last_combined_insn
= PREV_INSN (last_combined_insn
);
1258 if (last_combined_insn
== NULL_RTX
1259 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1260 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1261 last_combined_insn
= insn
;
1263 /* See if we know about function return values before this
1264 insn based upon SUBREG flags. */
1265 check_promoted_subreg (insn
, PATTERN (insn
));
1267 /* See if we can find hardregs and subreg of pseudos in
1268 narrower modes. This could help turning TRUNCATEs
1270 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1272 /* Try this insn with each insn it links back to. */
1274 FOR_EACH_LOG_LINK (links
, insn
)
1275 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1276 NULL
, &new_direct_jump_p
,
1277 last_combined_insn
)) != 0)
1279 statistics_counter_event (cfun
, "two-insn combine", 1);
1283 /* Try each sequence of three linked insns ending with this one. */
1285 if (max_combine
>= 3)
1286 FOR_EACH_LOG_LINK (links
, insn
)
1288 rtx_insn
*link
= links
->insn
;
1290 /* If the linked insn has been replaced by a note, then there
1291 is no point in pursuing this chain any further. */
1295 FOR_EACH_LOG_LINK (nextlinks
, link
)
1296 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1297 NULL
, &new_direct_jump_p
,
1298 last_combined_insn
)) != 0)
1300 statistics_counter_event (cfun
, "three-insn combine", 1);
1305 /* Try to combine a jump insn that uses CC0
1306 with a preceding insn that sets CC0, and maybe with its
1307 logical predecessor as well.
1308 This is how we make decrement-and-branch insns.
1309 We need this special code because data flow connections
1310 via CC0 do not get entered in LOG_LINKS. */
1314 && (prev
= prev_nonnote_insn (insn
)) != 0
1315 && NONJUMP_INSN_P (prev
)
1316 && sets_cc0_p (PATTERN (prev
)))
1318 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1320 last_combined_insn
)) != 0)
1323 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1324 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1325 NULL
, &new_direct_jump_p
,
1326 last_combined_insn
)) != 0)
1330 /* Do the same for an insn that explicitly references CC0. */
1331 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1332 && (prev
= prev_nonnote_insn (insn
)) != 0
1333 && NONJUMP_INSN_P (prev
)
1334 && sets_cc0_p (PATTERN (prev
))
1335 && GET_CODE (PATTERN (insn
)) == SET
1336 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1338 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1340 last_combined_insn
)) != 0)
1343 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1344 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1345 NULL
, &new_direct_jump_p
,
1346 last_combined_insn
)) != 0)
1350 /* Finally, see if any of the insns that this insn links to
1351 explicitly references CC0. If so, try this insn, that insn,
1352 and its predecessor if it sets CC0. */
1355 FOR_EACH_LOG_LINK (links
, insn
)
1356 if (NONJUMP_INSN_P (links
->insn
)
1357 && GET_CODE (PATTERN (links
->insn
)) == SET
1358 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1359 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1360 && NONJUMP_INSN_P (prev
)
1361 && sets_cc0_p (PATTERN (prev
))
1362 && (next
= try_combine (insn
, links
->insn
,
1363 prev
, NULL
, &new_direct_jump_p
,
1364 last_combined_insn
)) != 0)
1368 /* Try combining an insn with two different insns whose results it
1370 if (max_combine
>= 3)
1371 FOR_EACH_LOG_LINK (links
, insn
)
1372 for (nextlinks
= links
->next
; nextlinks
;
1373 nextlinks
= nextlinks
->next
)
1374 if ((next
= try_combine (insn
, links
->insn
,
1375 nextlinks
->insn
, NULL
,
1377 last_combined_insn
)) != 0)
1380 statistics_counter_event (cfun
, "three-insn combine", 1);
1384 /* Try four-instruction combinations. */
1385 if (max_combine
>= 4)
1386 FOR_EACH_LOG_LINK (links
, insn
)
1388 struct insn_link
*next1
;
1389 rtx_insn
*link
= links
->insn
;
1391 /* If the linked insn has been replaced by a note, then there
1392 is no point in pursuing this chain any further. */
1396 FOR_EACH_LOG_LINK (next1
, link
)
1398 rtx_insn
*link1
= next1
->insn
;
1401 /* I0 -> I1 -> I2 -> I3. */
1402 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1403 if ((next
= try_combine (insn
, link
, link1
,
1406 last_combined_insn
)) != 0)
1408 statistics_counter_event (cfun
, "four-insn combine", 1);
1411 /* I0, I1 -> I2, I2 -> I3. */
1412 for (nextlinks
= next1
->next
; nextlinks
;
1413 nextlinks
= nextlinks
->next
)
1414 if ((next
= try_combine (insn
, link
, link1
,
1417 last_combined_insn
)) != 0)
1419 statistics_counter_event (cfun
, "four-insn combine", 1);
1424 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1426 rtx_insn
*link1
= next1
->insn
;
1429 /* I0 -> I2; I1, I2 -> I3. */
1430 FOR_EACH_LOG_LINK (nextlinks
, link
)
1431 if ((next
= try_combine (insn
, link
, link1
,
1434 last_combined_insn
)) != 0)
1436 statistics_counter_event (cfun
, "four-insn combine", 1);
1439 /* I0 -> I1; I1, I2 -> I3. */
1440 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1441 if ((next
= try_combine (insn
, link
, link1
,
1444 last_combined_insn
)) != 0)
1446 statistics_counter_event (cfun
, "four-insn combine", 1);
1452 /* Try this insn with each REG_EQUAL note it links back to. */
1453 FOR_EACH_LOG_LINK (links
, insn
)
1456 rtx_insn
*temp
= links
->insn
;
1457 if ((set
= single_set (temp
)) != 0
1458 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1459 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1460 /* Avoid using a register that may already been marked
1461 dead by an earlier instruction. */
1462 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1463 && (GET_MODE (note
) == VOIDmode
1464 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1465 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1466 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1467 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1468 == GET_MODE (note
))))))
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1473 rtx orig_src
= SET_SRC (set
);
1474 rtx orig_dest
= SET_DEST (set
);
1475 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1476 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1477 SET_SRC (set
) = note
;
1479 i2mod_old_rhs
= copy_rtx (orig_src
);
1480 i2mod_new_rhs
= copy_rtx (note
);
1481 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1483 last_combined_insn
);
1487 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1490 SET_SRC (set
) = orig_src
;
1491 SET_DEST (set
) = orig_dest
;
1496 record_dead_and_set_regs (insn
);
1503 default_rtl_profile ();
1505 new_direct_jump_p
|= purge_all_dead_edges ();
1506 delete_noop_moves ();
1509 obstack_free (&insn_link_obstack
, NULL
);
1510 free (uid_log_links
);
1511 free (uid_insn_cost
);
1512 reg_stat
.release ();
1515 struct undo
*undo
, *next
;
1516 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1524 total_attempts
+= combine_attempts
;
1525 total_merges
+= combine_merges
;
1526 total_extras
+= combine_extras
;
1527 total_successes
+= combine_successes
;
1529 nonzero_sign_valid
= 0;
1530 rtl_hooks
= general_rtl_hooks
;
1532 /* Make recognizer allow volatile MEMs again. */
1535 return new_direct_jump_p
;
1538 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1541 init_reg_last (void)
1546 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1547 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1550 /* Set up any promoted values for incoming argument registers. */
1553 setup_incoming_promotions (rtx_insn
*first
)
1556 bool strictly_local
= false;
1558 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1559 arg
= DECL_CHAIN (arg
))
1561 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1563 machine_mode mode1
, mode2
, mode3
, mode4
;
1565 /* Only continue if the incoming argument is in a register. */
1569 /* Determine, if possible, whether all call sites of the current
1570 function lie within the current compilation unit. (This does
1571 take into account the exporting of a function via taking its
1572 address, and so forth.) */
1573 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1575 /* The mode and signedness of the argument before any promotions happen
1576 (equal to the mode of the pseudo holding it at that stage). */
1577 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1578 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1580 /* The mode and signedness of the argument after any source language and
1581 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1582 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1583 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1585 /* The mode and signedness of the argument as it is actually passed,
1586 see assign_parm_setup_reg in function.c. */
1587 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1588 TREE_TYPE (cfun
->decl
), 0);
1590 /* The mode of the register in which the argument is being passed. */
1591 mode4
= GET_MODE (reg
);
1593 /* Eliminate sign extensions in the callee when:
1594 (a) A mode promotion has occurred; */
1597 /* (b) The mode of the register is the same as the mode of
1598 the argument as it is passed; */
1601 /* (c) There's no language level extension; */
1604 /* (c.1) All callers are from the current compilation unit. If that's
1605 the case we don't have to rely on an ABI, we only have to know
1606 what we're generating right now, and we know that we will do the
1607 mode1 to mode2 promotion with the given sign. */
1608 else if (!strictly_local
)
1610 /* (c.2) The combination of the two promotions is useful. This is
1611 true when the signs match, or if the first promotion is unsigned.
1612 In the later case, (sign_extend (zero_extend x)) is the same as
1613 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1619 /* Record that the value was promoted from mode1 to mode3,
1620 so that any sign extension at the head of the current
1621 function may be eliminated. */
1622 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1623 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1624 record_value_for_reg (reg
, first
, x
);
1628 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1629 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1630 because some machines (maybe most) will actually do the sign-extension and
1631 this is the conservative approach.
1633 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1637 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1639 if (GET_MODE_PRECISION (mode
) < prec
1640 && CONST_INT_P (src
)
1642 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1643 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1648 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1652 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1655 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1656 unsigned HOST_WIDE_INT bits
= 0;
1657 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1658 unsigned int num
= 0;
1661 reg_equal
= XEXP (reg_equal_note
, 0);
1663 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1665 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1667 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1670 /* Don't call nonzero_bits if it cannot change anything. */
1671 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1673 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1674 if (reg_equal
&& bits
)
1675 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1676 rsp
->nonzero_bits
|= bits
;
1679 /* Don't call num_sign_bit_copies if it cannot change anything. */
1680 if (rsp
->sign_bit_copies
!= 1)
1682 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1683 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1685 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1686 if (num
== 0 || numeq
> num
)
1689 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1690 rsp
->sign_bit_copies
= num
;
1694 /* Called via note_stores. If X is a pseudo that is narrower than
1695 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1697 If we are setting only a portion of X and we can't figure out what
1698 portion, assume all bits will be used since we don't know what will
1701 Similarly, set how many bits of X are known to be copies of the sign bit
1702 at all locations in the function. This is the smallest number implied
1706 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1708 rtx_insn
*insn
= (rtx_insn
*) data
;
1711 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1712 /* If this register is undefined at the start of the file, we can't
1713 say what its contents were. */
1714 && ! REGNO_REG_SET_P
1715 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1716 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1718 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1720 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1722 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1723 rsp
->sign_bit_copies
= 1;
1727 /* If this register is being initialized using itself, and the
1728 register is uninitialized in this basic block, and there are
1729 no LOG_LINKS which set the register, then part of the
1730 register is uninitialized. In that case we can't assume
1731 anything about the number of nonzero bits.
1733 ??? We could do better if we checked this in
1734 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1735 could avoid making assumptions about the insn which initially
1736 sets the register, while still using the information in other
1737 insns. We would have to be careful to check every insn
1738 involved in the combination. */
1741 && reg_referenced_p (x
, PATTERN (insn
))
1742 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1745 struct insn_link
*link
;
1747 FOR_EACH_LOG_LINK (link
, insn
)
1748 if (dead_or_set_p (link
->insn
, x
))
1752 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1753 rsp
->sign_bit_copies
= 1;
1758 /* If this is a complex assignment, see if we can convert it into a
1759 simple assignment. */
1760 set
= expand_field_assignment (set
);
1762 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1763 set what we know about X. */
1765 if (SET_DEST (set
) == x
1766 || (paradoxical_subreg_p (SET_DEST (set
))
1767 && SUBREG_REG (SET_DEST (set
)) == x
))
1768 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1771 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1772 rsp
->sign_bit_copies
= 1;
1777 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1778 optionally insns that were previously combined into I3 or that will be
1779 combined into the merger of INSN and I3. The order is PRED, PRED2,
1780 INSN, SUCC, SUCC2, I3.
1782 Return 0 if the combination is not allowed for any reason.
1784 If the combination is allowed, *PDEST will be set to the single
1785 destination of INSN and *PSRC to the single source, and this function
1789 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1790 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1791 rtx
*pdest
, rtx
*psrc
)
1798 bool all_adjacent
= true;
1799 int (*is_volatile_p
) (const_rtx
);
1805 if (next_active_insn (succ2
) != i3
)
1806 all_adjacent
= false;
1807 if (next_active_insn (succ
) != succ2
)
1808 all_adjacent
= false;
1810 else if (next_active_insn (succ
) != i3
)
1811 all_adjacent
= false;
1812 if (next_active_insn (insn
) != succ
)
1813 all_adjacent
= false;
1815 else if (next_active_insn (insn
) != i3
)
1816 all_adjacent
= false;
1818 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1819 or a PARALLEL consisting of such a SET and CLOBBERs.
1821 If INSN has CLOBBER parallel parts, ignore them for our processing.
1822 By definition, these happen during the execution of the insn. When it
1823 is merged with another insn, all bets are off. If they are, in fact,
1824 needed and aren't also supplied in I3, they may be added by
1825 recog_for_combine. Otherwise, it won't match.
1827 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1830 Get the source and destination of INSN. If more than one, can't
1833 if (GET_CODE (PATTERN (insn
)) == SET
)
1834 set
= PATTERN (insn
);
1835 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1836 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1838 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1840 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1842 switch (GET_CODE (elt
))
1844 /* This is important to combine floating point insns
1845 for the SH4 port. */
1847 /* Combining an isolated USE doesn't make sense.
1848 We depend here on combinable_i3pat to reject them. */
1849 /* The code below this loop only verifies that the inputs of
1850 the SET in INSN do not change. We call reg_set_between_p
1851 to verify that the REG in the USE does not change between
1853 If the USE in INSN was for a pseudo register, the matching
1854 insn pattern will likely match any register; combining this
1855 with any other USE would only be safe if we knew that the
1856 used registers have identical values, or if there was
1857 something to tell them apart, e.g. different modes. For
1858 now, we forgo such complicated tests and simply disallow
1859 combining of USES of pseudo registers with any other USE. */
1860 if (REG_P (XEXP (elt
, 0))
1861 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1863 rtx i3pat
= PATTERN (i3
);
1864 int i
= XVECLEN (i3pat
, 0) - 1;
1865 unsigned int regno
= REGNO (XEXP (elt
, 0));
1869 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1871 if (GET_CODE (i3elt
) == USE
1872 && REG_P (XEXP (i3elt
, 0))
1873 && (REGNO (XEXP (i3elt
, 0)) == regno
1874 ? reg_set_between_p (XEXP (elt
, 0),
1875 PREV_INSN (insn
), i3
)
1876 : regno
>= FIRST_PSEUDO_REGISTER
))
1883 /* We can ignore CLOBBERs. */
1888 /* Ignore SETs whose result isn't used but not those that
1889 have side-effects. */
1890 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1891 && insn_nothrow_p (insn
)
1892 && !side_effects_p (elt
))
1895 /* If we have already found a SET, this is a second one and
1896 so we cannot combine with this insn. */
1904 /* Anything else means we can't combine. */
1910 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1911 so don't do anything with it. */
1912 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1921 /* The simplification in expand_field_assignment may call back to
1922 get_last_value, so set safe guard here. */
1923 subst_low_luid
= DF_INSN_LUID (insn
);
1925 set
= expand_field_assignment (set
);
1926 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1928 /* Do not eliminate user-specified register if it is in an
1929 asm input because we may break the register asm usage defined
1930 in GCC manual if allow to do so.
1931 Be aware that this may cover more cases than we expect but this
1932 should be harmless. */
1933 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1934 && extract_asm_operands (PATTERN (i3
)))
1937 /* Don't eliminate a store in the stack pointer. */
1938 if (dest
== stack_pointer_rtx
1939 /* Don't combine with an insn that sets a register to itself if it has
1940 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1941 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1942 /* Can't merge an ASM_OPERANDS. */
1943 || GET_CODE (src
) == ASM_OPERANDS
1944 /* Can't merge a function call. */
1945 || GET_CODE (src
) == CALL
1946 /* Don't eliminate a function call argument. */
1948 && (find_reg_fusage (i3
, USE
, dest
)
1950 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1951 && global_regs
[REGNO (dest
)])))
1952 /* Don't substitute into an incremented register. */
1953 || FIND_REG_INC_NOTE (i3
, dest
)
1954 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1955 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1956 /* Don't substitute into a non-local goto, this confuses CFG. */
1957 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1958 /* Make sure that DEST is not used after INSN but before SUCC, or
1959 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1962 && (reg_used_between_p (dest
, succ2
, i3
)
1963 || reg_used_between_p (dest
, succ
, succ2
)))
1964 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
1966 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1967 that case SUCC is not in the insn stream, so use SUCC2
1968 instead for this test. */
1969 && reg_used_between_p (dest
, insn
,
1971 && INSN_UID (succ
) == INSN_UID (succ2
)
1973 /* Make sure that the value that is to be substituted for the register
1974 does not use any registers whose values alter in between. However,
1975 If the insns are adjacent, a use can't cross a set even though we
1976 think it might (this can happen for a sequence of insns each setting
1977 the same destination; last_set of that register might point to
1978 a NOTE). If INSN has a REG_EQUIV note, the register is always
1979 equivalent to the memory so the substitution is valid even if there
1980 are intervening stores. Also, don't move a volatile asm or
1981 UNSPEC_VOLATILE across any other insns. */
1984 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1985 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1986 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1987 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1988 /* Don't combine across a CALL_INSN, because that would possibly
1989 change whether the life span of some REGs crosses calls or not,
1990 and it is a pain to update that information.
1991 Exception: if source is a constant, moving it later can't hurt.
1992 Accept that as a special case. */
1993 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1996 /* DEST must either be a REG or CC0. */
1999 /* If register alignment is being enforced for multi-word items in all
2000 cases except for parameters, it is possible to have a register copy
2001 insn referencing a hard register that is not allowed to contain the
2002 mode being copied and which would not be valid as an operand of most
2003 insns. Eliminate this problem by not combining with such an insn.
2005 Also, on some machines we don't want to extend the life of a hard
2009 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2010 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2011 /* Don't extend the life of a hard register unless it is
2012 user variable (if we have few registers) or it can't
2013 fit into the desired register (meaning something special
2015 Also avoid substituting a return register into I3, because
2016 reload can't handle a conflict with constraints of other
2018 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2019 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2022 else if (GET_CODE (dest
) != CC0
)
2026 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2027 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2028 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2030 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2032 /* If the clobber represents an earlyclobber operand, we must not
2033 substitute an expression containing the clobbered register.
2034 As we do not analyze the constraint strings here, we have to
2035 make the conservative assumption. However, if the register is
2036 a fixed hard reg, the clobber cannot represent any operand;
2037 we leave it up to the machine description to either accept or
2038 reject use-and-clobber patterns. */
2040 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2041 || !fixed_regs
[REGNO (reg
)])
2042 if (reg_overlap_mentioned_p (reg
, src
))
2046 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2047 or not), reject, unless nothing volatile comes between it and I3 */
2049 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2051 /* Make sure neither succ nor succ2 contains a volatile reference. */
2052 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2054 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2056 /* We'll check insns between INSN and I3 below. */
2059 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2060 to be an explicit register variable, and was chosen for a reason. */
2062 if (GET_CODE (src
) == ASM_OPERANDS
2063 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2066 /* If INSN contains volatile references (specifically volatile MEMs),
2067 we cannot combine across any other volatile references.
2068 Even if INSN doesn't contain volatile references, any intervening
2069 volatile insn might affect machine state. */
2071 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2075 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2076 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2079 /* If INSN contains an autoincrement or autodecrement, make sure that
2080 register is not used between there and I3, and not already used in
2081 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2082 Also insist that I3 not be a jump; if it were one
2083 and the incremented register were spilled, we would lose. */
2086 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2087 if (REG_NOTE_KIND (link
) == REG_INC
2089 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2090 || (pred
!= NULL_RTX
2091 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2092 || (pred2
!= NULL_RTX
2093 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2094 || (succ
!= NULL_RTX
2095 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2096 || (succ2
!= NULL_RTX
2097 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2098 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2101 /* Don't combine an insn that follows a CC0-setting insn.
2102 An insn that uses CC0 must not be separated from the one that sets it.
2103 We do, however, allow I2 to follow a CC0-setting insn if that insn
2104 is passed as I1; in that case it will be deleted also.
2105 We also allow combining in this case if all the insns are adjacent
2106 because that would leave the two CC0 insns adjacent as well.
2107 It would be more logical to test whether CC0 occurs inside I1 or I2,
2108 but that would be much slower, and this ought to be equivalent. */
2112 p
= prev_nonnote_insn (insn
);
2113 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2118 /* If we get here, we have passed all the tests and the combination is
2127 /* LOC is the location within I3 that contains its pattern or the component
2128 of a PARALLEL of the pattern. We validate that it is valid for combining.
2130 One problem is if I3 modifies its output, as opposed to replacing it
2131 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2132 doing so would produce an insn that is not equivalent to the original insns.
2136 (set (reg:DI 101) (reg:DI 100))
2137 (set (subreg:SI (reg:DI 101) 0) <foo>)
2139 This is NOT equivalent to:
2141 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2142 (set (reg:DI 101) (reg:DI 100))])
2144 Not only does this modify 100 (in which case it might still be valid
2145 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2147 We can also run into a problem if I2 sets a register that I1
2148 uses and I1 gets directly substituted into I3 (not via I2). In that
2149 case, we would be getting the wrong value of I2DEST into I3, so we
2150 must reject the combination. This case occurs when I2 and I1 both
2151 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2152 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2153 of a SET must prevent combination from occurring. The same situation
2154 can occur for I0, in which case I0_NOT_IN_SRC is set.
2156 Before doing the above check, we first try to expand a field assignment
2157 into a set of logical operations.
2159 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2160 we place a register that is both set and used within I3. If more than one
2161 such register is detected, we fail.
2163 Return 1 if the combination is valid, zero otherwise. */
2166 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2167 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2171 if (GET_CODE (x
) == SET
)
2174 rtx dest
= SET_DEST (set
);
2175 rtx src
= SET_SRC (set
);
2176 rtx inner_dest
= dest
;
2179 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2180 || GET_CODE (inner_dest
) == SUBREG
2181 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2182 inner_dest
= XEXP (inner_dest
, 0);
2184 /* Check for the case where I3 modifies its output, as discussed
2185 above. We don't want to prevent pseudos from being combined
2186 into the address of a MEM, so only prevent the combination if
2187 i1 or i2 set the same MEM. */
2188 if ((inner_dest
!= dest
&&
2189 (!MEM_P (inner_dest
)
2190 || rtx_equal_p (i2dest
, inner_dest
)
2191 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2192 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2193 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2194 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2195 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2197 /* This is the same test done in can_combine_p except we can't test
2198 all_adjacent; we don't have to, since this instruction will stay
2199 in place, thus we are not considering increasing the lifetime of
2202 Also, if this insn sets a function argument, combining it with
2203 something that might need a spill could clobber a previous
2204 function argument; the all_adjacent test in can_combine_p also
2205 checks this; here, we do a more specific test for this case. */
2207 || (REG_P (inner_dest
)
2208 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2209 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2210 GET_MODE (inner_dest
))))
2211 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2212 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2215 /* If DEST is used in I3, it is being killed in this insn, so
2216 record that for later. We have to consider paradoxical
2217 subregs here, since they kill the whole register, but we
2218 ignore partial subregs, STRICT_LOW_PART, etc.
2219 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2220 STACK_POINTER_REGNUM, since these are always considered to be
2221 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2223 if (GET_CODE (subdest
) == SUBREG
2224 && (GET_MODE_SIZE (GET_MODE (subdest
))
2225 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2226 subdest
= SUBREG_REG (subdest
);
2229 && reg_referenced_p (subdest
, PATTERN (i3
))
2230 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2231 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2232 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2233 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2234 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2235 || ! fixed_regs
[REGNO (subdest
)]))
2236 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2238 if (*pi3dest_killed
)
2241 *pi3dest_killed
= subdest
;
2245 else if (GET_CODE (x
) == PARALLEL
)
2249 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2250 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2251 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2258 /* Return 1 if X is an arithmetic expression that contains a multiplication
2259 and division. We don't count multiplications by powers of two here. */
2262 contains_muldiv (rtx x
)
2264 switch (GET_CODE (x
))
2266 case MOD
: case DIV
: case UMOD
: case UDIV
:
2270 return ! (CONST_INT_P (XEXP (x
, 1))
2271 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2274 return contains_muldiv (XEXP (x
, 0))
2275 || contains_muldiv (XEXP (x
, 1));
2278 return contains_muldiv (XEXP (x
, 0));
2284 /* Determine whether INSN can be used in a combination. Return nonzero if
2285 not. This is used in try_combine to detect early some cases where we
2286 can't perform combinations. */
2289 cant_combine_insn_p (rtx_insn
*insn
)
2294 /* If this isn't really an insn, we can't do anything.
2295 This can occur when flow deletes an insn that it has merged into an
2296 auto-increment address. */
2297 if (!NONDEBUG_INSN_P (insn
))
2300 /* Never combine loads and stores involving hard regs that are likely
2301 to be spilled. The register allocator can usually handle such
2302 reg-reg moves by tying. If we allow the combiner to make
2303 substitutions of likely-spilled regs, reload might die.
2304 As an exception, we allow combinations involving fixed regs; these are
2305 not available to the register allocator so there's no risk involved. */
2307 set
= single_set (insn
);
2310 src
= SET_SRC (set
);
2311 dest
= SET_DEST (set
);
2312 if (GET_CODE (src
) == SUBREG
)
2313 src
= SUBREG_REG (src
);
2314 if (GET_CODE (dest
) == SUBREG
)
2315 dest
= SUBREG_REG (dest
);
2316 if (REG_P (src
) && REG_P (dest
)
2317 && ((HARD_REGISTER_P (src
)
2318 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2319 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2320 || (HARD_REGISTER_P (dest
)
2321 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2322 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2328 struct likely_spilled_retval_info
2330 unsigned regno
, nregs
;
2334 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2335 hard registers that are known to be written to / clobbered in full. */
2337 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2339 struct likely_spilled_retval_info
*const info
=
2340 (struct likely_spilled_retval_info
*) data
;
2341 unsigned regno
, nregs
;
2344 if (!REG_P (XEXP (set
, 0)))
2347 if (regno
>= info
->regno
+ info
->nregs
)
2349 nregs
= REG_NREGS (x
);
2350 if (regno
+ nregs
<= info
->regno
)
2352 new_mask
= (2U << (nregs
- 1)) - 1;
2353 if (regno
< info
->regno
)
2354 new_mask
>>= info
->regno
- regno
;
2356 new_mask
<<= regno
- info
->regno
;
2357 info
->mask
&= ~new_mask
;
2360 /* Return nonzero iff part of the return value is live during INSN, and
2361 it is likely spilled. This can happen when more than one insn is needed
2362 to copy the return value, e.g. when we consider to combine into the
2363 second copy insn for a complex value. */
2366 likely_spilled_retval_p (rtx_insn
*insn
)
2368 rtx_insn
*use
= BB_END (this_basic_block
);
2371 unsigned regno
, nregs
;
2372 /* We assume here that no machine mode needs more than
2373 32 hard registers when the value overlaps with a register
2374 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2376 struct likely_spilled_retval_info info
;
2378 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2380 reg
= XEXP (PATTERN (use
), 0);
2381 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2383 regno
= REGNO (reg
);
2384 nregs
= REG_NREGS (reg
);
2387 mask
= (2U << (nregs
- 1)) - 1;
2389 /* Disregard parts of the return value that are set later. */
2393 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2395 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2398 /* Check if any of the (probably) live return value registers is
2403 if ((mask
& 1 << nregs
)
2404 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2410 /* Adjust INSN after we made a change to its destination.
2412 Changing the destination can invalidate notes that say something about
2413 the results of the insn and a LOG_LINK pointing to the insn. */
2416 adjust_for_new_dest (rtx_insn
*insn
)
2418 /* For notes, be conservative and simply remove them. */
2419 remove_reg_equal_equiv_notes (insn
);
2421 /* The new insn will have a destination that was previously the destination
2422 of an insn just above it. Call distribute_links to make a LOG_LINK from
2423 the next use of that destination. */
2425 rtx set
= single_set (insn
);
2428 rtx reg
= SET_DEST (set
);
2430 while (GET_CODE (reg
) == ZERO_EXTRACT
2431 || GET_CODE (reg
) == STRICT_LOW_PART
2432 || GET_CODE (reg
) == SUBREG
)
2433 reg
= XEXP (reg
, 0);
2434 gcc_assert (REG_P (reg
));
2436 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2438 df_insn_rescan (insn
);
2441 /* Return TRUE if combine can reuse reg X in mode MODE.
2442 ADDED_SETS is nonzero if the original set is still required. */
2444 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2452 /* Allow hard registers if the new mode is legal, and occupies no more
2453 registers than the old mode. */
2454 if (regno
< FIRST_PSEUDO_REGISTER
)
2455 return (HARD_REGNO_MODE_OK (regno
, mode
)
2456 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2458 /* Or a pseudo that is only used once. */
2459 return (regno
< reg_n_sets_max
2460 && REG_N_SETS (regno
) == 1
2462 && !REG_USERVAR_P (x
));
2466 /* Check whether X, the destination of a set, refers to part of
2467 the register specified by REG. */
2470 reg_subword_p (rtx x
, rtx reg
)
2472 /* Check that reg is an integer mode register. */
2473 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2476 if (GET_CODE (x
) == STRICT_LOW_PART
2477 || GET_CODE (x
) == ZERO_EXTRACT
)
2480 return GET_CODE (x
) == SUBREG
2481 && SUBREG_REG (x
) == reg
2482 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2485 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2486 Note that the INSN should be deleted *after* removing dead edges, so
2487 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2488 but not for a (set (pc) (label_ref FOO)). */
2491 update_cfg_for_uncondjump (rtx_insn
*insn
)
2493 basic_block bb
= BLOCK_FOR_INSN (insn
);
2494 gcc_assert (BB_END (bb
) == insn
);
2496 purge_dead_edges (bb
);
2499 if (EDGE_COUNT (bb
->succs
) == 1)
2503 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2505 /* Remove barriers from the footer if there are any. */
2506 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2507 if (BARRIER_P (insn
))
2509 if (PREV_INSN (insn
))
2510 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2512 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2513 if (NEXT_INSN (insn
))
2514 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2516 else if (LABEL_P (insn
))
2521 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2522 by an arbitrary number of CLOBBERs. */
2524 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2526 if (GET_CODE (pat
) != PARALLEL
)
2529 int len
= XVECLEN (pat
, 0);
2534 for (i
= 0; i
< n
; i
++)
2535 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2536 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2538 for ( ; i
< len
; i
++)
2539 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2540 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2546 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2547 CLOBBERs), can be split into individual SETs in that order, without
2548 changing semantics. */
2550 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2552 if (!insn_nothrow_p (insn
))
2555 rtx pat
= PATTERN (insn
);
2558 for (i
= 0; i
< n
; i
++)
2560 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2563 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2565 for (j
= i
+ 1; j
< n
; j
++)
2566 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2573 /* Try to combine the insns I0, I1 and I2 into I3.
2574 Here I0, I1 and I2 appear earlier than I3.
2575 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2578 If we are combining more than two insns and the resulting insn is not
2579 recognized, try splitting it into two insns. If that happens, I2 and I3
2580 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2581 Otherwise, I0, I1 and I2 are pseudo-deleted.
2583 Return 0 if the combination does not work. Then nothing is changed.
2584 If we did the combination, return the insn at which combine should
2587 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2588 new direct jump instruction.
2590 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2591 been I3 passed to an earlier try_combine within the same basic
2595 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2596 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2598 /* New patterns for I3 and I2, respectively. */
2599 rtx newpat
, newi2pat
= 0;
2600 rtvec newpat_vec_with_clobbers
= 0;
2601 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2602 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2604 int added_sets_0
, added_sets_1
, added_sets_2
;
2605 /* Total number of SETs to put into I3. */
2607 /* Nonzero if I2's or I1's body now appears in I3. */
2608 int i2_is_used
= 0, i1_is_used
= 0;
2609 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2610 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2611 /* Contains I3 if the destination of I3 is used in its source, which means
2612 that the old life of I3 is being killed. If that usage is placed into
2613 I2 and not in I3, a REG_DEAD note must be made. */
2614 rtx i3dest_killed
= 0;
2615 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2616 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2617 /* Copy of SET_SRC of I1 and I0, if needed. */
2618 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2619 /* Set if I2DEST was reused as a scratch register. */
2620 bool i2scratch
= false;
2621 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2622 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2623 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2624 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2625 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2626 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2627 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2628 /* Notes that must be added to REG_NOTES in I3 and I2. */
2629 rtx new_i3_notes
, new_i2_notes
;
2630 /* Notes that we substituted I3 into I2 instead of the normal case. */
2631 int i3_subst_into_i2
= 0;
2632 /* Notes that I1, I2 or I3 is a MULT operation. */
2635 int changed_i3_dest
= 0;
2638 rtx_insn
*temp_insn
;
2640 struct insn_link
*link
;
2642 rtx new_other_notes
;
2645 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2647 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2650 /* Only try four-insn combinations when there's high likelihood of
2651 success. Look for simple insns, such as loads of constants or
2652 binary operations involving a constant. */
2660 if (!flag_expensive_optimizations
)
2663 for (i
= 0; i
< 4; i
++)
2665 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2666 rtx set
= single_set (insn
);
2670 src
= SET_SRC (set
);
2671 if (CONSTANT_P (src
))
2676 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2678 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2679 || GET_CODE (src
) == LSHIFTRT
)
2683 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2684 are likely manipulating its value. Ideally we'll be able to combine
2685 all four insns into a bitfield insertion of some kind.
2687 Note the source in I0 might be inside a sign/zero extension and the
2688 memory modes in I0 and I3 might be different. So extract the address
2689 from the destination of I3 and search for it in the source of I0.
2691 In the event that there's a match but the source/dest do not actually
2692 refer to the same memory, the worst that happens is we try some
2693 combinations that we wouldn't have otherwise. */
2694 if ((set0
= single_set (i0
))
2695 /* Ensure the source of SET0 is a MEM, possibly buried inside
2697 && (GET_CODE (SET_SRC (set0
)) == MEM
2698 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2699 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2700 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2701 && (set3
= single_set (i3
))
2702 /* Ensure the destination of SET3 is a MEM. */
2703 && GET_CODE (SET_DEST (set3
)) == MEM
2704 /* Would it be better to extract the base address for the MEM
2705 in SET3 and look for that? I don't have cases where it matters
2706 but I could envision such cases. */
2707 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2710 if (ngood
< 2 && nshift
< 2)
2714 /* Exit early if one of the insns involved can't be used for
2717 || (i1
&& CALL_P (i1
))
2718 || (i0
&& CALL_P (i0
))
2719 || cant_combine_insn_p (i3
)
2720 || cant_combine_insn_p (i2
)
2721 || (i1
&& cant_combine_insn_p (i1
))
2722 || (i0
&& cant_combine_insn_p (i0
))
2723 || likely_spilled_retval_p (i3
))
2727 undobuf
.other_insn
= 0;
2729 /* Reset the hard register usage information. */
2730 CLEAR_HARD_REG_SET (newpat_used_regs
);
2732 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2735 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2736 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2738 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2739 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2741 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2742 INSN_UID (i2
), INSN_UID (i3
));
2745 /* If multiple insns feed into one of I2 or I3, they can be in any
2746 order. To simplify the code below, reorder them in sequence. */
2747 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2749 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2751 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2754 added_links_insn
= 0;
2756 /* First check for one important special case that the code below will
2757 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2758 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2759 we may be able to replace that destination with the destination of I3.
2760 This occurs in the common code where we compute both a quotient and
2761 remainder into a structure, in which case we want to do the computation
2762 directly into the structure to avoid register-register copies.
2764 Note that this case handles both multiple sets in I2 and also cases
2765 where I2 has a number of CLOBBERs inside the PARALLEL.
2767 We make very conservative checks below and only try to handle the
2768 most common cases of this. For example, we only handle the case
2769 where I2 and I3 are adjacent to avoid making difficult register
2772 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2773 && REG_P (SET_SRC (PATTERN (i3
)))
2774 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2775 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2776 && GET_CODE (PATTERN (i2
)) == PARALLEL
2777 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2778 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2779 below would need to check what is inside (and reg_overlap_mentioned_p
2780 doesn't support those codes anyway). Don't allow those destinations;
2781 the resulting insn isn't likely to be recognized anyway. */
2782 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2783 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2784 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2785 SET_DEST (PATTERN (i3
)))
2786 && next_active_insn (i2
) == i3
)
2788 rtx p2
= PATTERN (i2
);
2790 /* Make sure that the destination of I3,
2791 which we are going to substitute into one output of I2,
2792 is not used within another output of I2. We must avoid making this:
2793 (parallel [(set (mem (reg 69)) ...)
2794 (set (reg 69) ...)])
2795 which is not well-defined as to order of actions.
2796 (Besides, reload can't handle output reloads for this.)
2798 The problem can also happen if the dest of I3 is a memory ref,
2799 if another dest in I2 is an indirect memory ref.
2801 Neither can this PARALLEL be an asm. We do not allow combining
2802 that usually (see can_combine_p), so do not here either. */
2804 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2806 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2807 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2808 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2809 SET_DEST (XVECEXP (p2
, 0, i
))))
2811 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2812 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2817 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2818 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2819 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2824 subst_low_luid
= DF_INSN_LUID (i2
);
2826 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2827 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2828 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2829 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2831 /* Replace the dest in I2 with our dest and make the resulting
2832 insn the new pattern for I3. Then skip to where we validate
2833 the pattern. Everything was set up above. */
2834 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2836 i3_subst_into_i2
= 1;
2837 goto validate_replacement
;
2841 /* If I2 is setting a pseudo to a constant and I3 is setting some
2842 sub-part of it to another constant, merge them by making a new
2845 && (temp_expr
= single_set (i2
)) != 0
2846 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2847 && GET_CODE (PATTERN (i3
)) == SET
2848 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2849 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2851 rtx dest
= SET_DEST (PATTERN (i3
));
2855 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2857 if (CONST_INT_P (XEXP (dest
, 1))
2858 && CONST_INT_P (XEXP (dest
, 2)))
2860 width
= INTVAL (XEXP (dest
, 1));
2861 offset
= INTVAL (XEXP (dest
, 2));
2862 dest
= XEXP (dest
, 0);
2863 if (BITS_BIG_ENDIAN
)
2864 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2869 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2870 dest
= XEXP (dest
, 0);
2871 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2877 /* If this is the low part, we're done. */
2878 if (subreg_lowpart_p (dest
))
2880 /* Handle the case where inner is twice the size of outer. */
2881 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2882 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2883 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2884 /* Otherwise give up for now. */
2891 rtx inner
= SET_SRC (PATTERN (i3
));
2892 rtx outer
= SET_SRC (temp_expr
);
2895 = wi::insert (rtx_mode_t (outer
, GET_MODE (SET_DEST (temp_expr
))),
2896 rtx_mode_t (inner
, GET_MODE (dest
)),
2901 subst_low_luid
= DF_INSN_LUID (i2
);
2902 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2903 i2dest
= SET_DEST (temp_expr
);
2904 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2906 /* Replace the source in I2 with the new constant and make the
2907 resulting insn the new pattern for I3. Then skip to where we
2908 validate the pattern. Everything was set up above. */
2909 SUBST (SET_SRC (temp_expr
),
2910 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2912 newpat
= PATTERN (i2
);
2914 /* The dest of I3 has been replaced with the dest of I2. */
2915 changed_i3_dest
= 1;
2916 goto validate_replacement
;
2920 /* If we have no I1 and I2 looks like:
2921 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2923 make up a dummy I1 that is
2926 (set (reg:CC X) (compare:CC Y (const_int 0)))
2928 (We can ignore any trailing CLOBBERs.)
2930 This undoes a previous combination and allows us to match a branch-and-
2933 if (!HAVE_cc0
&& i1
== 0
2934 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2935 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2937 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2938 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2939 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2940 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2941 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2942 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2944 /* We make I1 with the same INSN_UID as I2. This gives it
2945 the same DF_INSN_LUID for value tracking. Our fake I1 will
2946 never appear in the insn stream so giving it the same INSN_UID
2947 as I2 will not cause a problem. */
2949 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2950 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2952 INSN_UID (i1
) = INSN_UID (i2
);
2954 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2955 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2956 SET_DEST (PATTERN (i1
)));
2957 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2958 SUBST_LINK (LOG_LINKS (i2
),
2959 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2962 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2963 make those two SETs separate I1 and I2 insns, and make an I0 that is
2965 if (!HAVE_cc0
&& i0
== 0
2966 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2967 && can_split_parallel_of_n_reg_sets (i2
, 2)
2968 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2969 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2971 /* If there is no I1, there is no I0 either. */
2974 /* We make I1 with the same INSN_UID as I2. This gives it
2975 the same DF_INSN_LUID for value tracking. Our fake I1 will
2976 never appear in the insn stream so giving it the same INSN_UID
2977 as I2 will not cause a problem. */
2979 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2980 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2982 INSN_UID (i1
) = INSN_UID (i2
);
2984 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2987 /* Verify that I2 and I1 are valid for combining. */
2988 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2989 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2991 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2998 /* Record whether I2DEST is used in I2SRC and similarly for the other
2999 cases. Knowing this will help in register status updating below. */
3000 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3001 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3002 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3003 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3004 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3005 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3006 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3007 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3008 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3010 /* For the earlier insns, determine which of the subsequent ones they
3012 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3013 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3014 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3015 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3016 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3018 /* Ensure that I3's pattern can be the destination of combines. */
3019 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3020 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3021 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3022 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3029 /* See if any of the insns is a MULT operation. Unless one is, we will
3030 reject a combination that is, since it must be slower. Be conservative
3032 if (GET_CODE (i2src
) == MULT
3033 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3034 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3035 || (GET_CODE (PATTERN (i3
)) == SET
3036 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3039 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3040 We used to do this EXCEPT in one case: I3 has a post-inc in an
3041 output operand. However, that exception can give rise to insns like
3043 which is a famous insn on the PDP-11 where the value of r3 used as the
3044 source was model-dependent. Avoid this sort of thing. */
3047 if (!(GET_CODE (PATTERN (i3
)) == SET
3048 && REG_P (SET_SRC (PATTERN (i3
)))
3049 && MEM_P (SET_DEST (PATTERN (i3
)))
3050 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3051 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3052 /* It's not the exception. */
3057 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3058 if (REG_NOTE_KIND (link
) == REG_INC
3059 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3061 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3068 /* See if the SETs in I1 or I2 need to be kept around in the merged
3069 instruction: whenever the value set there is still needed past I3.
3070 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3072 For the SET in I1, we have two cases: if I1 and I2 independently feed
3073 into I3, the set in I1 needs to be kept around unless I1DEST dies
3074 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3075 in I1 needs to be kept around unless I1DEST dies or is set in either
3076 I2 or I3. The same considerations apply to I0. */
3078 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3081 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3082 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3087 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3088 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3089 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3090 && dead_or_set_p (i2
, i0dest
)));
3094 /* We are about to copy insns for the case where they need to be kept
3095 around. Check that they can be copied in the merged instruction. */
3097 if (targetm
.cannot_copy_insn_p
3098 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3099 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3100 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3106 /* If the set in I2 needs to be kept around, we must make a copy of
3107 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3108 PATTERN (I2), we are only substituting for the original I1DEST, not into
3109 an already-substituted copy. This also prevents making self-referential
3110 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3115 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3116 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3118 i2pat
= copy_rtx (PATTERN (i2
));
3123 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3124 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3126 i1pat
= copy_rtx (PATTERN (i1
));
3131 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3132 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3134 i0pat
= copy_rtx (PATTERN (i0
));
3139 /* Substitute in the latest insn for the regs set by the earlier ones. */
3141 maxreg
= max_reg_num ();
3145 /* Many machines that don't use CC0 have insns that can both perform an
3146 arithmetic operation and set the condition code. These operations will
3147 be represented as a PARALLEL with the first element of the vector
3148 being a COMPARE of an arithmetic operation with the constant zero.
3149 The second element of the vector will set some pseudo to the result
3150 of the same arithmetic operation. If we simplify the COMPARE, we won't
3151 match such a pattern and so will generate an extra insn. Here we test
3152 for this case, where both the comparison and the operation result are
3153 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3154 I2SRC. Later we will make the PARALLEL that contains I2. */
3156 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3157 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3158 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3159 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3162 rtx
*cc_use_loc
= NULL
;
3163 rtx_insn
*cc_use_insn
= NULL
;
3164 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3165 machine_mode compare_mode
, orig_compare_mode
;
3166 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3168 newpat
= PATTERN (i3
);
3169 newpat_dest
= SET_DEST (newpat
);
3170 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3172 if (undobuf
.other_insn
== 0
3173 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3176 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3177 compare_code
= simplify_compare_const (compare_code
,
3178 GET_MODE (i2dest
), op0
, &op1
);
3179 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3182 /* Do the rest only if op1 is const0_rtx, which may be the
3183 result of simplification. */
3184 if (op1
== const0_rtx
)
3186 /* If a single use of the CC is found, prepare to modify it
3187 when SELECT_CC_MODE returns a new CC-class mode, or when
3188 the above simplify_compare_const() returned a new comparison
3189 operator. undobuf.other_insn is assigned the CC use insn
3190 when modifying it. */
3193 #ifdef SELECT_CC_MODE
3194 machine_mode new_mode
3195 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3196 if (new_mode
!= orig_compare_mode
3197 && can_change_dest_mode (SET_DEST (newpat
),
3198 added_sets_2
, new_mode
))
3200 unsigned int regno
= REGNO (newpat_dest
);
3201 compare_mode
= new_mode
;
3202 if (regno
< FIRST_PSEUDO_REGISTER
)
3203 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3206 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3207 newpat_dest
= regno_reg_rtx
[regno
];
3211 /* Cases for modifying the CC-using comparison. */
3212 if (compare_code
!= orig_compare_code
3213 /* ??? Do we need to verify the zero rtx? */
3214 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3216 /* Replace cc_use_loc with entire new RTX. */
3218 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3219 newpat_dest
, const0_rtx
));
3220 undobuf
.other_insn
= cc_use_insn
;
3222 else if (compare_mode
!= orig_compare_mode
)
3224 /* Just replace the CC reg with a new mode. */
3225 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3226 undobuf
.other_insn
= cc_use_insn
;
3230 /* Now we modify the current newpat:
3231 First, SET_DEST(newpat) is updated if the CC mode has been
3232 altered. For targets without SELECT_CC_MODE, this should be
3234 if (compare_mode
!= orig_compare_mode
)
3235 SUBST (SET_DEST (newpat
), newpat_dest
);
3236 /* This is always done to propagate i2src into newpat. */
3237 SUBST (SET_SRC (newpat
),
3238 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3239 /* Create new version of i2pat if needed; the below PARALLEL
3240 creation needs this to work correctly. */
3241 if (! rtx_equal_p (i2src
, op0
))
3242 i2pat
= gen_rtx_SET (i2dest
, op0
);
3247 if (i2_is_used
== 0)
3249 /* It is possible that the source of I2 or I1 may be performing
3250 an unneeded operation, such as a ZERO_EXTEND of something
3251 that is known to have the high part zero. Handle that case
3252 by letting subst look at the inner insns.
3254 Another way to do this would be to have a function that tries
3255 to simplify a single insn instead of merging two or more
3256 insns. We don't do this because of the potential of infinite
3257 loops and because of the potential extra memory required.
3258 However, doing it the way we are is a bit of a kludge and
3259 doesn't catch all cases.
3261 But only do this if -fexpensive-optimizations since it slows
3262 things down and doesn't usually win.
3264 This is not done in the COMPARE case above because the
3265 unmodified I2PAT is used in the PARALLEL and so a pattern
3266 with a modified I2SRC would not match. */
3268 if (flag_expensive_optimizations
)
3270 /* Pass pc_rtx so no substitutions are done, just
3274 subst_low_luid
= DF_INSN_LUID (i1
);
3275 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3278 subst_low_luid
= DF_INSN_LUID (i2
);
3279 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3282 n_occurrences
= 0; /* `subst' counts here */
3283 subst_low_luid
= DF_INSN_LUID (i2
);
3285 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3286 copy of I2SRC each time we substitute it, in order to avoid creating
3287 self-referential RTL when we will be substituting I1SRC for I1DEST
3288 later. Likewise if I0 feeds into I2, either directly or indirectly
3289 through I1, and I0DEST is in I0SRC. */
3290 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3291 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3292 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3293 && i0dest_in_i0src
));
3296 /* Record whether I2's body now appears within I3's body. */
3297 i2_is_used
= n_occurrences
;
3300 /* If we already got a failure, don't try to do more. Otherwise, try to
3301 substitute I1 if we have it. */
3303 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3305 /* Check that an autoincrement side-effect on I1 has not been lost.
3306 This happens if I1DEST is mentioned in I2 and dies there, and
3307 has disappeared from the new pattern. */
3308 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3310 && dead_or_set_p (i2
, i1dest
)
3311 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3312 /* Before we can do this substitution, we must redo the test done
3313 above (see detailed comments there) that ensures I1DEST isn't
3314 mentioned in any SETs in NEWPAT that are field assignments. */
3315 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3323 subst_low_luid
= DF_INSN_LUID (i1
);
3325 /* If the following substitution will modify I1SRC, make a copy of it
3326 for the case where it is substituted for I1DEST in I2PAT later. */
3327 if (added_sets_2
&& i1_feeds_i2_n
)
3328 i1src_copy
= copy_rtx (i1src
);
3330 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3331 copy of I1SRC each time we substitute it, in order to avoid creating
3332 self-referential RTL when we will be substituting I0SRC for I0DEST
3334 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3335 i0_feeds_i1_n
&& i0dest_in_i0src
);
3338 /* Record whether I1's body now appears within I3's body. */
3339 i1_is_used
= n_occurrences
;
3342 /* Likewise for I0 if we have it. */
3344 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3346 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3347 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3348 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3349 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3350 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3357 /* If the following substitution will modify I0SRC, make a copy of it
3358 for the case where it is substituted for I0DEST in I1PAT later. */
3359 if (added_sets_1
&& i0_feeds_i1_n
)
3360 i0src_copy
= copy_rtx (i0src
);
3361 /* And a copy for I0DEST in I2PAT substitution. */
3362 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3363 || (i0_feeds_i2_n
)))
3364 i0src_copy2
= copy_rtx (i0src
);
3367 subst_low_luid
= DF_INSN_LUID (i0
);
3368 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3372 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3373 to count all the ways that I2SRC and I1SRC can be used. */
3374 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3375 && i2_is_used
+ added_sets_2
> 1)
3376 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3377 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3379 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3380 && (n_occurrences
+ added_sets_0
3381 + (added_sets_1
&& i0_feeds_i1_n
)
3382 + (added_sets_2
&& i0_feeds_i2_n
)
3384 /* Fail if we tried to make a new register. */
3385 || max_reg_num () != maxreg
3386 /* Fail if we couldn't do something and have a CLOBBER. */
3387 || GET_CODE (newpat
) == CLOBBER
3388 /* Fail if this new pattern is a MULT and we didn't have one before
3389 at the outer level. */
3390 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3397 /* If the actions of the earlier insns must be kept
3398 in addition to substituting them into the latest one,
3399 we must make a new PARALLEL for the latest insn
3400 to hold additional the SETs. */
3402 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3404 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3407 if (GET_CODE (newpat
) == PARALLEL
)
3409 rtvec old
= XVEC (newpat
, 0);
3410 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3411 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3412 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3413 sizeof (old
->elem
[0]) * old
->num_elem
);
3418 total_sets
= 1 + extra_sets
;
3419 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3420 XVECEXP (newpat
, 0, 0) = old
;
3424 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3430 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3432 XVECEXP (newpat
, 0, --total_sets
) = t
;
3438 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3439 i0_feeds_i1_n
&& i0dest_in_i0src
);
3440 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3441 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3443 XVECEXP (newpat
, 0, --total_sets
) = t
;
3447 validate_replacement
:
3449 /* Note which hard regs this insn has as inputs. */
3450 mark_used_regs_combine (newpat
);
3452 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3453 consider splitting this pattern, we might need these clobbers. */
3454 if (i1
&& GET_CODE (newpat
) == PARALLEL
3455 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3457 int len
= XVECLEN (newpat
, 0);
3459 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3460 for (i
= 0; i
< len
; i
++)
3461 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3464 /* We have recognized nothing yet. */
3465 insn_code_number
= -1;
3467 /* See if this is a PARALLEL of two SETs where one SET's destination is
3468 a register that is unused and this isn't marked as an instruction that
3469 might trap in an EH region. In that case, we just need the other SET.
3470 We prefer this over the PARALLEL.
3472 This can occur when simplifying a divmod insn. We *must* test for this
3473 case here because the code below that splits two independent SETs doesn't
3474 handle this case correctly when it updates the register status.
3476 It's pointless doing this if we originally had two sets, one from
3477 i3, and one from i2. Combining then splitting the parallel results
3478 in the original i2 again plus an invalid insn (which we delete).
3479 The net effect is only to move instructions around, which makes
3480 debug info less accurate. */
3482 if (!(added_sets_2
&& i1
== 0)
3483 && is_parallel_of_n_reg_sets (newpat
, 2)
3484 && asm_noperands (newpat
) < 0)
3486 rtx set0
= XVECEXP (newpat
, 0, 0);
3487 rtx set1
= XVECEXP (newpat
, 0, 1);
3488 rtx oldpat
= newpat
;
3490 if (((REG_P (SET_DEST (set1
))
3491 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3492 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3493 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3494 && insn_nothrow_p (i3
)
3495 && !side_effects_p (SET_SRC (set1
)))
3498 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3501 else if (((REG_P (SET_DEST (set0
))
3502 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3503 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3504 && find_reg_note (i3
, REG_UNUSED
,
3505 SUBREG_REG (SET_DEST (set0
)))))
3506 && insn_nothrow_p (i3
)
3507 && !side_effects_p (SET_SRC (set0
)))
3510 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3512 if (insn_code_number
>= 0)
3513 changed_i3_dest
= 1;
3516 if (insn_code_number
< 0)
3520 /* Is the result of combination a valid instruction? */
3521 if (insn_code_number
< 0)
3522 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3524 /* If we were combining three insns and the result is a simple SET
3525 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3526 insns. There are two ways to do this. It can be split using a
3527 machine-specific method (like when you have an addition of a large
3528 constant) or by combine in the function find_split_point. */
3530 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3531 && asm_noperands (newpat
) < 0)
3533 rtx parallel
, *split
;
3534 rtx_insn
*m_split_insn
;
3536 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3537 use I2DEST as a scratch register will help. In the latter case,
3538 convert I2DEST to the mode of the source of NEWPAT if we can. */
3540 m_split_insn
= combine_split_insns (newpat
, i3
);
3542 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3543 inputs of NEWPAT. */
3545 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3546 possible to try that as a scratch reg. This would require adding
3547 more code to make it work though. */
3549 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3551 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3553 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3554 (temporarily, until we are committed to this instruction
3555 combination) does not work: for example, any call to nonzero_bits
3556 on the register (from a splitter in the MD file, for example)
3557 will get the old information, which is invalid.
3559 Since nowadays we can create registers during combine just fine,
3560 we should just create a new one here, not reuse i2dest. */
3562 /* First try to split using the original register as a
3563 scratch register. */
3564 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3565 gen_rtvec (2, newpat
,
3566 gen_rtx_CLOBBER (VOIDmode
,
3568 m_split_insn
= combine_split_insns (parallel
, i3
);
3570 /* If that didn't work, try changing the mode of I2DEST if
3572 if (m_split_insn
== 0
3573 && new_mode
!= GET_MODE (i2dest
)
3574 && new_mode
!= VOIDmode
3575 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3577 machine_mode old_mode
= GET_MODE (i2dest
);
3580 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3581 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3584 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3585 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3588 parallel
= (gen_rtx_PARALLEL
3590 gen_rtvec (2, newpat
,
3591 gen_rtx_CLOBBER (VOIDmode
,
3593 m_split_insn
= combine_split_insns (parallel
, i3
);
3595 if (m_split_insn
== 0
3596 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3600 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3601 buf
= undobuf
.undos
;
3602 undobuf
.undos
= buf
->next
;
3603 buf
->next
= undobuf
.frees
;
3604 undobuf
.frees
= buf
;
3608 i2scratch
= m_split_insn
!= 0;
3611 /* If recog_for_combine has discarded clobbers, try to use them
3612 again for the split. */
3613 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3615 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3616 m_split_insn
= combine_split_insns (parallel
, i3
);
3619 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3621 rtx m_split_pat
= PATTERN (m_split_insn
);
3622 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3623 if (insn_code_number
>= 0)
3624 newpat
= m_split_pat
;
3626 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3627 && (next_nonnote_nondebug_insn (i2
) == i3
3628 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3631 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3632 newi2pat
= PATTERN (m_split_insn
);
3634 i3set
= single_set (NEXT_INSN (m_split_insn
));
3635 i2set
= single_set (m_split_insn
);
3637 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3639 /* If I2 or I3 has multiple SETs, we won't know how to track
3640 register status, so don't use these insns. If I2's destination
3641 is used between I2 and I3, we also can't use these insns. */
3643 if (i2_code_number
>= 0 && i2set
&& i3set
3644 && (next_nonnote_nondebug_insn (i2
) == i3
3645 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3646 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3648 if (insn_code_number
>= 0)
3651 /* It is possible that both insns now set the destination of I3.
3652 If so, we must show an extra use of it. */
3654 if (insn_code_number
>= 0)
3656 rtx new_i3_dest
= SET_DEST (i3set
);
3657 rtx new_i2_dest
= SET_DEST (i2set
);
3659 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3660 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3661 || GET_CODE (new_i3_dest
) == SUBREG
)
3662 new_i3_dest
= XEXP (new_i3_dest
, 0);
3664 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3665 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3666 || GET_CODE (new_i2_dest
) == SUBREG
)
3667 new_i2_dest
= XEXP (new_i2_dest
, 0);
3669 if (REG_P (new_i3_dest
)
3670 && REG_P (new_i2_dest
)
3671 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3672 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3673 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3677 /* If we can split it and use I2DEST, go ahead and see if that
3678 helps things be recognized. Verify that none of the registers
3679 are set between I2 and I3. */
3680 if (insn_code_number
< 0
3681 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3682 && (!HAVE_cc0
|| REG_P (i2dest
))
3683 /* We need I2DEST in the proper mode. If it is a hard register
3684 or the only use of a pseudo, we can change its mode.
3685 Make sure we don't change a hard register to have a mode that
3686 isn't valid for it, or change the number of registers. */
3687 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3688 || GET_MODE (*split
) == VOIDmode
3689 || can_change_dest_mode (i2dest
, added_sets_2
,
3691 && (next_nonnote_nondebug_insn (i2
) == i3
3692 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3693 /* We can't overwrite I2DEST if its value is still used by
3695 && ! reg_referenced_p (i2dest
, newpat
))
3697 rtx newdest
= i2dest
;
3698 enum rtx_code split_code
= GET_CODE (*split
);
3699 machine_mode split_mode
= GET_MODE (*split
);
3700 bool subst_done
= false;
3701 newi2pat
= NULL_RTX
;
3705 /* *SPLIT may be part of I2SRC, so make sure we have the
3706 original expression around for later debug processing.
3707 We should not need I2SRC any more in other cases. */
3708 if (MAY_HAVE_DEBUG_INSNS
)
3709 i2src
= copy_rtx (i2src
);
3713 /* Get NEWDEST as a register in the proper mode. We have already
3714 validated that we can do this. */
3715 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3717 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3718 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3721 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3722 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3726 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3727 an ASHIFT. This can occur if it was inside a PLUS and hence
3728 appeared to be a memory address. This is a kludge. */
3729 if (split_code
== MULT
3730 && CONST_INT_P (XEXP (*split
, 1))
3731 && INTVAL (XEXP (*split
, 1)) > 0
3732 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3734 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3735 XEXP (*split
, 0), GEN_INT (i
)));
3736 /* Update split_code because we may not have a multiply
3738 split_code
= GET_CODE (*split
);
3741 /* Similarly for (plus (mult FOO (const_int pow2))). */
3742 if (split_code
== PLUS
3743 && GET_CODE (XEXP (*split
, 0)) == MULT
3744 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3745 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3746 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3748 rtx nsplit
= XEXP (*split
, 0);
3749 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3750 XEXP (nsplit
, 0), GEN_INT (i
)));
3751 /* Update split_code because we may not have a multiply
3753 split_code
= GET_CODE (*split
);
3756 #ifdef INSN_SCHEDULING
3757 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3758 be written as a ZERO_EXTEND. */
3759 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3761 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3762 what it really is. */
3763 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3765 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3766 SUBREG_REG (*split
)));
3768 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3769 SUBREG_REG (*split
)));
3773 /* Attempt to split binary operators using arithmetic identities. */
3774 if (BINARY_P (SET_SRC (newpat
))
3775 && split_mode
== GET_MODE (SET_SRC (newpat
))
3776 && ! side_effects_p (SET_SRC (newpat
)))
3778 rtx setsrc
= SET_SRC (newpat
);
3779 machine_mode mode
= GET_MODE (setsrc
);
3780 enum rtx_code code
= GET_CODE (setsrc
);
3781 rtx src_op0
= XEXP (setsrc
, 0);
3782 rtx src_op1
= XEXP (setsrc
, 1);
3784 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3785 if (rtx_equal_p (src_op0
, src_op1
))
3787 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3788 SUBST (XEXP (setsrc
, 0), newdest
);
3789 SUBST (XEXP (setsrc
, 1), newdest
);
3792 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3793 else if ((code
== PLUS
|| code
== MULT
)
3794 && GET_CODE (src_op0
) == code
3795 && GET_CODE (XEXP (src_op0
, 0)) == code
3796 && (INTEGRAL_MODE_P (mode
)
3797 || (FLOAT_MODE_P (mode
)
3798 && flag_unsafe_math_optimizations
)))
3800 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3801 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3802 rtx r
= XEXP (src_op0
, 1);
3805 /* Split both "((X op Y) op X) op Y" and
3806 "((X op Y) op Y) op X" as "T op T" where T is
3808 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3809 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3811 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3812 SUBST (XEXP (setsrc
, 0), newdest
);
3813 SUBST (XEXP (setsrc
, 1), newdest
);
3816 /* Split "((X op X) op Y) op Y)" as "T op T" where
3818 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3820 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3821 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3822 SUBST (XEXP (setsrc
, 0), newdest
);
3823 SUBST (XEXP (setsrc
, 1), newdest
);
3831 newi2pat
= gen_rtx_SET (newdest
, *split
);
3832 SUBST (*split
, newdest
);
3835 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3837 /* recog_for_combine might have added CLOBBERs to newi2pat.
3838 Make sure NEWPAT does not depend on the clobbered regs. */
3839 if (GET_CODE (newi2pat
) == PARALLEL
)
3840 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3841 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3843 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3844 if (reg_overlap_mentioned_p (reg
, newpat
))
3851 /* If the split point was a MULT and we didn't have one before,
3852 don't use one now. */
3853 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3854 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3858 /* Check for a case where we loaded from memory in a narrow mode and
3859 then sign extended it, but we need both registers. In that case,
3860 we have a PARALLEL with both loads from the same memory location.
3861 We can split this into a load from memory followed by a register-register
3862 copy. This saves at least one insn, more if register allocation can
3865 We cannot do this if the destination of the first assignment is a
3866 condition code register or cc0. We eliminate this case by making sure
3867 the SET_DEST and SET_SRC have the same mode.
3869 We cannot do this if the destination of the second assignment is
3870 a register that we have already assumed is zero-extended. Similarly
3871 for a SUBREG of such a register. */
3873 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3874 && GET_CODE (newpat
) == PARALLEL
3875 && XVECLEN (newpat
, 0) == 2
3876 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3877 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3878 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3879 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3880 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3881 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3882 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3883 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3885 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3886 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3887 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3889 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3890 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3891 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3892 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3893 != GET_MODE_MASK (word_mode
))))
3894 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3895 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3897 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3898 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3899 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3900 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3901 != GET_MODE_MASK (word_mode
)))))
3902 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3903 SET_SRC (XVECEXP (newpat
, 0, 1)))
3904 && ! find_reg_note (i3
, REG_UNUSED
,
3905 SET_DEST (XVECEXP (newpat
, 0, 0))))
3909 newi2pat
= XVECEXP (newpat
, 0, 0);
3910 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3911 newpat
= XVECEXP (newpat
, 0, 1);
3912 SUBST (SET_SRC (newpat
),
3913 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3914 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3916 if (i2_code_number
>= 0)
3917 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3919 if (insn_code_number
>= 0)
3923 /* Similarly, check for a case where we have a PARALLEL of two independent
3924 SETs but we started with three insns. In this case, we can do the sets
3925 as two separate insns. This case occurs when some SET allows two
3926 other insns to combine, but the destination of that SET is still live.
3928 Also do this if we started with two insns and (at least) one of the
3929 resulting sets is a noop; this noop will be deleted later. */
3931 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3932 && GET_CODE (newpat
) == PARALLEL
3933 && XVECLEN (newpat
, 0) == 2
3934 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3935 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3936 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3937 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3938 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3939 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3940 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3941 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3942 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3943 XVECEXP (newpat
, 0, 0))
3944 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3945 XVECEXP (newpat
, 0, 1))
3946 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3947 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3949 rtx set0
= XVECEXP (newpat
, 0, 0);
3950 rtx set1
= XVECEXP (newpat
, 0, 1);
3952 /* Normally, it doesn't matter which of the two is done first,
3953 but the one that references cc0 can't be the second, and
3954 one which uses any regs/memory set in between i2 and i3 can't
3955 be first. The PARALLEL might also have been pre-existing in i3,
3956 so we need to make sure that we won't wrongly hoist a SET to i2
3957 that would conflict with a death note present in there. */
3958 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3959 && !(REG_P (SET_DEST (set1
))
3960 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3961 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3962 && find_reg_note (i2
, REG_DEAD
,
3963 SUBREG_REG (SET_DEST (set1
))))
3964 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3965 /* If I3 is a jump, ensure that set0 is a jump so that
3966 we do not create invalid RTL. */
3967 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3973 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3974 && !(REG_P (SET_DEST (set0
))
3975 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3976 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3977 && find_reg_note (i2
, REG_DEAD
,
3978 SUBREG_REG (SET_DEST (set0
))))
3979 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3980 /* If I3 is a jump, ensure that set1 is a jump so that
3981 we do not create invalid RTL. */
3982 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3994 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3996 if (i2_code_number
>= 0)
3998 /* recog_for_combine might have added CLOBBERs to newi2pat.
3999 Make sure NEWPAT does not depend on the clobbered regs. */
4000 if (GET_CODE (newi2pat
) == PARALLEL
)
4002 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4003 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4005 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4006 if (reg_overlap_mentioned_p (reg
, newpat
))
4014 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4018 /* If it still isn't recognized, fail and change things back the way they
4020 if ((insn_code_number
< 0
4021 /* Is the result a reasonable ASM_OPERANDS? */
4022 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4028 /* If we had to change another insn, make sure it is valid also. */
4029 if (undobuf
.other_insn
)
4031 CLEAR_HARD_REG_SET (newpat_used_regs
);
4033 other_pat
= PATTERN (undobuf
.other_insn
);
4034 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4037 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4044 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4045 they are adjacent to each other or not. */
4048 rtx_insn
*p
= prev_nonnote_insn (i3
);
4049 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4050 && sets_cc0_p (newi2pat
))
4057 /* Only allow this combination if insn_rtx_costs reports that the
4058 replacement instructions are cheaper than the originals. */
4059 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4065 if (MAY_HAVE_DEBUG_INSNS
)
4069 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4070 if (undo
->kind
== UNDO_MODE
)
4072 rtx reg
= *undo
->where
.r
;
4073 machine_mode new_mode
= GET_MODE (reg
);
4074 machine_mode old_mode
= undo
->old_contents
.m
;
4076 /* Temporarily revert mode back. */
4077 adjust_reg_mode (reg
, old_mode
);
4079 if (reg
== i2dest
&& i2scratch
)
4081 /* If we used i2dest as a scratch register with a
4082 different mode, substitute it for the original
4083 i2src while its original mode is temporarily
4084 restored, and then clear i2scratch so that we don't
4085 do it again later. */
4086 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4089 /* Put back the new mode. */
4090 adjust_reg_mode (reg
, new_mode
);
4094 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4095 rtx_insn
*first
, *last
;
4100 last
= last_combined_insn
;
4105 last
= undobuf
.other_insn
;
4107 if (DF_INSN_LUID (last
)
4108 < DF_INSN_LUID (last_combined_insn
))
4109 last
= last_combined_insn
;
4112 /* We're dealing with a reg that changed mode but not
4113 meaning, so we want to turn it into a subreg for
4114 the new mode. However, because of REG sharing and
4115 because its mode had already changed, we have to do
4116 it in two steps. First, replace any debug uses of
4117 reg, with its original mode temporarily restored,
4118 with this copy we have created; then, replace the
4119 copy with the SUBREG of the original shared reg,
4120 once again changed to the new mode. */
4121 propagate_for_debug (first
, last
, reg
, tempreg
,
4123 adjust_reg_mode (reg
, new_mode
);
4124 propagate_for_debug (first
, last
, tempreg
,
4125 lowpart_subreg (old_mode
, reg
, new_mode
),
4131 /* If we will be able to accept this, we have made a
4132 change to the destination of I3. This requires us to
4133 do a few adjustments. */
4135 if (changed_i3_dest
)
4137 PATTERN (i3
) = newpat
;
4138 adjust_for_new_dest (i3
);
4141 /* We now know that we can do this combination. Merge the insns and
4142 update the status of registers and LOG_LINKS. */
4144 if (undobuf
.other_insn
)
4148 PATTERN (undobuf
.other_insn
) = other_pat
;
4150 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4151 ensure that they are still valid. Then add any non-duplicate
4152 notes added by recog_for_combine. */
4153 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4155 next
= XEXP (note
, 1);
4157 if ((REG_NOTE_KIND (note
) == REG_DEAD
4158 && !reg_referenced_p (XEXP (note
, 0),
4159 PATTERN (undobuf
.other_insn
)))
4160 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4161 && !reg_set_p (XEXP (note
, 0),
4162 PATTERN (undobuf
.other_insn
)))
4163 /* Simply drop equal note since it may be no longer valid
4164 for other_insn. It may be possible to record that CC
4165 register is changed and only discard those notes, but
4166 in practice it's unnecessary complication and doesn't
4167 give any meaningful improvement.
4170 || REG_NOTE_KIND (note
) == REG_EQUAL
4171 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4172 remove_note (undobuf
.other_insn
, note
);
4175 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4176 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4183 struct insn_link
*link
;
4186 /* I3 now uses what used to be its destination and which is now
4187 I2's destination. This requires us to do a few adjustments. */
4188 PATTERN (i3
) = newpat
;
4189 adjust_for_new_dest (i3
);
4191 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4194 However, some later insn might be using I2's dest and have
4195 a LOG_LINK pointing at I3. We must remove this link.
4196 The simplest way to remove the link is to point it at I1,
4197 which we know will be a NOTE. */
4199 /* newi2pat is usually a SET here; however, recog_for_combine might
4200 have added some clobbers. */
4201 if (GET_CODE (newi2pat
) == PARALLEL
)
4202 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4204 ni2dest
= SET_DEST (newi2pat
);
4206 for (insn
= NEXT_INSN (i3
);
4207 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4208 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4209 insn
= NEXT_INSN (insn
))
4211 if (NONDEBUG_INSN_P (insn
)
4212 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4214 FOR_EACH_LOG_LINK (link
, insn
)
4215 if (link
->insn
== i3
)
4224 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4225 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4228 /* Compute which registers we expect to eliminate. newi2pat may be setting
4229 either i3dest or i2dest, so we must check it. */
4230 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4231 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4234 /* For i1, we need to compute both local elimination and global
4235 elimination information with respect to newi2pat because i1dest
4236 may be the same as i3dest, in which case newi2pat may be setting
4237 i1dest. Global information is used when distributing REG_DEAD
4238 note for i2 and i3, in which case it does matter if newi2pat sets
4241 Local information is used when distributing REG_DEAD note for i1,
4242 in which case it doesn't matter if newi2pat sets i1dest or not.
4243 See PR62151, if we have four insns combination:
4245 i1: r1 <- i1src (using r0)
4247 i2: r0 <- i2src (using r1)
4248 i3: r3 <- i3src (using r0)
4250 From i1's point of view, r0 is eliminated, no matter if it is set
4251 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4252 should be discarded.
4254 Note local information only affects cases in forms like "I1->I2->I3",
4255 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4256 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4258 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4261 rtx elim_i1
= (local_elim_i1
== 0
4262 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4264 /* Same case as i1. */
4265 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4267 rtx elim_i0
= (local_elim_i0
== 0
4268 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4271 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4273 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4274 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4276 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4278 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4280 /* Ensure that we do not have something that should not be shared but
4281 occurs multiple times in the new insns. Check this by first
4282 resetting all the `used' flags and then copying anything is shared. */
4284 reset_used_flags (i3notes
);
4285 reset_used_flags (i2notes
);
4286 reset_used_flags (i1notes
);
4287 reset_used_flags (i0notes
);
4288 reset_used_flags (newpat
);
4289 reset_used_flags (newi2pat
);
4290 if (undobuf
.other_insn
)
4291 reset_used_flags (PATTERN (undobuf
.other_insn
));
4293 i3notes
= copy_rtx_if_shared (i3notes
);
4294 i2notes
= copy_rtx_if_shared (i2notes
);
4295 i1notes
= copy_rtx_if_shared (i1notes
);
4296 i0notes
= copy_rtx_if_shared (i0notes
);
4297 newpat
= copy_rtx_if_shared (newpat
);
4298 newi2pat
= copy_rtx_if_shared (newi2pat
);
4299 if (undobuf
.other_insn
)
4300 reset_used_flags (PATTERN (undobuf
.other_insn
));
4302 INSN_CODE (i3
) = insn_code_number
;
4303 PATTERN (i3
) = newpat
;
4305 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4307 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4308 link
= XEXP (link
, 1))
4312 /* I2SRC must still be meaningful at this point. Some
4313 splitting operations can invalidate I2SRC, but those
4314 operations do not apply to calls. */
4316 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4320 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4323 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4328 if (undobuf
.other_insn
)
4329 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4331 /* We had one special case above where I2 had more than one set and
4332 we replaced a destination of one of those sets with the destination
4333 of I3. In that case, we have to update LOG_LINKS of insns later
4334 in this basic block. Note that this (expensive) case is rare.
4336 Also, in this case, we must pretend that all REG_NOTEs for I2
4337 actually came from I3, so that REG_UNUSED notes from I2 will be
4338 properly handled. */
4340 if (i3_subst_into_i2
)
4342 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4343 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4344 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4345 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4346 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4347 && ! find_reg_note (i2
, REG_UNUSED
,
4348 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4349 for (temp_insn
= NEXT_INSN (i2
);
4351 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4352 || BB_HEAD (this_basic_block
) != temp_insn
);
4353 temp_insn
= NEXT_INSN (temp_insn
))
4354 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4355 FOR_EACH_LOG_LINK (link
, temp_insn
)
4356 if (link
->insn
== i2
)
4362 while (XEXP (link
, 1))
4363 link
= XEXP (link
, 1);
4364 XEXP (link
, 1) = i2notes
;
4371 LOG_LINKS (i3
) = NULL
;
4373 LOG_LINKS (i2
) = NULL
;
4378 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4379 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4381 INSN_CODE (i2
) = i2_code_number
;
4382 PATTERN (i2
) = newi2pat
;
4386 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4387 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4389 SET_INSN_DELETED (i2
);
4394 LOG_LINKS (i1
) = NULL
;
4396 if (MAY_HAVE_DEBUG_INSNS
)
4397 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4399 SET_INSN_DELETED (i1
);
4404 LOG_LINKS (i0
) = NULL
;
4406 if (MAY_HAVE_DEBUG_INSNS
)
4407 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4409 SET_INSN_DELETED (i0
);
4412 /* Get death notes for everything that is now used in either I3 or
4413 I2 and used to die in a previous insn. If we built two new
4414 patterns, move from I1 to I2 then I2 to I3 so that we get the
4415 proper movement on registers that I2 modifies. */
4418 from_luid
= DF_INSN_LUID (i0
);
4420 from_luid
= DF_INSN_LUID (i1
);
4422 from_luid
= DF_INSN_LUID (i2
);
4424 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4425 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4427 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4429 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4430 elim_i2
, elim_i1
, elim_i0
);
4432 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4433 elim_i2
, elim_i1
, elim_i0
);
4435 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4436 elim_i2
, local_elim_i1
, local_elim_i0
);
4438 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4439 elim_i2
, elim_i1
, local_elim_i0
);
4441 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4442 elim_i2
, elim_i1
, elim_i0
);
4444 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4445 know these are REG_UNUSED and want them to go to the desired insn,
4446 so we always pass it as i3. */
4448 if (newi2pat
&& new_i2_notes
)
4449 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4453 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4456 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4457 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4458 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4459 in that case, it might delete I2. Similarly for I2 and I1.
4460 Show an additional death due to the REG_DEAD note we make here. If
4461 we discard it in distribute_notes, we will decrement it again. */
4465 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4466 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4467 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4470 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4471 elim_i2
, elim_i1
, elim_i0
);
4474 if (i2dest_in_i2src
)
4476 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4477 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4478 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4479 NULL_RTX
, NULL_RTX
);
4481 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4482 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4485 if (i1dest_in_i1src
)
4487 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4488 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4489 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4490 NULL_RTX
, NULL_RTX
);
4492 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4493 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4496 if (i0dest_in_i0src
)
4498 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4499 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4500 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4501 NULL_RTX
, NULL_RTX
);
4503 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4504 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4507 distribute_links (i3links
);
4508 distribute_links (i2links
);
4509 distribute_links (i1links
);
4510 distribute_links (i0links
);
4514 struct insn_link
*link
;
4515 rtx_insn
*i2_insn
= 0;
4516 rtx i2_val
= 0, set
;
4518 /* The insn that used to set this register doesn't exist, and
4519 this life of the register may not exist either. See if one of
4520 I3's links points to an insn that sets I2DEST. If it does,
4521 that is now the last known value for I2DEST. If we don't update
4522 this and I2 set the register to a value that depended on its old
4523 contents, we will get confused. If this insn is used, thing
4524 will be set correctly in combine_instructions. */
4525 FOR_EACH_LOG_LINK (link
, i3
)
4526 if ((set
= single_set (link
->insn
)) != 0
4527 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4528 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4530 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4532 /* If the reg formerly set in I2 died only once and that was in I3,
4533 zero its use count so it won't make `reload' do any work. */
4535 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4536 && ! i2dest_in_i2src
4537 && REGNO (i2dest
) < reg_n_sets_max
)
4538 INC_REG_N_SETS (REGNO (i2dest
), -1);
4541 if (i1
&& REG_P (i1dest
))
4543 struct insn_link
*link
;
4544 rtx_insn
*i1_insn
= 0;
4545 rtx i1_val
= 0, set
;
4547 FOR_EACH_LOG_LINK (link
, i3
)
4548 if ((set
= single_set (link
->insn
)) != 0
4549 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4550 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4552 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4555 && ! i1dest_in_i1src
4556 && REGNO (i1dest
) < reg_n_sets_max
)
4557 INC_REG_N_SETS (REGNO (i1dest
), -1);
4560 if (i0
&& REG_P (i0dest
))
4562 struct insn_link
*link
;
4563 rtx_insn
*i0_insn
= 0;
4564 rtx i0_val
= 0, set
;
4566 FOR_EACH_LOG_LINK (link
, i3
)
4567 if ((set
= single_set (link
->insn
)) != 0
4568 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4569 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4571 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4574 && ! i0dest_in_i0src
4575 && REGNO (i0dest
) < reg_n_sets_max
)
4576 INC_REG_N_SETS (REGNO (i0dest
), -1);
4579 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4580 been made to this insn. The order is important, because newi2pat
4581 can affect nonzero_bits of newpat. */
4583 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4584 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4587 if (undobuf
.other_insn
!= NULL_RTX
)
4591 fprintf (dump_file
, "modifying other_insn ");
4592 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4594 df_insn_rescan (undobuf
.other_insn
);
4597 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4601 fprintf (dump_file
, "modifying insn i0 ");
4602 dump_insn_slim (dump_file
, i0
);
4604 df_insn_rescan (i0
);
4607 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4611 fprintf (dump_file
, "modifying insn i1 ");
4612 dump_insn_slim (dump_file
, i1
);
4614 df_insn_rescan (i1
);
4617 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4621 fprintf (dump_file
, "modifying insn i2 ");
4622 dump_insn_slim (dump_file
, i2
);
4624 df_insn_rescan (i2
);
4627 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4631 fprintf (dump_file
, "modifying insn i3 ");
4632 dump_insn_slim (dump_file
, i3
);
4634 df_insn_rescan (i3
);
4637 /* Set new_direct_jump_p if a new return or simple jump instruction
4638 has been created. Adjust the CFG accordingly. */
4639 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4641 *new_direct_jump_p
= 1;
4642 mark_jump_label (PATTERN (i3
), i3
, 0);
4643 update_cfg_for_uncondjump (i3
);
4646 if (undobuf
.other_insn
!= NULL_RTX
4647 && (returnjump_p (undobuf
.other_insn
)
4648 || any_uncondjump_p (undobuf
.other_insn
)))
4650 *new_direct_jump_p
= 1;
4651 update_cfg_for_uncondjump (undobuf
.other_insn
);
4654 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4655 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4657 basic_block bb
= BLOCK_FOR_INSN (i3
);
4659 remove_edge (split_block (bb
, i3
));
4660 emit_barrier_after_bb (bb
);
4661 *new_direct_jump_p
= 1;
4664 if (undobuf
.other_insn
4665 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4666 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4668 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4670 remove_edge (split_block (bb
, undobuf
.other_insn
));
4671 emit_barrier_after_bb (bb
);
4672 *new_direct_jump_p
= 1;
4675 /* A noop might also need cleaning up of CFG, if it comes from the
4676 simplification of a jump. */
4678 && GET_CODE (newpat
) == SET
4679 && SET_SRC (newpat
) == pc_rtx
4680 && SET_DEST (newpat
) == pc_rtx
)
4682 *new_direct_jump_p
= 1;
4683 update_cfg_for_uncondjump (i3
);
4686 if (undobuf
.other_insn
!= NULL_RTX
4687 && JUMP_P (undobuf
.other_insn
)
4688 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4689 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4690 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4692 *new_direct_jump_p
= 1;
4693 update_cfg_for_uncondjump (undobuf
.other_insn
);
4696 combine_successes
++;
4699 if (added_links_insn
4700 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4701 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4702 return added_links_insn
;
4704 return newi2pat
? i2
: i3
;
4707 /* Get a marker for undoing to the current state. */
4710 get_undo_marker (void)
4712 return undobuf
.undos
;
4715 /* Undo the modifications up to the marker. */
4718 undo_to_marker (void *marker
)
4720 struct undo
*undo
, *next
;
4722 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4730 *undo
->where
.r
= undo
->old_contents
.r
;
4733 *undo
->where
.i
= undo
->old_contents
.i
;
4736 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4739 *undo
->where
.l
= undo
->old_contents
.l
;
4745 undo
->next
= undobuf
.frees
;
4746 undobuf
.frees
= undo
;
4749 undobuf
.undos
= (struct undo
*) marker
;
4752 /* Undo all the modifications recorded in undobuf. */
4760 /* We've committed to accepting the changes we made. Move all
4761 of the undos to the free list. */
4766 struct undo
*undo
, *next
;
4768 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4771 undo
->next
= undobuf
.frees
;
4772 undobuf
.frees
= undo
;
4777 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4778 where we have an arithmetic expression and return that point. LOC will
4781 try_combine will call this function to see if an insn can be split into
4785 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4788 enum rtx_code code
= GET_CODE (x
);
4790 unsigned HOST_WIDE_INT len
= 0;
4791 HOST_WIDE_INT pos
= 0;
4793 rtx inner
= NULL_RTX
;
4795 /* First special-case some codes. */
4799 #ifdef INSN_SCHEDULING
4800 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4802 if (MEM_P (SUBREG_REG (x
)))
4805 return find_split_point (&SUBREG_REG (x
), insn
, false);
4808 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4809 using LO_SUM and HIGH. */
4810 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4811 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4813 machine_mode address_mode
= get_address_mode (x
);
4816 gen_rtx_LO_SUM (address_mode
,
4817 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4819 return &XEXP (XEXP (x
, 0), 0);
4822 /* If we have a PLUS whose second operand is a constant and the
4823 address is not valid, perhaps will can split it up using
4824 the machine-specific way to split large constants. We use
4825 the first pseudo-reg (one of the virtual regs) as a placeholder;
4826 it will not remain in the result. */
4827 if (GET_CODE (XEXP (x
, 0)) == PLUS
4828 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4829 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4830 MEM_ADDR_SPACE (x
)))
4832 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4833 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4836 /* This should have produced two insns, each of which sets our
4837 placeholder. If the source of the second is a valid address,
4838 we can make put both sources together and make a split point
4842 && NEXT_INSN (seq
) != NULL_RTX
4843 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4844 && NONJUMP_INSN_P (seq
)
4845 && GET_CODE (PATTERN (seq
)) == SET
4846 && SET_DEST (PATTERN (seq
)) == reg
4847 && ! reg_mentioned_p (reg
,
4848 SET_SRC (PATTERN (seq
)))
4849 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4850 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4851 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4852 && memory_address_addr_space_p
4853 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4854 MEM_ADDR_SPACE (x
)))
4856 rtx src1
= SET_SRC (PATTERN (seq
));
4857 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4859 /* Replace the placeholder in SRC2 with SRC1. If we can
4860 find where in SRC2 it was placed, that can become our
4861 split point and we can replace this address with SRC2.
4862 Just try two obvious places. */
4864 src2
= replace_rtx (src2
, reg
, src1
);
4866 if (XEXP (src2
, 0) == src1
)
4867 split
= &XEXP (src2
, 0);
4868 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4869 && XEXP (XEXP (src2
, 0), 0) == src1
)
4870 split
= &XEXP (XEXP (src2
, 0), 0);
4874 SUBST (XEXP (x
, 0), src2
);
4879 /* If that didn't work, perhaps the first operand is complex and
4880 needs to be computed separately, so make a split point there.
4881 This will occur on machines that just support REG + CONST
4882 and have a constant moved through some previous computation. */
4884 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4885 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4886 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4887 return &XEXP (XEXP (x
, 0), 0);
4890 /* If we have a PLUS whose first operand is complex, try computing it
4891 separately by making a split there. */
4892 if (GET_CODE (XEXP (x
, 0)) == PLUS
4893 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4895 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4896 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4897 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4898 return &XEXP (XEXP (x
, 0), 0);
4902 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4903 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4904 we need to put the operand into a register. So split at that
4907 if (SET_DEST (x
) == cc0_rtx
4908 && GET_CODE (SET_SRC (x
)) != COMPARE
4909 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4910 && !OBJECT_P (SET_SRC (x
))
4911 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4912 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4913 return &SET_SRC (x
);
4915 /* See if we can split SET_SRC as it stands. */
4916 split
= find_split_point (&SET_SRC (x
), insn
, true);
4917 if (split
&& split
!= &SET_SRC (x
))
4920 /* See if we can split SET_DEST as it stands. */
4921 split
= find_split_point (&SET_DEST (x
), insn
, false);
4922 if (split
&& split
!= &SET_DEST (x
))
4925 /* See if this is a bitfield assignment with everything constant. If
4926 so, this is an IOR of an AND, so split it into that. */
4927 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4928 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4929 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4930 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4931 && CONST_INT_P (SET_SRC (x
))
4932 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4933 + INTVAL (XEXP (SET_DEST (x
), 2)))
4934 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4935 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4937 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4938 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4939 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4940 rtx dest
= XEXP (SET_DEST (x
), 0);
4941 machine_mode mode
= GET_MODE (dest
);
4942 unsigned HOST_WIDE_INT mask
4943 = (HOST_WIDE_INT_1U
<< len
) - 1;
4946 if (BITS_BIG_ENDIAN
)
4947 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4949 or_mask
= gen_int_mode (src
<< pos
, mode
);
4952 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4955 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4957 simplify_gen_binary (IOR
, mode
,
4958 simplify_gen_binary (AND
, mode
,
4963 SUBST (SET_DEST (x
), dest
);
4965 split
= find_split_point (&SET_SRC (x
), insn
, true);
4966 if (split
&& split
!= &SET_SRC (x
))
4970 /* Otherwise, see if this is an operation that we can split into two.
4971 If so, try to split that. */
4972 code
= GET_CODE (SET_SRC (x
));
4977 /* If we are AND'ing with a large constant that is only a single
4978 bit and the result is only being used in a context where we
4979 need to know if it is zero or nonzero, replace it with a bit
4980 extraction. This will avoid the large constant, which might
4981 have taken more than one insn to make. If the constant were
4982 not a valid argument to the AND but took only one insn to make,
4983 this is no worse, but if it took more than one insn, it will
4986 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4987 && REG_P (XEXP (SET_SRC (x
), 0))
4988 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4989 && REG_P (SET_DEST (x
))
4990 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4991 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4992 && XEXP (*split
, 0) == SET_DEST (x
)
4993 && XEXP (*split
, 1) == const0_rtx
)
4995 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4996 XEXP (SET_SRC (x
), 0),
4997 pos
, NULL_RTX
, 1, 1, 0, 0);
4998 if (extraction
!= 0)
5000 SUBST (SET_SRC (x
), extraction
);
5001 return find_split_point (loc
, insn
, false);
5007 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5008 is known to be on, this can be converted into a NEG of a shift. */
5009 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5010 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5011 && 1 <= (pos
= exact_log2
5012 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5013 GET_MODE (XEXP (SET_SRC (x
), 0))))))
5015 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5019 gen_rtx_LSHIFTRT (mode
,
5020 XEXP (SET_SRC (x
), 0),
5023 split
= find_split_point (&SET_SRC (x
), insn
, true);
5024 if (split
&& split
!= &SET_SRC (x
))
5030 inner
= XEXP (SET_SRC (x
), 0);
5032 /* We can't optimize if either mode is a partial integer
5033 mode as we don't know how many bits are significant
5035 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5036 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5040 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5046 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5047 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5049 inner
= XEXP (SET_SRC (x
), 0);
5050 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5051 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5053 if (BITS_BIG_ENDIAN
)
5054 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5055 unsignedp
= (code
== ZERO_EXTRACT
);
5064 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5066 machine_mode mode
= GET_MODE (SET_SRC (x
));
5068 /* For unsigned, we have a choice of a shift followed by an
5069 AND or two shifts. Use two shifts for field sizes where the
5070 constant might be too large. We assume here that we can
5071 always at least get 8-bit constants in an AND insn, which is
5072 true for every current RISC. */
5074 if (unsignedp
&& len
<= 8)
5076 unsigned HOST_WIDE_INT mask
5077 = (HOST_WIDE_INT_1U
<< len
) - 1;
5081 (mode
, gen_lowpart (mode
, inner
),
5083 gen_int_mode (mask
, mode
)));
5085 split
= find_split_point (&SET_SRC (x
), insn
, true);
5086 if (split
&& split
!= &SET_SRC (x
))
5093 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5094 gen_rtx_ASHIFT (mode
,
5095 gen_lowpart (mode
, inner
),
5096 GEN_INT (GET_MODE_PRECISION (mode
)
5098 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5100 split
= find_split_point (&SET_SRC (x
), insn
, true);
5101 if (split
&& split
!= &SET_SRC (x
))
5106 /* See if this is a simple operation with a constant as the second
5107 operand. It might be that this constant is out of range and hence
5108 could be used as a split point. */
5109 if (BINARY_P (SET_SRC (x
))
5110 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5111 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5112 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5113 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5114 return &XEXP (SET_SRC (x
), 1);
5116 /* Finally, see if this is a simple operation with its first operand
5117 not in a register. The operation might require this operand in a
5118 register, so return it as a split point. We can always do this
5119 because if the first operand were another operation, we would have
5120 already found it as a split point. */
5121 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5122 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5123 return &XEXP (SET_SRC (x
), 0);
5129 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5130 it is better to write this as (not (ior A B)) so we can split it.
5131 Similarly for IOR. */
5132 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5135 gen_rtx_NOT (GET_MODE (x
),
5136 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5138 XEXP (XEXP (x
, 0), 0),
5139 XEXP (XEXP (x
, 1), 0))));
5140 return find_split_point (loc
, insn
, set_src
);
5143 /* Many RISC machines have a large set of logical insns. If the
5144 second operand is a NOT, put it first so we will try to split the
5145 other operand first. */
5146 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5148 rtx tem
= XEXP (x
, 0);
5149 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5150 SUBST (XEXP (x
, 1), tem
);
5156 /* Canonicalization can produce (minus A (mult B C)), where C is a
5157 constant. It may be better to try splitting (plus (mult B -C) A)
5158 instead if this isn't a multiply by a power of two. */
5159 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5160 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5161 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5163 machine_mode mode
= GET_MODE (x
);
5164 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5165 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5166 SUBST (*loc
, gen_rtx_PLUS (mode
,
5168 XEXP (XEXP (x
, 1), 0),
5169 gen_int_mode (other_int
,
5172 return find_split_point (loc
, insn
, set_src
);
5175 /* Split at a multiply-accumulate instruction. However if this is
5176 the SET_SRC, we likely do not have such an instruction and it's
5177 worthless to try this split. */
5179 && (GET_CODE (XEXP (x
, 0)) == MULT
5180 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5181 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5188 /* Otherwise, select our actions depending on our rtx class. */
5189 switch (GET_RTX_CLASS (code
))
5191 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5193 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5198 case RTX_COMM_ARITH
:
5200 case RTX_COMM_COMPARE
:
5201 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5206 /* Some machines have (and (shift ...) ...) insns. If X is not
5207 an AND, but XEXP (X, 0) is, use it as our split point. */
5208 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5209 return &XEXP (x
, 0);
5211 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5217 /* Otherwise, we don't have a split point. */
5222 /* Throughout X, replace FROM with TO, and return the result.
5223 The result is TO if X is FROM;
5224 otherwise the result is X, but its contents may have been modified.
5225 If they were modified, a record was made in undobuf so that
5226 undo_all will (among other things) return X to its original state.
5228 If the number of changes necessary is too much to record to undo,
5229 the excess changes are not made, so the result is invalid.
5230 The changes already made can still be undone.
5231 undobuf.num_undo is incremented for such changes, so by testing that
5232 the caller can tell whether the result is valid.
5234 `n_occurrences' is incremented each time FROM is replaced.
5236 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5238 IN_COND is nonzero if we are at the top level of a condition.
5240 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5241 by copying if `n_occurrences' is nonzero. */
5244 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5246 enum rtx_code code
= GET_CODE (x
);
5247 machine_mode op0_mode
= VOIDmode
;
5252 /* Two expressions are equal if they are identical copies of a shared
5253 RTX or if they are both registers with the same register number
5256 #define COMBINE_RTX_EQUAL_P(X,Y) \
5258 || (REG_P (X) && REG_P (Y) \
5259 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5261 /* Do not substitute into clobbers of regs -- this will never result in
5263 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5266 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5269 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5272 /* If X and FROM are the same register but different modes, they
5273 will not have been seen as equal above. However, the log links code
5274 will make a LOG_LINKS entry for that case. If we do nothing, we
5275 will try to rerecognize our original insn and, when it succeeds,
5276 we will delete the feeding insn, which is incorrect.
5278 So force this insn not to match in this (rare) case. */
5279 if (! in_dest
&& code
== REG
&& REG_P (from
)
5280 && reg_overlap_mentioned_p (x
, from
))
5281 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5283 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5284 of which may contain things that can be combined. */
5285 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5288 /* It is possible to have a subexpression appear twice in the insn.
5289 Suppose that FROM is a register that appears within TO.
5290 Then, after that subexpression has been scanned once by `subst',
5291 the second time it is scanned, TO may be found. If we were
5292 to scan TO here, we would find FROM within it and create a
5293 self-referent rtl structure which is completely wrong. */
5294 if (COMBINE_RTX_EQUAL_P (x
, to
))
5297 /* Parallel asm_operands need special attention because all of the
5298 inputs are shared across the arms. Furthermore, unsharing the
5299 rtl results in recognition failures. Failure to handle this case
5300 specially can result in circular rtl.
5302 Solve this by doing a normal pass across the first entry of the
5303 parallel, and only processing the SET_DESTs of the subsequent
5306 if (code
== PARALLEL
5307 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5308 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5310 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5312 /* If this substitution failed, this whole thing fails. */
5313 if (GET_CODE (new_rtx
) == CLOBBER
5314 && XEXP (new_rtx
, 0) == const0_rtx
)
5317 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5319 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5321 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5324 && GET_CODE (dest
) != CC0
5325 && GET_CODE (dest
) != PC
)
5327 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5329 /* If this substitution failed, this whole thing fails. */
5330 if (GET_CODE (new_rtx
) == CLOBBER
5331 && XEXP (new_rtx
, 0) == const0_rtx
)
5334 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5340 len
= GET_RTX_LENGTH (code
);
5341 fmt
= GET_RTX_FORMAT (code
);
5343 /* We don't need to process a SET_DEST that is a register, CC0,
5344 or PC, so set up to skip this common case. All other cases
5345 where we want to suppress replacing something inside a
5346 SET_SRC are handled via the IN_DEST operand. */
5348 && (REG_P (SET_DEST (x
))
5349 || GET_CODE (SET_DEST (x
)) == CC0
5350 || GET_CODE (SET_DEST (x
)) == PC
))
5353 /* Trying to simplify the operands of a widening MULT is not likely
5354 to create RTL matching a machine insn. */
5356 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5357 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5358 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5359 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5360 && REG_P (XEXP (XEXP (x
, 0), 0))
5361 && REG_P (XEXP (XEXP (x
, 1), 0))
5366 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5369 op0_mode
= GET_MODE (XEXP (x
, 0));
5371 for (i
= 0; i
< len
; i
++)
5376 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5378 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5380 new_rtx
= (unique_copy
&& n_occurrences
5381 ? copy_rtx (to
) : to
);
5386 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5389 /* If this substitution failed, this whole thing
5391 if (GET_CODE (new_rtx
) == CLOBBER
5392 && XEXP (new_rtx
, 0) == const0_rtx
)
5396 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5399 else if (fmt
[i
] == 'e')
5401 /* If this is a register being set, ignore it. */
5402 new_rtx
= XEXP (x
, i
);
5405 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5407 || code
== STRICT_LOW_PART
))
5410 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5412 /* In general, don't install a subreg involving two
5413 modes not tieable. It can worsen register
5414 allocation, and can even make invalid reload
5415 insns, since the reg inside may need to be copied
5416 from in the outside mode, and that may be invalid
5417 if it is an fp reg copied in integer mode.
5419 We allow two exceptions to this: It is valid if
5420 it is inside another SUBREG and the mode of that
5421 SUBREG and the mode of the inside of TO is
5422 tieable and it is valid if X is a SET that copies
5425 if (GET_CODE (to
) == SUBREG
5426 && ! MODES_TIEABLE_P (GET_MODE (to
),
5427 GET_MODE (SUBREG_REG (to
)))
5428 && ! (code
== SUBREG
5429 && MODES_TIEABLE_P (GET_MODE (x
),
5430 GET_MODE (SUBREG_REG (to
))))
5434 && XEXP (x
, 0) == cc0_rtx
))))
5435 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5439 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5440 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5443 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5445 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5449 /* If we are in a SET_DEST, suppress most cases unless we
5450 have gone inside a MEM, in which case we want to
5451 simplify the address. We assume here that things that
5452 are actually part of the destination have their inner
5453 parts in the first expression. This is true for SUBREG,
5454 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5455 things aside from REG and MEM that should appear in a
5457 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5459 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5460 || code
== ZERO_EXTRACT
))
5463 code
== IF_THEN_ELSE
&& i
== 0,
5466 /* If we found that we will have to reject this combination,
5467 indicate that by returning the CLOBBER ourselves, rather than
5468 an expression containing it. This will speed things up as
5469 well as prevent accidents where two CLOBBERs are considered
5470 to be equal, thus producing an incorrect simplification. */
5472 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5475 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5477 machine_mode mode
= GET_MODE (x
);
5479 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5480 GET_MODE (SUBREG_REG (x
)),
5483 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5485 else if (CONST_SCALAR_INT_P (new_rtx
)
5486 && GET_CODE (x
) == ZERO_EXTEND
)
5488 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5489 new_rtx
, GET_MODE (XEXP (x
, 0)));
5493 SUBST (XEXP (x
, i
), new_rtx
);
5498 /* Check if we are loading something from the constant pool via float
5499 extension; in this case we would undo compress_float_constant
5500 optimization and degenerate constant load to an immediate value. */
5501 if (GET_CODE (x
) == FLOAT_EXTEND
5502 && MEM_P (XEXP (x
, 0))
5503 && MEM_READONLY_P (XEXP (x
, 0)))
5505 rtx tmp
= avoid_constant_pool_reference (x
);
5510 /* Try to simplify X. If the simplification changed the code, it is likely
5511 that further simplification will help, so loop, but limit the number
5512 of repetitions that will be performed. */
5514 for (i
= 0; i
< 4; i
++)
5516 /* If X is sufficiently simple, don't bother trying to do anything
5518 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5519 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5521 if (GET_CODE (x
) == code
)
5524 code
= GET_CODE (x
);
5526 /* We no longer know the original mode of operand 0 since we
5527 have changed the form of X) */
5528 op0_mode
= VOIDmode
;
5534 /* If X is a commutative operation whose operands are not in the canonical
5535 order, use substitutions to swap them. */
5538 maybe_swap_commutative_operands (rtx x
)
5540 if (COMMUTATIVE_ARITH_P (x
)
5541 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5543 rtx temp
= XEXP (x
, 0);
5544 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5545 SUBST (XEXP (x
, 1), temp
);
5549 /* Simplify X, a piece of RTL. We just operate on the expression at the
5550 outer level; call `subst' to simplify recursively. Return the new
5553 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5554 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5558 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5561 enum rtx_code code
= GET_CODE (x
);
5562 machine_mode mode
= GET_MODE (x
);
5566 /* If this is a commutative operation, put a constant last and a complex
5567 expression first. We don't need to do this for comparisons here. */
5568 maybe_swap_commutative_operands (x
);
5570 /* Try to fold this expression in case we have constants that weren't
5573 switch (GET_RTX_CLASS (code
))
5576 if (op0_mode
== VOIDmode
)
5577 op0_mode
= GET_MODE (XEXP (x
, 0));
5578 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5581 case RTX_COMM_COMPARE
:
5583 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5584 if (cmp_mode
== VOIDmode
)
5586 cmp_mode
= GET_MODE (XEXP (x
, 1));
5587 if (cmp_mode
== VOIDmode
)
5588 cmp_mode
= op0_mode
;
5590 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5591 XEXP (x
, 0), XEXP (x
, 1));
5594 case RTX_COMM_ARITH
:
5596 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5598 case RTX_BITFIELD_OPS
:
5600 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5601 XEXP (x
, 1), XEXP (x
, 2));
5610 code
= GET_CODE (temp
);
5611 op0_mode
= VOIDmode
;
5612 mode
= GET_MODE (temp
);
5615 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5616 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5617 things. Check for cases where both arms are testing the same
5620 Don't do anything if all operands are very simple. */
5623 && ((!OBJECT_P (XEXP (x
, 0))
5624 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5625 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5626 || (!OBJECT_P (XEXP (x
, 1))
5627 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5628 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5630 && (!OBJECT_P (XEXP (x
, 0))
5631 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5632 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5634 rtx cond
, true_rtx
, false_rtx
;
5636 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5638 /* If everything is a comparison, what we have is highly unlikely
5639 to be simpler, so don't use it. */
5640 && ! (COMPARISON_P (x
)
5641 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5643 rtx cop1
= const0_rtx
;
5644 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5646 if (cond_code
== NE
&& COMPARISON_P (cond
))
5649 /* Simplify the alternative arms; this may collapse the true and
5650 false arms to store-flag values. Be careful to use copy_rtx
5651 here since true_rtx or false_rtx might share RTL with x as a
5652 result of the if_then_else_cond call above. */
5653 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5654 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5656 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5657 is unlikely to be simpler. */
5658 if (general_operand (true_rtx
, VOIDmode
)
5659 && general_operand (false_rtx
, VOIDmode
))
5661 enum rtx_code reversed
;
5663 /* Restarting if we generate a store-flag expression will cause
5664 us to loop. Just drop through in this case. */
5666 /* If the result values are STORE_FLAG_VALUE and zero, we can
5667 just make the comparison operation. */
5668 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5669 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5671 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5672 && ((reversed
= reversed_comparison_code_parts
5673 (cond_code
, cond
, cop1
, NULL
))
5675 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5678 /* Likewise, we can make the negate of a comparison operation
5679 if the result values are - STORE_FLAG_VALUE and zero. */
5680 else if (CONST_INT_P (true_rtx
)
5681 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5682 && false_rtx
== const0_rtx
)
5683 x
= simplify_gen_unary (NEG
, mode
,
5684 simplify_gen_relational (cond_code
,
5688 else if (CONST_INT_P (false_rtx
)
5689 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5690 && true_rtx
== const0_rtx
5691 && ((reversed
= reversed_comparison_code_parts
5692 (cond_code
, cond
, cop1
, NULL
))
5694 x
= simplify_gen_unary (NEG
, mode
,
5695 simplify_gen_relational (reversed
,
5700 return gen_rtx_IF_THEN_ELSE (mode
,
5701 simplify_gen_relational (cond_code
,
5706 true_rtx
, false_rtx
);
5708 code
= GET_CODE (x
);
5709 op0_mode
= VOIDmode
;
5714 /* First see if we can apply the inverse distributive law. */
5715 if (code
== PLUS
|| code
== MINUS
5716 || code
== AND
|| code
== IOR
|| code
== XOR
)
5718 x
= apply_distributive_law (x
);
5719 code
= GET_CODE (x
);
5720 op0_mode
= VOIDmode
;
5723 /* If CODE is an associative operation not otherwise handled, see if we
5724 can associate some operands. This can win if they are constants or
5725 if they are logically related (i.e. (a & b) & a). */
5726 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5727 || code
== AND
|| code
== IOR
|| code
== XOR
5728 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5729 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5730 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5732 if (GET_CODE (XEXP (x
, 0)) == code
)
5734 rtx other
= XEXP (XEXP (x
, 0), 0);
5735 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5736 rtx inner_op1
= XEXP (x
, 1);
5739 /* Make sure we pass the constant operand if any as the second
5740 one if this is a commutative operation. */
5741 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5742 std::swap (inner_op0
, inner_op1
);
5743 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5744 : code
== DIV
? MULT
5746 mode
, inner_op0
, inner_op1
);
5748 /* For commutative operations, try the other pair if that one
5750 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5752 other
= XEXP (XEXP (x
, 0), 1);
5753 inner
= simplify_binary_operation (code
, mode
,
5754 XEXP (XEXP (x
, 0), 0),
5759 return simplify_gen_binary (code
, mode
, other
, inner
);
5763 /* A little bit of algebraic simplification here. */
5767 /* Ensure that our address has any ASHIFTs converted to MULT in case
5768 address-recognizing predicates are called later. */
5769 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5770 SUBST (XEXP (x
, 0), temp
);
5774 if (op0_mode
== VOIDmode
)
5775 op0_mode
= GET_MODE (SUBREG_REG (x
));
5777 /* See if this can be moved to simplify_subreg. */
5778 if (CONSTANT_P (SUBREG_REG (x
))
5779 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5780 /* Don't call gen_lowpart if the inner mode
5781 is VOIDmode and we cannot simplify it, as SUBREG without
5782 inner mode is invalid. */
5783 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5784 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5785 return gen_lowpart (mode
, SUBREG_REG (x
));
5787 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5791 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5796 /* If op is known to have all lower bits zero, the result is zero. */
5798 && SCALAR_INT_MODE_P (mode
)
5799 && SCALAR_INT_MODE_P (op0_mode
)
5800 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5801 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5802 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5803 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5804 & GET_MODE_MASK (mode
)) == 0)
5805 return CONST0_RTX (mode
);
5808 /* Don't change the mode of the MEM if that would change the meaning
5810 if (MEM_P (SUBREG_REG (x
))
5811 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5812 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5813 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5814 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5816 /* Note that we cannot do any narrowing for non-constants since
5817 we might have been counting on using the fact that some bits were
5818 zero. We now do this in the SET. */
5823 temp
= expand_compound_operation (XEXP (x
, 0));
5825 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5826 replaced by (lshiftrt X C). This will convert
5827 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5829 if (GET_CODE (temp
) == ASHIFTRT
5830 && CONST_INT_P (XEXP (temp
, 1))
5831 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5832 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5833 INTVAL (XEXP (temp
, 1)));
5835 /* If X has only a single bit that might be nonzero, say, bit I, convert
5836 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5837 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5838 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5839 or a SUBREG of one since we'd be making the expression more
5840 complex if it was just a register. */
5843 && ! (GET_CODE (temp
) == SUBREG
5844 && REG_P (SUBREG_REG (temp
)))
5845 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5847 rtx temp1
= simplify_shift_const
5848 (NULL_RTX
, ASHIFTRT
, mode
,
5849 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5850 GET_MODE_PRECISION (mode
) - 1 - i
),
5851 GET_MODE_PRECISION (mode
) - 1 - i
);
5853 /* If all we did was surround TEMP with the two shifts, we
5854 haven't improved anything, so don't use it. Otherwise,
5855 we are better off with TEMP1. */
5856 if (GET_CODE (temp1
) != ASHIFTRT
5857 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5858 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5864 /* We can't handle truncation to a partial integer mode here
5865 because we don't know the real bitsize of the partial
5867 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5870 if (HWI_COMPUTABLE_MODE_P (mode
))
5872 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5873 GET_MODE_MASK (mode
), 0));
5875 /* We can truncate a constant value and return it. */
5876 if (CONST_INT_P (XEXP (x
, 0)))
5877 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5879 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5880 whose value is a comparison can be replaced with a subreg if
5881 STORE_FLAG_VALUE permits. */
5882 if (HWI_COMPUTABLE_MODE_P (mode
)
5883 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5884 && (temp
= get_last_value (XEXP (x
, 0)))
5885 && COMPARISON_P (temp
))
5886 return gen_lowpart (mode
, XEXP (x
, 0));
5890 /* (const (const X)) can become (const X). Do it this way rather than
5891 returning the inner CONST since CONST can be shared with a
5893 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5894 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5898 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5899 can add in an offset. find_split_point will split this address up
5900 again if it doesn't match. */
5901 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5902 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5907 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5908 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5909 bit-field and can be replaced by either a sign_extend or a
5910 sign_extract. The `and' may be a zero_extend and the two
5911 <c>, -<c> constants may be reversed. */
5912 if (GET_CODE (XEXP (x
, 0)) == XOR
5913 && CONST_INT_P (XEXP (x
, 1))
5914 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5915 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5916 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5917 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5918 && HWI_COMPUTABLE_MODE_P (mode
)
5919 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5920 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5921 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5922 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
5923 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5924 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5925 == (unsigned int) i
+ 1))))
5926 return simplify_shift_const
5927 (NULL_RTX
, ASHIFTRT
, mode
,
5928 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5929 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5930 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5931 GET_MODE_PRECISION (mode
) - (i
+ 1));
5933 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5934 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5935 the bitsize of the mode - 1. This allows simplification of
5936 "a = (b & 8) == 0;" */
5937 if (XEXP (x
, 1) == constm1_rtx
5938 && !REG_P (XEXP (x
, 0))
5939 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5940 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5941 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5942 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5943 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5944 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5945 GET_MODE_PRECISION (mode
) - 1),
5946 GET_MODE_PRECISION (mode
) - 1);
5948 /* If we are adding two things that have no bits in common, convert
5949 the addition into an IOR. This will often be further simplified,
5950 for example in cases like ((a & 1) + (a & 2)), which can
5953 if (HWI_COMPUTABLE_MODE_P (mode
)
5954 && (nonzero_bits (XEXP (x
, 0), mode
)
5955 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5957 /* Try to simplify the expression further. */
5958 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5959 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5961 /* If we could, great. If not, do not go ahead with the IOR
5962 replacement, since PLUS appears in many special purpose
5963 address arithmetic instructions. */
5964 if (GET_CODE (temp
) != CLOBBER
5965 && (GET_CODE (temp
) != IOR
5966 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5967 || XEXP (temp
, 1) != XEXP (x
, 1))
5968 && (XEXP (temp
, 0) != XEXP (x
, 1)
5969 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5973 /* Canonicalize x + x into x << 1. */
5974 if (GET_MODE_CLASS (mode
) == MODE_INT
5975 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
5976 && !side_effects_p (XEXP (x
, 0)))
5977 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
5982 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5983 (and <foo> (const_int pow2-1)) */
5984 if (GET_CODE (XEXP (x
, 1)) == AND
5985 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5986 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
5987 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5988 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5989 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5993 /* If we have (mult (plus A B) C), apply the distributive law and then
5994 the inverse distributive law to see if things simplify. This
5995 occurs mostly in addresses, often when unrolling loops. */
5997 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5999 rtx result
= distribute_and_simplify_rtx (x
, 0);
6004 /* Try simplify a*(b/c) as (a*b)/c. */
6005 if (FLOAT_MODE_P (mode
) && flag_associative_math
6006 && GET_CODE (XEXP (x
, 0)) == DIV
)
6008 rtx tem
= simplify_binary_operation (MULT
, mode
,
6009 XEXP (XEXP (x
, 0), 0),
6012 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6017 /* If this is a divide by a power of two, treat it as a shift if
6018 its first operand is a shift. */
6019 if (CONST_INT_P (XEXP (x
, 1))
6020 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6021 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6022 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6023 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6024 || GET_CODE (XEXP (x
, 0)) == ROTATE
6025 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6026 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
6030 case GT
: case GTU
: case GE
: case GEU
:
6031 case LT
: case LTU
: case LE
: case LEU
:
6032 case UNEQ
: case LTGT
:
6033 case UNGT
: case UNGE
:
6034 case UNLT
: case UNLE
:
6035 case UNORDERED
: case ORDERED
:
6036 /* If the first operand is a condition code, we can't do anything
6038 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6039 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6040 && ! CC0_P (XEXP (x
, 0))))
6042 rtx op0
= XEXP (x
, 0);
6043 rtx op1
= XEXP (x
, 1);
6044 enum rtx_code new_code
;
6046 if (GET_CODE (op0
) == COMPARE
)
6047 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6049 /* Simplify our comparison, if possible. */
6050 new_code
= simplify_comparison (code
, &op0
, &op1
);
6052 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6053 if only the low-order bit is possibly nonzero in X (such as when
6054 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6055 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6056 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6059 Remove any ZERO_EXTRACT we made when thinking this was a
6060 comparison. It may now be simpler to use, e.g., an AND. If a
6061 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6062 the call to make_compound_operation in the SET case.
6064 Don't apply these optimizations if the caller would
6065 prefer a comparison rather than a value.
6066 E.g., for the condition in an IF_THEN_ELSE most targets need
6067 an explicit comparison. */
6072 else if (STORE_FLAG_VALUE
== 1
6073 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6074 && op1
== const0_rtx
6075 && mode
== GET_MODE (op0
)
6076 && nonzero_bits (op0
, mode
) == 1)
6077 return gen_lowpart (mode
,
6078 expand_compound_operation (op0
));
6080 else if (STORE_FLAG_VALUE
== 1
6081 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6082 && op1
== const0_rtx
6083 && mode
== GET_MODE (op0
)
6084 && (num_sign_bit_copies (op0
, mode
)
6085 == GET_MODE_PRECISION (mode
)))
6087 op0
= expand_compound_operation (op0
);
6088 return simplify_gen_unary (NEG
, mode
,
6089 gen_lowpart (mode
, op0
),
6093 else if (STORE_FLAG_VALUE
== 1
6094 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6095 && op1
== const0_rtx
6096 && mode
== GET_MODE (op0
)
6097 && nonzero_bits (op0
, mode
) == 1)
6099 op0
= expand_compound_operation (op0
);
6100 return simplify_gen_binary (XOR
, mode
,
6101 gen_lowpart (mode
, op0
),
6105 else if (STORE_FLAG_VALUE
== 1
6106 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6107 && op1
== const0_rtx
6108 && mode
== GET_MODE (op0
)
6109 && (num_sign_bit_copies (op0
, mode
)
6110 == GET_MODE_PRECISION (mode
)))
6112 op0
= expand_compound_operation (op0
);
6113 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6116 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6121 else if (STORE_FLAG_VALUE
== -1
6122 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6123 && op1
== const0_rtx
6124 && mode
== GET_MODE (op0
)
6125 && (num_sign_bit_copies (op0
, mode
)
6126 == GET_MODE_PRECISION (mode
)))
6127 return gen_lowpart (mode
,
6128 expand_compound_operation (op0
));
6130 else if (STORE_FLAG_VALUE
== -1
6131 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6132 && op1
== const0_rtx
6133 && mode
== GET_MODE (op0
)
6134 && nonzero_bits (op0
, mode
) == 1)
6136 op0
= expand_compound_operation (op0
);
6137 return simplify_gen_unary (NEG
, mode
,
6138 gen_lowpart (mode
, op0
),
6142 else if (STORE_FLAG_VALUE
== -1
6143 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6144 && op1
== const0_rtx
6145 && mode
== GET_MODE (op0
)
6146 && (num_sign_bit_copies (op0
, mode
)
6147 == GET_MODE_PRECISION (mode
)))
6149 op0
= expand_compound_operation (op0
);
6150 return simplify_gen_unary (NOT
, mode
,
6151 gen_lowpart (mode
, op0
),
6155 /* If X is 0/1, (eq X 0) is X-1. */
6156 else if (STORE_FLAG_VALUE
== -1
6157 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6158 && op1
== const0_rtx
6159 && mode
== GET_MODE (op0
)
6160 && nonzero_bits (op0
, mode
) == 1)
6162 op0
= expand_compound_operation (op0
);
6163 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6166 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6167 one bit that might be nonzero, we can convert (ne x 0) to
6168 (ashift x c) where C puts the bit in the sign bit. Remove any
6169 AND with STORE_FLAG_VALUE when we are done, since we are only
6170 going to test the sign bit. */
6171 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6172 && HWI_COMPUTABLE_MODE_P (mode
)
6173 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6174 && op1
== const0_rtx
6175 && mode
== GET_MODE (op0
)
6176 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6178 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6179 expand_compound_operation (op0
),
6180 GET_MODE_PRECISION (mode
) - 1 - i
);
6181 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6187 /* If the code changed, return a whole new comparison.
6188 We also need to avoid using SUBST in cases where
6189 simplify_comparison has widened a comparison with a CONST_INT,
6190 since in that case the wider CONST_INT may fail the sanity
6191 checks in do_SUBST. */
6192 if (new_code
!= code
6193 || (CONST_INT_P (op1
)
6194 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6195 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6196 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6198 /* Otherwise, keep this operation, but maybe change its operands.
6199 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6200 SUBST (XEXP (x
, 0), op0
);
6201 SUBST (XEXP (x
, 1), op1
);
6206 return simplify_if_then_else (x
);
6212 /* If we are processing SET_DEST, we are done. */
6216 return expand_compound_operation (x
);
6219 return simplify_set (x
);
6223 return simplify_logical (x
);
6230 /* If this is a shift by a constant amount, simplify it. */
6231 if (CONST_INT_P (XEXP (x
, 1)))
6232 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6233 INTVAL (XEXP (x
, 1)));
6235 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6237 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6239 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6251 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6254 simplify_if_then_else (rtx x
)
6256 machine_mode mode
= GET_MODE (x
);
6257 rtx cond
= XEXP (x
, 0);
6258 rtx true_rtx
= XEXP (x
, 1);
6259 rtx false_rtx
= XEXP (x
, 2);
6260 enum rtx_code true_code
= GET_CODE (cond
);
6261 int comparison_p
= COMPARISON_P (cond
);
6264 enum rtx_code false_code
;
6267 /* Simplify storing of the truth value. */
6268 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6269 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6270 XEXP (cond
, 0), XEXP (cond
, 1));
6272 /* Also when the truth value has to be reversed. */
6274 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6275 && (reversed
= reversed_comparison (cond
, mode
)))
6278 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6279 in it is being compared against certain values. Get the true and false
6280 comparisons and see if that says anything about the value of each arm. */
6283 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6285 && REG_P (XEXP (cond
, 0)))
6288 rtx from
= XEXP (cond
, 0);
6289 rtx true_val
= XEXP (cond
, 1);
6290 rtx false_val
= true_val
;
6293 /* If FALSE_CODE is EQ, swap the codes and arms. */
6295 if (false_code
== EQ
)
6297 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6298 std::swap (true_rtx
, false_rtx
);
6301 /* If we are comparing against zero and the expression being tested has
6302 only a single bit that might be nonzero, that is its value when it is
6303 not equal to zero. Similarly if it is known to be -1 or 0. */
6305 if (true_code
== EQ
&& true_val
== const0_rtx
6306 && pow2p_hwi (nzb
= nonzero_bits (from
, GET_MODE (from
))))
6309 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6311 else if (true_code
== EQ
&& true_val
== const0_rtx
6312 && (num_sign_bit_copies (from
, GET_MODE (from
))
6313 == GET_MODE_PRECISION (GET_MODE (from
))))
6316 false_val
= constm1_rtx
;
6319 /* Now simplify an arm if we know the value of the register in the
6320 branch and it is used in the arm. Be careful due to the potential
6321 of locally-shared RTL. */
6323 if (reg_mentioned_p (from
, true_rtx
))
6324 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6326 pc_rtx
, pc_rtx
, 0, 0, 0);
6327 if (reg_mentioned_p (from
, false_rtx
))
6328 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6330 pc_rtx
, pc_rtx
, 0, 0, 0);
6332 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6333 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6335 true_rtx
= XEXP (x
, 1);
6336 false_rtx
= XEXP (x
, 2);
6337 true_code
= GET_CODE (cond
);
6340 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6341 reversed, do so to avoid needing two sets of patterns for
6342 subtract-and-branch insns. Similarly if we have a constant in the true
6343 arm, the false arm is the same as the first operand of the comparison, or
6344 the false arm is more complicated than the true arm. */
6347 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6348 && (true_rtx
== pc_rtx
6349 || (CONSTANT_P (true_rtx
)
6350 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6351 || true_rtx
== const0_rtx
6352 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6353 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6354 && !OBJECT_P (false_rtx
))
6355 || reg_mentioned_p (true_rtx
, false_rtx
)
6356 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6358 true_code
= reversed_comparison_code (cond
, NULL
);
6359 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6360 SUBST (XEXP (x
, 1), false_rtx
);
6361 SUBST (XEXP (x
, 2), true_rtx
);
6363 std::swap (true_rtx
, false_rtx
);
6366 /* It is possible that the conditional has been simplified out. */
6367 true_code
= GET_CODE (cond
);
6368 comparison_p
= COMPARISON_P (cond
);
6371 /* If the two arms are identical, we don't need the comparison. */
6373 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6376 /* Convert a == b ? b : a to "a". */
6377 if (true_code
== EQ
&& ! side_effects_p (cond
)
6378 && !HONOR_NANS (mode
)
6379 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6380 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6382 else if (true_code
== NE
&& ! side_effects_p (cond
)
6383 && !HONOR_NANS (mode
)
6384 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6385 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6388 /* Look for cases where we have (abs x) or (neg (abs X)). */
6390 if (GET_MODE_CLASS (mode
) == MODE_INT
6392 && XEXP (cond
, 1) == const0_rtx
6393 && GET_CODE (false_rtx
) == NEG
6394 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6395 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6396 && ! side_effects_p (true_rtx
))
6401 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6405 simplify_gen_unary (NEG
, mode
,
6406 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6412 /* Look for MIN or MAX. */
6414 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6416 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6417 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6418 && ! side_effects_p (cond
))
6423 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6426 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6429 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6432 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6437 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6438 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6439 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6440 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6441 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6442 neither 1 or -1, but it isn't worth checking for. */
6444 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6446 && GET_MODE_CLASS (mode
) == MODE_INT
6447 && ! side_effects_p (x
))
6449 rtx t
= make_compound_operation (true_rtx
, SET
);
6450 rtx f
= make_compound_operation (false_rtx
, SET
);
6451 rtx cond_op0
= XEXP (cond
, 0);
6452 rtx cond_op1
= XEXP (cond
, 1);
6453 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6454 machine_mode m
= mode
;
6455 rtx z
= 0, c1
= NULL_RTX
;
6457 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6458 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6459 || GET_CODE (t
) == ASHIFT
6460 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6461 && rtx_equal_p (XEXP (t
, 0), f
))
6462 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6464 /* If an identity-zero op is commutative, check whether there
6465 would be a match if we swapped the operands. */
6466 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6467 || GET_CODE (t
) == XOR
)
6468 && rtx_equal_p (XEXP (t
, 1), f
))
6469 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6470 else if (GET_CODE (t
) == SIGN_EXTEND
6471 && (GET_CODE (XEXP (t
, 0)) == PLUS
6472 || GET_CODE (XEXP (t
, 0)) == MINUS
6473 || GET_CODE (XEXP (t
, 0)) == IOR
6474 || GET_CODE (XEXP (t
, 0)) == XOR
6475 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6476 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6477 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6478 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6479 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6480 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6481 && (num_sign_bit_copies (f
, GET_MODE (f
))
6483 (GET_MODE_PRECISION (mode
)
6484 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6486 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6487 extend_op
= SIGN_EXTEND
;
6488 m
= GET_MODE (XEXP (t
, 0));
6490 else if (GET_CODE (t
) == SIGN_EXTEND
6491 && (GET_CODE (XEXP (t
, 0)) == PLUS
6492 || GET_CODE (XEXP (t
, 0)) == IOR
6493 || GET_CODE (XEXP (t
, 0)) == XOR
)
6494 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6495 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6496 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6497 && (num_sign_bit_copies (f
, GET_MODE (f
))
6499 (GET_MODE_PRECISION (mode
)
6500 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6502 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6503 extend_op
= SIGN_EXTEND
;
6504 m
= GET_MODE (XEXP (t
, 0));
6506 else if (GET_CODE (t
) == ZERO_EXTEND
6507 && (GET_CODE (XEXP (t
, 0)) == PLUS
6508 || GET_CODE (XEXP (t
, 0)) == MINUS
6509 || GET_CODE (XEXP (t
, 0)) == IOR
6510 || GET_CODE (XEXP (t
, 0)) == XOR
6511 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6512 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6513 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6514 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6515 && HWI_COMPUTABLE_MODE_P (mode
)
6516 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6517 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6518 && ((nonzero_bits (f
, GET_MODE (f
))
6519 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6522 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6523 extend_op
= ZERO_EXTEND
;
6524 m
= GET_MODE (XEXP (t
, 0));
6526 else if (GET_CODE (t
) == ZERO_EXTEND
6527 && (GET_CODE (XEXP (t
, 0)) == PLUS
6528 || GET_CODE (XEXP (t
, 0)) == IOR
6529 || GET_CODE (XEXP (t
, 0)) == XOR
)
6530 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6531 && HWI_COMPUTABLE_MODE_P (mode
)
6532 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6533 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6534 && ((nonzero_bits (f
, GET_MODE (f
))
6535 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6538 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6539 extend_op
= ZERO_EXTEND
;
6540 m
= GET_MODE (XEXP (t
, 0));
6545 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6546 cond_op0
, cond_op1
),
6547 pc_rtx
, pc_rtx
, 0, 0, 0);
6548 temp
= simplify_gen_binary (MULT
, m
, temp
,
6549 simplify_gen_binary (MULT
, m
, c1
,
6551 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6552 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6554 if (extend_op
!= UNKNOWN
)
6555 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6561 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6562 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6563 negation of a single bit, we can convert this operation to a shift. We
6564 can actually do this more generally, but it doesn't seem worth it. */
6566 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6567 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6568 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6569 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6570 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6571 == GET_MODE_PRECISION (mode
))
6572 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6574 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6575 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6577 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6578 non-zero bit in A is C1. */
6579 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6580 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6581 && INTEGRAL_MODE_P (GET_MODE (XEXP (cond
, 0)))
6582 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6583 == nonzero_bits (XEXP (cond
, 0), GET_MODE (XEXP (cond
, 0)))
6584 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6586 rtx val
= XEXP (cond
, 0);
6587 machine_mode val_mode
= GET_MODE (val
);
6588 if (val_mode
== mode
)
6590 else if (GET_MODE_PRECISION (val_mode
) < GET_MODE_PRECISION (mode
))
6591 return simplify_gen_unary (ZERO_EXTEND
, mode
, val
, val_mode
);
6597 /* Simplify X, a SET expression. Return the new expression. */
6600 simplify_set (rtx x
)
6602 rtx src
= SET_SRC (x
);
6603 rtx dest
= SET_DEST (x
);
6605 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6606 rtx_insn
*other_insn
;
6609 /* (set (pc) (return)) gets written as (return). */
6610 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6613 /* Now that we know for sure which bits of SRC we are using, see if we can
6614 simplify the expression for the object knowing that we only need the
6617 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6619 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6620 SUBST (SET_SRC (x
), src
);
6623 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6624 the comparison result and try to simplify it unless we already have used
6625 undobuf.other_insn. */
6626 if ((GET_MODE_CLASS (mode
) == MODE_CC
6627 || GET_CODE (src
) == COMPARE
6629 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6630 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6631 && COMPARISON_P (*cc_use
)
6632 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6634 enum rtx_code old_code
= GET_CODE (*cc_use
);
6635 enum rtx_code new_code
;
6637 int other_changed
= 0;
6638 rtx inner_compare
= NULL_RTX
;
6639 machine_mode compare_mode
= GET_MODE (dest
);
6641 if (GET_CODE (src
) == COMPARE
)
6643 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6644 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6646 inner_compare
= op0
;
6647 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6651 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6653 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6656 new_code
= old_code
;
6657 else if (!CONSTANT_P (tmp
))
6659 new_code
= GET_CODE (tmp
);
6660 op0
= XEXP (tmp
, 0);
6661 op1
= XEXP (tmp
, 1);
6665 rtx pat
= PATTERN (other_insn
);
6666 undobuf
.other_insn
= other_insn
;
6667 SUBST (*cc_use
, tmp
);
6669 /* Attempt to simplify CC user. */
6670 if (GET_CODE (pat
) == SET
)
6672 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6673 if (new_rtx
!= NULL_RTX
)
6674 SUBST (SET_SRC (pat
), new_rtx
);
6677 /* Convert X into a no-op move. */
6678 SUBST (SET_DEST (x
), pc_rtx
);
6679 SUBST (SET_SRC (x
), pc_rtx
);
6683 /* Simplify our comparison, if possible. */
6684 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6686 #ifdef SELECT_CC_MODE
6687 /* If this machine has CC modes other than CCmode, check to see if we
6688 need to use a different CC mode here. */
6689 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6690 compare_mode
= GET_MODE (op0
);
6691 else if (inner_compare
6692 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6693 && new_code
== old_code
6694 && op0
== XEXP (inner_compare
, 0)
6695 && op1
== XEXP (inner_compare
, 1))
6696 compare_mode
= GET_MODE (inner_compare
);
6698 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6700 /* If the mode changed, we have to change SET_DEST, the mode in the
6701 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6702 a hard register, just build new versions with the proper mode. If it
6703 is a pseudo, we lose unless it is only time we set the pseudo, in
6704 which case we can safely change its mode. */
6705 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6707 if (can_change_dest_mode (dest
, 0, compare_mode
))
6709 unsigned int regno
= REGNO (dest
);
6712 if (regno
< FIRST_PSEUDO_REGISTER
)
6713 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6716 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6717 new_dest
= regno_reg_rtx
[regno
];
6720 SUBST (SET_DEST (x
), new_dest
);
6721 SUBST (XEXP (*cc_use
, 0), new_dest
);
6727 #endif /* SELECT_CC_MODE */
6729 /* If the code changed, we have to build a new comparison in
6730 undobuf.other_insn. */
6731 if (new_code
!= old_code
)
6733 int other_changed_previously
= other_changed
;
6734 unsigned HOST_WIDE_INT mask
;
6735 rtx old_cc_use
= *cc_use
;
6737 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6741 /* If the only change we made was to change an EQ into an NE or
6742 vice versa, OP0 has only one bit that might be nonzero, and OP1
6743 is zero, check if changing the user of the condition code will
6744 produce a valid insn. If it won't, we can keep the original code
6745 in that insn by surrounding our operation with an XOR. */
6747 if (((old_code
== NE
&& new_code
== EQ
)
6748 || (old_code
== EQ
&& new_code
== NE
))
6749 && ! other_changed_previously
&& op1
== const0_rtx
6750 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6751 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6753 rtx pat
= PATTERN (other_insn
), note
= 0;
6755 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6756 && ! check_asm_operands (pat
)))
6758 *cc_use
= old_cc_use
;
6761 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6769 undobuf
.other_insn
= other_insn
;
6771 /* Don't generate a compare of a CC with 0, just use that CC. */
6772 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6774 SUBST (SET_SRC (x
), op0
);
6777 /* Otherwise, if we didn't previously have the same COMPARE we
6778 want, create it from scratch. */
6779 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6780 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6782 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6788 /* Get SET_SRC in a form where we have placed back any
6789 compound expressions. Then do the checks below. */
6790 src
= make_compound_operation (src
, SET
);
6791 SUBST (SET_SRC (x
), src
);
6794 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6795 and X being a REG or (subreg (reg)), we may be able to convert this to
6796 (set (subreg:m2 x) (op)).
6798 We can always do this if M1 is narrower than M2 because that means that
6799 we only care about the low bits of the result.
6801 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6802 perform a narrower operation than requested since the high-order bits will
6803 be undefined. On machine where it is defined, this transformation is safe
6804 as long as M1 and M2 have the same number of words. */
6806 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6807 && !OBJECT_P (SUBREG_REG (src
))
6808 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6810 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6811 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6812 && (WORD_REGISTER_OPERATIONS
6813 || (GET_MODE_SIZE (GET_MODE (src
))
6814 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6815 #ifdef CANNOT_CHANGE_MODE_CLASS
6816 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6817 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6818 GET_MODE (SUBREG_REG (src
)),
6822 || (GET_CODE (dest
) == SUBREG
6823 && REG_P (SUBREG_REG (dest
)))))
6825 SUBST (SET_DEST (x
),
6826 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6828 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6830 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6833 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6836 && GET_CODE (src
) == SUBREG
6837 && subreg_lowpart_p (src
)
6838 && (GET_MODE_PRECISION (GET_MODE (src
))
6839 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6841 rtx inner
= SUBREG_REG (src
);
6842 machine_mode inner_mode
= GET_MODE (inner
);
6844 /* Here we make sure that we don't have a sign bit on. */
6845 if (val_signbit_known_clear_p (GET_MODE (src
),
6846 nonzero_bits (inner
, inner_mode
)))
6848 SUBST (SET_SRC (x
), inner
);
6853 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6854 would require a paradoxical subreg. Replace the subreg with a
6855 zero_extend to avoid the reload that would otherwise be required. */
6857 enum rtx_code extend_op
;
6858 if (paradoxical_subreg_p (src
)
6859 && MEM_P (SUBREG_REG (src
))
6860 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6863 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6868 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6869 are comparing an item known to be 0 or -1 against 0, use a logical
6870 operation instead. Check for one of the arms being an IOR of the other
6871 arm with some value. We compute three terms to be IOR'ed together. In
6872 practice, at most two will be nonzero. Then we do the IOR's. */
6874 if (GET_CODE (dest
) != PC
6875 && GET_CODE (src
) == IF_THEN_ELSE
6876 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6877 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6878 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6879 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6880 && (!HAVE_conditional_move
6881 || ! can_conditionally_move_p (GET_MODE (src
)))
6882 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6883 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6884 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6885 && ! side_effects_p (src
))
6887 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6888 ? XEXP (src
, 1) : XEXP (src
, 2));
6889 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6890 ? XEXP (src
, 2) : XEXP (src
, 1));
6891 rtx term1
= const0_rtx
, term2
, term3
;
6893 if (GET_CODE (true_rtx
) == IOR
6894 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6895 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6896 else if (GET_CODE (true_rtx
) == IOR
6897 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6898 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6899 else if (GET_CODE (false_rtx
) == IOR
6900 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6901 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6902 else if (GET_CODE (false_rtx
) == IOR
6903 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6904 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6906 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6907 XEXP (XEXP (src
, 0), 0), true_rtx
);
6908 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6909 simplify_gen_unary (NOT
, GET_MODE (src
),
6910 XEXP (XEXP (src
, 0), 0),
6915 simplify_gen_binary (IOR
, GET_MODE (src
),
6916 simplify_gen_binary (IOR
, GET_MODE (src
),
6923 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6924 whole thing fail. */
6925 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6927 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6930 /* Convert this into a field assignment operation, if possible. */
6931 return make_field_assignment (x
);
6934 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6938 simplify_logical (rtx x
)
6940 machine_mode mode
= GET_MODE (x
);
6941 rtx op0
= XEXP (x
, 0);
6942 rtx op1
= XEXP (x
, 1);
6944 switch (GET_CODE (x
))
6947 /* We can call simplify_and_const_int only if we don't lose
6948 any (sign) bits when converting INTVAL (op1) to
6949 "unsigned HOST_WIDE_INT". */
6950 if (CONST_INT_P (op1
)
6951 && (HWI_COMPUTABLE_MODE_P (mode
)
6952 || INTVAL (op1
) > 0))
6954 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6955 if (GET_CODE (x
) != AND
)
6962 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6963 apply the distributive law and then the inverse distributive
6964 law to see if things simplify. */
6965 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6967 rtx result
= distribute_and_simplify_rtx (x
, 0);
6971 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6973 rtx result
= distribute_and_simplify_rtx (x
, 1);
6980 /* If we have (ior (and A B) C), apply the distributive law and then
6981 the inverse distributive law to see if things simplify. */
6983 if (GET_CODE (op0
) == AND
)
6985 rtx result
= distribute_and_simplify_rtx (x
, 0);
6990 if (GET_CODE (op1
) == AND
)
6992 rtx result
= distribute_and_simplify_rtx (x
, 1);
7005 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7006 operations" because they can be replaced with two more basic operations.
7007 ZERO_EXTEND is also considered "compound" because it can be replaced with
7008 an AND operation, which is simpler, though only one operation.
7010 The function expand_compound_operation is called with an rtx expression
7011 and will convert it to the appropriate shifts and AND operations,
7012 simplifying at each stage.
7014 The function make_compound_operation is called to convert an expression
7015 consisting of shifts and ANDs into the equivalent compound expression.
7016 It is the inverse of this function, loosely speaking. */
7019 expand_compound_operation (rtx x
)
7021 unsigned HOST_WIDE_INT pos
= 0, len
;
7023 unsigned int modewidth
;
7026 switch (GET_CODE (x
))
7032 /* We can't necessarily use a const_int for a multiword mode;
7033 it depends on implicitly extending the value.
7034 Since we don't know the right way to extend it,
7035 we can't tell whether the implicit way is right.
7037 Even for a mode that is no wider than a const_int,
7038 we can't win, because we need to sign extend one of its bits through
7039 the rest of it, and we don't know which bit. */
7040 if (CONST_INT_P (XEXP (x
, 0)))
7043 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7044 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7045 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7046 reloaded. If not for that, MEM's would very rarely be safe.
7048 Reject MODEs bigger than a word, because we might not be able
7049 to reference a two-register group starting with an arbitrary register
7050 (and currently gen_lowpart might crash for a SUBREG). */
7052 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7055 /* Reject MODEs that aren't scalar integers because turning vector
7056 or complex modes into shifts causes problems. */
7058 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7061 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7062 /* If the inner object has VOIDmode (the only way this can happen
7063 is if it is an ASM_OPERANDS), we can't do anything since we don't
7064 know how much masking to do. */
7076 /* If the operand is a CLOBBER, just return it. */
7077 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7080 if (!CONST_INT_P (XEXP (x
, 1))
7081 || !CONST_INT_P (XEXP (x
, 2))
7082 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7085 /* Reject MODEs that aren't scalar integers because turning vector
7086 or complex modes into shifts causes problems. */
7088 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7091 len
= INTVAL (XEXP (x
, 1));
7092 pos
= INTVAL (XEXP (x
, 2));
7094 /* This should stay within the object being extracted, fail otherwise. */
7095 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7098 if (BITS_BIG_ENDIAN
)
7099 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7106 /* Convert sign extension to zero extension, if we know that the high
7107 bit is not set, as this is easier to optimize. It will be converted
7108 back to cheaper alternative in make_extraction. */
7109 if (GET_CODE (x
) == SIGN_EXTEND
7110 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7111 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7112 & ~(((unsigned HOST_WIDE_INT
)
7113 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7117 machine_mode mode
= GET_MODE (x
);
7118 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7119 rtx temp2
= expand_compound_operation (temp
);
7121 /* Make sure this is a profitable operation. */
7122 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7123 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7125 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7126 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7132 /* We can optimize some special cases of ZERO_EXTEND. */
7133 if (GET_CODE (x
) == ZERO_EXTEND
)
7135 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7136 know that the last value didn't have any inappropriate bits
7138 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7139 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7140 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7141 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7142 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7143 return XEXP (XEXP (x
, 0), 0);
7145 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7146 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7147 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7148 && subreg_lowpart_p (XEXP (x
, 0))
7149 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7150 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7151 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7152 return SUBREG_REG (XEXP (x
, 0));
7154 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7155 is a comparison and STORE_FLAG_VALUE permits. This is like
7156 the first case, but it works even when GET_MODE (x) is larger
7157 than HOST_WIDE_INT. */
7158 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7159 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7160 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7161 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7162 <= HOST_BITS_PER_WIDE_INT
)
7163 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7164 return XEXP (XEXP (x
, 0), 0);
7166 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7167 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7168 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7169 && subreg_lowpart_p (XEXP (x
, 0))
7170 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7171 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7172 <= HOST_BITS_PER_WIDE_INT
)
7173 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7174 return SUBREG_REG (XEXP (x
, 0));
7178 /* If we reach here, we want to return a pair of shifts. The inner
7179 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7180 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7181 logical depending on the value of UNSIGNEDP.
7183 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7184 converted into an AND of a shift.
7186 We must check for the case where the left shift would have a negative
7187 count. This can happen in a case like (x >> 31) & 255 on machines
7188 that can't shift by a constant. On those machines, we would first
7189 combine the shift with the AND to produce a variable-position
7190 extraction. Then the constant of 31 would be substituted in
7191 to produce such a position. */
7193 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7194 if (modewidth
>= pos
+ len
)
7196 machine_mode mode
= GET_MODE (x
);
7197 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7198 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7200 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7201 tem
, modewidth
- pos
- len
);
7202 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7203 mode
, tem
, modewidth
- len
);
7205 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7206 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7207 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7210 (HOST_WIDE_INT_1U
<< len
) - 1);
7212 /* Any other cases we can't handle. */
7215 /* If we couldn't do this for some reason, return the original
7217 if (GET_CODE (tem
) == CLOBBER
)
7223 /* X is a SET which contains an assignment of one object into
7224 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7225 or certain SUBREGS). If possible, convert it into a series of
7228 We half-heartedly support variable positions, but do not at all
7229 support variable lengths. */
7232 expand_field_assignment (const_rtx x
)
7235 rtx pos
; /* Always counts from low bit. */
7237 rtx mask
, cleared
, masked
;
7238 machine_mode compute_mode
;
7240 /* Loop until we find something we can't simplify. */
7243 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7244 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7246 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7247 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7248 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7250 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7251 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7253 inner
= XEXP (SET_DEST (x
), 0);
7254 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7255 pos
= XEXP (SET_DEST (x
), 2);
7257 /* A constant position should stay within the width of INNER. */
7258 if (CONST_INT_P (pos
)
7259 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7262 if (BITS_BIG_ENDIAN
)
7264 if (CONST_INT_P (pos
))
7265 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7267 else if (GET_CODE (pos
) == MINUS
7268 && CONST_INT_P (XEXP (pos
, 1))
7269 && (INTVAL (XEXP (pos
, 1))
7270 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7271 /* If position is ADJUST - X, new position is X. */
7272 pos
= XEXP (pos
, 0);
7275 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7276 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7277 gen_int_mode (prec
- len
,
7284 /* A SUBREG between two modes that occupy the same numbers of words
7285 can be done by moving the SUBREG to the source. */
7286 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7287 /* We need SUBREGs to compute nonzero_bits properly. */
7288 && nonzero_sign_valid
7289 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7290 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7291 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7292 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7294 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7296 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7303 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7304 inner
= SUBREG_REG (inner
);
7306 compute_mode
= GET_MODE (inner
);
7308 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7309 if (! SCALAR_INT_MODE_P (compute_mode
))
7313 /* Don't do anything for vector or complex integral types. */
7314 if (! FLOAT_MODE_P (compute_mode
))
7317 /* Try to find an integral mode to pun with. */
7318 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7319 if (imode
== BLKmode
)
7322 compute_mode
= imode
;
7323 inner
= gen_lowpart (imode
, inner
);
7326 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7327 if (len
>= HOST_BITS_PER_WIDE_INT
)
7330 /* Don't try to compute in too wide unsupported modes. */
7331 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7334 /* Now compute the equivalent expression. Make a copy of INNER
7335 for the SET_DEST in case it is a MEM into which we will substitute;
7336 we don't want shared RTL in that case. */
7337 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7339 cleared
= simplify_gen_binary (AND
, compute_mode
,
7340 simplify_gen_unary (NOT
, compute_mode
,
7341 simplify_gen_binary (ASHIFT
,
7346 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7347 simplify_gen_binary (
7349 gen_lowpart (compute_mode
, SET_SRC (x
)),
7353 x
= gen_rtx_SET (copy_rtx (inner
),
7354 simplify_gen_binary (IOR
, compute_mode
,
7361 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7362 it is an RTX that represents the (variable) starting position; otherwise,
7363 POS is the (constant) starting bit position. Both are counted from the LSB.
7365 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7367 IN_DEST is nonzero if this is a reference in the destination of a SET.
7368 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7369 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7372 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7373 ZERO_EXTRACT should be built even for bits starting at bit 0.
7375 MODE is the desired mode of the result (if IN_DEST == 0).
7377 The result is an RTX for the extraction or NULL_RTX if the target
7381 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7382 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7383 int in_dest
, int in_compare
)
7385 /* This mode describes the size of the storage area
7386 to fetch the overall value from. Within that, we
7387 ignore the POS lowest bits, etc. */
7388 machine_mode is_mode
= GET_MODE (inner
);
7389 machine_mode inner_mode
;
7390 machine_mode wanted_inner_mode
;
7391 machine_mode wanted_inner_reg_mode
= word_mode
;
7392 machine_mode pos_mode
= word_mode
;
7393 machine_mode extraction_mode
= word_mode
;
7394 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7396 rtx orig_pos_rtx
= pos_rtx
;
7397 HOST_WIDE_INT orig_pos
;
7399 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7400 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7402 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7404 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7405 consider just the QI as the memory to extract from.
7406 The subreg adds or removes high bits; its mode is
7407 irrelevant to the meaning of this extraction,
7408 since POS and LEN count from the lsb. */
7409 if (MEM_P (SUBREG_REG (inner
)))
7410 is_mode
= GET_MODE (SUBREG_REG (inner
));
7411 inner
= SUBREG_REG (inner
);
7413 else if (GET_CODE (inner
) == ASHIFT
7414 && CONST_INT_P (XEXP (inner
, 1))
7415 && pos_rtx
== 0 && pos
== 0
7416 && len
> UINTVAL (XEXP (inner
, 1)))
7418 /* We're extracting the least significant bits of an rtx
7419 (ashift X (const_int C)), where LEN > C. Extract the
7420 least significant (LEN - C) bits of X, giving an rtx
7421 whose mode is MODE, then shift it left C times. */
7422 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7423 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7424 unsignedp
, in_dest
, in_compare
);
7426 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7428 else if (GET_CODE (inner
) == TRUNCATE
)
7429 inner
= XEXP (inner
, 0);
7431 inner_mode
= GET_MODE (inner
);
7433 /* See if this can be done without an extraction. We never can if the
7434 width of the field is not the same as that of some integer mode. For
7435 registers, we can only avoid the extraction if the position is at the
7436 low-order bit and this is either not in the destination or we have the
7437 appropriate STRICT_LOW_PART operation available.
7439 For MEM, we can avoid an extract if the field starts on an appropriate
7440 boundary and we can change the mode of the memory reference. */
7442 if (tmode
!= BLKmode
7443 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7445 && (pos
== 0 || REG_P (inner
))
7446 && (inner_mode
== tmode
7448 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7449 || reg_truncated_to_mode (tmode
, inner
))
7452 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7453 || (MEM_P (inner
) && pos_rtx
== 0
7455 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7456 : BITS_PER_UNIT
)) == 0
7457 /* We can't do this if we are widening INNER_MODE (it
7458 may not be aligned, for one thing). */
7459 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7460 && (inner_mode
== tmode
7461 || (! mode_dependent_address_p (XEXP (inner
, 0),
7462 MEM_ADDR_SPACE (inner
))
7463 && ! MEM_VOLATILE_P (inner
))))))
7465 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7466 field. If the original and current mode are the same, we need not
7467 adjust the offset. Otherwise, we do if bytes big endian.
7469 If INNER is not a MEM, get a piece consisting of just the field
7470 of interest (in this case POS % BITS_PER_WORD must be 0). */
7474 HOST_WIDE_INT offset
;
7476 /* POS counts from lsb, but make OFFSET count in memory order. */
7477 if (BYTES_BIG_ENDIAN
)
7478 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7480 offset
= pos
/ BITS_PER_UNIT
;
7482 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7484 else if (REG_P (inner
))
7486 if (tmode
!= inner_mode
)
7488 /* We can't call gen_lowpart in a DEST since we
7489 always want a SUBREG (see below) and it would sometimes
7490 return a new hard register. */
7493 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7495 if (WORDS_BIG_ENDIAN
7496 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7497 final_word
= ((GET_MODE_SIZE (inner_mode
)
7498 - GET_MODE_SIZE (tmode
))
7499 / UNITS_PER_WORD
) - final_word
;
7501 final_word
*= UNITS_PER_WORD
;
7502 if (BYTES_BIG_ENDIAN
&&
7503 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7504 final_word
+= (GET_MODE_SIZE (inner_mode
)
7505 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7507 /* Avoid creating invalid subregs, for example when
7508 simplifying (x>>32)&255. */
7509 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7512 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7515 new_rtx
= gen_lowpart (tmode
, inner
);
7521 new_rtx
= force_to_mode (inner
, tmode
,
7522 len
>= HOST_BITS_PER_WIDE_INT
7524 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7526 /* If this extraction is going into the destination of a SET,
7527 make a STRICT_LOW_PART unless we made a MEM. */
7530 return (MEM_P (new_rtx
) ? new_rtx
7531 : (GET_CODE (new_rtx
) != SUBREG
7532 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7533 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7538 if (CONST_SCALAR_INT_P (new_rtx
))
7539 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7540 mode
, new_rtx
, tmode
);
7542 /* If we know that no extraneous bits are set, and that the high
7543 bit is not set, convert the extraction to the cheaper of
7544 sign and zero extension, that are equivalent in these cases. */
7545 if (flag_expensive_optimizations
7546 && (HWI_COMPUTABLE_MODE_P (tmode
)
7547 && ((nonzero_bits (new_rtx
, tmode
)
7548 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7551 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7552 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7554 /* Prefer ZERO_EXTENSION, since it gives more information to
7556 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7557 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7562 /* Otherwise, sign- or zero-extend unless we already are in the
7565 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7569 /* Unless this is a COMPARE or we have a funny memory reference,
7570 don't do anything with zero-extending field extracts starting at
7571 the low-order bit since they are simple AND operations. */
7572 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7573 && ! in_compare
&& unsignedp
)
7576 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7577 if the position is not a constant and the length is not 1. In all
7578 other cases, we would only be going outside our object in cases when
7579 an original shift would have been undefined. */
7581 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7582 || (pos_rtx
!= 0 && len
!= 1)))
7585 enum extraction_pattern pattern
= (in_dest
? EP_insv
7586 : unsignedp
? EP_extzv
: EP_extv
);
7588 /* If INNER is not from memory, we want it to have the mode of a register
7589 extraction pattern's structure operand, or word_mode if there is no
7590 such pattern. The same applies to extraction_mode and pos_mode
7591 and their respective operands.
7593 For memory, assume that the desired extraction_mode and pos_mode
7594 are the same as for a register operation, since at present we don't
7595 have named patterns for aligned memory structures. */
7596 struct extraction_insn insn
;
7597 if (get_best_reg_extraction_insn (&insn
, pattern
,
7598 GET_MODE_BITSIZE (inner_mode
), mode
))
7600 wanted_inner_reg_mode
= insn
.struct_mode
;
7601 pos_mode
= insn
.pos_mode
;
7602 extraction_mode
= insn
.field_mode
;
7605 /* Never narrow an object, since that might not be safe. */
7607 if (mode
!= VOIDmode
7608 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7609 extraction_mode
= mode
;
7612 wanted_inner_mode
= wanted_inner_reg_mode
;
7615 /* Be careful not to go beyond the extracted object and maintain the
7616 natural alignment of the memory. */
7617 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7618 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7619 > GET_MODE_BITSIZE (wanted_inner_mode
))
7621 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7622 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7628 if (BITS_BIG_ENDIAN
)
7630 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7631 BITS_BIG_ENDIAN style. If position is constant, compute new
7632 position. Otherwise, build subtraction.
7633 Note that POS is relative to the mode of the original argument.
7634 If it's a MEM we need to recompute POS relative to that.
7635 However, if we're extracting from (or inserting into) a register,
7636 we want to recompute POS relative to wanted_inner_mode. */
7637 int width
= (MEM_P (inner
)
7638 ? GET_MODE_BITSIZE (is_mode
)
7639 : GET_MODE_BITSIZE (wanted_inner_mode
));
7642 pos
= width
- len
- pos
;
7645 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7646 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7648 /* POS may be less than 0 now, but we check for that below.
7649 Note that it can only be less than 0 if !MEM_P (inner). */
7652 /* If INNER has a wider mode, and this is a constant extraction, try to
7653 make it smaller and adjust the byte to point to the byte containing
7655 if (wanted_inner_mode
!= VOIDmode
7656 && inner_mode
!= wanted_inner_mode
7658 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7660 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7661 && ! MEM_VOLATILE_P (inner
))
7665 /* The computations below will be correct if the machine is big
7666 endian in both bits and bytes or little endian in bits and bytes.
7667 If it is mixed, we must adjust. */
7669 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7670 adjust OFFSET to compensate. */
7671 if (BYTES_BIG_ENDIAN
7672 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7673 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7675 /* We can now move to the desired byte. */
7676 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7677 * GET_MODE_SIZE (wanted_inner_mode
);
7678 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7680 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7681 && is_mode
!= wanted_inner_mode
)
7682 offset
= (GET_MODE_SIZE (is_mode
)
7683 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7685 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7688 /* If INNER is not memory, get it into the proper mode. If we are changing
7689 its mode, POS must be a constant and smaller than the size of the new
7691 else if (!MEM_P (inner
))
7693 /* On the LHS, don't create paradoxical subregs implicitely truncating
7694 the register unless TRULY_NOOP_TRUNCATION. */
7696 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7700 if (GET_MODE (inner
) != wanted_inner_mode
7702 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7708 inner
= force_to_mode (inner
, wanted_inner_mode
,
7710 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7712 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7717 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7718 have to zero extend. Otherwise, we can just use a SUBREG. */
7720 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7722 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7723 GET_MODE (pos_rtx
));
7725 /* If we know that no extraneous bits are set, and that the high
7726 bit is not set, convert extraction to cheaper one - either
7727 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7729 if (flag_expensive_optimizations
7730 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7731 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7732 & ~(((unsigned HOST_WIDE_INT
)
7733 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7737 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7738 GET_MODE (pos_rtx
));
7740 /* Prefer ZERO_EXTENSION, since it gives more information to
7742 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7743 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7749 /* Make POS_RTX unless we already have it and it is correct. If we don't
7750 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7752 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7753 pos_rtx
= orig_pos_rtx
;
7755 else if (pos_rtx
== 0)
7756 pos_rtx
= GEN_INT (pos
);
7758 /* Make the required operation. See if we can use existing rtx. */
7759 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7760 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7762 new_rtx
= gen_lowpart (mode
, new_rtx
);
7767 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7768 with any other operations in X. Return X without that shift if so. */
7771 extract_left_shift (rtx x
, int count
)
7773 enum rtx_code code
= GET_CODE (x
);
7774 machine_mode mode
= GET_MODE (x
);
7780 /* This is the shift itself. If it is wide enough, we will return
7781 either the value being shifted if the shift count is equal to
7782 COUNT or a shift for the difference. */
7783 if (CONST_INT_P (XEXP (x
, 1))
7784 && INTVAL (XEXP (x
, 1)) >= count
)
7785 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7786 INTVAL (XEXP (x
, 1)) - count
);
7790 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7791 return simplify_gen_unary (code
, mode
, tem
, mode
);
7795 case PLUS
: case IOR
: case XOR
: case AND
:
7796 /* If we can safely shift this constant and we find the inner shift,
7797 make a new operation. */
7798 if (CONST_INT_P (XEXP (x
, 1))
7799 && (UINTVAL (XEXP (x
, 1))
7800 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7801 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7803 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7804 return simplify_gen_binary (code
, mode
, tem
,
7805 gen_int_mode (val
, mode
));
7816 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7817 level of the expression and MODE is its mode. IN_CODE is as for
7818 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7819 that should be used when recursing on operands of *X_PTR.
7821 There are two possible actions:
7823 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7824 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7826 - Return a new rtx, which the caller returns directly. */
7829 make_compound_operation_int (machine_mode mode
, rtx
*x_ptr
,
7830 enum rtx_code in_code
,
7831 enum rtx_code
*next_code_ptr
)
7834 enum rtx_code next_code
= *next_code_ptr
;
7835 enum rtx_code code
= GET_CODE (x
);
7836 int mode_width
= GET_MODE_PRECISION (mode
);
7841 bool equality_comparison
= false;
7845 equality_comparison
= true;
7849 /* Process depending on the code of this operation. If NEW is set
7850 nonzero, it will be returned. */
7855 /* Convert shifts by constants into multiplications if inside
7857 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7858 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7859 && INTVAL (XEXP (x
, 1)) >= 0)
7861 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7862 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7864 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7865 if (GET_CODE (new_rtx
) == NEG
)
7867 new_rtx
= XEXP (new_rtx
, 0);
7870 multval
= trunc_int_for_mode (multval
, mode
);
7871 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7878 lhs
= make_compound_operation (lhs
, next_code
);
7879 rhs
= make_compound_operation (rhs
, next_code
);
7880 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
7882 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7884 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7886 else if (GET_CODE (lhs
) == MULT
7887 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7889 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7890 simplify_gen_unary (NEG
, mode
,
7893 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7897 SUBST (XEXP (x
, 0), lhs
);
7898 SUBST (XEXP (x
, 1), rhs
);
7900 maybe_swap_commutative_operands (x
);
7906 lhs
= make_compound_operation (lhs
, next_code
);
7907 rhs
= make_compound_operation (rhs
, next_code
);
7908 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
7910 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7912 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7914 else if (GET_CODE (rhs
) == MULT
7915 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7917 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7918 simplify_gen_unary (NEG
, mode
,
7921 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7925 SUBST (XEXP (x
, 0), lhs
);
7926 SUBST (XEXP (x
, 1), rhs
);
7931 /* If the second operand is not a constant, we can't do anything
7933 if (!CONST_INT_P (XEXP (x
, 1)))
7936 /* If the constant is a power of two minus one and the first operand
7937 is a logical right shift, make an extraction. */
7938 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7939 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7941 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7942 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7943 0, in_code
== COMPARE
);
7946 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7947 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7948 && subreg_lowpart_p (XEXP (x
, 0))
7949 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7950 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7952 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
7953 machine_mode inner_mode
= GET_MODE (inner_x0
);
7954 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
7955 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
7957 i
, 1, 0, in_code
== COMPARE
);
7961 /* If we narrowed the mode when dropping the subreg, then
7962 we must zero-extend to keep the semantics of the AND. */
7963 if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
7965 else if (SCALAR_INT_MODE_P (inner_mode
))
7966 new_rtx
= simplify_gen_unary (ZERO_EXTEND
, mode
,
7967 new_rtx
, inner_mode
);
7972 /* If that didn't give anything, see if the AND simplifies on
7974 if (!new_rtx
&& i
>= 0)
7976 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7977 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
7978 0, in_code
== COMPARE
);
7981 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7982 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7983 || GET_CODE (XEXP (x
, 0)) == IOR
)
7984 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7985 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7986 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7988 /* Apply the distributive law, and then try to make extractions. */
7989 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7990 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7992 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7994 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7997 /* If we are have (and (rotate X C) M) and C is larger than the number
7998 of bits in M, this is an extraction. */
8000 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8001 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8002 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8003 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8005 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8006 new_rtx
= make_extraction (mode
, new_rtx
,
8007 (GET_MODE_PRECISION (mode
)
8008 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8009 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8012 /* On machines without logical shifts, if the operand of the AND is
8013 a logical shift and our mask turns off all the propagated sign
8014 bits, we can replace the logical shift with an arithmetic shift. */
8015 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8016 && !have_insn_for (LSHIFTRT
, mode
)
8017 && have_insn_for (ASHIFTRT
, mode
)
8018 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8019 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8020 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8021 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8023 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8025 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8026 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8028 gen_rtx_ASHIFTRT (mode
,
8029 make_compound_operation
8030 (XEXP (XEXP (x
, 0), 0), next_code
),
8031 XEXP (XEXP (x
, 0), 1)));
8034 /* If the constant is one less than a power of two, this might be
8035 representable by an extraction even if no shift is present.
8036 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8037 we are in a COMPARE. */
8038 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8039 new_rtx
= make_extraction (mode
,
8040 make_compound_operation (XEXP (x
, 0),
8042 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8044 /* If we are in a comparison and this is an AND with a power of two,
8045 convert this into the appropriate bit extract. */
8046 else if (in_code
== COMPARE
8047 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8048 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8049 new_rtx
= make_extraction (mode
,
8050 make_compound_operation (XEXP (x
, 0),
8052 i
, NULL_RTX
, 1, 1, 0, 1);
8054 /* If the one operand is a paradoxical subreg of a register or memory and
8055 the constant (limited to the smaller mode) has only zero bits where
8056 the sub expression has known zero bits, this can be expressed as
8058 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8062 sub
= XEXP (XEXP (x
, 0), 0);
8063 machine_mode sub_mode
= GET_MODE (sub
);
8064 if ((REG_P (sub
) || MEM_P (sub
))
8065 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8067 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8068 unsigned HOST_WIDE_INT mask
;
8070 /* original AND constant with all the known zero bits set */
8071 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8072 if ((mask
& mode_mask
) == mode_mask
)
8074 new_rtx
= make_compound_operation (sub
, next_code
);
8075 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8076 GET_MODE_PRECISION (sub_mode
),
8077 1, 0, in_code
== COMPARE
);
8085 /* If the sign bit is known to be zero, replace this with an
8086 arithmetic shift. */
8087 if (have_insn_for (ASHIFTRT
, mode
)
8088 && ! have_insn_for (LSHIFTRT
, mode
)
8089 && mode_width
<= HOST_BITS_PER_WIDE_INT
8090 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8092 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8093 make_compound_operation (XEXP (x
, 0),
8105 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8106 this is a SIGN_EXTRACT. */
8107 if (CONST_INT_P (rhs
)
8108 && GET_CODE (lhs
) == ASHIFT
8109 && CONST_INT_P (XEXP (lhs
, 1))
8110 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8111 && INTVAL (XEXP (lhs
, 1)) >= 0
8112 && INTVAL (rhs
) < mode_width
)
8114 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8115 new_rtx
= make_extraction (mode
, new_rtx
,
8116 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8117 NULL_RTX
, mode_width
- INTVAL (rhs
),
8118 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8122 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8123 If so, try to merge the shifts into a SIGN_EXTEND. We could
8124 also do this for some cases of SIGN_EXTRACT, but it doesn't
8125 seem worth the effort; the case checked for occurs on Alpha. */
8128 && ! (GET_CODE (lhs
) == SUBREG
8129 && (OBJECT_P (SUBREG_REG (lhs
))))
8130 && CONST_INT_P (rhs
)
8131 && INTVAL (rhs
) >= 0
8132 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8133 && INTVAL (rhs
) < mode_width
8134 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8135 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8136 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8137 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8142 /* Call ourselves recursively on the inner expression. If we are
8143 narrowing the object and it has a different RTL code from
8144 what it originally did, do this SUBREG as a force_to_mode. */
8146 rtx inner
= SUBREG_REG (x
), simplified
;
8147 enum rtx_code subreg_code
= in_code
;
8149 /* If the SUBREG is masking of a logical right shift,
8150 make an extraction. */
8151 if (GET_CODE (inner
) == LSHIFTRT
8152 && CONST_INT_P (XEXP (inner
, 1))
8153 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8154 && (UINTVAL (XEXP (inner
, 1))
8155 < GET_MODE_PRECISION (GET_MODE (inner
)))
8156 && subreg_lowpart_p (x
))
8158 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8159 int width
= GET_MODE_PRECISION (GET_MODE (inner
))
8160 - INTVAL (XEXP (inner
, 1));
8161 if (width
> mode_width
)
8163 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8164 width
, 1, 0, in_code
== COMPARE
);
8168 /* If in_code is COMPARE, it isn't always safe to pass it through
8169 to the recursive make_compound_operation call. */
8170 if (subreg_code
== COMPARE
8171 && (!subreg_lowpart_p (x
)
8172 || GET_CODE (inner
) == SUBREG
8173 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8174 is (const_int 0), rather than
8175 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8176 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8177 for non-equality comparisons against 0 is not equivalent
8178 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8179 || (GET_CODE (inner
) == AND
8180 && CONST_INT_P (XEXP (inner
, 1))
8181 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8182 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8183 >= GET_MODE_BITSIZE (mode
) - 1)))
8186 tem
= make_compound_operation (inner
, subreg_code
);
8189 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8193 if (GET_CODE (tem
) != GET_CODE (inner
)
8194 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8195 && subreg_lowpart_p (x
))
8198 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8200 /* If we have something other than a SUBREG, we might have
8201 done an expansion, so rerun ourselves. */
8202 if (GET_CODE (newer
) != SUBREG
)
8203 newer
= make_compound_operation (newer
, in_code
);
8205 /* force_to_mode can expand compounds. If it just re-expanded the
8206 compound, use gen_lowpart to convert to the desired mode. */
8207 if (rtx_equal_p (newer
, x
)
8208 /* Likewise if it re-expanded the compound only partially.
8209 This happens for SUBREG of ZERO_EXTRACT if they extract
8210 the same number of bits. */
8211 || (GET_CODE (newer
) == SUBREG
8212 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8213 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8214 && GET_CODE (inner
) == AND
8215 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8216 return gen_lowpart (GET_MODE (x
), tem
);
8231 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8232 *next_code_ptr
= next_code
;
8236 /* Look at the expression rooted at X. Look for expressions
8237 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8238 Form these expressions.
8240 Return the new rtx, usually just X.
8242 Also, for machines like the VAX that don't have logical shift insns,
8243 try to convert logical to arithmetic shift operations in cases where
8244 they are equivalent. This undoes the canonicalizations to logical
8245 shifts done elsewhere.
8247 We try, as much as possible, to re-use rtl expressions to save memory.
8249 IN_CODE says what kind of expression we are processing. Normally, it is
8250 SET. In a memory address it is MEM. When processing the arguments of
8251 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8252 precisely it is an equality comparison against zero. */
8255 make_compound_operation (rtx x
, enum rtx_code in_code
)
8257 enum rtx_code code
= GET_CODE (x
);
8260 enum rtx_code next_code
;
8263 /* Select the code to be used in recursive calls. Once we are inside an
8264 address, we stay there. If we have a comparison, set to COMPARE,
8265 but once inside, go back to our default of SET. */
8267 next_code
= (code
== MEM
? MEM
8268 : ((code
== COMPARE
|| COMPARISON_P (x
))
8269 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8270 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8272 if (SCALAR_INT_MODE_P (GET_MODE (x
)))
8274 rtx new_rtx
= make_compound_operation_int (GET_MODE (x
), &x
,
8275 in_code
, &next_code
);
8278 code
= GET_CODE (x
);
8281 /* Now recursively process each operand of this operation. We need to
8282 handle ZERO_EXTEND specially so that we don't lose track of the
8284 if (code
== ZERO_EXTEND
)
8286 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8287 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8288 new_rtx
, GET_MODE (XEXP (x
, 0)));
8291 SUBST (XEXP (x
, 0), new_rtx
);
8295 fmt
= GET_RTX_FORMAT (code
);
8296 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8299 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8300 SUBST (XEXP (x
, i
), new_rtx
);
8302 else if (fmt
[i
] == 'E')
8303 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8305 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8306 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8309 maybe_swap_commutative_operands (x
);
8313 /* Given M see if it is a value that would select a field of bits
8314 within an item, but not the entire word. Return -1 if not.
8315 Otherwise, return the starting position of the field, where 0 is the
8318 *PLEN is set to the length of the field. */
8321 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8323 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8324 int pos
= m
? ctz_hwi (m
) : -1;
8328 /* Now shift off the low-order zero bits and see if we have a
8329 power of two minus 1. */
8330 len
= exact_log2 ((m
>> pos
) + 1);
8339 /* If X refers to a register that equals REG in value, replace these
8340 references with REG. */
8342 canon_reg_for_combine (rtx x
, rtx reg
)
8349 enum rtx_code code
= GET_CODE (x
);
8350 switch (GET_RTX_CLASS (code
))
8353 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8354 if (op0
!= XEXP (x
, 0))
8355 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8360 case RTX_COMM_ARITH
:
8361 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8362 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8363 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8364 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8368 case RTX_COMM_COMPARE
:
8369 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8370 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8371 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8372 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8373 GET_MODE (op0
), op0
, op1
);
8377 case RTX_BITFIELD_OPS
:
8378 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8379 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8380 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8381 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8382 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8383 GET_MODE (op0
), op0
, op1
, op2
);
8389 if (rtx_equal_p (get_last_value (reg
), x
)
8390 || rtx_equal_p (reg
, get_last_value (x
)))
8399 fmt
= GET_RTX_FORMAT (code
);
8401 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8404 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8405 if (op
!= XEXP (x
, i
))
8415 else if (fmt
[i
] == 'E')
8418 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8420 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8421 if (op
!= XVECEXP (x
, i
, j
))
8428 XVECEXP (x
, i
, j
) = op
;
8439 /* Return X converted to MODE. If the value is already truncated to
8440 MODE we can just return a subreg even though in the general case we
8441 would need an explicit truncation. */
8444 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8446 if (!CONST_INT_P (x
)
8447 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8448 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8449 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8451 /* Bit-cast X into an integer mode. */
8452 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8453 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8454 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8458 return gen_lowpart (mode
, x
);
8461 /* See if X can be simplified knowing that we will only refer to it in
8462 MODE and will only refer to those bits that are nonzero in MASK.
8463 If other bits are being computed or if masking operations are done
8464 that select a superset of the bits in MASK, they can sometimes be
8467 Return a possibly simplified expression, but always convert X to
8468 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8470 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8471 are all off in X. This is used when X will be complemented, by either
8472 NOT, NEG, or XOR. */
8475 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8478 enum rtx_code code
= GET_CODE (x
);
8479 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8480 machine_mode op_mode
;
8481 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8484 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8485 code below will do the wrong thing since the mode of such an
8486 expression is VOIDmode.
8488 Also do nothing if X is a CLOBBER; this can happen if X was
8489 the return value from a call to gen_lowpart. */
8490 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8493 /* We want to perform the operation in its present mode unless we know
8494 that the operation is valid in MODE, in which case we do the operation
8496 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8497 && have_insn_for (code
, mode
))
8498 ? mode
: GET_MODE (x
));
8500 /* It is not valid to do a right-shift in a narrower mode
8501 than the one it came in with. */
8502 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8503 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8504 op_mode
= GET_MODE (x
);
8506 /* Truncate MASK to fit OP_MODE. */
8508 mask
&= GET_MODE_MASK (op_mode
);
8510 /* When we have an arithmetic operation, or a shift whose count we
8511 do not know, we need to assume that all bits up to the highest-order
8512 bit in MASK will be needed. This is how we form such a mask. */
8513 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8514 fuller_mask
= HOST_WIDE_INT_M1U
;
8516 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8519 /* Determine what bits of X are guaranteed to be (non)zero. */
8520 nonzero
= nonzero_bits (x
, mode
);
8522 /* If none of the bits in X are needed, return a zero. */
8523 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8526 /* If X is a CONST_INT, return a new one. Do this here since the
8527 test below will fail. */
8528 if (CONST_INT_P (x
))
8530 if (SCALAR_INT_MODE_P (mode
))
8531 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8534 x
= GEN_INT (INTVAL (x
) & mask
);
8535 return gen_lowpart_common (mode
, x
);
8539 /* If X is narrower than MODE and we want all the bits in X's mode, just
8540 get X in the proper mode. */
8541 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8542 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8543 return gen_lowpart (mode
, x
);
8545 /* We can ignore the effect of a SUBREG if it narrows the mode or
8546 if the constant masks to zero all the bits the mode doesn't have. */
8547 if (GET_CODE (x
) == SUBREG
8548 && subreg_lowpart_p (x
)
8549 && ((GET_MODE_SIZE (GET_MODE (x
))
8550 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8552 & GET_MODE_MASK (GET_MODE (x
))
8553 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8554 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8556 /* The arithmetic simplifications here only work for scalar integer modes. */
8557 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8558 return gen_lowpart_or_truncate (mode
, x
);
8563 /* If X is a (clobber (const_int)), return it since we know we are
8564 generating something that won't match. */
8571 x
= expand_compound_operation (x
);
8572 if (GET_CODE (x
) != code
)
8573 return force_to_mode (x
, mode
, mask
, next_select
);
8577 /* Similarly for a truncate. */
8578 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8581 /* If this is an AND with a constant, convert it into an AND
8582 whose constant is the AND of that constant with MASK. If it
8583 remains an AND of MASK, delete it since it is redundant. */
8585 if (CONST_INT_P (XEXP (x
, 1)))
8587 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8588 mask
& INTVAL (XEXP (x
, 1)));
8590 /* If X is still an AND, see if it is an AND with a mask that
8591 is just some low-order bits. If so, and it is MASK, we don't
8594 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8595 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8599 /* If it remains an AND, try making another AND with the bits
8600 in the mode mask that aren't in MASK turned on. If the
8601 constant in the AND is wide enough, this might make a
8602 cheaper constant. */
8604 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8605 && GET_MODE_MASK (GET_MODE (x
)) != mask
8606 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8608 unsigned HOST_WIDE_INT cval
8609 = UINTVAL (XEXP (x
, 1))
8610 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8613 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8614 gen_int_mode (cval
, GET_MODE (x
)));
8615 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8616 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8626 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8627 low-order bits (as in an alignment operation) and FOO is already
8628 aligned to that boundary, mask C1 to that boundary as well.
8629 This may eliminate that PLUS and, later, the AND. */
8632 unsigned int width
= GET_MODE_PRECISION (mode
);
8633 unsigned HOST_WIDE_INT smask
= mask
;
8635 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8636 number, sign extend it. */
8638 if (width
< HOST_BITS_PER_WIDE_INT
8639 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8640 smask
|= HOST_WIDE_INT_M1U
<< width
;
8642 if (CONST_INT_P (XEXP (x
, 1))
8643 && pow2p_hwi (- smask
)
8644 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8645 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8646 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8647 (INTVAL (XEXP (x
, 1)) & smask
)),
8648 mode
, smask
, next_select
);
8654 /* Substituting into the operands of a widening MULT is not likely to
8655 create RTL matching a machine insn. */
8657 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8658 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8659 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8660 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8661 && REG_P (XEXP (XEXP (x
, 0), 0))
8662 && REG_P (XEXP (XEXP (x
, 1), 0)))
8663 return gen_lowpart_or_truncate (mode
, x
);
8665 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8666 most significant bit in MASK since carries from those bits will
8667 affect the bits we are interested in. */
8672 /* If X is (minus C Y) where C's least set bit is larger than any bit
8673 in the mask, then we may replace with (neg Y). */
8674 if (CONST_INT_P (XEXP (x
, 0))
8675 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8677 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8679 return force_to_mode (x
, mode
, mask
, next_select
);
8682 /* Similarly, if C contains every bit in the fuller_mask, then we may
8683 replace with (not Y). */
8684 if (CONST_INT_P (XEXP (x
, 0))
8685 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8687 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8688 XEXP (x
, 1), GET_MODE (x
));
8689 return force_to_mode (x
, mode
, mask
, next_select
);
8697 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8698 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8699 operation which may be a bitfield extraction. Ensure that the
8700 constant we form is not wider than the mode of X. */
8702 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8703 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8704 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8705 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8706 && CONST_INT_P (XEXP (x
, 1))
8707 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8708 + floor_log2 (INTVAL (XEXP (x
, 1))))
8709 < GET_MODE_PRECISION (GET_MODE (x
)))
8710 && (UINTVAL (XEXP (x
, 1))
8711 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8713 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8714 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8716 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8717 XEXP (XEXP (x
, 0), 0), temp
);
8718 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8719 XEXP (XEXP (x
, 0), 1));
8720 return force_to_mode (x
, mode
, mask
, next_select
);
8724 /* For most binary operations, just propagate into the operation and
8725 change the mode if we have an operation of that mode. */
8727 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8728 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8730 /* If we ended up truncating both operands, truncate the result of the
8731 operation instead. */
8732 if (GET_CODE (op0
) == TRUNCATE
8733 && GET_CODE (op1
) == TRUNCATE
)
8735 op0
= XEXP (op0
, 0);
8736 op1
= XEXP (op1
, 0);
8739 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8740 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8742 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8743 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8747 /* For left shifts, do the same, but just for the first operand.
8748 However, we cannot do anything with shifts where we cannot
8749 guarantee that the counts are smaller than the size of the mode
8750 because such a count will have a different meaning in a
8753 if (! (CONST_INT_P (XEXP (x
, 1))
8754 && INTVAL (XEXP (x
, 1)) >= 0
8755 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8756 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8757 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8758 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8761 /* If the shift count is a constant and we can do arithmetic in
8762 the mode of the shift, refine which bits we need. Otherwise, use the
8763 conservative form of the mask. */
8764 if (CONST_INT_P (XEXP (x
, 1))
8765 && INTVAL (XEXP (x
, 1)) >= 0
8766 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8767 && HWI_COMPUTABLE_MODE_P (op_mode
))
8768 mask
>>= INTVAL (XEXP (x
, 1));
8772 op0
= gen_lowpart_or_truncate (op_mode
,
8773 force_to_mode (XEXP (x
, 0), op_mode
,
8774 mask
, next_select
));
8776 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8777 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8781 /* Here we can only do something if the shift count is a constant,
8782 this shift constant is valid for the host, and we can do arithmetic
8785 if (CONST_INT_P (XEXP (x
, 1))
8786 && INTVAL (XEXP (x
, 1)) >= 0
8787 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8788 && HWI_COMPUTABLE_MODE_P (op_mode
))
8790 rtx inner
= XEXP (x
, 0);
8791 unsigned HOST_WIDE_INT inner_mask
;
8793 /* Select the mask of the bits we need for the shift operand. */
8794 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8796 /* We can only change the mode of the shift if we can do arithmetic
8797 in the mode of the shift and INNER_MASK is no wider than the
8798 width of X's mode. */
8799 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8800 op_mode
= GET_MODE (x
);
8802 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8804 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8805 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8808 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8809 shift and AND produces only copies of the sign bit (C2 is one less
8810 than a power of two), we can do this with just a shift. */
8812 if (GET_CODE (x
) == LSHIFTRT
8813 && CONST_INT_P (XEXP (x
, 1))
8814 /* The shift puts one of the sign bit copies in the least significant
8816 && ((INTVAL (XEXP (x
, 1))
8817 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8818 >= GET_MODE_PRECISION (GET_MODE (x
)))
8819 && pow2p_hwi (mask
+ 1)
8820 /* Number of bits left after the shift must be more than the mask
8822 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8823 <= GET_MODE_PRECISION (GET_MODE (x
)))
8824 /* Must be more sign bit copies than the mask needs. */
8825 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8826 >= exact_log2 (mask
+ 1)))
8827 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8828 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8829 - exact_log2 (mask
+ 1)));
8834 /* If we are just looking for the sign bit, we don't need this shift at
8835 all, even if it has a variable count. */
8836 if (val_signbit_p (GET_MODE (x
), mask
))
8837 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8839 /* If this is a shift by a constant, get a mask that contains those bits
8840 that are not copies of the sign bit. We then have two cases: If
8841 MASK only includes those bits, this can be a logical shift, which may
8842 allow simplifications. If MASK is a single-bit field not within
8843 those bits, we are requesting a copy of the sign bit and hence can
8844 shift the sign bit to the appropriate location. */
8846 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8847 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8851 /* If the considered data is wider than HOST_WIDE_INT, we can't
8852 represent a mask for all its bits in a single scalar.
8853 But we only care about the lower bits, so calculate these. */
8855 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8857 nonzero
= HOST_WIDE_INT_M1U
;
8859 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8860 is the number of bits a full-width mask would have set.
8861 We need only shift if these are fewer than nonzero can
8862 hold. If not, we must keep all bits set in nonzero. */
8864 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8865 < HOST_BITS_PER_WIDE_INT
)
8866 nonzero
>>= INTVAL (XEXP (x
, 1))
8867 + HOST_BITS_PER_WIDE_INT
8868 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8872 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8873 nonzero
>>= INTVAL (XEXP (x
, 1));
8876 if ((mask
& ~nonzero
) == 0)
8878 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8879 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8880 if (GET_CODE (x
) != ASHIFTRT
)
8881 return force_to_mode (x
, mode
, mask
, next_select
);
8884 else if ((i
= exact_log2 (mask
)) >= 0)
8886 x
= simplify_shift_const
8887 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8888 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8890 if (GET_CODE (x
) != ASHIFTRT
)
8891 return force_to_mode (x
, mode
, mask
, next_select
);
8895 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8896 even if the shift count isn't a constant. */
8898 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8899 XEXP (x
, 0), XEXP (x
, 1));
8903 /* If this is a zero- or sign-extension operation that just affects bits
8904 we don't care about, remove it. Be sure the call above returned
8905 something that is still a shift. */
8907 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8908 && CONST_INT_P (XEXP (x
, 1))
8909 && INTVAL (XEXP (x
, 1)) >= 0
8910 && (INTVAL (XEXP (x
, 1))
8911 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8912 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8913 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8914 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8921 /* If the shift count is constant and we can do computations
8922 in the mode of X, compute where the bits we care about are.
8923 Otherwise, we can't do anything. Don't change the mode of
8924 the shift or propagate MODE into the shift, though. */
8925 if (CONST_INT_P (XEXP (x
, 1))
8926 && INTVAL (XEXP (x
, 1)) >= 0)
8928 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8930 gen_int_mode (mask
, GET_MODE (x
)),
8932 if (temp
&& CONST_INT_P (temp
))
8933 x
= simplify_gen_binary (code
, GET_MODE (x
),
8934 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8935 INTVAL (temp
), next_select
),
8941 /* If we just want the low-order bit, the NEG isn't needed since it
8942 won't change the low-order bit. */
8944 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8946 /* We need any bits less significant than the most significant bit in
8947 MASK since carries from those bits will affect the bits we are
8953 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8954 same as the XOR case above. Ensure that the constant we form is not
8955 wider than the mode of X. */
8957 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8958 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8959 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8960 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8961 < GET_MODE_PRECISION (GET_MODE (x
)))
8962 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8964 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8966 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8967 XEXP (XEXP (x
, 0), 0), temp
);
8968 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8969 temp
, XEXP (XEXP (x
, 0), 1));
8971 return force_to_mode (x
, mode
, mask
, next_select
);
8974 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8975 use the full mask inside the NOT. */
8979 op0
= gen_lowpart_or_truncate (op_mode
,
8980 force_to_mode (XEXP (x
, 0), mode
, mask
,
8982 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8983 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8987 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8988 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8989 which is equal to STORE_FLAG_VALUE. */
8990 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8991 && XEXP (x
, 1) == const0_rtx
8992 && GET_MODE (XEXP (x
, 0)) == mode
8993 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
8994 && (nonzero_bits (XEXP (x
, 0), mode
)
8995 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8996 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9001 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9002 written in a narrower mode. We play it safe and do not do so. */
9004 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
9005 force_to_mode (XEXP (x
, 1), mode
,
9006 mask
, next_select
));
9007 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
9008 force_to_mode (XEXP (x
, 2), mode
,
9009 mask
, next_select
));
9010 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9011 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
9012 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9020 /* Ensure we return a value of the proper mode. */
9021 return gen_lowpart_or_truncate (mode
, x
);
9024 /* Return nonzero if X is an expression that has one of two values depending on
9025 whether some other value is zero or nonzero. In that case, we return the
9026 value that is being tested, *PTRUE is set to the value if the rtx being
9027 returned has a nonzero value, and *PFALSE is set to the other alternative.
9029 If we return zero, we set *PTRUE and *PFALSE to X. */
9032 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9034 machine_mode mode
= GET_MODE (x
);
9035 enum rtx_code code
= GET_CODE (x
);
9036 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9037 unsigned HOST_WIDE_INT nz
;
9039 /* If we are comparing a value against zero, we are done. */
9040 if ((code
== NE
|| code
== EQ
)
9041 && XEXP (x
, 1) == const0_rtx
)
9043 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9044 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9048 /* If this is a unary operation whose operand has one of two values, apply
9049 our opcode to compute those values. */
9050 else if (UNARY_P (x
)
9051 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9053 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9054 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9055 GET_MODE (XEXP (x
, 0)));
9059 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9060 make can't possibly match and would suppress other optimizations. */
9061 else if (code
== COMPARE
)
9064 /* If this is a binary operation, see if either side has only one of two
9065 values. If either one does or if both do and they are conditional on
9066 the same value, compute the new true and false values. */
9067 else if (BINARY_P (x
))
9069 rtx op0
= XEXP (x
, 0);
9070 rtx op1
= XEXP (x
, 1);
9071 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9072 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9074 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9075 && (REG_P (op0
) || REG_P (op1
)))
9077 /* Try to enable a simplification by undoing work done by
9078 if_then_else_cond if it converted a REG into something more
9083 true0
= false0
= op0
;
9088 true1
= false1
= op1
;
9092 if ((cond0
!= 0 || cond1
!= 0)
9093 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9095 /* If if_then_else_cond returned zero, then true/false are the
9096 same rtl. We must copy one of them to prevent invalid rtl
9099 true0
= copy_rtx (true0
);
9100 else if (cond1
== 0)
9101 true1
= copy_rtx (true1
);
9103 if (COMPARISON_P (x
))
9105 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9107 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9112 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9113 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9116 return cond0
? cond0
: cond1
;
9119 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9120 operands is zero when the other is nonzero, and vice-versa,
9121 and STORE_FLAG_VALUE is 1 or -1. */
9123 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9124 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9126 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9128 rtx op0
= XEXP (XEXP (x
, 0), 1);
9129 rtx op1
= XEXP (XEXP (x
, 1), 1);
9131 cond0
= XEXP (XEXP (x
, 0), 0);
9132 cond1
= XEXP (XEXP (x
, 1), 0);
9134 if (COMPARISON_P (cond0
)
9135 && COMPARISON_P (cond1
)
9136 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9137 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9138 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9139 || ((swap_condition (GET_CODE (cond0
))
9140 == reversed_comparison_code (cond1
, NULL
))
9141 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9142 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9143 && ! side_effects_p (x
))
9145 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9146 *pfalse
= simplify_gen_binary (MULT
, mode
,
9148 ? simplify_gen_unary (NEG
, mode
,
9156 /* Similarly for MULT, AND and UMIN, except that for these the result
9158 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9159 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9160 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9162 cond0
= XEXP (XEXP (x
, 0), 0);
9163 cond1
= XEXP (XEXP (x
, 1), 0);
9165 if (COMPARISON_P (cond0
)
9166 && COMPARISON_P (cond1
)
9167 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9168 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9169 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9170 || ((swap_condition (GET_CODE (cond0
))
9171 == reversed_comparison_code (cond1
, NULL
))
9172 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9173 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9174 && ! side_effects_p (x
))
9176 *ptrue
= *pfalse
= const0_rtx
;
9182 else if (code
== IF_THEN_ELSE
)
9184 /* If we have IF_THEN_ELSE already, extract the condition and
9185 canonicalize it if it is NE or EQ. */
9186 cond0
= XEXP (x
, 0);
9187 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9188 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9189 return XEXP (cond0
, 0);
9190 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9192 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9193 return XEXP (cond0
, 0);
9199 /* If X is a SUBREG, we can narrow both the true and false values
9200 if the inner expression, if there is a condition. */
9201 else if (code
== SUBREG
9202 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9205 true0
= simplify_gen_subreg (mode
, true0
,
9206 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9207 false0
= simplify_gen_subreg (mode
, false0
,
9208 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9209 if (true0
&& false0
)
9217 /* If X is a constant, this isn't special and will cause confusions
9218 if we treat it as such. Likewise if it is equivalent to a constant. */
9219 else if (CONSTANT_P (x
)
9220 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9223 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9224 will be least confusing to the rest of the compiler. */
9225 else if (mode
== BImode
)
9227 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9231 /* If X is known to be either 0 or -1, those are the true and
9232 false values when testing X. */
9233 else if (x
== constm1_rtx
|| x
== const0_rtx
9234 || (mode
!= VOIDmode
&& mode
!= BLKmode
9235 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9237 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9241 /* Likewise for 0 or a single bit. */
9242 else if (HWI_COMPUTABLE_MODE_P (mode
)
9243 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9245 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9249 /* Otherwise fail; show no condition with true and false values the same. */
9250 *ptrue
= *pfalse
= x
;
9254 /* Return the value of expression X given the fact that condition COND
9255 is known to be true when applied to REG as its first operand and VAL
9256 as its second. X is known to not be shared and so can be modified in
9259 We only handle the simplest cases, and specifically those cases that
9260 arise with IF_THEN_ELSE expressions. */
9263 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9265 enum rtx_code code
= GET_CODE (x
);
9269 if (side_effects_p (x
))
9272 /* If either operand of the condition is a floating point value,
9273 then we have to avoid collapsing an EQ comparison. */
9275 && rtx_equal_p (x
, reg
)
9276 && ! FLOAT_MODE_P (GET_MODE (x
))
9277 && ! FLOAT_MODE_P (GET_MODE (val
)))
9280 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9283 /* If X is (abs REG) and we know something about REG's relationship
9284 with zero, we may be able to simplify this. */
9286 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9289 case GE
: case GT
: case EQ
:
9292 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9294 GET_MODE (XEXP (x
, 0)));
9299 /* The only other cases we handle are MIN, MAX, and comparisons if the
9300 operands are the same as REG and VAL. */
9302 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9304 if (rtx_equal_p (XEXP (x
, 0), val
))
9306 std::swap (val
, reg
);
9307 cond
= swap_condition (cond
);
9310 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9312 if (COMPARISON_P (x
))
9314 if (comparison_dominates_p (cond
, code
))
9315 return const_true_rtx
;
9317 code
= reversed_comparison_code (x
, NULL
);
9319 && comparison_dominates_p (cond
, code
))
9324 else if (code
== SMAX
|| code
== SMIN
9325 || code
== UMIN
|| code
== UMAX
)
9327 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9329 /* Do not reverse the condition when it is NE or EQ.
9330 This is because we cannot conclude anything about
9331 the value of 'SMAX (x, y)' when x is not equal to y,
9332 but we can when x equals y. */
9333 if ((code
== SMAX
|| code
== UMAX
)
9334 && ! (cond
== EQ
|| cond
== NE
))
9335 cond
= reverse_condition (cond
);
9340 return unsignedp
? x
: XEXP (x
, 1);
9342 return unsignedp
? x
: XEXP (x
, 0);
9344 return unsignedp
? XEXP (x
, 1) : x
;
9346 return unsignedp
? XEXP (x
, 0) : x
;
9353 else if (code
== SUBREG
)
9355 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9356 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9358 if (SUBREG_REG (x
) != r
)
9360 /* We must simplify subreg here, before we lose track of the
9361 original inner_mode. */
9362 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9363 inner_mode
, SUBREG_BYTE (x
));
9367 SUBST (SUBREG_REG (x
), r
);
9372 /* We don't have to handle SIGN_EXTEND here, because even in the
9373 case of replacing something with a modeless CONST_INT, a
9374 CONST_INT is already (supposed to be) a valid sign extension for
9375 its narrower mode, which implies it's already properly
9376 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9377 story is different. */
9378 else if (code
== ZERO_EXTEND
)
9380 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9381 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9383 if (XEXP (x
, 0) != r
)
9385 /* We must simplify the zero_extend here, before we lose
9386 track of the original inner_mode. */
9387 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9392 SUBST (XEXP (x
, 0), r
);
9398 fmt
= GET_RTX_FORMAT (code
);
9399 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9402 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9403 else if (fmt
[i
] == 'E')
9404 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9405 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9412 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9413 assignment as a field assignment. */
9416 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9418 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9420 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9422 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9424 /* For big endian, adjust the memory offset. */
9425 if (BYTES_BIG_ENDIAN
)
9426 x
= adjust_address_nv (x
, GET_MODE (y
),
9427 -subreg_lowpart_offset (GET_MODE (x
),
9430 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9433 if (x
== y
|| rtx_equal_p (x
, y
))
9436 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9439 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9440 Note that all SUBREGs of MEM are paradoxical; otherwise they
9441 would have been rewritten. */
9442 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9443 && MEM_P (SUBREG_REG (y
))
9444 && rtx_equal_p (SUBREG_REG (y
),
9445 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9448 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9449 && MEM_P (SUBREG_REG (x
))
9450 && rtx_equal_p (SUBREG_REG (x
),
9451 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9454 /* We used to see if get_last_value of X and Y were the same but that's
9455 not correct. In one direction, we'll cause the assignment to have
9456 the wrong destination and in the case, we'll import a register into this
9457 insn that might have already have been dead. So fail if none of the
9458 above cases are true. */
9462 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9463 Return that assignment if so.
9465 We only handle the most common cases. */
9468 make_field_assignment (rtx x
)
9470 rtx dest
= SET_DEST (x
);
9471 rtx src
= SET_SRC (x
);
9476 unsigned HOST_WIDE_INT len
;
9480 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9481 a clear of a one-bit field. We will have changed it to
9482 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9485 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9486 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9487 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9488 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9490 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9493 return gen_rtx_SET (assign
, const0_rtx
);
9497 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9498 && subreg_lowpart_p (XEXP (src
, 0))
9499 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9500 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9501 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9502 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9503 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9504 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9506 assign
= make_extraction (VOIDmode
, dest
, 0,
9507 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9510 return gen_rtx_SET (assign
, const0_rtx
);
9514 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9516 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9517 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9518 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9520 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9523 return gen_rtx_SET (assign
, const1_rtx
);
9527 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9528 SRC is an AND with all bits of that field set, then we can discard
9530 if (GET_CODE (dest
) == ZERO_EXTRACT
9531 && CONST_INT_P (XEXP (dest
, 1))
9532 && GET_CODE (src
) == AND
9533 && CONST_INT_P (XEXP (src
, 1)))
9535 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9536 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9537 unsigned HOST_WIDE_INT ze_mask
;
9539 if (width
>= HOST_BITS_PER_WIDE_INT
)
9542 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9544 /* Complete overlap. We can remove the source AND. */
9545 if ((and_mask
& ze_mask
) == ze_mask
)
9546 return gen_rtx_SET (dest
, XEXP (src
, 0));
9548 /* Partial overlap. We can reduce the source AND. */
9549 if ((and_mask
& ze_mask
) != and_mask
)
9551 mode
= GET_MODE (src
);
9552 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9553 gen_int_mode (and_mask
& ze_mask
, mode
));
9554 return gen_rtx_SET (dest
, src
);
9558 /* The other case we handle is assignments into a constant-position
9559 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9560 a mask that has all one bits except for a group of zero bits and
9561 OTHER is known to have zeros where C1 has ones, this is such an
9562 assignment. Compute the position and length from C1. Shift OTHER
9563 to the appropriate position, force it to the required mode, and
9564 make the extraction. Check for the AND in both operands. */
9566 /* One or more SUBREGs might obscure the constant-position field
9567 assignment. The first one we are likely to encounter is an outer
9568 narrowing SUBREG, which we can just strip for the purposes of
9569 identifying the constant-field assignment. */
9570 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9571 src
= SUBREG_REG (src
);
9573 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9576 rhs
= expand_compound_operation (XEXP (src
, 0));
9577 lhs
= expand_compound_operation (XEXP (src
, 1));
9579 if (GET_CODE (rhs
) == AND
9580 && CONST_INT_P (XEXP (rhs
, 1))
9581 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9582 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9583 /* The second SUBREG that might get in the way is a paradoxical
9584 SUBREG around the first operand of the AND. We want to
9585 pretend the operand is as wide as the destination here. We
9586 do this by adjusting the MEM to wider mode for the sole
9587 purpose of the call to rtx_equal_for_field_assignment_p. Also
9588 note this trick only works for MEMs. */
9589 else if (GET_CODE (rhs
) == AND
9590 && paradoxical_subreg_p (XEXP (rhs
, 0))
9591 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9592 && CONST_INT_P (XEXP (rhs
, 1))
9593 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9595 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9596 else if (GET_CODE (lhs
) == AND
9597 && CONST_INT_P (XEXP (lhs
, 1))
9598 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9599 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9600 /* The second SUBREG that might get in the way is a paradoxical
9601 SUBREG around the first operand of the AND. We want to
9602 pretend the operand is as wide as the destination here. We
9603 do this by adjusting the MEM to wider mode for the sole
9604 purpose of the call to rtx_equal_for_field_assignment_p. Also
9605 note this trick only works for MEMs. */
9606 else if (GET_CODE (lhs
) == AND
9607 && paradoxical_subreg_p (XEXP (lhs
, 0))
9608 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9609 && CONST_INT_P (XEXP (lhs
, 1))
9610 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9612 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9616 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9617 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9618 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9619 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9622 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9626 /* The mode to use for the source is the mode of the assignment, or of
9627 what is inside a possible STRICT_LOW_PART. */
9628 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9629 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9631 /* Shift OTHER right POS places and make it the source, restricting it
9632 to the proper length and mode. */
9634 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9638 src
= force_to_mode (src
, mode
,
9639 len
>= HOST_BITS_PER_WIDE_INT
9641 : (HOST_WIDE_INT_1U
<< len
) - 1,
9644 /* If SRC is masked by an AND that does not make a difference in
9645 the value being stored, strip it. */
9646 if (GET_CODE (assign
) == ZERO_EXTRACT
9647 && CONST_INT_P (XEXP (assign
, 1))
9648 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9649 && GET_CODE (src
) == AND
9650 && CONST_INT_P (XEXP (src
, 1))
9651 && UINTVAL (XEXP (src
, 1))
9652 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9653 src
= XEXP (src
, 0);
9655 return gen_rtx_SET (assign
, src
);
9658 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9662 apply_distributive_law (rtx x
)
9664 enum rtx_code code
= GET_CODE (x
);
9665 enum rtx_code inner_code
;
9666 rtx lhs
, rhs
, other
;
9669 /* Distributivity is not true for floating point as it can change the
9670 value. So we don't do it unless -funsafe-math-optimizations. */
9671 if (FLOAT_MODE_P (GET_MODE (x
))
9672 && ! flag_unsafe_math_optimizations
)
9675 /* The outer operation can only be one of the following: */
9676 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9677 && code
!= PLUS
&& code
!= MINUS
)
9683 /* If either operand is a primitive we can't do anything, so get out
9685 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9688 lhs
= expand_compound_operation (lhs
);
9689 rhs
= expand_compound_operation (rhs
);
9690 inner_code
= GET_CODE (lhs
);
9691 if (inner_code
!= GET_CODE (rhs
))
9694 /* See if the inner and outer operations distribute. */
9701 /* These all distribute except over PLUS. */
9702 if (code
== PLUS
|| code
== MINUS
)
9707 if (code
!= PLUS
&& code
!= MINUS
)
9712 /* This is also a multiply, so it distributes over everything. */
9715 /* This used to handle SUBREG, but this turned out to be counter-
9716 productive, since (subreg (op ...)) usually is not handled by
9717 insn patterns, and this "optimization" therefore transformed
9718 recognizable patterns into unrecognizable ones. Therefore the
9719 SUBREG case was removed from here.
9721 It is possible that distributing SUBREG over arithmetic operations
9722 leads to an intermediate result than can then be optimized further,
9723 e.g. by moving the outer SUBREG to the other side of a SET as done
9724 in simplify_set. This seems to have been the original intent of
9725 handling SUBREGs here.
9727 However, with current GCC this does not appear to actually happen,
9728 at least on major platforms. If some case is found where removing
9729 the SUBREG case here prevents follow-on optimizations, distributing
9730 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9736 /* Set LHS and RHS to the inner operands (A and B in the example
9737 above) and set OTHER to the common operand (C in the example).
9738 There is only one way to do this unless the inner operation is
9740 if (COMMUTATIVE_ARITH_P (lhs
)
9741 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9742 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9743 else if (COMMUTATIVE_ARITH_P (lhs
)
9744 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9745 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9746 else if (COMMUTATIVE_ARITH_P (lhs
)
9747 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9748 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9749 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9750 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9754 /* Form the new inner operation, seeing if it simplifies first. */
9755 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9757 /* There is one exception to the general way of distributing:
9758 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9759 if (code
== XOR
&& inner_code
== IOR
)
9762 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9765 /* We may be able to continuing distributing the result, so call
9766 ourselves recursively on the inner operation before forming the
9767 outer operation, which we return. */
9768 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9769 apply_distributive_law (tem
), other
);
9772 /* See if X is of the form (* (+ A B) C), and if so convert to
9773 (+ (* A C) (* B C)) and try to simplify.
9775 Most of the time, this results in no change. However, if some of
9776 the operands are the same or inverses of each other, simplifications
9779 For example, (and (ior A B) (not B)) can occur as the result of
9780 expanding a bit field assignment. When we apply the distributive
9781 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9782 which then simplifies to (and (A (not B))).
9784 Note that no checks happen on the validity of applying the inverse
9785 distributive law. This is pointless since we can do it in the
9786 few places where this routine is called.
9788 N is the index of the term that is decomposed (the arithmetic operation,
9789 i.e. (+ A B) in the first example above). !N is the index of the term that
9790 is distributed, i.e. of C in the first example above. */
9792 distribute_and_simplify_rtx (rtx x
, int n
)
9795 enum rtx_code outer_code
, inner_code
;
9796 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9798 /* Distributivity is not true for floating point as it can change the
9799 value. So we don't do it unless -funsafe-math-optimizations. */
9800 if (FLOAT_MODE_P (GET_MODE (x
))
9801 && ! flag_unsafe_math_optimizations
)
9804 decomposed
= XEXP (x
, n
);
9805 if (!ARITHMETIC_P (decomposed
))
9808 mode
= GET_MODE (x
);
9809 outer_code
= GET_CODE (x
);
9810 distributed
= XEXP (x
, !n
);
9812 inner_code
= GET_CODE (decomposed
);
9813 inner_op0
= XEXP (decomposed
, 0);
9814 inner_op1
= XEXP (decomposed
, 1);
9816 /* Special case (and (xor B C) (not A)), which is equivalent to
9817 (xor (ior A B) (ior A C)) */
9818 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9820 distributed
= XEXP (distributed
, 0);
9826 /* Distribute the second term. */
9827 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9828 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9832 /* Distribute the first term. */
9833 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9834 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9837 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9839 if (GET_CODE (tmp
) != outer_code
9840 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9841 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9847 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9848 in MODE. Return an equivalent form, if different from (and VAROP
9849 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9852 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9853 unsigned HOST_WIDE_INT constop
)
9855 unsigned HOST_WIDE_INT nonzero
;
9856 unsigned HOST_WIDE_INT orig_constop
;
9861 orig_constop
= constop
;
9862 if (GET_CODE (varop
) == CLOBBER
)
9865 /* Simplify VAROP knowing that we will be only looking at some of the
9868 Note by passing in CONSTOP, we guarantee that the bits not set in
9869 CONSTOP are not significant and will never be examined. We must
9870 ensure that is the case by explicitly masking out those bits
9871 before returning. */
9872 varop
= force_to_mode (varop
, mode
, constop
, 0);
9874 /* If VAROP is a CLOBBER, we will fail so return it. */
9875 if (GET_CODE (varop
) == CLOBBER
)
9878 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9879 to VAROP and return the new constant. */
9880 if (CONST_INT_P (varop
))
9881 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9883 /* See what bits may be nonzero in VAROP. Unlike the general case of
9884 a call to nonzero_bits, here we don't care about bits outside
9887 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9889 /* Turn off all bits in the constant that are known to already be zero.
9890 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9891 which is tested below. */
9895 /* If we don't have any bits left, return zero. */
9899 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9900 a power of two, we can replace this with an ASHIFT. */
9901 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9902 && (i
= exact_log2 (constop
)) >= 0)
9903 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9905 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9906 or XOR, then try to apply the distributive law. This may eliminate
9907 operations if either branch can be simplified because of the AND.
9908 It may also make some cases more complex, but those cases probably
9909 won't match a pattern either with or without this. */
9911 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9915 apply_distributive_law
9916 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9917 simplify_and_const_int (NULL_RTX
,
9921 simplify_and_const_int (NULL_RTX
,
9926 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9927 the AND and see if one of the operands simplifies to zero. If so, we
9928 may eliminate it. */
9930 if (GET_CODE (varop
) == PLUS
9931 && pow2p_hwi (constop
+ 1))
9935 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9936 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9937 if (o0
== const0_rtx
)
9939 if (o1
== const0_rtx
)
9943 /* Make a SUBREG if necessary. If we can't make it, fail. */
9944 varop
= gen_lowpart (mode
, varop
);
9945 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9948 /* If we are only masking insignificant bits, return VAROP. */
9949 if (constop
== nonzero
)
9952 if (varop
== orig_varop
&& constop
== orig_constop
)
9955 /* Otherwise, return an AND. */
9956 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9960 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9963 Return an equivalent form, if different from X. Otherwise, return X. If
9964 X is zero, we are to always construct the equivalent form. */
9967 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9968 unsigned HOST_WIDE_INT constop
)
9970 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9975 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9976 gen_int_mode (constop
, mode
));
9977 if (GET_MODE (x
) != mode
)
9978 x
= gen_lowpart (mode
, x
);
9982 /* Given a REG, X, compute which bits in X can be nonzero.
9983 We don't care about bits outside of those defined in MODE.
9985 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9986 a shift, AND, or zero_extract, we can do better. */
9989 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9990 const_rtx known_x ATTRIBUTE_UNUSED
,
9991 machine_mode known_mode ATTRIBUTE_UNUSED
,
9992 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9993 unsigned HOST_WIDE_INT
*nonzero
)
9998 /* If X is a register whose nonzero bits value is current, use it.
9999 Otherwise, if X is a register whose value we can find, use that
10000 value. Otherwise, use the previously-computed global nonzero bits
10001 for this register. */
10003 rsp
= ®_stat
[REGNO (x
)];
10004 if (rsp
->last_set_value
!= 0
10005 && (rsp
->last_set_mode
== mode
10006 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10007 && GET_MODE_CLASS (mode
) == MODE_INT
))
10008 && ((rsp
->last_set_label
>= label_tick_ebb_start
10009 && rsp
->last_set_label
< label_tick
)
10010 || (rsp
->last_set_label
== label_tick
10011 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10012 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10013 && REGNO (x
) < reg_n_sets_max
10014 && REG_N_SETS (REGNO (x
)) == 1
10015 && !REGNO_REG_SET_P
10016 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10019 /* Note that, even if the precision of last_set_mode is lower than that
10020 of mode, record_value_for_reg invoked nonzero_bits on the register
10021 with nonzero_bits_mode (because last_set_mode is necessarily integral
10022 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10023 are all valid, hence in mode too since nonzero_bits_mode is defined
10024 to the largest HWI_COMPUTABLE_MODE_P mode. */
10025 *nonzero
&= rsp
->last_set_nonzero_bits
;
10029 tem
= get_last_value (x
);
10032 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10033 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
10034 GET_MODE_PRECISION (mode
));
10039 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10041 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10043 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
10044 /* We don't know anything about the upper bits. */
10045 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
10053 /* Return the number of bits at the high-order end of X that are known to
10054 be equal to the sign bit. X will be used in mode MODE; if MODE is
10055 VOIDmode, X will be used in its own mode. The returned value will always
10056 be between 1 and the number of bits in MODE. */
10059 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
10060 const_rtx known_x ATTRIBUTE_UNUSED
,
10061 machine_mode known_mode
10063 unsigned int known_ret ATTRIBUTE_UNUSED
,
10064 unsigned int *result
)
10067 reg_stat_type
*rsp
;
10069 rsp
= ®_stat
[REGNO (x
)];
10070 if (rsp
->last_set_value
!= 0
10071 && rsp
->last_set_mode
== mode
10072 && ((rsp
->last_set_label
>= label_tick_ebb_start
10073 && rsp
->last_set_label
< label_tick
)
10074 || (rsp
->last_set_label
== label_tick
10075 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10076 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10077 && REGNO (x
) < reg_n_sets_max
10078 && REG_N_SETS (REGNO (x
)) == 1
10079 && !REGNO_REG_SET_P
10080 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10083 *result
= rsp
->last_set_sign_bit_copies
;
10087 tem
= get_last_value (x
);
10091 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10092 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
10093 *result
= rsp
->sign_bit_copies
;
10098 /* Return the number of "extended" bits there are in X, when interpreted
10099 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10100 unsigned quantities, this is the number of high-order zero bits.
10101 For signed quantities, this is the number of copies of the sign bit
10102 minus 1. In both case, this function returns the number of "spare"
10103 bits. For example, if two quantities for which this function returns
10104 at least 1 are added, the addition is known not to overflow.
10106 This function will always return 0 unless called during combine, which
10107 implies that it must be called from a define_split. */
10110 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10112 if (nonzero_sign_valid
== 0)
10116 ? (HWI_COMPUTABLE_MODE_P (mode
)
10117 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
10118 - floor_log2 (nonzero_bits (x
, mode
)))
10120 : num_sign_bit_copies (x
, mode
) - 1);
10123 /* This function is called from `simplify_shift_const' to merge two
10124 outer operations. Specifically, we have already found that we need
10125 to perform operation *POP0 with constant *PCONST0 at the outermost
10126 position. We would now like to also perform OP1 with constant CONST1
10127 (with *POP0 being done last).
10129 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10130 the resulting operation. *PCOMP_P is set to 1 if we would need to
10131 complement the innermost operand, otherwise it is unchanged.
10133 MODE is the mode in which the operation will be done. No bits outside
10134 the width of this mode matter. It is assumed that the width of this mode
10135 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10137 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10138 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10139 result is simply *PCONST0.
10141 If the resulting operation cannot be expressed as one operation, we
10142 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10145 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10147 enum rtx_code op0
= *pop0
;
10148 HOST_WIDE_INT const0
= *pconst0
;
10150 const0
&= GET_MODE_MASK (mode
);
10151 const1
&= GET_MODE_MASK (mode
);
10153 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10157 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10160 if (op1
== UNKNOWN
|| op0
== SET
)
10163 else if (op0
== UNKNOWN
)
10164 op0
= op1
, const0
= const1
;
10166 else if (op0
== op1
)
10190 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10191 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10194 /* If the two constants aren't the same, we can't do anything. The
10195 remaining six cases can all be done. */
10196 else if (const0
!= const1
)
10204 /* (a & b) | b == b */
10206 else /* op1 == XOR */
10207 /* (a ^ b) | b == a | b */
10213 /* (a & b) ^ b == (~a) & b */
10214 op0
= AND
, *pcomp_p
= 1;
10215 else /* op1 == IOR */
10216 /* (a | b) ^ b == a & ~b */
10217 op0
= AND
, const0
= ~const0
;
10222 /* (a | b) & b == b */
10224 else /* op1 == XOR */
10225 /* (a ^ b) & b) == (~a) & b */
10232 /* Check for NO-OP cases. */
10233 const0
&= GET_MODE_MASK (mode
);
10235 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10237 else if (const0
== 0 && op0
== AND
)
10239 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10245 /* ??? Slightly redundant with the above mask, but not entirely.
10246 Moving this above means we'd have to sign-extend the mode mask
10247 for the final test. */
10248 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10249 *pconst0
= trunc_int_for_mode (const0
, mode
);
10254 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10255 the shift in. The original shift operation CODE is performed on OP in
10256 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10257 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10258 result of the shift is subject to operation OUTER_CODE with operand
10261 static machine_mode
10262 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10263 machine_mode orig_mode
, machine_mode mode
,
10264 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10266 if (orig_mode
== mode
)
10268 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10270 /* In general we can't perform in wider mode for right shift and rotate. */
10274 /* We can still widen if the bits brought in from the left are identical
10275 to the sign bit of ORIG_MODE. */
10276 if (num_sign_bit_copies (op
, mode
)
10277 > (unsigned) (GET_MODE_PRECISION (mode
)
10278 - GET_MODE_PRECISION (orig_mode
)))
10283 /* Similarly here but with zero bits. */
10284 if (HWI_COMPUTABLE_MODE_P (mode
)
10285 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10288 /* We can also widen if the bits brought in will be masked off. This
10289 operation is performed in ORIG_MODE. */
10290 if (outer_code
== AND
)
10292 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10295 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10304 gcc_unreachable ();
10311 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10312 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10313 if we cannot simplify it. Otherwise, return a simplified value.
10315 The shift is normally computed in the widest mode we find in VAROP, as
10316 long as it isn't a different number of words than RESULT_MODE. Exceptions
10317 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10320 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10321 rtx varop
, int orig_count
)
10323 enum rtx_code orig_code
= code
;
10324 rtx orig_varop
= varop
;
10326 machine_mode mode
= result_mode
;
10327 machine_mode shift_mode
, tmode
;
10328 unsigned int mode_words
10329 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10330 /* We form (outer_op (code varop count) (outer_const)). */
10331 enum rtx_code outer_op
= UNKNOWN
;
10332 HOST_WIDE_INT outer_const
= 0;
10333 int complement_p
= 0;
10336 /* Make sure and truncate the "natural" shift on the way in. We don't
10337 want to do this inside the loop as it makes it more difficult to
10339 if (SHIFT_COUNT_TRUNCATED
)
10340 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10342 /* If we were given an invalid count, don't do anything except exactly
10343 what was requested. */
10345 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10348 count
= orig_count
;
10350 /* Unless one of the branches of the `if' in this loop does a `continue',
10351 we will `break' the loop after the `if'. */
10355 /* If we have an operand of (clobber (const_int 0)), fail. */
10356 if (GET_CODE (varop
) == CLOBBER
)
10359 /* Convert ROTATERT to ROTATE. */
10360 if (code
== ROTATERT
)
10362 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10364 count
= bitsize
- count
;
10367 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10368 mode
, outer_op
, outer_const
);
10369 machine_mode shift_unit_mode
= GET_MODE_INNER (shift_mode
);
10371 /* Handle cases where the count is greater than the size of the mode
10372 minus 1. For ASHIFT, use the size minus one as the count (this can
10373 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10374 take the count modulo the size. For other shifts, the result is
10377 Since these shifts are being produced by the compiler by combining
10378 multiple operations, each of which are defined, we know what the
10379 result is supposed to be. */
10381 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10383 if (code
== ASHIFTRT
)
10384 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10385 else if (code
== ROTATE
|| code
== ROTATERT
)
10386 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10389 /* We can't simply return zero because there may be an
10391 varop
= const0_rtx
;
10397 /* If we discovered we had to complement VAROP, leave. Making a NOT
10398 here would cause an infinite loop. */
10402 if (shift_mode
== shift_unit_mode
)
10404 /* An arithmetic right shift of a quantity known to be -1 or 0
10406 if (code
== ASHIFTRT
10407 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10408 == GET_MODE_PRECISION (shift_unit_mode
)))
10414 /* If we are doing an arithmetic right shift and discarding all but
10415 the sign bit copies, this is equivalent to doing a shift by the
10416 bitsize minus one. Convert it into that shift because it will
10417 often allow other simplifications. */
10419 if (code
== ASHIFTRT
10420 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10421 >= GET_MODE_PRECISION (shift_unit_mode
)))
10422 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10424 /* We simplify the tests below and elsewhere by converting
10425 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10426 `make_compound_operation' will convert it to an ASHIFTRT for
10427 those machines (such as VAX) that don't have an LSHIFTRT. */
10428 if (code
== ASHIFTRT
10429 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10430 && val_signbit_known_clear_p (shift_unit_mode
,
10431 nonzero_bits (varop
,
10435 if (((code
== LSHIFTRT
10436 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10437 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10439 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10440 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10441 & GET_MODE_MASK (shift_unit_mode
))))
10442 && !side_effects_p (varop
))
10443 varop
= const0_rtx
;
10446 switch (GET_CODE (varop
))
10452 new_rtx
= expand_compound_operation (varop
);
10453 if (new_rtx
!= varop
)
10461 /* The following rules apply only to scalars. */
10462 if (shift_mode
!= shift_unit_mode
)
10465 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10466 minus the width of a smaller mode, we can do this with a
10467 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10468 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10469 && ! mode_dependent_address_p (XEXP (varop
, 0),
10470 MEM_ADDR_SPACE (varop
))
10471 && ! MEM_VOLATILE_P (varop
)
10472 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10473 MODE_INT
, 1)) != BLKmode
)
10475 new_rtx
= adjust_address_nv (varop
, tmode
,
10476 BYTES_BIG_ENDIAN
? 0
10477 : count
/ BITS_PER_UNIT
);
10479 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10480 : ZERO_EXTEND
, mode
, new_rtx
);
10487 /* The following rules apply only to scalars. */
10488 if (shift_mode
!= shift_unit_mode
)
10491 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10492 the same number of words as what we've seen so far. Then store
10493 the widest mode in MODE. */
10494 if (subreg_lowpart_p (varop
)
10495 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10496 > GET_MODE_SIZE (GET_MODE (varop
)))
10497 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10498 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10500 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10501 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10503 varop
= SUBREG_REG (varop
);
10504 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10505 mode
= GET_MODE (varop
);
10511 /* Some machines use MULT instead of ASHIFT because MULT
10512 is cheaper. But it is still better on those machines to
10513 merge two shifts into one. */
10514 if (CONST_INT_P (XEXP (varop
, 1))
10515 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10518 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10520 GEN_INT (exact_log2 (
10521 UINTVAL (XEXP (varop
, 1)))));
10527 /* Similar, for when divides are cheaper. */
10528 if (CONST_INT_P (XEXP (varop
, 1))
10529 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10532 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10534 GEN_INT (exact_log2 (
10535 UINTVAL (XEXP (varop
, 1)))));
10541 /* If we are extracting just the sign bit of an arithmetic
10542 right shift, that shift is not needed. However, the sign
10543 bit of a wider mode may be different from what would be
10544 interpreted as the sign bit in a narrower mode, so, if
10545 the result is narrower, don't discard the shift. */
10546 if (code
== LSHIFTRT
10547 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10548 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10549 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10551 varop
= XEXP (varop
, 0);
10560 /* The following rules apply only to scalars. */
10561 if (shift_mode
!= shift_unit_mode
)
10564 /* Here we have two nested shifts. The result is usually the
10565 AND of a new shift with a mask. We compute the result below. */
10566 if (CONST_INT_P (XEXP (varop
, 1))
10567 && INTVAL (XEXP (varop
, 1)) >= 0
10568 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10569 && HWI_COMPUTABLE_MODE_P (result_mode
)
10570 && HWI_COMPUTABLE_MODE_P (mode
))
10572 enum rtx_code first_code
= GET_CODE (varop
);
10573 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10574 unsigned HOST_WIDE_INT mask
;
10577 /* We have one common special case. We can't do any merging if
10578 the inner code is an ASHIFTRT of a smaller mode. However, if
10579 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10580 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10581 we can convert it to
10582 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10583 This simplifies certain SIGN_EXTEND operations. */
10584 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10585 && count
== (GET_MODE_PRECISION (result_mode
)
10586 - GET_MODE_PRECISION (GET_MODE (varop
))))
10588 /* C3 has the low-order C1 bits zero. */
10590 mask
= GET_MODE_MASK (mode
)
10591 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10593 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10594 XEXP (varop
, 0), mask
);
10595 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10597 count
= first_count
;
10602 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10603 than C1 high-order bits equal to the sign bit, we can convert
10604 this to either an ASHIFT or an ASHIFTRT depending on the
10607 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10609 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10610 && GET_MODE (varop
) == shift_mode
10611 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10614 varop
= XEXP (varop
, 0);
10615 count
-= first_count
;
10625 /* There are some cases we can't do. If CODE is ASHIFTRT,
10626 we can only do this if FIRST_CODE is also ASHIFTRT.
10628 We can't do the case when CODE is ROTATE and FIRST_CODE is
10631 If the mode of this shift is not the mode of the outer shift,
10632 we can't do this if either shift is a right shift or ROTATE.
10634 Finally, we can't do any of these if the mode is too wide
10635 unless the codes are the same.
10637 Handle the case where the shift codes are the same
10640 if (code
== first_code
)
10642 if (GET_MODE (varop
) != result_mode
10643 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10644 || code
== ROTATE
))
10647 count
+= first_count
;
10648 varop
= XEXP (varop
, 0);
10652 if (code
== ASHIFTRT
10653 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10654 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10655 || (GET_MODE (varop
) != result_mode
10656 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10657 || first_code
== ROTATE
10658 || code
== ROTATE
)))
10661 /* To compute the mask to apply after the shift, shift the
10662 nonzero bits of the inner shift the same way the
10663 outer shift will. */
10665 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10669 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10672 /* Give up if we can't compute an outer operation to use. */
10674 || !CONST_INT_P (mask_rtx
)
10675 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10677 result_mode
, &complement_p
))
10680 /* If the shifts are in the same direction, we add the
10681 counts. Otherwise, we subtract them. */
10682 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10683 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10684 count
+= first_count
;
10686 count
-= first_count
;
10688 /* If COUNT is positive, the new shift is usually CODE,
10689 except for the two exceptions below, in which case it is
10690 FIRST_CODE. If the count is negative, FIRST_CODE should
10693 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10694 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10696 else if (count
< 0)
10697 code
= first_code
, count
= -count
;
10699 varop
= XEXP (varop
, 0);
10703 /* If we have (A << B << C) for any shift, we can convert this to
10704 (A << C << B). This wins if A is a constant. Only try this if
10705 B is not a constant. */
10707 else if (GET_CODE (varop
) == code
10708 && CONST_INT_P (XEXP (varop
, 0))
10709 && !CONST_INT_P (XEXP (varop
, 1)))
10711 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10712 sure the result will be masked. See PR70222. */
10713 if (code
== LSHIFTRT
10714 && mode
!= result_mode
10715 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10716 GET_MODE_MASK (result_mode
)
10717 >> orig_count
, result_mode
,
10720 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10721 up outer sign extension (often left and right shift) is
10722 hardly more efficient than the original. See PR70429. */
10723 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10726 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10729 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10736 /* The following rules apply only to scalars. */
10737 if (shift_mode
!= shift_unit_mode
)
10740 /* Make this fit the case below. */
10741 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10747 /* The following rules apply only to scalars. */
10748 if (shift_mode
!= shift_unit_mode
)
10751 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10752 with C the size of VAROP - 1 and the shift is logical if
10753 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10754 we have an (le X 0) operation. If we have an arithmetic shift
10755 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10756 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10758 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10759 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10760 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10761 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10762 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10763 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10766 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10769 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10770 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10775 /* If we have (shift (logical)), move the logical to the outside
10776 to allow it to possibly combine with another logical and the
10777 shift to combine with another shift. This also canonicalizes to
10778 what a ZERO_EXTRACT looks like. Also, some machines have
10779 (and (shift)) insns. */
10781 if (CONST_INT_P (XEXP (varop
, 1))
10782 /* We can't do this if we have (ashiftrt (xor)) and the
10783 constant has its sign bit set in shift_mode with shift_mode
10784 wider than result_mode. */
10785 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10786 && result_mode
!= shift_mode
10787 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10789 && (new_rtx
= simplify_const_binary_operation
10790 (code
, result_mode
,
10791 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10792 GEN_INT (count
))) != 0
10793 && CONST_INT_P (new_rtx
)
10794 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10795 INTVAL (new_rtx
), result_mode
, &complement_p
))
10797 varop
= XEXP (varop
, 0);
10801 /* If we can't do that, try to simplify the shift in each arm of the
10802 logical expression, make a new logical expression, and apply
10803 the inverse distributive law. This also can't be done for
10804 (ashiftrt (xor)) where we've widened the shift and the constant
10805 changes the sign bit. */
10806 if (CONST_INT_P (XEXP (varop
, 1))
10807 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10808 && result_mode
!= shift_mode
10809 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10812 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10813 XEXP (varop
, 0), count
);
10814 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10815 XEXP (varop
, 1), count
);
10817 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10819 varop
= apply_distributive_law (varop
);
10827 /* The following rules apply only to scalars. */
10828 if (shift_mode
!= shift_unit_mode
)
10831 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10832 says that the sign bit can be tested, FOO has mode MODE, C is
10833 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10834 that may be nonzero. */
10835 if (code
== LSHIFTRT
10836 && XEXP (varop
, 1) == const0_rtx
10837 && GET_MODE (XEXP (varop
, 0)) == result_mode
10838 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10839 && HWI_COMPUTABLE_MODE_P (result_mode
)
10840 && STORE_FLAG_VALUE
== -1
10841 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10842 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10845 varop
= XEXP (varop
, 0);
10852 /* The following rules apply only to scalars. */
10853 if (shift_mode
!= shift_unit_mode
)
10856 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10857 than the number of bits in the mode is equivalent to A. */
10858 if (code
== LSHIFTRT
10859 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10860 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10862 varop
= XEXP (varop
, 0);
10867 /* NEG commutes with ASHIFT since it is multiplication. Move the
10868 NEG outside to allow shifts to combine. */
10870 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10873 varop
= XEXP (varop
, 0);
10879 /* The following rules apply only to scalars. */
10880 if (shift_mode
!= shift_unit_mode
)
10883 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10884 is one less than the number of bits in the mode is
10885 equivalent to (xor A 1). */
10886 if (code
== LSHIFTRT
10887 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10888 && XEXP (varop
, 1) == constm1_rtx
10889 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10890 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10894 varop
= XEXP (varop
, 0);
10898 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10899 that might be nonzero in BAR are those being shifted out and those
10900 bits are known zero in FOO, we can replace the PLUS with FOO.
10901 Similarly in the other operand order. This code occurs when
10902 we are computing the size of a variable-size array. */
10904 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10905 && count
< HOST_BITS_PER_WIDE_INT
10906 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10907 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10908 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10910 varop
= XEXP (varop
, 0);
10913 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10914 && count
< HOST_BITS_PER_WIDE_INT
10915 && HWI_COMPUTABLE_MODE_P (result_mode
)
10916 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10918 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10919 & nonzero_bits (XEXP (varop
, 1),
10922 varop
= XEXP (varop
, 1);
10926 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10928 && CONST_INT_P (XEXP (varop
, 1))
10929 && (new_rtx
= simplify_const_binary_operation
10930 (ASHIFT
, result_mode
,
10931 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10932 GEN_INT (count
))) != 0
10933 && CONST_INT_P (new_rtx
)
10934 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10935 INTVAL (new_rtx
), result_mode
, &complement_p
))
10937 varop
= XEXP (varop
, 0);
10941 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10942 signbit', and attempt to change the PLUS to an XOR and move it to
10943 the outer operation as is done above in the AND/IOR/XOR case
10944 leg for shift(logical). See details in logical handling above
10945 for reasoning in doing so. */
10946 if (code
== LSHIFTRT
10947 && CONST_INT_P (XEXP (varop
, 1))
10948 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10949 && (new_rtx
= simplify_const_binary_operation
10950 (code
, result_mode
,
10951 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10952 GEN_INT (count
))) != 0
10953 && CONST_INT_P (new_rtx
)
10954 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10955 INTVAL (new_rtx
), result_mode
, &complement_p
))
10957 varop
= XEXP (varop
, 0);
10964 /* The following rules apply only to scalars. */
10965 if (shift_mode
!= shift_unit_mode
)
10968 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10969 with C the size of VAROP - 1 and the shift is logical if
10970 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10971 we have a (gt X 0) operation. If the shift is arithmetic with
10972 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10973 we have a (neg (gt X 0)) operation. */
10975 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10976 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10977 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10978 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10979 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10980 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10981 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10984 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10987 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10988 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10995 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10996 if the truncate does not affect the value. */
10997 if (code
== LSHIFTRT
10998 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10999 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11000 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11001 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11002 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11004 rtx varop_inner
= XEXP (varop
, 0);
11007 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11008 XEXP (varop_inner
, 0),
11010 (count
+ INTVAL (XEXP (varop_inner
, 1))));
11011 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11024 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
11025 outer_op
, outer_const
);
11027 /* We have now finished analyzing the shift. The result should be
11028 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11029 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11030 to the result of the shift. OUTER_CONST is the relevant constant,
11031 but we must turn off all bits turned off in the shift. */
11033 if (outer_op
== UNKNOWN
11034 && orig_code
== code
&& orig_count
== count
11035 && varop
== orig_varop
11036 && shift_mode
== GET_MODE (varop
))
11039 /* Make a SUBREG if necessary. If we can't make it, fail. */
11040 varop
= gen_lowpart (shift_mode
, varop
);
11041 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11044 /* If we have an outer operation and we just made a shift, it is
11045 possible that we could have simplified the shift were it not
11046 for the outer operation. So try to do the simplification
11049 if (outer_op
!= UNKNOWN
)
11050 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11055 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11057 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11058 turn off all the bits that the shift would have turned off. */
11059 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11060 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
11061 GET_MODE_MASK (result_mode
) >> orig_count
);
11063 /* Do the remainder of the processing in RESULT_MODE. */
11064 x
= gen_lowpart_or_truncate (result_mode
, x
);
11066 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11069 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11071 if (outer_op
!= UNKNOWN
)
11073 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11074 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
11075 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
11077 if (outer_op
== AND
)
11078 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
11079 else if (outer_op
== SET
)
11081 /* This means that we have determined that the result is
11082 equivalent to a constant. This should be rare. */
11083 if (!side_effects_p (x
))
11084 x
= GEN_INT (outer_const
);
11086 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11087 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
11089 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
11090 GEN_INT (outer_const
));
11096 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11097 The result of the shift is RESULT_MODE. If we cannot simplify it,
11098 return X or, if it is NULL, synthesize the expression with
11099 simplify_gen_binary. Otherwise, return a simplified value.
11101 The shift is normally computed in the widest mode we find in VAROP, as
11102 long as it isn't a different number of words than RESULT_MODE. Exceptions
11103 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11106 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11107 rtx varop
, int count
)
11109 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11114 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11115 if (GET_MODE (x
) != result_mode
)
11116 x
= gen_lowpart (result_mode
, x
);
11121 /* A subroutine of recog_for_combine. See there for arguments and
11125 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11127 rtx pat
= *pnewpat
;
11128 rtx pat_without_clobbers
;
11129 int insn_code_number
;
11130 int num_clobbers_to_add
= 0;
11132 rtx notes
= NULL_RTX
;
11133 rtx old_notes
, old_pat
;
11136 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11137 we use to indicate that something didn't match. If we find such a
11138 thing, force rejection. */
11139 if (GET_CODE (pat
) == PARALLEL
)
11140 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11141 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11142 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11145 old_pat
= PATTERN (insn
);
11146 old_notes
= REG_NOTES (insn
);
11147 PATTERN (insn
) = pat
;
11148 REG_NOTES (insn
) = NULL_RTX
;
11150 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11151 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11153 if (insn_code_number
< 0)
11154 fputs ("Failed to match this instruction:\n", dump_file
);
11156 fputs ("Successfully matched this instruction:\n", dump_file
);
11157 print_rtl_single (dump_file
, pat
);
11160 /* If it isn't, there is the possibility that we previously had an insn
11161 that clobbered some register as a side effect, but the combined
11162 insn doesn't need to do that. So try once more without the clobbers
11163 unless this represents an ASM insn. */
11165 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11166 && GET_CODE (pat
) == PARALLEL
)
11170 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11171 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11174 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11178 SUBST_INT (XVECLEN (pat
, 0), pos
);
11181 pat
= XVECEXP (pat
, 0, 0);
11183 PATTERN (insn
) = pat
;
11184 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11185 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11187 if (insn_code_number
< 0)
11188 fputs ("Failed to match this instruction:\n", dump_file
);
11190 fputs ("Successfully matched this instruction:\n", dump_file
);
11191 print_rtl_single (dump_file
, pat
);
11195 pat_without_clobbers
= pat
;
11197 PATTERN (insn
) = old_pat
;
11198 REG_NOTES (insn
) = old_notes
;
11200 /* Recognize all noop sets, these will be killed by followup pass. */
11201 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11202 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11204 /* If we had any clobbers to add, make a new pattern than contains
11205 them. Then check to make sure that all of them are dead. */
11206 if (num_clobbers_to_add
)
11208 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11209 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11210 ? (XVECLEN (pat
, 0)
11211 + num_clobbers_to_add
)
11212 : num_clobbers_to_add
+ 1));
11214 if (GET_CODE (pat
) == PARALLEL
)
11215 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11216 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11218 XVECEXP (newpat
, 0, 0) = pat
;
11220 add_clobbers (newpat
, insn_code_number
);
11222 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11223 i
< XVECLEN (newpat
, 0); i
++)
11225 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11226 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11228 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11230 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11231 notes
= alloc_reg_note (REG_UNUSED
,
11232 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11238 if (insn_code_number
>= 0
11239 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11241 old_pat
= PATTERN (insn
);
11242 old_notes
= REG_NOTES (insn
);
11243 old_icode
= INSN_CODE (insn
);
11244 PATTERN (insn
) = pat
;
11245 REG_NOTES (insn
) = notes
;
11246 INSN_CODE (insn
) = insn_code_number
;
11248 /* Allow targets to reject combined insn. */
11249 if (!targetm
.legitimate_combined_insn (insn
))
11251 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11252 fputs ("Instruction not appropriate for target.",
11255 /* Callers expect recog_for_combine to strip
11256 clobbers from the pattern on failure. */
11257 pat
= pat_without_clobbers
;
11260 insn_code_number
= -1;
11263 PATTERN (insn
) = old_pat
;
11264 REG_NOTES (insn
) = old_notes
;
11265 INSN_CODE (insn
) = old_icode
;
11271 return insn_code_number
;
11274 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11275 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11276 Return whether anything was so changed. */
11279 change_zero_ext (rtx pat
)
11281 bool changed
= false;
11282 rtx
*src
= &SET_SRC (pat
);
11284 subrtx_ptr_iterator::array_type array
;
11285 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11288 machine_mode mode
= GET_MODE (x
);
11291 if (GET_CODE (x
) == ZERO_EXTRACT
11292 && CONST_INT_P (XEXP (x
, 1))
11293 && CONST_INT_P (XEXP (x
, 2))
11294 && GET_MODE (XEXP (x
, 0)) != VOIDmode
11295 && GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
11296 <= GET_MODE_PRECISION (mode
))
11298 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
11300 size
= INTVAL (XEXP (x
, 1));
11302 int start
= INTVAL (XEXP (x
, 2));
11303 if (BITS_BIG_ENDIAN
)
11304 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11307 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11310 if (mode
!= inner_mode
)
11311 x
= gen_lowpart_SUBREG (mode
, x
);
11313 else if (GET_CODE (x
) == ZERO_EXTEND
11314 && SCALAR_INT_MODE_P (mode
)
11315 && GET_CODE (XEXP (x
, 0)) == SUBREG
11316 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11317 && !paradoxical_subreg_p (XEXP (x
, 0))
11318 && subreg_lowpart_p (XEXP (x
, 0)))
11320 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11321 x
= SUBREG_REG (XEXP (x
, 0));
11322 if (GET_MODE (x
) != mode
)
11323 x
= gen_lowpart_SUBREG (mode
, x
);
11325 else if (GET_CODE (x
) == ZERO_EXTEND
11326 && SCALAR_INT_MODE_P (mode
)
11327 && REG_P (XEXP (x
, 0))
11328 && HARD_REGISTER_P (XEXP (x
, 0))
11329 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11331 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11332 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11337 if (!(GET_CODE (x
) == LSHIFTRT
11338 && CONST_INT_P (XEXP (x
, 1))
11339 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11341 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11342 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11350 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11351 maybe_swap_commutative_operands (**iter
);
11353 rtx
*dst
= &SET_DEST (pat
);
11354 if (GET_CODE (*dst
) == ZERO_EXTRACT
11355 && REG_P (XEXP (*dst
, 0))
11356 && CONST_INT_P (XEXP (*dst
, 1))
11357 && CONST_INT_P (XEXP (*dst
, 2)))
11359 rtx reg
= XEXP (*dst
, 0);
11360 int width
= INTVAL (XEXP (*dst
, 1));
11361 int offset
= INTVAL (XEXP (*dst
, 2));
11362 machine_mode mode
= GET_MODE (reg
);
11363 int reg_width
= GET_MODE_PRECISION (mode
);
11364 if (BITS_BIG_ENDIAN
)
11365 offset
= reg_width
- width
- offset
;
11368 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11369 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11370 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11372 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11375 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11376 w
= gen_rtx_IOR (mode
, x
, z
);
11377 SUBST (SET_DEST (pat
), reg
);
11378 SUBST (SET_SRC (pat
), w
);
11386 /* Like recog, but we receive the address of a pointer to a new pattern.
11387 We try to match the rtx that the pointer points to.
11388 If that fails, we may try to modify or replace the pattern,
11389 storing the replacement into the same pointer object.
11391 Modifications include deletion or addition of CLOBBERs. If the
11392 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11393 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11394 (and undo if that fails).
11396 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11397 the CLOBBERs are placed.
11399 The value is the final insn code from the pattern ultimately matched,
11403 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11405 rtx pat
= *pnewpat
;
11406 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11407 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11408 return insn_code_number
;
11410 void *marker
= get_undo_marker ();
11411 bool changed
= false;
11413 if (GET_CODE (pat
) == SET
)
11414 changed
= change_zero_ext (pat
);
11415 else if (GET_CODE (pat
) == PARALLEL
)
11418 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11420 rtx set
= XVECEXP (pat
, 0, i
);
11421 if (GET_CODE (set
) == SET
)
11422 changed
|= change_zero_ext (set
);
11428 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11430 if (insn_code_number
< 0)
11431 undo_to_marker (marker
);
11434 return insn_code_number
;
11437 /* Like gen_lowpart_general but for use by combine. In combine it
11438 is not possible to create any new pseudoregs. However, it is
11439 safe to create invalid memory addresses, because combine will
11440 try to recognize them and all they will do is make the combine
11443 If for some reason this cannot do its job, an rtx
11444 (clobber (const_int 0)) is returned.
11445 An insn containing that will not be recognized. */
11448 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11450 machine_mode imode
= GET_MODE (x
);
11451 unsigned int osize
= GET_MODE_SIZE (omode
);
11452 unsigned int isize
= GET_MODE_SIZE (imode
);
11455 if (omode
== imode
)
11458 /* We can only support MODE being wider than a word if X is a
11459 constant integer or has a mode the same size. */
11460 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11461 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11464 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11465 won't know what to do. So we will strip off the SUBREG here and
11466 process normally. */
11467 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11469 x
= SUBREG_REG (x
);
11471 /* For use in case we fall down into the address adjustments
11472 further below, we need to adjust the known mode and size of
11473 x; imode and isize, since we just adjusted x. */
11474 imode
= GET_MODE (x
);
11476 if (imode
== omode
)
11479 isize
= GET_MODE_SIZE (imode
);
11482 result
= gen_lowpart_common (omode
, x
);
11491 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11493 if (MEM_VOLATILE_P (x
)
11494 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11497 /* If we want to refer to something bigger than the original memref,
11498 generate a paradoxical subreg instead. That will force a reload
11499 of the original memref X. */
11501 return gen_rtx_SUBREG (omode
, x
, 0);
11503 if (WORDS_BIG_ENDIAN
)
11504 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11506 /* Adjust the address so that the address-after-the-data is
11508 if (BYTES_BIG_ENDIAN
)
11509 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11511 return adjust_address_nv (x
, omode
, offset
);
11514 /* If X is a comparison operator, rewrite it in a new mode. This
11515 probably won't match, but may allow further simplifications. */
11516 else if (COMPARISON_P (x
))
11517 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11519 /* If we couldn't simplify X any other way, just enclose it in a
11520 SUBREG. Normally, this SUBREG won't match, but some patterns may
11521 include an explicit SUBREG or we may simplify it further in combine. */
11526 if (imode
== VOIDmode
)
11528 imode
= int_mode_for_mode (omode
);
11529 x
= gen_lowpart_common (imode
, x
);
11533 res
= lowpart_subreg (omode
, x
, imode
);
11539 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11542 /* Try to simplify a comparison between OP0 and a constant OP1,
11543 where CODE is the comparison code that will be tested, into a
11544 (CODE OP0 const0_rtx) form.
11546 The result is a possibly different comparison code to use.
11547 *POP1 may be updated. */
11549 static enum rtx_code
11550 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11551 rtx op0
, rtx
*pop1
)
11553 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11554 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11556 /* Get the constant we are comparing against and turn off all bits
11557 not on in our mode. */
11558 if (mode
!= VOIDmode
)
11559 const_op
= trunc_int_for_mode (const_op
, mode
);
11561 /* If we are comparing against a constant power of two and the value
11562 being compared can only have that single bit nonzero (e.g., it was
11563 `and'ed with that bit), we can replace this with a comparison
11566 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11567 || code
== LT
|| code
== LTU
)
11568 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11569 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11570 && (nonzero_bits (op0
, mode
)
11571 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11573 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11577 /* Similarly, if we are comparing a value known to be either -1 or
11578 0 with -1, change it to the opposite comparison against zero. */
11580 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11581 || code
== GEU
|| code
== LTU
)
11582 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11584 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11588 /* Do some canonicalizations based on the comparison code. We prefer
11589 comparisons against zero and then prefer equality comparisons.
11590 If we can reduce the size of a constant, we will do that too. */
11594 /* < C is equivalent to <= (C - 1) */
11599 /* ... fall through to LE case below. */
11600 gcc_fallthrough ();
11606 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11613 /* If we are doing a <= 0 comparison on a value known to have
11614 a zero sign bit, we can replace this with == 0. */
11615 else if (const_op
== 0
11616 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11617 && (nonzero_bits (op0
, mode
)
11618 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11624 /* >= C is equivalent to > (C - 1). */
11629 /* ... fall through to GT below. */
11630 gcc_fallthrough ();
11636 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11643 /* If we are doing a > 0 comparison on a value known to have
11644 a zero sign bit, we can replace this with != 0. */
11645 else if (const_op
== 0
11646 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11647 && (nonzero_bits (op0
, mode
)
11648 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11654 /* < C is equivalent to <= (C - 1). */
11659 /* ... fall through ... */
11661 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11662 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11663 && (unsigned HOST_WIDE_INT
) const_op
11664 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11674 /* unsigned <= 0 is equivalent to == 0 */
11677 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11678 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11679 && (unsigned HOST_WIDE_INT
) const_op
11680 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11688 /* >= C is equivalent to > (C - 1). */
11693 /* ... fall through ... */
11696 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11697 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11698 && (unsigned HOST_WIDE_INT
) const_op
11699 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11709 /* unsigned > 0 is equivalent to != 0 */
11712 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11713 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11714 && (unsigned HOST_WIDE_INT
) const_op
11715 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11726 *pop1
= GEN_INT (const_op
);
11730 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11731 comparison code that will be tested.
11733 The result is a possibly different comparison code to use. *POP0 and
11734 *POP1 may be updated.
11736 It is possible that we might detect that a comparison is either always
11737 true or always false. However, we do not perform general constant
11738 folding in combine, so this knowledge isn't useful. Such tautologies
11739 should have been detected earlier. Hence we ignore all such cases. */
11741 static enum rtx_code
11742 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11748 machine_mode mode
, tmode
;
11750 /* Try a few ways of applying the same transformation to both operands. */
11753 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11754 so check specially. */
11755 if (!WORD_REGISTER_OPERATIONS
11756 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11757 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11758 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11759 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11760 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11761 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11762 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11763 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11764 && CONST_INT_P (XEXP (op0
, 1))
11765 && XEXP (op0
, 1) == XEXP (op1
, 1)
11766 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11767 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11768 && (INTVAL (XEXP (op0
, 1))
11769 == (GET_MODE_PRECISION (GET_MODE (op0
))
11770 - (GET_MODE_PRECISION
11771 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11773 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11774 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11777 /* If both operands are the same constant shift, see if we can ignore the
11778 shift. We can if the shift is a rotate or if the bits shifted out of
11779 this shift are known to be zero for both inputs and if the type of
11780 comparison is compatible with the shift. */
11781 if (GET_CODE (op0
) == GET_CODE (op1
)
11782 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11783 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11784 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11785 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11786 || (GET_CODE (op0
) == ASHIFTRT
11787 && (code
!= GTU
&& code
!= LTU
11788 && code
!= GEU
&& code
!= LEU
)))
11789 && CONST_INT_P (XEXP (op0
, 1))
11790 && INTVAL (XEXP (op0
, 1)) >= 0
11791 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11792 && XEXP (op0
, 1) == XEXP (op1
, 1))
11794 machine_mode mode
= GET_MODE (op0
);
11795 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11796 int shift_count
= INTVAL (XEXP (op0
, 1));
11798 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11799 mask
&= (mask
>> shift_count
) << shift_count
;
11800 else if (GET_CODE (op0
) == ASHIFT
)
11801 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11803 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11804 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11805 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11810 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11811 SUBREGs are of the same mode, and, in both cases, the AND would
11812 be redundant if the comparison was done in the narrower mode,
11813 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11814 and the operand's possibly nonzero bits are 0xffffff01; in that case
11815 if we only care about QImode, we don't need the AND). This case
11816 occurs if the output mode of an scc insn is not SImode and
11817 STORE_FLAG_VALUE == 1 (e.g., the 386).
11819 Similarly, check for a case where the AND's are ZERO_EXTEND
11820 operations from some narrower mode even though a SUBREG is not
11823 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11824 && CONST_INT_P (XEXP (op0
, 1))
11825 && CONST_INT_P (XEXP (op1
, 1)))
11827 rtx inner_op0
= XEXP (op0
, 0);
11828 rtx inner_op1
= XEXP (op1
, 0);
11829 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11830 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11833 if (paradoxical_subreg_p (inner_op0
)
11834 && GET_CODE (inner_op1
) == SUBREG
11835 && (GET_MODE (SUBREG_REG (inner_op0
))
11836 == GET_MODE (SUBREG_REG (inner_op1
)))
11837 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11838 <= HOST_BITS_PER_WIDE_INT
)
11839 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11840 GET_MODE (SUBREG_REG (inner_op0
)))))
11841 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11842 GET_MODE (SUBREG_REG (inner_op1
))))))
11844 op0
= SUBREG_REG (inner_op0
);
11845 op1
= SUBREG_REG (inner_op1
);
11847 /* The resulting comparison is always unsigned since we masked
11848 off the original sign bit. */
11849 code
= unsigned_condition (code
);
11855 for (tmode
= GET_CLASS_NARROWEST_MODE
11856 (GET_MODE_CLASS (GET_MODE (op0
)));
11857 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11858 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11860 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11861 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11862 code
= unsigned_condition (code
);
11871 /* If both operands are NOT, we can strip off the outer operation
11872 and adjust the comparison code for swapped operands; similarly for
11873 NEG, except that this must be an equality comparison. */
11874 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11875 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11876 && (code
== EQ
|| code
== NE
)))
11877 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11883 /* If the first operand is a constant, swap the operands and adjust the
11884 comparison code appropriately, but don't do this if the second operand
11885 is already a constant integer. */
11886 if (swap_commutative_operands_p (op0
, op1
))
11888 std::swap (op0
, op1
);
11889 code
= swap_condition (code
);
11892 /* We now enter a loop during which we will try to simplify the comparison.
11893 For the most part, we only are concerned with comparisons with zero,
11894 but some things may really be comparisons with zero but not start
11895 out looking that way. */
11897 while (CONST_INT_P (op1
))
11899 machine_mode mode
= GET_MODE (op0
);
11900 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11901 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11902 int equality_comparison_p
;
11903 int sign_bit_comparison_p
;
11904 int unsigned_comparison_p
;
11905 HOST_WIDE_INT const_op
;
11907 /* We only want to handle integral modes. This catches VOIDmode,
11908 CCmode, and the floating-point modes. An exception is that we
11909 can handle VOIDmode if OP0 is a COMPARE or a comparison
11912 if (GET_MODE_CLASS (mode
) != MODE_INT
11913 && ! (mode
== VOIDmode
11914 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11917 /* Try to simplify the compare to constant, possibly changing the
11918 comparison op, and/or changing op1 to zero. */
11919 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11920 const_op
= INTVAL (op1
);
11922 /* Compute some predicates to simplify code below. */
11924 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11925 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11926 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11929 /* If this is a sign bit comparison and we can do arithmetic in
11930 MODE, say that we will only be needing the sign bit of OP0. */
11931 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11932 op0
= force_to_mode (op0
, mode
,
11934 << (GET_MODE_PRECISION (mode
) - 1),
11937 /* Now try cases based on the opcode of OP0. If none of the cases
11938 does a "continue", we exit this loop immediately after the
11941 switch (GET_CODE (op0
))
11944 /* If we are extracting a single bit from a variable position in
11945 a constant that has only a single bit set and are comparing it
11946 with zero, we can convert this into an equality comparison
11947 between the position and the location of the single bit. */
11948 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11949 have already reduced the shift count modulo the word size. */
11950 if (!SHIFT_COUNT_TRUNCATED
11951 && CONST_INT_P (XEXP (op0
, 0))
11952 && XEXP (op0
, 1) == const1_rtx
11953 && equality_comparison_p
&& const_op
== 0
11954 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11956 if (BITS_BIG_ENDIAN
)
11957 i
= BITS_PER_WORD
- 1 - i
;
11959 op0
= XEXP (op0
, 2);
11963 /* Result is nonzero iff shift count is equal to I. */
11964 code
= reverse_condition (code
);
11971 tem
= expand_compound_operation (op0
);
11980 /* If testing for equality, we can take the NOT of the constant. */
11981 if (equality_comparison_p
11982 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11984 op0
= XEXP (op0
, 0);
11989 /* If just looking at the sign bit, reverse the sense of the
11991 if (sign_bit_comparison_p
)
11993 op0
= XEXP (op0
, 0);
11994 code
= (code
== GE
? LT
: GE
);
12000 /* If testing for equality, we can take the NEG of the constant. */
12001 if (equality_comparison_p
12002 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12004 op0
= XEXP (op0
, 0);
12009 /* The remaining cases only apply to comparisons with zero. */
12013 /* When X is ABS or is known positive,
12014 (neg X) is < 0 if and only if X != 0. */
12016 if (sign_bit_comparison_p
12017 && (GET_CODE (XEXP (op0
, 0)) == ABS
12018 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12019 && (nonzero_bits (XEXP (op0
, 0), mode
)
12020 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12023 op0
= XEXP (op0
, 0);
12024 code
= (code
== LT
? NE
: EQ
);
12028 /* If we have NEG of something whose two high-order bits are the
12029 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12030 if (num_sign_bit_copies (op0
, mode
) >= 2)
12032 op0
= XEXP (op0
, 0);
12033 code
= swap_condition (code
);
12039 /* If we are testing equality and our count is a constant, we
12040 can perform the inverse operation on our RHS. */
12041 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12042 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12043 op1
, XEXP (op0
, 1))) != 0)
12045 op0
= XEXP (op0
, 0);
12050 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12051 a particular bit. Convert it to an AND of a constant of that
12052 bit. This will be converted into a ZERO_EXTRACT. */
12053 if (const_op
== 0 && sign_bit_comparison_p
12054 && CONST_INT_P (XEXP (op0
, 1))
12055 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12057 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12060 - INTVAL (XEXP (op0
, 1)))));
12061 code
= (code
== LT
? NE
: EQ
);
12065 /* Fall through. */
12068 /* ABS is ignorable inside an equality comparison with zero. */
12069 if (const_op
== 0 && equality_comparison_p
)
12071 op0
= XEXP (op0
, 0);
12077 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12078 (compare FOO CONST) if CONST fits in FOO's mode and we
12079 are either testing inequality or have an unsigned
12080 comparison with ZERO_EXTEND or a signed comparison with
12081 SIGN_EXTEND. But don't do it if we don't have a compare
12082 insn of the given mode, since we'd have to revert it
12083 later on, and then we wouldn't know whether to sign- or
12085 mode
= GET_MODE (XEXP (op0
, 0));
12086 if (GET_MODE_CLASS (mode
) == MODE_INT
12087 && ! unsigned_comparison_p
12088 && HWI_COMPUTABLE_MODE_P (mode
)
12089 && trunc_int_for_mode (const_op
, mode
) == const_op
12090 && have_insn_for (COMPARE
, mode
))
12092 op0
= XEXP (op0
, 0);
12098 /* Check for the case where we are comparing A - C1 with C2, that is
12100 (subreg:MODE (plus (A) (-C1))) op (C2)
12102 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12103 comparison in the wider mode. One of the following two conditions
12104 must be true in order for this to be valid:
12106 1. The mode extension results in the same bit pattern being added
12107 on both sides and the comparison is equality or unsigned. As
12108 C2 has been truncated to fit in MODE, the pattern can only be
12111 2. The mode extension results in the sign bit being copied on
12114 The difficulty here is that we have predicates for A but not for
12115 (A - C1) so we need to check that C1 is within proper bounds so
12116 as to perturbate A as little as possible. */
12118 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12119 && subreg_lowpart_p (op0
)
12120 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
12121 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12122 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12124 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
12125 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12126 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12129 && (unsigned HOST_WIDE_INT
) c1
12130 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12131 && (equality_comparison_p
|| unsigned_comparison_p
)
12132 /* (A - C1) zero-extends if it is positive and sign-extends
12133 if it is negative, C2 both zero- and sign-extends. */
12134 && ((0 == (nonzero_bits (a
, inner_mode
)
12135 & ~GET_MODE_MASK (mode
))
12137 /* (A - C1) sign-extends if it is positive and 1-extends
12138 if it is negative, C2 both sign- and 1-extends. */
12139 || (num_sign_bit_copies (a
, inner_mode
)
12140 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12143 || ((unsigned HOST_WIDE_INT
) c1
12144 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12145 /* (A - C1) always sign-extends, like C2. */
12146 && num_sign_bit_copies (a
, inner_mode
)
12147 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12148 - (mode_width
- 1))))
12150 op0
= SUBREG_REG (op0
);
12155 /* If the inner mode is narrower and we are extracting the low part,
12156 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12157 if (subreg_lowpart_p (op0
)
12158 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
12160 else if (subreg_lowpart_p (op0
)
12161 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12162 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12163 && (code
== NE
|| code
== EQ
)
12164 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12165 <= HOST_BITS_PER_WIDE_INT
)
12166 && !paradoxical_subreg_p (op0
)
12167 && (nonzero_bits (SUBREG_REG (op0
),
12168 GET_MODE (SUBREG_REG (op0
)))
12169 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12171 /* Remove outer subregs that don't do anything. */
12172 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12174 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12175 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12177 op0
= SUBREG_REG (op0
);
12189 mode
= GET_MODE (XEXP (op0
, 0));
12190 if (GET_MODE_CLASS (mode
) == MODE_INT
12191 && (unsigned_comparison_p
|| equality_comparison_p
)
12192 && HWI_COMPUTABLE_MODE_P (mode
)
12193 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12195 && have_insn_for (COMPARE
, mode
))
12197 op0
= XEXP (op0
, 0);
12203 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12204 this for equality comparisons due to pathological cases involving
12206 if (equality_comparison_p
12207 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12208 op1
, XEXP (op0
, 1))))
12210 op0
= XEXP (op0
, 0);
12215 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12216 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12217 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12219 op0
= XEXP (XEXP (op0
, 0), 0);
12220 code
= (code
== LT
? EQ
: NE
);
12226 /* We used to optimize signed comparisons against zero, but that
12227 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12228 arrive here as equality comparisons, or (GEU, LTU) are
12229 optimized away. No need to special-case them. */
12231 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12232 (eq B (minus A C)), whichever simplifies. We can only do
12233 this for equality comparisons due to pathological cases involving
12235 if (equality_comparison_p
12236 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12237 XEXP (op0
, 1), op1
)))
12239 op0
= XEXP (op0
, 0);
12244 if (equality_comparison_p
12245 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12246 XEXP (op0
, 0), op1
)))
12248 op0
= XEXP (op0
, 1);
12253 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12254 of bits in X minus 1, is one iff X > 0. */
12255 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12256 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12257 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12258 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12260 op0
= XEXP (op0
, 1);
12261 code
= (code
== GE
? LE
: GT
);
12267 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12268 if C is zero or B is a constant. */
12269 if (equality_comparison_p
12270 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12271 XEXP (op0
, 1), op1
)))
12273 op0
= XEXP (op0
, 0);
12280 case UNEQ
: case LTGT
:
12281 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12282 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12283 case UNORDERED
: case ORDERED
:
12284 /* We can't do anything if OP0 is a condition code value, rather
12285 than an actual data value. */
12287 || CC0_P (XEXP (op0
, 0))
12288 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12291 /* Get the two operands being compared. */
12292 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12293 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12295 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12297 /* Check for the cases where we simply want the result of the
12298 earlier test or the opposite of that result. */
12299 if (code
== NE
|| code
== EQ
12300 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12301 && (code
== LT
|| code
== GE
)))
12303 enum rtx_code new_code
;
12304 if (code
== LT
|| code
== NE
)
12305 new_code
= GET_CODE (op0
);
12307 new_code
= reversed_comparison_code (op0
, NULL
);
12309 if (new_code
!= UNKNOWN
)
12320 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12322 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12323 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12324 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12326 op0
= XEXP (op0
, 1);
12327 code
= (code
== GE
? GT
: LE
);
12333 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12334 will be converted to a ZERO_EXTRACT later. */
12335 if (const_op
== 0 && equality_comparison_p
12336 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12337 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12339 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12340 XEXP (XEXP (op0
, 0), 1));
12341 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12345 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12346 zero and X is a comparison and C1 and C2 describe only bits set
12347 in STORE_FLAG_VALUE, we can compare with X. */
12348 if (const_op
== 0 && equality_comparison_p
12349 && mode_width
<= HOST_BITS_PER_WIDE_INT
12350 && CONST_INT_P (XEXP (op0
, 1))
12351 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12352 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12353 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12354 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12356 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12357 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12358 if ((~STORE_FLAG_VALUE
& mask
) == 0
12359 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12360 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12361 && COMPARISON_P (tem
))))
12363 op0
= XEXP (XEXP (op0
, 0), 0);
12368 /* If we are doing an equality comparison of an AND of a bit equal
12369 to the sign bit, replace this with a LT or GE comparison of
12370 the underlying value. */
12371 if (equality_comparison_p
12373 && CONST_INT_P (XEXP (op0
, 1))
12374 && mode_width
<= HOST_BITS_PER_WIDE_INT
12375 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12376 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12378 op0
= XEXP (op0
, 0);
12379 code
= (code
== EQ
? GE
: LT
);
12383 /* If this AND operation is really a ZERO_EXTEND from a narrower
12384 mode, the constant fits within that mode, and this is either an
12385 equality or unsigned comparison, try to do this comparison in
12390 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12391 -> (ne:DI (reg:SI 4) (const_int 0))
12393 unless TRULY_NOOP_TRUNCATION allows it or the register is
12394 known to hold a value of the required mode the
12395 transformation is invalid. */
12396 if ((equality_comparison_p
|| unsigned_comparison_p
)
12397 && CONST_INT_P (XEXP (op0
, 1))
12398 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12399 & GET_MODE_MASK (mode
))
12401 && const_op
>> i
== 0
12402 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12404 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12408 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12409 fits in both M1 and M2 and the SUBREG is either paradoxical
12410 or represents the low part, permute the SUBREG and the AND
12412 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12413 && CONST_INT_P (XEXP (op0
, 1)))
12415 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12416 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12417 /* Require an integral mode, to avoid creating something like
12419 if (SCALAR_INT_MODE_P (tmode
)
12420 /* It is unsafe to commute the AND into the SUBREG if the
12421 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12422 not defined. As originally written the upper bits
12423 have a defined value due to the AND operation.
12424 However, if we commute the AND inside the SUBREG then
12425 they no longer have defined values and the meaning of
12426 the code has been changed.
12427 Also C1 should not change value in the smaller mode,
12428 see PR67028 (a positive C1 can become negative in the
12429 smaller mode, so that the AND does no longer mask the
12431 && ((WORD_REGISTER_OPERATIONS
12432 && mode_width
> GET_MODE_PRECISION (tmode
)
12433 && mode_width
<= BITS_PER_WORD
12434 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12435 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12436 && subreg_lowpart_p (XEXP (op0
, 0))))
12437 && mode_width
<= HOST_BITS_PER_WIDE_INT
12438 && HWI_COMPUTABLE_MODE_P (tmode
)
12439 && (c1
& ~mask
) == 0
12440 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12442 && c1
!= GET_MODE_MASK (tmode
))
12444 op0
= simplify_gen_binary (AND
, tmode
,
12445 SUBREG_REG (XEXP (op0
, 0)),
12446 gen_int_mode (c1
, tmode
));
12447 op0
= gen_lowpart (mode
, op0
);
12452 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12453 if (const_op
== 0 && equality_comparison_p
12454 && XEXP (op0
, 1) == const1_rtx
12455 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12457 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12458 XEXP (XEXP (op0
, 0), 0), 1);
12459 code
= (code
== NE
? EQ
: NE
);
12463 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12464 (eq (and (lshiftrt X) 1) 0).
12465 Also handle the case where (not X) is expressed using xor. */
12466 if (const_op
== 0 && equality_comparison_p
12467 && XEXP (op0
, 1) == const1_rtx
12468 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12470 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12471 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12473 if (GET_CODE (shift_op
) == NOT
12474 || (GET_CODE (shift_op
) == XOR
12475 && CONST_INT_P (XEXP (shift_op
, 1))
12476 && CONST_INT_P (shift_count
)
12477 && HWI_COMPUTABLE_MODE_P (mode
)
12478 && (UINTVAL (XEXP (shift_op
, 1))
12479 == HOST_WIDE_INT_1U
12480 << INTVAL (shift_count
))))
12483 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12484 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12485 code
= (code
== NE
? EQ
: NE
);
12492 /* If we have (compare (ashift FOO N) (const_int C)) and
12493 the high order N bits of FOO (N+1 if an inequality comparison)
12494 are known to be zero, we can do this by comparing FOO with C
12495 shifted right N bits so long as the low-order N bits of C are
12497 if (CONST_INT_P (XEXP (op0
, 1))
12498 && INTVAL (XEXP (op0
, 1)) >= 0
12499 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12500 < HOST_BITS_PER_WIDE_INT
)
12501 && (((unsigned HOST_WIDE_INT
) const_op
12502 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12504 && mode_width
<= HOST_BITS_PER_WIDE_INT
12505 && (nonzero_bits (XEXP (op0
, 0), mode
)
12506 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12507 + ! equality_comparison_p
))) == 0)
12509 /* We must perform a logical shift, not an arithmetic one,
12510 as we want the top N bits of C to be zero. */
12511 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12513 temp
>>= INTVAL (XEXP (op0
, 1));
12514 op1
= gen_int_mode (temp
, mode
);
12515 op0
= XEXP (op0
, 0);
12519 /* If we are doing a sign bit comparison, it means we are testing
12520 a particular bit. Convert it to the appropriate AND. */
12521 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12522 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12524 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12527 - INTVAL (XEXP (op0
, 1)))));
12528 code
= (code
== LT
? NE
: EQ
);
12532 /* If this an equality comparison with zero and we are shifting
12533 the low bit to the sign bit, we can convert this to an AND of the
12535 if (const_op
== 0 && equality_comparison_p
12536 && CONST_INT_P (XEXP (op0
, 1))
12537 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12539 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12545 /* If this is an equality comparison with zero, we can do this
12546 as a logical shift, which might be much simpler. */
12547 if (equality_comparison_p
&& const_op
== 0
12548 && CONST_INT_P (XEXP (op0
, 1)))
12550 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12552 INTVAL (XEXP (op0
, 1)));
12556 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12557 do the comparison in a narrower mode. */
12558 if (! unsigned_comparison_p
12559 && CONST_INT_P (XEXP (op0
, 1))
12560 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12561 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12562 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12563 MODE_INT
, 1)) != BLKmode
12564 && (((unsigned HOST_WIDE_INT
) const_op
12565 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12566 <= GET_MODE_MASK (tmode
)))
12568 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12572 /* Likewise if OP0 is a PLUS of a sign extension with a
12573 constant, which is usually represented with the PLUS
12574 between the shifts. */
12575 if (! unsigned_comparison_p
12576 && CONST_INT_P (XEXP (op0
, 1))
12577 && GET_CODE (XEXP (op0
, 0)) == PLUS
12578 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12579 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12580 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12581 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12582 MODE_INT
, 1)) != BLKmode
12583 && (((unsigned HOST_WIDE_INT
) const_op
12584 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12585 <= GET_MODE_MASK (tmode
)))
12587 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12588 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12589 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12590 add_const
, XEXP (op0
, 1));
12592 op0
= simplify_gen_binary (PLUS
, tmode
,
12593 gen_lowpart (tmode
, inner
),
12600 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12601 the low order N bits of FOO are known to be zero, we can do this
12602 by comparing FOO with C shifted left N bits so long as no
12603 overflow occurs. Even if the low order N bits of FOO aren't known
12604 to be zero, if the comparison is >= or < we can use the same
12605 optimization and for > or <= by setting all the low
12606 order N bits in the comparison constant. */
12607 if (CONST_INT_P (XEXP (op0
, 1))
12608 && INTVAL (XEXP (op0
, 1)) > 0
12609 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12610 && mode_width
<= HOST_BITS_PER_WIDE_INT
12611 && (((unsigned HOST_WIDE_INT
) const_op
12612 + (GET_CODE (op0
) != LSHIFTRT
12613 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12616 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12618 unsigned HOST_WIDE_INT low_bits
12619 = (nonzero_bits (XEXP (op0
, 0), mode
)
12620 & ((HOST_WIDE_INT_1U
12621 << INTVAL (XEXP (op0
, 1))) - 1));
12622 if (low_bits
== 0 || !equality_comparison_p
)
12624 /* If the shift was logical, then we must make the condition
12626 if (GET_CODE (op0
) == LSHIFTRT
)
12627 code
= unsigned_condition (code
);
12629 const_op
= (unsigned HOST_WIDE_INT
) const_op
12630 << INTVAL (XEXP (op0
, 1));
12632 && (code
== GT
|| code
== GTU
12633 || code
== LE
|| code
== LEU
))
12635 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12636 op1
= GEN_INT (const_op
);
12637 op0
= XEXP (op0
, 0);
12642 /* If we are using this shift to extract just the sign bit, we
12643 can replace this with an LT or GE comparison. */
12645 && (equality_comparison_p
|| sign_bit_comparison_p
)
12646 && CONST_INT_P (XEXP (op0
, 1))
12647 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12649 op0
= XEXP (op0
, 0);
12650 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12662 /* Now make any compound operations involved in this comparison. Then,
12663 check for an outmost SUBREG on OP0 that is not doing anything or is
12664 paradoxical. The latter transformation must only be performed when
12665 it is known that the "extra" bits will be the same in op0 and op1 or
12666 that they don't matter. There are three cases to consider:
12668 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12669 care bits and we can assume they have any convenient value. So
12670 making the transformation is safe.
12672 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12673 In this case the upper bits of op0 are undefined. We should not make
12674 the simplification in that case as we do not know the contents of
12677 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12678 In that case we know those bits are zeros or ones. We must also be
12679 sure that they are the same as the upper bits of op1.
12681 We can never remove a SUBREG for a non-equality comparison because
12682 the sign bit is in a different place in the underlying object. */
12684 rtx_code op0_mco_code
= SET
;
12685 if (op1
== const0_rtx
)
12686 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12688 op0
= make_compound_operation (op0
, op0_mco_code
);
12689 op1
= make_compound_operation (op1
, SET
);
12691 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12692 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12693 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12694 && (code
== NE
|| code
== EQ
))
12696 if (paradoxical_subreg_p (op0
))
12698 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12700 if (REG_P (SUBREG_REG (op0
)))
12702 op0
= SUBREG_REG (op0
);
12703 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12706 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12707 <= HOST_BITS_PER_WIDE_INT
)
12708 && (nonzero_bits (SUBREG_REG (op0
),
12709 GET_MODE (SUBREG_REG (op0
)))
12710 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12712 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12714 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12715 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12716 op0
= SUBREG_REG (op0
), op1
= tem
;
12720 /* We now do the opposite procedure: Some machines don't have compare
12721 insns in all modes. If OP0's mode is an integer mode smaller than a
12722 word and we can't do a compare in that mode, see if there is a larger
12723 mode for which we can do the compare. There are a number of cases in
12724 which we can use the wider mode. */
12726 mode
= GET_MODE (op0
);
12727 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12728 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12729 && ! have_insn_for (COMPARE
, mode
))
12730 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12731 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12732 tmode
= GET_MODE_WIDER_MODE (tmode
))
12733 if (have_insn_for (COMPARE
, tmode
))
12737 /* If this is a test for negative, we can make an explicit
12738 test of the sign bit. Test this first so we can use
12739 a paradoxical subreg to extend OP0. */
12741 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12742 && HWI_COMPUTABLE_MODE_P (mode
))
12744 unsigned HOST_WIDE_INT sign
12745 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12746 op0
= simplify_gen_binary (AND
, tmode
,
12747 gen_lowpart (tmode
, op0
),
12748 gen_int_mode (sign
, tmode
));
12749 code
= (code
== LT
) ? NE
: EQ
;
12753 /* If the only nonzero bits in OP0 and OP1 are those in the
12754 narrower mode and this is an equality or unsigned comparison,
12755 we can use the wider mode. Similarly for sign-extended
12756 values, in which case it is true for all comparisons. */
12757 zero_extended
= ((code
== EQ
|| code
== NE
12758 || code
== GEU
|| code
== GTU
12759 || code
== LEU
|| code
== LTU
)
12760 && (nonzero_bits (op0
, tmode
)
12761 & ~GET_MODE_MASK (mode
)) == 0
12762 && ((CONST_INT_P (op1
)
12763 || (nonzero_bits (op1
, tmode
)
12764 & ~GET_MODE_MASK (mode
)) == 0)));
12767 || ((num_sign_bit_copies (op0
, tmode
)
12768 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12769 - GET_MODE_PRECISION (mode
)))
12770 && (num_sign_bit_copies (op1
, tmode
)
12771 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12772 - GET_MODE_PRECISION (mode
)))))
12774 /* If OP0 is an AND and we don't have an AND in MODE either,
12775 make a new AND in the proper mode. */
12776 if (GET_CODE (op0
) == AND
12777 && !have_insn_for (AND
, mode
))
12778 op0
= simplify_gen_binary (AND
, tmode
,
12779 gen_lowpart (tmode
,
12781 gen_lowpart (tmode
,
12787 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12788 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12792 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12793 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12800 /* We may have changed the comparison operands. Re-canonicalize. */
12801 if (swap_commutative_operands_p (op0
, op1
))
12803 std::swap (op0
, op1
);
12804 code
= swap_condition (code
);
12807 /* If this machine only supports a subset of valid comparisons, see if we
12808 can convert an unsupported one into a supported one. */
12809 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12817 /* Utility function for record_value_for_reg. Count number of
12822 enum rtx_code code
= GET_CODE (x
);
12826 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12827 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12829 rtx x0
= XEXP (x
, 0);
12830 rtx x1
= XEXP (x
, 1);
12833 return 1 + 2 * count_rtxs (x0
);
12835 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12836 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12837 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12838 return 2 + 2 * count_rtxs (x0
)
12839 + count_rtxs (x
== XEXP (x1
, 0)
12840 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12842 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12843 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12844 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12845 return 2 + 2 * count_rtxs (x1
)
12846 + count_rtxs (x
== XEXP (x0
, 0)
12847 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12850 fmt
= GET_RTX_FORMAT (code
);
12851 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12853 ret
+= count_rtxs (XEXP (x
, i
));
12854 else if (fmt
[i
] == 'E')
12855 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12856 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12861 /* Utility function for following routine. Called when X is part of a value
12862 being stored into last_set_value. Sets last_set_table_tick
12863 for each register mentioned. Similar to mention_regs in cse.c */
12866 update_table_tick (rtx x
)
12868 enum rtx_code code
= GET_CODE (x
);
12869 const char *fmt
= GET_RTX_FORMAT (code
);
12874 unsigned int regno
= REGNO (x
);
12875 unsigned int endregno
= END_REGNO (x
);
12878 for (r
= regno
; r
< endregno
; r
++)
12880 reg_stat_type
*rsp
= ®_stat
[r
];
12881 rsp
->last_set_table_tick
= label_tick
;
12887 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12890 /* Check for identical subexpressions. If x contains
12891 identical subexpression we only have to traverse one of
12893 if (i
== 0 && ARITHMETIC_P (x
))
12895 /* Note that at this point x1 has already been
12897 rtx x0
= XEXP (x
, 0);
12898 rtx x1
= XEXP (x
, 1);
12900 /* If x0 and x1 are identical then there is no need to
12905 /* If x0 is identical to a subexpression of x1 then while
12906 processing x1, x0 has already been processed. Thus we
12907 are done with x. */
12908 if (ARITHMETIC_P (x1
)
12909 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12912 /* If x1 is identical to a subexpression of x0 then we
12913 still have to process the rest of x0. */
12914 if (ARITHMETIC_P (x0
)
12915 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12917 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12922 update_table_tick (XEXP (x
, i
));
12924 else if (fmt
[i
] == 'E')
12925 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12926 update_table_tick (XVECEXP (x
, i
, j
));
12929 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12930 are saying that the register is clobbered and we no longer know its
12931 value. If INSN is zero, don't update reg_stat[].last_set; this is
12932 only permitted with VALUE also zero and is used to invalidate the
12936 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12938 unsigned int regno
= REGNO (reg
);
12939 unsigned int endregno
= END_REGNO (reg
);
12941 reg_stat_type
*rsp
;
12943 /* If VALUE contains REG and we have a previous value for REG, substitute
12944 the previous value. */
12945 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12949 /* Set things up so get_last_value is allowed to see anything set up to
12951 subst_low_luid
= DF_INSN_LUID (insn
);
12952 tem
= get_last_value (reg
);
12954 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12955 it isn't going to be useful and will take a lot of time to process,
12956 so just use the CLOBBER. */
12960 if (ARITHMETIC_P (tem
)
12961 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12962 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12963 tem
= XEXP (tem
, 0);
12964 else if (count_occurrences (value
, reg
, 1) >= 2)
12966 /* If there are two or more occurrences of REG in VALUE,
12967 prevent the value from growing too much. */
12968 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12969 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12972 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12976 /* For each register modified, show we don't know its value, that
12977 we don't know about its bitwise content, that its value has been
12978 updated, and that we don't know the location of the death of the
12980 for (i
= regno
; i
< endregno
; i
++)
12982 rsp
= ®_stat
[i
];
12985 rsp
->last_set
= insn
;
12987 rsp
->last_set_value
= 0;
12988 rsp
->last_set_mode
= VOIDmode
;
12989 rsp
->last_set_nonzero_bits
= 0;
12990 rsp
->last_set_sign_bit_copies
= 0;
12991 rsp
->last_death
= 0;
12992 rsp
->truncated_to_mode
= VOIDmode
;
12995 /* Mark registers that are being referenced in this value. */
12997 update_table_tick (value
);
12999 /* Now update the status of each register being set.
13000 If someone is using this register in this block, set this register
13001 to invalid since we will get confused between the two lives in this
13002 basic block. This makes using this register always invalid. In cse, we
13003 scan the table to invalidate all entries using this register, but this
13004 is too much work for us. */
13006 for (i
= regno
; i
< endregno
; i
++)
13008 rsp
= ®_stat
[i
];
13009 rsp
->last_set_label
= label_tick
;
13011 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13012 rsp
->last_set_invalid
= 1;
13014 rsp
->last_set_invalid
= 0;
13017 /* The value being assigned might refer to X (like in "x++;"). In that
13018 case, we must replace it with (clobber (const_int 0)) to prevent
13020 rsp
= ®_stat
[regno
];
13021 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13023 value
= copy_rtx (value
);
13024 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13028 /* For the main register being modified, update the value, the mode, the
13029 nonzero bits, and the number of sign bit copies. */
13031 rsp
->last_set_value
= value
;
13035 machine_mode mode
= GET_MODE (reg
);
13036 subst_low_luid
= DF_INSN_LUID (insn
);
13037 rsp
->last_set_mode
= mode
;
13038 if (GET_MODE_CLASS (mode
) == MODE_INT
13039 && HWI_COMPUTABLE_MODE_P (mode
))
13040 mode
= nonzero_bits_mode
;
13041 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13042 rsp
->last_set_sign_bit_copies
13043 = num_sign_bit_copies (value
, GET_MODE (reg
));
13047 /* Called via note_stores from record_dead_and_set_regs to handle one
13048 SET or CLOBBER in an insn. DATA is the instruction in which the
13049 set is occurring. */
13052 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13054 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13056 if (GET_CODE (dest
) == SUBREG
)
13057 dest
= SUBREG_REG (dest
);
13059 if (!record_dead_insn
)
13062 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13068 /* If we are setting the whole register, we know its value. Otherwise
13069 show that we don't know the value. We can handle SUBREG in
13071 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13072 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13073 else if (GET_CODE (setter
) == SET
13074 && GET_CODE (SET_DEST (setter
)) == SUBREG
13075 && SUBREG_REG (SET_DEST (setter
)) == dest
13076 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13077 && subreg_lowpart_p (SET_DEST (setter
)))
13078 record_value_for_reg (dest
, record_dead_insn
,
13079 gen_lowpart (GET_MODE (dest
),
13080 SET_SRC (setter
)));
13082 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13084 else if (MEM_P (dest
)
13085 /* Ignore pushes, they clobber nothing. */
13086 && ! push_operand (dest
, GET_MODE (dest
)))
13087 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13090 /* Update the records of when each REG was most recently set or killed
13091 for the things done by INSN. This is the last thing done in processing
13092 INSN in the combiner loop.
13094 We update reg_stat[], in particular fields last_set, last_set_value,
13095 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13096 last_death, and also the similar information mem_last_set (which insn
13097 most recently modified memory) and last_call_luid (which insn was the
13098 most recent subroutine call). */
13101 record_dead_and_set_regs (rtx_insn
*insn
)
13106 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13108 if (REG_NOTE_KIND (link
) == REG_DEAD
13109 && REG_P (XEXP (link
, 0)))
13111 unsigned int regno
= REGNO (XEXP (link
, 0));
13112 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13114 for (i
= regno
; i
< endregno
; i
++)
13116 reg_stat_type
*rsp
;
13118 rsp
= ®_stat
[i
];
13119 rsp
->last_death
= insn
;
13122 else if (REG_NOTE_KIND (link
) == REG_INC
)
13123 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13128 hard_reg_set_iterator hrsi
;
13129 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13131 reg_stat_type
*rsp
;
13133 rsp
= ®_stat
[i
];
13134 rsp
->last_set_invalid
= 1;
13135 rsp
->last_set
= insn
;
13136 rsp
->last_set_value
= 0;
13137 rsp
->last_set_mode
= VOIDmode
;
13138 rsp
->last_set_nonzero_bits
= 0;
13139 rsp
->last_set_sign_bit_copies
= 0;
13140 rsp
->last_death
= 0;
13141 rsp
->truncated_to_mode
= VOIDmode
;
13144 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13146 /* We can't combine into a call pattern. Remember, though, that
13147 the return value register is set at this LUID. We could
13148 still replace a register with the return value from the
13149 wrong subroutine call! */
13150 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13153 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13156 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13157 register present in the SUBREG, so for each such SUBREG go back and
13158 adjust nonzero and sign bit information of the registers that are
13159 known to have some zero/sign bits set.
13161 This is needed because when combine blows the SUBREGs away, the
13162 information on zero/sign bits is lost and further combines can be
13163 missed because of that. */
13166 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13168 struct insn_link
*links
;
13170 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13171 machine_mode mode
= GET_MODE (subreg
);
13173 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
13176 for (links
= LOG_LINKS (insn
); links
;)
13178 reg_stat_type
*rsp
;
13180 insn
= links
->insn
;
13181 set
= single_set (insn
);
13183 if (! set
|| !REG_P (SET_DEST (set
))
13184 || REGNO (SET_DEST (set
)) != regno
13185 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13187 links
= links
->next
;
13191 rsp
= ®_stat
[regno
];
13192 if (rsp
->last_set
== insn
)
13194 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13195 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13198 if (REG_P (SET_SRC (set
)))
13200 regno
= REGNO (SET_SRC (set
));
13201 links
= LOG_LINKS (insn
);
13208 /* Check if X, a register, is known to contain a value already
13209 truncated to MODE. In this case we can use a subreg to refer to
13210 the truncated value even though in the generic case we would need
13211 an explicit truncation. */
13214 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13216 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13217 machine_mode truncated
= rsp
->truncated_to_mode
;
13220 || rsp
->truncation_label
< label_tick_ebb_start
)
13222 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
13224 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13229 /* If X is a hard reg or a subreg record the mode that the register is
13230 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13231 to turn a truncate into a subreg using this information. Return true
13232 if traversing X is complete. */
13235 record_truncated_value (rtx x
)
13237 machine_mode truncated_mode
;
13238 reg_stat_type
*rsp
;
13240 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13242 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13243 truncated_mode
= GET_MODE (x
);
13245 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
13248 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13251 x
= SUBREG_REG (x
);
13253 /* ??? For hard-regs we now record everything. We might be able to
13254 optimize this using last_set_mode. */
13255 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13256 truncated_mode
= GET_MODE (x
);
13260 rsp
= ®_stat
[REGNO (x
)];
13261 if (rsp
->truncated_to_mode
== 0
13262 || rsp
->truncation_label
< label_tick_ebb_start
13263 || (GET_MODE_SIZE (truncated_mode
)
13264 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13266 rsp
->truncated_to_mode
= truncated_mode
;
13267 rsp
->truncation_label
= label_tick
;
13273 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13274 the modes they are used in. This can help truning TRUNCATEs into
13278 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13280 subrtx_var_iterator::array_type array
;
13281 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13282 if (record_truncated_value (*iter
))
13283 iter
.skip_subrtxes ();
13286 /* Scan X for promoted SUBREGs. For each one found,
13287 note what it implies to the registers used in it. */
13290 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13292 if (GET_CODE (x
) == SUBREG
13293 && SUBREG_PROMOTED_VAR_P (x
)
13294 && REG_P (SUBREG_REG (x
)))
13295 record_promoted_value (insn
, x
);
13298 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13301 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13305 check_promoted_subreg (insn
, XEXP (x
, i
));
13309 if (XVEC (x
, i
) != 0)
13310 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13311 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13317 /* Verify that all the registers and memory references mentioned in *LOC are
13318 still valid. *LOC was part of a value set in INSN when label_tick was
13319 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13320 the invalid references with (clobber (const_int 0)) and return 1. This
13321 replacement is useful because we often can get useful information about
13322 the form of a value (e.g., if it was produced by a shift that always
13323 produces -1 or 0) even though we don't know exactly what registers it
13324 was produced from. */
13327 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13330 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13331 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13336 unsigned int regno
= REGNO (x
);
13337 unsigned int endregno
= END_REGNO (x
);
13340 for (j
= regno
; j
< endregno
; j
++)
13342 reg_stat_type
*rsp
= ®_stat
[j
];
13343 if (rsp
->last_set_invalid
13344 /* If this is a pseudo-register that was only set once and not
13345 live at the beginning of the function, it is always valid. */
13346 || (! (regno
>= FIRST_PSEUDO_REGISTER
13347 && regno
< reg_n_sets_max
13348 && REG_N_SETS (regno
) == 1
13349 && (!REGNO_REG_SET_P
13350 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13352 && rsp
->last_set_label
> tick
))
13355 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13362 /* If this is a memory reference, make sure that there were no stores after
13363 it that might have clobbered the value. We don't have alias info, so we
13364 assume any store invalidates it. Moreover, we only have local UIDs, so
13365 we also assume that there were stores in the intervening basic blocks. */
13366 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13367 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13370 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13374 for (i
= 0; i
< len
; i
++)
13378 /* Check for identical subexpressions. If x contains
13379 identical subexpression we only have to traverse one of
13381 if (i
== 1 && ARITHMETIC_P (x
))
13383 /* Note that at this point x0 has already been checked
13384 and found valid. */
13385 rtx x0
= XEXP (x
, 0);
13386 rtx x1
= XEXP (x
, 1);
13388 /* If x0 and x1 are identical then x is also valid. */
13392 /* If x1 is identical to a subexpression of x0 then
13393 while checking x0, x1 has already been checked. Thus
13394 it is valid and so as x. */
13395 if (ARITHMETIC_P (x0
)
13396 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13399 /* If x0 is identical to a subexpression of x1 then x is
13400 valid iff the rest of x1 is valid. */
13401 if (ARITHMETIC_P (x1
)
13402 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13404 get_last_value_validate (&XEXP (x1
,
13405 x0
== XEXP (x1
, 0) ? 1 : 0),
13406 insn
, tick
, replace
);
13409 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13413 else if (fmt
[i
] == 'E')
13414 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13415 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13416 insn
, tick
, replace
) == 0)
13420 /* If we haven't found a reason for it to be invalid, it is valid. */
13424 /* Get the last value assigned to X, if known. Some registers
13425 in the value may be replaced with (clobber (const_int 0)) if their value
13426 is known longer known reliably. */
13429 get_last_value (const_rtx x
)
13431 unsigned int regno
;
13433 reg_stat_type
*rsp
;
13435 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13436 then convert it to the desired mode. If this is a paradoxical SUBREG,
13437 we cannot predict what values the "extra" bits might have. */
13438 if (GET_CODE (x
) == SUBREG
13439 && subreg_lowpart_p (x
)
13440 && !paradoxical_subreg_p (x
)
13441 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13442 return gen_lowpart (GET_MODE (x
), value
);
13448 rsp
= ®_stat
[regno
];
13449 value
= rsp
->last_set_value
;
13451 /* If we don't have a value, or if it isn't for this basic block and
13452 it's either a hard register, set more than once, or it's a live
13453 at the beginning of the function, return 0.
13455 Because if it's not live at the beginning of the function then the reg
13456 is always set before being used (is never used without being set).
13457 And, if it's set only once, and it's always set before use, then all
13458 uses must have the same last value, even if it's not from this basic
13462 || (rsp
->last_set_label
< label_tick_ebb_start
13463 && (regno
< FIRST_PSEUDO_REGISTER
13464 || regno
>= reg_n_sets_max
13465 || REG_N_SETS (regno
) != 1
13467 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13470 /* If the value was set in a later insn than the ones we are processing,
13471 we can't use it even if the register was only set once. */
13472 if (rsp
->last_set_label
== label_tick
13473 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13476 /* If fewer bits were set than what we are asked for now, we cannot use
13478 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13479 < GET_MODE_PRECISION (GET_MODE (x
)))
13482 /* If the value has all its registers valid, return it. */
13483 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13486 /* Otherwise, make a copy and replace any invalid register with
13487 (clobber (const_int 0)). If that fails for some reason, return 0. */
13489 value
= copy_rtx (value
);
13490 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13496 /* Return nonzero if expression X refers to a REG or to memory
13497 that is set in an instruction more recent than FROM_LUID. */
13500 use_crosses_set_p (const_rtx x
, int from_luid
)
13504 enum rtx_code code
= GET_CODE (x
);
13508 unsigned int regno
= REGNO (x
);
13509 unsigned endreg
= END_REGNO (x
);
13511 #ifdef PUSH_ROUNDING
13512 /* Don't allow uses of the stack pointer to be moved,
13513 because we don't know whether the move crosses a push insn. */
13514 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13517 for (; regno
< endreg
; regno
++)
13519 reg_stat_type
*rsp
= ®_stat
[regno
];
13521 && rsp
->last_set_label
== label_tick
13522 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13528 if (code
== MEM
&& mem_last_set
> from_luid
)
13531 fmt
= GET_RTX_FORMAT (code
);
13533 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13538 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13539 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13542 else if (fmt
[i
] == 'e'
13543 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13549 /* Define three variables used for communication between the following
13552 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13553 static int reg_dead_flag
;
13555 /* Function called via note_stores from reg_dead_at_p.
13557 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13558 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13561 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13563 unsigned int regno
, endregno
;
13568 regno
= REGNO (dest
);
13569 endregno
= END_REGNO (dest
);
13570 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13571 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13574 /* Return nonzero if REG is known to be dead at INSN.
13576 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13577 referencing REG, it is dead. If we hit a SET referencing REG, it is
13578 live. Otherwise, see if it is live or dead at the start of the basic
13579 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13580 must be assumed to be always live. */
13583 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13588 /* Set variables for reg_dead_at_p_1. */
13589 reg_dead_regno
= REGNO (reg
);
13590 reg_dead_endregno
= END_REGNO (reg
);
13594 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13595 we allow the machine description to decide whether use-and-clobber
13596 patterns are OK. */
13597 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13599 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13600 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13604 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13605 beginning of basic block. */
13606 block
= BLOCK_FOR_INSN (insn
);
13611 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13614 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13616 return reg_dead_flag
== 1 ? 1 : 0;
13618 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13622 if (insn
== BB_HEAD (block
))
13625 insn
= PREV_INSN (insn
);
13628 /* Look at live-in sets for the basic block that we were in. */
13629 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13630 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13636 /* Note hard registers in X that are used. */
13639 mark_used_regs_combine (rtx x
)
13641 RTX_CODE code
= GET_CODE (x
);
13642 unsigned int regno
;
13653 case ADDR_DIFF_VEC
:
13655 /* CC0 must die in the insn after it is set, so we don't need to take
13656 special note of it here. */
13661 /* If we are clobbering a MEM, mark any hard registers inside the
13662 address as used. */
13663 if (MEM_P (XEXP (x
, 0)))
13664 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13669 /* A hard reg in a wide mode may really be multiple registers.
13670 If so, mark all of them just like the first. */
13671 if (regno
< FIRST_PSEUDO_REGISTER
)
13673 /* None of this applies to the stack, frame or arg pointers. */
13674 if (regno
== STACK_POINTER_REGNUM
13675 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13676 && regno
== HARD_FRAME_POINTER_REGNUM
)
13677 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13678 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13679 || regno
== FRAME_POINTER_REGNUM
)
13682 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13688 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13690 rtx testreg
= SET_DEST (x
);
13692 while (GET_CODE (testreg
) == SUBREG
13693 || GET_CODE (testreg
) == ZERO_EXTRACT
13694 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13695 testreg
= XEXP (testreg
, 0);
13697 if (MEM_P (testreg
))
13698 mark_used_regs_combine (XEXP (testreg
, 0));
13700 mark_used_regs_combine (SET_SRC (x
));
13708 /* Recursively scan the operands of this expression. */
13711 const char *fmt
= GET_RTX_FORMAT (code
);
13713 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13716 mark_used_regs_combine (XEXP (x
, i
));
13717 else if (fmt
[i
] == 'E')
13721 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13722 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13728 /* Remove register number REGNO from the dead registers list of INSN.
13730 Return the note used to record the death, if there was one. */
13733 remove_death (unsigned int regno
, rtx_insn
*insn
)
13735 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13738 remove_note (insn
, note
);
13743 /* For each register (hardware or pseudo) used within expression X, if its
13744 death is in an instruction with luid between FROM_LUID (inclusive) and
13745 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13746 list headed by PNOTES.
13748 That said, don't move registers killed by maybe_kill_insn.
13750 This is done when X is being merged by combination into TO_INSN. These
13751 notes will then be distributed as needed. */
13754 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13759 enum rtx_code code
= GET_CODE (x
);
13763 unsigned int regno
= REGNO (x
);
13764 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13766 /* Don't move the register if it gets killed in between from and to. */
13767 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13768 && ! reg_referenced_p (x
, maybe_kill_insn
))
13772 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13773 && DF_INSN_LUID (where_dead
) >= from_luid
13774 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13776 rtx note
= remove_death (regno
, where_dead
);
13778 /* It is possible for the call above to return 0. This can occur
13779 when last_death points to I2 or I1 that we combined with.
13780 In that case make a new note.
13782 We must also check for the case where X is a hard register
13783 and NOTE is a death note for a range of hard registers
13784 including X. In that case, we must put REG_DEAD notes for
13785 the remaining registers in place of NOTE. */
13787 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13788 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13789 > GET_MODE_SIZE (GET_MODE (x
))))
13791 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13792 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13793 unsigned int ourend
= END_REGNO (x
);
13796 for (i
= deadregno
; i
< deadend
; i
++)
13797 if (i
< regno
|| i
>= ourend
)
13798 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13801 /* If we didn't find any note, or if we found a REG_DEAD note that
13802 covers only part of the given reg, and we have a multi-reg hard
13803 register, then to be safe we must check for REG_DEAD notes
13804 for each register other than the first. They could have
13805 their own REG_DEAD notes lying around. */
13806 else if ((note
== 0
13808 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13809 < GET_MODE_SIZE (GET_MODE (x
)))))
13810 && regno
< FIRST_PSEUDO_REGISTER
13811 && REG_NREGS (x
) > 1)
13813 unsigned int ourend
= END_REGNO (x
);
13814 unsigned int i
, offset
;
13818 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13822 for (i
= regno
+ offset
; i
< ourend
; i
++)
13823 move_deaths (regno_reg_rtx
[i
],
13824 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13827 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13829 XEXP (note
, 1) = *pnotes
;
13833 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13839 else if (GET_CODE (x
) == SET
)
13841 rtx dest
= SET_DEST (x
);
13843 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13845 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13846 that accesses one word of a multi-word item, some
13847 piece of everything register in the expression is used by
13848 this insn, so remove any old death. */
13849 /* ??? So why do we test for equality of the sizes? */
13851 if (GET_CODE (dest
) == ZERO_EXTRACT
13852 || GET_CODE (dest
) == STRICT_LOW_PART
13853 || (GET_CODE (dest
) == SUBREG
13854 && (((GET_MODE_SIZE (GET_MODE (dest
))
13855 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13856 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13857 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13859 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13863 /* If this is some other SUBREG, we know it replaces the entire
13864 value, so use that as the destination. */
13865 if (GET_CODE (dest
) == SUBREG
)
13866 dest
= SUBREG_REG (dest
);
13868 /* If this is a MEM, adjust deaths of anything used in the address.
13869 For a REG (the only other possibility), the entire value is
13870 being replaced so the old value is not used in this insn. */
13873 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13878 else if (GET_CODE (x
) == CLOBBER
)
13881 len
= GET_RTX_LENGTH (code
);
13882 fmt
= GET_RTX_FORMAT (code
);
13884 for (i
= 0; i
< len
; i
++)
13889 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13890 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13893 else if (fmt
[i
] == 'e')
13894 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13898 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13899 pattern of an insn. X must be a REG. */
13902 reg_bitfield_target_p (rtx x
, rtx body
)
13906 if (GET_CODE (body
) == SET
)
13908 rtx dest
= SET_DEST (body
);
13910 unsigned int regno
, tregno
, endregno
, endtregno
;
13912 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13913 target
= XEXP (dest
, 0);
13914 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13915 target
= SUBREG_REG (XEXP (dest
, 0));
13919 if (GET_CODE (target
) == SUBREG
)
13920 target
= SUBREG_REG (target
);
13922 if (!REG_P (target
))
13925 tregno
= REGNO (target
), regno
= REGNO (x
);
13926 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13927 return target
== x
;
13929 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13930 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13932 return endregno
> tregno
&& regno
< endtregno
;
13935 else if (GET_CODE (body
) == PARALLEL
)
13936 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13937 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13943 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13944 as appropriate. I3 and I2 are the insns resulting from the combination
13945 insns including FROM (I2 may be zero).
13947 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13948 not need REG_DEAD notes because they are being substituted for. This
13949 saves searching in the most common cases.
13951 Each note in the list is either ignored or placed on some insns, depending
13952 on the type of note. */
13955 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13956 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13958 rtx note
, next_note
;
13960 rtx_insn
*tem_insn
;
13962 for (note
= notes
; note
; note
= next_note
)
13964 rtx_insn
*place
= 0, *place2
= 0;
13966 next_note
= XEXP (note
, 1);
13967 switch (REG_NOTE_KIND (note
))
13971 /* Doesn't matter much where we put this, as long as it's somewhere.
13972 It is preferable to keep these notes on branches, which is most
13973 likely to be i3. */
13977 case REG_NON_LOCAL_GOTO
:
13982 gcc_assert (i2
&& JUMP_P (i2
));
13987 case REG_EH_REGION
:
13988 /* These notes must remain with the call or trapping instruction. */
13991 else if (i2
&& CALL_P (i2
))
13995 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13996 if (may_trap_p (i3
))
13998 else if (i2
&& may_trap_p (i2
))
14000 /* ??? Otherwise assume we've combined things such that we
14001 can now prove that the instructions can't trap. Drop the
14002 note in this case. */
14006 case REG_ARGS_SIZE
:
14007 /* ??? How to distribute between i3-i1. Assume i3 contains the
14008 entire adjustment. Assert i3 contains at least some adjust. */
14009 if (!noop_move_p (i3
))
14011 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
14012 /* fixup_args_size_notes looks at REG_NORETURN note,
14013 so ensure the note is placed there first. */
14017 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14018 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14022 XEXP (n
, 1) = REG_NOTES (i3
);
14023 REG_NOTES (i3
) = n
;
14027 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14028 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14029 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14030 gcc_assert (old_size
!= args_size
14032 && !ACCUMULATE_OUTGOING_ARGS
14033 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14040 case REG_CALL_DECL
:
14041 /* These notes must remain with the call. It should not be
14042 possible for both I2 and I3 to be a call. */
14047 gcc_assert (i2
&& CALL_P (i2
));
14053 /* Any clobbers for i3 may still exist, and so we must process
14054 REG_UNUSED notes from that insn.
14056 Any clobbers from i2 or i1 can only exist if they were added by
14057 recog_for_combine. In that case, recog_for_combine created the
14058 necessary REG_UNUSED notes. Trying to keep any original
14059 REG_UNUSED notes from these insns can cause incorrect output
14060 if it is for the same register as the original i3 dest.
14061 In that case, we will notice that the register is set in i3,
14062 and then add a REG_UNUSED note for the destination of i3, which
14063 is wrong. However, it is possible to have REG_UNUSED notes from
14064 i2 or i1 for register which were both used and clobbered, so
14065 we keep notes from i2 or i1 if they will turn into REG_DEAD
14068 /* If this register is set or clobbered in I3, put the note there
14069 unless there is one already. */
14070 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14072 if (from_insn
!= i3
)
14075 if (! (REG_P (XEXP (note
, 0))
14076 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14077 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14080 /* Otherwise, if this register is used by I3, then this register
14081 now dies here, so we must put a REG_DEAD note here unless there
14083 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14084 && ! (REG_P (XEXP (note
, 0))
14085 ? find_regno_note (i3
, REG_DEAD
,
14086 REGNO (XEXP (note
, 0)))
14087 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14089 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14097 /* These notes say something about results of an insn. We can
14098 only support them if they used to be on I3 in which case they
14099 remain on I3. Otherwise they are ignored.
14101 If the note refers to an expression that is not a constant, we
14102 must also ignore the note since we cannot tell whether the
14103 equivalence is still true. It might be possible to do
14104 slightly better than this (we only have a problem if I2DEST
14105 or I1DEST is present in the expression), but it doesn't
14106 seem worth the trouble. */
14108 if (from_insn
== i3
14109 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14114 /* These notes say something about how a register is used. They must
14115 be present on any use of the register in I2 or I3. */
14116 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14119 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14128 case REG_LABEL_TARGET
:
14129 case REG_LABEL_OPERAND
:
14130 /* This can show up in several ways -- either directly in the
14131 pattern, or hidden off in the constant pool with (or without?)
14132 a REG_EQUAL note. */
14133 /* ??? Ignore the without-reg_equal-note problem for now. */
14134 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14135 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14136 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14137 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14141 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14142 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14143 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14144 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14152 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14153 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14155 if (place
&& JUMP_P (place
)
14156 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14157 && (JUMP_LABEL (place
) == NULL
14158 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14160 rtx label
= JUMP_LABEL (place
);
14163 JUMP_LABEL (place
) = XEXP (note
, 0);
14164 else if (LABEL_P (label
))
14165 LABEL_NUSES (label
)--;
14168 if (place2
&& JUMP_P (place2
)
14169 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14170 && (JUMP_LABEL (place2
) == NULL
14171 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14173 rtx label
= JUMP_LABEL (place2
);
14176 JUMP_LABEL (place2
) = XEXP (note
, 0);
14177 else if (LABEL_P (label
))
14178 LABEL_NUSES (label
)--;
14184 /* This note says something about the value of a register prior
14185 to the execution of an insn. It is too much trouble to see
14186 if the note is still correct in all situations. It is better
14187 to simply delete it. */
14191 /* If we replaced the right hand side of FROM_INSN with a
14192 REG_EQUAL note, the original use of the dying register
14193 will not have been combined into I3 and I2. In such cases,
14194 FROM_INSN is guaranteed to be the first of the combined
14195 instructions, so we simply need to search back before
14196 FROM_INSN for the previous use or set of this register,
14197 then alter the notes there appropriately.
14199 If the register is used as an input in I3, it dies there.
14200 Similarly for I2, if it is nonzero and adjacent to I3.
14202 If the register is not used as an input in either I3 or I2
14203 and it is not one of the registers we were supposed to eliminate,
14204 there are two possibilities. We might have a non-adjacent I2
14205 or we might have somehow eliminated an additional register
14206 from a computation. For example, we might have had A & B where
14207 we discover that B will always be zero. In this case we will
14208 eliminate the reference to A.
14210 In both cases, we must search to see if we can find a previous
14211 use of A and put the death note there. */
14214 && from_insn
== i2mod
14215 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14216 tem_insn
= from_insn
;
14220 && CALL_P (from_insn
)
14221 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14223 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14225 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14226 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14228 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14230 && reg_overlap_mentioned_p (XEXP (note
, 0),
14232 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14233 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14236 /* If the new I2 sets the same register that is marked dead
14237 in the note, we do not know where to put the note.
14239 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14245 basic_block bb
= this_basic_block
;
14247 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14249 if (!NONDEBUG_INSN_P (tem_insn
))
14251 if (tem_insn
== BB_HEAD (bb
))
14256 /* If the register is being set at TEM_INSN, see if that is all
14257 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14258 into a REG_UNUSED note instead. Don't delete sets to
14259 global register vars. */
14260 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14261 || !global_regs
[REGNO (XEXP (note
, 0))])
14262 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14264 rtx set
= single_set (tem_insn
);
14265 rtx inner_dest
= 0;
14266 rtx_insn
*cc0_setter
= NULL
;
14269 for (inner_dest
= SET_DEST (set
);
14270 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14271 || GET_CODE (inner_dest
) == SUBREG
14272 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14273 inner_dest
= XEXP (inner_dest
, 0))
14276 /* Verify that it was the set, and not a clobber that
14277 modified the register.
14279 CC0 targets must be careful to maintain setter/user
14280 pairs. If we cannot delete the setter due to side
14281 effects, mark the user with an UNUSED note instead
14284 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14285 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14287 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14288 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14289 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14291 /* Move the notes and links of TEM_INSN elsewhere.
14292 This might delete other dead insns recursively.
14293 First set the pattern to something that won't use
14295 rtx old_notes
= REG_NOTES (tem_insn
);
14297 PATTERN (tem_insn
) = pc_rtx
;
14298 REG_NOTES (tem_insn
) = NULL
;
14300 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14301 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14302 distribute_links (LOG_LINKS (tem_insn
));
14304 unsigned int regno
= REGNO (XEXP (note
, 0));
14305 reg_stat_type
*rsp
= ®_stat
[regno
];
14306 if (rsp
->last_set
== tem_insn
)
14307 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14309 SET_INSN_DELETED (tem_insn
);
14310 if (tem_insn
== i2
)
14313 /* Delete the setter too. */
14316 PATTERN (cc0_setter
) = pc_rtx
;
14317 old_notes
= REG_NOTES (cc0_setter
);
14318 REG_NOTES (cc0_setter
) = NULL
;
14320 distribute_notes (old_notes
, cc0_setter
,
14322 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14323 distribute_links (LOG_LINKS (cc0_setter
));
14325 SET_INSN_DELETED (cc0_setter
);
14326 if (cc0_setter
== i2
)
14332 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14334 /* If there isn't already a REG_UNUSED note, put one
14335 here. Do not place a REG_DEAD note, even if
14336 the register is also used here; that would not
14337 match the algorithm used in lifetime analysis
14338 and can cause the consistency check in the
14339 scheduler to fail. */
14340 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14341 REGNO (XEXP (note
, 0))))
14346 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14347 || (CALL_P (tem_insn
)
14348 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14352 /* If we are doing a 3->2 combination, and we have a
14353 register which formerly died in i3 and was not used
14354 by i2, which now no longer dies in i3 and is used in
14355 i2 but does not die in i2, and place is between i2
14356 and i3, then we may need to move a link from place to
14358 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14360 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14361 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14363 struct insn_link
*links
= LOG_LINKS (place
);
14364 LOG_LINKS (place
) = NULL
;
14365 distribute_links (links
);
14370 if (tem_insn
== BB_HEAD (bb
))
14376 /* If the register is set or already dead at PLACE, we needn't do
14377 anything with this note if it is still a REG_DEAD note.
14378 We check here if it is set at all, not if is it totally replaced,
14379 which is what `dead_or_set_p' checks, so also check for it being
14382 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14384 unsigned int regno
= REGNO (XEXP (note
, 0));
14385 reg_stat_type
*rsp
= ®_stat
[regno
];
14387 if (dead_or_set_p (place
, XEXP (note
, 0))
14388 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14390 /* Unless the register previously died in PLACE, clear
14391 last_death. [I no longer understand why this is
14393 if (rsp
->last_death
!= place
)
14394 rsp
->last_death
= 0;
14398 rsp
->last_death
= place
;
14400 /* If this is a death note for a hard reg that is occupying
14401 multiple registers, ensure that we are still using all
14402 parts of the object. If we find a piece of the object
14403 that is unused, we must arrange for an appropriate REG_DEAD
14404 note to be added for it. However, we can't just emit a USE
14405 and tag the note to it, since the register might actually
14406 be dead; so we recourse, and the recursive call then finds
14407 the previous insn that used this register. */
14409 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14411 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14412 bool all_used
= true;
14415 for (i
= regno
; i
< endregno
; i
++)
14416 if ((! refers_to_regno_p (i
, PATTERN (place
))
14417 && ! find_regno_fusage (place
, USE
, i
))
14418 || dead_or_set_regno_p (place
, i
))
14426 /* Put only REG_DEAD notes for pieces that are
14427 not already dead or set. */
14429 for (i
= regno
; i
< endregno
;
14430 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14432 rtx piece
= regno_reg_rtx
[i
];
14433 basic_block bb
= this_basic_block
;
14435 if (! dead_or_set_p (place
, piece
)
14436 && ! reg_bitfield_target_p (piece
,
14439 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14442 distribute_notes (new_note
, place
, place
,
14443 NULL
, NULL_RTX
, NULL_RTX
,
14446 else if (! refers_to_regno_p (i
, PATTERN (place
))
14447 && ! find_regno_fusage (place
, USE
, i
))
14448 for (tem_insn
= PREV_INSN (place
); ;
14449 tem_insn
= PREV_INSN (tem_insn
))
14451 if (!NONDEBUG_INSN_P (tem_insn
))
14453 if (tem_insn
== BB_HEAD (bb
))
14457 if (dead_or_set_p (tem_insn
, piece
)
14458 || reg_bitfield_target_p (piece
,
14459 PATTERN (tem_insn
)))
14461 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14474 /* Any other notes should not be present at this point in the
14476 gcc_unreachable ();
14481 XEXP (note
, 1) = REG_NOTES (place
);
14482 REG_NOTES (place
) = note
;
14486 add_shallow_copy_of_reg_note (place2
, note
);
14490 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14491 I3, I2, and I1 to new locations. This is also called to add a link
14492 pointing at I3 when I3's destination is changed. */
14495 distribute_links (struct insn_link
*links
)
14497 struct insn_link
*link
, *next_link
;
14499 for (link
= links
; link
; link
= next_link
)
14501 rtx_insn
*place
= 0;
14505 next_link
= link
->next
;
14507 /* If the insn that this link points to is a NOTE, ignore it. */
14508 if (NOTE_P (link
->insn
))
14512 rtx pat
= PATTERN (link
->insn
);
14513 if (GET_CODE (pat
) == SET
)
14515 else if (GET_CODE (pat
) == PARALLEL
)
14518 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14520 set
= XVECEXP (pat
, 0, i
);
14521 if (GET_CODE (set
) != SET
)
14524 reg
= SET_DEST (set
);
14525 while (GET_CODE (reg
) == ZERO_EXTRACT
14526 || GET_CODE (reg
) == STRICT_LOW_PART
14527 || GET_CODE (reg
) == SUBREG
)
14528 reg
= XEXP (reg
, 0);
14533 if (REGNO (reg
) == link
->regno
)
14536 if (i
== XVECLEN (pat
, 0))
14542 reg
= SET_DEST (set
);
14544 while (GET_CODE (reg
) == ZERO_EXTRACT
14545 || GET_CODE (reg
) == STRICT_LOW_PART
14546 || GET_CODE (reg
) == SUBREG
)
14547 reg
= XEXP (reg
, 0);
14549 /* A LOG_LINK is defined as being placed on the first insn that uses
14550 a register and points to the insn that sets the register. Start
14551 searching at the next insn after the target of the link and stop
14552 when we reach a set of the register or the end of the basic block.
14554 Note that this correctly handles the link that used to point from
14555 I3 to I2. Also note that not much searching is typically done here
14556 since most links don't point very far away. */
14558 for (insn
= NEXT_INSN (link
->insn
);
14559 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14560 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14561 insn
= NEXT_INSN (insn
))
14562 if (DEBUG_INSN_P (insn
))
14564 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14566 if (reg_referenced_p (reg
, PATTERN (insn
)))
14570 else if (CALL_P (insn
)
14571 && find_reg_fusage (insn
, USE
, reg
))
14576 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14579 /* If we found a place to put the link, place it there unless there
14580 is already a link to the same insn as LINK at that point. */
14584 struct insn_link
*link2
;
14586 FOR_EACH_LOG_LINK (link2
, place
)
14587 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14592 link
->next
= LOG_LINKS (place
);
14593 LOG_LINKS (place
) = link
;
14595 /* Set added_links_insn to the earliest insn we added a
14597 if (added_links_insn
== 0
14598 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14599 added_links_insn
= place
;
14605 /* Check for any register or memory mentioned in EQUIV that is not
14606 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14607 of EXPR where some registers may have been replaced by constants. */
14610 unmentioned_reg_p (rtx equiv
, rtx expr
)
14612 subrtx_iterator::array_type array
;
14613 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14615 const_rtx x
= *iter
;
14616 if ((REG_P (x
) || MEM_P (x
))
14617 && !reg_mentioned_p (x
, expr
))
14623 DEBUG_FUNCTION
void
14624 dump_combine_stats (FILE *file
)
14628 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14629 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14633 dump_combine_total_stats (FILE *file
)
14637 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14638 total_attempts
, total_merges
, total_extras
, total_successes
);
14641 /* Try combining insns through substitution. */
14642 static unsigned int
14643 rest_of_handle_combine (void)
14645 int rebuild_jump_labels_after_combine
;
14647 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14648 df_note_add_problem ();
14651 regstat_init_n_sets_and_refs ();
14652 reg_n_sets_max
= max_reg_num ();
14654 rebuild_jump_labels_after_combine
14655 = combine_instructions (get_insns (), max_reg_num ());
14657 /* Combining insns may have turned an indirect jump into a
14658 direct jump. Rebuild the JUMP_LABEL fields of jumping
14660 if (rebuild_jump_labels_after_combine
)
14662 if (dom_info_available_p (CDI_DOMINATORS
))
14663 free_dominance_info (CDI_DOMINATORS
);
14664 timevar_push (TV_JUMP
);
14665 rebuild_jump_labels (get_insns ());
14667 timevar_pop (TV_JUMP
);
14670 regstat_free_n_sets_and_refs ();
14676 const pass_data pass_data_combine
=
14678 RTL_PASS
, /* type */
14679 "combine", /* name */
14680 OPTGROUP_NONE
, /* optinfo_flags */
14681 TV_COMBINE
, /* tv_id */
14682 PROP_cfglayout
, /* properties_required */
14683 0, /* properties_provided */
14684 0, /* properties_destroyed */
14685 0, /* todo_flags_start */
14686 TODO_df_finish
, /* todo_flags_finish */
14689 class pass_combine
: public rtl_opt_pass
14692 pass_combine (gcc::context
*ctxt
)
14693 : rtl_opt_pass (pass_data_combine
, ctxt
)
14696 /* opt_pass methods: */
14697 virtual bool gate (function
*) { return (optimize
> 0); }
14698 virtual unsigned int execute (function
*)
14700 return rest_of_handle_combine ();
14703 }; // class pass_combine
14705 } // anon namespace
14708 make_pass_combine (gcc::context
*ctxt
)
14710 return new pass_combine (ctxt
);