| blob | e4e758dbeb0c25c3d689dc957d6a18053d8e44f1 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
62 #endif
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
70 : 4)
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
78 const
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
106 in SFmode, DFmode and XFmode */
108 in SFmode, DFmode and XFmode */
111 in SImode and DImode */
113 in SImode and DImode */
116 in SImode, DImode and TImode */
118 in SImode, DImode and TImode */
146 };
148 /* Processor costs (relative to an add) */
149 static const
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
177 in SFmode, DFmode and XFmode */
179 in SFmode, DFmode and XFmode */
182 in SImode and DImode */
184 in SImode and DImode */
187 in SImode, DImode and TImode */
189 in SImode, DImode and TImode */
203 DUMMY_STRINGOP_ALGS},
205 DUMMY_STRINGOP_ALGS},
217 };
219 static const
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
247 in SFmode, DFmode and XFmode */
249 in SFmode, DFmode and XFmode */
252 in SImode and DImode */
254 in SImode and DImode */
257 in SImode, DImode and TImode */
259 in SImode, DImode and TImode */
262 shared for code and data, so 4kB is
263 not really precise. */
275 DUMMY_STRINGOP_ALGS},
277 DUMMY_STRINGOP_ALGS},
289 };
291 static const
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
319 in SFmode, DFmode and XFmode */
321 in SFmode, DFmode and XFmode */
324 in SImode and DImode */
326 in SImode and DImode */
329 in SImode, DImode and TImode */
331 in SImode, DImode and TImode */
345 DUMMY_STRINGOP_ALGS},
347 DUMMY_STRINGOP_ALGS},
359 };
361 static const
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
389 in SFmode, DFmode and XFmode */
391 in SFmode, DFmode and XFmode */
394 in SImode and DImode */
396 in SImode and DImode */
399 in SImode, DImode and TImode */
401 in SImode, DImode and TImode */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
418 */
421 DUMMY_STRINGOP_ALGS},
424 DUMMY_STRINGOP_ALGS},
436 };
438 static const
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
466 in SFmode, DFmode and XFmode */
468 in SFmode, DFmode and XFmode */
472 in SImode and DImode */
474 in SImode and DImode */
477 in SImode, DImode and TImode */
479 in SImode, DImode and TImode */
493 DUMMY_STRINGOP_ALGS},
495 DUMMY_STRINGOP_ALGS},
507 };
509 static const
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
537 in SFmode, DFmode and XFmode */
539 in SFmode, DFmode and XFmode */
542 in SImode and DImode */
544 in SImode and DImode */
547 in SImode, DImode and TImode */
549 in SImode, DImode and TImode */
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
566 DUMMY_STRINGOP_ALGS},
568 DUMMY_STRINGOP_ALGS},
580 };
582 static const
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
610 in SFmode, DFmode and XFmode */
612 in SFmode, DFmode and XFmode */
615 in SImode and DImode */
617 in SImode and DImode */
620 in SImode, DImode and TImode */
622 in SImode, DImode and TImode */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
639 DUMMY_STRINGOP_ALGS},
641 DUMMY_STRINGOP_ALGS},
653 };
655 static const
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
683 in SFmode, DFmode and XFmode */
685 in SFmode, DFmode and XFmode */
688 in SImode and DImode */
690 in SImode and DImode */
693 in SImode, DImode and TImode */
695 in SImode, DImode and TImode */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
704 time). */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
732 };
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
761 in SFmode, DFmode and XFmode */
763 in SFmode, DFmode and XFmode */
766 in SImode and DImode */
768 in SImode and DImode */
771 in SImode, DImode and TImode */
773 in SImode, DImode and TImode */
775 /* On K8
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
778 On AMDFAM10
779 MOVD reg64, xmmreg Double FADD 3
780 1/1 1/1
781 MOVD reg32, xmmreg Double FADD 3
782 1/1 1/1 */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
790 time). */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
819 };
843 in QImode, HImode and SImode.
844 Relative to reg-reg move (2). */
848 in SFmode, DFmode and XFmode */
850 in SFmode, DFmode and XFmode */
853 in SImode and DImode */
855 in SImode and DImode */
858 in SImode, DImode and TImode */
860 in SImode, DImode and TImode */
862 /* On K8
863 MOVD reg64, xmmreg Double FSTORE 4
864 MOVD reg32, xmmreg Double FSTORE 4
865 On AMDFAM10
866 MOVD reg64, xmmreg Double FADD 3
867 1/1 1/1
868 MOVD reg32, xmmreg Double FADD 3
869 1/1 1/1 */
873 /* New AMD processors never drop prefetches; if they cannot be performed
874 immediately, they are queued. We set number of simultaneous prefetches
875 to a large constant to reflect this (it probably is not a good idea not
876 to limit number of prefetches at all, as their execution also takes some
877 time). */
887 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
888 very small blocks it is better to use loop. For large blocks, libcall can
889 do nontemporary accesses and beat inline considerably. */
906 };
908 static const
931 in QImode, HImode and SImode.
932 Relative to reg-reg move (2). */
936 in SFmode, DFmode and XFmode */
938 in SFmode, DFmode and XFmode */
941 in SImode and DImode */
943 in SImode and DImode */
946 in SImode, DImode and TImode */
948 in SImode, DImode and TImode */
962 DUMMY_STRINGOP_ALGS},
965 DUMMY_STRINGOP_ALGS},
977 };
979 static const
1002 in QImode, HImode and SImode.
1003 Relative to reg-reg move (2). */
1007 in SFmode, DFmode and XFmode */
1009 in SFmode, DFmode and XFmode */
1012 in SImode and DImode */
1014 in SImode and DImode */
1017 in SImode, DImode and TImode */
1019 in SImode, DImode and TImode */
1050 };
1052 static const
1075 in QImode, HImode and SImode.
1076 Relative to reg-reg move (2). */
1080 in SFmode, DFmode and XFmode */
1082 in SFmode, DFmode and XFmode */
1085 in SImode and DImode */
1087 in SImode and DImode */
1090 in SImode, DImode and TImode */
1092 in SImode, DImode and TImode */
1123 };
1125 static const
1148 in QImode, HImode and SImode.
1149 Relative to reg-reg move (2). */
1153 in SFmode, DFmode and XFmode */
1155 in SFmode, DFmode and XFmode */
1158 in SImode and DImode */
1160 in SImode and DImode */
1163 in SImode, DImode and TImode */
1165 in SImode, DImode and TImode */
1196 };
1198 /* Generic64 should produce code tuned for Nocona and K8. */
1199 static const
1202 /* On all chips taken into consideration lea is 2 cycles and more. With
1203 this cost however our current implementation of synth_mult results in
1204 use of unnecessary temporary registers causing regression on several
1205 SPECfp benchmarks. */
1226 in QImode, HImode and SImode.
1227 Relative to reg-reg move (2). */
1231 in SFmode, DFmode and XFmode */
1233 in SFmode, DFmode and XFmode */
1236 in SImode and DImode */
1238 in SImode and DImode */
1241 in SImode, DImode and TImode */
1243 in SImode, DImode and TImode */
1249 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1250 is increased to perhaps more appropriate value of 5. */
1273 };
1275 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1276 static const
1299 in QImode, HImode and SImode.
1300 Relative to reg-reg move (2). */
1304 in SFmode, DFmode and XFmode */
1306 in SFmode, DFmode and XFmode */
1309 in SImode and DImode */
1311 in SImode and DImode */
1314 in SImode, DImode and TImode */
1316 in SImode, DImode and TImode */
1330 DUMMY_STRINGOP_ALGS},
1332 DUMMY_STRINGOP_ALGS},
1344 };
1348 /* Processor feature/optimization bitmasks. */
1349 #define m_386 (1<<PROCESSOR_I386)
1350 #define m_486 (1<<PROCESSOR_I486)
1351 #define m_PENT (1<<PROCESSOR_PENTIUM)
1352 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1353 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1354 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1355 #define m_CORE2 (1<<PROCESSOR_CORE2)
1356 #define m_ATOM (1<<PROCESSOR_ATOM)
1358 #define m_GEODE (1<<PROCESSOR_GEODE)
1359 #define m_K6 (1<<PROCESSOR_K6)
1360 #define m_K6_GEODE (m_K6 | m_GEODE)
1361 #define m_K8 (1<<PROCESSOR_K8)
1362 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1363 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1364 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1365 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1366 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1)
1368 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1369 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1371 /* Generic instruction choice should be common subset of supported CPUs
1372 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1373 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1375 /* Feature tests against the various tunings. */
1378 /* Feature tests against the various tunings used to create ix86_tune_features
1379 based on the processor mask. */
1381 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1382 negatively, so enabling for Generic64 seems like good code size
1383 tradeoff. We can't enable it for 32bit generic because it does not
1384 work well with PPro base chips. */
1387 /* X86_TUNE_PUSH_MEMORY */
1391 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1394 /* X86_TUNE_UNROLL_STRLEN */
1398 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1401 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1402 on simulation result. But after P4 was made, no performance benefit
1403 was observed with branch hints. It also increases the code size.
1404 As a result, icc never generates branch hints. */
1407 /* X86_TUNE_DOUBLE_WITH_ADD */
1410 /* X86_TUNE_USE_SAHF */
1414 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1415 partial dependencies. */
1419 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1420 register stalls on Generic32 compilation setting as well. However
1421 in current implementation the partial register stalls are not eliminated
1422 very well - they can be introduced via subregs synthesized by combine
1423 and can happen in caller/callee saving sequences. Because this option
1424 pays back little on PPro based chips and is in conflict with partial reg
1425 dependencies used by Athlon/P4 based chips, it is better to leave it off
1426 for generic32 for now. */
1427 m_PPRO,
1429 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1432 /* X86_TUNE_USE_HIMODE_FIOP */
1435 /* X86_TUNE_USE_SIMODE_FIOP */
1438 /* X86_TUNE_USE_MOV0 */
1439 m_K6,
1441 /* X86_TUNE_USE_CLTD */
1444 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1445 m_PENT4,
1447 /* X86_TUNE_SPLIT_LONG_MOVES */
1448 m_PPRO,
1450 /* X86_TUNE_READ_MODIFY_WRITE */
1453 /* X86_TUNE_READ_MODIFY */
1456 /* X86_TUNE_PROMOTE_QIMODE */
1460 /* X86_TUNE_FAST_PREFIX */
1463 /* X86_TUNE_SINGLE_STRINGOP */
1466 /* X86_TUNE_QIMODE_MATH */
1469 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1470 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1471 might be considered for Generic32 if our scheme for avoiding partial
1472 stalls was more effective. */
1475 /* X86_TUNE_PROMOTE_QI_REGS */
1478 /* X86_TUNE_PROMOTE_HI_REGS */
1479 m_PPRO,
1481 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1485 /* X86_TUNE_ADD_ESP_8 */
1489 /* X86_TUNE_SUB_ESP_4 */
1493 /* X86_TUNE_SUB_ESP_8 */
1497 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1498 for DFmode copies */
1502 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1505 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1506 conflict here in between PPro/Pentium4 based chips that thread 128bit
1507 SSE registers as single units versus K8 based chips that divide SSE
1508 registers to two 64bit halves. This knob promotes all store destinations
1509 to be 128bit to allow register renaming on 128bit SSE units, but usually
1510 results in one extra microop on 64bit SSE units. Experimental results
1511 shows that disabling this option on P4 brings over 20% SPECfp regression,
1512 while enabling it on K8 brings roughly 2.4% regression that can be partly
1513 masked by careful scheduling of moves. */
1517 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1520 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1521 m_BDVER1,
1523 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1524 m_BDVER1,
1526 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1527 are resolved on SSE register parts instead of whole registers, so we may
1528 maintain just lower part of scalar values in proper format leaving the
1529 upper part undefined. */
1530 m_ATHLON_K8,
1532 /* X86_TUNE_SSE_TYPELESS_STORES */
1533 m_AMD_MULTIPLE,
1535 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1538 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1541 /* X86_TUNE_PROLOGUE_USING_MOVE */
1544 /* X86_TUNE_EPILOGUE_USING_MOVE */
1547 /* X86_TUNE_SHIFT1 */
1550 /* X86_TUNE_USE_FFREEP */
1551 m_AMD_MULTIPLE,
1553 /* X86_TUNE_INTER_UNIT_MOVES */
1556 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1559 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1560 than 4 branch instructions in the 16 byte window. */
1564 /* X86_TUNE_SCHEDULE */
1568 /* X86_TUNE_USE_BT */
1571 /* X86_TUNE_USE_INCDEC */
1574 /* X86_TUNE_PAD_RETURNS */
1577 /* X86_TUNE_EXT_80387_CONSTANTS */
1581 /* X86_TUNE_SHORTEN_X87_SSE */
1584 /* X86_TUNE_AVOID_VECTOR_DECODE */
1587 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1588 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1591 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1592 vector path on AMD machines. */
1595 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1596 machines. */
1599 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1600 than a MOV. */
1601 m_PENT,
1603 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1604 but one byte longer. */
1605 m_PENT,
1607 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1608 operand that cannot be represented using a modRM byte. The XOR
1609 replacement is long decoded, so this split helps here as well. */
1610 m_K6,
1612 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1613 from FP to FP. */
1616 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1617 from integer to FP. */
1618 m_AMDFAM10,
1620 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1621 with a subsequent conditional jump instruction into a single
1622 compare-and-branch uop. */
1625 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1626 will impact LEA instruction selection. */
1627 m_ATOM,
1628 };
1630 /* Feature tests against the various architecture variations. */
1633 /* Feature tests against the various architecture variations, used to create
1634 ix86_arch_features based on the processor mask. */
1636 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1639 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1642 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1645 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1648 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1650 };
1652 static const unsigned int x86_accumulate_outgoing_args
1656 static const unsigned int x86_arch_always_fancy_math_387
1662 /* In case the average insn count for single function invocation is
1663 lower than this constant, emit fast (but longer) prologue and
1664 epilogue code. */
1665 #define FAST_PROLOGUE_INSN_COUNT 20
1667 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1672 /* Array of the smallest class containing reg number REGNO, indexed by
1673 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1676 {
1677 /* ax, dx, cx, bx */
1679 /* si, di, bp, sp */
1681 /* FP registers */
1684 /* arg pointer */
1685 NON_Q_REGS,
1686 /* flags, fpsr, fpcr, frame */
1688 /* SSE registers */
1691 /* MMX registers */
1694 /* REX registers */
1697 /* SSE REX registers */
1700 };
1702 /* The "default" register map used in 32bit mode. */
1705 {
1713 };
1715 /* The "default" register map used in 64bit mode. */
1718 {
1726 };
1728 /* Define the register numbers to be used in Dwarf debugging information.
1729 The SVR4 reference port C compiler uses the following register numbers
1730 in its Dwarf output code:
1731 0 for %eax (gcc regno = 0)
1732 1 for %ecx (gcc regno = 2)
1733 2 for %edx (gcc regno = 1)
1734 3 for %ebx (gcc regno = 3)
1735 4 for %esp (gcc regno = 7)
1736 5 for %ebp (gcc regno = 6)
1737 6 for %esi (gcc regno = 4)
1738 7 for %edi (gcc regno = 5)
1739 The following three DWARF register numbers are never generated by
1740 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1741 believes these numbers have these meanings.
1742 8 for %eip (no gcc equivalent)
1743 9 for %eflags (gcc regno = 17)
1744 10 for %trapno (no gcc equivalent)
1745 It is not at all clear how we should number the FP stack registers
1746 for the x86 architecture. If the version of SDB on x86/svr4 were
1747 a bit less brain dead with respect to floating-point then we would
1748 have a precedent to follow with respect to DWARF register numbers
1749 for x86 FP registers, but the SDB on x86/svr4 is so completely
1750 broken with respect to FP registers that it is hardly worth thinking
1751 of it as something to strive for compatibility with.
1752 The version of x86/svr4 SDB I have at the moment does (partially)
1753 seem to believe that DWARF register number 11 is associated with
1754 the x86 register %st(0), but that's about all. Higher DWARF
1755 register numbers don't seem to be associated with anything in
1756 particular, and even for DWARF regno 11, SDB only seems to under-
1757 stand that it should say that a variable lives in %st(0) (when
1758 asked via an `=' command) if we said it was in DWARF regno 11,
1759 but SDB still prints garbage when asked for the value of the
1760 variable in question (via a `/' command).
1761 (Also note that the labels SDB prints for various FP stack regs
1762 when doing an `x' command are all wrong.)
1763 Note that these problems generally don't affect the native SVR4
1764 C compiler because it doesn't allow the use of -O with -g and
1765 because when it is *not* optimizing, it allocates a memory
1766 location for each floating-point variable, and the memory
1767 location is what gets described in the DWARF AT_location
1768 attribute for the variable in question.
1769 Regardless of the severe mental illness of the x86/svr4 SDB, we
1770 do something sensible here and we use the following DWARF
1771 register numbers. Note that these are all stack-top-relative
1772 numbers.
1773 11 for %st(0) (gcc regno = 8)
1774 12 for %st(1) (gcc regno = 9)
1775 13 for %st(2) (gcc regno = 10)
1776 14 for %st(3) (gcc regno = 11)
1777 15 for %st(4) (gcc regno = 12)
1778 16 for %st(5) (gcc regno = 13)
1779 17 for %st(6) (gcc regno = 14)
1780 18 for %st(7) (gcc regno = 15)
1781 */
1783 {
1791 };
1793 /* Test and compare insns in i386.md store the information needed to
1794 generate branch and scc insns here. */
1799 /* Define parameter passing and return registers. */
1802 {
1804 };
1807 {
1809 };
1812 {
1814 };
1816 /* Define the structure for the machine field in struct function. */
1821 rtx rtl;
1823 };
1825 /* Structure describing stack frame layout.
1826 Stack grows downward:
1828 [arguments]
1829 <- ARG_POINTER
1830 saved pc
1832 saved frame pointer if frame_pointer_needed
1833 <- HARD_FRAME_POINTER
1834 [saved regs]
1836 [padding0]
1838 [saved SSE regs]
1840 [padding1] \
1841 )
1842 [va_arg registers] (
1843 > to_allocate <- FRAME_POINTER
1844 [frame] (
1845 )
1846 [padding2] /
1847 */
1848 struct ix86_frame
1849 {
1855 HOST_WIDE_INT frame;
1860 HOST_WIDE_INT to_allocate;
1861 /* The offsets relative to ARG_POINTER. */
1862 HOST_WIDE_INT frame_pointer_offset;
1863 HOST_WIDE_INT hard_frame_pointer_offset;
1864 HOST_WIDE_INT stack_pointer_offset;
1866 /* When save_regs_using_mov is set, emit prologue using
1867 move instead of push instructions. */
1869 };
1871 /* Code model option. */
1873 /* Asm dialect. */
1875 /* TLS dialects. */
1878 /* Which unit we are generating floating point math for. */
1881 /* Which cpu are we scheduling for. */
1884 /* Which cpu are we optimizing for. */
1887 /* Which instruction set architecture to use. */
1890 /* true if sse prefetch instruction is not NOOP. */
1893 /* ix86_regparm_string as a number */
1896 /* -mstackrealign option */
1910 /* Preferred alignment for stack boundary in bits. */
1913 /* Alignment for incoming stack boundary in bits specified at
1914 command line. */
1917 /* Default alignment for incoming stack boundary in bits. */
1920 /* Alignment for incoming stack boundary in bits. */
1923 /* The abi used by target. */
1926 /* Values 1-5: see jump.c */
1929 /* Calling abi specific va_list type nodes. */
1933 /* Variables which are this size or smaller are put in the data/bss
1934 or ldata/lbss sections. */
1938 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1942 /* Fence to use after loop using movnt. */
1943 tree x86_mfence;
1945 /* Register class used for passing given 64bit part of the argument.
1946 These represent classes as documented by the PS ABI, with the exception
1947 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1948 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1950 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1951 whenever possible (upper half does contain padding). */
1952 enum x86_64_reg_class
1953 {
1954 X86_64_NO_CLASS,
1955 X86_64_INTEGER_CLASS,
1956 X86_64_INTEGERSI_CLASS,
1957 X86_64_SSE_CLASS,
1958 X86_64_SSESF_CLASS,
1959 X86_64_SSEDF_CLASS,
1960 X86_64_SSEUP_CLASS,
1961 X86_64_X87_CLASS,
1962 X86_64_X87UP_CLASS,
1963 X86_64_COMPLEX_X87_CLASS,
1964 X86_64_MEMORY_CLASS
1965 };
1967 #define MAX_CLASSES 4
1969 /* Table of constants used by fldpi, fldln2, etc.... */
1973 \f
1985 enum ix86_function_specific_strings
1986 {
1987 IX86_FUNCTION_SPECIFIC_ARCH,
1988 IX86_FUNCTION_SPECIFIC_TUNE,
1989 IX86_FUNCTION_SPECIFIC_FPMATH,
1990 IX86_FUNCTION_SPECIFIC_MAX
1991 };
2008 \f
2009 #ifndef SUBTARGET32_DEFAULT_CPU
2011 #endif
2013 /* The svr4 ABI for the i386 says that records and unions are returned
2014 in memory. */
2015 #ifndef DEFAULT_PCC_STRUCT_RETURN
2016 #define DEFAULT_PCC_STRUCT_RETURN 1
2017 #endif
2019 /* Whether -mtune= or -march= were specified */
2023 /* Bit flags that specify the ISA we are compiling for. */
2026 /* A mask of ix86_isa_flags that includes bit X if X
2027 was set or cleared on the command line. */
2030 /* Define a set of ISAs which are available when a given ISA is
2031 enabled. MMX and SSE ISAs are handled separately. */
2033 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
2034 #define OPTION_MASK_ISA_3DNOW_SET \
2035 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
2037 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
2038 #define OPTION_MASK_ISA_SSE2_SET \
2039 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
2040 #define OPTION_MASK_ISA_SSE3_SET \
2041 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
2042 #define OPTION_MASK_ISA_SSSE3_SET \
2043 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
2044 #define OPTION_MASK_ISA_SSE4_1_SET \
2045 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
2046 #define OPTION_MASK_ISA_SSE4_2_SET \
2047 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
2048 #define OPTION_MASK_ISA_AVX_SET \
2049 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
2050 #define OPTION_MASK_ISA_FMA_SET \
2051 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
2053 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
2054 as -msse4.2. */
2055 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
2057 #define OPTION_MASK_ISA_SSE4A_SET \
2058 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
2059 #define OPTION_MASK_ISA_FMA4_SET \
2060 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
2061 | OPTION_MASK_ISA_AVX_SET)
2062 #define OPTION_MASK_ISA_XOP_SET \
2063 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
2064 #define OPTION_MASK_ISA_LWP_SET \
2065 OPTION_MASK_ISA_LWP
2067 /* AES and PCLMUL need SSE2 because they use xmm registers */
2068 #define OPTION_MASK_ISA_AES_SET \
2069 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
2070 #define OPTION_MASK_ISA_PCLMUL_SET \
2071 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
2073 #define OPTION_MASK_ISA_ABM_SET \
2074 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
2076 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
2077 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
2078 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
2079 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
2080 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
2082 /* Define a set of ISAs which aren't available when a given ISA is
2083 disabled. MMX and SSE ISAs are handled separately. */
2085 #define OPTION_MASK_ISA_MMX_UNSET \
2086 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
2087 #define OPTION_MASK_ISA_3DNOW_UNSET \
2088 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
2089 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
2091 #define OPTION_MASK_ISA_SSE_UNSET \
2092 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
2093 #define OPTION_MASK_ISA_SSE2_UNSET \
2094 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2095 #define OPTION_MASK_ISA_SSE3_UNSET \
2096 (OPTION_MASK_ISA_SSE3 \
2097 | OPTION_MASK_ISA_SSSE3_UNSET \
2098 | OPTION_MASK_ISA_SSE4A_UNSET )
2099 #define OPTION_MASK_ISA_SSSE3_UNSET \
2100 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2101 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2102 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2103 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2104 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2105 #define OPTION_MASK_ISA_AVX_UNSET \
2106 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2107 | OPTION_MASK_ISA_FMA4_UNSET)
2108 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2110 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2111 as -mno-sse4.1. */
2112 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2114 #define OPTION_MASK_ISA_SSE4A_UNSET \
2115 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2117 #define OPTION_MASK_ISA_FMA4_UNSET \
2118 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2119 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2120 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2122 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2123 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2124 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2125 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2126 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2127 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2128 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2129 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2131 /* Vectorization library interface and handlers. */
2136 /* Processor target table, indexed by processor number */
2137 struct ptt
2138 {
2145 };
2148 {
2165 };
2168 {
2191 "bdver1"
2192 };
2193 \f
2194 /* Implement TARGET_HANDLE_OPTION. */
2196 static bool
2198 {
2200 {
2203 {
2206 }
2207 else
2208 {
2211 }
2216 {
2219 }
2220 else
2221 {
2224 }
2232 {
2235 }
2236 else
2237 {
2240 }
2245 {
2248 }
2249 else
2250 {
2253 }
2258 {
2261 }
2262 else
2263 {
2266 }
2271 {
2274 }
2275 else
2276 {
2279 }
2284 {
2287 }
2288 else
2289 {
2292 }
2297 {
2300 }
2301 else
2302 {
2305 }
2310 {
2313 }
2314 else
2315 {
2318 }
2323 {
2326 }
2327 else
2328 {
2331 }
2346 {
2349 }
2350 else
2351 {
2354 }
2359 {
2362 }
2363 else
2364 {
2367 }
2372 {
2375 }
2376 else
2377 {
2380 }
2385 {
2388 }
2389 else
2390 {
2393 }
2398 {
2401 }
2402 else
2403 {
2406 }
2411 {
2414 }
2415 else
2416 {
2419 }
2424 {
2427 }
2428 else
2429 {
2432 }
2437 {
2440 }
2441 else
2442 {
2445 }
2450 {
2453 }
2454 else
2455 {
2458 }
2463 {
2466 }
2467 else
2468 {
2471 }
2476 {
2479 }
2480 else
2481 {
2484 }
2489 {
2492 }
2493 else
2494 {
2497 }
2502 }
2503 }
2504 \f
2505 /* Return a string that documents the current -m options. The caller is
2506 responsible for freeing the string. */
2511 {
2512 struct ix86_target_opts
2513 {
2516 };
2518 /* This table is ordered so that options like -msse4.2 that imply
2519 preceding options while match those first. */
2521 {
2543 };
2545 /* Flag options. */
2547 {
2568 };
2584 /* Add -march= option. */
2586 {
2589 }
2591 /* Add -mtune= option. */
2593 {
2596 }
2598 /* Pick out the options in isa options. */
2600 {
2602 {
2605 }
2606 }
2609 {
2612 }
2614 /* Add flag options. */
2616 {
2618 {
2621 }
2622 }
2625 {
2628 }
2630 /* Add -fpmath= option. */
2632 {
2635 }
2637 /* Any options? */
2643 /* Size the string. */
2647 {
2652 }
2654 /* Build the string. */
2659 {
2666 {
2668 line_len++;
2671 {
2675 }
2676 }
2680 {
2684 }
2685 }
2691 }
2693 /* Function that is callable from the debugger to print the current
2694 options. */
2695 void
2697 {
2703 {
2706 }
2707 else
2711 }
2712 \f
2713 /* Sometimes certain combinations of command options do not make
2714 sense on a particular target machine. You can define a macro
2715 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2716 defined, is executed once just after all the command options have
2717 been parsed.
2719 Don't use this macro to turn on various extra optimizations for
2720 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2722 void
2724 {
2732 /* Comes from final.c -- no real reason to change it. */
2733 #define MAX_CODE_ALIGN 16
2735 enum pta_flags
2736 {
2761 };
2763 static struct pta
2764 {
2769 }
2771 {
2858 };
2862 /* Set up prefix/suffix so the error messages refer to either the command
2863 line argument, or the attribute(target). */
2865 {
2869 }
2870 else
2871 {
2875 }
2877 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2878 SUBTARGET_OVERRIDE_OPTIONS;
2879 #endif
2881 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2882 SUBSUBTARGET_OVERRIDE_OPTIONS;
2883 #endif
2885 /* -fPIC is the default for x86_64. */
2889 /* Set the default values for switches whose default depends on TARGET_64BIT
2890 in case they weren't overwritten by command line options. */
2892 {
2893 /* Mach-O doesn't support omitting the frame pointer for now. */
2900 }
2901 else
2902 {
2909 }
2911 /* Need to check -mtune=generic first. */
2913 {
2916 /* As special support for cross compilers we read -mtune=native
2917 as -mtune=generic. With native compilers we won't see the
2918 -mtune=native, as it was changed by the driver. */
2920 {
2923 else
2925 }
2926 /* If this call is for setting the option attribute, allow the
2927 generic32/generic64 that was previously set. */
2931 ;
2939 }
2940 else
2941 {
2945 {
2948 }
2950 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2951 need to use a sensible tune option. */
2955 {
2958 else
2960 }
2961 }
2964 {
2973 /* rep; movq isn't available in 32-bit code. */
2981 else
2984 }
2988 else
2991 /* Validate -mabi= value. */
2993 {
2998 else
3001 }
3002 else
3006 {
3019 else
3022 }
3023 else
3024 {
3025 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3026 use of rip-relative addressing. This eliminates fixups that
3027 would otherwise be needed if this object is to be placed in a
3028 DLL, and is essentially just as efficient as direct addressing. */
3033 else
3035 }
3037 {
3043 else
3046 }
3056 {
3059 /* Default cpu tuning to the architecture. */
3136 }
3151 {
3155 {
3157 {
3165 }
3166 else
3169 }
3170 /* Intel CPUs have always interpreted SSE prefetch instructions as
3171 NOPs; so, we can enable SSE prefetch instructions even when
3172 -mtune (rather than -march) points us to a processor that has them.
3173 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3174 higher processors. */
3179 }
3191 else
3194 /* Arrange to set up i386_stack_locals for all functions. */
3197 /* Validate -mregparm= value. */
3199 {
3206 else
3208 }
3212 /* If the user has provided any of the -malign-* options,
3213 warn and use that value only if -falign-* is not set.
3214 Remove this code in GCC 3.2 or later. */
3216 {
3220 {
3225 else
3227 }
3228 }
3231 {
3235 {
3240 else
3242 }
3243 }
3246 {
3250 {
3255 else
3257 }
3258 }
3260 /* Default align_* from the processor table. */
3262 {
3265 }
3267 {
3270 }
3272 {
3274 }
3276 /* Validate -mbranch-cost= value, or provide default. */
3279 {
3283 else
3285 }
3287 {
3291 else
3293 }
3296 {
3301 else
3304 }
3307 {
3311 }
3314 {
3317 /* Enable by default the SSE and MMX builtins. Do allow the user to
3318 explicitly disable any of these. In particular, disabling SSE and
3319 MMX for kernel code is extremely useful. */
3321 ix86_isa_flags
3327 }
3328 else
3329 {
3333 ix86_isa_flags
3336 /* i386 ABI does not specify red zone. It still makes sense to use it
3337 when programmer takes care to stack from being destroyed. */
3340 }
3342 /* Keep nonleaf frame pointers. */
3348 /* If we're doing fast math, we don't care about comparison order
3349 wrt NaNs. This lets us use a shorter comparison sequence. */
3353 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3354 since the insns won't need emulation. */
3358 /* Likewise, if the target doesn't have a 387, or we've specified
3359 software floating point, don't use 387 inline intrinsics. */
3363 /* Turn on MMX builtins for -msse. */
3365 {
3368 }
3370 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3374 /* Validate -mpreferred-stack-boundary= value or default it to
3375 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3378 {
3383 else
3385 }
3387 /* Set the default value for -mstackrealign. */
3393 /* Validate -mincoming-stack-boundary= value or default it to
3394 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3397 {
3402 else
3403 {
3405 ix86_incoming_stack_boundary
3407 }
3408 }
3410 /* Accept -msseregparm only if at least SSE support is enabled. */
3417 {
3421 {
3423 {
3426 }
3427 else
3429 }
3435 {
3437 {
3440 }
3442 {
3445 }
3446 else
3448 }
3449 else
3452 }
3454 /* If the i387 is disabled, then do not return values in it. */
3458 /* Use external vectorized library in vectorizing intrinsics. */
3460 {
3465 else
3469 }
3476 /* ??? Unwind info is not correct around the CFG unless either a frame
3477 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3478 unwind info generation to be aware of the CFG and propagating states
3479 around edges. */
3482 && flag_omit_frame_pointer
3484 {
3490 }
3492 /* If stack probes are required, the space used for large function
3493 arguments on the stack must also be probed, so enable
3494 -maccumulate-outgoing-args so this happens in the prologue. */
3497 {
3502 }
3504 /* For sane SSE instruction set generation we need fcomi instruction.
3505 It is safe to enable all CMOVE instructions. */
3509 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3510 {
3516 }
3518 /* When scheduling description is not available, disable scheduler pass
3519 so it won't slow down the compilation and make x87 code slower. */
3533 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3534 can be optimized to ap = __builtin_next_arg (0). */
3539 {
3548 }
3549 else
3550 {
3559 }
3561 #ifdef USE_IX86_CLD
3562 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3565 #endif
3567 /* Save the initial options in case the user does function specific options */
3569 target_option_default_node = target_option_current_node
3571 }
3573 /* Update register usage after having seen the compiler flags. */
3575 void
3577 {
3582 {
3587 }
3589 /* The PIC register, if it exists, is fixed. */
3594 /* The MS_ABI changes the set of call-used registers. */
3596 {
3603 }
3605 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3606 other call-clobbered regs for 64-bit. */
3608 {
3615 }
3617 /* If MMX is disabled, squash the registers. */
3623 /* If SSE is disabled, squash the registers. */
3629 /* If the FPU is disabled, squash the registers. */
3635 /* If 32-bit, squash the 64-bit registers. */
3637 {
3642 }
3643 }
3645 \f
3646 /* Save the current options */
3648 static void
3650 {
3661 /* The fields are char but the variables are not; make sure the
3662 values fit in the fields. */
3668 }
3670 /* Restore the current options */
3672 static void
3674 {
3690 /* Recreate the arch feature tests if the arch changed */
3692 {
3697 }
3699 /* Recreate the tune optimization tests */
3701 {
3706 }
3707 }
3709 /* Print the current options */
3711 static void
3714 {
3739 {
3742 }
3743 }
3745 \f
3746 /* Inner function to process the attribute((target(...))), take an argument and
3747 set the current options from the argument. If we have a list, recursively go
3748 over the list. */
3750 static bool
3752 {
3756 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3757 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3758 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3759 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3761 enum ix86_opt_type
3762 {
3763 ix86_opt_unknown,
3764 ix86_opt_yes,
3765 ix86_opt_no,
3766 ix86_opt_str,
3767 ix86_opt_isa
3768 };
3770 static const struct
3771 {
3778 /* isa options */
3798 /* string options */
3803 /* flag options */
3805 OPT_mcld,
3806 MASK_CLD),
3809 OPT_mfancy_math_387,
3810 MASK_NO_FANCY_MATH_387),
3813 OPT_mieee_fp,
3814 MASK_IEEE_FP),
3817 OPT_minline_all_stringops,
3818 MASK_INLINE_ALL_STRINGOPS),
3821 OPT_minline_stringops_dynamically,
3822 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3825 OPT_mno_align_stringops,
3826 MASK_NO_ALIGN_STRINGOPS),
3829 OPT_mrecip,
3830 MASK_RECIP),
3832 };
3834 /* If this is a list, recurse to get the options. */
3836 {
3845 }
3850 /* Handle multiple arguments separated by commas. */
3854 {
3868 {
3872 }
3873 else
3874 {
3877 }
3879 /* Recognize no-xxx. */
3881 {
3885 }
3886 else
3889 /* Find the option. */
3893 {
3899 {
3904 }
3905 }
3907 /* Process the option. */
3909 {
3912 }
3918 {
3924 else
3926 }
3929 {
3931 {
3934 }
3935 else
3937 }
3939 else
3941 }
3944 }
3946 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3948 tree
3950 {
3962 /* Process each of the options on the chain. */
3966 /* If the changed options are different from the default, rerun override_options,
3967 and then save the options away. The string options are are attribute options,
3968 and will be undone when we copy the save structure. */
3974 {
3975 /* If we are using the default tune= or arch=, undo the string assigned,
3976 and use the default. */
3987 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3993 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3996 /* Add any builtin functions with the new isa if any. */
3999 /* Save the current options unless we are validating options for
4000 #pragma. */
4007 /* Free up memory allocated to hold the strings */
4011 }
4014 }
4016 /* Hook to validate attribute((target("string"))). */
4018 static bool
4021 tree args,
4023 {
4030 /* If the function changed the optimization levels as well as setting target
4031 options, start with the optimizations specified. */
4035 /* The target attributes may also change some optimization flags, so update
4036 the optimization options if necessary. */
4045 {
4050 }
4058 }
4060 \f
4061 /* Hook to determine if one function can safely inline another. */
4063 static bool
4065 {
4070 /* If callee has no option attributes, then it is ok to inline. */
4074 /* If caller has no option attributes, but callee does then it is not ok to
4075 inline. */
4079 else
4080 {
4084 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4085 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4086 function. */
4091 /* See if we have the same non-isa options. */
4095 /* See if arch, tune, etc. are the same. */
4108 else
4110 }
4113 }
4115 \f
4116 /* Remember the last target of ix86_set_current_function. */
4119 /* Establish appropriate back-end context for processing the function
4120 FNDECL. The argument might be NULL to indicate processing at top
4121 level, outside of any function scope. */
4122 static void
4124 {
4125 /* Only change the context if the function changes. This hook is called
4126 several times in the course of compiling a function, and we don't want to
4127 slow things down too much or call target_reinit when it isn't safe. */
4129 {
4130 tree old_tree = (ix86_previous_fndecl
4134 tree new_tree = (fndecl
4140 ;
4143 {
4146 }
4149 {
4155 }
4156 }
4157 }
4159 \f
4160 /* Return true if this goes in large data/bss. */
4162 static bool
4164 {
4168 /* Functions are never large data. */
4173 {
4179 }
4180 else
4181 {
4184 /* If this is an incomplete type with size 0, then we can't put it
4185 in data because it might be too big when completed. */
4188 }
4191 }
4193 /* Switch to the appropriate section for output of DECL.
4194 DECL is either a `VAR_DECL' node or a constant of some sort.
4195 RELOC indicates whether forming the initial value of DECL requires
4196 link-time relocations. */
4199 ATTRIBUTE_UNUSED;
4204 {
4207 {
4211 {
4245 /* We don't split these for medium model. Place them into
4246 default sections and hope for best. */
4251 }
4253 {
4254 /* We might get called with string constants, but get_named_section
4255 doesn't like them as they are not DECLs. Also, we need to set
4256 flags in that case. */
4260 }
4261 }
4263 }
4265 /* Build up a unique section name, expressed as a
4266 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4267 RELOC indicates whether the initial value of EXP requires
4268 link-time relocations. */
4270 static void ATTRIBUTE_UNUSED
4272 {
4275 {
4277 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4281 {
4305 /* We don't split these for medium model. Place them into
4306 default sections and hope for best. */
4314 }
4316 {
4323 /* If we're using one_only, then there needs to be a .gnu.linkonce
4324 prefix to the section name. */
4331 }
4332 }
4334 }
4336 #ifdef COMMON_ASM_OP
4337 /* This says how to output assembler code to declare an
4338 uninitialized external linkage data object.
4340 For medium model x86-64 we need to use .largecomm opcode for
4341 large objects. */
4342 void
4346 {
4350 else
4355 }
4356 #endif
4358 /* Utility function for targets to use in implementing
4359 ASM_OUTPUT_ALIGNED_BSS. */
4361 void
4365 {
4369 else
4372 #ifdef ASM_DECLARE_OBJECT_NAME
4375 #else
4376 /* Standard thing is just output label for the object. */
4380 }
4381 \f
4382 void
4384 {
4385 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4386 make the problem with not enough registers even worse. */
4387 #ifdef INSN_SCHEDULING
4390 #endif
4392 /* For -O2 and beyond, turn on -fzee for x86_64 target. */
4397 /* The Darwin libraries never set errno, so we might as well
4398 avoid calling them when that's the only reason we would. */
4401 /* The default values of these switches depend on the TARGET_64BIT
4402 that is not known at this moment. Mark these values with 2 and
4403 let user the to override these. In case there is no command line option
4404 specifying them, we will set the defaults in override_options. */
4410 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4411 SUBTARGET_OPTIMIZATION_OPTIONS;
4412 #endif
4413 }
4414 \f
4415 /* Decide whether we can make a sibling call to a function. DECL is the
4416 declaration of the function being targeted by the call and EXP is the
4417 CALL_EXPR representing the call. */
4419 static bool
4421 {
4425 /* If we are generating position-independent code, we cannot sibcall
4426 optimize any indirect call, or a direct call to a global function,
4427 as the PLT requires %ebx be live. */
4431 /* If we need to align the outgoing stack, then sibcalling would
4432 unalign the stack, which may break the called function. */
4438 {
4441 }
4442 else
4443 {
4444 /* We're looking at the CALL_EXPR, we need the type of the function. */
4449 }
4451 /* Check that the return value locations are the same. Like
4452 if we are returning floats on the 80387 register stack, we cannot
4453 make a sibcall from a function that doesn't return a float to a
4454 function that does or, conversely, from a function that does return
4455 a float to a function that doesn't; the necessary stack adjustment
4456 would not be executed. This is also the place we notice
4457 differences in the return value ABI. Note that it is ok for one
4458 of the functions to have void return type as long as the return
4459 value of the other is passed in a register. */
4464 {
4467 }
4469 ;
4474 {
4475 /* The SYSV ABI has more call-clobbered registers;
4476 disallow sibcalls from MS to SYSV. */
4480 }
4481 else
4482 {
4483 /* If this call is indirect, we'll need to be able to use a
4484 call-clobbered register for the address of the target function.
4485 Make sure that all such registers are not used for passing
4486 parameters. Note that DLLIMPORT functions are indirect. */
4489 {
4491 {
4492 /* ??? Need to count the actual number of registers to be used,
4493 not the possible number of registers. Fix later. */
4495 }
4496 }
4497 }
4499 /* Otherwise okay. That also includes certain types of indirect calls. */
4501 }
4503 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4504 and "sseregparm" calling convention attributes;
4505 arguments as in struct attribute_spec.handler. */
4507 static tree
4509 tree args,
4512 {
4517 {
4519 name);
4522 }
4524 /* Can combine regparm with all attributes but fastcall. */
4526 {
4527 tree cst;
4530 {
4532 }
4535 {
4537 }
4541 {
4544 name);
4546 }
4548 {
4552 }
4555 }
4558 {
4559 /* Do not warn when emulating the MS ABI. */
4564 name);
4567 }
4569 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4571 {
4573 {
4575 }
4577 {
4579 }
4581 {
4583 }
4585 {
4587 }
4588 }
4590 /* Can combine stdcall with fastcall (redundant), regparm and
4591 sseregparm. */
4593 {
4595 {
4597 }
4599 {
4601 }
4603 {
4605 }
4606 }
4608 /* Can combine cdecl with regparm and sseregparm. */
4610 {
4612 {
4614 }
4616 {
4618 }
4620 {
4622 }
4623 }
4625 {
4628 name);
4630 {
4632 }
4634 {
4636 }
4638 {
4640 }
4641 }
4643 /* Can combine sseregparm with all attributes. */
4646 }
4648 /* Return 0 if the attributes for two types are incompatible, 1 if they
4649 are compatible, and 2 if they are nearly compatible (which causes a
4650 warning to be generated). */
4652 static int
4654 {
4655 /* Check for mismatch of non-default calling convention. */
4662 /* Check for mismatched fastcall/regparm types. */
4669 /* Check for mismatched sseregparm types. */
4674 /* Check for mismatched thiscall types. */
4679 /* Check for mismatched return types (cdecl vs stdcall). */
4685 }
4686 \f
4687 /* Return the regparm value for a function with the indicated TYPE and DECL.
4688 DECL may be NULL when calling function indirectly
4689 or considering a libcall. */
4691 static int
4693 {
4694 tree attr;
4704 {
4707 }
4715 /* Use register calling convention for local functions when possible. */
4718 && optimize
4720 {
4721 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4724 {
4727 /* Make sure no regparm register is taken by a
4728 fixed register variable. */
4733 /* We don't want to use regparm(3) for nested functions as
4734 these use a static chain pointer in the third argument. */
4738 /* Each fixed register usage increases register pressure,
4739 so less registers should be used for argument passing.
4740 This functionality can be overriden by an explicit
4741 regparm value. */
4744 globals++;
4746 local_regparm
4751 }
4752 }
4755 }
4757 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4758 DFmode (2) arguments in SSE registers for a function with the
4759 indicated TYPE and DECL. DECL may be NULL when calling function
4760 indirectly or considering a libcall. Otherwise return 0. */
4762 static int
4764 {
4767 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4768 by the sseregparm attribute. */
4771 {
4773 {
4775 {
4779 else
4782 }
4784 }
4787 }
4789 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4790 (and DFmode for SSE2) arguments in SSE registers. */
4792 {
4793 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4797 }
4800 }
4802 /* Return true if EAX is live at the start of the function. Used by
4803 ix86_expand_prologue to determine if we need special help before
4804 calling allocate_stack_worker. */
4806 static bool
4808 {
4809 /* Cheat. Don't bother working forward from ix86_function_regparm
4810 to the function type to whether an actual argument is located in
4811 eax. Instead just look at cfg info, which is still close enough
4812 to correct at this point. This gives false positives for broken
4813 functions that might use uninitialized data that happens to be
4814 allocated in eax, but who cares? */
4816 }
4818 /* Value is the number of bytes of arguments automatically
4819 popped when returning from a subroutine call.
4820 FUNDECL is the declaration node of the function (as a tree),
4821 FUNTYPE is the data type of the function (as a tree),
4822 or for a library call it is an identifier node for the subroutine name.
4823 SIZE is the number of bytes of arguments passed on the stack.
4825 On the 80386, the RTD insn may be used to pop them if the number
4826 of args is fixed, but if the number is variable then the caller
4827 must pop them all. RTD can't be used for library calls now
4828 because the library is compiled with the Unix compiler.
4829 Use of RTD is a selectable option, since it is incompatible with
4830 standard Unix calling sequences. If the option is not selected,
4831 the caller must always pop the args.
4833 The attribute stdcall is equivalent to RTD on a per module basis. */
4835 int
4837 {
4840 /* None of the 64-bit ABIs pop arguments. */
4846 /* Cdecl functions override -mrtd, and never pop the stack. */
4848 {
4849 /* Stdcall and fastcall functions will pop the stack if not
4850 variable args. */
4858 }
4860 /* Lose any fake structure return argument if it is passed on the stack. */
4863 {
4867 }
4870 }
4871 \f
4872 /* Argument support functions. */
4874 /* Return true when register may be used to pass function parameters. */
4875 bool
4877 {
4882 {
4886 else
4892 }
4895 {
4898 }
4899 else
4900 {
4904 }
4906 /* TODO: The function should depend on current function ABI but
4907 builtins.c would need updating then. Therefore we use the
4908 default ABI. */
4910 /* RAX is used as hidden argument to va_arg functions. */
4916 else
4923 }
4925 /* Return if we do not know how to pass TYPE solely in registers. */
4927 static bool
4929 {
4933 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4934 The layout_type routine is crafty and tries to trick us into passing
4935 currently unsupported vector types on the stack by using TImode. */
4938 }
4940 /* It returns the size, in bytes, of the area reserved for arguments passed
4941 in registers for the function represented by fndecl dependent to the used
4942 abi format. */
4943 int
4945 {
4949 else
4954 }
4956 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4957 call abi used. */
4958 enum calling_abi
4960 {
4962 {
4965 {
4968 }
4972 }
4974 }
4976 static bool
4978 {
4980 {
4982 {
4984 {
4987 }
4990 }
4991 }
4993 }
4995 static enum calling_abi
4997 {
5001 }
5003 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5004 call abi used. */
5005 enum calling_abi
5007 {
5011 }
5013 /* regclass.c */
5016 /* Implementation of call abi switching target hook. Specific to FNDECL
5017 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
5018 for more details. */
5019 void
5021 {
5024 else
5026 }
5028 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
5029 re-initialization of init_regs each time we switch function context since
5030 this is needed only during RTL expansion. */
5031 static void
5033 {
5037 }
5039 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5040 for a call to a function whose data type is FNTYPE.
5041 For a library call, FNTYPE is 0. */
5043 void
5047 tree fndecl)
5048 {
5054 else
5056 /* Set up the number of registers to use for passing arguments. */
5063 {
5067 }
5069 {
5072 {
5075 ? X86_64_SSE_REGPARM_MAX
5077 }
5078 }
5085 /* Because type might mismatch in between caller and callee, we need to
5086 use actual type of function for local calls.
5087 FIXME: cgraph_analyze can be told to actually record if function uses
5088 va_start so for local functions maybe_vaarg can be made aggressive
5089 helping K&R code.
5090 FIXME: once typesytem is fixed, we won't need this code anymore. */
5098 {
5099 /* If there are variable arguments, then we won't pass anything
5100 in registers in 32-bit mode. */
5102 {
5110 }
5112 /* Use ecx and edx registers if function has fastcall attribute,
5113 else look for regparm information. */
5115 {
5117 {
5120 }
5122 {
5125 }
5126 else
5128 }
5130 /* Set up the number of SSE registers used for passing SFmode
5131 and DFmode arguments. Warn for mismatching ABI. */
5133 }
5134 }
5136 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5137 But in the case of vector types, it is some vector mode.
5139 When we have only some of our vector isa extensions enabled, then there
5140 are some modes for which vector_mode_supported_p is false. For these
5141 modes, the generic vector support in gcc will choose some non-vector mode
5142 in order to implement the type. By computing the natural mode, we'll
5143 select the proper ABI location for the operand and not depend on whatever
5144 the middle-end decides to do with these vector types.
5146 The midde-end can't deal with the vector types > 16 bytes. In this
5147 case, we return the original mode and warn ABI change if CUM isn't
5148 NULL. */
5150 static enum machine_mode
5152 {
5156 {
5159 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5161 {
5166 else
5169 /* Get the mode which has this inner mode and number of units. */
5173 {
5175 {
5179 && !warnedavx
5181 {
5185 }
5187 }
5188 else
5190 }
5193 }
5194 }
5197 }
5199 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5200 this may not agree with the mode that the type system has chosen for the
5201 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5202 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5204 static rtx
5207 {
5208 rtx tmp;
5212 else
5213 {
5217 }
5220 }
5222 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5223 of this code is to classify each 8bytes of incoming argument by the register
5224 class and assign registers accordingly. */
5226 /* Return the union class of CLASS1 and CLASS2.
5227 See the x86-64 PS ABI for details. */
5229 static enum x86_64_reg_class
5231 {
5232 /* Rule #1: If both classes are equal, this is the resulting class. */
5236 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5237 the other class. */
5243 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5247 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5255 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5256 MEMORY is used. */
5265 /* Rule #6: Otherwise class SSE is used. */
5267 }
5269 /* Classify the argument of type TYPE and mode MODE.
5270 CLASSES will be filled by the register class used to pass each word
5271 of the operand. The number of words is returned. In case the parameter
5272 should be passed in memory, 0 is returned. As a special case for zero
5273 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5275 BIT_OFFSET is used internally for handling records and specifies offset
5276 of the offset in bits modulo 256 to avoid overflow cases.
5278 See the x86-64 PS ABI for details.
5279 */
5281 static int
5284 {
5285 HOST_WIDE_INT bytes =
5289 /* Variable sized entities are always passed/returned in memory. */
5298 {
5300 tree field;
5303 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5310 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5311 signalize memory class, so handle it as special case. */
5313 {
5316 }
5318 /* Classify each field of record and merge classes. */
5320 {
5322 /* And now merge the fields of structure. */
5324 {
5326 {
5332 /* Bitfields are always classified as integer. Handle them
5333 early, since later code would consider them to be
5334 misaligned integers. */
5336 {
5344 }
5345 else
5346 {
5351 /* Flexible array member is ignored. */
5358 {
5362 {
5365 "The ABI of passing struct with"
5366 " a flexible array member has"
5368 }
5370 }
5372 subclasses,
5381 }
5382 }
5383 }
5387 /* Arrays are handled as small records. */
5388 {
5395 /* The partial classes are now full classes. */
5406 }
5409 /* Unions are similar to RECORD_TYPE but offset is always 0.
5410 */
5412 {
5414 {
5422 bit_offset);
5427 }
5428 }
5433 }
5436 {
5437 /* When size > 16 bytes, if the first one isn't
5438 X86_64_SSE_CLASS or any other ones aren't
5439 X86_64_SSEUP_CLASS, everything should be passed in
5440 memory. */
5447 }
5449 /* Final merger cleanup. */
5451 {
5452 /* If one class is MEMORY, everything should be passed in
5453 memory. */
5457 /* The X86_64_SSEUP_CLASS should be always preceded by
5458 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5462 {
5463 /* The first one should never be X86_64_SSEUP_CLASS. */
5466 }
5468 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5469 everything should be passed in memory. */
5472 {
5475 /* The first one should never be X86_64_X87UP_CLASS. */
5478 {
5481 "The ABI of passing union with long double"
5483 }
5485 }
5486 }
5488 }
5490 /* Compute alignment needed. We align all types to natural boundaries with
5491 exception of XFmode that is aligned to 64bits. */
5493 {
5502 /* Misaligned fields are always returned in memory. */
5505 }
5507 /* for V1xx modes, just use the base mode */
5512 /* Classification of atomic types. */
5514 {
5530 {
5534 {
5537 }
5539 {
5542 }
5544 {
5548 }
5550 {
5553 }
5554 else
5556 }
5563 /* OImode shouldn't be used directly. */
5570 else
5588 else
5589 {
5593 {
5596 "The ABI of passing structure with complex float"
5598 }
5601 }
5610 /* This modes is larger than 16 bytes. */
5653 else
5657 }
5658 }
5660 /* Examine the argument and return set number of register required in each
5661 class. Return 0 iff parameter should be passed in memory. */
5662 static int
5665 {
5675 {
5697 }
5699 }
5701 /* Construct container for the argument used by GCC interface. See
5702 FUNCTION_ARG for the detailed description. */
5704 static rtx
5708 {
5709 /* The following variables hold the static issued_error state. */
5723 rtx ret;
5734 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5735 some less clueful developer tries to use floating-point anyway. */
5737 {
5739 {
5741 {
5744 }
5745 }
5747 {
5750 }
5752 }
5754 /* Likewise, error if the ABI requires us to return values in the
5755 x87 registers and the user specified -mno-80387. */
5761 {
5763 {
5766 }
5768 }
5770 /* First construct simple cases. Avoid SCmode, since we want to use
5771 single register to pass this type. */
5774 {
5789 /* Zero sized array, struct or class. */
5793 }
5814 /* Otherwise figure out the entries of the PARALLEL. */
5816 {
5820 {
5825 /* Merge TImodes on aligned occasions here too. */
5830 else
5832 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5838 intreg++;
5845 sse_regno++;
5852 sse_regno++;
5857 {
5863 {
5865 i++;
5866 }
5867 else
5880 }
5885 sse_regno++;
5889 }
5890 }
5892 /* Empty aligned struct, union or class. */
5900 }
5902 /* Update the data in CUM to advance over an argument of mode MODE
5903 and data type TYPE. (TYPE is null for libcalls where that information
5904 may not be available.) */
5906 static void
5909 {
5911 {
5918 /* FALLTHRU */
5929 {
5932 }
5936 /* OImode shouldn't be used directly. */
5945 /* FALLTHRU */
5961 {
5966 {
5969 }
5970 }
5980 {
5985 {
5988 }
5989 }
5991 }
5992 }
5994 static void
5997 {
6000 /* Unnamed 256bit vector mode parameters are passed on stack. */
6007 {
6012 }
6013 else
6015 }
6017 static void
6019 HOST_WIDE_INT words)
6020 {
6021 /* Otherwise, this should be passed indirect. */
6026 {
6029 }
6030 }
6032 void
6035 {
6040 else
6051 else
6053 }
6055 /* Define where to put the arguments to a function.
6056 Value is zero to push the argument on the stack,
6057 or a hard register in which to store the argument.
6059 MODE is the argument's machine mode.
6060 TYPE is the data type of the argument (as a tree).
6061 This is null for libcalls where that information may
6062 not be available.
6063 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6064 the preceding args and about the function being called.
6065 NAMED is nonzero if this argument is a named parameter
6066 (otherwise it is an extra parameter matching an ellipsis). */
6068 static rtx
6072 {
6075 /* Avoid the AL settings for the Unix64 ABI. */
6080 {
6087 /* FALLTHRU */
6093 {
6096 /* Fastcall allocates the first two DWORD (SImode) or
6097 smaller arguments to ECX and EDX if it isn't an
6098 aggregate type . */
6100 {
6106 /* ECX not EAX is the first allocated register. */
6109 }
6111 }
6120 /* FALLTHRU */
6122 /* In 32bit, we pass TImode in xmm registers. */
6130 {
6132 {
6136 }
6140 }
6144 /* OImode shouldn't be used directly. */
6154 {
6158 }
6168 {
6170 {
6174 }
6178 }
6180 }
6183 }
6185 static rtx
6188 {
6189 /* Handle a hidden AL argument containing number of registers
6190 for varargs x86-64 functions. */
6195 ? SSE_REGPARM_MAX
6197 ? X86_64_SSE_REGPARM_MAX
6203 {
6213 /* Unnamed 256bit vector mode parameters are passed on stack. */
6217 }
6223 }
6225 static rtx
6228 HOST_WIDE_INT bytes)
6229 {
6232 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6233 We use value of -2 to specify that current function call is MSABI. */
6237 /* If we've run out of registers, it goes on the stack. */
6243 /* Only floating point modes are passed in anything but integer regs. */
6245 {
6248 else
6249 {
6252 /* Unnamed floating parameters are passed in both the
6253 SSE and integer registers. */
6259 }
6260 }
6261 /* Handle aggregated types passed in register. */
6263 {
6268 }
6271 }
6273 rtx
6276 {
6282 else
6286 /* To simplify the code below, represent vector types with a vector mode
6287 even if MMX/SSE are not active. */
6295 else
6297 }
6299 /* A C expression that indicates when an argument must be passed by
6300 reference. If nonzero for an argument, a copy of that argument is
6301 made in memory and a pointer to the argument is passed instead of
6302 the argument itself. The pointer is passed in whatever way is
6303 appropriate for passing a pointer to that type. */
6305 static bool
6309 {
6310 /* See Windows x64 Software Convention. */
6312 {
6315 {
6316 /* Arrays are passed by reference. */
6321 {
6322 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6323 are passed by reference. */
6325 }
6326 }
6328 /* __m128 is passed by reference. */
6334 }
6335 }
6340 }
6342 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6343 ABI. */
6344 static bool
6346 {
6358 {
6359 /* Walk the aggregates recursively. */
6361 {
6365 {
6366 tree field;
6368 /* Walk all the structure fields. */
6370 {
6374 }
6376 }
6379 /* Just for use if some languages passes arrays by value. */
6386 }
6387 }
6389 }
6391 /* Gives the alignment boundary, in bits, of an argument with the
6392 specified mode and type. */
6394 int
6396 {
6399 {
6400 /* Since canonical type is used for call, we convert it to
6401 canonical type if needed. */
6405 }
6406 else
6410 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6411 natural boundaries. */
6413 {
6414 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6415 make an exception for SSE modes since these require 128bit
6416 alignment.
6418 The handling here differs from field_alignment. ICC aligns MMX
6419 arguments to 4 byte boundaries, while structure fields are aligned
6420 to 8 byte boundaries. */
6422 {
6425 }
6426 else
6427 {
6430 }
6431 }
6435 }
6437 /* Return true if N is a possible register number of function value. */
6439 static bool
6441 {
6443 {
6448 /* TODO: The function should depend on current function ABI but
6449 builtins.c would need updating then. Therefore we use the
6450 default ABI. */
6462 }
6465 }
6467 /* Define how to find the value returned by a function.
6468 VALTYPE is the data type of the value (as a tree).
6469 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6470 otherwise, FUNC is 0. */
6472 static rtx
6475 {
6478 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6479 we normally prevent this case when mmx is not available. However
6480 some ABIs may require the result to be returned like DImode. */
6484 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6485 we prevent this case when sse is not available. However some ABIs
6486 may require the result to be returned like integer TImode. */
6491 /* 32-byte vector modes in %ymm0. */
6495 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6498 else
6499 /* Most things go in %eax. */
6502 /* Override FP return register with %xmm0 for local functions when
6503 SSE math is enabled or for functions with sseregparm attribute. */
6505 {
6510 }
6512 /* OImode shouldn't be used directly. */
6516 }
6518 static rtx
6520 const_tree valtype)
6521 {
6522 rtx ret;
6524 /* Handle libcalls, which don't provide a type node. */
6526 {
6528 {
6545 }
6546 }
6552 /* For zero sized structures, construct_container returns NULL, but we
6553 need to keep rest of compiler happy by returning meaningful value. */
6558 }
6560 static rtx
6562 {
6566 {
6568 {
6581 }
6582 }
6584 }
6586 static rtx
6589 {
6601 else
6603 }
6605 static rtx
6608 {
6614 }
6616 rtx
6618 {
6620 }
6622 /* Return true iff type is returned in memory. */
6624 static int ATTRIBUTE_UNUSED
6626 {
6627 HOST_WIDE_INT size;
6638 {
6639 /* User-created vectors small enough to fit in EAX. */
6643 /* MMX/3dNow values are returned in MM0,
6644 except when it doesn't exits. */
6648 /* SSE values are returned in XMM0, except when it doesn't exist. */
6652 /* AVX values are returned in YMM0, except when it doesn't exist. */
6655 }
6663 /* OImode shouldn't be used directly. */
6667 }
6669 static int ATTRIBUTE_UNUSED
6671 {
6674 }
6676 static int ATTRIBUTE_UNUSED
6678 {
6681 /* __m128 is returned in xmm0. */
6686 /* Otherwise, the size must be exactly in [1248]. */
6688 }
6690 static bool
6692 {
6693 #ifdef SUBTARGET_RETURN_IN_MEMORY
6695 #else
6699 {
6702 else
6704 }
6705 else
6707 #endif
6708 }
6710 /* Return false iff TYPE is returned in memory. This version is used
6711 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6712 but differs notably in that when MMX is available, 8-byte vectors
6713 are returned in memory, rather than in MMX registers. */
6715 bool
6717 {
6730 {
6731 /* Return in memory only if MMX registers *are* available. This
6732 seems backwards, but it is consistent with the existing
6733 Solaris x86 ABI. */
6738 }
6745 }
6747 /* When returning SSE vector types, we have a choice of either
6748 (1) being abi incompatible with a -march switch, or
6749 (2) generating an error.
6750 Given no good solution, I think the safest thing is one warning.
6751 The user won't be able to use -Werror, but....
6753 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6754 called in response to actually generating a caller or callee that
6755 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6756 via aggregate_value_p for general type probing from tree-ssa. */
6758 static rtx
6760 {
6764 {
6765 /* Look at the return type of the function, not the function type. */
6769 {
6772 {
6776 }
6777 }
6780 {
6782 {
6786 }
6787 }
6788 }
6791 }
6793 \f
6794 /* Create the va_list data type. */
6796 /* Returns the calling convention specific va_list date type.
6797 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6799 static tree
6801 {
6804 /* For i386 we use plain pointer to argument area. */
6814 unsigned_type_node);
6817 unsigned_type_node);
6820 ptr_type_node);
6823 ptr_type_node);
6842 /* The correct type is an array type of one element. */
6844 }
6846 /* Setup the builtin va_list data type and for 64-bit the additional
6847 calling convention specific va_list data types. */
6849 static tree
6851 {
6854 /* Initialize abi specific va_list builtin types. */
6856 {
6857 tree t;
6859 {
6864 }
6865 else
6866 {
6871 }
6873 {
6878 }
6879 else
6880 {
6885 }
6886 }
6889 }
6891 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6893 static void
6895 {
6897 rtx label;
6898 rtx tmp_reg;
6899 rtx nsse_reg;
6900 alias_set_type set;
6908 /* GPR size of varargs save area. */
6911 else
6914 /* FPR size of varargs save area. We don't need it if we don't pass
6915 anything in SSE registers. */
6918 else
6928 i < regparm
6930 i++)
6931 {
6938 }
6941 {
6942 /* Now emit code to save SSE registers. The AX parameter contains number
6943 of SSE parameter registers used to call this function. We use
6944 sse_prologue_save insn template that produces computed jump across
6945 SSE saves. We need some preparation work to get this working. */
6952 /* Compute address of memory block we save into. We always use pointer
6953 pointing 127 bytes after first byte to store - this is needed to keep
6954 instruction size limited by 4 bytes (5 bytes for AVX) with one
6955 byte displacement. */
6965 /* And finally do the dirty job! */
6969 }
6970 }
6972 static void
6974 {
6979 {
6990 }
6991 }
6993 static void
6997 {
6998 CUMULATIVE_ARGS next_cum;
6999 tree fntype;
7001 /* This argument doesn't appear to be used anymore. Which is good,
7002 because the old code here didn't suppress rtl generation. */
7010 /* For varargs, we do not want to skip the dummy va_dcl argument.
7011 For stdargs, we do want to skip the last named argument. */
7018 else
7020 }
7022 /* Checks if TYPE is of kind va_list char *. */
7024 static bool
7026 {
7027 tree canonic;
7029 /* For 32-bit it is always true. */
7035 }
7037 /* Implement va_start. */
7039 static void
7041 {
7045 tree type;
7047 /* Only 64bit target needs something special. */
7049 {
7052 }
7065 /* Count number of gp and fp argument registers used. */
7071 {
7077 }
7080 {
7086 }
7088 /* Find the overflow area. */
7099 {
7100 /* Find the register save area.
7101 Prologue of the function save it right above stack frame. */
7110 }
7111 }
7113 /* Implement va_arg. */
7115 static tree
7118 {
7125 rtx container;
7127 tree ptrtype;
7131 /* Only 64bit target needs something special. */
7155 {
7162 /* Unnamed 256bit vector mode parameters are passed on stack. */
7164 {
7167 }
7175 }
7177 /* Pull the value out of the saved registers. */
7182 {
7196 /* In case we are passing structure, verify that it is consecutive block
7197 on the register save area. If not we need to do moves. */
7199 {
7200 /* Verify that all registers are strictly consecutive */
7202 {
7206 {
7211 }
7212 }
7213 else
7214 {
7218 {
7223 }
7224 }
7225 }
7227 {
7230 }
7231 else
7232 {
7235 }
7237 /* First ensure that we fit completely in registers. */
7239 {
7246 }
7248 {
7256 }
7258 /* Compute index to start of area used for integer regs. */
7260 {
7261 /* int_addr = gpr + sav; */
7265 }
7267 {
7268 /* sse_addr = fpr + sav; */
7272 }
7274 {
7278 /* addr = &temp; */
7283 {
7296 {
7299 }
7300 else
7301 {
7304 }
7316 }
7317 }
7320 {
7324 }
7327 {
7331 }
7336 }
7338 /* ... otherwise out of the overflow area. */
7340 /* When we align parameter on stack for caller, if the parameter
7341 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7342 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7343 here with caller. */
7348 /* Care for on-stack alignment if needed. */
7352 else
7353 {
7363 }
7380 }
7381 \f
7382 /* Return nonzero if OPNUM's MEM should be matched
7383 in movabs* patterns. */
7385 int
7387 {
7399 }
7400 \f
7401 /* Initialize the table of extra 80387 mathematical constants. */
7403 static void
7405 {
7407 {
7413 };
7417 {
7419 /* Ensure each constant is rounded to XFmode precision. */
7422 }
7425 }
7427 /* Return true if the constant is something that can be loaded with
7428 a special instruction. */
7430 int
7432 {
7435 REAL_VALUE_TYPE r;
7447 /* For XFmode constants, try to find a special 80387 instruction when
7448 optimizing for size or on those CPUs that benefit from them. */
7451 {
7460 }
7462 /* Load of the constant -0.0 or -1.0 will be split as
7463 fldz;fchs or fld1;fchs sequence. */
7470 }
7472 /* Return the opcode of the special instruction to be used to load
7473 the constant X. */
7477 {
7479 {
7499 }
7500 }
7502 /* Return the CONST_DOUBLE representing the 80387 constant that is
7503 loaded by the specified special instruction. The argument IDX
7504 matches the return value from standard_80387_constant_p. */
7506 rtx
7508 {
7515 {
7526 }
7529 XFmode);
7530 }
7532 /* Return 1 if X is all 0s and 2 if x is all 1s
7533 in supported SSE vector mode. */
7535 int
7537 {
7544 {
7553 }
7556 }
7558 /* Return the opcode of the special instruction to be used to load
7559 the constant X. */
7563 {
7565 {
7568 {
7574 else
7579 else
7586 else
7591 else
7595 }
7600 }
7602 }
7604 /* Returns 1 if OP contains a symbol reference */
7606 int
7608 {
7617 {
7619 {
7625 }
7629 }
7632 }
7634 /* Return 1 if it is appropriate to emit `ret' instructions in the
7635 body of a function. Do this only if the epilogue is simple, needing a
7636 couple of insns. Prior to reloading, we can't tell how many registers
7637 must be saved, so return 0 then. Return 0 if there is no frame
7638 marker to de-allocate. */
7640 int
7642 {
7648 /* Don't allow more than 32 pop, since that's all we can do
7649 with one instruction. */
7657 }
7658 \f
7659 /* Value should be nonzero if functions must have frame pointers.
7660 Zero means the frame pointer need not be set up (and parms may
7661 be accessed via the stack pointer) in functions that seem suitable. */
7663 static bool
7665 {
7666 /* If we accessed previous frames, then the generated code expects
7667 to be able to access the saved ebp value in our frame. */
7671 /* Several x86 os'es need a frame pointer for other reasons,
7672 usually pertaining to setjmp. */
7676 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7677 the frame pointer by default. Turn it back on now if we've not
7678 got a leaf function. */
7680 && (!current_function_is_leaf
7688 }
7690 /* Record that the current function accesses previous call frames. */
7692 void
7694 {
7696 }
7697 \f
7698 #ifndef USE_HIDDEN_LINKONCE
7699 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7700 # define USE_HIDDEN_LINKONCE 1
7701 # else
7702 # define USE_HIDDEN_LINKONCE 0
7703 # endif
7704 #endif
7708 /* Fills in the label name that should be used for a pc thunk for
7709 the given register. */
7711 static void
7713 {
7718 else
7720 }
7723 /* This function generates code for -fpic that loads %ebx with
7724 the return address of the caller and then returns. */
7726 static void
7728 {
7733 {
7735 tree decl;
7750 #if TARGET_MACHO
7752 {
7761 }
7762 else
7763 #endif
7765 {
7776 }
7777 else
7778 {
7781 }
7787 /* Make sure unwind info is emitted for the thunk if needed. */
7799 }
7800 }
7802 /* Emit code for the SET_GOT patterns. */
7806 {
7812 {
7813 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7818 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7819 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7820 an unadorned address. */
7825 }
7830 {
7835 else
7836 {
7838 #ifdef DWARF2_UNWIND_INFO
7839 /* The call to next label acts as a push. */
7841 {
7842 rtx insn;
7846 stack_pointer_rtx,
7851 }
7852 #endif
7853 }
7855 #if TARGET_MACHO
7856 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7857 is what will be referenced by the Mach-O PIC subsystem. */
7860 #endif
7866 {
7868 #ifdef DWARF2_UNWIND_INFO
7869 /* The pop is a pop and clobbers dest, but doesn't restore it
7870 for unwind info purposes. */
7872 {
7873 rtx insn;
7879 stack_pointer_rtx,
7884 }
7885 #endif
7886 }
7887 }
7888 else
7889 {
7894 #ifdef DWARF2_UNWIND_INFO
7895 /* Ensure all queued register saves are flushed before the
7896 call. */
7898 {
7899 rtx insn;
7904 }
7905 #endif
7909 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7910 is what will be referenced by the Mach-O PIC subsystem. */
7911 #if TARGET_MACHO
7914 else
7917 #endif
7918 }
7925 else
7929 }
7931 /* Generate an "push" pattern for input ARG. */
7933 static rtx
7935 {
7942 stack_pointer_rtx)),
7943 arg);
7944 }
7946 /* Return >= 0 if there is an unused call-clobbered register available
7947 for the entire function. */
7949 static unsigned int
7951 {
7954 {
7956 /* Can't use the same register for both PIC and DRAP. */
7959 else
7964 }
7967 }
7969 /* Return 1 if we need to save REGNO. */
7970 static int
7972 {
7979 {
7983 }
7986 {
7989 {
7995 }
7996 }
8005 }
8007 /* Return number of saved general prupose registers. */
8009 static int
8011 {
8017 nregs ++;
8019 }
8021 /* Return number of saved SSE registrers. */
8023 static int
8025 {
8033 nregs ++;
8035 }
8037 /* Given FROM and TO register numbers, say whether this elimination is
8038 allowed. If stack alignment is needed, we can only replace argument
8039 pointer with hard frame pointer, or replace frame pointer with stack
8040 pointer. Otherwise, frame pointer elimination is automatically
8041 handled and all other eliminations are valid. */
8043 static bool
8045 {
8051 else
8053 }
8055 /* Return the offset between two registers, one to be eliminated, and the other
8056 its replacement, at the start of a routine. */
8058 HOST_WIDE_INT
8060 {
8069 else
8070 {
8078 }
8079 }
8081 /* In a dynamically-aligned function, we can't know the offset from
8082 stack pointer to frame pointer, so we must ensure that setjmp
8083 eliminates fp against the hard fp (%ebp) rather than trying to
8084 index from %esp up to the top of the frame across a gap that is
8085 of unknown (at compile-time) size. */
8086 static rtx
8088 {
8090 }
8092 /* Fill structure ix86_frame about frame of currently computed function. */
8094 static void
8096 {
8098 HOST_WIDE_INT offset;
8108 /* MS ABI seem to require stack alignment to be always 16 except for function
8109 prologues. */
8111 {
8116 }
8122 /* During reload iteration the amount of registers saved can change.
8123 Recompute the value as needed. Do not recompute when amount of registers
8124 didn't change as reload does multiple calls to the function and does not
8125 expect the decision to change within single iteration. */
8128 {
8133 /* The fast prologue uses move instead of push to save registers. This
8134 is significantly longer, but also executes faster as modern hardware
8135 can execute the moves in parallel, but can't do that for push/pop.
8137 Be careful about choosing what prologue to emit: When function takes
8138 many instructions to execute we may use slow version as well as in
8139 case function is known to be outside hot spot (this is known with
8140 feedback only). Weight the size of function by number of registers
8141 to save as it is cheap to use one or two push instructions but very
8142 slow to use many of them. */
8146 || (flag_branch_probabilities
8149 else
8152 }
8156 else
8159 /* Skip return address. */
8162 /* Skip pushed static chain. */
8166 /* Skip saved base pointer. */
8172 /* Set offset to aligned because the realigned frame starts from
8173 here. */
8177 /* Register save area */
8180 /* Align SSE reg save area. */
8183 else
8186 /* SSE register save area. */
8189 /* Va-arg area */
8193 /* Align start of frame for local function. */
8199 /* Frame pointer points here. */
8204 /* Add outgoing arguments area. Can be skipped if we eliminated
8205 all the function calls as dead code.
8206 Skipping is however impossible when function calls alloca. Alloca
8207 expander assumes that last crtl->outgoing_args_size
8208 of stack frame are unused. */
8212 {
8215 }
8216 else
8219 /* Align stack boundary. Only needed if we're calling another function
8220 or using alloca. */
8225 else
8230 /* We've reached end of stack frame. */
8233 /* Size prologue needs to allocate. */
8243 && current_function_sp_is_unchanging
8244 && current_function_is_leaf
8246 {
8252 }
8253 else
8257 }
8259 /* Emit code to save registers in the prologue. */
8261 static void
8263 {
8265 rtx insn;
8269 {
8272 }
8273 }
8275 /* Emit code to save registers using MOV insns. First register
8276 is restored from POINTER + OFFSET. */
8277 static void
8279 {
8281 rtx insn;
8285 {
8291 }
8292 }
8294 /* Emit code to save registers using MOV insns. First register
8295 is restored from POINTER + OFFSET. */
8296 static void
8298 {
8300 rtx insn;
8301 rtx mem;
8305 {
8311 }
8312 }
8316 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8317 manipulation insn. Don't add it if the previously
8318 saved value will be left untouched within stack red-zone till return,
8319 as unwinders can find the same value in the register and
8320 on the stack. */
8322 static void
8324 {
8326 && !TARGET_64BIT_MS_ABI
8332 {
8335 }
8336 else
8337 queued_cfa_restores
8339 }
8341 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8343 static void
8345 {
8346 rtx last;
8350 ;
8355 }
8357 /* Expand prologue or epilogue stack adjustment.
8358 The pattern exist to put a dependency on all ebp-based memory accesses.
8359 STYLE should be negative if instructions should be marked as frame related,
8360 zero if %r11 register is live and cannot be freely used and positive
8361 otherwise. */
8363 static void
8366 {
8367 rtx insn;
8373 else
8374 {
8375 rtx r11;
8376 /* r11 is used by indirect sibcall return as well, set before the
8377 epilogue and used after the epilogue. ATM indirect sibcall
8378 shouldn't be used together with huge frame sizes in one
8379 function because of the frame_size check in sibcall.c. */
8386 offset));
8387 }
8393 {
8394 rtx r;
8404 }
8407 }
8409 /* Find an available register to be used as dynamic realign argument
8410 pointer regsiter. Such a register will be written in prologue and
8411 used in begin of body, so it must not be
8412 1. parameter passing register.
8413 2. GOT pointer.
8414 We reuse static-chain register if it is available. Otherwise, we
8415 use DI for i386 and R13 for x86-64. We chose R13 since it has
8416 shorter encoding.
8418 Return: the regno of chosen register. */
8420 static unsigned int
8422 {
8426 {
8427 /* Use R13 for nested function or function need static chain.
8428 Since function with tail call may use any caller-saved
8429 registers in epilogue, DRAP must not use caller-saved
8430 register in such case. */
8435 }
8436 else
8437 {
8438 /* Use DI for nested function or function need static chain.
8439 Since function with tail call may use any caller-saved
8440 registers in epilogue, DRAP must not use caller-saved
8441 register in such case. */
8445 /* Reuse static chain register if it isn't used for parameter
8446 passing. */
8453 else
8455 }
8456 }
8458 /* Return minimum incoming stack alignment. */
8460 static unsigned int
8462 {
8465 /* Prefer the one specified at command line. */
8468 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8469 if -mstackrealign is used, it isn't used for sibcall check and
8470 estimated stack alignment is 128bit. */
8472 && !TARGET_64BIT
8473 && ix86_force_align_arg_pointer
8476 else
8479 /* Incoming stack alignment can be changed on individual functions
8480 via force_align_arg_pointer attribute. We use the smallest
8481 incoming stack boundary. */
8487 /* The incoming stack frame has to be aligned at least at
8488 parm_stack_boundary. */
8492 /* Stack at entrance of main is aligned by runtime. We use the
8493 smallest incoming stack boundary. */
8501 }
8503 /* Update incoming stack boundary and estimated stack alignment. */
8505 static void
8507 {
8508 ix86_incoming_stack_boundary
8511 /* x86_64 vararg needs 16byte stack alignment for register save
8512 area. */
8517 }
8519 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8520 needed or an rtx for DRAP otherwise. */
8522 static rtx
8524 {
8529 {
8530 /* Assign DRAP to vDRAP and returns vDRAP */
8532 rtx drap_vreg;
8533 rtx arg_ptr;
8546 {
8549 }
8551 }
8552 else
8554 }
8556 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8558 static rtx
8560 {
8562 }
8564 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8565 to be generated in correct form. */
8566 static void
8568 {
8569 /* Check if stack realign is really needed after reload, and
8570 stores result in cfun */
8571 unsigned int incoming_stack_boundary
8575 < (current_function_is_leaf
8580 {
8581 /* After stack_realign_needed is finalized, we can't no longer
8582 change it. */
8584 }
8585 else
8586 {
8589 }
8590 }
8592 /* Expand the prologue into a bunch of separate insns. */
8594 void
8596 {
8597 rtx insn;
8600 HOST_WIDE_INT allocate;
8605 /* DRAP should not coexist with stack_realign_fp */
8608 /* Initialize CFA state for before the prologue. */
8615 {
8618 /* Make sure the function starts with
8619 8b ff movl.s %edi,%edi
8620 55 push %ebp
8621 8b ec movl.s %esp,%ebp
8623 This matches the hookable function prologue in Win32 API
8624 functions in Microsoft Windows XP Service Pack 2 and newer.
8625 Wine uses this to enable Windows apps to hook the Win32 API
8626 functions provided by Wine. */
8631 stack_pointer_rtx));
8635 {
8636 /* The push %ebp and movl.s %esp, %ebp already set up
8637 the frame pointer. No need to do this again. */
8643 }
8644 else
8645 /* If the frame pointer is not needed, pop %ebp again. This
8646 could be optimized for cases where ebp needs to be backed up
8647 for some other reason. If stack realignment is needed, pop
8648 the base pointer again, align the stack, and later regenerate
8649 the frame pointer setup. The frame pointer generated by the
8650 hook prologue is not aligned, so it can't be used. */
8652 }
8654 /* The first insn of a function that accepts its static chain on the
8655 stack is to push the register that would be filled in by a direct
8656 call. This insn will be skipped by the trampoline. */
8658 {
8659 rtx t;
8664 /* We don't want to interpret this push insn as a register save,
8665 only as a stack adjustment. The real copy of the register as
8666 a save will be done later, if needed. */
8671 }
8673 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8674 of DRAP is needed and stack realignment is really needed after reload */
8676 {
8688 /* Grab the argument pointer. */
8692 /* Only need to push parameter pointer reg if it is caller
8693 saved reg */
8695 {
8696 /* Push arg pointer reg */
8699 }
8705 /* Align the stack. */
8707 stack_pointer_rtx,
8711 /* Replicate the return address on the stack so that return
8712 address can be reached via (argp - 1) slot. This is needed
8713 to implement macro RETURN_ADDR_RTX and intrinsic function
8714 expand_builtin_return_addr etc. */
8720 }
8722 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8723 slower on all targets. Also sdb doesn't like it. */
8726 {
8735 }
8738 {
8742 /* Align the stack. */
8744 stack_pointer_rtx,
8747 }
8753 else
8756 /* When using red zone we may start register saving before allocating
8757 the stack frame saving one cycle of the prologue. However I will
8758 avoid doing this if I am going to have to probe the stack since
8759 at least on x86_64 the stack probe can turn into a call that clobbers
8760 a red zone location */
8765 ? hard_frame_pointer_rtx
8770 ;
8775 else
8776 {
8779 rtx t;
8783 else
8787 {
8790 }
8796 else
8801 {
8807 }
8810 {
8813 allocate
8816 else
8819 }
8820 }
8825 {
8830 frame.to_allocate
8832 else
8835 }
8841 else
8851 {
8858 }
8861 {
8863 {
8865 {
8875 }
8876 else
8878 }
8879 else
8881 }
8883 /* In the pic_reg_used case, make sure that the got load isn't deleted
8884 when mcount needs it. Blockage to avoid call movement across mcount
8885 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8886 note. */
8891 {
8892 /* vDRAP is setup but after reload it turns out stack realign
8893 isn't necessary, here we will emit prologue to setup DRAP
8894 without stack realign adjustment */
8895 rtx x;
8902 }
8904 /* Prevent instructions from being scheduled into register save push
8905 sequence when access to the redzone area is done through frame pointer.
8906 The offset between the frame pointer and the stack pointer is calculated
8907 relative to the value of the stack pointer at the end of the function
8908 prologue, and moving instructions that access redzone area via frame
8909 pointer inside push sequence violates this assumption. */
8913 /* Emit cld instruction if stringops are used in the function. */
8916 }
8918 /* Emit code to restore REG using a POP insn. */
8920 static void
8922 {
8927 {
8928 /* Previously we'd represented the CFA as an expression
8929 like *(%ebp - 8). We've just popped that value from
8930 the stack, which means we need to reset the CFA to
8931 the drap register. This will remain until we restore
8932 the stack pointer. */
8936 }
8939 {
8944 }
8946 /* When the frame pointer is the CFA, and we pop it, we are
8947 swapping back to the stack pointer as the CFA. This happens
8948 for stack frames that don't allocate other data, so we assume
8949 the stack pointer is now pointing at the return address, i.e.
8950 the function entry state, which makes the offset be 1 word. */
8953 {
8961 }
8964 }
8966 /* Emit code to restore saved registers using POP insns. */
8968 static void
8970 {
8975 {
8977 red_offset);
8979 }
8980 }
8982 /* Emit code and notes for the LEAVE instruction. */
8984 static void
8986 {
8992 {
9000 }
9001 }
9003 /* Emit code to restore saved registers using MOV insns. First register
9004 is restored from POINTER + OFFSET. */
9005 static void
9007 HOST_WIDE_INT red_offset,
9009 {
9012 rtx insn;
9016 {
9019 /* Ensure that adjust_address won't be forced to produce pointer
9020 out of range allowed by x86-64 instruction set. */
9022 {
9023 rtx r11;
9030 }
9037 {
9038 /* Previously we'd represented the CFA as an expression
9039 like *(%ebp - 8). We've just popped that value from
9040 the stack, which means we need to reset the CFA to
9041 the drap register. This will remain until we restore
9042 the stack pointer. */
9045 }
9046 else
9050 }
9051 }
9053 /* Emit code to restore saved registers using MOV insns. First register
9054 is restored from POINTER + OFFSET. */
9055 static void
9057 HOST_WIDE_INT red_offset,
9059 {
9062 rtx mem;
9066 {
9069 /* Ensure that adjust_address won't be forced to produce pointer
9070 out of range allowed by x86-64 instruction set. */
9072 {
9073 rtx r11;
9080 }
9089 }
9090 }
9092 /* Restore function stack, frame, and registers. */
9094 void
9096 {
9105 /* When stack is realigned, SP must be valid. */
9106 sp_valid = (!frame_pointer_needed
9107 || current_function_sp_is_unchanging
9112 /* See the comment about red zone and frame
9113 pointer usage in ix86_expand_prologue. */
9120 /* Calculate start of saved registers relative to ebp. Special care
9121 must be taken for the normal return case of a function using
9122 eh_return: the eax and edx registers are marked as saved, but not
9123 restored along this path. */
9130 /* Calculate start of saved registers relative to esp on entry of the
9131 function. When realigning stack, this needs to be the most negative
9132 value possible at runtime. */
9145 /* If we're only restoring one register and sp is not valid then
9146 using a move instruction to restore the register since it's
9147 less work than reloading sp and popping the register.
9149 The default code result in stack adjustment using add/lea instruction,
9150 while this code results in LEAVE instruction (or discrete equivalent),
9151 so it is profitable in some other cases as well. Especially when there
9152 are no registers to restore. We also use this code when TARGET_USE_LEAVE
9153 and there is exactly one register to pop. This heuristic may need some
9154 tuning in future. */
9156 || (TARGET_EPILOGUE_USING_MOVE
9166 {
9167 /* Restore registers. We can use ebp or esp to address the memory
9168 locations. If both are available, default to ebp, since offsets
9169 are known to be small. Only exception is esp pointing directly
9170 to the end of block of saved registers, where we may simplify
9171 addressing mode.
9173 If we are realigning stack with bp and sp, regs restore can't
9174 be addressed by bp. sp must be used instead. */
9179 {
9184 frame.to_allocate
9187 red_offset
9190 }
9191 else
9192 {
9197 offset
9200 red_offset
9203 }
9207 /* eh_return epilogues need %ecx added to the stack pointer. */
9209 {
9212 /* Stack align doesn't work with eh_return. */
9214 /* Neither does regparm nested functions. */
9218 {
9226 /* Note that we use SA as a temporary CFA, as the return
9227 address is at the proper place relative to it. We
9228 pretend this happens at the FP restore insn because
9229 prior to this insn the FP would be stored at the wrong
9230 offset relative to SA, and after this insn we have no
9231 other reasonable register to use for the CFA. We don't
9232 bother resetting the CFA to the SP for the duration of
9233 the return insn. */
9244 }
9245 else
9246 {
9257 {
9261 UNITS_PER_WORD));
9263 }
9264 }
9265 }
9273 /* If not an i386, mov & pop is faster than "leave". */
9277 else
9278 {
9280 hard_frame_pointer_rtx,
9284 }
9285 }
9286 else
9287 {
9288 /* First step is to deallocate the stack frame so that we can
9289 pop the registers.
9291 If we realign stack with frame pointer, then stack pointer
9292 won't be able to recover via lea $offset(%bp), %sp, because
9293 there is a padding area between bp and sp for realign.
9294 "add $to_allocate, %sp" must be used instead. */
9296 {
9300 hard_frame_pointer_rtx,
9309 }
9311 {
9320 }
9327 {
9328 /* Leave results in shorter dependency chains on CPUs that are
9329 able to grok it fast. */
9332 else
9333 {
9334 /* For stack realigned really happens, recover stack
9335 pointer to hard frame pointer is a must, if not using
9336 leave. */
9339 hard_frame_pointer_rtx,
9342 red_offset);
9343 }
9344 }
9345 }
9348 {
9350 rtx insn;
9373 }
9375 /* Remove the saved static chain from the stack. The use of ECX is
9376 merely as a scratch register, not as the actual static chain. */
9378 {
9391 }
9393 /* Sibcall epilogues don't want a return instruction. */
9395 {
9398 }
9401 {
9404 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9405 address, do explicit add, and jump indirectly to the caller. */
9408 {
9410 rtx insn;
9412 /* There is no "pascal" calling convention in any 64bit ABI. */
9427 }
9428 else
9430 }
9431 else
9434 /* Restore the state back to the state from the prologue,
9435 so that it's correct for the next epilogue. */
9437 }
9439 /* Reset from the function's potential modifications. */
9441 static void
9443 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9444 {
9447 #if TARGET_MACHO
9448 /* Mach-O doesn't support labels at the end of objects, so if
9449 it looks like we might want one, insert a NOP. */
9450 {
9461 }
9462 #endif
9464 }
9465 \f
9466 /* Extract the parts of an RTL expression that is a valid memory address
9467 for an instruction. Return 0 if the structure of the address is
9468 grossly off. Return -1 if the address contains ASHIFT, so it is not
9469 strictly valid, but still used for computing length of lea instruction. */
9471 int
9473 {
9478 rtx tmp;
9485 {
9490 do
9491 {
9496 }
9503 {
9506 {
9529 && TARGET_TLS_DIRECT_SEG_REFS
9532 else
9542 else
9557 }
9558 }
9559 }
9561 {
9564 }
9566 {
9567 /* We're called for lea too, which implements ashift on occasion. */
9577 }
9578 else
9581 /* Extract the integral value of scale. */
9583 {
9587 }
9592 /* Avoid useless 0 displacement. */
9596 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9601 {
9602 rtx tmp;
9605 }
9607 /* Special case: %ebp cannot be encoded as a base without a displacement.
9608 Similarly %r13. */
9610 && base_reg
9619 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9620 Avoid this by transforming to [%esi+0].
9621 Reload calls address legitimization without cfun defined, so we need
9622 to test cfun for being non-NULL. */
9629 /* Special case: encode reg+reg instead of reg*2. */
9633 /* Special case: scaling cannot be encoded without base or displacement. */
9644 }
9645 \f
9646 /* Return cost of the memory address x.
9647 For i386, it is better to use a complex address than let gcc copy
9648 the address into a reg and make a new pseudo. But not if the address
9649 requires to two regs - that would mean more pseudos with longer
9650 lifetimes. */
9651 static int
9653 {
9665 /* Attempt to minimize number of registers in the address. */
9671 cost++;
9678 cost++;
9680 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9681 since it's predecode logic can't detect the length of instructions
9682 and it degenerates to vector decoded. Increase cost of such
9683 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9684 to split such addresses or even refuse such addresses at all.
9686 Following addressing modes are affected:
9687 [base+scale*index]
9688 [scale*index+disp]
9689 [base+index]
9691 The first and last case may be avoidable by explicitly coding the zero in
9692 memory address, but I don't have AMD-K6 machine handy to check this
9693 theory. */
9702 }
9703 \f
9704 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9705 this is used for to form addresses to local data when -fPIC is in
9706 use. */
9708 static bool
9710 {
9713 }
9715 /* Determine if a given RTX is a valid constant. We already know this
9716 satisfies CONSTANT_P. */
9718 bool
9720 {
9722 {
9727 {
9731 }
9736 /* Only some unspecs are valid as "constants". */
9739 {
9755 }
9757 /* We must have drilled down to a symbol. */
9762 /* FALLTHRU */
9765 /* TLS symbols are never valid. */
9769 /* DLLIMPORT symbols are never valid. */
9788 }
9790 /* Otherwise we handle everything else in the move patterns. */
9792 }
9794 /* Determine if it's legal to put X into the constant pool. This
9795 is not possible for the address of thread-local symbols, which
9796 is checked above. */
9798 static bool
9800 {
9801 /* We can always put integral constants and vectors in memory. */
9803 {
9811 }
9813 }
9816 /* Nonzero if the constant value X is a legitimate general operand
9817 when generating PIC code. It is given that flag_pic is on and
9818 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9820 bool
9822 {
9823 rtx inner;
9826 {
9833 /* Only some unspecs are valid as "constants". */
9836 {
9849 }
9850 /* FALLTHRU */
9858 }
9859 }
9861 /* Determine if a given CONST RTX is a valid memory displacement
9862 in PIC mode. */
9864 int
9866 {
9869 /* In 64bit mode we can allow direct addresses of symbols and labels
9870 when they are not dynamic symbols. */
9872 {
9876 {
9893 /* FALLTHRU */
9896 /* TLS references should always be enclosed in UNSPEC. */
9906 }
9907 }
9913 {
9914 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9915 of GOT tables. We should not need these anyway. */
9926 }
9930 {
9935 }
9944 {
9948 /* We need to check for both symbols and labels because VxWorks loads
9949 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9950 details. */
9954 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9955 While ABI specify also 32bit relocation but we don't produce it in
9956 small PIC model at all. */
9978 }
9981 }
9983 /* Recognizes RTL expressions that are valid memory addresses for an
9984 instruction. The MODE argument is the machine mode for the MEM
9985 expression that wants to use this address.
9987 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9988 convert common non-canonical forms to canonical form so that they will
9989 be recognized. */
9991 static bool
9994 {
9997 HOST_WIDE_INT scale;
10000 /* Decomposition failed. */
10008 /* Validate base register.
10010 Don't allow SUBREG's that span more than a word here. It can lead to spill
10011 failures when the base is one word out of a two word structure, which is
10012 represented internally as a DImode int. */
10015 {
10016 rtx reg;
10025 else
10026 /* Base is not a register. */
10030 /* Base is not in Pmode. */
10035 /* Base is not valid. */
10037 }
10039 /* Validate index register.
10041 Don't allow SUBREG's that span more than a word here -- same as above. */
10044 {
10045 rtx reg;
10054 else
10055 /* Index is not a register. */
10059 /* Index is not in Pmode. */
10064 /* Index is not valid. */
10066 }
10068 /* Validate scale factor. */
10070 {
10072 /* Scale without index. */
10076 /* Scale is not a valid multiplier. */
10078 }
10080 /* Validate displacement. */
10082 {
10087 {
10088 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
10089 used. While ABI specify also 32bit relocations, we don't produce
10090 them at all and use IP relative instead. */
10097 /* 64bit address unspec. */
10112 /* Invalid address unspec. */
10114 }
10117 && (flag_pic
10118 || (TARGET_MACHO
10119 #if TARGET_MACHO
10120 && MACHOPIC_INDIRECT
10122 #endif
10123 )))
10124 {
10126 is_legitimate_pic:
10128 {
10129 /* foo@dtpoff(%rX) is ok. */
10136 /* Non-constant pic memory reference. */
10138 }
10140 /* Displacement is an invalid pic construct. */
10143 /* This code used to verify that a symbolic pic displacement
10144 includes the pic_offset_table_rtx register.
10146 While this is good idea, unfortunately these constructs may
10147 be created by "adds using lea" optimization for incorrect
10148 code like:
10150 int a;
10151 int foo(int i)
10152 {
10153 return *(&a+i);
10154 }
10156 This code is nonsensical, but results in addressing
10157 GOT table with pic_offset_table_rtx base. We can't
10158 just refuse it easily, since it gets matched by
10159 "addsi3" pattern, that later gets split to lea in the
10160 case output register differs from input. While this
10161 can be handled by separate addsi pattern for this case
10162 that never results in lea, this seems to be easier and
10163 correct fix for crash to disable this test. */
10164 }
10171 /* Displacement is not constant. */
10175 /* Displacement is out of range. */
10177 }
10179 /* Everything looks valid. */
10181 }
10183 /* Determine if a given RTX is a valid constant address. */
10185 bool
10187 {
10189 }
10190 \f
10191 /* Return a unique alias set for the GOT. */
10193 static alias_set_type
10195 {
10200 }
10202 /* Return a legitimate reference for ORIG (an address) using the
10203 register REG. If REG is 0, a new pseudo is generated.
10205 There are two types of references that must be handled:
10207 1. Global data references must load the address from the GOT, via
10208 the PIC reg. An insn is emitted to do this load, and the reg is
10209 returned.
10211 2. Static data references, constant pool addresses, and code labels
10212 compute the address as an offset from the GOT, whose base is in
10213 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
10214 differentiate them from global data objects. The returned
10215 address is the PIC reg + an unspec constant.
10217 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
10218 reg also appears in the address. */
10220 static rtx
10222 {
10225 rtx base;
10227 #if TARGET_MACHO
10229 {
10232 /* Use the generic Mach-O PIC machinery. */
10234 }
10235 #endif
10242 {
10243 rtx tmpreg;
10244 /* This symbol may be referenced via a displacement from the PIC
10245 base address (@GOTOFF). */
10252 {
10254 UNSPEC_GOTOFF);
10256 }
10257 else
10262 else
10267 {
10271 }
10273 }
10275 {
10276 /* This symbol may be referenced via a displacement from the PIC
10277 base address (@GOTOFF). */
10284 {
10286 UNSPEC_GOTOFF);
10288 }
10289 else
10295 {
10298 }
10299 }
10301 /* We can't use @GOTOFF for text labels on VxWorks;
10302 see gotoff_operand. */
10304 {
10306 {
10312 {
10315 }
10316 }
10319 {
10327 /* Use directly gen_movsi, otherwise the address is loaded
10328 into register for CSE. We don't want to CSE this addresses,
10329 instead we CSE addresses from the GOT table, so skip this. */
10332 }
10333 else
10334 {
10335 /* This symbol must be referenced via a load from the
10336 Global Offset Table (@GOT). */
10352 }
10353 }
10354 else
10355 {
10358 {
10360 {
10363 }
10364 else
10366 }
10368 {
10371 /* We must match stuff we generate before. Assume the only
10372 unspecs that can get here are ours. Not that we could do
10373 anything with them anyway.... */
10379 }
10381 {
10384 /* Check first to see if this is a constant offset from a @GOTOFF
10385 symbol reference. */
10388 {
10390 {
10394 UNSPEC_GOTOFF);
10400 {
10403 }
10404 }
10405 else
10406 {
10409 {
10413 }
10414 }
10415 }
10416 else
10417 {
10424 else
10425 {
10427 {
10430 }
10432 }
10433 }
10434 }
10435 }
10437 }
10438 \f
10439 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10441 static rtx
10443 {
10455 }
10457 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10458 false if we expect this to be used for a memory address and true if
10459 we expect to load the address into a register. */
10461 static rtx
10463 {
10468 {
10474 {
10484 }
10487 else
10491 {
10495 }
10503 {
10515 }
10518 else
10522 {
10527 }
10535 {
10539 }
10545 {
10548 }
10550 {
10555 }
10557 {
10561 }
10562 else
10563 {
10566 }
10576 {
10580 }
10581 else
10582 {
10586 }
10596 {
10599 }
10600 else
10601 {
10605 }
10610 }
10613 }
10615 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10616 to symbol DECL. */
10619 htab_t dllimport_map;
10621 static tree
10623 {
10630 tree to;
10631 rtx rtl;
10675 }
10677 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10678 true if we require the result be a register. */
10680 static rtx
10682 {
10683 tree imp_decl;
10684 rtx x;
10693 }
10695 /* Try machine-dependent ways of modifying an illegitimate address
10696 to be legitimate. If we find one, return the new, valid address.
10697 This macro is used in only one place: `memory_address' in explow.c.
10699 OLDX is the address as it was before break_out_memory_refs was called.
10700 In some cases it is useful to look at this to decide what needs to be done.
10702 It is always safe for this macro to do nothing. It exists to recognize
10703 opportunities to optimize the output.
10705 For the 80386, we handle X+REG by loading X into a register R and
10706 using R+REG. R will go in a general reg and indexing will be used.
10707 However, if REG is a broken-out memory address or multiplication,
10708 nothing needs to be done because REG can certainly go in a general reg.
10710 When -fpic is used, special handling is needed for symbolic references.
10711 See comments by legitimize_pic_address in i386.c for details. */
10713 static rtx
10716 {
10727 {
10731 }
10734 {
10741 {
10744 }
10745 }
10750 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10754 {
10759 }
10762 {
10763 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10768 {
10774 }
10779 {
10785 }
10787 /* Put multiply first if it isn't already. */
10789 {
10794 }
10796 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10797 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10798 created by virtual register instantiation, register elimination, and
10799 similar optimizations. */
10801 {
10807 }
10809 /* Canonicalize
10810 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10811 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10816 {
10817 rtx constant;
10821 {
10824 }
10826 {
10829 }
10830 else
10834 {
10840 }
10841 }
10847 {
10850 }
10853 {
10856 }
10864 {
10867 }
10873 {
10881 }
10884 {
10892 }
10893 }
10896 }
10897 \f
10898 /* Print an integer constant expression in assembler syntax. Addition
10899 and subtraction are the only arithmetic that may appear in these
10900 expressions. FILE is the stdio stream to write to, X is the rtx, and
10901 CODE is the operand print code from the output string. */
10903 static void
10905 {
10909 {
10918 else
10919 {
10922 /* Mark the decl as referenced so that cgraph will
10923 output the function. */
10927 #if TARGET_MACHO
10931 #endif
10933 }
10941 /* FALLTHRU */
10952 /* This used to output parentheses around the expression,
10953 but that does not work on the 386 (either ATT or BSD assembler). */
10959 {
10960 /* We can use %d if the number is <32 bits and positive. */
10965 else
10967 }
10968 else
10969 /* We can't handle floating point constants;
10970 PRINT_OPERAND must handle them. */
10975 /* Some assemblers need integer constants to appear first. */
10977 {
10981 }
10982 else
10983 {
10988 }
11005 {
11020 /* FIXME: This might be @TPOFF in Sun ld too. */
11029 else
11039 else
11045 #if TARGET_MACHO
11050 #endif
11054 }
11059 }
11060 }
11062 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11063 We need to emit DTP-relative relocations. */
11065 static void ATTRIBUTE_UNUSED
11067 {
11072 {
11080 }
11081 }
11083 /* Return true if X is a representation of the PIC register. This copes
11084 with calls from ix86_find_base_term, where the register might have
11085 been replaced by a cselib value. */
11087 static bool
11089 {
11093 else
11095 }
11097 /* In the name of slightly smaller debug output, and to cater to
11098 general assembler lossage, recognize PIC+GOTOFF and turn it back
11099 into a direct symbol reference.
11101 On Darwin, this is necessary to avoid a crash, because Darwin
11102 has a different PIC label for each routine but the DWARF debugging
11103 information is not associated with any particular routine, so it's
11104 necessary to remove references to the PIC label from RTL stored by
11105 the DWARF output code. */
11107 static rtx
11109 {
11111 /* addend is NULL or some rtx if x is something+GOTOFF where
11112 something doesn't include the PIC register. */
11114 /* reg_addend is NULL or a multiple of some register. */
11116 /* const_addend is NULL or a const_int. */
11118 /* This is the result, or NULL. */
11127 {
11137 }
11144 /* %ebx + GOT/GOTOFF */
11145 ;
11147 {
11148 /* %ebx + %reg * scale + GOT/GOTOFF */
11154 else
11155 {
11158 }
11159 }
11160 else
11166 {
11169 }
11188 {
11189 /* If the rest of original X doesn't involve the PIC register, add
11190 addend and subtract pic_offset_table_rtx. This can happen e.g.
11191 for code like:
11192 leal (%ebx, %ecx, 4), %ecx
11193 ...
11194 movl foo@GOTOFF(%ecx), %edx
11195 in which case we return (%ecx - %ebx) + foo. */
11198 pic_offset_table_rtx),
11199 result);
11200 else
11202 }
11206 }
11208 /* If X is a machine specific address (i.e. a symbol or label being
11209 referenced as a displacement from the GOT implemented using an
11210 UNSPEC), then return the base term. Otherwise return X. */
11212 rtx
11214 {
11215 rtx term;
11218 {
11231 }
11234 }
11235 \f
11236 static void
11239 {
11243 {
11246 }
11251 {
11254 {
11273 }
11277 {
11296 }
11303 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
11304 Those same assemblers have the same but opposite lossage on cmov. */
11309 else
11314 {
11327 }
11335 {
11348 }
11351 /* ??? As above. */
11360 /* ??? As above. */
11365 else
11376 }
11378 }
11380 /* Print the name of register X to FILE based on its machine mode and number.
11381 If CODE is 'w', pretend the mode is HImode.
11382 If CODE is 'b', pretend the mode is QImode.
11383 If CODE is 'k', pretend the mode is SImode.
11384 If CODE is 'q', pretend the mode is DImode.
11385 If CODE is 'x', pretend the mode is V4SFmode.
11386 If CODE is 't', pretend the mode is V8SFmode.
11387 If CODE is 'h', pretend the reg is the 'high' byte register.
11388 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11389 If CODE is 'd', duplicate the operand for AVX instruction.
11390 */
11392 void
11394 {
11409 {
11413 }
11431 else
11434 /* Irritatingly, AMD extended registers use different naming convention
11435 from the normal registers. */
11437 {
11440 {
11459 }
11461 }
11465 {
11468 {
11471 }
11472 /* FALLTHRU */
11478 /* FALLTHRU */
11481 normal:
11496 {
11501 }
11505 }
11509 {
11512 else
11514 }
11515 }
11517 /* Locate some local-dynamic symbol still in use by this function
11518 so that we can print its name in some tls_local_dynamic_base
11519 pattern. */
11521 static int
11523 {
11528 {
11531 }
11534 }
11538 {
11539 rtx insn;
11550 }
11552 /* Meaning of CODE:
11553 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11554 C -- print opcode suffix for set/cmov insn.
11555 c -- like C, but print reversed condition
11556 F,f -- likewise, but for floating-point.
11557 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11558 otherwise nothing
11559 R -- print the prefix for register names.
11560 z -- print the opcode suffix for the size of the current operand.
11561 Z -- likewise, with special suffixes for x87 instructions.
11562 * -- print a star (in certain assembler syntax)
11563 A -- print an absolute memory reference.
11564 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11565 s -- print a shift double count, followed by the assemblers argument
11566 delimiter.
11567 b -- print the QImode name of the register for the indicated operand.
11568 %b0 would print %al if operands[0] is reg 0.
11569 w -- likewise, print the HImode name of the register.
11570 k -- likewise, print the SImode name of the register.
11571 q -- likewise, print the DImode name of the register.
11572 x -- likewise, print the V4SFmode name of the register.
11573 t -- likewise, print the V8SFmode name of the register.
11574 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11575 y -- print "st(0)" instead of "st" as a register.
11576 d -- print duplicated register operand for AVX instruction.
11577 D -- print condition for SSE cmp instruction.
11578 P -- if PIC, print an @PLT suffix.
11579 X -- don't print any sort of PIC '@' suffix for a symbol.
11580 & -- print some in-use local-dynamic symbol name.
11581 H -- print a memory address offset by 8; used for sse high-parts
11582 Y -- print condition for XOP pcom* instruction.
11583 + -- print a branch hint as 'cs' or 'ds' prefix
11584 ; -- print a semicolon (after prefixes due to bug in older gas).
11585 */
11587 void
11589 {
11591 {
11593 {
11600 {
11605 else
11608 }
11612 {
11618 /* Intel syntax. For absolute addresses, registers should not
11619 be surrounded by braces. */
11621 {
11626 }
11631 }
11669 {
11670 /* Opcodes don't get size suffixes if using Intel opcodes. */
11675 {
11693 output_operand_lossage
11696 }
11697 }
11700 warning
11702 /* FALLTHRU */
11705 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11710 {
11712 {
11714 #ifdef HAVE_AS_IX86_FILDS
11716 #endif
11724 #ifdef HAVE_AS_IX86_FILDQ
11726 #else
11728 #endif
11733 }
11734 }
11736 {
11737 /* 387 opcodes don't get size suffixes
11738 if the operands are registers. */
11743 {
11759 }
11760 }
11761 else
11762 {
11763 output_operand_lossage
11766 }
11768 output_operand_lossage
11787 {
11790 }
11794 /* Little bit of braindamage here. The SSE compare instructions
11795 does use completely different names for the comparisons that the
11796 fp conditional moves. */
11798 {
11800 {
11847 }
11848 }
11849 else
11850 {
11852 {
11887 }
11888 }
11891 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11893 {
11895 {
11902 }
11904 }
11905 #endif
11909 {
11911 "condition code, invalid operand code "
11914 }
11919 {
11921 "condition code, invalid operand code "
11924 }
11925 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11928 #endif
11932 /* Like above, but reverse condition */
11934 /* Check to see if argument to %c is really a constant
11935 and not a condition code which needs to be reversed. */
11937 {
11939 "condition code, invalid operand "
11942 }
11947 {
11949 "condition code, invalid operand "
11952 }
11953 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11956 #endif
11961 /* It doesn't actually matter what mode we use here, as we're
11962 only going to use this for printing. */
11967 {
11968 rtx x;
11976 {
11981 {
11985 /* Emit hints only in the case default branch prediction
11986 heuristics would fail. */
11988 {
11989 /* We use 3e (DS) prefix for taken branches and
11990 2e (CS) prefix for not taken branches. */
11993 else
11995 }
11996 }
11997 }
11999 }
12003 {
12054 }
12058 #if TARGET_MACHO || !HAVE_AS_IX86_REP_LOCK_PREFIX
12060 #endif
12065 }
12066 }
12072 {
12073 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
12076 {
12079 {
12088 else
12094 }
12096 /* Check for explicit size override (codes 'b', 'w' and 'k') */
12106 }
12109 /* Avoid (%rip) for call operands. */
12115 else
12117 }
12120 {
12121 REAL_VALUE_TYPE r;
12130 }
12132 /* These float cases don't actually occur as immediate operands. */
12134 {
12139 }
12143 {
12148 }
12150 else
12151 {
12152 /* We have patterns that allow zero sets of memory, for instance.
12153 In 64-bit mode, we should probably support all 8-byte vectors,
12154 since we can in fact encode that into an immediate. */
12156 {
12159 }
12162 {
12164 {
12167 }
12170 {
12173 else
12175 }
12176 }
12181 else
12183 }
12184 }
12185 \f
12186 /* Print a memory operand whose address is ADDR. */
12188 void
12190 {
12204 {
12215 }
12217 /* Use one byte shorter RIP relative addressing for 64bit mode. */
12219 {
12231 }
12233 {
12234 /* Displacement only requires special attention. */
12237 {
12241 }
12244 else
12246 }
12247 else
12248 {
12250 {
12252 {
12257 else
12259 }
12265 {
12270 }
12272 }
12273 else
12274 {
12278 {
12279 /* Pull out the offset of a symbol; print any symbol itself. */
12283 {
12287 }
12295 else
12297 }
12301 {
12304 {
12308 }
12309 }
12312 else
12316 {
12321 }
12323 }
12324 }
12325 }
12327 bool
12329 {
12330 rtx op;
12337 {
12340 /* FIXME: This might be @TPOFF in Sun ld. */
12351 else
12363 else
12370 #if TARGET_MACHO
12376 #endif
12380 }
12383 }
12384 \f
12385 /* Split one or more DImode RTL references into pairs of SImode
12386 references. The RTL can be REG, offsettable MEM, integer constant, or
12387 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12388 split and "num" is its length. lo_half and hi_half are output arrays
12389 that parallel "operands". */
12391 void
12393 {
12395 {
12398 /* simplify_subreg refuse to split volatile memory addresses,
12399 but we still have to handle it. */
12401 {
12404 }
12405 else
12406 {
12413 }
12414 }
12415 }
12416 /* Split one or more TImode RTL references into pairs of DImode
12417 references. The RTL can be REG, offsettable MEM, integer constant, or
12418 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12419 split and "num" is its length. lo_half and hi_half are output arrays
12420 that parallel "operands". */
12422 void
12424 {
12426 {
12429 /* simplify_subreg refuse to split volatile memory addresses, but we
12430 still have to handle it. */
12432 {
12435 }
12436 else
12437 {
12440 }
12441 }
12442 }
12443 \f
12444 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12445 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12446 is the expression of the binary operation. The output may either be
12447 emitted here, or returned to the caller, like all output_* functions.
12449 There is no guarantee that the operands are the same mode, as they
12450 might be within FLOAT or FLOAT_EXTEND expressions. */
12452 #ifndef SYSV386_COMPAT
12453 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12454 wants to fix the assemblers because that causes incompatibility
12455 with gcc. No-one wants to fix gcc because that causes
12456 incompatibility with assemblers... You can use the option of
12457 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12458 #define SYSV386_COMPAT 1
12459 #endif
12463 {
12469 #ifdef ENABLE_CHECKING
12470 /* Even if we do not want to check the inputs, this documents input
12471 constraints. Which helps in understanding the following code. */
12481 else
12483 #endif
12486 {
12491 else
12500 else
12509 else
12518 else
12525 }
12528 {
12530 {
12534 else
12536 }
12537 else
12538 {
12542 else
12544 }
12546 }
12550 {
12554 {
12558 }
12560 /* know operands[0] == operands[1]. */
12563 {
12566 }
12569 {
12571 /* How is it that we are storing to a dead operand[2]?
12572 Well, presumably operands[1] is dead too. We can't
12573 store the result to st(0) as st(0) gets popped on this
12574 instruction. Instead store to operands[2] (which I
12575 think has to be st(1)). st(1) will be popped later.
12576 gcc <= 2.8.1 didn't have this check and generated
12577 assembly code that the Unixware assembler rejected. */
12579 else
12582 }
12586 else
12593 {
12596 }
12599 {
12602 }
12605 {
12606 #if SYSV386_COMPAT
12607 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12608 derived assemblers, confusingly reverse the direction of
12609 the operation for fsub{r} and fdiv{r} when the
12610 destination register is not st(0). The Intel assembler
12611 doesn't have this brain damage. Read !SYSV386_COMPAT to
12612 figure out what the hardware really does. */
12615 else
12617 #else
12619 /* As above for fmul/fadd, we can't store to st(0). */
12621 else
12623 #endif
12625 }
12628 {
12629 #if SYSV386_COMPAT
12632 else
12634 #else
12637 else
12639 #endif
12641 }
12644 {
12647 else
12650 }
12652 {
12653 #if SYSV386_COMPAT
12655 #else
12657 #endif
12658 }
12659 else
12660 {
12661 #if SYSV386_COMPAT
12663 #else
12665 #endif
12666 }
12671 }
12675 }
12677 /* Return needed mode for entity in optimize_mode_switching pass. */
12679 int
12681 {
12684 /* The mode UNINITIALIZED is used to store control word after a
12685 function call or ASM pattern. The mode ANY specify that function
12686 has no requirements on the control word and make no changes in the
12687 bits we are interested in. */
12701 {
12724 }
12727 }
12729 /* Output code to initialize control word copies used by trunc?f?i and
12730 rounding patterns. CURRENT_MODE is set to current control word,
12731 while NEW_MODE is set to new control word. */
12733 void
12735 {
12737 rtx new_mode;
12748 {
12750 {
12752 /* round toward zero (truncate) */
12758 /* round down toward -oo */
12765 /* round up toward +oo */
12772 /* mask precision exception for nearbyint() */
12779 }
12780 }
12781 else
12782 {
12784 {
12786 /* round toward zero (truncate) */
12792 /* round down toward -oo */
12798 /* round up toward +oo */
12804 /* mask precision exception for nearbyint() */
12811 }
12812 }
12818 }
12820 /* Output code for INSN to convert a float to a signed int. OPERANDS
12821 are the insn operands. The output may be [HSD]Imode and the input
12822 operand may be [SDX]Fmode. */
12826 {
12831 /* Jump through a hoop or two for DImode, since the hardware has no
12832 non-popping instruction. We used to do this a different way, but
12833 that was somewhat fragile and broke with post-reload splitters. */
12843 else
12844 {
12849 else
12853 }
12856 }
12858 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12859 have the values zero or one, indicates the ffreep insn's operand
12860 from the OPERANDS array. */
12864 {
12866 #ifdef HAVE_AS_IX86_FFREEP
12868 #else
12869 {
12879 }
12880 #endif
12883 }
12886 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12887 should be used. UNORDERED_P is true when fucom should be used. */
12891 {
12897 {
12900 }
12901 else
12902 {
12905 }
12908 {
12917 else
12919 else
12922 else
12924 }
12931 {
12933 {
12936 }
12937 else
12939 }
12942 && stack_top_dies
12945 {
12946 /* If both the top of the 387 stack dies, and the other operand
12947 is also a stack register that dies, then this must be a
12948 `fcompp' float compare */
12951 {
12952 /* There is no double popping fcomi variant. Fortunately,
12953 eflags is immune from the fstp's cc clobbering. */
12956 else
12959 }
12960 else
12961 {
12964 else
12966 }
12967 }
12968 else
12969 {
12970 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12973 {
12981 NULL,
12982 NULL,
12989 NULL,
12990 NULL,
12991 NULL,
12992 NULL
12993 };
13008 }
13009 }
13011 void
13013 {
13016 #ifdef ASM_QUAD
13019 #else
13021 #endif
13024 }
13026 void
13028 {
13031 #ifdef ASM_QUAD
13034 #else
13036 #endif
13037 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
13043 #if TARGET_MACHO
13045 {
13049 }
13050 #endif
13051 else
13054 }
13055 \f
13056 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
13057 for the target. */
13059 void
13061 {
13062 rtx tmp;
13064 /* We play register width games, which are only valid after reload. */
13067 /* Avoid HImode and its attendant prefix byte. */
13072 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
13074 {
13077 }
13080 }
13082 /* X is an unchanging MEM. If it is a constant pool reference, return
13083 the constant pool rtx, else NULL. */
13085 rtx
13087 {
13094 }
13096 void
13098 {
13106 {
13109 {
13114 }
13118 }
13122 {
13135 {
13141 }
13142 }
13145 {
13147 {
13148 #if TARGET_MACHO
13150 {
13151 rtx temp = ((reload_in_progress
13158 }
13163 #endif
13164 }
13165 else
13166 {
13170 {
13175 }
13176 }
13177 }
13178 else
13179 {
13190 /* Force large constants in 64bit compilation into register
13191 to get them CSEed. */
13203 {
13204 /* If we are loading a floating point constant to a register,
13205 force the value to memory now, since we'll get better code
13206 out the back end. */
13210 {
13215 }
13216 }
13217 }
13220 }
13222 void
13224 {
13228 /* Force constants other than zero into memory. We do not know how
13229 the instructions used to build constants modify the upper 64 bits
13230 of the register, once we have that information we may be able
13231 to handle some of them more efficiently. */
13240 /* We need to check memory alignment for SSE mode since attribute
13241 can make operands unaligned. */
13246 {
13249 /* ix86_expand_vector_move_misalign() does not like constants ... */
13255 /* ... nor both arguments in memory. */
13263 }
13265 /* Make operand1 a register if it isn't already. */
13269 {
13272 }
13275 }
13277 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
13278 straight to ix86_expand_vector_move. */
13279 /* Code generation for scalar reg-reg moves of single and double precision data:
13280 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
13281 movaps reg, reg
13282 else
13283 movss reg, reg
13284 if (x86_sse_partial_reg_dependency == true)
13285 movapd reg, reg
13286 else
13287 movsd reg, reg
13289 Code generation for scalar loads of double precision data:
13290 if (x86_sse_split_regs == true)
13291 movlpd mem, reg (gas syntax)
13292 else
13293 movsd mem, reg
13295 Code generation for unaligned packed loads of single precision data
13296 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
13297 if (x86_sse_unaligned_move_optimal)
13298 movups mem, reg
13300 if (x86_sse_partial_reg_dependency == true)
13301 {
13302 xorps reg, reg
13303 movlps mem, reg
13304 movhps mem+8, reg
13305 }
13306 else
13307 {
13308 movlps mem, reg
13309 movhps mem+8, reg
13310 }
13312 Code generation for unaligned packed loads of double precision data
13313 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
13314 if (x86_sse_unaligned_move_optimal)
13315 movupd mem, reg
13317 if (x86_sse_split_regs == true)
13318 {
13319 movlpd mem, reg
13320 movhpd mem+8, reg
13321 }
13322 else
13323 {
13324 movsd mem, reg
13325 movhpd mem+8, reg
13326 }
13327 */
13329 void
13331 {
13338 {
13340 {
13344 {
13346 /* If we're optimizing for size, movups is the smallest. */
13348 {
13353 }
13365 }
13372 {
13381 {
13386 }
13394 }
13399 }
13402 }
13405 {
13406 /* If we're optimizing for size, movups is the smallest. */
13409 {
13414 }
13416 /* ??? If we have typed data, then it would appear that using
13417 movdqu is the only way to get unaligned data loaded with
13418 integer type. */
13420 {
13425 }
13428 {
13429 rtx zero;
13432 {
13437 }
13439 /* When SSE registers are split into halves, we can avoid
13440 writing to the top half twice. */
13442 {
13445 }
13446 else
13447 {
13448 /* ??? Not sure about the best option for the Intel chips.
13449 The following would seem to satisfy; the register is
13450 entirely cleared, breaking the dependency chain. We
13451 then store to the upper half, with a dependency depth
13452 of one. A rumor has it that Intel recommends two movsd
13453 followed by an unpacklpd, but this is unconfirmed. And
13454 given that the dependency depth of the unpacklpd would
13455 still be one, I'm not sure why this would be better. */
13457 }
13463 }
13464 else
13465 {
13467 {
13472 }
13476 else
13485 }
13486 }
13488 {
13489 /* If we're optimizing for size, movups is the smallest. */
13492 {
13497 }
13499 /* ??? Similar to above, only less clear because of quote
13500 typeless stores unquote. */
13503 {
13508 }
13511 {
13513 {
13517 }
13518 else
13519 {
13524 }
13525 }
13526 else
13527 {
13532 {
13535 }
13536 else
13537 {
13542 }
13543 }
13544 }
13545 else
13547 }
13549 /* Expand a push in MODE. This is some mode for which we do not support
13550 proper push instructions, at least from the registers that we expect
13551 the value to live in. */
13553 void
13555 {
13556 rtx tmp;
13566 /* When we push an operand onto stack, it has to be aligned at least
13567 at the function argument boundary. However since we don't have
13568 the argument type, we can't determine the actual argument
13569 boundary. */
13571 }
13573 /* Helper function of ix86_fixup_binary_operands to canonicalize
13574 operand order. Returns true if the operands should be swapped. */
13576 static bool
13578 rtx operands[])
13579 {
13584 /* If the operation is not commutative, we can't do anything. */
13588 /* Highest priority is that src1 should match dst. */
13594 /* Next highest priority is that immediate constants come second. */
13600 /* Lowest priority is that memory references should come second. */
13607 }
13610 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13611 destination to use for the operation. If different from the true
13612 destination in operands[0], a copy operation will be required. */
13614 rtx
13616 rtx operands[])
13617 {
13622 /* Canonicalize operand order. */
13624 {
13625 rtx temp;
13627 /* It is invalid to swap operands of different modes. */
13633 }
13635 /* Both source operands cannot be in memory. */
13637 {
13638 /* Optimization: Only read from memory once. */
13640 {
13643 }
13644 else
13646 }
13648 /* If the destination is memory, and we do not have matching source
13649 operands, do things in registers. */
13653 /* Source 1 cannot be a constant. */
13657 /* Source 1 cannot be a non-matching memory. */
13664 }
13666 /* Similarly, but assume that the destination has already been
13667 set up properly. */
13669 void
13672 {
13675 }
13677 /* Attempt to expand a binary operator. Make the expansion closer to the
13678 actual machine, then just general_operand, which will allow 3 separate
13679 memory references (one output, two input) in a single insn. */
13681 void
13683 rtx operands[])
13684 {
13691 /* Emit the instruction. */
13695 {
13696 /* Reload doesn't know about the flags register, and doesn't know that
13697 it doesn't want to clobber it. We can only do this with PLUS. */
13700 }
13701 else
13702 {
13705 }
13707 /* Fix up the destination if needed. */
13710 }
13712 /* Return TRUE or FALSE depending on whether the binary operator meets the
13713 appropriate constraints. */
13715 int
13718 {
13723 /* Both source operands cannot be in memory. */
13727 /* Canonicalize operand order for commutative operators. */
13729 {
13733 }
13735 /* If the destination is memory, we must have a matching source operand. */
13739 /* Source 1 cannot be a constant. */
13743 /* Source 1 cannot be a non-matching memory. */
13748 }
13750 /* Attempt to expand a unary operator. Make the expansion closer to the
13751 actual machine, then just general_operand, which will allow 2 separate
13752 memory references (one output, one input) in a single insn. */
13754 void
13756 rtx operands[])
13757 {
13764 /* If the destination is memory, and we do not have matching source
13765 operands, do things in registers. */
13768 {
13771 else
13773 }
13775 /* When source operand is memory, destination must match. */
13779 /* Emit the instruction. */
13783 {
13784 /* Reload doesn't know about the flags register, and doesn't know that
13785 it doesn't want to clobber it. */
13788 }
13789 else
13790 {
13793 }
13795 /* Fix up the destination if needed. */
13798 }
13800 #define LEA_SEARCH_THRESHOLD 12
13802 /* Search backward for non-agu definition of register number REGNO1
13803 or register number REGNO2 in INSN's basic block until
13804 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13805 2. Reach BB boundary, or
13806 3. Reach agu definition.
13807 Returns the distance between the non-agu definition point and INSN.
13808 If no definition point, returns -1. */
13810 static int
13812 rtx insn)
13813 {
13820 {
13823 {
13825 {
13826 distance++;
13832 {
13836 }
13837 }
13841 }
13842 }
13845 {
13846 edge e;
13847 edge_iterator ei;
13852 {
13855 }
13858 {
13863 {
13865 {
13866 distance++;
13872 {
13876 }
13877 }
13879 }
13880 }
13881 }
13885 done:
13886 /* get_attr_type may modify recog data. We want to make sure
13887 that recog data is valid for instruction INSN, on which
13888 distance_non_agu_define is called. INSN is unchanged here. */
13891 }
13893 /* Return the distance between INSN and the next insn that uses
13894 register number REGNO0 in memory address. Return -1 if no such
13895 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13897 static int
13899 {
13906 {
13909 {
13911 {
13912 distance++;
13918 {
13919 /* Return DISTANCE if OP0 is used in memory
13920 address in NEXT. */
13922 }
13928 {
13929 /* Return -1 if OP0 is set in NEXT. */
13931 }
13932 }
13936 }
13937 }
13940 {
13941 edge e;
13942 edge_iterator ei;
13947 {
13950 }
13953 {
13958 {
13960 {
13961 distance++;
13967 {
13968 /* Return DISTANCE if OP0 is used in memory
13969 address in NEXT. */
13971 }
13977 {
13978 /* Return -1 if OP0 is set in NEXT. */
13980 }
13982 }
13984 }
13985 }
13986 }
13989 }
13991 /* Define this macro to tune LEA priority vs ADD, it take effect when
13992 there is a dilemma of choicing LEA or ADD
13993 Negative value: ADD is more preferred than LEA
13994 Zero: Netrual
13995 Positive value: LEA is more preferred than ADD*/
13996 #define IX86_LEA_PRIORITY 2
13998 /* Return true if it is ok to optimize an ADD operation to LEA
13999 operation to avoid flag register consumation. For the processors
14000 like ATOM, if the destination register of LEA holds an actual
14001 address which will be used soon, LEA is better and otherwise ADD
14002 is better. */
14004 bool
14007 {
14017 /* If a = b + c, (a!=b && a!=c), must use lea form. */
14020 else
14021 {
14027 /* If this insn has both backward non-agu dependence and forward
14028 agu dependence, the one with short distance take effect. */
14035 }
14036 }
14038 /* Return true if destination reg of SET_BODY is shift count of
14039 USE_BODY. */
14041 static bool
14043 {
14044 rtx set_dest;
14045 rtx shift_rtx;
14048 /* Retrieve destination of SET_BODY. */
14050 {
14059 use_body))
14064 }
14066 /* Retrieve shift count of USE_BODY. */
14068 {
14080 }
14088 {
14091 /* Return true if shift count is dest of SET_BODY. */
14095 }
14098 }
14100 /* Return true if destination reg of SET_INSN is shift count of
14101 USE_INSN. */
14103 bool
14105 {
14108 }
14110 /* Return TRUE or FALSE depending on whether the unary operator meets the
14111 appropriate constraints. */
14113 int
14117 {
14118 /* If one of operands is memory, source and destination must match. */
14124 }
14126 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
14127 are ok, keeping in mind the possible movddup alternative. */
14129 bool
14131 {
14137 }
14139 /* Post-reload splitter for converting an SF or DFmode value in an
14140 SSE register into an unsigned SImode. */
14142 void
14144 {
14155 /* Load up the value into the low element. We must ensure that the other
14156 elements are valid floats -- zero is the easiest such value. */
14158 {
14161 else
14163 }
14164 else
14165 {
14170 else
14172 }
14192 else
14197 }
14199 /* Convert an unsigned DImode value into a DFmode, using only SSE.
14200 Expects the 64-bit DImode to be supplied in a pair of integral
14201 registers. Requires SSE2; will use SSE3 if available. For x86_32,
14202 -mfpmath=sse, !optimize_size only. */
14204 void
14206 {
14210 rtx x;
14216 {
14219 }
14220 else
14221 {
14225 }
14233 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
14236 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
14237 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
14238 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
14239 (0x1.0p84 + double(fp_value_hi_xmm)).
14240 Note these exponents differ by 32. */
14244 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
14245 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
14254 /* Add the upper and lower DFmode values together. */
14257 else
14258 {
14262 }
14265 }
14267 /* Not used, but eases macroization of patterns. */
14268 void
14270 rtx input ATTRIBUTE_UNUSED)
14271 {
14273 }
14275 /* Convert an unsigned SImode value into a DFmode. Only currently used
14276 for SSE, but applicable anywhere. */
14278 void
14280 {
14281 REAL_VALUE_TYPE TWO31r;
14296 }
14298 /* Convert a signed DImode value into a DFmode. Only used for SSE in
14299 32-bit mode; otherwise we have a direct convert instruction. */
14301 void
14303 {
14304 REAL_VALUE_TYPE TWO32r;
14322 }
14324 /* Convert an unsigned SImode value into a SFmode, using only SSE.
14325 For x86_32, -mfpmath=sse, !optimize_size only. */
14326 void
14328 {
14329 REAL_VALUE_TYPE ONE16r;
14348 }
14350 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
14351 then replicate the value for all elements of the vector
14352 register. */
14354 rtx
14356 {
14357 rtvec v;
14359 {
14373 else
14381 else
14387 }
14388 }
14390 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
14391 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
14392 for an SSE register. If VECT is true, then replicate the mask for
14393 all elements of the vector register. If INVERT is true, then create
14394 a mask excluding the sign bit. */
14396 rtx
14398 {
14402 rtx v;
14403 rtx mask;
14405 /* Find the sign bit, sign extended to 2*HWI. */
14407 {
14421 else
14429 {
14432 }
14433 else
14434 {
14435 rtvec vec;
14441 {
14444 }
14445 else
14455 }
14460 }
14465 /* Force this value into the low part of a fp vector constant. */
14474 }
14476 /* Generate code for floating point ABS or NEG. */
14478 void
14480 rtx operands[])
14481 {
14488 {
14491 }
14497 /* NEG and ABS performed with SSE use bitwise mask operations.
14498 Create the appropriate mask now. */
14501 else
14508 {
14512 }
14513 else
14514 {
14518 {
14523 }
14524 else
14526 }
14527 }
14529 /* Expand a copysign operation. Special case operand 0 being a constant. */
14531 void
14533 {
14544 {
14551 {
14558 else
14559 {
14563 }
14564 }
14574 else
14578 }
14579 else
14580 {
14590 else
14594 }
14595 }
14597 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14598 be a constant, and so has already been expanded into a vector constant. */
14600 void
14602 {
14618 {
14621 }
14622 }
14624 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14625 so we have to do two masks. */
14627 void
14629 {
14644 {
14645 /* Shouldn't happen often (it's useless, obviously), but when it does
14646 we'd generate incorrect code if we continue below. */
14649 }
14652 {
14663 }
14664 else
14665 {
14667 {
14669 }
14671 {
14675 }
14679 {
14682 }
14684 {
14689 }
14691 }
14695 }
14697 /* Return TRUE or FALSE depending on whether the first SET in INSN
14698 has source and destination with matching CC modes, and that the
14699 CC mode is at least as constrained as REQ_MODE. */
14701 int
14703 {
14704 rtx set;
14715 {
14725 /* FALLTHRU */
14729 /* FALLTHRU */
14733 /* FALLTHRU */
14743 }
14746 }
14748 /* Generate insn patterns to do an integer compare of OPERANDS. */
14750 static rtx
14752 {
14759 /* This is very simple, but making the interface the same as in the
14760 FP case makes the rest of the code easier. */
14764 /* Return the test that should be put into the flags user, i.e.
14765 the bcc, scc, or cmov instruction. */
14767 }
14769 /* Figure out whether to use ordered or unordered fp comparisons.
14770 Return the appropriate mode to use. */
14772 enum machine_mode
14774 {
14775 /* ??? In order to make all comparisons reversible, we do all comparisons
14776 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14777 all forms trapping and nontrapping comparisons, we can make inequality
14778 comparisons trapping again, since it results in better code when using
14779 FCOM based compares. */
14781 }
14783 enum machine_mode
14785 {
14789 {
14792 }
14795 {
14796 /* Only zero flag is needed. */
14800 /* Codes needing carry flag. */
14803 /* Detect overflow checks. They need just the carry flag. */
14807 else
14811 /* Detect overflow checks. They need just the carry flag. */
14815 else
14817 /* Codes possibly doable only with sign flag when
14818 comparing against zero. */
14823 else
14824 /* For other cases Carry flag is not required. */
14826 /* Codes doable only with sign flag when comparing
14827 against zero, but we miss jump instruction for it
14828 so we need to use relational tests against overflow
14829 that thus needs to be zero. */
14834 else
14836 /* strcmp pattern do (use flags) and combine may ask us for proper
14837 mode. */
14842 }
14843 }
14845 /* Return the fixed registers used for condition codes. */
14847 static bool
14849 {
14853 }
14855 /* If two condition code modes are compatible, return a condition code
14856 mode which is compatible with both. Otherwise, return
14857 VOIDmode. */
14859 static enum machine_mode
14861 {
14873 {
14887 {
14901 }
14905 /* These are only compatible with themselves, which we already
14906 checked above. */
14908 }
14909 }
14912 /* Return a comparison we can do and that it is equivalent to
14913 swap_condition (code) apart possibly from orderedness.
14914 But, never change orderedness if TARGET_IEEE_FP, returning
14915 UNKNOWN in that case if necessary. */
14917 static enum rtx_code
14919 {
14921 {
14932 }
14933 }
14935 /* Return cost of comparison CODE using the best strategy for performance.
14936 All following functions do use number of instructions as a cost metrics.
14937 In future this should be tweaked to compute bytes for optimize_size and
14938 take into account performance of various instructions on various CPUs. */
14940 static int
14942 {
14945 /* The cost of code using bit-twiddling on %ah. */
14947 {
14970 }
14973 {
14980 }
14981 }
14983 /* Return strategy to use for floating-point. We assume that fcomi is always
14984 preferrable where available, since that is also true when looking at size
14985 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14987 enum ix86_fpcmp_strategy
14989 {
14990 /* Do fcomi/sahf based test when profitable. */
14999 }
15001 /* Swap, force into registers, or otherwise massage the two operands
15002 to a fp comparison. The operands are updated in place; the new
15003 comparison code is returned. */
15005 static enum rtx_code
15007 {
15013 /* All of the unordered compare instructions only work on registers.
15014 The same is true of the fcomi compare instructions. The XFmode
15015 compare instructions require registers except when comparing
15016 against zero or when converting operand 1 from fixed point to
15017 floating point. */
15026 {
15029 }
15030 else
15031 {
15032 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
15033 things around if they appear profitable, otherwise force op0
15034 into a register. */
15040 {
15043 {
15044 rtx tmp;
15047 }
15048 }
15054 {
15059 {
15062 }
15063 else
15065 }
15066 }
15068 /* Try to rearrange the comparison to make it cheaper. */
15072 {
15073 rtx tmp;
15078 }
15083 }
15085 /* Convert comparison codes we use to represent FP comparison to integer
15086 code that will result in proper branch. Return UNKNOWN if no such code
15087 is available. */
15089 enum rtx_code
15091 {
15093 {
15116 }
15117 }
15119 /* Generate insn patterns to do a floating point compare of OPERANDS. */
15121 static rtx
15123 {
15130 /* Do fcomi/sahf based test when profitable. */
15132 {
15137 tmp);
15145 tmp);
15154 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
15161 /* In the unordered case, we have to check C2 for NaN's, which
15162 doesn't happen to work out to anything nice combination-wise.
15163 So do some bit twiddling on the value we've got in AH to come
15164 up with an appropriate set of condition codes. */
15168 {
15172 {
15175 }
15176 else
15177 {
15183 }
15188 {
15193 }
15194 else
15195 {
15198 }
15203 {
15206 }
15207 else
15208 {
15212 }
15217 {
15223 }
15224 else
15225 {
15228 }
15233 {
15238 }
15239 else
15240 {
15243 }
15248 {
15253 }
15254 else
15255 {
15258 }
15272 }
15277 }
15279 /* Return the test that should be put into the flags user, i.e.
15280 the bcc, scc, or cmov instruction. */
15283 const0_rtx);
15284 }
15286 rtx
15288 {
15297 {
15300 }
15301 else
15305 }
15307 void
15309 {
15310 rtx tmp;
15313 {
15320 simple:
15324 pc_rtx);
15332 /* Expand DImode branch into multiple compare+branch. */
15333 {
15339 {
15344 }
15346 {
15350 }
15351 else
15352 {
15356 }
15358 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15359 avoid two branches. This costs one extra insn, so disable when
15360 optimizing for size. */
15365 {
15385 }
15387 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15388 op1 is a constant and the low word is zero, then we can just
15389 examine the high word. Similarly for low word -1 and
15390 less-or-equal-than or greater-than. */
15394 {
15397 {
15402 }
15406 {
15411 }
15415 }
15417 /* Otherwise, we need two or three jumps. */
15426 {
15440 }
15442 /*
15443 * a < b =>
15444 * if (hi(a) < hi(b)) goto true;
15445 * if (hi(a) > hi(b)) goto false;
15446 * if (lo(a) < lo(b)) goto true;
15447 * false:
15448 */
15465 }
15468 /* If we have already emitted a compare insn, go straight to simple.
15469 ix86_expand_compare won't emit anything if ix86_compare_emitted
15470 is non NULL. */
15473 }
15474 }
15476 /* Split branch based on floating point condition. */
15477 void
15480 {
15481 rtx condition;
15482 rtx i;
15485 {
15490 }
15493 tmp);
15495 /* Remove pushed operand from stack. */
15505 }
15507 void
15509 {
15510 rtx ret;
15517 }
15519 /* Expand comparison setting or clearing carry flag. Return true when
15520 successful and set pop for the operation. */
15521 static bool
15523 {
15527 /* Do not handle DImode compares that go through special path. */
15532 {
15537 /* Shortcut: following common codes never translate
15538 into carry flag compares. */
15543 /* These comparisons require zero flag; swap operands so they won't. */
15546 {
15551 }
15553 /* Try to expand the comparison and verify that we end up with
15554 carry flag based comparison. This fails to be true only when
15555 we decide to expand comparison using arithmetic that is not
15556 too common scenario. */
15565 else
15574 }
15580 {
15585 /* Convert a==0 into (unsigned)a<1. */
15594 /* Convert a>b into b<a or a>=b-1. */
15598 {
15600 /* Bail out on overflow. We still can swap operands but that
15601 would force loading of the constant into register. */
15606 }
15607 else
15608 {
15613 }
15616 /* Convert a>=0 into (unsigned)a<0x80000000. */
15634 }
15635 /* Swapping operands may cause constant to appear as first operand. */
15637 {
15641 }
15647 }
15649 int
15651 {
15670 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15671 HImode insns, we'd be swallowed in word prefix ops. */
15677 {
15681 HOST_WIDE_INT diff;
15684 /* Sign bit compares are better done using shifts than we do by using
15685 sbb. */
15689 {
15690 /* Detect overlap between destination and compare sources. */
15694 {
15695 rtx flags;
15704 {
15706 compare_code
15708 }
15710 /* To simplify rest of code, restrict to the GEU case. */
15712 {
15718 }
15719 else
15720 {
15723 reverse_condition_maybe_unordered
15725 else
15728 }
15737 else
15740 }
15741 else
15742 {
15745 else
15746 {
15751 }
15754 }
15757 {
15758 /*
15759 * cmpl op0,op1
15760 * sbbl dest,dest
15761 * [addl dest, ct]
15762 *
15763 * Size 5 - 8.
15764 */
15769 }
15771 {
15772 /*
15773 * cmpl op0,op1
15774 * sbbl dest,dest
15775 * orl $ct, dest
15776 *
15777 * Size 8.
15778 */
15782 }
15784 {
15785 /*
15786 * cmpl op0,op1
15787 * sbbl dest,dest
15788 * notl dest
15789 * [addl dest, cf]
15790 *
15791 * Size 8 - 11.
15792 */
15798 }
15799 else
15800 {
15801 /*
15802 * cmpl op0,op1
15803 * sbbl dest,dest
15804 * [notl dest]
15805 * andl cf - ct, dest
15806 * [addl dest, ct]
15807 *
15808 * Size 8 - 11.
15809 */
15812 {
15816 }
15826 }
15832 }
15835 {
15838 HOST_WIDE_INT tmp;
15843 {
15846 /* We may be reversing unordered compare to normal compare, that
15847 is not valid in general (we may convert non-trapping condition
15848 to trapping one), however on i386 we currently emit all
15849 comparisons unordered. */
15852 }
15853 else
15854 {
15857 }
15858 }
15863 {
15868 {
15873 }
15874 }
15876 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15880 {
15881 /* If lea code below could be used, only optimize
15882 if it results in a 2 insn sequence. */
15888 {
15889 /*
15890 * notl op1 (if necessary)
15891 * sarl $31, op1
15892 * orl cf, op1
15893 */
15895 {
15899 }
15911 }
15912 }
15920 {
15921 /*
15922 * xorl dest,dest
15923 * cmpl op1,op2
15924 * setcc dest
15925 * lea cf(dest*(ct-cf)),dest
15926 *
15927 * Size 14.
15928 *
15929 * This also catches the degenerate setcc-only case.
15930 */
15932 rtx tmp;
15939 /* On x86_64 the lea instruction operates on Pmode, so we need
15940 to get arithmetics done in proper mode to match. */
15943 else
15944 {
15945 rtx out1;
15948 nops++;
15950 {
15952 nops++;
15953 }
15954 }
15956 {
15958 nops++;
15959 }
15961 {
15964 else
15966 }
15971 }
15973 /*
15974 * General case: Jumpful:
15975 * xorl dest,dest cmpl op1, op2
15976 * cmpl op1, op2 movl ct, dest
15977 * setcc dest jcc 1f
15978 * decl dest movl cf, dest
15979 * andl (cf-ct),dest 1:
15980 * addl ct,dest
15981 *
15982 * Size 20. Size 14.
15983 *
15984 * This is reasonably steep, but branch mispredict costs are
15985 * high on modern cpus, so consider failing only if optimizing
15986 * for space.
15987 */
15992 {
15994 {
16001 {
16004 /* We may be reversing unordered compare to normal compare,
16005 that is not valid in general (we may convert non-trapping
16006 condition to trapping one), however on i386 we currently
16007 emit all comparisons unordered. */
16009 }
16010 else
16011 {
16015 }
16016 }
16019 {
16020 /* notl op1 (if needed)
16021 sarl $31, op1
16022 andl (cf-ct), op1
16023 addl ct, op1
16025 For x < 0 (resp. x <= -1) there will be no notl,
16026 so if possible swap the constants to get rid of the
16027 complement.
16028 True/false will be -1/0 while code below (store flag
16029 followed by decrement) is 0/-1, so the constants need
16030 to be exchanged once more. */
16033 {
16036 }
16037 else
16038 {
16042 }
16046 }
16047 else
16048 {
16054 }
16066 }
16067 }
16070 {
16071 /* Try a few things more with specific constants and a variable. */
16073 optab op;
16079 /* If one of the two operands is an interesting constant, load a
16080 constant with the above and mask it in with a logical operation. */
16083 {
16089 else
16091 }
16093 {
16099 else
16101 }
16102 else
16109 /* Recurse to get the constant loaded. */
16113 /* Mask in the interesting variable. */
16115 OPTAB_WIDEN);
16120 }
16122 /*
16123 * For comparison with above,
16124 *
16125 * movl cf,dest
16126 * movl ct,tmp
16127 * cmpl op1,op2
16128 * cmovcc tmp,dest
16129 *
16130 * Size 15.
16131 */
16154 }
16156 /* Swap, force into registers, or otherwise massage the two operands
16157 to an sse comparison with a mask result. Thus we differ a bit from
16158 ix86_prepare_fp_compare_args which expects to produce a flags result.
16160 The DEST operand exists to help determine whether to commute commutative
16161 operators. The POP0/POP1 operands are updated in place. The new
16162 comparison code is returned, or UNKNOWN if not implementable. */
16164 static enum rtx_code
16167 {
16168 rtx tmp;
16171 {
16174 /* We have no LTGT as an operator. We could implement it with
16175 NE & ORDERED, but this requires an extra temporary. It's
16176 not clear that it's worth it. */
16183 /* These are supported directly. */
16190 /* For commutative operators, try to canonicalize the destination
16191 operand to be first in the comparison - this helps reload to
16192 avoid extra moves. */
16195 /* FALLTHRU */
16201 /* These are not supported directly. Swap the comparison operands
16202 to transform into something that is supported. */
16211 }
16214 }
16216 /* Detect conditional moves that exactly match min/max operational
16217 semantics. Note that this is IEEE safe, as long as we don't
16218 interchange the operands.
16220 Returns FALSE if this conditional move doesn't match a MIN/MAX,
16221 and TRUE if the operation is successful and instructions are emitted. */
16223 static bool
16226 {
16229 rtx tmp;
16232 ;
16234 {
16238 }
16239 else
16246 else
16251 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
16252 but MODE may be a vector mode and thus not appropriate. */
16254 {
16256 rtvec v;
16261 }
16262 else
16263 {
16266 }
16270 }
16272 /* Expand an sse vector comparison. Return the register with the result. */
16274 static rtx
16277 {
16279 rtx x;
16294 }
16296 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16297 operations. This is used for both scalar and vector conditional moves. */
16299 static void
16301 {
16306 {
16310 }
16312 {
16317 }
16319 {
16322 op_true,
16323 op_false));
16325 }
16326 else
16327 {
16334 else
16346 }
16347 }
16349 /* Expand a floating-point conditional move. Return true if successful. */
16351 int
16353 {
16361 {
16364 /* Since we've no cmove for sse registers, don't force bad register
16365 allocation just to gain access to it. Deny movcc when the
16366 comparison mode doesn't match the move mode. */
16388 }
16390 /* The floating point conditional move instructions don't directly
16391 support conditions resulting from a signed integer comparison. */
16395 {
16402 }
16409 }
16411 /* Expand a floating-point vector conditional move; a vcond operation
16412 rather than a movcc operation. */
16414 bool
16416 {
16418 rtx cmp;
16433 }
16435 /* Expand a signed/unsigned integral vector conditional move. */
16437 bool
16439 {
16448 /* XOP supports all of the comparisons on all vector int types. */
16450 {
16451 /* Canonicalize the comparison to EQ, GT, GTU. */
16453 {
16470 /* FALLTHRU */
16480 }
16482 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16484 {
16486 {
16488 /* SSE4.1 supports EQ. */
16495 /* SSE4.2 supports GT/GTU. */
16502 }
16503 }
16505 /* Unsigned parallel compare is not supported by the hardware.
16506 Play some tricks to turn this into a signed comparison
16507 against 0. */
16509 {
16513 {
16516 {
16520 /* Subtract (-(INT MAX) - 1) from both operands to make
16521 them signed. */
16535 }
16540 /* Perform a parallel unsigned saturating subtraction. */
16553 }
16554 }
16555 }
16563 }
16565 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16566 true if we should do zero extension, else sign extension. HIGH_P is
16567 true if we want the N/2 high elements, else the low elements. */
16569 void
16571 {
16577 {
16581 else
16587 else
16593 else
16598 }
16604 else
16609 }
16611 /* This function performs the same task as ix86_expand_sse_unpack,
16612 but with SSE4.1 instructions. */
16614 void
16616 {
16622 {
16626 else
16632 else
16638 else
16643 }
16647 {
16648 /* Shift higher 8 bytes to lower 8 bytes. */
16653 }
16654 else
16658 }
16660 /* Expand conditional increment or decrement using adb/sbb instructions.
16661 The default case using setcc followed by the conditional move can be
16662 done by generic code. */
16663 int
16665 {
16667 rtx flags;
16669 rtx compare_op;
16688 {
16691 }
16694 {
16698 reverse_condition_maybe_unordered
16700 else
16702 }
16706 /* Construct either adc or sbb insn. */
16708 {
16710 {
16725 }
16726 }
16727 else
16728 {
16730 {
16745 }
16746 }
16750 }
16753 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16754 works for floating pointer parameters and nonoffsetable memories.
16755 For pushes, it returns just stack offsets; the values will be saved
16756 in the right order. Maximally three parts are generated. */
16758 static int
16760 {
16765 else
16771 /* Optimize constant pool reference to immediates. This is used by fp
16772 moves, that force all constants to memory to allow combining. */
16774 {
16778 }
16781 {
16782 /* The only non-offsetable memories we handle are pushes. */
16791 }
16794 {
16796 /* Caution: if we looked through a constant pool memory above,
16797 the operand may actually have a different mode now. That's
16798 ok, since we want to pun this all the way back to an integer. */
16802 }
16805 {
16808 else
16809 {
16813 {
16817 }
16819 {
16824 }
16826 {
16827 REAL_VALUE_TYPE r;
16832 {
16847 }
16850 }
16851 else
16853 }
16854 }
16855 else
16856 {
16860 {
16863 {
16867 }
16869 {
16873 }
16875 {
16876 REAL_VALUE_TYPE r;
16882 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16885 = gen_int_mode
16888 DImode);
16889 else
16896 = gen_int_mode
16899 DImode);
16900 else
16902 }
16903 else
16905 }
16906 }
16909 }
16911 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16912 Return false when normal moves are needed; true when all required
16913 insns have been emitted. Operands 2-4 contain the input values
16914 int the correct order; operands 5-7 contain the output values. */
16916 void
16918 {
16926 /* The DFmode expanders may ask us to move double.
16927 For 64bit target this is single move. By hiding the fact
16928 here we simplify i386.md splitters. */
16930 {
16931 /* Optimize constant pool reference to immediates. This is used by
16932 fp moves, that force all constants to memory to allow combining. */
16939 {
16942 }
16943 else
16948 }
16950 /* The only non-offsettable memory we handle is push. */
16953 else
16960 /* When emitting push, take care for source operands on the stack. */
16963 {
16966 /* Compensate for the stack decrement by 4. */
16971 /* src_base refers to the stack pointer and is
16972 automatically decreased by emitted push. */
16976 }
16978 /* We need to do copy in the right order in case an address register
16979 of the source overlaps the destination. */
16981 {
16982 rtx tmp;
16985 {
16989 collisions++;
16990 }
16992 /* Collision in the middle part can be handled by reordering. */
16994 {
16997 }
17001 {
17003 {
17006 }
17007 else
17008 {
17011 }
17012 }
17014 /* If there are more collisions, we can't handle it by reordering.
17015 Do an lea to the last part and use only one colliding move. */
17017 {
17018 rtx base;
17024 /* Handle the case when the last part isn't valid for lea.
17025 Happens in 64-bit mode storing the 12-byte XFmode. */
17032 {
17035 }
17036 }
17037 }
17040 {
17042 {
17044 {
17049 }
17051 {
17054 }
17055 }
17056 else
17057 {
17058 /* In 64bit mode we don't have 32bit push available. In case this is
17059 register, it is OK - we will just use larger counterpart. We also
17060 retype memory - these comes from attempt to avoid REX prefix on
17061 moving of second half of TFmode value. */
17063 {
17065 {
17076 }
17080 }
17081 }
17085 }
17087 /* Choose correct order to not overwrite the source before it is copied. */
17097 {
17099 {
17102 }
17103 }
17104 else
17105 {
17107 {
17110 }
17111 }
17113 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
17115 {
17124 }
17130 }
17132 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
17133 left shift by a constant, either using a single shift or
17134 a sequence of add instructions. */
17136 static void
17138 {
17140 {
17142 ? gen_addsi3
17144 }
17147 {
17150 {
17152 ? gen_addsi3
17154 }
17155 }
17156 else
17158 ? gen_ashlsi3
17160 }
17162 void
17164 {
17170 {
17175 {
17181 }
17182 else
17183 {
17187 ? gen_x86_shld
17190 }
17192 }
17197 {
17198 /* Assuming we've chosen a QImode capable registers, then 1 << N
17199 can be done with two 32/64-bit shifts, no branches, no cmoves. */
17201 {
17217 }
17219 /* Otherwise, we can get the same results by manually performing
17220 a bit extract operation on bit 5/6, and then performing the two
17221 shifts. The two methods of getting 0/1 into low/high are exactly
17222 the same size. Avoiding the shift in the bit extract case helps
17223 pentium4 a bit; no one else seems to care much either way. */
17224 else
17225 {
17226 rtx x;
17230 else
17235 ? gen_lshrsi3
17239 ? gen_andsi3
17243 ? gen_xorsi3
17245 }
17248 ? gen_ashlsi3
17251 ? gen_ashlsi3
17254 }
17257 {
17258 /* For -1 << N, we can avoid the shld instruction, because we
17259 know that we're shifting 0...31/63 ones into a -1. */
17263 else
17265 }
17266 else
17267 {
17273 ? gen_x86_shld
17275 }
17278 ? gen_ashlsi3
17282 {
17285 ? gen_x86_shiftsi_adj_1
17287 scratch));
17288 }
17289 else
17291 ? gen_x86_shiftsi_adj_2
17293 }
17295 void
17297 {
17303 {
17308 {
17311 ? gen_ashrsi3
17316 }
17318 {
17322 ? gen_ashrsi3
17327 ? gen_ashrsi3
17330 }
17331 else
17332 {
17336 ? gen_x86_shrd
17339 ? gen_ashrsi3
17341 }
17342 }
17343 else
17344 {
17351 ? gen_x86_shrd
17354 ? gen_ashrsi3
17358 {
17361 ? gen_ashrsi3
17365 ? gen_x86_shiftsi_adj_1
17367 scratch));
17368 }
17369 else
17371 ? gen_x86_shiftsi_adj_3
17373 }
17374 }
17376 void
17378 {
17384 {
17389 {
17395 ? gen_lshrsi3
17398 }
17399 else
17400 {
17404 ? gen_x86_shrd
17407 ? gen_lshrsi3
17409 }
17410 }
17411 else
17412 {
17419 ? gen_x86_shrd
17422 ? gen_lshrsi3
17425 /* Heh. By reversing the arguments, we can reuse this pattern. */
17427 {
17430 ? gen_x86_shiftsi_adj_1
17432 scratch));
17433 }
17434 else
17436 ? gen_x86_shiftsi_adj_2
17438 }
17439 }
17441 /* Predict just emitted jump instruction to be taken with probability PROB. */
17442 static void
17444 {
17448 }
17450 /* Helper function for the string operations below. Dest VARIABLE whether
17451 it is aligned to VALUE bytes. If true, jump to the label. */
17452 static rtx
17454 {
17459 else
17465 else
17468 }
17470 /* Adjust COUNTER by the VALUE. */
17471 static void
17473 {
17476 else
17478 }
17480 /* Zero extend possibly SImode EXP to Pmode register. */
17481 rtx
17483 {
17484 rtx r;
17492 }
17494 /* Divide COUNTREG by SCALE. */
17495 static rtx
17497 {
17498 rtx sc;
17510 }
17512 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17513 DImode for constant loop counts. */
17515 static enum machine_mode
17517 {
17525 }
17527 /* When SRCPTR is non-NULL, output simple loop to move memory
17528 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17529 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17530 equivalent loop to set memory by VALUE (supposed to be in MODE).
17532 The size is rounded down to whole number of chunk size moved at once.
17533 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17536 static void
17541 {
17546 rtx size;
17547 rtx x_addr;
17548 rtx y_addr;
17557 /* Those two should combine. */
17559 {
17563 }
17573 {
17577 /* When unrolling for chips that reorder memory reads and writes,
17578 we can save registers by using single temporary.
17579 Also using 4 temporaries is overkill in 32bit mode. */
17581 {
17583 {
17585 {
17586 destmem =
17588 srcmem =
17590 }
17592 }
17593 }
17594 else
17595 {
17599 {
17602 {
17603 srcmem =
17605 }
17607 }
17609 {
17611 {
17612 destmem =
17614 }
17616 }
17617 }
17618 }
17619 else
17621 {
17623 destmem =
17626 }
17636 {
17642 else
17644 }
17645 else
17653 {
17658 }
17660 }
17662 /* Output "rep; mov" instruction.
17663 Arguments have same meaning as for previous function */
17664 static void
17667 rtx count,
17669 {
17670 rtx destexp;
17671 rtx srcexp;
17672 rtx countreg;
17674 /* If the size is known, it is shorter to use rep movs. */
17685 {
17692 }
17693 else
17694 {
17697 }
17699 {
17706 }
17707 else
17708 {
17713 }
17716 }
17718 /* Output "rep; stos" instruction.
17719 Arguments have same meaning as for previous function */
17720 static void
17723 rtx orig_value)
17724 {
17725 rtx destexp;
17726 rtx countreg;
17733 {
17737 }
17738 else
17741 {
17746 }
17750 }
17752 static void
17755 {
17759 }
17761 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17762 static void
17765 {
17768 {
17773 {
17775 {
17778 }
17779 else
17782 }
17784 {
17787 else
17788 {
17791 }
17793 }
17795 {
17798 }
17800 {
17803 }
17805 {
17808 }
17810 }
17812 {
17818 }
17820 /* When there are stringops, we can cheaply increase dest and src pointers.
17821 Otherwise we save code size by maintaining offset (zero is readily
17822 available from preceding rep operation) and using x86 addressing modes.
17823 */
17825 {
17827 {
17834 }
17836 {
17843 }
17845 {
17852 }
17853 }
17854 else
17855 {
17857 rtx tmp;
17860 {
17871 }
17873 {
17886 }
17888 {
17897 }
17898 }
17899 }
17901 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17902 static void
17905 {
17906 count =
17912 }
17914 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17915 static void
17917 {
17918 rtx dest;
17921 {
17926 {
17928 {
17933 }
17934 else
17937 }
17939 {
17941 {
17944 }
17945 else
17946 {
17951 }
17953 }
17955 {
17959 }
17961 {
17965 }
17967 {
17971 }
17973 }
17975 {
17978 }
17980 {
17983 {
17987 }
17988 else
17989 {
17995 }
17998 }
18000 {
18003 {
18006 }
18007 else
18008 {
18012 }
18015 }
18017 {
18023 }
18025 {
18031 }
18033 {
18039 }
18040 }
18042 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
18043 DESIRED_ALIGNMENT. */
18044 static void
18048 {
18050 {
18058 }
18060 {
18068 }
18070 {
18078 }
18080 }
18082 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
18083 ALIGN_BYTES is how many bytes need to be copied. */
18084 static rtx
18087 {
18097 {
18102 }
18104 {
18115 }
18117 {
18123 {
18131 }
18134 }
18140 {
18152 }
18159 }
18161 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
18162 DESIRED_ALIGNMENT. */
18163 static void
18166 {
18168 {
18175 }
18177 {
18184 }
18186 {
18193 }
18195 }
18197 /* Set enough from DST to align DST known to by aligned by ALIGN to
18198 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
18199 static rtx
18202 {
18206 {
18211 }
18213 {
18220 }
18222 {
18229 }
18236 }
18238 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
18239 static enum stringop_alg
18242 {
18245 /* Algorithms using the rep prefix want at least edi and ecx;
18246 additionally, memset wants eax and memcpy wants esi. Don't
18247 consider such algorithms if the user has appropriated those
18248 registers for their own purposes. */
18250 || (memset
18253 #define ALG_USABLE_P(alg) (rep_prefix_usable \
18254 || (alg != rep_prefix_1_byte \
18255 && alg != rep_prefix_4_byte \
18256 && alg != rep_prefix_8_byte))
18259 /* Even if the string operation call is cold, we still might spend a lot
18260 of time processing large blocks. */
18265 else
18273 else
18277 /* rep; movq or rep; movl is the smallest variant. */
18279 {
18282 else
18284 }
18285 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
18286 */
18290 {
18294 {
18295 /* We get here if the algorithms that were not libcall-based
18296 were rep-prefix based and we are unable to use rep prefixes
18297 based on global register usage. Break out of the loop and
18298 use the heuristic below. */
18302 {
18307 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18308 last non-libcall inline algorithm. */
18310 {
18311 /* When the current size is best to be copied by a libcall,
18312 but we are still forced to inline, run the heuristic below
18313 that will pick code for medium sized blocks. */
18317 }
18320 }
18321 }
18323 }
18324 /* When asked to inline the call anyway, try to pick meaningful choice.
18325 We look for maximal size of block that is faster to copy by hand and
18326 take blocks of at most of that size guessing that average size will
18327 be roughly half of the block.
18329 If this turns out to be bad, we might simply specify the preferred
18330 choice in ix86_costs. */
18333 {
18340 {
18347 }
18348 /* If there aren't any usable algorithms, then recursing on
18349 smaller sizes isn't going to find anything. Just return the
18350 simple byte-at-a-time copy loop. */
18352 {
18353 /* Pick something reasonable. */
18357 }
18366 }
18368 #undef ALG_USABLE_P
18369 }
18371 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18372 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18373 static int
18377 {
18380 {
18391 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18392 copying whole cacheline at once. */
18395 else
18399 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18400 copying whole cacheline at once. */
18403 else
18411 }
18420 }
18422 /* Return the smallest power of 2 greater than VAL. */
18423 static int
18425 {
18430 }
18432 /* Expand string move (memcpy) operation. Use i386 string operations when
18433 profitable. expand_setmem contains similar code. The code depends upon
18434 architecture, block size and alignment, but always has the same
18435 overall structure:
18437 1) Prologue guard: Conditional that jumps up to epilogues for small
18438 blocks that can be handled by epilogue alone. This is faster but
18439 also needed for correctness, since prologue assume the block is larger
18440 than the desired alignment.
18442 Optional dynamic check for size and libcall for large
18443 blocks is emitted here too, with -minline-stringops-dynamically.
18445 2) Prologue: copy first few bytes in order to get destination aligned
18446 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18447 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18448 We emit either a jump tree on power of two sized blocks, or a byte loop.
18450 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18451 with specified algorithm.
18453 4) Epilogue: code copying tail of the block that is too small to be
18454 handled by main body (or up to size guarded by prologue guard). */
18456 int
18459 {
18460 rtx destreg;
18461 rtx srcreg;
18463 rtx tmp;
18476 /* i386 can do misaligned access on reasonably increased cost. */
18480 /* ALIGN is the minimum of destination and source alignment, but we care here
18481 just about destination alignment. */
18490 /* Make sure we don't need to care about overflow later on. */
18494 /* Step 0: Decide on preferred algorithm, desired alignment and
18495 size of chunks to be copied by main loop. */
18511 {
18536 }
18540 /* Step 1: Prologue guard. */
18542 /* Alignment code needs count to be in register. */
18544 {
18547 {
18548 align_bytes
18552 else
18554 }
18557 }
18560 /* Ensure that alignment prologue won't copy past end of block. */
18562 {
18564 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18565 Make sure it is power of 2. */
18569 {
18571 {
18572 /* If main algorithm works on QImode, no epilogue is needed.
18573 For small sizes just don't align anything. */
18576 else
18578 }
18579 }
18580 else
18581 {
18588 else
18590 }
18591 }
18593 /* Emit code to decide on runtime whether library call or inline should be
18594 used. */
18596 {
18598 {
18600 {
18604 }
18605 }
18606 else
18607 {
18616 }
18617 }
18619 /* Step 2: Alignment prologue. */
18622 {
18624 {
18625 /* Except for the first move in epilogue, we no longer know
18626 constant offset in aliasing info. It don't seems to worth
18627 the pain to maintain it for the first move, so throw away
18628 the info early. */
18632 desired_align);
18633 }
18634 else
18635 {
18636 /* If we know how many bytes need to be stored before dst is
18637 sufficiently aligned, maintain aliasing info accurately. */
18642 }
18648 {
18649 /* It is possible that we copied enough so the main loop will not
18650 execute. */
18660 else
18662 }
18663 }
18665 {
18670 }
18674 /* Step 3: Main loop. */
18677 {
18690 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18691 registers for 4 temporaries anyway. */
18694 expected_size);
18698 DImode);
18702 SImode);
18706 QImode);
18708 }
18709 /* Adjust properly the offset of src and dest memory for aliasing. */
18711 {
18716 }
18717 else
18718 {
18721 }
18723 /* Step 4: Epilogue to copy the remaining bytes. */
18724 epilogue:
18726 {
18727 /* When the main loop is done, COUNT_EXP might hold original count,
18728 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18729 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18730 bytes. Compensate if needed. */
18733 {
18734 tmp =
18737 OPTAB_DIRECT);
18740 }
18743 }
18747 epilogue_size_needed);
18751 }
18753 /* Helper function for memcpy. For QImode value 0xXY produce
18754 0xXYXYXYXY of wide specified by MODE. This is essentially
18755 a * 0x10101010, but we can do slightly better than
18756 synth_mult by unwinding the sequence by hand on CPUs with
18757 slow multiply. */
18758 static rtx
18760 {
18762 rtx tmp;
18769 {
18777 }
18786 nops--;
18791 {
18795 OPTAB_DIRECT);
18796 }
18797 else
18798 {
18804 else
18806 else
18807 {
18810 reg =
18812 }
18822 }
18823 }
18825 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18826 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18827 alignment from ALIGN to DESIRED_ALIGN. */
18828 static rtx
18830 {
18831 rtx promoted_val;
18840 else
18844 }
18846 /* Expand string clear operation (bzero). Use i386 string operations when
18847 profitable. See expand_movmem comment for explanation of individual
18848 steps performed. */
18849 int
18852 {
18853 rtx destreg;
18855 rtx tmp;
18870 /* i386 can do misaligned access on reasonably increased cost. */
18879 /* Make sure we don't need to care about overflow later on. */
18883 /* Step 0: Decide on preferred algorithm, desired alignment and
18884 size of chunks to be copied by main loop. */
18899 {
18924 }
18927 /* Step 1: Prologue guard. */
18929 /* Alignment code needs count to be in register. */
18931 {
18934 {
18935 align_bytes
18939 else
18941 }
18943 {
18948 }
18949 }
18950 /* Do the cheap promotion to allow better CSE across the
18951 main loop and epilogue (ie one load of the big constant in the
18952 front of all code. */
18956 /* Ensure that alignment prologue won't copy past end of block. */
18958 {
18960 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18961 Make sure it is power of 2. */
18964 /* To improve performance of small blocks, we jump around the VAL
18965 promoting mode. This mean that if the promoted VAL is not constant,
18966 we might not use it in the epilogue and have to use byte
18967 loop variant. */
18971 {
18973 {
18974 /* If main algorithm works on QImode, no epilogue is needed.
18975 For small sizes just don't align anything. */
18978 else
18980 }
18981 }
18982 else
18983 {
18990 else
18992 }
18993 }
18995 {
19004 }
19006 /* Step 2: Alignment prologue. */
19008 /* Do the expensive promotion once we branched off the small blocks. */
19015 {
19017 {
19018 /* Except for the first move in epilogue, we no longer know
19019 constant offset in aliasing info. It don't seems to worth
19020 the pain to maintain it for the first move, so throw away
19021 the info early. */
19024 desired_align);
19025 }
19026 else
19027 {
19028 /* If we know how many bytes need to be stored before dst is
19029 sufficiently aligned, maintain aliasing info accurately. */
19034 }
19040 {
19041 /* It is possible that we copied enough so the main loop will not
19042 execute. */
19052 else
19054 }
19055 }
19057 {
19063 }
19067 /* Step 3: Main loop. */
19070 {
19098 }
19099 /* Adjust properly the offset of src and dest memory for aliasing. */
19103 else
19106 /* Step 4: Epilogue to copy the remaining bytes. */
19109 {
19110 /* When the main loop is done, COUNT_EXP might hold original count,
19111 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
19112 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
19113 bytes. Compensate if needed. */
19116 {
19117 tmp =
19120 OPTAB_DIRECT);
19123 }
19126 }
19127 epilogue:
19129 {
19132 epilogue_size_needed);
19133 else
19135 epilogue_size_needed);
19136 }
19140 }
19142 /* Expand the appropriate insns for doing strlen if not just doing
19143 repnz; scasb
19145 out = result, initialized with the start address
19146 align_rtx = alignment of the address.
19147 scratch = scratch register, initialized with the startaddress when
19148 not aligned, otherwise undefined
19150 This is just the body. It needs the initializations mentioned above and
19151 some address computing at the end. These things are done in i386.md. */
19153 static void
19155 {
19157 rtx tmp;
19162 rtx mem;
19165 rtx cmp;
19171 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
19173 /* Is there a known alignment and is it less than 4? */
19175 {
19178 /* Is there a known alignment and is it not 2? */
19180 {
19184 /* Leave just the 3 lower bits. */
19194 }
19195 else
19196 {
19197 /* Since the alignment is 2, we have to check 2 or 0 bytes;
19198 check if is aligned to 4 - byte. */
19205 }
19209 /* Now compare the bytes. */
19211 /* Compare the first n unaligned byte on a byte per byte basis. */
19215 /* Increment the address. */
19218 /* Not needed with an alignment of 2 */
19220 {
19224 end_0_label);
19229 }
19232 end_0_label);
19235 }
19237 /* Generate loop to check 4 bytes at a time. It is not a good idea to
19238 align this loop. It gives only huge programs, but does not help to
19239 speed up. */
19246 /* This formula yields a nonzero result iff one of the bytes is zero.
19247 This saves three branches inside loop and many cycles. */
19255 align_4_label);
19258 {
19264 /* If zero is not in the first two bytes, move two bytes forward. */
19270 reg,
19271 tmpreg)));
19272 /* Emit lea manually to avoid clobbering of flags. */
19280 reg2,
19281 out)));
19282 }
19283 else
19284 {
19286 /* Is zero in the first two bytes? */
19293 pc_rtx);
19297 /* Not in the first two. Move two bytes forward. */
19303 }
19305 /* Avoid branch in fixing the byte. */
19313 }
19315 /* Expand strlen. */
19317 int
19319 {
19322 /* The generic case of strlen expander is long. Avoid it's
19323 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19326 && !TARGET_INLINE_ALL_STRINGOPS
19336 {
19337 /* Well it seems that some optimizer does not combine a call like
19338 foo(strlen(bar), strlen(bar));
19339 when the move and the subtraction is done here. It does calculate
19340 the length just once when these instructions are done inside of
19341 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19342 often used and I use one fewer register for the lifetime of
19343 output_strlen_unroll() this is better. */
19349 /* strlensi_unroll_1 returns the address of the zero at the end of
19350 the string, like memchr(), so compute the length by subtracting
19351 the start address. */
19353 }
19354 else
19355 {
19356 rtx unspec;
19358 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19371 /* If .md starts supporting :P, this can be done in .md. */
19377 }
19379 }
19381 /* For given symbol (function) construct code to compute address of it's PLT
19382 entry in large x86-64 PIC model. */
19383 rtx
19385 {
19395 }
19397 void
19399 rtx callarg2,
19401 {
19409 {
19410 #if TARGET_MACHO
19413 #endif
19414 }
19415 else
19416 {
19417 /* Static functions and indirect calls don't need the pic register. */
19422 }
19425 {
19429 }
19439 {
19442 }
19448 {
19452 }
19456 {
19457 /* We need to represent that SI and DI registers are clobbered
19458 by SYSV calls. */
19464 };
19468 UNSPEC_MS_TO_SYSV_CALL);
19475 gen_rtx_REG
19483 }
19488 }
19490 \f
19491 /* Clear stack slot assignments remembered from previous functions.
19492 This is called from INIT_EXPANDERS once before RTL is emitted for each
19493 function. */
19497 {
19506 }
19508 /* Return a MEM corresponding to a stack slot with mode MODE.
19509 Allocate a new slot if necessary.
19511 The RTL for a function can have several slots available: N is
19512 which slot to use. */
19514 rtx
19516 {
19521 /* Virtual slot is valid only before vregs are instantiated. */
19537 }
19539 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19542 rtx
19544 {
19547 {
19549 (TARGET_ANY_GNU_TLS
19553 }
19556 }
19558 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19561 rtx
19563 {
19566 {
19571 }
19574 }
19575 \f
19576 /* Calculate the length of the memory address in the instruction
19577 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19579 int
19581 {
19606 /* Rule of thumb:
19607 - esp as the base always wants an index,
19608 - ebp as the base always wants a displacement,
19609 - r12 as the base always wants an index,
19610 - r13 as the base always wants a displacement. */
19612 /* Register Indirect. */
19614 {
19615 /* esp (for its index) and ebp (for its displacement) need
19616 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19617 code. */
19626 }
19628 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19629 is not disp32, but disp32(%rip), so for disp32
19630 SIB byte is needed, unless print_operand_address
19631 optimizes it into disp32(%rip) or (%rip) is implied
19632 by UNSPEC. */
19634 {
19637 {
19653 }
19654 }
19656 else
19657 {
19658 /* Find the length of the displacement constant. */
19660 {
19663 else
19665 }
19666 /* ebp always wants a displacement. Similarly r13. */
19671 /* An index requires the two-byte modrm form.... */
19673 /* ...like esp (or r12), which always wants an index. */
19679 }
19682 {
19689 }
19692 }
19694 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19695 is set, expect that insn have 8bit immediate alternative. */
19696 int
19698 {
19704 {
19709 {
19712 {
19724 }
19726 {
19729 }
19730 }
19732 {
19742 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19748 }
19749 }
19751 }
19752 /* Compute default value for "length_address" attribute. */
19753 int
19755 {
19759 {
19769 {
19774 }
19777 }
19782 {
19785 {
19790 constraints++;
19793 ;
19794 /* Skip ignored operands. */
19797 }
19799 }
19801 }
19803 /* Compute default value for "length_vex" attribute. It includes
19804 2 or 3 byte VEX prefix and 1 opcode byte. */
19806 int
19809 {
19812 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19813 byte VEX prefix. */
19817 /* We can always use 2 byte VEX prefix in 32bit. */
19825 {
19826 /* REX.W bit uses 3 byte VEX prefix. */
19830 }
19831 else
19832 {
19833 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19837 }
19840 }
19841 \f
19842 /* Return the maximum number of instructions a cpu can issue. */
19844 static int
19846 {
19848 {
19870 }
19871 }
19873 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19874 by DEP_INSN and nothing set by DEP_INSN. */
19876 static int
19878 {
19881 /* Simplify the test for uninteresting insns. */
19889 {
19892 }
19897 {
19900 }
19901 else
19907 /* This test is true if the dependent insn reads the flags but
19908 not any other potentially set register. */
19916 }
19918 /* Return true iff USE_INSN has a memory address with operands set by
19919 SET_INSN. */
19921 bool
19923 {
19928 {
19931 }
19933 }
19935 static int
19937 {
19943 /* Anti and output dependencies have zero cost on all CPUs. */
19949 /* If we can't recognize the insns, we can't really do anything. */
19957 {
19959 /* Address Generation Interlock adds a cycle of latency. */
19961 {
19972 }
19976 /* ??? Compares pair with jump/setcc. */
19980 /* Floating point stores require value to be ready one cycle earlier. */
19990 /* INT->FP conversion is expensive. */
19994 /* There is one cycle extra latency between an FP op and a store. */
20002 /* Show ability of reorder buffer to hide latency of load by executing
20003 in parallel with previous instruction in case
20004 previous instruction is not needed to compute the address. */
20007 {
20008 /* Claim moves to take one cycle, as core can issue one load
20009 at time and the next load can start cycle later. */
20014 cost--;
20015 }
20021 /* The esp dependency is resolved before the instruction is really
20022 finished. */
20027 /* INT->FP conversion is expensive. */
20031 /* Show ability of reorder buffer to hide latency of load by executing
20032 in parallel with previous instruction in case
20033 previous instruction is not needed to compute the address. */
20036 {
20037 /* Claim moves to take one cycle, as core can issue one load
20038 at time and the next load can start cycle later. */
20044 else
20046 }
20058 /* Show ability of reorder buffer to hide latency of load by executing
20059 in parallel with previous instruction in case
20060 previous instruction is not needed to compute the address. */
20063 {
20067 /* Because of the difference between the length of integer and
20068 floating unit pipeline preparation stages, the memory operands
20069 for floating point are cheaper.
20071 ??? For Athlon it the difference is most probably 2. */
20074 else
20079 else
20081 }
20085 }
20088 }
20090 /* How many alternative schedules to try. This should be as wide as the
20091 scheduling freedom in the DFA, but no wider. Making this value too
20092 large results extra work for the scheduler. */
20094 static int
20096 {
20098 {
20108 }
20109 }
20111 \f
20112 /* Compute the alignment given to a constant that is being placed in memory.
20113 EXP is the constant and ALIGN is the alignment that the object would
20114 ordinarily have.
20115 The value of this function is used instead of that alignment to align
20116 the object. */
20118 int
20120 {
20123 {
20128 }
20134 }
20136 /* Compute the alignment for a static variable.
20137 TYPE is the data type, and ALIGN is the alignment that
20138 the object would ordinarily have. The value of this function is used
20139 instead of that alignment to align the object. */
20141 int
20143 {
20154 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20155 to 16byte boundary. */
20157 {
20164 }
20167 {
20172 }
20174 {
20181 }
20186 {
20191 }
20194 {
20199 }
20202 }
20204 /* Compute the alignment for a local variable or a stack slot. EXP is
20205 the data type or decl itself, MODE is the widest mode available and
20206 ALIGN is the alignment that the object would ordinarily have. The
20207 value of this macro is used instead of that alignment to align the
20208 object. */
20210 unsigned int
20213 {
20217 {
20220 }
20221 else
20222 {
20225 }
20227 /* Don't do dynamic stack realignment for long long objects with
20228 -mpreferred-stack-boundary=2. */
20237 /* If TYPE is NULL, we are allocating a stack slot for caller-save
20238 register in MODE. We will return the largest alignment of XF
20239 and DF. */
20241 {
20245 }
20247 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20248 to 16byte boundary. Exact wording is:
20250 An array uses the same alignment as its elements, except that a local or
20251 global array variable of length at least 16 bytes or
20252 a C99 variable-length array variable always has alignment of at least 16 bytes.
20254 This was added to allow use of aligned SSE instructions at arrays. This
20255 rule is meant for static storage (where compiler can not do the analysis
20256 by itself). We follow it for automatic variables only when convenient.
20257 We fully control everything in the function compiled and functions from
20258 other unit can not rely on the alignment.
20260 Exclude va_list type. It is the common case of local array where
20261 we can not benefit from the alignment. */
20264 {
20273 }
20275 {
20280 }
20282 {
20288 }
20293 {
20298 }
20301 {
20307 }
20309 }
20311 /* Compute the minimum required alignment for dynamic stack realignment
20312 purposes for a local variable, parameter or a stack slot. EXP is
20313 the data type or decl itself, MODE is its mode and ALIGN is the
20314 alignment that the object would ordinarily have. */
20316 unsigned int
20319 {
20326 {
20329 }
20330 else
20331 {
20334 }
20336 /* Don't do dynamic stack realignment for long long objects with
20337 -mpreferred-stack-boundary=2. */
20344 }
20345 \f
20346 /* Find a location for the static chain incoming to a nested function.
20347 This is a register, unless all free registers are used by arguments. */
20349 static rtx
20351 {
20358 {
20359 /* We always use R10 in 64-bit mode. */
20361 }
20362 else
20363 {
20364 tree fntype;
20365 /* By default in 32-bit mode we use ECX to pass the static chain. */
20370 {
20371 /* Fastcall functions use ecx/edx for arguments, which leaves
20372 us with EAX for the static chain. */
20374 }
20376 {
20377 /* Thiscall functions use ecx for arguments, which leaves
20378 us with EAX for the static chain. */
20380 }
20382 {
20383 /* For regparm 3, we have no free call-clobbered registers in
20384 which to store the static chain. In order to implement this,
20385 we have the trampoline push the static chain to the stack.
20386 However, we can't push a value below the return address when
20387 we call the nested function directly, so we have to use an
20388 alternate entry point. For this we use ESI, and have the
20389 alternate entry point push ESI, so that things appear the
20390 same once we're executing the nested function. */
20392 {
20397 }
20399 }
20400 }
20403 }
20405 /* Emit RTL insns to initialize the variable parts of a trampoline.
20406 FNDECL is the decl of the target address; M_TRAMP is a MEM for
20407 the trampoline, and CHAIN_VALUE is an RTX for the static chain
20408 to be passed to the target function. */
20410 static void
20412 {
20418 {
20422 /* Depending on the static chain location, either load a register
20423 with a constant, or push the constant to the stack. All of the
20424 instructions are the same size. */
20427 {
20432 else
20434 }
20435 else
20444 /* Compute offset from the end of the jmp to the target function.
20445 In the case in which the trampoline stores the static chain on
20446 the stack, we need to skip the first insn which pushes the
20447 (call-saved) register static chain; this push is 1 byte. */
20458 }
20459 else
20460 {
20463 /* Load the function address to r11. Try to load address using
20464 the shorter movl instead of movabs. We may want to support
20465 movq for kernel mode, but kernel does not use trampolines at
20466 the moment. */
20468 {
20477 }
20478 else
20479 {
20486 }
20488 /* Load static chain using movabs to r10. */
20496 /* Jump to r11; the last (unused) byte is a nop, only there to
20497 pad the write out to a single 32-bit store. */
20503 }
20505 #ifdef ENABLE_EXECUTE_STACK
20506 #ifdef CHECK_EXECUTE_STACK_ENABLED
20508 #endif
20511 #endif
20512 }
20513 \f
20514 /* The following file contains several enumerations and data structures
20515 built from the definitions in i386-builtin-types.def. */
20519 /* Table for the ix86 builtin non-function types. */
20522 /* Retrieve an element from the above table, building some of
20523 the types lazily. */
20525 static tree
20527 {
20539 {
20547 }
20548 else
20549 {
20555 else
20563 }
20567 }
20569 /* Table for the ix86 builtin function types. */
20572 /* Retrieve an element from the above table, building some of
20573 the types lazily. */
20575 static tree
20577 {
20578 tree type;
20587 {
20595 {
20598 }
20601 }
20602 else
20603 {
20609 }
20613 }
20616 /* Codes for all the SSE/MMX builtins. */
20617 enum ix86_builtins
20618 {
20619 IX86_BUILTIN_ADDPS,
20620 IX86_BUILTIN_ADDSS,
20621 IX86_BUILTIN_DIVPS,
20622 IX86_BUILTIN_DIVSS,
20623 IX86_BUILTIN_MULPS,
20624 IX86_BUILTIN_MULSS,
20625 IX86_BUILTIN_SUBPS,
20626 IX86_BUILTIN_SUBSS,
20628 IX86_BUILTIN_CMPEQPS,
20629 IX86_BUILTIN_CMPLTPS,
20630 IX86_BUILTIN_CMPLEPS,
20631 IX86_BUILTIN_CMPGTPS,
20632 IX86_BUILTIN_CMPGEPS,
20633 IX86_BUILTIN_CMPNEQPS,
20634 IX86_BUILTIN_CMPNLTPS,
20635 IX86_BUILTIN_CMPNLEPS,
20636 IX86_BUILTIN_CMPNGTPS,
20637 IX86_BUILTIN_CMPNGEPS,
20638 IX86_BUILTIN_CMPORDPS,
20639 IX86_BUILTIN_CMPUNORDPS,
20640 IX86_BUILTIN_CMPEQSS,
20641 IX86_BUILTIN_CMPLTSS,
20642 IX86_BUILTIN_CMPLESS,
20643 IX86_BUILTIN_CMPNEQSS,
20644 IX86_BUILTIN_CMPNLTSS,
20645 IX86_BUILTIN_CMPNLESS,
20646 IX86_BUILTIN_CMPNGTSS,
20647 IX86_BUILTIN_CMPNGESS,
20648 IX86_BUILTIN_CMPORDSS,
20649 IX86_BUILTIN_CMPUNORDSS,
20651 IX86_BUILTIN_COMIEQSS,
20652 IX86_BUILTIN_COMILTSS,
20653 IX86_BUILTIN_COMILESS,
20654 IX86_BUILTIN_COMIGTSS,
20655 IX86_BUILTIN_COMIGESS,
20656 IX86_BUILTIN_COMINEQSS,
20657 IX86_BUILTIN_UCOMIEQSS,
20658 IX86_BUILTIN_UCOMILTSS,
20659 IX86_BUILTIN_UCOMILESS,
20660 IX86_BUILTIN_UCOMIGTSS,
20661 IX86_BUILTIN_UCOMIGESS,
20662 IX86_BUILTIN_UCOMINEQSS,
20664 IX86_BUILTIN_CVTPI2PS,
20665 IX86_BUILTIN_CVTPS2PI,
20666 IX86_BUILTIN_CVTSI2SS,
20667 IX86_BUILTIN_CVTSI642SS,
20668 IX86_BUILTIN_CVTSS2SI,
20669 IX86_BUILTIN_CVTSS2SI64,
20670 IX86_BUILTIN_CVTTPS2PI,
20671 IX86_BUILTIN_CVTTSS2SI,
20672 IX86_BUILTIN_CVTTSS2SI64,
20674 IX86_BUILTIN_MAXPS,
20675 IX86_BUILTIN_MAXSS,
20676 IX86_BUILTIN_MINPS,
20677 IX86_BUILTIN_MINSS,
20679 IX86_BUILTIN_LOADUPS,
20680 IX86_BUILTIN_STOREUPS,
20681 IX86_BUILTIN_MOVSS,
20683 IX86_BUILTIN_MOVHLPS,
20684 IX86_BUILTIN_MOVLHPS,
20685 IX86_BUILTIN_LOADHPS,
20686 IX86_BUILTIN_LOADLPS,
20687 IX86_BUILTIN_STOREHPS,
20688 IX86_BUILTIN_STORELPS,
20690 IX86_BUILTIN_MASKMOVQ,
20691 IX86_BUILTIN_MOVMSKPS,
20692 IX86_BUILTIN_PMOVMSKB,
20694 IX86_BUILTIN_MOVNTPS,
20695 IX86_BUILTIN_MOVNTQ,
20697 IX86_BUILTIN_LOADDQU,
20698 IX86_BUILTIN_STOREDQU,
20700 IX86_BUILTIN_PACKSSWB,
20701 IX86_BUILTIN_PACKSSDW,
20702 IX86_BUILTIN_PACKUSWB,
20704 IX86_BUILTIN_PADDB,
20705 IX86_BUILTIN_PADDW,
20706 IX86_BUILTIN_PADDD,
20707 IX86_BUILTIN_PADDQ,
20708 IX86_BUILTIN_PADDSB,
20709 IX86_BUILTIN_PADDSW,
20710 IX86_BUILTIN_PADDUSB,
20711 IX86_BUILTIN_PADDUSW,
20712 IX86_BUILTIN_PSUBB,
20713 IX86_BUILTIN_PSUBW,
20714 IX86_BUILTIN_PSUBD,
20715 IX86_BUILTIN_PSUBQ,
20716 IX86_BUILTIN_PSUBSB,
20717 IX86_BUILTIN_PSUBSW,
20718 IX86_BUILTIN_PSUBUSB,
20719 IX86_BUILTIN_PSUBUSW,
20721 IX86_BUILTIN_PAND,
20722 IX86_BUILTIN_PANDN,
20723 IX86_BUILTIN_POR,
20724 IX86_BUILTIN_PXOR,
20726 IX86_BUILTIN_PAVGB,
20727 IX86_BUILTIN_PAVGW,
20729 IX86_BUILTIN_PCMPEQB,
20730 IX86_BUILTIN_PCMPEQW,
20731 IX86_BUILTIN_PCMPEQD,
20732 IX86_BUILTIN_PCMPGTB,
20733 IX86_BUILTIN_PCMPGTW,
20734 IX86_BUILTIN_PCMPGTD,
20736 IX86_BUILTIN_PMADDWD,
20738 IX86_BUILTIN_PMAXSW,
20739 IX86_BUILTIN_PMAXUB,
20740 IX86_BUILTIN_PMINSW,
20741 IX86_BUILTIN_PMINUB,
20743 IX86_BUILTIN_PMULHUW,
20744 IX86_BUILTIN_PMULHW,
20745 IX86_BUILTIN_PMULLW,
20747 IX86_BUILTIN_PSADBW,
20748 IX86_BUILTIN_PSHUFW,
20750 IX86_BUILTIN_PSLLW,
20751 IX86_BUILTIN_PSLLD,
20752 IX86_BUILTIN_PSLLQ,
20753 IX86_BUILTIN_PSRAW,
20754 IX86_BUILTIN_PSRAD,
20755 IX86_BUILTIN_PSRLW,
20756 IX86_BUILTIN_PSRLD,
20757 IX86_BUILTIN_PSRLQ,
20758 IX86_BUILTIN_PSLLWI,
20759 IX86_BUILTIN_PSLLDI,
20760 IX86_BUILTIN_PSLLQI,
20761 IX86_BUILTIN_PSRAWI,
20762 IX86_BUILTIN_PSRADI,
20763 IX86_BUILTIN_PSRLWI,
20764 IX86_BUILTIN_PSRLDI,
20765 IX86_BUILTIN_PSRLQI,
20767 IX86_BUILTIN_PUNPCKHBW,
20768 IX86_BUILTIN_PUNPCKHWD,
20769 IX86_BUILTIN_PUNPCKHDQ,
20770 IX86_BUILTIN_PUNPCKLBW,
20771 IX86_BUILTIN_PUNPCKLWD,
20772 IX86_BUILTIN_PUNPCKLDQ,
20774 IX86_BUILTIN_SHUFPS,
20776 IX86_BUILTIN_RCPPS,
20777 IX86_BUILTIN_RCPSS,
20778 IX86_BUILTIN_RSQRTPS,
20779 IX86_BUILTIN_RSQRTPS_NR,
20780 IX86_BUILTIN_RSQRTSS,
20781 IX86_BUILTIN_RSQRTF,
20782 IX86_BUILTIN_SQRTPS,
20783 IX86_BUILTIN_SQRTPS_NR,
20784 IX86_BUILTIN_SQRTSS,
20786 IX86_BUILTIN_UNPCKHPS,
20787 IX86_BUILTIN_UNPCKLPS,
20789 IX86_BUILTIN_ANDPS,
20790 IX86_BUILTIN_ANDNPS,
20791 IX86_BUILTIN_ORPS,
20792 IX86_BUILTIN_XORPS,
20794 IX86_BUILTIN_EMMS,
20795 IX86_BUILTIN_LDMXCSR,
20796 IX86_BUILTIN_STMXCSR,
20797 IX86_BUILTIN_SFENCE,
20799 /* 3DNow! Original */
20800 IX86_BUILTIN_FEMMS,
20801 IX86_BUILTIN_PAVGUSB,
20802 IX86_BUILTIN_PF2ID,
20803 IX86_BUILTIN_PFACC,
20804 IX86_BUILTIN_PFADD,
20805 IX86_BUILTIN_PFCMPEQ,
20806 IX86_BUILTIN_PFCMPGE,
20807 IX86_BUILTIN_PFCMPGT,
20808 IX86_BUILTIN_PFMAX,
20809 IX86_BUILTIN_PFMIN,
20810 IX86_BUILTIN_PFMUL,
20811 IX86_BUILTIN_PFRCP,
20812 IX86_BUILTIN_PFRCPIT1,
20813 IX86_BUILTIN_PFRCPIT2,
20814 IX86_BUILTIN_PFRSQIT1,
20815 IX86_BUILTIN_PFRSQRT,
20816 IX86_BUILTIN_PFSUB,
20817 IX86_BUILTIN_PFSUBR,
20818 IX86_BUILTIN_PI2FD,
20819 IX86_BUILTIN_PMULHRW,
20821 /* 3DNow! Athlon Extensions */
20822 IX86_BUILTIN_PF2IW,
20823 IX86_BUILTIN_PFNACC,
20824 IX86_BUILTIN_PFPNACC,
20825 IX86_BUILTIN_PI2FW,
20826 IX86_BUILTIN_PSWAPDSI,
20827 IX86_BUILTIN_PSWAPDSF,
20829 /* SSE2 */
20830 IX86_BUILTIN_ADDPD,
20831 IX86_BUILTIN_ADDSD,
20832 IX86_BUILTIN_DIVPD,
20833 IX86_BUILTIN_DIVSD,
20834 IX86_BUILTIN_MULPD,
20835 IX86_BUILTIN_MULSD,
20836 IX86_BUILTIN_SUBPD,
20837 IX86_BUILTIN_SUBSD,
20839 IX86_BUILTIN_CMPEQPD,
20840 IX86_BUILTIN_CMPLTPD,
20841 IX86_BUILTIN_CMPLEPD,
20842 IX86_BUILTIN_CMPGTPD,
20843 IX86_BUILTIN_CMPGEPD,
20844 IX86_BUILTIN_CMPNEQPD,
20845 IX86_BUILTIN_CMPNLTPD,
20846 IX86_BUILTIN_CMPNLEPD,
20847 IX86_BUILTIN_CMPNGTPD,
20848 IX86_BUILTIN_CMPNGEPD,
20849 IX86_BUILTIN_CMPORDPD,
20850 IX86_BUILTIN_CMPUNORDPD,
20851 IX86_BUILTIN_CMPEQSD,
20852 IX86_BUILTIN_CMPLTSD,
20853 IX86_BUILTIN_CMPLESD,
20854 IX86_BUILTIN_CMPNEQSD,
20855 IX86_BUILTIN_CMPNLTSD,
20856 IX86_BUILTIN_CMPNLESD,
20857 IX86_BUILTIN_CMPORDSD,
20858 IX86_BUILTIN_CMPUNORDSD,
20860 IX86_BUILTIN_COMIEQSD,
20861 IX86_BUILTIN_COMILTSD,
20862 IX86_BUILTIN_COMILESD,
20863 IX86_BUILTIN_COMIGTSD,
20864 IX86_BUILTIN_COMIGESD,
20865 IX86_BUILTIN_COMINEQSD,
20866 IX86_BUILTIN_UCOMIEQSD,
20867 IX86_BUILTIN_UCOMILTSD,
20868 IX86_BUILTIN_UCOMILESD,
20869 IX86_BUILTIN_UCOMIGTSD,
20870 IX86_BUILTIN_UCOMIGESD,
20871 IX86_BUILTIN_UCOMINEQSD,
20873 IX86_BUILTIN_MAXPD,
20874 IX86_BUILTIN_MAXSD,
20875 IX86_BUILTIN_MINPD,
20876 IX86_BUILTIN_MINSD,
20878 IX86_BUILTIN_ANDPD,
20879 IX86_BUILTIN_ANDNPD,
20880 IX86_BUILTIN_ORPD,
20881 IX86_BUILTIN_XORPD,
20883 IX86_BUILTIN_SQRTPD,
20884 IX86_BUILTIN_SQRTSD,
20886 IX86_BUILTIN_UNPCKHPD,
20887 IX86_BUILTIN_UNPCKLPD,
20889 IX86_BUILTIN_SHUFPD,
20891 IX86_BUILTIN_LOADUPD,
20892 IX86_BUILTIN_STOREUPD,
20893 IX86_BUILTIN_MOVSD,
20895 IX86_BUILTIN_LOADHPD,
20896 IX86_BUILTIN_LOADLPD,
20898 IX86_BUILTIN_CVTDQ2PD,
20899 IX86_BUILTIN_CVTDQ2PS,
20901 IX86_BUILTIN_CVTPD2DQ,
20902 IX86_BUILTIN_CVTPD2PI,
20903 IX86_BUILTIN_CVTPD2PS,
20904 IX86_BUILTIN_CVTTPD2DQ,
20905 IX86_BUILTIN_CVTTPD2PI,
20907 IX86_BUILTIN_CVTPI2PD,
20908 IX86_BUILTIN_CVTSI2SD,
20909 IX86_BUILTIN_CVTSI642SD,
20911 IX86_BUILTIN_CVTSD2SI,
20912 IX86_BUILTIN_CVTSD2SI64,
20913 IX86_BUILTIN_CVTSD2SS,
20914 IX86_BUILTIN_CVTSS2SD,
20915 IX86_BUILTIN_CVTTSD2SI,
20916 IX86_BUILTIN_CVTTSD2SI64,
20918 IX86_BUILTIN_CVTPS2DQ,
20919 IX86_BUILTIN_CVTPS2PD,
20920 IX86_BUILTIN_CVTTPS2DQ,
20922 IX86_BUILTIN_MOVNTI,
20923 IX86_BUILTIN_MOVNTPD,
20924 IX86_BUILTIN_MOVNTDQ,
20926 IX86_BUILTIN_MOVQ128,
20928 /* SSE2 MMX */
20929 IX86_BUILTIN_MASKMOVDQU,
20930 IX86_BUILTIN_MOVMSKPD,
20931 IX86_BUILTIN_PMOVMSKB128,
20933 IX86_BUILTIN_PACKSSWB128,
20934 IX86_BUILTIN_PACKSSDW128,
20935 IX86_BUILTIN_PACKUSWB128,
20937 IX86_BUILTIN_PADDB128,
20938 IX86_BUILTIN_PADDW128,
20939 IX86_BUILTIN_PADDD128,
20940 IX86_BUILTIN_PADDQ128,
20941 IX86_BUILTIN_PADDSB128,
20942 IX86_BUILTIN_PADDSW128,
20943 IX86_BUILTIN_PADDUSB128,
20944 IX86_BUILTIN_PADDUSW128,
20945 IX86_BUILTIN_PSUBB128,
20946 IX86_BUILTIN_PSUBW128,
20947 IX86_BUILTIN_PSUBD128,
20948 IX86_BUILTIN_PSUBQ128,
20949 IX86_BUILTIN_PSUBSB128,
20950 IX86_BUILTIN_PSUBSW128,
20951 IX86_BUILTIN_PSUBUSB128,
20952 IX86_BUILTIN_PSUBUSW128,
20954 IX86_BUILTIN_PAND128,
20955 IX86_BUILTIN_PANDN128,
20956 IX86_BUILTIN_POR128,
20957 IX86_BUILTIN_PXOR128,
20959 IX86_BUILTIN_PAVGB128,
20960 IX86_BUILTIN_PAVGW128,
20962 IX86_BUILTIN_PCMPEQB128,
20963 IX86_BUILTIN_PCMPEQW128,
20964 IX86_BUILTIN_PCMPEQD128,
20965 IX86_BUILTIN_PCMPGTB128,
20966 IX86_BUILTIN_PCMPGTW128,
20967 IX86_BUILTIN_PCMPGTD128,
20969 IX86_BUILTIN_PMADDWD128,
20971 IX86_BUILTIN_PMAXSW128,
20972 IX86_BUILTIN_PMAXUB128,
20973 IX86_BUILTIN_PMINSW128,
20974 IX86_BUILTIN_PMINUB128,
20976 IX86_BUILTIN_PMULUDQ,
20977 IX86_BUILTIN_PMULUDQ128,
20978 IX86_BUILTIN_PMULHUW128,
20979 IX86_BUILTIN_PMULHW128,
20980 IX86_BUILTIN_PMULLW128,
20982 IX86_BUILTIN_PSADBW128,
20983 IX86_BUILTIN_PSHUFHW,
20984 IX86_BUILTIN_PSHUFLW,
20985 IX86_BUILTIN_PSHUFD,
20987 IX86_BUILTIN_PSLLDQI128,
20988 IX86_BUILTIN_PSLLWI128,
20989 IX86_BUILTIN_PSLLDI128,
20990 IX86_BUILTIN_PSLLQI128,
20991 IX86_BUILTIN_PSRAWI128,
20992 IX86_BUILTIN_PSRADI128,
20993 IX86_BUILTIN_PSRLDQI128,
20994 IX86_BUILTIN_PSRLWI128,
20995 IX86_BUILTIN_PSRLDI128,
20996 IX86_BUILTIN_PSRLQI128,
20998 IX86_BUILTIN_PSLLDQ128,
20999 IX86_BUILTIN_PSLLW128,
21000 IX86_BUILTIN_PSLLD128,
21001 IX86_BUILTIN_PSLLQ128,
21002 IX86_BUILTIN_PSRAW128,
21003 IX86_BUILTIN_PSRAD128,
21004 IX86_BUILTIN_PSRLW128,
21005 IX86_BUILTIN_PSRLD128,
21006 IX86_BUILTIN_PSRLQ128,
21008 IX86_BUILTIN_PUNPCKHBW128,
21009 IX86_BUILTIN_PUNPCKHWD128,
21010 IX86_BUILTIN_PUNPCKHDQ128,
21011 IX86_BUILTIN_PUNPCKHQDQ128,
21012 IX86_BUILTIN_PUNPCKLBW128,
21013 IX86_BUILTIN_PUNPCKLWD128,
21014 IX86_BUILTIN_PUNPCKLDQ128,
21015 IX86_BUILTIN_PUNPCKLQDQ128,
21017 IX86_BUILTIN_CLFLUSH,
21018 IX86_BUILTIN_MFENCE,
21019 IX86_BUILTIN_LFENCE,
21021 IX86_BUILTIN_BSRSI,
21022 IX86_BUILTIN_BSRDI,
21023 IX86_BUILTIN_RDPMC,
21024 IX86_BUILTIN_RDTSC,
21025 IX86_BUILTIN_RDTSCP,
21026 IX86_BUILTIN_ROLQI,
21027 IX86_BUILTIN_ROLHI,
21028 IX86_BUILTIN_RORQI,
21029 IX86_BUILTIN_RORHI,
21031 /* SSE3. */
21032 IX86_BUILTIN_ADDSUBPS,
21033 IX86_BUILTIN_HADDPS,
21034 IX86_BUILTIN_HSUBPS,
21035 IX86_BUILTIN_MOVSHDUP,
21036 IX86_BUILTIN_MOVSLDUP,
21037 IX86_BUILTIN_ADDSUBPD,
21038 IX86_BUILTIN_HADDPD,
21039 IX86_BUILTIN_HSUBPD,
21040 IX86_BUILTIN_LDDQU,
21042 IX86_BUILTIN_MONITOR,
21043 IX86_BUILTIN_MWAIT,
21045 /* SSSE3. */
21046 IX86_BUILTIN_PHADDW,
21047 IX86_BUILTIN_PHADDD,
21048 IX86_BUILTIN_PHADDSW,
21049 IX86_BUILTIN_PHSUBW,
21050 IX86_BUILTIN_PHSUBD,
21051 IX86_BUILTIN_PHSUBSW,
21052 IX86_BUILTIN_PMADDUBSW,
21053 IX86_BUILTIN_PMULHRSW,
21054 IX86_BUILTIN_PSHUFB,
21055 IX86_BUILTIN_PSIGNB,
21056 IX86_BUILTIN_PSIGNW,
21057 IX86_BUILTIN_PSIGND,
21058 IX86_BUILTIN_PALIGNR,
21059 IX86_BUILTIN_PABSB,
21060 IX86_BUILTIN_PABSW,
21061 IX86_BUILTIN_PABSD,
21063 IX86_BUILTIN_PHADDW128,
21064 IX86_BUILTIN_PHADDD128,
21065 IX86_BUILTIN_PHADDSW128,
21066 IX86_BUILTIN_PHSUBW128,
21067 IX86_BUILTIN_PHSUBD128,
21068 IX86_BUILTIN_PHSUBSW128,
21069 IX86_BUILTIN_PMADDUBSW128,
21070 IX86_BUILTIN_PMULHRSW128,
21071 IX86_BUILTIN_PSHUFB128,
21072 IX86_BUILTIN_PSIGNB128,
21073 IX86_BUILTIN_PSIGNW128,
21074 IX86_BUILTIN_PSIGND128,
21075 IX86_BUILTIN_PALIGNR128,
21076 IX86_BUILTIN_PABSB128,
21077 IX86_BUILTIN_PABSW128,
21078 IX86_BUILTIN_PABSD128,
21080 /* AMDFAM10 - SSE4A New Instructions. */
21081 IX86_BUILTIN_MOVNTSD,
21082 IX86_BUILTIN_MOVNTSS,
21083 IX86_BUILTIN_EXTRQI,
21084 IX86_BUILTIN_EXTRQ,
21085 IX86_BUILTIN_INSERTQI,
21086 IX86_BUILTIN_INSERTQ,
21088 /* SSE4.1. */
21089 IX86_BUILTIN_BLENDPD,
21090 IX86_BUILTIN_BLENDPS,
21091 IX86_BUILTIN_BLENDVPD,
21092 IX86_BUILTIN_BLENDVPS,
21093 IX86_BUILTIN_PBLENDVB128,
21094 IX86_BUILTIN_PBLENDW128,
21096 IX86_BUILTIN_DPPD,
21097 IX86_BUILTIN_DPPS,
21099 IX86_BUILTIN_INSERTPS128,
21101 IX86_BUILTIN_MOVNTDQA,
21102 IX86_BUILTIN_MPSADBW128,
21103 IX86_BUILTIN_PACKUSDW128,
21104 IX86_BUILTIN_PCMPEQQ,
21105 IX86_BUILTIN_PHMINPOSUW128,
21107 IX86_BUILTIN_PMAXSB128,
21108 IX86_BUILTIN_PMAXSD128,
21109 IX86_BUILTIN_PMAXUD128,
21110 IX86_BUILTIN_PMAXUW128,
21112 IX86_BUILTIN_PMINSB128,
21113 IX86_BUILTIN_PMINSD128,
21114 IX86_BUILTIN_PMINUD128,
21115 IX86_BUILTIN_PMINUW128,
21117 IX86_BUILTIN_PMOVSXBW128,
21118 IX86_BUILTIN_PMOVSXBD128,
21119 IX86_BUILTIN_PMOVSXBQ128,
21120 IX86_BUILTIN_PMOVSXWD128,
21121 IX86_BUILTIN_PMOVSXWQ128,
21122 IX86_BUILTIN_PMOVSXDQ128,
21124 IX86_BUILTIN_PMOVZXBW128,
21125 IX86_BUILTIN_PMOVZXBD128,
21126 IX86_BUILTIN_PMOVZXBQ128,
21127 IX86_BUILTIN_PMOVZXWD128,
21128 IX86_BUILTIN_PMOVZXWQ128,
21129 IX86_BUILTIN_PMOVZXDQ128,
21131 IX86_BUILTIN_PMULDQ128,
21132 IX86_BUILTIN_PMULLD128,
21134 IX86_BUILTIN_ROUNDPD,
21135 IX86_BUILTIN_ROUNDPS,
21136 IX86_BUILTIN_ROUNDSD,
21137 IX86_BUILTIN_ROUNDSS,
21139 IX86_BUILTIN_PTESTZ,
21140 IX86_BUILTIN_PTESTC,
21141 IX86_BUILTIN_PTESTNZC,
21143 IX86_BUILTIN_VEC_INIT_V2SI,
21144 IX86_BUILTIN_VEC_INIT_V4HI,
21145 IX86_BUILTIN_VEC_INIT_V8QI,
21146 IX86_BUILTIN_VEC_EXT_V2DF,
21147 IX86_BUILTIN_VEC_EXT_V2DI,
21148 IX86_BUILTIN_VEC_EXT_V4SF,
21149 IX86_BUILTIN_VEC_EXT_V4SI,
21150 IX86_BUILTIN_VEC_EXT_V8HI,
21151 IX86_BUILTIN_VEC_EXT_V2SI,
21152 IX86_BUILTIN_VEC_EXT_V4HI,
21153 IX86_BUILTIN_VEC_EXT_V16QI,
21154 IX86_BUILTIN_VEC_SET_V2DI,
21155 IX86_BUILTIN_VEC_SET_V4SF,
21156 IX86_BUILTIN_VEC_SET_V4SI,
21157 IX86_BUILTIN_VEC_SET_V8HI,
21158 IX86_BUILTIN_VEC_SET_V4HI,
21159 IX86_BUILTIN_VEC_SET_V16QI,
21161 IX86_BUILTIN_VEC_PACK_SFIX,
21163 /* SSE4.2. */
21164 IX86_BUILTIN_CRC32QI,
21165 IX86_BUILTIN_CRC32HI,
21166 IX86_BUILTIN_CRC32SI,
21167 IX86_BUILTIN_CRC32DI,
21169 IX86_BUILTIN_PCMPESTRI128,
21170 IX86_BUILTIN_PCMPESTRM128,
21171 IX86_BUILTIN_PCMPESTRA128,
21172 IX86_BUILTIN_PCMPESTRC128,
21173 IX86_BUILTIN_PCMPESTRO128,
21174 IX86_BUILTIN_PCMPESTRS128,
21175 IX86_BUILTIN_PCMPESTRZ128,
21176 IX86_BUILTIN_PCMPISTRI128,
21177 IX86_BUILTIN_PCMPISTRM128,
21178 IX86_BUILTIN_PCMPISTRA128,
21179 IX86_BUILTIN_PCMPISTRC128,
21180 IX86_BUILTIN_PCMPISTRO128,
21181 IX86_BUILTIN_PCMPISTRS128,
21182 IX86_BUILTIN_PCMPISTRZ128,
21184 IX86_BUILTIN_PCMPGTQ,
21186 /* AES instructions */
21187 IX86_BUILTIN_AESENC128,
21188 IX86_BUILTIN_AESENCLAST128,
21189 IX86_BUILTIN_AESDEC128,
21190 IX86_BUILTIN_AESDECLAST128,
21191 IX86_BUILTIN_AESIMC128,
21192 IX86_BUILTIN_AESKEYGENASSIST128,
21194 /* PCLMUL instruction */
21195 IX86_BUILTIN_PCLMULQDQ128,
21197 /* AVX */
21198 IX86_BUILTIN_ADDPD256,
21199 IX86_BUILTIN_ADDPS256,
21200 IX86_BUILTIN_ADDSUBPD256,
21201 IX86_BUILTIN_ADDSUBPS256,
21202 IX86_BUILTIN_ANDPD256,
21203 IX86_BUILTIN_ANDPS256,
21204 IX86_BUILTIN_ANDNPD256,
21205 IX86_BUILTIN_ANDNPS256,
21206 IX86_BUILTIN_BLENDPD256,
21207 IX86_BUILTIN_BLENDPS256,
21208 IX86_BUILTIN_BLENDVPD256,
21209 IX86_BUILTIN_BLENDVPS256,
21210 IX86_BUILTIN_DIVPD256,
21211 IX86_BUILTIN_DIVPS256,
21212 IX86_BUILTIN_DPPS256,
21213 IX86_BUILTIN_HADDPD256,
21214 IX86_BUILTIN_HADDPS256,
21215 IX86_BUILTIN_HSUBPD256,
21216 IX86_BUILTIN_HSUBPS256,
21217 IX86_BUILTIN_MAXPD256,
21218 IX86_BUILTIN_MAXPS256,
21219 IX86_BUILTIN_MINPD256,
21220 IX86_BUILTIN_MINPS256,
21221 IX86_BUILTIN_MULPD256,
21222 IX86_BUILTIN_MULPS256,
21223 IX86_BUILTIN_ORPD256,
21224 IX86_BUILTIN_ORPS256,
21225 IX86_BUILTIN_SHUFPD256,
21226 IX86_BUILTIN_SHUFPS256,
21227 IX86_BUILTIN_SUBPD256,
21228 IX86_BUILTIN_SUBPS256,
21229 IX86_BUILTIN_XORPD256,
21230 IX86_BUILTIN_XORPS256,
21231 IX86_BUILTIN_CMPSD,
21232 IX86_BUILTIN_CMPSS,
21233 IX86_BUILTIN_CMPPD,
21234 IX86_BUILTIN_CMPPS,
21235 IX86_BUILTIN_CMPPD256,
21236 IX86_BUILTIN_CMPPS256,
21237 IX86_BUILTIN_CVTDQ2PD256,
21238 IX86_BUILTIN_CVTDQ2PS256,
21239 IX86_BUILTIN_CVTPD2PS256,
21240 IX86_BUILTIN_CVTPS2DQ256,
21241 IX86_BUILTIN_CVTPS2PD256,
21242 IX86_BUILTIN_CVTTPD2DQ256,
21243 IX86_BUILTIN_CVTPD2DQ256,
21244 IX86_BUILTIN_CVTTPS2DQ256,
21245 IX86_BUILTIN_EXTRACTF128PD256,
21246 IX86_BUILTIN_EXTRACTF128PS256,
21247 IX86_BUILTIN_EXTRACTF128SI256,
21248 IX86_BUILTIN_VZEROALL,
21249 IX86_BUILTIN_VZEROUPPER,
21250 IX86_BUILTIN_VPERMILVARPD,
21251 IX86_BUILTIN_VPERMILVARPS,
21252 IX86_BUILTIN_VPERMILVARPD256,
21253 IX86_BUILTIN_VPERMILVARPS256,
21254 IX86_BUILTIN_VPERMILPD,
21255 IX86_BUILTIN_VPERMILPS,
21256 IX86_BUILTIN_VPERMILPD256,
21257 IX86_BUILTIN_VPERMILPS256,
21258 IX86_BUILTIN_VPERMIL2PD,
21259 IX86_BUILTIN_VPERMIL2PS,
21260 IX86_BUILTIN_VPERMIL2PD256,
21261 IX86_BUILTIN_VPERMIL2PS256,
21262 IX86_BUILTIN_VPERM2F128PD256,
21263 IX86_BUILTIN_VPERM2F128PS256,
21264 IX86_BUILTIN_VPERM2F128SI256,
21265 IX86_BUILTIN_VBROADCASTSS,
21266 IX86_BUILTIN_VBROADCASTSD256,
21267 IX86_BUILTIN_VBROADCASTSS256,
21268 IX86_BUILTIN_VBROADCASTPD256,
21269 IX86_BUILTIN_VBROADCASTPS256,
21270 IX86_BUILTIN_VINSERTF128PD256,
21271 IX86_BUILTIN_VINSERTF128PS256,
21272 IX86_BUILTIN_VINSERTF128SI256,
21273 IX86_BUILTIN_LOADUPD256,
21274 IX86_BUILTIN_LOADUPS256,
21275 IX86_BUILTIN_STOREUPD256,
21276 IX86_BUILTIN_STOREUPS256,
21277 IX86_BUILTIN_LDDQU256,
21278 IX86_BUILTIN_MOVNTDQ256,
21279 IX86_BUILTIN_MOVNTPD256,
21280 IX86_BUILTIN_MOVNTPS256,
21281 IX86_BUILTIN_LOADDQU256,
21282 IX86_BUILTIN_STOREDQU256,
21283 IX86_BUILTIN_MASKLOADPD,
21284 IX86_BUILTIN_MASKLOADPS,
21285 IX86_BUILTIN_MASKSTOREPD,
21286 IX86_BUILTIN_MASKSTOREPS,
21287 IX86_BUILTIN_MASKLOADPD256,
21288 IX86_BUILTIN_MASKLOADPS256,
21289 IX86_BUILTIN_MASKSTOREPD256,
21290 IX86_BUILTIN_MASKSTOREPS256,
21291 IX86_BUILTIN_MOVSHDUP256,
21292 IX86_BUILTIN_MOVSLDUP256,
21293 IX86_BUILTIN_MOVDDUP256,
21295 IX86_BUILTIN_SQRTPD256,
21296 IX86_BUILTIN_SQRTPS256,
21297 IX86_BUILTIN_SQRTPS_NR256,
21298 IX86_BUILTIN_RSQRTPS256,
21299 IX86_BUILTIN_RSQRTPS_NR256,
21301 IX86_BUILTIN_RCPPS256,
21303 IX86_BUILTIN_ROUNDPD256,
21304 IX86_BUILTIN_ROUNDPS256,
21306 IX86_BUILTIN_UNPCKHPD256,
21307 IX86_BUILTIN_UNPCKLPD256,
21308 IX86_BUILTIN_UNPCKHPS256,
21309 IX86_BUILTIN_UNPCKLPS256,
21311 IX86_BUILTIN_SI256_SI,
21312 IX86_BUILTIN_PS256_PS,
21313 IX86_BUILTIN_PD256_PD,
21314 IX86_BUILTIN_SI_SI256,
21315 IX86_BUILTIN_PS_PS256,
21316 IX86_BUILTIN_PD_PD256,
21318 IX86_BUILTIN_VTESTZPD,
21319 IX86_BUILTIN_VTESTCPD,
21320 IX86_BUILTIN_VTESTNZCPD,
21321 IX86_BUILTIN_VTESTZPS,
21322 IX86_BUILTIN_VTESTCPS,
21323 IX86_BUILTIN_VTESTNZCPS,
21324 IX86_BUILTIN_VTESTZPD256,
21325 IX86_BUILTIN_VTESTCPD256,
21326 IX86_BUILTIN_VTESTNZCPD256,
21327 IX86_BUILTIN_VTESTZPS256,
21328 IX86_BUILTIN_VTESTCPS256,
21329 IX86_BUILTIN_VTESTNZCPS256,
21330 IX86_BUILTIN_PTESTZ256,
21331 IX86_BUILTIN_PTESTC256,
21332 IX86_BUILTIN_PTESTNZC256,
21334 IX86_BUILTIN_MOVMSKPD256,
21335 IX86_BUILTIN_MOVMSKPS256,
21337 /* TFmode support builtins. */
21338 IX86_BUILTIN_INFQ,
21339 IX86_BUILTIN_HUGE_VALQ,
21340 IX86_BUILTIN_FABSQ,
21341 IX86_BUILTIN_COPYSIGNQ,
21343 /* Vectorizer support builtins. */
21344 IX86_BUILTIN_CPYSGNPS,
21345 IX86_BUILTIN_CPYSGNPD,
21347 IX86_BUILTIN_CVTUDQ2PS,
21349 IX86_BUILTIN_VEC_PERM_V2DF,
21350 IX86_BUILTIN_VEC_PERM_V4SF,
21351 IX86_BUILTIN_VEC_PERM_V2DI,
21352 IX86_BUILTIN_VEC_PERM_V4SI,
21353 IX86_BUILTIN_VEC_PERM_V8HI,
21354 IX86_BUILTIN_VEC_PERM_V16QI,
21355 IX86_BUILTIN_VEC_PERM_V2DI_U,
21356 IX86_BUILTIN_VEC_PERM_V4SI_U,
21357 IX86_BUILTIN_VEC_PERM_V8HI_U,
21358 IX86_BUILTIN_VEC_PERM_V16QI_U,
21359 IX86_BUILTIN_VEC_PERM_V4DF,
21360 IX86_BUILTIN_VEC_PERM_V8SF,
21362 /* FMA4 and XOP instructions. */
21363 IX86_BUILTIN_VFMADDSS,
21364 IX86_BUILTIN_VFMADDSD,
21365 IX86_BUILTIN_VFMADDPS,
21366 IX86_BUILTIN_VFMADDPD,
21367 IX86_BUILTIN_VFMSUBSS,
21368 IX86_BUILTIN_VFMSUBSD,
21369 IX86_BUILTIN_VFMSUBPS,
21370 IX86_BUILTIN_VFMSUBPD,
21371 IX86_BUILTIN_VFMADDSUBPS,
21372 IX86_BUILTIN_VFMADDSUBPD,
21373 IX86_BUILTIN_VFMSUBADDPS,
21374 IX86_BUILTIN_VFMSUBADDPD,
21375 IX86_BUILTIN_VFNMADDSS,
21376 IX86_BUILTIN_VFNMADDSD,
21377 IX86_BUILTIN_VFNMADDPS,
21378 IX86_BUILTIN_VFNMADDPD,
21379 IX86_BUILTIN_VFNMSUBSS,
21380 IX86_BUILTIN_VFNMSUBSD,
21381 IX86_BUILTIN_VFNMSUBPS,
21382 IX86_BUILTIN_VFNMSUBPD,
21383 IX86_BUILTIN_VFMADDPS256,
21384 IX86_BUILTIN_VFMADDPD256,
21385 IX86_BUILTIN_VFMSUBPS256,
21386 IX86_BUILTIN_VFMSUBPD256,
21387 IX86_BUILTIN_VFMADDSUBPS256,
21388 IX86_BUILTIN_VFMADDSUBPD256,
21389 IX86_BUILTIN_VFMSUBADDPS256,
21390 IX86_BUILTIN_VFMSUBADDPD256,
21391 IX86_BUILTIN_VFNMADDPS256,
21392 IX86_BUILTIN_VFNMADDPD256,
21393 IX86_BUILTIN_VFNMSUBPS256,
21394 IX86_BUILTIN_VFNMSUBPD256,
21396 IX86_BUILTIN_VPCMOV,
21397 IX86_BUILTIN_VPCMOV_V2DI,
21398 IX86_BUILTIN_VPCMOV_V4SI,
21399 IX86_BUILTIN_VPCMOV_V8HI,
21400 IX86_BUILTIN_VPCMOV_V16QI,
21401 IX86_BUILTIN_VPCMOV_V4SF,
21402 IX86_BUILTIN_VPCMOV_V2DF,
21403 IX86_BUILTIN_VPCMOV256,
21404 IX86_BUILTIN_VPCMOV_V4DI256,
21405 IX86_BUILTIN_VPCMOV_V8SI256,
21406 IX86_BUILTIN_VPCMOV_V16HI256,
21407 IX86_BUILTIN_VPCMOV_V32QI256,
21408 IX86_BUILTIN_VPCMOV_V8SF256,
21409 IX86_BUILTIN_VPCMOV_V4DF256,
21411 IX86_BUILTIN_VPPERM,
21413 IX86_BUILTIN_VPMACSSWW,
21414 IX86_BUILTIN_VPMACSWW,
21415 IX86_BUILTIN_VPMACSSWD,
21416 IX86_BUILTIN_VPMACSWD,
21417 IX86_BUILTIN_VPMACSSDD,
21418 IX86_BUILTIN_VPMACSDD,
21419 IX86_BUILTIN_VPMACSSDQL,
21420 IX86_BUILTIN_VPMACSSDQH,
21421 IX86_BUILTIN_VPMACSDQL,
21422 IX86_BUILTIN_VPMACSDQH,
21423 IX86_BUILTIN_VPMADCSSWD,
21424 IX86_BUILTIN_VPMADCSWD,
21426 IX86_BUILTIN_VPHADDBW,
21427 IX86_BUILTIN_VPHADDBD,
21428 IX86_BUILTIN_VPHADDBQ,
21429 IX86_BUILTIN_VPHADDWD,
21430 IX86_BUILTIN_VPHADDWQ,
21431 IX86_BUILTIN_VPHADDDQ,
21432 IX86_BUILTIN_VPHADDUBW,
21433 IX86_BUILTIN_VPHADDUBD,
21434 IX86_BUILTIN_VPHADDUBQ,
21435 IX86_BUILTIN_VPHADDUWD,
21436 IX86_BUILTIN_VPHADDUWQ,
21437 IX86_BUILTIN_VPHADDUDQ,
21438 IX86_BUILTIN_VPHSUBBW,
21439 IX86_BUILTIN_VPHSUBWD,
21440 IX86_BUILTIN_VPHSUBDQ,
21442 IX86_BUILTIN_VPROTB,
21443 IX86_BUILTIN_VPROTW,
21444 IX86_BUILTIN_VPROTD,
21445 IX86_BUILTIN_VPROTQ,
21446 IX86_BUILTIN_VPROTB_IMM,
21447 IX86_BUILTIN_VPROTW_IMM,
21448 IX86_BUILTIN_VPROTD_IMM,
21449 IX86_BUILTIN_VPROTQ_IMM,
21451 IX86_BUILTIN_VPSHLB,
21452 IX86_BUILTIN_VPSHLW,
21453 IX86_BUILTIN_VPSHLD,
21454 IX86_BUILTIN_VPSHLQ,
21455 IX86_BUILTIN_VPSHAB,
21456 IX86_BUILTIN_VPSHAW,
21457 IX86_BUILTIN_VPSHAD,
21458 IX86_BUILTIN_VPSHAQ,
21460 IX86_BUILTIN_VFRCZSS,
21461 IX86_BUILTIN_VFRCZSD,
21462 IX86_BUILTIN_VFRCZPS,
21463 IX86_BUILTIN_VFRCZPD,
21464 IX86_BUILTIN_VFRCZPS256,
21465 IX86_BUILTIN_VFRCZPD256,
21467 IX86_BUILTIN_VPCOMEQUB,
21468 IX86_BUILTIN_VPCOMNEUB,
21469 IX86_BUILTIN_VPCOMLTUB,
21470 IX86_BUILTIN_VPCOMLEUB,
21471 IX86_BUILTIN_VPCOMGTUB,
21472 IX86_BUILTIN_VPCOMGEUB,
21473 IX86_BUILTIN_VPCOMFALSEUB,
21474 IX86_BUILTIN_VPCOMTRUEUB,
21476 IX86_BUILTIN_VPCOMEQUW,
21477 IX86_BUILTIN_VPCOMNEUW,
21478 IX86_BUILTIN_VPCOMLTUW,
21479 IX86_BUILTIN_VPCOMLEUW,
21480 IX86_BUILTIN_VPCOMGTUW,
21481 IX86_BUILTIN_VPCOMGEUW,
21482 IX86_BUILTIN_VPCOMFALSEUW,
21483 IX86_BUILTIN_VPCOMTRUEUW,
21485 IX86_BUILTIN_VPCOMEQUD,
21486 IX86_BUILTIN_VPCOMNEUD,
21487 IX86_BUILTIN_VPCOMLTUD,
21488 IX86_BUILTIN_VPCOMLEUD,
21489 IX86_BUILTIN_VPCOMGTUD,
21490 IX86_BUILTIN_VPCOMGEUD,
21491 IX86_BUILTIN_VPCOMFALSEUD,
21492 IX86_BUILTIN_VPCOMTRUEUD,
21494 IX86_BUILTIN_VPCOMEQUQ,
21495 IX86_BUILTIN_VPCOMNEUQ,
21496 IX86_BUILTIN_VPCOMLTUQ,
21497 IX86_BUILTIN_VPCOMLEUQ,
21498 IX86_BUILTIN_VPCOMGTUQ,
21499 IX86_BUILTIN_VPCOMGEUQ,
21500 IX86_BUILTIN_VPCOMFALSEUQ,
21501 IX86_BUILTIN_VPCOMTRUEUQ,
21503 IX86_BUILTIN_VPCOMEQB,
21504 IX86_BUILTIN_VPCOMNEB,
21505 IX86_BUILTIN_VPCOMLTB,
21506 IX86_BUILTIN_VPCOMLEB,
21507 IX86_BUILTIN_VPCOMGTB,
21508 IX86_BUILTIN_VPCOMGEB,
21509 IX86_BUILTIN_VPCOMFALSEB,
21510 IX86_BUILTIN_VPCOMTRUEB,
21512 IX86_BUILTIN_VPCOMEQW,
21513 IX86_BUILTIN_VPCOMNEW,
21514 IX86_BUILTIN_VPCOMLTW,
21515 IX86_BUILTIN_VPCOMLEW,
21516 IX86_BUILTIN_VPCOMGTW,
21517 IX86_BUILTIN_VPCOMGEW,
21518 IX86_BUILTIN_VPCOMFALSEW,
21519 IX86_BUILTIN_VPCOMTRUEW,
21521 IX86_BUILTIN_VPCOMEQD,
21522 IX86_BUILTIN_VPCOMNED,
21523 IX86_BUILTIN_VPCOMLTD,
21524 IX86_BUILTIN_VPCOMLED,
21525 IX86_BUILTIN_VPCOMGTD,
21526 IX86_BUILTIN_VPCOMGED,
21527 IX86_BUILTIN_VPCOMFALSED,
21528 IX86_BUILTIN_VPCOMTRUED,
21530 IX86_BUILTIN_VPCOMEQQ,
21531 IX86_BUILTIN_VPCOMNEQ,
21532 IX86_BUILTIN_VPCOMLTQ,
21533 IX86_BUILTIN_VPCOMLEQ,
21534 IX86_BUILTIN_VPCOMGTQ,
21535 IX86_BUILTIN_VPCOMGEQ,
21536 IX86_BUILTIN_VPCOMFALSEQ,
21537 IX86_BUILTIN_VPCOMTRUEQ,
21539 /* LWP instructions. */
21540 IX86_BUILTIN_LLWPCB,
21541 IX86_BUILTIN_SLWPCB,
21542 IX86_BUILTIN_LWPVAL32,
21543 IX86_BUILTIN_LWPVAL64,
21544 IX86_BUILTIN_LWPINS32,
21545 IX86_BUILTIN_LWPINS64,
21547 IX86_BUILTIN_CLZS,
21549 IX86_BUILTIN_MAX
21550 };
21552 /* Table for the ix86 builtin decls. */
21555 /* Table of all of the builtin functions that are possible with different ISA's
21556 but are waiting to be built until a function is declared to use that
21557 ISA. */
21564 };
21569 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21570 of which isa_flags to use in the ix86_builtins_isa array. Stores the
21571 function decl in the ix86_builtins array. Returns the function decl or
21572 NULL_TREE, if the builtin was not added.
21574 If the front end has a special hook for builtin functions, delay adding
21575 builtin functions that aren't in the current ISA until the ISA is changed
21576 with function specific optimization. Doing so, can save about 300K for the
21577 default compiler. When the builtin is expanded, check at that time whether
21578 it is valid.
21580 If the front end doesn't have a special hook, record all builtins, even if
21581 it isn't an instruction set in the current ISA in case the user uses
21582 function specific options for a different ISA, so that we don't get scope
21583 errors if a builtin is added in the middle of a function scope. */
21588 {
21592 {
21600 {
21606 }
21607 else
21608 {
21614 }
21615 }
21618 }
21620 /* Like def_builtin, but also marks the function decl "const". */
21625 {
21629 else
21633 }
21635 /* Add any new builtin functions for a given ISA that may not have been
21636 declared. This saves a bit of space compared to adding all of the
21637 declarations to the tree, even if we didn't use them. */
21639 static void
21641 {
21645 {
21648 {
21651 /* Don't define the builtin again. */
21657 NULL_TREE);
21662 }
21663 }
21664 }
21666 /* Bits for builtin_description.flag. */
21668 /* Set when we don't support the comparison natively, and should
21669 swap_comparison in order to support it. */
21670 #define BUILTIN_DESC_SWAP_OPERANDS 1
21672 struct builtin_description
21673 {
21680 };
21683 {
21684 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21685 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21686 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21687 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21688 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21689 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21690 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21691 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21692 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21693 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21694 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21695 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21698 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21699 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21700 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21701 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21702 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21703 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21704 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21705 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21707 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21708 };
21711 {
21712 /* SSE4.2 */
21713 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21714 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21715 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21716 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21717 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21718 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21719 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21720 };
21723 {
21724 /* SSE4.2 */
21725 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21726 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21727 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21728 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21729 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21730 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21731 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21732 };
21734 /* Special builtins with variable number of arguments. */
21736 {
21737 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21738 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21740 /* MMX */
21741 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21743 /* 3DNow! */
21744 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21746 /* SSE */
21747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21756 /* SSE or 3DNow!A */
21757 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21758 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
21760 /* SSE2 */
21761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21762 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21768 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21769 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21771 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21774 /* SSE3 */
21775 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21777 /* SSE4.1 */
21778 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21780 /* SSE4A */
21781 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21782 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21784 /* AVX */
21785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21788 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21789 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21790 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21815 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
21816 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
21817 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
21818 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
21819 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
21820 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
21822 };
21824 /* Builtins with variable number of arguments. */
21826 {
21827 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21828 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21829 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21830 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21831 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21832 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21833 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21835 /* MMX */
21836 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21837 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21838 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21839 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21840 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21841 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21843 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21844 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21845 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21846 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21847 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21848 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21849 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21850 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21852 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21853 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21855 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21856 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21857 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21858 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21860 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21861 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21862 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21863 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21864 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21865 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21867 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21868 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21869 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21870 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21871 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21872 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21874 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21875 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21876 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21878 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21880 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21881 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21882 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21883 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21884 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21885 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21887 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21888 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21889 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21890 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21891 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21892 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21894 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21895 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21896 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21897 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21899 /* 3DNow! */
21900 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21901 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21902 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21903 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21905 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21906 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21907 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21908 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21909 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21910 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21911 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21912 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21913 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21914 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21915 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21916 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21917 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21918 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21919 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21921 /* 3DNow!A */
21922 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21923 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21924 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21925 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21926 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21927 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21929 /* SSE */
21930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21932 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21934 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21938 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21941 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21945 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21946 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21947 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21949 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21950 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21955 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21957 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21958 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21959 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21961 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21962 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21963 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21964 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21965 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21966 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21967 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21968 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21969 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21970 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21971 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21972 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21973 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21974 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21975 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21977 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21978 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21980 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21982 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21984 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21985 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21987 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21989 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21990 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21992 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21993 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21995 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21996 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21997 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21999 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
22001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
22002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
22003 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
22005 /* SSE MMX or 3Dnow!A */
22006 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22007 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22008 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22010 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22011 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22012 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22013 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22015 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
22016 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
22018 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
22020 /* SSE2 */
22021 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22023 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
22024 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
22025 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
22026 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
22027 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
22028 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22029 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
22030 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
22031 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
22032 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
22033 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
22034 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
22036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
22037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
22038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
22039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
22040 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
22041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
22043 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
22044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
22045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
22046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
22047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
22049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
22051 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
22052 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
22053 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
22054 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
22056 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
22057 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
22058 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
22060 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22061 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22062 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22063 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22067 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
22070 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
22071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
22072 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
22074 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
22076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
22077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
22078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22080 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
22082 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
22083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
22084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
22086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
22087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
22088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22091 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22095 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22097 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22098 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22100 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22103 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22104 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22106 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
22108 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22109 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22110 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22111 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22112 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22113 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22114 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22115 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22126 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22127 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
22129 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22131 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22132 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22139 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22140 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22144 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22145 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22146 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22149 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22150 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22151 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22152 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22153 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22154 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22155 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22156 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
22159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
22162 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
22165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
22166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22168 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
22170 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
22171 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
22172 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
22173 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
22175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
22176 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22177 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22178 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22179 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22180 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22181 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
22184 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22185 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22186 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22187 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22188 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22189 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22191 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22192 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22193 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22194 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
22197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
22202 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
22203 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
22205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22207 /* SSE2 MMX */
22208 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22209 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22211 /* SSE3 */
22212 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
22213 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22215 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22216 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22217 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22218 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22219 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22220 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22222 /* SSSE3 */
22223 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
22224 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
22225 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22226 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
22227 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
22228 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
22230 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22231 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22232 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22233 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22234 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22235 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22236 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22237 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22238 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22239 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22240 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22241 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22242 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
22243 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
22244 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22245 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22246 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22247 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22248 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22249 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22250 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22251 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22252 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22253 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22255 /* SSSE3. */
22256 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
22257 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
22259 /* SSE4.1 */
22260 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22261 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22262 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
22263 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
22264 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22265 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22266 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22267 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
22268 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22269 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
22271 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22272 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22273 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22274 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22275 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22276 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22277 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22278 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22279 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22280 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22281 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22282 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22283 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22285 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22286 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22287 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22288 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22289 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22290 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22291 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22292 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22293 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22294 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22295 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22296 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22298 /* SSE4.1 */
22299 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22300 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22301 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22302 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22304 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22305 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22306 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22308 /* SSE4.2 */
22309 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22310 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22311 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22312 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22313 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22315 /* SSE4A */
22316 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22317 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22318 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22319 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22321 /* AES */
22322 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22323 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22325 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22326 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22327 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22328 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22330 /* PCLMUL */
22331 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22333 /* AVX */
22334 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22335 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22336 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22337 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22338 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22339 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22340 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22341 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22342 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22343 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22344 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22345 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22346 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22347 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22348 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22349 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22350 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22351 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22352 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22353 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22354 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22355 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22356 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22357 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22358 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22359 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22361 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22362 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22363 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22364 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22368 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22369 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22372 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22373 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22374 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22375 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22376 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22377 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22378 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22379 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22380 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22381 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22382 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22383 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22384 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22385 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22386 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22387 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22388 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22389 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22390 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22395 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22397 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22398 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22399 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22401 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22403 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22405 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22406 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22407 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22409 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22411 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22413 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22430 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22433 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22434 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22435 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22439 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22447 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
22448 };
22450 /* FMA4 and XOP. */
22451 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
22452 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
22453 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
22454 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
22455 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
22456 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
22457 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
22458 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
22459 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
22460 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
22461 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
22462 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
22463 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
22464 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
22465 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
22466 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
22467 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
22468 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
22469 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
22470 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
22471 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
22472 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
22473 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
22474 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
22475 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
22476 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
22477 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
22478 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
22479 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
22480 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
22481 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
22482 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
22483 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
22484 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
22485 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
22486 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
22487 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
22488 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
22489 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
22490 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
22491 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
22492 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
22493 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
22494 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
22495 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
22496 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
22497 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
22498 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
22499 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
22500 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
22501 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
22502 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
22505 {
22506 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22507 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22508 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22509 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22510 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22511 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22512 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22513 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22515 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22516 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22517 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22518 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22519 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22520 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22521 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22522 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22524 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22525 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22526 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22527 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22529 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22530 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22531 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22532 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22534 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22535 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22536 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22537 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22539 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22540 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22541 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22542 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
22555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
22556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
22557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
22597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
22599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22617 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22621 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22629 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22633 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22636 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22637 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22639 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22641 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22642 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22644 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22645 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22649 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22651 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22652 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22656 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22657 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22658 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22659 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22660 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22661 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22663 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22664 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22665 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22666 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22667 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22668 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22669 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22671 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22672 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22673 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22674 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22675 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22676 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22677 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22679 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22680 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22681 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22682 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22683 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22684 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22685 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22686 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22688 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22689 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22690 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22691 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22692 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22693 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22694 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22695 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22697 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
22698 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
22699 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
22700 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
22702 };
22704 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22705 in the current target ISA to allow the user to compile particular modules
22706 with different target specific options that differ from the command line
22707 options. */
22708 static void
22710 {
22715 /* Add all special builtins with variable number of operands. */
22719 {
22725 }
22727 /* Add all builtins with variable number of operands. */
22731 {
22737 }
22739 /* pcmpestr[im] insns. */
22743 {
22746 else
22749 }
22751 /* pcmpistr[im] insns. */
22755 {
22758 else
22761 }
22763 /* comi/ucomi insns. */
22765 {
22768 else
22771 }
22773 /* SSE */
22779 /* SSE or 3DNow!A */
22782 IX86_BUILTIN_MASKMOVQ);
22784 /* SSE2 */
22793 /* SSE3. */
22799 /* AES */
22813 /* PCLMUL */
22817 /* MMX access to the vec_init patterns. */
22822 V4HI_FTYPE_HI_HI_HI_HI,
22823 IX86_BUILTIN_VEC_INIT_V4HI);
22826 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
22827 IX86_BUILTIN_VEC_INIT_V8QI);
22829 /* Access to the vec_extract patterns. */
22851 /* Access to the vec_set patterns. */
22872 /* Add FMA4 multi-arg argument instructions */
22874 {
22880 }
22881 }
22883 /* Internal method for ix86_init_builtins. */
22885 static void
22887 {
22899 sysv_va_ref =
22902 fnvoid_va_end_ms =
22904 fnvoid_va_start_ms =
22906 fnvoid_va_end_sysv =
22908 fnvoid_va_start_sysv =
22910 NULL_TREE);
22911 fnvoid_va_copy_ms =
22913 NULL_TREE);
22914 fnvoid_va_copy_sysv =
22930 }
22932 static void
22934 {
22937 /* The __float80 type. */
22940 {
22941 /* The __float80 type. */
22946 }
22949 /* The __float128 type. */
22955 /* This macro is built by i386-builtin-types.awk. */
22956 DEFINE_BUILTIN_PRIMITIVE_TYPES;
22957 }
22959 static void
22961 {
22962 tree t;
22966 /* TFmode support builtins. */
22972 /* We will expand them to normal call if SSE2 isn't available since
22973 they are used by libgcc. */
22990 }
22992 /* Return the ix86 builtin for CODE. */
22994 static tree
22996 {
23001 }
23003 /* Errors in the source file can cause expand_expr to return const0_rtx
23004 where we expect a vector. To avoid crashing, use one of the vector
23005 clear instructions. */
23006 static rtx
23008 {
23012 }
23014 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23016 static rtx
23018 {
23019 rtx pat;
23039 {
23043 }
23057 }
23059 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23061 static rtx
23065 {
23066 rtx pat;
23074 rtx op;
23081 {
23161 }
23171 {
23178 {
23180 {
23183 }
23184 }
23185 else
23186 {
23190 /* If we aren't optimizing, only allow one memory operand to be
23191 generated. */
23193 num_memory++;
23201 }
23205 }
23208 {
23219 else
23220 {
23226 }
23239 }
23246 }
23248 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23249 insns with vec_merge. */
23251 static rtx
23253 rtx target)
23254 {
23255 rtx pat;
23282 }
23284 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23286 static rtx
23289 {
23290 rtx pat;
23295 rtx op2;
23306 /* Swap operands if we have a comparison that isn't available in
23307 hardware. */
23309 {
23314 }
23334 }
23336 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23338 static rtx
23340 rtx target)
23341 {
23342 rtx pat;
23356 /* Swap operands if we have a comparison that isn't available in
23357 hardware. */
23359 {
23363 }
23384 const0_rtx)));
23387 }
23389 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23391 static rtx
23393 rtx target)
23394 {
23395 rtx pat;
23428 const0_rtx)));
23431 }
23433 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23435 static rtx
23438 {
23439 rtx pat;
23477 {
23480 }
23483 {
23492 }
23494 {
23503 }
23504 else
23505 {
23512 }
23520 {
23525 emit_insn
23529 FLAGS_REG),
23530 const0_rtx)));
23532 }
23533 else
23535 }
23538 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23540 static rtx
23543 {
23544 rtx pat;
23572 {
23575 }
23578 {
23587 }
23589 {
23598 }
23599 else
23600 {
23607 }
23615 {
23620 emit_insn
23624 FLAGS_REG),
23625 const0_rtx)));
23627 }
23628 else
23630 }
23632 /* Subroutine of ix86_expand_builtin to take care of insns with
23633 variable number of operands. */
23635 static rtx
23638 {
23643 struct
23644 {
23645 rtx op;
23657 {
23868 }
23873 {
23876 }
23879 {
23886 }
23887 else
23888 {
23891 }
23894 {
23901 {
23902 /* SIMD shift insns take either an 8-bit immediate or
23903 register as count. But builtin functions take int as
23904 count. If count doesn't match, we put it in register. */
23906 {
23910 }
23911 }
23913 {
23916 {
23958 {
23961 {
23964 }
23970 }
23972 }
23973 }
23974 else
23975 {
23979 /* If we aren't optimizing, only allow one memory operand to
23980 be generated. */
23982 num_memory++;
23985 {
23988 }
23989 else
23990 {
23993 }
23994 }
23998 }
24001 {
24018 }
24025 }
24027 /* Subroutine of ix86_expand_builtin to take care of special insns
24028 with variable number of operands. */
24030 static rtx
24033 {
24034 tree arg;
24037 struct
24038 {
24039 rtx op;
24049 {
24086 /* Reserve memory operand for target. */
24109 /* Reserve memory operand for target. */
24123 }
24128 {
24134 }
24135 else
24136 {
24143 }
24146 {
24155 {
24157 {
24163 else
24166 }
24167 }
24168 else
24169 {
24171 {
24172 /* This must be the memory operand. */
24176 }
24177 else
24178 {
24179 /* This must be register. */
24186 }
24187 }
24191 }
24194 {
24209 }
24215 }
24217 /* Return the integer constant in ARG. Constrain it to be in the range
24218 of the subparts of VEC_TYPE; issue an error if not. */
24220 static int
24222 {
24227 {
24230 }
24233 }
24235 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24236 ix86_expand_vector_init. We DO have language-level syntax for this, in
24237 the form of (type){ init-list }. Except that since we can't place emms
24238 instructions from inside the compiler, we can't allow the use of MMX
24239 registers unless the user explicitly asks for it. So we do *not* define
24240 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24241 we have builtins invoked by mmintrin.h that gives us license to emit
24242 these sorts of instructions. */
24244 static rtx
24246 {
24256 {
24259 }
24266 }
24268 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24269 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24270 had a language-level syntax for referencing vector elements. */
24272 static rtx
24274 {
24278 rtx op0;
24298 }
24300 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24301 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24302 a language-level syntax for referencing vector elements. */
24304 static rtx
24306 {
24330 /* OP0 is the source of these builtin functions and shouldn't be
24331 modified. Create a copy, use it and return it as target. */
24337 }
24339 /* Expand an expression EXP that calls a built-in function,
24340 with result going to TARGET if that's convenient
24341 (and in mode MODE if that's convenient).
24342 SUBTARGET may be used as the target for computing one of EXP's operands.
24343 IGNORE is nonzero if the value is to be ignored. */
24345 static rtx
24349 {
24359 /* Determine whether the builtin function is available under the current ISA.
24360 Originally the builtin was not created if it wasn't applicable to the
24361 current ISA based on the command line switches. With function specific
24362 options, we need to check in the context of the function making the call
24363 whether it is supported. */
24366 {
24372 else
24373 {
24377 }
24379 }
24382 {
24386 ? CODE_FOR_mmx_maskmovq
24388 /* Note the arg order is different from the operand order. */
24503 {
24504 REAL_VALUE_TYPE inf;
24505 rtx tmp;
24517 }
24538 }
24551 {
24555 /* Emit a normal call if SSE2 isn't available. */
24559 }
24584 }
24586 /* Returns a function decl for a vectorized version of the builtin function
24587 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24588 if it is not available. */
24590 static tree
24592 tree type_in)
24593 {
24609 {
24647 ;
24648 }
24650 /* Dispatch to a handler for a vectorization library. */
24653 type_in);
24656 }
24658 /* Handler for an SVML-style interface to
24659 a library with vectorized intrinsics. */
24661 static tree
24663 {
24671 /* The SVML is suitable for unsafe math only. */
24684 {
24731 }
24740 {
24743 }
24744 else
24747 /* Convert to uppercase. */
24753 arity++;
24757 else
24760 /* Build a function declaration for the vectorized function. */
24769 }
24771 /* Handler for an ACML-style interface to
24772 a library with vectorized intrinsics. */
24774 static tree
24776 {
24784 /* The ACML is 64bits only and suitable for unsafe math only as
24785 it does not correctly support parts of IEEE with the required
24786 precision such as denormals. */
24800 {
24830 }
24838 arity++;
24842 else
24845 /* Build a function declaration for the vectorized function. */
24854 }
24857 /* Returns a decl of a function that implements conversion of an integer vector
24858 into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
24859 are the types involved when converting according to CODE.
24860 Return NULL_TREE if it is not available. */
24862 static tree
24865 {
24870 {
24873 {
24876 {
24883 ? NULL_TREE
24887 }
24891 {
24894 ? NULL_TREE
24898 }
24902 }
24906 {
24909 {
24912 ? NULL_TREE
24916 ? NULL_TREE
24920 }
24925 {
24928 ? NULL_TREE
24932 }
24937 }
24941 }
24944 }
24946 /* Returns a code for a target-specific builtin that implements
24947 reciprocal of the function, or NULL_TREE if not available. */
24949 static tree
24952 {
24959 /* Machine dependent builtins. */
24961 {
24962 /* Vectorized version of sqrt to rsqrt conversion. */
24968 }
24969 else
24970 /* Normal builtins. */
24972 {
24973 /* Sqrt to rsqrt conversion. */
24979 }
24980 }
24981 \f
24982 /* Helper for avx_vpermilps256_operand et al. This is also used by
24983 the expansion functions to turn the parallel back into a mask.
24984 The return value is 0 for no match and the imm8+1 for a match. */
24986 int
24988 {
24996 /* Validate that all of the elements are constants, and not totally
24997 out of range. Copy the data into an integral array to make the
24998 subsequent checks easier. */
25000 {
25010 }
25013 {
25015 /* In the 256-bit DFmode case, we can only move elements within
25016 a 128-bit lane. */
25018 {
25022 }
25024 {
25028 }
25032 /* In the 256-bit SFmode case, we have full freedom of movement
25033 within the low 128-bit lane, but the high 128-bit lane must
25034 mirror the exact same pattern. */
25039 /* FALLTHRU */
25043 /* In the 128-bit case, we've full freedom in the placement of
25044 the elements from the source operand. */
25051 }
25053 /* Make sure success has a non-zero value by adding one. */
25055 }
25057 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
25058 the expansion functions to turn the parallel back into a mask.
25059 The return value is 0 for no match and the imm8+1 for a match. */
25061 int
25063 {
25071 /* Validate that all of the elements are constants, and not totally
25072 out of range. Copy the data into an integral array to make the
25073 subsequent checks easier. */
25075 {
25085 }
25087 /* Validate that the halves of the permute are halves. */
25095 /* Reconstruct the mask. */
25097 {
25103 }
25105 /* Make sure success has a non-zero value by adding one. */
25107 }
25108 \f
25110 /* Store OPERAND to the memory after reload is completed. This means
25111 that we can't easily use assign_stack_local. */
25112 rtx
25114 {
25115 rtx result;
25119 {
25122 stack_pointer_rtx,
25125 }
25127 {
25129 {
25133 /* FALLTHRU */
25139 stack_pointer_rtx)),
25140 operand));
25144 }
25146 }
25147 else
25148 {
25150 {
25152 {
25159 stack_pointer_rtx)),
25165 stack_pointer_rtx)),
25167 }
25170 /* Store HImodes as SImodes. */
25172 /* FALLTHRU */
25178 stack_pointer_rtx)),
25179 operand));
25183 }
25185 }
25187 }
25189 /* Free operand from the memory. */
25190 void
25192 {
25194 {
25199 else
25201 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25202 to pop or add instruction if registers are available. */
25206 }
25207 }
25209 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25210 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25211 same. */
25214 {
25217 };
25220 };
25223 }
25225 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25226 QImode must go into class Q_REGS.
25227 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25228 movdf to do mem-to-mem moves through integer regs. */
25229 enum reg_class
25231 {
25234 /* We're only allowed to return a subclass of CLASS. Many of the
25235 following checks fail for NO_REGS, so eliminate that early. */
25239 /* All classes can load zeros. */
25243 /* Force constants into memory if we are loading a (nonzero) constant into
25244 an MMX or SSE register. This is because there are no MMX/SSE instructions
25245 to load from a constant. */
25250 /* Prefer SSE regs only, if we can use them for math. */
25254 /* Floating-point constants need more complex checks. */
25256 {
25257 /* General regs can load everything. */
25261 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25262 zero above. We only want to wind up preferring 80387 registers if
25263 we plan on doing computation with them. */
25266 {
25267 /* Limit class to non-sse. */
25276 }
25279 }
25281 /* Generally when we see PLUS here, it's the function invariant
25282 (plus soft-fp const_int). Which can only be computed into general
25283 regs. */
25287 /* QImode constants are easy to load, but non-constant QImode data
25288 must go into Q_REGS. */
25290 {
25296 }
25299 }
25301 /* Discourage putting floating-point values in SSE registers unless
25302 SSE math is being used, and likewise for the 387 registers. */
25303 enum reg_class
25305 {
25308 /* Restrict the output reload class to the register bank that we are doing
25309 math on. If we would like not to return a subset of CLASS, reject this
25310 alternative: if reload cannot do this, it will still use its choice. */
25316 {
25321 else
25323 }
25326 }
25328 static enum reg_class
25332 {
25333 /* QImode spills from non-QI registers require
25334 intermediate register on 32bit targets. */
25339 {
25344 else
25350 /* Return Q_REGS if the operand is in memory. */
25353 }
25356 }
25358 /* If we are copying between general and FP registers, we need a memory
25359 location. The same is true for SSE and MMX registers.
25361 To optimize register_move_cost performance, allow inline variant.
25363 The macro can't work reliably when one of the CLASSES is class containing
25364 registers from multiple units (SSE, MMX, integer). We avoid this by never
25365 combining those units in single alternative in the machine description.
25366 Ensure that this constraint holds to avoid unexpected surprises.
25368 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25369 enforce these sanity checks. */
25374 {
25381 {
25384 }
25389 /* ??? This is a lie. We do have moves between mmx/general, and for
25390 mmx/sse2. But by saying we need secondary memory we discourage the
25391 register allocator from using the mmx registers unless needed. */
25396 {
25397 /* SSE1 doesn't have any direct moves from other classes. */
25401 /* If the target says that inter-unit moves are more expensive
25402 than moving through memory, then don't generate them. */
25406 /* Between SSE and general, we have moves no larger than word size. */
25409 }
25412 }
25414 int
25417 {
25419 }
25421 /* Return true if the registers in CLASS cannot represent the change from
25422 modes FROM to TO. */
25424 bool
25427 {
25431 /* x87 registers can't do subreg at all, as all values are reformatted
25432 to extended precision. */
25437 {
25438 /* Vector registers do not support QI or HImode loads. If we don't
25439 disallow a change to these modes, reload will assume it's ok to
25440 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25441 the vec_dupv4hi pattern. */
25445 /* Vector registers do not support subreg with nonzero offsets, which
25446 are otherwise valid for integer registers. Since we can't see
25447 whether we have a nonzero offset from here, prohibit all
25448 nonparadoxical subregs changing size. */
25451 }
25454 }
25456 /* Return the cost of moving data of mode M between a
25457 register and memory. A value of 2 is the default; this cost is
25458 relative to those in `REGISTER_MOVE_COST'.
25460 This function is used extensively by register_move_cost that is used to
25461 build tables at startup. Make it inline in this case.
25462 When IN is 2, return maximum of in and out move cost.
25464 If moving between registers and memory is more expensive than
25465 between two registers, you should define this macro to express the
25466 relative cost.
25468 Model also increased moving costs of QImode registers in non
25469 Q_REGS classes.
25470 */
25474 {
25477 {
25480 {
25492 }
25496 }
25498 {
25501 {
25513 }
25517 }
25519 {
25522 {
25531 }
25535 }
25537 {
25540 {
25546 else
25551 }
25552 else
25553 {
25558 else
25560 }
25567 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25574 else
25578 }
25579 }
25581 int
25583 {
25585 }
25588 /* Return the cost of moving data from a register in class CLASS1 to
25589 one in class CLASS2.
25591 It is not required that the cost always equal 2 when FROM is the same as TO;
25592 on some machines it is expensive to move between registers if they are not
25593 general registers. */
25595 int
25598 {
25599 /* In case we require secondary memory, compute cost of the store followed
25600 by load. In order to avoid bad register allocation choices, we need
25601 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25604 {
25610 /* In case of copying from general_purpose_register we may emit multiple
25611 stores followed by single load causing memory size mismatch stall.
25612 Count this as arbitrarily high cost of 20. */
25616 /* In the case of FP/MMX moves, the registers actually overlap, and we
25617 have to switch modes in order to treat them differently. */
25623 }
25625 /* Moves between SSE/MMX and integer unit are expensive. */
25629 /* ??? By keeping returned value relatively high, we limit the number
25630 of moves between integer and MMX/SSE registers for all targets.
25631 Additionally, high value prevents problem with x86_modes_tieable_p(),
25632 where integer modes in MMX/SSE registers are not tieable
25633 because of missing QImode and HImode moves to, from or between
25634 MMX/SSE registers. */
25644 }
25646 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25648 bool
25650 {
25651 /* Flags and only flags can only hold CCmode values. */
25661 {
25662 /* We implement the move patterns for all vector modes into and
25663 out of SSE registers, even when no operation instructions
25664 are available. OImode move is available only when AVX is
25665 enabled. */
25672 }
25674 {
25675 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25676 so if the register is available at all, then we can move data of
25677 the given mode into or out of it. */
25680 }
25683 {
25684 /* Take care for QImode values - they can be in non-QI regs,
25685 but then they do cause partial register stalls. */
25691 }
25692 /* We handle both integer and floats in the general purpose registers. */
25699 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25700 on to use that value in smaller contexts, this can easily force a
25701 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25702 supporting DImode, allow it. */
25707 }
25709 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25710 tieable integer mode. */
25712 static bool
25714 {
25716 {
25729 }
25730 }
25732 /* Return true if MODE1 is accessible in a register that can hold MODE2
25733 without copying. That is, all register classes that can hold MODE2
25734 can also hold MODE1. */
25736 bool
25738 {
25746 /* MODE2 being XFmode implies fp stack or general regs, which means we
25747 can tie any smaller floating point modes to it. Note that we do not
25748 tie this with TFmode. */
25752 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25753 that we can tie it with SFmode. */
25757 /* If MODE2 is only appropriate for an SSE register, then tie with
25758 any other mode acceptable to SSE registers. */
25764 /* If MODE2 is appropriate for an MMX register, then tie
25765 with any other mode acceptable to MMX registers. */
25772 }
25774 /* Compute a (partial) cost for rtx X. Return true if the complete
25775 cost has been computed, and false if subexpressions should be
25776 scanned. In either case, *TOTAL contains the cost result. */
25778 static bool
25780 {
25786 {
25796 && (!TARGET_64BIT
25801 else
25808 else
25810 {
25819 /* Start with (MEM (SYMBOL_REF)), since that's where
25820 it'll probably end up. Add a penalty for size. */
25825 }
25829 /* The zero extensions is often completely free on x86_64, so make
25830 it as cheap as possible. */
25836 else
25847 {
25850 {
25853 }
25856 {
25859 }
25860 }
25861 /* FALLTHRU */
25868 {
25870 {
25873 else
25875 }
25876 else
25877 {
25880 else
25882 }
25883 }
25884 else
25885 {
25888 else
25890 }
25895 {
25896 /* ??? SSE scalar cost should be used here. */
25899 }
25901 {
25904 }
25906 {
25907 /* ??? SSE vector cost should be used here. */
25910 }
25911 else
25912 {
25917 {
25920 nbits++;
25921 }
25922 else
25923 /* This is arbitrary. */
25926 /* Compute costs correctly for widening multiplication. */
25930 {
25937 {
25941 else
25943 }
25947 }
25954 }
25961 /* ??? SSE cost should be used here. */
25966 /* ??? SSE vector cost should be used here. */
25968 else
25975 {
25980 {
25983 {
25990 }
25991 }
25994 {
25997 {
26002 }
26003 }
26005 {
26011 }
26012 }
26013 /* FALLTHRU */
26017 {
26018 /* ??? SSE cost should be used here. */
26021 }
26023 {
26026 }
26028 {
26029 /* ??? SSE vector cost should be used here. */
26032 }
26033 /* FALLTHRU */
26039 {
26046 }
26047 /* FALLTHRU */
26051 {
26052 /* ??? SSE cost should be used here. */
26055 }
26057 {
26060 }
26062 {
26063 /* ??? SSE vector cost should be used here. */
26066 }
26067 /* FALLTHRU */
26072 else
26081 {
26082 /* This kind of construct is implemented using test[bwl].
26083 Treat it as if we had an AND. */
26088 }
26098 /* ??? SSE cost should be used here. */
26103 /* ??? SSE vector cost should be used here. */
26109 /* ??? SSE cost should be used here. */
26114 /* ??? SSE vector cost should be used here. */
26127 /* ??? Assume all of these vector manipulation patterns are
26128 recognizable. In which case they all pretty much have the
26129 same cost. */
26135 }
26136 }
26138 #if TARGET_MACHO
26142 /* Given a symbol name and its associated stub, write out the
26143 definition of the stub. */
26145 void
26147 {
26152 /* For 64-bit we shouldn't get here. */
26155 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26170 else
26177 {
26181 }
26182 else
26188 {
26191 }
26192 else
26201 }
26204 /* Order the registers for register allocator. */
26206 void
26208 {
26212 /* First allocate the local general purpose registers. */
26217 /* Global general purpose registers. */
26222 /* x87 registers come first in case we are doing FP math
26223 using them. */
26228 /* SSE registers. */
26234 /* x87 registers. */
26242 /* Initialize the rest of array as we do not allocate some registers
26243 at all. */
26246 }
26248 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26249 struct attribute_spec.handler. */
26250 static tree
26252 tree args ATTRIBUTE_UNUSED,
26254 {
26259 {
26261 name);
26264 }
26266 {
26268 name);
26271 }
26273 /* Can combine regparm with all attributes but fastcall. */
26275 {
26277 {
26279 }
26282 }
26284 {
26286 {
26288 }
26291 }
26294 }
26296 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26297 struct attribute_spec.handler. */
26298 static tree
26300 tree args ATTRIBUTE_UNUSED,
26302 {
26305 {
26308 }
26309 else
26314 {
26316 name);
26318 }
26324 {
26326 name);
26328 }
26331 }
26333 static tree
26335 tree args ATTRIBUTE_UNUSED,
26337 {
26339 {
26341 name);
26344 }
26347 {
26349 name);
26351 }
26353 #ifndef HAVE_AS_IX86_SWAP
26355 #endif
26358 }
26360 static bool
26362 {
26366 }
26368 /* Returns an expression indicating where the this parameter is
26369 located on entry to the FUNCTION. */
26371 static rtx
26373 {
26379 {
26384 else
26387 }
26392 {
26398 {
26403 }
26404 else
26405 {
26408 {
26413 }
26414 }
26416 }
26419 }
26421 /* Determine whether x86_output_mi_thunk can succeed. */
26423 static bool
26425 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26427 {
26428 /* 64-bit can handle anything. */
26432 /* For 32-bit, everything's fine if we have one free register. */
26436 /* Need a free register for vcall_offset. */
26440 /* Need a free register for GOT references. */
26444 /* Otherwise ok. */
26446 }
26448 /* Output the assembler code for a thunk function. THUNK_DECL is the
26449 declaration for the thunk function itself, FUNCTION is the decl for
26450 the target function. DELTA is an immediate constant offset to be
26451 added to THIS. If VCALL_OFFSET is nonzero, the word at
26452 *(*this + vcall_offset) should be added to THIS. */
26454 static void
26458 {
26463 /* Make sure unwind info is emitted for the thunk if needed. */
26466 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26467 pull it in now and let DELTA benefit. */
26471 {
26472 /* Put the this parameter into %eax. */
26476 }
26477 else
26480 /* Adjust the this parameter by a fixed constant. */
26482 {
26486 {
26488 {
26494 }
26497 else
26499 }
26502 else
26504 }
26506 /* Adjust the this parameter by a value stored in the vtable. */
26508 {
26511 else
26512 {
26520 }
26526 /* Adjust the this parameter. */
26529 {
26535 }
26538 }
26540 /* If necessary, drop THIS back to its stack slot. */
26542 {
26546 }
26550 {
26553 /* All thunks should be in the same object as their target,
26554 and thus binds_local_p should be true. */
26557 else
26558 {
26564 }
26565 }
26566 else
26567 {
26570 else
26571 #if TARGET_MACHO
26573 {
26575 tmp = (gen_rtx_SYMBOL_REF
26581 }
26582 else
26584 {
26591 }
26592 }
26594 }
26596 static void
26598 {
26600 #if TARGET_MACHO
26602 #endif
26609 }
26611 int
26613 {
26625 }
26627 /* Output assembler code to FILE to increment profiler label # LABELNO
26628 for profiling a function entry. */
26629 void
26631 {
26633 {
26634 #ifndef NO_PROFILE_COUNTERS
26636 #endif
26640 else
26642 }
26644 {
26645 #ifndef NO_PROFILE_COUNTERS
26647 labelno);
26648 #endif
26650 }
26651 else
26652 {
26653 #ifndef NO_PROFILE_COUNTERS
26655 labelno);
26656 #endif
26658 }
26659 }
26661 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26662 /* We don't have exact information about the insn sizes, but we may assume
26663 quite safely that we are informed about all 1 byte insns and memory
26664 address sizes. This is enough to eliminate unnecessary padding in
26665 99% of cases. */
26667 static int
26669 {
26675 /* Discard alignments we've emit and jump instructions. */
26682 /* Important case - calls are always 5 bytes.
26683 It is common to have many calls in the row. */
26692 /* For normal instructions we rely on get_attr_length being exact,
26693 with a few exceptions. */
26695 {
26699 {
26709 /* Otherwise trust get_attr_length. */
26711 }
26716 }
26719 else
26721 }
26723 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26724 window. */
26726 static void
26728 {
26733 /* Look for all minimal intervals of instructions containing 4 jumps.
26734 The intervals are bounded by START and INSN. NBYTES is the total
26735 size of instructions in the interval including INSN and not including
26736 START. When the NBYTES is smaller than 16 bytes, it is possible
26737 that the end of START and INSN ends up in the same 16byte page.
26739 The smallest offset in the page INSN can start is the case where START
26740 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26741 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26742 */
26744 {
26748 {
26754 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26755 already in the current 16 byte page, because otherwise
26756 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26757 bytes to reach 16 byte boundary. */
26765 {
26767 {
26774 else
26777 }
26778 }
26780 }
26791 njumps++;
26792 else
26796 {
26803 else
26806 }
26813 {
26820 }
26821 }
26822 }
26823 #endif
26825 /* AMD Athlon works faster
26826 when RET is not destination of conditional jump or directly preceded
26827 by other jump instruction. We avoid the penalty by inserting NOP just
26828 before the RET instructions in such cases. */
26829 static void
26831 {
26832 edge e;
26833 edge_iterator ei;
26836 {
26839 rtx prev;
26849 {
26850 edge e;
26851 edge_iterator ei;
26857 }
26859 {
26865 /* Empty functions get branch mispredict even when the jump destination
26866 is not visible to us. */
26869 }
26871 {
26874 }
26875 }
26876 }
26878 /* Implement machine specific optimizations. We implement padding of returns
26879 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26880 static void
26882 {
26884 {
26887 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26890 #endif
26891 }
26892 }
26894 /* Return nonzero when QImode register that must be represented via REX prefix
26895 is used. */
26896 bool
26898 {
26906 }
26908 /* Return nonzero when P points to register encoded via REX prefix.
26909 Called via for_each_rtx. */
26910 static int
26912 {
26918 }
26920 /* Return true when INSN mentions register that must be encoded using REX
26921 prefix. */
26922 bool
26924 {
26927 }
26929 /* If profitable, negate (without causing overflow) integer constant
26930 of mode MODE at location LOC. Return true in this case. */
26931 bool
26933 {
26934 HOST_WIDE_INT val;
26940 {
26942 /* DImode x86_64 constants must fit in 32 bits. */
26955 }
26957 /* Avoid overflows. */
26963 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
26964 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
26967 {
26970 }
26973 }
26975 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26976 optabs would emit if we didn't have TFmode patterns. */
26978 void
26980 {
27014 }
27015 \f
27016 /* AVX does not support 32-byte integer vector operations,
27017 thus the longest vector we are faced with is V16QImode. */
27018 #define MAX_VECT_LEN 16
27020 struct expand_vec_perm_d
27021 {
27027 };
27032 /* Get a vector mode of the same size as the original but with elements
27033 twice as wide. This is only guaranteed to apply to integral vectors. */
27037 {
27038 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
27043 }
27045 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27046 with all elements equal to VAR. Return true if successful. */
27048 static bool
27051 {
27055 {
27060 /* FALLTHRU */
27070 {
27073 /* First attempt to recognize VAL as-is. */
27077 {
27078 rtx seq;
27079 /* If that fails, force VAL into a register. */
27090 }
27091 }
27098 {
27099 rtx x;
27106 }
27116 {
27120 permute:
27127 /* Extend to SImode using a paradoxical SUBREG. */
27131 /* Insert the SImode value as low element of a V4SImode vector. */
27139 }
27147 widen:
27148 /* Replicate the value once into the next wider mode and recurse. */
27149 {
27151 rtx x;
27167 }
27171 {
27180 }
27185 }
27186 }
27188 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27189 whose ONE_VAR element is VAR, and other elements are zero. Return true
27190 if successful. */
27192 static bool
27195 {
27197 rtx new_target;
27202 {
27204 /* For SSE4.1, we normally use vector set. But if the second
27205 element is zero and inter-unit moves are OK, we use movq
27206 instead. */
27207 use_vector_set = (TARGET_64BIT
27208 && TARGET_SSE4_1
27209 && !(TARGET_INTER_UNIT_MOVES
27231 /* Use ix86_expand_vector_set in 64bit mode only. */
27236 }
27239 {
27244 }
27247 {
27252 /* FALLTHRU */
27267 else
27274 {
27275 /* We need to shuffle the value to the correct position, so
27276 create a new pseudo to store the intermediate result. */
27278 /* With SSE2, we can use the integer shuffle insns. */
27280 {
27282 const1_rtx,
27289 }
27291 /* Otherwise convert the intermediate result to V4SFmode and
27292 use the SSE1 shuffle instructions. */
27294 {
27297 }
27298 else
27302 const1_rtx,
27311 }
27326 widen:
27330 /* Zero extend the variable element to SImode and recurse. */
27343 }
27344 }
27346 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27347 consisting of the values in VALS. It is known that all elements
27348 except ONE_VAR are constants. Return true if successful. */
27350 static bool
27353 {
27363 {
27368 /* For the two element vectors, it's just as easy to use
27369 the general case. */
27373 /* Use ix86_expand_vector_set in 64bit mode only. */
27395 widen:
27396 /* There's no way to set one QImode entry easily. Combine
27397 the variable value with its adjacent constant value, and
27398 promote to an HImode set. */
27401 {
27406 }
27407 else
27408 {
27411 }
27425 }
27430 }
27432 /* A subroutine of ix86_expand_vector_init_general. Use vector
27433 concatenate to handle the most general case: all values variable,
27434 and none identical. */
27436 static void
27439 {
27442 rtvec v;
27446 {
27449 {
27482 }
27495 {
27510 }
27515 {
27526 }
27529 half:
27530 /* FIXME: We process inputs backward to help RA. PR 36222. */
27534 {
27539 }
27543 {
27546 {
27550 }
27553 }
27554 else
27560 }
27561 }
27563 /* A subroutine of ix86_expand_vector_init_general. Use vector
27564 interleave to handle the most general case: all values variable,
27565 and none identical. */
27567 static void
27570 {
27579 {
27600 }
27603 {
27604 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27608 /* Insert the SImode value as low element of V4SImode vector. */
27612 op0),
27614 const1_rtx);
27617 /* Cast the V4SImode vector back to a vector in orignal mode. */
27621 /* Load even elements into the second positon. */
27625 const1_rtx));
27627 /* Cast vector to FIRST_IMODE vector. */
27630 }
27632 /* Interleave low FIRST_IMODE vectors. */
27634 {
27638 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27641 }
27643 /* Interleave low SECOND_IMODE vectors. */
27645 {
27648 {
27653 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27654 vector. */
27657 }
27660 /* FALLTHRU */
27667 /* Cast the SECOND_IMODE vector back to a vector on original
27668 mode. */
27675 }
27676 }
27678 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27679 all values variable, and none identical. */
27681 static void
27684 {
27690 {
27695 /* FALLTHRU */
27719 half:
27736 /* FALLTHRU */
27742 /* Don't use ix86_expand_vector_init_interleave if we can't
27743 move from GPR to SSE register directly. */
27759 }
27761 {
27773 {
27777 {
27783 else
27784 {
27789 }
27790 }
27793 }
27798 {
27804 }
27806 {
27812 }
27813 else
27815 }
27816 }
27818 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27819 instructions unless MMX_OK is true. */
27821 void
27823 {
27830 rtx x;
27833 {
27843 }
27845 /* Constants are best loaded from the constant pool. */
27847 {
27850 }
27852 /* If all values are identical, broadcast the value. */
27858 /* Values where only one field is non-constant are best loaded from
27859 the pool and overwritten via move later. */
27861 {
27865 one_var))
27870 }
27873 }
27875 void
27877 {
27882 rtx tmp;
27884 = {
27891 };
27893 = {
27900 };
27904 {
27908 {
27913 else
27917 }
27926 {
27929 /* For the two element vectors, we implement a VEC_CONCAT with
27930 the extraction of the other element. */
27937 else
27942 }
27951 {
27957 /* tmp = target = A B C D */
27959 /* target = A A B B */
27961 /* target = X A B B */
27963 /* target = A X C D */
27970 /* tmp = target = A B C D */
27972 /* tmp = X B C D */
27974 /* target = A B X D */
27981 /* tmp = target = A B C D */
27983 /* tmp = X B C D */
27985 /* target = A B X D */
27993 }
28001 /* Element 0 handled by vec_merge below. */
28003 {
28006 }
28009 {
28010 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28011 store into element 0, then shuffle them back. */
28028 }
28029 else
28030 {
28031 /* For SSE1, we have to reuse the V4SF code. */
28034 }
28087 half:
28088 /* Compute offset. */
28094 /* Extract the half. */
28098 /* Put val in tmp at elt. */
28101 /* Put it back. */
28107 }
28110 {
28114 }
28115 else
28116 {
28125 }
28126 }
28128 void
28130 {
28134 rtx tmp;
28137 {
28142 /* FALLTHRU */
28155 {
28175 }
28187 {
28189 {
28209 }
28213 }
28214 else
28215 {
28216 /* For SSE1, we have to reuse the V4SF code. */
28220 }
28235 /* ??? Could extract the appropriate HImode element and shift. */
28238 }
28241 {
28245 /* Let the rtl optimizers know about the zero extension performed. */
28247 {
28250 }
28253 }
28254 else
28255 {
28262 }
28263 }
28265 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28266 pattern to reduce; DEST is the destination; IN is the input vector. */
28268 void
28270 {
28284 }
28285 \f
28286 /* Target hook for scalar_mode_supported_p. */
28287 static bool
28289 {
28294 else
28296 }
28298 /* Implements target hook vector_mode_supported_p. */
28299 static bool
28301 {
28313 }
28315 /* Target hook for c_mode_for_suffix. */
28316 static enum machine_mode
28318 {
28325 }
28327 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28329 We do this in the new i386 backend to maintain source compatibility
28330 with the old cc0-based compiler. */
28332 static tree
28334 tree inputs ATTRIBUTE_UNUSED,
28335 tree clobbers)
28336 {
28338 clobbers);
28340 clobbers);
28342 }
28344 /* Implements target vector targetm.asm.encode_section_info. This
28345 is not used by netware. */
28347 static void ATTRIBUTE_UNUSED
28349 {
28356 }
28358 /* Worker function for REVERSE_CONDITION. */
28360 enum rtx_code
28362 {
28366 }
28368 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28369 to OPERANDS[0]. */
28373 {
28375 {
28378 {
28382 }
28386 }
28388 {
28392 else
28393 {
28394 /* There is no non-popping store to memory for XFmode.
28395 So if we need one, follow the store with a load. */
28398 else
28400 }
28401 }
28402 else
28404 }
28406 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28407 FP status register is set. */
28409 void
28411 {
28413 rtx temp;
28418 {
28423 }
28424 else
28425 {
28430 }
28434 pc_rtx);
28439 }
28441 /* Output code to perform a log1p XFmode calculation. */
28444 {
28450 rtx test;
28456 XFmode));
28470 }
28472 /* Output code to perform a Newton-Rhapson approximation of a single precision
28473 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28476 {
28491 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28493 /* x0 = rcp(b) estimate */
28496 UNSPEC_RCP)));
28497 /* e0 = x0 * a */
28500 /* e1 = x0 * b */
28503 /* x1 = 2. - e1 */
28506 /* res = e0 * x1 */
28509 }
28511 /* Output code to perform a Newton-Rhapson approximation of a
28512 single precision floating point [reciprocal] square root. */
28516 {
28518 REAL_VALUE_TYPE r;
28533 {
28536 }
28538 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28539 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28541 /* x0 = rsqrt(a) estimate */
28544 UNSPEC_RSQRT)));
28546 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28548 {
28560 }
28562 /* e0 = x0 * a */
28565 /* e1 = e0 * x0 */
28569 /* e2 = e1 - 3. */
28576 /* e3 = -.5 * x0 */
28579 else
28580 /* e3 = -.5 * e0 */
28583 /* ret = e2 * e3 */
28586 }
28588 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28590 static void ATTRIBUTE_UNUSED
28592 tree decl)
28593 {
28594 /* With Binutils 2.15, the "@unwind" marker must be specified on
28595 every occurrence of the ".eh_frame" section, not just the first
28596 one. */
28599 {
28603 }
28605 }
28607 /* Return the mangling of TYPE if it is an extended fundamental type. */
28611 {
28619 {
28621 /* __float128 is "g". */
28624 /* "long double" or __float80 is "e". */
28628 }
28629 }
28631 /* For 32-bit code we can save PIC register setup by using
28632 __stack_chk_fail_local hidden function instead of calling
28633 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28634 register, so it is better to call __stack_chk_fail directly. */
28636 static tree
28638 {
28639 return TARGET_64BIT
28642 }
28644 /* Select a format to encode pointers in exception handling data. CODE
28645 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28646 true if the symbol may be affected by dynamic relocations.
28648 ??? All x86 object file formats are capable of representing this.
28649 After all, the relocation needed is the same as for the call insn.
28650 Whether or not a particular assembler allows us to enter such, I
28651 guess we'll have to see. */
28652 int
28654 {
28656 {
28663 }
28668 }
28669 \f
28670 /* Expand copysign from SIGN to the positive value ABS_VALUE
28671 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28672 the sign-bit. */
28673 static void
28675 {
28679 {
28682 {
28683 /* We need to generate a scalar mode mask in this case. */
28688 }
28689 }
28690 else
28696 }
28698 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28699 mask for masking out the sign-bit is stored in *SMASK, if that is
28700 non-null. */
28701 static rtx
28703 {
28710 {
28711 /* We need to generate a scalar mode mask in this case. */
28716 }
28724 }
28726 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28727 swapping the operands if SWAP_OPERANDS is true. The expanded
28728 code is a forward jump to a newly created label in case the
28729 comparison is true. The generated label rtx is returned. */
28730 static rtx
28733 {
28737 {
28741 }
28754 }
28756 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28757 using comparison code CODE. Operands are swapped for the comparison if
28758 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28759 static rtx
28762 {
28767 {
28771 }
28776 else
28781 }
28783 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28784 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28785 static rtx
28787 {
28788 REAL_VALUE_TYPE TWO52r;
28789 rtx TWO52;
28796 }
28798 /* Expand SSE sequence for computing lround from OP1 storing
28799 into OP0. */
28800 void
28802 {
28803 /* C code for the stuff we're doing below:
28804 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28805 return (long)tmp;
28806 */
28810 rtx adj;
28812 /* load nextafter (0.5, 0.0) */
28817 /* adj = copysign (0.5, op1) */
28821 /* adj = op1 + adj */
28824 /* op0 = (imode)adj */
28826 }
28828 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28829 into OPERAND0. */
28830 void
28832 {
28833 /* C code for the stuff we're doing below (for do_floor):
28834 xi = (long)op1;
28835 xi -= (double)xi > op1 ? 1 : 0;
28836 return xi;
28837 */
28842 /* reg = (long)op1 */
28846 /* freg = (double)reg */
28850 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28861 }
28863 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28864 result in OPERAND0. */
28865 void
28867 {
28868 /* C code for the stuff we're doing below:
28869 xa = fabs (operand1);
28870 if (!isless (xa, 2**52))
28871 return operand1;
28872 xa = xa + 2**52 - 2**52;
28873 return copysign (xa, operand1);
28874 */
28881 /* xa = abs (operand1) */
28884 /* if (!isless (xa, TWO52)) goto label; */
28897 }
28899 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28900 into OPERAND0. */
28901 void
28903 {
28904 /* C code for the stuff we expand below.
28905 double xa = fabs (x), x2;
28906 if (!isless (xa, TWO52))
28907 return x;
28908 xa = xa + TWO52 - TWO52;
28909 x2 = copysign (xa, x);
28910 Compensate. Floor:
28911 if (x2 > x)
28912 x2 -= 1;
28913 Compensate. Ceil:
28914 if (x2 < x)
28915 x2 -= -1;
28916 return x2;
28917 */
28923 /* Temporary for holding the result, initialized to the input
28924 operand to ease control flow. */
28928 /* xa = abs (operand1) */
28931 /* if (!isless (xa, TWO52)) goto label; */
28934 /* xa = xa + TWO52 - TWO52; */
28938 /* xa = copysign (xa, operand1) */
28941 /* generate 1.0 or -1.0 */
28946 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28950 /* We always need to subtract here to preserve signed zero. */
28959 }
28961 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28962 into OPERAND0. */
28963 void
28965 {
28966 /* C code for the stuff we expand below.
28967 double xa = fabs (x), x2;
28968 if (!isless (xa, TWO52))
28969 return x;
28970 x2 = (double)(long)x;
28971 Compensate. Floor:
28972 if (x2 > x)
28973 x2 -= 1;
28974 Compensate. Ceil:
28975 if (x2 < x)
28976 x2 += 1;
28977 if (HONOR_SIGNED_ZEROS (mode))
28978 return copysign (x2, x);
28979 return x2;
28980 */
28986 /* Temporary for holding the result, initialized to the input
28987 operand to ease control flow. */
28991 /* xa = abs (operand1) */
28994 /* if (!isless (xa, TWO52)) goto label; */
28997 /* xa = (double)(long)x */
29002 /* generate 1.0 */
29005 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29020 }
29022 /* Expand SSE sequence for computing round from OPERAND1 storing
29023 into OPERAND0. Sequence that works without relying on DImode truncation
29024 via cvttsd2siq that is only available on 64bit targets. */
29025 void
29027 {
29028 /* C code for the stuff we expand below.
29029 double xa = fabs (x), xa2, x2;
29030 if (!isless (xa, TWO52))
29031 return x;
29032 Using the absolute value and copying back sign makes
29033 -0.0 -> -0.0 correct.
29034 xa2 = xa + TWO52 - TWO52;
29035 Compensate.
29036 dxa = xa2 - xa;
29037 if (dxa <= -0.5)
29038 xa2 += 1;
29039 else if (dxa > 0.5)
29040 xa2 -= 1;
29041 x2 = copysign (xa2, x);
29042 return x2;
29043 */
29049 /* Temporary for holding the result, initialized to the input
29050 operand to ease control flow. */
29054 /* xa = abs (operand1) */
29057 /* if (!isless (xa, TWO52)) goto label; */
29060 /* xa2 = xa + TWO52 - TWO52; */
29064 /* dxa = xa2 - xa; */
29067 /* generate 0.5, 1.0 and -0.5 */
29073 /* Compensate. */
29075 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29080 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29086 /* res = copysign (xa2, operand1) */
29093 }
29095 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29096 into OPERAND0. */
29097 void
29099 {
29100 /* C code for SSE variant we expand below.
29101 double xa = fabs (x), x2;
29102 if (!isless (xa, TWO52))
29103 return x;
29104 x2 = (double)(long)x;
29105 if (HONOR_SIGNED_ZEROS (mode))
29106 return copysign (x2, x);
29107 return x2;
29108 */
29114 /* Temporary for holding the result, initialized to the input
29115 operand to ease control flow. */
29119 /* xa = abs (operand1) */
29122 /* if (!isless (xa, TWO52)) goto label; */
29125 /* x = (double)(long)x */
29137 }
29139 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29140 into OPERAND0. */
29141 void
29143 {
29147 /* C code for SSE variant we expand below.
29148 double xa = fabs (x), x2;
29149 if (!isless (xa, TWO52))
29150 return x;
29151 xa2 = xa + TWO52 - TWO52;
29152 Compensate:
29153 if (xa2 > xa)
29154 xa2 -= 1.0;
29155 x2 = copysign (xa2, x);
29156 return x2;
29157 */
29161 /* Temporary for holding the result, initialized to the input
29162 operand to ease control flow. */
29166 /* xa = abs (operand1) */
29169 /* if (!isless (xa, TWO52)) goto label; */
29172 /* res = xa + TWO52 - TWO52; */
29177 /* generate 1.0 */
29180 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29188 /* res = copysign (res, operand1) */
29195 }
29197 /* Expand SSE sequence for computing round from OPERAND1 storing
29198 into OPERAND0. */
29199 void
29201 {
29202 /* C code for the stuff we're doing below:
29203 double xa = fabs (x);
29204 if (!isless (xa, TWO52))
29205 return x;
29206 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29207 return copysign (xa, x);
29208 */
29214 /* Temporary for holding the result, initialized to the input
29215 operand to ease control flow. */
29223 /* load nextafter (0.5, 0.0) */
29228 /* xa = xa + 0.5 */
29232 /* xa = (double)(int64_t)xa */
29237 /* res = copysign (xa, operand1) */
29244 }
29245 \f
29247 /* Table of valid machine attributes. */
29249 {
29250 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29251 /* Stdcall attribute says callee is responsible for popping arguments
29252 if they are not variable. */
29254 /* Fastcall attribute says callee is responsible for popping arguments
29255 if they are not variable. */
29257 /* Thiscall attribute says callee is responsible for popping arguments
29258 if they are not variable. */
29260 /* Cdecl attribute says the callee is a normal C declaration */
29262 /* Regparm attribute specifies how many integer arguments are to be
29263 passed in registers. */
29265 /* Sseregparm attribute says we are using x86_64 calling conventions
29266 for FP arguments. */
29268 /* force_align_arg_pointer says this function realigns the stack at entry. */
29271 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29275 #endif
29278 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29279 SUBTARGET_ATTRIBUTE_TABLE,
29280 #endif
29281 /* ms_abi and sysv_abi calling convention function attributes. */
29285 /* End element. */
29287 };
29289 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29290 static int
29292 {
29293 /* If the branch of the runtime test is taken - i.e. - the vectorized
29294 version is skipped - this incurs a misprediction cost (because the
29295 vectorized version is expected to be the fall-through). So we subtract
29296 the latency of a mispredicted branch from the costs that are incured
29297 when the vectorized version is executed.
29299 TODO: The values in individual target tables have to be tuned or new
29300 fields may be needed. For eg. on K8, the default branch path is the
29301 not-taken path. If the taken path is predicted correctly, the minimum
29302 penalty of going down the taken-path is 1 cycle. If the taken-path is
29303 not predicted correctly, then the minimum penalty is 10 cycles. */
29306 {
29308 }
29309 else
29311 }
29313 /* Implement targetm.vectorize.builtin_vec_perm. */
29315 static tree
29317 {
29325 {
29332 get_di:
29343 get_si:
29362 }
29369 }
29371 /* Return a vector mode with twice as many elements as VMODE. */
29372 /* ??? Consider moving this to a table generated by genmodes.c. */
29374 static enum machine_mode
29376 {
29378 {
29401 }
29402 }
29404 /* Construct (set target (vec_select op0 (parallel perm))) and
29405 return true if that's a valid instruction in the active ISA. */
29407 static bool
29409 {
29422 {
29425 }
29427 }
29429 /* Similar, but generate a vec_concat from op0 and op1 as well. */
29431 static bool
29434 {
29436 rtx x;
29441 }
29443 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29444 in terms of blendp[sd] / pblendw / pblendvb. */
29446 static bool
29448 {
29458 /* This is a blend, not a permute. Elements must stay in their
29459 respective lanes. */
29461 {
29465 }
29470 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
29471 decision should be extracted elsewhere, so that we only try that
29472 sequence once all budget==3 options have been tried. */
29474 /* For bytes, see if bytes move in pairs so we can use pblendw with
29475 an immediate argument, rather than pblendvb with a vector argument. */
29477 {
29483 {
29494 }
29495 }
29503 {
29527 do_subreg:
29536 }
29538 /* This matches five different patterns with the different modes. */
29544 }
29546 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29547 in terms of the variable form of vpermilps.
29549 Note that we will have already failed the immediate input vpermilps,
29550 which requires that the high and low part shuffle be identical; the
29551 variable form doesn't require that. */
29553 static bool
29555 {
29562 /* We can only permute within the 128-bit lane. */
29564 {
29568 }
29574 {
29577 /* Within each 128-bit lane, the elements of op0 are numbered
29578 from 0 and the elements of op1 are numbered from 4. */
29585 }
29592 }
29594 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29595 in terms of pshufb or vpperm. */
29597 static bool
29599 {
29615 {
29619 }
29628 else
29629 {
29632 }
29635 }
29637 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
29638 in a single instruction. */
29640 static bool
29642 {
29646 /* Check plain VEC_SELECT first, because AVX has instructions that could
29647 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
29648 input where SEL+CONCAT may not. */
29650 {
29659 /* There are plenty of patterns in sse.md that are written for
29660 SEL+CONCAT and are not replicated for a single op. Perhaps
29661 that should be changed, to avoid the nastiness here. */
29663 /* Recognize interleave style patterns, which means incrementing
29664 every other permutation operand. */
29666 {
29669 }
29673 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
29675 {
29677 {
29682 }
29686 }
29687 }
29689 /* Finally, try the fully general two operand permute. */
29693 /* Recognize interleave style patterns with reversed operands. */
29695 {
29697 {
29701 else
29704 }
29708 }
29710 /* Try the SSE4.1 blend variable merge instructions. */
29714 /* Try one of the AVX vpermil variable permutations. */
29718 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
29723 }
29725 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29726 in terms of a pair of pshuflw + pshufhw instructions. */
29728 static bool
29730 {
29738 /* The two permutations only operate in 64-bit lanes. */
29749 /* Emit the pshuflw. */
29756 /* Emit the pshufhw. */
29764 }
29766 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29767 the permutation using the SSSE3 palignr instruction. This succeeds
29768 when all of the elements in PERM fit within one vector and we merely
29769 need to shift them down so that a single vector permutation has a
29770 chance to succeed. */
29772 static bool
29774 {
29778 rtx shift;
29780 /* Even with AVX, palignr only operates on 128-bit vectors. */
29786 {
29792 }
29796 /* Given that we have SSSE3, we know we'll be able to implement the
29797 single operand permutation after the palignr with pshufb. */
29810 {
29815 }
29817 /* Test for the degenerate case where the alignment by itself
29818 produces the desired permutation. */
29826 }
29828 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29829 a two vector permutation into a single vector permutation by using
29830 an interleave operation to merge the vectors. */
29832 static bool
29834 {
29839 rtx seq;
29845 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
29846 lanes. We can use similar techniques with the vperm2f128 instruction,
29847 but it requires slightly different logic. */
29851 /* Examine from whence the elements come. */
29856 /* Split the two input vectors into 4 halves. */
29865 /* If the elements from the low halves use interleave low, and similarly
29866 for interleave high. If the elements are from mis-matched halves, we
29867 can use shufps for V4SF/V4SI or do a DImode shuffle. */
29869 {
29871 {
29876 }
29877 }
29879 {
29881 {
29886 }
29887 }
29889 {
29891 {
29896 }
29898 {
29903 }
29904 }
29906 {
29908 {
29913 }
29915 {
29920 }
29921 }
29922 else
29925 /* Use the remapping array set up above to move the elements from their
29926 swizzled locations into their final destinations. */
29929 {
29933 }
29938 /* Test if the final remap can be done with a single insn. For V4SFmode or
29939 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
29949 {
29953 }
29960 }
29962 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
29963 permutation with two pshufb insns and an ior. We should have already
29964 failed all two instruction sequences. */
29966 static bool
29968 {
29979 /* Generate two permutation masks. If the required element is within
29980 the given vector it is shuffled into the proper lane. If the required
29981 element is in the other vector, force a zero into the lane by setting
29982 bit 7 in the permutation mask. */
29985 {
29992 {
29995 }
29996 }
30016 }
30018 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
30019 and extract-odd permutations. */
30021 static bool
30023 {
30027 {
30032 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
30036 /* Now an unpck[lh]pd will produce the result required. */
30039 else
30045 {
30055 /* Shuffle within the 128-bit lanes to produce:
30056 { 0 2 1 3 4 6 5 7 } and { 8 a 9 b c e d f }. */
30060 /* Shuffle the lanes around to produce:
30061 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
30065 /* Now a vpermil2p will produce the result required. */
30066 /* ??? The vpermil2p requires a vector constant. Another option
30067 is a unpck[lh]ps to merge the two vectors to produce
30068 { 0 4 2 6 8 c a e } or { 1 5 3 7 9 d b f }. Then use another
30069 vpermilps to get the elements into the final order. */
30074 }
30081 /* These are always directly implementable by expand_vec_perm_1. */
30087 else
30088 {
30089 /* We need 2*log2(N)-1 operations to achieve odd/even
30090 with interleave. */
30099 else
30102 }
30108 else
30109 {
30121 else
30124 }
30129 }
30132 }
30134 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
30135 extract-even and extract-odd permutations. */
30137 static bool
30139 {
30151 }
30153 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
30154 permutations. We assume that expand_vec_perm_1 has already failed. */
30156 static bool
30158 {
30166 {
30169 /* These are special-cased in sse.md so that we can optionally
30170 use the vbroadcast instruction. They expand to two insns
30171 if the input happens to be in a register. */
30178 /* These are always implementable using standard shuffle patterns. */
30183 /* These can be implemented via interleave. We save one insn by
30184 stopping once we have promoted to V4SImode and then use pshufd. */
30185 do
30186 {
30190 {
30193 }
30199 }
30209 }
30210 }
30212 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
30213 broadcast permutations. */
30215 static bool
30217 {
30229 }
30231 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
30232 With all of the interface bits taken care of, perform the expansion
30233 in D and return true on success. */
30235 static bool
30237 {
30238 /* Try a single instruction expansion. */
30242 /* Try sequences of two instructions. */
30256 /* Try sequences of three instructions. */
30261 /* ??? Look for narrow permutations whose element orderings would
30262 allow the promotion to a wider mode. */
30264 /* ??? Look for sequences of interleave or a wider permute that place
30265 the data into the correct lanes for a half-vector shuffle like
30266 pshuf[lh]w or vpermilps. */
30268 /* ??? Look for sequences of interleave that produce the desired results.
30269 The combinatorics of punpck[lh] get pretty ugly... */
30275 }
30277 /* Extract the values from the vector CST into the permutation array in D.
30278 Return 0 on error, 1 if all values from the permutation come from the
30279 first vector, 2 if all values from the second vector, and 3 otherwise. */
30281 static int
30283 {
30289 {
30300 }
30303 /* For all elements from second vector, fold the elements to first. */
30309 }
30311 static rtx
30313 {
30327 {
30331 }
30334 {
30344 {
30350 }
30352 /* The elements of PERM do not suggest that only the first operand
30353 is used, but both operands are identical. Allow easier matching
30354 of the permutation by folding the permutation into the single
30355 input vector. */
30356 {
30361 }
30362 /* FALLTHRU */
30375 }
30381 /* For compiler generated permutations, we should never got here, because
30382 the compiler should also be checking the ok hook. But since this is a
30383 builtin the user has access too, so don't abort. */
30385 {
30408 }
30409 exit_error:
30411 }
30413 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
30415 static bool
30417 {
30426 /* Given sufficient ISA support we can just return true here
30427 for selected vector modes. */
30429 {
30430 /* All implementable with a single vpperm insn. */
30433 /* All implementable with 2 pshufb + 1 ior. */
30436 /* All implementable with shufpd or unpck[lh]pd. */
30439 }
30443 /* This hook is cannot be called in response to something that the
30444 user does (unlike the builtin expander) so we shouldn't ever see
30445 an error generated from the extract. */
30449 /* Implementable with shufps or pshufd. */
30453 /* Otherwise we have to go through the motions and see if we can
30454 figure out how to generate the requested permutation. */
30465 }
30467 void
30469 {
30483 /* We'll either be able to implement the permutation directly... */
30487 /* ... or we use the special-case patterns. */
30489 }
30490 \f
30491 /* This function returns the calling abi specific va_list type node.
30492 It returns the FNDECL specific va_list type. */
30494 tree
30496 {
30503 else
30505 }
30507 /* Returns the canonical va_list type specified by TYPE. If there
30508 is no valid TYPE provided, it return NULL_TREE. */
30510 tree
30512 {
30515 /* Resolve references and pointers to va_list type. */
30522 {
30527 {
30528 /* If va_list is an array type, the argument may have decayed
30529 to a pointer type, e.g. by being passed to another function.
30530 In that case, unwrap both types so that we can compare the
30531 underlying records. */
30534 {
30537 }
30538 }
30545 {
30546 /* If va_list is an array type, the argument may have decayed
30547 to a pointer type, e.g. by being passed to another function.
30548 In that case, unwrap both types so that we can compare the
30549 underlying records. */
30552 {
30555 }
30556 }
30563 {
30564 /* If va_list is an array type, the argument may have decayed
30565 to a pointer type, e.g. by being passed to another function.
30566 In that case, unwrap both types so that we can compare the
30567 underlying records. */
30570 {
30573 }
30574 }
30578 }
30580 }
30582 /* Iterate through the target-specific builtin types for va_list.
30583 IDX denotes the iterator, *PTREE is set to the result type of
30584 the va_list builtin, and *PNAME to its internal type.
30585 Returns zero if there is no element for this index, otherwise
30586 IDX should be increased upon the next call.
30587 Note, do not iterate a base builtin's name like __builtin_va_list.
30588 Used from c_common_nodes_and_builtins. */
30590 int
30592 {
30606 }
30608 }
30610 /* Initialize the GCC target structure. */
30611 #undef TARGET_RETURN_IN_MEMORY
30612 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30614 #undef TARGET_LEGITIMIZE_ADDRESS
30615 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30617 #undef TARGET_ATTRIBUTE_TABLE
30618 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30619 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30620 # undef TARGET_MERGE_DECL_ATTRIBUTES
30621 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30622 #endif
30624 #undef TARGET_COMP_TYPE_ATTRIBUTES
30625 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30627 #undef TARGET_INIT_BUILTINS
30628 #define TARGET_INIT_BUILTINS ix86_init_builtins
30629 #undef TARGET_BUILTIN_DECL
30630 #define TARGET_BUILTIN_DECL ix86_builtin_decl
30631 #undef TARGET_EXPAND_BUILTIN
30632 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30634 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30635 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30636 ix86_builtin_vectorized_function
30638 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30639 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30641 #undef TARGET_BUILTIN_RECIPROCAL
30642 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30644 #undef TARGET_ASM_FUNCTION_EPILOGUE
30645 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30647 #undef TARGET_ENCODE_SECTION_INFO
30648 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30649 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30650 #else
30651 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30652 #endif
30654 #undef TARGET_ASM_OPEN_PAREN
30656 #undef TARGET_ASM_CLOSE_PAREN
30659 #undef TARGET_ASM_BYTE_OP
30660 #define TARGET_ASM_BYTE_OP ASM_BYTE
30662 #undef TARGET_ASM_ALIGNED_HI_OP
30663 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30664 #undef TARGET_ASM_ALIGNED_SI_OP
30665 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30666 #ifdef ASM_QUAD
30667 #undef TARGET_ASM_ALIGNED_DI_OP
30668 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30669 #endif
30671 #undef TARGET_ASM_UNALIGNED_HI_OP
30672 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30673 #undef TARGET_ASM_UNALIGNED_SI_OP
30674 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30675 #undef TARGET_ASM_UNALIGNED_DI_OP
30676 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30678 #undef TARGET_SCHED_ADJUST_COST
30679 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30680 #undef TARGET_SCHED_ISSUE_RATE
30681 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30682 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30683 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30684 ia32_multipass_dfa_lookahead
30686 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30687 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30689 #ifdef HAVE_AS_TLS
30690 #undef TARGET_HAVE_TLS
30691 #define TARGET_HAVE_TLS true
30692 #endif
30693 #undef TARGET_CANNOT_FORCE_CONST_MEM
30694 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30695 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30696 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30698 #undef TARGET_DELEGITIMIZE_ADDRESS
30699 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30701 #undef TARGET_MS_BITFIELD_LAYOUT_P
30702 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30704 #if TARGET_MACHO
30705 #undef TARGET_BINDS_LOCAL_P
30706 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30707 #endif
30708 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30709 #undef TARGET_BINDS_LOCAL_P
30710 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30711 #endif
30713 #undef TARGET_ASM_OUTPUT_MI_THUNK
30714 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30715 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30716 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30718 #undef TARGET_ASM_FILE_START
30719 #define TARGET_ASM_FILE_START x86_file_start
30721 #undef TARGET_DEFAULT_TARGET_FLAGS
30722 #define TARGET_DEFAULT_TARGET_FLAGS \
30723 (TARGET_DEFAULT \
30724 | TARGET_SUBTARGET_DEFAULT \
30725 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT \
30726 | MASK_FUSED_MADD)
30728 #undef TARGET_HANDLE_OPTION
30729 #define TARGET_HANDLE_OPTION ix86_handle_option
30731 #undef TARGET_RTX_COSTS
30732 #define TARGET_RTX_COSTS ix86_rtx_costs
30733 #undef TARGET_ADDRESS_COST
30734 #define TARGET_ADDRESS_COST ix86_address_cost
30736 #undef TARGET_FIXED_CONDITION_CODE_REGS
30737 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30738 #undef TARGET_CC_MODES_COMPATIBLE
30739 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30741 #undef TARGET_MACHINE_DEPENDENT_REORG
30742 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30744 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30745 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30747 #undef TARGET_BUILD_BUILTIN_VA_LIST
30748 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30750 #undef TARGET_FN_ABI_VA_LIST
30751 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30753 #undef TARGET_CANONICAL_VA_LIST_TYPE
30754 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30756 #undef TARGET_EXPAND_BUILTIN_VA_START
30757 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30759 #undef TARGET_MD_ASM_CLOBBERS
30760 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30762 #undef TARGET_PROMOTE_PROTOTYPES
30763 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30764 #undef TARGET_STRUCT_VALUE_RTX
30765 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30766 #undef TARGET_SETUP_INCOMING_VARARGS
30767 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30768 #undef TARGET_MUST_PASS_IN_STACK
30769 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30770 #undef TARGET_PASS_BY_REFERENCE
30771 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30772 #undef TARGET_INTERNAL_ARG_POINTER
30773 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30774 #undef TARGET_UPDATE_STACK_BOUNDARY
30775 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30776 #undef TARGET_GET_DRAP_RTX
30777 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30778 #undef TARGET_STRICT_ARGUMENT_NAMING
30779 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30780 #undef TARGET_STATIC_CHAIN
30781 #define TARGET_STATIC_CHAIN ix86_static_chain
30782 #undef TARGET_TRAMPOLINE_INIT
30783 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
30785 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30786 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30788 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30789 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30791 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30792 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30794 #undef TARGET_C_MODE_FOR_SUFFIX
30795 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30797 #ifdef HAVE_AS_TLS
30798 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30799 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30800 #endif
30802 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30803 #undef TARGET_INSERT_ATTRIBUTES
30804 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30805 #endif
30807 #undef TARGET_MANGLE_TYPE
30808 #define TARGET_MANGLE_TYPE ix86_mangle_type
30810 #undef TARGET_STACK_PROTECT_FAIL
30811 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30813 #undef TARGET_FUNCTION_VALUE
30814 #define TARGET_FUNCTION_VALUE ix86_function_value
30816 #undef TARGET_FUNCTION_VALUE_REGNO_P
30817 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
30819 #undef TARGET_SECONDARY_RELOAD
30820 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30822 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30823 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
30824 ix86_builtin_vectorization_cost
30825 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
30826 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
30827 ix86_vectorize_builtin_vec_perm
30828 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
30829 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
30830 ix86_vectorize_builtin_vec_perm_ok
30832 #undef TARGET_SET_CURRENT_FUNCTION
30833 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30835 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30836 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30838 #undef TARGET_OPTION_SAVE
30839 #define TARGET_OPTION_SAVE ix86_function_specific_save
30841 #undef TARGET_OPTION_RESTORE
30842 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30844 #undef TARGET_OPTION_PRINT
30845 #define TARGET_OPTION_PRINT ix86_function_specific_print
30847 #undef TARGET_CAN_INLINE_P
30848 #define TARGET_CAN_INLINE_P ix86_can_inline_p
30850 #undef TARGET_EXPAND_TO_RTL_HOOK
30851 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30853 #undef TARGET_LEGITIMATE_ADDRESS_P
30854 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30856 #undef TARGET_IRA_COVER_CLASSES
30857 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
30859 #undef TARGET_FRAME_POINTER_REQUIRED
30860 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
30862 #undef TARGET_CAN_ELIMINATE
30863 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
30865 #undef TARGET_ASM_CODE_END
30866 #define TARGET_ASM_CODE_END ix86_code_end
30869 \f