1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
44 #include "target-def.h"
49 /* Usable when we have an amount to add or subtract, and want the
50 optimal size of the insn. */
51 #define ADDITIVE_SIZE_MODIFIER(size) \
52 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
54 #define LOSE_AND_RETURN(msgid, x) \
57 cris_operand_lossage (msgid, x); \
61 enum cris_retinsn_type
62 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
64 /* Per-function machine data. */
65 struct GTY(()) machine_function
67 int needs_return_address_on_stack
;
69 /* This is the number of registers we save in the prologue due to
73 enum cris_retinsn_type return_type
;
76 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
78 static char cris_output_insn_is_bound
= 0;
80 /* In code for output macros, this is how we know whether e.g. constant
81 goes in code or in a static initializer. */
82 static int in_code
= 0;
84 /* Fix for reg_overlap_mentioned_p. */
85 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
87 static enum machine_mode
cris_promote_function_mode (const_tree
, enum machine_mode
,
88 int *, const_tree
, int);
90 static void cris_print_base (rtx
, FILE *);
92 static void cris_print_index (rtx
, FILE *);
94 static void cris_output_addr_const (FILE *, rtx
);
96 static struct machine_function
* cris_init_machine_status (void);
98 static rtx
cris_struct_value_rtx (tree
, int);
100 static void cris_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
101 tree type
, int *, int);
103 static int cris_initial_frame_pointer_offset (void);
105 static int saved_regs_mentioned (rtx
);
107 static void cris_operand_lossage (const char *, rtx
);
109 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
111 static void cris_asm_output_mi_thunk
112 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
114 static void cris_file_start (void);
115 static void cris_init_libfuncs (void);
117 static bool cris_rtx_costs (rtx
, int, int, int *, bool);
118 static int cris_address_cost (rtx
, bool);
119 static bool cris_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
121 static int cris_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
123 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
125 static bool cris_handle_option (size_t, const char *, int);
127 static bool cris_frame_pointer_required (void);
129 static void cris_asm_trampoline_template (FILE *);
130 static void cris_trampoline_init (rtx
, tree
, rtx
);
132 static rtx
cris_function_value(const_tree
, const_tree
, bool);
133 static rtx
cris_libcall_value (enum machine_mode
, const_rtx
);
135 /* This is the parsed result of the "-max-stack-stackframe=" option. If
136 it (still) is zero, then there was no such option given. */
137 int cris_max_stackframe
= 0;
139 /* This is the parsed result of the "-march=" option, if given. */
140 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
142 #undef TARGET_ASM_ALIGNED_HI_OP
143 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
144 #undef TARGET_ASM_ALIGNED_SI_OP
145 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
146 #undef TARGET_ASM_ALIGNED_DI_OP
147 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
149 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
150 available in ELF. These "normal" pseudos do not have any alignment
151 constraints or side-effects. */
152 #undef TARGET_ASM_UNALIGNED_HI_OP
153 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
155 #undef TARGET_ASM_UNALIGNED_SI_OP
156 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
158 #undef TARGET_ASM_UNALIGNED_DI_OP
159 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
161 #undef TARGET_ASM_OUTPUT_MI_THUNK
162 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
163 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
164 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
166 #undef TARGET_ASM_FILE_START
167 #define TARGET_ASM_FILE_START cris_file_start
169 #undef TARGET_INIT_LIBFUNCS
170 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
172 #undef TARGET_RTX_COSTS
173 #define TARGET_RTX_COSTS cris_rtx_costs
174 #undef TARGET_ADDRESS_COST
175 #define TARGET_ADDRESS_COST cris_address_cost
177 #undef TARGET_PROMOTE_FUNCTION_MODE
178 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
180 #undef TARGET_STRUCT_VALUE_RTX
181 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
182 #undef TARGET_SETUP_INCOMING_VARARGS
183 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
184 #undef TARGET_PASS_BY_REFERENCE
185 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
186 #undef TARGET_ARG_PARTIAL_BYTES
187 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
188 #undef TARGET_MD_ASM_CLOBBERS
189 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
190 #undef TARGET_DEFAULT_TARGET_FLAGS
191 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
192 #undef TARGET_HANDLE_OPTION
193 #define TARGET_HANDLE_OPTION cris_handle_option
194 #undef TARGET_FRAME_POINTER_REQUIRED
195 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
197 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
198 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
199 #undef TARGET_TRAMPOLINE_INIT
200 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
202 #undef TARGET_FUNCTION_VALUE
203 #define TARGET_FUNCTION_VALUE cris_function_value
204 #undef TARGET_LIBCALL_VALUE
205 #define TARGET_LIBCALL_VALUE cris_libcall_value
207 struct gcc_target targetm
= TARGET_INITIALIZER
;
209 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
212 cris_movem_load_rest_p (rtx op
, int offs
)
214 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
220 unsigned int regno
= 0;
222 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
223 other than (MEM reg). */
225 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
226 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
227 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
230 /* Check a possible post-inc indicator. */
231 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
233 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
234 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
240 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
241 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
242 || !CONST_INT_P (inc
)
243 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
253 regno
= reg_count
- 1;
256 elt
= XVECEXP (op
, 0, offs
);
257 src_addr
= XEXP (SET_SRC (elt
), 0);
259 if (GET_CODE (elt
) != SET
260 || !REG_P (SET_DEST (elt
))
261 || GET_MODE (SET_DEST (elt
)) != SImode
262 || REGNO (SET_DEST (elt
)) != regno
263 || !MEM_P (SET_SRC (elt
))
264 || GET_MODE (SET_SRC (elt
)) != SImode
265 || !memory_address_p (SImode
, src_addr
))
268 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
270 rtx elt
= XVECEXP (op
, 0, i
);
273 if (GET_CODE (elt
) != SET
274 || !REG_P (SET_DEST (elt
))
275 || GET_MODE (SET_DEST (elt
)) != SImode
276 || REGNO (SET_DEST (elt
)) != regno
277 || !MEM_P (SET_SRC (elt
))
278 || GET_MODE (SET_SRC (elt
)) != SImode
279 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
280 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
281 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
282 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
289 /* Worker function for predicate for the parallel contents in a movem
293 cris_store_multiple_op_p (rtx op
)
295 int reg_count
= XVECLEN (op
, 0);
306 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
307 other than (MEM reg) and (MEM (PLUS reg const)). */
311 elt
= XVECEXP (op
, 0, 0);
313 if (GET_CODE (elt
) != SET
)
316 dest
= SET_DEST (elt
);
318 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
321 dest_addr
= XEXP (dest
, 0);
323 /* Check a possible post-inc indicator. */
324 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
326 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
327 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
333 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
334 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
335 || !CONST_INT_P (inc
)
336 /* Support increment by number of registers, and by the offset
337 of the destination, if it has the form (MEM (PLUS reg
339 || !((REG_P (dest_addr
)
340 && REGNO (dest_addr
) == REGNO (reg
)
341 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
342 || (GET_CODE (dest_addr
) == PLUS
343 && REG_P (XEXP (dest_addr
, 0))
344 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
345 && CONST_INT_P (XEXP (dest_addr
, 1))
346 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
357 regno
= reg_count
- 1;
360 if (GET_CODE (elt
) != SET
361 || !REG_P (SET_SRC (elt
))
362 || GET_MODE (SET_SRC (elt
)) != SImode
363 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
364 || !MEM_P (SET_DEST (elt
))
365 || GET_MODE (SET_DEST (elt
)) != SImode
)
368 if (REG_P (dest_addr
))
370 dest_base
= dest_addr
;
373 else if (GET_CODE (dest_addr
) == PLUS
374 && REG_P (XEXP (dest_addr
, 0))
375 && CONST_INT_P (XEXP (dest_addr
, 1)))
377 dest_base
= XEXP (dest_addr
, 0);
378 offset
= INTVAL (XEXP (dest_addr
, 1));
383 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
385 rtx elt
= XVECEXP (op
, 0, i
);
388 if (GET_CODE (elt
) != SET
389 || !REG_P (SET_SRC (elt
))
390 || GET_MODE (SET_SRC (elt
)) != SImode
391 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
392 || !MEM_P (SET_DEST (elt
))
393 || GET_MODE (SET_DEST (elt
)) != SImode
394 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
395 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
396 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
397 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
404 /* The CONDITIONAL_REGISTER_USAGE worker. */
407 cris_conditional_register_usage (void)
409 /* FIXME: This isn't nice. We should be able to use that register for
410 something else if the PIC table isn't needed. */
412 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
413 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
415 /* Allow use of ACR (PC in pre-V32) and tweak order. */
418 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
421 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
424 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
426 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
429 if (TARGET_HAS_MUL_INSNS
)
430 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
432 /* On early versions, we must use the 16-bit condition-code register,
433 which has another name. */
434 if (cris_cpu_version
< 8)
435 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
438 /* Return crtl->uses_pic_offset_table. For use in cris.md,
439 since some generated files do not include function.h. */
442 cris_cfun_uses_pic_table (void)
444 return crtl
->uses_pic_offset_table
;
447 /* Given an rtx, return the text string corresponding to the CODE of X.
448 Intended for use in the assembly language output section of a
454 cris_output_insn_is_bound
= 0;
455 switch (GET_CODE (x
))
466 /* This function is for retrieving a part of an instruction name for
467 an operator, for immediate output. If that ever happens for
468 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
470 internal_error ("MULT case in cris_op_str");
506 /* Used to control the sign/zero-extend character for the 'E' modifier.
508 cris_output_insn_is_bound
= 1;
513 return "Unknown operator";
518 /* Emit an error message when we're in an asm, and a fatal error for
519 "normal" insns. Formatted output isn't easily implemented, since we
520 use output_operand_lossage to output the actual message and handle the
521 categorization of the error. */
524 cris_operand_lossage (const char *msgid
, rtx op
)
527 output_operand_lossage ("%s", msgid
);
530 /* Print an index part of an address to file. */
533 cris_print_index (rtx index
, FILE *file
)
535 /* Make the index "additive" unless we'll output a negative number, in
536 which case the sign character is free (as in free beer). */
537 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
541 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
542 else if (CONSTANT_P (index
))
543 cris_output_addr_const (file
, index
);
544 else if (GET_CODE (index
) == MULT
)
546 fprintf (file
, "$%s.",
547 reg_names
[REGNO (XEXP (index
, 0))]);
549 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
551 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
553 rtx inner
= XEXP (index
, 0);
554 rtx inner_inner
= XEXP (inner
, 0);
556 if (GET_CODE (inner_inner
) == POST_INC
)
558 fprintf (file
, "[$%s+].",
559 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
560 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
564 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
566 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
569 else if (MEM_P (index
))
571 rtx inner
= XEXP (index
, 0);
572 if (GET_CODE (inner
) == POST_INC
)
573 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
575 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
578 cris_operand_lossage ("unexpected index-type in cris_print_index",
582 /* Print a base rtx of an address to file. */
585 cris_print_base (rtx base
, FILE *file
)
588 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
589 else if (GET_CODE (base
) == POST_INC
)
591 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
592 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
595 cris_operand_lossage ("unexpected base-type in cris_print_base",
599 /* Usable as a guard in expressions. */
602 cris_fatal (char *arg
)
604 internal_error (arg
);
606 /* We'll never get here; this is just to appease compilers. */
610 /* Return nonzero if REGNO is an ordinary register that *needs* to be
611 saved together with other registers, possibly by a MOVEM instruction,
612 or is saved for target-independent reasons. There may be
613 target-dependent reasons to save the register anyway; this is just a
614 wrapper for a complicated conditional. */
617 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
620 (((df_regs_ever_live_p (regno
)
621 && !call_used_regs
[regno
])
622 || (regno
== PIC_OFFSET_TABLE_REGNUM
624 /* It is saved anyway, if there would be a gap. */
626 && df_regs_ever_live_p (regno
+ 1)
627 && !call_used_regs
[regno
+ 1]))))
628 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
629 && regno
!= CRIS_SRP_REGNUM
)
630 || (crtl
->calls_eh_return
631 && (regno
== EH_RETURN_DATA_REGNO (0)
632 || regno
== EH_RETURN_DATA_REGNO (1)
633 || regno
== EH_RETURN_DATA_REGNO (2)
634 || regno
== EH_RETURN_DATA_REGNO (3)));
637 /* Return nonzero if there are regs mentioned in the insn that are not all
638 in the call_used regs. This is part of the decision whether an insn
639 can be put in the epilogue. */
642 saved_regs_mentioned (rtx x
)
648 /* Mainly stolen from refers_to_regno_p in rtlanal.c. */
656 return !call_used_regs
[i
];
659 /* If this is a SUBREG of a hard reg, we can see exactly which
660 registers are being modified. Otherwise, handle normally. */
661 i
= REGNO (SUBREG_REG (x
));
662 return !call_used_regs
[i
];
668 fmt
= GET_RTX_FORMAT (code
);
669 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
673 if (saved_regs_mentioned (XEXP (x
, i
)))
676 else if (fmt
[i
] == 'E')
679 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
680 if (saved_regs_mentioned (XEXP (x
, i
)))
688 /* The PRINT_OPERAND worker. */
691 cris_print_operand (FILE *file
, rtx x
, int code
)
695 /* Size-strings corresponding to MULT expressions. */
696 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
698 /* New code entries should just be added to the switch below. If
699 handling is finished, just return. If handling was just a
700 modification of the operand, the modified operand should be put in
701 "operand", and then do a break to let default handling
702 (zero-modifier) output the operand. */
707 /* Print the unsigned supplied integer as if it were signed
708 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
710 || !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (x
), 'O'))
711 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
712 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
713 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
717 /* Print assembler code for operator. */
718 fprintf (file
, "%s", cris_op_str (operand
));
723 /* A movem modifier working on a parallel; output the register
727 if (GET_CODE (x
) != PARALLEL
)
728 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
730 /* The second item can be (set reg (plus reg const)) to denote a
733 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
735 : XVECLEN (x
, 0) - 1);
737 fprintf (file
, "$%s", reg_names
[regno
]);
743 /* A similar movem modifier; output the memory operand. */
746 if (GET_CODE (x
) != PARALLEL
)
747 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
749 /* The lowest mem operand is in the first item, but perhaps it
750 needs to be output as postincremented. */
751 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
752 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
753 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
755 /* The second item can be a (set reg (plus reg const)) to denote
757 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
759 /* It's a post-increment, if the address is a naked (reg). */
761 addr
= gen_rtx_POST_INC (SImode
, addr
);
764 /* Otherwise, it's a side-effect; RN=RN+M. */
765 fprintf (file
, "[$%s=$%s%s%d]",
766 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
767 reg_names
[REGNO (XEXP (addr
, 0))],
768 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
769 (int) INTVAL (XEXP (addr
, 1)));
773 output_address (addr
);
778 /* Adjust a power of two to its log2. */
779 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
780 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
781 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
785 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
786 respectively. This modifier also terminates the inhibiting
787 effects of the 'x' modifier. */
788 cris_output_insn_is_bound
= 0;
789 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
793 if (INTVAL (x
) <= 255)
795 else if (INTVAL (x
) <= 65535)
805 /* For a non-integer, print the size of the operand. */
806 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
807 ? 'd' : GET_MODE (x
) == HImode
? 'w'
808 : GET_MODE (x
) == QImode
? 'b'
809 /* If none of the above, emit an erroneous size letter. */
815 /* Const_int: print b for -127 <= x <= 255,
816 w for -32768 <= x <= 65535, else die. */
818 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
819 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
820 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
824 /* If this is a GOT-symbol, print the size-letter corresponding to
825 -fpic/-fPIC. For everything else, print "d". */
827 && GET_CODE (x
) == CONST
828 && GET_CODE (XEXP (x
, 0)) == UNSPEC
829 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
834 /* Output a 'nop' if there's nothing for the delay slot.
835 This method stolen from the sparc files. */
836 if (dbr_sequence_length () == 0)
837 fputs ("\n\tnop", file
);
841 /* Output directive for alignment padded with "nop" insns.
842 Optimizing for size, it's plain 4-byte alignment, otherwise we
843 align the section to a cache-line (32 bytes) and skip at max 2
844 bytes, i.e. we skip if it's the last insn on a cache-line. The
845 latter is faster by a small amount (for two test-programs 99.6%
846 and 99.9%) and larger by a small amount (ditto 100.1% and
847 100.2%). This is supposed to be the simplest yet performance-
848 wise least intrusive way to make sure the immediately following
849 (supposed) muls/mulu insn isn't located at the end of a
853 ? ".p2alignw 2,0x050f\n\t"
854 : ".p2alignw 5,0x050f,2\n\t", file
);
858 /* The PIC register. */
860 internal_error ("invalid use of ':' modifier");
861 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
865 /* Print high (most significant) part of something. */
866 switch (GET_CODE (operand
))
869 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
870 value is kept here, and so may be other than 0 or -1. */
871 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
872 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
876 /* High part of a long long constant. */
877 if (GET_MODE (operand
) == VOIDmode
)
879 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
883 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
886 /* Print reg + 1. Check that there's not an attempt to print
887 high-parts of registers like stack-pointer or higher, except
888 for SRP (where the "high part" is MOF). */
889 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
890 && (REGNO (operand
) != CRIS_SRP_REGNUM
891 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
892 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
893 LOSE_AND_RETURN ("bad register", operand
);
894 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
898 /* Adjust memory address to high part. */
900 rtx adj_mem
= operand
;
902 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
904 /* Adjust so we can use two SImode in DImode.
905 Calling adj_offsettable_operand will make sure it is an
906 offsettable address. Don't do this for a postincrement
907 though; it should remain as it was. */
908 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
910 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
912 output_address (XEXP (adj_mem
, 0));
917 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
921 /* Strip the MEM expression. */
922 operand
= XEXP (operand
, 0);
926 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
927 iterators and attributes in cris.md to avoid the need for %x
928 and %E (and %e) and state passed between those modifiers. */
929 cris_output_insn_is_bound
= 0;
932 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
933 cris_output_insn_is_bound is nonzero. */
934 if (GET_CODE (operand
) != SIGN_EXTEND
935 && GET_CODE (operand
) != ZERO_EXTEND
936 && !CONST_INT_P (operand
))
937 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
939 if (cris_output_insn_is_bound
)
941 cris_output_insn_is_bound
= 0;
945 putc (GET_CODE (operand
) == SIGN_EXTEND
946 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
951 /* Print the size letter of the inner element. We can do it by
952 calling ourselves with the 's' modifier. */
953 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
954 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
955 cris_print_operand (file
, XEXP (operand
, 0), 's');
959 /* Print the least significant part of operand. */
960 if (GET_CODE (operand
) == CONST_DOUBLE
)
962 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
965 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
967 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
968 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
971 /* Otherwise the least significant part equals the normal part,
972 so handle it normally. */
976 /* When emitting an add for the high part of a DImode constant, we
977 want to use addq for 0 and adds.w for -1. */
978 if (!CONST_INT_P (operand
))
979 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
980 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
984 /* If this is a GOT symbol, force it to be emitted as :GOT and
985 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
986 Avoid making this too much of a special case. */
987 if (flag_pic
== 1 && CONSTANT_P (operand
))
989 int flag_pic_save
= flag_pic
;
992 cris_output_addr_const (file
, operand
);
993 flag_pic
= flag_pic_save
;
999 /* When emitting an sub for the high part of a DImode constant, we
1000 want to use subq for 0 and subs.w for -1. */
1001 if (!CONST_INT_P (operand
))
1002 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1003 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1007 /* Print the operand as the index-part of an address.
1008 Easiest way out is to use cris_print_index. */
1009 cris_print_index (operand
, file
);
1013 /* Print the size letter for an operand to a MULT, which must be a
1014 const_int with a suitable value. */
1015 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1016 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1017 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1021 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1023 && GET_CODE (operand
) == CONST
1024 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1025 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1026 fprintf (file
, "u.w");
1028 fprintf (file
, ".d");
1032 /* No code, print as usual. */
1036 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1039 /* Print an operand as without a modifier letter. */
1040 switch (GET_CODE (operand
))
1043 if (REGNO (operand
) > 15
1044 && REGNO (operand
) != CRIS_MOF_REGNUM
1045 && REGNO (operand
) != CRIS_SRP_REGNUM
1046 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1047 internal_error ("internal error: bad register: %d", REGNO (operand
));
1048 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1052 output_address (XEXP (operand
, 0));
1056 if (GET_MODE (operand
) == VOIDmode
)
1057 /* A long long constant. */
1058 output_addr_const (file
, operand
);
1061 /* Only single precision is allowed as plain operands the
1062 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1067 /* FIXME: Perhaps check overflow of the "single". */
1068 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1069 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1071 fprintf (file
, "0x%lx", l
);
1078 cris_output_addr_const (file
, operand
);
1084 /* For a (MULT (reg X) const_int) we output "rX.S". */
1085 int i
= CONST_INT_P (XEXP (operand
, 1))
1086 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1087 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1088 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1091 || (!CONST_INT_P (XEXP (operand
, 0))
1092 && !CONST_INT_P (XEXP (operand
, 1))))
1093 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1095 cris_print_base (reg
, file
);
1096 fprintf (file
, ".%c",
1097 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1099 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1105 /* No need to handle all strange variants, let output_addr_const
1107 if (CONSTANT_P (operand
))
1109 cris_output_addr_const (file
, operand
);
1113 LOSE_AND_RETURN ("unexpected operand", x
);
1117 /* The PRINT_OPERAND_ADDRESS worker. */
1120 cris_print_operand_address (FILE *file
, rtx x
)
1122 /* All these were inside MEM:s so output indirection characters. */
1125 if (CONSTANT_ADDRESS_P (x
))
1126 cris_output_addr_const (file
, x
);
1127 else if (BASE_OR_AUTOINCR_P (x
))
1128 cris_print_base (x
, file
);
1129 else if (GET_CODE (x
) == PLUS
)
1137 cris_print_base (x1
, file
);
1138 cris_print_index (x2
, file
);
1140 else if (BASE_P (x2
))
1142 cris_print_base (x2
, file
);
1143 cris_print_index (x1
, file
);
1146 LOSE_AND_RETURN ("unrecognized address", x
);
1150 /* A DIP. Output more indirection characters. */
1152 cris_print_base (XEXP (x
, 0), file
);
1156 LOSE_AND_RETURN ("unrecognized address", x
);
1161 /* The RETURN_ADDR_RTX worker.
1162 We mark that the return address is used, either by EH or
1163 __builtin_return_address, for use by the function prologue and
1164 epilogue. FIXME: This isn't optimal; we just use the mark in the
1165 prologue and epilogue to say that the return address is to be stored
1166 in the stack frame. We could return SRP for leaf-functions and use the
1167 initial-value machinery. */
1170 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1172 cfun
->machine
->needs_return_address_on_stack
= 1;
1174 /* The return-address is stored just above the saved frame-pointer (if
1175 present). Apparently we can't eliminate from the frame-pointer in
1176 that direction, so use the incoming args (maybe pretended) pointer. */
1178 ? gen_rtx_MEM (Pmode
, plus_constant (virtual_incoming_args_rtx
, -4))
1182 /* Accessor used in cris.md:return because cfun->machine isn't available
1186 cris_return_address_on_stack (void)
1188 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1189 || cfun
->machine
->needs_return_address_on_stack
;
1192 /* Accessor used in cris.md:return because cfun->machine isn't available
1196 cris_return_address_on_stack_for_return (void)
1198 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1199 : cris_return_address_on_stack ();
1202 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1203 handles FP -> SP elimination offset. */
1206 cris_initial_frame_pointer_offset (void)
1210 /* Initial offset is 0 if we don't have a frame pointer. */
1212 bool got_really_used
= false;
1214 if (crtl
->uses_pic_offset_table
)
1216 push_topmost_sequence ();
1218 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1220 pop_topmost_sequence ();
1223 /* And 4 for each register pushed. */
1224 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1225 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1228 /* And then, last, we add the locals allocated. */
1229 offs
+= get_frame_size ();
1231 /* And more; the accumulated args size. */
1232 offs
+= crtl
->outgoing_args_size
;
1234 /* Then round it off, in case we use aligned stack. */
1235 if (TARGET_STACK_ALIGN
)
1236 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1241 /* The INITIAL_ELIMINATION_OFFSET worker.
1242 Calculate the difference between imaginary registers such as frame
1243 pointer and the stack pointer. Used to eliminate the frame pointer
1244 and imaginary arg pointer. */
1247 cris_initial_elimination_offset (int fromreg
, int toreg
)
1250 = cris_initial_frame_pointer_offset ();
1252 /* We should be able to use regs_ever_live and related prologue
1253 information here, or alpha should not as well. */
1254 bool return_address_on_stack
= cris_return_address_on_stack ();
1256 /* Here we act as if the frame-pointer were needed. */
1257 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1259 if (fromreg
== ARG_POINTER_REGNUM
1260 && toreg
== FRAME_POINTER_REGNUM
)
1261 return ap_fp_offset
;
1263 /* Between the frame pointer and the stack are only "normal" stack
1264 variables and saved registers. */
1265 if (fromreg
== FRAME_POINTER_REGNUM
1266 && toreg
== STACK_POINTER_REGNUM
)
1267 return fp_sp_offset
;
1269 /* We need to balance out the frame pointer here. */
1270 if (fromreg
== ARG_POINTER_REGNUM
1271 && toreg
== STACK_POINTER_REGNUM
)
1272 return ap_fp_offset
+ fp_sp_offset
- 4;
1277 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1280 cris_reload_address_legitimized (rtx x
,
1281 enum machine_mode mode ATTRIBUTE_UNUSED
,
1282 int opnum ATTRIBUTE_UNUSED
,
1284 int ind_levels ATTRIBUTE_UNUSED
)
1286 enum reload_type type
= itype
;
1291 if (GET_CODE (x
) != PLUS
)
1298 op0p
= &XEXP (x
, 0);
1300 op1p
= &XEXP (x
, 1);
1305 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1307 rtx op00
= XEXP (op0
, 0);
1308 rtx op000
= XEXP (op00
, 0);
1309 rtx
*op000p
= &XEXP (op00
, 0);
1311 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1313 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1315 bool something_reloaded
= false;
1317 if (GET_CODE (op000
) == POST_INC
1318 && REG_P (XEXP (op000
, 0))
1319 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1320 /* No, this gets too complicated and is too rare to care
1321 about trying to improve on the general code Here.
1322 As the return-value is an all-or-nothing indicator, we
1323 punt on the other register too. */
1327 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1329 /* The address of the inner mem is a pseudo or wrong
1330 reg: reload that. */
1331 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1332 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1333 something_reloaded
= true;
1336 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1338 /* Base register is a pseudo or wrong reg: reload it. */
1339 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1340 GET_MODE (x
), VOIDmode
, 0, 0,
1342 something_reloaded
= true;
1345 gcc_assert (something_reloaded
);
1354 /* Worker function for REGISTER_MOVE_COST. */
1357 cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1358 enum reg_class from
, enum reg_class to
)
1362 /* Pretend that classes that we don't support are ALL_REGS, so
1363 we give them the highest cost. */
1364 if (from
!= SPECIAL_REGS
&& from
!= MOF_REGS
1365 && from
!= GENERAL_REGS
&& from
!= GENNONACR_REGS
)
1368 if (to
!= SPECIAL_REGS
&& to
!= MOF_REGS
1369 && to
!= GENERAL_REGS
&& to
!= GENNONACR_REGS
)
1373 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1374 their move cost within that class is higher. How about 7? That's 3
1375 for a move to a GENERAL_REGS register, 3 for the move from the
1376 GENERAL_REGS register, and 1 for the increased register pressure.
1377 Also, it's higher than the memory move cost, which is in order.
1378 We also do this for ALL_REGS, since we don't want that class to be
1379 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1380 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1381 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1382 used when a GENERAL_REGS should be used, even if there are call-saved
1383 GENERAL_REGS left to allocate. This is because the fall-back when
1384 the most preferred register class isn't available, isn't the next
1385 (or next good) wider register class, but the *most widest* register
1388 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1389 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1390 || from
== ALL_REGS
|| to
== ALL_REGS
)
1393 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1394 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1400 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1401 FIXME: this code is historical; its functionality should be
1402 refactored to look at insn attributes and moved to
1403 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1406 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1408 /* "Normal" means, for:
1413 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1414 register or (v32 and (...) is -32..-1), then CC does not change.
1415 CC_NO_OVERFLOW unless (...) is reg or mem.
1424 (set (reg1) (mem (bdap/biap)))
1425 (set (reg2) (bdap/biap))):
1426 CC is (reg1) and (mem (reg2))
1429 (set (mem (bdap/biap)) (reg1)) [or 0]
1430 (set (reg2) (bdap/biap))):
1433 (where reg and mem includes strict_low_parts variants thereof)
1435 For all others, assume CC is clobbered.
1436 Note that we do not have to care about setting CC_NO_OVERFLOW,
1437 since the overflow flag is set to 0 (i.e. right) for
1438 instructions where it does not have any sane sense, but where
1439 other flags have meanings. (This includes shifts; the carry is
1442 Note that there are other parallel constructs we could match,
1443 but we don't do that yet. */
1445 if (GET_CODE (exp
) == SET
)
1447 /* FIXME: Check when this happens. It looks like we should
1448 actually do a CC_STATUS_INIT here to be safe. */
1449 if (SET_DEST (exp
) == pc_rtx
)
1452 /* Record CC0 changes, so we do not have to output multiple
1454 if (SET_DEST (exp
) == cc0_rtx
)
1458 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1459 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1460 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1462 cc_status
.value1
= SET_SRC (exp
);
1464 /* Handle flags for the special btstq on one bit. */
1465 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1466 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1468 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1470 cc_status
.flags
= CC_INVERTED
;
1472 /* A one-bit btstq. */
1473 cc_status
.flags
= CC_Z_IN_NOT_N
;
1476 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1478 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1479 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1480 /* For some reason gcc will not canonicalize compare
1481 operations, reversing the sign by itself if
1482 operands are in wrong order. */
1483 /* (But NOT inverted; eq is still eq.) */
1484 cc_status
.flags
= CC_REVERSED
;
1486 /* This seems to be overlooked by gcc. FIXME: Check again.
1487 FIXME: Is it really safe? */
1489 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1490 XEXP (SET_SRC (exp
), 0),
1491 XEXP (SET_SRC (exp
), 1));
1495 else if (REG_P (SET_DEST (exp
))
1496 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1497 && REG_P (XEXP (SET_DEST (exp
), 0))))
1499 /* A register is set; normally CC is set to show that no
1500 test insn is needed. Catch the exceptions. */
1502 /* If not to cc0, then no "set"s in non-natural mode give
1504 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1505 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1507 /* ... except add:s and sub:s in DImode. */
1508 if (GET_MODE (SET_DEST (exp
)) == DImode
1509 && (GET_CODE (SET_SRC (exp
)) == PLUS
1510 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1513 cc_status
.value1
= SET_DEST (exp
);
1514 cc_status
.value2
= SET_SRC (exp
);
1516 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1518 cc_status
.value2
= 0;
1520 /* Add and sub may set V, which gets us
1521 unoptimizable results in "gt" and "le" condition
1523 cc_status
.flags
|= CC_NO_OVERFLOW
;
1528 else if (SET_SRC (exp
) == const0_rtx
1529 || (REG_P (SET_SRC (exp
))
1530 && (REGNO (SET_SRC (exp
))
1531 > CRIS_LAST_GENERAL_REGISTER
))
1533 && GET_CODE (SET_SRC (exp
)) == CONST_INT
1534 && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (SET_SRC (exp
)),
1537 /* There's no CC0 change for this case. Just check
1539 if (cc_status
.value1
1540 && modified_in_p (cc_status
.value1
, insn
))
1541 cc_status
.value1
= 0;
1543 if (cc_status
.value2
1544 && modified_in_p (cc_status
.value2
, insn
))
1545 cc_status
.value2
= 0;
1552 cc_status
.value1
= SET_DEST (exp
);
1553 cc_status
.value2
= SET_SRC (exp
);
1555 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1557 cc_status
.value2
= 0;
1559 /* Some operations may set V, which gets us
1560 unoptimizable results in "gt" and "le" condition
1562 if (GET_CODE (SET_SRC (exp
)) == PLUS
1563 || GET_CODE (SET_SRC (exp
)) == MINUS
1564 || GET_CODE (SET_SRC (exp
)) == NEG
)
1565 cc_status
.flags
|= CC_NO_OVERFLOW
;
1567 /* For V32, nothing with a register destination sets
1568 C and V usefully. */
1570 cc_status
.flags
|= CC_NO_OVERFLOW
;
1575 else if (MEM_P (SET_DEST (exp
))
1576 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1577 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1579 /* When SET to MEM, then CC is not changed (except for
1581 if (cc_status
.value1
1582 && modified_in_p (cc_status
.value1
, insn
))
1583 cc_status
.value1
= 0;
1585 if (cc_status
.value2
1586 && modified_in_p (cc_status
.value2
, insn
))
1587 cc_status
.value2
= 0;
1592 else if (GET_CODE (exp
) == PARALLEL
)
1594 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1595 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1596 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1598 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1599 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1603 /* For "move.S [rx=ry+o],rz", say CC reflects
1604 value1=rz and value2=[rx] */
1605 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1607 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1608 XEXP (XVECEXP (exp
, 0, 1), 0));
1610 /* Huh? A side-effect cannot change the destination
1612 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1614 internal_error ("internal error: sideeffect-insn affecting main effect");
1616 /* For V32, moves to registers don't set C and V. */
1618 cc_status
.flags
|= CC_NO_OVERFLOW
;
1621 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1622 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1623 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1625 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1626 say flags are not changed, except for overlap. */
1627 if (cc_status
.value1
1628 && modified_in_p (cc_status
.value1
, insn
))
1629 cc_status
.value1
= 0;
1631 if (cc_status
.value2
1632 && modified_in_p (cc_status
.value2
, insn
))
1633 cc_status
.value2
= 0;
1640 /* If we got here, the case wasn't covered by the code above. */
1644 /* This function looks into the pattern to see how this insn affects
1647 Used when to eliminate test insns before a condition-code user,
1648 such as a "scc" insn or a conditional branch. This includes
1649 checking if the entities that cc was updated by, are changed by the
1652 Currently a jumble of the old peek-inside-the-insn and the newer
1653 check-cc-attribute methods. */
1656 cris_notice_update_cc (rtx exp
, rtx insn
)
1658 enum attr_cc attrval
= get_attr_cc (insn
);
1660 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1661 to still set CC_REVERSED as below, since that's required by some
1662 compare insn alternatives. (FIXME: GCC should do this virtual
1663 operand swap by itself.) A test-case that may otherwise fail is
1664 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1669 if (attrval
== CC_REV
)
1670 cc_status
.flags
= CC_REVERSED
;
1674 /* Slowly, we're converting to using attributes to control the setting
1675 of condition-code status. */
1679 /* Even if it is "none", a setting may clobber a previous
1680 cc-value, so check. */
1681 if (GET_CODE (exp
) == SET
)
1683 if (cc_status
.value1
1684 && modified_in_p (cc_status
.value1
, insn
))
1685 cc_status
.value1
= 0;
1687 if (cc_status
.value2
1688 && modified_in_p (cc_status
.value2
, insn
))
1689 cc_status
.value2
= 0;
1700 cris_normal_notice_update_cc (exp
, insn
);
1702 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1703 can change bge => bpl and blt => bmi by passing on to the cc0
1704 user that V should not be considered; bgt and ble are taken
1705 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1706 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1707 cc_status
.flags
|= CC_NO_OVERFLOW
;
1711 internal_error ("unknown cc_attr value");
1717 /* Return != 0 if the return sequence for the current function is short,
1718 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1719 registers must be saved, so return 0 then. */
1722 cris_simple_epilogue (void)
1725 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1726 bool got_really_used
= false;
1728 if (! reload_completed
1729 || frame_pointer_needed
1730 || get_frame_size () != 0
1731 || crtl
->args
.pretend_args_size
1733 || crtl
->outgoing_args_size
1734 || crtl
->calls_eh_return
1736 /* If we're not supposed to emit prologue and epilogue, we must
1737 not emit return-type instructions. */
1738 || !TARGET_PROLOGUE_EPILOGUE
)
1741 /* Can't return from stacked return address with v32. */
1742 if (TARGET_V32
&& cris_return_address_on_stack ())
1745 if (crtl
->uses_pic_offset_table
)
1747 push_topmost_sequence ();
1749 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
1750 pop_topmost_sequence ();
1753 /* No simple epilogue if there are saved registers. */
1754 for (regno
= 0; regno
< reglimit
; regno
++)
1755 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1761 /* Expand a return insn (just one insn) marked as using SRP or stack
1762 slot depending on parameter ON_STACK. */
1765 cris_expand_return (bool on_stack
)
1767 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1768 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1769 GCC expect just (return) to do the right thing when optimizing, so
1770 we do that until they're fixed. Currently, all return insns in a
1771 function must be the same (not really a limiting factor) so we need
1772 to check that it doesn't change half-way through. */
1773 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
1775 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
1776 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
1778 cfun
->machine
->return_type
1779 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
1782 /* Compute a (partial) cost for rtx X. Return true if the complete
1783 cost has been computed, and false if subexpressions should be
1784 scanned. In either case, *TOTAL contains the cost result. */
1787 cris_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
1794 HOST_WIDE_INT val
= INTVAL (x
);
1797 else if (val
< 32 && val
>= -32)
1799 /* Eight or 16 bits are a word and cycle more expensive. */
1800 else if (val
<= 32767 && val
>= -32768)
1802 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
1803 another word. FIXME: This isn't linear to 16 bits. */
1819 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
1822 /* Make 0.0 cheap, else test-insns will not be used. */
1827 /* If we have one arm of an ADDI, make sure it gets the cost of
1828 one insn, i.e. zero cost for this operand, and just the cost
1829 of the PLUS, as the insn is created by combine from a PLUS
1830 and an ASHIFT, and the MULT cost below would make the
1831 combined value be larger than the separate insns. The insn
1832 validity is checked elsewhere by combine.
1834 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
1835 function should be rewritten. */
1836 if (outer_code
== PLUS
&& BIAP_INDEX_P (x
))
1842 /* Identify values that are no powers of two. Powers of 2 are
1843 taken care of already and those values should not be changed. */
1844 if (!CONST_INT_P (XEXP (x
, 1))
1845 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1847 /* If we have a multiply insn, then the cost is between
1848 1 and 2 "fast" instructions. */
1849 if (TARGET_HAS_MUL_INSNS
)
1851 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1855 /* Estimate as 4 + 4 * #ofbits. */
1856 *total
= COSTS_N_INSNS (132);
1865 if (!CONST_INT_P (XEXP (x
, 1))
1866 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1868 /* Estimate this as 4 + 8 * #of bits. */
1869 *total
= COSTS_N_INSNS (260);
1875 if (CONST_INT_P (XEXP (x
, 1))
1876 /* Two constants may actually happen before optimization. */
1877 && !CONST_INT_P (XEXP (x
, 0))
1878 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x
, 1)), 'I'))
1880 *total
= (rtx_cost (XEXP (x
, 0), outer_code
, speed
) + 2
1881 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
1887 if (outer_code
!= COMPARE
)
1891 case ZERO_EXTEND
: case SIGN_EXTEND
:
1892 *total
= rtx_cost (XEXP (x
, 0), outer_code
, speed
);
1900 /* The ADDRESS_COST worker. */
1903 cris_address_cost (rtx x
, bool speed ATTRIBUTE_UNUSED
)
1905 /* The metric to use for the cost-macros is unclear.
1906 The metric used here is (the number of cycles needed) / 2,
1907 where we consider equal a cycle for a word of code and a cycle to
1908 read memory. FIXME: Adding "+ 1" to all values would avoid
1909 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
1910 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
1911 Unfortunately(?) such a hack would expose other pessimizations,
1912 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
1913 loop there, without apparent reason. */
1915 /* The cheapest addressing modes get 0, since nothing extra is needed. */
1916 if (BASE_OR_AUTOINCR_P (x
))
1919 /* An indirect mem must be a DIP. This means two bytes extra for code,
1920 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
1924 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1925 an extra DIP prefix and 4 bytes of constant in most cases. */
1929 /* Handle BIAP and BDAP prefixes. */
1930 if (GET_CODE (x
) == PLUS
)
1932 rtx tem1
= XEXP (x
, 0);
1933 rtx tem2
= XEXP (x
, 1);
1935 /* Local extended canonicalization rule: the first operand must
1936 be REG, unless it's an operation (MULT). */
1937 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
1938 tem1
= tem2
, tem2
= XEXP (x
, 0);
1940 /* We'll "assume" we have canonical RTX now. */
1941 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
1943 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
1944 recognize the typical MULT which is always in tem1 because of
1945 insn canonicalization. */
1946 if ((GET_CODE (tem1
) == MULT
&& BIAP_INDEX_P (tem1
))
1950 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
1951 PLUS is always found in tem2. */
1952 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
1955 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1957 if (CONST_INT_P (tem2
)
1958 && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (tem2
), 'L'))
1961 /* A BDAP with some other constant is 2 bytes extra. */
1962 if (CONSTANT_P (tem2
))
1963 return (2 + 2 + 2) / 2;
1965 /* BDAP with something indirect should have a higher cost than
1966 BIAP with register. FIXME: Should it cost like a MEM or more? */
1967 return (2 + 2 + 2) / 2;
1970 /* What else? Return a high cost. It matters only for valid
1971 addressing modes. */
1975 /* Check various objections to the side-effect. Used in the test-part
1976 of an anonymous insn describing an insn with a possible side-effect.
1977 Returns nonzero if the implied side-effect is ok.
1980 ops : An array of rtx:es. lreg, rreg, rval,
1981 The variables multop and other_op are indexes into this,
1982 or -1 if they are not applicable.
1983 lreg : The register that gets assigned in the side-effect.
1984 rreg : One register in the side-effect expression
1985 rval : The other register, or an int.
1986 multop : An integer to multiply rval with.
1987 other_op : One of the entities of the main effect,
1988 whose mode we must consider. */
1991 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
1992 int lreg
, int rreg
, int rval
,
1993 int multop
, int other_op
)
1995 /* Find what value to multiply with, for rx =ry + rz * n. */
1996 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
1998 rtx reg_rtx
= ops
[rreg
];
1999 rtx val_rtx
= ops
[rval
];
2001 /* The operands may be swapped. Canonicalize them in reg_rtx and
2002 val_rtx, where reg_rtx always is a reg (for this constraint to
2004 if (! BASE_P (reg_rtx
))
2005 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2007 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2008 we have no business. */
2009 if (! BASE_P (reg_rtx
))
2012 /* Don't do this when -mno-split. */
2013 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2016 /* The mult expression may be hidden in lreg. FIXME: Add more
2017 commentary about that. */
2018 if (GET_CODE (val_rtx
) == MULT
)
2020 mult
= INTVAL (XEXP (val_rtx
, 1));
2021 val_rtx
= XEXP (val_rtx
, 0);
2025 /* First check the "other operand". */
2028 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2031 /* Check if the lvalue register is the same as the "other
2032 operand". If so, the result is undefined and we shouldn't do
2033 this. FIXME: Check again. */
2034 if ((BASE_P (ops
[lreg
])
2035 && BASE_P (ops
[other_op
])
2036 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2037 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2041 /* Do not accept frame_pointer_rtx as any operand. */
2042 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2043 || ops
[rval
] == frame_pointer_rtx
2044 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2048 && ! BASE_P (val_rtx
))
2051 /* Do not allow rx = rx + n if a normal add or sub with same size
2053 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2054 && CONST_INT_P (val_rtx
)
2055 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2058 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2059 if (CONSTANT_P (val_rtx
))
2062 if (MEM_P (val_rtx
) && BASE_OR_AUTOINCR_P (XEXP (val_rtx
, 0)))
2065 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2066 && MEM_P (XEXP (val_rtx
, 0))
2067 && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx
, 0), 0)))
2070 /* If we got here, it's not a valid addressing mode. */
2073 else if (code
== MULT
2074 || (code
== PLUS
&& BASE_P (val_rtx
)))
2076 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2077 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2078 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2081 /* Do not allow bad multiply-values. */
2082 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2085 /* Only allow r + ... */
2086 if (! BASE_P (reg_rtx
))
2089 /* If we got here, all seems ok.
2090 (All checks need to be done above). */
2094 /* If we get here, the caller got its initial tests wrong. */
2095 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2098 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2099 insn for other reasons. */
2102 cris_cc0_user_requires_cmp (rtx insn
)
2104 rtx cc0_user
= NULL
;
2108 gcc_assert (insn
!= NULL
);
2113 cc0_user
= next_cc0_user (insn
);
2114 if (cc0_user
== NULL
)
2117 body
= PATTERN (cc0_user
);
2118 set
= single_set (cc0_user
);
2120 /* Users can be sCC and bCC. */
2121 if (JUMP_P (cc0_user
)
2122 && GET_CODE (body
) == SET
2123 && SET_DEST (body
) == pc_rtx
2124 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2125 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2128 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2129 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2134 GET_CODE (SET_SRC (body
)) == GT
2135 || GET_CODE (SET_SRC (body
)) == LE
;
2141 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2142 does not handle the case where the IN operand is strict_low_part; it
2143 does handle it for X. Test-case in Axis-20010516. This function takes
2144 care of that for THIS port. FIXME: strict_low_part is going away
2148 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2150 /* The function reg_overlap_mentioned now handles when X is
2151 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2152 if (GET_CODE (in
) == STRICT_LOW_PART
)
2155 return reg_overlap_mentioned_p (x
, in
);
2158 /* The TARGET_ASM_NAMED_SECTION worker.
2159 We just dispatch to the functions for ELF and a.out. */
2162 cris_target_asm_named_section (const char *name
, unsigned int flags
,
2166 default_no_named_section (name
, flags
, decl
);
2168 default_elf_asm_named_section (name
, flags
, decl
);
2171 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2172 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2176 cris_valid_pic_const (rtx x
, bool any_operand
)
2178 gcc_assert (flag_pic
);
2180 switch (GET_CODE (x
))
2189 if (GET_CODE (x
) != CONST
)
2194 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2195 if (GET_CODE (x
) == PLUS
2196 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2197 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2198 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2199 && CONST_INT_P (XEXP (x
, 1)))
2202 if (GET_CODE (x
) == UNSPEC
)
2203 switch (XINT (x
, 1))
2205 /* A PCREL operand is only valid for call and movsi. */
2206 case CRIS_UNSPEC_PLT_PCREL
:
2207 case CRIS_UNSPEC_PCREL
:
2208 return !any_operand
;
2210 case CRIS_UNSPEC_PLT_GOTREL
:
2211 case CRIS_UNSPEC_PLTGOTREAD
:
2212 case CRIS_UNSPEC_GOTREAD
:
2213 case CRIS_UNSPEC_GOTREL
:
2219 return cris_pic_symbol_type_of (x
) == cris_no_symbol
;
2222 /* Helper function to find the right PIC-type symbol to generate,
2223 given the original (non-PIC) representation. */
2225 enum cris_pic_symbol_type
2226 cris_pic_symbol_type_of (rtx x
)
2228 switch (GET_CODE (x
))
2231 return SYMBOL_REF_LOCAL_P (x
)
2232 ? cris_rel_symbol
: cris_got_symbol
;
2235 return cris_rel_symbol
;
2238 return cris_pic_symbol_type_of (XEXP (x
, 0));
2243 enum cris_pic_symbol_type t1
= cris_pic_symbol_type_of (XEXP (x
, 0));
2244 enum cris_pic_symbol_type t2
= cris_pic_symbol_type_of (XEXP (x
, 1));
2246 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2248 if (t1
== cris_got_symbol
|| t1
== cris_got_symbol
)
2249 return cris_got_symbol_needing_fixup
;
2251 return t1
!= cris_no_symbol
? t1
: t2
;
2256 return cris_no_symbol
;
2259 /* Likely an offsettability-test attempting to add a constant to
2260 a GOTREAD symbol, which can't be handled. */
2261 return cris_invalid_pic_symbol
;
2264 fatal_insn ("unrecognized supposed constant", x
);
2270 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2273 cris_legitimate_pic_operand (rtx x
)
2275 /* Symbols are not valid PIC operands as-is; just constants. */
2276 return cris_valid_pic_const (x
, true);
2279 /* The ASM_OUTPUT_CASE_END worker. */
2282 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2286 rtx whole_jump_insn
= PATTERN (PREV_INSN (PREV_INSN (table
)));
2288 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2291 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2292 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2294 asm_fprintf (stream
,
2295 "\t.word %LL%d-.%s\n",
2296 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2297 (parallel_jump
, 0, 0),
2299 (TARGET_PDEBUG
? "; default" : ""));
2303 asm_fprintf (stream
,
2304 "\t.word %LL%d-%LL%d%s\n",
2305 CODE_LABEL_NUMBER (XEXP
2311 (PREV_INSN (table
))), 0, 0), 1),
2314 (TARGET_PDEBUG
? "; default" : ""));
2317 /* TARGET_HANDLE_OPTION worker. We just store the values into local
2318 variables here. Checks for correct semantics are in
2319 cris_override_options. */
2322 cris_handle_option (size_t code
, const char *arg ATTRIBUTE_UNUSED
,
2323 int value ATTRIBUTE_UNUSED
)
2331 + MASK_ALIGN_BY_32
);
2334 case OPT_mno_etrax100
:
2338 + MASK_ALIGN_BY_32
);
2344 |= (MASK_STACK_ALIGN
2347 + MASK_ALIGN_BY_32
);
2353 |= (MASK_STACK_ALIGN
2361 &= ~(MASK_STACK_ALIGN
2370 CRIS_SUBTARGET_HANDLE_OPTION(code
, arg
, value
);
2375 /* The OVERRIDE_OPTIONS worker.
2376 As is the norm, this also parses -mfoo=bar type parameters. */
2379 cris_override_options (void)
2381 if (cris_max_stackframe_str
)
2383 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2385 /* Do some sanity checking. */
2386 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2387 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2388 cris_max_stackframe
, 0x20000000);
2391 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2392 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2393 cris_cpu_version
= CRIS_CPU_SVINTO
;
2394 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2395 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2397 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2401 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2403 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2404 cris_cpu_version
= 3;
2406 if (strcmp ("svinto", cris_cpu_str
) == 0
2407 || strcmp ("etrax100", cris_cpu_str
) == 0)
2408 cris_cpu_version
= 8;
2410 if (strcmp ("ng", cris_cpu_str
) == 0
2411 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2412 cris_cpu_version
= 10;
2414 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2415 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2418 /* Set the target flags. */
2419 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2420 target_flags
|= MASK_ETRAX4_ADD
;
2422 /* If this is Svinto or higher, align for 32 bit accesses. */
2423 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2425 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2426 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2429 /* Note that we do not add new flags when it can be completely
2430 described with a macro that uses -mcpu=X. So
2431 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2437 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2439 if (strcmp ("etrax4", cris_tune_str
) == 0)
2442 if (strcmp ("svinto", cris_tune_str
) == 0
2443 || strcmp ("etrax100", cris_tune_str
) == 0)
2446 if (strcmp ("ng", cris_tune_str
) == 0
2447 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2450 if (cris_tune
< 0 || cris_tune
> 32)
2451 error ("unknown CRIS cpu version specification in -mtune= : %s",
2454 if (cris_tune
>= CRIS_CPU_SVINTO
)
2455 /* We have currently nothing more to tune than alignment for
2458 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2459 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2462 if (cris_cpu_version
>= CRIS_CPU_V32
)
2463 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2467 /* Use error rather than warning, so invalid use is easily
2468 detectable. Still change to the values we expect, to avoid
2472 error ("-fPIC and -fpic are not supported in this configuration");
2476 /* Turn off function CSE. We need to have the addresses reach the
2477 call expanders to get PLT-marked, as they could otherwise be
2478 compared against zero directly or indirectly. After visiting the
2479 call expanders they will then be cse:ed, as the call expanders
2480 force_reg the addresses, effectively forcing flag_no_function_cse
2482 flag_no_function_cse
= 1;
2485 if (write_symbols
== DWARF2_DEBUG
&& ! TARGET_ELF
)
2487 warning (0, "that particular -g option is invalid with -maout and -melinux");
2488 write_symbols
= DBX_DEBUG
;
2491 /* Set the per-function-data initializer. */
2492 init_machine_status
= cris_init_machine_status
;
2495 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2498 cris_asm_output_mi_thunk (FILE *stream
,
2499 tree thunkdecl ATTRIBUTE_UNUSED
,
2500 HOST_WIDE_INT delta
,
2501 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2505 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2506 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2507 reg_names
[CRIS_FIRST_ARG_REG
]);
2509 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2510 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2511 reg_names
[CRIS_FIRST_ARG_REG
]);
2515 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2517 name
= (* targetm
.strip_name_encoding
) (name
);
2521 fprintf (stream
, "\tba ");
2522 assemble_name (stream
, name
);
2523 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2527 fprintf (stream
, "add.d ");
2528 assemble_name (stream
, name
);
2529 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2534 fprintf (stream
, "jump ");
2535 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2536 fprintf (stream
, "\n");
2539 fprintf (stream
, "\tnop\n");
2543 /* Boilerplate emitted at start of file.
2545 NO_APP *only at file start* means faster assembly. It also means
2546 comments are not allowed. In some cases comments will be output
2547 for debugging purposes. Make sure they are allowed then.
2549 We want a .file directive only if TARGET_ELF. */
2551 cris_file_start (void)
2553 /* These expressions can vary at run time, so we cannot put
2554 them into TARGET_INITIALIZER. */
2555 targetm
.file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2556 targetm
.file_start_file_directive
= TARGET_ELF
;
2558 default_file_start ();
2561 /* Rename the function calls for integer multiply and divide. */
2563 cris_init_libfuncs (void)
2565 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2566 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2567 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2568 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2569 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2572 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2576 cris_init_expanders (void)
2578 /* Nothing here at the moment. */
2581 /* Zero initialization is OK for all current fields. */
2583 static struct machine_function
*
2584 cris_init_machine_status (void)
2586 return GGC_CNEW (struct machine_function
);
2589 /* Split a 2 word move (DI or presumably DF) into component parts.
2590 Originally a copy of gen_split_move_double in m32r.c. */
2593 cris_split_movdx (rtx
*operands
)
2595 enum machine_mode mode
= GET_MODE (operands
[0]);
2596 rtx dest
= operands
[0];
2597 rtx src
= operands
[1];
2600 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2601 longer happen; after reload there are no SUBREGs any more, and we're
2602 only called after reload. */
2603 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2608 int dregno
= REGNO (dest
);
2610 /* Reg-to-reg copy. */
2613 int sregno
= REGNO (src
);
2615 int reverse
= (dregno
== sregno
+ 1);
2617 /* We normally copy the low-numbered register first. However, if
2618 the first register operand 0 is the same as the second register of
2619 operand 1, we must copy in the opposite order. */
2620 emit_insn (gen_rtx_SET (VOIDmode
,
2621 operand_subword (dest
, reverse
, TRUE
, mode
),
2622 operand_subword (src
, reverse
, TRUE
, mode
)));
2624 emit_insn (gen_rtx_SET (VOIDmode
,
2625 operand_subword (dest
, !reverse
, TRUE
, mode
),
2626 operand_subword (src
, !reverse
, TRUE
, mode
)));
2628 /* Constant-to-reg copy. */
2629 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2632 split_double (src
, &words
[0], &words
[1]);
2633 emit_insn (gen_rtx_SET (VOIDmode
,
2634 operand_subword (dest
, 0, TRUE
, mode
),
2637 emit_insn (gen_rtx_SET (VOIDmode
,
2638 operand_subword (dest
, 1, TRUE
, mode
),
2641 /* Mem-to-reg copy. */
2642 else if (MEM_P (src
))
2644 /* If the high-address word is used in the address, we must load it
2645 last. Otherwise, load it first. */
2646 rtx addr
= XEXP (src
, 0);
2648 = (refers_to_regno_p (dregno
, dregno
+ 1, addr
, NULL
) != 0);
2650 /* The original code implies that we can't do
2651 move.x [rN+],rM move.x [rN],rM+1
2652 when rN is dead, because of REG_NOTES damage. That is
2653 consistent with what I've seen, so don't try it.
2655 We have two different cases here; if the addr is POST_INC,
2656 just pass it through, otherwise add constants. */
2658 if (GET_CODE (addr
) == POST_INC
)
2663 /* Whenever we emit insns with post-incremented
2664 addresses ourselves, we must add a post-inc note
2666 mem
= change_address (src
, SImode
, addr
);
2668 = gen_rtx_SET (VOIDmode
,
2669 operand_subword (dest
, 0, TRUE
, mode
), mem
);
2670 insn
= emit_insn (insn
);
2671 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2673 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2676 mem
= copy_rtx (mem
);
2678 = gen_rtx_SET (VOIDmode
,
2679 operand_subword (dest
, 1, TRUE
, mode
), mem
);
2680 insn
= emit_insn (insn
);
2681 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2683 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2688 /* Make sure we don't get any other addresses with
2689 embedded postincrements. They should be stopped in
2690 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2692 if (side_effects_p (addr
))
2693 fatal_insn ("unexpected side-effects in address", addr
);
2695 emit_insn (gen_rtx_SET
2697 operand_subword (dest
, reverse
, TRUE
, mode
),
2700 plus_constant (addr
,
2701 reverse
* UNITS_PER_WORD
))));
2702 emit_insn (gen_rtx_SET
2704 operand_subword (dest
, ! reverse
, TRUE
, mode
),
2707 plus_constant (addr
,
2713 internal_error ("Unknown src");
2715 /* Reg-to-mem copy or clear mem. */
2716 else if (MEM_P (dest
)
2718 || src
== const0_rtx
2719 || src
== CONST0_RTX (DFmode
)))
2721 rtx addr
= XEXP (dest
, 0);
2723 if (GET_CODE (addr
) == POST_INC
)
2728 /* Whenever we emit insns with post-incremented addresses
2729 ourselves, we must add a post-inc note manually. */
2730 mem
= change_address (dest
, SImode
, addr
);
2732 = gen_rtx_SET (VOIDmode
,
2733 mem
, operand_subword (src
, 0, TRUE
, mode
));
2734 insn
= emit_insn (insn
);
2735 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2737 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2740 mem
= copy_rtx (mem
);
2742 = gen_rtx_SET (VOIDmode
,
2744 operand_subword (src
, 1, TRUE
, mode
));
2745 insn
= emit_insn (insn
);
2746 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2748 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2753 /* Make sure we don't get any other addresses with embedded
2754 postincrements. They should be stopped in
2755 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2756 if (side_effects_p (addr
))
2757 fatal_insn ("unexpected side-effects in address", addr
);
2759 emit_insn (gen_rtx_SET
2761 change_address (dest
, SImode
, addr
),
2762 operand_subword (src
, 0, TRUE
, mode
)));
2764 emit_insn (gen_rtx_SET
2766 change_address (dest
, SImode
,
2767 plus_constant (addr
,
2769 operand_subword (src
, 1, TRUE
, mode
)));
2774 internal_error ("Unknown dest");
2781 /* The expander for the prologue pattern name. */
2784 cris_expand_prologue (void)
2787 int size
= get_frame_size ();
2788 /* Shorten the used name for readability. */
2789 int cfoa_size
= crtl
->outgoing_args_size
;
2790 int last_movem_reg
= -1;
2793 int return_address_on_stack
= cris_return_address_on_stack ();
2794 int got_really_used
= false;
2795 int n_movem_regs
= 0;
2796 int pretend
= crtl
->args
.pretend_args_size
;
2798 /* Don't do anything if no prologues or epilogues are wanted. */
2799 if (!TARGET_PROLOGUE_EPILOGUE
)
2802 CRIS_ASSERT (size
>= 0);
2804 if (crtl
->uses_pic_offset_table
)
2806 /* A reference may have been optimized out (like the abort () in
2807 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2809 push_topmost_sequence ();
2811 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
2812 pop_topmost_sequence ();
2815 /* Align the size to what's best for the CPU model. */
2816 if (TARGET_STACK_ALIGN
)
2817 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
2821 /* See also cris_setup_incoming_varargs where
2822 cfun->machine->stdarg_regs is set. There are other setters of
2823 crtl->args.pretend_args_size than stdarg handling, like
2824 for an argument passed with parts in R13 and stack. We must
2825 not store R13 into the pretend-area for that case, as GCC does
2826 that itself. "Our" store would be marked as redundant and GCC
2827 will attempt to remove it, which will then be flagged as an
2828 internal error; trying to remove a frame-related insn. */
2829 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
2831 framesize
+= pretend
;
2833 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
2835 regno
--, pretend
-= 4, stdarg_regs
--)
2837 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2839 plus_constant (stack_pointer_rtx
,
2841 /* FIXME: When dwarf2 frame output and unless asynchronous
2842 exceptions, make dwarf2 bundle together all stack
2843 adjustments like it does for registers between stack
2845 RTX_FRAME_RELATED_P (insn
) = 1;
2847 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2848 set_mem_alias_set (mem
, get_varargs_alias_set ());
2849 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
2851 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2852 the value isn't restored, so we don't want to tell dwarf2
2853 that it's been stored to stack, else EH handling info would
2857 /* For other setters of crtl->args.pretend_args_size, we
2858 just adjust the stack by leaving the remaining size in
2859 "pretend", handled below. */
2862 /* Save SRP if not a leaf function. */
2863 if (return_address_on_stack
)
2865 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2867 plus_constant (stack_pointer_rtx
,
2870 RTX_FRAME_RELATED_P (insn
) = 1;
2872 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2873 set_mem_alias_set (mem
, get_frame_alias_set ());
2874 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
2875 RTX_FRAME_RELATED_P (insn
) = 1;
2879 /* Set up the frame pointer, if needed. */
2880 if (frame_pointer_needed
)
2882 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2884 plus_constant (stack_pointer_rtx
,
2887 RTX_FRAME_RELATED_P (insn
) = 1;
2889 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2890 set_mem_alias_set (mem
, get_frame_alias_set ());
2891 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
2892 RTX_FRAME_RELATED_P (insn
) = 1;
2894 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
2895 RTX_FRAME_RELATED_P (insn
) = 1;
2900 /* Between frame-pointer and saved registers lie the area for local
2901 variables. If we get here with "pretended" size remaining, count
2902 it into the general stack size. */
2905 /* Get a contiguous sequence of registers, starting with R0, that need
2907 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2909 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2913 /* Check if movem may be used for registers so far. */
2914 if (regno
== last_movem_reg
+ 1)
2915 /* Yes, update next expected register. */
2916 last_movem_reg
= regno
;
2919 /* We cannot use movem for all registers. We have to flush
2920 any movem:ed registers we got so far. */
2921 if (last_movem_reg
!= -1)
2924 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2926 /* It is a win to use a side-effect assignment for
2927 64 <= size <= 128. But side-effect on movem was
2928 not usable for CRIS v0..3. Also only do it if
2929 side-effects insns are allowed. */
2930 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2931 && (last_movem_reg
+ 1) * 4 + size
<= 128
2932 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
2933 && TARGET_SIDE_EFFECT_PREFIXES
)
2936 = gen_rtx_MEM (SImode
,
2937 plus_constant (stack_pointer_rtx
,
2938 -(n_saved
* 4 + size
)));
2939 set_mem_alias_set (mem
, get_frame_alias_set ());
2941 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2942 -(n_saved
* 4 + size
),
2948 = gen_rtx_SET (VOIDmode
,
2950 plus_constant (stack_pointer_rtx
,
2951 -(n_saved
* 4 + size
)));
2952 insn
= emit_insn (insn
);
2953 RTX_FRAME_RELATED_P (insn
) = 1;
2955 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2956 set_mem_alias_set (mem
, get_frame_alias_set ());
2957 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2961 framesize
+= n_saved
* 4 + size
;
2962 last_movem_reg
= -1;
2966 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2968 plus_constant (stack_pointer_rtx
,
2970 RTX_FRAME_RELATED_P (insn
) = 1;
2972 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2973 set_mem_alias_set (mem
, get_frame_alias_set ());
2974 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
2975 RTX_FRAME_RELATED_P (insn
) = 1;
2977 framesize
+= 4 + size
;
2983 /* Check after, if we could movem all registers. This is the normal case. */
2984 if (last_movem_reg
!= -1)
2987 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2989 /* Side-effect on movem was not usable for CRIS v0..3. Also only
2990 do it if side-effects insns are allowed. */
2991 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2992 && (last_movem_reg
+ 1) * 4 + size
<= 128
2993 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
2994 && TARGET_SIDE_EFFECT_PREFIXES
)
2997 = gen_rtx_MEM (SImode
,
2998 plus_constant (stack_pointer_rtx
,
2999 -(n_saved
* 4 + size
)));
3000 set_mem_alias_set (mem
, get_frame_alias_set ());
3001 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3002 -(n_saved
* 4 + size
), true);
3007 = gen_rtx_SET (VOIDmode
,
3009 plus_constant (stack_pointer_rtx
,
3010 -(n_saved
* 4 + size
)));
3011 insn
= emit_insn (insn
);
3012 RTX_FRAME_RELATED_P (insn
) = 1;
3014 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3015 set_mem_alias_set (mem
, get_frame_alias_set ());
3016 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3019 framesize
+= n_saved
* 4 + size
;
3020 /* We have to put outgoing argument space after regs. */
3023 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3025 plus_constant (stack_pointer_rtx
,
3027 RTX_FRAME_RELATED_P (insn
) = 1;
3028 framesize
+= cfoa_size
;
3031 else if ((size
+ cfoa_size
) > 0)
3033 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3035 plus_constant (stack_pointer_rtx
,
3036 -(cfoa_size
+ size
))));
3037 RTX_FRAME_RELATED_P (insn
) = 1;
3038 framesize
+= size
+ cfoa_size
;
3041 /* Set up the PIC register, if it is used. */
3042 if (got_really_used
)
3045 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3046 emit_move_insn (pic_offset_table_rtx
, got
);
3048 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3049 follow exceptional paths and tries to delete the GOT load as
3050 unused, if it isn't used on the non-exceptional paths. Other
3051 ports have similar or other cover-ups, or plain bugs marking
3052 the GOT register load as maybe-dead. To see this, remove the
3053 line below and try libsupc++/vec.cc or a trivial
3054 "static void y (); void x () {try {y ();} catch (...) {}}". */
3055 emit_use (pic_offset_table_rtx
);
3058 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3059 warning (0, "stackframe too big: %d bytes", framesize
);
3062 /* The expander for the epilogue pattern. */
3065 cris_expand_epilogue (void)
3068 int size
= get_frame_size ();
3069 int last_movem_reg
= -1;
3070 int argspace_offset
= crtl
->outgoing_args_size
;
3071 int pretend
= crtl
->args
.pretend_args_size
;
3073 bool return_address_on_stack
= cris_return_address_on_stack ();
3074 /* A reference may have been optimized out
3075 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3076 so check that it's still used. */
3077 int got_really_used
= false;
3078 int n_movem_regs
= 0;
3080 if (!TARGET_PROLOGUE_EPILOGUE
)
3083 if (crtl
->uses_pic_offset_table
)
3085 /* A reference may have been optimized out (like the abort () in
3086 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3088 push_topmost_sequence ();
3090 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
3091 pop_topmost_sequence ();
3094 /* Align byte count of stack frame. */
3095 if (TARGET_STACK_ALIGN
)
3096 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3098 /* Check how many saved regs we can movem. They start at r0 and must
3101 regno
< FIRST_PSEUDO_REGISTER
;
3103 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3107 if (regno
== last_movem_reg
+ 1)
3108 last_movem_reg
= regno
;
3113 /* If there was only one register that really needed to be saved
3114 through movem, don't use movem. */
3115 if (n_movem_regs
== 1)
3116 last_movem_reg
= -1;
3118 /* Now emit "normal" move insns for all regs higher than the movem
3120 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3121 regno
> last_movem_reg
;
3123 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3127 if (argspace_offset
)
3129 /* There is an area for outgoing parameters located before
3130 the saved registers. We have to adjust for that. */
3131 emit_insn (gen_rtx_SET (VOIDmode
,
3133 plus_constant (stack_pointer_rtx
,
3135 /* Make sure we only do this once. */
3136 argspace_offset
= 0;
3139 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3140 stack_pointer_rtx
));
3141 set_mem_alias_set (mem
, get_frame_alias_set ());
3142 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
3144 /* Whenever we emit insns with post-incremented addresses
3145 ourselves, we must add a post-inc note manually. */
3147 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3150 /* If we have any movem-restore, do it now. */
3151 if (last_movem_reg
!= -1)
3155 if (argspace_offset
)
3157 emit_insn (gen_rtx_SET (VOIDmode
,
3159 plus_constant (stack_pointer_rtx
,
3161 argspace_offset
= 0;
3164 mem
= gen_rtx_MEM (SImode
,
3165 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3166 set_mem_alias_set (mem
, get_frame_alias_set ());
3168 = emit_insn (cris_gen_movem_load (mem
,
3169 GEN_INT (last_movem_reg
+ 1), 0));
3170 /* Whenever we emit insns with post-incremented addresses
3171 ourselves, we must add a post-inc note manually. */
3172 if (side_effects_p (PATTERN (insn
)))
3174 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3177 /* If we don't clobber all of the allocated stack area (we've already
3178 deallocated saved registers), GCC might want to schedule loads from
3179 the stack to *after* the stack-pointer restore, which introduces an
3180 interrupt race condition. This happened for the initial-value
3181 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3182 other failure for that test). It also happened for the stack slot
3183 for the return value in (one version of)
3184 linux/fs/dcache.c:__d_lookup, at least with "-O2
3185 -fno-omit-frame-pointer". */
3187 /* Restore frame pointer if necessary. */
3188 if (frame_pointer_needed
)
3192 emit_insn (gen_cris_frame_deallocated_barrier ());
3194 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3195 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3196 stack_pointer_rtx
));
3197 set_mem_alias_set (mem
, get_frame_alias_set ());
3198 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3200 /* Whenever we emit insns with post-incremented addresses
3201 ourselves, we must add a post-inc note manually. */
3203 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3205 else if ((size
+ argspace_offset
) != 0)
3207 emit_insn (gen_cris_frame_deallocated_barrier ());
3209 /* If there was no frame-pointer to restore sp from, we must
3210 explicitly deallocate local variables. */
3212 /* Handle space for outgoing parameters that hasn't been handled
3214 size
+= argspace_offset
;
3216 emit_insn (gen_rtx_SET (VOIDmode
,
3218 plus_constant (stack_pointer_rtx
, size
)));
3221 /* If this function has no pushed register parameters
3222 (stdargs/varargs), and if it is not a leaf function, then we have
3223 the return address on the stack. */
3224 if (return_address_on_stack
&& pretend
== 0)
3226 if (TARGET_V32
|| crtl
->calls_eh_return
)
3230 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3231 mem
= gen_rtx_MEM (SImode
,
3232 gen_rtx_POST_INC (SImode
,
3233 stack_pointer_rtx
));
3234 set_mem_alias_set (mem
, get_frame_alias_set ());
3235 insn
= emit_move_insn (srpreg
, mem
);
3237 /* Whenever we emit insns with post-incremented addresses
3238 ourselves, we must add a post-inc note manually. */
3240 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3242 if (crtl
->calls_eh_return
)
3243 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3245 gen_rtx_raw_REG (SImode
,
3246 CRIS_STACKADJ_REG
)));
3247 cris_expand_return (false);
3250 cris_expand_return (true);
3255 /* If we pushed some register parameters, then adjust the stack for
3259 /* If SRP is stored on the way, we need to restore it first. */
3260 if (return_address_on_stack
)
3263 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3266 mem
= gen_rtx_MEM (SImode
,
3267 gen_rtx_POST_INC (SImode
,
3268 stack_pointer_rtx
));
3269 set_mem_alias_set (mem
, get_frame_alias_set ());
3270 insn
= emit_move_insn (srpreg
, mem
);
3272 /* Whenever we emit insns with post-incremented addresses
3273 ourselves, we must add a post-inc note manually. */
3275 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3278 emit_insn (gen_rtx_SET (VOIDmode
,
3280 plus_constant (stack_pointer_rtx
, pretend
)));
3283 /* Perform the "physical" unwinding that the EH machinery calculated. */
3284 if (crtl
->calls_eh_return
)
3285 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3287 gen_rtx_raw_REG (SImode
,
3288 CRIS_STACKADJ_REG
)));
3289 cris_expand_return (false);
3292 /* Worker function for generating movem from mem for load_multiple. */
3295 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3297 int nregs
= INTVAL (nregs_rtx
);
3301 rtx srcreg
= XEXP (src
, 0);
3302 unsigned int regno
= nregs
- 1;
3311 if (GET_CODE (srcreg
) == POST_INC
)
3312 srcreg
= XEXP (srcreg
, 0);
3314 CRIS_ASSERT (REG_P (srcreg
));
3316 /* Don't use movem for just one insn. The insns are equivalent except
3317 for the pipeline hazard (on v32); movem does not forward the loaded
3318 registers so there's a three cycles penalty for their use. */
3320 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3322 vec
= rtvec_alloc (nprefix
+ nregs
3323 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3325 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3327 RTVEC_ELT (vec
, nprefix
+ 1)
3328 = gen_rtx_SET (VOIDmode
, srcreg
, plus_constant (srcreg
, nregs
* 4));
3332 src
= replace_equiv_address (src
, srcreg
);
3333 RTVEC_ELT (vec
, nprefix
)
3334 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
), src
);
3337 for (i
= 1; i
< nregs
; i
++, eltno
++)
3339 RTVEC_ELT (vec
, nprefix
+ eltno
)
3340 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
),
3341 adjust_address_nv (src
, SImode
, i
* 4));
3345 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3348 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3349 are added that the dwarf2 machinery understands. */
3352 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3355 int nregs
= INTVAL (nregs_rtx
);
3360 rtx destreg
= XEXP (dest
, 0);
3361 unsigned int regno
= nregs
- 1;
3370 if (GET_CODE (destreg
) == POST_INC
)
3371 increment
+= nregs
* 4;
3373 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3374 destreg
= XEXP (destreg
, 0);
3376 CRIS_ASSERT (REG_P (destreg
));
3378 /* Don't use movem for just one insn. The insns are equivalent except
3379 for the pipeline hazard (on v32); movem does not forward the loaded
3380 registers so there's a three cycles penalty for use. */
3383 rtx mov
= gen_rtx_SET (VOIDmode
, dest
, gen_rtx_REG (SImode
, 0));
3387 insn
= emit_insn (mov
);
3389 RTX_FRAME_RELATED_P (insn
) = 1;
3393 /* If there was a request for a side-effect, create the ordinary
3395 vec
= rtvec_alloc (2);
3397 RTVEC_ELT (vec
, 0) = mov
;
3398 RTVEC_ELT (vec
, 1) = gen_rtx_SET (VOIDmode
, destreg
,
3399 plus_constant (destreg
, increment
));
3402 RTX_FRAME_RELATED_P (mov
) = 1;
3403 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3408 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3410 = gen_rtx_SET (VOIDmode
,
3411 replace_equiv_address (dest
,
3412 plus_constant (destreg
,
3414 gen_rtx_REG (SImode
, regno
));
3417 /* The dwarf2 info wants this mark on each component in a parallel
3418 that's part of the prologue (though it's optional on the first
3421 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3426 = gen_rtx_SET (VOIDmode
, destreg
,
3427 plus_constant (destreg
,
3429 ? increment
: nregs
* 4));
3433 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3435 /* Don't call adjust_address_nv on a post-incremented address if
3437 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3438 dest
= replace_equiv_address (dest
, destreg
);
3441 for (i
= 1; i
< nregs
; i
++, eltno
++)
3443 RTVEC_ELT (vec
, eltno
)
3444 = gen_rtx_SET (VOIDmode
, adjust_address_nv (dest
, SImode
, i
* 4),
3445 gen_rtx_REG (SImode
, regno
));
3447 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3452 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3454 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3455 we need to keep the stack adjustment separate, after the
3456 MEM-setters. Else the stack-adjustment in the second component of
3457 the parallel would be mishandled; the offsets for the SETs that
3458 follow it would be wrong. We prepare for this by adding a
3459 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3460 followed by the increment. Note that we have FRAME_RELATED_P on
3461 all the SETs, including the original stack adjustment SET in the
3467 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3468 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3469 for (i
= 1; i
< nregs
; i
++)
3471 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3472 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3474 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, seq
,
3478 RTX_FRAME_RELATED_P (insn
) = 1;
3484 /* Worker function for expanding the address for PIC function calls. */
3487 cris_expand_pic_call_address (rtx
*opp
)
3491 gcc_assert (MEM_P (op
));
3494 /* It might be that code can be generated that jumps to 0 (or to a
3495 specific address). Don't die on that. (There is a
3497 if (CONSTANT_ADDRESS_P (op
) && !CONST_INT_P (op
))
3499 enum cris_pic_symbol_type t
= cris_pic_symbol_type_of (op
);
3501 CRIS_ASSERT (can_create_pseudo_p ());
3503 /* For local symbols (non-PLT), just get the plain symbol
3504 reference into a register. For symbols that can be PLT, make
3506 if (t
== cris_rel_symbol
)
3508 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3509 into a register caused performance regression for 3.2.1,
3510 observable in __floatdidf and elsewhere in libgcc. */
3513 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3514 HOST_WIDE_INT offs
= get_integer_term (op
);
3516 /* We can't get calls to sym+N, N integer, can we? */
3517 gcc_assert (offs
== 0);
3519 op
= gen_rtx_CONST (Pmode
,
3520 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3521 CRIS_UNSPEC_PCREL
));
3524 op
= force_reg (Pmode
, op
);
3526 else if (t
== cris_got_symbol
)
3528 if (TARGET_AVOID_GOTPLT
)
3530 /* Change a "jsr sym" into (allocate register rM, rO)
3531 "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM"
3532 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3533 "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))"
3536 gcc_assert (can_create_pseudo_p ());
3537 crtl
->uses_pic_offset_table
= 1;
3538 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3540 ? CRIS_UNSPEC_PLT_PCREL
3541 : CRIS_UNSPEC_PLT_GOTREL
);
3542 tem
= gen_rtx_CONST (Pmode
, tem
);
3547 rm
= gen_reg_rtx (Pmode
);
3548 emit_move_insn (rm
, tem
);
3549 ro
= gen_reg_rtx (Pmode
);
3550 if (expand_binop (Pmode
, add_optab
, rm
,
3551 pic_offset_table_rtx
,
3552 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3553 internal_error ("expand_binop failed in movsi got");
3559 /* Change a "jsr sym" into (allocate register rM, rO)
3560 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3561 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3562 marked as not trapping and not aliasing. No "move.d
3563 [rO],rP" as that would invite to re-use of a value
3564 that should not be reused. FIXME: Need a peephole2
3565 for cases when this is cse:d from the call, to change
3566 back to just get the PLT entry address, so we don't
3567 resolve the same symbol over and over (the memory
3568 access of the PLTGOT isn't constant). */
3569 rtx tem
, mem
, rm
, ro
;
3571 gcc_assert (can_create_pseudo_p ());
3572 crtl
->uses_pic_offset_table
= 1;
3573 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3574 CRIS_UNSPEC_PLTGOTREAD
);
3575 rm
= gen_reg_rtx (Pmode
);
3576 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3577 ro
= gen_reg_rtx (Pmode
);
3578 if (expand_binop (Pmode
, add_optab
, rm
,
3579 pic_offset_table_rtx
,
3580 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3581 internal_error ("expand_binop failed in movsi got");
3582 mem
= gen_rtx_MEM (Pmode
, ro
);
3584 /* This MEM doesn't alias anything. Whether it aliases
3585 other same symbols is unimportant. */
3586 set_mem_alias_set (mem
, new_alias_set ());
3587 MEM_NOTRAP_P (mem
) = 1;
3592 /* Can't possibly get a GOT-needing-fixup for a function-call,
3594 fatal_insn ("Unidentifiable call op", op
);
3596 *opp
= replace_equiv_address (*opp
, op
);
3600 /* Make sure operands are in the right order for an addsi3 insn as
3601 generated by a define_split. Nothing but REG_P as the first
3602 operand is recognized by addsi3 after reload. OPERANDS contains
3603 the operands, with the first at OPERANDS[N] and the second at
3607 cris_order_for_addsi3 (rtx
*operands
, int n
)
3609 if (!REG_P (operands
[n
]))
3611 rtx tem
= operands
[n
];
3612 operands
[n
] = operands
[n
+ 1];
3613 operands
[n
+ 1] = tem
;
3617 /* Use from within code, from e.g. PRINT_OPERAND and
3618 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3619 different things depending on whether code operand or constant is
3623 cris_output_addr_const (FILE *file
, rtx x
)
3626 output_addr_const (file
, x
);
3630 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3633 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3635 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3637 if (flag_pic
&& in_code
> 0)
3639 const char *origstr
= XSTR (x
, 0);
3641 str
= (* targetm
.strip_name_encoding
) (origstr
);
3642 assemble_name (file
, str
);
3645 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3646 output_operand_lossage ("PIC register isn't set up");
3649 assemble_name (file
, XSTR (x
, 0));
3652 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3655 cris_asm_output_label_ref (FILE *file
, char *buf
)
3657 if (flag_pic
&& in_code
> 0)
3659 assemble_name (file
, buf
);
3662 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3663 internal_error ("emitting PIC operand, but PIC register isn't set up");
3666 assemble_name (file
, buf
);
3669 /* Worker function for OUTPUT_ADDR_CONST_EXTRA. */
3672 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3674 switch (GET_CODE (xconst
))
3679 x
= XVECEXP (xconst
, 0, 0);
3680 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3681 || GET_CODE (x
) == LABEL_REF
3682 || GET_CODE (x
) == CONST
);
3683 output_addr_const (file
, x
);
3684 switch (XINT (xconst
, 1))
3686 case CRIS_UNSPEC_PCREL
:
3687 /* We only get this with -fpic/PIC to tell it apart from an
3688 invalid symbol. We can't tell here, but it should only
3689 be the operand of a call or movsi. */
3690 gcc_assert (TARGET_V32
&& flag_pic
);
3693 case CRIS_UNSPEC_PLT_PCREL
:
3694 gcc_assert (TARGET_V32
);
3695 fprintf (file
, ":PLT");
3698 case CRIS_UNSPEC_PLT_GOTREL
:
3699 gcc_assert (!TARGET_V32
);
3700 fprintf (file
, ":PLTG");
3703 case CRIS_UNSPEC_GOTREL
:
3704 gcc_assert (!TARGET_V32
);
3705 fprintf (file
, ":GOTOFF");
3708 case CRIS_UNSPEC_GOTREAD
:
3710 fprintf (file
, ":GOT16");
3712 fprintf (file
, ":GOT");
3715 case CRIS_UNSPEC_PLTGOTREAD
:
3717 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
3719 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
3732 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3735 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3736 int incoming ATTRIBUTE_UNUSED
)
3738 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3741 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3744 cris_setup_incoming_varargs (CUMULATIVE_ARGS
*ca
,
3745 enum machine_mode mode ATTRIBUTE_UNUSED
,
3746 tree type ATTRIBUTE_UNUSED
,
3747 int *pretend_arg_size
,
3750 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3752 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
3753 cfun
->machine
->stdarg_regs
= stdarg_regs
;
3754 *pretend_arg_size
= stdarg_regs
* 4;
3758 fprintf (asm_out_file
,
3759 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3760 ca
->regs
, *pretend_arg_size
, second_time
);
3763 /* Return true if TYPE must be passed by invisible reference.
3764 For cris, we pass <= 8 bytes by value, others by reference. */
3767 cris_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
3768 enum machine_mode mode
, const_tree type
,
3769 bool named ATTRIBUTE_UNUSED
)
3771 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
3772 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
3775 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
3776 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
3777 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
3780 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
3781 enum machine_mode mode
,
3782 int *punsignedp ATTRIBUTE_UNUSED
,
3783 const_tree fntype ATTRIBUTE_UNUSED
,
3786 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
3787 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
3788 Maybe pointless as of now, but let's keep the old behavior. */
3789 if (for_return
== 1)
3791 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
3794 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3798 cris_function_value(const_tree type
,
3799 const_tree func ATTRIBUTE_UNUSED
,
3800 bool outgoing ATTRIBUTE_UNUSED
)
3802 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
3805 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3809 cris_libcall_value (enum machine_mode mode
,
3810 const_rtx fun ATTRIBUTE_UNUSED
)
3812 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
3815 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3819 cris_function_value_regno_p (const unsigned int regno
)
3821 return (regno
== CRIS_FIRST_ARG_REG
);
3825 cris_arg_partial_bytes (CUMULATIVE_ARGS
*ca
, enum machine_mode mode
,
3826 tree type
, bool named ATTRIBUTE_UNUSED
)
3828 if (ca
->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
3829 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
3830 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
3831 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
3832 return UNITS_PER_WORD
;
3837 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
3840 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
3842 HARD_REG_SET mof_set
;
3846 CLEAR_HARD_REG_SET (mof_set
);
3847 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
3849 /* For the time being, all asms clobber condition codes. Revisit when
3850 there's a reasonable use for inputs/outputs that mention condition
3853 = tree_cons (NULL_TREE
,
3854 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
3855 reg_names
[CRIS_CC0_REGNUM
]),
3858 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
3860 tree val
= TREE_VALUE (t
);
3862 /* The constraint letter for the singleton register class of MOF
3863 is 'h'. If it's mentioned in the constraints, the asm is
3864 MOF-aware and adding it to the clobbers would cause it to have
3865 impossible constraints. */
3866 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
3868 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
3872 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
3874 tree val
= TREE_VALUE (t
);
3876 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
3878 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
3882 return tree_cons (NULL_TREE
,
3883 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
3884 reg_names
[CRIS_MOF_REGNUM
]),
3888 /* Implement TARGET_FRAME_POINTER_REQUIRED.
3890 Really only needed if the stack frame has variable length (alloca
3891 or variable sized local arguments (GNU C extension). See PR39499 and
3892 PR38609 for the reason this isn't just 0. */
3895 cris_frame_pointer_required (void)
3897 return !current_function_sp_is_unchanging
;
3900 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
3902 This looks too complicated, and it is. I assigned r7 to be the
3903 static chain register, but it is call-saved, so we have to save it,
3904 and come back to restore it after the call, so we have to save srp...
3905 Anyway, trampolines are rare enough that we can cope with this
3906 somewhat lack of elegance.
3907 (Do not be tempted to "straighten up" whitespace in the asms; the
3908 assembler #NO_APP state mandates strict spacing). */
3909 /* ??? See the i386 regparm=3 implementation that pushes the static
3910 chain value to the stack in the trampoline, and uses a call-saved
3911 register when called directly. */
3914 cris_asm_trampoline_template (FILE *f
)
3918 /* This normally-unused nop insn acts as an instruction to
3919 the simulator to flush its instruction cache. None of
3920 the other instructions in the trampoline template suits
3921 as a trigger for V32. The pc-relative addressing mode
3922 works nicely as a trigger for V10.
3923 FIXME: Have specific V32 template (possibly avoiding the
3924 use of a special instruction). */
3925 fprintf (f
, "\tclearf x\n");
3926 /* We have to use a register as an intermediate, choosing
3927 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
3928 so we can use it for address indirection and jsr target. */
3929 fprintf (f
, "\tmove $r1,$mof\n");
3931 fprintf (f
, "\tmove.d 0,$r1\n");
3932 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3933 fprintf (f
, "\taddq 6,$r1\n");
3934 fprintf (f
, "\tmove $mof,[$r1]\n");
3935 fprintf (f
, "\taddq 6,$r1\n");
3936 fprintf (f
, "\tmove $srp,[$r1]\n");
3938 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3940 fprintf (f
, "\tmove.d 0,$r1\n");
3941 fprintf (f
, "\tjsr $r1\n");
3942 fprintf (f
, "\tsetf\n");
3944 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3946 fprintf (f
, "\tmove.d 0,$r1\n");
3948 fprintf (f
, "\tmove.d 0,$r9\n");
3949 fprintf (f
, "\tjump $r9\n");
3950 fprintf (f
, "\tsetf\n");
3954 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3955 fprintf (f
, "\tmove $srp,[$pc+22]\n");
3956 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3957 fprintf (f
, "\tjsr 0\n");
3958 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3959 fprintf (f
, "\tjump 0\n");
3963 /* Implement TARGET_TRAMPOLINE_INIT. */
3966 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3968 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3969 rtx tramp
= XEXP (m_tramp
, 0);
3972 emit_block_move (m_tramp
, assemble_trampoline_template (),
3973 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
3977 mem
= adjust_address (m_tramp
, SImode
, 6);
3978 emit_move_insn (mem
, plus_constant (tramp
, 38));
3979 mem
= adjust_address (m_tramp
, SImode
, 22);
3980 emit_move_insn (mem
, chain_value
);
3981 mem
= adjust_address (m_tramp
, SImode
, 28);
3982 emit_move_insn (mem
, fnaddr
);
3986 mem
= adjust_address (m_tramp
, SImode
, 10);
3987 emit_move_insn (mem
, chain_value
);
3988 mem
= adjust_address (m_tramp
, SImode
, 16);
3989 emit_move_insn (mem
, fnaddr
);
3992 /* Note that there is no need to do anything with the cache for
3993 sake of a trampoline. */
3998 /* Various small functions to replace macros. Only called from a
3999 debugger. They might collide with gcc functions or system functions,
4000 so only emit them when '#if 1' above. */
4002 enum rtx_code
Get_code (rtx
);
4007 return GET_CODE (x
);
4010 const char *Get_mode (rtx
);
4015 return GET_MODE_NAME (GET_MODE (x
));
4018 rtx
Xexp (rtx
, int);
4026 rtx
Xvecexp (rtx
, int, int);
4029 Xvecexp (rtx x
, int n
, int m
)
4031 return XVECEXP (x
, n
, m
);
4034 int Get_rtx_len (rtx
);
4039 return GET_RTX_LENGTH (GET_CODE (x
));
4042 /* Use upper-case to distinguish from local variables that are sometimes
4043 called next_insn and prev_insn. */
4045 rtx
Next_insn (rtx
);
4048 Next_insn (rtx insn
)
4050 return NEXT_INSN (insn
);
4053 rtx
Prev_insn (rtx
);
4056 Prev_insn (rtx insn
)
4058 return PREV_INSN (insn
);
4062 #include "gt-cris.h"
4066 * eval: (c-set-style "gnu")
4067 * indent-tabs-mode: t