| blob | 8d952975818a1e2bf78b0465e494ca21ee487a5e |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
62 #endif
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
70 : 4)
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
78 const
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
106 in SFmode, DFmode and XFmode */
108 in SFmode, DFmode and XFmode */
111 in SImode and DImode */
113 in SImode and DImode */
116 in SImode, DImode and TImode */
118 in SImode, DImode and TImode */
146 };
148 /* Processor costs (relative to an add) */
149 static const
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
177 in SFmode, DFmode and XFmode */
179 in SFmode, DFmode and XFmode */
182 in SImode and DImode */
184 in SImode and DImode */
187 in SImode, DImode and TImode */
189 in SImode, DImode and TImode */
203 DUMMY_STRINGOP_ALGS},
205 DUMMY_STRINGOP_ALGS},
217 };
219 static const
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
247 in SFmode, DFmode and XFmode */
249 in SFmode, DFmode and XFmode */
252 in SImode and DImode */
254 in SImode and DImode */
257 in SImode, DImode and TImode */
259 in SImode, DImode and TImode */
262 shared for code and data, so 4kB is
263 not really precise. */
275 DUMMY_STRINGOP_ALGS},
277 DUMMY_STRINGOP_ALGS},
289 };
291 static const
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
319 in SFmode, DFmode and XFmode */
321 in SFmode, DFmode and XFmode */
324 in SImode and DImode */
326 in SImode and DImode */
329 in SImode, DImode and TImode */
331 in SImode, DImode and TImode */
345 DUMMY_STRINGOP_ALGS},
347 DUMMY_STRINGOP_ALGS},
359 };
361 static const
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
389 in SFmode, DFmode and XFmode */
391 in SFmode, DFmode and XFmode */
394 in SImode and DImode */
396 in SImode and DImode */
399 in SImode, DImode and TImode */
401 in SImode, DImode and TImode */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
418 */
421 DUMMY_STRINGOP_ALGS},
424 DUMMY_STRINGOP_ALGS},
436 };
438 static const
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
466 in SFmode, DFmode and XFmode */
468 in SFmode, DFmode and XFmode */
472 in SImode and DImode */
474 in SImode and DImode */
477 in SImode, DImode and TImode */
479 in SImode, DImode and TImode */
493 DUMMY_STRINGOP_ALGS},
495 DUMMY_STRINGOP_ALGS},
507 };
509 static const
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
537 in SFmode, DFmode and XFmode */
539 in SFmode, DFmode and XFmode */
542 in SImode and DImode */
544 in SImode and DImode */
547 in SImode, DImode and TImode */
549 in SImode, DImode and TImode */
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
566 DUMMY_STRINGOP_ALGS},
568 DUMMY_STRINGOP_ALGS},
580 };
582 static const
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
610 in SFmode, DFmode and XFmode */
612 in SFmode, DFmode and XFmode */
615 in SImode and DImode */
617 in SImode and DImode */
620 in SImode, DImode and TImode */
622 in SImode, DImode and TImode */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
639 DUMMY_STRINGOP_ALGS},
641 DUMMY_STRINGOP_ALGS},
653 };
655 static const
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
683 in SFmode, DFmode and XFmode */
685 in SFmode, DFmode and XFmode */
688 in SImode and DImode */
690 in SImode and DImode */
693 in SImode, DImode and TImode */
695 in SImode, DImode and TImode */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
704 time). */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
732 };
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
761 in SFmode, DFmode and XFmode */
763 in SFmode, DFmode and XFmode */
766 in SImode and DImode */
768 in SImode and DImode */
771 in SImode, DImode and TImode */
773 in SImode, DImode and TImode */
775 /* On K8
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
778 On AMDFAM10
779 MOVD reg64, xmmreg Double FADD 3
780 1/1 1/1
781 MOVD reg32, xmmreg Double FADD 3
782 1/1 1/1 */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
790 time). */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
819 };
843 in QImode, HImode and SImode.
844 Relative to reg-reg move (2). */
848 in SFmode, DFmode and XFmode */
850 in SFmode, DFmode and XFmode */
853 in SImode and DImode */
855 in SImode and DImode */
858 in SImode, DImode and TImode */
860 in SImode, DImode and TImode */
862 /* On K8
863 MOVD reg64, xmmreg Double FSTORE 4
864 MOVD reg32, xmmreg Double FSTORE 4
865 On AMDFAM10
866 MOVD reg64, xmmreg Double FADD 3
867 1/1 1/1
868 MOVD reg32, xmmreg Double FADD 3
869 1/1 1/1 */
873 /* New AMD processors never drop prefetches; if they cannot be performed
874 immediately, they are queued. We set number of simultaneous prefetches
875 to a large constant to reflect this (it probably is not a good idea not
876 to limit number of prefetches at all, as their execution also takes some
877 time). */
887 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
888 very small blocks it is better to use loop. For large blocks, libcall can
889 do nontemporary accesses and beat inline considerably. */
906 };
908 static const
931 in QImode, HImode and SImode.
932 Relative to reg-reg move (2). */
936 in SFmode, DFmode and XFmode */
938 in SFmode, DFmode and XFmode */
941 in SImode and DImode */
943 in SImode and DImode */
946 in SImode, DImode and TImode */
948 in SImode, DImode and TImode */
962 DUMMY_STRINGOP_ALGS},
965 DUMMY_STRINGOP_ALGS},
977 };
979 static const
1002 in QImode, HImode and SImode.
1003 Relative to reg-reg move (2). */
1007 in SFmode, DFmode and XFmode */
1009 in SFmode, DFmode and XFmode */
1012 in SImode and DImode */
1014 in SImode and DImode */
1017 in SImode, DImode and TImode */
1019 in SImode, DImode and TImode */
1050 };
1052 static const
1075 in QImode, HImode and SImode.
1076 Relative to reg-reg move (2). */
1080 in SFmode, DFmode and XFmode */
1082 in SFmode, DFmode and XFmode */
1085 in SImode and DImode */
1087 in SImode and DImode */
1090 in SImode, DImode and TImode */
1092 in SImode, DImode and TImode */
1123 };
1125 static const
1148 in QImode, HImode and SImode.
1149 Relative to reg-reg move (2). */
1153 in SFmode, DFmode and XFmode */
1155 in SFmode, DFmode and XFmode */
1158 in SImode and DImode */
1160 in SImode and DImode */
1163 in SImode, DImode and TImode */
1165 in SImode, DImode and TImode */
1196 };
1198 /* Generic64 should produce code tuned for Nocona and K8. */
1199 static const
1202 /* On all chips taken into consideration lea is 2 cycles and more. With
1203 this cost however our current implementation of synth_mult results in
1204 use of unnecessary temporary registers causing regression on several
1205 SPECfp benchmarks. */
1226 in QImode, HImode and SImode.
1227 Relative to reg-reg move (2). */
1231 in SFmode, DFmode and XFmode */
1233 in SFmode, DFmode and XFmode */
1236 in SImode and DImode */
1238 in SImode and DImode */
1241 in SImode, DImode and TImode */
1243 in SImode, DImode and TImode */
1249 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1250 is increased to perhaps more appropriate value of 5. */
1273 };
1275 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1276 static const
1299 in QImode, HImode and SImode.
1300 Relative to reg-reg move (2). */
1304 in SFmode, DFmode and XFmode */
1306 in SFmode, DFmode and XFmode */
1309 in SImode and DImode */
1311 in SImode and DImode */
1314 in SImode, DImode and TImode */
1316 in SImode, DImode and TImode */
1330 DUMMY_STRINGOP_ALGS},
1332 DUMMY_STRINGOP_ALGS},
1344 };
1348 /* Processor feature/optimization bitmasks. */
1349 #define m_386 (1<<PROCESSOR_I386)
1350 #define m_486 (1<<PROCESSOR_I486)
1351 #define m_PENT (1<<PROCESSOR_PENTIUM)
1352 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1353 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1354 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1355 #define m_CORE2 (1<<PROCESSOR_CORE2)
1356 #define m_ATOM (1<<PROCESSOR_ATOM)
1358 #define m_GEODE (1<<PROCESSOR_GEODE)
1359 #define m_K6 (1<<PROCESSOR_K6)
1360 #define m_K6_GEODE (m_K6 | m_GEODE)
1361 #define m_K8 (1<<PROCESSOR_K8)
1362 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1363 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1364 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1365 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1366 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1)
1368 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1369 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1371 /* Generic instruction choice should be common subset of supported CPUs
1372 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1373 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1375 /* Feature tests against the various tunings. */
1378 /* Feature tests against the various tunings used to create ix86_tune_features
1379 based on the processor mask. */
1381 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1382 negatively, so enabling for Generic64 seems like good code size
1383 tradeoff. We can't enable it for 32bit generic because it does not
1384 work well with PPro base chips. */
1387 /* X86_TUNE_PUSH_MEMORY */
1391 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1394 /* X86_TUNE_UNROLL_STRLEN */
1398 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1401 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1402 on simulation result. But after P4 was made, no performance benefit
1403 was observed with branch hints. It also increases the code size.
1404 As a result, icc never generates branch hints. */
1407 /* X86_TUNE_DOUBLE_WITH_ADD */
1410 /* X86_TUNE_USE_SAHF */
1414 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1415 partial dependencies. */
1419 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1420 register stalls on Generic32 compilation setting as well. However
1421 in current implementation the partial register stalls are not eliminated
1422 very well - they can be introduced via subregs synthesized by combine
1423 and can happen in caller/callee saving sequences. Because this option
1424 pays back little on PPro based chips and is in conflict with partial reg
1425 dependencies used by Athlon/P4 based chips, it is better to leave it off
1426 for generic32 for now. */
1427 m_PPRO,
1429 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1432 /* X86_TUNE_USE_HIMODE_FIOP */
1435 /* X86_TUNE_USE_SIMODE_FIOP */
1438 /* X86_TUNE_USE_MOV0 */
1439 m_K6,
1441 /* X86_TUNE_USE_CLTD */
1444 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1445 m_PENT4,
1447 /* X86_TUNE_SPLIT_LONG_MOVES */
1448 m_PPRO,
1450 /* X86_TUNE_READ_MODIFY_WRITE */
1453 /* X86_TUNE_READ_MODIFY */
1456 /* X86_TUNE_PROMOTE_QIMODE */
1460 /* X86_TUNE_FAST_PREFIX */
1463 /* X86_TUNE_SINGLE_STRINGOP */
1466 /* X86_TUNE_QIMODE_MATH */
1469 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1470 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1471 might be considered for Generic32 if our scheme for avoiding partial
1472 stalls was more effective. */
1475 /* X86_TUNE_PROMOTE_QI_REGS */
1478 /* X86_TUNE_PROMOTE_HI_REGS */
1479 m_PPRO,
1481 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1485 /* X86_TUNE_ADD_ESP_8 */
1489 /* X86_TUNE_SUB_ESP_4 */
1493 /* X86_TUNE_SUB_ESP_8 */
1497 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1498 for DFmode copies */
1502 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1505 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1506 conflict here in between PPro/Pentium4 based chips that thread 128bit
1507 SSE registers as single units versus K8 based chips that divide SSE
1508 registers to two 64bit halves. This knob promotes all store destinations
1509 to be 128bit to allow register renaming on 128bit SSE units, but usually
1510 results in one extra microop on 64bit SSE units. Experimental results
1511 shows that disabling this option on P4 brings over 20% SPECfp regression,
1512 while enabling it on K8 brings roughly 2.4% regression that can be partly
1513 masked by careful scheduling of moves. */
1517 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1520 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1521 m_BDVER1,
1523 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1524 m_BDVER1,
1526 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1527 are resolved on SSE register parts instead of whole registers, so we may
1528 maintain just lower part of scalar values in proper format leaving the
1529 upper part undefined. */
1530 m_ATHLON_K8,
1532 /* X86_TUNE_SSE_TYPELESS_STORES */
1533 m_AMD_MULTIPLE,
1535 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1538 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1541 /* X86_TUNE_PROLOGUE_USING_MOVE */
1544 /* X86_TUNE_EPILOGUE_USING_MOVE */
1547 /* X86_TUNE_SHIFT1 */
1550 /* X86_TUNE_USE_FFREEP */
1551 m_AMD_MULTIPLE,
1553 /* X86_TUNE_INTER_UNIT_MOVES */
1556 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1559 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1560 than 4 branch instructions in the 16 byte window. */
1564 /* X86_TUNE_SCHEDULE */
1568 /* X86_TUNE_USE_BT */
1571 /* X86_TUNE_USE_INCDEC */
1574 /* X86_TUNE_PAD_RETURNS */
1577 /* X86_TUNE_EXT_80387_CONSTANTS */
1581 /* X86_TUNE_SHORTEN_X87_SSE */
1584 /* X86_TUNE_AVOID_VECTOR_DECODE */
1587 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1588 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1591 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1592 vector path on AMD machines. */
1595 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1596 machines. */
1599 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1600 than a MOV. */
1601 m_PENT,
1603 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1604 but one byte longer. */
1605 m_PENT,
1607 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1608 operand that cannot be represented using a modRM byte. The XOR
1609 replacement is long decoded, so this split helps here as well. */
1610 m_K6,
1612 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1613 from FP to FP. */
1616 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1617 from integer to FP. */
1618 m_AMDFAM10,
1620 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1621 with a subsequent conditional jump instruction into a single
1622 compare-and-branch uop. */
1625 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1626 will impact LEA instruction selection. */
1627 m_ATOM,
1628 };
1630 /* Feature tests against the various architecture variations. */
1633 /* Feature tests against the various architecture variations, used to create
1634 ix86_arch_features based on the processor mask. */
1636 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1639 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1642 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1645 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1648 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1650 };
1652 static const unsigned int x86_accumulate_outgoing_args
1656 static const unsigned int x86_arch_always_fancy_math_387
1662 /* In case the average insn count for single function invocation is
1663 lower than this constant, emit fast (but longer) prologue and
1664 epilogue code. */
1665 #define FAST_PROLOGUE_INSN_COUNT 20
1667 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1672 /* Array of the smallest class containing reg number REGNO, indexed by
1673 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1676 {
1677 /* ax, dx, cx, bx */
1679 /* si, di, bp, sp */
1681 /* FP registers */
1684 /* arg pointer */
1685 NON_Q_REGS,
1686 /* flags, fpsr, fpcr, frame */
1688 /* SSE registers */
1691 /* MMX registers */
1694 /* REX registers */
1697 /* SSE REX registers */
1700 };
1702 /* The "default" register map used in 32bit mode. */
1705 {
1713 };
1715 /* The "default" register map used in 64bit mode. */
1718 {
1726 };
1728 /* Define the register numbers to be used in Dwarf debugging information.
1729 The SVR4 reference port C compiler uses the following register numbers
1730 in its Dwarf output code:
1731 0 for %eax (gcc regno = 0)
1732 1 for %ecx (gcc regno = 2)
1733 2 for %edx (gcc regno = 1)
1734 3 for %ebx (gcc regno = 3)
1735 4 for %esp (gcc regno = 7)
1736 5 for %ebp (gcc regno = 6)
1737 6 for %esi (gcc regno = 4)
1738 7 for %edi (gcc regno = 5)
1739 The following three DWARF register numbers are never generated by
1740 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1741 believes these numbers have these meanings.
1742 8 for %eip (no gcc equivalent)
1743 9 for %eflags (gcc regno = 17)
1744 10 for %trapno (no gcc equivalent)
1745 It is not at all clear how we should number the FP stack registers
1746 for the x86 architecture. If the version of SDB on x86/svr4 were
1747 a bit less brain dead with respect to floating-point then we would
1748 have a precedent to follow with respect to DWARF register numbers
1749 for x86 FP registers, but the SDB on x86/svr4 is so completely
1750 broken with respect to FP registers that it is hardly worth thinking
1751 of it as something to strive for compatibility with.
1752 The version of x86/svr4 SDB I have at the moment does (partially)
1753 seem to believe that DWARF register number 11 is associated with
1754 the x86 register %st(0), but that's about all. Higher DWARF
1755 register numbers don't seem to be associated with anything in
1756 particular, and even for DWARF regno 11, SDB only seems to under-
1757 stand that it should say that a variable lives in %st(0) (when
1758 asked via an `=' command) if we said it was in DWARF regno 11,
1759 but SDB still prints garbage when asked for the value of the
1760 variable in question (via a `/' command).
1761 (Also note that the labels SDB prints for various FP stack regs
1762 when doing an `x' command are all wrong.)
1763 Note that these problems generally don't affect the native SVR4
1764 C compiler because it doesn't allow the use of -O with -g and
1765 because when it is *not* optimizing, it allocates a memory
1766 location for each floating-point variable, and the memory
1767 location is what gets described in the DWARF AT_location
1768 attribute for the variable in question.
1769 Regardless of the severe mental illness of the x86/svr4 SDB, we
1770 do something sensible here and we use the following DWARF
1771 register numbers. Note that these are all stack-top-relative
1772 numbers.
1773 11 for %st(0) (gcc regno = 8)
1774 12 for %st(1) (gcc regno = 9)
1775 13 for %st(2) (gcc regno = 10)
1776 14 for %st(3) (gcc regno = 11)
1777 15 for %st(4) (gcc regno = 12)
1778 16 for %st(5) (gcc regno = 13)
1779 17 for %st(6) (gcc regno = 14)
1780 18 for %st(7) (gcc regno = 15)
1781 */
1783 {
1791 };
1793 /* Test and compare insns in i386.md store the information needed to
1794 generate branch and scc insns here. */
1799 /* Define parameter passing and return registers. */
1802 {
1804 };
1807 {
1809 };
1812 {
1814 };
1816 /* Define the structure for the machine field in struct function. */
1821 rtx rtl;
1823 };
1825 /* Structure describing stack frame layout.
1826 Stack grows downward:
1828 [arguments]
1829 <- ARG_POINTER
1830 saved pc
1832 saved frame pointer if frame_pointer_needed
1833 <- HARD_FRAME_POINTER
1834 [saved regs]
1836 [padding0]
1838 [saved SSE regs]
1840 [padding1] \
1841 )
1842 [va_arg registers] (
1843 > to_allocate <- FRAME_POINTER
1844 [frame] (
1845 )
1846 [padding2] /
1847 */
1848 struct ix86_frame
1849 {
1856 HOST_WIDE_INT frame;
1860 HOST_WIDE_INT to_allocate;
1861 /* The offsets relative to ARG_POINTER. */
1862 HOST_WIDE_INT frame_pointer_offset;
1863 HOST_WIDE_INT hard_frame_pointer_offset;
1864 HOST_WIDE_INT stack_pointer_offset;
1866 /* When save_regs_using_mov is set, emit prologue using
1867 move instead of push instructions. */
1869 };
1871 /* Code model option. */
1873 /* Asm dialect. */
1875 /* TLS dialects. */
1878 /* Which unit we are generating floating point math for. */
1881 /* Which cpu are we scheduling for. */
1884 /* Which cpu are we optimizing for. */
1887 /* Which instruction set architecture to use. */
1890 /* true if sse prefetch instruction is not NOOP. */
1893 /* ix86_regparm_string as a number */
1896 /* -mstackrealign option */
1910 /* Preferred alignment for stack boundary in bits. */
1913 /* Alignment for incoming stack boundary in bits specified at
1914 command line. */
1917 /* Default alignment for incoming stack boundary in bits. */
1920 /* Alignment for incoming stack boundary in bits. */
1923 /* The abi used by target. */
1926 /* Values 1-5: see jump.c */
1929 /* Calling abi specific va_list type nodes. */
1933 /* Variables which are this size or smaller are put in the data/bss
1934 or ldata/lbss sections. */
1938 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1942 /* Fence to use after loop using movnt. */
1943 tree x86_mfence;
1945 /* Register class used for passing given 64bit part of the argument.
1946 These represent classes as documented by the PS ABI, with the exception
1947 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1948 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1950 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1951 whenever possible (upper half does contain padding). */
1952 enum x86_64_reg_class
1953 {
1954 X86_64_NO_CLASS,
1955 X86_64_INTEGER_CLASS,
1956 X86_64_INTEGERSI_CLASS,
1957 X86_64_SSE_CLASS,
1958 X86_64_SSESF_CLASS,
1959 X86_64_SSEDF_CLASS,
1960 X86_64_SSEUP_CLASS,
1961 X86_64_X87_CLASS,
1962 X86_64_X87UP_CLASS,
1963 X86_64_COMPLEX_X87_CLASS,
1964 X86_64_MEMORY_CLASS
1965 };
1967 #define MAX_CLASSES 4
1969 /* Table of constants used by fldpi, fldln2, etc.... */
1973 \f
1986 enum ix86_function_specific_strings
1987 {
1988 IX86_FUNCTION_SPECIFIC_ARCH,
1989 IX86_FUNCTION_SPECIFIC_TUNE,
1990 IX86_FUNCTION_SPECIFIC_FPMATH,
1991 IX86_FUNCTION_SPECIFIC_MAX
1992 };
2009 \f
2010 #ifndef SUBTARGET32_DEFAULT_CPU
2012 #endif
2014 /* The svr4 ABI for the i386 says that records and unions are returned
2015 in memory. */
2016 #ifndef DEFAULT_PCC_STRUCT_RETURN
2017 #define DEFAULT_PCC_STRUCT_RETURN 1
2018 #endif
2020 /* Whether -mtune= or -march= were specified */
2024 /* Bit flags that specify the ISA we are compiling for. */
2027 /* A mask of ix86_isa_flags that includes bit X if X
2028 was set or cleared on the command line. */
2031 /* Define a set of ISAs which are available when a given ISA is
2032 enabled. MMX and SSE ISAs are handled separately. */
2034 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
2035 #define OPTION_MASK_ISA_3DNOW_SET \
2036 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
2038 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
2039 #define OPTION_MASK_ISA_SSE2_SET \
2040 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
2041 #define OPTION_MASK_ISA_SSE3_SET \
2042 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
2043 #define OPTION_MASK_ISA_SSSE3_SET \
2044 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
2045 #define OPTION_MASK_ISA_SSE4_1_SET \
2046 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
2047 #define OPTION_MASK_ISA_SSE4_2_SET \
2048 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
2049 #define OPTION_MASK_ISA_AVX_SET \
2050 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
2051 #define OPTION_MASK_ISA_FMA_SET \
2052 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
2054 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
2055 as -msse4.2. */
2056 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
2058 #define OPTION_MASK_ISA_SSE4A_SET \
2059 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
2060 #define OPTION_MASK_ISA_FMA4_SET \
2061 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
2062 | OPTION_MASK_ISA_AVX_SET)
2063 #define OPTION_MASK_ISA_XOP_SET \
2064 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
2065 #define OPTION_MASK_ISA_LWP_SET \
2066 OPTION_MASK_ISA_LWP
2068 /* AES and PCLMUL need SSE2 because they use xmm registers */
2069 #define OPTION_MASK_ISA_AES_SET \
2070 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
2071 #define OPTION_MASK_ISA_PCLMUL_SET \
2072 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
2074 #define OPTION_MASK_ISA_ABM_SET \
2075 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
2077 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
2078 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
2079 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
2080 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
2081 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
2083 /* Define a set of ISAs which aren't available when a given ISA is
2084 disabled. MMX and SSE ISAs are handled separately. */
2086 #define OPTION_MASK_ISA_MMX_UNSET \
2087 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
2088 #define OPTION_MASK_ISA_3DNOW_UNSET \
2089 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
2090 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
2092 #define OPTION_MASK_ISA_SSE_UNSET \
2093 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
2094 #define OPTION_MASK_ISA_SSE2_UNSET \
2095 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2096 #define OPTION_MASK_ISA_SSE3_UNSET \
2097 (OPTION_MASK_ISA_SSE3 \
2098 | OPTION_MASK_ISA_SSSE3_UNSET \
2099 | OPTION_MASK_ISA_SSE4A_UNSET )
2100 #define OPTION_MASK_ISA_SSSE3_UNSET \
2101 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2102 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2103 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2104 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2105 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2106 #define OPTION_MASK_ISA_AVX_UNSET \
2107 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2108 | OPTION_MASK_ISA_FMA4_UNSET)
2109 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2111 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2112 as -mno-sse4.1. */
2113 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2115 #define OPTION_MASK_ISA_SSE4A_UNSET \
2116 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2118 #define OPTION_MASK_ISA_FMA4_UNSET \
2119 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2120 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2121 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2123 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2124 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2125 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2126 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2127 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2128 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2129 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2130 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2132 /* Vectorization library interface and handlers. */
2137 /* Processor target table, indexed by processor number */
2138 struct ptt
2139 {
2146 };
2149 {
2166 };
2169 {
2192 "bdver1"
2193 };
2194 \f
2195 /* Implement TARGET_HANDLE_OPTION. */
2197 static bool
2199 {
2201 {
2204 {
2207 }
2208 else
2209 {
2212 }
2217 {
2220 }
2221 else
2222 {
2225 }
2233 {
2236 }
2237 else
2238 {
2241 }
2246 {
2249 }
2250 else
2251 {
2254 }
2259 {
2262 }
2263 else
2264 {
2267 }
2272 {
2275 }
2276 else
2277 {
2280 }
2285 {
2288 }
2289 else
2290 {
2293 }
2298 {
2301 }
2302 else
2303 {
2306 }
2311 {
2314 }
2315 else
2316 {
2319 }
2324 {
2327 }
2328 else
2329 {
2332 }
2347 {
2350 }
2351 else
2352 {
2355 }
2360 {
2363 }
2364 else
2365 {
2368 }
2373 {
2376 }
2377 else
2378 {
2381 }
2386 {
2389 }
2390 else
2391 {
2394 }
2399 {
2402 }
2403 else
2404 {
2407 }
2412 {
2415 }
2416 else
2417 {
2420 }
2425 {
2428 }
2429 else
2430 {
2433 }
2438 {
2441 }
2442 else
2443 {
2446 }
2451 {
2454 }
2455 else
2456 {
2459 }
2464 {
2467 }
2468 else
2469 {
2472 }
2477 {
2480 }
2481 else
2482 {
2485 }
2490 {
2493 }
2494 else
2495 {
2498 }
2503 }
2504 }
2505 \f
2506 /* Return a string that documents the current -m options. The caller is
2507 responsible for freeing the string. */
2512 {
2513 struct ix86_target_opts
2514 {
2517 };
2519 /* This table is ordered so that options like -msse4.2 that imply
2520 preceding options while match those first. */
2522 {
2544 };
2546 /* Flag options. */
2548 {
2569 };
2585 /* Add -march= option. */
2587 {
2590 }
2592 /* Add -mtune= option. */
2594 {
2597 }
2599 /* Pick out the options in isa options. */
2601 {
2603 {
2606 }
2607 }
2610 {
2613 }
2615 /* Add flag options. */
2617 {
2619 {
2622 }
2623 }
2626 {
2629 }
2631 /* Add -fpmath= option. */
2633 {
2636 }
2638 /* Any options? */
2644 /* Size the string. */
2648 {
2653 }
2655 /* Build the string. */
2660 {
2667 {
2669 line_len++;
2672 {
2676 }
2677 }
2681 {
2685 }
2686 }
2692 }
2694 /* Return TRUE if software prefetching is beneficial for the
2695 given CPU. */
2697 static bool
2699 {
2701 {
2711 }
2712 }
2714 /* Function that is callable from the debugger to print the current
2715 options. */
2716 void
2718 {
2724 {
2727 }
2728 else
2732 }
2733 \f
2734 /* Sometimes certain combinations of command options do not make
2735 sense on a particular target machine. You can define a macro
2736 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2737 defined, is executed once just after all the command options have
2738 been parsed.
2740 Don't use this macro to turn on various extra optimizations for
2741 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2743 void
2745 {
2753 /* Comes from final.c -- no real reason to change it. */
2754 #define MAX_CODE_ALIGN 16
2756 enum pta_flags
2757 {
2782 };
2784 static struct pta
2785 {
2790 }
2792 {
2879 };
2883 /* Set up prefix/suffix so the error messages refer to either the command
2884 line argument, or the attribute(target). */
2886 {
2890 }
2891 else
2892 {
2896 }
2898 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2899 SUBTARGET_OVERRIDE_OPTIONS;
2900 #endif
2902 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2903 SUBSUBTARGET_OVERRIDE_OPTIONS;
2904 #endif
2906 /* -fPIC is the default for x86_64. */
2910 /* Set the default values for switches whose default depends on TARGET_64BIT
2911 in case they weren't overwritten by command line options. */
2913 {
2916 /* Mach-O doesn't support omitting the frame pointer for now. */
2923 }
2924 else
2925 {
2934 }
2936 /* Need to check -mtune=generic first. */
2938 {
2941 /* As special support for cross compilers we read -mtune=native
2942 as -mtune=generic. With native compilers we won't see the
2943 -mtune=native, as it was changed by the driver. */
2945 {
2948 else
2950 }
2951 /* If this call is for setting the option attribute, allow the
2952 generic32/generic64 that was previously set. */
2956 ;
2964 }
2965 else
2966 {
2970 {
2973 }
2975 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2976 need to use a sensible tune option. */
2980 {
2983 else
2985 }
2986 }
2989 {
2998 /* rep; movq isn't available in 32-bit code. */
3006 else
3009 }
3013 else
3016 /* Validate -mabi= value. */
3018 {
3023 else
3026 }
3027 else
3031 {
3044 else
3047 }
3048 else
3049 {
3050 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3051 use of rip-relative addressing. This eliminates fixups that
3052 would otherwise be needed if this object is to be placed in a
3053 DLL, and is essentially just as efficient as direct addressing. */
3058 else
3060 }
3062 {
3068 else
3071 }
3081 {
3084 /* Default cpu tuning to the architecture. */
3161 }
3176 {
3180 {
3182 {
3190 }
3191 else
3194 }
3195 /* Intel CPUs have always interpreted SSE prefetch instructions as
3196 NOPs; so, we can enable SSE prefetch instructions even when
3197 -mtune (rather than -march) points us to a processor that has them.
3198 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3199 higher processors. */
3204 }
3216 else
3219 /* Arrange to set up i386_stack_locals for all functions. */
3222 /* Validate -mregparm= value. */
3224 {
3231 else
3233 }
3237 /* If the user has provided any of the -malign-* options,
3238 warn and use that value only if -falign-* is not set.
3239 Remove this code in GCC 3.2 or later. */
3241 {
3245 {
3250 else
3252 }
3253 }
3256 {
3260 {
3265 else
3267 }
3268 }
3271 {
3275 {
3280 else
3282 }
3283 }
3285 /* Default align_* from the processor table. */
3287 {
3290 }
3292 {
3295 }
3297 {
3299 }
3301 /* Validate -mbranch-cost= value, or provide default. */
3304 {
3308 else
3310 }
3312 {
3316 else
3318 }
3321 {
3326 else
3329 }
3332 {
3336 }
3339 {
3342 /* Enable by default the SSE and MMX builtins. Do allow the user to
3343 explicitly disable any of these. In particular, disabling SSE and
3344 MMX for kernel code is extremely useful. */
3346 ix86_isa_flags
3352 }
3353 else
3354 {
3358 ix86_isa_flags
3361 /* i386 ABI does not specify red zone. It still makes sense to use it
3362 when programmer takes care to stack from being destroyed. */
3365 }
3367 /* Keep nonleaf frame pointers. */
3373 /* If we're doing fast math, we don't care about comparison order
3374 wrt NaNs. This lets us use a shorter comparison sequence. */
3378 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3379 since the insns won't need emulation. */
3383 /* Likewise, if the target doesn't have a 387, or we've specified
3384 software floating point, don't use 387 inline intrinsics. */
3388 /* Turn on MMX builtins for -msse. */
3390 {
3393 }
3395 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3399 /* Validate -mpreferred-stack-boundary= value or default it to
3400 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3403 {
3408 else
3410 }
3412 /* Set the default value for -mstackrealign. */
3418 /* Validate -mincoming-stack-boundary= value or default it to
3419 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3422 {
3427 else
3428 {
3430 ix86_incoming_stack_boundary
3432 }
3433 }
3435 /* Accept -msseregparm only if at least SSE support is enabled. */
3442 {
3446 {
3448 {
3451 }
3452 else
3454 }
3460 {
3462 {
3465 }
3467 {
3470 }
3471 else
3473 }
3474 else
3477 }
3479 /* If the i387 is disabled, then do not return values in it. */
3483 /* Use external vectorized library in vectorizing intrinsics. */
3485 {
3490 else
3494 }
3501 /* ??? Unwind info is not correct around the CFG unless either a frame
3502 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3503 unwind info generation to be aware of the CFG and propagating states
3504 around edges. */
3507 && flag_omit_frame_pointer
3509 {
3515 }
3517 /* If stack probes are required, the space used for large function
3518 arguments on the stack must also be probed, so enable
3519 -maccumulate-outgoing-args so this happens in the prologue. */
3522 {
3527 }
3529 /* For sane SSE instruction set generation we need fcomi instruction.
3530 It is safe to enable all CMOVE instructions. */
3534 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3535 {
3541 }
3543 /* When scheduling description is not available, disable scheduler pass
3544 so it won't slow down the compilation and make x87 code slower. */
3558 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3560 && HAVE_prefetch
3565 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3566 can be optimized to ap = __builtin_next_arg (0). */
3571 {
3580 }
3581 else
3582 {
3591 }
3593 #ifdef USE_IX86_CLD
3594 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3597 #endif
3599 /* Save the initial options in case the user does function specific options */
3601 target_option_default_node = target_option_current_node
3603 }
3605 /* Update register usage after having seen the compiler flags. */
3607 void
3609 {
3614 {
3619 }
3621 /* The PIC register, if it exists, is fixed. */
3626 /* The MS_ABI changes the set of call-used registers. */
3628 {
3635 }
3637 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3638 other call-clobbered regs for 64-bit. */
3640 {
3647 }
3649 /* If MMX is disabled, squash the registers. */
3655 /* If SSE is disabled, squash the registers. */
3661 /* If the FPU is disabled, squash the registers. */
3667 /* If 32-bit, squash the 64-bit registers. */
3669 {
3674 }
3675 }
3677 \f
3678 /* Save the current options */
3680 static void
3682 {
3693 /* The fields are char but the variables are not; make sure the
3694 values fit in the fields. */
3700 }
3702 /* Restore the current options */
3704 static void
3706 {
3722 /* Recreate the arch feature tests if the arch changed */
3724 {
3729 }
3731 /* Recreate the tune optimization tests */
3733 {
3738 }
3739 }
3741 /* Print the current options */
3743 static void
3746 {
3771 {
3774 }
3775 }
3777 \f
3778 /* Inner function to process the attribute((target(...))), take an argument and
3779 set the current options from the argument. If we have a list, recursively go
3780 over the list. */
3782 static bool
3784 {
3788 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3789 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3790 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3791 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3793 enum ix86_opt_type
3794 {
3795 ix86_opt_unknown,
3796 ix86_opt_yes,
3797 ix86_opt_no,
3798 ix86_opt_str,
3799 ix86_opt_isa
3800 };
3802 static const struct
3803 {
3810 /* isa options */
3830 /* string options */
3835 /* flag options */
3837 OPT_mcld,
3838 MASK_CLD),
3841 OPT_mfancy_math_387,
3842 MASK_NO_FANCY_MATH_387),
3845 OPT_mieee_fp,
3846 MASK_IEEE_FP),
3849 OPT_minline_all_stringops,
3850 MASK_INLINE_ALL_STRINGOPS),
3853 OPT_minline_stringops_dynamically,
3854 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3857 OPT_mno_align_stringops,
3858 MASK_NO_ALIGN_STRINGOPS),
3861 OPT_mrecip,
3862 MASK_RECIP),
3864 };
3866 /* If this is a list, recurse to get the options. */
3868 {
3877 }
3882 /* Handle multiple arguments separated by commas. */
3886 {
3900 {
3904 }
3905 else
3906 {
3909 }
3911 /* Recognize no-xxx. */
3913 {
3917 }
3918 else
3921 /* Find the option. */
3925 {
3931 {
3936 }
3937 }
3939 /* Process the option. */
3941 {
3944 }
3950 {
3956 else
3958 }
3961 {
3963 {
3966 }
3967 else
3969 }
3971 else
3973 }
3976 }
3978 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3980 tree
3982 {
3994 /* Process each of the options on the chain. */
3998 /* If the changed options are different from the default, rerun override_options,
3999 and then save the options away. The string options are are attribute options,
4000 and will be undone when we copy the save structure. */
4006 {
4007 /* If we are using the default tune= or arch=, undo the string assigned,
4008 and use the default. */
4019 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4025 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4028 /* Add any builtin functions with the new isa if any. */
4031 /* Save the current options unless we are validating options for
4032 #pragma. */
4039 /* Free up memory allocated to hold the strings */
4043 }
4046 }
4048 /* Hook to validate attribute((target("string"))). */
4050 static bool
4053 tree args,
4055 {
4062 /* If the function changed the optimization levels as well as setting target
4063 options, start with the optimizations specified. */
4067 /* The target attributes may also change some optimization flags, so update
4068 the optimization options if necessary. */
4077 {
4082 }
4090 }
4092 \f
4093 /* Hook to determine if one function can safely inline another. */
4095 static bool
4097 {
4102 /* If callee has no option attributes, then it is ok to inline. */
4106 /* If caller has no option attributes, but callee does then it is not ok to
4107 inline. */
4111 else
4112 {
4116 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4117 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4118 function. */
4123 /* See if we have the same non-isa options. */
4127 /* See if arch, tune, etc. are the same. */
4140 else
4142 }
4145 }
4147 \f
4148 /* Remember the last target of ix86_set_current_function. */
4151 /* Establish appropriate back-end context for processing the function
4152 FNDECL. The argument might be NULL to indicate processing at top
4153 level, outside of any function scope. */
4154 static void
4156 {
4157 /* Only change the context if the function changes. This hook is called
4158 several times in the course of compiling a function, and we don't want to
4159 slow things down too much or call target_reinit when it isn't safe. */
4161 {
4162 tree old_tree = (ix86_previous_fndecl
4166 tree new_tree = (fndecl
4172 ;
4175 {
4178 }
4181 {
4187 }
4188 }
4189 }
4191 \f
4192 /* Return true if this goes in large data/bss. */
4194 static bool
4196 {
4200 /* Functions are never large data. */
4205 {
4211 }
4212 else
4213 {
4216 /* If this is an incomplete type with size 0, then we can't put it
4217 in data because it might be too big when completed. */
4220 }
4223 }
4225 /* Switch to the appropriate section for output of DECL.
4226 DECL is either a `VAR_DECL' node or a constant of some sort.
4227 RELOC indicates whether forming the initial value of DECL requires
4228 link-time relocations. */
4231 ATTRIBUTE_UNUSED;
4236 {
4239 {
4243 {
4277 /* We don't split these for medium model. Place them into
4278 default sections and hope for best. */
4283 }
4285 {
4286 /* We might get called with string constants, but get_named_section
4287 doesn't like them as they are not DECLs. Also, we need to set
4288 flags in that case. */
4292 }
4293 }
4295 }
4297 /* Build up a unique section name, expressed as a
4298 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4299 RELOC indicates whether the initial value of EXP requires
4300 link-time relocations. */
4302 static void ATTRIBUTE_UNUSED
4304 {
4307 {
4309 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4313 {
4337 /* We don't split these for medium model. Place them into
4338 default sections and hope for best. */
4346 }
4348 {
4355 /* If we're using one_only, then there needs to be a .gnu.linkonce
4356 prefix to the section name. */
4363 }
4364 }
4366 }
4368 #ifdef COMMON_ASM_OP
4369 /* This says how to output assembler code to declare an
4370 uninitialized external linkage data object.
4372 For medium model x86-64 we need to use .largecomm opcode for
4373 large objects. */
4374 void
4378 {
4382 else
4387 }
4388 #endif
4390 /* Utility function for targets to use in implementing
4391 ASM_OUTPUT_ALIGNED_BSS. */
4393 void
4397 {
4401 else
4404 #ifdef ASM_DECLARE_OBJECT_NAME
4407 #else
4408 /* Standard thing is just output label for the object. */
4412 }
4413 \f
4414 void
4416 {
4417 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4418 make the problem with not enough registers even worse. */
4419 #ifdef INSN_SCHEDULING
4422 #endif
4425 /* The Darwin libraries never set errno, so we might as well
4426 avoid calling them when that's the only reason we would. */
4429 /* The default values of these switches depend on the TARGET_64BIT
4430 that is not known at this moment. Mark these values with 2 and
4431 let user the to override these. In case there is no command line option
4432 specifying them, we will set the defaults in override_options. */
4436 /* For -O2 and beyond, turn on -fzee for x86_64 target. */
4443 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4444 SUBTARGET_OPTIMIZATION_OPTIONS;
4445 #endif
4446 }
4447 \f
4448 /* Decide whether we can make a sibling call to a function. DECL is the
4449 declaration of the function being targeted by the call and EXP is the
4450 CALL_EXPR representing the call. */
4452 static bool
4454 {
4458 /* If we are generating position-independent code, we cannot sibcall
4459 optimize any indirect call, or a direct call to a global function,
4460 as the PLT requires %ebx be live. */
4464 /* If we need to align the outgoing stack, then sibcalling would
4465 unalign the stack, which may break the called function. */
4471 {
4474 }
4475 else
4476 {
4477 /* We're looking at the CALL_EXPR, we need the type of the function. */
4482 }
4484 /* Check that the return value locations are the same. Like
4485 if we are returning floats on the 80387 register stack, we cannot
4486 make a sibcall from a function that doesn't return a float to a
4487 function that does or, conversely, from a function that does return
4488 a float to a function that doesn't; the necessary stack adjustment
4489 would not be executed. This is also the place we notice
4490 differences in the return value ABI. Note that it is ok for one
4491 of the functions to have void return type as long as the return
4492 value of the other is passed in a register. */
4497 {
4500 }
4502 ;
4507 {
4508 /* The SYSV ABI has more call-clobbered registers;
4509 disallow sibcalls from MS to SYSV. */
4513 }
4514 else
4515 {
4516 /* If this call is indirect, we'll need to be able to use a
4517 call-clobbered register for the address of the target function.
4518 Make sure that all such registers are not used for passing
4519 parameters. Note that DLLIMPORT functions are indirect. */
4522 {
4524 {
4525 /* ??? Need to count the actual number of registers to be used,
4526 not the possible number of registers. Fix later. */
4528 }
4529 }
4530 }
4532 /* Otherwise okay. That also includes certain types of indirect calls. */
4534 }
4536 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4537 and "sseregparm" calling convention attributes;
4538 arguments as in struct attribute_spec.handler. */
4540 static tree
4542 tree args,
4545 {
4550 {
4552 name);
4555 }
4557 /* Can combine regparm with all attributes but fastcall. */
4559 {
4560 tree cst;
4563 {
4565 }
4568 {
4570 }
4574 {
4577 name);
4579 }
4581 {
4585 }
4588 }
4591 {
4592 /* Do not warn when emulating the MS ABI. */
4597 name);
4600 }
4602 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4604 {
4606 {
4608 }
4610 {
4612 }
4614 {
4616 }
4618 {
4620 }
4621 }
4623 /* Can combine stdcall with fastcall (redundant), regparm and
4624 sseregparm. */
4626 {
4628 {
4630 }
4632 {
4634 }
4636 {
4638 }
4639 }
4641 /* Can combine cdecl with regparm and sseregparm. */
4643 {
4645 {
4647 }
4649 {
4651 }
4653 {
4655 }
4656 }
4658 {
4661 name);
4663 {
4665 }
4667 {
4669 }
4671 {
4673 }
4674 }
4676 /* Can combine sseregparm with all attributes. */
4679 }
4681 /* Return 0 if the attributes for two types are incompatible, 1 if they
4682 are compatible, and 2 if they are nearly compatible (which causes a
4683 warning to be generated). */
4685 static int
4687 {
4688 /* Check for mismatch of non-default calling convention. */
4695 /* Check for mismatched fastcall/regparm types. */
4702 /* Check for mismatched sseregparm types. */
4707 /* Check for mismatched thiscall types. */
4712 /* Check for mismatched return types (cdecl vs stdcall). */
4718 }
4719 \f
4720 /* Return the regparm value for a function with the indicated TYPE and DECL.
4721 DECL may be NULL when calling function indirectly
4722 or considering a libcall. */
4724 static int
4726 {
4727 tree attr;
4737 {
4740 }
4748 /* Use register calling convention for local functions when possible. */
4751 && optimize
4753 {
4754 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4757 {
4760 /* Make sure no regparm register is taken by a
4761 fixed register variable. */
4766 /* We don't want to use regparm(3) for nested functions as
4767 these use a static chain pointer in the third argument. */
4771 /* Each fixed register usage increases register pressure,
4772 so less registers should be used for argument passing.
4773 This functionality can be overriden by an explicit
4774 regparm value. */
4777 globals++;
4779 local_regparm
4784 }
4785 }
4788 }
4790 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4791 DFmode (2) arguments in SSE registers for a function with the
4792 indicated TYPE and DECL. DECL may be NULL when calling function
4793 indirectly or considering a libcall. Otherwise return 0. */
4795 static int
4797 {
4800 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4801 by the sseregparm attribute. */
4804 {
4806 {
4808 {
4812 else
4815 }
4817 }
4820 }
4822 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4823 (and DFmode for SSE2) arguments in SSE registers. */
4825 {
4826 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4830 }
4833 }
4835 /* Return true if EAX is live at the start of the function. Used by
4836 ix86_expand_prologue to determine if we need special help before
4837 calling allocate_stack_worker. */
4839 static bool
4841 {
4842 /* Cheat. Don't bother working forward from ix86_function_regparm
4843 to the function type to whether an actual argument is located in
4844 eax. Instead just look at cfg info, which is still close enough
4845 to correct at this point. This gives false positives for broken
4846 functions that might use uninitialized data that happens to be
4847 allocated in eax, but who cares? */
4849 }
4851 /* Value is the number of bytes of arguments automatically
4852 popped when returning from a subroutine call.
4853 FUNDECL is the declaration node of the function (as a tree),
4854 FUNTYPE is the data type of the function (as a tree),
4855 or for a library call it is an identifier node for the subroutine name.
4856 SIZE is the number of bytes of arguments passed on the stack.
4858 On the 80386, the RTD insn may be used to pop them if the number
4859 of args is fixed, but if the number is variable then the caller
4860 must pop them all. RTD can't be used for library calls now
4861 because the library is compiled with the Unix compiler.
4862 Use of RTD is a selectable option, since it is incompatible with
4863 standard Unix calling sequences. If the option is not selected,
4864 the caller must always pop the args.
4866 The attribute stdcall is equivalent to RTD on a per module basis. */
4868 static int
4870 {
4873 /* None of the 64-bit ABIs pop arguments. */
4879 /* Cdecl functions override -mrtd, and never pop the stack. */
4881 {
4882 /* Stdcall and fastcall functions will pop the stack if not
4883 variable args. */
4891 }
4893 /* Lose any fake structure return argument if it is passed on the stack. */
4896 {
4900 }
4903 }
4904 \f
4905 /* Argument support functions. */
4907 /* Return true when register may be used to pass function parameters. */
4908 bool
4910 {
4915 {
4919 else
4925 }
4928 {
4931 }
4932 else
4933 {
4937 }
4939 /* TODO: The function should depend on current function ABI but
4940 builtins.c would need updating then. Therefore we use the
4941 default ABI. */
4943 /* RAX is used as hidden argument to va_arg functions. */
4949 else
4956 }
4958 /* Return if we do not know how to pass TYPE solely in registers. */
4960 static bool
4962 {
4966 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4967 The layout_type routine is crafty and tries to trick us into passing
4968 currently unsupported vector types on the stack by using TImode. */
4971 }
4973 /* It returns the size, in bytes, of the area reserved for arguments passed
4974 in registers for the function represented by fndecl dependent to the used
4975 abi format. */
4976 int
4978 {
4982 else
4987 }
4989 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4990 call abi used. */
4991 enum calling_abi
4993 {
4995 {
4998 {
5001 }
5005 }
5007 }
5009 static bool
5011 {
5013 {
5015 {
5017 {
5020 }
5023 }
5024 }
5026 }
5028 static enum calling_abi
5030 {
5034 }
5036 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5037 call abi used. */
5038 enum calling_abi
5040 {
5044 }
5046 /* regclass.c */
5049 /* Implementation of call abi switching target hook. Specific to FNDECL
5050 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
5051 for more details. */
5052 void
5054 {
5057 else
5059 }
5061 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
5062 re-initialization of init_regs each time we switch function context since
5063 this is needed only during RTL expansion. */
5064 static void
5066 {
5070 }
5072 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5073 for a call to a function whose data type is FNTYPE.
5074 For a library call, FNTYPE is 0. */
5076 void
5080 tree fndecl)
5081 {
5087 else
5089 /* Set up the number of registers to use for passing arguments. */
5096 {
5098 ? X86_64_REGPARM_MAX
5100 }
5102 {
5105 {
5107 ? X86_64_SSE_REGPARM_MAX
5109 }
5110 }
5117 /* Because type might mismatch in between caller and callee, we need to
5118 use actual type of function for local calls.
5119 FIXME: cgraph_analyze can be told to actually record if function uses
5120 va_start so for local functions maybe_vaarg can be made aggressive
5121 helping K&R code.
5122 FIXME: once typesytem is fixed, we won't need this code anymore. */
5130 {
5131 /* If there are variable arguments, then we won't pass anything
5132 in registers in 32-bit mode. */
5134 {
5142 }
5144 /* Use ecx and edx registers if function has fastcall attribute,
5145 else look for regparm information. */
5147 {
5149 {
5152 }
5154 {
5157 }
5158 else
5160 }
5162 /* Set up the number of SSE registers used for passing SFmode
5163 and DFmode arguments. Warn for mismatching ABI. */
5165 }
5166 }
5168 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5169 But in the case of vector types, it is some vector mode.
5171 When we have only some of our vector isa extensions enabled, then there
5172 are some modes for which vector_mode_supported_p is false. For these
5173 modes, the generic vector support in gcc will choose some non-vector mode
5174 in order to implement the type. By computing the natural mode, we'll
5175 select the proper ABI location for the operand and not depend on whatever
5176 the middle-end decides to do with these vector types.
5178 The midde-end can't deal with the vector types > 16 bytes. In this
5179 case, we return the original mode and warn ABI change if CUM isn't
5180 NULL. */
5182 static enum machine_mode
5184 {
5188 {
5191 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5193 {
5198 else
5201 /* Get the mode which has this inner mode and number of units. */
5205 {
5207 {
5211 && !warnedavx
5213 {
5217 }
5219 }
5220 else
5222 }
5225 }
5226 }
5229 }
5231 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5232 this may not agree with the mode that the type system has chosen for the
5233 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5234 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5236 static rtx
5239 {
5240 rtx tmp;
5244 else
5245 {
5249 }
5252 }
5254 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5255 of this code is to classify each 8bytes of incoming argument by the register
5256 class and assign registers accordingly. */
5258 /* Return the union class of CLASS1 and CLASS2.
5259 See the x86-64 PS ABI for details. */
5261 static enum x86_64_reg_class
5263 {
5264 /* Rule #1: If both classes are equal, this is the resulting class. */
5268 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5269 the other class. */
5275 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5279 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5287 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5288 MEMORY is used. */
5297 /* Rule #6: Otherwise class SSE is used. */
5299 }
5301 /* Classify the argument of type TYPE and mode MODE.
5302 CLASSES will be filled by the register class used to pass each word
5303 of the operand. The number of words is returned. In case the parameter
5304 should be passed in memory, 0 is returned. As a special case for zero
5305 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5307 BIT_OFFSET is used internally for handling records and specifies offset
5308 of the offset in bits modulo 256 to avoid overflow cases.
5310 See the x86-64 PS ABI for details.
5311 */
5313 static int
5316 {
5317 HOST_WIDE_INT bytes =
5321 /* Variable sized entities are always passed/returned in memory. */
5330 {
5332 tree field;
5335 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5342 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5343 signalize memory class, so handle it as special case. */
5345 {
5348 }
5350 /* Classify each field of record and merge classes. */
5352 {
5354 /* And now merge the fields of structure. */
5356 {
5358 {
5364 /* Bitfields are always classified as integer. Handle them
5365 early, since later code would consider them to be
5366 misaligned integers. */
5368 {
5376 }
5377 else
5378 {
5383 /* Flexible array member is ignored. */
5390 {
5394 {
5397 "The ABI of passing struct with"
5398 " a flexible array member has"
5400 }
5402 }
5404 subclasses,
5413 }
5414 }
5415 }
5419 /* Arrays are handled as small records. */
5420 {
5427 /* The partial classes are now full classes. */
5438 }
5441 /* Unions are similar to RECORD_TYPE but offset is always 0.
5442 */
5444 {
5446 {
5454 bit_offset);
5459 }
5460 }
5465 }
5468 {
5469 /* When size > 16 bytes, if the first one isn't
5470 X86_64_SSE_CLASS or any other ones aren't
5471 X86_64_SSEUP_CLASS, everything should be passed in
5472 memory. */
5479 }
5481 /* Final merger cleanup. */
5483 {
5484 /* If one class is MEMORY, everything should be passed in
5485 memory. */
5489 /* The X86_64_SSEUP_CLASS should be always preceded by
5490 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5494 {
5495 /* The first one should never be X86_64_SSEUP_CLASS. */
5498 }
5500 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5501 everything should be passed in memory. */
5504 {
5507 /* The first one should never be X86_64_X87UP_CLASS. */
5510 {
5513 "The ABI of passing union with long double"
5515 }
5517 }
5518 }
5520 }
5522 /* Compute alignment needed. We align all types to natural boundaries with
5523 exception of XFmode that is aligned to 64bits. */
5525 {
5534 /* Misaligned fields are always returned in memory. */
5537 }
5539 /* for V1xx modes, just use the base mode */
5544 /* Classification of atomic types. */
5546 {
5562 {
5566 {
5569 }
5571 {
5574 }
5576 {
5580 }
5582 {
5585 }
5586 else
5588 }
5595 /* OImode shouldn't be used directly. */
5602 else
5620 else
5621 {
5625 {
5628 "The ABI of passing structure with complex float"
5630 }
5633 }
5642 /* This modes is larger than 16 bytes. */
5685 else
5689 }
5690 }
5692 /* Examine the argument and return set number of register required in each
5693 class. Return 0 iff parameter should be passed in memory. */
5694 static int
5697 {
5707 {
5729 }
5731 }
5733 /* Construct container for the argument used by GCC interface. See
5734 FUNCTION_ARG for the detailed description. */
5736 static rtx
5740 {
5741 /* The following variables hold the static issued_error state. */
5755 rtx ret;
5766 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5767 some less clueful developer tries to use floating-point anyway. */
5769 {
5771 {
5773 {
5776 }
5777 }
5779 {
5782 }
5784 }
5786 /* Likewise, error if the ABI requires us to return values in the
5787 x87 registers and the user specified -mno-80387. */
5793 {
5795 {
5798 }
5800 }
5802 /* First construct simple cases. Avoid SCmode, since we want to use
5803 single register to pass this type. */
5806 {
5821 /* Zero sized array, struct or class. */
5825 }
5846 /* Otherwise figure out the entries of the PARALLEL. */
5848 {
5852 {
5857 /* Merge TImodes on aligned occasions here too. */
5862 else
5864 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5870 intreg++;
5877 sse_regno++;
5884 sse_regno++;
5889 {
5895 {
5897 i++;
5898 }
5899 else
5912 }
5917 sse_regno++;
5921 }
5922 }
5924 /* Empty aligned struct, union or class. */
5932 }
5934 /* Update the data in CUM to advance over an argument of mode MODE
5935 and data type TYPE. (TYPE is null for libcalls where that information
5936 may not be available.) */
5938 static void
5941 HOST_WIDE_INT words)
5942 {
5944 {
5951 /* FALLTHRU */
5962 {
5965 }
5969 /* OImode shouldn't be used directly. */
5978 /* FALLTHRU */
5994 {
5999 {
6002 }
6003 }
6013 {
6018 {
6021 }
6022 }
6024 }
6025 }
6027 static void
6030 {
6033 /* Unnamed 256bit vector mode parameters are passed on stack. */
6040 {
6045 }
6046 else
6048 }
6050 static void
6052 HOST_WIDE_INT words)
6053 {
6054 /* Otherwise, this should be passed indirect. */
6059 {
6062 }
6063 }
6065 /* Update the data in CUM to advance over an argument of mode MODE and
6066 data type TYPE. (TYPE is null for libcalls where that information
6067 may not be available.) */
6069 static void
6072 {
6077 else
6088 else
6090 }
6092 /* Define where to put the arguments to a function.
6093 Value is zero to push the argument on the stack,
6094 or a hard register in which to store the argument.
6096 MODE is the argument's machine mode.
6097 TYPE is the data type of the argument (as a tree).
6098 This is null for libcalls where that information may
6099 not be available.
6100 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6101 the preceding args and about the function being called.
6102 NAMED is nonzero if this argument is a named parameter
6103 (otherwise it is an extra parameter matching an ellipsis). */
6105 static rtx
6109 {
6112 /* Avoid the AL settings for the Unix64 ABI. */
6117 {
6124 /* FALLTHRU */
6130 {
6133 /* Fastcall allocates the first two DWORD (SImode) or
6134 smaller arguments to ECX and EDX if it isn't an
6135 aggregate type . */
6137 {
6143 /* ECX not EAX is the first allocated register. */
6146 }
6148 }
6157 /* FALLTHRU */
6159 /* In 32bit, we pass TImode in xmm registers. */
6167 {
6169 {
6173 }
6177 }
6181 /* OImode shouldn't be used directly. */
6191 {
6195 }
6205 {
6207 {
6211 }
6215 }
6217 }
6220 }
6222 static rtx
6225 {
6226 /* Handle a hidden AL argument containing number of registers
6227 for varargs x86-64 functions. */
6231 ? X86_64_SSE_REGPARM_MAX
6236 {
6246 /* Unnamed 256bit vector mode parameters are passed on stack. */
6250 }
6256 }
6258 static rtx
6261 HOST_WIDE_INT bytes)
6262 {
6265 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6266 We use value of -2 to specify that current function call is MSABI. */
6270 /* If we've run out of registers, it goes on the stack. */
6276 /* Only floating point modes are passed in anything but integer regs. */
6278 {
6281 else
6282 {
6285 /* Unnamed floating parameters are passed in both the
6286 SSE and integer registers. */
6292 }
6293 }
6294 /* Handle aggregated types passed in register. */
6296 {
6301 }
6304 }
6306 /* Return where to put the arguments to a function.
6307 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6309 MODE is the argument's machine mode. TYPE is the data type of the
6310 argument. It is null for libcalls where that information may not be
6311 available. CUM gives information about the preceding args and about
6312 the function being called. NAMED is nonzero if this argument is a
6313 named parameter (otherwise it is an extra parameter matching an
6314 ellipsis). */
6316 static rtx
6319 {
6325 else
6329 /* To simplify the code below, represent vector types with a vector mode
6330 even if MMX/SSE are not active. */
6338 else
6340 }
6342 /* A C expression that indicates when an argument must be passed by
6343 reference. If nonzero for an argument, a copy of that argument is
6344 made in memory and a pointer to the argument is passed instead of
6345 the argument itself. The pointer is passed in whatever way is
6346 appropriate for passing a pointer to that type. */
6348 static bool
6352 {
6353 /* See Windows x64 Software Convention. */
6355 {
6358 {
6359 /* Arrays are passed by reference. */
6364 {
6365 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6366 are passed by reference. */
6368 }
6369 }
6371 /* __m128 is passed by reference. */
6377 }
6378 }
6383 }
6385 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6386 ABI. */
6387 static bool
6389 {
6401 {
6402 /* Walk the aggregates recursively. */
6404 {
6408 {
6409 tree field;
6411 /* Walk all the structure fields. */
6413 {
6417 }
6419 }
6422 /* Just for use if some languages passes arrays by value. */
6429 }
6430 }
6432 }
6434 /* Gives the alignment boundary, in bits, of an argument with the
6435 specified mode and type. */
6437 int
6439 {
6442 {
6443 /* Since the main variant type is used for call, we convert it to
6444 the main variant type. */
6447 }
6448 else
6452 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6453 natural boundaries. */
6455 {
6456 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6457 make an exception for SSE modes since these require 128bit
6458 alignment.
6460 The handling here differs from field_alignment. ICC aligns MMX
6461 arguments to 4 byte boundaries, while structure fields are aligned
6462 to 8 byte boundaries. */
6464 {
6467 }
6468 else
6469 {
6472 }
6473 }
6477 }
6479 /* Return true if N is a possible register number of function value. */
6481 static bool
6483 {
6485 {
6490 /* TODO: The function should depend on current function ABI but
6491 builtins.c would need updating then. Therefore we use the
6492 default ABI. */
6504 }
6507 }
6509 /* Define how to find the value returned by a function.
6510 VALTYPE is the data type of the value (as a tree).
6511 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6512 otherwise, FUNC is 0. */
6514 static rtx
6517 {
6520 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6521 we normally prevent this case when mmx is not available. However
6522 some ABIs may require the result to be returned like DImode. */
6526 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6527 we prevent this case when sse is not available. However some ABIs
6528 may require the result to be returned like integer TImode. */
6533 /* 32-byte vector modes in %ymm0. */
6537 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6540 else
6541 /* Most things go in %eax. */
6544 /* Override FP return register with %xmm0 for local functions when
6545 SSE math is enabled or for functions with sseregparm attribute. */
6547 {
6552 }
6554 /* OImode shouldn't be used directly. */
6558 }
6560 static rtx
6562 const_tree valtype)
6563 {
6564 rtx ret;
6566 /* Handle libcalls, which don't provide a type node. */
6568 {
6570 {
6587 }
6588 }
6594 /* For zero sized structures, construct_container returns NULL, but we
6595 need to keep rest of compiler happy by returning meaningful value. */
6600 }
6602 static rtx
6604 {
6608 {
6610 {
6623 }
6624 }
6626 }
6628 static rtx
6631 {
6643 else
6645 }
6647 static rtx
6650 {
6656 }
6658 rtx
6660 {
6662 }
6664 /* Return true iff type is returned in memory. */
6666 static int ATTRIBUTE_UNUSED
6668 {
6669 HOST_WIDE_INT size;
6680 {
6681 /* User-created vectors small enough to fit in EAX. */
6685 /* MMX/3dNow values are returned in MM0,
6686 except when it doesn't exits. */
6690 /* SSE values are returned in XMM0, except when it doesn't exist. */
6694 /* AVX values are returned in YMM0, except when it doesn't exist. */
6697 }
6705 /* OImode shouldn't be used directly. */
6709 }
6711 static int ATTRIBUTE_UNUSED
6713 {
6716 }
6718 static int ATTRIBUTE_UNUSED
6720 {
6723 /* __m128 is returned in xmm0. */
6728 /* Otherwise, the size must be exactly in [1248]. */
6730 }
6732 static bool
6734 {
6735 #ifdef SUBTARGET_RETURN_IN_MEMORY
6737 #else
6741 {
6744 else
6746 }
6747 else
6749 #endif
6750 }
6752 /* Return false iff TYPE is returned in memory. This version is used
6753 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6754 but differs notably in that when MMX is available, 8-byte vectors
6755 are returned in memory, rather than in MMX registers. */
6757 bool
6759 {
6772 {
6773 /* Return in memory only if MMX registers *are* available. This
6774 seems backwards, but it is consistent with the existing
6775 Solaris x86 ABI. */
6780 }
6787 }
6789 /* When returning SSE vector types, we have a choice of either
6790 (1) being abi incompatible with a -march switch, or
6791 (2) generating an error.
6792 Given no good solution, I think the safest thing is one warning.
6793 The user won't be able to use -Werror, but....
6795 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6796 called in response to actually generating a caller or callee that
6797 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6798 via aggregate_value_p for general type probing from tree-ssa. */
6800 static rtx
6802 {
6806 {
6807 /* Look at the return type of the function, not the function type. */
6811 {
6814 {
6818 }
6819 }
6822 {
6824 {
6828 }
6829 }
6830 }
6833 }
6835 \f
6836 /* Create the va_list data type. */
6838 /* Returns the calling convention specific va_list date type.
6839 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6841 static tree
6843 {
6846 /* For i386 we use plain pointer to argument area. */
6856 unsigned_type_node);
6859 unsigned_type_node);
6862 ptr_type_node);
6865 ptr_type_node);
6884 /* The correct type is an array type of one element. */
6886 }
6888 /* Setup the builtin va_list data type and for 64-bit the additional
6889 calling convention specific va_list data types. */
6891 static tree
6893 {
6896 /* Initialize abi specific va_list builtin types. */
6898 {
6899 tree t;
6901 {
6906 }
6907 else
6908 {
6913 }
6915 {
6920 }
6921 else
6922 {
6927 }
6928 }
6931 }
6933 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6935 static void
6937 {
6939 rtx label;
6940 rtx tmp_reg;
6941 rtx nsse_reg;
6942 alias_set_type set;
6945 /* GPR size of varargs save area. */
6948 else
6951 /* FPR size of varargs save area. We don't need it if we don't pass
6952 anything in SSE registers. */
6955 else
6965 i < X86_64_REGPARM_MAX
6967 i++)
6968 {
6975 }
6978 {
6979 /* Now emit code to save SSE registers. The AX parameter contains number
6980 of SSE parameter registers used to call this function. We use
6981 sse_prologue_save insn template that produces computed jump across
6982 SSE saves. We need some preparation work to get this working. */
6989 /* Compute address of memory block we save into. We always use pointer
6990 pointing 127 bytes after first byte to store - this is needed to keep
6991 instruction size limited by 4 bytes (5 bytes for AVX) with one
6992 byte displacement. */
7002 /* And finally do the dirty job! */
7006 }
7007 }
7009 static void
7011 {
7016 {
7027 }
7028 }
7030 static void
7034 {
7035 CUMULATIVE_ARGS next_cum;
7036 tree fntype;
7038 /* This argument doesn't appear to be used anymore. Which is good,
7039 because the old code here didn't suppress rtl generation. */
7047 /* For varargs, we do not want to skip the dummy va_dcl argument.
7048 For stdargs, we do want to skip the last named argument. */
7055 else
7057 }
7059 /* Checks if TYPE is of kind va_list char *. */
7061 static bool
7063 {
7064 tree canonic;
7066 /* For 32-bit it is always true. */
7072 }
7074 /* Implement va_start. */
7076 static void
7078 {
7082 tree type;
7084 /* Only 64bit target needs something special. */
7086 {
7089 }
7102 /* Count number of gp and fp argument registers used. */
7108 {
7114 }
7117 {
7123 }
7125 /* Find the overflow area. */
7136 {
7137 /* Find the register save area.
7138 Prologue of the function save it right above stack frame. */
7147 }
7148 }
7150 /* Implement va_arg. */
7152 static tree
7155 {
7162 rtx container;
7164 tree ptrtype;
7168 /* Only 64bit target needs something special. */
7192 {
7199 /* Unnamed 256bit vector mode parameters are passed on stack. */
7201 {
7204 }
7212 }
7214 /* Pull the value out of the saved registers. */
7219 {
7233 /* In case we are passing structure, verify that it is consecutive block
7234 on the register save area. If not we need to do moves. */
7236 {
7237 /* Verify that all registers are strictly consecutive */
7239 {
7243 {
7248 }
7249 }
7250 else
7251 {
7255 {
7260 }
7261 }
7262 }
7264 {
7267 }
7268 else
7269 {
7272 }
7274 /* First ensure that we fit completely in registers. */
7276 {
7283 }
7285 {
7293 }
7295 /* Compute index to start of area used for integer regs. */
7297 {
7298 /* int_addr = gpr + sav; */
7302 }
7304 {
7305 /* sse_addr = fpr + sav; */
7309 }
7311 {
7315 /* addr = &temp; */
7320 {
7324 tree piece_type;
7325 tree addr_type;
7326 tree daddr_type;
7333 {
7338 }
7342 else
7349 {
7352 }
7353 else
7354 {
7357 }
7366 {
7371 }
7372 else
7373 {
7374 tree copy
7379 }
7381 }
7382 }
7385 {
7389 }
7392 {
7396 }
7401 }
7403 /* ... otherwise out of the overflow area. */
7405 /* When we align parameter on stack for caller, if the parameter
7406 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7407 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7408 here with caller. */
7413 /* Care for on-stack alignment if needed. */
7417 else
7418 {
7428 }
7445 }
7446 \f
7447 /* Return nonzero if OPNUM's MEM should be matched
7448 in movabs* patterns. */
7450 int
7452 {
7464 }
7465 \f
7466 /* Initialize the table of extra 80387 mathematical constants. */
7468 static void
7470 {
7472 {
7478 };
7482 {
7484 /* Ensure each constant is rounded to XFmode precision. */
7487 }
7490 }
7492 /* Return true if the constant is something that can be loaded with
7493 a special instruction. */
7495 int
7497 {
7500 REAL_VALUE_TYPE r;
7512 /* For XFmode constants, try to find a special 80387 instruction when
7513 optimizing for size or on those CPUs that benefit from them. */
7516 {
7525 }
7527 /* Load of the constant -0.0 or -1.0 will be split as
7528 fldz;fchs or fld1;fchs sequence. */
7535 }
7537 /* Return the opcode of the special instruction to be used to load
7538 the constant X. */
7542 {
7544 {
7564 }
7565 }
7567 /* Return the CONST_DOUBLE representing the 80387 constant that is
7568 loaded by the specified special instruction. The argument IDX
7569 matches the return value from standard_80387_constant_p. */
7571 rtx
7573 {
7580 {
7591 }
7594 XFmode);
7595 }
7597 /* Return 1 if X is all 0s and 2 if x is all 1s
7598 in supported SSE vector mode. */
7600 int
7602 {
7609 {
7618 }
7621 }
7623 /* Return the opcode of the special instruction to be used to load
7624 the constant X. */
7628 {
7630 {
7633 {
7639 else
7644 else
7651 else
7656 else
7660 }
7665 }
7667 }
7669 /* Returns 1 if OP contains a symbol reference */
7671 int
7673 {
7682 {
7684 {
7690 }
7694 }
7697 }
7699 /* Return 1 if it is appropriate to emit `ret' instructions in the
7700 body of a function. Do this only if the epilogue is simple, needing a
7701 couple of insns. Prior to reloading, we can't tell how many registers
7702 must be saved, so return 0 then. Return 0 if there is no frame
7703 marker to de-allocate. */
7705 int
7707 {
7713 /* Don't allow more than 32 pop, since that's all we can do
7714 with one instruction. */
7722 }
7723 \f
7724 /* Value should be nonzero if functions must have frame pointers.
7725 Zero means the frame pointer need not be set up (and parms may
7726 be accessed via the stack pointer) in functions that seem suitable. */
7728 static bool
7730 {
7731 /* If we accessed previous frames, then the generated code expects
7732 to be able to access the saved ebp value in our frame. */
7736 /* Several x86 os'es need a frame pointer for other reasons,
7737 usually pertaining to setjmp. */
7741 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7742 the frame pointer by default. Turn it back on now if we've not
7743 got a leaf function. */
7745 && (!current_function_is_leaf
7753 }
7755 /* Record that the current function accesses previous call frames. */
7757 void
7759 {
7761 }
7762 \f
7763 #ifndef USE_HIDDEN_LINKONCE
7764 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7765 # define USE_HIDDEN_LINKONCE 1
7766 # else
7767 # define USE_HIDDEN_LINKONCE 0
7768 # endif
7769 #endif
7773 /* Fills in the label name that should be used for a pc thunk for
7774 the given register. */
7776 static void
7778 {
7783 else
7785 }
7788 /* This function generates code for -fpic that loads %ebx with
7789 the return address of the caller and then returns. */
7791 static void
7793 {
7798 {
7800 tree decl;
7815 #if TARGET_MACHO
7817 {
7826 }
7827 else
7828 #endif
7830 {
7841 }
7842 else
7843 {
7846 }
7852 /* Make sure unwind info is emitted for the thunk if needed. */
7864 }
7865 }
7867 /* Emit code for the SET_GOT patterns. */
7871 {
7877 {
7878 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7883 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7884 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7885 an unadorned address. */
7890 }
7895 {
7900 else
7901 {
7903 #ifdef DWARF2_UNWIND_INFO
7904 /* The call to next label acts as a push. */
7906 {
7907 rtx insn;
7911 stack_pointer_rtx,
7916 }
7917 #endif
7918 }
7920 #if TARGET_MACHO
7921 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7922 is what will be referenced by the Mach-O PIC subsystem. */
7925 #endif
7931 {
7933 #ifdef DWARF2_UNWIND_INFO
7934 /* The pop is a pop and clobbers dest, but doesn't restore it
7935 for unwind info purposes. */
7937 {
7938 rtx insn;
7944 stack_pointer_rtx,
7949 }
7950 #endif
7951 }
7952 }
7953 else
7954 {
7959 #ifdef DWARF2_UNWIND_INFO
7960 /* Ensure all queued register saves are flushed before the
7961 call. */
7963 {
7964 rtx insn;
7969 }
7970 #endif
7974 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7975 is what will be referenced by the Mach-O PIC subsystem. */
7976 #if TARGET_MACHO
7979 else
7982 #endif
7983 }
7990 else
7994 }
7996 /* Generate an "push" pattern for input ARG. */
7998 static rtx
8000 {
8007 stack_pointer_rtx)),
8008 arg);
8009 }
8011 /* Return >= 0 if there is an unused call-clobbered register available
8012 for the entire function. */
8014 static unsigned int
8016 {
8019 {
8021 /* Can't use the same register for both PIC and DRAP. */
8024 else
8029 }
8032 }
8034 /* Return 1 if we need to save REGNO. */
8035 static int
8037 {
8044 {
8048 }
8051 {
8054 {
8060 }
8061 }
8070 }
8072 /* Return number of saved general prupose registers. */
8074 static int
8076 {
8082 nregs ++;
8084 }
8086 /* Return number of saved SSE registrers. */
8088 static int
8090 {
8098 nregs ++;
8100 }
8102 /* Given FROM and TO register numbers, say whether this elimination is
8103 allowed. If stack alignment is needed, we can only replace argument
8104 pointer with hard frame pointer, or replace frame pointer with stack
8105 pointer. Otherwise, frame pointer elimination is automatically
8106 handled and all other eliminations are valid. */
8108 static bool
8110 {
8116 else
8118 }
8120 /* Return the offset between two registers, one to be eliminated, and the other
8121 its replacement, at the start of a routine. */
8123 HOST_WIDE_INT
8125 {
8134 else
8135 {
8143 }
8144 }
8146 /* In a dynamically-aligned function, we can't know the offset from
8147 stack pointer to frame pointer, so we must ensure that setjmp
8148 eliminates fp against the hard fp (%ebp) rather than trying to
8149 index from %esp up to the top of the frame across a gap that is
8150 of unknown (at compile-time) size. */
8151 static rtx
8153 {
8155 }
8157 /* Fill structure ix86_frame about frame of currently computed function. */
8159 static void
8161 {
8163 HOST_WIDE_INT offset;
8173 /* MS ABI seem to require stack alignment to be always 16 except for function
8174 prologues and leaf. */
8178 {
8183 }
8189 /* During reload iteration the amount of registers saved can change.
8190 Recompute the value as needed. Do not recompute when amount of registers
8191 didn't change as reload does multiple calls to the function and does not
8192 expect the decision to change within single iteration. */
8195 {
8200 /* The fast prologue uses move instead of push to save registers. This
8201 is significantly longer, but also executes faster as modern hardware
8202 can execute the moves in parallel, but can't do that for push/pop.
8204 Be careful about choosing what prologue to emit: When function takes
8205 many instructions to execute we may use slow version as well as in
8206 case function is known to be outside hot spot (this is known with
8207 feedback only). Weight the size of function by number of registers
8208 to save as it is cheap to use one or two push instructions but very
8209 slow to use many of them. */
8213 || (flag_branch_probabilities
8216 else
8219 }
8223 else
8226 /* Skip return address. */
8229 /* Skip pushed static chain. */
8233 /* Skip saved base pointer. */
8239 /* Set offset to aligned because the realigned frame starts from
8240 here. */
8244 /* Register save area */
8247 /* Align SSE reg save area. */
8250 else
8253 /* SSE register save area. */
8256 /* Va-arg area */
8260 /* Align start of frame for local function. */
8266 /* Frame pointer points here. */
8271 /* Add outgoing arguments area. Can be skipped if we eliminated
8272 all the function calls as dead code.
8273 Skipping is however impossible when function calls alloca. Alloca
8274 expander assumes that last crtl->outgoing_args_size
8275 of stack frame are unused. */
8279 {
8282 }
8283 else
8286 /* Align stack boundary. Only needed if we're calling another function
8287 or using alloca. */
8292 else
8297 /* We've reached end of stack frame. */
8300 /* Size prologue needs to allocate. */
8310 && current_function_sp_is_unchanging
8311 && current_function_is_leaf
8313 {
8319 }
8320 else
8324 }
8326 /* Emit code to save registers in the prologue. */
8328 static void
8330 {
8332 rtx insn;
8336 {
8339 }
8340 }
8342 /* Emit code to save registers using MOV insns. First register
8343 is restored from POINTER + OFFSET. */
8344 static void
8346 {
8348 rtx insn;
8352 {
8358 }
8359 }
8361 /* Emit code to save registers using MOV insns. First register
8362 is restored from POINTER + OFFSET. */
8363 static void
8365 {
8367 rtx insn;
8368 rtx mem;
8372 {
8378 }
8379 }
8383 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8384 manipulation insn. Don't add it if the previously
8385 saved value will be left untouched within stack red-zone till return,
8386 as unwinders can find the same value in the register and
8387 on the stack. */
8389 static void
8391 {
8393 && !TARGET_64BIT_MS_ABI
8399 {
8402 }
8403 else
8404 queued_cfa_restores
8406 }
8408 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8410 static void
8412 {
8413 rtx last;
8417 ;
8422 }
8424 /* Expand prologue or epilogue stack adjustment.
8425 The pattern exist to put a dependency on all ebp-based memory accesses.
8426 STYLE should be negative if instructions should be marked as frame related,
8427 zero if %r11 register is live and cannot be freely used and positive
8428 otherwise. */
8430 static void
8433 {
8434 rtx insn;
8440 else
8441 {
8442 rtx tmp;
8443 /* r11 is used by indirect sibcall return as well, set before the
8444 epilogue and used after the epilogue. */
8447 else
8448 {
8452 }
8457 offset));
8458 }
8464 {
8465 rtx r;
8475 }
8478 }
8480 /* Find an available register to be used as dynamic realign argument
8481 pointer regsiter. Such a register will be written in prologue and
8482 used in begin of body, so it must not be
8483 1. parameter passing register.
8484 2. GOT pointer.
8485 We reuse static-chain register if it is available. Otherwise, we
8486 use DI for i386 and R13 for x86-64. We chose R13 since it has
8487 shorter encoding.
8489 Return: the regno of chosen register. */
8491 static unsigned int
8493 {
8497 {
8498 /* Use R13 for nested function or function need static chain.
8499 Since function with tail call may use any caller-saved
8500 registers in epilogue, DRAP must not use caller-saved
8501 register in such case. */
8506 }
8507 else
8508 {
8509 /* Use DI for nested function or function need static chain.
8510 Since function with tail call may use any caller-saved
8511 registers in epilogue, DRAP must not use caller-saved
8512 register in such case. */
8516 /* Reuse static chain register if it isn't used for parameter
8517 passing. */
8524 else
8526 }
8527 }
8529 /* Return minimum incoming stack alignment. */
8531 static unsigned int
8533 {
8536 /* Prefer the one specified at command line. */
8539 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8540 if -mstackrealign is used, it isn't used for sibcall check and
8541 estimated stack alignment is 128bit. */
8543 && !TARGET_64BIT
8544 && ix86_force_align_arg_pointer
8547 else
8550 /* Incoming stack alignment can be changed on individual functions
8551 via force_align_arg_pointer attribute. We use the smallest
8552 incoming stack boundary. */
8558 /* The incoming stack frame has to be aligned at least at
8559 parm_stack_boundary. */
8563 /* Stack at entrance of main is aligned by runtime. We use the
8564 smallest incoming stack boundary. */
8572 }
8574 /* Update incoming stack boundary and estimated stack alignment. */
8576 static void
8578 {
8579 ix86_incoming_stack_boundary
8582 /* x86_64 vararg needs 16byte stack alignment for register save
8583 area. */
8588 }
8590 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8591 needed or an rtx for DRAP otherwise. */
8593 static rtx
8595 {
8600 {
8601 /* Assign DRAP to vDRAP and returns vDRAP */
8603 rtx drap_vreg;
8604 rtx arg_ptr;
8617 {
8620 }
8622 }
8623 else
8625 }
8627 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8629 static rtx
8631 {
8633 }
8635 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8636 to be generated in correct form. */
8637 static void
8639 {
8640 /* Check if stack realign is really needed after reload, and
8641 stores result in cfun */
8642 unsigned int incoming_stack_boundary
8646 < (current_function_is_leaf
8651 {
8652 /* After stack_realign_needed is finalized, we can't no longer
8653 change it. */
8655 }
8656 else
8657 {
8660 }
8661 }
8663 /* Expand the prologue into a bunch of separate insns. */
8665 void
8667 {
8668 rtx insn;
8671 HOST_WIDE_INT allocate;
8676 /* DRAP should not coexist with stack_realign_fp */
8679 /* Initialize CFA state for before the prologue. */
8686 {
8689 /* Make sure the function starts with
8690 8b ff movl.s %edi,%edi
8691 55 push %ebp
8692 8b ec movl.s %esp,%ebp
8694 This matches the hookable function prologue in Win32 API
8695 functions in Microsoft Windows XP Service Pack 2 and newer.
8696 Wine uses this to enable Windows apps to hook the Win32 API
8697 functions provided by Wine. */
8702 stack_pointer_rtx));
8706 {
8707 /* The push %ebp and movl.s %esp, %ebp already set up
8708 the frame pointer. No need to do this again. */
8714 }
8715 else
8716 /* If the frame pointer is not needed, pop %ebp again. This
8717 could be optimized for cases where ebp needs to be backed up
8718 for some other reason. If stack realignment is needed, pop
8719 the base pointer again, align the stack, and later regenerate
8720 the frame pointer setup. The frame pointer generated by the
8721 hook prologue is not aligned, so it can't be used. */
8723 }
8725 /* The first insn of a function that accepts its static chain on the
8726 stack is to push the register that would be filled in by a direct
8727 call. This insn will be skipped by the trampoline. */
8729 {
8730 rtx t;
8735 /* We don't want to interpret this push insn as a register save,
8736 only as a stack adjustment. The real copy of the register as
8737 a save will be done later, if needed. */
8742 }
8744 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8745 of DRAP is needed and stack realignment is really needed after reload */
8747 {
8759 /* Grab the argument pointer. */
8763 /* Only need to push parameter pointer reg if it is caller
8764 saved reg */
8766 {
8767 /* Push arg pointer reg */
8770 }
8776 /* Align the stack. */
8778 stack_pointer_rtx,
8782 /* Replicate the return address on the stack so that return
8783 address can be reached via (argp - 1) slot. This is needed
8784 to implement macro RETURN_ADDR_RTX and intrinsic function
8785 expand_builtin_return_addr etc. */
8791 }
8793 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8794 slower on all targets. Also sdb doesn't like it. */
8797 {
8806 }
8809 {
8813 /* Align the stack. */
8815 stack_pointer_rtx,
8818 }
8824 else
8827 /* When using red zone we may start register saving before allocating
8828 the stack frame saving one cycle of the prologue. However I will
8829 avoid doing this if I am going to have to probe the stack since
8830 at least on x86_64 the stack probe can turn into a call that clobbers
8831 a red zone location */
8836 ? hard_frame_pointer_rtx
8841 ;
8846 else
8847 {
8850 rtx t;
8854 else
8858 {
8861 }
8867 else
8872 {
8878 }
8881 {
8884 allocate
8887 else
8890 }
8891 }
8896 {
8901 frame.to_allocate
8903 else
8906 }
8912 else
8922 {
8929 }
8932 {
8934 {
8936 {
8946 }
8947 else
8949 }
8950 else
8952 }
8954 /* In the pic_reg_used case, make sure that the got load isn't deleted
8955 when mcount needs it. Blockage to avoid call movement across mcount
8956 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8957 note. */
8962 {
8963 /* vDRAP is setup but after reload it turns out stack realign
8964 isn't necessary, here we will emit prologue to setup DRAP
8965 without stack realign adjustment */
8966 rtx x;
8973 }
8975 /* Prevent instructions from being scheduled into register save push
8976 sequence when access to the redzone area is done through frame pointer.
8977 The offset between the frame pointer and the stack pointer is calculated
8978 relative to the value of the stack pointer at the end of the function
8979 prologue, and moving instructions that access redzone area via frame
8980 pointer inside push sequence violates this assumption. */
8984 /* Emit cld instruction if stringops are used in the function. */
8987 }
8989 /* Emit code to restore REG using a POP insn. */
8991 static void
8993 {
8998 {
8999 /* Previously we'd represented the CFA as an expression
9000 like *(%ebp - 8). We've just popped that value from
9001 the stack, which means we need to reset the CFA to
9002 the drap register. This will remain until we restore
9003 the stack pointer. */
9007 }
9010 {
9015 }
9017 /* When the frame pointer is the CFA, and we pop it, we are
9018 swapping back to the stack pointer as the CFA. This happens
9019 for stack frames that don't allocate other data, so we assume
9020 the stack pointer is now pointing at the return address, i.e.
9021 the function entry state, which makes the offset be 1 word. */
9024 {
9032 }
9035 }
9037 /* Emit code to restore saved registers using POP insns. */
9039 static void
9041 {
9046 {
9048 red_offset);
9050 }
9051 }
9053 /* Emit code and notes for the LEAVE instruction. */
9055 static void
9057 {
9063 {
9071 }
9072 }
9074 /* Emit code to restore saved registers using MOV insns. First register
9075 is restored from POINTER + OFFSET. */
9076 static void
9078 HOST_WIDE_INT red_offset,
9080 {
9083 rtx insn;
9087 {
9090 /* Ensure that adjust_address won't be forced to produce pointer
9091 out of range allowed by x86-64 instruction set. */
9093 {
9094 rtx r11;
9101 }
9108 {
9109 /* Previously we'd represented the CFA as an expression
9110 like *(%ebp - 8). We've just popped that value from
9111 the stack, which means we need to reset the CFA to
9112 the drap register. This will remain until we restore
9113 the stack pointer. */
9116 }
9117 else
9121 }
9122 }
9124 /* Emit code to restore saved registers using MOV insns. First register
9125 is restored from POINTER + OFFSET. */
9126 static void
9128 HOST_WIDE_INT red_offset,
9130 {
9133 rtx mem;
9137 {
9140 /* Ensure that adjust_address won't be forced to produce pointer
9141 out of range allowed by x86-64 instruction set. */
9143 {
9144 rtx r11;
9151 }
9160 }
9161 }
9163 /* Restore function stack, frame, and registers. */
9165 void
9167 {
9176 /* When stack is realigned, SP must be valid. */
9177 sp_valid = (!frame_pointer_needed
9178 || current_function_sp_is_unchanging
9183 /* See the comment about red zone and frame
9184 pointer usage in ix86_expand_prologue. */
9191 /* Calculate start of saved registers relative to ebp. Special care
9192 must be taken for the normal return case of a function using
9193 eh_return: the eax and edx registers are marked as saved, but not
9194 restored along this path. */
9201 /* Calculate start of saved registers relative to esp on entry of the
9202 function. When realigning stack, this needs to be the most negative
9203 value possible at runtime. */
9216 /* If we're only restoring one register and sp is not valid then
9217 using a move instruction to restore the register since it's
9218 less work than reloading sp and popping the register.
9220 The default code result in stack adjustment using add/lea instruction,
9221 while this code results in LEAVE instruction (or discrete equivalent),
9222 so it is profitable in some other cases as well. Especially when there
9223 are no registers to restore. We also use this code when TARGET_USE_LEAVE
9224 and there is exactly one register to pop. This heuristic may need some
9225 tuning in future. */
9227 || (TARGET_EPILOGUE_USING_MOVE
9237 {
9238 /* Restore registers. We can use ebp or esp to address the memory
9239 locations. If both are available, default to ebp, since offsets
9240 are known to be small. Only exception is esp pointing directly
9241 to the end of block of saved registers, where we may simplify
9242 addressing mode.
9244 If we are realigning stack with bp and sp, regs restore can't
9245 be addressed by bp. sp must be used instead. */
9250 {
9255 frame.to_allocate
9258 red_offset
9261 }
9262 else
9263 {
9268 offset
9271 red_offset
9274 }
9278 /* eh_return epilogues need %ecx added to the stack pointer. */
9280 {
9283 /* Stack align doesn't work with eh_return. */
9285 /* Neither does regparm nested functions. */
9289 {
9297 /* Note that we use SA as a temporary CFA, as the return
9298 address is at the proper place relative to it. We
9299 pretend this happens at the FP restore insn because
9300 prior to this insn the FP would be stored at the wrong
9301 offset relative to SA, and after this insn we have no
9302 other reasonable register to use for the CFA. We don't
9303 bother resetting the CFA to the SP for the duration of
9304 the return insn. */
9315 }
9316 else
9317 {
9328 {
9332 UNITS_PER_WORD));
9334 }
9335 }
9336 }
9344 /* If not an i386, mov & pop is faster than "leave". */
9348 else
9349 {
9351 hard_frame_pointer_rtx,
9355 }
9356 }
9357 else
9358 {
9359 /* First step is to deallocate the stack frame so that we can
9360 pop the registers.
9362 If we realign stack with frame pointer, then stack pointer
9363 won't be able to recover via lea $offset(%bp), %sp, because
9364 there is a padding area between bp and sp for realign.
9365 "add $to_allocate, %sp" must be used instead. */
9367 {
9371 hard_frame_pointer_rtx,
9380 }
9382 {
9391 }
9398 {
9399 /* Leave results in shorter dependency chains on CPUs that are
9400 able to grok it fast. */
9403 else
9404 {
9405 /* For stack realigned really happens, recover stack
9406 pointer to hard frame pointer is a must, if not using
9407 leave. */
9410 hard_frame_pointer_rtx,
9413 red_offset);
9414 }
9415 }
9416 }
9419 {
9421 rtx insn;
9445 }
9447 /* Remove the saved static chain from the stack. The use of ECX is
9448 merely as a scratch register, not as the actual static chain. */
9450 {
9463 }
9465 /* Sibcall epilogues don't want a return instruction. */
9467 {
9470 }
9473 {
9476 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9477 address, do explicit add, and jump indirectly to the caller. */
9480 {
9482 rtx insn;
9484 /* There is no "pascal" calling convention in any 64bit ABI. */
9499 }
9500 else
9502 }
9503 else
9506 /* Restore the state back to the state from the prologue,
9507 so that it's correct for the next epilogue. */
9509 }
9511 /* Reset from the function's potential modifications. */
9513 static void
9515 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9516 {
9519 #if TARGET_MACHO
9520 /* Mach-O doesn't support labels at the end of objects, so if
9521 it looks like we might want one, insert a NOP. */
9522 {
9533 }
9534 #endif
9536 }
9537 \f
9538 /* Extract the parts of an RTL expression that is a valid memory address
9539 for an instruction. Return 0 if the structure of the address is
9540 grossly off. Return -1 if the address contains ASHIFT, so it is not
9541 strictly valid, but still used for computing length of lea instruction. */
9543 int
9545 {
9550 rtx tmp;
9557 {
9562 do
9563 {
9568 }
9575 {
9578 {
9601 && TARGET_TLS_DIRECT_SEG_REFS
9604 else
9614 else
9629 }
9630 }
9631 }
9633 {
9636 }
9638 {
9639 /* We're called for lea too, which implements ashift on occasion. */
9649 }
9650 else
9653 /* Extract the integral value of scale. */
9655 {
9659 }
9664 /* Avoid useless 0 displacement. */
9668 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9673 {
9674 rtx tmp;
9677 }
9679 /* Special case: %ebp cannot be encoded as a base without a displacement.
9680 Similarly %r13. */
9682 && base_reg
9691 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9692 Avoid this by transforming to [%esi+0].
9693 Reload calls address legitimization without cfun defined, so we need
9694 to test cfun for being non-NULL. */
9701 /* Special case: encode reg+reg instead of reg*2. */
9705 /* Special case: scaling cannot be encoded without base or displacement. */
9716 }
9717 \f
9718 /* Return cost of the memory address x.
9719 For i386, it is better to use a complex address than let gcc copy
9720 the address into a reg and make a new pseudo. But not if the address
9721 requires to two regs - that would mean more pseudos with longer
9722 lifetimes. */
9723 static int
9725 {
9737 /* Attempt to minimize number of registers in the address. */
9743 cost++;
9750 cost++;
9752 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9753 since it's predecode logic can't detect the length of instructions
9754 and it degenerates to vector decoded. Increase cost of such
9755 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9756 to split such addresses or even refuse such addresses at all.
9758 Following addressing modes are affected:
9759 [base+scale*index]
9760 [scale*index+disp]
9761 [base+index]
9763 The first and last case may be avoidable by explicitly coding the zero in
9764 memory address, but I don't have AMD-K6 machine handy to check this
9765 theory. */
9774 }
9775 \f
9776 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9777 this is used for to form addresses to local data when -fPIC is in
9778 use. */
9780 static bool
9782 {
9785 }
9787 /* Determine if a given RTX is a valid constant. We already know this
9788 satisfies CONSTANT_P. */
9790 bool
9792 {
9794 {
9799 {
9803 }
9808 /* Only some unspecs are valid as "constants". */
9811 {
9827 }
9829 /* We must have drilled down to a symbol. */
9834 /* FALLTHRU */
9837 /* TLS symbols are never valid. */
9841 /* DLLIMPORT symbols are never valid. */
9860 }
9862 /* Otherwise we handle everything else in the move patterns. */
9864 }
9866 /* Determine if it's legal to put X into the constant pool. This
9867 is not possible for the address of thread-local symbols, which
9868 is checked above. */
9870 static bool
9872 {
9873 /* We can always put integral constants and vectors in memory. */
9875 {
9883 }
9885 }
9888 /* Nonzero if the constant value X is a legitimate general operand
9889 when generating PIC code. It is given that flag_pic is on and
9890 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9892 bool
9894 {
9895 rtx inner;
9898 {
9905 /* Only some unspecs are valid as "constants". */
9908 {
9921 }
9922 /* FALLTHRU */
9930 }
9931 }
9933 /* Determine if a given CONST RTX is a valid memory displacement
9934 in PIC mode. */
9936 int
9938 {
9941 /* In 64bit mode we can allow direct addresses of symbols and labels
9942 when they are not dynamic symbols. */
9944 {
9948 {
9965 /* FALLTHRU */
9968 /* TLS references should always be enclosed in UNSPEC. */
9978 }
9979 }
9985 {
9986 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9987 of GOT tables. We should not need these anyway. */
9998 }
10002 {
10007 }
10016 {
10020 /* We need to check for both symbols and labels because VxWorks loads
10021 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
10022 details. */
10026 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
10027 While ABI specify also 32bit relocation but we don't produce it in
10028 small PIC model at all. */
10050 }
10053 }
10055 /* Recognizes RTL expressions that are valid memory addresses for an
10056 instruction. The MODE argument is the machine mode for the MEM
10057 expression that wants to use this address.
10059 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
10060 convert common non-canonical forms to canonical form so that they will
10061 be recognized. */
10063 static bool
10066 {
10069 HOST_WIDE_INT scale;
10072 /* Decomposition failed. */
10080 /* Validate base register.
10082 Don't allow SUBREG's that span more than a word here. It can lead to spill
10083 failures when the base is one word out of a two word structure, which is
10084 represented internally as a DImode int. */
10087 {
10088 rtx reg;
10097 else
10098 /* Base is not a register. */
10102 /* Base is not in Pmode. */
10107 /* Base is not valid. */
10109 }
10111 /* Validate index register.
10113 Don't allow SUBREG's that span more than a word here -- same as above. */
10116 {
10117 rtx reg;
10126 else
10127 /* Index is not a register. */
10131 /* Index is not in Pmode. */
10136 /* Index is not valid. */
10138 }
10140 /* Validate scale factor. */
10142 {
10144 /* Scale without index. */
10148 /* Scale is not a valid multiplier. */
10150 }
10152 /* Validate displacement. */
10154 {
10159 {
10160 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
10161 used. While ABI specify also 32bit relocations, we don't produce
10162 them at all and use IP relative instead. */
10169 /* 64bit address unspec. */
10184 /* Invalid address unspec. */
10186 }
10189 && (flag_pic
10190 || (TARGET_MACHO
10191 #if TARGET_MACHO
10192 && MACHOPIC_INDIRECT
10194 #endif
10195 )))
10196 {
10198 is_legitimate_pic:
10200 {
10201 /* foo@dtpoff(%rX) is ok. */
10208 /* Non-constant pic memory reference. */
10210 }
10212 /* Displacement is an invalid pic construct. */
10215 /* This code used to verify that a symbolic pic displacement
10216 includes the pic_offset_table_rtx register.
10218 While this is good idea, unfortunately these constructs may
10219 be created by "adds using lea" optimization for incorrect
10220 code like:
10222 int a;
10223 int foo(int i)
10224 {
10225 return *(&a+i);
10226 }
10228 This code is nonsensical, but results in addressing
10229 GOT table with pic_offset_table_rtx base. We can't
10230 just refuse it easily, since it gets matched by
10231 "addsi3" pattern, that later gets split to lea in the
10232 case output register differs from input. While this
10233 can be handled by separate addsi pattern for this case
10234 that never results in lea, this seems to be easier and
10235 correct fix for crash to disable this test. */
10236 }
10243 /* Displacement is not constant. */
10247 /* Displacement is out of range. */
10249 }
10251 /* Everything looks valid. */
10253 }
10255 /* Determine if a given RTX is a valid constant address. */
10257 bool
10259 {
10261 }
10262 \f
10263 /* Return a unique alias set for the GOT. */
10265 static alias_set_type
10267 {
10272 }
10274 /* Return a legitimate reference for ORIG (an address) using the
10275 register REG. If REG is 0, a new pseudo is generated.
10277 There are two types of references that must be handled:
10279 1. Global data references must load the address from the GOT, via
10280 the PIC reg. An insn is emitted to do this load, and the reg is
10281 returned.
10283 2. Static data references, constant pool addresses, and code labels
10284 compute the address as an offset from the GOT, whose base is in
10285 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
10286 differentiate them from global data objects. The returned
10287 address is the PIC reg + an unspec constant.
10289 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
10290 reg also appears in the address. */
10292 static rtx
10294 {
10297 rtx base;
10299 #if TARGET_MACHO
10301 {
10304 /* Use the generic Mach-O PIC machinery. */
10306 }
10307 #endif
10314 {
10315 rtx tmpreg;
10316 /* This symbol may be referenced via a displacement from the PIC
10317 base address (@GOTOFF). */
10324 {
10326 UNSPEC_GOTOFF);
10328 }
10329 else
10334 else
10339 {
10343 }
10345 }
10347 {
10348 /* This symbol may be referenced via a displacement from the PIC
10349 base address (@GOTOFF). */
10356 {
10358 UNSPEC_GOTOFF);
10360 }
10361 else
10367 {
10370 }
10371 }
10373 /* We can't use @GOTOFF for text labels on VxWorks;
10374 see gotoff_operand. */
10376 {
10378 {
10384 {
10387 }
10388 }
10391 {
10399 /* Use directly gen_movsi, otherwise the address is loaded
10400 into register for CSE. We don't want to CSE this addresses,
10401 instead we CSE addresses from the GOT table, so skip this. */
10404 }
10405 else
10406 {
10407 /* This symbol must be referenced via a load from the
10408 Global Offset Table (@GOT). */
10424 }
10425 }
10426 else
10427 {
10430 {
10432 {
10435 }
10436 else
10438 }
10440 {
10443 /* We must match stuff we generate before. Assume the only
10444 unspecs that can get here are ours. Not that we could do
10445 anything with them anyway.... */
10451 }
10453 {
10456 /* Check first to see if this is a constant offset from a @GOTOFF
10457 symbol reference. */
10460 {
10462 {
10466 UNSPEC_GOTOFF);
10472 {
10475 }
10476 }
10477 else
10478 {
10481 {
10485 }
10486 }
10487 }
10488 else
10489 {
10496 else
10497 {
10499 {
10502 }
10504 }
10505 }
10506 }
10507 }
10509 }
10510 \f
10511 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10513 static rtx
10515 {
10527 }
10529 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10530 false if we expect this to be used for a memory address and true if
10531 we expect to load the address into a register. */
10533 static rtx
10535 {
10540 {
10546 {
10556 }
10559 else
10563 {
10567 }
10575 {
10587 }
10590 else
10594 {
10599 }
10607 {
10611 }
10617 {
10620 }
10622 {
10627 }
10629 {
10633 }
10634 else
10635 {
10638 }
10648 {
10652 }
10653 else
10654 {
10658 }
10668 {
10671 }
10672 else
10673 {
10677 }
10682 }
10685 }
10687 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10688 to symbol DECL. */
10691 htab_t dllimport_map;
10693 static tree
10695 {
10702 tree to;
10703 rtx rtl;
10747 }
10749 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10750 true if we require the result be a register. */
10752 static rtx
10754 {
10755 tree imp_decl;
10756 rtx x;
10765 }
10767 /* Try machine-dependent ways of modifying an illegitimate address
10768 to be legitimate. If we find one, return the new, valid address.
10769 This macro is used in only one place: `memory_address' in explow.c.
10771 OLDX is the address as it was before break_out_memory_refs was called.
10772 In some cases it is useful to look at this to decide what needs to be done.
10774 It is always safe for this macro to do nothing. It exists to recognize
10775 opportunities to optimize the output.
10777 For the 80386, we handle X+REG by loading X into a register R and
10778 using R+REG. R will go in a general reg and indexing will be used.
10779 However, if REG is a broken-out memory address or multiplication,
10780 nothing needs to be done because REG can certainly go in a general reg.
10782 When -fpic is used, special handling is needed for symbolic references.
10783 See comments by legitimize_pic_address in i386.c for details. */
10785 static rtx
10788 {
10799 {
10803 }
10806 {
10813 {
10816 }
10817 }
10822 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10826 {
10831 }
10834 {
10835 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10840 {
10846 }
10851 {
10857 }
10859 /* Put multiply first if it isn't already. */
10861 {
10866 }
10868 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10869 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10870 created by virtual register instantiation, register elimination, and
10871 similar optimizations. */
10873 {
10879 }
10881 /* Canonicalize
10882 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10883 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10888 {
10889 rtx constant;
10893 {
10896 }
10898 {
10901 }
10902 else
10906 {
10912 }
10913 }
10919 {
10922 }
10925 {
10928 }
10936 {
10939 }
10945 {
10953 }
10956 {
10964 }
10965 }
10968 }
10969 \f
10970 /* Print an integer constant expression in assembler syntax. Addition
10971 and subtraction are the only arithmetic that may appear in these
10972 expressions. FILE is the stdio stream to write to, X is the rtx, and
10973 CODE is the operand print code from the output string. */
10975 static void
10977 {
10981 {
10990 else
10991 {
10994 /* Mark the decl as referenced so that cgraph will
10995 output the function. */
10999 #if TARGET_MACHO
11003 #endif
11005 }
11013 /* FALLTHRU */
11024 /* This used to output parentheses around the expression,
11025 but that does not work on the 386 (either ATT or BSD assembler). */
11031 {
11032 /* We can use %d if the number is <32 bits and positive. */
11037 else
11039 }
11040 else
11041 /* We can't handle floating point constants;
11042 TARGET_PRINT_OPERAND must handle them. */
11047 /* Some assemblers need integer constants to appear first. */
11049 {
11053 }
11054 else
11055 {
11060 }
11077 {
11092 /* FIXME: This might be @TPOFF in Sun ld too. */
11101 else
11111 else
11117 #if TARGET_MACHO
11122 #endif
11126 }
11131 }
11132 }
11134 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11135 We need to emit DTP-relative relocations. */
11137 static void ATTRIBUTE_UNUSED
11139 {
11144 {
11152 }
11153 }
11155 /* Return true if X is a representation of the PIC register. This copes
11156 with calls from ix86_find_base_term, where the register might have
11157 been replaced by a cselib value. */
11159 static bool
11161 {
11165 else
11167 }
11169 /* In the name of slightly smaller debug output, and to cater to
11170 general assembler lossage, recognize PIC+GOTOFF and turn it back
11171 into a direct symbol reference.
11173 On Darwin, this is necessary to avoid a crash, because Darwin
11174 has a different PIC label for each routine but the DWARF debugging
11175 information is not associated with any particular routine, so it's
11176 necessary to remove references to the PIC label from RTL stored by
11177 the DWARF output code. */
11179 static rtx
11181 {
11183 /* addend is NULL or some rtx if x is something+GOTOFF where
11184 something doesn't include the PIC register. */
11186 /* reg_addend is NULL or a multiple of some register. */
11188 /* const_addend is NULL or a const_int. */
11190 /* This is the result, or NULL. */
11199 {
11209 }
11216 /* %ebx + GOT/GOTOFF */
11217 ;
11219 {
11220 /* %ebx + %reg * scale + GOT/GOTOFF */
11226 else
11227 {
11230 }
11231 }
11232 else
11238 {
11241 }
11260 {
11261 /* If the rest of original X doesn't involve the PIC register, add
11262 addend and subtract pic_offset_table_rtx. This can happen e.g.
11263 for code like:
11264 leal (%ebx, %ecx, 4), %ecx
11265 ...
11266 movl foo@GOTOFF(%ecx), %edx
11267 in which case we return (%ecx - %ebx) + foo. */
11270 pic_offset_table_rtx),
11271 result);
11272 else
11274 }
11278 }
11280 /* If X is a machine specific address (i.e. a symbol or label being
11281 referenced as a displacement from the GOT implemented using an
11282 UNSPEC), then return the base term. Otherwise return X. */
11284 rtx
11286 {
11287 rtx term;
11290 {
11303 }
11306 }
11307 \f
11308 static void
11311 {
11315 {
11318 }
11323 {
11326 {
11345 }
11349 {
11368 }
11375 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
11376 Those same assemblers have the same but opposite lossage on cmov. */
11381 else
11386 {
11399 }
11407 {
11420 }
11423 /* ??? As above. */
11432 /* ??? As above. */
11437 else
11448 }
11450 }
11452 /* Print the name of register X to FILE based on its machine mode and number.
11453 If CODE is 'w', pretend the mode is HImode.
11454 If CODE is 'b', pretend the mode is QImode.
11455 If CODE is 'k', pretend the mode is SImode.
11456 If CODE is 'q', pretend the mode is DImode.
11457 If CODE is 'x', pretend the mode is V4SFmode.
11458 If CODE is 't', pretend the mode is V8SFmode.
11459 If CODE is 'h', pretend the reg is the 'high' byte register.
11460 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11461 If CODE is 'd', duplicate the operand for AVX instruction.
11462 */
11464 void
11466 {
11481 {
11485 }
11503 else
11506 /* Irritatingly, AMD extended registers use different naming convention
11507 from the normal registers. */
11509 {
11512 {
11531 }
11533 }
11537 {
11540 {
11543 }
11544 /* FALLTHRU */
11550 /* FALLTHRU */
11553 normal:
11568 {
11573 }
11577 }
11581 {
11584 else
11586 }
11587 }
11589 /* Locate some local-dynamic symbol still in use by this function
11590 so that we can print its name in some tls_local_dynamic_base
11591 pattern. */
11593 static int
11595 {
11600 {
11603 }
11606 }
11610 {
11611 rtx insn;
11622 }
11624 /* Meaning of CODE:
11625 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11626 C -- print opcode suffix for set/cmov insn.
11627 c -- like C, but print reversed condition
11628 F,f -- likewise, but for floating-point.
11629 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11630 otherwise nothing
11631 R -- print the prefix for register names.
11632 z -- print the opcode suffix for the size of the current operand.
11633 Z -- likewise, with special suffixes for x87 instructions.
11634 * -- print a star (in certain assembler syntax)
11635 A -- print an absolute memory reference.
11636 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11637 s -- print a shift double count, followed by the assemblers argument
11638 delimiter.
11639 b -- print the QImode name of the register for the indicated operand.
11640 %b0 would print %al if operands[0] is reg 0.
11641 w -- likewise, print the HImode name of the register.
11642 k -- likewise, print the SImode name of the register.
11643 q -- likewise, print the DImode name of the register.
11644 x -- likewise, print the V4SFmode name of the register.
11645 t -- likewise, print the V8SFmode name of the register.
11646 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11647 y -- print "st(0)" instead of "st" as a register.
11648 d -- print duplicated register operand for AVX instruction.
11649 D -- print condition for SSE cmp instruction.
11650 P -- if PIC, print an @PLT suffix.
11651 X -- don't print any sort of PIC '@' suffix for a symbol.
11652 & -- print some in-use local-dynamic symbol name.
11653 H -- print a memory address offset by 8; used for sse high-parts
11654 Y -- print condition for XOP pcom* instruction.
11655 + -- print a branch hint as 'cs' or 'ds' prefix
11656 ; -- print a semicolon (after prefixes due to bug in older gas).
11657 */
11659 void
11661 {
11663 {
11665 {
11672 {
11677 else
11680 }
11684 {
11690 /* Intel syntax. For absolute addresses, registers should not
11691 be surrounded by braces. */
11693 {
11698 }
11703 }
11741 {
11742 /* Opcodes don't get size suffixes if using Intel opcodes. */
11747 {
11765 output_operand_lossage
11768 }
11769 }
11772 warning
11774 /* FALLTHRU */
11777 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11782 {
11784 {
11786 #ifdef HAVE_AS_IX86_FILDS
11788 #endif
11796 #ifdef HAVE_AS_IX86_FILDQ
11798 #else
11800 #endif
11805 }
11806 }
11808 {
11809 /* 387 opcodes don't get size suffixes
11810 if the operands are registers. */
11815 {
11831 }
11832 }
11833 else
11834 {
11835 output_operand_lossage
11838 }
11840 output_operand_lossage
11859 {
11862 }
11866 /* Little bit of braindamage here. The SSE compare instructions
11867 does use completely different names for the comparisons that the
11868 fp conditional moves. */
11870 {
11872 {
11919 }
11920 }
11921 else
11922 {
11924 {
11959 }
11960 }
11963 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11965 {
11967 {
11974 }
11976 }
11977 #endif
11981 {
11983 "condition code, invalid operand code "
11986 }
11991 {
11993 "condition code, invalid operand code "
11996 }
11997 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
12000 #endif
12004 /* Like above, but reverse condition */
12006 /* Check to see if argument to %c is really a constant
12007 and not a condition code which needs to be reversed. */
12009 {
12011 "condition code, invalid operand "
12014 }
12019 {
12021 "condition code, invalid operand "
12024 }
12025 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
12028 #endif
12033 /* It doesn't actually matter what mode we use here, as we're
12034 only going to use this for printing. */
12039 {
12040 rtx x;
12048 {
12053 {
12057 /* Emit hints only in the case default branch prediction
12058 heuristics would fail. */
12060 {
12061 /* We use 3e (DS) prefix for taken branches and
12062 2e (CS) prefix for not taken branches. */
12065 else
12067 }
12068 }
12069 }
12071 }
12075 {
12126 }
12130 #if TARGET_MACHO || !HAVE_AS_IX86_REP_LOCK_PREFIX
12132 #endif
12137 }
12138 }
12144 {
12145 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
12148 {
12151 {
12160 else
12166 }
12168 /* Check for explicit size override (codes 'b', 'w' and 'k') */
12178 }
12181 /* Avoid (%rip) for call operands. */
12187 else
12189 }
12192 {
12193 REAL_VALUE_TYPE r;
12202 }
12204 /* These float cases don't actually occur as immediate operands. */
12206 {
12211 }
12215 {
12220 }
12222 else
12223 {
12224 /* We have patterns that allow zero sets of memory, for instance.
12225 In 64-bit mode, we should probably support all 8-byte vectors,
12226 since we can in fact encode that into an immediate. */
12228 {
12231 }
12234 {
12236 {
12239 }
12242 {
12245 else
12247 }
12248 }
12253 else
12255 }
12256 }
12258 static bool
12260 {
12262 }
12263 \f
12264 /* Print a memory operand whose address is ADDR. */
12266 static void
12268 {
12282 {
12293 }
12295 /* Use one byte shorter RIP relative addressing for 64bit mode. */
12297 {
12309 }
12311 {
12312 /* Displacement only requires special attention. */
12315 {
12319 }
12322 else
12324 }
12325 else
12326 {
12328 {
12330 {
12335 else
12337 }
12343 {
12348 }
12350 }
12351 else
12352 {
12356 {
12357 /* Pull out the offset of a symbol; print any symbol itself. */
12361 {
12365 }
12373 else
12375 }
12379 {
12382 {
12386 }
12387 }
12390 else
12394 {
12399 }
12401 }
12402 }
12403 }
12405 bool
12407 {
12408 rtx op;
12415 {
12418 /* FIXME: This might be @TPOFF in Sun ld. */
12429 else
12441 else
12448 #if TARGET_MACHO
12454 #endif
12458 }
12461 }
12462 \f
12463 /* Split one or more DImode RTL references into pairs of SImode
12464 references. The RTL can be REG, offsettable MEM, integer constant, or
12465 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12466 split and "num" is its length. lo_half and hi_half are output arrays
12467 that parallel "operands". */
12469 void
12471 {
12473 {
12476 /* simplify_subreg refuse to split volatile memory addresses,
12477 but we still have to handle it. */
12479 {
12482 }
12483 else
12484 {
12491 }
12492 }
12493 }
12494 /* Split one or more TImode RTL references into pairs of DImode
12495 references. The RTL can be REG, offsettable MEM, integer constant, or
12496 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12497 split and "num" is its length. lo_half and hi_half are output arrays
12498 that parallel "operands". */
12500 void
12502 {
12504 {
12507 /* simplify_subreg refuse to split volatile memory addresses, but we
12508 still have to handle it. */
12510 {
12513 }
12514 else
12515 {
12518 }
12519 }
12520 }
12521 \f
12522 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12523 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12524 is the expression of the binary operation. The output may either be
12525 emitted here, or returned to the caller, like all output_* functions.
12527 There is no guarantee that the operands are the same mode, as they
12528 might be within FLOAT or FLOAT_EXTEND expressions. */
12530 #ifndef SYSV386_COMPAT
12531 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12532 wants to fix the assemblers because that causes incompatibility
12533 with gcc. No-one wants to fix gcc because that causes
12534 incompatibility with assemblers... You can use the option of
12535 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12536 #define SYSV386_COMPAT 1
12537 #endif
12541 {
12547 #ifdef ENABLE_CHECKING
12548 /* Even if we do not want to check the inputs, this documents input
12549 constraints. Which helps in understanding the following code. */
12559 else
12561 #endif
12564 {
12569 else
12578 else
12587 else
12596 else
12603 }
12606 {
12608 {
12612 else
12614 }
12615 else
12616 {
12620 else
12622 }
12624 }
12628 {
12632 {
12636 }
12638 /* know operands[0] == operands[1]. */
12641 {
12644 }
12647 {
12649 /* How is it that we are storing to a dead operand[2]?
12650 Well, presumably operands[1] is dead too. We can't
12651 store the result to st(0) as st(0) gets popped on this
12652 instruction. Instead store to operands[2] (which I
12653 think has to be st(1)). st(1) will be popped later.
12654 gcc <= 2.8.1 didn't have this check and generated
12655 assembly code that the Unixware assembler rejected. */
12657 else
12660 }
12664 else
12671 {
12674 }
12677 {
12680 }
12683 {
12684 #if SYSV386_COMPAT
12685 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12686 derived assemblers, confusingly reverse the direction of
12687 the operation for fsub{r} and fdiv{r} when the
12688 destination register is not st(0). The Intel assembler
12689 doesn't have this brain damage. Read !SYSV386_COMPAT to
12690 figure out what the hardware really does. */
12693 else
12695 #else
12697 /* As above for fmul/fadd, we can't store to st(0). */
12699 else
12701 #endif
12703 }
12706 {
12707 #if SYSV386_COMPAT
12710 else
12712 #else
12715 else
12717 #endif
12719 }
12722 {
12725 else
12728 }
12730 {
12731 #if SYSV386_COMPAT
12733 #else
12735 #endif
12736 }
12737 else
12738 {
12739 #if SYSV386_COMPAT
12741 #else
12743 #endif
12744 }
12749 }
12753 }
12755 /* Return needed mode for entity in optimize_mode_switching pass. */
12757 int
12759 {
12762 /* The mode UNINITIALIZED is used to store control word after a
12763 function call or ASM pattern. The mode ANY specify that function
12764 has no requirements on the control word and make no changes in the
12765 bits we are interested in. */
12779 {
12802 }
12805 }
12807 /* Output code to initialize control word copies used by trunc?f?i and
12808 rounding patterns. CURRENT_MODE is set to current control word,
12809 while NEW_MODE is set to new control word. */
12811 void
12813 {
12815 rtx new_mode;
12826 {
12828 {
12830 /* round toward zero (truncate) */
12836 /* round down toward -oo */
12843 /* round up toward +oo */
12850 /* mask precision exception for nearbyint() */
12857 }
12858 }
12859 else
12860 {
12862 {
12864 /* round toward zero (truncate) */
12870 /* round down toward -oo */
12876 /* round up toward +oo */
12882 /* mask precision exception for nearbyint() */
12889 }
12890 }
12896 }
12898 /* Output code for INSN to convert a float to a signed int. OPERANDS
12899 are the insn operands. The output may be [HSD]Imode and the input
12900 operand may be [SDX]Fmode. */
12904 {
12909 /* Jump through a hoop or two for DImode, since the hardware has no
12910 non-popping instruction. We used to do this a different way, but
12911 that was somewhat fragile and broke with post-reload splitters. */
12921 else
12922 {
12927 else
12931 }
12934 }
12936 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12937 have the values zero or one, indicates the ffreep insn's operand
12938 from the OPERANDS array. */
12942 {
12944 #ifdef HAVE_AS_IX86_FFREEP
12946 #else
12947 {
12957 }
12958 #endif
12961 }
12964 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12965 should be used. UNORDERED_P is true when fucom should be used. */
12969 {
12975 {
12978 }
12979 else
12980 {
12983 }
12986 {
12995 else
12997 else
13000 else
13002 }
13009 {
13011 {
13014 }
13015 else
13017 }
13020 && stack_top_dies
13023 {
13024 /* If both the top of the 387 stack dies, and the other operand
13025 is also a stack register that dies, then this must be a
13026 `fcompp' float compare */
13029 {
13030 /* There is no double popping fcomi variant. Fortunately,
13031 eflags is immune from the fstp's cc clobbering. */
13034 else
13037 }
13038 else
13039 {
13042 else
13044 }
13045 }
13046 else
13047 {
13048 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
13051 {
13059 NULL,
13060 NULL,
13067 NULL,
13068 NULL,
13069 NULL,
13070 NULL
13071 };
13086 }
13087 }
13089 void
13091 {
13094 #ifdef ASM_QUAD
13097 #else
13099 #endif
13102 }
13104 void
13106 {
13109 #ifdef ASM_QUAD
13112 #else
13114 #endif
13115 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
13121 #if TARGET_MACHO
13123 {
13127 }
13128 #endif
13129 else
13132 }
13133 \f
13134 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
13135 for the target. */
13137 void
13139 {
13140 rtx tmp;
13142 /* We play register width games, which are only valid after reload. */
13145 /* Avoid HImode and its attendant prefix byte. */
13150 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
13152 {
13155 }
13158 }
13160 /* X is an unchanging MEM. If it is a constant pool reference, return
13161 the constant pool rtx, else NULL. */
13163 rtx
13165 {
13172 }
13174 void
13176 {
13184 {
13187 {
13192 }
13196 }
13200 {
13213 {
13219 }
13220 }
13223 {
13225 {
13226 #if TARGET_MACHO
13228 {
13229 rtx temp = ((reload_in_progress
13236 }
13241 #endif
13242 }
13243 else
13244 {
13248 {
13253 }
13254 }
13255 }
13256 else
13257 {
13268 /* Force large constants in 64bit compilation into register
13269 to get them CSEed. */
13281 {
13282 /* If we are loading a floating point constant to a register,
13283 force the value to memory now, since we'll get better code
13284 out the back end. */
13288 {
13293 }
13294 }
13295 }
13298 }
13300 void
13302 {
13306 /* Force constants other than zero into memory. We do not know how
13307 the instructions used to build constants modify the upper 64 bits
13308 of the register, once we have that information we may be able
13309 to handle some of them more efficiently. */
13318 /* We need to check memory alignment for SSE mode since attribute
13319 can make operands unaligned. */
13324 {
13327 /* ix86_expand_vector_move_misalign() does not like constants ... */
13333 /* ... nor both arguments in memory. */
13341 }
13343 /* Make operand1 a register if it isn't already. */
13347 {
13350 }
13353 }
13355 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
13356 straight to ix86_expand_vector_move. */
13357 /* Code generation for scalar reg-reg moves of single and double precision data:
13358 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
13359 movaps reg, reg
13360 else
13361 movss reg, reg
13362 if (x86_sse_partial_reg_dependency == true)
13363 movapd reg, reg
13364 else
13365 movsd reg, reg
13367 Code generation for scalar loads of double precision data:
13368 if (x86_sse_split_regs == true)
13369 movlpd mem, reg (gas syntax)
13370 else
13371 movsd mem, reg
13373 Code generation for unaligned packed loads of single precision data
13374 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
13375 if (x86_sse_unaligned_move_optimal)
13376 movups mem, reg
13378 if (x86_sse_partial_reg_dependency == true)
13379 {
13380 xorps reg, reg
13381 movlps mem, reg
13382 movhps mem+8, reg
13383 }
13384 else
13385 {
13386 movlps mem, reg
13387 movhps mem+8, reg
13388 }
13390 Code generation for unaligned packed loads of double precision data
13391 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
13392 if (x86_sse_unaligned_move_optimal)
13393 movupd mem, reg
13395 if (x86_sse_split_regs == true)
13396 {
13397 movlpd mem, reg
13398 movhpd mem+8, reg
13399 }
13400 else
13401 {
13402 movsd mem, reg
13403 movhpd mem+8, reg
13404 }
13405 */
13407 void
13409 {
13416 {
13418 {
13422 {
13424 /* If we're optimizing for size, movups is the smallest. */
13426 {
13431 }
13443 }
13450 {
13459 {
13464 }
13472 }
13477 }
13480 }
13483 {
13484 /* If we're optimizing for size, movups is the smallest. */
13487 {
13492 }
13494 /* ??? If we have typed data, then it would appear that using
13495 movdqu is the only way to get unaligned data loaded with
13496 integer type. */
13498 {
13503 }
13506 {
13507 rtx zero;
13510 {
13515 }
13517 /* When SSE registers are split into halves, we can avoid
13518 writing to the top half twice. */
13520 {
13523 }
13524 else
13525 {
13526 /* ??? Not sure about the best option for the Intel chips.
13527 The following would seem to satisfy; the register is
13528 entirely cleared, breaking the dependency chain. We
13529 then store to the upper half, with a dependency depth
13530 of one. A rumor has it that Intel recommends two movsd
13531 followed by an unpacklpd, but this is unconfirmed. And
13532 given that the dependency depth of the unpacklpd would
13533 still be one, I'm not sure why this would be better. */
13535 }
13541 }
13542 else
13543 {
13545 {
13550 }
13554 else
13563 }
13564 }
13566 {
13567 /* If we're optimizing for size, movups is the smallest. */
13570 {
13575 }
13577 /* ??? Similar to above, only less clear because of quote
13578 typeless stores unquote. */
13581 {
13586 }
13589 {
13591 {
13595 }
13596 else
13597 {
13602 }
13603 }
13604 else
13605 {
13610 {
13613 }
13614 else
13615 {
13620 }
13621 }
13622 }
13623 else
13625 }
13627 /* Expand a push in MODE. This is some mode for which we do not support
13628 proper push instructions, at least from the registers that we expect
13629 the value to live in. */
13631 void
13633 {
13634 rtx tmp;
13644 /* When we push an operand onto stack, it has to be aligned at least
13645 at the function argument boundary. However since we don't have
13646 the argument type, we can't determine the actual argument
13647 boundary. */
13649 }
13651 /* Helper function of ix86_fixup_binary_operands to canonicalize
13652 operand order. Returns true if the operands should be swapped. */
13654 static bool
13656 rtx operands[])
13657 {
13662 /* If the operation is not commutative, we can't do anything. */
13666 /* Highest priority is that src1 should match dst. */
13672 /* Next highest priority is that immediate constants come second. */
13678 /* Lowest priority is that memory references should come second. */
13685 }
13688 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13689 destination to use for the operation. If different from the true
13690 destination in operands[0], a copy operation will be required. */
13692 rtx
13694 rtx operands[])
13695 {
13700 /* Canonicalize operand order. */
13702 {
13703 rtx temp;
13705 /* It is invalid to swap operands of different modes. */
13711 }
13713 /* Both source operands cannot be in memory. */
13715 {
13716 /* Optimization: Only read from memory once. */
13718 {
13721 }
13722 else
13724 }
13726 /* If the destination is memory, and we do not have matching source
13727 operands, do things in registers. */
13731 /* Source 1 cannot be a constant. */
13735 /* Source 1 cannot be a non-matching memory. */
13742 }
13744 /* Similarly, but assume that the destination has already been
13745 set up properly. */
13747 void
13750 {
13753 }
13755 /* Attempt to expand a binary operator. Make the expansion closer to the
13756 actual machine, then just general_operand, which will allow 3 separate
13757 memory references (one output, two input) in a single insn. */
13759 void
13761 rtx operands[])
13762 {
13769 /* Emit the instruction. */
13773 {
13774 /* Reload doesn't know about the flags register, and doesn't know that
13775 it doesn't want to clobber it. We can only do this with PLUS. */
13778 }
13779 else
13780 {
13783 }
13785 /* Fix up the destination if needed. */
13788 }
13790 /* Return TRUE or FALSE depending on whether the binary operator meets the
13791 appropriate constraints. */
13793 int
13796 {
13801 /* Both source operands cannot be in memory. */
13805 /* Canonicalize operand order for commutative operators. */
13807 {
13811 }
13813 /* If the destination is memory, we must have a matching source operand. */
13817 /* Source 1 cannot be a constant. */
13821 /* Source 1 cannot be a non-matching memory. */
13826 }
13828 /* Attempt to expand a unary operator. Make the expansion closer to the
13829 actual machine, then just general_operand, which will allow 2 separate
13830 memory references (one output, one input) in a single insn. */
13832 void
13834 rtx operands[])
13835 {
13842 /* If the destination is memory, and we do not have matching source
13843 operands, do things in registers. */
13846 {
13849 else
13851 }
13853 /* When source operand is memory, destination must match. */
13857 /* Emit the instruction. */
13861 {
13862 /* Reload doesn't know about the flags register, and doesn't know that
13863 it doesn't want to clobber it. */
13866 }
13867 else
13868 {
13871 }
13873 /* Fix up the destination if needed. */
13876 }
13878 #define LEA_SEARCH_THRESHOLD 12
13880 /* Search backward for non-agu definition of register number REGNO1
13881 or register number REGNO2 in INSN's basic block until
13882 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13883 2. Reach BB boundary, or
13884 3. Reach agu definition.
13885 Returns the distance between the non-agu definition point and INSN.
13886 If no definition point, returns -1. */
13888 static int
13890 rtx insn)
13891 {
13898 {
13901 {
13903 {
13904 distance++;
13910 {
13914 }
13915 }
13919 }
13920 }
13923 {
13924 edge e;
13925 edge_iterator ei;
13930 {
13933 }
13936 {
13941 {
13943 {
13944 distance++;
13950 {
13954 }
13955 }
13957 }
13958 }
13959 }
13963 done:
13964 /* get_attr_type may modify recog data. We want to make sure
13965 that recog data is valid for instruction INSN, on which
13966 distance_non_agu_define is called. INSN is unchanged here. */
13969 }
13971 /* Return the distance between INSN and the next insn that uses
13972 register number REGNO0 in memory address. Return -1 if no such
13973 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13975 static int
13977 {
13984 {
13987 {
13989 {
13990 distance++;
13996 {
13997 /* Return DISTANCE if OP0 is used in memory
13998 address in NEXT. */
14000 }
14006 {
14007 /* Return -1 if OP0 is set in NEXT. */
14009 }
14010 }
14014 }
14015 }
14018 {
14019 edge e;
14020 edge_iterator ei;
14025 {
14028 }
14031 {
14036 {
14038 {
14039 distance++;
14045 {
14046 /* Return DISTANCE if OP0 is used in memory
14047 address in NEXT. */
14049 }
14055 {
14056 /* Return -1 if OP0 is set in NEXT. */
14058 }
14060 }
14062 }
14063 }
14064 }
14067 }
14069 /* Define this macro to tune LEA priority vs ADD, it take effect when
14070 there is a dilemma of choicing LEA or ADD
14071 Negative value: ADD is more preferred than LEA
14072 Zero: Netrual
14073 Positive value: LEA is more preferred than ADD*/
14074 #define IX86_LEA_PRIORITY 2
14076 /* Return true if it is ok to optimize an ADD operation to LEA
14077 operation to avoid flag register consumation. For the processors
14078 like ATOM, if the destination register of LEA holds an actual
14079 address which will be used soon, LEA is better and otherwise ADD
14080 is better. */
14082 bool
14085 {
14095 /* If a = b + c, (a!=b && a!=c), must use lea form. */
14098 else
14099 {
14105 /* If this insn has both backward non-agu dependence and forward
14106 agu dependence, the one with short distance take effect. */
14113 }
14114 }
14116 /* Return true if destination reg of SET_BODY is shift count of
14117 USE_BODY. */
14119 static bool
14121 {
14122 rtx set_dest;
14123 rtx shift_rtx;
14126 /* Retrieve destination of SET_BODY. */
14128 {
14137 use_body))
14142 }
14144 /* Retrieve shift count of USE_BODY. */
14146 {
14158 }
14166 {
14169 /* Return true if shift count is dest of SET_BODY. */
14173 }
14176 }
14178 /* Return true if destination reg of SET_INSN is shift count of
14179 USE_INSN. */
14181 bool
14183 {
14186 }
14188 /* Return TRUE or FALSE depending on whether the unary operator meets the
14189 appropriate constraints. */
14191 int
14195 {
14196 /* If one of operands is memory, source and destination must match. */
14202 }
14204 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
14205 are ok, keeping in mind the possible movddup alternative. */
14207 bool
14209 {
14215 }
14217 /* Post-reload splitter for converting an SF or DFmode value in an
14218 SSE register into an unsigned SImode. */
14220 void
14222 {
14233 /* Load up the value into the low element. We must ensure that the other
14234 elements are valid floats -- zero is the easiest such value. */
14236 {
14239 else
14241 }
14242 else
14243 {
14248 else
14250 }
14270 else
14275 }
14277 /* Convert an unsigned DImode value into a DFmode, using only SSE.
14278 Expects the 64-bit DImode to be supplied in a pair of integral
14279 registers. Requires SSE2; will use SSE3 if available. For x86_32,
14280 -mfpmath=sse, !optimize_size only. */
14282 void
14284 {
14288 rtx x;
14294 {
14297 }
14298 else
14299 {
14303 }
14311 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
14314 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
14315 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
14316 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
14317 (0x1.0p84 + double(fp_value_hi_xmm)).
14318 Note these exponents differ by 32. */
14322 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
14323 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
14332 /* Add the upper and lower DFmode values together. */
14335 else
14336 {
14340 }
14343 }
14345 /* Not used, but eases macroization of patterns. */
14346 void
14348 rtx input ATTRIBUTE_UNUSED)
14349 {
14351 }
14353 /* Convert an unsigned SImode value into a DFmode. Only currently used
14354 for SSE, but applicable anywhere. */
14356 void
14358 {
14359 REAL_VALUE_TYPE TWO31r;
14374 }
14376 /* Convert a signed DImode value into a DFmode. Only used for SSE in
14377 32-bit mode; otherwise we have a direct convert instruction. */
14379 void
14381 {
14382 REAL_VALUE_TYPE TWO32r;
14400 }
14402 /* Convert an unsigned SImode value into a SFmode, using only SSE.
14403 For x86_32, -mfpmath=sse, !optimize_size only. */
14404 void
14406 {
14407 REAL_VALUE_TYPE ONE16r;
14426 }
14428 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
14429 then replicate the value for all elements of the vector
14430 register. */
14432 rtx
14434 {
14435 rtvec v;
14437 {
14451 else
14459 else
14465 }
14466 }
14468 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
14469 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
14470 for an SSE register. If VECT is true, then replicate the mask for
14471 all elements of the vector register. If INVERT is true, then create
14472 a mask excluding the sign bit. */
14474 rtx
14476 {
14480 rtx v;
14481 rtx mask;
14483 /* Find the sign bit, sign extended to 2*HWI. */
14485 {
14499 else
14507 {
14510 }
14511 else
14512 {
14513 rtvec vec;
14519 {
14522 }
14523 else
14533 }
14538 }
14543 /* Force this value into the low part of a fp vector constant. */
14552 }
14554 /* Generate code for floating point ABS or NEG. */
14556 void
14558 rtx operands[])
14559 {
14566 {
14569 }
14575 /* NEG and ABS performed with SSE use bitwise mask operations.
14576 Create the appropriate mask now. */
14579 else
14586 {
14590 }
14591 else
14592 {
14596 {
14601 }
14602 else
14604 }
14605 }
14607 /* Expand a copysign operation. Special case operand 0 being a constant. */
14609 void
14611 {
14622 {
14629 {
14636 else
14637 {
14641 }
14642 }
14652 else
14656 }
14657 else
14658 {
14668 else
14672 }
14673 }
14675 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14676 be a constant, and so has already been expanded into a vector constant. */
14678 void
14680 {
14696 {
14699 }
14700 }
14702 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14703 so we have to do two masks. */
14705 void
14707 {
14722 {
14723 /* Shouldn't happen often (it's useless, obviously), but when it does
14724 we'd generate incorrect code if we continue below. */
14727 }
14730 {
14741 }
14742 else
14743 {
14745 {
14747 }
14749 {
14753 }
14757 {
14760 }
14762 {
14767 }
14769 }
14773 }
14775 /* Return TRUE or FALSE depending on whether the first SET in INSN
14776 has source and destination with matching CC modes, and that the
14777 CC mode is at least as constrained as REQ_MODE. */
14779 int
14781 {
14782 rtx set;
14793 {
14803 /* FALLTHRU */
14807 /* FALLTHRU */
14811 /* FALLTHRU */
14821 }
14824 }
14826 /* Generate insn patterns to do an integer compare of OPERANDS. */
14828 static rtx
14830 {
14837 /* This is very simple, but making the interface the same as in the
14838 FP case makes the rest of the code easier. */
14842 /* Return the test that should be put into the flags user, i.e.
14843 the bcc, scc, or cmov instruction. */
14845 }
14847 /* Figure out whether to use ordered or unordered fp comparisons.
14848 Return the appropriate mode to use. */
14850 enum machine_mode
14852 {
14853 /* ??? In order to make all comparisons reversible, we do all comparisons
14854 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14855 all forms trapping and nontrapping comparisons, we can make inequality
14856 comparisons trapping again, since it results in better code when using
14857 FCOM based compares. */
14859 }
14861 enum machine_mode
14863 {
14867 {
14870 }
14873 {
14874 /* Only zero flag is needed. */
14878 /* Codes needing carry flag. */
14881 /* Detect overflow checks. They need just the carry flag. */
14885 else
14889 /* Detect overflow checks. They need just the carry flag. */
14893 else
14895 /* Codes possibly doable only with sign flag when
14896 comparing against zero. */
14901 else
14902 /* For other cases Carry flag is not required. */
14904 /* Codes doable only with sign flag when comparing
14905 against zero, but we miss jump instruction for it
14906 so we need to use relational tests against overflow
14907 that thus needs to be zero. */
14912 else
14914 /* strcmp pattern do (use flags) and combine may ask us for proper
14915 mode. */
14920 }
14921 }
14923 /* Return the fixed registers used for condition codes. */
14925 static bool
14927 {
14931 }
14933 /* If two condition code modes are compatible, return a condition code
14934 mode which is compatible with both. Otherwise, return
14935 VOIDmode. */
14937 static enum machine_mode
14939 {
14951 {
14965 {
14979 }
14983 /* These are only compatible with themselves, which we already
14984 checked above. */
14986 }
14987 }
14990 /* Return a comparison we can do and that it is equivalent to
14991 swap_condition (code) apart possibly from orderedness.
14992 But, never change orderedness if TARGET_IEEE_FP, returning
14993 UNKNOWN in that case if necessary. */
14995 static enum rtx_code
14997 {
14999 {
15010 }
15011 }
15013 /* Return cost of comparison CODE using the best strategy for performance.
15014 All following functions do use number of instructions as a cost metrics.
15015 In future this should be tweaked to compute bytes for optimize_size and
15016 take into account performance of various instructions on various CPUs. */
15018 static int
15020 {
15023 /* The cost of code using bit-twiddling on %ah. */
15025 {
15048 }
15051 {
15058 }
15059 }
15061 /* Return strategy to use for floating-point. We assume that fcomi is always
15062 preferrable where available, since that is also true when looking at size
15063 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
15065 enum ix86_fpcmp_strategy
15067 {
15068 /* Do fcomi/sahf based test when profitable. */
15077 }
15079 /* Swap, force into registers, or otherwise massage the two operands
15080 to a fp comparison. The operands are updated in place; the new
15081 comparison code is returned. */
15083 static enum rtx_code
15085 {
15091 /* All of the unordered compare instructions only work on registers.
15092 The same is true of the fcomi compare instructions. The XFmode
15093 compare instructions require registers except when comparing
15094 against zero or when converting operand 1 from fixed point to
15095 floating point. */
15104 {
15107 }
15108 else
15109 {
15110 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
15111 things around if they appear profitable, otherwise force op0
15112 into a register. */
15118 {
15121 {
15122 rtx tmp;
15125 }
15126 }
15132 {
15137 {
15140 }
15141 else
15143 }
15144 }
15146 /* Try to rearrange the comparison to make it cheaper. */
15150 {
15151 rtx tmp;
15156 }
15161 }
15163 /* Convert comparison codes we use to represent FP comparison to integer
15164 code that will result in proper branch. Return UNKNOWN if no such code
15165 is available. */
15167 enum rtx_code
15169 {
15171 {
15194 }
15195 }
15197 /* Generate insn patterns to do a floating point compare of OPERANDS. */
15199 static rtx
15201 {
15208 /* Do fcomi/sahf based test when profitable. */
15210 {
15215 tmp);
15223 tmp);
15232 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
15239 /* In the unordered case, we have to check C2 for NaN's, which
15240 doesn't happen to work out to anything nice combination-wise.
15241 So do some bit twiddling on the value we've got in AH to come
15242 up with an appropriate set of condition codes. */
15246 {
15250 {
15253 }
15254 else
15255 {
15261 }
15266 {
15271 }
15272 else
15273 {
15276 }
15281 {
15284 }
15285 else
15286 {
15290 }
15295 {
15301 }
15302 else
15303 {
15306 }
15311 {
15316 }
15317 else
15318 {
15321 }
15326 {
15331 }
15332 else
15333 {
15336 }
15350 }
15355 }
15357 /* Return the test that should be put into the flags user, i.e.
15358 the bcc, scc, or cmov instruction. */
15361 const0_rtx);
15362 }
15364 rtx
15366 {
15375 {
15378 }
15379 else
15383 }
15385 void
15387 {
15388 rtx tmp;
15391 {
15398 simple:
15402 pc_rtx);
15410 /* Expand DImode branch into multiple compare+branch. */
15411 {
15417 {
15422 }
15424 {
15428 }
15429 else
15430 {
15434 }
15436 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15437 avoid two branches. This costs one extra insn, so disable when
15438 optimizing for size. */
15443 {
15463 }
15465 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15466 op1 is a constant and the low word is zero, then we can just
15467 examine the high word. Similarly for low word -1 and
15468 less-or-equal-than or greater-than. */
15472 {
15475 {
15480 }
15484 {
15489 }
15493 }
15495 /* Otherwise, we need two or three jumps. */
15504 {
15518 }
15520 /*
15521 * a < b =>
15522 * if (hi(a) < hi(b)) goto true;
15523 * if (hi(a) > hi(b)) goto false;
15524 * if (lo(a) < lo(b)) goto true;
15525 * false:
15526 */
15543 }
15546 /* If we have already emitted a compare insn, go straight to simple.
15547 ix86_expand_compare won't emit anything if ix86_compare_emitted
15548 is non NULL. */
15551 }
15552 }
15554 /* Split branch based on floating point condition. */
15555 void
15558 {
15559 rtx condition;
15560 rtx i;
15563 {
15568 }
15571 tmp);
15573 /* Remove pushed operand from stack. */
15583 }
15585 void
15587 {
15588 rtx ret;
15595 }
15597 /* Expand comparison setting or clearing carry flag. Return true when
15598 successful and set pop for the operation. */
15599 static bool
15601 {
15605 /* Do not handle DImode compares that go through special path. */
15610 {
15615 /* Shortcut: following common codes never translate
15616 into carry flag compares. */
15621 /* These comparisons require zero flag; swap operands so they won't. */
15624 {
15629 }
15631 /* Try to expand the comparison and verify that we end up with
15632 carry flag based comparison. This fails to be true only when
15633 we decide to expand comparison using arithmetic that is not
15634 too common scenario. */
15643 else
15652 }
15658 {
15663 /* Convert a==0 into (unsigned)a<1. */
15672 /* Convert a>b into b<a or a>=b-1. */
15676 {
15678 /* Bail out on overflow. We still can swap operands but that
15679 would force loading of the constant into register. */
15684 }
15685 else
15686 {
15691 }
15694 /* Convert a>=0 into (unsigned)a<0x80000000. */
15712 }
15713 /* Swapping operands may cause constant to appear as first operand. */
15715 {
15719 }
15725 }
15727 int
15729 {
15748 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15749 HImode insns, we'd be swallowed in word prefix ops. */
15755 {
15759 HOST_WIDE_INT diff;
15762 /* Sign bit compares are better done using shifts than we do by using
15763 sbb. */
15767 {
15768 /* Detect overlap between destination and compare sources. */
15772 {
15773 rtx flags;
15782 {
15784 compare_code
15786 }
15788 /* To simplify rest of code, restrict to the GEU case. */
15790 {
15796 }
15797 else
15798 {
15801 reverse_condition_maybe_unordered
15803 else
15806 }
15815 else
15818 }
15819 else
15820 {
15823 else
15824 {
15829 }
15832 }
15835 {
15836 /*
15837 * cmpl op0,op1
15838 * sbbl dest,dest
15839 * [addl dest, ct]
15840 *
15841 * Size 5 - 8.
15842 */
15847 }
15849 {
15850 /*
15851 * cmpl op0,op1
15852 * sbbl dest,dest
15853 * orl $ct, dest
15854 *
15855 * Size 8.
15856 */
15860 }
15862 {
15863 /*
15864 * cmpl op0,op1
15865 * sbbl dest,dest
15866 * notl dest
15867 * [addl dest, cf]
15868 *
15869 * Size 8 - 11.
15870 */
15876 }
15877 else
15878 {
15879 /*
15880 * cmpl op0,op1
15881 * sbbl dest,dest
15882 * [notl dest]
15883 * andl cf - ct, dest
15884 * [addl dest, ct]
15885 *
15886 * Size 8 - 11.
15887 */
15890 {
15894 }
15904 }
15910 }
15913 {
15916 HOST_WIDE_INT tmp;
15921 {
15924 /* We may be reversing unordered compare to normal compare, that
15925 is not valid in general (we may convert non-trapping condition
15926 to trapping one), however on i386 we currently emit all
15927 comparisons unordered. */
15930 }
15931 else
15932 {
15935 }
15936 }
15941 {
15946 {
15951 }
15952 }
15954 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15958 {
15959 /* If lea code below could be used, only optimize
15960 if it results in a 2 insn sequence. */
15966 {
15967 /*
15968 * notl op1 (if necessary)
15969 * sarl $31, op1
15970 * orl cf, op1
15971 */
15973 {
15977 }
15989 }
15990 }
15998 {
15999 /*
16000 * xorl dest,dest
16001 * cmpl op1,op2
16002 * setcc dest
16003 * lea cf(dest*(ct-cf)),dest
16004 *
16005 * Size 14.
16006 *
16007 * This also catches the degenerate setcc-only case.
16008 */
16010 rtx tmp;
16017 /* On x86_64 the lea instruction operates on Pmode, so we need
16018 to get arithmetics done in proper mode to match. */
16021 else
16022 {
16023 rtx out1;
16026 nops++;
16028 {
16030 nops++;
16031 }
16032 }
16034 {
16036 nops++;
16037 }
16039 {
16042 else
16044 }
16049 }
16051 /*
16052 * General case: Jumpful:
16053 * xorl dest,dest cmpl op1, op2
16054 * cmpl op1, op2 movl ct, dest
16055 * setcc dest jcc 1f
16056 * decl dest movl cf, dest
16057 * andl (cf-ct),dest 1:
16058 * addl ct,dest
16059 *
16060 * Size 20. Size 14.
16061 *
16062 * This is reasonably steep, but branch mispredict costs are
16063 * high on modern cpus, so consider failing only if optimizing
16064 * for space.
16065 */
16070 {
16072 {
16079 {
16082 /* We may be reversing unordered compare to normal compare,
16083 that is not valid in general (we may convert non-trapping
16084 condition to trapping one), however on i386 we currently
16085 emit all comparisons unordered. */
16087 }
16088 else
16089 {
16093 }
16094 }
16097 {
16098 /* notl op1 (if needed)
16099 sarl $31, op1
16100 andl (cf-ct), op1
16101 addl ct, op1
16103 For x < 0 (resp. x <= -1) there will be no notl,
16104 so if possible swap the constants to get rid of the
16105 complement.
16106 True/false will be -1/0 while code below (store flag
16107 followed by decrement) is 0/-1, so the constants need
16108 to be exchanged once more. */
16111 {
16114 }
16115 else
16116 {
16120 }
16124 }
16125 else
16126 {
16132 }
16144 }
16145 }
16148 {
16149 /* Try a few things more with specific constants and a variable. */
16151 optab op;
16157 /* If one of the two operands is an interesting constant, load a
16158 constant with the above and mask it in with a logical operation. */
16161 {
16167 else
16169 }
16171 {
16177 else
16179 }
16180 else
16187 /* Recurse to get the constant loaded. */
16191 /* Mask in the interesting variable. */
16193 OPTAB_WIDEN);
16198 }
16200 /*
16201 * For comparison with above,
16202 *
16203 * movl cf,dest
16204 * movl ct,tmp
16205 * cmpl op1,op2
16206 * cmovcc tmp,dest
16207 *
16208 * Size 15.
16209 */
16232 }
16234 /* Swap, force into registers, or otherwise massage the two operands
16235 to an sse comparison with a mask result. Thus we differ a bit from
16236 ix86_prepare_fp_compare_args which expects to produce a flags result.
16238 The DEST operand exists to help determine whether to commute commutative
16239 operators. The POP0/POP1 operands are updated in place. The new
16240 comparison code is returned, or UNKNOWN if not implementable. */
16242 static enum rtx_code
16245 {
16246 rtx tmp;
16249 {
16252 /* We have no LTGT as an operator. We could implement it with
16253 NE & ORDERED, but this requires an extra temporary. It's
16254 not clear that it's worth it. */
16261 /* These are supported directly. */
16268 /* For commutative operators, try to canonicalize the destination
16269 operand to be first in the comparison - this helps reload to
16270 avoid extra moves. */
16273 /* FALLTHRU */
16279 /* These are not supported directly. Swap the comparison operands
16280 to transform into something that is supported. */
16289 }
16292 }
16294 /* Detect conditional moves that exactly match min/max operational
16295 semantics. Note that this is IEEE safe, as long as we don't
16296 interchange the operands.
16298 Returns FALSE if this conditional move doesn't match a MIN/MAX,
16299 and TRUE if the operation is successful and instructions are emitted. */
16301 static bool
16304 {
16307 rtx tmp;
16310 ;
16312 {
16316 }
16317 else
16324 else
16329 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
16330 but MODE may be a vector mode and thus not appropriate. */
16332 {
16334 rtvec v;
16339 }
16340 else
16341 {
16344 }
16348 }
16350 /* Expand an sse vector comparison. Return the register with the result. */
16352 static rtx
16355 {
16357 rtx x;
16372 }
16374 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16375 operations. This is used for both scalar and vector conditional moves. */
16377 static void
16379 {
16384 {
16388 }
16390 {
16395 }
16397 {
16400 op_true,
16401 op_false));
16403 }
16404 else
16405 {
16412 else
16424 }
16425 }
16427 /* Expand a floating-point conditional move. Return true if successful. */
16429 int
16431 {
16439 {
16442 /* Since we've no cmove for sse registers, don't force bad register
16443 allocation just to gain access to it. Deny movcc when the
16444 comparison mode doesn't match the move mode. */
16466 }
16468 /* The floating point conditional move instructions don't directly
16469 support conditions resulting from a signed integer comparison. */
16473 {
16480 }
16487 }
16489 /* Expand a floating-point vector conditional move; a vcond operation
16490 rather than a movcc operation. */
16492 bool
16494 {
16496 rtx cmp;
16511 }
16513 /* Expand a signed/unsigned integral vector conditional move. */
16515 bool
16517 {
16526 /* XOP supports all of the comparisons on all vector int types. */
16528 {
16529 /* Canonicalize the comparison to EQ, GT, GTU. */
16531 {
16548 /* FALLTHRU */
16558 }
16560 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16562 {
16564 {
16566 /* SSE4.1 supports EQ. */
16573 /* SSE4.2 supports GT/GTU. */
16580 }
16581 }
16583 /* Unsigned parallel compare is not supported by the hardware.
16584 Play some tricks to turn this into a signed comparison
16585 against 0. */
16587 {
16591 {
16594 {
16598 /* Subtract (-(INT MAX) - 1) from both operands to make
16599 them signed. */
16613 }
16618 /* Perform a parallel unsigned saturating subtraction. */
16631 }
16632 }
16633 }
16641 }
16643 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16644 true if we should do zero extension, else sign extension. HIGH_P is
16645 true if we want the N/2 high elements, else the low elements. */
16647 void
16649 {
16655 {
16659 else
16665 else
16671 else
16676 }
16682 else
16687 }
16689 /* This function performs the same task as ix86_expand_sse_unpack,
16690 but with SSE4.1 instructions. */
16692 void
16694 {
16700 {
16704 else
16710 else
16716 else
16721 }
16725 {
16726 /* Shift higher 8 bytes to lower 8 bytes. */
16731 }
16732 else
16736 }
16738 /* Expand conditional increment or decrement using adb/sbb instructions.
16739 The default case using setcc followed by the conditional move can be
16740 done by generic code. */
16741 int
16743 {
16745 rtx flags;
16747 rtx compare_op;
16766 {
16769 }
16772 {
16776 reverse_condition_maybe_unordered
16778 else
16780 }
16784 /* Construct either adc or sbb insn. */
16786 {
16788 {
16803 }
16804 }
16805 else
16806 {
16808 {
16823 }
16824 }
16828 }
16831 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16832 works for floating pointer parameters and nonoffsetable memories.
16833 For pushes, it returns just stack offsets; the values will be saved
16834 in the right order. Maximally three parts are generated. */
16836 static int
16838 {
16843 else
16849 /* Optimize constant pool reference to immediates. This is used by fp
16850 moves, that force all constants to memory to allow combining. */
16852 {
16856 }
16859 {
16860 /* The only non-offsetable memories we handle are pushes. */
16869 }
16872 {
16874 /* Caution: if we looked through a constant pool memory above,
16875 the operand may actually have a different mode now. That's
16876 ok, since we want to pun this all the way back to an integer. */
16880 }
16883 {
16886 else
16887 {
16891 {
16895 }
16897 {
16902 }
16904 {
16905 REAL_VALUE_TYPE r;
16910 {
16925 }
16928 }
16929 else
16931 }
16932 }
16933 else
16934 {
16938 {
16941 {
16945 }
16947 {
16951 }
16953 {
16954 REAL_VALUE_TYPE r;
16960 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16963 = gen_int_mode
16966 DImode);
16967 else
16974 = gen_int_mode
16977 DImode);
16978 else
16980 }
16981 else
16983 }
16984 }
16987 }
16989 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16990 Return false when normal moves are needed; true when all required
16991 insns have been emitted. Operands 2-4 contain the input values
16992 int the correct order; operands 5-7 contain the output values. */
16994 void
16996 {
17004 /* The DFmode expanders may ask us to move double.
17005 For 64bit target this is single move. By hiding the fact
17006 here we simplify i386.md splitters. */
17008 {
17009 /* Optimize constant pool reference to immediates. This is used by
17010 fp moves, that force all constants to memory to allow combining. */
17017 {
17020 }
17021 else
17026 }
17028 /* The only non-offsettable memory we handle is push. */
17031 else
17038 /* When emitting push, take care for source operands on the stack. */
17041 {
17044 /* Compensate for the stack decrement by 4. */
17049 /* src_base refers to the stack pointer and is
17050 automatically decreased by emitted push. */
17054 }
17056 /* We need to do copy in the right order in case an address register
17057 of the source overlaps the destination. */
17059 {
17060 rtx tmp;
17063 {
17067 collisions++;
17068 }
17070 /* Collision in the middle part can be handled by reordering. */
17072 {
17075 }
17079 {
17081 {
17084 }
17085 else
17086 {
17089 }
17090 }
17092 /* If there are more collisions, we can't handle it by reordering.
17093 Do an lea to the last part and use only one colliding move. */
17095 {
17096 rtx base;
17102 /* Handle the case when the last part isn't valid for lea.
17103 Happens in 64-bit mode storing the 12-byte XFmode. */
17110 {
17113 }
17114 }
17115 }
17118 {
17120 {
17122 {
17127 }
17129 {
17132 }
17133 }
17134 else
17135 {
17136 /* In 64bit mode we don't have 32bit push available. In case this is
17137 register, it is OK - we will just use larger counterpart. We also
17138 retype memory - these comes from attempt to avoid REX prefix on
17139 moving of second half of TFmode value. */
17141 {
17143 {
17154 }
17158 }
17159 }
17163 }
17165 /* Choose correct order to not overwrite the source before it is copied. */
17175 {
17177 {
17180 }
17181 }
17182 else
17183 {
17185 {
17188 }
17189 }
17191 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
17193 {
17202 }
17208 }
17210 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
17211 left shift by a constant, either using a single shift or
17212 a sequence of add instructions. */
17214 static void
17216 {
17218 {
17220 ? gen_addsi3
17222 }
17225 {
17228 {
17230 ? gen_addsi3
17232 }
17233 }
17234 else
17236 ? gen_ashlsi3
17238 }
17240 void
17242 {
17248 {
17253 {
17259 }
17260 else
17261 {
17265 ? gen_x86_shld
17268 }
17270 }
17275 {
17276 /* Assuming we've chosen a QImode capable registers, then 1 << N
17277 can be done with two 32/64-bit shifts, no branches, no cmoves. */
17279 {
17295 }
17297 /* Otherwise, we can get the same results by manually performing
17298 a bit extract operation on bit 5/6, and then performing the two
17299 shifts. The two methods of getting 0/1 into low/high are exactly
17300 the same size. Avoiding the shift in the bit extract case helps
17301 pentium4 a bit; no one else seems to care much either way. */
17302 else
17303 {
17304 rtx x;
17308 else
17313 ? gen_lshrsi3
17317 ? gen_andsi3
17321 ? gen_xorsi3
17323 }
17326 ? gen_ashlsi3
17329 ? gen_ashlsi3
17332 }
17335 {
17336 /* For -1 << N, we can avoid the shld instruction, because we
17337 know that we're shifting 0...31/63 ones into a -1. */
17341 else
17343 }
17344 else
17345 {
17351 ? gen_x86_shld
17353 }
17356 ? gen_ashlsi3
17360 {
17363 ? gen_x86_shiftsi_adj_1
17365 scratch));
17366 }
17367 else
17369 ? gen_x86_shiftsi_adj_2
17371 }
17373 void
17375 {
17381 {
17386 {
17389 ? gen_ashrsi3
17394 }
17396 {
17400 ? gen_ashrsi3
17405 ? gen_ashrsi3
17408 }
17409 else
17410 {
17414 ? gen_x86_shrd
17417 ? gen_ashrsi3
17419 }
17420 }
17421 else
17422 {
17429 ? gen_x86_shrd
17432 ? gen_ashrsi3
17436 {
17439 ? gen_ashrsi3
17443 ? gen_x86_shiftsi_adj_1
17445 scratch));
17446 }
17447 else
17449 ? gen_x86_shiftsi_adj_3
17451 }
17452 }
17454 void
17456 {
17462 {
17467 {
17473 ? gen_lshrsi3
17476 }
17477 else
17478 {
17482 ? gen_x86_shrd
17485 ? gen_lshrsi3
17487 }
17488 }
17489 else
17490 {
17497 ? gen_x86_shrd
17500 ? gen_lshrsi3
17503 /* Heh. By reversing the arguments, we can reuse this pattern. */
17505 {
17508 ? gen_x86_shiftsi_adj_1
17510 scratch));
17511 }
17512 else
17514 ? gen_x86_shiftsi_adj_2
17516 }
17517 }
17519 /* Predict just emitted jump instruction to be taken with probability PROB. */
17520 static void
17522 {
17526 }
17528 /* Helper function for the string operations below. Dest VARIABLE whether
17529 it is aligned to VALUE bytes. If true, jump to the label. */
17530 static rtx
17532 {
17537 else
17543 else
17546 }
17548 /* Adjust COUNTER by the VALUE. */
17549 static void
17551 {
17554 else
17556 }
17558 /* Zero extend possibly SImode EXP to Pmode register. */
17559 rtx
17561 {
17562 rtx r;
17570 }
17572 /* Divide COUNTREG by SCALE. */
17573 static rtx
17575 {
17576 rtx sc;
17588 }
17590 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17591 DImode for constant loop counts. */
17593 static enum machine_mode
17595 {
17603 }
17605 /* When SRCPTR is non-NULL, output simple loop to move memory
17606 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17607 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17608 equivalent loop to set memory by VALUE (supposed to be in MODE).
17610 The size is rounded down to whole number of chunk size moved at once.
17611 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17614 static void
17619 {
17624 rtx size;
17625 rtx x_addr;
17626 rtx y_addr;
17635 /* Those two should combine. */
17637 {
17641 }
17651 {
17655 /* When unrolling for chips that reorder memory reads and writes,
17656 we can save registers by using single temporary.
17657 Also using 4 temporaries is overkill in 32bit mode. */
17659 {
17661 {
17663 {
17664 destmem =
17666 srcmem =
17668 }
17670 }
17671 }
17672 else
17673 {
17677 {
17680 {
17681 srcmem =
17683 }
17685 }
17687 {
17689 {
17690 destmem =
17692 }
17694 }
17695 }
17696 }
17697 else
17699 {
17701 destmem =
17704 }
17714 {
17720 else
17722 }
17723 else
17731 {
17736 }
17738 }
17740 /* Output "rep; mov" instruction.
17741 Arguments have same meaning as for previous function */
17742 static void
17745 rtx count,
17747 {
17748 rtx destexp;
17749 rtx srcexp;
17750 rtx countreg;
17752 /* If the size is known, it is shorter to use rep movs. */
17763 {
17770 }
17771 else
17772 {
17775 }
17777 {
17784 }
17785 else
17786 {
17791 }
17794 }
17796 /* Output "rep; stos" instruction.
17797 Arguments have same meaning as for previous function */
17798 static void
17801 rtx orig_value)
17802 {
17803 rtx destexp;
17804 rtx countreg;
17811 {
17815 }
17816 else
17819 {
17824 }
17828 }
17830 static void
17833 {
17837 }
17839 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17840 static void
17843 {
17846 {
17851 {
17853 {
17856 }
17857 else
17860 }
17862 {
17865 else
17866 {
17869 }
17871 }
17873 {
17876 }
17878 {
17881 }
17883 {
17886 }
17888 }
17890 {
17896 }
17898 /* When there are stringops, we can cheaply increase dest and src pointers.
17899 Otherwise we save code size by maintaining offset (zero is readily
17900 available from preceding rep operation) and using x86 addressing modes.
17901 */
17903 {
17905 {
17912 }
17914 {
17921 }
17923 {
17930 }
17931 }
17932 else
17933 {
17935 rtx tmp;
17938 {
17949 }
17951 {
17964 }
17966 {
17975 }
17976 }
17977 }
17979 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17980 static void
17983 {
17984 count =
17990 }
17992 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17993 static void
17995 {
17996 rtx dest;
17999 {
18004 {
18006 {
18011 }
18012 else
18015 }
18017 {
18019 {
18022 }
18023 else
18024 {
18029 }
18031 }
18033 {
18037 }
18039 {
18043 }
18045 {
18049 }
18051 }
18053 {
18056 }
18058 {
18061 {
18065 }
18066 else
18067 {
18073 }
18076 }
18078 {
18081 {
18084 }
18085 else
18086 {
18090 }
18093 }
18095 {
18101 }
18103 {
18109 }
18111 {
18117 }
18118 }
18120 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
18121 DESIRED_ALIGNMENT. */
18122 static void
18126 {
18128 {
18136 }
18138 {
18146 }
18148 {
18156 }
18158 }
18160 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
18161 ALIGN_BYTES is how many bytes need to be copied. */
18162 static rtx
18165 {
18175 {
18180 }
18182 {
18193 }
18195 {
18201 {
18209 }
18212 }
18218 {
18230 }
18237 }
18239 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
18240 DESIRED_ALIGNMENT. */
18241 static void
18244 {
18246 {
18253 }
18255 {
18262 }
18264 {
18271 }
18273 }
18275 /* Set enough from DST to align DST known to by aligned by ALIGN to
18276 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
18277 static rtx
18280 {
18284 {
18289 }
18291 {
18298 }
18300 {
18307 }
18314 }
18316 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
18317 static enum stringop_alg
18320 {
18323 /* Algorithms using the rep prefix want at least edi and ecx;
18324 additionally, memset wants eax and memcpy wants esi. Don't
18325 consider such algorithms if the user has appropriated those
18326 registers for their own purposes. */
18328 || (memset
18331 #define ALG_USABLE_P(alg) (rep_prefix_usable \
18332 || (alg != rep_prefix_1_byte \
18333 && alg != rep_prefix_4_byte \
18334 && alg != rep_prefix_8_byte))
18337 /* Even if the string operation call is cold, we still might spend a lot
18338 of time processing large blocks. */
18343 else
18351 else
18355 /* rep; movq or rep; movl is the smallest variant. */
18357 {
18360 else
18362 }
18363 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
18364 */
18368 {
18372 {
18373 /* We get here if the algorithms that were not libcall-based
18374 were rep-prefix based and we are unable to use rep prefixes
18375 based on global register usage. Break out of the loop and
18376 use the heuristic below. */
18380 {
18385 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18386 last non-libcall inline algorithm. */
18388 {
18389 /* When the current size is best to be copied by a libcall,
18390 but we are still forced to inline, run the heuristic below
18391 that will pick code for medium sized blocks. */
18395 }
18398 }
18399 }
18401 }
18402 /* When asked to inline the call anyway, try to pick meaningful choice.
18403 We look for maximal size of block that is faster to copy by hand and
18404 take blocks of at most of that size guessing that average size will
18405 be roughly half of the block.
18407 If this turns out to be bad, we might simply specify the preferred
18408 choice in ix86_costs. */
18411 {
18418 {
18425 }
18426 /* If there aren't any usable algorithms, then recursing on
18427 smaller sizes isn't going to find anything. Just return the
18428 simple byte-at-a-time copy loop. */
18430 {
18431 /* Pick something reasonable. */
18435 }
18444 }
18446 #undef ALG_USABLE_P
18447 }
18449 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18450 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18451 static int
18455 {
18458 {
18469 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18470 copying whole cacheline at once. */
18473 else
18477 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18478 copying whole cacheline at once. */
18481 else
18489 }
18498 }
18500 /* Return the smallest power of 2 greater than VAL. */
18501 static int
18503 {
18508 }
18510 /* Expand string move (memcpy) operation. Use i386 string operations when
18511 profitable. expand_setmem contains similar code. The code depends upon
18512 architecture, block size and alignment, but always has the same
18513 overall structure:
18515 1) Prologue guard: Conditional that jumps up to epilogues for small
18516 blocks that can be handled by epilogue alone. This is faster but
18517 also needed for correctness, since prologue assume the block is larger
18518 than the desired alignment.
18520 Optional dynamic check for size and libcall for large
18521 blocks is emitted here too, with -minline-stringops-dynamically.
18523 2) Prologue: copy first few bytes in order to get destination aligned
18524 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18525 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18526 We emit either a jump tree on power of two sized blocks, or a byte loop.
18528 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18529 with specified algorithm.
18531 4) Epilogue: code copying tail of the block that is too small to be
18532 handled by main body (or up to size guarded by prologue guard). */
18534 int
18537 {
18538 rtx destreg;
18539 rtx srcreg;
18541 rtx tmp;
18554 /* i386 can do misaligned access on reasonably increased cost. */
18558 /* ALIGN is the minimum of destination and source alignment, but we care here
18559 just about destination alignment. */
18568 /* Make sure we don't need to care about overflow later on. */
18572 /* Step 0: Decide on preferred algorithm, desired alignment and
18573 size of chunks to be copied by main loop. */
18589 {
18614 }
18618 /* Step 1: Prologue guard. */
18620 /* Alignment code needs count to be in register. */
18622 {
18625 {
18626 align_bytes
18630 else
18632 }
18635 }
18638 /* Ensure that alignment prologue won't copy past end of block. */
18640 {
18642 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18643 Make sure it is power of 2. */
18647 {
18649 {
18650 /* If main algorithm works on QImode, no epilogue is needed.
18651 For small sizes just don't align anything. */
18654 else
18656 }
18657 }
18658 else
18659 {
18666 else
18668 }
18669 }
18671 /* Emit code to decide on runtime whether library call or inline should be
18672 used. */
18674 {
18676 {
18678 {
18682 }
18683 }
18684 else
18685 {
18694 }
18695 }
18697 /* Step 2: Alignment prologue. */
18700 {
18702 {
18703 /* Except for the first move in epilogue, we no longer know
18704 constant offset in aliasing info. It don't seems to worth
18705 the pain to maintain it for the first move, so throw away
18706 the info early. */
18710 desired_align);
18711 }
18712 else
18713 {
18714 /* If we know how many bytes need to be stored before dst is
18715 sufficiently aligned, maintain aliasing info accurately. */
18720 }
18726 {
18727 /* It is possible that we copied enough so the main loop will not
18728 execute. */
18738 else
18740 }
18741 }
18743 {
18748 }
18752 /* Step 3: Main loop. */
18755 {
18768 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18769 registers for 4 temporaries anyway. */
18772 expected_size);
18776 DImode);
18780 SImode);
18784 QImode);
18786 }
18787 /* Adjust properly the offset of src and dest memory for aliasing. */
18789 {
18794 }
18795 else
18796 {
18799 }
18801 /* Step 4: Epilogue to copy the remaining bytes. */
18802 epilogue:
18804 {
18805 /* When the main loop is done, COUNT_EXP might hold original count,
18806 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18807 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18808 bytes. Compensate if needed. */
18811 {
18812 tmp =
18815 OPTAB_DIRECT);
18818 }
18821 }
18825 epilogue_size_needed);
18829 }
18831 /* Helper function for memcpy. For QImode value 0xXY produce
18832 0xXYXYXYXY of wide specified by MODE. This is essentially
18833 a * 0x10101010, but we can do slightly better than
18834 synth_mult by unwinding the sequence by hand on CPUs with
18835 slow multiply. */
18836 static rtx
18838 {
18840 rtx tmp;
18847 {
18855 }
18864 nops--;
18869 {
18873 OPTAB_DIRECT);
18874 }
18875 else
18876 {
18882 else
18884 else
18885 {
18888 reg =
18890 }
18900 }
18901 }
18903 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18904 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18905 alignment from ALIGN to DESIRED_ALIGN. */
18906 static rtx
18908 {
18909 rtx promoted_val;
18918 else
18922 }
18924 /* Expand string clear operation (bzero). Use i386 string operations when
18925 profitable. See expand_movmem comment for explanation of individual
18926 steps performed. */
18927 int
18930 {
18931 rtx destreg;
18933 rtx tmp;
18948 /* i386 can do misaligned access on reasonably increased cost. */
18957 /* Make sure we don't need to care about overflow later on. */
18961 /* Step 0: Decide on preferred algorithm, desired alignment and
18962 size of chunks to be copied by main loop. */
18977 {
19002 }
19005 /* Step 1: Prologue guard. */
19007 /* Alignment code needs count to be in register. */
19009 {
19012 {
19013 align_bytes
19017 else
19019 }
19021 {
19026 }
19027 }
19028 /* Do the cheap promotion to allow better CSE across the
19029 main loop and epilogue (ie one load of the big constant in the
19030 front of all code. */
19034 /* Ensure that alignment prologue won't copy past end of block. */
19036 {
19038 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
19039 Make sure it is power of 2. */
19042 /* To improve performance of small blocks, we jump around the VAL
19043 promoting mode. This mean that if the promoted VAL is not constant,
19044 we might not use it in the epilogue and have to use byte
19045 loop variant. */
19049 {
19051 {
19052 /* If main algorithm works on QImode, no epilogue is needed.
19053 For small sizes just don't align anything. */
19056 else
19058 }
19059 }
19060 else
19061 {
19068 else
19070 }
19071 }
19073 {
19082 }
19084 /* Step 2: Alignment prologue. */
19086 /* Do the expensive promotion once we branched off the small blocks. */
19093 {
19095 {
19096 /* Except for the first move in epilogue, we no longer know
19097 constant offset in aliasing info. It don't seems to worth
19098 the pain to maintain it for the first move, so throw away
19099 the info early. */
19102 desired_align);
19103 }
19104 else
19105 {
19106 /* If we know how many bytes need to be stored before dst is
19107 sufficiently aligned, maintain aliasing info accurately. */
19112 }
19118 {
19119 /* It is possible that we copied enough so the main loop will not
19120 execute. */
19130 else
19132 }
19133 }
19135 {
19141 }
19145 /* Step 3: Main loop. */
19148 {
19176 }
19177 /* Adjust properly the offset of src and dest memory for aliasing. */
19181 else
19184 /* Step 4: Epilogue to copy the remaining bytes. */
19187 {
19188 /* When the main loop is done, COUNT_EXP might hold original count,
19189 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
19190 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
19191 bytes. Compensate if needed. */
19194 {
19195 tmp =
19198 OPTAB_DIRECT);
19201 }
19204 }
19205 epilogue:
19207 {
19210 epilogue_size_needed);
19211 else
19213 epilogue_size_needed);
19214 }
19218 }
19220 /* Expand the appropriate insns for doing strlen if not just doing
19221 repnz; scasb
19223 out = result, initialized with the start address
19224 align_rtx = alignment of the address.
19225 scratch = scratch register, initialized with the startaddress when
19226 not aligned, otherwise undefined
19228 This is just the body. It needs the initializations mentioned above and
19229 some address computing at the end. These things are done in i386.md. */
19231 static void
19233 {
19235 rtx tmp;
19240 rtx mem;
19243 rtx cmp;
19249 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
19251 /* Is there a known alignment and is it less than 4? */
19253 {
19256 /* Is there a known alignment and is it not 2? */
19258 {
19262 /* Leave just the 3 lower bits. */
19272 }
19273 else
19274 {
19275 /* Since the alignment is 2, we have to check 2 or 0 bytes;
19276 check if is aligned to 4 - byte. */
19283 }
19287 /* Now compare the bytes. */
19289 /* Compare the first n unaligned byte on a byte per byte basis. */
19293 /* Increment the address. */
19296 /* Not needed with an alignment of 2 */
19298 {
19302 end_0_label);
19307 }
19310 end_0_label);
19313 }
19315 /* Generate loop to check 4 bytes at a time. It is not a good idea to
19316 align this loop. It gives only huge programs, but does not help to
19317 speed up. */
19324 /* This formula yields a nonzero result iff one of the bytes is zero.
19325 This saves three branches inside loop and many cycles. */
19333 align_4_label);
19336 {
19342 /* If zero is not in the first two bytes, move two bytes forward. */
19348 reg,
19349 tmpreg)));
19350 /* Emit lea manually to avoid clobbering of flags. */
19358 reg2,
19359 out)));
19360 }
19361 else
19362 {
19364 /* Is zero in the first two bytes? */
19371 pc_rtx);
19375 /* Not in the first two. Move two bytes forward. */
19381 }
19383 /* Avoid branch in fixing the byte. */
19391 }
19393 /* Expand strlen. */
19395 int
19397 {
19400 /* The generic case of strlen expander is long. Avoid it's
19401 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19404 && !TARGET_INLINE_ALL_STRINGOPS
19414 {
19415 /* Well it seems that some optimizer does not combine a call like
19416 foo(strlen(bar), strlen(bar));
19417 when the move and the subtraction is done here. It does calculate
19418 the length just once when these instructions are done inside of
19419 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19420 often used and I use one fewer register for the lifetime of
19421 output_strlen_unroll() this is better. */
19427 /* strlensi_unroll_1 returns the address of the zero at the end of
19428 the string, like memchr(), so compute the length by subtracting
19429 the start address. */
19431 }
19432 else
19433 {
19434 rtx unspec;
19436 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19449 /* If .md starts supporting :P, this can be done in .md. */
19455 }
19457 }
19459 /* For given symbol (function) construct code to compute address of it's PLT
19460 entry in large x86-64 PIC model. */
19461 rtx
19463 {
19473 }
19475 void
19477 rtx callarg2,
19479 {
19487 {
19488 #if TARGET_MACHO
19491 #endif
19492 }
19493 else
19494 {
19495 /* Static functions and indirect calls don't need the pic register. */
19500 }
19503 {
19507 }
19517 {
19520 }
19526 {
19530 }
19534 {
19535 /* We need to represent that SI and DI registers are clobbered
19536 by SYSV calls. */
19542 };
19546 UNSPEC_MS_TO_SYSV_CALL);
19553 gen_rtx_REG
19561 }
19566 }
19568 \f
19569 /* Clear stack slot assignments remembered from previous functions.
19570 This is called from INIT_EXPANDERS once before RTL is emitted for each
19571 function. */
19575 {
19584 }
19586 /* Return a MEM corresponding to a stack slot with mode MODE.
19587 Allocate a new slot if necessary.
19589 The RTL for a function can have several slots available: N is
19590 which slot to use. */
19592 rtx
19594 {
19599 /* Virtual slot is valid only before vregs are instantiated. */
19614 }
19616 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19619 rtx
19621 {
19624 {
19626 (TARGET_ANY_GNU_TLS
19630 }
19633 }
19635 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19638 rtx
19640 {
19643 {
19648 }
19651 }
19652 \f
19653 /* Calculate the length of the memory address in the instruction
19654 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19656 int
19658 {
19683 /* Rule of thumb:
19684 - esp as the base always wants an index,
19685 - ebp as the base always wants a displacement,
19686 - r12 as the base always wants an index,
19687 - r13 as the base always wants a displacement. */
19689 /* Register Indirect. */
19691 {
19692 /* esp (for its index) and ebp (for its displacement) need
19693 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19694 code. */
19703 }
19705 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19706 is not disp32, but disp32(%rip), so for disp32
19707 SIB byte is needed, unless print_operand_address
19708 optimizes it into disp32(%rip) or (%rip) is implied
19709 by UNSPEC. */
19711 {
19714 {
19730 }
19731 }
19733 else
19734 {
19735 /* Find the length of the displacement constant. */
19737 {
19740 else
19742 }
19743 /* ebp always wants a displacement. Similarly r13. */
19748 /* An index requires the two-byte modrm form.... */
19750 /* ...like esp (or r12), which always wants an index. */
19756 }
19759 {
19766 }
19769 }
19771 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19772 is set, expect that insn have 8bit immediate alternative. */
19773 int
19775 {
19781 {
19786 {
19789 {
19801 }
19803 {
19806 }
19807 }
19809 {
19819 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19825 }
19826 }
19828 }
19829 /* Compute default value for "length_address" attribute. */
19830 int
19832 {
19836 {
19846 {
19851 }
19854 }
19859 {
19862 {
19867 constraints++;
19870 ;
19871 /* Skip ignored operands. */
19874 }
19876 }
19878 }
19880 /* Compute default value for "length_vex" attribute. It includes
19881 2 or 3 byte VEX prefix and 1 opcode byte. */
19883 int
19886 {
19889 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19890 byte VEX prefix. */
19894 /* We can always use 2 byte VEX prefix in 32bit. */
19902 {
19903 /* REX.W bit uses 3 byte VEX prefix. */
19907 }
19908 else
19909 {
19910 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19914 }
19917 }
19918 \f
19919 /* Return the maximum number of instructions a cpu can issue. */
19921 static int
19923 {
19925 {
19947 }
19948 }
19950 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19951 by DEP_INSN and nothing set by DEP_INSN. */
19953 static int
19955 {
19958 /* Simplify the test for uninteresting insns. */
19966 {
19969 }
19974 {
19977 }
19978 else
19984 /* This test is true if the dependent insn reads the flags but
19985 not any other potentially set register. */
19993 }
19995 /* Return true iff USE_INSN has a memory address with operands set by
19996 SET_INSN. */
19998 bool
20000 {
20005 {
20008 }
20010 }
20012 static int
20014 {
20020 /* Anti and output dependencies have zero cost on all CPUs. */
20026 /* If we can't recognize the insns, we can't really do anything. */
20034 {
20036 /* Address Generation Interlock adds a cycle of latency. */
20038 {
20049 }
20053 /* ??? Compares pair with jump/setcc. */
20057 /* Floating point stores require value to be ready one cycle earlier. */
20067 /* INT->FP conversion is expensive. */
20071 /* There is one cycle extra latency between an FP op and a store. */
20079 /* Show ability of reorder buffer to hide latency of load by executing
20080 in parallel with previous instruction in case
20081 previous instruction is not needed to compute the address. */
20084 {
20085 /* Claim moves to take one cycle, as core can issue one load
20086 at time and the next load can start cycle later. */
20091 cost--;
20092 }
20098 /* The esp dependency is resolved before the instruction is really
20099 finished. */
20104 /* INT->FP conversion is expensive. */
20108 /* Show ability of reorder buffer to hide latency of load by executing
20109 in parallel with previous instruction in case
20110 previous instruction is not needed to compute the address. */
20113 {
20114 /* Claim moves to take one cycle, as core can issue one load
20115 at time and the next load can start cycle later. */
20121 else
20123 }
20135 /* Show ability of reorder buffer to hide latency of load by executing
20136 in parallel with previous instruction in case
20137 previous instruction is not needed to compute the address. */
20140 {
20144 /* Because of the difference between the length of integer and
20145 floating unit pipeline preparation stages, the memory operands
20146 for floating point are cheaper.
20148 ??? For Athlon it the difference is most probably 2. */
20151 else
20156 else
20158 }
20162 }
20165 }
20167 /* How many alternative schedules to try. This should be as wide as the
20168 scheduling freedom in the DFA, but no wider. Making this value too
20169 large results extra work for the scheduler. */
20171 static int
20173 {
20175 {
20185 }
20186 }
20188 \f
20189 /* Compute the alignment given to a constant that is being placed in memory.
20190 EXP is the constant and ALIGN is the alignment that the object would
20191 ordinarily have.
20192 The value of this function is used instead of that alignment to align
20193 the object. */
20195 int
20197 {
20200 {
20205 }
20211 }
20213 /* Compute the alignment for a static variable.
20214 TYPE is the data type, and ALIGN is the alignment that
20215 the object would ordinarily have. The value of this function is used
20216 instead of that alignment to align the object. */
20218 int
20220 {
20231 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20232 to 16byte boundary. */
20234 {
20241 }
20244 {
20249 }
20251 {
20258 }
20263 {
20268 }
20271 {
20276 }
20279 }
20281 /* Compute the alignment for a local variable or a stack slot. EXP is
20282 the data type or decl itself, MODE is the widest mode available and
20283 ALIGN is the alignment that the object would ordinarily have. The
20284 value of this macro is used instead of that alignment to align the
20285 object. */
20287 unsigned int
20290 {
20294 {
20297 }
20298 else
20299 {
20302 }
20304 /* Don't do dynamic stack realignment for long long objects with
20305 -mpreferred-stack-boundary=2. */
20314 /* If TYPE is NULL, we are allocating a stack slot for caller-save
20315 register in MODE. We will return the largest alignment of XF
20316 and DF. */
20318 {
20322 }
20324 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20325 to 16byte boundary. Exact wording is:
20327 An array uses the same alignment as its elements, except that a local or
20328 global array variable of length at least 16 bytes or
20329 a C99 variable-length array variable always has alignment of at least 16 bytes.
20331 This was added to allow use of aligned SSE instructions at arrays. This
20332 rule is meant for static storage (where compiler can not do the analysis
20333 by itself). We follow it for automatic variables only when convenient.
20334 We fully control everything in the function compiled and functions from
20335 other unit can not rely on the alignment.
20337 Exclude va_list type. It is the common case of local array where
20338 we can not benefit from the alignment. */
20341 {
20350 }
20352 {
20357 }
20359 {
20365 }
20370 {
20375 }
20378 {
20384 }
20386 }
20388 /* Compute the minimum required alignment for dynamic stack realignment
20389 purposes for a local variable, parameter or a stack slot. EXP is
20390 the data type or decl itself, MODE is its mode and ALIGN is the
20391 alignment that the object would ordinarily have. */
20393 unsigned int
20396 {
20403 {
20406 }
20407 else
20408 {
20411 }
20413 /* Don't do dynamic stack realignment for long long objects with
20414 -mpreferred-stack-boundary=2. */
20421 }
20422 \f
20423 /* Find a location for the static chain incoming to a nested function.
20424 This is a register, unless all free registers are used by arguments. */
20426 static rtx
20428 {
20435 {
20436 /* We always use R10 in 64-bit mode. */
20438 }
20439 else
20440 {
20441 tree fntype;
20442 /* By default in 32-bit mode we use ECX to pass the static chain. */
20447 {
20448 /* Fastcall functions use ecx/edx for arguments, which leaves
20449 us with EAX for the static chain. */
20451 }
20453 {
20454 /* Thiscall functions use ecx for arguments, which leaves
20455 us with EAX for the static chain. */
20457 }
20459 {
20460 /* For regparm 3, we have no free call-clobbered registers in
20461 which to store the static chain. In order to implement this,
20462 we have the trampoline push the static chain to the stack.
20463 However, we can't push a value below the return address when
20464 we call the nested function directly, so we have to use an
20465 alternate entry point. For this we use ESI, and have the
20466 alternate entry point push ESI, so that things appear the
20467 same once we're executing the nested function. */
20469 {
20474 }
20476 }
20477 }
20480 }
20482 /* Emit RTL insns to initialize the variable parts of a trampoline.
20483 FNDECL is the decl of the target address; M_TRAMP is a MEM for
20484 the trampoline, and CHAIN_VALUE is an RTX for the static chain
20485 to be passed to the target function. */
20487 static void
20489 {
20495 {
20499 /* Depending on the static chain location, either load a register
20500 with a constant, or push the constant to the stack. All of the
20501 instructions are the same size. */
20504 {
20509 else
20511 }
20512 else
20521 /* Compute offset from the end of the jmp to the target function.
20522 In the case in which the trampoline stores the static chain on
20523 the stack, we need to skip the first insn which pushes the
20524 (call-saved) register static chain; this push is 1 byte. */
20535 }
20536 else
20537 {
20540 /* Load the function address to r11. Try to load address using
20541 the shorter movl instead of movabs. We may want to support
20542 movq for kernel mode, but kernel does not use trampolines at
20543 the moment. */
20545 {
20554 }
20555 else
20556 {
20563 }
20565 /* Load static chain using movabs to r10. */
20573 /* Jump to r11; the last (unused) byte is a nop, only there to
20574 pad the write out to a single 32-bit store. */
20580 }
20582 #ifdef ENABLE_EXECUTE_STACK
20583 #ifdef CHECK_EXECUTE_STACK_ENABLED
20585 #endif
20588 #endif
20589 }
20590 \f
20591 /* The following file contains several enumerations and data structures
20592 built from the definitions in i386-builtin-types.def. */
20596 /* Table for the ix86 builtin non-function types. */
20599 /* Retrieve an element from the above table, building some of
20600 the types lazily. */
20602 static tree
20604 {
20616 {
20624 }
20625 else
20626 {
20632 else
20640 }
20644 }
20646 /* Table for the ix86 builtin function types. */
20649 /* Retrieve an element from the above table, building some of
20650 the types lazily. */
20652 static tree
20654 {
20655 tree type;
20664 {
20672 {
20675 }
20678 }
20679 else
20680 {
20686 }
20690 }
20693 /* Codes for all the SSE/MMX builtins. */
20694 enum ix86_builtins
20695 {
20696 IX86_BUILTIN_ADDPS,
20697 IX86_BUILTIN_ADDSS,
20698 IX86_BUILTIN_DIVPS,
20699 IX86_BUILTIN_DIVSS,
20700 IX86_BUILTIN_MULPS,
20701 IX86_BUILTIN_MULSS,
20702 IX86_BUILTIN_SUBPS,
20703 IX86_BUILTIN_SUBSS,
20705 IX86_BUILTIN_CMPEQPS,
20706 IX86_BUILTIN_CMPLTPS,
20707 IX86_BUILTIN_CMPLEPS,
20708 IX86_BUILTIN_CMPGTPS,
20709 IX86_BUILTIN_CMPGEPS,
20710 IX86_BUILTIN_CMPNEQPS,
20711 IX86_BUILTIN_CMPNLTPS,
20712 IX86_BUILTIN_CMPNLEPS,
20713 IX86_BUILTIN_CMPNGTPS,
20714 IX86_BUILTIN_CMPNGEPS,
20715 IX86_BUILTIN_CMPORDPS,
20716 IX86_BUILTIN_CMPUNORDPS,
20717 IX86_BUILTIN_CMPEQSS,
20718 IX86_BUILTIN_CMPLTSS,
20719 IX86_BUILTIN_CMPLESS,
20720 IX86_BUILTIN_CMPNEQSS,
20721 IX86_BUILTIN_CMPNLTSS,
20722 IX86_BUILTIN_CMPNLESS,
20723 IX86_BUILTIN_CMPNGTSS,
20724 IX86_BUILTIN_CMPNGESS,
20725 IX86_BUILTIN_CMPORDSS,
20726 IX86_BUILTIN_CMPUNORDSS,
20728 IX86_BUILTIN_COMIEQSS,
20729 IX86_BUILTIN_COMILTSS,
20730 IX86_BUILTIN_COMILESS,
20731 IX86_BUILTIN_COMIGTSS,
20732 IX86_BUILTIN_COMIGESS,
20733 IX86_BUILTIN_COMINEQSS,
20734 IX86_BUILTIN_UCOMIEQSS,
20735 IX86_BUILTIN_UCOMILTSS,
20736 IX86_BUILTIN_UCOMILESS,
20737 IX86_BUILTIN_UCOMIGTSS,
20738 IX86_BUILTIN_UCOMIGESS,
20739 IX86_BUILTIN_UCOMINEQSS,
20741 IX86_BUILTIN_CVTPI2PS,
20742 IX86_BUILTIN_CVTPS2PI,
20743 IX86_BUILTIN_CVTSI2SS,
20744 IX86_BUILTIN_CVTSI642SS,
20745 IX86_BUILTIN_CVTSS2SI,
20746 IX86_BUILTIN_CVTSS2SI64,
20747 IX86_BUILTIN_CVTTPS2PI,
20748 IX86_BUILTIN_CVTTSS2SI,
20749 IX86_BUILTIN_CVTTSS2SI64,
20751 IX86_BUILTIN_MAXPS,
20752 IX86_BUILTIN_MAXSS,
20753 IX86_BUILTIN_MINPS,
20754 IX86_BUILTIN_MINSS,
20756 IX86_BUILTIN_LOADUPS,
20757 IX86_BUILTIN_STOREUPS,
20758 IX86_BUILTIN_MOVSS,
20760 IX86_BUILTIN_MOVHLPS,
20761 IX86_BUILTIN_MOVLHPS,
20762 IX86_BUILTIN_LOADHPS,
20763 IX86_BUILTIN_LOADLPS,
20764 IX86_BUILTIN_STOREHPS,
20765 IX86_BUILTIN_STORELPS,
20767 IX86_BUILTIN_MASKMOVQ,
20768 IX86_BUILTIN_MOVMSKPS,
20769 IX86_BUILTIN_PMOVMSKB,
20771 IX86_BUILTIN_MOVNTPS,
20772 IX86_BUILTIN_MOVNTQ,
20774 IX86_BUILTIN_LOADDQU,
20775 IX86_BUILTIN_STOREDQU,
20777 IX86_BUILTIN_PACKSSWB,
20778 IX86_BUILTIN_PACKSSDW,
20779 IX86_BUILTIN_PACKUSWB,
20781 IX86_BUILTIN_PADDB,
20782 IX86_BUILTIN_PADDW,
20783 IX86_BUILTIN_PADDD,
20784 IX86_BUILTIN_PADDQ,
20785 IX86_BUILTIN_PADDSB,
20786 IX86_BUILTIN_PADDSW,
20787 IX86_BUILTIN_PADDUSB,
20788 IX86_BUILTIN_PADDUSW,
20789 IX86_BUILTIN_PSUBB,
20790 IX86_BUILTIN_PSUBW,
20791 IX86_BUILTIN_PSUBD,
20792 IX86_BUILTIN_PSUBQ,
20793 IX86_BUILTIN_PSUBSB,
20794 IX86_BUILTIN_PSUBSW,
20795 IX86_BUILTIN_PSUBUSB,
20796 IX86_BUILTIN_PSUBUSW,
20798 IX86_BUILTIN_PAND,
20799 IX86_BUILTIN_PANDN,
20800 IX86_BUILTIN_POR,
20801 IX86_BUILTIN_PXOR,
20803 IX86_BUILTIN_PAVGB,
20804 IX86_BUILTIN_PAVGW,
20806 IX86_BUILTIN_PCMPEQB,
20807 IX86_BUILTIN_PCMPEQW,
20808 IX86_BUILTIN_PCMPEQD,
20809 IX86_BUILTIN_PCMPGTB,
20810 IX86_BUILTIN_PCMPGTW,
20811 IX86_BUILTIN_PCMPGTD,
20813 IX86_BUILTIN_PMADDWD,
20815 IX86_BUILTIN_PMAXSW,
20816 IX86_BUILTIN_PMAXUB,
20817 IX86_BUILTIN_PMINSW,
20818 IX86_BUILTIN_PMINUB,
20820 IX86_BUILTIN_PMULHUW,
20821 IX86_BUILTIN_PMULHW,
20822 IX86_BUILTIN_PMULLW,
20824 IX86_BUILTIN_PSADBW,
20825 IX86_BUILTIN_PSHUFW,
20827 IX86_BUILTIN_PSLLW,
20828 IX86_BUILTIN_PSLLD,
20829 IX86_BUILTIN_PSLLQ,
20830 IX86_BUILTIN_PSRAW,
20831 IX86_BUILTIN_PSRAD,
20832 IX86_BUILTIN_PSRLW,
20833 IX86_BUILTIN_PSRLD,
20834 IX86_BUILTIN_PSRLQ,
20835 IX86_BUILTIN_PSLLWI,
20836 IX86_BUILTIN_PSLLDI,
20837 IX86_BUILTIN_PSLLQI,
20838 IX86_BUILTIN_PSRAWI,
20839 IX86_BUILTIN_PSRADI,
20840 IX86_BUILTIN_PSRLWI,
20841 IX86_BUILTIN_PSRLDI,
20842 IX86_BUILTIN_PSRLQI,
20844 IX86_BUILTIN_PUNPCKHBW,
20845 IX86_BUILTIN_PUNPCKHWD,
20846 IX86_BUILTIN_PUNPCKHDQ,
20847 IX86_BUILTIN_PUNPCKLBW,
20848 IX86_BUILTIN_PUNPCKLWD,
20849 IX86_BUILTIN_PUNPCKLDQ,
20851 IX86_BUILTIN_SHUFPS,
20853 IX86_BUILTIN_RCPPS,
20854 IX86_BUILTIN_RCPSS,
20855 IX86_BUILTIN_RSQRTPS,
20856 IX86_BUILTIN_RSQRTPS_NR,
20857 IX86_BUILTIN_RSQRTSS,
20858 IX86_BUILTIN_RSQRTF,
20859 IX86_BUILTIN_SQRTPS,
20860 IX86_BUILTIN_SQRTPS_NR,
20861 IX86_BUILTIN_SQRTSS,
20863 IX86_BUILTIN_UNPCKHPS,
20864 IX86_BUILTIN_UNPCKLPS,
20866 IX86_BUILTIN_ANDPS,
20867 IX86_BUILTIN_ANDNPS,
20868 IX86_BUILTIN_ORPS,
20869 IX86_BUILTIN_XORPS,
20871 IX86_BUILTIN_EMMS,
20872 IX86_BUILTIN_LDMXCSR,
20873 IX86_BUILTIN_STMXCSR,
20874 IX86_BUILTIN_SFENCE,
20876 /* 3DNow! Original */
20877 IX86_BUILTIN_FEMMS,
20878 IX86_BUILTIN_PAVGUSB,
20879 IX86_BUILTIN_PF2ID,
20880 IX86_BUILTIN_PFACC,
20881 IX86_BUILTIN_PFADD,
20882 IX86_BUILTIN_PFCMPEQ,
20883 IX86_BUILTIN_PFCMPGE,
20884 IX86_BUILTIN_PFCMPGT,
20885 IX86_BUILTIN_PFMAX,
20886 IX86_BUILTIN_PFMIN,
20887 IX86_BUILTIN_PFMUL,
20888 IX86_BUILTIN_PFRCP,
20889 IX86_BUILTIN_PFRCPIT1,
20890 IX86_BUILTIN_PFRCPIT2,
20891 IX86_BUILTIN_PFRSQIT1,
20892 IX86_BUILTIN_PFRSQRT,
20893 IX86_BUILTIN_PFSUB,
20894 IX86_BUILTIN_PFSUBR,
20895 IX86_BUILTIN_PI2FD,
20896 IX86_BUILTIN_PMULHRW,
20898 /* 3DNow! Athlon Extensions */
20899 IX86_BUILTIN_PF2IW,
20900 IX86_BUILTIN_PFNACC,
20901 IX86_BUILTIN_PFPNACC,
20902 IX86_BUILTIN_PI2FW,
20903 IX86_BUILTIN_PSWAPDSI,
20904 IX86_BUILTIN_PSWAPDSF,
20906 /* SSE2 */
20907 IX86_BUILTIN_ADDPD,
20908 IX86_BUILTIN_ADDSD,
20909 IX86_BUILTIN_DIVPD,
20910 IX86_BUILTIN_DIVSD,
20911 IX86_BUILTIN_MULPD,
20912 IX86_BUILTIN_MULSD,
20913 IX86_BUILTIN_SUBPD,
20914 IX86_BUILTIN_SUBSD,
20916 IX86_BUILTIN_CMPEQPD,
20917 IX86_BUILTIN_CMPLTPD,
20918 IX86_BUILTIN_CMPLEPD,
20919 IX86_BUILTIN_CMPGTPD,
20920 IX86_BUILTIN_CMPGEPD,
20921 IX86_BUILTIN_CMPNEQPD,
20922 IX86_BUILTIN_CMPNLTPD,
20923 IX86_BUILTIN_CMPNLEPD,
20924 IX86_BUILTIN_CMPNGTPD,
20925 IX86_BUILTIN_CMPNGEPD,
20926 IX86_BUILTIN_CMPORDPD,
20927 IX86_BUILTIN_CMPUNORDPD,
20928 IX86_BUILTIN_CMPEQSD,
20929 IX86_BUILTIN_CMPLTSD,
20930 IX86_BUILTIN_CMPLESD,
20931 IX86_BUILTIN_CMPNEQSD,
20932 IX86_BUILTIN_CMPNLTSD,
20933 IX86_BUILTIN_CMPNLESD,
20934 IX86_BUILTIN_CMPORDSD,
20935 IX86_BUILTIN_CMPUNORDSD,
20937 IX86_BUILTIN_COMIEQSD,
20938 IX86_BUILTIN_COMILTSD,
20939 IX86_BUILTIN_COMILESD,
20940 IX86_BUILTIN_COMIGTSD,
20941 IX86_BUILTIN_COMIGESD,
20942 IX86_BUILTIN_COMINEQSD,
20943 IX86_BUILTIN_UCOMIEQSD,
20944 IX86_BUILTIN_UCOMILTSD,
20945 IX86_BUILTIN_UCOMILESD,
20946 IX86_BUILTIN_UCOMIGTSD,
20947 IX86_BUILTIN_UCOMIGESD,
20948 IX86_BUILTIN_UCOMINEQSD,
20950 IX86_BUILTIN_MAXPD,
20951 IX86_BUILTIN_MAXSD,
20952 IX86_BUILTIN_MINPD,
20953 IX86_BUILTIN_MINSD,
20955 IX86_BUILTIN_ANDPD,
20956 IX86_BUILTIN_ANDNPD,
20957 IX86_BUILTIN_ORPD,
20958 IX86_BUILTIN_XORPD,
20960 IX86_BUILTIN_SQRTPD,
20961 IX86_BUILTIN_SQRTSD,
20963 IX86_BUILTIN_UNPCKHPD,
20964 IX86_BUILTIN_UNPCKLPD,
20966 IX86_BUILTIN_SHUFPD,
20968 IX86_BUILTIN_LOADUPD,
20969 IX86_BUILTIN_STOREUPD,
20970 IX86_BUILTIN_MOVSD,
20972 IX86_BUILTIN_LOADHPD,
20973 IX86_BUILTIN_LOADLPD,
20975 IX86_BUILTIN_CVTDQ2PD,
20976 IX86_BUILTIN_CVTDQ2PS,
20978 IX86_BUILTIN_CVTPD2DQ,
20979 IX86_BUILTIN_CVTPD2PI,
20980 IX86_BUILTIN_CVTPD2PS,
20981 IX86_BUILTIN_CVTTPD2DQ,
20982 IX86_BUILTIN_CVTTPD2PI,
20984 IX86_BUILTIN_CVTPI2PD,
20985 IX86_BUILTIN_CVTSI2SD,
20986 IX86_BUILTIN_CVTSI642SD,
20988 IX86_BUILTIN_CVTSD2SI,
20989 IX86_BUILTIN_CVTSD2SI64,
20990 IX86_BUILTIN_CVTSD2SS,
20991 IX86_BUILTIN_CVTSS2SD,
20992 IX86_BUILTIN_CVTTSD2SI,
20993 IX86_BUILTIN_CVTTSD2SI64,
20995 IX86_BUILTIN_CVTPS2DQ,
20996 IX86_BUILTIN_CVTPS2PD,
20997 IX86_BUILTIN_CVTTPS2DQ,
20999 IX86_BUILTIN_MOVNTI,
21000 IX86_BUILTIN_MOVNTPD,
21001 IX86_BUILTIN_MOVNTDQ,
21003 IX86_BUILTIN_MOVQ128,
21005 /* SSE2 MMX */
21006 IX86_BUILTIN_MASKMOVDQU,
21007 IX86_BUILTIN_MOVMSKPD,
21008 IX86_BUILTIN_PMOVMSKB128,
21010 IX86_BUILTIN_PACKSSWB128,
21011 IX86_BUILTIN_PACKSSDW128,
21012 IX86_BUILTIN_PACKUSWB128,
21014 IX86_BUILTIN_PADDB128,
21015 IX86_BUILTIN_PADDW128,
21016 IX86_BUILTIN_PADDD128,
21017 IX86_BUILTIN_PADDQ128,
21018 IX86_BUILTIN_PADDSB128,
21019 IX86_BUILTIN_PADDSW128,
21020 IX86_BUILTIN_PADDUSB128,
21021 IX86_BUILTIN_PADDUSW128,
21022 IX86_BUILTIN_PSUBB128,
21023 IX86_BUILTIN_PSUBW128,
21024 IX86_BUILTIN_PSUBD128,
21025 IX86_BUILTIN_PSUBQ128,
21026 IX86_BUILTIN_PSUBSB128,
21027 IX86_BUILTIN_PSUBSW128,
21028 IX86_BUILTIN_PSUBUSB128,
21029 IX86_BUILTIN_PSUBUSW128,
21031 IX86_BUILTIN_PAND128,
21032 IX86_BUILTIN_PANDN128,
21033 IX86_BUILTIN_POR128,
21034 IX86_BUILTIN_PXOR128,
21036 IX86_BUILTIN_PAVGB128,
21037 IX86_BUILTIN_PAVGW128,
21039 IX86_BUILTIN_PCMPEQB128,
21040 IX86_BUILTIN_PCMPEQW128,
21041 IX86_BUILTIN_PCMPEQD128,
21042 IX86_BUILTIN_PCMPGTB128,
21043 IX86_BUILTIN_PCMPGTW128,
21044 IX86_BUILTIN_PCMPGTD128,
21046 IX86_BUILTIN_PMADDWD128,
21048 IX86_BUILTIN_PMAXSW128,
21049 IX86_BUILTIN_PMAXUB128,
21050 IX86_BUILTIN_PMINSW128,
21051 IX86_BUILTIN_PMINUB128,
21053 IX86_BUILTIN_PMULUDQ,
21054 IX86_BUILTIN_PMULUDQ128,
21055 IX86_BUILTIN_PMULHUW128,
21056 IX86_BUILTIN_PMULHW128,
21057 IX86_BUILTIN_PMULLW128,
21059 IX86_BUILTIN_PSADBW128,
21060 IX86_BUILTIN_PSHUFHW,
21061 IX86_BUILTIN_PSHUFLW,
21062 IX86_BUILTIN_PSHUFD,
21064 IX86_BUILTIN_PSLLDQI128,
21065 IX86_BUILTIN_PSLLWI128,
21066 IX86_BUILTIN_PSLLDI128,
21067 IX86_BUILTIN_PSLLQI128,
21068 IX86_BUILTIN_PSRAWI128,
21069 IX86_BUILTIN_PSRADI128,
21070 IX86_BUILTIN_PSRLDQI128,
21071 IX86_BUILTIN_PSRLWI128,
21072 IX86_BUILTIN_PSRLDI128,
21073 IX86_BUILTIN_PSRLQI128,
21075 IX86_BUILTIN_PSLLDQ128,
21076 IX86_BUILTIN_PSLLW128,
21077 IX86_BUILTIN_PSLLD128,
21078 IX86_BUILTIN_PSLLQ128,
21079 IX86_BUILTIN_PSRAW128,
21080 IX86_BUILTIN_PSRAD128,
21081 IX86_BUILTIN_PSRLW128,
21082 IX86_BUILTIN_PSRLD128,
21083 IX86_BUILTIN_PSRLQ128,
21085 IX86_BUILTIN_PUNPCKHBW128,
21086 IX86_BUILTIN_PUNPCKHWD128,
21087 IX86_BUILTIN_PUNPCKHDQ128,
21088 IX86_BUILTIN_PUNPCKHQDQ128,
21089 IX86_BUILTIN_PUNPCKLBW128,
21090 IX86_BUILTIN_PUNPCKLWD128,
21091 IX86_BUILTIN_PUNPCKLDQ128,
21092 IX86_BUILTIN_PUNPCKLQDQ128,
21094 IX86_BUILTIN_CLFLUSH,
21095 IX86_BUILTIN_MFENCE,
21096 IX86_BUILTIN_LFENCE,
21098 IX86_BUILTIN_BSRSI,
21099 IX86_BUILTIN_BSRDI,
21100 IX86_BUILTIN_RDPMC,
21101 IX86_BUILTIN_RDTSC,
21102 IX86_BUILTIN_RDTSCP,
21103 IX86_BUILTIN_ROLQI,
21104 IX86_BUILTIN_ROLHI,
21105 IX86_BUILTIN_RORQI,
21106 IX86_BUILTIN_RORHI,
21108 /* SSE3. */
21109 IX86_BUILTIN_ADDSUBPS,
21110 IX86_BUILTIN_HADDPS,
21111 IX86_BUILTIN_HSUBPS,
21112 IX86_BUILTIN_MOVSHDUP,
21113 IX86_BUILTIN_MOVSLDUP,
21114 IX86_BUILTIN_ADDSUBPD,
21115 IX86_BUILTIN_HADDPD,
21116 IX86_BUILTIN_HSUBPD,
21117 IX86_BUILTIN_LDDQU,
21119 IX86_BUILTIN_MONITOR,
21120 IX86_BUILTIN_MWAIT,
21122 /* SSSE3. */
21123 IX86_BUILTIN_PHADDW,
21124 IX86_BUILTIN_PHADDD,
21125 IX86_BUILTIN_PHADDSW,
21126 IX86_BUILTIN_PHSUBW,
21127 IX86_BUILTIN_PHSUBD,
21128 IX86_BUILTIN_PHSUBSW,
21129 IX86_BUILTIN_PMADDUBSW,
21130 IX86_BUILTIN_PMULHRSW,
21131 IX86_BUILTIN_PSHUFB,
21132 IX86_BUILTIN_PSIGNB,
21133 IX86_BUILTIN_PSIGNW,
21134 IX86_BUILTIN_PSIGND,
21135 IX86_BUILTIN_PALIGNR,
21136 IX86_BUILTIN_PABSB,
21137 IX86_BUILTIN_PABSW,
21138 IX86_BUILTIN_PABSD,
21140 IX86_BUILTIN_PHADDW128,
21141 IX86_BUILTIN_PHADDD128,
21142 IX86_BUILTIN_PHADDSW128,
21143 IX86_BUILTIN_PHSUBW128,
21144 IX86_BUILTIN_PHSUBD128,
21145 IX86_BUILTIN_PHSUBSW128,
21146 IX86_BUILTIN_PMADDUBSW128,
21147 IX86_BUILTIN_PMULHRSW128,
21148 IX86_BUILTIN_PSHUFB128,
21149 IX86_BUILTIN_PSIGNB128,
21150 IX86_BUILTIN_PSIGNW128,
21151 IX86_BUILTIN_PSIGND128,
21152 IX86_BUILTIN_PALIGNR128,
21153 IX86_BUILTIN_PABSB128,
21154 IX86_BUILTIN_PABSW128,
21155 IX86_BUILTIN_PABSD128,
21157 /* AMDFAM10 - SSE4A New Instructions. */
21158 IX86_BUILTIN_MOVNTSD,
21159 IX86_BUILTIN_MOVNTSS,
21160 IX86_BUILTIN_EXTRQI,
21161 IX86_BUILTIN_EXTRQ,
21162 IX86_BUILTIN_INSERTQI,
21163 IX86_BUILTIN_INSERTQ,
21165 /* SSE4.1. */
21166 IX86_BUILTIN_BLENDPD,
21167 IX86_BUILTIN_BLENDPS,
21168 IX86_BUILTIN_BLENDVPD,
21169 IX86_BUILTIN_BLENDVPS,
21170 IX86_BUILTIN_PBLENDVB128,
21171 IX86_BUILTIN_PBLENDW128,
21173 IX86_BUILTIN_DPPD,
21174 IX86_BUILTIN_DPPS,
21176 IX86_BUILTIN_INSERTPS128,
21178 IX86_BUILTIN_MOVNTDQA,
21179 IX86_BUILTIN_MPSADBW128,
21180 IX86_BUILTIN_PACKUSDW128,
21181 IX86_BUILTIN_PCMPEQQ,
21182 IX86_BUILTIN_PHMINPOSUW128,
21184 IX86_BUILTIN_PMAXSB128,
21185 IX86_BUILTIN_PMAXSD128,
21186 IX86_BUILTIN_PMAXUD128,
21187 IX86_BUILTIN_PMAXUW128,
21189 IX86_BUILTIN_PMINSB128,
21190 IX86_BUILTIN_PMINSD128,
21191 IX86_BUILTIN_PMINUD128,
21192 IX86_BUILTIN_PMINUW128,
21194 IX86_BUILTIN_PMOVSXBW128,
21195 IX86_BUILTIN_PMOVSXBD128,
21196 IX86_BUILTIN_PMOVSXBQ128,
21197 IX86_BUILTIN_PMOVSXWD128,
21198 IX86_BUILTIN_PMOVSXWQ128,
21199 IX86_BUILTIN_PMOVSXDQ128,
21201 IX86_BUILTIN_PMOVZXBW128,
21202 IX86_BUILTIN_PMOVZXBD128,
21203 IX86_BUILTIN_PMOVZXBQ128,
21204 IX86_BUILTIN_PMOVZXWD128,
21205 IX86_BUILTIN_PMOVZXWQ128,
21206 IX86_BUILTIN_PMOVZXDQ128,
21208 IX86_BUILTIN_PMULDQ128,
21209 IX86_BUILTIN_PMULLD128,
21211 IX86_BUILTIN_ROUNDPD,
21212 IX86_BUILTIN_ROUNDPS,
21213 IX86_BUILTIN_ROUNDSD,
21214 IX86_BUILTIN_ROUNDSS,
21216 IX86_BUILTIN_PTESTZ,
21217 IX86_BUILTIN_PTESTC,
21218 IX86_BUILTIN_PTESTNZC,
21220 IX86_BUILTIN_VEC_INIT_V2SI,
21221 IX86_BUILTIN_VEC_INIT_V4HI,
21222 IX86_BUILTIN_VEC_INIT_V8QI,
21223 IX86_BUILTIN_VEC_EXT_V2DF,
21224 IX86_BUILTIN_VEC_EXT_V2DI,
21225 IX86_BUILTIN_VEC_EXT_V4SF,
21226 IX86_BUILTIN_VEC_EXT_V4SI,
21227 IX86_BUILTIN_VEC_EXT_V8HI,
21228 IX86_BUILTIN_VEC_EXT_V2SI,
21229 IX86_BUILTIN_VEC_EXT_V4HI,
21230 IX86_BUILTIN_VEC_EXT_V16QI,
21231 IX86_BUILTIN_VEC_SET_V2DI,
21232 IX86_BUILTIN_VEC_SET_V4SF,
21233 IX86_BUILTIN_VEC_SET_V4SI,
21234 IX86_BUILTIN_VEC_SET_V8HI,
21235 IX86_BUILTIN_VEC_SET_V4HI,
21236 IX86_BUILTIN_VEC_SET_V16QI,
21238 IX86_BUILTIN_VEC_PACK_SFIX,
21240 /* SSE4.2. */
21241 IX86_BUILTIN_CRC32QI,
21242 IX86_BUILTIN_CRC32HI,
21243 IX86_BUILTIN_CRC32SI,
21244 IX86_BUILTIN_CRC32DI,
21246 IX86_BUILTIN_PCMPESTRI128,
21247 IX86_BUILTIN_PCMPESTRM128,
21248 IX86_BUILTIN_PCMPESTRA128,
21249 IX86_BUILTIN_PCMPESTRC128,
21250 IX86_BUILTIN_PCMPESTRO128,
21251 IX86_BUILTIN_PCMPESTRS128,
21252 IX86_BUILTIN_PCMPESTRZ128,
21253 IX86_BUILTIN_PCMPISTRI128,
21254 IX86_BUILTIN_PCMPISTRM128,
21255 IX86_BUILTIN_PCMPISTRA128,
21256 IX86_BUILTIN_PCMPISTRC128,
21257 IX86_BUILTIN_PCMPISTRO128,
21258 IX86_BUILTIN_PCMPISTRS128,
21259 IX86_BUILTIN_PCMPISTRZ128,
21261 IX86_BUILTIN_PCMPGTQ,
21263 /* AES instructions */
21264 IX86_BUILTIN_AESENC128,
21265 IX86_BUILTIN_AESENCLAST128,
21266 IX86_BUILTIN_AESDEC128,
21267 IX86_BUILTIN_AESDECLAST128,
21268 IX86_BUILTIN_AESIMC128,
21269 IX86_BUILTIN_AESKEYGENASSIST128,
21271 /* PCLMUL instruction */
21272 IX86_BUILTIN_PCLMULQDQ128,
21274 /* AVX */
21275 IX86_BUILTIN_ADDPD256,
21276 IX86_BUILTIN_ADDPS256,
21277 IX86_BUILTIN_ADDSUBPD256,
21278 IX86_BUILTIN_ADDSUBPS256,
21279 IX86_BUILTIN_ANDPD256,
21280 IX86_BUILTIN_ANDPS256,
21281 IX86_BUILTIN_ANDNPD256,
21282 IX86_BUILTIN_ANDNPS256,
21283 IX86_BUILTIN_BLENDPD256,
21284 IX86_BUILTIN_BLENDPS256,
21285 IX86_BUILTIN_BLENDVPD256,
21286 IX86_BUILTIN_BLENDVPS256,
21287 IX86_BUILTIN_DIVPD256,
21288 IX86_BUILTIN_DIVPS256,
21289 IX86_BUILTIN_DPPS256,
21290 IX86_BUILTIN_HADDPD256,
21291 IX86_BUILTIN_HADDPS256,
21292 IX86_BUILTIN_HSUBPD256,
21293 IX86_BUILTIN_HSUBPS256,
21294 IX86_BUILTIN_MAXPD256,
21295 IX86_BUILTIN_MAXPS256,
21296 IX86_BUILTIN_MINPD256,
21297 IX86_BUILTIN_MINPS256,
21298 IX86_BUILTIN_MULPD256,
21299 IX86_BUILTIN_MULPS256,
21300 IX86_BUILTIN_ORPD256,
21301 IX86_BUILTIN_ORPS256,
21302 IX86_BUILTIN_SHUFPD256,
21303 IX86_BUILTIN_SHUFPS256,
21304 IX86_BUILTIN_SUBPD256,
21305 IX86_BUILTIN_SUBPS256,
21306 IX86_BUILTIN_XORPD256,
21307 IX86_BUILTIN_XORPS256,
21308 IX86_BUILTIN_CMPSD,
21309 IX86_BUILTIN_CMPSS,
21310 IX86_BUILTIN_CMPPD,
21311 IX86_BUILTIN_CMPPS,
21312 IX86_BUILTIN_CMPPD256,
21313 IX86_BUILTIN_CMPPS256,
21314 IX86_BUILTIN_CVTDQ2PD256,
21315 IX86_BUILTIN_CVTDQ2PS256,
21316 IX86_BUILTIN_CVTPD2PS256,
21317 IX86_BUILTIN_CVTPS2DQ256,
21318 IX86_BUILTIN_CVTPS2PD256,
21319 IX86_BUILTIN_CVTTPD2DQ256,
21320 IX86_BUILTIN_CVTPD2DQ256,
21321 IX86_BUILTIN_CVTTPS2DQ256,
21322 IX86_BUILTIN_EXTRACTF128PD256,
21323 IX86_BUILTIN_EXTRACTF128PS256,
21324 IX86_BUILTIN_EXTRACTF128SI256,
21325 IX86_BUILTIN_VZEROALL,
21326 IX86_BUILTIN_VZEROUPPER,
21327 IX86_BUILTIN_VPERMILVARPD,
21328 IX86_BUILTIN_VPERMILVARPS,
21329 IX86_BUILTIN_VPERMILVARPD256,
21330 IX86_BUILTIN_VPERMILVARPS256,
21331 IX86_BUILTIN_VPERMILPD,
21332 IX86_BUILTIN_VPERMILPS,
21333 IX86_BUILTIN_VPERMILPD256,
21334 IX86_BUILTIN_VPERMILPS256,
21335 IX86_BUILTIN_VPERMIL2PD,
21336 IX86_BUILTIN_VPERMIL2PS,
21337 IX86_BUILTIN_VPERMIL2PD256,
21338 IX86_BUILTIN_VPERMIL2PS256,
21339 IX86_BUILTIN_VPERM2F128PD256,
21340 IX86_BUILTIN_VPERM2F128PS256,
21341 IX86_BUILTIN_VPERM2F128SI256,
21342 IX86_BUILTIN_VBROADCASTSS,
21343 IX86_BUILTIN_VBROADCASTSD256,
21344 IX86_BUILTIN_VBROADCASTSS256,
21345 IX86_BUILTIN_VBROADCASTPD256,
21346 IX86_BUILTIN_VBROADCASTPS256,
21347 IX86_BUILTIN_VINSERTF128PD256,
21348 IX86_BUILTIN_VINSERTF128PS256,
21349 IX86_BUILTIN_VINSERTF128SI256,
21350 IX86_BUILTIN_LOADUPD256,
21351 IX86_BUILTIN_LOADUPS256,
21352 IX86_BUILTIN_STOREUPD256,
21353 IX86_BUILTIN_STOREUPS256,
21354 IX86_BUILTIN_LDDQU256,
21355 IX86_BUILTIN_MOVNTDQ256,
21356 IX86_BUILTIN_MOVNTPD256,
21357 IX86_BUILTIN_MOVNTPS256,
21358 IX86_BUILTIN_LOADDQU256,
21359 IX86_BUILTIN_STOREDQU256,
21360 IX86_BUILTIN_MASKLOADPD,
21361 IX86_BUILTIN_MASKLOADPS,
21362 IX86_BUILTIN_MASKSTOREPD,
21363 IX86_BUILTIN_MASKSTOREPS,
21364 IX86_BUILTIN_MASKLOADPD256,
21365 IX86_BUILTIN_MASKLOADPS256,
21366 IX86_BUILTIN_MASKSTOREPD256,
21367 IX86_BUILTIN_MASKSTOREPS256,
21368 IX86_BUILTIN_MOVSHDUP256,
21369 IX86_BUILTIN_MOVSLDUP256,
21370 IX86_BUILTIN_MOVDDUP256,
21372 IX86_BUILTIN_SQRTPD256,
21373 IX86_BUILTIN_SQRTPS256,
21374 IX86_BUILTIN_SQRTPS_NR256,
21375 IX86_BUILTIN_RSQRTPS256,
21376 IX86_BUILTIN_RSQRTPS_NR256,
21378 IX86_BUILTIN_RCPPS256,
21380 IX86_BUILTIN_ROUNDPD256,
21381 IX86_BUILTIN_ROUNDPS256,
21383 IX86_BUILTIN_UNPCKHPD256,
21384 IX86_BUILTIN_UNPCKLPD256,
21385 IX86_BUILTIN_UNPCKHPS256,
21386 IX86_BUILTIN_UNPCKLPS256,
21388 IX86_BUILTIN_SI256_SI,
21389 IX86_BUILTIN_PS256_PS,
21390 IX86_BUILTIN_PD256_PD,
21391 IX86_BUILTIN_SI_SI256,
21392 IX86_BUILTIN_PS_PS256,
21393 IX86_BUILTIN_PD_PD256,
21395 IX86_BUILTIN_VTESTZPD,
21396 IX86_BUILTIN_VTESTCPD,
21397 IX86_BUILTIN_VTESTNZCPD,
21398 IX86_BUILTIN_VTESTZPS,
21399 IX86_BUILTIN_VTESTCPS,
21400 IX86_BUILTIN_VTESTNZCPS,
21401 IX86_BUILTIN_VTESTZPD256,
21402 IX86_BUILTIN_VTESTCPD256,
21403 IX86_BUILTIN_VTESTNZCPD256,
21404 IX86_BUILTIN_VTESTZPS256,
21405 IX86_BUILTIN_VTESTCPS256,
21406 IX86_BUILTIN_VTESTNZCPS256,
21407 IX86_BUILTIN_PTESTZ256,
21408 IX86_BUILTIN_PTESTC256,
21409 IX86_BUILTIN_PTESTNZC256,
21411 IX86_BUILTIN_MOVMSKPD256,
21412 IX86_BUILTIN_MOVMSKPS256,
21414 /* TFmode support builtins. */
21415 IX86_BUILTIN_INFQ,
21416 IX86_BUILTIN_HUGE_VALQ,
21417 IX86_BUILTIN_FABSQ,
21418 IX86_BUILTIN_COPYSIGNQ,
21420 /* Vectorizer support builtins. */
21421 IX86_BUILTIN_CPYSGNPS,
21422 IX86_BUILTIN_CPYSGNPD,
21424 IX86_BUILTIN_CVTUDQ2PS,
21426 IX86_BUILTIN_VEC_PERM_V2DF,
21427 IX86_BUILTIN_VEC_PERM_V4SF,
21428 IX86_BUILTIN_VEC_PERM_V2DI,
21429 IX86_BUILTIN_VEC_PERM_V4SI,
21430 IX86_BUILTIN_VEC_PERM_V8HI,
21431 IX86_BUILTIN_VEC_PERM_V16QI,
21432 IX86_BUILTIN_VEC_PERM_V2DI_U,
21433 IX86_BUILTIN_VEC_PERM_V4SI_U,
21434 IX86_BUILTIN_VEC_PERM_V8HI_U,
21435 IX86_BUILTIN_VEC_PERM_V16QI_U,
21436 IX86_BUILTIN_VEC_PERM_V4DF,
21437 IX86_BUILTIN_VEC_PERM_V8SF,
21439 /* FMA4 and XOP instructions. */
21440 IX86_BUILTIN_VFMADDSS,
21441 IX86_BUILTIN_VFMADDSD,
21442 IX86_BUILTIN_VFMADDPS,
21443 IX86_BUILTIN_VFMADDPD,
21444 IX86_BUILTIN_VFMSUBSS,
21445 IX86_BUILTIN_VFMSUBSD,
21446 IX86_BUILTIN_VFMSUBPS,
21447 IX86_BUILTIN_VFMSUBPD,
21448 IX86_BUILTIN_VFMADDSUBPS,
21449 IX86_BUILTIN_VFMADDSUBPD,
21450 IX86_BUILTIN_VFMSUBADDPS,
21451 IX86_BUILTIN_VFMSUBADDPD,
21452 IX86_BUILTIN_VFNMADDSS,
21453 IX86_BUILTIN_VFNMADDSD,
21454 IX86_BUILTIN_VFNMADDPS,
21455 IX86_BUILTIN_VFNMADDPD,
21456 IX86_BUILTIN_VFNMSUBSS,
21457 IX86_BUILTIN_VFNMSUBSD,
21458 IX86_BUILTIN_VFNMSUBPS,
21459 IX86_BUILTIN_VFNMSUBPD,
21460 IX86_BUILTIN_VFMADDPS256,
21461 IX86_BUILTIN_VFMADDPD256,
21462 IX86_BUILTIN_VFMSUBPS256,
21463 IX86_BUILTIN_VFMSUBPD256,
21464 IX86_BUILTIN_VFMADDSUBPS256,
21465 IX86_BUILTIN_VFMADDSUBPD256,
21466 IX86_BUILTIN_VFMSUBADDPS256,
21467 IX86_BUILTIN_VFMSUBADDPD256,
21468 IX86_BUILTIN_VFNMADDPS256,
21469 IX86_BUILTIN_VFNMADDPD256,
21470 IX86_BUILTIN_VFNMSUBPS256,
21471 IX86_BUILTIN_VFNMSUBPD256,
21473 IX86_BUILTIN_VPCMOV,
21474 IX86_BUILTIN_VPCMOV_V2DI,
21475 IX86_BUILTIN_VPCMOV_V4SI,
21476 IX86_BUILTIN_VPCMOV_V8HI,
21477 IX86_BUILTIN_VPCMOV_V16QI,
21478 IX86_BUILTIN_VPCMOV_V4SF,
21479 IX86_BUILTIN_VPCMOV_V2DF,
21480 IX86_BUILTIN_VPCMOV256,
21481 IX86_BUILTIN_VPCMOV_V4DI256,
21482 IX86_BUILTIN_VPCMOV_V8SI256,
21483 IX86_BUILTIN_VPCMOV_V16HI256,
21484 IX86_BUILTIN_VPCMOV_V32QI256,
21485 IX86_BUILTIN_VPCMOV_V8SF256,
21486 IX86_BUILTIN_VPCMOV_V4DF256,
21488 IX86_BUILTIN_VPPERM,
21490 IX86_BUILTIN_VPMACSSWW,
21491 IX86_BUILTIN_VPMACSWW,
21492 IX86_BUILTIN_VPMACSSWD,
21493 IX86_BUILTIN_VPMACSWD,
21494 IX86_BUILTIN_VPMACSSDD,
21495 IX86_BUILTIN_VPMACSDD,
21496 IX86_BUILTIN_VPMACSSDQL,
21497 IX86_BUILTIN_VPMACSSDQH,
21498 IX86_BUILTIN_VPMACSDQL,
21499 IX86_BUILTIN_VPMACSDQH,
21500 IX86_BUILTIN_VPMADCSSWD,
21501 IX86_BUILTIN_VPMADCSWD,
21503 IX86_BUILTIN_VPHADDBW,
21504 IX86_BUILTIN_VPHADDBD,
21505 IX86_BUILTIN_VPHADDBQ,
21506 IX86_BUILTIN_VPHADDWD,
21507 IX86_BUILTIN_VPHADDWQ,
21508 IX86_BUILTIN_VPHADDDQ,
21509 IX86_BUILTIN_VPHADDUBW,
21510 IX86_BUILTIN_VPHADDUBD,
21511 IX86_BUILTIN_VPHADDUBQ,
21512 IX86_BUILTIN_VPHADDUWD,
21513 IX86_BUILTIN_VPHADDUWQ,
21514 IX86_BUILTIN_VPHADDUDQ,
21515 IX86_BUILTIN_VPHSUBBW,
21516 IX86_BUILTIN_VPHSUBWD,
21517 IX86_BUILTIN_VPHSUBDQ,
21519 IX86_BUILTIN_VPROTB,
21520 IX86_BUILTIN_VPROTW,
21521 IX86_BUILTIN_VPROTD,
21522 IX86_BUILTIN_VPROTQ,
21523 IX86_BUILTIN_VPROTB_IMM,
21524 IX86_BUILTIN_VPROTW_IMM,
21525 IX86_BUILTIN_VPROTD_IMM,
21526 IX86_BUILTIN_VPROTQ_IMM,
21528 IX86_BUILTIN_VPSHLB,
21529 IX86_BUILTIN_VPSHLW,
21530 IX86_BUILTIN_VPSHLD,
21531 IX86_BUILTIN_VPSHLQ,
21532 IX86_BUILTIN_VPSHAB,
21533 IX86_BUILTIN_VPSHAW,
21534 IX86_BUILTIN_VPSHAD,
21535 IX86_BUILTIN_VPSHAQ,
21537 IX86_BUILTIN_VFRCZSS,
21538 IX86_BUILTIN_VFRCZSD,
21539 IX86_BUILTIN_VFRCZPS,
21540 IX86_BUILTIN_VFRCZPD,
21541 IX86_BUILTIN_VFRCZPS256,
21542 IX86_BUILTIN_VFRCZPD256,
21544 IX86_BUILTIN_VPCOMEQUB,
21545 IX86_BUILTIN_VPCOMNEUB,
21546 IX86_BUILTIN_VPCOMLTUB,
21547 IX86_BUILTIN_VPCOMLEUB,
21548 IX86_BUILTIN_VPCOMGTUB,
21549 IX86_BUILTIN_VPCOMGEUB,
21550 IX86_BUILTIN_VPCOMFALSEUB,
21551 IX86_BUILTIN_VPCOMTRUEUB,
21553 IX86_BUILTIN_VPCOMEQUW,
21554 IX86_BUILTIN_VPCOMNEUW,
21555 IX86_BUILTIN_VPCOMLTUW,
21556 IX86_BUILTIN_VPCOMLEUW,
21557 IX86_BUILTIN_VPCOMGTUW,
21558 IX86_BUILTIN_VPCOMGEUW,
21559 IX86_BUILTIN_VPCOMFALSEUW,
21560 IX86_BUILTIN_VPCOMTRUEUW,
21562 IX86_BUILTIN_VPCOMEQUD,
21563 IX86_BUILTIN_VPCOMNEUD,
21564 IX86_BUILTIN_VPCOMLTUD,
21565 IX86_BUILTIN_VPCOMLEUD,
21566 IX86_BUILTIN_VPCOMGTUD,
21567 IX86_BUILTIN_VPCOMGEUD,
21568 IX86_BUILTIN_VPCOMFALSEUD,
21569 IX86_BUILTIN_VPCOMTRUEUD,
21571 IX86_BUILTIN_VPCOMEQUQ,
21572 IX86_BUILTIN_VPCOMNEUQ,
21573 IX86_BUILTIN_VPCOMLTUQ,
21574 IX86_BUILTIN_VPCOMLEUQ,
21575 IX86_BUILTIN_VPCOMGTUQ,
21576 IX86_BUILTIN_VPCOMGEUQ,
21577 IX86_BUILTIN_VPCOMFALSEUQ,
21578 IX86_BUILTIN_VPCOMTRUEUQ,
21580 IX86_BUILTIN_VPCOMEQB,
21581 IX86_BUILTIN_VPCOMNEB,
21582 IX86_BUILTIN_VPCOMLTB,
21583 IX86_BUILTIN_VPCOMLEB,
21584 IX86_BUILTIN_VPCOMGTB,
21585 IX86_BUILTIN_VPCOMGEB,
21586 IX86_BUILTIN_VPCOMFALSEB,
21587 IX86_BUILTIN_VPCOMTRUEB,
21589 IX86_BUILTIN_VPCOMEQW,
21590 IX86_BUILTIN_VPCOMNEW,
21591 IX86_BUILTIN_VPCOMLTW,
21592 IX86_BUILTIN_VPCOMLEW,
21593 IX86_BUILTIN_VPCOMGTW,
21594 IX86_BUILTIN_VPCOMGEW,
21595 IX86_BUILTIN_VPCOMFALSEW,
21596 IX86_BUILTIN_VPCOMTRUEW,
21598 IX86_BUILTIN_VPCOMEQD,
21599 IX86_BUILTIN_VPCOMNED,
21600 IX86_BUILTIN_VPCOMLTD,
21601 IX86_BUILTIN_VPCOMLED,
21602 IX86_BUILTIN_VPCOMGTD,
21603 IX86_BUILTIN_VPCOMGED,
21604 IX86_BUILTIN_VPCOMFALSED,
21605 IX86_BUILTIN_VPCOMTRUED,
21607 IX86_BUILTIN_VPCOMEQQ,
21608 IX86_BUILTIN_VPCOMNEQ,
21609 IX86_BUILTIN_VPCOMLTQ,
21610 IX86_BUILTIN_VPCOMLEQ,
21611 IX86_BUILTIN_VPCOMGTQ,
21612 IX86_BUILTIN_VPCOMGEQ,
21613 IX86_BUILTIN_VPCOMFALSEQ,
21614 IX86_BUILTIN_VPCOMTRUEQ,
21616 /* LWP instructions. */
21617 IX86_BUILTIN_LLWPCB,
21618 IX86_BUILTIN_SLWPCB,
21619 IX86_BUILTIN_LWPVAL32,
21620 IX86_BUILTIN_LWPVAL64,
21621 IX86_BUILTIN_LWPINS32,
21622 IX86_BUILTIN_LWPINS64,
21624 IX86_BUILTIN_CLZS,
21626 IX86_BUILTIN_MAX
21627 };
21629 /* Table for the ix86 builtin decls. */
21632 /* Table of all of the builtin functions that are possible with different ISA's
21633 but are waiting to be built until a function is declared to use that
21634 ISA. */
21641 };
21646 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21647 of which isa_flags to use in the ix86_builtins_isa array. Stores the
21648 function decl in the ix86_builtins array. Returns the function decl or
21649 NULL_TREE, if the builtin was not added.
21651 If the front end has a special hook for builtin functions, delay adding
21652 builtin functions that aren't in the current ISA until the ISA is changed
21653 with function specific optimization. Doing so, can save about 300K for the
21654 default compiler. When the builtin is expanded, check at that time whether
21655 it is valid.
21657 If the front end doesn't have a special hook, record all builtins, even if
21658 it isn't an instruction set in the current ISA in case the user uses
21659 function specific options for a different ISA, so that we don't get scope
21660 errors if a builtin is added in the middle of a function scope. */
21665 {
21669 {
21678 {
21684 }
21685 else
21686 {
21692 }
21693 }
21696 }
21698 /* Like def_builtin, but also marks the function decl "const". */
21703 {
21707 else
21711 }
21713 /* Add any new builtin functions for a given ISA that may not have been
21714 declared. This saves a bit of space compared to adding all of the
21715 declarations to the tree, even if we didn't use them. */
21717 static void
21719 {
21723 {
21726 {
21729 /* Don't define the builtin again. */
21735 NULL_TREE);
21740 }
21741 }
21742 }
21744 /* Bits for builtin_description.flag. */
21746 /* Set when we don't support the comparison natively, and should
21747 swap_comparison in order to support it. */
21748 #define BUILTIN_DESC_SWAP_OPERANDS 1
21750 struct builtin_description
21751 {
21758 };
21761 {
21762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21774 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21775 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21776 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21777 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21781 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21782 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21783 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21786 };
21789 {
21790 /* SSE4.2 */
21791 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21792 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21793 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21794 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21795 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21796 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21797 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21798 };
21801 {
21802 /* SSE4.2 */
21803 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21804 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21805 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21806 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21807 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21808 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21809 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21810 };
21812 /* Special builtins with variable number of arguments. */
21814 {
21815 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21816 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21818 /* MMX */
21819 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21821 /* 3DNow! */
21822 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21824 /* SSE */
21825 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21826 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21827 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21829 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21830 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21831 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21832 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21834 /* SSE or 3DNow!A */
21835 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21836 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
21838 /* SSE2 */
21839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21852 /* SSE3 */
21853 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21855 /* SSE4.1 */
21856 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21858 /* SSE4A */
21859 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21860 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21862 /* AVX */
21863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21866 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21867 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21868 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21870 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21873 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21876 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21881 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21885 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21886 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21887 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21888 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21889 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21893 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
21894 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
21895 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
21896 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
21897 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
21898 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
21900 };
21902 /* Builtins with variable number of arguments. */
21904 {
21905 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21906 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21907 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21908 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21909 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21910 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21911 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21913 /* MMX */
21914 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21915 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21916 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21917 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21918 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21919 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21921 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21922 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21923 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21924 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21925 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21926 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21927 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21928 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21930 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21931 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21933 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21934 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21935 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21936 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21938 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21939 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21940 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21941 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21942 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21943 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21945 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21946 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21947 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21948 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21949 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21950 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21952 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21953 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21954 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21956 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21958 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21959 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21960 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21961 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21962 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21963 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21965 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21966 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21967 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21968 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21974 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21977 /* 3DNow! */
21978 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21979 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21980 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21981 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21983 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21984 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21985 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21986 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21987 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21988 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21989 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21990 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21991 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21992 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21993 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21994 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21995 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21996 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21997 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21999 /* 3DNow!A */
22000 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
22001 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
22002 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
22003 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
22004 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
22005 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
22007 /* SSE */
22008 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
22009 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22010 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22011 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22012 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
22015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
22016 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
22017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
22018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
22019 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
22021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22023 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22024 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22025 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22026 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22027 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22028 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22029 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22030 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22032 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
22033 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
22034 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
22035 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
22036 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
22037 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
22038 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
22039 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
22040 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
22041 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
22042 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
22043 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
22044 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
22045 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
22046 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
22047 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
22048 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
22049 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
22050 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
22051 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
22052 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
22053 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
22055 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22056 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22057 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22058 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22060 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22061 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22062 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22063 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22065 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22067 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22068 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22069 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22070 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22071 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
22074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
22075 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
22077 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
22079 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
22080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
22081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
22083 /* SSE MMX or 3Dnow!A */
22084 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22085 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22086 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22088 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22089 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22090 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22091 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22093 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
22094 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
22096 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
22098 /* SSE2 */
22099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22101 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
22102 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
22103 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
22104 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
22105 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
22106 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22107 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
22108 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
22109 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
22110 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
22111 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
22112 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
22114 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
22115 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
22116 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
22117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
22118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
22119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
22121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
22122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
22123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
22124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
22125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
22127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
22129 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
22130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
22131 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
22132 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
22134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
22135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
22136 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
22138 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22139 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22140 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22141 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
22148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
22149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
22150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
22152 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
22154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
22155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
22156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
22160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
22161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
22162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
22164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
22165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
22166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22168 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22169 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22170 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22171 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22173 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22175 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22176 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22178 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22181 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22182 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22184 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
22186 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22187 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22188 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22189 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22190 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22191 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22192 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22193 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22204 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22205 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
22207 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22208 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22209 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22210 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22222 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22223 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22224 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22227 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22228 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22229 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22230 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22231 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22232 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22233 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22234 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
22237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
22240 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
22243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
22244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22246 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
22248 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
22249 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
22250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
22251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
22253 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
22254 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22255 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22256 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22257 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22258 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22259 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
22262 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22263 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22264 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22265 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22266 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22267 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22269 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22270 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22271 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22272 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
22275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
22280 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
22281 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
22283 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22285 /* SSE2 MMX */
22286 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22287 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22289 /* SSE3 */
22290 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
22291 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22293 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22294 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22295 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22296 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22297 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22298 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22300 /* SSSE3 */
22301 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
22302 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
22303 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22304 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
22305 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
22306 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
22308 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22309 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22310 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22311 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22312 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22313 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22314 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22315 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22316 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22317 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22318 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22319 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22320 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
22321 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
22322 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22323 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22324 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22325 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22326 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22327 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22328 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22329 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22330 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22331 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22333 /* SSSE3. */
22334 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
22335 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
22337 /* SSE4.1 */
22338 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22339 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22340 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
22341 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
22342 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22343 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22344 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22345 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
22346 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22347 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
22349 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22350 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22351 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22352 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22353 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22354 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22355 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22356 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22357 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22358 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22359 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22360 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22361 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22363 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22364 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22365 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22366 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22367 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22368 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22369 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22370 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22371 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22372 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22373 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22374 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22376 /* SSE4.1 */
22377 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22378 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22379 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22380 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22382 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22383 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22384 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22386 /* SSE4.2 */
22387 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22388 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22389 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22390 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22391 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22393 /* SSE4A */
22394 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22395 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22396 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22397 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22399 /* AES */
22400 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22401 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22403 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22404 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22405 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22406 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22408 /* PCLMUL */
22409 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22411 /* AVX */
22412 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22413 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22416 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22417 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22420 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22426 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22427 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22428 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22429 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22430 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22431 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22432 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22433 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22434 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22435 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22436 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22437 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22439 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22446 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22447 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22448 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22449 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22450 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22451 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22452 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22453 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22454 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22455 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22456 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22457 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22458 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22459 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22460 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22461 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22462 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22463 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22464 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22466 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22467 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22468 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22469 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22470 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22471 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22472 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22473 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22474 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22475 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22476 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22477 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22479 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22480 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22481 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22483 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22484 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22485 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22486 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22487 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22489 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22491 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22492 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22494 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22495 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22496 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22497 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22500 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22501 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22502 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22503 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22504 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22506 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22511 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22516 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22525 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
22526 };
22528 /* FMA4 and XOP. */
22529 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
22530 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
22531 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
22532 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
22533 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
22534 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
22535 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
22536 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
22537 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
22538 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
22539 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
22540 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
22541 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
22542 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
22543 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
22544 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
22545 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
22546 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
22547 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
22548 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
22549 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
22550 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
22551 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
22552 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
22553 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
22554 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
22555 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
22556 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
22557 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
22558 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
22559 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
22560 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
22561 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
22562 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
22563 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
22564 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
22565 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
22566 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
22567 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
22568 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
22569 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
22570 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
22571 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
22572 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
22573 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
22574 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
22575 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
22576 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
22577 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
22578 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
22579 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
22580 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
22583 {
22584 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22585 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22586 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22587 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22588 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22589 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22590 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22591 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22593 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22594 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22595 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22596 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22597 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22598 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22599 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22600 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22602 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22603 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22604 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22605 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22607 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22608 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22609 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22610 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22612 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22613 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22614 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22615 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22617 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22618 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22619 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22620 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22630 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
22633 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
22634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
22635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22636 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22638 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22641 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22642 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22644 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22645 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22646 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22649 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22651 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22654 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22656 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22657 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22658 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22659 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22660 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22661 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22662 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22663 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22664 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22665 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22666 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22667 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22668 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22670 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22671 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22672 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22673 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22674 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
22675 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
22677 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22678 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22679 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22680 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22681 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22682 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22683 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22684 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22685 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22686 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22687 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22688 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22689 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22690 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22691 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22693 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22694 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22695 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22696 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22697 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22698 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22699 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22701 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22702 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22703 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22704 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22705 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22706 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22707 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22709 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22710 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22711 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22712 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22713 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22714 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22715 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22717 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22718 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22719 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22720 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22721 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22722 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22723 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22725 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22726 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22727 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22728 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22729 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22730 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22731 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22733 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22734 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22735 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22736 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22737 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22738 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22739 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22741 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22742 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22743 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22744 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22745 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22746 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22747 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22749 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22750 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22751 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22752 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22753 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22754 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22755 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22757 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22758 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22759 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22760 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22761 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22762 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22763 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22764 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22766 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22767 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22768 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22769 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22770 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22771 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22772 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22773 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22775 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
22776 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
22777 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
22778 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
22780 };
22782 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22783 in the current target ISA to allow the user to compile particular modules
22784 with different target specific options that differ from the command line
22785 options. */
22786 static void
22788 {
22793 /* Add all special builtins with variable number of operands. */
22797 {
22803 }
22805 /* Add all builtins with variable number of operands. */
22809 {
22815 }
22817 /* pcmpestr[im] insns. */
22821 {
22824 else
22827 }
22829 /* pcmpistr[im] insns. */
22833 {
22836 else
22839 }
22841 /* comi/ucomi insns. */
22843 {
22846 else
22849 }
22851 /* SSE */
22857 /* SSE or 3DNow!A */
22860 IX86_BUILTIN_MASKMOVQ);
22862 /* SSE2 */
22871 /* SSE3. */
22877 /* AES */
22891 /* PCLMUL */
22895 /* MMX access to the vec_init patterns. */
22900 V4HI_FTYPE_HI_HI_HI_HI,
22901 IX86_BUILTIN_VEC_INIT_V4HI);
22904 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
22905 IX86_BUILTIN_VEC_INIT_V8QI);
22907 /* Access to the vec_extract patterns. */
22929 /* Access to the vec_set patterns. */
22950 /* Add FMA4 multi-arg argument instructions */
22952 {
22958 }
22959 }
22961 /* Internal method for ix86_init_builtins. */
22963 static void
22965 {
22977 sysv_va_ref =
22980 fnvoid_va_end_ms =
22982 fnvoid_va_start_ms =
22984 fnvoid_va_end_sysv =
22986 fnvoid_va_start_sysv =
22988 NULL_TREE);
22989 fnvoid_va_copy_ms =
22991 NULL_TREE);
22992 fnvoid_va_copy_sysv =
23008 }
23010 static void
23012 {
23015 /* The __float80 type. */
23018 {
23019 /* The __float80 type. */
23024 }
23027 /* The __float128 type. */
23033 /* This macro is built by i386-builtin-types.awk. */
23034 DEFINE_BUILTIN_PRIMITIVE_TYPES;
23035 }
23037 static void
23039 {
23040 tree t;
23044 /* TFmode support builtins. */
23050 /* We will expand them to normal call if SSE2 isn't available since
23051 they are used by libgcc. */
23068 }
23070 /* Return the ix86 builtin for CODE. */
23072 static tree
23074 {
23079 }
23081 /* Errors in the source file can cause expand_expr to return const0_rtx
23082 where we expect a vector. To avoid crashing, use one of the vector
23083 clear instructions. */
23084 static rtx
23086 {
23090 }
23092 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23094 static rtx
23096 {
23097 rtx pat;
23117 {
23121 }
23135 }
23137 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23139 static rtx
23143 {
23144 rtx pat;
23152 rtx op;
23159 {
23239 }
23249 {
23256 {
23258 {
23261 }
23262 }
23263 else
23264 {
23268 /* If we aren't optimizing, only allow one memory operand to be
23269 generated. */
23271 num_memory++;
23279 }
23283 }
23286 {
23297 else
23298 {
23304 }
23317 }
23324 }
23326 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23327 insns with vec_merge. */
23329 static rtx
23331 rtx target)
23332 {
23333 rtx pat;
23360 }
23362 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23364 static rtx
23367 {
23368 rtx pat;
23373 rtx op2;
23384 /* Swap operands if we have a comparison that isn't available in
23385 hardware. */
23387 {
23392 }
23412 }
23414 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23416 static rtx
23418 rtx target)
23419 {
23420 rtx pat;
23434 /* Swap operands if we have a comparison that isn't available in
23435 hardware. */
23437 {
23441 }
23462 const0_rtx)));
23465 }
23467 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23469 static rtx
23471 rtx target)
23472 {
23473 rtx pat;
23506 const0_rtx)));
23509 }
23511 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23513 static rtx
23516 {
23517 rtx pat;
23555 {
23558 }
23561 {
23570 }
23572 {
23581 }
23582 else
23583 {
23590 }
23598 {
23603 emit_insn
23607 FLAGS_REG),
23608 const0_rtx)));
23610 }
23611 else
23613 }
23616 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23618 static rtx
23621 {
23622 rtx pat;
23650 {
23653 }
23656 {
23665 }
23667 {
23676 }
23677 else
23678 {
23685 }
23693 {
23698 emit_insn
23702 FLAGS_REG),
23703 const0_rtx)));
23705 }
23706 else
23708 }
23710 /* Subroutine of ix86_expand_builtin to take care of insns with
23711 variable number of operands. */
23713 static rtx
23716 {
23721 struct
23722 {
23723 rtx op;
23735 {
23946 }
23951 {
23954 }
23957 {
23964 }
23965 else
23966 {
23969 }
23972 {
23979 {
23980 /* SIMD shift insns take either an 8-bit immediate or
23981 register as count. But builtin functions take int as
23982 count. If count doesn't match, we put it in register. */
23984 {
23988 }
23989 }
23991 {
23994 {
24036 {
24039 {
24042 }
24048 }
24050 }
24051 }
24052 else
24053 {
24057 /* If we aren't optimizing, only allow one memory operand to
24058 be generated. */
24060 num_memory++;
24063 {
24066 }
24067 else
24068 {
24071 }
24072 }
24076 }
24079 {
24096 }
24103 }
24105 /* Subroutine of ix86_expand_builtin to take care of special insns
24106 with variable number of operands. */
24108 static rtx
24111 {
24112 tree arg;
24115 struct
24116 {
24117 rtx op;
24127 {
24164 /* Reserve memory operand for target. */
24187 /* Reserve memory operand for target. */
24201 }
24206 {
24212 }
24213 else
24214 {
24221 }
24224 {
24233 {
24235 {
24241 else
24244 }
24245 }
24246 else
24247 {
24249 {
24250 /* This must be the memory operand. */
24254 }
24255 else
24256 {
24257 /* This must be register. */
24264 }
24265 }
24269 }
24272 {
24287 }
24293 }
24295 /* Return the integer constant in ARG. Constrain it to be in the range
24296 of the subparts of VEC_TYPE; issue an error if not. */
24298 static int
24300 {
24305 {
24308 }
24311 }
24313 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24314 ix86_expand_vector_init. We DO have language-level syntax for this, in
24315 the form of (type){ init-list }. Except that since we can't place emms
24316 instructions from inside the compiler, we can't allow the use of MMX
24317 registers unless the user explicitly asks for it. So we do *not* define
24318 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24319 we have builtins invoked by mmintrin.h that gives us license to emit
24320 these sorts of instructions. */
24322 static rtx
24324 {
24334 {
24337 }
24344 }
24346 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24347 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24348 had a language-level syntax for referencing vector elements. */
24350 static rtx
24352 {
24356 rtx op0;
24376 }
24378 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24379 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24380 a language-level syntax for referencing vector elements. */
24382 static rtx
24384 {
24408 /* OP0 is the source of these builtin functions and shouldn't be
24409 modified. Create a copy, use it and return it as target. */
24415 }
24417 /* Expand an expression EXP that calls a built-in function,
24418 with result going to TARGET if that's convenient
24419 (and in mode MODE if that's convenient).
24420 SUBTARGET may be used as the target for computing one of EXP's operands.
24421 IGNORE is nonzero if the value is to be ignored. */
24423 static rtx
24427 {
24437 /* Determine whether the builtin function is available under the current ISA.
24438 Originally the builtin was not created if it wasn't applicable to the
24439 current ISA based on the command line switches. With function specific
24440 options, we need to check in the context of the function making the call
24441 whether it is supported. */
24444 {
24450 else
24451 {
24455 }
24457 }
24460 {
24464 ? CODE_FOR_mmx_maskmovq
24466 /* Note the arg order is different from the operand order. */
24581 {
24582 REAL_VALUE_TYPE inf;
24583 rtx tmp;
24595 }
24616 }
24629 {
24633 /* Emit a normal call if SSE2 isn't available. */
24637 }
24662 }
24664 /* Returns a function decl for a vectorized version of the builtin function
24665 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24666 if it is not available. */
24668 static tree
24670 tree type_in)
24671 {
24687 {
24725 ;
24726 }
24728 /* Dispatch to a handler for a vectorization library. */
24731 type_in);
24734 }
24736 /* Handler for an SVML-style interface to
24737 a library with vectorized intrinsics. */
24739 static tree
24741 {
24749 /* The SVML is suitable for unsafe math only. */
24762 {
24809 }
24818 {
24821 }
24822 else
24825 /* Convert to uppercase. */
24831 arity++;
24835 else
24838 /* Build a function declaration for the vectorized function. */
24847 }
24849 /* Handler for an ACML-style interface to
24850 a library with vectorized intrinsics. */
24852 static tree
24854 {
24862 /* The ACML is 64bits only and suitable for unsafe math only as
24863 it does not correctly support parts of IEEE with the required
24864 precision such as denormals. */
24878 {
24908 }
24916 arity++;
24920 else
24923 /* Build a function declaration for the vectorized function. */
24932 }
24935 /* Returns a decl of a function that implements conversion of an integer vector
24936 into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
24937 are the types involved when converting according to CODE.
24938 Return NULL_TREE if it is not available. */
24940 static tree
24943 {
24948 {
24951 {
24954 {
24961 ? NULL_TREE
24965 }
24969 {
24972 ? NULL_TREE
24976 }
24980 }
24984 {
24987 {
24990 ? NULL_TREE
24994 ? NULL_TREE
24998 }
25003 {
25006 ? NULL_TREE
25010 }
25015 }
25019 }
25022 }
25024 /* Returns a code for a target-specific builtin that implements
25025 reciprocal of the function, or NULL_TREE if not available. */
25027 static tree
25030 {
25037 /* Machine dependent builtins. */
25039 {
25040 /* Vectorized version of sqrt to rsqrt conversion. */
25046 }
25047 else
25048 /* Normal builtins. */
25050 {
25051 /* Sqrt to rsqrt conversion. */
25057 }
25058 }
25059 \f
25060 /* Helper for avx_vpermilps256_operand et al. This is also used by
25061 the expansion functions to turn the parallel back into a mask.
25062 The return value is 0 for no match and the imm8+1 for a match. */
25064 int
25066 {
25074 /* Validate that all of the elements are constants, and not totally
25075 out of range. Copy the data into an integral array to make the
25076 subsequent checks easier. */
25078 {
25088 }
25091 {
25093 /* In the 256-bit DFmode case, we can only move elements within
25094 a 128-bit lane. */
25096 {
25100 }
25102 {
25106 }
25110 /* In the 256-bit SFmode case, we have full freedom of movement
25111 within the low 128-bit lane, but the high 128-bit lane must
25112 mirror the exact same pattern. */
25117 /* FALLTHRU */
25121 /* In the 128-bit case, we've full freedom in the placement of
25122 the elements from the source operand. */
25129 }
25131 /* Make sure success has a non-zero value by adding one. */
25133 }
25135 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
25136 the expansion functions to turn the parallel back into a mask.
25137 The return value is 0 for no match and the imm8+1 for a match. */
25139 int
25141 {
25149 /* Validate that all of the elements are constants, and not totally
25150 out of range. Copy the data into an integral array to make the
25151 subsequent checks easier. */
25153 {
25163 }
25165 /* Validate that the halves of the permute are halves. */
25173 /* Reconstruct the mask. */
25175 {
25181 }
25183 /* Make sure success has a non-zero value by adding one. */
25185 }
25186 \f
25188 /* Store OPERAND to the memory after reload is completed. This means
25189 that we can't easily use assign_stack_local. */
25190 rtx
25192 {
25193 rtx result;
25197 {
25200 stack_pointer_rtx,
25203 }
25205 {
25207 {
25211 /* FALLTHRU */
25217 stack_pointer_rtx)),
25218 operand));
25222 }
25224 }
25225 else
25226 {
25228 {
25230 {
25237 stack_pointer_rtx)),
25243 stack_pointer_rtx)),
25245 }
25248 /* Store HImodes as SImodes. */
25250 /* FALLTHRU */
25256 stack_pointer_rtx)),
25257 operand));
25261 }
25263 }
25265 }
25267 /* Free operand from the memory. */
25268 void
25270 {
25272 {
25277 else
25279 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25280 to pop or add instruction if registers are available. */
25284 }
25285 }
25287 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25288 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25289 same. */
25292 {
25295 };
25298 };
25301 }
25303 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25304 QImode must go into class Q_REGS.
25305 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25306 movdf to do mem-to-mem moves through integer regs. */
25307 enum reg_class
25309 {
25312 /* We're only allowed to return a subclass of CLASS. Many of the
25313 following checks fail for NO_REGS, so eliminate that early. */
25317 /* All classes can load zeros. */
25321 /* Force constants into memory if we are loading a (nonzero) constant into
25322 an MMX or SSE register. This is because there are no MMX/SSE instructions
25323 to load from a constant. */
25328 /* Prefer SSE regs only, if we can use them for math. */
25332 /* Floating-point constants need more complex checks. */
25334 {
25335 /* General regs can load everything. */
25339 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25340 zero above. We only want to wind up preferring 80387 registers if
25341 we plan on doing computation with them. */
25344 {
25345 /* Limit class to non-sse. */
25354 }
25357 }
25359 /* Generally when we see PLUS here, it's the function invariant
25360 (plus soft-fp const_int). Which can only be computed into general
25361 regs. */
25365 /* QImode constants are easy to load, but non-constant QImode data
25366 must go into Q_REGS. */
25368 {
25374 }
25377 }
25379 /* Discourage putting floating-point values in SSE registers unless
25380 SSE math is being used, and likewise for the 387 registers. */
25381 enum reg_class
25383 {
25386 /* Restrict the output reload class to the register bank that we are doing
25387 math on. If we would like not to return a subset of CLASS, reject this
25388 alternative: if reload cannot do this, it will still use its choice. */
25394 {
25399 else
25401 }
25404 }
25406 static enum reg_class
25410 {
25411 /* QImode spills from non-QI registers require
25412 intermediate register on 32bit targets. */
25417 {
25422 else
25428 /* Return Q_REGS if the operand is in memory. */
25431 }
25434 }
25436 /* If we are copying between general and FP registers, we need a memory
25437 location. The same is true for SSE and MMX registers.
25439 To optimize register_move_cost performance, allow inline variant.
25441 The macro can't work reliably when one of the CLASSES is class containing
25442 registers from multiple units (SSE, MMX, integer). We avoid this by never
25443 combining those units in single alternative in the machine description.
25444 Ensure that this constraint holds to avoid unexpected surprises.
25446 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25447 enforce these sanity checks. */
25452 {
25459 {
25462 }
25467 /* ??? This is a lie. We do have moves between mmx/general, and for
25468 mmx/sse2. But by saying we need secondary memory we discourage the
25469 register allocator from using the mmx registers unless needed. */
25474 {
25475 /* SSE1 doesn't have any direct moves from other classes. */
25479 /* If the target says that inter-unit moves are more expensive
25480 than moving through memory, then don't generate them. */
25484 /* Between SSE and general, we have moves no larger than word size. */
25487 }
25490 }
25492 int
25495 {
25497 }
25499 /* Return true if the registers in CLASS cannot represent the change from
25500 modes FROM to TO. */
25502 bool
25505 {
25509 /* x87 registers can't do subreg at all, as all values are reformatted
25510 to extended precision. */
25515 {
25516 /* Vector registers do not support QI or HImode loads. If we don't
25517 disallow a change to these modes, reload will assume it's ok to
25518 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25519 the vec_dupv4hi pattern. */
25523 /* Vector registers do not support subreg with nonzero offsets, which
25524 are otherwise valid for integer registers. Since we can't see
25525 whether we have a nonzero offset from here, prohibit all
25526 nonparadoxical subregs changing size. */
25529 }
25532 }
25534 /* Return the cost of moving data of mode M between a
25535 register and memory. A value of 2 is the default; this cost is
25536 relative to those in `REGISTER_MOVE_COST'.
25538 This function is used extensively by register_move_cost that is used to
25539 build tables at startup. Make it inline in this case.
25540 When IN is 2, return maximum of in and out move cost.
25542 If moving between registers and memory is more expensive than
25543 between two registers, you should define this macro to express the
25544 relative cost.
25546 Model also increased moving costs of QImode registers in non
25547 Q_REGS classes.
25548 */
25552 {
25555 {
25558 {
25570 }
25574 }
25576 {
25579 {
25591 }
25595 }
25597 {
25600 {
25609 }
25613 }
25615 {
25618 {
25624 else
25629 }
25630 else
25631 {
25636 else
25638 }
25645 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25652 else
25656 }
25657 }
25659 static int
25662 {
25664 }
25667 /* Return the cost of moving data from a register in class CLASS1 to
25668 one in class CLASS2.
25670 It is not required that the cost always equal 2 when FROM is the same as TO;
25671 on some machines it is expensive to move between registers if they are not
25672 general registers. */
25674 static int
25677 {
25678 /* In case we require secondary memory, compute cost of the store followed
25679 by load. In order to avoid bad register allocation choices, we need
25680 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25683 {
25689 /* In case of copying from general_purpose_register we may emit multiple
25690 stores followed by single load causing memory size mismatch stall.
25691 Count this as arbitrarily high cost of 20. */
25695 /* In the case of FP/MMX moves, the registers actually overlap, and we
25696 have to switch modes in order to treat them differently. */
25702 }
25704 /* Moves between SSE/MMX and integer unit are expensive. */
25708 /* ??? By keeping returned value relatively high, we limit the number
25709 of moves between integer and MMX/SSE registers for all targets.
25710 Additionally, high value prevents problem with x86_modes_tieable_p(),
25711 where integer modes in MMX/SSE registers are not tieable
25712 because of missing QImode and HImode moves to, from or between
25713 MMX/SSE registers. */
25723 }
25725 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25727 bool
25729 {
25730 /* Flags and only flags can only hold CCmode values. */
25740 {
25741 /* We implement the move patterns for all vector modes into and
25742 out of SSE registers, even when no operation instructions
25743 are available. OImode move is available only when AVX is
25744 enabled. */
25751 }
25753 {
25754 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25755 so if the register is available at all, then we can move data of
25756 the given mode into or out of it. */
25759 }
25762 {
25763 /* Take care for QImode values - they can be in non-QI regs,
25764 but then they do cause partial register stalls. */
25770 }
25771 /* We handle both integer and floats in the general purpose registers. */
25778 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25779 on to use that value in smaller contexts, this can easily force a
25780 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25781 supporting DImode, allow it. */
25786 }
25788 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25789 tieable integer mode. */
25791 static bool
25793 {
25795 {
25808 }
25809 }
25811 /* Return true if MODE1 is accessible in a register that can hold MODE2
25812 without copying. That is, all register classes that can hold MODE2
25813 can also hold MODE1. */
25815 bool
25817 {
25825 /* MODE2 being XFmode implies fp stack or general regs, which means we
25826 can tie any smaller floating point modes to it. Note that we do not
25827 tie this with TFmode. */
25831 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25832 that we can tie it with SFmode. */
25836 /* If MODE2 is only appropriate for an SSE register, then tie with
25837 any other mode acceptable to SSE registers. */
25843 /* If MODE2 is appropriate for an MMX register, then tie
25844 with any other mode acceptable to MMX registers. */
25851 }
25853 /* Compute a (partial) cost for rtx X. Return true if the complete
25854 cost has been computed, and false if subexpressions should be
25855 scanned. In either case, *TOTAL contains the cost result. */
25857 static bool
25859 {
25865 {
25875 && (!TARGET_64BIT
25880 else
25887 else
25889 {
25898 /* Start with (MEM (SYMBOL_REF)), since that's where
25899 it'll probably end up. Add a penalty for size. */
25904 }
25908 /* The zero extensions is often completely free on x86_64, so make
25909 it as cheap as possible. */
25915 else
25926 {
25929 {
25932 }
25935 {
25938 }
25939 }
25940 /* FALLTHRU */
25947 {
25949 {
25952 else
25954 }
25955 else
25956 {
25959 else
25961 }
25962 }
25963 else
25964 {
25967 else
25969 }
25974 {
25975 /* ??? SSE scalar cost should be used here. */
25978 }
25980 {
25983 }
25985 {
25986 /* ??? SSE vector cost should be used here. */
25989 }
25990 else
25991 {
25996 {
25999 nbits++;
26000 }
26001 else
26002 /* This is arbitrary. */
26005 /* Compute costs correctly for widening multiplication. */
26009 {
26016 {
26020 else
26022 }
26026 }
26033 }
26040 /* ??? SSE cost should be used here. */
26045 /* ??? SSE vector cost should be used here. */
26047 else
26054 {
26059 {
26062 {
26069 }
26070 }
26073 {
26076 {
26081 }
26082 }
26084 {
26090 }
26091 }
26092 /* FALLTHRU */
26096 {
26097 /* ??? SSE cost should be used here. */
26100 }
26102 {
26105 }
26107 {
26108 /* ??? SSE vector cost should be used here. */
26111 }
26112 /* FALLTHRU */
26118 {
26125 }
26126 /* FALLTHRU */
26130 {
26131 /* ??? SSE cost should be used here. */
26134 }
26136 {
26139 }
26141 {
26142 /* ??? SSE vector cost should be used here. */
26145 }
26146 /* FALLTHRU */
26151 else
26160 {
26161 /* This kind of construct is implemented using test[bwl].
26162 Treat it as if we had an AND. */
26167 }
26177 /* ??? SSE cost should be used here. */
26182 /* ??? SSE vector cost should be used here. */
26188 /* ??? SSE cost should be used here. */
26193 /* ??? SSE vector cost should be used here. */
26206 /* ??? Assume all of these vector manipulation patterns are
26207 recognizable. In which case they all pretty much have the
26208 same cost. */
26214 }
26215 }
26217 #if TARGET_MACHO
26221 /* Given a symbol name and its associated stub, write out the
26222 definition of the stub. */
26224 void
26226 {
26231 /* For 64-bit we shouldn't get here. */
26234 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26249 else
26256 {
26260 }
26261 else
26267 {
26270 }
26271 else
26280 }
26283 /* Order the registers for register allocator. */
26285 void
26287 {
26291 /* First allocate the local general purpose registers. */
26296 /* Global general purpose registers. */
26301 /* x87 registers come first in case we are doing FP math
26302 using them. */
26307 /* SSE registers. */
26313 /* x87 registers. */
26321 /* Initialize the rest of array as we do not allocate some registers
26322 at all. */
26325 }
26327 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26328 struct attribute_spec.handler. */
26329 static tree
26331 tree args ATTRIBUTE_UNUSED,
26333 {
26338 {
26340 name);
26343 }
26345 {
26347 name);
26350 }
26352 /* Can combine regparm with all attributes but fastcall. */
26354 {
26356 {
26358 }
26361 }
26363 {
26365 {
26367 }
26370 }
26373 }
26375 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26376 struct attribute_spec.handler. */
26377 static tree
26379 tree args ATTRIBUTE_UNUSED,
26381 {
26384 {
26387 }
26388 else
26393 {
26395 name);
26397 }
26403 {
26405 name);
26407 }
26410 }
26412 static tree
26414 tree args ATTRIBUTE_UNUSED,
26416 {
26418 {
26420 name);
26423 }
26426 {
26428 name);
26430 }
26432 #ifndef HAVE_AS_IX86_SWAP
26434 #endif
26437 }
26439 static bool
26441 {
26445 }
26447 /* Returns an expression indicating where the this parameter is
26448 located on entry to the FUNCTION. */
26450 static rtx
26452 {
26458 {
26463 else
26466 }
26471 {
26477 {
26482 }
26483 else
26484 {
26487 {
26492 }
26493 }
26495 }
26498 }
26500 /* Determine whether x86_output_mi_thunk can succeed. */
26502 static bool
26504 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26506 {
26507 /* 64-bit can handle anything. */
26511 /* For 32-bit, everything's fine if we have one free register. */
26515 /* Need a free register for vcall_offset. */
26519 /* Need a free register for GOT references. */
26523 /* Otherwise ok. */
26525 }
26527 /* Output the assembler code for a thunk function. THUNK_DECL is the
26528 declaration for the thunk function itself, FUNCTION is the decl for
26529 the target function. DELTA is an immediate constant offset to be
26530 added to THIS. If VCALL_OFFSET is nonzero, the word at
26531 *(*this + vcall_offset) should be added to THIS. */
26533 static void
26537 {
26542 /* Make sure unwind info is emitted for the thunk if needed. */
26545 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26546 pull it in now and let DELTA benefit. */
26550 {
26551 /* Put the this parameter into %eax. */
26555 }
26556 else
26559 /* Adjust the this parameter by a fixed constant. */
26561 {
26565 {
26567 {
26573 }
26576 else
26578 }
26581 else
26583 }
26585 /* Adjust the this parameter by a value stored in the vtable. */
26587 {
26590 else
26591 {
26599 }
26605 /* Adjust the this parameter. */
26608 {
26614 }
26617 }
26619 /* If necessary, drop THIS back to its stack slot. */
26621 {
26625 }
26629 {
26632 /* All thunks should be in the same object as their target,
26633 and thus binds_local_p should be true. */
26636 else
26637 {
26643 }
26644 }
26645 else
26646 {
26649 else
26650 #if TARGET_MACHO
26652 {
26654 tmp = (gen_rtx_SYMBOL_REF
26660 }
26661 else
26663 {
26670 }
26671 }
26673 }
26675 static void
26677 {
26679 #if TARGET_MACHO
26681 #endif
26688 }
26690 int
26692 {
26704 }
26706 /* Output assembler code to FILE to increment profiler label # LABELNO
26707 for profiling a function entry. */
26708 void
26710 {
26712 {
26713 #ifndef NO_PROFILE_COUNTERS
26715 #endif
26719 else
26721 }
26723 {
26724 #ifndef NO_PROFILE_COUNTERS
26727 #endif
26729 }
26730 else
26731 {
26732 #ifndef NO_PROFILE_COUNTERS
26735 #endif
26737 }
26738 }
26740 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26741 /* We don't have exact information about the insn sizes, but we may assume
26742 quite safely that we are informed about all 1 byte insns and memory
26743 address sizes. This is enough to eliminate unnecessary padding in
26744 99% of cases. */
26746 static int
26748 {
26754 /* Discard alignments we've emit and jump instructions. */
26761 /* Important case - calls are always 5 bytes.
26762 It is common to have many calls in the row. */
26771 /* For normal instructions we rely on get_attr_length being exact,
26772 with a few exceptions. */
26774 {
26778 {
26788 /* Otherwise trust get_attr_length. */
26790 }
26795 }
26798 else
26800 }
26802 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26803 window. */
26805 static void
26807 {
26812 /* Look for all minimal intervals of instructions containing 4 jumps.
26813 The intervals are bounded by START and INSN. NBYTES is the total
26814 size of instructions in the interval including INSN and not including
26815 START. When the NBYTES is smaller than 16 bytes, it is possible
26816 that the end of START and INSN ends up in the same 16byte page.
26818 The smallest offset in the page INSN can start is the case where START
26819 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26820 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26821 */
26823 {
26827 {
26833 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26834 already in the current 16 byte page, because otherwise
26835 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26836 bytes to reach 16 byte boundary. */
26844 {
26846 {
26853 else
26856 }
26857 }
26859 }
26870 njumps++;
26871 else
26875 {
26882 else
26885 }
26892 {
26899 }
26900 }
26901 }
26902 #endif
26904 /* AMD Athlon works faster
26905 when RET is not destination of conditional jump or directly preceded
26906 by other jump instruction. We avoid the penalty by inserting NOP just
26907 before the RET instructions in such cases. */
26908 static void
26910 {
26911 edge e;
26912 edge_iterator ei;
26915 {
26918 rtx prev;
26928 {
26929 edge e;
26930 edge_iterator ei;
26936 }
26938 {
26944 /* Empty functions get branch mispredict even when the jump destination
26945 is not visible to us. */
26948 }
26950 {
26953 }
26954 }
26955 }
26957 /* Implement machine specific optimizations. We implement padding of returns
26958 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26959 static void
26961 {
26963 {
26966 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26969 #endif
26970 }
26971 }
26973 /* Return nonzero when QImode register that must be represented via REX prefix
26974 is used. */
26975 bool
26977 {
26985 }
26987 /* Return nonzero when P points to register encoded via REX prefix.
26988 Called via for_each_rtx. */
26989 static int
26991 {
26997 }
26999 /* Return true when INSN mentions register that must be encoded using REX
27000 prefix. */
27001 bool
27003 {
27006 }
27008 /* If profitable, negate (without causing overflow) integer constant
27009 of mode MODE at location LOC. Return true in this case. */
27010 bool
27012 {
27013 HOST_WIDE_INT val;
27019 {
27021 /* DImode x86_64 constants must fit in 32 bits. */
27034 }
27036 /* Avoid overflows. */
27042 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
27043 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
27046 {
27049 }
27052 }
27054 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27055 optabs would emit if we didn't have TFmode patterns. */
27057 void
27059 {
27093 }
27094 \f
27095 /* AVX does not support 32-byte integer vector operations,
27096 thus the longest vector we are faced with is V16QImode. */
27097 #define MAX_VECT_LEN 16
27099 struct expand_vec_perm_d
27100 {
27106 };
27111 /* Get a vector mode of the same size as the original but with elements
27112 twice as wide. This is only guaranteed to apply to integral vectors. */
27116 {
27117 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
27122 }
27124 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27125 with all elements equal to VAR. Return true if successful. */
27127 static bool
27130 {
27134 {
27139 /* FALLTHRU */
27149 {
27152 /* First attempt to recognize VAL as-is. */
27156 {
27157 rtx seq;
27158 /* If that fails, force VAL into a register. */
27169 }
27170 }
27177 {
27178 rtx x;
27185 }
27195 {
27199 permute:
27206 /* Extend to SImode using a paradoxical SUBREG. */
27210 /* Insert the SImode value as low element of a V4SImode vector. */
27218 }
27226 widen:
27227 /* Replicate the value once into the next wider mode and recurse. */
27228 {
27230 rtx x;
27246 }
27250 {
27259 }
27264 }
27265 }
27267 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27268 whose ONE_VAR element is VAR, and other elements are zero. Return true
27269 if successful. */
27271 static bool
27274 {
27276 rtx new_target;
27281 {
27283 /* For SSE4.1, we normally use vector set. But if the second
27284 element is zero and inter-unit moves are OK, we use movq
27285 instead. */
27286 use_vector_set = (TARGET_64BIT
27287 && TARGET_SSE4_1
27288 && !(TARGET_INTER_UNIT_MOVES
27310 /* Use ix86_expand_vector_set in 64bit mode only. */
27315 }
27318 {
27323 }
27326 {
27331 /* FALLTHRU */
27346 else
27353 {
27354 /* We need to shuffle the value to the correct position, so
27355 create a new pseudo to store the intermediate result. */
27357 /* With SSE2, we can use the integer shuffle insns. */
27359 {
27361 const1_rtx,
27368 }
27370 /* Otherwise convert the intermediate result to V4SFmode and
27371 use the SSE1 shuffle instructions. */
27373 {
27376 }
27377 else
27381 const1_rtx,
27390 }
27405 widen:
27409 /* Zero extend the variable element to SImode and recurse. */
27422 }
27423 }
27425 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27426 consisting of the values in VALS. It is known that all elements
27427 except ONE_VAR are constants. Return true if successful. */
27429 static bool
27432 {
27442 {
27447 /* For the two element vectors, it's just as easy to use
27448 the general case. */
27452 /* Use ix86_expand_vector_set in 64bit mode only. */
27474 widen:
27475 /* There's no way to set one QImode entry easily. Combine
27476 the variable value with its adjacent constant value, and
27477 promote to an HImode set. */
27480 {
27485 }
27486 else
27487 {
27490 }
27504 }
27509 }
27511 /* A subroutine of ix86_expand_vector_init_general. Use vector
27512 concatenate to handle the most general case: all values variable,
27513 and none identical. */
27515 static void
27518 {
27521 rtvec v;
27525 {
27528 {
27561 }
27574 {
27589 }
27594 {
27605 }
27608 half:
27609 /* FIXME: We process inputs backward to help RA. PR 36222. */
27613 {
27618 }
27622 {
27625 {
27629 }
27632 }
27633 else
27639 }
27640 }
27642 /* A subroutine of ix86_expand_vector_init_general. Use vector
27643 interleave to handle the most general case: all values variable,
27644 and none identical. */
27646 static void
27649 {
27658 {
27679 }
27682 {
27683 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27687 /* Insert the SImode value as low element of V4SImode vector. */
27691 op0),
27693 const1_rtx);
27696 /* Cast the V4SImode vector back to a vector in orignal mode. */
27700 /* Load even elements into the second positon. */
27704 const1_rtx));
27706 /* Cast vector to FIRST_IMODE vector. */
27709 }
27711 /* Interleave low FIRST_IMODE vectors. */
27713 {
27717 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27720 }
27722 /* Interleave low SECOND_IMODE vectors. */
27724 {
27727 {
27732 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27733 vector. */
27736 }
27739 /* FALLTHRU */
27746 /* Cast the SECOND_IMODE vector back to a vector on original
27747 mode. */
27754 }
27755 }
27757 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27758 all values variable, and none identical. */
27760 static void
27763 {
27769 {
27774 /* FALLTHRU */
27798 half:
27815 /* FALLTHRU */
27821 /* Don't use ix86_expand_vector_init_interleave if we can't
27822 move from GPR to SSE register directly. */
27838 }
27840 {
27852 {
27856 {
27862 else
27863 {
27868 }
27869 }
27872 }
27877 {
27883 }
27885 {
27891 }
27892 else
27894 }
27895 }
27897 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27898 instructions unless MMX_OK is true. */
27900 void
27902 {
27909 rtx x;
27912 {
27922 }
27924 /* Constants are best loaded from the constant pool. */
27926 {
27929 }
27931 /* If all values are identical, broadcast the value. */
27937 /* Values where only one field is non-constant are best loaded from
27938 the pool and overwritten via move later. */
27940 {
27944 one_var))
27949 }
27952 }
27954 void
27956 {
27961 rtx tmp;
27963 = {
27970 };
27972 = {
27979 };
27983 {
27987 {
27992 else
27996 }
28005 {
28008 /* For the two element vectors, we implement a VEC_CONCAT with
28009 the extraction of the other element. */
28016 else
28021 }
28030 {
28036 /* tmp = target = A B C D */
28038 /* target = A A B B */
28040 /* target = X A B B */
28042 /* target = A X C D */
28049 /* tmp = target = A B C D */
28051 /* tmp = X B C D */
28053 /* target = A B X D */
28060 /* tmp = target = A B C D */
28062 /* tmp = X B C D */
28064 /* target = A B X D */
28072 }
28080 /* Element 0 handled by vec_merge below. */
28082 {
28085 }
28088 {
28089 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28090 store into element 0, then shuffle them back. */
28107 }
28108 else
28109 {
28110 /* For SSE1, we have to reuse the V4SF code. */
28113 }
28166 half:
28167 /* Compute offset. */
28173 /* Extract the half. */
28177 /* Put val in tmp at elt. */
28180 /* Put it back. */
28186 }
28189 {
28193 }
28194 else
28195 {
28204 }
28205 }
28207 void
28209 {
28213 rtx tmp;
28216 {
28221 /* FALLTHRU */
28234 {
28254 }
28266 {
28268 {
28288 }
28292 }
28293 else
28294 {
28295 /* For SSE1, we have to reuse the V4SF code. */
28299 }
28314 /* ??? Could extract the appropriate HImode element and shift. */
28317 }
28320 {
28324 /* Let the rtl optimizers know about the zero extension performed. */
28326 {
28329 }
28332 }
28333 else
28334 {
28341 }
28342 }
28344 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28345 pattern to reduce; DEST is the destination; IN is the input vector. */
28347 void
28349 {
28363 }
28364 \f
28365 /* Target hook for scalar_mode_supported_p. */
28366 static bool
28368 {
28373 else
28375 }
28377 /* Implements target hook vector_mode_supported_p. */
28378 static bool
28380 {
28392 }
28394 /* Target hook for c_mode_for_suffix. */
28395 static enum machine_mode
28397 {
28404 }
28406 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28408 We do this in the new i386 backend to maintain source compatibility
28409 with the old cc0-based compiler. */
28411 static tree
28413 tree inputs ATTRIBUTE_UNUSED,
28414 tree clobbers)
28415 {
28417 clobbers);
28419 clobbers);
28421 }
28423 /* Implements target vector targetm.asm.encode_section_info. This
28424 is not used by netware. */
28426 static void ATTRIBUTE_UNUSED
28428 {
28435 }
28437 /* Worker function for REVERSE_CONDITION. */
28439 enum rtx_code
28441 {
28445 }
28447 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28448 to OPERANDS[0]. */
28452 {
28454 {
28457 {
28461 }
28465 }
28467 {
28471 else
28472 {
28473 /* There is no non-popping store to memory for XFmode.
28474 So if we need one, follow the store with a load. */
28477 else
28479 }
28480 }
28481 else
28483 }
28485 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28486 FP status register is set. */
28488 void
28490 {
28492 rtx temp;
28497 {
28502 }
28503 else
28504 {
28509 }
28513 pc_rtx);
28518 }
28520 /* Output code to perform a log1p XFmode calculation. */
28523 {
28529 rtx test;
28535 XFmode));
28549 }
28551 /* Output code to perform a Newton-Rhapson approximation of a single precision
28552 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28555 {
28570 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28572 /* x0 = rcp(b) estimate */
28575 UNSPEC_RCP)));
28576 /* e0 = x0 * a */
28579 /* e1 = x0 * b */
28582 /* x1 = 2. - e1 */
28585 /* res = e0 * x1 */
28588 }
28590 /* Output code to perform a Newton-Rhapson approximation of a
28591 single precision floating point [reciprocal] square root. */
28595 {
28597 REAL_VALUE_TYPE r;
28612 {
28615 }
28617 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28618 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28620 /* x0 = rsqrt(a) estimate */
28623 UNSPEC_RSQRT)));
28625 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28627 {
28639 }
28641 /* e0 = x0 * a */
28644 /* e1 = e0 * x0 */
28648 /* e2 = e1 - 3. */
28655 /* e3 = -.5 * x0 */
28658 else
28659 /* e3 = -.5 * e0 */
28662 /* ret = e2 * e3 */
28665 }
28667 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28669 static void ATTRIBUTE_UNUSED
28671 tree decl)
28672 {
28673 /* With Binutils 2.15, the "@unwind" marker must be specified on
28674 every occurrence of the ".eh_frame" section, not just the first
28675 one. */
28678 {
28682 }
28684 }
28686 /* Return the mangling of TYPE if it is an extended fundamental type. */
28690 {
28698 {
28700 /* __float128 is "g". */
28703 /* "long double" or __float80 is "e". */
28707 }
28708 }
28710 /* For 32-bit code we can save PIC register setup by using
28711 __stack_chk_fail_local hidden function instead of calling
28712 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28713 register, so it is better to call __stack_chk_fail directly. */
28715 static tree
28717 {
28718 return TARGET_64BIT
28721 }
28723 /* Select a format to encode pointers in exception handling data. CODE
28724 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28725 true if the symbol may be affected by dynamic relocations.
28727 ??? All x86 object file formats are capable of representing this.
28728 After all, the relocation needed is the same as for the call insn.
28729 Whether or not a particular assembler allows us to enter such, I
28730 guess we'll have to see. */
28731 int
28733 {
28735 {
28742 }
28747 }
28748 \f
28749 /* Expand copysign from SIGN to the positive value ABS_VALUE
28750 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28751 the sign-bit. */
28752 static void
28754 {
28758 {
28761 {
28762 /* We need to generate a scalar mode mask in this case. */
28767 }
28768 }
28769 else
28775 }
28777 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28778 mask for masking out the sign-bit is stored in *SMASK, if that is
28779 non-null. */
28780 static rtx
28782 {
28789 {
28790 /* We need to generate a scalar mode mask in this case. */
28795 }
28803 }
28805 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28806 swapping the operands if SWAP_OPERANDS is true. The expanded
28807 code is a forward jump to a newly created label in case the
28808 comparison is true. The generated label rtx is returned. */
28809 static rtx
28812 {
28816 {
28820 }
28833 }
28835 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28836 using comparison code CODE. Operands are swapped for the comparison if
28837 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28838 static rtx
28841 {
28846 {
28850 }
28855 else
28860 }
28862 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28863 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28864 static rtx
28866 {
28867 REAL_VALUE_TYPE TWO52r;
28868 rtx TWO52;
28875 }
28877 /* Expand SSE sequence for computing lround from OP1 storing
28878 into OP0. */
28879 void
28881 {
28882 /* C code for the stuff we're doing below:
28883 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28884 return (long)tmp;
28885 */
28889 rtx adj;
28891 /* load nextafter (0.5, 0.0) */
28896 /* adj = copysign (0.5, op1) */
28900 /* adj = op1 + adj */
28903 /* op0 = (imode)adj */
28905 }
28907 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28908 into OPERAND0. */
28909 void
28911 {
28912 /* C code for the stuff we're doing below (for do_floor):
28913 xi = (long)op1;
28914 xi -= (double)xi > op1 ? 1 : 0;
28915 return xi;
28916 */
28921 /* reg = (long)op1 */
28925 /* freg = (double)reg */
28929 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28940 }
28942 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28943 result in OPERAND0. */
28944 void
28946 {
28947 /* C code for the stuff we're doing below:
28948 xa = fabs (operand1);
28949 if (!isless (xa, 2**52))
28950 return operand1;
28951 xa = xa + 2**52 - 2**52;
28952 return copysign (xa, operand1);
28953 */
28960 /* xa = abs (operand1) */
28963 /* if (!isless (xa, TWO52)) goto label; */
28976 }
28978 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28979 into OPERAND0. */
28980 void
28982 {
28983 /* C code for the stuff we expand below.
28984 double xa = fabs (x), x2;
28985 if (!isless (xa, TWO52))
28986 return x;
28987 xa = xa + TWO52 - TWO52;
28988 x2 = copysign (xa, x);
28989 Compensate. Floor:
28990 if (x2 > x)
28991 x2 -= 1;
28992 Compensate. Ceil:
28993 if (x2 < x)
28994 x2 -= -1;
28995 return x2;
28996 */
29002 /* Temporary for holding the result, initialized to the input
29003 operand to ease control flow. */
29007 /* xa = abs (operand1) */
29010 /* if (!isless (xa, TWO52)) goto label; */
29013 /* xa = xa + TWO52 - TWO52; */
29017 /* xa = copysign (xa, operand1) */
29020 /* generate 1.0 or -1.0 */
29025 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29029 /* We always need to subtract here to preserve signed zero. */
29038 }
29040 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29041 into OPERAND0. */
29042 void
29044 {
29045 /* C code for the stuff we expand below.
29046 double xa = fabs (x), x2;
29047 if (!isless (xa, TWO52))
29048 return x;
29049 x2 = (double)(long)x;
29050 Compensate. Floor:
29051 if (x2 > x)
29052 x2 -= 1;
29053 Compensate. Ceil:
29054 if (x2 < x)
29055 x2 += 1;
29056 if (HONOR_SIGNED_ZEROS (mode))
29057 return copysign (x2, x);
29058 return x2;
29059 */
29065 /* Temporary for holding the result, initialized to the input
29066 operand to ease control flow. */
29070 /* xa = abs (operand1) */
29073 /* if (!isless (xa, TWO52)) goto label; */
29076 /* xa = (double)(long)x */
29081 /* generate 1.0 */
29084 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29099 }
29101 /* Expand SSE sequence for computing round from OPERAND1 storing
29102 into OPERAND0. Sequence that works without relying on DImode truncation
29103 via cvttsd2siq that is only available on 64bit targets. */
29104 void
29106 {
29107 /* C code for the stuff we expand below.
29108 double xa = fabs (x), xa2, x2;
29109 if (!isless (xa, TWO52))
29110 return x;
29111 Using the absolute value and copying back sign makes
29112 -0.0 -> -0.0 correct.
29113 xa2 = xa + TWO52 - TWO52;
29114 Compensate.
29115 dxa = xa2 - xa;
29116 if (dxa <= -0.5)
29117 xa2 += 1;
29118 else if (dxa > 0.5)
29119 xa2 -= 1;
29120 x2 = copysign (xa2, x);
29121 return x2;
29122 */
29128 /* Temporary for holding the result, initialized to the input
29129 operand to ease control flow. */
29133 /* xa = abs (operand1) */
29136 /* if (!isless (xa, TWO52)) goto label; */
29139 /* xa2 = xa + TWO52 - TWO52; */
29143 /* dxa = xa2 - xa; */
29146 /* generate 0.5, 1.0 and -0.5 */
29152 /* Compensate. */
29154 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29159 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29165 /* res = copysign (xa2, operand1) */
29172 }
29174 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29175 into OPERAND0. */
29176 void
29178 {
29179 /* C code for SSE variant we expand below.
29180 double xa = fabs (x), x2;
29181 if (!isless (xa, TWO52))
29182 return x;
29183 x2 = (double)(long)x;
29184 if (HONOR_SIGNED_ZEROS (mode))
29185 return copysign (x2, x);
29186 return x2;
29187 */
29193 /* Temporary for holding the result, initialized to the input
29194 operand to ease control flow. */
29198 /* xa = abs (operand1) */
29201 /* if (!isless (xa, TWO52)) goto label; */
29204 /* x = (double)(long)x */
29216 }
29218 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29219 into OPERAND0. */
29220 void
29222 {
29226 /* C code for SSE variant we expand below.
29227 double xa = fabs (x), x2;
29228 if (!isless (xa, TWO52))
29229 return x;
29230 xa2 = xa + TWO52 - TWO52;
29231 Compensate:
29232 if (xa2 > xa)
29233 xa2 -= 1.0;
29234 x2 = copysign (xa2, x);
29235 return x2;
29236 */
29240 /* Temporary for holding the result, initialized to the input
29241 operand to ease control flow. */
29245 /* xa = abs (operand1) */
29248 /* if (!isless (xa, TWO52)) goto label; */
29251 /* res = xa + TWO52 - TWO52; */
29256 /* generate 1.0 */
29259 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29267 /* res = copysign (res, operand1) */
29274 }
29276 /* Expand SSE sequence for computing round from OPERAND1 storing
29277 into OPERAND0. */
29278 void
29280 {
29281 /* C code for the stuff we're doing below:
29282 double xa = fabs (x);
29283 if (!isless (xa, TWO52))
29284 return x;
29285 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29286 return copysign (xa, x);
29287 */
29293 /* Temporary for holding the result, initialized to the input
29294 operand to ease control flow. */
29302 /* load nextafter (0.5, 0.0) */
29307 /* xa = xa + 0.5 */
29311 /* xa = (double)(int64_t)xa */
29316 /* res = copysign (xa, operand1) */
29323 }
29324 \f
29326 /* Table of valid machine attributes. */
29328 {
29329 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29330 /* Stdcall attribute says callee is responsible for popping arguments
29331 if they are not variable. */
29333 /* Fastcall attribute says callee is responsible for popping arguments
29334 if they are not variable. */
29336 /* Thiscall attribute says callee is responsible for popping arguments
29337 if they are not variable. */
29339 /* Cdecl attribute says the callee is a normal C declaration */
29341 /* Regparm attribute specifies how many integer arguments are to be
29342 passed in registers. */
29344 /* Sseregparm attribute says we are using x86_64 calling conventions
29345 for FP arguments. */
29347 /* force_align_arg_pointer says this function realigns the stack at entry. */
29350 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29354 #endif
29357 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29358 SUBTARGET_ATTRIBUTE_TABLE,
29359 #endif
29360 /* ms_abi and sysv_abi calling convention function attributes. */
29364 /* End element. */
29366 };
29368 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29369 static int
29371 {
29373 {
29412 }
29413 }
29416 /* Implement targetm.vectorize.builtin_vec_perm. */
29418 static tree
29420 {
29428 {
29435 get_di:
29446 get_si:
29465 }
29472 }
29474 /* Return a vector mode with twice as many elements as VMODE. */
29475 /* ??? Consider moving this to a table generated by genmodes.c. */
29477 static enum machine_mode
29479 {
29481 {
29504 }
29505 }
29507 /* Construct (set target (vec_select op0 (parallel perm))) and
29508 return true if that's a valid instruction in the active ISA. */
29510 static bool
29512 {
29525 {
29528 }
29530 }
29532 /* Similar, but generate a vec_concat from op0 and op1 as well. */
29534 static bool
29537 {
29539 rtx x;
29544 }
29546 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29547 in terms of blendp[sd] / pblendw / pblendvb. */
29549 static bool
29551 {
29561 /* This is a blend, not a permute. Elements must stay in their
29562 respective lanes. */
29564 {
29568 }
29573 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
29574 decision should be extracted elsewhere, so that we only try that
29575 sequence once all budget==3 options have been tried. */
29577 /* For bytes, see if bytes move in pairs so we can use pblendw with
29578 an immediate argument, rather than pblendvb with a vector argument. */
29580 {
29586 {
29597 }
29598 }
29606 {
29630 do_subreg:
29639 }
29641 /* This matches five different patterns with the different modes. */
29647 }
29649 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29650 in terms of the variable form of vpermilps.
29652 Note that we will have already failed the immediate input vpermilps,
29653 which requires that the high and low part shuffle be identical; the
29654 variable form doesn't require that. */
29656 static bool
29658 {
29665 /* We can only permute within the 128-bit lane. */
29667 {
29671 }
29677 {
29680 /* Within each 128-bit lane, the elements of op0 are numbered
29681 from 0 and the elements of op1 are numbered from 4. */
29688 }
29695 }
29697 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29698 in terms of pshufb or vpperm. */
29700 static bool
29702 {
29718 {
29722 }
29731 else
29732 {
29735 }
29738 }
29740 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
29741 in a single instruction. */
29743 static bool
29745 {
29749 /* Check plain VEC_SELECT first, because AVX has instructions that could
29750 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
29751 input where SEL+CONCAT may not. */
29753 {
29762 /* There are plenty of patterns in sse.md that are written for
29763 SEL+CONCAT and are not replicated for a single op. Perhaps
29764 that should be changed, to avoid the nastiness here. */
29766 /* Recognize interleave style patterns, which means incrementing
29767 every other permutation operand. */
29769 {
29772 }
29776 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
29778 {
29780 {
29785 }
29789 }
29790 }
29792 /* Finally, try the fully general two operand permute. */
29796 /* Recognize interleave style patterns with reversed operands. */
29798 {
29800 {
29804 else
29807 }
29811 }
29813 /* Try the SSE4.1 blend variable merge instructions. */
29817 /* Try one of the AVX vpermil variable permutations. */
29821 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
29826 }
29828 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29829 in terms of a pair of pshuflw + pshufhw instructions. */
29831 static bool
29833 {
29841 /* The two permutations only operate in 64-bit lanes. */
29852 /* Emit the pshuflw. */
29859 /* Emit the pshufhw. */
29867 }
29869 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29870 the permutation using the SSSE3 palignr instruction. This succeeds
29871 when all of the elements in PERM fit within one vector and we merely
29872 need to shift them down so that a single vector permutation has a
29873 chance to succeed. */
29875 static bool
29877 {
29881 rtx shift;
29883 /* Even with AVX, palignr only operates on 128-bit vectors. */
29889 {
29895 }
29899 /* Given that we have SSSE3, we know we'll be able to implement the
29900 single operand permutation after the palignr with pshufb. */
29913 {
29918 }
29920 /* Test for the degenerate case where the alignment by itself
29921 produces the desired permutation. */
29929 }
29931 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29932 a two vector permutation into a single vector permutation by using
29933 an interleave operation to merge the vectors. */
29935 static bool
29937 {
29942 rtx seq;
29948 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
29949 lanes. We can use similar techniques with the vperm2f128 instruction,
29950 but it requires slightly different logic. */
29954 /* Examine from whence the elements come. */
29959 /* Split the two input vectors into 4 halves. */
29968 /* If the elements from the low halves use interleave low, and similarly
29969 for interleave high. If the elements are from mis-matched halves, we
29970 can use shufps for V4SF/V4SI or do a DImode shuffle. */
29972 {
29974 {
29979 }
29980 }
29982 {
29984 {
29989 }
29990 }
29992 {
29994 {
29999 }
30001 {
30006 }
30007 }
30009 {
30011 {
30016 }
30018 {
30023 }
30024 }
30025 else
30028 /* Use the remapping array set up above to move the elements from their
30029 swizzled locations into their final destinations. */
30032 {
30036 }
30041 /* Test if the final remap can be done with a single insn. For V4SFmode or
30042 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
30052 {
30056 }
30063 }
30065 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
30066 permutation with two pshufb insns and an ior. We should have already
30067 failed all two instruction sequences. */
30069 static bool
30071 {
30082 /* Generate two permutation masks. If the required element is within
30083 the given vector it is shuffled into the proper lane. If the required
30084 element is in the other vector, force a zero into the lane by setting
30085 bit 7 in the permutation mask. */
30088 {
30095 {
30098 }
30099 }
30119 }
30121 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
30122 and extract-odd permutations. */
30124 static bool
30126 {
30130 {
30135 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
30139 /* Now an unpck[lh]pd will produce the result required. */
30142 else
30148 {
30158 /* Shuffle within the 128-bit lanes to produce:
30159 { 0 2 1 3 4 6 5 7 } and { 8 a 9 b c e d f }. */
30163 /* Shuffle the lanes around to produce:
30164 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
30168 /* Now a vpermil2p will produce the result required. */
30169 /* ??? The vpermil2p requires a vector constant. Another option
30170 is a unpck[lh]ps to merge the two vectors to produce
30171 { 0 4 2 6 8 c a e } or { 1 5 3 7 9 d b f }. Then use another
30172 vpermilps to get the elements into the final order. */
30177 }
30184 /* These are always directly implementable by expand_vec_perm_1. */
30190 else
30191 {
30192 /* We need 2*log2(N)-1 operations to achieve odd/even
30193 with interleave. */
30202 else
30205 }
30211 else
30212 {
30224 else
30227 }
30232 }
30235 }
30237 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
30238 extract-even and extract-odd permutations. */
30240 static bool
30242 {
30254 }
30256 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
30257 permutations. We assume that expand_vec_perm_1 has already failed. */
30259 static bool
30261 {
30269 {
30272 /* These are special-cased in sse.md so that we can optionally
30273 use the vbroadcast instruction. They expand to two insns
30274 if the input happens to be in a register. */
30281 /* These are always implementable using standard shuffle patterns. */
30286 /* These can be implemented via interleave. We save one insn by
30287 stopping once we have promoted to V4SImode and then use pshufd. */
30288 do
30289 {
30293 {
30296 }
30302 }
30312 }
30313 }
30315 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
30316 broadcast permutations. */
30318 static bool
30320 {
30332 }
30334 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
30335 With all of the interface bits taken care of, perform the expansion
30336 in D and return true on success. */
30338 static bool
30340 {
30341 /* Try a single instruction expansion. */
30345 /* Try sequences of two instructions. */
30359 /* Try sequences of three instructions. */
30364 /* ??? Look for narrow permutations whose element orderings would
30365 allow the promotion to a wider mode. */
30367 /* ??? Look for sequences of interleave or a wider permute that place
30368 the data into the correct lanes for a half-vector shuffle like
30369 pshuf[lh]w or vpermilps. */
30371 /* ??? Look for sequences of interleave that produce the desired results.
30372 The combinatorics of punpck[lh] get pretty ugly... */
30378 }
30380 /* Extract the values from the vector CST into the permutation array in D.
30381 Return 0 on error, 1 if all values from the permutation come from the
30382 first vector, 2 if all values from the second vector, and 3 otherwise. */
30384 static int
30386 {
30392 {
30403 }
30406 /* For all elements from second vector, fold the elements to first. */
30412 }
30414 static rtx
30416 {
30430 {
30434 }
30437 {
30447 {
30453 }
30455 /* The elements of PERM do not suggest that only the first operand
30456 is used, but both operands are identical. Allow easier matching
30457 of the permutation by folding the permutation into the single
30458 input vector. */
30459 {
30464 }
30465 /* FALLTHRU */
30478 }
30484 /* For compiler generated permutations, we should never got here, because
30485 the compiler should also be checking the ok hook. But since this is a
30486 builtin the user has access too, so don't abort. */
30488 {
30511 }
30512 exit_error:
30514 }
30516 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
30518 static bool
30520 {
30529 /* Given sufficient ISA support we can just return true here
30530 for selected vector modes. */
30532 {
30533 /* All implementable with a single vpperm insn. */
30536 /* All implementable with 2 pshufb + 1 ior. */
30539 /* All implementable with shufpd or unpck[lh]pd. */
30542 }
30546 /* This hook is cannot be called in response to something that the
30547 user does (unlike the builtin expander) so we shouldn't ever see
30548 an error generated from the extract. */
30552 /* Implementable with shufps or pshufd. */
30556 /* Otherwise we have to go through the motions and see if we can
30557 figure out how to generate the requested permutation. */
30568 }
30570 void
30572 {
30586 /* We'll either be able to implement the permutation directly... */
30590 /* ... or we use the special-case patterns. */
30592 }
30593 \f
30594 /* This function returns the calling abi specific va_list type node.
30595 It returns the FNDECL specific va_list type. */
30597 static tree
30599 {
30606 else
30608 }
30610 /* Returns the canonical va_list type specified by TYPE. If there
30611 is no valid TYPE provided, it return NULL_TREE. */
30613 static tree
30615 {
30618 /* Resolve references and pointers to va_list type. */
30625 {
30630 {
30631 /* If va_list is an array type, the argument may have decayed
30632 to a pointer type, e.g. by being passed to another function.
30633 In that case, unwrap both types so that we can compare the
30634 underlying records. */
30637 {
30640 }
30641 }
30648 {
30649 /* If va_list is an array type, the argument may have decayed
30650 to a pointer type, e.g. by being passed to another function.
30651 In that case, unwrap both types so that we can compare the
30652 underlying records. */
30655 {
30658 }
30659 }
30666 {
30667 /* If va_list is an array type, the argument may have decayed
30668 to a pointer type, e.g. by being passed to another function.
30669 In that case, unwrap both types so that we can compare the
30670 underlying records. */
30673 {
30676 }
30677 }
30681 }
30683 }
30685 /* Iterate through the target-specific builtin types for va_list.
30686 IDX denotes the iterator, *PTREE is set to the result type of
30687 the va_list builtin, and *PNAME to its internal type.
30688 Returns zero if there is no element for this index, otherwise
30689 IDX should be increased upon the next call.
30690 Note, do not iterate a base builtin's name like __builtin_va_list.
30691 Used from c_common_nodes_and_builtins. */
30693 static int
30695 {
30697 {
30699 {
30712 }
30713 }
30716 }
30718 /* Initialize the GCC target structure. */
30719 #undef TARGET_RETURN_IN_MEMORY
30720 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30722 #undef TARGET_LEGITIMIZE_ADDRESS
30723 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30725 #undef TARGET_ATTRIBUTE_TABLE
30726 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30727 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30728 # undef TARGET_MERGE_DECL_ATTRIBUTES
30729 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30730 #endif
30732 #undef TARGET_COMP_TYPE_ATTRIBUTES
30733 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30735 #undef TARGET_INIT_BUILTINS
30736 #define TARGET_INIT_BUILTINS ix86_init_builtins
30737 #undef TARGET_BUILTIN_DECL
30738 #define TARGET_BUILTIN_DECL ix86_builtin_decl
30739 #undef TARGET_EXPAND_BUILTIN
30740 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30742 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30743 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30744 ix86_builtin_vectorized_function
30746 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30747 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30749 #undef TARGET_BUILTIN_RECIPROCAL
30750 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30752 #undef TARGET_ASM_FUNCTION_EPILOGUE
30753 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30755 #undef TARGET_ENCODE_SECTION_INFO
30756 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30757 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30758 #else
30759 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30760 #endif
30762 #undef TARGET_ASM_OPEN_PAREN
30764 #undef TARGET_ASM_CLOSE_PAREN
30767 #undef TARGET_ASM_BYTE_OP
30768 #define TARGET_ASM_BYTE_OP ASM_BYTE
30770 #undef TARGET_ASM_ALIGNED_HI_OP
30771 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30772 #undef TARGET_ASM_ALIGNED_SI_OP
30773 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30774 #ifdef ASM_QUAD
30775 #undef TARGET_ASM_ALIGNED_DI_OP
30776 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30777 #endif
30779 #undef TARGET_ASM_UNALIGNED_HI_OP
30780 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30781 #undef TARGET_ASM_UNALIGNED_SI_OP
30782 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30783 #undef TARGET_ASM_UNALIGNED_DI_OP
30784 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30786 #undef TARGET_PRINT_OPERAND
30787 #define TARGET_PRINT_OPERAND ix86_print_operand
30788 #undef TARGET_PRINT_OPERAND_ADDRESS
30789 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
30790 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
30791 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
30793 #undef TARGET_SCHED_ADJUST_COST
30794 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30795 #undef TARGET_SCHED_ISSUE_RATE
30796 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30797 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30798 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30799 ia32_multipass_dfa_lookahead
30801 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30802 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30804 #ifdef HAVE_AS_TLS
30805 #undef TARGET_HAVE_TLS
30806 #define TARGET_HAVE_TLS true
30807 #endif
30808 #undef TARGET_CANNOT_FORCE_CONST_MEM
30809 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30810 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30811 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30813 #undef TARGET_DELEGITIMIZE_ADDRESS
30814 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30816 #undef TARGET_MS_BITFIELD_LAYOUT_P
30817 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30819 #if TARGET_MACHO
30820 #undef TARGET_BINDS_LOCAL_P
30821 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30822 #endif
30823 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30824 #undef TARGET_BINDS_LOCAL_P
30825 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30826 #endif
30828 #undef TARGET_ASM_OUTPUT_MI_THUNK
30829 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30830 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30831 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30833 #undef TARGET_ASM_FILE_START
30834 #define TARGET_ASM_FILE_START x86_file_start
30836 #undef TARGET_DEFAULT_TARGET_FLAGS
30837 #define TARGET_DEFAULT_TARGET_FLAGS \
30838 (TARGET_DEFAULT \
30839 | TARGET_SUBTARGET_DEFAULT \
30840 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT \
30841 | MASK_FUSED_MADD)
30843 #undef TARGET_HANDLE_OPTION
30844 #define TARGET_HANDLE_OPTION ix86_handle_option
30846 #undef TARGET_REGISTER_MOVE_COST
30847 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
30848 #undef TARGET_MEMORY_MOVE_COST
30849 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
30850 #undef TARGET_RTX_COSTS
30851 #define TARGET_RTX_COSTS ix86_rtx_costs
30852 #undef TARGET_ADDRESS_COST
30853 #define TARGET_ADDRESS_COST ix86_address_cost
30855 #undef TARGET_FIXED_CONDITION_CODE_REGS
30856 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30857 #undef TARGET_CC_MODES_COMPATIBLE
30858 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30860 #undef TARGET_MACHINE_DEPENDENT_REORG
30861 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30863 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30864 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30866 #undef TARGET_BUILD_BUILTIN_VA_LIST
30867 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30869 #undef TARGET_ENUM_VA_LIST_P
30870 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
30872 #undef TARGET_FN_ABI_VA_LIST
30873 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30875 #undef TARGET_CANONICAL_VA_LIST_TYPE
30876 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30878 #undef TARGET_EXPAND_BUILTIN_VA_START
30879 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30881 #undef TARGET_MD_ASM_CLOBBERS
30882 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30884 #undef TARGET_PROMOTE_PROTOTYPES
30885 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30886 #undef TARGET_STRUCT_VALUE_RTX
30887 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30888 #undef TARGET_SETUP_INCOMING_VARARGS
30889 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30890 #undef TARGET_MUST_PASS_IN_STACK
30891 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30892 #undef TARGET_FUNCTION_ARG_ADVANCE
30893 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
30894 #undef TARGET_FUNCTION_ARG
30895 #define TARGET_FUNCTION_ARG ix86_function_arg
30896 #undef TARGET_PASS_BY_REFERENCE
30897 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30898 #undef TARGET_INTERNAL_ARG_POINTER
30899 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30900 #undef TARGET_UPDATE_STACK_BOUNDARY
30901 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30902 #undef TARGET_GET_DRAP_RTX
30903 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30904 #undef TARGET_STRICT_ARGUMENT_NAMING
30905 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30906 #undef TARGET_STATIC_CHAIN
30907 #define TARGET_STATIC_CHAIN ix86_static_chain
30908 #undef TARGET_TRAMPOLINE_INIT
30909 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
30910 #undef TARGET_RETURN_POPS_ARGS
30911 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
30913 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30914 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30916 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30917 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30919 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30920 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30922 #undef TARGET_C_MODE_FOR_SUFFIX
30923 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30925 #ifdef HAVE_AS_TLS
30926 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30927 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30928 #endif
30930 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30931 #undef TARGET_INSERT_ATTRIBUTES
30932 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30933 #endif
30935 #undef TARGET_MANGLE_TYPE
30936 #define TARGET_MANGLE_TYPE ix86_mangle_type
30938 #undef TARGET_STACK_PROTECT_FAIL
30939 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30941 #undef TARGET_FUNCTION_VALUE
30942 #define TARGET_FUNCTION_VALUE ix86_function_value
30944 #undef TARGET_FUNCTION_VALUE_REGNO_P
30945 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
30947 #undef TARGET_SECONDARY_RELOAD
30948 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30950 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30951 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
30952 ix86_builtin_vectorization_cost
30953 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
30954 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
30955 ix86_vectorize_builtin_vec_perm
30956 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
30957 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
30958 ix86_vectorize_builtin_vec_perm_ok
30960 #undef TARGET_SET_CURRENT_FUNCTION
30961 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30963 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30964 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30966 #undef TARGET_OPTION_SAVE
30967 #define TARGET_OPTION_SAVE ix86_function_specific_save
30969 #undef TARGET_OPTION_RESTORE
30970 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30972 #undef TARGET_OPTION_PRINT
30973 #define TARGET_OPTION_PRINT ix86_function_specific_print
30975 #undef TARGET_CAN_INLINE_P
30976 #define TARGET_CAN_INLINE_P ix86_can_inline_p
30978 #undef TARGET_EXPAND_TO_RTL_HOOK
30979 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30981 #undef TARGET_LEGITIMATE_ADDRESS_P
30982 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30984 #undef TARGET_IRA_COVER_CLASSES
30985 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
30987 #undef TARGET_FRAME_POINTER_REQUIRED
30988 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
30990 #undef TARGET_CAN_ELIMINATE
30991 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
30993 #undef TARGET_ASM_CODE_END
30994 #define TARGET_ASM_CODE_END ix86_code_end
30997 \f