Revise -mdisable-fpregs option and add new -msoft-mult option

[official-gcc.git] / gcc / config / rs6000 / rs6000-cpus.def

/* IBM RS/6000 CPU names..
   Copyright (C) 1991-2021 Free Software Foundation, Inc.
   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* ISA masks.  */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS           OPTION_MASK_MFCRF
#define ISA_2_2_MASKS           (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS           (ISA_2_2_MASKS | OPTION_MASK_FPRND)

  /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
     power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
     as optional.  Group masks by server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED  (ISA_2_4_MASKS                          \
                                 | OPTION_MASK_CMPB                     \
                                 | OPTION_MASK_RECIP_PRECISION          \
                                 | OPTION_MASK_PPC_GFXOPT               \
                                 | OPTION_MASK_PPC_GPOPT)

#define ISA_2_5_MASKS_SERVER    (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)

  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
     altivec is a win so enable it.  */
#define ISA_2_6_MASKS_EMBEDDED  (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER    (ISA_2_5_MASKS_SERVER                   \
                                 | OPTION_MASK_POPCNTD                  \
                                 | OPTION_MASK_ALTIVEC                  \
                                 | OPTION_MASK_VSX)

/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
   fusion here, instead set it in rs6000.c if we are tuning for a power8
   system.  */
#define ISA_2_7_MASKS_SERVER    (ISA_2_6_MASKS_SERVER                   \
                                 | OPTION_MASK_P8_VECTOR                \
                                 | OPTION_MASK_CRYPTO                   \
                                 | OPTION_MASK_DIRECT_MOVE              \
                                 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
                                 | OPTION_MASK_QUAD_MEMORY              \
                                 | OPTION_MASK_QUAD_MEMORY_ATOMIC)

/* ISA masks setting fusion options.  */
#define OTHER_FUSION_MASKS      (OPTION_MASK_P8_FUSION                  \
                                 | OPTION_MASK_P8_FUSION_SIGN)

/* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
   FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
#define ISA_3_0_MASKS_SERVER    ((ISA_2_7_MASKS_SERVER                  \
                                  | OPTION_MASK_ISEL                    \
                                  | OPTION_MASK_MODULO                  \
                                  | OPTION_MASK_P9_MINMAX               \
                                  | OPTION_MASK_P9_MISC                 \
                                  | OPTION_MASK_P9_VECTOR)              \
                                 & ~OTHER_FUSION_MASKS)

/* Support for the IEEE 128-bit floating point hardware requires a lot of the
   VSX instructions that are part of ISA 3.0.  */
#define ISA_3_0_MASKS_IEEE      (OPTION_MASK_VSX                        \
                                 | OPTION_MASK_P8_VECTOR                \
                                 | OPTION_MASK_P9_VECTOR)

/* Flags that need to be turned off if -mno-power10.  */
/* We comment out PCREL_OPT here to disable it by default because SPEC2017
   performance was degraded by it.  */
#define OTHER_POWER10_MASKS     (OPTION_MASK_MMA                        \
                                 | OPTION_MASK_PCREL                    \
                                 /* | OPTION_MASK_PCREL_OPT */          \
                                 | OPTION_MASK_PREFIXED)

#define ISA_3_1_MASKS_SERVER    (ISA_3_0_MASKS_SERVER                   \
                                 | OPTION_MASK_POWER10                  \
                                 | OTHER_POWER10_MASKS                  \
                                 | OPTION_MASK_P10_FUSION               \
                                 | OPTION_MASK_P10_FUSION_LD_CMPI       \
                                 | OPTION_MASK_P10_FUSION_2LOGICAL      \
                                 | OPTION_MASK_P10_FUSION_LOGADD        \
                                 | OPTION_MASK_P10_FUSION_ADDLOG        \
                                 | OPTION_MASK_P10_FUSION_2ADD          \
                                 | OPTION_MASK_P10_FUSION_2STORE)

/* Flags that need to be turned off if -mno-power9-vector.  */
#define OTHER_P9_VECTOR_MASKS   (OPTION_MASK_FLOAT128_HW                \
                                 | OPTION_MASK_P9_MINMAX)

/* Flags that need to be turned off if -mno-power8-vector.  */
#define OTHER_P8_VECTOR_MASKS   (OTHER_P9_VECTOR_MASKS                  \
                                 | OPTION_MASK_P9_VECTOR                \
                                 | OPTION_MASK_DIRECT_MOVE              \
                                 | OPTION_MASK_CRYPTO)

/* Flags that need to be turned off if -mno-vsx.  */
#define OTHER_VSX_VECTOR_MASKS  (OTHER_P8_VECTOR_MASKS                  \
                                 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
                                 | OPTION_MASK_FLOAT128_KEYWORD         \
                                 | OPTION_MASK_P8_VECTOR)

/* Flags that need to be turned off if -mno-altivec.  */
#define OTHER_ALTIVEC_MASKS     (OTHER_VSX_VECTOR_MASKS                 \
                                 | OPTION_MASK_VSX)

#define POWERPC_7400_MASK       (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

/* Deal with ports that do not have -mstrict-align.  */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
#define POWERPC_MASKS           (OPTION_MASK_ALTIVEC                    \
                                 | OPTION_MASK_CMPB                     \
                                 | OPTION_MASK_CRYPTO                   \
                                 | OPTION_MASK_DFP                      \
                                 | OPTION_MASK_DIRECT_MOVE              \
                                 | OPTION_MASK_DLMZB                    \
                                 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
                                 | OPTION_MASK_FLOAT128_HW              \
                                 | OPTION_MASK_FLOAT128_KEYWORD         \
                                 | OPTION_MASK_FPRND                    \
                                 | OPTION_MASK_POWER10                  \
                                 | OPTION_MASK_P10_FUSION               \
                                 | OPTION_MASK_P10_FUSION_LD_CMPI       \
                                 | OPTION_MASK_P10_FUSION_2LOGICAL      \
                                 | OPTION_MASK_P10_FUSION_LOGADD        \
                                 | OPTION_MASK_P10_FUSION_ADDLOG        \
                                 | OPTION_MASK_P10_FUSION_2ADD          \
                                 | OPTION_MASK_P10_FUSION_2STORE        \
                                 | OPTION_MASK_HTM                      \
                                 | OPTION_MASK_ISEL                     \
                                 | OPTION_MASK_MFCRF                    \
                                 | OPTION_MASK_MMA                      \
                                 | OPTION_MASK_MODULO                   \
                                 | OPTION_MASK_MULHW                    \
                                 | OPTION_MASK_NO_UPDATE                \
                                 | OPTION_MASK_P8_FUSION                \
                                 | OPTION_MASK_P8_VECTOR                \
                                 | OPTION_MASK_P9_MINMAX                \
                                 | OPTION_MASK_P9_MISC                  \
                                 | OPTION_MASK_P9_VECTOR                \
                                 | OPTION_MASK_PCREL                    \
                                 | OPTION_MASK_PCREL_OPT                \
                                 | OPTION_MASK_POPCNTB                  \
                                 | OPTION_MASK_POPCNTD                  \
                                 | OPTION_MASK_POWERPC64                \
                                 | OPTION_MASK_PPC_GFXOPT               \
                                 | OPTION_MASK_PPC_GPOPT                \
                                 | OPTION_MASK_PREFIXED                 \
                                 | OPTION_MASK_QUAD_MEMORY              \
                                 | OPTION_MASK_QUAD_MEMORY_ATOMIC       \
                                 | OPTION_MASK_RECIP_PRECISION          \
                                 | OPTION_MASK_SOFT_FLOAT               \
                                 | OPTION_MASK_STRICT_ALIGN_OPTIONAL    \
                                 | OPTION_MASK_VSX)

#endif

/* This table occasionally claims that a processor does not support a
   particular feature even though it does, but the feature is slower than the
   alternative.  Thus, it shouldn't be relied on as a complete description of
   the processor's support.

   Please keep this list in order, and don't forget to update the documentation
   in invoke.texi when adding a new processor or flag.

   Before including this file, define a macro:

   RS6000_CPU (NAME, CPU, FLAGS)

   where the arguments are the fields of struct rs6000_ptt.  */

RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
            MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
            | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
            MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
            | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
            MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
            | MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
            MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
            MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
            | MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
            POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
            POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
            POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
            | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
            | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
            | OPTION_MASK_HTM)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
            | OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
            | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)