1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 /* This file should be included last. */
86 #include "target-def.h"
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
93 systems will also set long double to be IEEE 128-bit. AIX and Darwin
94 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
95 those systems will not pick up this default. This needs to be after all
96 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
98 #ifndef TARGET_IEEEQUAD_DEFAULT
99 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
100 #define TARGET_IEEEQUAD_DEFAULT 1
102 #define TARGET_IEEEQUAD_DEFAULT 0
106 static pad_direction
rs6000_function_arg_padding (machine_mode
, const_tree
);
108 /* Structure used to define the rs6000 stack */
109 typedef struct rs6000_stack
{
110 int reload_completed
; /* stack info won't change from here on */
111 int first_gp_reg_save
; /* first callee saved GP register used */
112 int first_fp_reg_save
; /* first callee saved FP register used */
113 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
114 int lr_save_p
; /* true if the link reg needs to be saved */
115 int cr_save_p
; /* true if the CR reg needs to be saved */
116 unsigned int vrsave_mask
; /* mask of vec registers to save */
117 int push_p
; /* true if we need to allocate stack space */
118 int calls_p
; /* true if the function makes any calls */
119 int world_save_p
; /* true if we're saving *everything*:
120 r13-r31, cr, f14-f31, vrsave, v20-v31 */
121 enum rs6000_abi abi
; /* which ABI to use */
122 int gp_save_offset
; /* offset to save GP regs from initial SP */
123 int fp_save_offset
; /* offset to save FP regs from initial SP */
124 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
125 int lr_save_offset
; /* offset to save LR from initial SP */
126 int cr_save_offset
; /* offset to save CR from initial SP */
127 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
128 int varargs_save_offset
; /* offset to save the varargs registers */
129 int ehrd_offset
; /* offset to EH return data */
130 int ehcr_offset
; /* offset to EH CR field data */
131 int reg_size
; /* register size (4 or 8) */
132 HOST_WIDE_INT vars_size
; /* variable save area size */
133 int parm_size
; /* outgoing parameter size */
134 int save_size
; /* save area size */
135 int fixed_size
; /* fixed size of stack frame */
136 int gp_size
; /* size of saved GP registers */
137 int fp_size
; /* size of saved FP registers */
138 int altivec_size
; /* size of saved AltiVec registers */
139 int cr_size
; /* size to hold CR if not in fixed area */
140 int vrsave_size
; /* size to hold VRSAVE */
141 int altivec_padding_size
; /* size of altivec alignment padding */
142 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
146 /* A C structure for machine-specific, per-function data.
147 This is added to the cfun structure. */
148 typedef struct GTY(()) machine_function
150 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
151 int ra_needs_full_frame
;
152 /* Flags if __builtin_return_address (0) was used. */
154 /* Cache lr_save_p after expansion of builtin_eh_return. */
156 /* Whether we need to save the TOC to the reserved stack location in the
157 function prologue. */
158 bool save_toc_in_prologue
;
159 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
160 varargs save area. */
161 HOST_WIDE_INT varargs_save_offset
;
162 /* Alternative internal arg pointer for -fsplit-stack. */
163 rtx split_stack_arg_pointer
;
164 bool split_stack_argp_used
;
165 /* Flag if r2 setup is needed with ELFv2 ABI. */
166 bool r2_setup_needed
;
167 /* The number of components we use for separate shrink-wrapping. */
169 /* The components already handled by separate shrink-wrapping, which should
170 not be considered by the prologue and epilogue. */
171 bool gpr_is_wrapped_separately
[32];
172 bool fpr_is_wrapped_separately
[32];
173 bool lr_is_wrapped_separately
;
174 bool toc_is_wrapped_separately
;
177 /* Support targetm.vectorize.builtin_mask_for_load. */
178 static GTY(()) tree altivec_builtin_mask_for_load
;
180 /* Set to nonzero once AIX common-mode calls have been defined. */
181 static GTY(()) int common_mode_defined
;
183 /* Label number of label created for -mrelocatable, to call to so we can
184 get the address of the GOT section */
185 static int rs6000_pic_labelno
;
188 /* Counter for labels which are to be placed in .fixup. */
189 int fixuplabelno
= 0;
192 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
195 /* Specify the machine mode that pointers have. After generation of rtl, the
196 compiler makes no further distinction between pointers and any other objects
197 of this machine mode. */
198 scalar_int_mode rs6000_pmode
;
201 /* Note whether IEEE 128-bit floating point was passed or returned, either as
202 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
203 floating point. We changed the default C++ mangling for these types and we
204 may want to generate a weak alias of the old mangling (U10__float128) to the
205 new mangling (u9__ieee128). */
206 static bool rs6000_passes_ieee128
;
209 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
210 name used in current releases (i.e. u9__ieee128). */
211 static bool ieee128_mangling_gcc_8_1
;
213 /* Width in bits of a pointer. */
214 unsigned rs6000_pointer_size
;
216 #ifdef HAVE_AS_GNU_ATTRIBUTE
217 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
218 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
220 /* Flag whether floating point values have been passed/returned.
221 Note that this doesn't say whether fprs are used, since the
222 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
223 should be set for soft-float values passed in gprs and ieee128
224 values passed in vsx registers. */
225 static bool rs6000_passes_float
;
226 static bool rs6000_passes_long_double
;
227 /* Flag whether vector values have been passed/returned. */
228 static bool rs6000_passes_vector
;
229 /* Flag whether small (<= 8 byte) structures have been returned. */
230 static bool rs6000_returns_struct
;
233 /* Value is TRUE if register/mode pair is acceptable. */
234 static bool rs6000_hard_regno_mode_ok_p
235 [NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
237 /* Maximum number of registers needed for a given register class and mode. */
238 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
240 /* How many registers are needed for a given register and mode. */
241 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
243 /* Map register number to register class. */
244 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
246 static int dbg_cost_ctrl
;
248 /* Built in types. */
249 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
250 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
252 /* Flag to say the TOC is initialized */
253 int toc_initialized
, need_toc_init
;
254 char toc_label_name
[10];
256 /* Cached value of rs6000_variable_issue. This is cached in
257 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
258 static short cached_can_issue_more
;
260 static GTY(()) section
*read_only_data_section
;
261 static GTY(()) section
*private_data_section
;
262 static GTY(()) section
*tls_data_section
;
263 static GTY(()) section
*tls_private_data_section
;
264 static GTY(()) section
*read_only_private_data_section
;
265 static GTY(()) section
*sdata2_section
;
266 static GTY(()) section
*toc_section
;
268 struct builtin_description
270 const HOST_WIDE_INT mask
;
271 const enum insn_code icode
;
272 const char *const name
;
273 const enum rs6000_builtins code
;
276 /* Describe the vector unit used for modes. */
277 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
278 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
280 /* Register classes for various constraints that are based on the target
282 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
284 /* Describe the alignment of a vector. */
285 int rs6000_vector_align
[NUM_MACHINE_MODES
];
287 /* Map selected modes to types for builtins. */
288 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
290 /* What modes to automatically generate reciprocal divide estimate (fre) and
291 reciprocal sqrt (frsqrte) for. */
292 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
294 /* Masks to determine which reciprocal esitmate instructions to generate
296 enum rs6000_recip_mask
{
297 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
298 RECIP_DF_DIV
= 0x002,
299 RECIP_V4SF_DIV
= 0x004,
300 RECIP_V2DF_DIV
= 0x008,
302 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
303 RECIP_DF_RSQRT
= 0x020,
304 RECIP_V4SF_RSQRT
= 0x040,
305 RECIP_V2DF_RSQRT
= 0x080,
307 /* Various combination of flags for -mrecip=xxx. */
309 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
310 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
311 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
313 RECIP_HIGH_PRECISION
= RECIP_ALL
,
315 /* On low precision machines like the power5, don't enable double precision
316 reciprocal square root estimate, since it isn't accurate enough. */
317 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
320 /* -mrecip options. */
323 const char *string
; /* option name */
324 unsigned int mask
; /* mask bits to set */
325 } recip_options
[] = {
326 { "all", RECIP_ALL
},
327 { "none", RECIP_NONE
},
328 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
330 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
331 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
332 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
333 | RECIP_V2DF_RSQRT
) },
334 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
335 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
338 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
344 { "power9", PPC_PLATFORM_POWER9
},
345 { "power8", PPC_PLATFORM_POWER8
},
346 { "power7", PPC_PLATFORM_POWER7
},
347 { "power6x", PPC_PLATFORM_POWER6X
},
348 { "power6", PPC_PLATFORM_POWER6
},
349 { "power5+", PPC_PLATFORM_POWER5_PLUS
},
350 { "power5", PPC_PLATFORM_POWER5
},
351 { "ppc970", PPC_PLATFORM_PPC970
},
352 { "power4", PPC_PLATFORM_POWER4
},
353 { "ppca2", PPC_PLATFORM_PPCA2
},
354 { "ppc476", PPC_PLATFORM_PPC476
},
355 { "ppc464", PPC_PLATFORM_PPC464
},
356 { "ppc440", PPC_PLATFORM_PPC440
},
357 { "ppc405", PPC_PLATFORM_PPC405
},
358 { "ppc-cell-be", PPC_PLATFORM_CELL_BE
}
361 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
367 } cpu_supports_info
[] = {
368 /* AT_HWCAP masks. */
369 { "4xxmac", PPC_FEATURE_HAS_4xxMAC
, 0 },
370 { "altivec", PPC_FEATURE_HAS_ALTIVEC
, 0 },
371 { "arch_2_05", PPC_FEATURE_ARCH_2_05
, 0 },
372 { "arch_2_06", PPC_FEATURE_ARCH_2_06
, 0 },
373 { "archpmu", PPC_FEATURE_PERFMON_COMPAT
, 0 },
374 { "booke", PPC_FEATURE_BOOKE
, 0 },
375 { "cellbe", PPC_FEATURE_CELL_BE
, 0 },
376 { "dfp", PPC_FEATURE_HAS_DFP
, 0 },
377 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE
, 0 },
378 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE
, 0 },
379 { "fpu", PPC_FEATURE_HAS_FPU
, 0 },
380 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP
, 0 },
381 { "mmu", PPC_FEATURE_HAS_MMU
, 0 },
382 { "notb", PPC_FEATURE_NO_TB
, 0 },
383 { "pa6t", PPC_FEATURE_PA6T
, 0 },
384 { "power4", PPC_FEATURE_POWER4
, 0 },
385 { "power5", PPC_FEATURE_POWER5
, 0 },
386 { "power5+", PPC_FEATURE_POWER5_PLUS
, 0 },
387 { "power6x", PPC_FEATURE_POWER6_EXT
, 0 },
388 { "ppc32", PPC_FEATURE_32
, 0 },
389 { "ppc601", PPC_FEATURE_601_INSTR
, 0 },
390 { "ppc64", PPC_FEATURE_64
, 0 },
391 { "ppcle", PPC_FEATURE_PPC_LE
, 0 },
392 { "smt", PPC_FEATURE_SMT
, 0 },
393 { "spe", PPC_FEATURE_HAS_SPE
, 0 },
394 { "true_le", PPC_FEATURE_TRUE_LE
, 0 },
395 { "ucache", PPC_FEATURE_UNIFIED_CACHE
, 0 },
396 { "vsx", PPC_FEATURE_HAS_VSX
, 0 },
398 /* AT_HWCAP2 masks. */
399 { "arch_2_07", PPC_FEATURE2_ARCH_2_07
, 1 },
400 { "dscr", PPC_FEATURE2_HAS_DSCR
, 1 },
401 { "ebb", PPC_FEATURE2_HAS_EBB
, 1 },
402 { "htm", PPC_FEATURE2_HAS_HTM
, 1 },
403 { "htm-nosc", PPC_FEATURE2_HTM_NOSC
, 1 },
404 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND
, 1 },
405 { "isel", PPC_FEATURE2_HAS_ISEL
, 1 },
406 { "tar", PPC_FEATURE2_HAS_TAR
, 1 },
407 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO
, 1 },
408 { "arch_3_00", PPC_FEATURE2_ARCH_3_00
, 1 },
409 { "ieee128", PPC_FEATURE2_HAS_IEEE128
, 1 },
410 { "darn", PPC_FEATURE2_DARN
, 1 },
411 { "scv", PPC_FEATURE2_SCV
, 1 }
414 /* On PowerPC, we have a limited number of target clones that we care about
415 which means we can use an array to hold the options, rather than having more
416 elaborate data structures to identify each possible variation. Order the
417 clones from the default to the highest ISA. */
419 CLONE_DEFAULT
= 0, /* default clone. */
420 CLONE_ISA_2_05
, /* ISA 2.05 (power6). */
421 CLONE_ISA_2_06
, /* ISA 2.06 (power7). */
422 CLONE_ISA_2_07
, /* ISA 2.07 (power8). */
423 CLONE_ISA_3_00
, /* ISA 3.00 (power9). */
427 /* Map compiler ISA bits into HWCAP names. */
429 HOST_WIDE_INT isa_mask
; /* rs6000_isa mask */
430 const char *name
; /* name to use in __builtin_cpu_supports. */
433 static const struct clone_map rs6000_clone_map
[CLONE_MAX
] = {
434 { 0, "" }, /* Default options. */
435 { OPTION_MASK_CMPB
, "arch_2_05" }, /* ISA 2.05 (power6). */
436 { OPTION_MASK_POPCNTD
, "arch_2_06" }, /* ISA 2.06 (power7). */
437 { OPTION_MASK_P8_VECTOR
, "arch_2_07" }, /* ISA 2.07 (power8). */
438 { OPTION_MASK_P9_VECTOR
, "arch_3_00" }, /* ISA 3.00 (power9). */
442 /* Newer LIBCs explicitly export this symbol to declare that they provide
443 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
444 reference to this symbol whenever we expand a CPU builtin, so that
445 we never link against an old LIBC. */
446 const char *tcb_verification_symbol
= "__parse_hwcap_and_convert_at_platform";
448 /* True if we have expanded a CPU builtin. */
451 /* Pointer to function (in rs6000-c.c) that can define or undefine target
452 macros that have changed. Languages that don't support the preprocessor
453 don't link in rs6000-c.c, so we can't call it directly. */
454 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
456 /* Simplfy register classes into simpler classifications. We assume
457 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
458 check for standard register classes (gpr/floating/altivec/vsx) and
459 floating/vector classes (float/altivec/vsx). */
461 enum rs6000_reg_type
{
472 /* Map register class to register type. */
473 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
475 /* First/last register type for the 'normal' register types (i.e. general
476 purpose, floating point, altivec, and VSX registers). */
477 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
479 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
482 /* Register classes we care about in secondary reload or go if legitimate
483 address. We only need to worry about GPR, FPR, and Altivec registers here,
484 along an ANY field that is the OR of the 3 register classes. */
486 enum rs6000_reload_reg_type
{
487 RELOAD_REG_GPR
, /* General purpose registers. */
488 RELOAD_REG_FPR
, /* Traditional floating point regs. */
489 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
490 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
494 /* For setting up register classes, loop through the 3 register classes mapping
495 into real registers, and skip the ANY class, which is just an OR of the
497 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
498 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
500 /* Map reload register type to a register in the register class. */
501 struct reload_reg_map_type
{
502 const char *name
; /* Register class name. */
503 int reg
; /* Register in the register class. */
506 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
507 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
508 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
509 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
510 { "Any", -1 }, /* RELOAD_REG_ANY. */
513 /* Mask bits for each register class, indexed per mode. Historically the
514 compiler has been more restrictive which types can do PRE_MODIFY instead of
515 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
516 typedef unsigned char addr_mask_type
;
518 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
519 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
520 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
521 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
522 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
523 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
524 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
525 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
527 /* Register type masks based on the type, of valid addressing modes. */
528 struct rs6000_reg_addr
{
529 enum insn_code reload_load
; /* INSN to reload for loading. */
530 enum insn_code reload_store
; /* INSN to reload for storing. */
531 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
532 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
533 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
534 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
535 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
538 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
540 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
542 mode_supports_pre_incdec_p (machine_mode mode
)
544 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
548 /* Helper function to say whether a mode supports PRE_MODIFY. */
550 mode_supports_pre_modify_p (machine_mode mode
)
552 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
556 /* Return true if we have D-form addressing in altivec registers. */
558 mode_supports_vmx_dform (machine_mode mode
)
560 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_OFFSET
) != 0);
563 /* Return true if we have D-form addressing in VSX registers. This addressing
564 is more limited than normal d-form addressing in that the offset must be
565 aligned on a 16-byte boundary. */
567 mode_supports_dq_form (machine_mode mode
)
569 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_QUAD_OFFSET
)
573 /* Given that there exists at least one variable that is set (produced)
574 by OUT_INSN and read (consumed) by IN_INSN, return true iff
575 IN_INSN represents one or more memory store operations and none of
576 the variables set by OUT_INSN is used by IN_INSN as the address of a
577 store operation. If either IN_INSN or OUT_INSN does not represent
578 a "single" RTL SET expression (as loosely defined by the
579 implementation of the single_set function) or a PARALLEL with only
580 SETs, CLOBBERs, and USEs inside, this function returns false.
582 This rs6000-specific version of store_data_bypass_p checks for
583 certain conditions that result in assertion failures (and internal
584 compiler errors) in the generic store_data_bypass_p function and
585 returns false rather than calling store_data_bypass_p if one of the
586 problematic conditions is detected. */
589 rs6000_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
596 in_set
= single_set (in_insn
);
599 if (MEM_P (SET_DEST (in_set
)))
601 out_set
= single_set (out_insn
);
604 out_pat
= PATTERN (out_insn
);
605 if (GET_CODE (out_pat
) == PARALLEL
)
607 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
609 out_exp
= XVECEXP (out_pat
, 0, i
);
610 if ((GET_CODE (out_exp
) == CLOBBER
)
611 || (GET_CODE (out_exp
) == USE
))
613 else if (GET_CODE (out_exp
) != SET
)
622 in_pat
= PATTERN (in_insn
);
623 if (GET_CODE (in_pat
) != PARALLEL
)
626 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
628 in_exp
= XVECEXP (in_pat
, 0, i
);
629 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
631 else if (GET_CODE (in_exp
) != SET
)
634 if (MEM_P (SET_DEST (in_exp
)))
636 out_set
= single_set (out_insn
);
639 out_pat
= PATTERN (out_insn
);
640 if (GET_CODE (out_pat
) != PARALLEL
)
642 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
644 out_exp
= XVECEXP (out_pat
, 0, j
);
645 if ((GET_CODE (out_exp
) == CLOBBER
)
646 || (GET_CODE (out_exp
) == USE
))
648 else if (GET_CODE (out_exp
) != SET
)
655 return store_data_bypass_p (out_insn
, in_insn
);
659 /* Processor costs (relative to an add) */
661 const struct processor_costs
*rs6000_cost
;
663 /* Instruction size costs on 32bit processors. */
665 struct processor_costs size32_cost
= {
666 COSTS_N_INSNS (1), /* mulsi */
667 COSTS_N_INSNS (1), /* mulsi_const */
668 COSTS_N_INSNS (1), /* mulsi_const9 */
669 COSTS_N_INSNS (1), /* muldi */
670 COSTS_N_INSNS (1), /* divsi */
671 COSTS_N_INSNS (1), /* divdi */
672 COSTS_N_INSNS (1), /* fp */
673 COSTS_N_INSNS (1), /* dmul */
674 COSTS_N_INSNS (1), /* sdiv */
675 COSTS_N_INSNS (1), /* ddiv */
676 32, /* cache line size */
680 0, /* SF->DF convert */
683 /* Instruction size costs on 64bit processors. */
685 struct processor_costs size64_cost
= {
686 COSTS_N_INSNS (1), /* mulsi */
687 COSTS_N_INSNS (1), /* mulsi_const */
688 COSTS_N_INSNS (1), /* mulsi_const9 */
689 COSTS_N_INSNS (1), /* muldi */
690 COSTS_N_INSNS (1), /* divsi */
691 COSTS_N_INSNS (1), /* divdi */
692 COSTS_N_INSNS (1), /* fp */
693 COSTS_N_INSNS (1), /* dmul */
694 COSTS_N_INSNS (1), /* sdiv */
695 COSTS_N_INSNS (1), /* ddiv */
696 128, /* cache line size */
700 0, /* SF->DF convert */
703 /* Instruction costs on RS64A processors. */
705 struct processor_costs rs64a_cost
= {
706 COSTS_N_INSNS (20), /* mulsi */
707 COSTS_N_INSNS (12), /* mulsi_const */
708 COSTS_N_INSNS (8), /* mulsi_const9 */
709 COSTS_N_INSNS (34), /* muldi */
710 COSTS_N_INSNS (65), /* divsi */
711 COSTS_N_INSNS (67), /* divdi */
712 COSTS_N_INSNS (4), /* fp */
713 COSTS_N_INSNS (4), /* dmul */
714 COSTS_N_INSNS (31), /* sdiv */
715 COSTS_N_INSNS (31), /* ddiv */
716 128, /* cache line size */
720 0, /* SF->DF convert */
723 /* Instruction costs on MPCCORE processors. */
725 struct processor_costs mpccore_cost
= {
726 COSTS_N_INSNS (2), /* mulsi */
727 COSTS_N_INSNS (2), /* mulsi_const */
728 COSTS_N_INSNS (2), /* mulsi_const9 */
729 COSTS_N_INSNS (2), /* muldi */
730 COSTS_N_INSNS (6), /* divsi */
731 COSTS_N_INSNS (6), /* divdi */
732 COSTS_N_INSNS (4), /* fp */
733 COSTS_N_INSNS (5), /* dmul */
734 COSTS_N_INSNS (10), /* sdiv */
735 COSTS_N_INSNS (17), /* ddiv */
736 32, /* cache line size */
740 0, /* SF->DF convert */
743 /* Instruction costs on PPC403 processors. */
745 struct processor_costs ppc403_cost
= {
746 COSTS_N_INSNS (4), /* mulsi */
747 COSTS_N_INSNS (4), /* mulsi_const */
748 COSTS_N_INSNS (4), /* mulsi_const9 */
749 COSTS_N_INSNS (4), /* muldi */
750 COSTS_N_INSNS (33), /* divsi */
751 COSTS_N_INSNS (33), /* divdi */
752 COSTS_N_INSNS (11), /* fp */
753 COSTS_N_INSNS (11), /* dmul */
754 COSTS_N_INSNS (11), /* sdiv */
755 COSTS_N_INSNS (11), /* ddiv */
756 32, /* cache line size */
760 0, /* SF->DF convert */
763 /* Instruction costs on PPC405 processors. */
765 struct processor_costs ppc405_cost
= {
766 COSTS_N_INSNS (5), /* mulsi */
767 COSTS_N_INSNS (4), /* mulsi_const */
768 COSTS_N_INSNS (3), /* mulsi_const9 */
769 COSTS_N_INSNS (5), /* muldi */
770 COSTS_N_INSNS (35), /* divsi */
771 COSTS_N_INSNS (35), /* divdi */
772 COSTS_N_INSNS (11), /* fp */
773 COSTS_N_INSNS (11), /* dmul */
774 COSTS_N_INSNS (11), /* sdiv */
775 COSTS_N_INSNS (11), /* ddiv */
776 32, /* cache line size */
780 0, /* SF->DF convert */
783 /* Instruction costs on PPC440 processors. */
785 struct processor_costs ppc440_cost
= {
786 COSTS_N_INSNS (3), /* mulsi */
787 COSTS_N_INSNS (2), /* mulsi_const */
788 COSTS_N_INSNS (2), /* mulsi_const9 */
789 COSTS_N_INSNS (3), /* muldi */
790 COSTS_N_INSNS (34), /* divsi */
791 COSTS_N_INSNS (34), /* divdi */
792 COSTS_N_INSNS (5), /* fp */
793 COSTS_N_INSNS (5), /* dmul */
794 COSTS_N_INSNS (19), /* sdiv */
795 COSTS_N_INSNS (33), /* ddiv */
796 32, /* cache line size */
800 0, /* SF->DF convert */
803 /* Instruction costs on PPC476 processors. */
805 struct processor_costs ppc476_cost
= {
806 COSTS_N_INSNS (4), /* mulsi */
807 COSTS_N_INSNS (4), /* mulsi_const */
808 COSTS_N_INSNS (4), /* mulsi_const9 */
809 COSTS_N_INSNS (4), /* muldi */
810 COSTS_N_INSNS (11), /* divsi */
811 COSTS_N_INSNS (11), /* divdi */
812 COSTS_N_INSNS (6), /* fp */
813 COSTS_N_INSNS (6), /* dmul */
814 COSTS_N_INSNS (19), /* sdiv */
815 COSTS_N_INSNS (33), /* ddiv */
816 32, /* l1 cache line size */
820 0, /* SF->DF convert */
823 /* Instruction costs on PPC601 processors. */
825 struct processor_costs ppc601_cost
= {
826 COSTS_N_INSNS (5), /* mulsi */
827 COSTS_N_INSNS (5), /* mulsi_const */
828 COSTS_N_INSNS (5), /* mulsi_const9 */
829 COSTS_N_INSNS (5), /* muldi */
830 COSTS_N_INSNS (36), /* divsi */
831 COSTS_N_INSNS (36), /* divdi */
832 COSTS_N_INSNS (4), /* fp */
833 COSTS_N_INSNS (5), /* dmul */
834 COSTS_N_INSNS (17), /* sdiv */
835 COSTS_N_INSNS (31), /* ddiv */
836 32, /* cache line size */
840 0, /* SF->DF convert */
843 /* Instruction costs on PPC603 processors. */
845 struct processor_costs ppc603_cost
= {
846 COSTS_N_INSNS (5), /* mulsi */
847 COSTS_N_INSNS (3), /* mulsi_const */
848 COSTS_N_INSNS (2), /* mulsi_const9 */
849 COSTS_N_INSNS (5), /* muldi */
850 COSTS_N_INSNS (37), /* divsi */
851 COSTS_N_INSNS (37), /* divdi */
852 COSTS_N_INSNS (3), /* fp */
853 COSTS_N_INSNS (4), /* dmul */
854 COSTS_N_INSNS (18), /* sdiv */
855 COSTS_N_INSNS (33), /* ddiv */
856 32, /* cache line size */
860 0, /* SF->DF convert */
863 /* Instruction costs on PPC604 processors. */
865 struct processor_costs ppc604_cost
= {
866 COSTS_N_INSNS (4), /* mulsi */
867 COSTS_N_INSNS (4), /* mulsi_const */
868 COSTS_N_INSNS (4), /* mulsi_const9 */
869 COSTS_N_INSNS (4), /* muldi */
870 COSTS_N_INSNS (20), /* divsi */
871 COSTS_N_INSNS (20), /* divdi */
872 COSTS_N_INSNS (3), /* fp */
873 COSTS_N_INSNS (3), /* dmul */
874 COSTS_N_INSNS (18), /* sdiv */
875 COSTS_N_INSNS (32), /* ddiv */
876 32, /* cache line size */
880 0, /* SF->DF convert */
883 /* Instruction costs on PPC604e processors. */
885 struct processor_costs ppc604e_cost
= {
886 COSTS_N_INSNS (2), /* mulsi */
887 COSTS_N_INSNS (2), /* mulsi_const */
888 COSTS_N_INSNS (2), /* mulsi_const9 */
889 COSTS_N_INSNS (2), /* muldi */
890 COSTS_N_INSNS (20), /* divsi */
891 COSTS_N_INSNS (20), /* divdi */
892 COSTS_N_INSNS (3), /* fp */
893 COSTS_N_INSNS (3), /* dmul */
894 COSTS_N_INSNS (18), /* sdiv */
895 COSTS_N_INSNS (32), /* ddiv */
896 32, /* cache line size */
900 0, /* SF->DF convert */
903 /* Instruction costs on PPC620 processors. */
905 struct processor_costs ppc620_cost
= {
906 COSTS_N_INSNS (5), /* mulsi */
907 COSTS_N_INSNS (4), /* mulsi_const */
908 COSTS_N_INSNS (3), /* mulsi_const9 */
909 COSTS_N_INSNS (7), /* muldi */
910 COSTS_N_INSNS (21), /* divsi */
911 COSTS_N_INSNS (37), /* divdi */
912 COSTS_N_INSNS (3), /* fp */
913 COSTS_N_INSNS (3), /* dmul */
914 COSTS_N_INSNS (18), /* sdiv */
915 COSTS_N_INSNS (32), /* ddiv */
916 128, /* cache line size */
920 0, /* SF->DF convert */
923 /* Instruction costs on PPC630 processors. */
925 struct processor_costs ppc630_cost
= {
926 COSTS_N_INSNS (5), /* mulsi */
927 COSTS_N_INSNS (4), /* mulsi_const */
928 COSTS_N_INSNS (3), /* mulsi_const9 */
929 COSTS_N_INSNS (7), /* muldi */
930 COSTS_N_INSNS (21), /* divsi */
931 COSTS_N_INSNS (37), /* divdi */
932 COSTS_N_INSNS (3), /* fp */
933 COSTS_N_INSNS (3), /* dmul */
934 COSTS_N_INSNS (17), /* sdiv */
935 COSTS_N_INSNS (21), /* ddiv */
936 128, /* cache line size */
940 0, /* SF->DF convert */
943 /* Instruction costs on Cell processor. */
944 /* COSTS_N_INSNS (1) ~ one add. */
946 struct processor_costs ppccell_cost
= {
947 COSTS_N_INSNS (9/2)+2, /* mulsi */
948 COSTS_N_INSNS (6/2), /* mulsi_const */
949 COSTS_N_INSNS (6/2), /* mulsi_const9 */
950 COSTS_N_INSNS (15/2)+2, /* muldi */
951 COSTS_N_INSNS (38/2), /* divsi */
952 COSTS_N_INSNS (70/2), /* divdi */
953 COSTS_N_INSNS (10/2), /* fp */
954 COSTS_N_INSNS (10/2), /* dmul */
955 COSTS_N_INSNS (74/2), /* sdiv */
956 COSTS_N_INSNS (74/2), /* ddiv */
957 128, /* cache line size */
961 0, /* SF->DF convert */
964 /* Instruction costs on PPC750 and PPC7400 processors. */
966 struct processor_costs ppc750_cost
= {
967 COSTS_N_INSNS (5), /* mulsi */
968 COSTS_N_INSNS (3), /* mulsi_const */
969 COSTS_N_INSNS (2), /* mulsi_const9 */
970 COSTS_N_INSNS (5), /* muldi */
971 COSTS_N_INSNS (17), /* divsi */
972 COSTS_N_INSNS (17), /* divdi */
973 COSTS_N_INSNS (3), /* fp */
974 COSTS_N_INSNS (3), /* dmul */
975 COSTS_N_INSNS (17), /* sdiv */
976 COSTS_N_INSNS (31), /* ddiv */
977 32, /* cache line size */
981 0, /* SF->DF convert */
984 /* Instruction costs on PPC7450 processors. */
986 struct processor_costs ppc7450_cost
= {
987 COSTS_N_INSNS (4), /* mulsi */
988 COSTS_N_INSNS (3), /* mulsi_const */
989 COSTS_N_INSNS (3), /* mulsi_const9 */
990 COSTS_N_INSNS (4), /* muldi */
991 COSTS_N_INSNS (23), /* divsi */
992 COSTS_N_INSNS (23), /* divdi */
993 COSTS_N_INSNS (5), /* fp */
994 COSTS_N_INSNS (5), /* dmul */
995 COSTS_N_INSNS (21), /* sdiv */
996 COSTS_N_INSNS (35), /* ddiv */
997 32, /* cache line size */
1001 0, /* SF->DF convert */
1004 /* Instruction costs on PPC8540 processors. */
1006 struct processor_costs ppc8540_cost
= {
1007 COSTS_N_INSNS (4), /* mulsi */
1008 COSTS_N_INSNS (4), /* mulsi_const */
1009 COSTS_N_INSNS (4), /* mulsi_const9 */
1010 COSTS_N_INSNS (4), /* muldi */
1011 COSTS_N_INSNS (19), /* divsi */
1012 COSTS_N_INSNS (19), /* divdi */
1013 COSTS_N_INSNS (4), /* fp */
1014 COSTS_N_INSNS (4), /* dmul */
1015 COSTS_N_INSNS (29), /* sdiv */
1016 COSTS_N_INSNS (29), /* ddiv */
1017 32, /* cache line size */
1020 1, /* prefetch streams /*/
1021 0, /* SF->DF convert */
1024 /* Instruction costs on E300C2 and E300C3 cores. */
1026 struct processor_costs ppce300c2c3_cost
= {
1027 COSTS_N_INSNS (4), /* mulsi */
1028 COSTS_N_INSNS (4), /* mulsi_const */
1029 COSTS_N_INSNS (4), /* mulsi_const9 */
1030 COSTS_N_INSNS (4), /* muldi */
1031 COSTS_N_INSNS (19), /* divsi */
1032 COSTS_N_INSNS (19), /* divdi */
1033 COSTS_N_INSNS (3), /* fp */
1034 COSTS_N_INSNS (4), /* dmul */
1035 COSTS_N_INSNS (18), /* sdiv */
1036 COSTS_N_INSNS (33), /* ddiv */
1040 1, /* prefetch streams /*/
1041 0, /* SF->DF convert */
1044 /* Instruction costs on PPCE500MC processors. */
1046 struct processor_costs ppce500mc_cost
= {
1047 COSTS_N_INSNS (4), /* mulsi */
1048 COSTS_N_INSNS (4), /* mulsi_const */
1049 COSTS_N_INSNS (4), /* mulsi_const9 */
1050 COSTS_N_INSNS (4), /* muldi */
1051 COSTS_N_INSNS (14), /* divsi */
1052 COSTS_N_INSNS (14), /* divdi */
1053 COSTS_N_INSNS (8), /* fp */
1054 COSTS_N_INSNS (10), /* dmul */
1055 COSTS_N_INSNS (36), /* sdiv */
1056 COSTS_N_INSNS (66), /* ddiv */
1057 64, /* cache line size */
1060 1, /* prefetch streams /*/
1061 0, /* SF->DF convert */
1064 /* Instruction costs on PPCE500MC64 processors. */
1066 struct processor_costs ppce500mc64_cost
= {
1067 COSTS_N_INSNS (4), /* mulsi */
1068 COSTS_N_INSNS (4), /* mulsi_const */
1069 COSTS_N_INSNS (4), /* mulsi_const9 */
1070 COSTS_N_INSNS (4), /* muldi */
1071 COSTS_N_INSNS (14), /* divsi */
1072 COSTS_N_INSNS (14), /* divdi */
1073 COSTS_N_INSNS (4), /* fp */
1074 COSTS_N_INSNS (10), /* dmul */
1075 COSTS_N_INSNS (36), /* sdiv */
1076 COSTS_N_INSNS (66), /* ddiv */
1077 64, /* cache line size */
1080 1, /* prefetch streams /*/
1081 0, /* SF->DF convert */
1084 /* Instruction costs on PPCE5500 processors. */
1086 struct processor_costs ppce5500_cost
= {
1087 COSTS_N_INSNS (5), /* mulsi */
1088 COSTS_N_INSNS (5), /* mulsi_const */
1089 COSTS_N_INSNS (4), /* mulsi_const9 */
1090 COSTS_N_INSNS (5), /* muldi */
1091 COSTS_N_INSNS (14), /* divsi */
1092 COSTS_N_INSNS (14), /* divdi */
1093 COSTS_N_INSNS (7), /* fp */
1094 COSTS_N_INSNS (10), /* dmul */
1095 COSTS_N_INSNS (36), /* sdiv */
1096 COSTS_N_INSNS (66), /* ddiv */
1097 64, /* cache line size */
1100 1, /* prefetch streams /*/
1101 0, /* SF->DF convert */
1104 /* Instruction costs on PPCE6500 processors. */
1106 struct processor_costs ppce6500_cost
= {
1107 COSTS_N_INSNS (5), /* mulsi */
1108 COSTS_N_INSNS (5), /* mulsi_const */
1109 COSTS_N_INSNS (4), /* mulsi_const9 */
1110 COSTS_N_INSNS (5), /* muldi */
1111 COSTS_N_INSNS (14), /* divsi */
1112 COSTS_N_INSNS (14), /* divdi */
1113 COSTS_N_INSNS (7), /* fp */
1114 COSTS_N_INSNS (10), /* dmul */
1115 COSTS_N_INSNS (36), /* sdiv */
1116 COSTS_N_INSNS (66), /* ddiv */
1117 64, /* cache line size */
1120 1, /* prefetch streams /*/
1121 0, /* SF->DF convert */
1124 /* Instruction costs on AppliedMicro Titan processors. */
1126 struct processor_costs titan_cost
= {
1127 COSTS_N_INSNS (5), /* mulsi */
1128 COSTS_N_INSNS (5), /* mulsi_const */
1129 COSTS_N_INSNS (5), /* mulsi_const9 */
1130 COSTS_N_INSNS (5), /* muldi */
1131 COSTS_N_INSNS (18), /* divsi */
1132 COSTS_N_INSNS (18), /* divdi */
1133 COSTS_N_INSNS (10), /* fp */
1134 COSTS_N_INSNS (10), /* dmul */
1135 COSTS_N_INSNS (46), /* sdiv */
1136 COSTS_N_INSNS (72), /* ddiv */
1137 32, /* cache line size */
1140 1, /* prefetch streams /*/
1141 0, /* SF->DF convert */
1144 /* Instruction costs on POWER4 and POWER5 processors. */
1146 struct processor_costs power4_cost
= {
1147 COSTS_N_INSNS (3), /* mulsi */
1148 COSTS_N_INSNS (2), /* mulsi_const */
1149 COSTS_N_INSNS (2), /* mulsi_const9 */
1150 COSTS_N_INSNS (4), /* muldi */
1151 COSTS_N_INSNS (18), /* divsi */
1152 COSTS_N_INSNS (34), /* divdi */
1153 COSTS_N_INSNS (3), /* fp */
1154 COSTS_N_INSNS (3), /* dmul */
1155 COSTS_N_INSNS (17), /* sdiv */
1156 COSTS_N_INSNS (17), /* ddiv */
1157 128, /* cache line size */
1159 1024, /* l2 cache */
1160 8, /* prefetch streams /*/
1161 0, /* SF->DF convert */
1164 /* Instruction costs on POWER6 processors. */
1166 struct processor_costs power6_cost
= {
1167 COSTS_N_INSNS (8), /* mulsi */
1168 COSTS_N_INSNS (8), /* mulsi_const */
1169 COSTS_N_INSNS (8), /* mulsi_const9 */
1170 COSTS_N_INSNS (8), /* muldi */
1171 COSTS_N_INSNS (22), /* divsi */
1172 COSTS_N_INSNS (28), /* divdi */
1173 COSTS_N_INSNS (3), /* fp */
1174 COSTS_N_INSNS (3), /* dmul */
1175 COSTS_N_INSNS (13), /* sdiv */
1176 COSTS_N_INSNS (16), /* ddiv */
1177 128, /* cache line size */
1179 2048, /* l2 cache */
1180 16, /* prefetch streams */
1181 0, /* SF->DF convert */
1184 /* Instruction costs on POWER7 processors. */
1186 struct processor_costs power7_cost
= {
1187 COSTS_N_INSNS (2), /* mulsi */
1188 COSTS_N_INSNS (2), /* mulsi_const */
1189 COSTS_N_INSNS (2), /* mulsi_const9 */
1190 COSTS_N_INSNS (2), /* muldi */
1191 COSTS_N_INSNS (18), /* divsi */
1192 COSTS_N_INSNS (34), /* divdi */
1193 COSTS_N_INSNS (3), /* fp */
1194 COSTS_N_INSNS (3), /* dmul */
1195 COSTS_N_INSNS (13), /* sdiv */
1196 COSTS_N_INSNS (16), /* ddiv */
1197 128, /* cache line size */
1200 12, /* prefetch streams */
1201 COSTS_N_INSNS (3), /* SF->DF convert */
1204 /* Instruction costs on POWER8 processors. */
1206 struct processor_costs power8_cost
= {
1207 COSTS_N_INSNS (3), /* mulsi */
1208 COSTS_N_INSNS (3), /* mulsi_const */
1209 COSTS_N_INSNS (3), /* mulsi_const9 */
1210 COSTS_N_INSNS (3), /* muldi */
1211 COSTS_N_INSNS (19), /* divsi */
1212 COSTS_N_INSNS (35), /* divdi */
1213 COSTS_N_INSNS (3), /* fp */
1214 COSTS_N_INSNS (3), /* dmul */
1215 COSTS_N_INSNS (14), /* sdiv */
1216 COSTS_N_INSNS (17), /* ddiv */
1217 128, /* cache line size */
1220 12, /* prefetch streams */
1221 COSTS_N_INSNS (3), /* SF->DF convert */
1224 /* Instruction costs on POWER9 processors. */
1226 struct processor_costs power9_cost
= {
1227 COSTS_N_INSNS (3), /* mulsi */
1228 COSTS_N_INSNS (3), /* mulsi_const */
1229 COSTS_N_INSNS (3), /* mulsi_const9 */
1230 COSTS_N_INSNS (3), /* muldi */
1231 COSTS_N_INSNS (8), /* divsi */
1232 COSTS_N_INSNS (12), /* divdi */
1233 COSTS_N_INSNS (3), /* fp */
1234 COSTS_N_INSNS (3), /* dmul */
1235 COSTS_N_INSNS (13), /* sdiv */
1236 COSTS_N_INSNS (18), /* ddiv */
1237 128, /* cache line size */
1240 8, /* prefetch streams */
1241 COSTS_N_INSNS (3), /* SF->DF convert */
1244 /* Instruction costs on POWER A2 processors. */
1246 struct processor_costs ppca2_cost
= {
1247 COSTS_N_INSNS (16), /* mulsi */
1248 COSTS_N_INSNS (16), /* mulsi_const */
1249 COSTS_N_INSNS (16), /* mulsi_const9 */
1250 COSTS_N_INSNS (16), /* muldi */
1251 COSTS_N_INSNS (22), /* divsi */
1252 COSTS_N_INSNS (28), /* divdi */
1253 COSTS_N_INSNS (3), /* fp */
1254 COSTS_N_INSNS (3), /* dmul */
1255 COSTS_N_INSNS (59), /* sdiv */
1256 COSTS_N_INSNS (72), /* ddiv */
1259 2048, /* l2 cache */
1260 16, /* prefetch streams */
1261 0, /* SF->DF convert */
1265 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1266 #undef RS6000_BUILTIN_0
1267 #undef RS6000_BUILTIN_1
1268 #undef RS6000_BUILTIN_2
1269 #undef RS6000_BUILTIN_3
1270 #undef RS6000_BUILTIN_A
1271 #undef RS6000_BUILTIN_D
1272 #undef RS6000_BUILTIN_H
1273 #undef RS6000_BUILTIN_P
1274 #undef RS6000_BUILTIN_X
1276 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1277 { NAME, ICODE, MASK, ATTR },
1279 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1280 { NAME, ICODE, MASK, ATTR },
1282 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1283 { NAME, ICODE, MASK, ATTR },
1285 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1286 { NAME, ICODE, MASK, ATTR },
1288 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1289 { NAME, ICODE, MASK, ATTR },
1291 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1292 { NAME, ICODE, MASK, ATTR },
1294 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1295 { NAME, ICODE, MASK, ATTR },
1297 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1298 { NAME, ICODE, MASK, ATTR },
1300 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1301 { NAME, ICODE, MASK, ATTR },
1303 struct rs6000_builtin_info_type
{
1305 const enum insn_code icode
;
1306 const HOST_WIDE_INT mask
;
1307 const unsigned attr
;
1310 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1312 #include "rs6000-builtin.def"
1315 #undef RS6000_BUILTIN_0
1316 #undef RS6000_BUILTIN_1
1317 #undef RS6000_BUILTIN_2
1318 #undef RS6000_BUILTIN_3
1319 #undef RS6000_BUILTIN_A
1320 #undef RS6000_BUILTIN_D
1321 #undef RS6000_BUILTIN_H
1322 #undef RS6000_BUILTIN_P
1323 #undef RS6000_BUILTIN_X
1325 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1326 static tree (*rs6000_veclib_handler
) (combined_fn
, tree
, tree
);
1329 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1330 static struct machine_function
* rs6000_init_machine_status (void);
1331 static int rs6000_ra_ever_killed (void);
1332 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1333 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1334 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1335 static tree
rs6000_builtin_vectorized_libmass (combined_fn
, tree
, tree
);
1336 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1337 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1338 static bool rs6000_debug_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
1339 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1341 static int rs6000_debug_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
1343 static bool is_microcoded_insn (rtx_insn
*);
1344 static bool is_nonpipeline_insn (rtx_insn
*);
1345 static bool is_cracked_insn (rtx_insn
*);
1346 static bool is_load_insn (rtx
, rtx
*);
1347 static bool is_store_insn (rtx
, rtx
*);
1348 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1349 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1350 static bool insn_must_be_first_in_group (rtx_insn
*);
1351 static bool insn_must_be_last_in_group (rtx_insn
*);
1352 static void altivec_init_builtins (void);
1353 static tree
builtin_function_type (machine_mode
, machine_mode
,
1354 machine_mode
, machine_mode
,
1355 enum rs6000_builtins
, const char *name
);
1356 static void rs6000_common_init_builtins (void);
1357 static void htm_init_builtins (void);
1358 static rs6000_stack_t
*rs6000_stack_info (void);
1359 static void is_altivec_return_reg (rtx
, void *);
1360 int easy_vector_constant (rtx
, machine_mode
);
1361 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1362 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1363 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1366 static void macho_branch_islands (void);
1368 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1370 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1372 static bool rs6000_mode_dependent_address (const_rtx
);
1373 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1374 static bool rs6000_offsettable_memref_p (rtx
, machine_mode
, bool);
1375 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1377 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1380 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1381 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1383 static bool rs6000_debug_secondary_memory_needed (machine_mode
,
1386 static bool rs6000_debug_can_change_mode_class (machine_mode
,
1389 static bool rs6000_save_toc_in_prologue_p (void);
1390 static rtx
rs6000_internal_arg_pointer (void);
1392 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1394 = rs6000_legitimize_reload_address
;
1396 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1397 = rs6000_mode_dependent_address
;
1399 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1401 = rs6000_secondary_reload_class
;
1403 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1404 = rs6000_preferred_reload_class
;
1406 const int INSN_NOT_AVAILABLE
= -1;
1408 static void rs6000_print_isa_options (FILE *, int, const char *,
1410 static void rs6000_print_builtin_options (FILE *, int, const char *,
1412 static HOST_WIDE_INT
rs6000_disable_incompatible_switches (void);
1414 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1415 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1416 enum rs6000_reg_type
,
1418 secondary_reload_info
*,
1420 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1421 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused
));
1422 static tree
rs6000_fold_builtin (tree
, int, tree
*, bool);
1424 /* Hash table stuff for keeping track of TOC entries. */
1426 struct GTY((for_user
)) toc_hash_struct
1428 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1429 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1431 machine_mode key_mode
;
1435 struct toc_hasher
: ggc_ptr_hash
<toc_hash_struct
>
1437 static hashval_t
hash (toc_hash_struct
*);
1438 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1441 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1443 /* Hash table to keep track of the argument types for builtin functions. */
1445 struct GTY((for_user
)) builtin_hash_struct
1448 machine_mode mode
[4]; /* return value + 3 arguments. */
1449 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1452 struct builtin_hasher
: ggc_ptr_hash
<builtin_hash_struct
>
1454 static hashval_t
hash (builtin_hash_struct
*);
1455 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1458 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1461 /* Default register names. */
1462 char rs6000_reg_names
[][8] =
1464 "0", "1", "2", "3", "4", "5", "6", "7",
1465 "8", "9", "10", "11", "12", "13", "14", "15",
1466 "16", "17", "18", "19", "20", "21", "22", "23",
1467 "24", "25", "26", "27", "28", "29", "30", "31",
1468 "0", "1", "2", "3", "4", "5", "6", "7",
1469 "8", "9", "10", "11", "12", "13", "14", "15",
1470 "16", "17", "18", "19", "20", "21", "22", "23",
1471 "24", "25", "26", "27", "28", "29", "30", "31",
1472 "mq", "lr", "ctr","ap",
1473 "0", "1", "2", "3", "4", "5", "6", "7",
1475 /* AltiVec registers. */
1476 "0", "1", "2", "3", "4", "5", "6", "7",
1477 "8", "9", "10", "11", "12", "13", "14", "15",
1478 "16", "17", "18", "19", "20", "21", "22", "23",
1479 "24", "25", "26", "27", "28", "29", "30", "31",
1481 /* Soft frame pointer. */
1483 /* HTM SPR registers. */
1484 "tfhar", "tfiar", "texasr"
1487 #ifdef TARGET_REGNAMES
1488 static const char alt_reg_names
[][8] =
1490 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1491 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1492 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1493 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1494 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1495 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1496 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1497 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1498 "mq", "lr", "ctr", "ap",
1499 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1501 /* AltiVec registers. */
1502 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1503 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1504 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1505 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1507 /* Soft frame pointer. */
1509 /* HTM SPR registers. */
1510 "tfhar", "tfiar", "texasr"
1514 /* Table of valid machine attributes. */
1516 static const struct attribute_spec rs6000_attribute_table
[] =
1518 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1519 affects_type_identity, handler, exclude } */
1520 { "altivec", 1, 1, false, true, false, false,
1521 rs6000_handle_altivec_attribute
, NULL
},
1522 { "longcall", 0, 0, false, true, true, false,
1523 rs6000_handle_longcall_attribute
, NULL
},
1524 { "shortcall", 0, 0, false, true, true, false,
1525 rs6000_handle_longcall_attribute
, NULL
},
1526 { "ms_struct", 0, 0, false, false, false, false,
1527 rs6000_handle_struct_attribute
, NULL
},
1528 { "gcc_struct", 0, 0, false, false, false, false,
1529 rs6000_handle_struct_attribute
, NULL
},
1530 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1531 SUBTARGET_ATTRIBUTE_TABLE
,
1533 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
1536 #ifndef TARGET_PROFILE_KERNEL
1537 #define TARGET_PROFILE_KERNEL 0
1540 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1541 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1543 /* Initialize the GCC target structure. */
1544 #undef TARGET_ATTRIBUTE_TABLE
1545 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1546 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1547 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1548 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1549 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1551 #undef TARGET_ASM_ALIGNED_DI_OP
1552 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1554 /* Default unaligned ops are only provided for ELF. Find the ops needed
1555 for non-ELF systems. */
1556 #ifndef OBJECT_FORMAT_ELF
1558 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1560 #undef TARGET_ASM_UNALIGNED_HI_OP
1561 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1562 #undef TARGET_ASM_UNALIGNED_SI_OP
1563 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1564 #undef TARGET_ASM_UNALIGNED_DI_OP
1565 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1568 #undef TARGET_ASM_UNALIGNED_HI_OP
1569 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1570 #undef TARGET_ASM_UNALIGNED_SI_OP
1571 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1572 #undef TARGET_ASM_UNALIGNED_DI_OP
1573 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1574 #undef TARGET_ASM_ALIGNED_DI_OP
1575 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1579 /* This hook deals with fixups for relocatable code and DI-mode objects
1581 #undef TARGET_ASM_INTEGER
1582 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1584 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1585 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1586 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1589 #undef TARGET_SET_UP_BY_PROLOGUE
1590 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1592 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1593 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1594 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1595 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1596 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1597 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1598 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1599 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1600 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1601 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1602 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1603 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1605 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1606 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1608 #undef TARGET_INTERNAL_ARG_POINTER
1609 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1611 #undef TARGET_HAVE_TLS
1612 #define TARGET_HAVE_TLS HAVE_AS_TLS
1614 #undef TARGET_CANNOT_FORCE_CONST_MEM
1615 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1617 #undef TARGET_DELEGITIMIZE_ADDRESS
1618 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1620 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1621 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1623 #undef TARGET_LEGITIMATE_COMBINED_INSN
1624 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1626 #undef TARGET_ASM_FUNCTION_PROLOGUE
1627 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1628 #undef TARGET_ASM_FUNCTION_EPILOGUE
1629 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1631 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1632 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1634 #undef TARGET_LEGITIMIZE_ADDRESS
1635 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1637 #undef TARGET_SCHED_VARIABLE_ISSUE
1638 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1640 #undef TARGET_SCHED_ISSUE_RATE
1641 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1642 #undef TARGET_SCHED_ADJUST_COST
1643 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1644 #undef TARGET_SCHED_ADJUST_PRIORITY
1645 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1646 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1647 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1648 #undef TARGET_SCHED_INIT
1649 #define TARGET_SCHED_INIT rs6000_sched_init
1650 #undef TARGET_SCHED_FINISH
1651 #define TARGET_SCHED_FINISH rs6000_sched_finish
1652 #undef TARGET_SCHED_REORDER
1653 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1654 #undef TARGET_SCHED_REORDER2
1655 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1657 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1658 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1660 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1661 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1663 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1664 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1665 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1666 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1667 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1668 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1669 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1670 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1672 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1673 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1675 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1676 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1677 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1678 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1679 rs6000_builtin_support_vector_misalignment
1680 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1681 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1682 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1683 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1684 rs6000_builtin_vectorization_cost
1685 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1686 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1687 rs6000_preferred_simd_mode
1688 #undef TARGET_VECTORIZE_INIT_COST
1689 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1690 #undef TARGET_VECTORIZE_ADD_STMT_COST
1691 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1692 #undef TARGET_VECTORIZE_FINISH_COST
1693 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1694 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1695 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1697 #undef TARGET_INIT_BUILTINS
1698 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1699 #undef TARGET_BUILTIN_DECL
1700 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1702 #undef TARGET_FOLD_BUILTIN
1703 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1704 #undef TARGET_GIMPLE_FOLD_BUILTIN
1705 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1707 #undef TARGET_EXPAND_BUILTIN
1708 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1710 #undef TARGET_MANGLE_TYPE
1711 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1713 #undef TARGET_INIT_LIBFUNCS
1714 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1717 #undef TARGET_BINDS_LOCAL_P
1718 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1721 #undef TARGET_MS_BITFIELD_LAYOUT_P
1722 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1724 #undef TARGET_ASM_OUTPUT_MI_THUNK
1725 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1727 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1728 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1730 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1731 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1733 #undef TARGET_REGISTER_MOVE_COST
1734 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1735 #undef TARGET_MEMORY_MOVE_COST
1736 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1737 #undef TARGET_CANNOT_COPY_INSN_P
1738 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1739 #undef TARGET_RTX_COSTS
1740 #define TARGET_RTX_COSTS rs6000_rtx_costs
1741 #undef TARGET_ADDRESS_COST
1742 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1743 #undef TARGET_INSN_COST
1744 #define TARGET_INSN_COST rs6000_insn_cost
1746 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1747 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1749 #undef TARGET_PROMOTE_FUNCTION_MODE
1750 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1752 #undef TARGET_RETURN_IN_MEMORY
1753 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1755 #undef TARGET_RETURN_IN_MSB
1756 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1758 #undef TARGET_SETUP_INCOMING_VARARGS
1759 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1761 /* Always strict argument naming on rs6000. */
1762 #undef TARGET_STRICT_ARGUMENT_NAMING
1763 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1765 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1766 #undef TARGET_SPLIT_COMPLEX_ARG
1767 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1768 #undef TARGET_MUST_PASS_IN_STACK
1769 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1770 #undef TARGET_PASS_BY_REFERENCE
1771 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1772 #undef TARGET_ARG_PARTIAL_BYTES
1773 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1774 #undef TARGET_FUNCTION_ARG_ADVANCE
1775 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1776 #undef TARGET_FUNCTION_ARG
1777 #define TARGET_FUNCTION_ARG rs6000_function_arg
1778 #undef TARGET_FUNCTION_ARG_PADDING
1779 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1780 #undef TARGET_FUNCTION_ARG_BOUNDARY
1781 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1783 #undef TARGET_BUILD_BUILTIN_VA_LIST
1784 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1786 #undef TARGET_EXPAND_BUILTIN_VA_START
1787 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1789 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1790 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1792 #undef TARGET_EH_RETURN_FILTER_MODE
1793 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1795 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1796 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1798 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1799 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1801 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1802 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1804 #undef TARGET_FLOATN_MODE
1805 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1807 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1808 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1810 #undef TARGET_MD_ASM_ADJUST
1811 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1813 #undef TARGET_OPTION_OVERRIDE
1814 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1816 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1817 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1818 rs6000_builtin_vectorized_function
1820 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1821 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1822 rs6000_builtin_md_vectorized_function
1824 #undef TARGET_STACK_PROTECT_GUARD
1825 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1828 #undef TARGET_STACK_PROTECT_FAIL
1829 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1833 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1834 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1837 /* Use a 32-bit anchor range. This leads to sequences like:
1839 addis tmp,anchor,high
1842 where tmp itself acts as an anchor, and can be shared between
1843 accesses to the same 64k page. */
1844 #undef TARGET_MIN_ANCHOR_OFFSET
1845 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1846 #undef TARGET_MAX_ANCHOR_OFFSET
1847 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1848 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1849 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1850 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1851 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1853 #undef TARGET_BUILTIN_RECIPROCAL
1854 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1856 #undef TARGET_SECONDARY_RELOAD
1857 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED
1859 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1860 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1861 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1863 #undef TARGET_LEGITIMATE_ADDRESS_P
1864 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1866 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1867 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1869 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1870 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1872 #undef TARGET_CAN_ELIMINATE
1873 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1875 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1876 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1878 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1879 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1881 #undef TARGET_TRAMPOLINE_INIT
1882 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1884 #undef TARGET_FUNCTION_VALUE
1885 #define TARGET_FUNCTION_VALUE rs6000_function_value
1887 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1888 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1890 #undef TARGET_OPTION_SAVE
1891 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1893 #undef TARGET_OPTION_RESTORE
1894 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1896 #undef TARGET_OPTION_PRINT
1897 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1899 #undef TARGET_CAN_INLINE_P
1900 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1902 #undef TARGET_SET_CURRENT_FUNCTION
1903 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1905 #undef TARGET_LEGITIMATE_CONSTANT_P
1906 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1908 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1909 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1911 #undef TARGET_CAN_USE_DOLOOP_P
1912 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1914 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1915 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1917 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1918 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1919 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1920 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1921 #undef TARGET_UNWIND_WORD_MODE
1922 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1924 #undef TARGET_OFFLOAD_OPTIONS
1925 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1927 #undef TARGET_C_MODE_FOR_SUFFIX
1928 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1930 #undef TARGET_INVALID_BINARY_OP
1931 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1933 #undef TARGET_OPTAB_SUPPORTED_P
1934 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1936 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1937 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1939 #undef TARGET_COMPARE_VERSION_PRIORITY
1940 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1942 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1943 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1944 rs6000_generate_version_dispatcher_body
1946 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1947 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1948 rs6000_get_function_versions_dispatcher
1950 #undef TARGET_OPTION_FUNCTION_VERSIONS
1951 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1953 #undef TARGET_HARD_REGNO_NREGS
1954 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1955 #undef TARGET_HARD_REGNO_MODE_OK
1956 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1958 #undef TARGET_MODES_TIEABLE_P
1959 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1961 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1962 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1963 rs6000_hard_regno_call_part_clobbered
1965 #undef TARGET_SLOW_UNALIGNED_ACCESS
1966 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1968 #undef TARGET_CAN_CHANGE_MODE_CLASS
1969 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1971 #undef TARGET_CONSTANT_ALIGNMENT
1972 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1974 #undef TARGET_STARTING_FRAME_OFFSET
1975 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1977 #if TARGET_ELF && RS6000_WEAK
1978 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1979 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1982 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1983 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1985 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1986 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1989 /* Processor table. */
1992 const char *const name
; /* Canonical processor name. */
1993 const enum processor_type processor
; /* Processor type enum value. */
1994 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1997 static struct rs6000_ptt
const processor_target_table
[] =
1999 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
2000 #include "rs6000-cpus.def"
2004 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2008 rs6000_cpu_name_lookup (const char *name
)
2014 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2015 if (! strcmp (name
, processor_target_table
[i
].name
))
2023 /* Return number of consecutive hard regs needed starting at reg REGNO
2024 to hold something of mode MODE.
2025 This is ordinarily the length in words of a value of mode MODE
2026 but can be less for certain modes in special long registers.
2028 POWER and PowerPC GPRs hold 32 bits worth;
2029 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2032 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
2034 unsigned HOST_WIDE_INT reg_size
;
2036 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2037 128-bit floating point that can go in vector registers, which has VSX
2038 memory addressing. */
2039 if (FP_REGNO_P (regno
))
2040 reg_size
= (VECTOR_MEM_VSX_P (mode
) || FLOAT128_VECTOR_P (mode
)
2041 ? UNITS_PER_VSX_WORD
2042 : UNITS_PER_FP_WORD
);
2044 else if (ALTIVEC_REGNO_P (regno
))
2045 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2048 reg_size
= UNITS_PER_WORD
;
2050 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
2053 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2056 rs6000_hard_regno_mode_ok_uncached (int regno
, machine_mode mode
)
2058 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
2060 if (COMPLEX_MODE_P (mode
))
2061 mode
= GET_MODE_INNER (mode
);
2063 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2064 register combinations, and use PTImode where we need to deal with quad
2065 word memory operations. Don't allow quad words in the argument or frame
2066 pointer registers, just registers 0..31. */
2067 if (mode
== PTImode
)
2068 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2069 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2070 && ((regno
& 1) == 0));
2072 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2073 implementations. Don't allow an item to be split between a FP register
2074 and an Altivec register. Allow TImode in all VSX registers if the user
2076 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
2077 && (VECTOR_MEM_VSX_P (mode
)
2078 || FLOAT128_VECTOR_P (mode
)
2079 || reg_addr
[mode
].scalar_in_vmx_p
2081 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
2083 if (FP_REGNO_P (regno
))
2084 return FP_REGNO_P (last_regno
);
2086 if (ALTIVEC_REGNO_P (regno
))
2088 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
2091 return ALTIVEC_REGNO_P (last_regno
);
2095 /* The GPRs can hold any mode, but values bigger than one register
2096 cannot go past R31. */
2097 if (INT_REGNO_P (regno
))
2098 return INT_REGNO_P (last_regno
);
2100 /* The float registers (except for VSX vector modes) can only hold floating
2101 modes and DImode. */
2102 if (FP_REGNO_P (regno
))
2104 if (FLOAT128_VECTOR_P (mode
))
2107 if (SCALAR_FLOAT_MODE_P (mode
)
2108 && (mode
!= TDmode
|| (regno
% 2) == 0)
2109 && FP_REGNO_P (last_regno
))
2112 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2114 if(GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
2117 if (TARGET_P8_VECTOR
&& (mode
== SImode
))
2120 if (TARGET_P9_VECTOR
&& (mode
== QImode
|| mode
== HImode
))
2127 /* The CR register can only hold CC modes. */
2128 if (CR_REGNO_P (regno
))
2129 return GET_MODE_CLASS (mode
) == MODE_CC
;
2131 if (CA_REGNO_P (regno
))
2132 return mode
== Pmode
|| mode
== SImode
;
2134 /* AltiVec only in AldyVec registers. */
2135 if (ALTIVEC_REGNO_P (regno
))
2136 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
2137 || mode
== V1TImode
);
2139 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2140 and it must be able to fit within the register set. */
2142 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
2145 /* Implement TARGET_HARD_REGNO_NREGS. */
2148 rs6000_hard_regno_nregs_hook (unsigned int regno
, machine_mode mode
)
2150 return rs6000_hard_regno_nregs
[mode
][regno
];
2153 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2156 rs6000_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2158 return rs6000_hard_regno_mode_ok_p
[mode
][regno
];
2161 /* Implement TARGET_MODES_TIEABLE_P.
2163 PTImode cannot tie with other modes because PTImode is restricted to even
2164 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2167 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2168 128-bit floating point on VSX systems ties with other vectors. */
2171 rs6000_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2173 if (mode1
== PTImode
)
2174 return mode2
== PTImode
;
2175 if (mode2
== PTImode
)
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1
))
2179 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2
);
2180 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2
))
2183 if (SCALAR_FLOAT_MODE_P (mode1
))
2184 return SCALAR_FLOAT_MODE_P (mode2
);
2185 if (SCALAR_FLOAT_MODE_P (mode2
))
2188 if (GET_MODE_CLASS (mode1
) == MODE_CC
)
2189 return GET_MODE_CLASS (mode2
) == MODE_CC
;
2190 if (GET_MODE_CLASS (mode2
) == MODE_CC
)
2196 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2199 rs6000_hard_regno_call_part_clobbered (unsigned int regno
, machine_mode mode
)
2203 && GET_MODE_SIZE (mode
) > 4
2204 && INT_REGNO_P (regno
))
2208 && FP_REGNO_P (regno
)
2209 && GET_MODE_SIZE (mode
) > 8
2210 && !FLOAT128_2REG_P (mode
))
2216 /* Print interesting facts about registers. */
2218 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
2222 for (r
= first_regno
; r
<= last_regno
; ++r
)
2224 const char *comma
= "";
2227 if (first_regno
== last_regno
)
2228 fprintf (stderr
, "%s:\t", reg_name
);
2230 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
2233 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2234 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
2238 fprintf (stderr
, ",\n\t");
2243 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
2244 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
2245 rs6000_hard_regno_nregs
[m
][r
]);
2247 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
2252 if (call_used_regs
[r
])
2256 fprintf (stderr
, ",\n\t");
2261 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
2269 fprintf (stderr
, ",\n\t");
2274 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
2280 fprintf (stderr
, ",\n\t");
2284 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
2285 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
2290 fprintf (stderr
, ",\n\t");
2294 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
2299 rs6000_debug_vector_unit (enum rs6000_vector v
)
2305 case VECTOR_NONE
: ret
= "none"; break;
2306 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
2307 case VECTOR_VSX
: ret
= "vsx"; break;
2308 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
2309 default: ret
= "unknown"; break;
2315 /* Inner function printing just the address mask for a particular reload
2317 DEBUG_FUNCTION
char *
2318 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
2323 if ((mask
& RELOAD_REG_VALID
) != 0)
2325 else if (keep_spaces
)
2328 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
2330 else if (keep_spaces
)
2333 if ((mask
& RELOAD_REG_INDEXED
) != 0)
2335 else if (keep_spaces
)
2338 if ((mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
2340 else if ((mask
& RELOAD_REG_OFFSET
) != 0)
2342 else if (keep_spaces
)
2345 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2347 else if (keep_spaces
)
2350 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2352 else if (keep_spaces
)
2355 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2357 else if (keep_spaces
)
2365 /* Print the address masks in a human readble fashion. */
2367 rs6000_debug_print_mode (ssize_t m
)
2372 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2373 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2374 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2375 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2377 if ((reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2378 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
2380 fprintf (stderr
, "%*s Reload=%c%c", spaces
, "",
2381 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2382 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
2386 spaces
+= sizeof (" Reload=sl") - 1;
2388 if (reg_addr
[m
].scalar_in_vmx_p
)
2390 fprintf (stderr
, "%*s Upper=y", spaces
, "");
2394 spaces
+= sizeof (" Upper=y") - 1;
2396 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2397 || rs6000_vector_mem
[m
] != VECTOR_NONE
)
2399 fprintf (stderr
, "%*s vector: arith=%-10s mem=%s",
2401 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2402 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]));
2405 fputs ("\n", stderr
);
2408 #define DEBUG_FMT_ID "%-32s= "
2409 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2410 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2411 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2413 /* Print various interesting information with -mdebug=reg. */
2415 rs6000_debug_reg_global (void)
2417 static const char *const tf
[2] = { "false", "true" };
2418 const char *nl
= (const char *)0;
2421 char costly_num
[20];
2423 char flags_buffer
[40];
2424 const char *costly_str
;
2425 const char *nop_str
;
2426 const char *trace_str
;
2427 const char *abi_str
;
2428 const char *cmodel_str
;
2429 struct cl_target_option cl_opts
;
2431 /* Modes we want tieable information on. */
2432 static const machine_mode print_tieable_modes
[] = {
2466 /* Virtual regs we are interested in. */
2467 const static struct {
2468 int regno
; /* register number. */
2469 const char *name
; /* register name. */
2470 } virtual_regs
[] = {
2471 { STACK_POINTER_REGNUM
, "stack pointer:" },
2472 { TOC_REGNUM
, "toc: " },
2473 { STATIC_CHAIN_REGNUM
, "static chain: " },
2474 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2475 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2476 { ARG_POINTER_REGNUM
, "arg pointer: " },
2477 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2478 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2479 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2480 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2481 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2482 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2483 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2484 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2485 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2486 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2489 fputs ("\nHard register information:\n", stderr
);
2490 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2491 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2492 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2495 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2496 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2497 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2498 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2499 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2500 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2502 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2503 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2504 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2508 "d reg_class = %s\n"
2509 "f reg_class = %s\n"
2510 "v reg_class = %s\n"
2511 "wa reg_class = %s\n"
2512 "wb reg_class = %s\n"
2513 "wd reg_class = %s\n"
2514 "we reg_class = %s\n"
2515 "wf reg_class = %s\n"
2516 "wg reg_class = %s\n"
2517 "wh reg_class = %s\n"
2518 "wi reg_class = %s\n"
2519 "wj reg_class = %s\n"
2520 "wk reg_class = %s\n"
2521 "wl reg_class = %s\n"
2522 "wm reg_class = %s\n"
2523 "wo reg_class = %s\n"
2524 "wp reg_class = %s\n"
2525 "wq reg_class = %s\n"
2526 "wr reg_class = %s\n"
2527 "ws reg_class = %s\n"
2528 "wt reg_class = %s\n"
2529 "wu reg_class = %s\n"
2530 "wv reg_class = %s\n"
2531 "ww reg_class = %s\n"
2532 "wx reg_class = %s\n"
2533 "wy reg_class = %s\n"
2534 "wz reg_class = %s\n"
2535 "wA reg_class = %s\n"
2536 "wH reg_class = %s\n"
2537 "wI reg_class = %s\n"
2538 "wJ reg_class = %s\n"
2539 "wK reg_class = %s\n"
2541 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2542 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2543 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2544 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2545 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wb
]],
2546 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2547 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_we
]],
2548 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2549 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2550 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2551 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2552 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2553 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2554 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2555 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2556 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wo
]],
2557 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wp
]],
2558 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wq
]],
2559 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2560 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2561 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2562 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2563 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2564 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2565 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2566 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2567 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]],
2568 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wA
]],
2569 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wH
]],
2570 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wI
]],
2571 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wJ
]],
2572 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wK
]]);
2575 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2576 rs6000_debug_print_mode (m
);
2578 fputs ("\n", stderr
);
2580 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2582 machine_mode mode1
= print_tieable_modes
[m1
];
2583 bool first_time
= true;
2585 nl
= (const char *)0;
2586 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2588 machine_mode mode2
= print_tieable_modes
[m2
];
2589 if (mode1
!= mode2
&& rs6000_modes_tieable_p (mode1
, mode2
))
2593 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2598 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2603 fputs ("\n", stderr
);
2609 if (rs6000_recip_control
)
2611 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2613 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2614 if (rs6000_recip_bits
[m
])
2617 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2619 (RS6000_RECIP_AUTO_RE_P (m
)
2621 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2622 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2624 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2627 fputs ("\n", stderr
);
2630 if (rs6000_cpu_index
>= 0)
2632 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2634 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2636 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2637 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2640 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2642 if (rs6000_tune_index
>= 0)
2644 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2646 = processor_target_table
[rs6000_tune_index
].target_enable
;
2648 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2649 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2652 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2654 cl_target_option_save (&cl_opts
, &global_options
);
2655 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2658 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2659 rs6000_isa_flags_explicit
);
2661 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2662 rs6000_builtin_mask
);
2664 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2666 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2667 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2669 switch (rs6000_sched_costly_dep
)
2671 case max_dep_latency
:
2672 costly_str
= "max_dep_latency";
2676 costly_str
= "no_dep_costly";
2679 case all_deps_costly
:
2680 costly_str
= "all_deps_costly";
2683 case true_store_to_load_dep_costly
:
2684 costly_str
= "true_store_to_load_dep_costly";
2687 case store_to_load_dep_costly
:
2688 costly_str
= "store_to_load_dep_costly";
2692 costly_str
= costly_num
;
2693 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2697 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2699 switch (rs6000_sched_insert_nops
)
2701 case sched_finish_regroup_exact
:
2702 nop_str
= "sched_finish_regroup_exact";
2705 case sched_finish_pad_groups
:
2706 nop_str
= "sched_finish_pad_groups";
2709 case sched_finish_none
:
2710 nop_str
= "sched_finish_none";
2715 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2719 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2721 switch (rs6000_sdata
)
2728 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2732 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2736 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2741 switch (rs6000_traceback
)
2743 case traceback_default
: trace_str
= "default"; break;
2744 case traceback_none
: trace_str
= "none"; break;
2745 case traceback_part
: trace_str
= "part"; break;
2746 case traceback_full
: trace_str
= "full"; break;
2747 default: trace_str
= "unknown"; break;
2750 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2752 switch (rs6000_current_cmodel
)
2754 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2755 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2756 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2757 default: cmodel_str
= "unknown"; break;
2760 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2762 switch (rs6000_current_abi
)
2764 case ABI_NONE
: abi_str
= "none"; break;
2765 case ABI_AIX
: abi_str
= "aix"; break;
2766 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2767 case ABI_V4
: abi_str
= "V4"; break;
2768 case ABI_DARWIN
: abi_str
= "darwin"; break;
2769 default: abi_str
= "unknown"; break;
2772 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2774 if (rs6000_altivec_abi
)
2775 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2777 if (rs6000_darwin64_abi
)
2778 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2780 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2781 (TARGET_SOFT_FLOAT
? "true" : "false"));
2783 if (TARGET_LINK_STACK
)
2784 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2786 if (TARGET_P8_FUSION
)
2790 strcpy (options
, "power8");
2791 if (TARGET_P8_FUSION_SIGN
)
2792 strcat (options
, ", sign");
2794 fprintf (stderr
, DEBUG_FMT_S
, "fusion", options
);
2797 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2798 TARGET_SECURE_PLT
? "secure" : "bss");
2799 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2800 aix_struct_return
? "aix" : "sysv");
2801 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2802 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2803 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2804 tf
[!!rs6000_align_branch_targets
]);
2805 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2806 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2807 rs6000_long_double_type_size
);
2808 if (rs6000_long_double_type_size
> 64)
2810 fprintf (stderr
, DEBUG_FMT_S
, "long double type",
2811 TARGET_IEEEQUAD
? "IEEE" : "IBM");
2812 fprintf (stderr
, DEBUG_FMT_S
, "default long double type",
2813 TARGET_IEEEQUAD_DEFAULT
? "IEEE" : "IBM");
2815 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2816 (int)rs6000_sched_restricted_insns_priority
);
2817 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2819 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2820 (int)RS6000_BUILTIN_COUNT
);
2822 fprintf (stderr
, DEBUG_FMT_D
, "Enable float128 on VSX",
2823 (int)TARGET_FLOAT128_ENABLE_TYPE
);
2826 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2827 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2829 if (TARGET_DIRECT_MOVE_128
)
2830 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit mfvsrld element",
2831 (int)VECTOR_ELEMENT_MFVSRLD_64BIT
);
2835 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2836 legitimate address support to figure out the appropriate addressing to
2840 rs6000_setup_reg_addr_masks (void)
2842 ssize_t rc
, reg
, m
, nregs
;
2843 addr_mask_type any_addr_mask
, addr_mask
;
2845 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2847 machine_mode m2
= (machine_mode
) m
;
2848 bool complex_p
= false;
2849 bool small_int_p
= (m2
== QImode
|| m2
== HImode
|| m2
== SImode
);
2852 if (COMPLEX_MODE_P (m2
))
2855 m2
= GET_MODE_INNER (m2
);
2858 msize
= GET_MODE_SIZE (m2
);
2860 /* SDmode is special in that we want to access it only via REG+REG
2861 addressing on power7 and above, since we want to use the LFIWZX and
2862 STFIWZX instructions to load it. */
2863 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2866 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2869 reg
= reload_reg_map
[rc
].reg
;
2871 /* Can mode values go in the GPR/FPR/Altivec registers? */
2872 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2874 bool small_int_vsx_p
= (small_int_p
2875 && (rc
== RELOAD_REG_FPR
2876 || rc
== RELOAD_REG_VMX
));
2878 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2879 addr_mask
|= RELOAD_REG_VALID
;
2881 /* Indicate if the mode takes more than 1 physical register. If
2882 it takes a single register, indicate it can do REG+REG
2883 addressing. Small integers in VSX registers can only do
2884 REG+REG addressing. */
2885 if (small_int_vsx_p
)
2886 addr_mask
|= RELOAD_REG_INDEXED
;
2887 else if (nregs
> 1 || m
== BLKmode
|| complex_p
)
2888 addr_mask
|= RELOAD_REG_MULTIPLE
;
2890 addr_mask
|= RELOAD_REG_INDEXED
;
2892 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2893 addressing. If we allow scalars into Altivec registers,
2894 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2896 For VSX systems, we don't allow update addressing for
2897 DFmode/SFmode if those registers can go in both the
2898 traditional floating point registers and Altivec registers.
2899 The load/store instructions for the Altivec registers do not
2900 have update forms. If we allowed update addressing, it seems
2901 to break IV-OPT code using floating point if the index type is
2902 int instead of long (PR target/81550 and target/84042). */
2905 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2907 && !VECTOR_MODE_P (m2
)
2908 && !FLOAT128_VECTOR_P (m2
)
2910 && (m
!= E_DFmode
|| !TARGET_VSX
)
2911 && (m
!= E_SFmode
|| !TARGET_P8_VECTOR
)
2912 && !small_int_vsx_p
)
2914 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2916 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2917 we don't allow PRE_MODIFY for some multi-register
2922 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2926 if (TARGET_POWERPC64
)
2927 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2932 if (TARGET_HARD_FLOAT
)
2933 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2939 /* GPR and FPR registers can do REG+OFFSET addressing, except
2940 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2941 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2942 if ((addr_mask
!= 0) && !indexed_only_p
2944 && (rc
== RELOAD_REG_GPR
2945 || ((msize
== 8 || m2
== SFmode
)
2946 && (rc
== RELOAD_REG_FPR
2947 || (rc
== RELOAD_REG_VMX
&& TARGET_P9_VECTOR
)))))
2948 addr_mask
|= RELOAD_REG_OFFSET
;
2950 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2951 instructions are enabled. The offset for 128-bit VSX registers is
2952 only 12-bits. While GPRs can handle the full offset range, VSX
2953 registers can only handle the restricted range. */
2954 else if ((addr_mask
!= 0) && !indexed_only_p
2955 && msize
== 16 && TARGET_P9_VECTOR
2956 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2
)
2957 || (m2
== TImode
&& TARGET_VSX
)))
2959 addr_mask
|= RELOAD_REG_OFFSET
;
2960 if (rc
== RELOAD_REG_FPR
|| rc
== RELOAD_REG_VMX
)
2961 addr_mask
|= RELOAD_REG_QUAD_OFFSET
;
2964 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2965 addressing on 128-bit types. */
2966 if (rc
== RELOAD_REG_VMX
&& msize
== 16
2967 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2968 addr_mask
|= RELOAD_REG_AND_M16
;
2970 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2971 any_addr_mask
|= addr_mask
;
2974 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2979 /* Initialize the various global tables that are based on register size. */
2981 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2987 /* Precalculate REGNO_REG_CLASS. */
2988 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2989 for (r
= 1; r
< 32; ++r
)
2990 rs6000_regno_regclass
[r
] = BASE_REGS
;
2992 for (r
= 32; r
< 64; ++r
)
2993 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2995 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2996 rs6000_regno_regclass
[r
] = NO_REGS
;
2998 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2999 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
3001 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
3002 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
3003 rs6000_regno_regclass
[r
] = CR_REGS
;
3005 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
3006 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
3007 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
3008 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
3009 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
3010 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
3011 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
3012 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
3013 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
3014 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
3016 /* Precalculate register class to simpler reload register class. We don't
3017 need all of the register classes that are combinations of different
3018 classes, just the simple ones that have constraint letters. */
3019 for (c
= 0; c
< N_REG_CLASSES
; c
++)
3020 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
3022 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
3023 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
3024 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
3025 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
3026 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
3027 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
3028 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
3029 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
3030 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
3031 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
3035 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
3036 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
3040 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
3041 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
3044 /* Precalculate the valid memory formats as well as the vector information,
3045 this must be set up before the rs6000_hard_regno_nregs_internal calls
3047 gcc_assert ((int)VECTOR_NONE
== 0);
3048 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
3049 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
3051 gcc_assert ((int)CODE_FOR_nothing
== 0);
3052 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
3054 gcc_assert ((int)NO_REGS
== 0);
3055 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
3057 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3058 believes it can use native alignment or still uses 128-bit alignment. */
3059 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
3070 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3071 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3072 if (TARGET_FLOAT128_TYPE
)
3074 rs6000_vector_mem
[KFmode
] = VECTOR_VSX
;
3075 rs6000_vector_align
[KFmode
] = 128;
3077 if (FLOAT128_IEEE_P (TFmode
))
3079 rs6000_vector_mem
[TFmode
] = VECTOR_VSX
;
3080 rs6000_vector_align
[TFmode
] = 128;
3084 /* V2DF mode, VSX only. */
3087 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
3088 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
3089 rs6000_vector_align
[V2DFmode
] = align64
;
3092 /* V4SF mode, either VSX or Altivec. */
3095 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
3096 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
3097 rs6000_vector_align
[V4SFmode
] = align32
;
3099 else if (TARGET_ALTIVEC
)
3101 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
3102 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
3103 rs6000_vector_align
[V4SFmode
] = align32
;
3106 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3110 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
3111 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
3112 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
3113 rs6000_vector_align
[V4SImode
] = align32
;
3114 rs6000_vector_align
[V8HImode
] = align32
;
3115 rs6000_vector_align
[V16QImode
] = align32
;
3119 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
3120 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
3121 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
3125 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
3126 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
3127 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
3131 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3132 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3135 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
3136 rs6000_vector_unit
[V2DImode
]
3137 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3138 rs6000_vector_align
[V2DImode
] = align64
;
3140 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
3141 rs6000_vector_unit
[V1TImode
]
3142 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3143 rs6000_vector_align
[V1TImode
] = 128;
3146 /* DFmode, see if we want to use the VSX unit. Memory is handled
3147 differently, so don't set rs6000_vector_mem. */
3150 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
3151 rs6000_vector_align
[DFmode
] = 64;
3154 /* SFmode, see if we want to use the VSX unit. */
3155 if (TARGET_P8_VECTOR
)
3157 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
3158 rs6000_vector_align
[SFmode
] = 32;
3161 /* Allow TImode in VSX register and set the VSX memory macros. */
3164 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
3165 rs6000_vector_align
[TImode
] = align64
;
3168 /* Register class constraints for the constraints that depend on compile
3169 switches. When the VSX code was added, different constraints were added
3170 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3171 of the VSX registers are used. The register classes for scalar floating
3172 point types is set, based on whether we allow that type into the upper
3173 (Altivec) registers. GCC has register classes to target the Altivec
3174 registers for load/store operations, to select using a VSX memory
3175 operation instead of the traditional floating point operation. The
3178 d - Register class to use with traditional DFmode instructions.
3179 f - Register class to use with traditional SFmode instructions.
3180 v - Altivec register.
3181 wa - Any VSX register.
3182 wc - Reserved to represent individual CR bits (used in LLVM).
3183 wd - Preferred register class for V2DFmode.
3184 wf - Preferred register class for V4SFmode.
3185 wg - Float register for power6x move insns.
3186 wh - FP register for direct move instructions.
3187 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3188 wj - FP or VSX register to hold 64-bit integers for direct moves.
3189 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3190 wl - Float register if we can do 32-bit signed int loads.
3191 wm - VSX register for ISA 2.07 direct move operations.
3192 wn - always NO_REGS.
3193 wr - GPR if 64-bit mode is permitted.
3194 ws - Register class to do ISA 2.06 DF operations.
3195 wt - VSX register for TImode in VSX registers.
3196 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3197 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3198 ww - Register class to do SF conversions in with VSX operations.
3199 wx - Float register if we can do 32-bit int stores.
3200 wy - Register class to do ISA 2.07 SF operations.
3201 wz - Float register if we can do 32-bit unsigned int loads.
3202 wH - Altivec register if SImode is allowed in VSX registers.
3203 wI - VSX register if SImode is allowed in VSX registers.
3204 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3205 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3207 if (TARGET_HARD_FLOAT
)
3209 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
3210 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
3215 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
3216 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
3217 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
3218 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
; /* DFmode */
3219 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
; /* DFmode */
3220 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = VSX_REGS
; /* DImode */
3221 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
3224 /* Add conditional constraints based on various options, to allow us to
3225 collapse multiple insn patterns. */
3227 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
3229 if (TARGET_MFPGPR
) /* DFmode */
3230 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
3233 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
3235 if (TARGET_DIRECT_MOVE
)
3237 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
3238 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
3239 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
3240 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
3241 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
3242 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
3245 if (TARGET_POWERPC64
)
3247 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
3248 rs6000_constraints
[RS6000_CONSTRAINT_wA
] = BASE_REGS
;
3251 if (TARGET_P8_VECTOR
) /* SFmode */
3253 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
3254 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
3255 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
3257 else if (TARGET_VSX
)
3258 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3261 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
3264 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
3266 if (TARGET_FLOAT128_TYPE
)
3268 rs6000_constraints
[RS6000_CONSTRAINT_wq
] = VSX_REGS
; /* KFmode */
3269 if (FLOAT128_IEEE_P (TFmode
))
3270 rs6000_constraints
[RS6000_CONSTRAINT_wp
] = VSX_REGS
; /* TFmode */
3273 if (TARGET_P9_VECTOR
)
3275 /* Support for new D-form instructions. */
3276 rs6000_constraints
[RS6000_CONSTRAINT_wb
] = ALTIVEC_REGS
;
3278 /* Support for ISA 3.0 (power9) vectors. */
3279 rs6000_constraints
[RS6000_CONSTRAINT_wo
] = VSX_REGS
;
3282 /* Support for new direct moves (ISA 3.0 + 64bit). */
3283 if (TARGET_DIRECT_MOVE_128
)
3284 rs6000_constraints
[RS6000_CONSTRAINT_we
] = VSX_REGS
;
3286 /* Support small integers in VSX registers. */
3287 if (TARGET_P8_VECTOR
)
3289 rs6000_constraints
[RS6000_CONSTRAINT_wH
] = ALTIVEC_REGS
;
3290 rs6000_constraints
[RS6000_CONSTRAINT_wI
] = FLOAT_REGS
;
3291 if (TARGET_P9_VECTOR
)
3293 rs6000_constraints
[RS6000_CONSTRAINT_wJ
] = FLOAT_REGS
;
3294 rs6000_constraints
[RS6000_CONSTRAINT_wK
] = ALTIVEC_REGS
;
3298 /* Set up the reload helper and direct move functions. */
3299 if (TARGET_VSX
|| TARGET_ALTIVEC
)
3303 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
3304 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
3305 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
3306 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
3307 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
3308 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
3309 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
3310 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
3311 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
3312 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
3313 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
3314 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
3315 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
3316 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
3317 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
3318 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
3319 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
3320 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
3321 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
3322 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
3324 if (FLOAT128_VECTOR_P (KFmode
))
3326 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_di_store
;
3327 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_di_load
;
3330 if (FLOAT128_VECTOR_P (TFmode
))
3332 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_di_store
;
3333 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_di_load
;
3336 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3338 if (TARGET_NO_SDMODE_STACK
)
3340 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
3341 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
3346 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
3347 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
3350 if (TARGET_DIRECT_MOVE
&& !TARGET_DIRECT_MOVE_128
)
3352 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
3353 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
3354 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
3355 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
3356 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
3357 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
3358 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
3359 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
3360 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
3362 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
3363 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
3364 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
3365 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
3366 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
3367 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
3368 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
3369 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
3370 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
3372 if (FLOAT128_VECTOR_P (KFmode
))
3374 reg_addr
[KFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxkf
;
3375 reg_addr
[KFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprkf
;
3378 if (FLOAT128_VECTOR_P (TFmode
))
3380 reg_addr
[TFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxtf
;
3381 reg_addr
[TFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprtf
;
3387 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
3388 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
3389 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
3390 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
3391 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
3392 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
3393 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
3394 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
3395 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
3396 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
3397 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
3398 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
3399 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
3400 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
3401 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
3402 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
3403 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
3404 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
3405 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
3406 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
3408 if (FLOAT128_VECTOR_P (KFmode
))
3410 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_si_store
;
3411 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_si_load
;
3414 if (FLOAT128_IEEE_P (TFmode
))
3416 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_si_store
;
3417 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_si_load
;
3420 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3422 if (TARGET_NO_SDMODE_STACK
)
3424 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
3425 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
3430 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
3431 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
3434 if (TARGET_DIRECT_MOVE
)
3436 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
3437 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
3438 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
3442 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
3443 reg_addr
[DImode
].scalar_in_vmx_p
= true;
3445 if (TARGET_P8_VECTOR
)
3447 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
3448 reg_addr
[SImode
].scalar_in_vmx_p
= true;
3450 if (TARGET_P9_VECTOR
)
3452 reg_addr
[HImode
].scalar_in_vmx_p
= true;
3453 reg_addr
[QImode
].scalar_in_vmx_p
= true;
3458 /* Precalculate HARD_REGNO_NREGS. */
3459 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3460 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3461 rs6000_hard_regno_nregs
[m
][r
]
3462 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
)m
);
3464 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3465 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3466 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3467 if (rs6000_hard_regno_mode_ok_uncached (r
, (machine_mode
)m
))
3468 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
3470 /* Precalculate CLASS_MAX_NREGS sizes. */
3471 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
3475 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
3476 reg_size
= UNITS_PER_VSX_WORD
;
3478 else if (c
== ALTIVEC_REGS
)
3479 reg_size
= UNITS_PER_ALTIVEC_WORD
;
3481 else if (c
== FLOAT_REGS
)
3482 reg_size
= UNITS_PER_FP_WORD
;
3485 reg_size
= UNITS_PER_WORD
;
3487 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3489 machine_mode m2
= (machine_mode
)m
;
3490 int reg_size2
= reg_size
;
3492 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3494 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
) && FLOAT128_2REG_P (m
))
3495 reg_size2
= UNITS_PER_FP_WORD
;
3497 rs6000_class_max_nregs
[m
][c
]
3498 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3502 /* Calculate which modes to automatically generate code to use a the
3503 reciprocal divide and square root instructions. In the future, possibly
3504 automatically generate the instructions even if the user did not specify
3505 -mrecip. The older machines double precision reciprocal sqrt estimate is
3506 not accurate enough. */
3507 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3509 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3511 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3512 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3513 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3514 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3515 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3517 if (TARGET_FRSQRTES
)
3518 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3520 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3521 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3522 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3523 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3524 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3526 if (rs6000_recip_control
)
3528 if (!flag_finite_math_only
)
3529 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3531 if (flag_trapping_math
)
3532 warning (0, "%qs requires %qs or %qs", "-mrecip",
3533 "-fno-trapping-math", "-ffast-math");
3534 if (!flag_reciprocal_math
)
3535 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3537 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3539 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3540 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3541 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3543 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3544 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3545 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3547 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3548 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3549 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3551 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3552 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3553 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3555 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3556 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3557 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3559 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3560 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3561 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3563 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3564 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3565 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3567 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3568 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3569 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3573 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3574 legitimate address support to figure out the appropriate addressing to
3576 rs6000_setup_reg_addr_masks ();
3578 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3580 if (TARGET_DEBUG_REG
)
3581 rs6000_debug_reg_global ();
3583 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3585 "SImode variable mult cost = %d\n"
3586 "SImode constant mult cost = %d\n"
3587 "SImode short constant mult cost = %d\n"
3588 "DImode multipliciation cost = %d\n"
3589 "SImode division cost = %d\n"
3590 "DImode division cost = %d\n"
3591 "Simple fp operation cost = %d\n"
3592 "DFmode multiplication cost = %d\n"
3593 "SFmode division cost = %d\n"
3594 "DFmode division cost = %d\n"
3595 "cache line size = %d\n"
3596 "l1 cache size = %d\n"
3597 "l2 cache size = %d\n"
3598 "simultaneous prefetches = %d\n"
3601 rs6000_cost
->mulsi_const
,
3602 rs6000_cost
->mulsi_const9
,
3610 rs6000_cost
->cache_line_size
,
3611 rs6000_cost
->l1_cache_size
,
3612 rs6000_cost
->l2_cache_size
,
3613 rs6000_cost
->simultaneous_prefetches
);
3618 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3621 darwin_rs6000_override_options (void)
3623 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3625 rs6000_altivec_abi
= 1;
3626 TARGET_ALTIVEC_VRSAVE
= 1;
3627 rs6000_current_abi
= ABI_DARWIN
;
3629 if (DEFAULT_ABI
== ABI_DARWIN
3631 darwin_one_byte_bool
= 1;
3633 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3635 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3636 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3640 rs6000_default_long_calls
= 1;
3641 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3644 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3646 if (!flag_mkernel
&& !flag_apple_kext
3648 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3649 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3651 /* Unless the user (not the configurer) has explicitly overridden
3652 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3653 G4 unless targeting the kernel. */
3656 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3657 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3658 && ! global_options_set
.x_rs6000_cpu_index
)
3660 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3665 /* If not otherwise specified by a target, make 'long double' equivalent to
3668 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3669 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3672 /* Return the builtin mask of the various options used that could affect which
3673 builtins were used. In the past we used target_flags, but we've run out of
3674 bits, and some options are no longer in target_flags. */
3677 rs6000_builtin_mask_calculate (void)
3679 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3680 | ((TARGET_CMPB
) ? RS6000_BTM_CMPB
: 0)
3681 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3682 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3683 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3684 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3685 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3686 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3687 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3688 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3689 | ((TARGET_P9_VECTOR
) ? RS6000_BTM_P9_VECTOR
: 0)
3690 | ((TARGET_P9_MISC
) ? RS6000_BTM_P9_MISC
: 0)
3691 | ((TARGET_MODULO
) ? RS6000_BTM_MODULO
: 0)
3692 | ((TARGET_64BIT
) ? RS6000_BTM_64BIT
: 0)
3693 | ((TARGET_POWERPC64
) ? RS6000_BTM_POWERPC64
: 0)
3694 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3695 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3696 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3697 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3698 | ((TARGET_LONG_DOUBLE_128
3699 && TARGET_HARD_FLOAT
3700 && !TARGET_IEEEQUAD
) ? RS6000_BTM_LDBL128
: 0)
3701 | ((TARGET_FLOAT128_TYPE
) ? RS6000_BTM_FLOAT128
: 0)
3702 | ((TARGET_FLOAT128_HW
) ? RS6000_BTM_FLOAT128_HW
: 0));
3705 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3706 to clobber the XER[CA] bit because clobbering that bit without telling
3707 the compiler worked just fine with versions of GCC before GCC 5, and
3708 breaking a lot of older code in ways that are hard to track down is
3709 not such a great idea. */
3712 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3713 vec
<const char *> &/*constraints*/,
3714 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3716 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3717 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3721 /* Override command line options.
3723 Combine build-specific configuration information with options
3724 specified on the command line to set various state variables which
3725 influence code generation, optimization, and expansion of built-in
3726 functions. Assure that command-line configuration preferences are
3727 compatible with each other and with the build configuration; issue
3728 warnings while adjusting configuration or error messages while
3729 rejecting configuration.
3731 Upon entry to this function:
3733 This function is called once at the beginning of
3734 compilation, and then again at the start and end of compiling
3735 each section of code that has a different configuration, as
3736 indicated, for example, by adding the
3738 __attribute__((__target__("cpu=power9")))
3740 qualifier to a function definition or, for example, by bracketing
3743 #pragma GCC target("altivec")
3747 #pragma GCC reset_options
3749 directives. Parameter global_init_p is true for the initial
3750 invocation, which initializes global variables, and false for all
3751 subsequent invocations.
3754 Various global state information is assumed to be valid. This
3755 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3756 default CPU specified at build configure time, TARGET_DEFAULT,
3757 representing the default set of option flags for the default
3758 target, and global_options_set.x_rs6000_isa_flags, representing
3759 which options were requested on the command line.
3761 Upon return from this function:
3763 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3764 was set by name on the command line. Additionally, if certain
3765 attributes are automatically enabled or disabled by this function
3766 in order to assure compatibility between options and
3767 configuration, the flags associated with those attributes are
3768 also set. By setting these "explicit bits", we avoid the risk
3769 that other code might accidentally overwrite these particular
3770 attributes with "default values".
3772 The various bits of rs6000_isa_flags are set to indicate the
3773 target options that have been selected for the most current
3774 compilation efforts. This has the effect of also turning on the
3775 associated TARGET_XXX values since these are macros which are
3776 generally defined to test the corresponding bit of the
3777 rs6000_isa_flags variable.
3779 The variable rs6000_builtin_mask is set to represent the target
3780 options for the most current compilation efforts, consistent with
3781 the current contents of rs6000_isa_flags. This variable controls
3782 expansion of built-in functions.
3784 Various other global variables and fields of global structures
3785 (over 50 in all) are initialized to reflect the desired options
3786 for the most current compilation efforts. */
3789 rs6000_option_override_internal (bool global_init_p
)
3793 HOST_WIDE_INT set_masks
;
3794 HOST_WIDE_INT ignore_masks
;
3797 struct cl_target_option
*main_target_opt
3798 = ((global_init_p
|| target_option_default_node
== NULL
)
3799 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3801 /* Print defaults. */
3802 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3803 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3805 /* Remember the explicit arguments. */
3807 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3809 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3810 library functions, so warn about it. The flag may be useful for
3811 performance studies from time to time though, so don't disable it
3813 if (global_options_set
.x_rs6000_alignment_flags
3814 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3815 && DEFAULT_ABI
== ABI_DARWIN
3817 warning (0, "%qs is not supported for 64-bit Darwin;"
3818 " it is incompatible with the installed C and C++ libraries",
3821 /* Numerous experiment shows that IRA based loop pressure
3822 calculation works better for RTL loop invariant motion on targets
3823 with enough (>= 32) registers. It is an expensive optimization.
3824 So it is on only for peak performance. */
3825 if (optimize
>= 3 && global_init_p
3826 && !global_options_set
.x_flag_ira_loop_pressure
)
3827 flag_ira_loop_pressure
= 1;
3829 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3830 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3831 options were already specified. */
3832 if (flag_sanitize
& SANITIZE_USER_ADDRESS
3833 && !global_options_set
.x_flag_asynchronous_unwind_tables
)
3834 flag_asynchronous_unwind_tables
= 1;
3836 /* Set the pointer size. */
3839 rs6000_pmode
= DImode
;
3840 rs6000_pointer_size
= 64;
3844 rs6000_pmode
= SImode
;
3845 rs6000_pointer_size
= 32;
3848 /* Some OSs don't support saving the high part of 64-bit registers on context
3849 switch. Other OSs don't support saving Altivec registers. On those OSs,
3850 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3851 if the user wants either, the user must explicitly specify them and we
3852 won't interfere with the user's specification. */
3854 set_masks
= POWERPC_MASKS
;
3855 #ifdef OS_MISSING_POWERPC64
3856 if (OS_MISSING_POWERPC64
)
3857 set_masks
&= ~OPTION_MASK_POWERPC64
;
3859 #ifdef OS_MISSING_ALTIVEC
3860 if (OS_MISSING_ALTIVEC
)
3861 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
3862 | OTHER_VSX_VECTOR_MASKS
);
3865 /* Don't override by the processor default if given explicitly. */
3866 set_masks
&= ~rs6000_isa_flags_explicit
;
3868 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3869 the cpu in a target attribute or pragma, but did not specify a tuning
3870 option, use the cpu for the tuning option rather than the option specified
3871 with -mtune on the command line. Process a '--with-cpu' configuration
3872 request as an implicit --cpu. */
3873 if (rs6000_cpu_index
>= 0)
3874 cpu_index
= rs6000_cpu_index
;
3875 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3876 cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3877 else if (OPTION_TARGET_CPU_DEFAULT
)
3878 cpu_index
= rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT
);
3880 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3881 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3882 with those from the cpu, except for options that were explicitly set. If
3883 we don't have a cpu, do not override the target bits set in
3887 rs6000_cpu_index
= cpu_index
;
3888 rs6000_isa_flags
&= ~set_masks
;
3889 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3894 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3895 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3896 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3897 to using rs6000_isa_flags, we need to do the initialization here.
3899 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3900 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3901 HOST_WIDE_INT flags
;
3903 flags
= TARGET_DEFAULT
;
3906 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3907 const char *default_cpu
= (!TARGET_POWERPC64
3912 int default_cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3913 flags
= processor_target_table
[default_cpu_index
].target_enable
;
3915 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
3918 if (rs6000_tune_index
>= 0)
3919 tune_index
= rs6000_tune_index
;
3920 else if (cpu_index
>= 0)
3921 rs6000_tune_index
= tune_index
= cpu_index
;
3925 enum processor_type tune_proc
3926 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3929 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3930 if (processor_target_table
[i
].processor
== tune_proc
)
3938 rs6000_cpu
= processor_target_table
[cpu_index
].processor
;
3940 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
3942 gcc_assert (tune_index
>= 0);
3943 rs6000_tune
= processor_target_table
[tune_index
].processor
;
3945 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3946 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3947 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3950 error ("AltiVec not supported in this target");
3953 /* If we are optimizing big endian systems for space, use the load/store
3954 multiple instructions. */
3955 if (BYTES_BIG_ENDIAN
&& optimize_size
)
3956 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
;
3958 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3959 because the hardware doesn't support the instructions used in little
3960 endian mode, and causes an alignment trap. The 750 does not cause an
3961 alignment trap (except when the target is unaligned). */
3963 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
&& TARGET_MULTIPLE
)
3965 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3966 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3967 warning (0, "%qs is not supported on little endian systems",
3971 /* If little-endian, default to -mstrict-align on older processors.
3972 Testing for htm matches power8 and later. */
3973 if (!BYTES_BIG_ENDIAN
3974 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3975 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3977 if (!rs6000_fold_gimple
)
3979 "gimple folding of rs6000 builtins has been disabled.\n");
3981 /* Add some warnings for VSX. */
3984 const char *msg
= NULL
;
3985 if (!TARGET_HARD_FLOAT
)
3987 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3988 msg
= N_("-mvsx requires hardware floating point");
3991 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3992 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3995 else if (TARGET_AVOID_XFORM
> 0)
3996 msg
= N_("-mvsx needs indexed addressing");
3997 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3998 & OPTION_MASK_ALTIVEC
))
4000 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4001 msg
= N_("-mvsx and -mno-altivec are incompatible");
4003 msg
= N_("-mno-altivec disables vsx");
4009 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
4010 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4014 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4015 the -mcpu setting to enable options that conflict. */
4016 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
4017 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
4018 | OPTION_MASK_ALTIVEC
4019 | OPTION_MASK_VSX
)) != 0)
4020 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
4021 | OPTION_MASK_DIRECT_MOVE
)
4022 & ~rs6000_isa_flags_explicit
);
4024 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4025 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
4027 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4028 off all of the options that depend on those flags. */
4029 ignore_masks
= rs6000_disable_incompatible_switches ();
4031 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4032 unless the user explicitly used the -mno-<option> to disable the code. */
4033 if (TARGET_P9_VECTOR
|| TARGET_MODULO
|| TARGET_P9_MISC
)
4034 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4035 else if (TARGET_P9_MINMAX
)
4039 if (cpu_index
== PROCESSOR_POWER9
)
4041 /* legacy behavior: allow -mcpu=power9 with certain
4042 capabilities explicitly disabled. */
4043 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4046 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4047 "for <xxx> less than power9", "-mcpu");
4049 else if ((ISA_3_0_MASKS_SERVER
& rs6000_isa_flags_explicit
)
4050 != (ISA_3_0_MASKS_SERVER
& rs6000_isa_flags
4051 & rs6000_isa_flags_explicit
))
4052 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4053 were explicitly cleared. */
4054 error ("%qs incompatible with explicitly disabled options",
4057 rs6000_isa_flags
|= ISA_3_0_MASKS_SERVER
;
4059 else if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
4060 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~ignore_masks
);
4061 else if (TARGET_VSX
)
4062 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~ignore_masks
);
4063 else if (TARGET_POPCNTD
)
4064 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~ignore_masks
);
4065 else if (TARGET_DFP
)
4066 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~ignore_masks
);
4067 else if (TARGET_CMPB
)
4068 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~ignore_masks
);
4069 else if (TARGET_FPRND
)
4070 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~ignore_masks
);
4071 else if (TARGET_POPCNTB
)
4072 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~ignore_masks
);
4073 else if (TARGET_ALTIVEC
)
4074 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~ignore_masks
);
4076 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
4078 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
4079 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4080 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
4083 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
4085 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
4086 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4087 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
4090 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
4092 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4093 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4094 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4097 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
4099 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4100 && (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
))
4101 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4102 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
) == 0)
4104 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4105 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4106 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4110 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4112 rs6000_isa_flags
|= OPTION_MASK_VSX
;
4113 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4117 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
4119 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
4120 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4121 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
4124 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4125 silently turn off quad memory mode. */
4126 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
4128 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4129 warning (0, N_("-mquad-memory requires 64-bit mode"));
4131 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
4132 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4134 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
4135 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
4138 /* Non-atomic quad memory load/store are disabled for little endian, since
4139 the words are reversed, but atomic operations can still be done by
4140 swapping the words. */
4141 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
4143 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4144 warning (0, N_("-mquad-memory is not available in little endian "
4147 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
4150 /* Assume if the user asked for normal quad memory instructions, they want
4151 the atomic versions as well, unless they explicity told us not to use quad
4152 word atomic instructions. */
4153 if (TARGET_QUAD_MEMORY
4154 && !TARGET_QUAD_MEMORY_ATOMIC
4155 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
4156 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
4158 /* If we can shrink-wrap the TOC register save separately, then use
4159 -msave-toc-indirect unless explicitly disabled. */
4160 if ((rs6000_isa_flags_explicit
& OPTION_MASK_SAVE_TOC_INDIRECT
) == 0
4161 && flag_shrink_wrap_separate
4162 && optimize_function_for_speed_p (cfun
))
4163 rs6000_isa_flags
|= OPTION_MASK_SAVE_TOC_INDIRECT
;
4165 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4166 generating power8 instructions. Power9 does not optimize power8 fusion
4168 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
4170 if (processor_target_table
[tune_index
].processor
== PROCESSOR_POWER8
)
4171 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4173 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4176 /* Setting additional fusion flags turns on base fusion. */
4177 if (!TARGET_P8_FUSION
&& TARGET_P8_FUSION_SIGN
)
4179 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4181 if (TARGET_P8_FUSION_SIGN
)
4182 error ("%qs requires %qs", "-mpower8-fusion-sign",
4185 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4188 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4191 /* Power8 does not fuse sign extended loads with the addis. If we are
4192 optimizing at high levels for speed, convert a sign extended load into a
4193 zero extending load, and an explicit sign extension. */
4194 if (TARGET_P8_FUSION
4195 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
4196 && optimize_function_for_speed_p (cfun
)
4198 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
4200 /* ISA 3.0 vector instructions include ISA 2.07. */
4201 if (TARGET_P9_VECTOR
&& !TARGET_P8_VECTOR
)
4203 /* We prefer to not mention undocumented options in
4204 error messages. However, if users have managed to select
4205 power9-vector without selecting power8-vector, they
4206 already know about undocumented flags. */
4207 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) &&
4208 (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
))
4209 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4210 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) == 0)
4212 rs6000_isa_flags
&= ~OPTION_MASK_P9_VECTOR
;
4213 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4214 rs6000_isa_flags_explicit
|= OPTION_MASK_P9_VECTOR
;
4218 /* OPTION_MASK_P9_VECTOR is explicit and
4219 OPTION_MASK_P8_VECTOR is not explicit. */
4220 rs6000_isa_flags
|= OPTION_MASK_P8_VECTOR
;
4221 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4225 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4226 support. If we only have ISA 2.06 support, and the user did not specify
4227 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4228 but we don't enable the full vectorization support */
4229 if (TARGET_ALLOW_MOVMISALIGN
== -1 && TARGET_P8_VECTOR
&& TARGET_DIRECT_MOVE
)
4230 TARGET_ALLOW_MOVMISALIGN
= 1;
4232 else if (TARGET_ALLOW_MOVMISALIGN
&& !TARGET_VSX
)
4234 if (TARGET_ALLOW_MOVMISALIGN
> 0
4235 && global_options_set
.x_TARGET_ALLOW_MOVMISALIGN
)
4236 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4238 TARGET_ALLOW_MOVMISALIGN
= 0;
4241 /* Determine when unaligned vector accesses are permitted, and when
4242 they are preferred over masked Altivec loads. Note that if
4243 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4244 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4246 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4250 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4251 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4253 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4256 else if (!TARGET_ALLOW_MOVMISALIGN
)
4258 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4259 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4260 "-mallow-movmisalign");
4262 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4266 /* Use long double size to select the appropriate long double. We use
4267 TYPE_PRECISION to differentiate the 3 different long double types. We map
4268 128 into the precision used for TFmode. */
4269 int default_long_double_size
= (RS6000_DEFAULT_LONG_DOUBLE_SIZE
== 64
4271 : FLOAT_PRECISION_TFmode
);
4273 /* Set long double size before the IEEE 128-bit tests. */
4274 if (!global_options_set
.x_rs6000_long_double_type_size
)
4276 if (main_target_opt
!= NULL
4277 && (main_target_opt
->x_rs6000_long_double_type_size
4278 != default_long_double_size
))
4279 error ("target attribute or pragma changes long double size");
4281 rs6000_long_double_type_size
= default_long_double_size
;
4283 else if (rs6000_long_double_type_size
== 128)
4284 rs6000_long_double_type_size
= FLOAT_PRECISION_TFmode
;
4286 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4287 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4288 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4289 those systems will not pick up this default. Warn if the user changes the
4290 default unless -Wno-psabi. */
4291 if (!global_options_set
.x_rs6000_ieeequad
)
4292 rs6000_ieeequad
= TARGET_IEEEQUAD_DEFAULT
;
4294 else if (rs6000_ieeequad
!= TARGET_IEEEQUAD_DEFAULT
&& TARGET_LONG_DOUBLE_128
)
4296 static bool warned_change_long_double
;
4297 if (!warned_change_long_double
)
4299 warned_change_long_double
= true;
4300 if (TARGET_IEEEQUAD
)
4301 warning (OPT_Wpsabi
, "Using IEEE extended precision long double");
4303 warning (OPT_Wpsabi
, "Using IBM extended precision long double");
4307 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4308 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4309 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4310 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4311 the keyword as well as the type. */
4312 TARGET_FLOAT128_TYPE
= TARGET_FLOAT128_ENABLE_TYPE
&& TARGET_VSX
;
4314 /* IEEE 128-bit floating point requires VSX support. */
4315 if (TARGET_FLOAT128_KEYWORD
)
4319 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) != 0)
4320 error ("%qs requires VSX support", "-mfloat128");
4322 TARGET_FLOAT128_TYPE
= 0;
4323 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_KEYWORD
4324 | OPTION_MASK_FLOAT128_HW
);
4326 else if (!TARGET_FLOAT128_TYPE
)
4328 TARGET_FLOAT128_TYPE
= 1;
4329 warning (0, "The -mfloat128 option may not be fully supported");
4333 /* Enable the __float128 keyword under Linux by default. */
4334 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_KEYWORD
4335 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) == 0)
4336 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_KEYWORD
;
4338 /* If we have are supporting the float128 type and full ISA 3.0 support,
4339 enable -mfloat128-hardware by default. However, don't enable the
4340 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4341 because sometimes the compiler wants to put things in an integer
4342 container, and if we don't have __int128 support, it is impossible. */
4343 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_HW
&& TARGET_64BIT
4344 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) == ISA_3_0_MASKS_IEEE
4345 && !(rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
))
4346 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_HW
;
4348 if (TARGET_FLOAT128_HW
4349 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) != ISA_3_0_MASKS_IEEE
)
4351 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4352 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4354 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4357 if (TARGET_FLOAT128_HW
&& !TARGET_64BIT
)
4359 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4360 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4362 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4365 /* Print the options after updating the defaults. */
4366 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4367 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
4369 /* E500mc does "better" if we inline more aggressively. Respect the
4370 user's opinion, though. */
4371 if (rs6000_block_move_inline_limit
== 0
4372 && (rs6000_tune
== PROCESSOR_PPCE500MC
4373 || rs6000_tune
== PROCESSOR_PPCE500MC64
4374 || rs6000_tune
== PROCESSOR_PPCE5500
4375 || rs6000_tune
== PROCESSOR_PPCE6500
))
4376 rs6000_block_move_inline_limit
= 128;
4378 /* store_one_arg depends on expand_block_move to handle at least the
4379 size of reg_parm_stack_space. */
4380 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
4381 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
4385 /* If the appropriate debug option is enabled, replace the target hooks
4386 with debug versions that call the real version and then prints
4387 debugging information. */
4388 if (TARGET_DEBUG_COST
)
4390 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
4391 targetm
.address_cost
= rs6000_debug_address_cost
;
4392 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
4395 if (TARGET_DEBUG_ADDR
)
4397 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
4398 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
4399 rs6000_secondary_reload_class_ptr
4400 = rs6000_debug_secondary_reload_class
;
4401 targetm
.secondary_memory_needed
4402 = rs6000_debug_secondary_memory_needed
;
4403 targetm
.can_change_mode_class
4404 = rs6000_debug_can_change_mode_class
;
4405 rs6000_preferred_reload_class_ptr
4406 = rs6000_debug_preferred_reload_class
;
4407 rs6000_legitimize_reload_address_ptr
4408 = rs6000_debug_legitimize_reload_address
;
4409 rs6000_mode_dependent_address_ptr
4410 = rs6000_debug_mode_dependent_address
;
4413 if (rs6000_veclibabi_name
)
4415 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
4416 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
4419 error ("unknown vectorization library ABI type (%qs) for "
4420 "%qs switch", rs6000_veclibabi_name
, "-mveclibabi=");
4426 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4427 target attribute or pragma which automatically enables both options,
4428 unless the altivec ABI was set. This is set by default for 64-bit, but
4430 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4432 TARGET_FLOAT128_TYPE
= 0;
4433 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
4434 | OPTION_MASK_FLOAT128_KEYWORD
)
4435 & ~rs6000_isa_flags_explicit
);
4438 /* Enable Altivec ABI for AIX -maltivec. */
4439 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
4441 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4442 error ("target attribute or pragma changes AltiVec ABI");
4444 rs6000_altivec_abi
= 1;
4447 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4448 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4449 be explicitly overridden in either case. */
4452 if (!global_options_set
.x_rs6000_altivec_abi
4453 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
4455 if (main_target_opt
!= NULL
&&
4456 !main_target_opt
->x_rs6000_altivec_abi
)
4457 error ("target attribute or pragma changes AltiVec ABI");
4459 rs6000_altivec_abi
= 1;
4463 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4464 So far, the only darwin64 targets are also MACH-O. */
4466 && DEFAULT_ABI
== ABI_DARWIN
4469 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
4470 error ("target attribute or pragma changes darwin64 ABI");
4473 rs6000_darwin64_abi
= 1;
4474 /* Default to natural alignment, for better performance. */
4475 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
4479 /* Place FP constants in the constant pool instead of TOC
4480 if section anchors enabled. */
4481 if (flag_section_anchors
4482 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
4483 TARGET_NO_FP_IN_TOC
= 1;
4485 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4486 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
4488 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4489 SUBTARGET_OVERRIDE_OPTIONS
;
4491 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4492 SUBSUBTARGET_OVERRIDE_OPTIONS
;
4494 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4495 SUB3TARGET_OVERRIDE_OPTIONS
;
4498 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4499 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
4501 rs6000_always_hint
= (rs6000_tune
!= PROCESSOR_POWER4
4502 && rs6000_tune
!= PROCESSOR_POWER5
4503 && rs6000_tune
!= PROCESSOR_POWER6
4504 && rs6000_tune
!= PROCESSOR_POWER7
4505 && rs6000_tune
!= PROCESSOR_POWER8
4506 && rs6000_tune
!= PROCESSOR_POWER9
4507 && rs6000_tune
!= PROCESSOR_PPCA2
4508 && rs6000_tune
!= PROCESSOR_CELL
4509 && rs6000_tune
!= PROCESSOR_PPC476
);
4510 rs6000_sched_groups
= (rs6000_tune
== PROCESSOR_POWER4
4511 || rs6000_tune
== PROCESSOR_POWER5
4512 || rs6000_tune
== PROCESSOR_POWER7
4513 || rs6000_tune
== PROCESSOR_POWER8
);
4514 rs6000_align_branch_targets
= (rs6000_tune
== PROCESSOR_POWER4
4515 || rs6000_tune
== PROCESSOR_POWER5
4516 || rs6000_tune
== PROCESSOR_POWER6
4517 || rs6000_tune
== PROCESSOR_POWER7
4518 || rs6000_tune
== PROCESSOR_POWER8
4519 || rs6000_tune
== PROCESSOR_POWER9
4520 || rs6000_tune
== PROCESSOR_PPCE500MC
4521 || rs6000_tune
== PROCESSOR_PPCE500MC64
4522 || rs6000_tune
== PROCESSOR_PPCE5500
4523 || rs6000_tune
== PROCESSOR_PPCE6500
);
4525 /* Allow debug switches to override the above settings. These are set to -1
4526 in rs6000.opt to indicate the user hasn't directly set the switch. */
4527 if (TARGET_ALWAYS_HINT
>= 0)
4528 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
4530 if (TARGET_SCHED_GROUPS
>= 0)
4531 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
4533 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
4534 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
4536 rs6000_sched_restricted_insns_priority
4537 = (rs6000_sched_groups
? 1 : 0);
4539 /* Handle -msched-costly-dep option. */
4540 rs6000_sched_costly_dep
4541 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
4543 if (rs6000_sched_costly_dep_str
)
4545 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
4546 rs6000_sched_costly_dep
= no_dep_costly
;
4547 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
4548 rs6000_sched_costly_dep
= all_deps_costly
;
4549 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
4550 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
4551 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
4552 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
4554 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
4555 atoi (rs6000_sched_costly_dep_str
));
4558 /* Handle -minsert-sched-nops option. */
4559 rs6000_sched_insert_nops
4560 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
4562 if (rs6000_sched_insert_nops_str
)
4564 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
4565 rs6000_sched_insert_nops
= sched_finish_none
;
4566 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
4567 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
4568 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
4569 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
4571 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
4572 atoi (rs6000_sched_insert_nops_str
));
4575 /* Handle stack protector */
4576 if (!global_options_set
.x_rs6000_stack_protector_guard
)
4577 #ifdef TARGET_THREAD_SSP_OFFSET
4578 rs6000_stack_protector_guard
= SSP_TLS
;
4580 rs6000_stack_protector_guard
= SSP_GLOBAL
;
4583 #ifdef TARGET_THREAD_SSP_OFFSET
4584 rs6000_stack_protector_guard_offset
= TARGET_THREAD_SSP_OFFSET
;
4585 rs6000_stack_protector_guard_reg
= TARGET_64BIT
? 13 : 2;
4588 if (global_options_set
.x_rs6000_stack_protector_guard_offset_str
)
4591 const char *str
= rs6000_stack_protector_guard_offset_str
;
4594 long offset
= strtol (str
, &endp
, 0);
4595 if (!*str
|| *endp
|| errno
)
4596 error ("%qs is not a valid number in %qs", str
,
4597 "-mstack-protector-guard-offset=");
4599 if (!IN_RANGE (offset
, -0x8000, 0x7fff)
4600 || (TARGET_64BIT
&& (offset
& 3)))
4601 error ("%qs is not a valid offset in %qs", str
,
4602 "-mstack-protector-guard-offset=");
4604 rs6000_stack_protector_guard_offset
= offset
;
4607 if (global_options_set
.x_rs6000_stack_protector_guard_reg_str
)
4609 const char *str
= rs6000_stack_protector_guard_reg_str
;
4610 int reg
= decode_reg_name (str
);
4612 if (!IN_RANGE (reg
, 1, 31))
4613 error ("%qs is not a valid base register in %qs", str
,
4614 "-mstack-protector-guard-reg=");
4616 rs6000_stack_protector_guard_reg
= reg
;
4619 if (rs6000_stack_protector_guard
== SSP_TLS
4620 && !IN_RANGE (rs6000_stack_protector_guard_reg
, 1, 31))
4621 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4625 #ifdef TARGET_REGNAMES
4626 /* If the user desires alternate register names, copy in the
4627 alternate names now. */
4628 if (TARGET_REGNAMES
)
4629 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
4632 /* Set aix_struct_return last, after the ABI is determined.
4633 If -maix-struct-return or -msvr4-struct-return was explicitly
4634 used, don't override with the ABI default. */
4635 if (!global_options_set
.x_aix_struct_return
)
4636 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
4639 /* IBM XL compiler defaults to unsigned bitfields. */
4640 if (TARGET_XL_COMPAT
)
4641 flag_signed_bitfields
= 0;
4644 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
4645 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
4647 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
4649 /* We can only guarantee the availability of DI pseudo-ops when
4650 assembling for 64-bit targets. */
4653 targetm
.asm_out
.aligned_op
.di
= NULL
;
4654 targetm
.asm_out
.unaligned_op
.di
= NULL
;
4658 /* Set branch target alignment, if not optimizing for size. */
4661 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4662 aligned 8byte to avoid misprediction by the branch predictor. */
4663 if (rs6000_tune
== PROCESSOR_TITAN
4664 || rs6000_tune
== PROCESSOR_CELL
)
4666 if (flag_align_functions
&& !str_align_functions
)
4667 str_align_functions
= "8";
4668 if (flag_align_jumps
&& !str_align_jumps
)
4669 str_align_jumps
= "8";
4670 if (flag_align_loops
&& !str_align_loops
)
4671 str_align_loops
= "8";
4673 if (rs6000_align_branch_targets
)
4675 if (flag_align_functions
&& !str_align_functions
)
4676 str_align_functions
= "16";
4677 if (flag_align_jumps
&& !str_align_jumps
)
4678 str_align_jumps
= "16";
4679 if (flag_align_loops
&& !str_align_loops
)
4681 can_override_loop_align
= 1;
4682 str_align_loops
= "16";
4686 if (flag_align_jumps
&& !str_align_jumps
)
4687 str_align_jumps
= "16";
4688 if (flag_align_loops
&& !str_align_loops
)
4689 str_align_loops
= "16";
4692 /* Arrange to save and restore machine status around nested functions. */
4693 init_machine_status
= rs6000_init_machine_status
;
4695 /* We should always be splitting complex arguments, but we can't break
4696 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4697 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
4698 targetm
.calls
.split_complex_arg
= NULL
;
4700 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4701 if (DEFAULT_ABI
== ABI_AIX
)
4702 targetm
.calls
.custom_function_descriptors
= 0;
4705 /* Initialize rs6000_cost with the appropriate target costs. */
4707 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
4709 switch (rs6000_tune
)
4711 case PROCESSOR_RS64A
:
4712 rs6000_cost
= &rs64a_cost
;
4715 case PROCESSOR_MPCCORE
:
4716 rs6000_cost
= &mpccore_cost
;
4719 case PROCESSOR_PPC403
:
4720 rs6000_cost
= &ppc403_cost
;
4723 case PROCESSOR_PPC405
:
4724 rs6000_cost
= &ppc405_cost
;
4727 case PROCESSOR_PPC440
:
4728 rs6000_cost
= &ppc440_cost
;
4731 case PROCESSOR_PPC476
:
4732 rs6000_cost
= &ppc476_cost
;
4735 case PROCESSOR_PPC601
:
4736 rs6000_cost
= &ppc601_cost
;
4739 case PROCESSOR_PPC603
:
4740 rs6000_cost
= &ppc603_cost
;
4743 case PROCESSOR_PPC604
:
4744 rs6000_cost
= &ppc604_cost
;
4747 case PROCESSOR_PPC604e
:
4748 rs6000_cost
= &ppc604e_cost
;
4751 case PROCESSOR_PPC620
:
4752 rs6000_cost
= &ppc620_cost
;
4755 case PROCESSOR_PPC630
:
4756 rs6000_cost
= &ppc630_cost
;
4759 case PROCESSOR_CELL
:
4760 rs6000_cost
= &ppccell_cost
;
4763 case PROCESSOR_PPC750
:
4764 case PROCESSOR_PPC7400
:
4765 rs6000_cost
= &ppc750_cost
;
4768 case PROCESSOR_PPC7450
:
4769 rs6000_cost
= &ppc7450_cost
;
4772 case PROCESSOR_PPC8540
:
4773 case PROCESSOR_PPC8548
:
4774 rs6000_cost
= &ppc8540_cost
;
4777 case PROCESSOR_PPCE300C2
:
4778 case PROCESSOR_PPCE300C3
:
4779 rs6000_cost
= &ppce300c2c3_cost
;
4782 case PROCESSOR_PPCE500MC
:
4783 rs6000_cost
= &ppce500mc_cost
;
4786 case PROCESSOR_PPCE500MC64
:
4787 rs6000_cost
= &ppce500mc64_cost
;
4790 case PROCESSOR_PPCE5500
:
4791 rs6000_cost
= &ppce5500_cost
;
4794 case PROCESSOR_PPCE6500
:
4795 rs6000_cost
= &ppce6500_cost
;
4798 case PROCESSOR_TITAN
:
4799 rs6000_cost
= &titan_cost
;
4802 case PROCESSOR_POWER4
:
4803 case PROCESSOR_POWER5
:
4804 rs6000_cost
= &power4_cost
;
4807 case PROCESSOR_POWER6
:
4808 rs6000_cost
= &power6_cost
;
4811 case PROCESSOR_POWER7
:
4812 rs6000_cost
= &power7_cost
;
4815 case PROCESSOR_POWER8
:
4816 rs6000_cost
= &power8_cost
;
4819 case PROCESSOR_POWER9
:
4820 rs6000_cost
= &power9_cost
;
4823 case PROCESSOR_PPCA2
:
4824 rs6000_cost
= &ppca2_cost
;
4833 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
4834 rs6000_cost
->simultaneous_prefetches
,
4835 global_options
.x_param_values
,
4836 global_options_set
.x_param_values
);
4837 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
4838 global_options
.x_param_values
,
4839 global_options_set
.x_param_values
);
4840 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
4841 rs6000_cost
->cache_line_size
,
4842 global_options
.x_param_values
,
4843 global_options_set
.x_param_values
);
4844 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
4845 global_options
.x_param_values
,
4846 global_options_set
.x_param_values
);
4848 /* Increase loop peeling limits based on performance analysis. */
4849 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
4850 global_options
.x_param_values
,
4851 global_options_set
.x_param_values
);
4852 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
4853 global_options
.x_param_values
,
4854 global_options_set
.x_param_values
);
4856 /* Use the 'model' -fsched-pressure algorithm by default. */
4857 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
,
4858 SCHED_PRESSURE_MODEL
,
4859 global_options
.x_param_values
,
4860 global_options_set
.x_param_values
);
4862 /* If using typedef char *va_list, signal that
4863 __builtin_va_start (&ap, 0) can be optimized to
4864 ap = __builtin_next_arg (0). */
4865 if (DEFAULT_ABI
!= ABI_V4
)
4866 targetm
.expand_builtin_va_start
= NULL
;
4869 /* If not explicitly specified via option, decide whether to generate indexed
4870 load/store instructions. A value of -1 indicates that the
4871 initial value of this variable has not been overwritten. During
4872 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4873 if (TARGET_AVOID_XFORM
== -1)
4874 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4875 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4876 need indexed accesses and the type used is the scalar type of the element
4877 being loaded or stored. */
4878 TARGET_AVOID_XFORM
= (rs6000_tune
== PROCESSOR_POWER6
&& TARGET_CMPB
4879 && !TARGET_ALTIVEC
);
4881 /* Set the -mrecip options. */
4882 if (rs6000_recip_name
)
4884 char *p
= ASTRDUP (rs6000_recip_name
);
4886 unsigned int mask
, i
;
4889 while ((q
= strtok (p
, ",")) != NULL
)
4900 if (!strcmp (q
, "default"))
4901 mask
= ((TARGET_RECIP_PRECISION
)
4902 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
4905 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
4906 if (!strcmp (q
, recip_options
[i
].string
))
4908 mask
= recip_options
[i
].mask
;
4912 if (i
== ARRAY_SIZE (recip_options
))
4914 error ("unknown option for %<%s=%s%>", "-mrecip", q
);
4922 rs6000_recip_control
&= ~mask
;
4924 rs6000_recip_control
|= mask
;
4928 /* Set the builtin mask of the various options used that could affect which
4929 builtins were used. In the past we used target_flags, but we've run out
4930 of bits, and some options are no longer in target_flags. */
4931 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4932 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4933 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
4934 rs6000_builtin_mask
);
4936 /* Initialize all of the registers. */
4937 rs6000_init_hard_regno_mode_ok (global_init_p
);
4939 /* Save the initial options in case the user does function specific options */
4941 target_option_default_node
= target_option_current_node
4942 = build_target_option_node (&global_options
);
4944 /* If not explicitly specified via option, decide whether to generate the
4945 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4946 if (TARGET_LINK_STACK
== -1)
4947 SET_TARGET_LINK_STACK (rs6000_tune
== PROCESSOR_PPC476
&& flag_pic
);
4949 /* Deprecate use of -mno-speculate-indirect-jumps. */
4950 if (!rs6000_speculate_indirect_jumps
)
4951 warning (0, "%qs is deprecated and not recommended in any circumstances",
4952 "-mno-speculate-indirect-jumps");
4957 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4958 define the target cpu type. */
4961 rs6000_option_override (void)
4963 (void) rs6000_option_override_internal (true);
4967 /* Implement targetm.vectorize.builtin_mask_for_load. */
4969 rs6000_builtin_mask_for_load (void)
4971 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4972 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
4973 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
4974 return altivec_builtin_mask_for_load
;
4979 /* Implement LOOP_ALIGN. */
4981 rs6000_loop_align (rtx label
)
4986 /* Don't override loop alignment if -falign-loops was specified. */
4987 if (!can_override_loop_align
)
4990 bb
= BLOCK_FOR_INSN (label
);
4991 ninsns
= num_loop_insns(bb
->loop_father
);
4993 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4994 if (ninsns
> 4 && ninsns
<= 8
4995 && (rs6000_tune
== PROCESSOR_POWER4
4996 || rs6000_tune
== PROCESSOR_POWER5
4997 || rs6000_tune
== PROCESSOR_POWER6
4998 || rs6000_tune
== PROCESSOR_POWER7
4999 || rs6000_tune
== PROCESSOR_POWER8
))
5000 return align_flags (5);
5005 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5006 after applying N number of iterations. This routine does not determine
5007 how may iterations are required to reach desired alignment. */
5010 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
5017 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
5020 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
5030 /* Assuming that all other types are naturally aligned. CHECKME! */
5035 /* Return true if the vector misalignment factor is supported by the
5038 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
5045 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5048 /* Return if movmisalign pattern is not supported for this mode. */
5049 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
5052 if (misalignment
== -1)
5054 /* Misalignment factor is unknown at compile time but we know
5055 it's word aligned. */
5056 if (rs6000_vector_alignment_reachable (type
, is_packed
))
5058 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
5060 if (element_size
== 64 || element_size
== 32)
5067 /* VSX supports word-aligned vector. */
5068 if (misalignment
% 4 == 0)
5074 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5076 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
5077 tree vectype
, int misalign
)
5082 switch (type_of_cost
)
5092 case cond_branch_not_taken
:
5101 case vec_promote_demote
:
5107 case cond_branch_taken
:
5110 case unaligned_load
:
5111 case vector_gather_load
:
5112 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5115 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5117 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5119 /* Double word aligned. */
5127 /* Double word aligned. */
5131 /* Unknown misalignment. */
5144 /* Misaligned loads are not supported. */
5149 case unaligned_store
:
5150 case vector_scatter_store
:
5151 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5154 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5156 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5158 /* Double word aligned. */
5166 /* Double word aligned. */
5170 /* Unknown misalignment. */
5183 /* Misaligned stores are not supported. */
5189 /* This is a rough approximation assuming non-constant elements
5190 constructed into a vector via element insertion. FIXME:
5191 vec_construct is not granular enough for uniformly good
5192 decisions. If the initialization is a splat, this is
5193 cheaper than we estimate. Improve this someday. */
5194 elem_type
= TREE_TYPE (vectype
);
5195 /* 32-bit vectors loaded into registers are stored as double
5196 precision, so we need 2 permutes, 2 converts, and 1 merge
5197 to construct a vector of short floats from them. */
5198 if (SCALAR_FLOAT_TYPE_P (elem_type
)
5199 && TYPE_PRECISION (elem_type
) == 32)
5201 /* On POWER9, integer vector types are built up in GPRs and then
5202 use a direct move (2 cycles). For POWER8 this is even worse,
5203 as we need two direct moves and a merge, and the direct moves
5205 else if (INTEGRAL_TYPE_P (elem_type
))
5207 if (TARGET_P9_VECTOR
)
5208 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 2;
5210 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 5;
5213 /* V2DFmode doesn't need a direct move. */
5221 /* Implement targetm.vectorize.preferred_simd_mode. */
5224 rs6000_preferred_simd_mode (scalar_mode mode
)
5233 if (TARGET_ALTIVEC
|| TARGET_VSX
)
5253 typedef struct _rs6000_cost_data
5255 struct loop
*loop_info
;
5259 /* Test for likely overcommitment of vector hardware resources. If a
5260 loop iteration is relatively large, and too large a percentage of
5261 instructions in the loop are vectorized, the cost model may not
5262 adequately reflect delays from unavailable vector resources.
5263 Penalize the loop body cost for this case. */
5266 rs6000_density_test (rs6000_cost_data
*data
)
5268 const int DENSITY_PCT_THRESHOLD
= 85;
5269 const int DENSITY_SIZE_THRESHOLD
= 70;
5270 const int DENSITY_PENALTY
= 10;
5271 struct loop
*loop
= data
->loop_info
;
5272 basic_block
*bbs
= get_loop_body (loop
);
5273 int nbbs
= loop
->num_nodes
;
5274 loop_vec_info loop_vinfo
= loop_vec_info_for_loop (data
->loop_info
);
5275 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
5278 for (i
= 0; i
< nbbs
; i
++)
5280 basic_block bb
= bbs
[i
];
5281 gimple_stmt_iterator gsi
;
5283 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
5285 gimple
*stmt
= gsi_stmt (gsi
);
5286 stmt_vec_info stmt_info
= loop_vinfo
->lookup_stmt (stmt
);
5288 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
5289 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
5295 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
5297 if (density_pct
> DENSITY_PCT_THRESHOLD
5298 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
5300 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
5301 if (dump_enabled_p ())
5302 dump_printf_loc (MSG_NOTE
, vect_location
,
5303 "density %d%%, cost %d exceeds threshold, penalizing "
5304 "loop body cost by %d%%", density_pct
,
5305 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
5309 /* Implement targetm.vectorize.init_cost. */
5311 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5312 instruction is needed by the vectorization. */
5313 static bool rs6000_vect_nonmem
;
5316 rs6000_init_cost (struct loop
*loop_info
)
5318 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
5319 data
->loop_info
= loop_info
;
5320 data
->cost
[vect_prologue
] = 0;
5321 data
->cost
[vect_body
] = 0;
5322 data
->cost
[vect_epilogue
] = 0;
5323 rs6000_vect_nonmem
= false;
5327 /* Implement targetm.vectorize.add_stmt_cost. */
5330 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
5331 struct _stmt_vec_info
*stmt_info
, int misalign
,
5332 enum vect_cost_model_location where
)
5334 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5335 unsigned retval
= 0;
5337 if (flag_vect_cost_model
)
5339 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
5340 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
5342 /* Statements in an inner loop relative to the loop being
5343 vectorized are weighted more heavily. The value here is
5344 arbitrary and could potentially be improved with analysis. */
5345 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
5346 count
*= 50; /* FIXME. */
5348 retval
= (unsigned) (count
* stmt_cost
);
5349 cost_data
->cost
[where
] += retval
;
5351 /* Check whether we're doing something other than just a copy loop.
5352 Not all such loops may be profitably vectorized; see
5353 rs6000_finish_cost. */
5354 if ((kind
== vec_to_scalar
|| kind
== vec_perm
5355 || kind
== vec_promote_demote
|| kind
== vec_construct
5356 || kind
== scalar_to_vec
)
5357 || (where
== vect_body
&& kind
== vector_stmt
))
5358 rs6000_vect_nonmem
= true;
5364 /* Implement targetm.vectorize.finish_cost. */
5367 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
5368 unsigned *body_cost
, unsigned *epilogue_cost
)
5370 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5372 if (cost_data
->loop_info
)
5373 rs6000_density_test (cost_data
);
5375 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5376 that require versioning for any reason. The vectorization is at
5377 best a wash inside the loop, and the versioning checks make
5378 profitability highly unlikely and potentially quite harmful. */
5379 if (cost_data
->loop_info
)
5381 loop_vec_info vec_info
= loop_vec_info_for_loop (cost_data
->loop_info
);
5382 if (!rs6000_vect_nonmem
5383 && LOOP_VINFO_VECT_FACTOR (vec_info
) == 2
5384 && LOOP_REQUIRES_VERSIONING (vec_info
))
5385 cost_data
->cost
[vect_body
] += 10000;
5388 *prologue_cost
= cost_data
->cost
[vect_prologue
];
5389 *body_cost
= cost_data
->cost
[vect_body
];
5390 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
5393 /* Implement targetm.vectorize.destroy_cost_data. */
5396 rs6000_destroy_cost_data (void *data
)
5401 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5402 library with vectorized intrinsics. */
5405 rs6000_builtin_vectorized_libmass (combined_fn fn
, tree type_out
,
5409 const char *suffix
= NULL
;
5410 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
5413 machine_mode el_mode
, in_mode
;
5416 /* Libmass is suitable for unsafe math only as it does not correctly support
5417 parts of IEEE with the required precision such as denormals. Only support
5418 it if we have VSX to use the simd d2 or f4 functions.
5419 XXX: Add variable length support. */
5420 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
5423 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5424 n
= TYPE_VECTOR_SUBPARTS (type_out
);
5425 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5426 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5427 if (el_mode
!= in_mode
5463 if (el_mode
== DFmode
&& n
== 2)
5465 bdecl
= mathfn_built_in (double_type_node
, fn
);
5466 suffix
= "d2"; /* pow -> powd2 */
5468 else if (el_mode
== SFmode
&& n
== 4)
5470 bdecl
= mathfn_built_in (float_type_node
, fn
);
5471 suffix
= "4"; /* powf -> powf4 */
5483 gcc_assert (suffix
!= NULL
);
5484 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
5488 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
5489 strcat (name
, suffix
);
5492 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
5493 else if (n_args
== 2)
5494 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
5498 /* Build a function declaration for the vectorized function. */
5499 new_fndecl
= build_decl (BUILTINS_LOCATION
,
5500 FUNCTION_DECL
, get_identifier (name
), fntype
);
5501 TREE_PUBLIC (new_fndecl
) = 1;
5502 DECL_EXTERNAL (new_fndecl
) = 1;
5503 DECL_IS_NOVOPS (new_fndecl
) = 1;
5504 TREE_READONLY (new_fndecl
) = 1;
5509 /* Returns a function decl for a vectorized version of the builtin function
5510 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5511 if it is not available. */
5514 rs6000_builtin_vectorized_function (unsigned int fn
, tree type_out
,
5517 machine_mode in_mode
, out_mode
;
5520 if (TARGET_DEBUG_BUILTIN
)
5521 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5522 combined_fn_name (combined_fn (fn
)),
5523 GET_MODE_NAME (TYPE_MODE (type_out
)),
5524 GET_MODE_NAME (TYPE_MODE (type_in
)));
5526 if (TREE_CODE (type_out
) != VECTOR_TYPE
5527 || TREE_CODE (type_in
) != VECTOR_TYPE
)
5530 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5531 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5532 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5533 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5538 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5539 && out_mode
== DFmode
&& out_n
== 2
5540 && in_mode
== DFmode
&& in_n
== 2)
5541 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
5542 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5543 && out_mode
== SFmode
&& out_n
== 4
5544 && in_mode
== SFmode
&& in_n
== 4)
5545 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
5546 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5547 && out_mode
== SFmode
&& out_n
== 4
5548 && in_mode
== SFmode
&& in_n
== 4)
5549 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
5552 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5553 && out_mode
== DFmode
&& out_n
== 2
5554 && in_mode
== DFmode
&& in_n
== 2)
5555 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
5556 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5557 && out_mode
== SFmode
&& out_n
== 4
5558 && in_mode
== SFmode
&& in_n
== 4)
5559 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
5560 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5561 && out_mode
== SFmode
&& out_n
== 4
5562 && in_mode
== SFmode
&& in_n
== 4)
5563 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
5566 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5567 && out_mode
== DFmode
&& out_n
== 2
5568 && in_mode
== DFmode
&& in_n
== 2)
5569 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
5570 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5571 && out_mode
== SFmode
&& out_n
== 4
5572 && in_mode
== SFmode
&& in_n
== 4)
5573 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
5574 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5575 && out_mode
== SFmode
&& out_n
== 4
5576 && in_mode
== SFmode
&& in_n
== 4)
5577 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
5580 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5581 && out_mode
== DFmode
&& out_n
== 2
5582 && in_mode
== DFmode
&& in_n
== 2)
5583 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
5584 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5585 && out_mode
== SFmode
&& out_n
== 4
5586 && in_mode
== SFmode
&& in_n
== 4)
5587 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
5588 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5589 && out_mode
== SFmode
&& out_n
== 4
5590 && in_mode
== SFmode
&& in_n
== 4)
5591 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5594 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5595 && out_mode
== DFmode
&& out_n
== 2
5596 && in_mode
== DFmode
&& in_n
== 2)
5597 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5598 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5599 && out_mode
== SFmode
&& out_n
== 4
5600 && in_mode
== SFmode
&& in_n
== 4)
5601 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5602 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5603 && out_mode
== SFmode
&& out_n
== 4
5604 && in_mode
== SFmode
&& in_n
== 4)
5605 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5608 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5609 && flag_unsafe_math_optimizations
5610 && out_mode
== DFmode
&& out_n
== 2
5611 && in_mode
== DFmode
&& in_n
== 2)
5612 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5613 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5614 && flag_unsafe_math_optimizations
5615 && out_mode
== SFmode
&& out_n
== 4
5616 && in_mode
== SFmode
&& in_n
== 4)
5617 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
5620 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5621 && !flag_trapping_math
5622 && out_mode
== DFmode
&& out_n
== 2
5623 && in_mode
== DFmode
&& in_n
== 2)
5624 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
5625 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5626 && !flag_trapping_math
5627 && out_mode
== SFmode
&& out_n
== 4
5628 && in_mode
== SFmode
&& in_n
== 4)
5629 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
5635 /* Generate calls to libmass if appropriate. */
5636 if (rs6000_veclib_handler
)
5637 return rs6000_veclib_handler (combined_fn (fn
), type_out
, type_in
);
5642 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5645 rs6000_builtin_md_vectorized_function (tree fndecl
, tree type_out
,
5648 machine_mode in_mode
, out_mode
;
5651 if (TARGET_DEBUG_BUILTIN
)
5652 fprintf (stderr
, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5653 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
5654 GET_MODE_NAME (TYPE_MODE (type_out
)),
5655 GET_MODE_NAME (TYPE_MODE (type_in
)));
5657 if (TREE_CODE (type_out
) != VECTOR_TYPE
5658 || TREE_CODE (type_in
) != VECTOR_TYPE
)
5661 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5662 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5663 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5664 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5666 enum rs6000_builtins fn
5667 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
5670 case RS6000_BUILTIN_RSQRTF
:
5671 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5672 && out_mode
== SFmode
&& out_n
== 4
5673 && in_mode
== SFmode
&& in_n
== 4)
5674 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
5676 case RS6000_BUILTIN_RSQRT
:
5677 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5678 && out_mode
== DFmode
&& out_n
== 2
5679 && in_mode
== DFmode
&& in_n
== 2)
5680 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
5682 case RS6000_BUILTIN_RECIPF
:
5683 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5684 && out_mode
== SFmode
&& out_n
== 4
5685 && in_mode
== SFmode
&& in_n
== 4)
5686 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
5688 case RS6000_BUILTIN_RECIP
:
5689 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5690 && out_mode
== DFmode
&& out_n
== 2
5691 && in_mode
== DFmode
&& in_n
== 2)
5692 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
5700 /* Default CPU string for rs6000*_file_start functions. */
5701 static const char *rs6000_default_cpu
;
5703 /* Do anything needed at the start of the asm file. */
5706 rs6000_file_start (void)
5709 const char *start
= buffer
;
5710 FILE *file
= asm_out_file
;
5712 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
5714 default_file_start ();
5716 if (flag_verbose_asm
)
5718 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
5720 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
5722 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
5726 if (global_options_set
.x_rs6000_cpu_index
)
5728 fprintf (file
, "%s -mcpu=%s", start
,
5729 processor_target_table
[rs6000_cpu_index
].name
);
5733 if (global_options_set
.x_rs6000_tune_index
)
5735 fprintf (file
, "%s -mtune=%s", start
,
5736 processor_target_table
[rs6000_tune_index
].name
);
5740 if (PPC405_ERRATUM77
)
5742 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
5746 #ifdef USING_ELFOS_H
5747 switch (rs6000_sdata
)
5749 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
5750 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
5751 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
5752 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
5755 if (rs6000_sdata
&& g_switch_value
)
5757 fprintf (file
, "%s -G %d", start
,
5767 #ifdef USING_ELFOS_H
5768 if (!(rs6000_default_cpu
&& rs6000_default_cpu
[0])
5769 && !global_options_set
.x_rs6000_cpu_index
)
5771 fputs ("\t.machine ", asm_out_file
);
5772 if ((rs6000_isa_flags
& OPTION_MASK_MODULO
) != 0)
5773 fputs ("power9\n", asm_out_file
);
5774 else if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
5775 fputs ("power8\n", asm_out_file
);
5776 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
5777 fputs ("power7\n", asm_out_file
);
5778 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
5779 fputs ("power6\n", asm_out_file
);
5780 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
5781 fputs ("power5\n", asm_out_file
);
5782 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
5783 fputs ("power4\n", asm_out_file
);
5784 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
5785 fputs ("ppc64\n", asm_out_file
);
5787 fputs ("ppc\n", asm_out_file
);
5791 if (DEFAULT_ABI
== ABI_ELFv2
)
5792 fprintf (file
, "\t.abiversion 2\n");
5796 /* Return nonzero if this function is known to have a null epilogue. */
5799 direct_return (void)
5801 if (reload_completed
)
5803 rs6000_stack_t
*info
= rs6000_stack_info ();
5805 if (info
->first_gp_reg_save
== 32
5806 && info
->first_fp_reg_save
== 64
5807 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
5808 && ! info
->lr_save_p
5809 && ! info
->cr_save_p
5810 && info
->vrsave_size
== 0
5818 /* Return the number of instructions it takes to form a constant in an
5819 integer register. */
5822 num_insns_constant_wide (HOST_WIDE_INT value
)
5824 /* signed constant loadable with addi */
5825 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
5828 /* constant loadable with addis */
5829 else if ((value
& 0xffff) == 0
5830 && (value
>> 31 == -1 || value
>> 31 == 0))
5833 else if (TARGET_POWERPC64
)
5835 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
5836 HOST_WIDE_INT high
= value
>> 31;
5838 if (high
== 0 || high
== -1)
5844 return num_insns_constant_wide (high
) + 1;
5846 return num_insns_constant_wide (low
) + 1;
5848 return (num_insns_constant_wide (high
)
5849 + num_insns_constant_wide (low
) + 1);
5857 num_insns_constant (rtx op
, machine_mode mode
)
5859 HOST_WIDE_INT low
, high
;
5861 switch (GET_CODE (op
))
5864 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
5865 && rs6000_is_valid_and_mask (op
, mode
))
5868 return num_insns_constant_wide (INTVAL (op
));
5870 case CONST_WIDE_INT
:
5873 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
5874 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
5875 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
5880 if (mode
== SFmode
|| mode
== SDmode
)
5884 if (DECIMAL_FLOAT_MODE_P (mode
))
5885 REAL_VALUE_TO_TARGET_DECIMAL32
5886 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5888 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5889 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
5893 if (DECIMAL_FLOAT_MODE_P (mode
))
5894 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5896 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5897 high
= l
[WORDS_BIG_ENDIAN
== 0];
5898 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5901 return (num_insns_constant_wide (low
)
5902 + num_insns_constant_wide (high
));
5905 if ((high
== 0 && low
>= 0)
5906 || (high
== -1 && low
< 0))
5907 return num_insns_constant_wide (low
);
5909 else if (rs6000_is_valid_and_mask (op
, mode
))
5913 return num_insns_constant_wide (high
) + 1;
5916 return (num_insns_constant_wide (high
)
5917 + num_insns_constant_wide (low
) + 1);
5925 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5926 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5927 corresponding element of the vector, but for V4SFmode, the
5928 corresponding "float" is interpreted as an SImode integer. */
5931 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5935 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5936 gcc_assert (GET_MODE (op
) != V2DImode
5937 && GET_MODE (op
) != V2DFmode
);
5939 tmp
= CONST_VECTOR_ELT (op
, elt
);
5940 if (GET_MODE (op
) == V4SFmode
)
5941 tmp
= gen_lowpart (SImode
, tmp
);
5942 return INTVAL (tmp
);
5945 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5946 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5947 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5948 all items are set to the same value and contain COPIES replicas of the
5949 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5950 operand and the others are set to the value of the operand's msb. */
5953 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5955 machine_mode mode
= GET_MODE (op
);
5956 machine_mode inner
= GET_MODE_INNER (mode
);
5964 HOST_WIDE_INT splat_val
;
5965 HOST_WIDE_INT msb_val
;
5967 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5970 nunits
= GET_MODE_NUNITS (mode
);
5971 bitsize
= GET_MODE_BITSIZE (inner
);
5972 mask
= GET_MODE_MASK (inner
);
5974 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5976 msb_val
= val
>= 0 ? 0 : -1;
5978 /* Construct the value to be splatted, if possible. If not, return 0. */
5979 for (i
= 2; i
<= copies
; i
*= 2)
5981 HOST_WIDE_INT small_val
;
5983 small_val
= splat_val
>> bitsize
;
5985 if (splat_val
!= ((HOST_WIDE_INT
)
5986 ((unsigned HOST_WIDE_INT
) small_val
<< bitsize
)
5987 | (small_val
& mask
)))
5989 splat_val
= small_val
;
5992 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5993 if (EASY_VECTOR_15 (splat_val
))
5996 /* Also check if we can splat, and then add the result to itself. Do so if
5997 the value is positive, of if the splat instruction is using OP's mode;
5998 for splat_val < 0, the splat and the add should use the same mode. */
5999 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
6000 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
6003 /* Also check if are loading up the most significant bit which can be done by
6004 loading up -1 and shifting the value left by -1. */
6005 else if (EASY_VECTOR_MSB (splat_val
, inner
))
6011 /* Check if VAL is present in every STEP-th element, and the
6012 other elements are filled with its most significant bit. */
6013 for (i
= 1; i
< nunits
; ++i
)
6015 HOST_WIDE_INT desired_val
;
6016 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
6017 if ((i
& (step
- 1)) == 0)
6020 desired_val
= msb_val
;
6022 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
6029 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6030 instruction, filling in the bottom elements with 0 or -1.
6032 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6033 for the number of zeroes to shift in, or negative for the number of 0xff
6036 OP is a CONST_VECTOR. */
6039 vspltis_shifted (rtx op
)
6041 machine_mode mode
= GET_MODE (op
);
6042 machine_mode inner
= GET_MODE_INNER (mode
);
6050 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
)
6053 /* We need to create pseudo registers to do the shift, so don't recognize
6054 shift vector constants after reload. */
6055 if (!can_create_pseudo_p ())
6058 nunits
= GET_MODE_NUNITS (mode
);
6059 mask
= GET_MODE_MASK (inner
);
6061 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? 0 : nunits
- 1);
6063 /* Check if the value can really be the operand of a vspltis[bhw]. */
6064 if (EASY_VECTOR_15 (val
))
6067 /* Also check if we are loading up the most significant bit which can be done
6068 by loading up -1 and shifting the value left by -1. */
6069 else if (EASY_VECTOR_MSB (val
, inner
))
6075 /* Check if VAL is present in every STEP-th element until we find elements
6076 that are 0 or all 1 bits. */
6077 for (i
= 1; i
< nunits
; ++i
)
6079 unsigned elt
= BYTES_BIG_ENDIAN
? i
: nunits
- 1 - i
;
6080 HOST_WIDE_INT elt_val
= const_vector_elt_as_int (op
, elt
);
6082 /* If the value isn't the splat value, check for the remaining elements
6088 for (j
= i
+1; j
< nunits
; ++j
)
6090 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6091 if (const_vector_elt_as_int (op
, elt2
) != 0)
6095 return (nunits
- i
) * GET_MODE_SIZE (inner
);
6098 else if ((elt_val
& mask
) == mask
)
6100 for (j
= i
+1; j
< nunits
; ++j
)
6102 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6103 if ((const_vector_elt_as_int (op
, elt2
) & mask
) != mask
)
6107 return -((nunits
- i
) * GET_MODE_SIZE (inner
));
6115 /* If all elements are equal, we don't need to do VLSDOI. */
6120 /* Return true if OP is of the given MODE and can be synthesized
6121 with a vspltisb, vspltish or vspltisw. */
6124 easy_altivec_constant (rtx op
, machine_mode mode
)
6126 unsigned step
, copies
;
6128 if (mode
== VOIDmode
)
6129 mode
= GET_MODE (op
);
6130 else if (mode
!= GET_MODE (op
))
6133 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6135 if (mode
== V2DFmode
)
6136 return zero_constant (op
, mode
);
6138 else if (mode
== V2DImode
)
6140 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
6141 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
6144 if (zero_constant (op
, mode
))
6147 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
6148 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
6154 /* V1TImode is a special container for TImode. Ignore for now. */
6155 else if (mode
== V1TImode
)
6158 /* Start with a vspltisw. */
6159 step
= GET_MODE_NUNITS (mode
) / 4;
6162 if (vspltis_constant (op
, step
, copies
))
6165 /* Then try with a vspltish. */
6171 if (vspltis_constant (op
, step
, copies
))
6174 /* And finally a vspltisb. */
6180 if (vspltis_constant (op
, step
, copies
))
6183 if (vspltis_shifted (op
) != 0)
6189 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6190 result is OP. Abort if it is not possible. */
6193 gen_easy_altivec_constant (rtx op
)
6195 machine_mode mode
= GET_MODE (op
);
6196 int nunits
= GET_MODE_NUNITS (mode
);
6197 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6198 unsigned step
= nunits
/ 4;
6199 unsigned copies
= 1;
6201 /* Start with a vspltisw. */
6202 if (vspltis_constant (op
, step
, copies
))
6203 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
6205 /* Then try with a vspltish. */
6211 if (vspltis_constant (op
, step
, copies
))
6212 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
6214 /* And finally a vspltisb. */
6220 if (vspltis_constant (op
, step
, copies
))
6221 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
6226 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6227 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6229 Return the number of instructions needed (1 or 2) into the address pointed
6232 Return the constant that is being split via CONSTANT_PTR. */
6235 xxspltib_constant_p (rtx op
,
6240 size_t nunits
= GET_MODE_NUNITS (mode
);
6242 HOST_WIDE_INT value
;
6245 /* Set the returned values to out of bound values. */
6246 *num_insns_ptr
= -1;
6247 *constant_ptr
= 256;
6249 if (!TARGET_P9_VECTOR
)
6252 if (mode
== VOIDmode
)
6253 mode
= GET_MODE (op
);
6255 else if (mode
!= GET_MODE (op
) && GET_MODE (op
) != VOIDmode
)
6258 /* Handle (vec_duplicate <constant>). */
6259 if (GET_CODE (op
) == VEC_DUPLICATE
)
6261 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6262 && mode
!= V2DImode
)
6265 element
= XEXP (op
, 0);
6266 if (!CONST_INT_P (element
))
6269 value
= INTVAL (element
);
6270 if (!IN_RANGE (value
, -128, 127))
6274 /* Handle (const_vector [...]). */
6275 else if (GET_CODE (op
) == CONST_VECTOR
)
6277 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6278 && mode
!= V2DImode
)
6281 element
= CONST_VECTOR_ELT (op
, 0);
6282 if (!CONST_INT_P (element
))
6285 value
= INTVAL (element
);
6286 if (!IN_RANGE (value
, -128, 127))
6289 for (i
= 1; i
< nunits
; i
++)
6291 element
= CONST_VECTOR_ELT (op
, i
);
6292 if (!CONST_INT_P (element
))
6295 if (value
!= INTVAL (element
))
6300 /* Handle integer constants being loaded into the upper part of the VSX
6301 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6302 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6303 else if (CONST_INT_P (op
))
6305 if (!SCALAR_INT_MODE_P (mode
))
6308 value
= INTVAL (op
);
6309 if (!IN_RANGE (value
, -128, 127))
6312 if (!IN_RANGE (value
, -1, 0))
6314 if (!(reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
))
6317 if (EASY_VECTOR_15 (value
))
6325 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6326 sign extend. Special case 0/-1 to allow getting any VSX register instead
6327 of an Altivec register. */
6328 if ((mode
== V4SImode
|| mode
== V8HImode
) && !IN_RANGE (value
, -1, 0)
6329 && EASY_VECTOR_15 (value
))
6332 /* Return # of instructions and the constant byte for XXSPLTIB. */
6333 if (mode
== V16QImode
)
6336 else if (IN_RANGE (value
, -1, 0))
6342 *constant_ptr
= (int) value
;
6347 output_vec_const_move (rtx
*operands
)
6355 mode
= GET_MODE (dest
);
6359 bool dest_vmx_p
= ALTIVEC_REGNO_P (REGNO (dest
));
6360 int xxspltib_value
= 256;
6363 if (zero_constant (vec
, mode
))
6365 if (TARGET_P9_VECTOR
)
6366 return "xxspltib %x0,0";
6368 else if (dest_vmx_p
)
6369 return "vspltisw %0,0";
6372 return "xxlxor %x0,%x0,%x0";
6375 if (all_ones_constant (vec
, mode
))
6377 if (TARGET_P9_VECTOR
)
6378 return "xxspltib %x0,255";
6380 else if (dest_vmx_p
)
6381 return "vspltisw %0,-1";
6383 else if (TARGET_P8_VECTOR
)
6384 return "xxlorc %x0,%x0,%x0";
6390 if (TARGET_P9_VECTOR
6391 && xxspltib_constant_p (vec
, mode
, &num_insns
, &xxspltib_value
))
6395 operands
[2] = GEN_INT (xxspltib_value
& 0xff);
6396 return "xxspltib %x0,%2";
6407 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest
)));
6408 if (zero_constant (vec
, mode
))
6409 return "vspltisw %0,0";
6411 if (all_ones_constant (vec
, mode
))
6412 return "vspltisw %0,-1";
6414 /* Do we need to construct a value using VSLDOI? */
6415 shift
= vspltis_shifted (vec
);
6419 splat_vec
= gen_easy_altivec_constant (vec
);
6420 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
6421 operands
[1] = XEXP (splat_vec
, 0);
6422 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
6425 switch (GET_MODE (splat_vec
))
6428 return "vspltisw %0,%1";
6431 return "vspltish %0,%1";
6434 return "vspltisb %0,%1";
6444 /* Initialize vector TARGET to VALS. */
6447 rs6000_expand_vector_init (rtx target
, rtx vals
)
6449 machine_mode mode
= GET_MODE (target
);
6450 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6451 int n_elts
= GET_MODE_NUNITS (mode
);
6452 int n_var
= 0, one_var
= -1;
6453 bool all_same
= true, all_const_zero
= true;
6457 for (i
= 0; i
< n_elts
; ++i
)
6459 x
= XVECEXP (vals
, 0, i
);
6460 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6461 ++n_var
, one_var
= i
;
6462 else if (x
!= CONST0_RTX (inner_mode
))
6463 all_const_zero
= false;
6465 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6471 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
6472 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
6473 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
6475 /* Zero register. */
6476 emit_move_insn (target
, CONST0_RTX (mode
));
6479 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
6481 /* Splat immediate. */
6482 emit_insn (gen_rtx_SET (target
, const_vec
));
6487 /* Load from constant pool. */
6488 emit_move_insn (target
, const_vec
);
6493 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6494 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
6498 size_t num_elements
= all_same
? 1 : 2;
6499 for (i
= 0; i
< num_elements
; i
++)
6501 op
[i
] = XVECEXP (vals
, 0, i
);
6502 /* Just in case there is a SUBREG with a smaller mode, do a
6504 if (GET_MODE (op
[i
]) != inner_mode
)
6506 rtx tmp
= gen_reg_rtx (inner_mode
);
6507 convert_move (tmp
, op
[i
], 0);
6510 /* Allow load with splat double word. */
6511 else if (MEM_P (op
[i
]))
6514 op
[i
] = force_reg (inner_mode
, op
[i
]);
6516 else if (!REG_P (op
[i
]))
6517 op
[i
] = force_reg (inner_mode
, op
[i
]);
6522 if (mode
== V2DFmode
)
6523 emit_insn (gen_vsx_splat_v2df (target
, op
[0]));
6525 emit_insn (gen_vsx_splat_v2di (target
, op
[0]));
6529 if (mode
== V2DFmode
)
6530 emit_insn (gen_vsx_concat_v2df (target
, op
[0], op
[1]));
6532 emit_insn (gen_vsx_concat_v2di (target
, op
[0], op
[1]));
6537 /* Special case initializing vector int if we are on 64-bit systems with
6538 direct move or we have the ISA 3.0 instructions. */
6539 if (mode
== V4SImode
&& VECTOR_MEM_VSX_P (V4SImode
)
6540 && TARGET_DIRECT_MOVE_64BIT
)
6544 rtx element0
= XVECEXP (vals
, 0, 0);
6545 if (MEM_P (element0
))
6546 element0
= rs6000_force_indexed_or_indirect_mem (element0
);
6548 element0
= force_reg (SImode
, element0
);
6550 if (TARGET_P9_VECTOR
)
6551 emit_insn (gen_vsx_splat_v4si (target
, element0
));
6554 rtx tmp
= gen_reg_rtx (DImode
);
6555 emit_insn (gen_zero_extendsidi2 (tmp
, element0
));
6556 emit_insn (gen_vsx_splat_v4si_di (target
, tmp
));
6565 for (i
= 0; i
< 4; i
++)
6566 elements
[i
] = force_reg (SImode
, XVECEXP (vals
, 0, i
));
6568 emit_insn (gen_vsx_init_v4si (target
, elements
[0], elements
[1],
6569 elements
[2], elements
[3]));
6574 /* With single precision floating point on VSX, know that internally single
6575 precision is actually represented as a double, and either make 2 V2DF
6576 vectors, and convert these vectors to single precision, or do one
6577 conversion, and splat the result to the other elements. */
6578 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (V4SFmode
))
6582 rtx element0
= XVECEXP (vals
, 0, 0);
6584 if (TARGET_P9_VECTOR
)
6586 if (MEM_P (element0
))
6587 element0
= rs6000_force_indexed_or_indirect_mem (element0
);
6589 emit_insn (gen_vsx_splat_v4sf (target
, element0
));
6594 rtx freg
= gen_reg_rtx (V4SFmode
);
6595 rtx sreg
= force_reg (SFmode
, element0
);
6596 rtx cvt
= (TARGET_XSCVDPSPN
6597 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
6598 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
6601 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
,
6607 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
6608 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
6609 rtx flt_even
= gen_reg_rtx (V4SFmode
);
6610 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
6611 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
6612 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
6613 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
6614 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
6616 /* Use VMRGEW if we can instead of doing a permute. */
6617 if (TARGET_P8_VECTOR
)
6619 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op2
));
6620 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op1
, op3
));
6621 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6622 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6623 if (BYTES_BIG_ENDIAN
)
6624 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_even
, flt_odd
));
6626 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_odd
, flt_even
));
6630 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
6631 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
6632 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6633 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6634 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
6640 /* Special case initializing vector short/char that are splats if we are on
6641 64-bit systems with direct move. */
6642 if (all_same
&& TARGET_DIRECT_MOVE_64BIT
6643 && (mode
== V16QImode
|| mode
== V8HImode
))
6645 rtx op0
= XVECEXP (vals
, 0, 0);
6646 rtx di_tmp
= gen_reg_rtx (DImode
);
6649 op0
= force_reg (GET_MODE_INNER (mode
), op0
);
6651 if (mode
== V16QImode
)
6653 emit_insn (gen_zero_extendqidi2 (di_tmp
, op0
));
6654 emit_insn (gen_vsx_vspltb_di (target
, di_tmp
));
6658 if (mode
== V8HImode
)
6660 emit_insn (gen_zero_extendhidi2 (di_tmp
, op0
));
6661 emit_insn (gen_vsx_vsplth_di (target
, di_tmp
));
6666 /* Store value to stack temp. Load vector element. Splat. However, splat
6667 of 64-bit items is not supported on Altivec. */
6668 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
6670 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6671 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
6672 XVECEXP (vals
, 0, 0));
6673 x
= gen_rtx_UNSPEC (VOIDmode
,
6674 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6675 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6677 gen_rtx_SET (target
, mem
),
6679 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
6680 gen_rtx_PARALLEL (VOIDmode
,
6681 gen_rtvec (1, const0_rtx
)));
6682 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
6686 /* One field is non-constant. Load constant then overwrite
6690 rtx copy
= copy_rtx (vals
);
6692 /* Load constant part of vector, substitute neighboring value for
6694 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
6695 rs6000_expand_vector_init (target
, copy
);
6697 /* Insert variable. */
6698 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
6702 /* Construct the vector in memory one field at a time
6703 and load the whole vector. */
6704 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6705 for (i
= 0; i
< n_elts
; i
++)
6706 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
6707 i
* GET_MODE_SIZE (inner_mode
)),
6708 XVECEXP (vals
, 0, i
));
6709 emit_move_insn (target
, mem
);
6712 /* Set field ELT of TARGET to VAL. */
6715 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
6717 machine_mode mode
= GET_MODE (target
);
6718 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6719 rtx reg
= gen_reg_rtx (mode
);
6721 int width
= GET_MODE_SIZE (inner_mode
);
6724 val
= force_reg (GET_MODE (val
), val
);
6726 if (VECTOR_MEM_VSX_P (mode
))
6728 rtx insn
= NULL_RTX
;
6729 rtx elt_rtx
= GEN_INT (elt
);
6731 if (mode
== V2DFmode
)
6732 insn
= gen_vsx_set_v2df (target
, target
, val
, elt_rtx
);
6734 else if (mode
== V2DImode
)
6735 insn
= gen_vsx_set_v2di (target
, target
, val
, elt_rtx
);
6737 else if (TARGET_P9_VECTOR
&& TARGET_POWERPC64
)
6739 if (mode
== V4SImode
)
6740 insn
= gen_vsx_set_v4si_p9 (target
, target
, val
, elt_rtx
);
6741 else if (mode
== V8HImode
)
6742 insn
= gen_vsx_set_v8hi_p9 (target
, target
, val
, elt_rtx
);
6743 else if (mode
== V16QImode
)
6744 insn
= gen_vsx_set_v16qi_p9 (target
, target
, val
, elt_rtx
);
6745 else if (mode
== V4SFmode
)
6746 insn
= gen_vsx_set_v4sf_p9 (target
, target
, val
, elt_rtx
);
6756 /* Simplify setting single element vectors like V1TImode. */
6757 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
6759 emit_move_insn (target
, gen_lowpart (mode
, val
));
6763 /* Load single variable value. */
6764 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6765 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
6766 x
= gen_rtx_UNSPEC (VOIDmode
,
6767 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6768 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6770 gen_rtx_SET (reg
, mem
),
6773 /* Linear sequence. */
6774 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
6775 for (i
= 0; i
< 16; ++i
)
6776 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
6778 /* Set permute mask to insert element into target. */
6779 for (i
= 0; i
< width
; ++i
)
6780 XVECEXP (mask
, 0, elt
*width
+ i
)
6781 = GEN_INT (i
+ 0x10);
6782 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
6784 if (BYTES_BIG_ENDIAN
)
6785 x
= gen_rtx_UNSPEC (mode
,
6786 gen_rtvec (3, target
, reg
,
6787 force_reg (V16QImode
, x
)),
6791 if (TARGET_P9_VECTOR
)
6792 x
= gen_rtx_UNSPEC (mode
,
6793 gen_rtvec (3, reg
, target
,
6794 force_reg (V16QImode
, x
)),
6798 /* Invert selector. We prefer to generate VNAND on P8 so
6799 that future fusion opportunities can kick in, but must
6800 generate VNOR elsewhere. */
6801 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
6802 rtx iorx
= (TARGET_P8_VECTOR
6803 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
6804 : gen_rtx_AND (V16QImode
, notx
, notx
));
6805 rtx tmp
= gen_reg_rtx (V16QImode
);
6806 emit_insn (gen_rtx_SET (tmp
, iorx
));
6808 /* Permute with operands reversed and adjusted selector. */
6809 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
6814 emit_insn (gen_rtx_SET (target
, x
));
6817 /* Extract field ELT from VEC into TARGET. */
6820 rs6000_expand_vector_extract (rtx target
, rtx vec
, rtx elt
)
6822 machine_mode mode
= GET_MODE (vec
);
6823 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6826 if (VECTOR_MEM_VSX_P (mode
) && CONST_INT_P (elt
))
6833 gcc_assert (INTVAL (elt
) == 0 && inner_mode
== TImode
);
6834 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
6837 emit_insn (gen_vsx_extract_v2df (target
, vec
, elt
));
6840 emit_insn (gen_vsx_extract_v2di (target
, vec
, elt
));
6843 emit_insn (gen_vsx_extract_v4sf (target
, vec
, elt
));
6846 if (TARGET_DIRECT_MOVE_64BIT
)
6848 emit_insn (gen_vsx_extract_v16qi (target
, vec
, elt
));
6854 if (TARGET_DIRECT_MOVE_64BIT
)
6856 emit_insn (gen_vsx_extract_v8hi (target
, vec
, elt
));
6862 if (TARGET_DIRECT_MOVE_64BIT
)
6864 emit_insn (gen_vsx_extract_v4si (target
, vec
, elt
));
6870 else if (VECTOR_MEM_VSX_P (mode
) && !CONST_INT_P (elt
)
6871 && TARGET_DIRECT_MOVE_64BIT
)
6873 if (GET_MODE (elt
) != DImode
)
6875 rtx tmp
= gen_reg_rtx (DImode
);
6876 convert_move (tmp
, elt
, 0);
6879 else if (!REG_P (elt
))
6880 elt
= force_reg (DImode
, elt
);
6885 emit_insn (gen_vsx_extract_v2df_var (target
, vec
, elt
));
6889 emit_insn (gen_vsx_extract_v2di_var (target
, vec
, elt
));
6893 emit_insn (gen_vsx_extract_v4sf_var (target
, vec
, elt
));
6897 emit_insn (gen_vsx_extract_v4si_var (target
, vec
, elt
));
6901 emit_insn (gen_vsx_extract_v8hi_var (target
, vec
, elt
));
6905 emit_insn (gen_vsx_extract_v16qi_var (target
, vec
, elt
));
6913 gcc_assert (CONST_INT_P (elt
));
6915 /* Allocate mode-sized buffer. */
6916 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6918 emit_move_insn (mem
, vec
);
6920 /* Add offset to field within buffer matching vector element. */
6921 mem
= adjust_address_nv (mem
, inner_mode
,
6922 INTVAL (elt
) * GET_MODE_SIZE (inner_mode
));
6924 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
6927 /* Helper function to return the register number of a RTX. */
6929 regno_or_subregno (rtx op
)
6933 else if (SUBREG_P (op
))
6934 return subreg_regno (op
);
6939 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6940 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6941 temporary (BASE_TMP) to fixup the address. Return the new memory address
6942 that is valid for reads or writes to a given register (SCALAR_REG). */
6945 rs6000_adjust_vec_address (rtx scalar_reg
,
6949 machine_mode scalar_mode
)
6951 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
6952 rtx addr
= XEXP (mem
, 0);
6957 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6958 gcc_assert (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
);
6960 /* Calculate what we need to add to the address to get the element
6962 if (CONST_INT_P (element
))
6963 element_offset
= GEN_INT (INTVAL (element
) * scalar_size
);
6966 int byte_shift
= exact_log2 (scalar_size
);
6967 gcc_assert (byte_shift
>= 0);
6969 if (byte_shift
== 0)
6970 element_offset
= element
;
6974 if (TARGET_POWERPC64
)
6975 emit_insn (gen_ashldi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
6977 emit_insn (gen_ashlsi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
6979 element_offset
= base_tmp
;
6983 /* Create the new address pointing to the element within the vector. If we
6984 are adding 0, we don't have to change the address. */
6985 if (element_offset
== const0_rtx
)
6988 /* A simple indirect address can be converted into a reg + offset
6990 else if (REG_P (addr
) || SUBREG_P (addr
))
6991 new_addr
= gen_rtx_PLUS (Pmode
, addr
, element_offset
);
6993 /* Optimize D-FORM addresses with constant offset with a constant element, to
6994 include the element offset in the address directly. */
6995 else if (GET_CODE (addr
) == PLUS
)
6997 rtx op0
= XEXP (addr
, 0);
6998 rtx op1
= XEXP (addr
, 1);
7001 gcc_assert (REG_P (op0
) || SUBREG_P (op0
));
7002 if (CONST_INT_P (op1
) && CONST_INT_P (element_offset
))
7004 HOST_WIDE_INT offset
= INTVAL (op1
) + INTVAL (element_offset
);
7005 rtx offset_rtx
= GEN_INT (offset
);
7007 if (IN_RANGE (offset
, -32768, 32767)
7008 && (scalar_size
< 8 || (offset
& 0x3) == 0))
7009 new_addr
= gen_rtx_PLUS (Pmode
, op0
, offset_rtx
);
7012 emit_move_insn (base_tmp
, offset_rtx
);
7013 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7018 bool op1_reg_p
= (REG_P (op1
) || SUBREG_P (op1
));
7019 bool ele_reg_p
= (REG_P (element_offset
) || SUBREG_P (element_offset
));
7021 /* Note, ADDI requires the register being added to be a base
7022 register. If the register was R0, load it up into the temporary
7025 && (ele_reg_p
|| reg_or_subregno (op1
) != FIRST_GPR_REGNO
))
7027 insn
= gen_add3_insn (base_tmp
, op1
, element_offset
);
7028 gcc_assert (insn
!= NULL_RTX
);
7033 && reg_or_subregno (element_offset
) != FIRST_GPR_REGNO
)
7035 insn
= gen_add3_insn (base_tmp
, element_offset
, op1
);
7036 gcc_assert (insn
!= NULL_RTX
);
7042 emit_move_insn (base_tmp
, op1
);
7043 emit_insn (gen_add2_insn (base_tmp
, element_offset
));
7046 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7052 emit_move_insn (base_tmp
, addr
);
7053 new_addr
= gen_rtx_PLUS (Pmode
, base_tmp
, element_offset
);
7056 /* If we have a PLUS, we need to see whether the particular register class
7057 allows for D-FORM or X-FORM addressing. */
7058 if (GET_CODE (new_addr
) == PLUS
)
7060 rtx op1
= XEXP (new_addr
, 1);
7061 addr_mask_type addr_mask
;
7062 int scalar_regno
= regno_or_subregno (scalar_reg
);
7064 gcc_assert (scalar_regno
< FIRST_PSEUDO_REGISTER
);
7065 if (INT_REGNO_P (scalar_regno
))
7066 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_GPR
];
7068 else if (FP_REGNO_P (scalar_regno
))
7069 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_FPR
];
7071 else if (ALTIVEC_REGNO_P (scalar_regno
))
7072 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_VMX
];
7077 if (REG_P (op1
) || SUBREG_P (op1
))
7078 valid_addr_p
= (addr_mask
& RELOAD_REG_INDEXED
) != 0;
7080 valid_addr_p
= (addr_mask
& RELOAD_REG_OFFSET
) != 0;
7083 else if (REG_P (new_addr
) || SUBREG_P (new_addr
))
7084 valid_addr_p
= true;
7087 valid_addr_p
= false;
7091 emit_move_insn (base_tmp
, new_addr
);
7092 new_addr
= base_tmp
;
7095 return change_address (mem
, scalar_mode
, new_addr
);
7098 /* Split a variable vec_extract operation into the component instructions. */
7101 rs6000_split_vec_extract_var (rtx dest
, rtx src
, rtx element
, rtx tmp_gpr
,
7104 machine_mode mode
= GET_MODE (src
);
7105 machine_mode scalar_mode
= GET_MODE (dest
);
7106 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7107 int byte_shift
= exact_log2 (scalar_size
);
7109 gcc_assert (byte_shift
>= 0);
7111 /* If we are given a memory address, optimize to load just the element. We
7112 don't have to adjust the vector element number on little endian
7116 gcc_assert (REG_P (tmp_gpr
));
7117 emit_move_insn (dest
, rs6000_adjust_vec_address (dest
, src
, element
,
7118 tmp_gpr
, scalar_mode
));
7122 else if (REG_P (src
) || SUBREG_P (src
))
7124 int bit_shift
= byte_shift
+ 3;
7126 int dest_regno
= regno_or_subregno (dest
);
7127 int src_regno
= regno_or_subregno (src
);
7128 int element_regno
= regno_or_subregno (element
);
7130 gcc_assert (REG_P (tmp_gpr
));
7132 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7133 a general purpose register. */
7134 if (TARGET_P9_VECTOR
7135 && (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
7136 && INT_REGNO_P (dest_regno
)
7137 && ALTIVEC_REGNO_P (src_regno
)
7138 && INT_REGNO_P (element_regno
))
7140 rtx dest_si
= gen_rtx_REG (SImode
, dest_regno
);
7141 rtx element_si
= gen_rtx_REG (SImode
, element_regno
);
7143 if (mode
== V16QImode
)
7144 emit_insn (BYTES_BIG_ENDIAN
7145 ? gen_vextublx (dest_si
, element_si
, src
)
7146 : gen_vextubrx (dest_si
, element_si
, src
));
7148 else if (mode
== V8HImode
)
7150 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7151 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const1_rtx
));
7152 emit_insn (BYTES_BIG_ENDIAN
7153 ? gen_vextuhlx (dest_si
, tmp_gpr_si
, src
)
7154 : gen_vextuhrx (dest_si
, tmp_gpr_si
, src
));
7160 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7161 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const2_rtx
));
7162 emit_insn (BYTES_BIG_ENDIAN
7163 ? gen_vextuwlx (dest_si
, tmp_gpr_si
, src
)
7164 : gen_vextuwrx (dest_si
, tmp_gpr_si
, src
));
7171 gcc_assert (REG_P (tmp_altivec
));
7173 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7174 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7175 will shift the element into the upper position (adding 3 to convert a
7176 byte shift into a bit shift). */
7177 if (scalar_size
== 8)
7179 if (!BYTES_BIG_ENDIAN
)
7181 emit_insn (gen_xordi3 (tmp_gpr
, element
, const1_rtx
));
7187 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7189 emit_insn (gen_rtx_SET (tmp_gpr
,
7190 gen_rtx_AND (DImode
,
7191 gen_rtx_ASHIFT (DImode
,
7198 if (!BYTES_BIG_ENDIAN
)
7200 rtx num_ele_m1
= GEN_INT (GET_MODE_NUNITS (mode
) - 1);
7202 emit_insn (gen_anddi3 (tmp_gpr
, element
, num_ele_m1
));
7203 emit_insn (gen_subdi3 (tmp_gpr
, num_ele_m1
, tmp_gpr
));
7209 emit_insn (gen_ashldi3 (tmp_gpr
, element2
, GEN_INT (bit_shift
)));
7212 /* Get the value into the lower byte of the Altivec register where VSLO
7214 if (TARGET_P9_VECTOR
)
7215 emit_insn (gen_vsx_splat_v2di (tmp_altivec
, tmp_gpr
));
7216 else if (can_create_pseudo_p ())
7217 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_gpr
, tmp_gpr
));
7220 rtx tmp_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7221 emit_move_insn (tmp_di
, tmp_gpr
);
7222 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_di
, tmp_di
));
7225 /* Do the VSLO to get the value into the final location. */
7229 emit_insn (gen_vsx_vslo_v2df (dest
, src
, tmp_altivec
));
7233 emit_insn (gen_vsx_vslo_v2di (dest
, src
, tmp_altivec
));
7238 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7239 rtx tmp_altivec_v4sf
= gen_rtx_REG (V4SFmode
, REGNO (tmp_altivec
));
7240 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7241 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7244 emit_insn (gen_vsx_xscvspdp_scalar2 (dest
, tmp_altivec_v4sf
));
7252 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7253 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7254 rtx tmp_gpr_di
= gen_rtx_REG (DImode
, REGNO (dest
));
7255 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7257 emit_move_insn (tmp_gpr_di
, tmp_altivec_di
);
7258 emit_insn (gen_ashrdi3 (tmp_gpr_di
, tmp_gpr_di
,
7259 GEN_INT (64 - (8 * scalar_size
))));
7273 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7274 selects whether the alignment is abi mandated, optional, or
7275 both abi and optional alignment. */
7278 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
7280 if (how
!= align_opt
)
7282 if (TREE_CODE (type
) == VECTOR_TYPE
&& align
< 128)
7286 if (how
!= align_abi
)
7288 if (TREE_CODE (type
) == ARRAY_TYPE
7289 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
7291 if (align
< BITS_PER_WORD
)
7292 align
= BITS_PER_WORD
;
7299 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7300 instructions simply ignore the low bits; VSX memory instructions
7301 are aligned to 4 or 8 bytes. */
7304 rs6000_slow_unaligned_access (machine_mode mode
, unsigned int align
)
7306 return (STRICT_ALIGNMENT
7307 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7308 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && align
< 32)
7309 || ((VECTOR_MODE_P (mode
) || FLOAT128_VECTOR_P (mode
))
7310 && (int) align
< VECTOR_ALIGN (mode
)))));
7313 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7316 rs6000_special_adjust_field_align_p (tree type
, unsigned int computed
)
7318 if (TARGET_ALTIVEC
&& TREE_CODE (type
) == VECTOR_TYPE
)
7320 if (computed
!= 128)
7323 if (!warned
&& warn_psabi
)
7326 inform (input_location
,
7327 "the layout of aggregates containing vectors with"
7328 " %d-byte alignment has changed in GCC 5",
7329 computed
/ BITS_PER_UNIT
);
7332 /* In current GCC there is no special case. */
7339 /* AIX increases natural record alignment to doubleword if the first
7340 field is an FP double while the FP fields remain word aligned. */
7343 rs6000_special_round_type_align (tree type
, unsigned int computed
,
7344 unsigned int specified
)
7346 unsigned int align
= MAX (computed
, specified
);
7347 tree field
= TYPE_FIELDS (type
);
7349 /* Skip all non field decls */
7350 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7351 field
= DECL_CHAIN (field
);
7353 if (field
!= NULL
&& field
!= type
)
7355 type
= TREE_TYPE (field
);
7356 while (TREE_CODE (type
) == ARRAY_TYPE
)
7357 type
= TREE_TYPE (type
);
7359 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
7360 align
= MAX (align
, 64);
7366 /* Darwin increases record alignment to the natural alignment of
7370 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
7371 unsigned int specified
)
7373 unsigned int align
= MAX (computed
, specified
);
7375 if (TYPE_PACKED (type
))
7378 /* Find the first field, looking down into aggregates. */
7380 tree field
= TYPE_FIELDS (type
);
7381 /* Skip all non field decls */
7382 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7383 field
= DECL_CHAIN (field
);
7386 /* A packed field does not contribute any extra alignment. */
7387 if (DECL_PACKED (field
))
7389 type
= TREE_TYPE (field
);
7390 while (TREE_CODE (type
) == ARRAY_TYPE
)
7391 type
= TREE_TYPE (type
);
7392 } while (AGGREGATE_TYPE_P (type
));
7394 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
7395 align
= MAX (align
, TYPE_ALIGN (type
));
7400 /* Return 1 for an operand in small memory on V.4/eabi. */
7403 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
7404 machine_mode mode ATTRIBUTE_UNUSED
)
7409 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
7412 if (DEFAULT_ABI
!= ABI_V4
)
7415 if (GET_CODE (op
) == SYMBOL_REF
)
7418 else if (GET_CODE (op
) != CONST
7419 || GET_CODE (XEXP (op
, 0)) != PLUS
7420 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
7421 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
7426 rtx sum
= XEXP (op
, 0);
7427 HOST_WIDE_INT summand
;
7429 /* We have to be careful here, because it is the referenced address
7430 that must be 32k from _SDA_BASE_, not just the symbol. */
7431 summand
= INTVAL (XEXP (sum
, 1));
7432 if (summand
< 0 || summand
> g_switch_value
)
7435 sym_ref
= XEXP (sum
, 0);
7438 return SYMBOL_REF_SMALL_P (sym_ref
);
7444 /* Return true if either operand is a general purpose register. */
7447 gpr_or_gpr_p (rtx op0
, rtx op1
)
7449 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
7450 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
7453 /* Return true if this is a move direct operation between GPR registers and
7454 floating point/VSX registers. */
7457 direct_move_p (rtx op0
, rtx op1
)
7461 if (!REG_P (op0
) || !REG_P (op1
))
7464 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
7467 regno0
= REGNO (op0
);
7468 regno1
= REGNO (op1
);
7469 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
7472 if (INT_REGNO_P (regno0
))
7473 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
7475 else if (INT_REGNO_P (regno1
))
7477 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
7480 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
7487 /* Return true if the OFFSET is valid for the quad address instructions that
7488 use d-form (register + offset) addressing. */
7491 quad_address_offset_p (HOST_WIDE_INT offset
)
7493 return (IN_RANGE (offset
, -32768, 32767) && ((offset
) & 0xf) == 0);
7496 /* Return true if the ADDR is an acceptable address for a quad memory
7497 operation of mode MODE (either LQ/STQ for general purpose registers, or
7498 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7499 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7500 3.0 LXV/STXV instruction. */
7503 quad_address_p (rtx addr
, machine_mode mode
, bool strict
)
7507 if (GET_MODE_SIZE (mode
) != 16)
7510 if (legitimate_indirect_address_p (addr
, strict
))
7513 if (VECTOR_MODE_P (mode
) && !mode_supports_dq_form (mode
))
7516 if (GET_CODE (addr
) != PLUS
)
7519 op0
= XEXP (addr
, 0);
7520 if (!REG_P (op0
) || !INT_REG_OK_FOR_BASE_P (op0
, strict
))
7523 op1
= XEXP (addr
, 1);
7524 if (!CONST_INT_P (op1
))
7527 return quad_address_offset_p (INTVAL (op1
));
7530 /* Return true if this is a load or store quad operation. This function does
7531 not handle the atomic quad memory instructions. */
7534 quad_load_store_p (rtx op0
, rtx op1
)
7538 if (!TARGET_QUAD_MEMORY
)
7541 else if (REG_P (op0
) && MEM_P (op1
))
7542 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
7543 && quad_memory_operand (op1
, GET_MODE (op1
))
7544 && !reg_overlap_mentioned_p (op0
, op1
));
7546 else if (MEM_P (op0
) && REG_P (op1
))
7547 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
7548 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
7553 if (TARGET_DEBUG_ADDR
)
7555 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
7556 ret
? "true" : "false");
7557 debug_rtx (gen_rtx_SET (op0
, op1
));
7563 /* Given an address, return a constant offset term if one exists. */
7566 address_offset (rtx op
)
7568 if (GET_CODE (op
) == PRE_INC
7569 || GET_CODE (op
) == PRE_DEC
)
7571 else if (GET_CODE (op
) == PRE_MODIFY
7572 || GET_CODE (op
) == LO_SUM
)
7575 if (GET_CODE (op
) == CONST
)
7578 if (GET_CODE (op
) == PLUS
)
7581 if (CONST_INT_P (op
))
7587 /* Return true if the MEM operand is a memory operand suitable for use
7588 with a (full width, possibly multiple) gpr load/store. On
7589 powerpc64 this means the offset must be divisible by 4.
7590 Implements 'Y' constraint.
7592 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7593 a constraint function we know the operand has satisfied a suitable
7594 memory predicate. Also accept some odd rtl generated by reload
7595 (see rs6000_legitimize_reload_address for various forms). It is
7596 important that reload rtl be accepted by appropriate constraints
7597 but not by the operand predicate.
7599 Offsetting a lo_sum should not be allowed, except where we know by
7600 alignment that a 32k boundary is not crossed, but see the ???
7601 comment in rs6000_legitimize_reload_address. Note that by
7602 "offsetting" here we mean a further offset to access parts of the
7603 MEM. It's fine to have a lo_sum where the inner address is offset
7604 from a sym, since the same sym+offset will appear in the high part
7605 of the address calculation. */
7608 mem_operand_gpr (rtx op
, machine_mode mode
)
7610 unsigned HOST_WIDE_INT offset
;
7612 rtx addr
= XEXP (op
, 0);
7614 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7616 && (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
7617 && mode_supports_pre_incdec_p (mode
)
7618 && legitimate_indirect_address_p (XEXP (addr
, 0), false))
7621 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7622 if (!rs6000_offsettable_memref_p (op
, mode
, false))
7625 op
= address_offset (addr
);
7629 offset
= INTVAL (op
);
7630 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
7633 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
7637 if (GET_CODE (addr
) == LO_SUM
)
7638 /* For lo_sum addresses, we must allow any offset except one that
7639 causes a wrap, so test only the low 16 bits. */
7640 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
7642 return offset
+ 0x8000 < 0x10000u
- extra
;
7645 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7646 enforce an offset divisible by 4 even for 32-bit. */
7649 mem_operand_ds_form (rtx op
, machine_mode mode
)
7651 unsigned HOST_WIDE_INT offset
;
7653 rtx addr
= XEXP (op
, 0);
7655 if (!offsettable_address_p (false, mode
, addr
))
7658 op
= address_offset (addr
);
7662 offset
= INTVAL (op
);
7663 if ((offset
& 3) != 0)
7666 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
7670 if (GET_CODE (addr
) == LO_SUM
)
7671 /* For lo_sum addresses, we must allow any offset except one that
7672 causes a wrap, so test only the low 16 bits. */
7673 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
7675 return offset
+ 0x8000 < 0x10000u
- extra
;
7678 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7681 reg_offset_addressing_ok_p (machine_mode mode
)
7695 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7696 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7697 a vector mode, if we want to use the VSX registers to move it around,
7698 we need to restrict ourselves to reg+reg addressing. Similarly for
7699 IEEE 128-bit floating point that is passed in a single vector
7701 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
7702 return mode_supports_dq_form (mode
);
7706 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7707 addressing for the LFIWZX and STFIWX instructions. */
7708 if (TARGET_NO_SDMODE_STACK
)
7720 virtual_stack_registers_memory_p (rtx op
)
7724 if (GET_CODE (op
) == REG
)
7725 regnum
= REGNO (op
);
7727 else if (GET_CODE (op
) == PLUS
7728 && GET_CODE (XEXP (op
, 0)) == REG
7729 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
7730 regnum
= REGNO (XEXP (op
, 0));
7735 return (regnum
>= FIRST_VIRTUAL_REGISTER
7736 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
7739 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7740 is known to not straddle a 32k boundary. This function is used
7741 to determine whether -mcmodel=medium code can use TOC pointer
7742 relative addressing for OP. This means the alignment of the TOC
7743 pointer must also be taken into account, and unfortunately that is
7746 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7747 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7751 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
7755 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
7757 if (GET_CODE (op
) != SYMBOL_REF
)
7760 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7762 if (mode_supports_dq_form (mode
))
7765 dsize
= GET_MODE_SIZE (mode
);
7766 decl
= SYMBOL_REF_DECL (op
);
7772 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7773 replacing memory addresses with an anchor plus offset. We
7774 could find the decl by rummaging around in the block->objects
7775 VEC for the given offset but that seems like too much work. */
7776 dalign
= BITS_PER_UNIT
;
7777 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
7778 && SYMBOL_REF_ANCHOR_P (op
)
7779 && SYMBOL_REF_BLOCK (op
) != NULL
)
7781 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
7783 dalign
= block
->alignment
;
7784 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
7786 else if (CONSTANT_POOL_ADDRESS_P (op
))
7788 /* It would be nice to have get_pool_align().. */
7789 machine_mode cmode
= get_pool_mode (op
);
7791 dalign
= GET_MODE_ALIGNMENT (cmode
);
7794 else if (DECL_P (decl
))
7796 dalign
= DECL_ALIGN (decl
);
7800 /* Allow BLKmode when the entire object is known to not
7801 cross a 32k boundary. */
7802 if (!DECL_SIZE_UNIT (decl
))
7805 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
7808 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
7812 dalign
/= BITS_PER_UNIT
;
7813 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7814 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7815 return dalign
>= dsize
;
7821 /* Find how many bits of the alignment we know for this access. */
7822 dalign
/= BITS_PER_UNIT
;
7823 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7824 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7826 lsb
= offset
& -offset
;
7830 return dalign
>= dsize
;
7834 constant_pool_expr_p (rtx op
)
7838 split_const (op
, &base
, &offset
);
7839 return (GET_CODE (base
) == SYMBOL_REF
7840 && CONSTANT_POOL_ADDRESS_P (base
)
7841 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
7844 /* These are only used to pass through from print_operand/print_operand_address
7845 to rs6000_output_addr_const_extra over the intervening function
7846 output_addr_const which is not target code. */
7847 static const_rtx tocrel_base_oac
, tocrel_offset_oac
;
7849 /* Return true if OP is a toc pointer relative address (the output
7850 of create_TOC_reference). If STRICT, do not match non-split
7851 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7852 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7853 TOCREL_OFFSET_RET respectively. */
7856 toc_relative_expr_p (const_rtx op
, bool strict
, const_rtx
*tocrel_base_ret
,
7857 const_rtx
*tocrel_offset_ret
)
7862 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7864 /* When strict ensure we have everything tidy. */
7866 && !(GET_CODE (op
) == LO_SUM
7867 && REG_P (XEXP (op
, 0))
7868 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
)))
7871 /* When not strict, allow non-split TOC addresses and also allow
7872 (lo_sum (high ..)) TOC addresses created during reload. */
7873 if (GET_CODE (op
) == LO_SUM
)
7877 const_rtx tocrel_base
= op
;
7878 const_rtx tocrel_offset
= const0_rtx
;
7880 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
7882 tocrel_base
= XEXP (op
, 0);
7883 tocrel_offset
= XEXP (op
, 1);
7886 if (tocrel_base_ret
)
7887 *tocrel_base_ret
= tocrel_base
;
7888 if (tocrel_offset_ret
)
7889 *tocrel_offset_ret
= tocrel_offset
;
7891 return (GET_CODE (tocrel_base
) == UNSPEC
7892 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
7893 && REG_P (XVECEXP (tocrel_base
, 0, 1))
7894 && REGNO (XVECEXP (tocrel_base
, 0, 1)) == TOC_REGISTER
);
7897 /* Return true if X is a constant pool address, and also for cmodel=medium
7898 if X is a toc-relative address known to be offsettable within MODE. */
7901 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
7904 const_rtx tocrel_base
, tocrel_offset
;
7905 return (toc_relative_expr_p (x
, strict
, &tocrel_base
, &tocrel_offset
)
7906 && (TARGET_CMODEL
!= CMODEL_MEDIUM
7907 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
7909 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
7910 INTVAL (tocrel_offset
), mode
)));
7914 legitimate_small_data_p (machine_mode mode
, rtx x
)
7916 return (DEFAULT_ABI
== ABI_V4
7917 && !flag_pic
&& !TARGET_TOC
7918 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
7919 && small_data_operand (x
, mode
));
7923 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
7924 bool strict
, bool worst_case
)
7926 unsigned HOST_WIDE_INT offset
;
7929 if (GET_CODE (x
) != PLUS
)
7931 if (!REG_P (XEXP (x
, 0)))
7933 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
7935 if (mode_supports_dq_form (mode
))
7936 return quad_address_p (x
, mode
, strict
);
7937 if (!reg_offset_addressing_ok_p (mode
))
7938 return virtual_stack_registers_memory_p (x
);
7939 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
7941 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
7944 offset
= INTVAL (XEXP (x
, 1));
7951 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7953 if (VECTOR_MEM_VSX_P (mode
))
7958 if (!TARGET_POWERPC64
)
7960 else if (offset
& 3)
7973 if (!TARGET_POWERPC64
)
7975 else if (offset
& 3)
7984 return offset
< 0x10000 - extra
;
7988 legitimate_indexed_address_p (rtx x
, int strict
)
7992 if (GET_CODE (x
) != PLUS
)
7998 return (REG_P (op0
) && REG_P (op1
)
7999 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
8000 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
8001 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
8002 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
8006 avoiding_indexed_address_p (machine_mode mode
)
8008 /* Avoid indexed addressing for modes that have non-indexed
8009 load/store instruction forms. */
8010 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
8014 legitimate_indirect_address_p (rtx x
, int strict
)
8016 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
8020 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
8022 if (!TARGET_MACHO
|| !flag_pic
8023 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
8027 if (GET_CODE (x
) != LO_SUM
)
8029 if (GET_CODE (XEXP (x
, 0)) != REG
)
8031 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
8035 return CONSTANT_P (x
);
8039 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
8041 if (GET_CODE (x
) != LO_SUM
)
8043 if (GET_CODE (XEXP (x
, 0)) != REG
)
8045 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8047 /* quad word addresses are restricted, and we can't use LO_SUM. */
8048 if (mode_supports_dq_form (mode
))
8052 if (TARGET_ELF
|| TARGET_MACHO
)
8056 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
8058 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8059 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8060 recognizes some LO_SUM addresses as valid although this
8061 function says opposite. In most cases, LRA through different
8062 transformations can generate correct code for address reloads.
8063 It can not manage only some LO_SUM cases. So we need to add
8064 code analogous to one in rs6000_legitimize_reload_address for
8065 LOW_SUM here saying that some addresses are still valid. */
8066 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
8067 && small_toc_ref (x
, VOIDmode
));
8068 if (TARGET_TOC
&& ! large_toc_ok
)
8070 if (GET_MODE_NUNITS (mode
) != 1)
8072 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
8073 && !(/* ??? Assume floating point reg based on mode? */
8074 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
)))
8077 return CONSTANT_P (x
) || large_toc_ok
;
8084 /* Try machine-dependent ways of modifying an illegitimate address
8085 to be legitimate. If we find one, return the new, valid address.
8086 This is used from only one place: `memory_address' in explow.c.
8088 OLDX is the address as it was before break_out_memory_refs was
8089 called. In some cases it is useful to look at this to decide what
8092 It is always safe for this function to do nothing. It exists to
8093 recognize opportunities to optimize the output.
8095 On RS/6000, first check for the sum of a register with a constant
8096 integer that is out of range. If so, generate code to add the
8097 constant with the low-order 16 bits masked to the register and force
8098 this result into another register (this can be done with `cau').
8099 Then generate an address of REG+(CONST&0xffff), allowing for the
8100 possibility of bit 16 being a one.
8102 Then check for the sum of a register and something not constant, try to
8103 load the other things into a register and return the sum. */
8106 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
8111 if (!reg_offset_addressing_ok_p (mode
)
8112 || mode_supports_dq_form (mode
))
8114 if (virtual_stack_registers_memory_p (x
))
8117 /* In theory we should not be seeing addresses of the form reg+0,
8118 but just in case it is generated, optimize it away. */
8119 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
8120 return force_reg (Pmode
, XEXP (x
, 0));
8122 /* For TImode with load/store quad, restrict addresses to just a single
8123 pointer, so it works with both GPRs and VSX registers. */
8124 /* Make sure both operands are registers. */
8125 else if (GET_CODE (x
) == PLUS
8126 && (mode
!= TImode
|| !TARGET_VSX
))
8127 return gen_rtx_PLUS (Pmode
,
8128 force_reg (Pmode
, XEXP (x
, 0)),
8129 force_reg (Pmode
, XEXP (x
, 1)));
8131 return force_reg (Pmode
, x
);
8133 if (GET_CODE (x
) == SYMBOL_REF
)
8135 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
8137 return rs6000_legitimize_tls_address (x
, model
);
8149 /* As in legitimate_offset_address_p we do not assume
8150 worst-case. The mode here is just a hint as to the registers
8151 used. A TImode is usually in gprs, but may actually be in
8152 fprs. Leave worst-case scenario for reload to handle via
8153 insn constraints. PTImode is only GPRs. */
8160 if (GET_CODE (x
) == PLUS
8161 && GET_CODE (XEXP (x
, 0)) == REG
8162 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8163 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
8164 >= 0x10000 - extra
))
8166 HOST_WIDE_INT high_int
, low_int
;
8168 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8169 if (low_int
>= 0x8000 - extra
)
8171 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
8172 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8173 GEN_INT (high_int
)), 0);
8174 return plus_constant (Pmode
, sum
, low_int
);
8176 else if (GET_CODE (x
) == PLUS
8177 && GET_CODE (XEXP (x
, 0)) == REG
8178 && GET_CODE (XEXP (x
, 1)) != CONST_INT
8179 && GET_MODE_NUNITS (mode
) == 1
8180 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8181 || (/* ??? Assume floating point reg based on mode? */
8182 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
)))
8183 && !avoiding_indexed_address_p (mode
))
8185 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8186 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
8188 else if ((TARGET_ELF
8190 || !MACHO_DYNAMIC_NO_PIC_P
8196 && GET_CODE (x
) != CONST_INT
8197 && GET_CODE (x
) != CONST_WIDE_INT
8198 && GET_CODE (x
) != CONST_DOUBLE
8200 && GET_MODE_NUNITS (mode
) == 1
8201 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8202 || (/* ??? Assume floating point reg based on mode? */
8203 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
))))
8205 rtx reg
= gen_reg_rtx (Pmode
);
8207 emit_insn (gen_elf_high (reg
, x
));
8209 emit_insn (gen_macho_high (reg
, x
));
8210 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
8213 && GET_CODE (x
) == SYMBOL_REF
8214 && constant_pool_expr_p (x
)
8215 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
8216 return create_TOC_reference (x
, NULL_RTX
);
8221 /* Debug version of rs6000_legitimize_address. */
8223 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
8229 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
8230 insns
= get_insns ();
8236 "\nrs6000_legitimize_address: mode %s, old code %s, "
8237 "new code %s, modified\n",
8238 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
8239 GET_RTX_NAME (GET_CODE (ret
)));
8241 fprintf (stderr
, "Original address:\n");
8244 fprintf (stderr
, "oldx:\n");
8247 fprintf (stderr
, "New address:\n");
8252 fprintf (stderr
, "Insns added:\n");
8253 debug_rtx_list (insns
, 20);
8259 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8260 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
8271 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8272 We need to emit DTP-relative relocations. */
8274 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
8276 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8281 fputs ("\t.long\t", file
);
8284 fputs (DOUBLE_INT_ASM_OP
, file
);
8289 output_addr_const (file
, x
);
8291 fputs ("@dtprel+0x8000", file
);
8292 else if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
)
8294 switch (SYMBOL_REF_TLS_MODEL (x
))
8298 case TLS_MODEL_LOCAL_EXEC
:
8299 fputs ("@le", file
);
8301 case TLS_MODEL_INITIAL_EXEC
:
8302 fputs ("@ie", file
);
8304 case TLS_MODEL_GLOBAL_DYNAMIC
:
8305 case TLS_MODEL_LOCAL_DYNAMIC
:
8314 /* Return true if X is a symbol that refers to real (rather than emulated)
8318 rs6000_real_tls_symbol_ref_p (rtx x
)
8320 return (GET_CODE (x
) == SYMBOL_REF
8321 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
8324 /* In the name of slightly smaller debug output, and to cater to
8325 general assembler lossage, recognize various UNSPEC sequences
8326 and turn them back into a direct symbol reference. */
8329 rs6000_delegitimize_address (rtx orig_x
)
8333 orig_x
= delegitimize_mem_from_attrs (orig_x
);
8339 if (TARGET_CMODEL
!= CMODEL_SMALL
8340 && GET_CODE (y
) == LO_SUM
)
8344 if (GET_CODE (y
) == PLUS
8345 && GET_MODE (y
) == Pmode
8346 && CONST_INT_P (XEXP (y
, 1)))
8348 offset
= XEXP (y
, 1);
8352 if (GET_CODE (y
) == UNSPEC
8353 && XINT (y
, 1) == UNSPEC_TOCREL
)
8355 y
= XVECEXP (y
, 0, 0);
8358 /* Do not associate thread-local symbols with the original
8359 constant pool symbol. */
8361 && GET_CODE (y
) == SYMBOL_REF
8362 && CONSTANT_POOL_ADDRESS_P (y
)
8363 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
8367 if (offset
!= NULL_RTX
)
8368 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
8369 if (!MEM_P (orig_x
))
8372 return replace_equiv_address_nv (orig_x
, y
);
8376 && GET_CODE (orig_x
) == LO_SUM
8377 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
8379 y
= XEXP (XEXP (orig_x
, 1), 0);
8380 if (GET_CODE (y
) == UNSPEC
8381 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
8382 return XVECEXP (y
, 0, 0);
8388 /* Return true if X shouldn't be emitted into the debug info.
8389 The linker doesn't like .toc section references from
8390 .debug_* sections, so reject .toc section symbols. */
8393 rs6000_const_not_ok_for_debug_p (rtx x
)
8395 if (GET_CODE (x
) == UNSPEC
)
8397 if (GET_CODE (x
) == SYMBOL_REF
8398 && CONSTANT_POOL_ADDRESS_P (x
))
8400 rtx c
= get_pool_constant (x
);
8401 machine_mode cmode
= get_pool_mode (x
);
8402 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
8409 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8412 rs6000_legitimate_combined_insn (rtx_insn
*insn
)
8414 int icode
= INSN_CODE (insn
);
8416 /* Reject creating doloop insns. Combine should not be allowed
8417 to create these for a number of reasons:
8418 1) In a nested loop, if combine creates one of these in an
8419 outer loop and the register allocator happens to allocate ctr
8420 to the outer loop insn, then the inner loop can't use ctr.
8421 Inner loops ought to be more highly optimized.
8422 2) Combine often wants to create one of these from what was
8423 originally a three insn sequence, first combining the three
8424 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8425 allocated ctr, the splitter takes use back to the three insn
8426 sequence. It's better to stop combine at the two insn
8428 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8429 insns, the register allocator sometimes uses floating point
8430 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8431 jump insn and output reloads are not implemented for jumps,
8432 the ctrsi/ctrdi splitters need to handle all possible cases.
8433 That's a pain, and it gets to be seriously difficult when a
8434 splitter that runs after reload needs memory to transfer from
8435 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8436 for the difficult case. It's better to not create problems
8437 in the first place. */
8438 if (icode
!= CODE_FOR_nothing
8439 && (icode
== CODE_FOR_bdz_si
8440 || icode
== CODE_FOR_bdz_di
8441 || icode
== CODE_FOR_bdnz_si
8442 || icode
== CODE_FOR_bdnz_di
8443 || icode
== CODE_FOR_bdztf_si
8444 || icode
== CODE_FOR_bdztf_di
8445 || icode
== CODE_FOR_bdnztf_si
8446 || icode
== CODE_FOR_bdnztf_di
))
8452 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8454 static GTY(()) rtx rs6000_tls_symbol
;
8456 rs6000_tls_get_addr (void)
8458 if (!rs6000_tls_symbol
)
8459 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
8461 return rs6000_tls_symbol
;
8464 /* Construct the SYMBOL_REF for TLS GOT references. */
8466 static GTY(()) rtx rs6000_got_symbol
;
8468 rs6000_got_sym (void)
8470 if (!rs6000_got_symbol
)
8472 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8473 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
8474 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
8477 return rs6000_got_symbol
;
8480 /* AIX Thread-Local Address support. */
8483 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
8485 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
8489 name
= XSTR (addr
, 0);
8490 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8491 or the symbol will be in TLS private data section. */
8492 if (name
[strlen (name
) - 1] != ']'
8493 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
8494 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
8496 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
8497 strcpy (tlsname
, name
);
8499 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
8500 tlsaddr
= copy_rtx (addr
);
8501 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
8506 /* Place addr into TOC constant pool. */
8507 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
8509 /* Output the TOC entry and create the MEM referencing the value. */
8510 if (constant_pool_expr_p (XEXP (sym
, 0))
8511 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
8513 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
8514 mem
= gen_const_mem (Pmode
, tocref
);
8515 set_mem_alias_set (mem
, get_TOC_alias_set ());
8520 /* Use global-dynamic for local-dynamic. */
8521 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
8522 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
8524 /* Create new TOC reference for @m symbol. */
8525 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
8526 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
8527 strcpy (tlsname
, "*LCM");
8528 strcat (tlsname
, name
+ 3);
8529 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
8530 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
8531 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
8532 rtx modmem
= gen_const_mem (Pmode
, tocref
);
8533 set_mem_alias_set (modmem
, get_TOC_alias_set ());
8535 rtx modreg
= gen_reg_rtx (Pmode
);
8536 emit_insn (gen_rtx_SET (modreg
, modmem
));
8538 tmpreg
= gen_reg_rtx (Pmode
);
8539 emit_insn (gen_rtx_SET (tmpreg
, mem
));
8541 dest
= gen_reg_rtx (Pmode
);
8543 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
8545 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
8548 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8549 else if (TARGET_32BIT
)
8551 tlsreg
= gen_reg_rtx (SImode
);
8552 emit_insn (gen_tls_get_tpointer (tlsreg
));
8555 tlsreg
= gen_rtx_REG (DImode
, 13);
8557 /* Load the TOC value into temporary register. */
8558 tmpreg
= gen_reg_rtx (Pmode
);
8559 emit_insn (gen_rtx_SET (tmpreg
, mem
));
8560 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
8561 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
8563 /* Add TOC symbol value to TLS pointer. */
8564 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
8569 /* Mess with a call, to make it look like the tls_gdld insns when
8570 !TARGET_TLS_MARKERS. These insns have an extra unspec to
8571 differentiate them from standard calls, because they need to emit
8572 the arg setup insns as well as the actual call. That keeps the
8573 arg setup insns immediately adjacent to the branch and link. */
8576 edit_tls_call_insn (rtx arg
)
8578 rtx call_insn
= last_call_insn ();
8579 if (!TARGET_TLS_MARKERS
)
8581 rtx patt
= PATTERN (call_insn
);
8582 gcc_assert (GET_CODE (patt
) == PARALLEL
);
8583 rtvec orig
= XVEC (patt
, 0);
8584 rtvec v
= rtvec_alloc (GET_NUM_ELEM (orig
) + 1);
8585 gcc_assert (GET_NUM_ELEM (orig
) > 0);
8586 /* The (set (..) (call (mem ..))). */
8587 RTVEC_ELT (v
, 0) = RTVEC_ELT (orig
, 0);
8588 /* The extra unspec. */
8589 RTVEC_ELT (v
, 1) = arg
;
8590 /* All other assorted call pattern pieces. */
8591 for (int i
= 1; i
< GET_NUM_ELEM (orig
); i
++)
8592 RTVEC_ELT (v
, i
+ 1) = RTVEC_ELT (orig
, i
);
8595 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
8596 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
8597 pic_offset_table_rtx
);
8600 /* Passes the tls arg value for global dynamic and local dynamic
8601 emit_library_call_value in rs6000_legitimize_tls_address to
8602 rs6000_call_aix and rs6000_call_sysv. This is used to emit the
8603 marker relocs put on __tls_get_addr calls. */
8604 static rtx global_tlsarg
;
8606 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8607 this (thread-local) address. */
8610 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
8615 return rs6000_legitimize_tls_address_aix (addr
, model
);
8617 dest
= gen_reg_rtx (Pmode
);
8618 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
8624 tlsreg
= gen_rtx_REG (Pmode
, 13);
8625 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
8629 tlsreg
= gen_rtx_REG (Pmode
, 2);
8630 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
8634 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
8638 tmp
= gen_reg_rtx (Pmode
);
8641 tlsreg
= gen_rtx_REG (Pmode
, 13);
8642 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
8646 tlsreg
= gen_rtx_REG (Pmode
, 2);
8647 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
8651 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
8653 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
8658 rtx got
, tga
, tmp1
, tmp2
;
8660 /* We currently use relocations like @got@tlsgd for tls, which
8661 means the linker will handle allocation of tls entries, placing
8662 them in the .got section. So use a pointer to the .got section,
8663 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8664 or to secondary GOT sections used by 32-bit -fPIC. */
8666 got
= gen_rtx_REG (Pmode
, 2);
8670 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
8673 rtx gsym
= rs6000_got_sym ();
8674 got
= gen_reg_rtx (Pmode
);
8676 rs6000_emit_move (got
, gsym
, Pmode
);
8681 tmp1
= gen_reg_rtx (Pmode
);
8682 tmp2
= gen_reg_rtx (Pmode
);
8683 mem
= gen_const_mem (Pmode
, tmp1
);
8684 lab
= gen_label_rtx ();
8685 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
8686 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
8687 if (TARGET_LINK_STACK
)
8688 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
8689 emit_move_insn (tmp2
, mem
);
8690 rtx_insn
*last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
8691 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
8696 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
8698 rtx arg
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addr
, got
),
8700 global_tlsarg
= arg
;
8701 rtx argreg
= const0_rtx
;
8702 if (TARGET_TLS_MARKERS
)
8704 argreg
= gen_rtx_REG (Pmode
, 3);
8705 emit_insn (gen_rtx_SET (argreg
, arg
));
8708 tga
= rs6000_tls_get_addr ();
8709 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
8711 global_tlsarg
= NULL_RTX
;
8713 edit_tls_call_insn (arg
);
8715 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
8717 rtx arg
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got
),
8719 global_tlsarg
= arg
;
8720 rtx argreg
= const0_rtx
;
8721 if (TARGET_TLS_MARKERS
)
8723 argreg
= gen_rtx_REG (Pmode
, 3);
8724 emit_insn (gen_rtx_SET (argreg
, arg
));
8727 tga
= rs6000_tls_get_addr ();
8728 tmp1
= gen_reg_rtx (Pmode
);
8729 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
8731 global_tlsarg
= NULL_RTX
;
8733 edit_tls_call_insn (arg
);
8735 if (rs6000_tls_size
== 16)
8738 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
8740 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
8742 else if (rs6000_tls_size
== 32)
8744 tmp2
= gen_reg_rtx (Pmode
);
8746 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
8748 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
8751 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
8753 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
8757 tmp2
= gen_reg_rtx (Pmode
);
8759 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
8761 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
8763 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
8769 /* IE, or 64-bit offset LE. */
8770 tmp2
= gen_reg_rtx (Pmode
);
8772 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
8774 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
8777 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
8779 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
8787 /* Only create the global variable for the stack protect guard if we are using
8788 the global flavor of that guard. */
8790 rs6000_init_stack_protect_guard (void)
8792 if (rs6000_stack_protector_guard
== SSP_GLOBAL
)
8793 return default_stack_protect_guard ();
8798 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8801 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
8803 if (GET_CODE (x
) == HIGH
8804 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
8807 /* A TLS symbol in the TOC cannot contain a sum. */
8808 if (GET_CODE (x
) == CONST
8809 && GET_CODE (XEXP (x
, 0)) == PLUS
8810 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
8811 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
8814 /* Do not place an ELF TLS symbol in the constant pool. */
8815 return TARGET_ELF
&& tls_referenced_p (x
);
8818 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8819 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8820 can be addressed relative to the toc pointer. */
8823 use_toc_relative_ref (rtx sym
, machine_mode mode
)
8825 return ((constant_pool_expr_p (sym
)
8826 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
8827 get_pool_mode (sym
)))
8828 || (TARGET_CMODEL
== CMODEL_MEDIUM
8829 && SYMBOL_REF_LOCAL_P (sym
)
8830 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
8833 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
8834 replace the input X, or the original X if no replacement is called for.
8835 The output parameter *WIN is 1 if the calling macro should goto WIN,
8838 For RS/6000, we wish to handle large displacements off a base
8839 register by splitting the addend across an addiu/addis and the mem insn.
8840 This cuts number of extra insns needed from 3 to 1.
8842 On Darwin, we use this to generate code for floating point constants.
8843 A movsf_low is generated so we wind up with 2 instructions rather than 3.
8844 The Darwin code is inside #if TARGET_MACHO because only then are the
8845 machopic_* functions defined. */
8847 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
8848 int opnum
, int type
,
8849 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
8851 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
8852 bool quad_offset_p
= mode_supports_dq_form (mode
);
8854 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
8855 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
8858 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
8859 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)
8860 || (mode
== SFmode
&& recog_data
.operand_mode
[0] == V4SFmode
8861 && TARGET_P9_VECTOR
)
8862 || (mode
== SImode
&& recog_data
.operand_mode
[0] == V4SImode
8863 && TARGET_P9_VECTOR
)))
8864 reg_offset_p
= false;
8866 /* We must recognize output that we have already generated ourselves. */
8867 if (GET_CODE (x
) == PLUS
8868 && GET_CODE (XEXP (x
, 0)) == PLUS
8869 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
8870 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
8871 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8873 if (TARGET_DEBUG_ADDR
)
8875 fprintf (stderr
, "\nlegitimize_reload_address push_reload #1:\n");
8878 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8879 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
8880 opnum
, (enum reload_type
) type
);
8885 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
8886 if (GET_CODE (x
) == LO_SUM
8887 && GET_CODE (XEXP (x
, 0)) == HIGH
)
8889 if (TARGET_DEBUG_ADDR
)
8891 fprintf (stderr
, "\nlegitimize_reload_address push_reload #2:\n");
8894 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8895 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8896 opnum
, (enum reload_type
) type
);
8902 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
8903 && GET_CODE (x
) == LO_SUM
8904 && GET_CODE (XEXP (x
, 0)) == PLUS
8905 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
8906 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
8907 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
8908 && machopic_operand_p (XEXP (x
, 1)))
8910 /* Result of previous invocation of this function on Darwin
8911 floating point constant. */
8912 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8913 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8914 opnum
, (enum reload_type
) type
);
8920 if (TARGET_CMODEL
!= CMODEL_SMALL
8923 && small_toc_ref (x
, VOIDmode
))
8925 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
8926 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
8927 if (TARGET_DEBUG_ADDR
)
8929 fprintf (stderr
, "\nlegitimize_reload_address push_reload #3:\n");
8932 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8933 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8934 opnum
, (enum reload_type
) type
);
8939 if (GET_CODE (x
) == PLUS
8940 && REG_P (XEXP (x
, 0))
8941 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
8942 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
8943 && CONST_INT_P (XEXP (x
, 1))
8945 && (quad_offset_p
|| !VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
8947 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
8948 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
8950 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8952 /* Check for 32-bit overflow or quad addresses with one of the
8953 four least significant bits set. */
8954 if (high
+ low
!= val
8955 || (quad_offset_p
&& (low
& 0xf)))
8961 /* Reload the high part into a base reg; leave the low part
8962 in the mem directly. */
8964 x
= gen_rtx_PLUS (GET_MODE (x
),
8965 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
8969 if (TARGET_DEBUG_ADDR
)
8971 fprintf (stderr
, "\nlegitimize_reload_address push_reload #4:\n");
8974 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8975 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
8976 opnum
, (enum reload_type
) type
);
8981 if (GET_CODE (x
) == SYMBOL_REF
8984 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
8986 && DEFAULT_ABI
== ABI_DARWIN
8987 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
8988 && machopic_symbol_defined_p (x
)
8990 && DEFAULT_ABI
== ABI_V4
8993 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
8994 The same goes for DImode without 64-bit gprs and DFmode and DDmode
8996 ??? Assume floating point reg based on mode? This assumption is
8997 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
8998 where reload ends up doing a DFmode load of a constant from
8999 mem using two gprs. Unfortunately, at this point reload
9000 hasn't yet selected regs so poking around in reload data
9001 won't help and even if we could figure out the regs reliably,
9002 we'd still want to allow this transformation when the mem is
9003 naturally aligned. Since we say the address is good here, we
9004 can't disable offsets from LO_SUMs in mem_operand_gpr.
9005 FIXME: Allow offset from lo_sum for other modes too, when
9006 mem is sufficiently aligned.
9008 Also disallow this if the type can go in VMX/Altivec registers, since
9009 those registers do not have d-form (reg+offset) address modes. */
9010 && !reg_addr
[mode
].scalar_in_vmx_p
9015 && (mode
!= TImode
|| !TARGET_VSX
)
9017 && (mode
!= DImode
|| TARGET_POWERPC64
)
9018 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
9019 || TARGET_HARD_FLOAT
))
9024 rtx offset
= machopic_gen_offset (x
);
9025 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9026 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
9027 gen_rtx_HIGH (Pmode
, offset
)), offset
);
9031 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9032 gen_rtx_HIGH (Pmode
, x
), x
);
9034 if (TARGET_DEBUG_ADDR
)
9036 fprintf (stderr
, "\nlegitimize_reload_address push_reload #5:\n");
9039 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9040 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9041 opnum
, (enum reload_type
) type
);
9046 /* Reload an offset address wrapped by an AND that represents the
9047 masking of the lower bits. Strip the outer AND and let reload
9048 convert the offset address into an indirect address. For VSX,
9049 force reload to create the address with an AND in a separate
9050 register, because we can't guarantee an altivec register will
9052 if (VECTOR_MEM_ALTIVEC_P (mode
)
9053 && GET_CODE (x
) == AND
9054 && GET_CODE (XEXP (x
, 0)) == PLUS
9055 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
9056 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
9057 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9058 && INTVAL (XEXP (x
, 1)) == -16)
9068 && GET_CODE (x
) == SYMBOL_REF
9069 && use_toc_relative_ref (x
, mode
))
9071 x
= create_TOC_reference (x
, NULL_RTX
);
9072 if (TARGET_CMODEL
!= CMODEL_SMALL
)
9074 if (TARGET_DEBUG_ADDR
)
9076 fprintf (stderr
, "\nlegitimize_reload_address push_reload #6:\n");
9079 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9080 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9081 opnum
, (enum reload_type
) type
);
9090 /* Debug version of rs6000_legitimize_reload_address. */
9092 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
9093 int opnum
, int type
,
9094 int ind_levels
, int *win
)
9096 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
9099 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9100 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9101 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
9105 fprintf (stderr
, "Same address returned\n");
9107 fprintf (stderr
, "NULL returned\n");
9110 fprintf (stderr
, "New address:\n");
9117 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9118 that is a valid memory address for an instruction.
9119 The MODE argument is the machine mode for the MEM expression
9120 that wants to use this address.
9122 On the RS/6000, there are four valid address: a SYMBOL_REF that
9123 refers to a constant pool entry of an address (or the sum of it
9124 plus a constant), a short (16-bit signed) constant plus a register,
9125 the sum of two registers, or a register indirect, possibly with an
9126 auto-increment. For DFmode, DDmode and DImode with a constant plus
9127 register, we must ensure that both words are addressable or PowerPC64
9128 with offset word aligned.
9130 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9131 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9132 because adjacent memory cells are accessed by adding word-sized offsets
9133 during assembly output. */
9135 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
9137 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
9138 bool quad_offset_p
= mode_supports_dq_form (mode
);
9140 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9141 if (VECTOR_MEM_ALTIVEC_P (mode
)
9142 && GET_CODE (x
) == AND
9143 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9144 && INTVAL (XEXP (x
, 1)) == -16)
9147 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
9149 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
9152 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
9153 && mode_supports_pre_incdec_p (mode
)
9154 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
9156 /* Handle restricted vector d-form offsets in ISA 3.0. */
9159 if (quad_address_p (x
, mode
, reg_ok_strict
))
9162 else if (virtual_stack_registers_memory_p (x
))
9165 else if (reg_offset_p
)
9167 if (legitimate_small_data_p (mode
, x
))
9169 if (legitimate_constant_pool_address_p (x
, mode
,
9170 reg_ok_strict
|| lra_in_progress
))
9174 /* For TImode, if we have TImode in VSX registers, only allow register
9175 indirect addresses. This will allow the values to go in either GPRs
9176 or VSX registers without reloading. The vector types would tend to
9177 go into VSX registers, so we allow REG+REG, while TImode seems
9178 somewhat split, in that some uses are GPR based, and some VSX based. */
9179 /* FIXME: We could loosen this by changing the following to
9180 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9181 but currently we cannot allow REG+REG addressing for TImode. See
9182 PR72827 for complete details on how this ends up hoodwinking DSE. */
9183 if (mode
== TImode
&& TARGET_VSX
)
9185 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9188 && GET_CODE (x
) == PLUS
9189 && GET_CODE (XEXP (x
, 0)) == REG
9190 && (XEXP (x
, 0) == virtual_stack_vars_rtx
9191 || XEXP (x
, 0) == arg_pointer_rtx
)
9192 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9194 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
9196 if (!FLOAT128_2REG_P (mode
)
9197 && (TARGET_HARD_FLOAT
9199 || (mode
!= DFmode
&& mode
!= DDmode
))
9200 && (TARGET_POWERPC64
|| mode
!= DImode
)
9201 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
9203 && !avoiding_indexed_address_p (mode
)
9204 && legitimate_indexed_address_p (x
, reg_ok_strict
))
9206 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
9207 && mode_supports_pre_modify_p (mode
)
9208 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
9209 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
9210 reg_ok_strict
, false)
9211 || (!avoiding_indexed_address_p (mode
)
9212 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
9213 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
9215 if (reg_offset_p
&& !quad_offset_p
9216 && legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
9221 /* Debug version of rs6000_legitimate_address_p. */
9223 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
9226 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
9228 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9229 "strict = %d, reload = %s, code = %s\n",
9230 ret
? "true" : "false",
9231 GET_MODE_NAME (mode
),
9233 (reload_completed
? "after" : "before"),
9234 GET_RTX_NAME (GET_CODE (x
)));
9240 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9243 rs6000_mode_dependent_address_p (const_rtx addr
,
9244 addr_space_t as ATTRIBUTE_UNUSED
)
9246 return rs6000_mode_dependent_address_ptr (addr
);
9249 /* Go to LABEL if ADDR (a legitimate address expression)
9250 has an effect that depends on the machine mode it is used for.
9252 On the RS/6000 this is true of all integral offsets (since AltiVec
9253 and VSX modes don't allow them) or is a pre-increment or decrement.
9255 ??? Except that due to conceptual problems in offsettable_address_p
9256 we can't really report the problems of integral offsets. So leave
9257 this assuming that the adjustable offset must be valid for the
9258 sub-words of a TFmode operand, which is what we had before. */
9261 rs6000_mode_dependent_address (const_rtx addr
)
9263 switch (GET_CODE (addr
))
9266 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9267 is considered a legitimate address before reload, so there
9268 are no offset restrictions in that case. Note that this
9269 condition is safe in strict mode because any address involving
9270 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9271 been rejected as illegitimate. */
9272 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
9273 && XEXP (addr
, 0) != arg_pointer_rtx
9274 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
9276 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
9277 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
9282 /* Anything in the constant pool is sufficiently aligned that
9283 all bytes have the same high part address. */
9284 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
9286 /* Auto-increment cases are now treated generically in recog.c. */
9288 return TARGET_UPDATE
;
9290 /* AND is only allowed in Altivec loads. */
9301 /* Debug version of rs6000_mode_dependent_address. */
9303 rs6000_debug_mode_dependent_address (const_rtx addr
)
9305 bool ret
= rs6000_mode_dependent_address (addr
);
9307 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
9308 ret
? "true" : "false");
9314 /* Implement FIND_BASE_TERM. */
9317 rs6000_find_base_term (rtx op
)
9322 if (GET_CODE (base
) == CONST
)
9323 base
= XEXP (base
, 0);
9324 if (GET_CODE (base
) == PLUS
)
9325 base
= XEXP (base
, 0);
9326 if (GET_CODE (base
) == UNSPEC
)
9327 switch (XINT (base
, 1))
9330 case UNSPEC_MACHOPIC_OFFSET
:
9331 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9332 for aliasing purposes. */
9333 return XVECEXP (base
, 0, 0);
9339 /* More elaborate version of recog's offsettable_memref_p predicate
9340 that works around the ??? note of rs6000_mode_dependent_address.
9341 In particular it accepts
9343 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9345 in 32-bit mode, that the recog predicate rejects. */
9348 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
, bool strict
)
9355 /* First mimic offsettable_memref_p. */
9356 if (offsettable_address_p (strict
, GET_MODE (op
), XEXP (op
, 0)))
9359 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9360 the latter predicate knows nothing about the mode of the memory
9361 reference and, therefore, assumes that it is the largest supported
9362 mode (TFmode). As a consequence, legitimate offsettable memory
9363 references are rejected. rs6000_legitimate_offset_address_p contains
9364 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9365 at least with a little bit of help here given that we know the
9366 actual registers used. */
9367 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
9368 || GET_MODE_SIZE (reg_mode
) == 4);
9369 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
9370 strict
, worst_case
);
9373 /* Determine the reassociation width to be used in reassociate_bb.
9374 This takes into account how many parallel operations we
9375 can actually do of a given type, and also the latency.
9379 vect add/sub/mul 2/cycle
9380 fp add/sub/mul 2/cycle
9385 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
9388 switch (rs6000_tune
)
9390 case PROCESSOR_POWER8
:
9391 case PROCESSOR_POWER9
:
9392 if (DECIMAL_FLOAT_MODE_P (mode
))
9394 if (VECTOR_MODE_P (mode
))
9396 if (INTEGRAL_MODE_P (mode
))
9398 if (FLOAT_MODE_P (mode
))
9407 /* Change register usage conditional on target flags. */
9409 rs6000_conditional_register_usage (void)
9413 if (TARGET_DEBUG_TARGET
)
9414 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
9416 /* Set MQ register fixed (already call_used) so that it will not be
9420 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9422 fixed_regs
[13] = call_used_regs
[13]
9423 = call_really_used_regs
[13] = 1;
9425 /* Conditionally disable FPRs. */
9426 if (TARGET_SOFT_FLOAT
)
9427 for (i
= 32; i
< 64; i
++)
9428 fixed_regs
[i
] = call_used_regs
[i
]
9429 = call_really_used_regs
[i
] = 1;
9431 /* The TOC register is not killed across calls in a way that is
9432 visible to the compiler. */
9433 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9434 call_really_used_regs
[2] = 0;
9436 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
9437 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9439 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
9440 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9441 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9442 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9444 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
9445 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9446 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9447 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9449 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
9450 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9451 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9453 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
9455 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
9456 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9457 call_really_used_regs
[VRSAVE_REGNO
] = 1;
9460 if (TARGET_ALTIVEC
|| TARGET_VSX
)
9461 global_regs
[VSCR_REGNO
] = 1;
9463 if (TARGET_ALTIVEC_ABI
)
9465 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
9466 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9468 /* AIX reserves VR20:31 in non-extended ABI mode. */
9470 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
9471 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9476 /* Output insns to set DEST equal to the constant SOURCE as a series of
9477 lis, ori and shl instructions and return TRUE. */
9480 rs6000_emit_set_const (rtx dest
, rtx source
)
9482 machine_mode mode
= GET_MODE (dest
);
9487 gcc_checking_assert (CONST_INT_P (source
));
9488 c
= INTVAL (source
);
9493 emit_insn (gen_rtx_SET (dest
, source
));
9497 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
9499 emit_insn (gen_rtx_SET (copy_rtx (temp
),
9500 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
9501 emit_insn (gen_rtx_SET (dest
,
9502 gen_rtx_IOR (SImode
, copy_rtx (temp
),
9503 GEN_INT (c
& 0xffff))));
9507 if (!TARGET_POWERPC64
)
9511 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
9513 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
9515 emit_move_insn (hi
, GEN_INT (c
>> 32));
9516 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
9517 emit_move_insn (lo
, GEN_INT (c
));
9520 rs6000_emit_set_long_const (dest
, c
);
9527 insn
= get_last_insn ();
9528 set
= single_set (insn
);
9529 if (! CONSTANT_P (SET_SRC (set
)))
9530 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
9535 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9536 Output insns to set DEST equal to the constant C as a series of
9537 lis, ori and shl instructions. */
9540 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
9543 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
9553 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
9554 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
9555 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
9557 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
9558 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
9560 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9562 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9563 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
9565 emit_move_insn (dest
,
9566 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9569 else if (ud3
== 0 && ud4
== 0)
9571 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9573 gcc_assert (ud2
& 0x8000);
9574 emit_move_insn (copy_rtx (temp
),
9575 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
9577 emit_move_insn (copy_rtx (temp
),
9578 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9580 emit_move_insn (dest
,
9581 gen_rtx_ZERO_EXTEND (DImode
,
9582 gen_lowpart (SImode
,
9585 else if ((ud4
== 0xffff && (ud3
& 0x8000))
9586 || (ud4
== 0 && ! (ud3
& 0x8000)))
9588 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9590 emit_move_insn (copy_rtx (temp
),
9591 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
9593 emit_move_insn (copy_rtx (temp
),
9594 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9596 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9597 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
9600 emit_move_insn (dest
,
9601 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9606 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9608 emit_move_insn (copy_rtx (temp
),
9609 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
9611 emit_move_insn (copy_rtx (temp
),
9612 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9615 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
9616 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
9619 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9620 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9621 GEN_INT (ud2
<< 16)));
9623 emit_move_insn (dest
,
9624 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9629 /* Helper for the following. Get rid of [r+r] memory refs
9630 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9633 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
9635 if (GET_CODE (operands
[0]) == MEM
9636 && GET_CODE (XEXP (operands
[0], 0)) != REG
9637 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
9638 GET_MODE (operands
[0]), false))
9640 = replace_equiv_address (operands
[0],
9641 copy_addr_to_reg (XEXP (operands
[0], 0)));
9643 if (GET_CODE (operands
[1]) == MEM
9644 && GET_CODE (XEXP (operands
[1], 0)) != REG
9645 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
9646 GET_MODE (operands
[1]), false))
9648 = replace_equiv_address (operands
[1],
9649 copy_addr_to_reg (XEXP (operands
[1], 0)));
9652 /* Generate a vector of constants to permute MODE for a little-endian
9653 storage operation by swapping the two halves of a vector. */
9655 rs6000_const_vec (machine_mode mode
)
9683 v
= rtvec_alloc (subparts
);
9685 for (i
= 0; i
< subparts
/ 2; ++i
)
9686 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
9687 for (i
= subparts
/ 2; i
< subparts
; ++i
)
9688 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
9693 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9696 rs6000_emit_le_vsx_permute (rtx dest
, rtx source
, machine_mode mode
)
9698 /* Scalar permutations are easier to express in integer modes rather than
9699 floating-point modes, so cast them here. We use V1TImode instead
9700 of TImode to ensure that the values don't go through GPRs. */
9701 if (FLOAT128_VECTOR_P (mode
))
9703 dest
= gen_lowpart (V1TImode
, dest
);
9704 source
= gen_lowpart (V1TImode
, source
);
9708 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9710 if (mode
== TImode
|| mode
== V1TImode
)
9711 emit_insn (gen_rtx_SET (dest
, gen_rtx_ROTATE (mode
, source
,
9715 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
9716 emit_insn (gen_rtx_SET (dest
, gen_rtx_VEC_SELECT (mode
, source
, par
)));
9720 /* Emit a little-endian load from vector memory location SOURCE to VSX
9721 register DEST in mode MODE. The load is done with two permuting
9722 insn's that represent an lxvd2x and xxpermdi. */
9724 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
9726 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9728 if (mode
== TImode
|| mode
== V1TImode
)
9731 dest
= gen_lowpart (V2DImode
, dest
);
9732 source
= adjust_address (source
, V2DImode
, 0);
9735 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
9736 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
9737 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
9740 /* Emit a little-endian store to vector memory location DEST from VSX
9741 register SOURCE in mode MODE. The store is done with two permuting
9742 insn's that represent an xxpermdi and an stxvd2x. */
9744 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
9746 /* This should never be called during or after LRA, because it does
9747 not re-permute the source register. It is intended only for use
9749 gcc_assert (!lra_in_progress
&& !reload_completed
);
9751 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9753 if (mode
== TImode
|| mode
== V1TImode
)
9756 dest
= adjust_address (dest
, V2DImode
, 0);
9757 source
= gen_lowpart (V2DImode
, source
);
9760 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
9761 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
9762 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
9765 /* Emit a sequence representing a little-endian VSX load or store,
9766 moving data from SOURCE to DEST in mode MODE. This is done
9767 separately from rs6000_emit_move to ensure it is called only
9768 during expand. LE VSX loads and stores introduced later are
9769 handled with a split. The expand-time RTL generation allows
9770 us to optimize away redundant pairs of register-permutes. */
9772 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
9774 gcc_assert (!BYTES_BIG_ENDIAN
9775 && VECTOR_MEM_VSX_P (mode
)
9776 && !TARGET_P9_VECTOR
9777 && !gpr_or_gpr_p (dest
, source
)
9778 && (MEM_P (source
) ^ MEM_P (dest
)));
9782 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
9783 rs6000_emit_le_vsx_load (dest
, source
, mode
);
9787 if (!REG_P (source
))
9788 source
= force_reg (mode
, source
);
9789 rs6000_emit_le_vsx_store (dest
, source
, mode
);
9793 /* Return whether a SFmode or SImode move can be done without converting one
9794 mode to another. This arrises when we have:
9796 (SUBREG:SF (REG:SI ...))
9797 (SUBREG:SI (REG:SF ...))
9799 and one of the values is in a floating point/vector register, where SFmode
9800 scalars are stored in DFmode format. */
9803 valid_sf_si_move (rtx dest
, rtx src
, machine_mode mode
)
9805 if (TARGET_ALLOW_SF_SUBREG
)
9808 if (mode
!= SFmode
&& GET_MODE_CLASS (mode
) != MODE_INT
)
9811 if (!SUBREG_P (src
) || !sf_subreg_operand (src
, mode
))
9814 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9815 if (SUBREG_P (dest
))
9817 rtx dest_subreg
= SUBREG_REG (dest
);
9818 rtx src_subreg
= SUBREG_REG (src
);
9819 return GET_MODE (dest_subreg
) == GET_MODE (src_subreg
);
9826 /* Helper function to change moves with:
9828 (SUBREG:SF (REG:SI)) and
9829 (SUBREG:SI (REG:SF))
9831 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9832 values are stored as DFmode values in the VSX registers. We need to convert
9833 the bits before we can use a direct move or operate on the bits in the
9834 vector register as an integer type.
9836 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9839 rs6000_emit_move_si_sf_subreg (rtx dest
, rtx source
, machine_mode mode
)
9841 if (TARGET_DIRECT_MOVE_64BIT
&& !lra_in_progress
&& !reload_completed
9842 && (!SUBREG_P (dest
) || !sf_subreg_operand (dest
, mode
))
9843 && SUBREG_P (source
) && sf_subreg_operand (source
, mode
))
9845 rtx inner_source
= SUBREG_REG (source
);
9846 machine_mode inner_mode
= GET_MODE (inner_source
);
9848 if (mode
== SImode
&& inner_mode
== SFmode
)
9850 emit_insn (gen_movsi_from_sf (dest
, inner_source
));
9854 if (mode
== SFmode
&& inner_mode
== SImode
)
9856 emit_insn (gen_movsf_from_si (dest
, inner_source
));
9864 /* Emit a move from SOURCE to DEST in mode MODE. */
9866 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
9870 operands
[1] = source
;
9872 if (TARGET_DEBUG_ADDR
)
9875 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9876 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9877 GET_MODE_NAME (mode
),
9880 can_create_pseudo_p ());
9882 fprintf (stderr
, "source:\n");
9886 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
9887 if (CONST_WIDE_INT_P (operands
[1])
9888 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9890 /* This should be fixed with the introduction of CONST_WIDE_INT. */
9894 #ifdef HAVE_AS_GNU_ATTRIBUTE
9895 /* If we use a long double type, set the flags in .gnu_attribute that say
9896 what the long double type is. This is to allow the linker's warning
9897 message for the wrong long double to be useful, even if the function does
9898 not do a call (for example, doing a 128-bit add on power9 if the long
9899 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9900 used if they aren't the default long dobule type. */
9901 if (rs6000_gnu_attr
&& (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
))
9903 if (TARGET_LONG_DOUBLE_128
&& (mode
== TFmode
|| mode
== TCmode
))
9904 rs6000_passes_float
= rs6000_passes_long_double
= true;
9906 else if (!TARGET_LONG_DOUBLE_128
&& (mode
== DFmode
|| mode
== DCmode
))
9907 rs6000_passes_float
= rs6000_passes_long_double
= true;
9911 /* See if we need to special case SImode/SFmode SUBREG moves. */
9912 if ((mode
== SImode
|| mode
== SFmode
) && SUBREG_P (source
)
9913 && rs6000_emit_move_si_sf_subreg (dest
, source
, mode
))
9916 /* Check if GCC is setting up a block move that will end up using FP
9917 registers as temporaries. We must make sure this is acceptable. */
9918 if (GET_CODE (operands
[0]) == MEM
9919 && GET_CODE (operands
[1]) == MEM
9921 && (rs6000_slow_unaligned_access (DImode
, MEM_ALIGN (operands
[0]))
9922 || rs6000_slow_unaligned_access (DImode
, MEM_ALIGN (operands
[1])))
9923 && ! (rs6000_slow_unaligned_access (SImode
,
9924 (MEM_ALIGN (operands
[0]) > 32
9925 ? 32 : MEM_ALIGN (operands
[0])))
9926 || rs6000_slow_unaligned_access (SImode
,
9927 (MEM_ALIGN (operands
[1]) > 32
9928 ? 32 : MEM_ALIGN (operands
[1]))))
9929 && ! MEM_VOLATILE_P (operands
[0])
9930 && ! MEM_VOLATILE_P (operands
[1]))
9932 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
9933 adjust_address (operands
[1], SImode
, 0));
9934 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
9935 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
9939 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
9940 && !gpc_reg_operand (operands
[1], mode
))
9941 operands
[1] = force_reg (mode
, operands
[1]);
9943 /* Recognize the case where operand[1] is a reference to thread-local
9944 data and load its address to a register. */
9945 if (tls_referenced_p (operands
[1]))
9947 enum tls_model model
;
9948 rtx tmp
= operands
[1];
9951 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
9953 addend
= XEXP (XEXP (tmp
, 0), 1);
9954 tmp
= XEXP (XEXP (tmp
, 0), 0);
9957 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
9958 model
= SYMBOL_REF_TLS_MODEL (tmp
);
9959 gcc_assert (model
!= 0);
9961 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
9964 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
9965 tmp
= force_operand (tmp
, operands
[0]);
9970 /* 128-bit constant floating-point values on Darwin should really be loaded
9971 as two parts. However, this premature splitting is a problem when DFmode
9972 values can go into Altivec registers. */
9973 if (FLOAT128_IBM_P (mode
) && !reg_addr
[DFmode
].scalar_in_vmx_p
9974 && GET_CODE (operands
[1]) == CONST_DOUBLE
)
9976 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
9977 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
9979 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
9980 GET_MODE_SIZE (DFmode
)),
9981 simplify_gen_subreg (DFmode
, operands
[1], mode
,
9982 GET_MODE_SIZE (DFmode
)),
9987 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9988 p1:SD) if p1 is not of floating point class and p0 is spilled as
9989 we can have no analogous movsd_store for this. */
9990 if (lra_in_progress
&& mode
== DDmode
9991 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
9992 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
9993 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
9994 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
9997 int regno
= REGNO (SUBREG_REG (operands
[1]));
9999 if (regno
>= FIRST_PSEUDO_REGISTER
)
10001 cl
= reg_preferred_class (regno
);
10002 regno
= reg_renumber
[regno
];
10004 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
10006 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10009 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
10010 operands
[1] = SUBREG_REG (operands
[1]);
10013 if (lra_in_progress
10015 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
10016 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10017 && (REG_P (operands
[1])
10018 || (GET_CODE (operands
[1]) == SUBREG
10019 && REG_P (SUBREG_REG (operands
[1])))))
10021 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
10022 ? SUBREG_REG (operands
[1]) : operands
[1]);
10025 if (regno
>= FIRST_PSEUDO_REGISTER
)
10027 cl
= reg_preferred_class (regno
);
10028 gcc_assert (cl
!= NO_REGS
);
10029 regno
= reg_renumber
[regno
];
10031 regno
= ira_class_hard_regs
[cl
][0];
10033 if (FP_REGNO_P (regno
))
10035 if (GET_MODE (operands
[0]) != DDmode
)
10036 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
10037 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
10039 else if (INT_REGNO_P (regno
))
10040 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10045 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10046 p:DD)) if p0 is not of floating point class and p1 is spilled as
10047 we can have no analogous movsd_load for this. */
10048 if (lra_in_progress
&& mode
== DDmode
10049 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
10050 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
10051 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10052 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10055 int regno
= REGNO (SUBREG_REG (operands
[0]));
10057 if (regno
>= FIRST_PSEUDO_REGISTER
)
10059 cl
= reg_preferred_class (regno
);
10060 regno
= reg_renumber
[regno
];
10062 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
10064 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10067 operands
[0] = SUBREG_REG (operands
[0]);
10068 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
10071 if (lra_in_progress
10073 && (REG_P (operands
[0])
10074 || (GET_CODE (operands
[0]) == SUBREG
10075 && REG_P (SUBREG_REG (operands
[0]))))
10076 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10077 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10079 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
10080 ? SUBREG_REG (operands
[0]) : operands
[0]);
10083 if (regno
>= FIRST_PSEUDO_REGISTER
)
10085 cl
= reg_preferred_class (regno
);
10086 gcc_assert (cl
!= NO_REGS
);
10087 regno
= reg_renumber
[regno
];
10089 regno
= ira_class_hard_regs
[cl
][0];
10091 if (FP_REGNO_P (regno
))
10093 if (GET_MODE (operands
[1]) != DDmode
)
10094 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
10095 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
10097 else if (INT_REGNO_P (regno
))
10098 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10104 /* FIXME: In the long term, this switch statement should go away
10105 and be replaced by a sequence of tests based on things like
10111 if (CONSTANT_P (operands
[1])
10112 && GET_CODE (operands
[1]) != CONST_INT
)
10113 operands
[1] = force_const_mem (mode
, operands
[1]);
10120 if (FLOAT128_2REG_P (mode
))
10121 rs6000_eliminate_indexed_memrefs (operands
);
10128 if (CONSTANT_P (operands
[1])
10129 && ! easy_fp_constant (operands
[1], mode
))
10130 operands
[1] = force_const_mem (mode
, operands
[1]);
10140 if (CONSTANT_P (operands
[1])
10141 && !easy_vector_constant (operands
[1], mode
))
10142 operands
[1] = force_const_mem (mode
, operands
[1]);
10147 /* Use default pattern for address of ELF small data */
10150 && DEFAULT_ABI
== ABI_V4
10151 && (GET_CODE (operands
[1]) == SYMBOL_REF
10152 || GET_CODE (operands
[1]) == CONST
)
10153 && small_data_operand (operands
[1], mode
))
10155 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10159 if (DEFAULT_ABI
== ABI_V4
10160 && mode
== Pmode
&& mode
== SImode
10161 && flag_pic
== 1 && got_operand (operands
[1], mode
))
10163 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
10167 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
10171 && CONSTANT_P (operands
[1])
10172 && GET_CODE (operands
[1]) != HIGH
10173 && GET_CODE (operands
[1]) != CONST_INT
)
10175 rtx target
= (!can_create_pseudo_p ()
10177 : gen_reg_rtx (mode
));
10179 /* If this is a function address on -mcall-aixdesc,
10180 convert it to the address of the descriptor. */
10181 if (DEFAULT_ABI
== ABI_AIX
10182 && GET_CODE (operands
[1]) == SYMBOL_REF
10183 && XSTR (operands
[1], 0)[0] == '.')
10185 const char *name
= XSTR (operands
[1], 0);
10187 while (*name
== '.')
10189 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
10190 CONSTANT_POOL_ADDRESS_P (new_ref
)
10191 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
10192 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
10193 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
10194 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
10195 operands
[1] = new_ref
;
10198 if (DEFAULT_ABI
== ABI_DARWIN
)
10201 if (MACHO_DYNAMIC_NO_PIC_P
)
10203 /* Take care of any required data indirection. */
10204 operands
[1] = rs6000_machopic_legitimize_pic_address (
10205 operands
[1], mode
, operands
[0]);
10206 if (operands
[0] != operands
[1])
10207 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10211 emit_insn (gen_macho_high (target
, operands
[1]));
10212 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
10216 emit_insn (gen_elf_high (target
, operands
[1]));
10217 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
10221 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10222 and we have put it in the TOC, we just need to make a TOC-relative
10223 reference to it. */
10225 && GET_CODE (operands
[1]) == SYMBOL_REF
10226 && use_toc_relative_ref (operands
[1], mode
))
10227 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
10228 else if (mode
== Pmode
10229 && CONSTANT_P (operands
[1])
10230 && GET_CODE (operands
[1]) != HIGH
10231 && ((GET_CODE (operands
[1]) != CONST_INT
10232 && ! easy_fp_constant (operands
[1], mode
))
10233 || (GET_CODE (operands
[1]) == CONST_INT
10234 && (num_insns_constant (operands
[1], mode
)
10235 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
10236 || (GET_CODE (operands
[0]) == REG
10237 && FP_REGNO_P (REGNO (operands
[0]))))
10238 && !toc_relative_expr_p (operands
[1], false, NULL
, NULL
)
10239 && (TARGET_CMODEL
== CMODEL_SMALL
10240 || can_create_pseudo_p ()
10241 || (REG_P (operands
[0])
10242 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
10246 /* Darwin uses a special PIC legitimizer. */
10247 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
10250 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
10252 if (operands
[0] != operands
[1])
10253 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10258 /* If we are to limit the number of things we put in the TOC and
10259 this is a symbol plus a constant we can add in one insn,
10260 just put the symbol in the TOC and add the constant. */
10261 if (GET_CODE (operands
[1]) == CONST
10262 && TARGET_NO_SUM_IN_TOC
10263 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
10264 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
10265 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
10266 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
10267 && ! side_effects_p (operands
[0]))
10270 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
10271 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
10273 sym
= force_reg (mode
, sym
);
10274 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
10278 operands
[1] = force_const_mem (mode
, operands
[1]);
10281 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
10282 && use_toc_relative_ref (XEXP (operands
[1], 0), mode
))
10284 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
10286 operands
[1] = gen_const_mem (mode
, tocref
);
10287 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
10293 if (!VECTOR_MEM_VSX_P (TImode
))
10294 rs6000_eliminate_indexed_memrefs (operands
);
10298 rs6000_eliminate_indexed_memrefs (operands
);
10302 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
10305 /* Above, we may have called force_const_mem which may have returned
10306 an invalid address. If we can, fix this up; otherwise, reload will
10307 have to deal with it. */
10308 if (GET_CODE (operands
[1]) == MEM
)
10309 operands
[1] = validize_mem (operands
[1]);
10311 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10314 /* Nonzero if we can use a floating-point register to pass this arg. */
10315 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10316 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10317 && (CUM)->fregno <= FP_ARG_MAX_REG \
10318 && TARGET_HARD_FLOAT)
10320 /* Nonzero if we can use an AltiVec register to pass this arg. */
10321 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10322 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10323 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10324 && TARGET_ALTIVEC_ABI \
10327 /* Walk down the type tree of TYPE counting consecutive base elements.
10328 If *MODEP is VOIDmode, then set it to the first valid floating point
10329 or vector type. If a non-floating point or vector type is found, or
10330 if a floating point or vector type that doesn't match a non-VOIDmode
10331 *MODEP is found, then return -1, otherwise return the count in the
10335 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
10338 HOST_WIDE_INT size
;
10340 switch (TREE_CODE (type
))
10343 mode
= TYPE_MODE (type
);
10344 if (!SCALAR_FLOAT_MODE_P (mode
))
10347 if (*modep
== VOIDmode
)
10350 if (*modep
== mode
)
10356 mode
= TYPE_MODE (TREE_TYPE (type
));
10357 if (!SCALAR_FLOAT_MODE_P (mode
))
10360 if (*modep
== VOIDmode
)
10363 if (*modep
== mode
)
10369 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
10372 /* Use V4SImode as representative of all 128-bit vector types. */
10373 size
= int_size_in_bytes (type
);
10383 if (*modep
== VOIDmode
)
10386 /* Vector modes are considered to be opaque: two vectors are
10387 equivalent for the purposes of being homogeneous aggregates
10388 if they are the same size. */
10389 if (*modep
== mode
)
10397 tree index
= TYPE_DOMAIN (type
);
10399 /* Can't handle incomplete types nor sizes that are not
10401 if (!COMPLETE_TYPE_P (type
)
10402 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10405 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
10408 || !TYPE_MAX_VALUE (index
)
10409 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
10410 || !TYPE_MIN_VALUE (index
)
10411 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
10415 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
10416 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
10418 /* There must be no padding. */
10419 if (wi::to_wide (TYPE_SIZE (type
))
10420 != count
* GET_MODE_BITSIZE (*modep
))
10432 /* Can't handle incomplete types nor sizes that are not
10434 if (!COMPLETE_TYPE_P (type
)
10435 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10438 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10440 if (TREE_CODE (field
) != FIELD_DECL
)
10443 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10446 count
+= sub_count
;
10449 /* There must be no padding. */
10450 if (wi::to_wide (TYPE_SIZE (type
))
10451 != count
* GET_MODE_BITSIZE (*modep
))
10458 case QUAL_UNION_TYPE
:
10460 /* These aren't very interesting except in a degenerate case. */
10465 /* Can't handle incomplete types nor sizes that are not
10467 if (!COMPLETE_TYPE_P (type
)
10468 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10471 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10473 if (TREE_CODE (field
) != FIELD_DECL
)
10476 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10479 count
= count
> sub_count
? count
: sub_count
;
10482 /* There must be no padding. */
10483 if (wi::to_wide (TYPE_SIZE (type
))
10484 != count
* GET_MODE_BITSIZE (*modep
))
10497 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10498 float or vector aggregate that shall be passed in FP/vector registers
10499 according to the ELFv2 ABI, return the homogeneous element mode in
10500 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10502 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10505 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
10506 machine_mode
*elt_mode
,
10509 /* Note that we do not accept complex types at the top level as
10510 homogeneous aggregates; these types are handled via the
10511 targetm.calls.split_complex_arg mechanism. Complex types
10512 can be elements of homogeneous aggregates, however. */
10513 if (TARGET_HARD_FLOAT
&& DEFAULT_ABI
== ABI_ELFv2
&& type
10514 && AGGREGATE_TYPE_P (type
))
10516 machine_mode field_mode
= VOIDmode
;
10517 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
10519 if (field_count
> 0)
10521 int reg_size
= ALTIVEC_OR_VSX_VECTOR_MODE (field_mode
) ? 16 : 8;
10522 int field_size
= ROUND_UP (GET_MODE_SIZE (field_mode
), reg_size
);
10524 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10525 up to AGGR_ARG_NUM_REG registers. */
10526 if (field_count
* field_size
<= AGGR_ARG_NUM_REG
* reg_size
)
10529 *elt_mode
= field_mode
;
10531 *n_elts
= field_count
;
10544 /* Return a nonzero value to say to return the function value in
10545 memory, just as large structures are always returned. TYPE will be
10546 the data type of the value, and FNTYPE will be the type of the
10547 function doing the returning, or @code{NULL} for libcalls.
10549 The AIX ABI for the RS/6000 specifies that all structures are
10550 returned in memory. The Darwin ABI does the same.
10552 For the Darwin 64 Bit ABI, a function result can be returned in
10553 registers or in memory, depending on the size of the return data
10554 type. If it is returned in registers, the value occupies the same
10555 registers as it would if it were the first and only function
10556 argument. Otherwise, the function places its result in memory at
10557 the location pointed to by GPR3.
10559 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10560 but a draft put them in memory, and GCC used to implement the draft
10561 instead of the final standard. Therefore, aix_struct_return
10562 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10563 compatibility can change DRAFT_V4_STRUCT_RET to override the
10564 default, and -m switches get the final word. See
10565 rs6000_option_override_internal for more details.
10567 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10568 long double support is enabled. These values are returned in memory.
10570 int_size_in_bytes returns -1 for variable size objects, which go in
10571 memory always. The cast to unsigned makes -1 > 8. */
10574 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
10576 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10578 && rs6000_darwin64_abi
10579 && TREE_CODE (type
) == RECORD_TYPE
10580 && int_size_in_bytes (type
) > 0)
10582 CUMULATIVE_ARGS valcum
;
10586 valcum
.fregno
= FP_ARG_MIN_REG
;
10587 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
10588 /* Do a trial code generation as if this were going to be passed
10589 as an argument; if any part goes in memory, we return NULL. */
10590 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
10593 /* Otherwise fall through to more conventional ABI rules. */
10596 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10597 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
10601 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10602 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
10603 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
10606 if (AGGREGATE_TYPE_P (type
)
10607 && (aix_struct_return
10608 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
10611 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10612 modes only exist for GCC vector types if -maltivec. */
10613 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
10614 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10617 /* Return synthetic vectors in memory. */
10618 if (TREE_CODE (type
) == VECTOR_TYPE
10619 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10621 static bool warned_for_return_big_vectors
= false;
10622 if (!warned_for_return_big_vectors
)
10624 warning (OPT_Wpsabi
, "GCC vector returned by reference: "
10625 "non-standard ABI extension with no compatibility "
10627 warned_for_return_big_vectors
= true;
10632 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
10633 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
10639 /* Specify whether values returned in registers should be at the most
10640 significant end of a register. We want aggregates returned by
10641 value to match the way aggregates are passed to functions. */
10644 rs6000_return_in_msb (const_tree valtype
)
10646 return (DEFAULT_ABI
== ABI_ELFv2
10647 && BYTES_BIG_ENDIAN
10648 && AGGREGATE_TYPE_P (valtype
)
10649 && (rs6000_function_arg_padding (TYPE_MODE (valtype
), valtype
)
10653 #ifdef HAVE_AS_GNU_ATTRIBUTE
10654 /* Return TRUE if a call to function FNDECL may be one that
10655 potentially affects the function calling ABI of the object file. */
10658 call_ABI_of_interest (tree fndecl
)
10660 if (rs6000_gnu_attr
&& symtab
->state
== EXPANSION
)
10662 struct cgraph_node
*c_node
;
10664 /* Libcalls are always interesting. */
10665 if (fndecl
== NULL_TREE
)
10668 /* Any call to an external function is interesting. */
10669 if (DECL_EXTERNAL (fndecl
))
10672 /* Interesting functions that we are emitting in this object file. */
10673 c_node
= cgraph_node::get (fndecl
);
10674 c_node
= c_node
->ultimate_alias_target ();
10675 return !c_node
->only_called_directly_p ();
10681 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10682 for a call to a function whose data type is FNTYPE.
10683 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10685 For incoming args we set the number of arguments in the prototype large
10686 so we never return a PARALLEL. */
10689 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
10690 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
10691 int libcall
, int n_named_args
,
10693 machine_mode return_mode ATTRIBUTE_UNUSED
)
10695 static CUMULATIVE_ARGS zero_cumulative
;
10697 *cum
= zero_cumulative
;
10699 cum
->fregno
= FP_ARG_MIN_REG
;
10700 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
10701 cum
->prototype
= (fntype
&& prototype_p (fntype
));
10702 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
10703 ? CALL_LIBCALL
: CALL_NORMAL
);
10704 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
10705 cum
->stdarg
= stdarg_p (fntype
);
10706 cum
->libcall
= libcall
;
10708 cum
->nargs_prototype
= 0;
10709 if (incoming
|| cum
->prototype
)
10710 cum
->nargs_prototype
= n_named_args
;
10712 /* Check for a longcall attribute. */
10713 if ((!fntype
&& rs6000_default_long_calls
)
10715 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
10716 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
10717 cum
->call_cookie
|= CALL_LONG
;
10718 else if (DEFAULT_ABI
!= ABI_DARWIN
)
10720 bool is_local
= (fndecl
10721 && !DECL_EXTERNAL (fndecl
)
10722 && !DECL_WEAK (fndecl
)
10723 && (*targetm
.binds_local_p
) (fndecl
));
10729 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype
)))
10730 cum
->call_cookie
|= CALL_LONG
;
10735 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype
))))
10736 cum
->call_cookie
|= CALL_LONG
;
10740 if (TARGET_DEBUG_ARG
)
10742 fprintf (stderr
, "\ninit_cumulative_args:");
10745 tree ret_type
= TREE_TYPE (fntype
);
10746 fprintf (stderr
, " ret code = %s,",
10747 get_tree_code_name (TREE_CODE (ret_type
)));
10750 if (cum
->call_cookie
& CALL_LONG
)
10751 fprintf (stderr
, " longcall,");
10753 fprintf (stderr
, " proto = %d, nargs = %d\n",
10754 cum
->prototype
, cum
->nargs_prototype
);
10757 #ifdef HAVE_AS_GNU_ATTRIBUTE
10758 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
))
10760 cum
->escapes
= call_ABI_of_interest (fndecl
);
10767 return_type
= TREE_TYPE (fntype
);
10768 return_mode
= TYPE_MODE (return_type
);
10771 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
10773 if (return_type
!= NULL
)
10775 if (TREE_CODE (return_type
) == RECORD_TYPE
10776 && TYPE_TRANSPARENT_AGGR (return_type
))
10778 return_type
= TREE_TYPE (first_field (return_type
));
10779 return_mode
= TYPE_MODE (return_type
);
10781 if (AGGREGATE_TYPE_P (return_type
)
10782 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
10784 rs6000_returns_struct
= true;
10786 if (SCALAR_FLOAT_MODE_P (return_mode
))
10788 rs6000_passes_float
= true;
10789 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
10790 && (FLOAT128_IBM_P (return_mode
)
10791 || FLOAT128_IEEE_P (return_mode
)
10792 || (return_type
!= NULL
10793 && (TYPE_MAIN_VARIANT (return_type
)
10794 == long_double_type_node
))))
10795 rs6000_passes_long_double
= true;
10797 /* Note if we passed or return a IEEE 128-bit type. We changed
10798 the mangling for these types, and we may need to make an alias
10799 with the old mangling. */
10800 if (FLOAT128_IEEE_P (return_mode
))
10801 rs6000_passes_ieee128
= true;
10803 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
))
10804 rs6000_passes_vector
= true;
10811 && TARGET_ALTIVEC_ABI
10812 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
10814 error ("cannot return value in vector register because"
10815 " altivec instructions are disabled, use %qs"
10816 " to enable them", "-maltivec");
10820 /* The mode the ABI uses for a word. This is not the same as word_mode
10821 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10823 static scalar_int_mode
10824 rs6000_abi_word_mode (void)
10826 return TARGET_32BIT
? SImode
: DImode
;
10829 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10831 rs6000_offload_options (void)
10834 return xstrdup ("-foffload-abi=lp64");
10836 return xstrdup ("-foffload-abi=ilp32");
10839 /* On rs6000, function arguments are promoted, as are function return
10842 static machine_mode
10843 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
10845 int *punsignedp ATTRIBUTE_UNUSED
,
10848 PROMOTE_MODE (mode
, *punsignedp
, type
);
10853 /* Return true if TYPE must be passed on the stack and not in registers. */
10856 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
10858 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
10859 return must_pass_in_stack_var_size (mode
, type
);
10861 return must_pass_in_stack_var_size_or_pad (mode
, type
);
10865 is_complex_IBM_long_double (machine_mode mode
)
10867 return mode
== ICmode
|| (mode
== TCmode
&& FLOAT128_IBM_P (TCmode
));
10870 /* Whether ABI_V4 passes MODE args to a function in floating point
10874 abi_v4_pass_in_fpr (machine_mode mode
, bool named
)
10876 if (!TARGET_HARD_FLOAT
)
10878 if (mode
== DFmode
)
10880 if (mode
== SFmode
&& named
)
10882 /* ABI_V4 passes complex IBM long double in 8 gprs.
10883 Stupid, but we can't change the ABI now. */
10884 if (is_complex_IBM_long_double (mode
))
10886 if (FLOAT128_2REG_P (mode
))
10888 if (DECIMAL_FLOAT_MODE_P (mode
))
10893 /* Implement TARGET_FUNCTION_ARG_PADDING.
10895 For the AIX ABI structs are always stored left shifted in their
10898 static pad_direction
10899 rs6000_function_arg_padding (machine_mode mode
, const_tree type
)
10901 #ifndef AGGREGATE_PADDING_FIXED
10902 #define AGGREGATE_PADDING_FIXED 0
10904 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10905 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10908 if (!AGGREGATE_PADDING_FIXED
)
10910 /* GCC used to pass structures of the same size as integer types as
10911 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10912 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10913 passed padded downward, except that -mstrict-align further
10914 muddied the water in that multi-component structures of 2 and 4
10915 bytes in size were passed padded upward.
10917 The following arranges for best compatibility with previous
10918 versions of gcc, but removes the -mstrict-align dependency. */
10919 if (BYTES_BIG_ENDIAN
)
10921 HOST_WIDE_INT size
= 0;
10923 if (mode
== BLKmode
)
10925 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
10926 size
= int_size_in_bytes (type
);
10929 size
= GET_MODE_SIZE (mode
);
10931 if (size
== 1 || size
== 2 || size
== 4)
10932 return PAD_DOWNWARD
;
10937 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
10939 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
10943 /* Fall back to the default. */
10944 return default_function_arg_padding (mode
, type
);
10947 /* If defined, a C expression that gives the alignment boundary, in bits,
10948 of an argument with the specified mode and type. If it is not defined,
10949 PARM_BOUNDARY is used for all arguments.
10951 V.4 wants long longs and doubles to be double word aligned. Just
10952 testing the mode size is a boneheaded way to do this as it means
10953 that other types such as complex int are also double word aligned.
10954 However, we're stuck with this because changing the ABI might break
10955 existing library interfaces.
10957 Quadword align Altivec/VSX vectors.
10958 Quadword align large synthetic vector types. */
10960 static unsigned int
10961 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
10963 machine_mode elt_mode
;
10966 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10968 if (DEFAULT_ABI
== ABI_V4
10969 && (GET_MODE_SIZE (mode
) == 8
10970 || (TARGET_HARD_FLOAT
10971 && !is_complex_IBM_long_double (mode
)
10972 && FLOAT128_2REG_P (mode
))))
10974 else if (FLOAT128_VECTOR_P (mode
))
10976 else if (type
&& TREE_CODE (type
) == VECTOR_TYPE
10977 && int_size_in_bytes (type
) >= 8
10978 && int_size_in_bytes (type
) < 16)
10980 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
10981 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10982 && int_size_in_bytes (type
) >= 16))
10985 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10986 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10987 -mcompat-align-parm is used. */
10988 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
10989 || DEFAULT_ABI
== ABI_ELFv2
)
10990 && type
&& TYPE_ALIGN (type
) > 64)
10992 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10993 or homogeneous float/vector aggregates here. We already handled
10994 vector aggregates above, but still need to check for float here. */
10995 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
10996 && !SCALAR_FLOAT_MODE_P (elt_mode
));
10998 /* We used to check for BLKmode instead of the above aggregate type
10999 check. Warn when this results in any difference to the ABI. */
11000 if (aggregate_p
!= (mode
== BLKmode
))
11002 static bool warned
;
11003 if (!warned
&& warn_psabi
)
11006 inform (input_location
,
11007 "the ABI of passing aggregates with %d-byte alignment"
11008 " has changed in GCC 5",
11009 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
11017 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11018 implement the "aggregate type" check as a BLKmode check here; this
11019 means certain aggregate types are in fact not aligned. */
11020 if (TARGET_MACHO
&& rs6000_darwin64_abi
11022 && type
&& TYPE_ALIGN (type
) > 64)
11025 return PARM_BOUNDARY
;
11028 /* The offset in words to the start of the parameter save area. */
11030 static unsigned int
11031 rs6000_parm_offset (void)
11033 return (DEFAULT_ABI
== ABI_V4
? 2
11034 : DEFAULT_ABI
== ABI_ELFv2
? 4
11038 /* For a function parm of MODE and TYPE, return the starting word in
11039 the parameter area. NWORDS of the parameter area are already used. */
11041 static unsigned int
11042 rs6000_parm_start (machine_mode mode
, const_tree type
,
11043 unsigned int nwords
)
11045 unsigned int align
;
11047 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
11048 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
11051 /* Compute the size (in words) of a function argument. */
11053 static unsigned long
11054 rs6000_arg_size (machine_mode mode
, const_tree type
)
11056 unsigned long size
;
11058 if (mode
!= BLKmode
)
11059 size
= GET_MODE_SIZE (mode
);
11061 size
= int_size_in_bytes (type
);
11064 return (size
+ 3) >> 2;
11066 return (size
+ 7) >> 3;
11069 /* Use this to flush pending int fields. */
11072 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
11073 HOST_WIDE_INT bitpos
, int final
)
11075 unsigned int startbit
, endbit
;
11076 int intregs
, intoffset
;
11078 /* Handle the situations where a float is taking up the first half
11079 of the GPR, and the other half is empty (typically due to
11080 alignment restrictions). We can detect this by a 8-byte-aligned
11081 int field, or by seeing that this is the final flush for this
11082 argument. Count the word and continue on. */
11083 if (cum
->floats_in_gpr
== 1
11084 && (cum
->intoffset
% 64 == 0
11085 || (cum
->intoffset
== -1 && final
)))
11088 cum
->floats_in_gpr
= 0;
11091 if (cum
->intoffset
== -1)
11094 intoffset
= cum
->intoffset
;
11095 cum
->intoffset
= -1;
11096 cum
->floats_in_gpr
= 0;
11098 if (intoffset
% BITS_PER_WORD
!= 0)
11100 unsigned int bits
= BITS_PER_WORD
- intoffset
% BITS_PER_WORD
;
11101 if (!int_mode_for_size (bits
, 0).exists ())
11103 /* We couldn't find an appropriate mode, which happens,
11104 e.g., in packed structs when there are 3 bytes to load.
11105 Back intoffset back to the beginning of the word in this
11107 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11111 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11112 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11113 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11114 cum
->words
+= intregs
;
11115 /* words should be unsigned. */
11116 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
11118 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
11123 /* The darwin64 ABI calls for us to recurse down through structs,
11124 looking for elements passed in registers. Unfortunately, we have
11125 to track int register count here also because of misalignments
11126 in powerpc alignment mode. */
11129 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
11131 HOST_WIDE_INT startbitpos
)
11135 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11136 if (TREE_CODE (f
) == FIELD_DECL
)
11138 HOST_WIDE_INT bitpos
= startbitpos
;
11139 tree ftype
= TREE_TYPE (f
);
11141 if (ftype
== error_mark_node
)
11143 mode
= TYPE_MODE (ftype
);
11145 if (DECL_SIZE (f
) != 0
11146 && tree_fits_uhwi_p (bit_position (f
)))
11147 bitpos
+= int_bit_position (f
);
11149 /* ??? FIXME: else assume zero offset. */
11151 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11152 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
11153 else if (USE_FP_FOR_ARG_P (cum
, mode
))
11155 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11156 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11157 cum
->fregno
+= n_fpregs
;
11158 /* Single-precision floats present a special problem for
11159 us, because they are smaller than an 8-byte GPR, and so
11160 the structure-packing rules combined with the standard
11161 varargs behavior mean that we want to pack float/float
11162 and float/int combinations into a single register's
11163 space. This is complicated by the arg advance flushing,
11164 which works on arbitrarily large groups of int-type
11166 if (mode
== SFmode
)
11168 if (cum
->floats_in_gpr
== 1)
11170 /* Two floats in a word; count the word and reset
11171 the float count. */
11173 cum
->floats_in_gpr
= 0;
11175 else if (bitpos
% 64 == 0)
11177 /* A float at the beginning of an 8-byte word;
11178 count it and put off adjusting cum->words until
11179 we see if a arg advance flush is going to do it
11181 cum
->floats_in_gpr
++;
11185 /* The float is at the end of a word, preceded
11186 by integer fields, so the arg advance flush
11187 just above has already set cum->words and
11188 everything is taken care of. */
11192 cum
->words
+= n_fpregs
;
11194 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11196 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11200 else if (cum
->intoffset
== -1)
11201 cum
->intoffset
= bitpos
;
11205 /* Check for an item that needs to be considered specially under the darwin 64
11206 bit ABI. These are record types where the mode is BLK or the structure is
11207 8 bytes in size. */
11209 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
11211 return rs6000_darwin64_abi
11212 && ((mode
== BLKmode
11213 && TREE_CODE (type
) == RECORD_TYPE
11214 && int_size_in_bytes (type
) > 0)
11215 || (type
&& TREE_CODE (type
) == RECORD_TYPE
11216 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
11219 /* Update the data in CUM to advance over an argument
11220 of mode MODE and data type TYPE.
11221 (TYPE is null for libcalls where that information may not be available.)
11223 Note that for args passed by reference, function_arg will be called
11224 with MODE and TYPE set to that of the pointer to the arg, not the arg
11228 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
11229 const_tree type
, bool named
, int depth
)
11231 machine_mode elt_mode
;
11234 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11236 /* Only tick off an argument if we're not recursing. */
11238 cum
->nargs_prototype
--;
11240 #ifdef HAVE_AS_GNU_ATTRIBUTE
11241 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
11244 if (SCALAR_FLOAT_MODE_P (mode
))
11246 rs6000_passes_float
= true;
11247 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
11248 && (FLOAT128_IBM_P (mode
)
11249 || FLOAT128_IEEE_P (mode
)
11251 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
)))
11252 rs6000_passes_long_double
= true;
11254 /* Note if we passed or return a IEEE 128-bit type. We changed the
11255 mangling for these types, and we may need to make an alias with
11256 the old mangling. */
11257 if (FLOAT128_IEEE_P (mode
))
11258 rs6000_passes_ieee128
= true;
11260 if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
11261 rs6000_passes_vector
= true;
11265 if (TARGET_ALTIVEC_ABI
11266 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11267 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11268 && int_size_in_bytes (type
) == 16)))
11270 bool stack
= false;
11272 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11274 cum
->vregno
+= n_elts
;
11276 if (!TARGET_ALTIVEC
)
11277 error ("cannot pass argument in vector register because"
11278 " altivec instructions are disabled, use %qs"
11279 " to enable them", "-maltivec");
11281 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11282 even if it is going to be passed in a vector register.
11283 Darwin does the same for variable-argument functions. */
11284 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11286 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
11296 /* Vector parameters must be 16-byte aligned. In 32-bit
11297 mode this means we need to take into account the offset
11298 to the parameter save area. In 64-bit mode, they just
11299 have to start on an even word, since the parameter save
11300 area is 16-byte aligned. */
11302 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11304 align
= cum
->words
& 1;
11305 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
11307 if (TARGET_DEBUG_ARG
)
11309 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
11310 cum
->words
, align
);
11311 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
11312 cum
->nargs_prototype
, cum
->prototype
,
11313 GET_MODE_NAME (mode
));
11317 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11319 int size
= int_size_in_bytes (type
);
11320 /* Variable sized types have size == -1 and are
11321 treated as if consisting entirely of ints.
11322 Pad to 16 byte boundary if needed. */
11323 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11324 && (cum
->words
% 2) != 0)
11326 /* For varargs, we can just go up by the size of the struct. */
11328 cum
->words
+= (size
+ 7) / 8;
11331 /* It is tempting to say int register count just goes up by
11332 sizeof(type)/8, but this is wrong in a case such as
11333 { int; double; int; } [powerpc alignment]. We have to
11334 grovel through the fields for these too. */
11335 cum
->intoffset
= 0;
11336 cum
->floats_in_gpr
= 0;
11337 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
11338 rs6000_darwin64_record_arg_advance_flush (cum
,
11339 size
* BITS_PER_UNIT
, 1);
11341 if (TARGET_DEBUG_ARG
)
11343 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
11344 cum
->words
, TYPE_ALIGN (type
), size
);
11346 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11347 cum
->nargs_prototype
, cum
->prototype
,
11348 GET_MODE_NAME (mode
));
11351 else if (DEFAULT_ABI
== ABI_V4
)
11353 if (abi_v4_pass_in_fpr (mode
, named
))
11355 /* _Decimal128 must use an even/odd register pair. This assumes
11356 that the register number is odd when fregno is odd. */
11357 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11360 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11361 <= FP_ARG_V4_MAX_REG
)
11362 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
11365 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
11366 if (mode
== DFmode
|| FLOAT128_IBM_P (mode
)
11367 || mode
== DDmode
|| mode
== TDmode
)
11368 cum
->words
+= cum
->words
& 1;
11369 cum
->words
+= rs6000_arg_size (mode
, type
);
11374 int n_words
= rs6000_arg_size (mode
, type
);
11375 int gregno
= cum
->sysv_gregno
;
11377 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11378 As does any other 2 word item such as complex int due to a
11379 historical mistake. */
11381 gregno
+= (1 - gregno
) & 1;
11383 /* Multi-reg args are not split between registers and stack. */
11384 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11386 /* Long long is aligned on the stack. So are other 2 word
11387 items such as complex int due to a historical mistake. */
11389 cum
->words
+= cum
->words
& 1;
11390 cum
->words
+= n_words
;
11393 /* Note: continuing to accumulate gregno past when we've started
11394 spilling to the stack indicates the fact that we've started
11395 spilling to the stack to expand_builtin_saveregs. */
11396 cum
->sysv_gregno
= gregno
+ n_words
;
11399 if (TARGET_DEBUG_ARG
)
11401 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11402 cum
->words
, cum
->fregno
);
11403 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
11404 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
11405 fprintf (stderr
, "mode = %4s, named = %d\n",
11406 GET_MODE_NAME (mode
), named
);
11411 int n_words
= rs6000_arg_size (mode
, type
);
11412 int start_words
= cum
->words
;
11413 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
11415 cum
->words
= align_words
+ n_words
;
11417 if (SCALAR_FLOAT_MODE_P (elt_mode
) && TARGET_HARD_FLOAT
)
11419 /* _Decimal128 must be passed in an even/odd float register pair.
11420 This assumes that the register number is odd when fregno is
11422 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11424 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
11427 if (TARGET_DEBUG_ARG
)
11429 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11430 cum
->words
, cum
->fregno
);
11431 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
11432 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
11433 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
11434 named
, align_words
- start_words
, depth
);
11440 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
11441 const_tree type
, bool named
)
11443 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
11447 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11448 structure between cum->intoffset and bitpos to integer registers. */
11451 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
11452 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
11455 unsigned int regno
;
11456 unsigned int startbit
, endbit
;
11457 int this_regno
, intregs
, intoffset
;
11460 if (cum
->intoffset
== -1)
11463 intoffset
= cum
->intoffset
;
11464 cum
->intoffset
= -1;
11466 /* If this is the trailing part of a word, try to only load that
11467 much into the register. Otherwise load the whole register. Note
11468 that in the latter case we may pick up unwanted bits. It's not a
11469 problem at the moment but may wish to revisit. */
11471 if (intoffset
% BITS_PER_WORD
!= 0)
11473 unsigned int bits
= BITS_PER_WORD
- intoffset
% BITS_PER_WORD
;
11474 if (!int_mode_for_size (bits
, 0).exists (&mode
))
11476 /* We couldn't find an appropriate mode, which happens,
11477 e.g., in packed structs when there are 3 bytes to load.
11478 Back intoffset back to the beginning of the word in this
11480 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11487 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11488 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11489 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11490 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
11492 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
11493 cum
->use_stack
= 1;
11495 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
11499 intoffset
/= BITS_PER_UNIT
;
11502 regno
= GP_ARG_MIN_REG
+ this_regno
;
11503 reg
= gen_rtx_REG (mode
, regno
);
11505 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
11508 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
11512 while (intregs
> 0);
11515 /* Recursive workhorse for the following. */
11518 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
11519 HOST_WIDE_INT startbitpos
, rtx rvec
[],
11524 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11525 if (TREE_CODE (f
) == FIELD_DECL
)
11527 HOST_WIDE_INT bitpos
= startbitpos
;
11528 tree ftype
= TREE_TYPE (f
);
11530 if (ftype
== error_mark_node
)
11532 mode
= TYPE_MODE (ftype
);
11534 if (DECL_SIZE (f
) != 0
11535 && tree_fits_uhwi_p (bit_position (f
)))
11536 bitpos
+= int_bit_position (f
);
11538 /* ??? FIXME: else assume zero offset. */
11540 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11541 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
11542 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
11544 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11548 case E_SCmode
: mode
= SFmode
; break;
11549 case E_DCmode
: mode
= DFmode
; break;
11550 case E_TCmode
: mode
= TFmode
; break;
11554 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
11555 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
11557 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
11558 && (mode
== TFmode
|| mode
== TDmode
));
11559 /* Long double or _Decimal128 split over regs and memory. */
11560 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
11564 = gen_rtx_EXPR_LIST (VOIDmode
,
11565 gen_rtx_REG (mode
, cum
->fregno
++),
11566 GEN_INT (bitpos
/ BITS_PER_UNIT
));
11567 if (FLOAT128_2REG_P (mode
))
11570 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11572 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
11574 = gen_rtx_EXPR_LIST (VOIDmode
,
11575 gen_rtx_REG (mode
, cum
->vregno
++),
11576 GEN_INT (bitpos
/ BITS_PER_UNIT
));
11578 else if (cum
->intoffset
== -1)
11579 cum
->intoffset
= bitpos
;
11583 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11584 the register(s) to be used for each field and subfield of a struct
11585 being passed by value, along with the offset of where the
11586 register's value may be found in the block. FP fields go in FP
11587 register, vector fields go in vector registers, and everything
11588 else goes in int registers, packed as in memory.
11590 This code is also used for function return values. RETVAL indicates
11591 whether this is the case.
11593 Much of this is taken from the SPARC V9 port, which has a similar
11594 calling convention. */
11597 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
11598 bool named
, bool retval
)
11600 rtx rvec
[FIRST_PSEUDO_REGISTER
];
11601 int k
= 1, kbase
= 1;
11602 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
11603 /* This is a copy; modifications are not visible to our caller. */
11604 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
11605 CUMULATIVE_ARGS
*cum
= ©_cum
;
11607 /* Pad to 16 byte boundary if needed. */
11608 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11609 && (cum
->words
% 2) != 0)
11612 cum
->intoffset
= 0;
11613 cum
->use_stack
= 0;
11614 cum
->named
= named
;
11616 /* Put entries into rvec[] for individual FP and vector fields, and
11617 for the chunks of memory that go in int regs. Note we start at
11618 element 1; 0 is reserved for an indication of using memory, and
11619 may or may not be filled in below. */
11620 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
11621 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
11623 /* If any part of the struct went on the stack put all of it there.
11624 This hack is because the generic code for
11625 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11626 parts of the struct are not at the beginning. */
11627 if (cum
->use_stack
)
11630 return NULL_RTX
; /* doesn't go in registers at all */
11632 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11634 if (k
> 1 || cum
->use_stack
)
11635 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
11640 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11643 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
11648 rtx rvec
[GP_ARG_NUM_REG
+ 1];
11650 if (align_words
>= GP_ARG_NUM_REG
)
11653 n_units
= rs6000_arg_size (mode
, type
);
11655 /* Optimize the simple case where the arg fits in one gpr, except in
11656 the case of BLKmode due to assign_parms assuming that registers are
11657 BITS_PER_WORD wide. */
11659 || (n_units
== 1 && mode
!= BLKmode
))
11660 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
11663 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
11664 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11665 using a magic NULL_RTX component.
11666 This is not strictly correct. Only some of the arg belongs in
11667 memory, not all of it. However, the normal scheme using
11668 function_arg_partial_nregs can result in unusual subregs, eg.
11669 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11670 store the whole arg to memory is often more efficient than code
11671 to store pieces, and we know that space is available in the right
11672 place for the whole arg. */
11673 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11678 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
11679 rtx off
= GEN_INT (i
++ * 4);
11680 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11682 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
11684 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
11687 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11688 but must also be copied into the parameter save area starting at
11689 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11690 to the GPRs and/or memory. Return the number of elements used. */
11693 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
11694 int align_words
, rtx
*rvec
)
11698 if (align_words
< GP_ARG_NUM_REG
)
11700 int n_words
= rs6000_arg_size (mode
, type
);
11702 if (align_words
+ n_words
> GP_ARG_NUM_REG
11704 || (TARGET_32BIT
&& TARGET_POWERPC64
))
11706 /* If this is partially on the stack, then we only
11707 include the portion actually in registers here. */
11708 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
11711 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
11713 /* Not all of the arg fits in gprs. Say that it goes in memory
11714 too, using a magic NULL_RTX component. Also see comment in
11715 rs6000_mixed_function_arg for why the normal
11716 function_arg_partial_nregs scheme doesn't work in this case. */
11717 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11722 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
11723 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
11724 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11726 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
11730 /* The whole arg fits in gprs. */
11731 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
11732 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
11737 /* It's entirely in memory. */
11738 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11744 /* RVEC is a vector of K components of an argument of mode MODE.
11745 Construct the final function_arg return value from it. */
11748 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
11750 gcc_assert (k
>= 1);
11752 /* Avoid returning a PARALLEL in the trivial cases. */
11755 if (XEXP (rvec
[0], 0) == NULL_RTX
)
11758 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
11759 return XEXP (rvec
[0], 0);
11762 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
11765 /* Determine where to put an argument to a function.
11766 Value is zero to push the argument on the stack,
11767 or a hard register in which to store the argument.
11769 MODE is the argument's machine mode.
11770 TYPE is the data type of the argument (as a tree).
11771 This is null for libcalls where that information may
11773 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11774 the preceding args and about the function being called. It is
11775 not modified in this routine.
11776 NAMED is nonzero if this argument is a named parameter
11777 (otherwise it is an extra parameter matching an ellipsis).
11779 On RS/6000 the first eight words of non-FP are normally in registers
11780 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11781 Under V.4, the first 8 FP args are in registers.
11783 If this is floating-point and no prototype is specified, we use
11784 both an FP and integer register (or possibly FP reg and stack). Library
11785 functions (when CALL_LIBCALL is set) always have the proper types for args,
11786 so we can pass the FP value just in one register. emit_library_function
11787 doesn't support PARALLEL anyway.
11789 Note that for args passed by reference, function_arg will be called
11790 with MODE and TYPE set to that of the pointer to the arg, not the arg
11794 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
11795 const_tree type
, bool named
)
11797 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11798 enum rs6000_abi abi
= DEFAULT_ABI
;
11799 machine_mode elt_mode
;
11802 /* Return a marker to indicate whether CR1 needs to set or clear the
11803 bit that V.4 uses to say fp args were passed in registers.
11804 Assume that we don't need the marker for software floating point,
11805 or compiler generated library calls. */
11806 if (mode
== VOIDmode
)
11809 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
11811 || (cum
->nargs_prototype
< 0
11812 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
)))
11813 && TARGET_HARD_FLOAT
)
11814 return GEN_INT (cum
->call_cookie
11815 | ((cum
->fregno
== FP_ARG_MIN_REG
)
11816 ? CALL_V4_SET_FP_ARGS
11817 : CALL_V4_CLEAR_FP_ARGS
));
11819 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
11822 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11824 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11826 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
11827 if (rslt
!= NULL_RTX
)
11829 /* Else fall through to usual handling. */
11832 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11834 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
11838 /* Do we also need to pass this argument in the parameter save area?
11839 Library support functions for IEEE 128-bit are assumed to not need the
11840 value passed both in GPRs and in vector registers. */
11841 if (TARGET_64BIT
&& !cum
->prototype
11842 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
11844 int align_words
= ROUND_UP (cum
->words
, 2);
11845 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
11848 /* Describe where this argument goes in the vector registers. */
11849 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
11851 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
11852 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
11853 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11856 return rs6000_finish_function_arg (mode
, rvec
, k
);
11858 else if (TARGET_ALTIVEC_ABI
11859 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
11860 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11861 && int_size_in_bytes (type
) == 16)))
11863 if (named
|| abi
== ABI_V4
)
11867 /* Vector parameters to varargs functions under AIX or Darwin
11868 get passed in memory and possibly also in GPRs. */
11869 int align
, align_words
, n_words
;
11870 machine_mode part_mode
;
11872 /* Vector parameters must be 16-byte aligned. In 32-bit
11873 mode this means we need to take into account the offset
11874 to the parameter save area. In 64-bit mode, they just
11875 have to start on an even word, since the parameter save
11876 area is 16-byte aligned. */
11878 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11880 align
= cum
->words
& 1;
11881 align_words
= cum
->words
+ align
;
11883 /* Out of registers? Memory, then. */
11884 if (align_words
>= GP_ARG_NUM_REG
)
11887 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11888 return rs6000_mixed_function_arg (mode
, type
, align_words
);
11890 /* The vector value goes in GPRs. Only the part of the
11891 value in GPRs is reported here. */
11893 n_words
= rs6000_arg_size (mode
, type
);
11894 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
11895 /* Fortunately, there are only two possibilities, the value
11896 is either wholly in GPRs or half in GPRs and half not. */
11897 part_mode
= DImode
;
11899 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
11903 else if (abi
== ABI_V4
)
11905 if (abi_v4_pass_in_fpr (mode
, named
))
11907 /* _Decimal128 must use an even/odd register pair. This assumes
11908 that the register number is odd when fregno is odd. */
11909 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11912 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11913 <= FP_ARG_V4_MAX_REG
)
11914 return gen_rtx_REG (mode
, cum
->fregno
);
11920 int n_words
= rs6000_arg_size (mode
, type
);
11921 int gregno
= cum
->sysv_gregno
;
11923 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11924 As does any other 2 word item such as complex int due to a
11925 historical mistake. */
11927 gregno
+= (1 - gregno
) & 1;
11929 /* Multi-reg args are not split between registers and stack. */
11930 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11933 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11934 return rs6000_mixed_function_arg (mode
, type
,
11935 gregno
- GP_ARG_MIN_REG
);
11936 return gen_rtx_REG (mode
, gregno
);
11941 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
11943 /* _Decimal128 must be passed in an even/odd float register pair.
11944 This assumes that the register number is odd when fregno is odd. */
11945 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11948 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
11950 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
11953 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
11956 /* Do we also need to pass this argument in the parameter
11958 if (type
&& (cum
->nargs_prototype
<= 0
11959 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11960 && TARGET_XL_COMPAT
11961 && align_words
>= GP_ARG_NUM_REG
)))
11962 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
11964 /* Describe where this argument goes in the fprs. */
11965 for (i
= 0; i
< n_elts
11966 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
11968 /* Check if the argument is split over registers and memory.
11969 This can only ever happen for long double or _Decimal128;
11970 complex types are handled via split_complex_arg. */
11971 machine_mode fmode
= elt_mode
;
11972 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
11974 gcc_assert (FLOAT128_2REG_P (fmode
));
11975 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
11978 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
11979 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
11980 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11983 /* If there were not enough FPRs to hold the argument, the rest
11984 usually goes into memory. However, if the current position
11985 is still within the register parameter area, a portion may
11986 actually have to go into GPRs.
11988 Note that it may happen that the portion of the argument
11989 passed in the first "half" of the first GPR was already
11990 passed in the last FPR as well.
11992 For unnamed arguments, we already set up GPRs to cover the
11993 whole argument in rs6000_psave_function_arg, so there is
11994 nothing further to do at this point. */
11995 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
11996 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
11997 && cum
->nargs_prototype
> 0)
11999 static bool warned
;
12001 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
12002 int n_words
= rs6000_arg_size (mode
, type
);
12004 align_words
+= fpr_words
;
12005 n_words
-= fpr_words
;
12009 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
12010 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
12011 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12013 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
12015 if (!warned
&& warn_psabi
)
12018 inform (input_location
,
12019 "the ABI of passing homogeneous float aggregates"
12020 " has changed in GCC 5");
12024 return rs6000_finish_function_arg (mode
, rvec
, k
);
12026 else if (align_words
< GP_ARG_NUM_REG
)
12028 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12029 return rs6000_mixed_function_arg (mode
, type
, align_words
);
12031 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12038 /* For an arg passed partly in registers and partly in memory, this is
12039 the number of bytes passed in registers. For args passed entirely in
12040 registers or entirely in memory, zero. When an arg is described by a
12041 PARALLEL, perhaps using more than one register type, this function
12042 returns the number of bytes used by the first element of the PARALLEL. */
12045 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
12046 tree type
, bool named
)
12048 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12049 bool passed_in_gprs
= true;
12052 machine_mode elt_mode
;
12055 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
12057 if (DEFAULT_ABI
== ABI_V4
)
12060 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
12062 /* If we are passing this arg in the fixed parameter save area (gprs or
12063 memory) as well as VRs, we do not use the partial bytes mechanism;
12064 instead, rs6000_function_arg will return a PARALLEL including a memory
12065 element as necessary. Library support functions for IEEE 128-bit are
12066 assumed to not need the value passed both in GPRs and in vector
12068 if (TARGET_64BIT
&& !cum
->prototype
12069 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
12072 /* Otherwise, we pass in VRs only. Check for partial copies. */
12073 passed_in_gprs
= false;
12074 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
12075 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
12078 /* In this complicated case we just disable the partial_nregs code. */
12079 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
12082 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12084 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
12086 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12088 /* If we are passing this arg in the fixed parameter save area
12089 (gprs or memory) as well as FPRs, we do not use the partial
12090 bytes mechanism; instead, rs6000_function_arg will return a
12091 PARALLEL including a memory element as necessary. */
12093 && (cum
->nargs_prototype
<= 0
12094 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12095 && TARGET_XL_COMPAT
12096 && align_words
>= GP_ARG_NUM_REG
)))
12099 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12100 passed_in_gprs
= false;
12101 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
12103 /* Compute number of bytes / words passed in FPRs. If there
12104 is still space available in the register parameter area
12105 *after* that amount, a part of the argument will be passed
12106 in GPRs. In that case, the total amount passed in any
12107 registers is equal to the amount that would have been passed
12108 in GPRs if everything were passed there, so we fall back to
12109 the GPR code below to compute the appropriate value. */
12110 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
12111 * MIN (8, GET_MODE_SIZE (elt_mode
)));
12112 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
12114 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
12115 passed_in_gprs
= true;
12122 && align_words
< GP_ARG_NUM_REG
12123 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
12124 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
12126 if (ret
!= 0 && TARGET_DEBUG_ARG
)
12127 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
12132 /* A C expression that indicates when an argument must be passed by
12133 reference. If nonzero for an argument, a copy of that argument is
12134 made in memory and a pointer to the argument is passed instead of
12135 the argument itself. The pointer is passed in whatever way is
12136 appropriate for passing a pointer to that type.
12138 Under V.4, aggregates and long double are passed by reference.
12140 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12141 reference unless the AltiVec vector extension ABI is in force.
12143 As an extension to all ABIs, variable sized types are passed by
12147 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
12148 machine_mode mode
, const_tree type
,
12149 bool named ATTRIBUTE_UNUSED
)
12154 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
12155 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
12157 if (TARGET_DEBUG_ARG
)
12158 fprintf (stderr
, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12162 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
12164 if (TARGET_DEBUG_ARG
)
12165 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
12169 if (int_size_in_bytes (type
) < 0)
12171 if (TARGET_DEBUG_ARG
)
12172 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
12176 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12177 modes only exist for GCC vector types if -maltivec. */
12178 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12180 if (TARGET_DEBUG_ARG
)
12181 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
12185 /* Pass synthetic vectors in memory. */
12186 if (TREE_CODE (type
) == VECTOR_TYPE
12187 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
12189 static bool warned_for_pass_big_vectors
= false;
12190 if (TARGET_DEBUG_ARG
)
12191 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
12192 if (!warned_for_pass_big_vectors
)
12194 warning (OPT_Wpsabi
, "GCC vector passed by reference: "
12195 "non-standard ABI extension with no compatibility "
12197 warned_for_pass_big_vectors
= true;
12205 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12206 already processes. Return true if the parameter must be passed
12207 (fully or partially) on the stack. */
12210 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
12216 /* Catch errors. */
12217 if (type
== NULL
|| type
== error_mark_node
)
12220 /* Handle types with no storage requirement. */
12221 if (TYPE_MODE (type
) == VOIDmode
)
12224 /* Handle complex types. */
12225 if (TREE_CODE (type
) == COMPLEX_TYPE
)
12226 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
12227 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
12229 /* Handle transparent aggregates. */
12230 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
12231 && TYPE_TRANSPARENT_AGGR (type
))
12232 type
= TREE_TYPE (first_field (type
));
12234 /* See if this arg was passed by invisible reference. */
12235 if (pass_by_reference (get_cumulative_args (args_so_far
),
12236 TYPE_MODE (type
), type
, true))
12237 type
= build_pointer_type (type
);
12239 /* Find mode as it is passed by the ABI. */
12240 unsignedp
= TYPE_UNSIGNED (type
);
12241 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
12243 /* If we must pass in stack, we need a stack. */
12244 if (rs6000_must_pass_in_stack (mode
, type
))
12247 /* If there is no incoming register, we need a stack. */
12248 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
12249 if (entry_parm
== NULL
)
12252 /* Likewise if we need to pass both in registers and on the stack. */
12253 if (GET_CODE (entry_parm
) == PARALLEL
12254 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
12257 /* Also true if we're partially in registers and partially not. */
12258 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
12261 /* Update info on where next arg arrives in registers. */
12262 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
12266 /* Return true if FUN has no prototype, has a variable argument
12267 list, or passes any parameter in memory. */
12270 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
12272 tree fntype
, result
;
12273 CUMULATIVE_ARGS args_so_far_v
;
12274 cumulative_args_t args_so_far
;
12277 /* Must be a libcall, all of which only use reg parms. */
12282 fntype
= TREE_TYPE (fun
);
12284 /* Varargs functions need the parameter save area. */
12285 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
12288 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
12289 args_so_far
= pack_cumulative_args (&args_so_far_v
);
12291 /* When incoming, we will have been passed the function decl.
12292 It is necessary to use the decl to handle K&R style functions,
12293 where TYPE_ARG_TYPES may not be available. */
12296 gcc_assert (DECL_P (fun
));
12297 result
= DECL_RESULT (fun
);
12300 result
= TREE_TYPE (fntype
);
12302 if (result
&& aggregate_value_p (result
, fntype
))
12304 if (!TYPE_P (result
))
12305 result
= TREE_TYPE (result
);
12306 result
= build_pointer_type (result
);
12307 rs6000_parm_needs_stack (args_so_far
, result
);
12314 for (parm
= DECL_ARGUMENTS (fun
);
12315 parm
&& parm
!= void_list_node
;
12316 parm
= TREE_CHAIN (parm
))
12317 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
12322 function_args_iterator args_iter
;
12325 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
12326 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
12333 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12334 usually a constant depending on the ABI. However, in the ELFv2 ABI
12335 the register parameter area is optional when calling a function that
12336 has a prototype is scope, has no variable argument list, and passes
12337 all parameters in registers. */
12340 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
12342 int reg_parm_stack_space
;
12344 switch (DEFAULT_ABI
)
12347 reg_parm_stack_space
= 0;
12352 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12356 /* ??? Recomputing this every time is a bit expensive. Is there
12357 a place to cache this information? */
12358 if (rs6000_function_parms_need_stack (fun
, incoming
))
12359 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12361 reg_parm_stack_space
= 0;
12365 return reg_parm_stack_space
;
12369 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
12372 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
12377 for (i
= 0; i
< nregs
; i
++)
12379 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
12380 if (reload_completed
)
12382 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
12385 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
12386 i
* GET_MODE_SIZE (reg_mode
));
12389 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
12393 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
12397 /* Perform any needed actions needed for a function that is receiving a
12398 variable number of arguments.
12402 MODE and TYPE are the mode and type of the current parameter.
12404 PRETEND_SIZE is a variable that should be set to the amount of stack
12405 that must be pushed by the prolog to pretend that our caller pushed
12408 Normally, this macro will push all remaining incoming registers on the
12409 stack and set PRETEND_SIZE to the length of the registers pushed. */
12412 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
12413 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
12416 CUMULATIVE_ARGS next_cum
;
12417 int reg_size
= TARGET_32BIT
? 4 : 8;
12418 rtx save_area
= NULL_RTX
, mem
;
12419 int first_reg_offset
;
12420 alias_set_type set
;
12422 /* Skip the last named argument. */
12423 next_cum
= *get_cumulative_args (cum
);
12424 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
12426 if (DEFAULT_ABI
== ABI_V4
)
12428 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
12432 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
12433 HOST_WIDE_INT offset
= 0;
12435 /* Try to optimize the size of the varargs save area.
12436 The ABI requires that ap.reg_save_area is doubleword
12437 aligned, but we don't need to allocate space for all
12438 the bytes, only those to which we actually will save
12440 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
12441 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
12442 if (TARGET_HARD_FLOAT
12443 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
12444 && cfun
->va_list_fpr_size
)
12447 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
12448 * UNITS_PER_FP_WORD
;
12449 if (cfun
->va_list_fpr_size
12450 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12451 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
12453 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12454 * UNITS_PER_FP_WORD
;
12458 offset
= -((first_reg_offset
* reg_size
) & ~7);
12459 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
12461 gpr_reg_num
= cfun
->va_list_gpr_size
;
12462 if (reg_size
== 4 && (first_reg_offset
& 1))
12465 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
12468 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
12469 * UNITS_PER_FP_WORD
12470 - (int) (GP_ARG_NUM_REG
* reg_size
);
12472 if (gpr_size
+ fpr_size
)
12475 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
12476 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
12477 reg_save_area
= XEXP (reg_save_area
, 0);
12478 if (GET_CODE (reg_save_area
) == PLUS
)
12480 gcc_assert (XEXP (reg_save_area
, 0)
12481 == virtual_stack_vars_rtx
);
12482 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
12483 offset
+= INTVAL (XEXP (reg_save_area
, 1));
12486 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
12489 cfun
->machine
->varargs_save_offset
= offset
;
12490 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
12495 first_reg_offset
= next_cum
.words
;
12496 save_area
= crtl
->args
.internal_arg_pointer
;
12498 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
12499 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
12502 set
= get_varargs_alias_set ();
12503 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
12504 && cfun
->va_list_gpr_size
)
12506 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
12508 if (va_list_gpr_counter_field
)
12509 /* V4 va_list_gpr_size counts number of registers needed. */
12510 n_gpr
= cfun
->va_list_gpr_size
;
12512 /* char * va_list instead counts number of bytes needed. */
12513 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
12518 mem
= gen_rtx_MEM (BLKmode
,
12519 plus_constant (Pmode
, save_area
,
12520 first_reg_offset
* reg_size
));
12521 MEM_NOTRAP_P (mem
) = 1;
12522 set_mem_alias_set (mem
, set
);
12523 set_mem_align (mem
, BITS_PER_WORD
);
12525 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
12529 /* Save FP registers if needed. */
12530 if (DEFAULT_ABI
== ABI_V4
12531 && TARGET_HARD_FLOAT
12533 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
12534 && cfun
->va_list_fpr_size
)
12536 int fregno
= next_cum
.fregno
, nregs
;
12537 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
12538 rtx lab
= gen_label_rtx ();
12539 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
12540 * UNITS_PER_FP_WORD
);
12543 (gen_rtx_SET (pc_rtx
,
12544 gen_rtx_IF_THEN_ELSE (VOIDmode
,
12545 gen_rtx_NE (VOIDmode
, cr1
,
12547 gen_rtx_LABEL_REF (VOIDmode
, lab
),
12551 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
12552 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
12554 mem
= gen_rtx_MEM (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
12555 plus_constant (Pmode
, save_area
, off
));
12556 MEM_NOTRAP_P (mem
) = 1;
12557 set_mem_alias_set (mem
, set
);
12558 set_mem_align (mem
, GET_MODE_ALIGNMENT (
12559 TARGET_HARD_FLOAT
? DFmode
: SFmode
));
12560 emit_move_insn (mem
, gen_rtx_REG (
12561 TARGET_HARD_FLOAT
? DFmode
: SFmode
, fregno
));
12568 /* Create the va_list data type. */
12571 rs6000_build_builtin_va_list (void)
12573 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
12575 /* For AIX, prefer 'char *' because that's what the system
12576 header files like. */
12577 if (DEFAULT_ABI
!= ABI_V4
)
12578 return build_pointer_type (char_type_node
);
12580 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
12581 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
12582 get_identifier ("__va_list_tag"), record
);
12584 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
12585 unsigned_char_type_node
);
12586 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
12587 unsigned_char_type_node
);
12588 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12589 every user file. */
12590 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12591 get_identifier ("reserved"), short_unsigned_type_node
);
12592 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12593 get_identifier ("overflow_arg_area"),
12595 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12596 get_identifier ("reg_save_area"),
12599 va_list_gpr_counter_field
= f_gpr
;
12600 va_list_fpr_counter_field
= f_fpr
;
12602 DECL_FIELD_CONTEXT (f_gpr
) = record
;
12603 DECL_FIELD_CONTEXT (f_fpr
) = record
;
12604 DECL_FIELD_CONTEXT (f_res
) = record
;
12605 DECL_FIELD_CONTEXT (f_ovf
) = record
;
12606 DECL_FIELD_CONTEXT (f_sav
) = record
;
12608 TYPE_STUB_DECL (record
) = type_decl
;
12609 TYPE_NAME (record
) = type_decl
;
12610 TYPE_FIELDS (record
) = f_gpr
;
12611 DECL_CHAIN (f_gpr
) = f_fpr
;
12612 DECL_CHAIN (f_fpr
) = f_res
;
12613 DECL_CHAIN (f_res
) = f_ovf
;
12614 DECL_CHAIN (f_ovf
) = f_sav
;
12616 layout_type (record
);
12618 /* The correct type is an array type of one element. */
12619 return build_array_type (record
, build_index_type (size_zero_node
));
12622 /* Implement va_start. */
12625 rs6000_va_start (tree valist
, rtx nextarg
)
12627 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
12628 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
12629 tree gpr
, fpr
, ovf
, sav
, t
;
12631 /* Only SVR4 needs something special. */
12632 if (DEFAULT_ABI
!= ABI_V4
)
12634 std_expand_builtin_va_start (valist
, nextarg
);
12638 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12639 f_fpr
= DECL_CHAIN (f_gpr
);
12640 f_res
= DECL_CHAIN (f_fpr
);
12641 f_ovf
= DECL_CHAIN (f_res
);
12642 f_sav
= DECL_CHAIN (f_ovf
);
12644 valist
= build_simple_mem_ref (valist
);
12645 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12646 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
12648 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
12650 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
12653 /* Count number of gp and fp argument registers used. */
12654 words
= crtl
->args
.info
.words
;
12655 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
12657 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
12660 if (TARGET_DEBUG_ARG
)
12661 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
12662 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
12663 words
, n_gpr
, n_fpr
);
12665 if (cfun
->va_list_gpr_size
)
12667 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
12668 build_int_cst (NULL_TREE
, n_gpr
));
12669 TREE_SIDE_EFFECTS (t
) = 1;
12670 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12673 if (cfun
->va_list_fpr_size
)
12675 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
12676 build_int_cst (NULL_TREE
, n_fpr
));
12677 TREE_SIDE_EFFECTS (t
) = 1;
12678 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12680 #ifdef HAVE_AS_GNU_ATTRIBUTE
12681 if (call_ABI_of_interest (cfun
->decl
))
12682 rs6000_passes_float
= true;
12686 /* Find the overflow area. */
12687 t
= make_tree (TREE_TYPE (ovf
), crtl
->args
.internal_arg_pointer
);
12689 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
12690 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
12691 TREE_SIDE_EFFECTS (t
) = 1;
12692 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12694 /* If there were no va_arg invocations, don't set up the register
12696 if (!cfun
->va_list_gpr_size
12697 && !cfun
->va_list_fpr_size
12698 && n_gpr
< GP_ARG_NUM_REG
12699 && n_fpr
< FP_ARG_V4_MAX_REG
)
12702 /* Find the register save area. */
12703 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
12704 if (cfun
->machine
->varargs_save_offset
)
12705 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
12706 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
12707 TREE_SIDE_EFFECTS (t
) = 1;
12708 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12711 /* Implement va_arg. */
12714 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
12715 gimple_seq
*post_p
)
12717 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
12718 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
12719 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
12720 tree lab_false
, lab_over
, addr
;
12722 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
12726 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
12728 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
12729 return build_va_arg_indirect_ref (t
);
12732 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12733 earlier version of gcc, with the property that it always applied alignment
12734 adjustments to the va-args (even for zero-sized types). The cheapest way
12735 to deal with this is to replicate the effect of the part of
12736 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12738 We don't need to check for pass-by-reference because of the test above.
12739 We can return a simplifed answer, since we know there's no offset to add. */
12742 && rs6000_darwin64_abi
)
12743 || DEFAULT_ABI
== ABI_ELFv2
12744 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
12745 && integer_zerop (TYPE_SIZE (type
)))
12747 unsigned HOST_WIDE_INT align
, boundary
;
12748 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
12749 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
12750 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
12751 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
12752 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
12753 boundary
/= BITS_PER_UNIT
;
12754 if (boundary
> align
)
12757 /* This updates arg ptr by the amount that would be necessary
12758 to align the zero-sized (but not zero-alignment) item. */
12759 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
12760 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
12761 gimplify_and_add (t
, pre_p
);
12763 t
= fold_convert (sizetype
, valist_tmp
);
12764 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
12765 fold_convert (TREE_TYPE (valist
),
12766 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
12767 size_int (-boundary
))));
12768 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
12769 gimplify_and_add (t
, pre_p
);
12771 /* Since it is zero-sized there's no increment for the item itself. */
12772 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
12773 return build_va_arg_indirect_ref (valist_tmp
);
12776 if (DEFAULT_ABI
!= ABI_V4
)
12778 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
12780 tree elem_type
= TREE_TYPE (type
);
12781 machine_mode elem_mode
= TYPE_MODE (elem_type
);
12782 int elem_size
= GET_MODE_SIZE (elem_mode
);
12784 if (elem_size
< UNITS_PER_WORD
)
12786 tree real_part
, imag_part
;
12787 gimple_seq post
= NULL
;
12789 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
12791 /* Copy the value into a temporary, lest the formal temporary
12792 be reused out from under us. */
12793 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
12794 gimple_seq_add_seq (pre_p
, post
);
12796 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
12799 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
12803 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
12806 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12807 f_fpr
= DECL_CHAIN (f_gpr
);
12808 f_res
= DECL_CHAIN (f_fpr
);
12809 f_ovf
= DECL_CHAIN (f_res
);
12810 f_sav
= DECL_CHAIN (f_ovf
);
12812 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12813 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
12815 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
12817 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
12820 size
= int_size_in_bytes (type
);
12821 rsize
= (size
+ 3) / 4;
12822 int pad
= 4 * rsize
- size
;
12825 machine_mode mode
= TYPE_MODE (type
);
12826 if (abi_v4_pass_in_fpr (mode
, false))
12828 /* FP args go in FP registers, if present. */
12830 n_reg
= (size
+ 7) / 8;
12831 sav_ofs
= (TARGET_HARD_FLOAT
? 8 : 4) * 4;
12832 sav_scale
= (TARGET_HARD_FLOAT
? 8 : 4);
12833 if (mode
!= SFmode
&& mode
!= SDmode
)
12838 /* Otherwise into GP registers. */
12847 /* Pull the value out of the saved registers.... */
12850 addr
= create_tmp_var (ptr_type_node
, "addr");
12852 /* AltiVec vectors never go in registers when -mabi=altivec. */
12853 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12857 lab_false
= create_artificial_label (input_location
);
12858 lab_over
= create_artificial_label (input_location
);
12860 /* Long long is aligned in the registers. As are any other 2 gpr
12861 item such as complex int due to a historical mistake. */
12863 if (n_reg
== 2 && reg
== gpr
)
12866 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12867 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
12868 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
12869 unshare_expr (reg
), u
);
12871 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12872 reg number is 0 for f1, so we want to make it odd. */
12873 else if (reg
== fpr
&& mode
== TDmode
)
12875 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12876 build_int_cst (TREE_TYPE (reg
), 1));
12877 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
12880 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
12881 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
12882 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
12883 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
12884 gimplify_and_add (t
, pre_p
);
12888 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
12890 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12891 build_int_cst (TREE_TYPE (reg
), n_reg
));
12892 u
= fold_convert (sizetype
, u
);
12893 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
12894 t
= fold_build_pointer_plus (t
, u
);
12896 /* _Decimal32 varargs are located in the second word of the 64-bit
12897 FP register for 32-bit binaries. */
12898 if (TARGET_32BIT
&& TARGET_HARD_FLOAT
&& mode
== SDmode
)
12899 t
= fold_build_pointer_plus_hwi (t
, size
);
12901 /* Args are passed right-aligned. */
12902 if (BYTES_BIG_ENDIAN
)
12903 t
= fold_build_pointer_plus_hwi (t
, pad
);
12905 gimplify_assign (addr
, t
, pre_p
);
12907 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
12909 stmt
= gimple_build_label (lab_false
);
12910 gimple_seq_add_stmt (pre_p
, stmt
);
12912 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
12914 /* Ensure that we don't find any more args in regs.
12915 Alignment has taken care of for special cases. */
12916 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
12920 /* ... otherwise out of the overflow area. */
12922 /* Care for on-stack alignment if needed. */
12926 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
12927 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
12928 build_int_cst (TREE_TYPE (t
), -align
));
12931 /* Args are passed right-aligned. */
12932 if (BYTES_BIG_ENDIAN
)
12933 t
= fold_build_pointer_plus_hwi (t
, pad
);
12935 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
12937 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
12939 t
= fold_build_pointer_plus_hwi (t
, size
);
12940 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
12944 stmt
= gimple_build_label (lab_over
);
12945 gimple_seq_add_stmt (pre_p
, stmt
);
12948 if (STRICT_ALIGNMENT
12949 && (TYPE_ALIGN (type
)
12950 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
12952 /* The value (of type complex double, for example) may not be
12953 aligned in memory in the saved registers, so copy via a
12954 temporary. (This is the same code as used for SPARC.) */
12955 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
12956 tree dest_addr
= build_fold_addr_expr (tmp
);
12958 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
12959 3, dest_addr
, addr
, size_int (rsize
* 4));
12960 TREE_ADDRESSABLE (tmp
) = 1;
12962 gimplify_and_add (copy
, pre_p
);
12966 addr
= fold_convert (ptrtype
, addr
);
12967 return build_va_arg_indirect_ref (addr
);
12973 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
12976 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
12977 const char *attr_string
= "";
12979 gcc_assert (name
!= NULL
);
12980 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
12982 if (rs6000_builtin_decls
[(int)code
])
12983 fatal_error (input_location
,
12984 "internal error: builtin function %qs already processed",
12987 rs6000_builtin_decls
[(int)code
] = t
=
12988 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
12990 /* Set any special attributes. */
12991 if ((classify
& RS6000_BTC_CONST
) != 0)
12993 /* const function, function only depends on the inputs. */
12994 TREE_READONLY (t
) = 1;
12995 TREE_NOTHROW (t
) = 1;
12996 attr_string
= ", const";
12998 else if ((classify
& RS6000_BTC_PURE
) != 0)
13000 /* pure function, function can read global memory, but does not set any
13002 DECL_PURE_P (t
) = 1;
13003 TREE_NOTHROW (t
) = 1;
13004 attr_string
= ", pure";
13006 else if ((classify
& RS6000_BTC_FP
) != 0)
13008 /* Function is a math function. If rounding mode is on, then treat the
13009 function as not reading global memory, but it can have arbitrary side
13010 effects. If it is off, then assume the function is a const function.
13011 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13012 builtin-attribute.def that is used for the math functions. */
13013 TREE_NOTHROW (t
) = 1;
13014 if (flag_rounding_math
)
13016 DECL_PURE_P (t
) = 1;
13017 DECL_IS_NOVOPS (t
) = 1;
13018 attr_string
= ", fp, pure";
13022 TREE_READONLY (t
) = 1;
13023 attr_string
= ", fp, const";
13026 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
13027 gcc_unreachable ();
13029 if (TARGET_DEBUG_BUILTIN
)
13030 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
13031 (int)code
, name
, attr_string
);
13034 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13036 #undef RS6000_BUILTIN_0
13037 #undef RS6000_BUILTIN_1
13038 #undef RS6000_BUILTIN_2
13039 #undef RS6000_BUILTIN_3
13040 #undef RS6000_BUILTIN_A
13041 #undef RS6000_BUILTIN_D
13042 #undef RS6000_BUILTIN_H
13043 #undef RS6000_BUILTIN_P
13044 #undef RS6000_BUILTIN_X
13046 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13047 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13048 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13049 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13050 { MASK, ICODE, NAME, ENUM },
13052 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13053 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13054 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13055 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13056 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13058 static const struct builtin_description bdesc_3arg
[] =
13060 #include "rs6000-builtin.def"
13063 /* DST operations: void foo (void *, const int, const char). */
13065 #undef RS6000_BUILTIN_0
13066 #undef RS6000_BUILTIN_1
13067 #undef RS6000_BUILTIN_2
13068 #undef RS6000_BUILTIN_3
13069 #undef RS6000_BUILTIN_A
13070 #undef RS6000_BUILTIN_D
13071 #undef RS6000_BUILTIN_H
13072 #undef RS6000_BUILTIN_P
13073 #undef RS6000_BUILTIN_X
13075 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13076 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13077 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13078 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13079 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13080 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13081 { MASK, ICODE, NAME, ENUM },
13083 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13084 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13085 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13087 static const struct builtin_description bdesc_dst
[] =
13089 #include "rs6000-builtin.def"
13092 /* Simple binary operations: VECc = foo (VECa, VECb). */
13094 #undef RS6000_BUILTIN_0
13095 #undef RS6000_BUILTIN_1
13096 #undef RS6000_BUILTIN_2
13097 #undef RS6000_BUILTIN_3
13098 #undef RS6000_BUILTIN_A
13099 #undef RS6000_BUILTIN_D
13100 #undef RS6000_BUILTIN_H
13101 #undef RS6000_BUILTIN_P
13102 #undef RS6000_BUILTIN_X
13104 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13105 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13106 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13107 { MASK, ICODE, NAME, ENUM },
13109 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13110 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13111 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13112 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13113 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13114 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13116 static const struct builtin_description bdesc_2arg
[] =
13118 #include "rs6000-builtin.def"
13121 #undef RS6000_BUILTIN_0
13122 #undef RS6000_BUILTIN_1
13123 #undef RS6000_BUILTIN_2
13124 #undef RS6000_BUILTIN_3
13125 #undef RS6000_BUILTIN_A
13126 #undef RS6000_BUILTIN_D
13127 #undef RS6000_BUILTIN_H
13128 #undef RS6000_BUILTIN_P
13129 #undef RS6000_BUILTIN_X
13131 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13132 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13133 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13134 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13135 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13136 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13137 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13138 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13139 { MASK, ICODE, NAME, ENUM },
13141 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13143 /* AltiVec predicates. */
13145 static const struct builtin_description bdesc_altivec_preds
[] =
13147 #include "rs6000-builtin.def"
13150 /* ABS* operations. */
13152 #undef RS6000_BUILTIN_0
13153 #undef RS6000_BUILTIN_1
13154 #undef RS6000_BUILTIN_2
13155 #undef RS6000_BUILTIN_3
13156 #undef RS6000_BUILTIN_A
13157 #undef RS6000_BUILTIN_D
13158 #undef RS6000_BUILTIN_H
13159 #undef RS6000_BUILTIN_P
13160 #undef RS6000_BUILTIN_X
13162 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13163 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13164 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13165 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13166 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13167 { MASK, ICODE, NAME, ENUM },
13169 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13170 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13171 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13172 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13174 static const struct builtin_description bdesc_abs
[] =
13176 #include "rs6000-builtin.def"
13179 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13182 #undef RS6000_BUILTIN_0
13183 #undef RS6000_BUILTIN_1
13184 #undef RS6000_BUILTIN_2
13185 #undef RS6000_BUILTIN_3
13186 #undef RS6000_BUILTIN_A
13187 #undef RS6000_BUILTIN_D
13188 #undef RS6000_BUILTIN_H
13189 #undef RS6000_BUILTIN_P
13190 #undef RS6000_BUILTIN_X
13192 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13193 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13194 { MASK, ICODE, NAME, ENUM },
13196 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13197 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13198 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13199 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13200 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13201 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13202 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13204 static const struct builtin_description bdesc_1arg
[] =
13206 #include "rs6000-builtin.def"
13209 /* Simple no-argument operations: result = __builtin_darn_32 () */
13211 #undef RS6000_BUILTIN_0
13212 #undef RS6000_BUILTIN_1
13213 #undef RS6000_BUILTIN_2
13214 #undef RS6000_BUILTIN_3
13215 #undef RS6000_BUILTIN_A
13216 #undef RS6000_BUILTIN_D
13217 #undef RS6000_BUILTIN_H
13218 #undef RS6000_BUILTIN_P
13219 #undef RS6000_BUILTIN_X
13221 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13222 { MASK, ICODE, NAME, ENUM },
13224 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13225 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13226 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13227 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13228 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13229 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13230 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13231 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13233 static const struct builtin_description bdesc_0arg
[] =
13235 #include "rs6000-builtin.def"
13238 /* HTM builtins. */
13239 #undef RS6000_BUILTIN_0
13240 #undef RS6000_BUILTIN_1
13241 #undef RS6000_BUILTIN_2
13242 #undef RS6000_BUILTIN_3
13243 #undef RS6000_BUILTIN_A
13244 #undef RS6000_BUILTIN_D
13245 #undef RS6000_BUILTIN_H
13246 #undef RS6000_BUILTIN_P
13247 #undef RS6000_BUILTIN_X
13249 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13250 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13251 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13252 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13253 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13254 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13255 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13256 { MASK, ICODE, NAME, ENUM },
13258 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13259 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13261 static const struct builtin_description bdesc_htm
[] =
13263 #include "rs6000-builtin.def"
13266 #undef RS6000_BUILTIN_0
13267 #undef RS6000_BUILTIN_1
13268 #undef RS6000_BUILTIN_2
13269 #undef RS6000_BUILTIN_3
13270 #undef RS6000_BUILTIN_A
13271 #undef RS6000_BUILTIN_D
13272 #undef RS6000_BUILTIN_H
13273 #undef RS6000_BUILTIN_P
13275 /* Return true if a builtin function is overloaded. */
13277 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
13279 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
13283 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode
)
13285 return rs6000_builtin_info
[(int)fncode
].name
;
13288 /* Expand an expression EXP that calls a builtin without arguments. */
13290 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
13293 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13295 if (icode
== CODE_FOR_nothing
)
13296 /* Builtin not supported on this processor. */
13299 if (icode
== CODE_FOR_rs6000_mffsl
13300 && rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13302 error ("__builtin_mffsl() not supported with -msoft-float");
13307 || GET_MODE (target
) != tmode
13308 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13309 target
= gen_reg_rtx (tmode
);
13311 pat
= GEN_FCN (icode
) (target
);
13321 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
13324 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13325 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13326 rtx op0
= expand_normal (arg0
);
13327 rtx op1
= expand_normal (arg1
);
13328 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13329 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13331 if (icode
== CODE_FOR_nothing
)
13332 /* Builtin not supported on this processor. */
13335 /* If we got invalid arguments bail out before generating bad rtl. */
13336 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13339 if (GET_CODE (op0
) != CONST_INT
13340 || INTVAL (op0
) > 255
13341 || INTVAL (op0
) < 0)
13343 error ("argument 1 must be an 8-bit field value");
13347 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13348 op0
= copy_to_mode_reg (mode0
, op0
);
13350 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13351 op1
= copy_to_mode_reg (mode1
, op1
);
13353 pat
= GEN_FCN (icode
) (op0
, op1
);
13362 rs6000_expand_mtfsb_builtin (enum insn_code icode
, tree exp
)
13365 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13366 rtx op0
= expand_normal (arg0
);
13368 if (icode
== CODE_FOR_nothing
)
13369 /* Builtin not supported on this processor. */
13372 if (rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13374 error ("__builtin_mtfsb0 and __builtin_mtfsb1 not supported with -msoft-float");
13378 /* If we got invalid arguments bail out before generating bad rtl. */
13379 if (arg0
== error_mark_node
)
13382 /* Only allow bit numbers 0 to 31. */
13383 if (!u5bit_cint_operand (op0
, VOIDmode
))
13385 error ("Argument must be a constant between 0 and 31.");
13389 pat
= GEN_FCN (icode
) (op0
);
13398 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode
, tree exp
)
13401 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13402 rtx op0
= expand_normal (arg0
);
13403 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13405 if (icode
== CODE_FOR_nothing
)
13406 /* Builtin not supported on this processor. */
13409 if (rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13411 error ("__builtin_set_fpscr_rn not supported with -msoft-float");
13415 /* If we got invalid arguments bail out before generating bad rtl. */
13416 if (arg0
== error_mark_node
)
13419 /* If the argument is a constant, check the range. Argument can only be a
13420 2-bit value. Unfortunately, can't check the range of the value at
13421 compile time if the argument is a variable. The least significant two
13422 bits of the argument, regardless of type, are used to set the rounding
13423 mode. All other bits are ignored. */
13424 if (GET_CODE (op0
) == CONST_INT
&& !const_0_to_3_operand(op0
, VOIDmode
))
13426 error ("Argument must be a value between 0 and 3.");
13430 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13431 op0
= copy_to_mode_reg (mode0
, op0
);
13433 pat
= GEN_FCN (icode
) (op0
);
13441 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode
, tree exp
)
13444 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13445 rtx op0
= expand_normal (arg0
);
13446 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13449 /* Builtin not supported in 32-bit mode. */
13450 fatal_error (input_location
,
13451 "__builtin_set_fpscr_drn is not supported in 32-bit mode.");
13453 if (rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13455 error ("__builtin_set_fpscr_drn not supported with -msoft-float");
13459 if (icode
== CODE_FOR_nothing
)
13460 /* Builtin not supported on this processor. */
13463 /* If we got invalid arguments bail out before generating bad rtl. */
13464 if (arg0
== error_mark_node
)
13467 /* If the argument is a constant, check the range. Agrument can only be a
13468 3-bit value. Unfortunately, can't check the range of the value at
13469 compile time if the argument is a variable. The least significant two
13470 bits of the argument, regardless of type, are used to set the rounding
13471 mode. All other bits are ignored. */
13472 if (GET_CODE (op0
) == CONST_INT
&& !const_0_to_7_operand(op0
, VOIDmode
))
13474 error ("Argument must be a value between 0 and 7.");
13478 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13479 op0
= copy_to_mode_reg (mode0
, op0
);
13481 pat
= GEN_FCN (icode
) (op0
);
13490 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13493 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13494 rtx op0
= expand_normal (arg0
);
13495 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13496 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13498 if (icode
== CODE_FOR_nothing
)
13499 /* Builtin not supported on this processor. */
13502 /* If we got invalid arguments bail out before generating bad rtl. */
13503 if (arg0
== error_mark_node
)
13506 if (icode
== CODE_FOR_altivec_vspltisb
13507 || icode
== CODE_FOR_altivec_vspltish
13508 || icode
== CODE_FOR_altivec_vspltisw
)
13510 /* Only allow 5-bit *signed* literals. */
13511 if (GET_CODE (op0
) != CONST_INT
13512 || INTVAL (op0
) > 15
13513 || INTVAL (op0
) < -16)
13515 error ("argument 1 must be a 5-bit signed literal");
13516 return CONST0_RTX (tmode
);
13521 || GET_MODE (target
) != tmode
13522 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13523 target
= gen_reg_rtx (tmode
);
13525 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13526 op0
= copy_to_mode_reg (mode0
, op0
);
13528 pat
= GEN_FCN (icode
) (target
, op0
);
13537 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
13539 rtx pat
, scratch1
, scratch2
;
13540 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13541 rtx op0
= expand_normal (arg0
);
13542 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13543 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13545 /* If we have invalid arguments, bail out before generating bad rtl. */
13546 if (arg0
== error_mark_node
)
13550 || GET_MODE (target
) != tmode
13551 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13552 target
= gen_reg_rtx (tmode
);
13554 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13555 op0
= copy_to_mode_reg (mode0
, op0
);
13557 scratch1
= gen_reg_rtx (mode0
);
13558 scratch2
= gen_reg_rtx (mode0
);
13560 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
13569 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13572 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13573 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13574 rtx op0
= expand_normal (arg0
);
13575 rtx op1
= expand_normal (arg1
);
13576 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13577 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13578 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13580 if (icode
== CODE_FOR_nothing
)
13581 /* Builtin not supported on this processor. */
13584 /* If we got invalid arguments bail out before generating bad rtl. */
13585 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13588 if (icode
== CODE_FOR_unpackv1ti
13589 || icode
== CODE_FOR_unpackkf
13590 || icode
== CODE_FOR_unpacktf
13591 || icode
== CODE_FOR_unpackif
13592 || icode
== CODE_FOR_unpacktd
)
13594 /* Only allow 1-bit unsigned literals. */
13596 if (TREE_CODE (arg1
) != INTEGER_CST
13597 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
13599 error ("argument 2 must be a 1-bit unsigned literal");
13600 return CONST0_RTX (tmode
);
13603 else if (icode
== CODE_FOR_altivec_vspltw
)
13605 /* Only allow 2-bit unsigned literals. */
13607 if (TREE_CODE (arg1
) != INTEGER_CST
13608 || TREE_INT_CST_LOW (arg1
) & ~3)
13610 error ("argument 2 must be a 2-bit unsigned literal");
13611 return CONST0_RTX (tmode
);
13614 else if (icode
== CODE_FOR_altivec_vsplth
)
13616 /* Only allow 3-bit unsigned literals. */
13618 if (TREE_CODE (arg1
) != INTEGER_CST
13619 || TREE_INT_CST_LOW (arg1
) & ~7)
13621 error ("argument 2 must be a 3-bit unsigned literal");
13622 return CONST0_RTX (tmode
);
13625 else if (icode
== CODE_FOR_altivec_vspltb
)
13627 /* Only allow 4-bit unsigned literals. */
13629 if (TREE_CODE (arg1
) != INTEGER_CST
13630 || TREE_INT_CST_LOW (arg1
) & ~15)
13632 error ("argument 2 must be a 4-bit unsigned literal");
13633 return CONST0_RTX (tmode
);
13636 else if (icode
== CODE_FOR_altivec_vcfux
13637 || icode
== CODE_FOR_altivec_vcfsx
13638 || icode
== CODE_FOR_altivec_vctsxs
13639 || icode
== CODE_FOR_altivec_vctuxs
)
13641 /* Only allow 5-bit unsigned literals. */
13643 if (TREE_CODE (arg1
) != INTEGER_CST
13644 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13646 error ("argument 2 must be a 5-bit unsigned literal");
13647 return CONST0_RTX (tmode
);
13650 else if (icode
== CODE_FOR_dfptstsfi_eq_dd
13651 || icode
== CODE_FOR_dfptstsfi_lt_dd
13652 || icode
== CODE_FOR_dfptstsfi_gt_dd
13653 || icode
== CODE_FOR_dfptstsfi_unordered_dd
13654 || icode
== CODE_FOR_dfptstsfi_eq_td
13655 || icode
== CODE_FOR_dfptstsfi_lt_td
13656 || icode
== CODE_FOR_dfptstsfi_gt_td
13657 || icode
== CODE_FOR_dfptstsfi_unordered_td
)
13659 /* Only allow 6-bit unsigned literals. */
13661 if (TREE_CODE (arg0
) != INTEGER_CST
13662 || !IN_RANGE (TREE_INT_CST_LOW (arg0
), 0, 63))
13664 error ("argument 1 must be a 6-bit unsigned literal");
13665 return CONST0_RTX (tmode
);
13668 else if (icode
== CODE_FOR_xststdcqp_kf
13669 || icode
== CODE_FOR_xststdcqp_tf
13670 || icode
== CODE_FOR_xststdcdp
13671 || icode
== CODE_FOR_xststdcsp
13672 || icode
== CODE_FOR_xvtstdcdp
13673 || icode
== CODE_FOR_xvtstdcsp
)
13675 /* Only allow 7-bit unsigned literals. */
13677 if (TREE_CODE (arg1
) != INTEGER_CST
13678 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 127))
13680 error ("argument 2 must be a 7-bit unsigned literal");
13681 return CONST0_RTX (tmode
);
13686 || GET_MODE (target
) != tmode
13687 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13688 target
= gen_reg_rtx (tmode
);
13690 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13691 op0
= copy_to_mode_reg (mode0
, op0
);
13692 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13693 op1
= copy_to_mode_reg (mode1
, op1
);
13695 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13704 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13707 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
13708 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13709 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13710 rtx op0
= expand_normal (arg0
);
13711 rtx op1
= expand_normal (arg1
);
13712 machine_mode tmode
= SImode
;
13713 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13714 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13717 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
13719 error ("argument 1 of %qs must be a constant",
13720 "__builtin_altivec_predicate");
13724 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
13726 gcc_assert (mode0
== mode1
);
13728 /* If we have invalid arguments, bail out before generating bad rtl. */
13729 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13733 || GET_MODE (target
) != tmode
13734 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13735 target
= gen_reg_rtx (tmode
);
13737 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13738 op0
= copy_to_mode_reg (mode0
, op0
);
13739 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13740 op1
= copy_to_mode_reg (mode1
, op1
);
13742 /* Note that for many of the relevant operations (e.g. cmpne or
13743 cmpeq) with float or double operands, it makes more sense for the
13744 mode of the allocated scratch register to select a vector of
13745 integer. But the choice to copy the mode of operand 0 was made
13746 long ago and there are no plans to change it. */
13747 scratch
= gen_reg_rtx (mode0
);
13749 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13754 /* The vec_any* and vec_all* predicates use the same opcodes for two
13755 different operations, but the bits in CR6 will be different
13756 depending on what information we want. So we have to play tricks
13757 with CR6 to get the right bits out.
13759 If you think this is disgusting, look at the specs for the
13760 AltiVec predicates. */
13762 switch (cr6_form_int
)
13765 emit_insn (gen_cr6_test_for_zero (target
));
13768 emit_insn (gen_cr6_test_for_zero_reverse (target
));
13771 emit_insn (gen_cr6_test_for_lt (target
));
13774 emit_insn (gen_cr6_test_for_lt_reverse (target
));
13777 error ("argument 1 of %qs is out of range",
13778 "__builtin_altivec_predicate");
13786 swap_endian_selector_for_mode (machine_mode mode
)
13788 unsigned int swap1
[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13789 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13790 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13791 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13793 unsigned int *swaparray
, i
;
13813 gcc_unreachable ();
13816 for (i
= 0; i
< 16; ++i
)
13817 perm
[i
] = GEN_INT (swaparray
[i
]);
13819 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
,
13820 gen_rtvec_v (16, perm
)));
13824 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
13827 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13828 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13829 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13830 machine_mode mode0
= Pmode
;
13831 machine_mode mode1
= Pmode
;
13832 rtx op0
= expand_normal (arg0
);
13833 rtx op1
= expand_normal (arg1
);
13835 if (icode
== CODE_FOR_nothing
)
13836 /* Builtin not supported on this processor. */
13839 /* If we got invalid arguments bail out before generating bad rtl. */
13840 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13844 || GET_MODE (target
) != tmode
13845 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13846 target
= gen_reg_rtx (tmode
);
13848 op1
= copy_to_mode_reg (mode1
, op1
);
13850 /* For LVX, express the RTL accurately by ANDing the address with -16.
13851 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13852 so the raw address is fine. */
13853 if (icode
== CODE_FOR_altivec_lvx_v1ti
13854 || icode
== CODE_FOR_altivec_lvx_v2df
13855 || icode
== CODE_FOR_altivec_lvx_v2di
13856 || icode
== CODE_FOR_altivec_lvx_v4sf
13857 || icode
== CODE_FOR_altivec_lvx_v4si
13858 || icode
== CODE_FOR_altivec_lvx_v8hi
13859 || icode
== CODE_FOR_altivec_lvx_v16qi
)
13862 if (op0
== const0_rtx
)
13866 op0
= copy_to_mode_reg (mode0
, op0
);
13867 rawaddr
= gen_rtx_PLUS (Pmode
, op1
, op0
);
13869 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
13870 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, addr
);
13872 emit_insn (gen_rtx_SET (target
, addr
));
13876 if (op0
== const0_rtx
)
13877 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
13880 op0
= copy_to_mode_reg (mode0
, op0
);
13881 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
,
13882 gen_rtx_PLUS (Pmode
, op1
, op0
));
13885 pat
= GEN_FCN (icode
) (target
, addr
);
13895 altivec_expand_stxvl_builtin (enum insn_code icode
, tree exp
)
13898 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13899 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13900 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13901 rtx op0
= expand_normal (arg0
);
13902 rtx op1
= expand_normal (arg1
);
13903 rtx op2
= expand_normal (arg2
);
13904 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13905 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13906 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
13908 if (icode
== CODE_FOR_nothing
)
13909 /* Builtin not supported on this processor. */
13912 /* If we got invalid arguments bail out before generating bad rtl. */
13913 if (arg0
== error_mark_node
13914 || arg1
== error_mark_node
13915 || arg2
== error_mark_node
)
13918 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13919 op0
= copy_to_mode_reg (mode0
, op0
);
13920 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13921 op1
= copy_to_mode_reg (mode1
, op1
);
13922 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13923 op2
= copy_to_mode_reg (mode2
, op2
);
13925 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
13933 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
13935 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13936 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13937 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13938 rtx op0
= expand_normal (arg0
);
13939 rtx op1
= expand_normal (arg1
);
13940 rtx op2
= expand_normal (arg2
);
13941 rtx pat
, addr
, rawaddr
;
13942 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13943 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
13944 machine_mode mode1
= Pmode
;
13945 machine_mode mode2
= Pmode
;
13947 /* Invalid arguments. Bail before doing anything stoopid! */
13948 if (arg0
== error_mark_node
13949 || arg1
== error_mark_node
13950 || arg2
== error_mark_node
)
13953 op2
= copy_to_mode_reg (mode2
, op2
);
13955 /* For STVX, express the RTL accurately by ANDing the address with -16.
13956 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13957 so the raw address is fine. */
13958 if (icode
== CODE_FOR_altivec_stvx_v2df
13959 || icode
== CODE_FOR_altivec_stvx_v2di
13960 || icode
== CODE_FOR_altivec_stvx_v4sf
13961 || icode
== CODE_FOR_altivec_stvx_v4si
13962 || icode
== CODE_FOR_altivec_stvx_v8hi
13963 || icode
== CODE_FOR_altivec_stvx_v16qi
)
13965 if (op1
== const0_rtx
)
13969 op1
= copy_to_mode_reg (mode1
, op1
);
13970 rawaddr
= gen_rtx_PLUS (Pmode
, op2
, op1
);
13973 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
13974 addr
= gen_rtx_MEM (tmode
, addr
);
13976 op0
= copy_to_mode_reg (tmode
, op0
);
13978 emit_insn (gen_rtx_SET (addr
, op0
));
13982 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
13983 op0
= copy_to_mode_reg (smode
, op0
);
13985 if (op1
== const0_rtx
)
13986 addr
= gen_rtx_MEM (tmode
, op2
);
13989 op1
= copy_to_mode_reg (mode1
, op1
);
13990 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op2
, op1
));
13993 pat
= GEN_FCN (icode
) (addr
, op0
);
14001 /* Return the appropriate SPR number associated with the given builtin. */
14002 static inline HOST_WIDE_INT
14003 htm_spr_num (enum rs6000_builtins code
)
14005 if (code
== HTM_BUILTIN_GET_TFHAR
14006 || code
== HTM_BUILTIN_SET_TFHAR
)
14008 else if (code
== HTM_BUILTIN_GET_TFIAR
14009 || code
== HTM_BUILTIN_SET_TFIAR
)
14011 else if (code
== HTM_BUILTIN_GET_TEXASR
14012 || code
== HTM_BUILTIN_SET_TEXASR
)
14014 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
14015 || code
== HTM_BUILTIN_SET_TEXASRU
);
14016 return TEXASRU_SPR
;
14019 /* Return the appropriate SPR regno associated with the given builtin. */
14020 static inline HOST_WIDE_INT
14021 htm_spr_regno (enum rs6000_builtins code
)
14023 if (code
== HTM_BUILTIN_GET_TFHAR
14024 || code
== HTM_BUILTIN_SET_TFHAR
)
14025 return TFHAR_REGNO
;
14026 else if (code
== HTM_BUILTIN_GET_TFIAR
14027 || code
== HTM_BUILTIN_SET_TFIAR
)
14028 return TFIAR_REGNO
;
14029 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
14030 || code
== HTM_BUILTIN_SET_TEXASR
14031 || code
== HTM_BUILTIN_GET_TEXASRU
14032 || code
== HTM_BUILTIN_SET_TEXASRU
);
14033 return TEXASR_REGNO
;
14036 /* Return the correct ICODE value depending on whether we are
14037 setting or reading the HTM SPRs. */
14038 static inline enum insn_code
14039 rs6000_htm_spr_icode (bool nonvoid
)
14042 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
14044 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
14047 /* Expand the HTM builtin in EXP and store the result in TARGET.
14048 Store true in *EXPANDEDP if we found a builtin to expand. */
14050 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
14052 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14053 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
14054 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14055 const struct builtin_description
*d
;
14060 if (!TARGET_POWERPC64
14061 && (fcode
== HTM_BUILTIN_TABORTDC
14062 || fcode
== HTM_BUILTIN_TABORTDCI
))
14064 size_t uns_fcode
= (size_t)fcode
;
14065 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
14066 error ("builtin %qs is only valid in 64-bit mode", name
);
14070 /* Expand the HTM builtins. */
14072 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14073 if (d
->code
== fcode
)
14075 rtx op
[MAX_HTM_OPERANDS
], pat
;
14078 call_expr_arg_iterator iter
;
14079 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
14080 enum insn_code icode
= d
->icode
;
14081 const struct insn_operand_data
*insn_op
;
14082 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
14086 icode
= rs6000_htm_spr_icode (nonvoid
);
14087 insn_op
= &insn_data
[icode
].operand
[0];
14091 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: E_SImode
;
14093 || GET_MODE (target
) != tmode
14094 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
14095 target
= gen_reg_rtx (tmode
);
14097 op
[nopnds
++] = target
;
14100 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
14102 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
14105 insn_op
= &insn_data
[icode
].operand
[nopnds
];
14107 op
[nopnds
] = expand_normal (arg
);
14109 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
14111 if (!strcmp (insn_op
->constraint
, "n"))
14113 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
14114 if (!CONST_INT_P (op
[nopnds
]))
14115 error ("argument %d must be an unsigned literal", arg_num
);
14117 error ("argument %d is an unsigned literal that is "
14118 "out of range", arg_num
);
14121 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
14127 /* Handle the builtins for extended mnemonics. These accept
14128 no arguments, but map to builtins that take arguments. */
14131 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
14132 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
14133 op
[nopnds
++] = GEN_INT (1);
14135 attr
|= RS6000_BTC_UNARY
;
14137 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
14138 op
[nopnds
++] = GEN_INT (0);
14140 attr
|= RS6000_BTC_UNARY
;
14146 /* If this builtin accesses SPRs, then pass in the appropriate
14147 SPR number and SPR regno as the last two operands. */
14150 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
14151 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
14152 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
14154 /* If this builtin accesses a CR, then pass in a scratch
14155 CR as the last operand. */
14156 else if (attr
& RS6000_BTC_CR
)
14157 { cr
= gen_reg_rtx (CCmode
);
14163 int expected_nopnds
= 0;
14164 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
14165 expected_nopnds
= 1;
14166 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
14167 expected_nopnds
= 2;
14168 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
14169 expected_nopnds
= 3;
14170 if (!(attr
& RS6000_BTC_VOID
))
14171 expected_nopnds
+= 1;
14173 expected_nopnds
+= 2;
14175 gcc_assert (nopnds
== expected_nopnds
14176 && nopnds
<= MAX_HTM_OPERANDS
);
14182 pat
= GEN_FCN (icode
) (op
[0]);
14185 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
14188 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
14191 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
14194 gcc_unreachable ();
14200 if (attr
& RS6000_BTC_CR
)
14202 if (fcode
== HTM_BUILTIN_TBEGIN
)
14204 /* Emit code to set TARGET to true or false depending on
14205 whether the tbegin. instruction successfully or failed
14206 to start a transaction. We do this by placing the 1's
14207 complement of CR's EQ bit into TARGET. */
14208 rtx scratch
= gen_reg_rtx (SImode
);
14209 emit_insn (gen_rtx_SET (scratch
,
14210 gen_rtx_EQ (SImode
, cr
,
14212 emit_insn (gen_rtx_SET (target
,
14213 gen_rtx_XOR (SImode
, scratch
,
14218 /* Emit code to copy the 4-bit condition register field
14219 CR into the least significant end of register TARGET. */
14220 rtx scratch1
= gen_reg_rtx (SImode
);
14221 rtx scratch2
= gen_reg_rtx (SImode
);
14222 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
14223 emit_insn (gen_movcc (subreg
, cr
));
14224 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
14225 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
14234 *expandedp
= false;
14238 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14241 cpu_expand_builtin (enum rs6000_builtins fcode
, tree exp ATTRIBUTE_UNUSED
,
14244 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14245 if (fcode
== RS6000_BUILTIN_CPU_INIT
)
14248 if (target
== 0 || GET_MODE (target
) != SImode
)
14249 target
= gen_reg_rtx (SImode
);
14251 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14252 tree arg
= TREE_OPERAND (CALL_EXPR_ARG (exp
, 0), 0);
14253 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14254 to a STRING_CST. */
14255 if (TREE_CODE (arg
) == ARRAY_REF
14256 && TREE_CODE (TREE_OPERAND (arg
, 0)) == STRING_CST
14257 && TREE_CODE (TREE_OPERAND (arg
, 1)) == INTEGER_CST
14258 && compare_tree_int (TREE_OPERAND (arg
, 1), 0) == 0)
14259 arg
= TREE_OPERAND (arg
, 0);
14261 if (TREE_CODE (arg
) != STRING_CST
)
14263 error ("builtin %qs only accepts a string argument",
14264 rs6000_builtin_info
[(size_t) fcode
].name
);
14268 if (fcode
== RS6000_BUILTIN_CPU_IS
)
14270 const char *cpu
= TREE_STRING_POINTER (arg
);
14271 rtx cpuid
= NULL_RTX
;
14272 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_is_info
); i
++)
14273 if (strcmp (cpu
, cpu_is_info
[i
].cpu
) == 0)
14275 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14276 cpuid
= GEN_INT (cpu_is_info
[i
].cpuid
+ _DL_FIRST_PLATFORM
);
14279 if (cpuid
== NULL_RTX
)
14281 /* Invalid CPU argument. */
14282 error ("cpu %qs is an invalid argument to builtin %qs",
14283 cpu
, rs6000_builtin_info
[(size_t) fcode
].name
);
14287 rtx platform
= gen_reg_rtx (SImode
);
14288 rtx tcbmem
= gen_const_mem (SImode
,
14289 gen_rtx_PLUS (Pmode
,
14290 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14291 GEN_INT (TCB_PLATFORM_OFFSET
)));
14292 emit_move_insn (platform
, tcbmem
);
14293 emit_insn (gen_eqsi3 (target
, platform
, cpuid
));
14295 else if (fcode
== RS6000_BUILTIN_CPU_SUPPORTS
)
14297 const char *hwcap
= TREE_STRING_POINTER (arg
);
14298 rtx mask
= NULL_RTX
;
14300 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_supports_info
); i
++)
14301 if (strcmp (hwcap
, cpu_supports_info
[i
].hwcap
) == 0)
14303 mask
= GEN_INT (cpu_supports_info
[i
].mask
);
14304 hwcap_offset
= TCB_HWCAP_OFFSET (cpu_supports_info
[i
].id
);
14307 if (mask
== NULL_RTX
)
14309 /* Invalid HWCAP argument. */
14310 error ("%s %qs is an invalid argument to builtin %qs",
14311 "hwcap", hwcap
, rs6000_builtin_info
[(size_t) fcode
].name
);
14315 rtx tcb_hwcap
= gen_reg_rtx (SImode
);
14316 rtx tcbmem
= gen_const_mem (SImode
,
14317 gen_rtx_PLUS (Pmode
,
14318 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14319 GEN_INT (hwcap_offset
)));
14320 emit_move_insn (tcb_hwcap
, tcbmem
);
14321 rtx scratch1
= gen_reg_rtx (SImode
);
14322 emit_insn (gen_rtx_SET (scratch1
, gen_rtx_AND (SImode
, tcb_hwcap
, mask
)));
14323 rtx scratch2
= gen_reg_rtx (SImode
);
14324 emit_insn (gen_eqsi3 (scratch2
, scratch1
, const0_rtx
));
14325 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (SImode
, scratch2
, const1_rtx
)));
14328 gcc_unreachable ();
14330 /* Record that we have expanded a CPU builtin, so that we can later
14331 emit a reference to the special symbol exported by LIBC to ensure we
14332 do not link against an old LIBC that doesn't support this feature. */
14333 cpu_builtin_p
= true;
14336 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14337 "capability bits", rs6000_builtin_info
[(size_t) fcode
].name
);
14339 /* For old LIBCs, always return FALSE. */
14340 emit_move_insn (target
, GEN_INT (0));
14341 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14347 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
14350 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14351 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14352 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14353 rtx op0
= expand_normal (arg0
);
14354 rtx op1
= expand_normal (arg1
);
14355 rtx op2
= expand_normal (arg2
);
14356 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14357 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14358 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14359 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
14361 if (icode
== CODE_FOR_nothing
)
14362 /* Builtin not supported on this processor. */
14365 /* If we got invalid arguments bail out before generating bad rtl. */
14366 if (arg0
== error_mark_node
14367 || arg1
== error_mark_node
14368 || arg2
== error_mark_node
)
14371 /* Check and prepare argument depending on the instruction code.
14373 Note that a switch statement instead of the sequence of tests
14374 would be incorrect as many of the CODE_FOR values could be
14375 CODE_FOR_nothing and that would yield multiple alternatives
14376 with identical values. We'd never reach here at runtime in
14378 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
14379 || icode
== CODE_FOR_altivec_vsldoi_v2df
14380 || icode
== CODE_FOR_altivec_vsldoi_v4si
14381 || icode
== CODE_FOR_altivec_vsldoi_v8hi
14382 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
14384 /* Only allow 4-bit unsigned literals. */
14386 if (TREE_CODE (arg2
) != INTEGER_CST
14387 || TREE_INT_CST_LOW (arg2
) & ~0xf)
14389 error ("argument 3 must be a 4-bit unsigned literal");
14390 return CONST0_RTX (tmode
);
14393 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
14394 || icode
== CODE_FOR_vsx_xxpermdi_v2di
14395 || icode
== CODE_FOR_vsx_xxpermdi_v2df_be
14396 || icode
== CODE_FOR_vsx_xxpermdi_v2di_be
14397 || icode
== CODE_FOR_vsx_xxpermdi_v1ti
14398 || icode
== CODE_FOR_vsx_xxpermdi_v4sf
14399 || icode
== CODE_FOR_vsx_xxpermdi_v4si
14400 || icode
== CODE_FOR_vsx_xxpermdi_v8hi
14401 || icode
== CODE_FOR_vsx_xxpermdi_v16qi
14402 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
14403 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
14404 || icode
== CODE_FOR_vsx_xxsldwi_v4si
14405 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
14406 || icode
== CODE_FOR_vsx_xxsldwi_v2di
14407 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
14409 /* Only allow 2-bit unsigned literals. */
14411 if (TREE_CODE (arg2
) != INTEGER_CST
14412 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14414 error ("argument 3 must be a 2-bit unsigned literal");
14415 return CONST0_RTX (tmode
);
14418 else if (icode
== CODE_FOR_vsx_set_v2df
14419 || icode
== CODE_FOR_vsx_set_v2di
14420 || icode
== CODE_FOR_bcdadd
14421 || icode
== CODE_FOR_bcdadd_lt
14422 || icode
== CODE_FOR_bcdadd_eq
14423 || icode
== CODE_FOR_bcdadd_gt
14424 || icode
== CODE_FOR_bcdsub
14425 || icode
== CODE_FOR_bcdsub_lt
14426 || icode
== CODE_FOR_bcdsub_eq
14427 || icode
== CODE_FOR_bcdsub_gt
)
14429 /* Only allow 1-bit unsigned literals. */
14431 if (TREE_CODE (arg2
) != INTEGER_CST
14432 || TREE_INT_CST_LOW (arg2
) & ~0x1)
14434 error ("argument 3 must be a 1-bit unsigned literal");
14435 return CONST0_RTX (tmode
);
14438 else if (icode
== CODE_FOR_dfp_ddedpd_dd
14439 || icode
== CODE_FOR_dfp_ddedpd_td
)
14441 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14443 if (TREE_CODE (arg0
) != INTEGER_CST
14444 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14446 error ("argument 1 must be 0 or 2");
14447 return CONST0_RTX (tmode
);
14450 else if (icode
== CODE_FOR_dfp_denbcd_dd
14451 || icode
== CODE_FOR_dfp_denbcd_td
)
14453 /* Only allow 1-bit unsigned literals. */
14455 if (TREE_CODE (arg0
) != INTEGER_CST
14456 || TREE_INT_CST_LOW (arg0
) & ~0x1)
14458 error ("argument 1 must be a 1-bit unsigned literal");
14459 return CONST0_RTX (tmode
);
14462 else if (icode
== CODE_FOR_dfp_dscli_dd
14463 || icode
== CODE_FOR_dfp_dscli_td
14464 || icode
== CODE_FOR_dfp_dscri_dd
14465 || icode
== CODE_FOR_dfp_dscri_td
)
14467 /* Only allow 6-bit unsigned literals. */
14469 if (TREE_CODE (arg1
) != INTEGER_CST
14470 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
14472 error ("argument 2 must be a 6-bit unsigned literal");
14473 return CONST0_RTX (tmode
);
14476 else if (icode
== CODE_FOR_crypto_vshasigmaw
14477 || icode
== CODE_FOR_crypto_vshasigmad
)
14479 /* Check whether the 2nd and 3rd arguments are integer constants and in
14480 range and prepare arguments. */
14482 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (wi::to_wide (arg1
), 2))
14484 error ("argument 2 must be 0 or 1");
14485 return CONST0_RTX (tmode
);
14489 if (TREE_CODE (arg2
) != INTEGER_CST
14490 || wi::geu_p (wi::to_wide (arg2
), 16))
14492 error ("argument 3 must be in the range 0..15");
14493 return CONST0_RTX (tmode
);
14498 || GET_MODE (target
) != tmode
14499 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14500 target
= gen_reg_rtx (tmode
);
14502 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14503 op0
= copy_to_mode_reg (mode0
, op0
);
14504 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14505 op1
= copy_to_mode_reg (mode1
, op1
);
14506 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
14507 op2
= copy_to_mode_reg (mode2
, op2
);
14509 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
14518 /* Expand the dst builtins. */
14520 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
14523 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14524 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14525 tree arg0
, arg1
, arg2
;
14526 machine_mode mode0
, mode1
;
14527 rtx pat
, op0
, op1
, op2
;
14528 const struct builtin_description
*d
;
14531 *expandedp
= false;
14533 /* Handle DST variants. */
14535 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14536 if (d
->code
== fcode
)
14538 arg0
= CALL_EXPR_ARG (exp
, 0);
14539 arg1
= CALL_EXPR_ARG (exp
, 1);
14540 arg2
= CALL_EXPR_ARG (exp
, 2);
14541 op0
= expand_normal (arg0
);
14542 op1
= expand_normal (arg1
);
14543 op2
= expand_normal (arg2
);
14544 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14545 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14547 /* Invalid arguments, bail out before generating bad rtl. */
14548 if (arg0
== error_mark_node
14549 || arg1
== error_mark_node
14550 || arg2
== error_mark_node
)
14555 if (TREE_CODE (arg2
) != INTEGER_CST
14556 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14558 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
14562 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
14563 op0
= copy_to_mode_reg (Pmode
, op0
);
14564 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
14565 op1
= copy_to_mode_reg (mode1
, op1
);
14567 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
14577 /* Expand vec_init builtin. */
14579 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
14581 machine_mode tmode
= TYPE_MODE (type
);
14582 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
14583 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
14585 gcc_assert (VECTOR_MODE_P (tmode
));
14586 gcc_assert (n_elt
== call_expr_nargs (exp
));
14588 if (!target
|| !register_operand (target
, tmode
))
14589 target
= gen_reg_rtx (tmode
);
14591 /* If we have a vector compromised of a single element, such as V1TImode, do
14592 the initialization directly. */
14593 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
14595 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
14596 emit_move_insn (target
, gen_lowpart (tmode
, x
));
14600 rtvec v
= rtvec_alloc (n_elt
);
14602 for (i
= 0; i
< n_elt
; ++i
)
14604 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
14605 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
14608 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
14614 /* Return the integer constant in ARG. Constrain it to be in the range
14615 of the subparts of VEC_TYPE; issue an error if not. */
14618 get_element_number (tree vec_type
, tree arg
)
14620 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
14622 if (!tree_fits_uhwi_p (arg
)
14623 || (elt
= tree_to_uhwi (arg
), elt
> max
))
14625 error ("selector must be an integer constant in the range 0..%wi", max
);
14632 /* Expand vec_set builtin. */
14634 altivec_expand_vec_set_builtin (tree exp
)
14636 machine_mode tmode
, mode1
;
14637 tree arg0
, arg1
, arg2
;
14641 arg0
= CALL_EXPR_ARG (exp
, 0);
14642 arg1
= CALL_EXPR_ARG (exp
, 1);
14643 arg2
= CALL_EXPR_ARG (exp
, 2);
14645 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
14646 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
14647 gcc_assert (VECTOR_MODE_P (tmode
));
14649 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
14650 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
14651 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
14653 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
14654 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
14656 op0
= force_reg (tmode
, op0
);
14657 op1
= force_reg (mode1
, op1
);
14659 rs6000_expand_vector_set (op0
, op1
, elt
);
14664 /* Expand vec_ext builtin. */
14666 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
14668 machine_mode tmode
, mode0
;
14673 arg0
= CALL_EXPR_ARG (exp
, 0);
14674 arg1
= CALL_EXPR_ARG (exp
, 1);
14676 op0
= expand_normal (arg0
);
14677 op1
= expand_normal (arg1
);
14679 /* Call get_element_number to validate arg1 if it is a constant. */
14680 if (TREE_CODE (arg1
) == INTEGER_CST
)
14681 (void) get_element_number (TREE_TYPE (arg0
), arg1
);
14683 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
14684 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
14685 gcc_assert (VECTOR_MODE_P (mode0
));
14687 op0
= force_reg (mode0
, op0
);
14689 if (optimize
|| !target
|| !register_operand (target
, tmode
))
14690 target
= gen_reg_rtx (tmode
);
14692 rs6000_expand_vector_extract (target
, op0
, op1
);
14697 /* Expand the builtin in EXP and store the result in TARGET. Store
14698 true in *EXPANDEDP if we found a builtin to expand. */
14700 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
14702 const struct builtin_description
*d
;
14704 enum insn_code icode
;
14705 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14706 tree arg0
, arg1
, arg2
;
14708 machine_mode tmode
, mode0
;
14709 enum rs6000_builtins fcode
14710 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14712 if (rs6000_overloaded_builtin_p (fcode
))
14715 error ("unresolved overload for Altivec builtin %qF", fndecl
);
14717 /* Given it is invalid, just generate a normal call. */
14718 return expand_call (exp
, target
, false);
14721 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
14729 case ALTIVEC_BUILTIN_STVX_V2DF
:
14730 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
14731 case ALTIVEC_BUILTIN_STVX_V2DI
:
14732 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
14733 case ALTIVEC_BUILTIN_STVX_V4SF
:
14734 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
14735 case ALTIVEC_BUILTIN_STVX
:
14736 case ALTIVEC_BUILTIN_STVX_V4SI
:
14737 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
14738 case ALTIVEC_BUILTIN_STVX_V8HI
:
14739 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
14740 case ALTIVEC_BUILTIN_STVX_V16QI
:
14741 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
14742 case ALTIVEC_BUILTIN_STVEBX
:
14743 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
14744 case ALTIVEC_BUILTIN_STVEHX
:
14745 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
14746 case ALTIVEC_BUILTIN_STVEWX
:
14747 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
14748 case ALTIVEC_BUILTIN_STVXL_V2DF
:
14749 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
14750 case ALTIVEC_BUILTIN_STVXL_V2DI
:
14751 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
14752 case ALTIVEC_BUILTIN_STVXL_V4SF
:
14753 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
14754 case ALTIVEC_BUILTIN_STVXL
:
14755 case ALTIVEC_BUILTIN_STVXL_V4SI
:
14756 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
14757 case ALTIVEC_BUILTIN_STVXL_V8HI
:
14758 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
14759 case ALTIVEC_BUILTIN_STVXL_V16QI
:
14760 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
14762 case ALTIVEC_BUILTIN_STVLX
:
14763 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
14764 case ALTIVEC_BUILTIN_STVLXL
:
14765 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
14766 case ALTIVEC_BUILTIN_STVRX
:
14767 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
14768 case ALTIVEC_BUILTIN_STVRXL
:
14769 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
14771 case P9V_BUILTIN_STXVL
:
14772 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl
, exp
);
14774 case P9V_BUILTIN_XST_LEN_R
:
14775 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r
, exp
);
14777 case VSX_BUILTIN_STXVD2X_V1TI
:
14778 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
14779 case VSX_BUILTIN_STXVD2X_V2DF
:
14780 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
14781 case VSX_BUILTIN_STXVD2X_V2DI
:
14782 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
14783 case VSX_BUILTIN_STXVW4X_V4SF
:
14784 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
14785 case VSX_BUILTIN_STXVW4X_V4SI
:
14786 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
14787 case VSX_BUILTIN_STXVW4X_V8HI
:
14788 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
14789 case VSX_BUILTIN_STXVW4X_V16QI
:
14790 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
14792 /* For the following on big endian, it's ok to use any appropriate
14793 unaligned-supporting store, so use a generic expander. For
14794 little-endian, the exact element-reversing instruction must
14796 case VSX_BUILTIN_ST_ELEMREV_V1TI
:
14798 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v1ti
14799 : CODE_FOR_vsx_st_elemrev_v1ti
);
14800 return altivec_expand_stv_builtin (code
, exp
);
14802 case VSX_BUILTIN_ST_ELEMREV_V2DF
:
14804 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2df
14805 : CODE_FOR_vsx_st_elemrev_v2df
);
14806 return altivec_expand_stv_builtin (code
, exp
);
14808 case VSX_BUILTIN_ST_ELEMREV_V2DI
:
14810 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2di
14811 : CODE_FOR_vsx_st_elemrev_v2di
);
14812 return altivec_expand_stv_builtin (code
, exp
);
14814 case VSX_BUILTIN_ST_ELEMREV_V4SF
:
14816 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4sf
14817 : CODE_FOR_vsx_st_elemrev_v4sf
);
14818 return altivec_expand_stv_builtin (code
, exp
);
14820 case VSX_BUILTIN_ST_ELEMREV_V4SI
:
14822 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4si
14823 : CODE_FOR_vsx_st_elemrev_v4si
);
14824 return altivec_expand_stv_builtin (code
, exp
);
14826 case VSX_BUILTIN_ST_ELEMREV_V8HI
:
14828 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v8hi
14829 : CODE_FOR_vsx_st_elemrev_v8hi
);
14830 return altivec_expand_stv_builtin (code
, exp
);
14832 case VSX_BUILTIN_ST_ELEMREV_V16QI
:
14834 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v16qi
14835 : CODE_FOR_vsx_st_elemrev_v16qi
);
14836 return altivec_expand_stv_builtin (code
, exp
);
14839 case ALTIVEC_BUILTIN_MFVSCR
:
14840 icode
= CODE_FOR_altivec_mfvscr
;
14841 tmode
= insn_data
[icode
].operand
[0].mode
;
14844 || GET_MODE (target
) != tmode
14845 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14846 target
= gen_reg_rtx (tmode
);
14848 pat
= GEN_FCN (icode
) (target
);
14854 case ALTIVEC_BUILTIN_MTVSCR
:
14855 icode
= CODE_FOR_altivec_mtvscr
;
14856 arg0
= CALL_EXPR_ARG (exp
, 0);
14857 op0
= expand_normal (arg0
);
14858 mode0
= insn_data
[icode
].operand
[0].mode
;
14860 /* If we got invalid arguments bail out before generating bad rtl. */
14861 if (arg0
== error_mark_node
)
14864 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
14865 op0
= copy_to_mode_reg (mode0
, op0
);
14867 pat
= GEN_FCN (icode
) (op0
);
14872 case ALTIVEC_BUILTIN_DSSALL
:
14873 emit_insn (gen_altivec_dssall ());
14876 case ALTIVEC_BUILTIN_DSS
:
14877 icode
= CODE_FOR_altivec_dss
;
14878 arg0
= CALL_EXPR_ARG (exp
, 0);
14880 op0
= expand_normal (arg0
);
14881 mode0
= insn_data
[icode
].operand
[0].mode
;
14883 /* If we got invalid arguments bail out before generating bad rtl. */
14884 if (arg0
== error_mark_node
)
14887 if (TREE_CODE (arg0
) != INTEGER_CST
14888 || TREE_INT_CST_LOW (arg0
) & ~0x3)
14890 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14894 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
14895 op0
= copy_to_mode_reg (mode0
, op0
);
14897 emit_insn (gen_altivec_dss (op0
));
14900 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
14901 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
14902 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
14903 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
14904 case VSX_BUILTIN_VEC_INIT_V2DF
:
14905 case VSX_BUILTIN_VEC_INIT_V2DI
:
14906 case VSX_BUILTIN_VEC_INIT_V1TI
:
14907 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
14909 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
14910 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
14911 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
14912 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
14913 case VSX_BUILTIN_VEC_SET_V2DF
:
14914 case VSX_BUILTIN_VEC_SET_V2DI
:
14915 case VSX_BUILTIN_VEC_SET_V1TI
:
14916 return altivec_expand_vec_set_builtin (exp
);
14918 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
14919 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
14920 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
14921 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
14922 case VSX_BUILTIN_VEC_EXT_V2DF
:
14923 case VSX_BUILTIN_VEC_EXT_V2DI
:
14924 case VSX_BUILTIN_VEC_EXT_V1TI
:
14925 return altivec_expand_vec_ext_builtin (exp
, target
);
14927 case P9V_BUILTIN_VEC_EXTRACT4B
:
14928 arg1
= CALL_EXPR_ARG (exp
, 1);
14931 /* Generate a normal call if it is invalid. */
14932 if (arg1
== error_mark_node
)
14933 return expand_call (exp
, target
, false);
14935 if (TREE_CODE (arg1
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg1
) > 12)
14937 error ("second argument to %qs must be 0..12", "vec_vextract4b");
14938 return expand_call (exp
, target
, false);
14942 case P9V_BUILTIN_VEC_INSERT4B
:
14943 arg2
= CALL_EXPR_ARG (exp
, 2);
14946 /* Generate a normal call if it is invalid. */
14947 if (arg2
== error_mark_node
)
14948 return expand_call (exp
, target
, false);
14950 if (TREE_CODE (arg2
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg2
) > 12)
14952 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
14953 return expand_call (exp
, target
, false);
14959 /* Fall through. */
14962 /* Expand abs* operations. */
14964 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14965 if (d
->code
== fcode
)
14966 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
14968 /* Expand the AltiVec predicates. */
14969 d
= bdesc_altivec_preds
;
14970 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14971 if (d
->code
== fcode
)
14972 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
14974 /* LV* are funky. We initialized them differently. */
14977 case ALTIVEC_BUILTIN_LVSL
:
14978 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
14979 exp
, target
, false);
14980 case ALTIVEC_BUILTIN_LVSR
:
14981 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
14982 exp
, target
, false);
14983 case ALTIVEC_BUILTIN_LVEBX
:
14984 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
14985 exp
, target
, false);
14986 case ALTIVEC_BUILTIN_LVEHX
:
14987 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
14988 exp
, target
, false);
14989 case ALTIVEC_BUILTIN_LVEWX
:
14990 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
14991 exp
, target
, false);
14992 case ALTIVEC_BUILTIN_LVXL_V2DF
:
14993 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
14994 exp
, target
, false);
14995 case ALTIVEC_BUILTIN_LVXL_V2DI
:
14996 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
14997 exp
, target
, false);
14998 case ALTIVEC_BUILTIN_LVXL_V4SF
:
14999 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
15000 exp
, target
, false);
15001 case ALTIVEC_BUILTIN_LVXL
:
15002 case ALTIVEC_BUILTIN_LVXL_V4SI
:
15003 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
15004 exp
, target
, false);
15005 case ALTIVEC_BUILTIN_LVXL_V8HI
:
15006 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
15007 exp
, target
, false);
15008 case ALTIVEC_BUILTIN_LVXL_V16QI
:
15009 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
15010 exp
, target
, false);
15011 case ALTIVEC_BUILTIN_LVX_V1TI
:
15012 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti
,
15013 exp
, target
, false);
15014 case ALTIVEC_BUILTIN_LVX_V2DF
:
15015 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
15016 exp
, target
, false);
15017 case ALTIVEC_BUILTIN_LVX_V2DI
:
15018 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
15019 exp
, target
, false);
15020 case ALTIVEC_BUILTIN_LVX_V4SF
:
15021 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
15022 exp
, target
, false);
15023 case ALTIVEC_BUILTIN_LVX
:
15024 case ALTIVEC_BUILTIN_LVX_V4SI
:
15025 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
15026 exp
, target
, false);
15027 case ALTIVEC_BUILTIN_LVX_V8HI
:
15028 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
15029 exp
, target
, false);
15030 case ALTIVEC_BUILTIN_LVX_V16QI
:
15031 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
15032 exp
, target
, false);
15033 case ALTIVEC_BUILTIN_LVLX
:
15034 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
15035 exp
, target
, true);
15036 case ALTIVEC_BUILTIN_LVLXL
:
15037 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
15038 exp
, target
, true);
15039 case ALTIVEC_BUILTIN_LVRX
:
15040 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
15041 exp
, target
, true);
15042 case ALTIVEC_BUILTIN_LVRXL
:
15043 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
15044 exp
, target
, true);
15045 case VSX_BUILTIN_LXVD2X_V1TI
:
15046 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
15047 exp
, target
, false);
15048 case VSX_BUILTIN_LXVD2X_V2DF
:
15049 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
15050 exp
, target
, false);
15051 case VSX_BUILTIN_LXVD2X_V2DI
:
15052 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
15053 exp
, target
, false);
15054 case VSX_BUILTIN_LXVW4X_V4SF
:
15055 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
15056 exp
, target
, false);
15057 case VSX_BUILTIN_LXVW4X_V4SI
:
15058 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
15059 exp
, target
, false);
15060 case VSX_BUILTIN_LXVW4X_V8HI
:
15061 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
15062 exp
, target
, false);
15063 case VSX_BUILTIN_LXVW4X_V16QI
:
15064 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
15065 exp
, target
, false);
15066 /* For the following on big endian, it's ok to use any appropriate
15067 unaligned-supporting load, so use a generic expander. For
15068 little-endian, the exact element-reversing instruction must
15070 case VSX_BUILTIN_LD_ELEMREV_V2DF
:
15072 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2df
15073 : CODE_FOR_vsx_ld_elemrev_v2df
);
15074 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15076 case VSX_BUILTIN_LD_ELEMREV_V1TI
:
15078 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v1ti
15079 : CODE_FOR_vsx_ld_elemrev_v1ti
);
15080 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15082 case VSX_BUILTIN_LD_ELEMREV_V2DI
:
15084 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2di
15085 : CODE_FOR_vsx_ld_elemrev_v2di
);
15086 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15088 case VSX_BUILTIN_LD_ELEMREV_V4SF
:
15090 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4sf
15091 : CODE_FOR_vsx_ld_elemrev_v4sf
);
15092 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15094 case VSX_BUILTIN_LD_ELEMREV_V4SI
:
15096 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4si
15097 : CODE_FOR_vsx_ld_elemrev_v4si
);
15098 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15100 case VSX_BUILTIN_LD_ELEMREV_V8HI
:
15102 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v8hi
15103 : CODE_FOR_vsx_ld_elemrev_v8hi
);
15104 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15106 case VSX_BUILTIN_LD_ELEMREV_V16QI
:
15108 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v16qi
15109 : CODE_FOR_vsx_ld_elemrev_v16qi
);
15110 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15115 /* Fall through. */
15118 *expandedp
= false;
15122 /* Check whether a builtin function is supported in this target
15125 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode
)
15127 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[fncode
].mask
;
15128 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
15134 /* Raise an error message for a builtin function that is called without the
15135 appropriate target options being set. */
15138 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
15140 size_t uns_fncode
= (size_t) fncode
;
15141 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
15142 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
15144 gcc_assert (name
!= NULL
);
15145 if ((fnmask
& RS6000_BTM_CELL
) != 0)
15146 error ("builtin function %qs is only valid for the cell processor", name
);
15147 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
15148 error ("builtin function %qs requires the %qs option", name
, "-mvsx");
15149 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
15150 error ("builtin function %qs requires the %qs option", name
, "-mhtm");
15151 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
15152 error ("builtin function %qs requires the %qs option", name
, "-maltivec");
15153 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
15154 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
15155 error ("builtin function %qs requires the %qs and %qs options",
15156 name
, "-mhard-dfp", "-mpower8-vector");
15157 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
15158 error ("builtin function %qs requires the %qs option", name
, "-mhard-dfp");
15159 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
15160 error ("builtin function %qs requires the %qs option", name
,
15161 "-mpower8-vector");
15162 else if ((fnmask
& (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
15163 == (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
15164 error ("builtin function %qs requires the %qs and %qs options",
15165 name
, "-mcpu=power9", "-m64");
15166 else if ((fnmask
& RS6000_BTM_P9_VECTOR
) != 0)
15167 error ("builtin function %qs requires the %qs option", name
,
15169 else if ((fnmask
& (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
15170 == (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
15171 error ("builtin function %qs requires the %qs and %qs options",
15172 name
, "-mcpu=power9", "-m64");
15173 else if ((fnmask
& RS6000_BTM_P9_MISC
) == RS6000_BTM_P9_MISC
)
15174 error ("builtin function %qs requires the %qs option", name
,
15176 else if ((fnmask
& RS6000_BTM_LDBL128
) == RS6000_BTM_LDBL128
)
15178 if (!TARGET_HARD_FLOAT
)
15179 error ("builtin function %qs requires the %qs option", name
,
15182 error ("builtin function %qs requires the %qs option", name
,
15183 TARGET_IEEEQUAD
? "-mabi=ibmlongdouble" : "-mlong-double-128");
15185 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
15186 error ("builtin function %qs requires the %qs option", name
,
15188 else if ((fnmask
& RS6000_BTM_FLOAT128_HW
) != 0)
15189 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
15191 else if ((fnmask
& RS6000_BTM_FLOAT128
) != 0)
15192 error ("builtin function %qs requires the %qs option", name
, "-mfloat128");
15193 else if ((fnmask
& (RS6000_BTM_POPCNTD
| RS6000_BTM_POWERPC64
))
15194 == (RS6000_BTM_POPCNTD
| RS6000_BTM_POWERPC64
))
15195 error ("builtin function %qs requires the %qs (or newer), and "
15196 "%qs or %qs options",
15197 name
, "-mcpu=power7", "-m64", "-mpowerpc64");
15199 error ("builtin function %qs is not supported with the current options",
15203 /* Target hook for early folding of built-ins, shamelessly stolen
15207 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED
,
15208 int n_args ATTRIBUTE_UNUSED
,
15209 tree
*args ATTRIBUTE_UNUSED
,
15210 bool ignore ATTRIBUTE_UNUSED
)
15212 #ifdef SUBTARGET_FOLD_BUILTIN
15213 return SUBTARGET_FOLD_BUILTIN (fndecl
, n_args
, args
, ignore
);
15219 /* Helper function to sort out which built-ins may be valid without having
15222 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code
)
15226 case ALTIVEC_BUILTIN_STVX_V16QI
:
15227 case ALTIVEC_BUILTIN_STVX_V8HI
:
15228 case ALTIVEC_BUILTIN_STVX_V4SI
:
15229 case ALTIVEC_BUILTIN_STVX_V4SF
:
15230 case ALTIVEC_BUILTIN_STVX_V2DI
:
15231 case ALTIVEC_BUILTIN_STVX_V2DF
:
15232 case VSX_BUILTIN_STXVW4X_V16QI
:
15233 case VSX_BUILTIN_STXVW4X_V8HI
:
15234 case VSX_BUILTIN_STXVW4X_V4SF
:
15235 case VSX_BUILTIN_STXVW4X_V4SI
:
15236 case VSX_BUILTIN_STXVD2X_V2DF
:
15237 case VSX_BUILTIN_STXVD2X_V2DI
:
15244 /* Helper function to handle the gimple folding of a vector compare
15245 operation. This sets up true/false vectors, and uses the
15246 VEC_COND_EXPR operation.
15247 CODE indicates which comparison is to be made. (EQ, GT, ...).
15248 TYPE indicates the type of the result. */
15250 fold_build_vec_cmp (tree_code code
, tree type
,
15251 tree arg0
, tree arg1
)
15253 tree cmp_type
= build_same_sized_truth_vector_type (type
);
15254 tree zero_vec
= build_zero_cst (type
);
15255 tree minus_one_vec
= build_minus_one_cst (type
);
15256 tree cmp
= fold_build2 (code
, cmp_type
, arg0
, arg1
);
15257 return fold_build3 (VEC_COND_EXPR
, type
, cmp
, minus_one_vec
, zero_vec
);
15260 /* Helper function to handle the in-between steps for the
15261 vector compare built-ins. */
15263 fold_compare_helper (gimple_stmt_iterator
*gsi
, tree_code code
, gimple
*stmt
)
15265 tree arg0
= gimple_call_arg (stmt
, 0);
15266 tree arg1
= gimple_call_arg (stmt
, 1);
15267 tree lhs
= gimple_call_lhs (stmt
);
15268 tree cmp
= fold_build_vec_cmp (code
, TREE_TYPE (lhs
), arg0
, arg1
);
15269 gimple
*g
= gimple_build_assign (lhs
, cmp
);
15270 gimple_set_location (g
, gimple_location (stmt
));
15271 gsi_replace (gsi
, g
, true);
15274 /* Helper function to map V2DF and V4SF types to their
15275 integral equivalents (V2DI and V4SI). */
15276 tree
map_to_integral_tree_type (tree input_tree_type
)
15278 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type
)))
15279 return input_tree_type
;
15282 if (types_compatible_p (TREE_TYPE (input_tree_type
),
15283 TREE_TYPE (V2DF_type_node
)))
15284 return V2DI_type_node
;
15285 else if (types_compatible_p (TREE_TYPE (input_tree_type
),
15286 TREE_TYPE (V4SF_type_node
)))
15287 return V4SI_type_node
;
15289 gcc_unreachable ();
15293 /* Helper function to handle the vector merge[hl] built-ins. The
15294 implementation difference between h and l versions for this code are in
15295 the values used when building of the permute vector for high word versus
15296 low word merge. The variance is keyed off the use_high parameter. */
15298 fold_mergehl_helper (gimple_stmt_iterator
*gsi
, gimple
*stmt
, int use_high
)
15300 tree arg0
= gimple_call_arg (stmt
, 0);
15301 tree arg1
= gimple_call_arg (stmt
, 1);
15302 tree lhs
= gimple_call_lhs (stmt
);
15303 tree lhs_type
= TREE_TYPE (lhs
);
15304 int n_elts
= TYPE_VECTOR_SUBPARTS (lhs_type
);
15305 int midpoint
= n_elts
/ 2;
15311 /* The permute_type will match the lhs for integral types. For double and
15312 float types, the permute type needs to map to the V2 or V4 type that
15315 permute_type
= map_to_integral_tree_type (lhs_type
);
15316 tree_vector_builder
elts (permute_type
, VECTOR_CST_NELTS (arg0
), 1);
15318 for (int i
= 0; i
< midpoint
; i
++)
15320 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15322 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15323 offset
+ n_elts
+ i
));
15326 tree permute
= elts
.build ();
15328 gimple
*g
= gimple_build_assign (lhs
, VEC_PERM_EXPR
, arg0
, arg1
, permute
);
15329 gimple_set_location (g
, gimple_location (stmt
));
15330 gsi_replace (gsi
, g
, true);
15333 /* Helper function to handle the vector merge[eo] built-ins. */
15335 fold_mergeeo_helper (gimple_stmt_iterator
*gsi
, gimple
*stmt
, int use_odd
)
15337 tree arg0
= gimple_call_arg (stmt
, 0);
15338 tree arg1
= gimple_call_arg (stmt
, 1);
15339 tree lhs
= gimple_call_lhs (stmt
);
15340 tree lhs_type
= TREE_TYPE (lhs
);
15341 int n_elts
= TYPE_VECTOR_SUBPARTS (lhs_type
);
15343 /* The permute_type will match the lhs for integral types. For double and
15344 float types, the permute type needs to map to the V2 or V4 type that
15347 permute_type
= map_to_integral_tree_type (lhs_type
);
15349 tree_vector_builder
elts (permute_type
, VECTOR_CST_NELTS (arg0
), 1);
15351 /* Build the permute vector. */
15352 for (int i
= 0; i
< n_elts
/ 2; i
++)
15354 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15356 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15357 2*i
+ use_odd
+ n_elts
));
15360 tree permute
= elts
.build ();
15362 gimple
*g
= gimple_build_assign (lhs
, VEC_PERM_EXPR
, arg0
, arg1
, permute
);
15363 gimple_set_location (g
, gimple_location (stmt
));
15364 gsi_replace (gsi
, g
, true);
15367 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15368 a constant, use rs6000_fold_builtin.) */
15371 rs6000_gimple_fold_builtin (gimple_stmt_iterator
*gsi
)
15373 gimple
*stmt
= gsi_stmt (*gsi
);
15374 tree fndecl
= gimple_call_fndecl (stmt
);
15375 gcc_checking_assert (fndecl
&& DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
);
15376 enum rs6000_builtins fn_code
15377 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15378 tree arg0
, arg1
, lhs
, temp
;
15381 size_t uns_fncode
= (size_t) fn_code
;
15382 enum insn_code icode
= rs6000_builtin_info
[uns_fncode
].icode
;
15383 const char *fn_name1
= rs6000_builtin_info
[uns_fncode
].name
;
15384 const char *fn_name2
= (icode
!= CODE_FOR_nothing
)
15385 ? get_insn_name ((int) icode
)
15388 if (TARGET_DEBUG_BUILTIN
)
15389 fprintf (stderr
, "rs6000_gimple_fold_builtin %d %s %s\n",
15390 fn_code
, fn_name1
, fn_name2
);
15392 if (!rs6000_fold_gimple
)
15395 /* Prevent gimple folding for code that does not have a LHS, unless it is
15396 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15397 if (!gimple_call_lhs (stmt
) && !rs6000_builtin_valid_without_lhs (fn_code
))
15400 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15401 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fncode
].mask
;
15402 bool func_valid_p
= (rs6000_builtin_mask
& mask
) == mask
;
15408 /* Flavors of vec_add. We deliberately don't expand
15409 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15410 TImode, resulting in much poorer code generation. */
15411 case ALTIVEC_BUILTIN_VADDUBM
:
15412 case ALTIVEC_BUILTIN_VADDUHM
:
15413 case ALTIVEC_BUILTIN_VADDUWM
:
15414 case P8V_BUILTIN_VADDUDM
:
15415 case ALTIVEC_BUILTIN_VADDFP
:
15416 case VSX_BUILTIN_XVADDDP
:
15417 arg0
= gimple_call_arg (stmt
, 0);
15418 arg1
= gimple_call_arg (stmt
, 1);
15419 lhs
= gimple_call_lhs (stmt
);
15420 g
= gimple_build_assign (lhs
, PLUS_EXPR
, arg0
, arg1
);
15421 gimple_set_location (g
, gimple_location (stmt
));
15422 gsi_replace (gsi
, g
, true);
15424 /* Flavors of vec_sub. We deliberately don't expand
15425 P8V_BUILTIN_VSUBUQM. */
15426 case ALTIVEC_BUILTIN_VSUBUBM
:
15427 case ALTIVEC_BUILTIN_VSUBUHM
:
15428 case ALTIVEC_BUILTIN_VSUBUWM
:
15429 case P8V_BUILTIN_VSUBUDM
:
15430 case ALTIVEC_BUILTIN_VSUBFP
:
15431 case VSX_BUILTIN_XVSUBDP
:
15432 arg0
= gimple_call_arg (stmt
, 0);
15433 arg1
= gimple_call_arg (stmt
, 1);
15434 lhs
= gimple_call_lhs (stmt
);
15435 g
= gimple_build_assign (lhs
, MINUS_EXPR
, arg0
, arg1
);
15436 gimple_set_location (g
, gimple_location (stmt
));
15437 gsi_replace (gsi
, g
, true);
15439 case VSX_BUILTIN_XVMULSP
:
15440 case VSX_BUILTIN_XVMULDP
:
15441 arg0
= gimple_call_arg (stmt
, 0);
15442 arg1
= gimple_call_arg (stmt
, 1);
15443 lhs
= gimple_call_lhs (stmt
);
15444 g
= gimple_build_assign (lhs
, MULT_EXPR
, arg0
, arg1
);
15445 gimple_set_location (g
, gimple_location (stmt
));
15446 gsi_replace (gsi
, g
, true);
15448 /* Even element flavors of vec_mul (signed). */
15449 case ALTIVEC_BUILTIN_VMULESB
:
15450 case ALTIVEC_BUILTIN_VMULESH
:
15451 case P8V_BUILTIN_VMULESW
:
15452 /* Even element flavors of vec_mul (unsigned). */
15453 case ALTIVEC_BUILTIN_VMULEUB
:
15454 case ALTIVEC_BUILTIN_VMULEUH
:
15455 case P8V_BUILTIN_VMULEUW
:
15456 arg0
= gimple_call_arg (stmt
, 0);
15457 arg1
= gimple_call_arg (stmt
, 1);
15458 lhs
= gimple_call_lhs (stmt
);
15459 g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_EVEN_EXPR
, arg0
, arg1
);
15460 gimple_set_location (g
, gimple_location (stmt
));
15461 gsi_replace (gsi
, g
, true);
15463 /* Odd element flavors of vec_mul (signed). */
15464 case ALTIVEC_BUILTIN_VMULOSB
:
15465 case ALTIVEC_BUILTIN_VMULOSH
:
15466 case P8V_BUILTIN_VMULOSW
:
15467 /* Odd element flavors of vec_mul (unsigned). */
15468 case ALTIVEC_BUILTIN_VMULOUB
:
15469 case ALTIVEC_BUILTIN_VMULOUH
:
15470 case P8V_BUILTIN_VMULOUW
:
15471 arg0
= gimple_call_arg (stmt
, 0);
15472 arg1
= gimple_call_arg (stmt
, 1);
15473 lhs
= gimple_call_lhs (stmt
);
15474 g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_ODD_EXPR
, arg0
, arg1
);
15475 gimple_set_location (g
, gimple_location (stmt
));
15476 gsi_replace (gsi
, g
, true);
15478 /* Flavors of vec_div (Integer). */
15479 case VSX_BUILTIN_DIV_V2DI
:
15480 case VSX_BUILTIN_UDIV_V2DI
:
15481 arg0
= gimple_call_arg (stmt
, 0);
15482 arg1
= gimple_call_arg (stmt
, 1);
15483 lhs
= gimple_call_lhs (stmt
);
15484 g
= gimple_build_assign (lhs
, TRUNC_DIV_EXPR
, arg0
, arg1
);
15485 gimple_set_location (g
, gimple_location (stmt
));
15486 gsi_replace (gsi
, g
, true);
15488 /* Flavors of vec_div (Float). */
15489 case VSX_BUILTIN_XVDIVSP
:
15490 case VSX_BUILTIN_XVDIVDP
:
15491 arg0
= gimple_call_arg (stmt
, 0);
15492 arg1
= gimple_call_arg (stmt
, 1);
15493 lhs
= gimple_call_lhs (stmt
);
15494 g
= gimple_build_assign (lhs
, RDIV_EXPR
, arg0
, arg1
);
15495 gimple_set_location (g
, gimple_location (stmt
));
15496 gsi_replace (gsi
, g
, true);
15498 /* Flavors of vec_and. */
15499 case ALTIVEC_BUILTIN_VAND
:
15500 arg0
= gimple_call_arg (stmt
, 0);
15501 arg1
= gimple_call_arg (stmt
, 1);
15502 lhs
= gimple_call_lhs (stmt
);
15503 g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, arg1
);
15504 gimple_set_location (g
, gimple_location (stmt
));
15505 gsi_replace (gsi
, g
, true);
15507 /* Flavors of vec_andc. */
15508 case ALTIVEC_BUILTIN_VANDC
:
15509 arg0
= gimple_call_arg (stmt
, 0);
15510 arg1
= gimple_call_arg (stmt
, 1);
15511 lhs
= gimple_call_lhs (stmt
);
15512 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15513 g
= gimple_build_assign (temp
, BIT_NOT_EXPR
, arg1
);
15514 gimple_set_location (g
, gimple_location (stmt
));
15515 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15516 g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, temp
);
15517 gimple_set_location (g
, gimple_location (stmt
));
15518 gsi_replace (gsi
, g
, true);
15520 /* Flavors of vec_nand. */
15521 case P8V_BUILTIN_VEC_NAND
:
15522 case P8V_BUILTIN_NAND_V16QI
:
15523 case P8V_BUILTIN_NAND_V8HI
:
15524 case P8V_BUILTIN_NAND_V4SI
:
15525 case P8V_BUILTIN_NAND_V4SF
:
15526 case P8V_BUILTIN_NAND_V2DF
:
15527 case P8V_BUILTIN_NAND_V2DI
:
15528 arg0
= gimple_call_arg (stmt
, 0);
15529 arg1
= gimple_call_arg (stmt
, 1);
15530 lhs
= gimple_call_lhs (stmt
);
15531 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15532 g
= gimple_build_assign (temp
, BIT_AND_EXPR
, arg0
, arg1
);
15533 gimple_set_location (g
, gimple_location (stmt
));
15534 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15535 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15536 gimple_set_location (g
, gimple_location (stmt
));
15537 gsi_replace (gsi
, g
, true);
15539 /* Flavors of vec_or. */
15540 case ALTIVEC_BUILTIN_VOR
:
15541 arg0
= gimple_call_arg (stmt
, 0);
15542 arg1
= gimple_call_arg (stmt
, 1);
15543 lhs
= gimple_call_lhs (stmt
);
15544 g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, arg1
);
15545 gimple_set_location (g
, gimple_location (stmt
));
15546 gsi_replace (gsi
, g
, true);
15548 /* flavors of vec_orc. */
15549 case P8V_BUILTIN_ORC_V16QI
:
15550 case P8V_BUILTIN_ORC_V8HI
:
15551 case P8V_BUILTIN_ORC_V4SI
:
15552 case P8V_BUILTIN_ORC_V4SF
:
15553 case P8V_BUILTIN_ORC_V2DF
:
15554 case P8V_BUILTIN_ORC_V2DI
:
15555 arg0
= gimple_call_arg (stmt
, 0);
15556 arg1
= gimple_call_arg (stmt
, 1);
15557 lhs
= gimple_call_lhs (stmt
);
15558 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15559 g
= gimple_build_assign (temp
, BIT_NOT_EXPR
, arg1
);
15560 gimple_set_location (g
, gimple_location (stmt
));
15561 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15562 g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, temp
);
15563 gimple_set_location (g
, gimple_location (stmt
));
15564 gsi_replace (gsi
, g
, true);
15566 /* Flavors of vec_xor. */
15567 case ALTIVEC_BUILTIN_VXOR
:
15568 arg0
= gimple_call_arg (stmt
, 0);
15569 arg1
= gimple_call_arg (stmt
, 1);
15570 lhs
= gimple_call_lhs (stmt
);
15571 g
= gimple_build_assign (lhs
, BIT_XOR_EXPR
, arg0
, arg1
);
15572 gimple_set_location (g
, gimple_location (stmt
));
15573 gsi_replace (gsi
, g
, true);
15575 /* Flavors of vec_nor. */
15576 case ALTIVEC_BUILTIN_VNOR
:
15577 arg0
= gimple_call_arg (stmt
, 0);
15578 arg1
= gimple_call_arg (stmt
, 1);
15579 lhs
= gimple_call_lhs (stmt
);
15580 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15581 g
= gimple_build_assign (temp
, BIT_IOR_EXPR
, arg0
, arg1
);
15582 gimple_set_location (g
, gimple_location (stmt
));
15583 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15584 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15585 gimple_set_location (g
, gimple_location (stmt
));
15586 gsi_replace (gsi
, g
, true);
15588 /* flavors of vec_abs. */
15589 case ALTIVEC_BUILTIN_ABS_V16QI
:
15590 case ALTIVEC_BUILTIN_ABS_V8HI
:
15591 case ALTIVEC_BUILTIN_ABS_V4SI
:
15592 case ALTIVEC_BUILTIN_ABS_V4SF
:
15593 case P8V_BUILTIN_ABS_V2DI
:
15594 case VSX_BUILTIN_XVABSDP
:
15595 arg0
= gimple_call_arg (stmt
, 0);
15596 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0
)))
15597 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0
))))
15599 lhs
= gimple_call_lhs (stmt
);
15600 g
= gimple_build_assign (lhs
, ABS_EXPR
, arg0
);
15601 gimple_set_location (g
, gimple_location (stmt
));
15602 gsi_replace (gsi
, g
, true);
15604 /* flavors of vec_min. */
15605 case VSX_BUILTIN_XVMINDP
:
15606 case P8V_BUILTIN_VMINSD
:
15607 case P8V_BUILTIN_VMINUD
:
15608 case ALTIVEC_BUILTIN_VMINSB
:
15609 case ALTIVEC_BUILTIN_VMINSH
:
15610 case ALTIVEC_BUILTIN_VMINSW
:
15611 case ALTIVEC_BUILTIN_VMINUB
:
15612 case ALTIVEC_BUILTIN_VMINUH
:
15613 case ALTIVEC_BUILTIN_VMINUW
:
15614 case ALTIVEC_BUILTIN_VMINFP
:
15615 arg0
= gimple_call_arg (stmt
, 0);
15616 arg1
= gimple_call_arg (stmt
, 1);
15617 lhs
= gimple_call_lhs (stmt
);
15618 g
= gimple_build_assign (lhs
, MIN_EXPR
, arg0
, arg1
);
15619 gimple_set_location (g
, gimple_location (stmt
));
15620 gsi_replace (gsi
, g
, true);
15622 /* flavors of vec_max. */
15623 case VSX_BUILTIN_XVMAXDP
:
15624 case P8V_BUILTIN_VMAXSD
:
15625 case P8V_BUILTIN_VMAXUD
:
15626 case ALTIVEC_BUILTIN_VMAXSB
:
15627 case ALTIVEC_BUILTIN_VMAXSH
:
15628 case ALTIVEC_BUILTIN_VMAXSW
:
15629 case ALTIVEC_BUILTIN_VMAXUB
:
15630 case ALTIVEC_BUILTIN_VMAXUH
:
15631 case ALTIVEC_BUILTIN_VMAXUW
:
15632 case ALTIVEC_BUILTIN_VMAXFP
:
15633 arg0
= gimple_call_arg (stmt
, 0);
15634 arg1
= gimple_call_arg (stmt
, 1);
15635 lhs
= gimple_call_lhs (stmt
);
15636 g
= gimple_build_assign (lhs
, MAX_EXPR
, arg0
, arg1
);
15637 gimple_set_location (g
, gimple_location (stmt
));
15638 gsi_replace (gsi
, g
, true);
15640 /* Flavors of vec_eqv. */
15641 case P8V_BUILTIN_EQV_V16QI
:
15642 case P8V_BUILTIN_EQV_V8HI
:
15643 case P8V_BUILTIN_EQV_V4SI
:
15644 case P8V_BUILTIN_EQV_V4SF
:
15645 case P8V_BUILTIN_EQV_V2DF
:
15646 case P8V_BUILTIN_EQV_V2DI
:
15647 arg0
= gimple_call_arg (stmt
, 0);
15648 arg1
= gimple_call_arg (stmt
, 1);
15649 lhs
= gimple_call_lhs (stmt
);
15650 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15651 g
= gimple_build_assign (temp
, BIT_XOR_EXPR
, arg0
, arg1
);
15652 gimple_set_location (g
, gimple_location (stmt
));
15653 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15654 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15655 gimple_set_location (g
, gimple_location (stmt
));
15656 gsi_replace (gsi
, g
, true);
15658 /* Flavors of vec_rotate_left. */
15659 case ALTIVEC_BUILTIN_VRLB
:
15660 case ALTIVEC_BUILTIN_VRLH
:
15661 case ALTIVEC_BUILTIN_VRLW
:
15662 case P8V_BUILTIN_VRLD
:
15663 arg0
= gimple_call_arg (stmt
, 0);
15664 arg1
= gimple_call_arg (stmt
, 1);
15665 lhs
= gimple_call_lhs (stmt
);
15666 g
= gimple_build_assign (lhs
, LROTATE_EXPR
, arg0
, arg1
);
15667 gimple_set_location (g
, gimple_location (stmt
));
15668 gsi_replace (gsi
, g
, true);
15670 /* Flavors of vector shift right algebraic.
15671 vec_sra{b,h,w} -> vsra{b,h,w}. */
15672 case ALTIVEC_BUILTIN_VSRAB
:
15673 case ALTIVEC_BUILTIN_VSRAH
:
15674 case ALTIVEC_BUILTIN_VSRAW
:
15675 case P8V_BUILTIN_VSRAD
:
15676 arg0
= gimple_call_arg (stmt
, 0);
15677 arg1
= gimple_call_arg (stmt
, 1);
15678 lhs
= gimple_call_lhs (stmt
);
15679 g
= gimple_build_assign (lhs
, RSHIFT_EXPR
, arg0
, arg1
);
15680 gimple_set_location (g
, gimple_location (stmt
));
15681 gsi_replace (gsi
, g
, true);
15683 /* Flavors of vector shift left.
15684 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15685 case ALTIVEC_BUILTIN_VSLB
:
15686 case ALTIVEC_BUILTIN_VSLH
:
15687 case ALTIVEC_BUILTIN_VSLW
:
15688 case P8V_BUILTIN_VSLD
:
15691 gimple_seq stmts
= NULL
;
15692 arg0
= gimple_call_arg (stmt
, 0);
15693 tree arg0_type
= TREE_TYPE (arg0
);
15694 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type
))
15695 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type
)))
15697 arg1
= gimple_call_arg (stmt
, 1);
15698 tree arg1_type
= TREE_TYPE (arg1
);
15699 tree unsigned_arg1_type
= unsigned_type_for (TREE_TYPE (arg1
));
15700 tree unsigned_element_type
= unsigned_type_for (TREE_TYPE (arg1_type
));
15701 loc
= gimple_location (stmt
);
15702 lhs
= gimple_call_lhs (stmt
);
15703 /* Force arg1 into the range valid matching the arg0 type. */
15704 /* Build a vector consisting of the max valid bit-size values. */
15705 int n_elts
= VECTOR_CST_NELTS (arg1
);
15706 int tree_size_in_bits
= TREE_INT_CST_LOW (size_in_bytes (arg1_type
))
15708 tree element_size
= build_int_cst (unsigned_element_type
,
15709 tree_size_in_bits
/ n_elts
);
15710 tree_vector_builder
elts (unsigned_type_for (arg1_type
), n_elts
, 1);
15711 for (int i
= 0; i
< n_elts
; i
++)
15712 elts
.safe_push (element_size
);
15713 tree modulo_tree
= elts
.build ();
15714 /* Modulo the provided shift value against that vector. */
15715 tree unsigned_arg1
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15716 unsigned_arg1_type
, arg1
);
15717 tree new_arg1
= gimple_build (&stmts
, loc
, TRUNC_MOD_EXPR
,
15718 unsigned_arg1_type
, unsigned_arg1
,
15720 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15721 /* And finally, do the shift. */
15722 g
= gimple_build_assign (lhs
, LSHIFT_EXPR
, arg0
, new_arg1
);
15723 gimple_set_location (g
, gimple_location (stmt
));
15724 gsi_replace (gsi
, g
, true);
15727 /* Flavors of vector shift right. */
15728 case ALTIVEC_BUILTIN_VSRB
:
15729 case ALTIVEC_BUILTIN_VSRH
:
15730 case ALTIVEC_BUILTIN_VSRW
:
15731 case P8V_BUILTIN_VSRD
:
15733 arg0
= gimple_call_arg (stmt
, 0);
15734 arg1
= gimple_call_arg (stmt
, 1);
15735 lhs
= gimple_call_lhs (stmt
);
15736 gimple_seq stmts
= NULL
;
15737 /* Convert arg0 to unsigned. */
15739 = gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15740 unsigned_type_for (TREE_TYPE (arg0
)), arg0
);
15742 = gimple_build (&stmts
, RSHIFT_EXPR
,
15743 TREE_TYPE (arg0_unsigned
), arg0_unsigned
, arg1
);
15744 /* Convert result back to the lhs type. */
15745 res
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
, TREE_TYPE (lhs
), res
);
15746 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15747 update_call_from_tree (gsi
, res
);
15750 /* Vector loads. */
15751 case ALTIVEC_BUILTIN_LVX_V16QI
:
15752 case ALTIVEC_BUILTIN_LVX_V8HI
:
15753 case ALTIVEC_BUILTIN_LVX_V4SI
:
15754 case ALTIVEC_BUILTIN_LVX_V4SF
:
15755 case ALTIVEC_BUILTIN_LVX_V2DI
:
15756 case ALTIVEC_BUILTIN_LVX_V2DF
:
15757 case ALTIVEC_BUILTIN_LVX_V1TI
:
15759 arg0
= gimple_call_arg (stmt
, 0); // offset
15760 arg1
= gimple_call_arg (stmt
, 1); // address
15761 lhs
= gimple_call_lhs (stmt
);
15762 location_t loc
= gimple_location (stmt
);
15763 /* Since arg1 may be cast to a different type, just use ptr_type_node
15764 here instead of trying to enforce TBAA on pointer types. */
15765 tree arg1_type
= ptr_type_node
;
15766 tree lhs_type
= TREE_TYPE (lhs
);
15767 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15768 the tree using the value from arg0. The resulting type will match
15769 the type of arg1. */
15770 gimple_seq stmts
= NULL
;
15771 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg0
);
15772 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15773 arg1_type
, arg1
, temp_offset
);
15774 /* Mask off any lower bits from the address. */
15775 tree aligned_addr
= gimple_build (&stmts
, loc
, BIT_AND_EXPR
,
15776 arg1_type
, temp_addr
,
15777 build_int_cst (arg1_type
, -16));
15778 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15779 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15780 take an offset, but since we've already incorporated the offset
15781 above, here we just pass in a zero. */
15783 = gimple_build_assign (lhs
, build2 (MEM_REF
, lhs_type
, aligned_addr
,
15784 build_int_cst (arg1_type
, 0)));
15785 gimple_set_location (g
, loc
);
15786 gsi_replace (gsi
, g
, true);
15789 /* Vector stores. */
15790 case ALTIVEC_BUILTIN_STVX_V16QI
:
15791 case ALTIVEC_BUILTIN_STVX_V8HI
:
15792 case ALTIVEC_BUILTIN_STVX_V4SI
:
15793 case ALTIVEC_BUILTIN_STVX_V4SF
:
15794 case ALTIVEC_BUILTIN_STVX_V2DI
:
15795 case ALTIVEC_BUILTIN_STVX_V2DF
:
15797 arg0
= gimple_call_arg (stmt
, 0); /* Value to be stored. */
15798 arg1
= gimple_call_arg (stmt
, 1); /* Offset. */
15799 tree arg2
= gimple_call_arg (stmt
, 2); /* Store-to address. */
15800 location_t loc
= gimple_location (stmt
);
15801 tree arg0_type
= TREE_TYPE (arg0
);
15802 /* Use ptr_type_node (no TBAA) for the arg2_type.
15803 FIXME: (Richard) "A proper fix would be to transition this type as
15804 seen from the frontend to GIMPLE, for example in a similar way we
15805 do for MEM_REFs by piggy-backing that on an extra argument, a
15806 constant zero pointer of the alias pointer type to use (which would
15807 also serve as a type indicator of the store itself). I'd use a
15808 target specific internal function for this (not sure if we can have
15809 those target specific, but I guess if it's folded away then that's
15810 fine) and get away with the overload set." */
15811 tree arg2_type
= ptr_type_node
;
15812 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15813 the tree using the value from arg0. The resulting type will match
15814 the type of arg2. */
15815 gimple_seq stmts
= NULL
;
15816 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg1
);
15817 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15818 arg2_type
, arg2
, temp_offset
);
15819 /* Mask off any lower bits from the address. */
15820 tree aligned_addr
= gimple_build (&stmts
, loc
, BIT_AND_EXPR
,
15821 arg2_type
, temp_addr
,
15822 build_int_cst (arg2_type
, -16));
15823 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15824 /* The desired gimple result should be similar to:
15825 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15827 = gimple_build_assign (build2 (MEM_REF
, arg0_type
, aligned_addr
,
15828 build_int_cst (arg2_type
, 0)), arg0
);
15829 gimple_set_location (g
, loc
);
15830 gsi_replace (gsi
, g
, true);
15834 /* unaligned Vector loads. */
15835 case VSX_BUILTIN_LXVW4X_V16QI
:
15836 case VSX_BUILTIN_LXVW4X_V8HI
:
15837 case VSX_BUILTIN_LXVW4X_V4SF
:
15838 case VSX_BUILTIN_LXVW4X_V4SI
:
15839 case VSX_BUILTIN_LXVD2X_V2DF
:
15840 case VSX_BUILTIN_LXVD2X_V2DI
:
15842 arg0
= gimple_call_arg (stmt
, 0); // offset
15843 arg1
= gimple_call_arg (stmt
, 1); // address
15844 lhs
= gimple_call_lhs (stmt
);
15845 location_t loc
= gimple_location (stmt
);
15846 /* Since arg1 may be cast to a different type, just use ptr_type_node
15847 here instead of trying to enforce TBAA on pointer types. */
15848 tree arg1_type
= ptr_type_node
;
15849 tree lhs_type
= TREE_TYPE (lhs
);
15850 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15851 required alignment (power) is 4 bytes regardless of data type. */
15852 tree align_ltype
= build_aligned_type (lhs_type
, 4);
15853 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15854 the tree using the value from arg0. The resulting type will match
15855 the type of arg1. */
15856 gimple_seq stmts
= NULL
;
15857 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg0
);
15858 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15859 arg1_type
, arg1
, temp_offset
);
15860 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15861 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15862 take an offset, but since we've already incorporated the offset
15863 above, here we just pass in a zero. */
15865 g
= gimple_build_assign (lhs
, build2 (MEM_REF
, align_ltype
, temp_addr
,
15866 build_int_cst (arg1_type
, 0)));
15867 gimple_set_location (g
, loc
);
15868 gsi_replace (gsi
, g
, true);
15872 /* unaligned Vector stores. */
15873 case VSX_BUILTIN_STXVW4X_V16QI
:
15874 case VSX_BUILTIN_STXVW4X_V8HI
:
15875 case VSX_BUILTIN_STXVW4X_V4SF
:
15876 case VSX_BUILTIN_STXVW4X_V4SI
:
15877 case VSX_BUILTIN_STXVD2X_V2DF
:
15878 case VSX_BUILTIN_STXVD2X_V2DI
:
15880 arg0
= gimple_call_arg (stmt
, 0); /* Value to be stored. */
15881 arg1
= gimple_call_arg (stmt
, 1); /* Offset. */
15882 tree arg2
= gimple_call_arg (stmt
, 2); /* Store-to address. */
15883 location_t loc
= gimple_location (stmt
);
15884 tree arg0_type
= TREE_TYPE (arg0
);
15885 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15886 tree arg2_type
= ptr_type_node
;
15887 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15888 required alignment (power) is 4 bytes regardless of data type. */
15889 tree align_stype
= build_aligned_type (arg0_type
, 4);
15890 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15891 the tree using the value from arg1. */
15892 gimple_seq stmts
= NULL
;
15893 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg1
);
15894 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15895 arg2_type
, arg2
, temp_offset
);
15896 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15898 g
= gimple_build_assign (build2 (MEM_REF
, align_stype
, temp_addr
,
15899 build_int_cst (arg2_type
, 0)), arg0
);
15900 gimple_set_location (g
, loc
);
15901 gsi_replace (gsi
, g
, true);
15905 /* Vector Fused multiply-add (fma). */
15906 case ALTIVEC_BUILTIN_VMADDFP
:
15907 case VSX_BUILTIN_XVMADDDP
:
15908 case ALTIVEC_BUILTIN_VMLADDUHM
:
15910 arg0
= gimple_call_arg (stmt
, 0);
15911 arg1
= gimple_call_arg (stmt
, 1);
15912 tree arg2
= gimple_call_arg (stmt
, 2);
15913 lhs
= gimple_call_lhs (stmt
);
15914 gcall
*g
= gimple_build_call_internal (IFN_FMA
, 3, arg0
, arg1
, arg2
);
15915 gimple_call_set_lhs (g
, lhs
);
15916 gimple_call_set_nothrow (g
, true);
15917 gimple_set_location (g
, gimple_location (stmt
));
15918 gsi_replace (gsi
, g
, true);
15922 /* Vector compares; EQ, NE, GE, GT, LE. */
15923 case ALTIVEC_BUILTIN_VCMPEQUB
:
15924 case ALTIVEC_BUILTIN_VCMPEQUH
:
15925 case ALTIVEC_BUILTIN_VCMPEQUW
:
15926 case P8V_BUILTIN_VCMPEQUD
:
15927 fold_compare_helper (gsi
, EQ_EXPR
, stmt
);
15930 case P9V_BUILTIN_CMPNEB
:
15931 case P9V_BUILTIN_CMPNEH
:
15932 case P9V_BUILTIN_CMPNEW
:
15933 fold_compare_helper (gsi
, NE_EXPR
, stmt
);
15936 case VSX_BUILTIN_CMPGE_16QI
:
15937 case VSX_BUILTIN_CMPGE_U16QI
:
15938 case VSX_BUILTIN_CMPGE_8HI
:
15939 case VSX_BUILTIN_CMPGE_U8HI
:
15940 case VSX_BUILTIN_CMPGE_4SI
:
15941 case VSX_BUILTIN_CMPGE_U4SI
:
15942 case VSX_BUILTIN_CMPGE_2DI
:
15943 case VSX_BUILTIN_CMPGE_U2DI
:
15944 fold_compare_helper (gsi
, GE_EXPR
, stmt
);
15947 case ALTIVEC_BUILTIN_VCMPGTSB
:
15948 case ALTIVEC_BUILTIN_VCMPGTUB
:
15949 case ALTIVEC_BUILTIN_VCMPGTSH
:
15950 case ALTIVEC_BUILTIN_VCMPGTUH
:
15951 case ALTIVEC_BUILTIN_VCMPGTSW
:
15952 case ALTIVEC_BUILTIN_VCMPGTUW
:
15953 case P8V_BUILTIN_VCMPGTUD
:
15954 case P8V_BUILTIN_VCMPGTSD
:
15955 fold_compare_helper (gsi
, GT_EXPR
, stmt
);
15958 case VSX_BUILTIN_CMPLE_16QI
:
15959 case VSX_BUILTIN_CMPLE_U16QI
:
15960 case VSX_BUILTIN_CMPLE_8HI
:
15961 case VSX_BUILTIN_CMPLE_U8HI
:
15962 case VSX_BUILTIN_CMPLE_4SI
:
15963 case VSX_BUILTIN_CMPLE_U4SI
:
15964 case VSX_BUILTIN_CMPLE_2DI
:
15965 case VSX_BUILTIN_CMPLE_U2DI
:
15966 fold_compare_helper (gsi
, LE_EXPR
, stmt
);
15969 /* flavors of vec_splat_[us]{8,16,32}. */
15970 case ALTIVEC_BUILTIN_VSPLTISB
:
15971 case ALTIVEC_BUILTIN_VSPLTISH
:
15972 case ALTIVEC_BUILTIN_VSPLTISW
:
15975 if (fn_code
== ALTIVEC_BUILTIN_VSPLTISB
)
15977 else if (fn_code
== ALTIVEC_BUILTIN_VSPLTISH
)
15982 arg0
= gimple_call_arg (stmt
, 0);
15983 lhs
= gimple_call_lhs (stmt
);
15985 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15986 5-bit signed constant in range -16 to +15. */
15987 if (TREE_CODE (arg0
) != INTEGER_CST
15988 || !IN_RANGE (sext_hwi (TREE_INT_CST_LOW (arg0
), size
),
15991 gimple_seq stmts
= NULL
;
15992 location_t loc
= gimple_location (stmt
);
15993 tree splat_value
= gimple_convert (&stmts
, loc
,
15994 TREE_TYPE (TREE_TYPE (lhs
)), arg0
);
15995 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15996 tree splat_tree
= build_vector_from_val (TREE_TYPE (lhs
), splat_value
);
15997 g
= gimple_build_assign (lhs
, splat_tree
);
15998 gimple_set_location (g
, gimple_location (stmt
));
15999 gsi_replace (gsi
, g
, true);
16003 /* Flavors of vec_splat. */
16004 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
16005 case ALTIVEC_BUILTIN_VSPLTB
:
16006 case ALTIVEC_BUILTIN_VSPLTH
:
16007 case ALTIVEC_BUILTIN_VSPLTW
:
16008 case VSX_BUILTIN_XXSPLTD_V2DI
:
16009 case VSX_BUILTIN_XXSPLTD_V2DF
:
16011 arg0
= gimple_call_arg (stmt
, 0); /* input vector. */
16012 arg1
= gimple_call_arg (stmt
, 1); /* index into arg0. */
16013 /* Only fold the vec_splat_*() if arg1 is both a constant value and
16014 is a valid index into the arg0 vector. */
16015 unsigned int n_elts
= VECTOR_CST_NELTS (arg0
);
16016 if (TREE_CODE (arg1
) != INTEGER_CST
16017 || TREE_INT_CST_LOW (arg1
) > (n_elts
-1))
16019 lhs
= gimple_call_lhs (stmt
);
16020 tree lhs_type
= TREE_TYPE (lhs
);
16021 tree arg0_type
= TREE_TYPE (arg0
);
16023 if (TREE_CODE (arg0
) == VECTOR_CST
)
16024 splat
= VECTOR_CST_ELT (arg0
, TREE_INT_CST_LOW (arg1
));
16027 /* Determine (in bits) the length and start location of the
16028 splat value for a call to the tree_vec_extract helper. */
16029 int splat_elem_size
= TREE_INT_CST_LOW (size_in_bytes (arg0_type
))
16030 * BITS_PER_UNIT
/ n_elts
;
16031 int splat_start_bit
= TREE_INT_CST_LOW (arg1
) * splat_elem_size
;
16032 tree len
= build_int_cst (bitsizetype
, splat_elem_size
);
16033 tree start
= build_int_cst (bitsizetype
, splat_start_bit
);
16034 splat
= tree_vec_extract (gsi
, TREE_TYPE (lhs_type
), arg0
,
16037 /* And finally, build the new vector. */
16038 tree splat_tree
= build_vector_from_val (lhs_type
, splat
);
16039 g
= gimple_build_assign (lhs
, splat_tree
);
16040 gimple_set_location (g
, gimple_location (stmt
));
16041 gsi_replace (gsi
, g
, true);
16045 /* vec_mergel (integrals). */
16046 case ALTIVEC_BUILTIN_VMRGLH
:
16047 case ALTIVEC_BUILTIN_VMRGLW
:
16048 case VSX_BUILTIN_XXMRGLW_4SI
:
16049 case ALTIVEC_BUILTIN_VMRGLB
:
16050 case VSX_BUILTIN_VEC_MERGEL_V2DI
:
16051 case VSX_BUILTIN_XXMRGLW_4SF
:
16052 case VSX_BUILTIN_VEC_MERGEL_V2DF
:
16053 fold_mergehl_helper (gsi
, stmt
, 1);
16055 /* vec_mergeh (integrals). */
16056 case ALTIVEC_BUILTIN_VMRGHH
:
16057 case ALTIVEC_BUILTIN_VMRGHW
:
16058 case VSX_BUILTIN_XXMRGHW_4SI
:
16059 case ALTIVEC_BUILTIN_VMRGHB
:
16060 case VSX_BUILTIN_VEC_MERGEH_V2DI
:
16061 case VSX_BUILTIN_XXMRGHW_4SF
:
16062 case VSX_BUILTIN_VEC_MERGEH_V2DF
:
16063 fold_mergehl_helper (gsi
, stmt
, 0);
16066 /* Flavors of vec_mergee. */
16067 case P8V_BUILTIN_VMRGEW_V4SI
:
16068 case P8V_BUILTIN_VMRGEW_V2DI
:
16069 case P8V_BUILTIN_VMRGEW_V4SF
:
16070 case P8V_BUILTIN_VMRGEW_V2DF
:
16071 fold_mergeeo_helper (gsi
, stmt
, 0);
16073 /* Flavors of vec_mergeo. */
16074 case P8V_BUILTIN_VMRGOW_V4SI
:
16075 case P8V_BUILTIN_VMRGOW_V2DI
:
16076 case P8V_BUILTIN_VMRGOW_V4SF
:
16077 case P8V_BUILTIN_VMRGOW_V2DF
:
16078 fold_mergeeo_helper (gsi
, stmt
, 1);
16081 /* d = vec_pack (a, b) */
16082 case P8V_BUILTIN_VPKUDUM
:
16083 case ALTIVEC_BUILTIN_VPKUHUM
:
16084 case ALTIVEC_BUILTIN_VPKUWUM
:
16086 arg0
= gimple_call_arg (stmt
, 0);
16087 arg1
= gimple_call_arg (stmt
, 1);
16088 lhs
= gimple_call_lhs (stmt
);
16089 gimple
*g
= gimple_build_assign (lhs
, VEC_PACK_TRUNC_EXPR
, arg0
, arg1
);
16090 gimple_set_location (g
, gimple_location (stmt
));
16091 gsi_replace (gsi
, g
, true);
16095 /* d = vec_unpackh (a) */
16096 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
16097 in this code is sensitive to endian-ness, and needs to be inverted to
16098 handle both LE and BE targets. */
16099 case ALTIVEC_BUILTIN_VUPKHSB
:
16100 case ALTIVEC_BUILTIN_VUPKHSH
:
16101 case P8V_BUILTIN_VUPKHSW
:
16103 arg0
= gimple_call_arg (stmt
, 0);
16104 lhs
= gimple_call_lhs (stmt
);
16105 if (BYTES_BIG_ENDIAN
)
16106 g
= gimple_build_assign (lhs
, VEC_UNPACK_HI_EXPR
, arg0
);
16108 g
= gimple_build_assign (lhs
, VEC_UNPACK_LO_EXPR
, arg0
);
16109 gimple_set_location (g
, gimple_location (stmt
));
16110 gsi_replace (gsi
, g
, true);
16113 /* d = vec_unpackl (a) */
16114 case ALTIVEC_BUILTIN_VUPKLSB
:
16115 case ALTIVEC_BUILTIN_VUPKLSH
:
16116 case P8V_BUILTIN_VUPKLSW
:
16118 arg0
= gimple_call_arg (stmt
, 0);
16119 lhs
= gimple_call_lhs (stmt
);
16120 if (BYTES_BIG_ENDIAN
)
16121 g
= gimple_build_assign (lhs
, VEC_UNPACK_LO_EXPR
, arg0
);
16123 g
= gimple_build_assign (lhs
, VEC_UNPACK_HI_EXPR
, arg0
);
16124 gimple_set_location (g
, gimple_location (stmt
));
16125 gsi_replace (gsi
, g
, true);
16128 /* There is no gimple type corresponding with pixel, so just return. */
16129 case ALTIVEC_BUILTIN_VUPKHPX
:
16130 case ALTIVEC_BUILTIN_VUPKLPX
:
16134 case ALTIVEC_BUILTIN_VPERM_16QI
:
16135 case ALTIVEC_BUILTIN_VPERM_8HI
:
16136 case ALTIVEC_BUILTIN_VPERM_4SI
:
16137 case ALTIVEC_BUILTIN_VPERM_2DI
:
16138 case ALTIVEC_BUILTIN_VPERM_4SF
:
16139 case ALTIVEC_BUILTIN_VPERM_2DF
:
16141 arg0
= gimple_call_arg (stmt
, 0);
16142 arg1
= gimple_call_arg (stmt
, 1);
16143 tree permute
= gimple_call_arg (stmt
, 2);
16144 lhs
= gimple_call_lhs (stmt
);
16145 location_t loc
= gimple_location (stmt
);
16146 gimple_seq stmts
= NULL
;
16147 // convert arg0 and arg1 to match the type of the permute
16148 // for the VEC_PERM_EXPR operation.
16149 tree permute_type
= (TREE_TYPE (permute
));
16150 tree arg0_ptype
= gimple_convert (&stmts
, loc
, permute_type
, arg0
);
16151 tree arg1_ptype
= gimple_convert (&stmts
, loc
, permute_type
, arg1
);
16152 tree lhs_ptype
= gimple_build (&stmts
, loc
, VEC_PERM_EXPR
,
16153 permute_type
, arg0_ptype
, arg1_ptype
,
16155 // Convert the result back to the desired lhs type upon completion.
16156 tree temp
= gimple_convert (&stmts
, loc
, TREE_TYPE (lhs
), lhs_ptype
);
16157 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
16158 g
= gimple_build_assign (lhs
, temp
);
16159 gimple_set_location (g
, loc
);
16160 gsi_replace (gsi
, g
, true);
16165 if (TARGET_DEBUG_BUILTIN
)
16166 fprintf (stderr
, "gimple builtin intrinsic not matched:%d %s %s\n",
16167 fn_code
, fn_name1
, fn_name2
);
16174 /* Expand an expression EXP that calls a built-in function,
16175 with result going to TARGET if that's convenient
16176 (and in mode MODE if that's convenient).
16177 SUBTARGET may be used as the target for computing one of EXP's operands.
16178 IGNORE is nonzero if the value is to be ignored. */
16181 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
16182 machine_mode mode ATTRIBUTE_UNUSED
,
16183 int ignore ATTRIBUTE_UNUSED
)
16185 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
16186 enum rs6000_builtins fcode
16187 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
16188 size_t uns_fcode
= (size_t)fcode
;
16189 const struct builtin_description
*d
;
16193 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
16194 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
16195 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
16197 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16198 floating point type, depending on whether long double is the IBM extended
16199 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16200 we only define one variant of the built-in function, and switch the code
16201 when defining it, rather than defining two built-ins and using the
16202 overload table in rs6000-c.c to switch between the two. If we don't have
16203 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16204 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16205 if (FLOAT128_IEEE_P (TFmode
))
16211 case CODE_FOR_sqrtkf2_odd
: icode
= CODE_FOR_sqrttf2_odd
; break;
16212 case CODE_FOR_trunckfdf2_odd
: icode
= CODE_FOR_trunctfdf2_odd
; break;
16213 case CODE_FOR_addkf3_odd
: icode
= CODE_FOR_addtf3_odd
; break;
16214 case CODE_FOR_subkf3_odd
: icode
= CODE_FOR_subtf3_odd
; break;
16215 case CODE_FOR_mulkf3_odd
: icode
= CODE_FOR_multf3_odd
; break;
16216 case CODE_FOR_divkf3_odd
: icode
= CODE_FOR_divtf3_odd
; break;
16217 case CODE_FOR_fmakf4_odd
: icode
= CODE_FOR_fmatf4_odd
; break;
16218 case CODE_FOR_xsxexpqp_kf
: icode
= CODE_FOR_xsxexpqp_tf
; break;
16219 case CODE_FOR_xsxsigqp_kf
: icode
= CODE_FOR_xsxsigqp_tf
; break;
16220 case CODE_FOR_xststdcnegqp_kf
: icode
= CODE_FOR_xststdcnegqp_tf
; break;
16221 case CODE_FOR_xsiexpqp_kf
: icode
= CODE_FOR_xsiexpqp_tf
; break;
16222 case CODE_FOR_xsiexpqpf_kf
: icode
= CODE_FOR_xsiexpqpf_tf
; break;
16223 case CODE_FOR_xststdcqp_kf
: icode
= CODE_FOR_xststdcqp_tf
; break;
16226 if (TARGET_DEBUG_BUILTIN
)
16228 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
16229 const char *name2
= (icode
!= CODE_FOR_nothing
)
16230 ? get_insn_name ((int) icode
)
16234 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
16236 default: name3
= "unknown"; break;
16237 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
16238 case RS6000_BTC_UNARY
: name3
= "unary"; break;
16239 case RS6000_BTC_BINARY
: name3
= "binary"; break;
16240 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
16241 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
16242 case RS6000_BTC_ABS
: name3
= "abs"; break;
16243 case RS6000_BTC_DST
: name3
= "dst"; break;
16248 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16249 (name1
) ? name1
: "---", fcode
,
16250 (name2
) ? name2
: "---", (int) icode
,
16252 func_valid_p
? "" : ", not valid");
16257 rs6000_invalid_builtin (fcode
);
16259 /* Given it is invalid, just generate a normal call. */
16260 return expand_call (exp
, target
, ignore
);
16265 case RS6000_BUILTIN_RECIP
:
16266 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
16268 case RS6000_BUILTIN_RECIPF
:
16269 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
16271 case RS6000_BUILTIN_RSQRTF
:
16272 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
16274 case RS6000_BUILTIN_RSQRT
:
16275 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
16277 case POWER7_BUILTIN_BPERMD
:
16278 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
16279 ? CODE_FOR_bpermd_di
16280 : CODE_FOR_bpermd_si
), exp
, target
);
16282 case RS6000_BUILTIN_GET_TB
:
16283 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
16286 case RS6000_BUILTIN_MFTB
:
16287 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
16288 ? CODE_FOR_rs6000_mftb_di
16289 : CODE_FOR_rs6000_mftb_si
),
16292 case RS6000_BUILTIN_MFFS
:
16293 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
16295 case RS6000_BUILTIN_MTFSB0
:
16296 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0
, exp
);
16298 case RS6000_BUILTIN_MTFSB1
:
16299 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1
, exp
);
16301 case RS6000_BUILTIN_SET_FPSCR_RN
:
16302 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn
,
16305 case RS6000_BUILTIN_SET_FPSCR_DRN
:
16307 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn
,
16310 case RS6000_BUILTIN_MFFSL
:
16311 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl
, target
);
16313 case RS6000_BUILTIN_MTFSF
:
16314 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
16316 case RS6000_BUILTIN_CPU_INIT
:
16317 case RS6000_BUILTIN_CPU_IS
:
16318 case RS6000_BUILTIN_CPU_SUPPORTS
:
16319 return cpu_expand_builtin (fcode
, exp
, target
);
16321 case MISC_BUILTIN_SPEC_BARRIER
:
16323 emit_insn (gen_speculation_barrier ());
16327 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
16328 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
16330 int icode2
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
16331 : (int) CODE_FOR_altivec_lvsl_direct
);
16332 machine_mode tmode
= insn_data
[icode2
].operand
[0].mode
;
16333 machine_mode mode
= insn_data
[icode2
].operand
[1].mode
;
16337 gcc_assert (TARGET_ALTIVEC
);
16339 arg
= CALL_EXPR_ARG (exp
, 0);
16340 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
16341 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
16342 addr
= memory_address (mode
, op
);
16343 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
16347 /* For the load case need to negate the address. */
16348 op
= gen_reg_rtx (GET_MODE (addr
));
16349 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
16351 op
= gen_rtx_MEM (mode
, op
);
16354 || GET_MODE (target
) != tmode
16355 || ! (*insn_data
[icode2
].operand
[0].predicate
) (target
, tmode
))
16356 target
= gen_reg_rtx (tmode
);
16358 pat
= GEN_FCN (icode2
) (target
, op
);
16366 case ALTIVEC_BUILTIN_VCFUX
:
16367 case ALTIVEC_BUILTIN_VCFSX
:
16368 case ALTIVEC_BUILTIN_VCTUXS
:
16369 case ALTIVEC_BUILTIN_VCTSXS
:
16370 /* FIXME: There's got to be a nicer way to handle this case than
16371 constructing a new CALL_EXPR. */
16372 if (call_expr_nargs (exp
) == 1)
16374 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
16375 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
16379 /* For the pack and unpack int128 routines, fix up the builtin so it
16380 uses the correct IBM128 type. */
16381 case MISC_BUILTIN_PACK_IF
:
16382 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
16384 icode
= CODE_FOR_packtf
;
16385 fcode
= MISC_BUILTIN_PACK_TF
;
16386 uns_fcode
= (size_t)fcode
;
16390 case MISC_BUILTIN_UNPACK_IF
:
16391 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
16393 icode
= CODE_FOR_unpacktf
;
16394 fcode
= MISC_BUILTIN_UNPACK_TF
;
16395 uns_fcode
= (size_t)fcode
;
16403 if (TARGET_ALTIVEC
)
16405 ret
= altivec_expand_builtin (exp
, target
, &success
);
16412 ret
= htm_expand_builtin (exp
, target
, &success
);
16418 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
16419 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16420 gcc_assert (attr
== RS6000_BTC_UNARY
16421 || attr
== RS6000_BTC_BINARY
16422 || attr
== RS6000_BTC_TERNARY
16423 || attr
== RS6000_BTC_SPECIAL
);
16425 /* Handle simple unary operations. */
16427 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
16428 if (d
->code
== fcode
)
16429 return rs6000_expand_unop_builtin (icode
, exp
, target
);
16431 /* Handle simple binary operations. */
16433 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
16434 if (d
->code
== fcode
)
16435 return rs6000_expand_binop_builtin (icode
, exp
, target
);
16437 /* Handle simple ternary operations. */
16439 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
16440 if (d
->code
== fcode
)
16441 return rs6000_expand_ternop_builtin (icode
, exp
, target
);
16443 /* Handle simple no-argument operations. */
16445 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
16446 if (d
->code
== fcode
)
16447 return rs6000_expand_zeroop_builtin (icode
, target
);
16449 gcc_unreachable ();
16452 /* Create a builtin vector type with a name. Taking care not to give
16453 the canonical type a name. */
16456 rs6000_vector_type (const char *name
, tree elt_type
, unsigned num_elts
)
16458 tree result
= build_vector_type (elt_type
, num_elts
);
16460 /* Copy so we don't give the canonical type a name. */
16461 result
= build_variant_type_copy (result
);
16463 add_builtin_type (name
, result
);
16469 rs6000_init_builtins (void)
16475 if (TARGET_DEBUG_BUILTIN
)
16476 fprintf (stderr
, "rs6000_init_builtins%s%s\n",
16477 (TARGET_ALTIVEC
) ? ", altivec" : "",
16478 (TARGET_VSX
) ? ", vsx" : "");
16480 V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
? "__vector long"
16481 : "__vector long long",
16482 intDI_type_node
, 2);
16483 V2DF_type_node
= rs6000_vector_type ("__vector double", double_type_node
, 2);
16484 V4SI_type_node
= rs6000_vector_type ("__vector signed int",
16485 intSI_type_node
, 4);
16486 V4SF_type_node
= rs6000_vector_type ("__vector float", float_type_node
, 4);
16487 V8HI_type_node
= rs6000_vector_type ("__vector signed short",
16488 intHI_type_node
, 8);
16489 V16QI_type_node
= rs6000_vector_type ("__vector signed char",
16490 intQI_type_node
, 16);
16492 unsigned_V16QI_type_node
= rs6000_vector_type ("__vector unsigned char",
16493 unsigned_intQI_type_node
, 16);
16494 unsigned_V8HI_type_node
= rs6000_vector_type ("__vector unsigned short",
16495 unsigned_intHI_type_node
, 8);
16496 unsigned_V4SI_type_node
= rs6000_vector_type ("__vector unsigned int",
16497 unsigned_intSI_type_node
, 4);
16498 unsigned_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16499 ? "__vector unsigned long"
16500 : "__vector unsigned long long",
16501 unsigned_intDI_type_node
, 2);
16503 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
16505 const_str_type_node
16506 = build_pointer_type (build_qualified_type (char_type_node
,
16509 /* We use V1TI mode as a special container to hold __int128_t items that
16510 must live in VSX registers. */
16511 if (intTI_type_node
)
16513 V1TI_type_node
= rs6000_vector_type ("__vector __int128",
16514 intTI_type_node
, 1);
16515 unsigned_V1TI_type_node
16516 = rs6000_vector_type ("__vector unsigned __int128",
16517 unsigned_intTI_type_node
, 1);
16520 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16521 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16522 'vector unsigned short'. */
16524 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
16525 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16526 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
16527 bool_long_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
16528 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16530 long_integer_type_internal_node
= long_integer_type_node
;
16531 long_unsigned_type_internal_node
= long_unsigned_type_node
;
16532 long_long_integer_type_internal_node
= long_long_integer_type_node
;
16533 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
16534 intQI_type_internal_node
= intQI_type_node
;
16535 uintQI_type_internal_node
= unsigned_intQI_type_node
;
16536 intHI_type_internal_node
= intHI_type_node
;
16537 uintHI_type_internal_node
= unsigned_intHI_type_node
;
16538 intSI_type_internal_node
= intSI_type_node
;
16539 uintSI_type_internal_node
= unsigned_intSI_type_node
;
16540 intDI_type_internal_node
= intDI_type_node
;
16541 uintDI_type_internal_node
= unsigned_intDI_type_node
;
16542 intTI_type_internal_node
= intTI_type_node
;
16543 uintTI_type_internal_node
= unsigned_intTI_type_node
;
16544 float_type_internal_node
= float_type_node
;
16545 double_type_internal_node
= double_type_node
;
16546 long_double_type_internal_node
= long_double_type_node
;
16547 dfloat64_type_internal_node
= dfloat64_type_node
;
16548 dfloat128_type_internal_node
= dfloat128_type_node
;
16549 void_type_internal_node
= void_type_node
;
16551 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16552 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16553 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16554 format that uses a pair of doubles, depending on the switches and
16557 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16558 floating point, we need make sure the type is non-zero or else self-test
16559 fails during bootstrap.
16561 Always create __ibm128 as a separate type, even if the current long double
16562 format is IBM extended double.
16564 For IEEE 128-bit floating point, always create the type __ieee128. If the
16565 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16567 if (TARGET_FLOAT128_TYPE
)
16569 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
)
16570 ibm128_float_type_node
= long_double_type_node
;
16573 ibm128_float_type_node
= make_node (REAL_TYPE
);
16574 TYPE_PRECISION (ibm128_float_type_node
) = 128;
16575 SET_TYPE_MODE (ibm128_float_type_node
, IFmode
);
16576 layout_type (ibm128_float_type_node
);
16579 lang_hooks
.types
.register_builtin_type (ibm128_float_type_node
,
16582 if (TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
)
16583 ieee128_float_type_node
= long_double_type_node
;
16585 ieee128_float_type_node
= float128_type_node
;
16587 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
16592 ieee128_float_type_node
= ibm128_float_type_node
= long_double_type_node
;
16594 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16596 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
16597 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
16598 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
16599 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
16600 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
16601 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
16602 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
16603 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
16604 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
16605 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
16606 builtin_mode_to_type
[IFmode
][0] = ibm128_float_type_node
;
16607 builtin_mode_to_type
[KFmode
][0] = ieee128_float_type_node
;
16608 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
16609 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
16610 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
16611 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
16612 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
16613 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
16614 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
16615 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
16616 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
16617 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
16618 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
16619 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
16620 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
16621 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
16622 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
16624 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
16625 TYPE_NAME (bool_char_type_node
) = tdecl
;
16627 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
16628 TYPE_NAME (bool_short_type_node
) = tdecl
;
16630 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
16631 TYPE_NAME (bool_int_type_node
) = tdecl
;
16633 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
16634 TYPE_NAME (pixel_type_node
) = tdecl
;
16636 bool_V16QI_type_node
= rs6000_vector_type ("__vector __bool char",
16637 bool_char_type_node
, 16);
16638 bool_V8HI_type_node
= rs6000_vector_type ("__vector __bool short",
16639 bool_short_type_node
, 8);
16640 bool_V4SI_type_node
= rs6000_vector_type ("__vector __bool int",
16641 bool_int_type_node
, 4);
16642 bool_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16643 ? "__vector __bool long"
16644 : "__vector __bool long long",
16645 bool_long_long_type_node
, 2);
16646 pixel_V8HI_type_node
= rs6000_vector_type ("__vector __pixel",
16647 pixel_type_node
, 8);
16649 /* Create Altivec and VSX builtins on machines with at least the
16650 general purpose extensions (970 and newer) to allow the use of
16651 the target attribute. */
16652 if (TARGET_EXTRA_BUILTINS
)
16653 altivec_init_builtins ();
16655 htm_init_builtins ();
16657 if (TARGET_EXTRA_BUILTINS
)
16658 rs6000_common_init_builtins ();
16660 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
16661 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
16662 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
16664 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
16665 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
16666 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
16668 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
16669 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
16670 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
16672 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
16673 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
16674 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
16676 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
16677 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
16678 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
16679 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
16681 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16683 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
16686 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16689 ftype
= build_function_type_list (unsigned_intSI_type_node
,
16691 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
16693 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
16694 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
16696 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
16697 def_builtin ("__builtin_mffsl", ftype
, RS6000_BUILTIN_MFFSL
);
16699 ftype
= build_function_type_list (void_type_node
,
16702 def_builtin ("__builtin_mtfsb0", ftype
, RS6000_BUILTIN_MTFSB0
);
16704 ftype
= build_function_type_list (void_type_node
,
16707 def_builtin ("__builtin_mtfsb1", ftype
, RS6000_BUILTIN_MTFSB1
);
16709 ftype
= build_function_type_list (void_type_node
,
16712 def_builtin ("__builtin_set_fpscr_rn", ftype
, RS6000_BUILTIN_SET_FPSCR_RN
);
16714 ftype
= build_function_type_list (void_type_node
,
16717 def_builtin ("__builtin_set_fpscr_drn", ftype
, RS6000_BUILTIN_SET_FPSCR_DRN
);
16719 ftype
= build_function_type_list (void_type_node
,
16720 intSI_type_node
, double_type_node
,
16722 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
16724 ftype
= build_function_type_list (void_type_node
, NULL_TREE
);
16725 def_builtin ("__builtin_cpu_init", ftype
, RS6000_BUILTIN_CPU_INIT
);
16726 def_builtin ("__builtin_ppc_speculation_barrier", ftype
,
16727 MISC_BUILTIN_SPEC_BARRIER
);
16729 ftype
= build_function_type_list (bool_int_type_node
, const_ptr_type_node
,
16731 def_builtin ("__builtin_cpu_is", ftype
, RS6000_BUILTIN_CPU_IS
);
16732 def_builtin ("__builtin_cpu_supports", ftype
, RS6000_BUILTIN_CPU_SUPPORTS
);
16734 /* AIX libm provides clog as __clog. */
16735 if (TARGET_XCOFF
&&
16736 (tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
16737 set_user_assembler_name (tdecl
, "__clog");
16739 #ifdef SUBTARGET_INIT_BUILTINS
16740 SUBTARGET_INIT_BUILTINS
;
16744 /* Returns the rs6000 builtin decl for CODE. */
16747 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
16749 HOST_WIDE_INT fnmask
;
16751 if (code
>= RS6000_BUILTIN_COUNT
)
16752 return error_mark_node
;
16754 fnmask
= rs6000_builtin_info
[code
].mask
;
16755 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
16757 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
16758 return error_mark_node
;
16761 return rs6000_builtin_decls
[code
];
16765 altivec_init_builtins (void)
16767 const struct builtin_description
*d
;
16771 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
16773 tree pvoid_type_node
= build_pointer_type (void_type_node
);
16775 tree pcvoid_type_node
16776 = build_pointer_type (build_qualified_type (void_type_node
,
16779 tree int_ftype_opaque
16780 = build_function_type_list (integer_type_node
,
16781 opaque_V4SI_type_node
, NULL_TREE
);
16782 tree opaque_ftype_opaque
16783 = build_function_type_list (integer_type_node
, NULL_TREE
);
16784 tree opaque_ftype_opaque_int
16785 = build_function_type_list (opaque_V4SI_type_node
,
16786 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
16787 tree opaque_ftype_opaque_opaque_int
16788 = build_function_type_list (opaque_V4SI_type_node
,
16789 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16790 integer_type_node
, NULL_TREE
);
16791 tree opaque_ftype_opaque_opaque_opaque
16792 = build_function_type_list (opaque_V4SI_type_node
,
16793 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16794 opaque_V4SI_type_node
, NULL_TREE
);
16795 tree opaque_ftype_opaque_opaque
16796 = build_function_type_list (opaque_V4SI_type_node
,
16797 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16799 tree int_ftype_int_opaque_opaque
16800 = build_function_type_list (integer_type_node
,
16801 integer_type_node
, opaque_V4SI_type_node
,
16802 opaque_V4SI_type_node
, NULL_TREE
);
16803 tree int_ftype_int_v4si_v4si
16804 = build_function_type_list (integer_type_node
,
16805 integer_type_node
, V4SI_type_node
,
16806 V4SI_type_node
, NULL_TREE
);
16807 tree int_ftype_int_v2di_v2di
16808 = build_function_type_list (integer_type_node
,
16809 integer_type_node
, V2DI_type_node
,
16810 V2DI_type_node
, NULL_TREE
);
16811 tree void_ftype_v4si
16812 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
16813 tree v8hi_ftype_void
16814 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
16815 tree void_ftype_void
16816 = build_function_type_list (void_type_node
, NULL_TREE
);
16817 tree void_ftype_int
16818 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
16820 tree opaque_ftype_long_pcvoid
16821 = build_function_type_list (opaque_V4SI_type_node
,
16822 long_integer_type_node
, pcvoid_type_node
,
16824 tree v16qi_ftype_long_pcvoid
16825 = build_function_type_list (V16QI_type_node
,
16826 long_integer_type_node
, pcvoid_type_node
,
16828 tree v8hi_ftype_long_pcvoid
16829 = build_function_type_list (V8HI_type_node
,
16830 long_integer_type_node
, pcvoid_type_node
,
16832 tree v4si_ftype_long_pcvoid
16833 = build_function_type_list (V4SI_type_node
,
16834 long_integer_type_node
, pcvoid_type_node
,
16836 tree v4sf_ftype_long_pcvoid
16837 = build_function_type_list (V4SF_type_node
,
16838 long_integer_type_node
, pcvoid_type_node
,
16840 tree v2df_ftype_long_pcvoid
16841 = build_function_type_list (V2DF_type_node
,
16842 long_integer_type_node
, pcvoid_type_node
,
16844 tree v2di_ftype_long_pcvoid
16845 = build_function_type_list (V2DI_type_node
,
16846 long_integer_type_node
, pcvoid_type_node
,
16848 tree v1ti_ftype_long_pcvoid
16849 = build_function_type_list (V1TI_type_node
,
16850 long_integer_type_node
, pcvoid_type_node
,
16853 tree void_ftype_opaque_long_pvoid
16854 = build_function_type_list (void_type_node
,
16855 opaque_V4SI_type_node
, long_integer_type_node
,
16856 pvoid_type_node
, NULL_TREE
);
16857 tree void_ftype_v4si_long_pvoid
16858 = build_function_type_list (void_type_node
,
16859 V4SI_type_node
, long_integer_type_node
,
16860 pvoid_type_node
, NULL_TREE
);
16861 tree void_ftype_v16qi_long_pvoid
16862 = build_function_type_list (void_type_node
,
16863 V16QI_type_node
, long_integer_type_node
,
16864 pvoid_type_node
, NULL_TREE
);
16866 tree void_ftype_v16qi_pvoid_long
16867 = build_function_type_list (void_type_node
,
16868 V16QI_type_node
, pvoid_type_node
,
16869 long_integer_type_node
, NULL_TREE
);
16871 tree void_ftype_v8hi_long_pvoid
16872 = build_function_type_list (void_type_node
,
16873 V8HI_type_node
, long_integer_type_node
,
16874 pvoid_type_node
, NULL_TREE
);
16875 tree void_ftype_v4sf_long_pvoid
16876 = build_function_type_list (void_type_node
,
16877 V4SF_type_node
, long_integer_type_node
,
16878 pvoid_type_node
, NULL_TREE
);
16879 tree void_ftype_v2df_long_pvoid
16880 = build_function_type_list (void_type_node
,
16881 V2DF_type_node
, long_integer_type_node
,
16882 pvoid_type_node
, NULL_TREE
);
16883 tree void_ftype_v1ti_long_pvoid
16884 = build_function_type_list (void_type_node
,
16885 V1TI_type_node
, long_integer_type_node
,
16886 pvoid_type_node
, NULL_TREE
);
16887 tree void_ftype_v2di_long_pvoid
16888 = build_function_type_list (void_type_node
,
16889 V2DI_type_node
, long_integer_type_node
,
16890 pvoid_type_node
, NULL_TREE
);
16891 tree int_ftype_int_v8hi_v8hi
16892 = build_function_type_list (integer_type_node
,
16893 integer_type_node
, V8HI_type_node
,
16894 V8HI_type_node
, NULL_TREE
);
16895 tree int_ftype_int_v16qi_v16qi
16896 = build_function_type_list (integer_type_node
,
16897 integer_type_node
, V16QI_type_node
,
16898 V16QI_type_node
, NULL_TREE
);
16899 tree int_ftype_int_v4sf_v4sf
16900 = build_function_type_list (integer_type_node
,
16901 integer_type_node
, V4SF_type_node
,
16902 V4SF_type_node
, NULL_TREE
);
16903 tree int_ftype_int_v2df_v2df
16904 = build_function_type_list (integer_type_node
,
16905 integer_type_node
, V2DF_type_node
,
16906 V2DF_type_node
, NULL_TREE
);
16907 tree v2di_ftype_v2di
16908 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
16909 tree v4si_ftype_v4si
16910 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
16911 tree v8hi_ftype_v8hi
16912 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
16913 tree v16qi_ftype_v16qi
16914 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
16915 tree v4sf_ftype_v4sf
16916 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
16917 tree v2df_ftype_v2df
16918 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
16919 tree void_ftype_pcvoid_int_int
16920 = build_function_type_list (void_type_node
,
16921 pcvoid_type_node
, integer_type_node
,
16922 integer_type_node
, NULL_TREE
);
16924 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
16925 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
16926 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
16927 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
16928 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
16929 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
16930 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
16931 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
16932 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
16933 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
16934 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
16935 ALTIVEC_BUILTIN_LVXL_V2DF
);
16936 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
16937 ALTIVEC_BUILTIN_LVXL_V2DI
);
16938 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
16939 ALTIVEC_BUILTIN_LVXL_V4SF
);
16940 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
16941 ALTIVEC_BUILTIN_LVXL_V4SI
);
16942 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
16943 ALTIVEC_BUILTIN_LVXL_V8HI
);
16944 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
16945 ALTIVEC_BUILTIN_LVXL_V16QI
);
16946 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
16947 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid
,
16948 ALTIVEC_BUILTIN_LVX_V1TI
);
16949 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
16950 ALTIVEC_BUILTIN_LVX_V2DF
);
16951 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
16952 ALTIVEC_BUILTIN_LVX_V2DI
);
16953 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
16954 ALTIVEC_BUILTIN_LVX_V4SF
);
16955 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
16956 ALTIVEC_BUILTIN_LVX_V4SI
);
16957 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
16958 ALTIVEC_BUILTIN_LVX_V8HI
);
16959 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
16960 ALTIVEC_BUILTIN_LVX_V16QI
);
16961 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
16962 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
16963 ALTIVEC_BUILTIN_STVX_V2DF
);
16964 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
16965 ALTIVEC_BUILTIN_STVX_V2DI
);
16966 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
16967 ALTIVEC_BUILTIN_STVX_V4SF
);
16968 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
16969 ALTIVEC_BUILTIN_STVX_V4SI
);
16970 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
16971 ALTIVEC_BUILTIN_STVX_V8HI
);
16972 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
16973 ALTIVEC_BUILTIN_STVX_V16QI
);
16974 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
16975 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
16976 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
16977 ALTIVEC_BUILTIN_STVXL_V2DF
);
16978 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
16979 ALTIVEC_BUILTIN_STVXL_V2DI
);
16980 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
16981 ALTIVEC_BUILTIN_STVXL_V4SF
);
16982 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
16983 ALTIVEC_BUILTIN_STVXL_V4SI
);
16984 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
16985 ALTIVEC_BUILTIN_STVXL_V8HI
);
16986 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
16987 ALTIVEC_BUILTIN_STVXL_V16QI
);
16988 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
16989 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
16990 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
16991 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
16992 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
16993 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
16994 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
16995 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
16996 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
16997 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
16998 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
16999 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
17000 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
17001 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
17002 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
17003 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
17005 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
17006 VSX_BUILTIN_LXVD2X_V2DF
);
17007 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
17008 VSX_BUILTIN_LXVD2X_V2DI
);
17009 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
17010 VSX_BUILTIN_LXVW4X_V4SF
);
17011 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
17012 VSX_BUILTIN_LXVW4X_V4SI
);
17013 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
17014 VSX_BUILTIN_LXVW4X_V8HI
);
17015 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
17016 VSX_BUILTIN_LXVW4X_V16QI
);
17017 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
17018 VSX_BUILTIN_STXVD2X_V2DF
);
17019 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
17020 VSX_BUILTIN_STXVD2X_V2DI
);
17021 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
17022 VSX_BUILTIN_STXVW4X_V4SF
);
17023 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
17024 VSX_BUILTIN_STXVW4X_V4SI
);
17025 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
17026 VSX_BUILTIN_STXVW4X_V8HI
);
17027 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
17028 VSX_BUILTIN_STXVW4X_V16QI
);
17030 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid
,
17031 VSX_BUILTIN_LD_ELEMREV_V2DF
);
17032 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid
,
17033 VSX_BUILTIN_LD_ELEMREV_V2DI
);
17034 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid
,
17035 VSX_BUILTIN_LD_ELEMREV_V4SF
);
17036 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid
,
17037 VSX_BUILTIN_LD_ELEMREV_V4SI
);
17038 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid
,
17039 VSX_BUILTIN_LD_ELEMREV_V8HI
);
17040 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid
,
17041 VSX_BUILTIN_LD_ELEMREV_V16QI
);
17042 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid
,
17043 VSX_BUILTIN_ST_ELEMREV_V2DF
);
17044 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid
,
17045 VSX_BUILTIN_ST_ELEMREV_V1TI
);
17046 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid
,
17047 VSX_BUILTIN_ST_ELEMREV_V2DI
);
17048 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid
,
17049 VSX_BUILTIN_ST_ELEMREV_V4SF
);
17050 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid
,
17051 VSX_BUILTIN_ST_ELEMREV_V4SI
);
17052 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid
,
17053 VSX_BUILTIN_ST_ELEMREV_V8HI
);
17054 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid
,
17055 VSX_BUILTIN_ST_ELEMREV_V16QI
);
17057 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
17058 VSX_BUILTIN_VEC_LD
);
17059 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
17060 VSX_BUILTIN_VEC_ST
);
17061 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid
,
17062 VSX_BUILTIN_VEC_XL
);
17063 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid
,
17064 VSX_BUILTIN_VEC_XL_BE
);
17065 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid
,
17066 VSX_BUILTIN_VEC_XST
);
17067 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid
,
17068 VSX_BUILTIN_VEC_XST_BE
);
17070 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
17071 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
17072 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
17074 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
17075 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
17076 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
17077 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
17078 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
17079 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
17080 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
17081 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
17082 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
17083 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
17084 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
17085 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
17087 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque
,
17088 ALTIVEC_BUILTIN_VEC_ADDE
);
17089 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque
,
17090 ALTIVEC_BUILTIN_VEC_ADDEC
);
17091 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque
,
17092 ALTIVEC_BUILTIN_VEC_CMPNE
);
17093 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque
,
17094 ALTIVEC_BUILTIN_VEC_MUL
);
17095 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque
,
17096 ALTIVEC_BUILTIN_VEC_SUBE
);
17097 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque
,
17098 ALTIVEC_BUILTIN_VEC_SUBEC
);
17100 /* Cell builtins. */
17101 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
17102 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
17103 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
17104 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
17106 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
17107 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
17108 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
17109 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
17111 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
17112 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
17113 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
17114 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
17116 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
17117 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
17118 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
17119 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
17121 if (TARGET_P9_VECTOR
)
17123 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long
,
17124 P9V_BUILTIN_STXVL
);
17125 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long
,
17126 P9V_BUILTIN_XST_LEN_R
);
17129 /* Add the DST variants. */
17131 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
17133 HOST_WIDE_INT mask
= d
->mask
;
17135 /* It is expected that these dst built-in functions may have
17136 d->icode equal to CODE_FOR_nothing. */
17137 if ((mask
& builtin_mask
) != mask
)
17139 if (TARGET_DEBUG_BUILTIN
)
17140 fprintf (stderr
, "altivec_init_builtins, skip dst %s\n",
17144 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
17147 /* Initialize the predicates. */
17148 d
= bdesc_altivec_preds
;
17149 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
17151 machine_mode mode1
;
17153 HOST_WIDE_INT mask
= d
->mask
;
17155 if ((mask
& builtin_mask
) != mask
)
17157 if (TARGET_DEBUG_BUILTIN
)
17158 fprintf (stderr
, "altivec_init_builtins, skip predicate %s\n",
17163 if (rs6000_overloaded_builtin_p (d
->code
))
17167 /* Cannot define builtin if the instruction is disabled. */
17168 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17169 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
17175 type
= int_ftype_int_opaque_opaque
;
17178 type
= int_ftype_int_v2di_v2di
;
17181 type
= int_ftype_int_v4si_v4si
;
17184 type
= int_ftype_int_v8hi_v8hi
;
17187 type
= int_ftype_int_v16qi_v16qi
;
17190 type
= int_ftype_int_v4sf_v4sf
;
17193 type
= int_ftype_int_v2df_v2df
;
17196 gcc_unreachable ();
17199 def_builtin (d
->name
, type
, d
->code
);
17202 /* Initialize the abs* operators. */
17204 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
17206 machine_mode mode0
;
17208 HOST_WIDE_INT mask
= d
->mask
;
17210 if ((mask
& builtin_mask
) != mask
)
17212 if (TARGET_DEBUG_BUILTIN
)
17213 fprintf (stderr
, "altivec_init_builtins, skip abs %s\n",
17218 /* Cannot define builtin if the instruction is disabled. */
17219 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17220 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
17225 type
= v2di_ftype_v2di
;
17228 type
= v4si_ftype_v4si
;
17231 type
= v8hi_ftype_v8hi
;
17234 type
= v16qi_ftype_v16qi
;
17237 type
= v4sf_ftype_v4sf
;
17240 type
= v2df_ftype_v2df
;
17243 gcc_unreachable ();
17246 def_builtin (d
->name
, type
, d
->code
);
17249 /* Initialize target builtin that implements
17250 targetm.vectorize.builtin_mask_for_load. */
17252 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
17253 v16qi_ftype_long_pcvoid
,
17254 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
17255 BUILT_IN_MD
, NULL
, NULL_TREE
);
17256 TREE_READONLY (decl
) = 1;
17257 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17258 altivec_builtin_mask_for_load
= decl
;
17260 /* Access to the vec_init patterns. */
17261 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
17262 integer_type_node
, integer_type_node
,
17263 integer_type_node
, NULL_TREE
);
17264 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
17266 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
17267 short_integer_type_node
,
17268 short_integer_type_node
,
17269 short_integer_type_node
,
17270 short_integer_type_node
,
17271 short_integer_type_node
,
17272 short_integer_type_node
,
17273 short_integer_type_node
, NULL_TREE
);
17274 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
17276 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
17277 char_type_node
, char_type_node
,
17278 char_type_node
, char_type_node
,
17279 char_type_node
, char_type_node
,
17280 char_type_node
, char_type_node
,
17281 char_type_node
, char_type_node
,
17282 char_type_node
, char_type_node
,
17283 char_type_node
, char_type_node
,
17284 char_type_node
, NULL_TREE
);
17285 def_builtin ("__builtin_vec_init_v16qi", ftype
,
17286 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
17288 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
17289 float_type_node
, float_type_node
,
17290 float_type_node
, NULL_TREE
);
17291 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
17293 /* VSX builtins. */
17294 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
17295 double_type_node
, NULL_TREE
);
17296 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
17298 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
17299 intDI_type_node
, NULL_TREE
);
17300 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
17302 /* Access to the vec_set patterns. */
17303 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
17305 integer_type_node
, NULL_TREE
);
17306 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
17308 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
17310 integer_type_node
, NULL_TREE
);
17311 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
17313 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
17315 integer_type_node
, NULL_TREE
);
17316 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
17318 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
17320 integer_type_node
, NULL_TREE
);
17321 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
17323 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
17325 integer_type_node
, NULL_TREE
);
17326 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
17328 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
17330 integer_type_node
, NULL_TREE
);
17331 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
17333 /* Access to the vec_extract patterns. */
17334 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
17335 integer_type_node
, NULL_TREE
);
17336 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
17338 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
17339 integer_type_node
, NULL_TREE
);
17340 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
17342 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
17343 integer_type_node
, NULL_TREE
);
17344 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
17346 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
17347 integer_type_node
, NULL_TREE
);
17348 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
17350 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
17351 integer_type_node
, NULL_TREE
);
17352 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
17354 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
17355 integer_type_node
, NULL_TREE
);
17356 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
17359 if (V1TI_type_node
)
17361 tree v1ti_ftype_long_pcvoid
17362 = build_function_type_list (V1TI_type_node
,
17363 long_integer_type_node
, pcvoid_type_node
,
17365 tree void_ftype_v1ti_long_pvoid
17366 = build_function_type_list (void_type_node
,
17367 V1TI_type_node
, long_integer_type_node
,
17368 pvoid_type_node
, NULL_TREE
);
17369 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid
,
17370 VSX_BUILTIN_LD_ELEMREV_V1TI
);
17371 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
17372 VSX_BUILTIN_LXVD2X_V1TI
);
17373 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
17374 VSX_BUILTIN_STXVD2X_V1TI
);
17375 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
17376 NULL_TREE
, NULL_TREE
);
17377 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
17378 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
17380 integer_type_node
, NULL_TREE
);
17381 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
17382 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
17383 integer_type_node
, NULL_TREE
);
17384 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
17390 htm_init_builtins (void)
17392 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17393 const struct builtin_description
*d
;
17397 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
17399 tree op
[MAX_HTM_OPERANDS
], type
;
17400 HOST_WIDE_INT mask
= d
->mask
;
17401 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
17402 bool void_func
= (attr
& RS6000_BTC_VOID
);
17403 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
17405 tree gpr_type_node
;
17409 /* It is expected that these htm built-in functions may have
17410 d->icode equal to CODE_FOR_nothing. */
17412 if (TARGET_32BIT
&& TARGET_POWERPC64
)
17413 gpr_type_node
= long_long_unsigned_type_node
;
17415 gpr_type_node
= long_unsigned_type_node
;
17417 if (attr
& RS6000_BTC_SPR
)
17419 rettype
= gpr_type_node
;
17420 argtype
= gpr_type_node
;
17422 else if (d
->code
== HTM_BUILTIN_TABORTDC
17423 || d
->code
== HTM_BUILTIN_TABORTDCI
)
17425 rettype
= unsigned_type_node
;
17426 argtype
= gpr_type_node
;
17430 rettype
= unsigned_type_node
;
17431 argtype
= unsigned_type_node
;
17434 if ((mask
& builtin_mask
) != mask
)
17436 if (TARGET_DEBUG_BUILTIN
)
17437 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
17443 if (TARGET_DEBUG_BUILTIN
)
17444 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
17445 (long unsigned) i
);
17449 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
17451 if (attr_args
== RS6000_BTC_UNARY
)
17452 op
[nopnds
++] = argtype
;
17453 else if (attr_args
== RS6000_BTC_BINARY
)
17455 op
[nopnds
++] = argtype
;
17456 op
[nopnds
++] = argtype
;
17458 else if (attr_args
== RS6000_BTC_TERNARY
)
17460 op
[nopnds
++] = argtype
;
17461 op
[nopnds
++] = argtype
;
17462 op
[nopnds
++] = argtype
;
17468 type
= build_function_type_list (op
[0], NULL_TREE
);
17471 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
17474 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
17477 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
17481 gcc_unreachable ();
17484 def_builtin (d
->name
, type
, d
->code
);
17488 /* Hash function for builtin functions with up to 3 arguments and a return
17491 builtin_hasher::hash (builtin_hash_struct
*bh
)
17496 for (i
= 0; i
< 4; i
++)
17498 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
17499 ret
= (ret
* 2) + bh
->uns_p
[i
];
17505 /* Compare builtin hash entries H1 and H2 for equivalence. */
17507 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
17509 return ((p1
->mode
[0] == p2
->mode
[0])
17510 && (p1
->mode
[1] == p2
->mode
[1])
17511 && (p1
->mode
[2] == p2
->mode
[2])
17512 && (p1
->mode
[3] == p2
->mode
[3])
17513 && (p1
->uns_p
[0] == p2
->uns_p
[0])
17514 && (p1
->uns_p
[1] == p2
->uns_p
[1])
17515 && (p1
->uns_p
[2] == p2
->uns_p
[2])
17516 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
17519 /* Map types for builtin functions with an explicit return type and up to 3
17520 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17521 of the argument. */
17523 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
17524 machine_mode mode_arg1
, machine_mode mode_arg2
,
17525 enum rs6000_builtins builtin
, const char *name
)
17527 struct builtin_hash_struct h
;
17528 struct builtin_hash_struct
*h2
;
17531 tree ret_type
= NULL_TREE
;
17532 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
17534 /* Create builtin_hash_table. */
17535 if (builtin_hash_table
== NULL
)
17536 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
17538 h
.type
= NULL_TREE
;
17539 h
.mode
[0] = mode_ret
;
17540 h
.mode
[1] = mode_arg0
;
17541 h
.mode
[2] = mode_arg1
;
17542 h
.mode
[3] = mode_arg2
;
17548 /* If the builtin is a type that produces unsigned results or takes unsigned
17549 arguments, and it is returned as a decl for the vectorizer (such as
17550 widening multiplies, permute), make sure the arguments and return value
17551 are type correct. */
17554 /* unsigned 1 argument functions. */
17555 case CRYPTO_BUILTIN_VSBOX
:
17556 case P8V_BUILTIN_VGBBD
:
17557 case MISC_BUILTIN_CDTBCD
:
17558 case MISC_BUILTIN_CBCDTD
:
17563 /* unsigned 2 argument functions. */
17564 case ALTIVEC_BUILTIN_VMULEUB
:
17565 case ALTIVEC_BUILTIN_VMULEUH
:
17566 case P8V_BUILTIN_VMULEUW
:
17567 case ALTIVEC_BUILTIN_VMULOUB
:
17568 case ALTIVEC_BUILTIN_VMULOUH
:
17569 case P8V_BUILTIN_VMULOUW
:
17570 case CRYPTO_BUILTIN_VCIPHER
:
17571 case CRYPTO_BUILTIN_VCIPHERLAST
:
17572 case CRYPTO_BUILTIN_VNCIPHER
:
17573 case CRYPTO_BUILTIN_VNCIPHERLAST
:
17574 case CRYPTO_BUILTIN_VPMSUMB
:
17575 case CRYPTO_BUILTIN_VPMSUMH
:
17576 case CRYPTO_BUILTIN_VPMSUMW
:
17577 case CRYPTO_BUILTIN_VPMSUMD
:
17578 case CRYPTO_BUILTIN_VPMSUM
:
17579 case MISC_BUILTIN_ADDG6S
:
17580 case MISC_BUILTIN_DIVWEU
:
17581 case MISC_BUILTIN_DIVDEU
:
17582 case VSX_BUILTIN_UDIV_V2DI
:
17583 case ALTIVEC_BUILTIN_VMAXUB
:
17584 case ALTIVEC_BUILTIN_VMINUB
:
17585 case ALTIVEC_BUILTIN_VMAXUH
:
17586 case ALTIVEC_BUILTIN_VMINUH
:
17587 case ALTIVEC_BUILTIN_VMAXUW
:
17588 case ALTIVEC_BUILTIN_VMINUW
:
17589 case P8V_BUILTIN_VMAXUD
:
17590 case P8V_BUILTIN_VMINUD
:
17596 /* unsigned 3 argument functions. */
17597 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
17598 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
17599 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
17600 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
17601 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
17602 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
17603 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
17604 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
17605 case VSX_BUILTIN_VPERM_16QI_UNS
:
17606 case VSX_BUILTIN_VPERM_8HI_UNS
:
17607 case VSX_BUILTIN_VPERM_4SI_UNS
:
17608 case VSX_BUILTIN_VPERM_2DI_UNS
:
17609 case VSX_BUILTIN_XXSEL_16QI_UNS
:
17610 case VSX_BUILTIN_XXSEL_8HI_UNS
:
17611 case VSX_BUILTIN_XXSEL_4SI_UNS
:
17612 case VSX_BUILTIN_XXSEL_2DI_UNS
:
17613 case CRYPTO_BUILTIN_VPERMXOR
:
17614 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
17615 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
17616 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
17617 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
17618 case CRYPTO_BUILTIN_VSHASIGMAW
:
17619 case CRYPTO_BUILTIN_VSHASIGMAD
:
17620 case CRYPTO_BUILTIN_VSHASIGMA
:
17627 /* signed permute functions with unsigned char mask. */
17628 case ALTIVEC_BUILTIN_VPERM_16QI
:
17629 case ALTIVEC_BUILTIN_VPERM_8HI
:
17630 case ALTIVEC_BUILTIN_VPERM_4SI
:
17631 case ALTIVEC_BUILTIN_VPERM_4SF
:
17632 case ALTIVEC_BUILTIN_VPERM_2DI
:
17633 case ALTIVEC_BUILTIN_VPERM_2DF
:
17634 case VSX_BUILTIN_VPERM_16QI
:
17635 case VSX_BUILTIN_VPERM_8HI
:
17636 case VSX_BUILTIN_VPERM_4SI
:
17637 case VSX_BUILTIN_VPERM_4SF
:
17638 case VSX_BUILTIN_VPERM_2DI
:
17639 case VSX_BUILTIN_VPERM_2DF
:
17643 /* unsigned args, signed return. */
17644 case VSX_BUILTIN_XVCVUXDSP
:
17645 case VSX_BUILTIN_XVCVUXDDP_UNS
:
17646 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
17650 /* signed args, unsigned return. */
17651 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
17652 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
17653 case MISC_BUILTIN_UNPACK_TD
:
17654 case MISC_BUILTIN_UNPACK_V1TI
:
17658 /* unsigned arguments, bool return (compares). */
17659 case ALTIVEC_BUILTIN_VCMPEQUB
:
17660 case ALTIVEC_BUILTIN_VCMPEQUH
:
17661 case ALTIVEC_BUILTIN_VCMPEQUW
:
17662 case P8V_BUILTIN_VCMPEQUD
:
17663 case VSX_BUILTIN_CMPGE_U16QI
:
17664 case VSX_BUILTIN_CMPGE_U8HI
:
17665 case VSX_BUILTIN_CMPGE_U4SI
:
17666 case VSX_BUILTIN_CMPGE_U2DI
:
17667 case ALTIVEC_BUILTIN_VCMPGTUB
:
17668 case ALTIVEC_BUILTIN_VCMPGTUH
:
17669 case ALTIVEC_BUILTIN_VCMPGTUW
:
17670 case P8V_BUILTIN_VCMPGTUD
:
17675 /* unsigned arguments for 128-bit pack instructions. */
17676 case MISC_BUILTIN_PACK_TD
:
17677 case MISC_BUILTIN_PACK_V1TI
:
17682 /* unsigned second arguments (vector shift right). */
17683 case ALTIVEC_BUILTIN_VSRB
:
17684 case ALTIVEC_BUILTIN_VSRH
:
17685 case ALTIVEC_BUILTIN_VSRW
:
17686 case P8V_BUILTIN_VSRD
:
17694 /* Figure out how many args are present. */
17695 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
17698 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
17699 if (!ret_type
&& h
.uns_p
[0])
17700 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
17703 fatal_error (input_location
,
17704 "internal error: builtin function %qs had an unexpected "
17705 "return type %qs", name
, GET_MODE_NAME (h
.mode
[0]));
17707 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
17708 arg_type
[i
] = NULL_TREE
;
17710 for (i
= 0; i
< num_args
; i
++)
17712 int m
= (int) h
.mode
[i
+1];
17713 int uns_p
= h
.uns_p
[i
+1];
17715 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
17716 if (!arg_type
[i
] && uns_p
)
17717 arg_type
[i
] = builtin_mode_to_type
[m
][0];
17720 fatal_error (input_location
,
17721 "internal error: builtin function %qs, argument %d "
17722 "had unexpected argument type %qs", name
, i
,
17723 GET_MODE_NAME (m
));
17726 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
17727 if (*found
== NULL
)
17729 h2
= ggc_alloc
<builtin_hash_struct
> ();
17733 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
17734 arg_type
[2], NULL_TREE
);
17737 return (*found
)->type
;
17741 rs6000_common_init_builtins (void)
17743 const struct builtin_description
*d
;
17746 tree opaque_ftype_opaque
= NULL_TREE
;
17747 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
17748 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
17749 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17751 /* Create Altivec and VSX builtins on machines with at least the
17752 general purpose extensions (970 and newer) to allow the use of
17753 the target attribute. */
17755 if (TARGET_EXTRA_BUILTINS
)
17756 builtin_mask
|= RS6000_BTM_COMMON
;
17758 /* Add the ternary operators. */
17760 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
17763 HOST_WIDE_INT mask
= d
->mask
;
17765 if ((mask
& builtin_mask
) != mask
)
17767 if (TARGET_DEBUG_BUILTIN
)
17768 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
17772 if (rs6000_overloaded_builtin_p (d
->code
))
17774 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
17775 type
= opaque_ftype_opaque_opaque_opaque
17776 = build_function_type_list (opaque_V4SI_type_node
,
17777 opaque_V4SI_type_node
,
17778 opaque_V4SI_type_node
,
17779 opaque_V4SI_type_node
,
17784 enum insn_code icode
= d
->icode
;
17787 if (TARGET_DEBUG_BUILTIN
)
17788 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17794 if (icode
== CODE_FOR_nothing
)
17796 if (TARGET_DEBUG_BUILTIN
)
17797 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
17803 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
17804 insn_data
[icode
].operand
[1].mode
,
17805 insn_data
[icode
].operand
[2].mode
,
17806 insn_data
[icode
].operand
[3].mode
,
17810 def_builtin (d
->name
, type
, d
->code
);
17813 /* Add the binary operators. */
17815 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
17817 machine_mode mode0
, mode1
, mode2
;
17819 HOST_WIDE_INT mask
= d
->mask
;
17821 if ((mask
& builtin_mask
) != mask
)
17823 if (TARGET_DEBUG_BUILTIN
)
17824 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
17828 if (rs6000_overloaded_builtin_p (d
->code
))
17830 if (! (type
= opaque_ftype_opaque_opaque
))
17831 type
= opaque_ftype_opaque_opaque
17832 = build_function_type_list (opaque_V4SI_type_node
,
17833 opaque_V4SI_type_node
,
17834 opaque_V4SI_type_node
,
17839 enum insn_code icode
= d
->icode
;
17842 if (TARGET_DEBUG_BUILTIN
)
17843 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17849 if (icode
== CODE_FOR_nothing
)
17851 if (TARGET_DEBUG_BUILTIN
)
17852 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
17858 mode0
= insn_data
[icode
].operand
[0].mode
;
17859 mode1
= insn_data
[icode
].operand
[1].mode
;
17860 mode2
= insn_data
[icode
].operand
[2].mode
;
17862 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
17866 def_builtin (d
->name
, type
, d
->code
);
17869 /* Add the simple unary operators. */
17871 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
17873 machine_mode mode0
, mode1
;
17875 HOST_WIDE_INT mask
= d
->mask
;
17877 if ((mask
& builtin_mask
) != mask
)
17879 if (TARGET_DEBUG_BUILTIN
)
17880 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
17884 if (rs6000_overloaded_builtin_p (d
->code
))
17886 if (! (type
= opaque_ftype_opaque
))
17887 type
= opaque_ftype_opaque
17888 = build_function_type_list (opaque_V4SI_type_node
,
17889 opaque_V4SI_type_node
,
17894 enum insn_code icode
= d
->icode
;
17897 if (TARGET_DEBUG_BUILTIN
)
17898 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17904 if (icode
== CODE_FOR_nothing
)
17906 if (TARGET_DEBUG_BUILTIN
)
17907 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
17913 mode0
= insn_data
[icode
].operand
[0].mode
;
17914 mode1
= insn_data
[icode
].operand
[1].mode
;
17916 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
17920 def_builtin (d
->name
, type
, d
->code
);
17923 /* Add the simple no-argument operators. */
17925 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
17927 machine_mode mode0
;
17929 HOST_WIDE_INT mask
= d
->mask
;
17931 if ((mask
& builtin_mask
) != mask
)
17933 if (TARGET_DEBUG_BUILTIN
)
17934 fprintf (stderr
, "rs6000_builtin, skip no-argument %s\n", d
->name
);
17937 if (rs6000_overloaded_builtin_p (d
->code
))
17939 if (!opaque_ftype_opaque
)
17940 opaque_ftype_opaque
17941 = build_function_type_list (opaque_V4SI_type_node
, NULL_TREE
);
17942 type
= opaque_ftype_opaque
;
17946 enum insn_code icode
= d
->icode
;
17949 if (TARGET_DEBUG_BUILTIN
)
17950 fprintf (stderr
, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17951 (long unsigned) i
);
17954 if (icode
== CODE_FOR_nothing
)
17956 if (TARGET_DEBUG_BUILTIN
)
17958 "rs6000_builtin, skip no-argument %s (no code)\n",
17962 mode0
= insn_data
[icode
].operand
[0].mode
;
17963 type
= builtin_function_type (mode0
, VOIDmode
, VOIDmode
, VOIDmode
,
17966 def_builtin (d
->name
, type
, d
->code
);
17970 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17972 init_float128_ibm (machine_mode mode
)
17974 if (!TARGET_XL_COMPAT
)
17976 set_optab_libfunc (add_optab
, mode
, "__gcc_qadd");
17977 set_optab_libfunc (sub_optab
, mode
, "__gcc_qsub");
17978 set_optab_libfunc (smul_optab
, mode
, "__gcc_qmul");
17979 set_optab_libfunc (sdiv_optab
, mode
, "__gcc_qdiv");
17981 if (!TARGET_HARD_FLOAT
)
17983 set_optab_libfunc (neg_optab
, mode
, "__gcc_qneg");
17984 set_optab_libfunc (eq_optab
, mode
, "__gcc_qeq");
17985 set_optab_libfunc (ne_optab
, mode
, "__gcc_qne");
17986 set_optab_libfunc (gt_optab
, mode
, "__gcc_qgt");
17987 set_optab_libfunc (ge_optab
, mode
, "__gcc_qge");
17988 set_optab_libfunc (lt_optab
, mode
, "__gcc_qlt");
17989 set_optab_libfunc (le_optab
, mode
, "__gcc_qle");
17990 set_optab_libfunc (unord_optab
, mode
, "__gcc_qunord");
17992 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__gcc_stoq");
17993 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__gcc_dtoq");
17994 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__gcc_qtos");
17995 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__gcc_qtod");
17996 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__gcc_qtoi");
17997 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__gcc_qtou");
17998 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__gcc_itoq");
17999 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__gcc_utoq");
18004 set_optab_libfunc (add_optab
, mode
, "_xlqadd");
18005 set_optab_libfunc (sub_optab
, mode
, "_xlqsub");
18006 set_optab_libfunc (smul_optab
, mode
, "_xlqmul");
18007 set_optab_libfunc (sdiv_optab
, mode
, "_xlqdiv");
18010 /* Add various conversions for IFmode to use the traditional TFmode
18012 if (mode
== IFmode
)
18014 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdtf");
18015 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddtf");
18016 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctdtf");
18017 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunctfsd");
18018 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunctfdd");
18019 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtftd");
18021 if (TARGET_POWERPC64
)
18023 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixtfti");
18024 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunstfti");
18025 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattitf");
18026 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntitf");
18031 /* Create a decl for either complex long double multiply or complex long double
18032 divide when long double is IEEE 128-bit floating point. We can't use
18033 __multc3 and __divtc3 because the original long double using IBM extended
18034 double used those names. The complex multiply/divide functions are encoded
18035 as builtin functions with a complex result and 4 scalar inputs. */
18038 create_complex_muldiv (const char *name
, built_in_function fncode
, tree fntype
)
18040 tree fndecl
= add_builtin_function (name
, fntype
, fncode
, BUILT_IN_NORMAL
,
18043 set_builtin_decl (fncode
, fndecl
, true);
18045 if (TARGET_DEBUG_BUILTIN
)
18046 fprintf (stderr
, "create complex %s, fncode: %d\n", name
, (int) fncode
);
18051 /* Set up IEEE 128-bit floating point routines. Use different names if the
18052 arguments can be passed in a vector register. The historical PowerPC
18053 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18054 continue to use that if we aren't using vector registers to pass IEEE
18055 128-bit floating point. */
18058 init_float128_ieee (machine_mode mode
)
18060 if (FLOAT128_VECTOR_P (mode
))
18062 static bool complex_muldiv_init_p
= false;
18064 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
18065 we have clone or target attributes, this will be called a second
18066 time. We want to create the built-in function only once. */
18067 if (mode
== TFmode
&& TARGET_IEEEQUAD
&& !complex_muldiv_init_p
)
18069 complex_muldiv_init_p
= true;
18070 built_in_function fncode_mul
=
18071 (built_in_function
) (BUILT_IN_COMPLEX_MUL_MIN
+ TCmode
18072 - MIN_MODE_COMPLEX_FLOAT
);
18073 built_in_function fncode_div
=
18074 (built_in_function
) (BUILT_IN_COMPLEX_DIV_MIN
+ TCmode
18075 - MIN_MODE_COMPLEX_FLOAT
);
18077 tree fntype
= build_function_type_list (complex_long_double_type_node
,
18078 long_double_type_node
,
18079 long_double_type_node
,
18080 long_double_type_node
,
18081 long_double_type_node
,
18084 create_complex_muldiv ("__mulkc3", fncode_mul
, fntype
);
18085 create_complex_muldiv ("__divkc3", fncode_div
, fntype
);
18088 set_optab_libfunc (add_optab
, mode
, "__addkf3");
18089 set_optab_libfunc (sub_optab
, mode
, "__subkf3");
18090 set_optab_libfunc (neg_optab
, mode
, "__negkf2");
18091 set_optab_libfunc (smul_optab
, mode
, "__mulkf3");
18092 set_optab_libfunc (sdiv_optab
, mode
, "__divkf3");
18093 set_optab_libfunc (sqrt_optab
, mode
, "__sqrtkf2");
18094 set_optab_libfunc (abs_optab
, mode
, "__abskf2");
18095 set_optab_libfunc (powi_optab
, mode
, "__powikf2");
18097 set_optab_libfunc (eq_optab
, mode
, "__eqkf2");
18098 set_optab_libfunc (ne_optab
, mode
, "__nekf2");
18099 set_optab_libfunc (gt_optab
, mode
, "__gtkf2");
18100 set_optab_libfunc (ge_optab
, mode
, "__gekf2");
18101 set_optab_libfunc (lt_optab
, mode
, "__ltkf2");
18102 set_optab_libfunc (le_optab
, mode
, "__lekf2");
18103 set_optab_libfunc (unord_optab
, mode
, "__unordkf2");
18105 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__extendsfkf2");
18106 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__extenddfkf2");
18107 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__trunckfsf2");
18108 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__trunckfdf2");
18110 set_conv_libfunc (sext_optab
, mode
, IFmode
, "__trunctfkf2");
18111 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18112 set_conv_libfunc (sext_optab
, mode
, TFmode
, "__trunctfkf2");
18114 set_conv_libfunc (trunc_optab
, IFmode
, mode
, "__extendkftf2");
18115 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18116 set_conv_libfunc (trunc_optab
, TFmode
, mode
, "__extendkftf2");
18118 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdkf");
18119 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddkf");
18120 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctdkf");
18121 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunckfsd");
18122 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunckfdd");
18123 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendkftd");
18125 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__fixkfsi");
18126 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__fixunskfsi");
18127 set_conv_libfunc (sfix_optab
, DImode
, mode
, "__fixkfdi");
18128 set_conv_libfunc (ufix_optab
, DImode
, mode
, "__fixunskfdi");
18130 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__floatsikf");
18131 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__floatunsikf");
18132 set_conv_libfunc (sfloat_optab
, mode
, DImode
, "__floatdikf");
18133 set_conv_libfunc (ufloat_optab
, mode
, DImode
, "__floatundikf");
18135 if (TARGET_POWERPC64
)
18137 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixkfti");
18138 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunskfti");
18139 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattikf");
18140 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntikf");
18146 set_optab_libfunc (add_optab
, mode
, "_q_add");
18147 set_optab_libfunc (sub_optab
, mode
, "_q_sub");
18148 set_optab_libfunc (neg_optab
, mode
, "_q_neg");
18149 set_optab_libfunc (smul_optab
, mode
, "_q_mul");
18150 set_optab_libfunc (sdiv_optab
, mode
, "_q_div");
18151 if (TARGET_PPC_GPOPT
)
18152 set_optab_libfunc (sqrt_optab
, mode
, "_q_sqrt");
18154 set_optab_libfunc (eq_optab
, mode
, "_q_feq");
18155 set_optab_libfunc (ne_optab
, mode
, "_q_fne");
18156 set_optab_libfunc (gt_optab
, mode
, "_q_fgt");
18157 set_optab_libfunc (ge_optab
, mode
, "_q_fge");
18158 set_optab_libfunc (lt_optab
, mode
, "_q_flt");
18159 set_optab_libfunc (le_optab
, mode
, "_q_fle");
18161 set_conv_libfunc (sext_optab
, mode
, SFmode
, "_q_stoq");
18162 set_conv_libfunc (sext_optab
, mode
, DFmode
, "_q_dtoq");
18163 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "_q_qtos");
18164 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "_q_qtod");
18165 set_conv_libfunc (sfix_optab
, SImode
, mode
, "_q_qtoi");
18166 set_conv_libfunc (ufix_optab
, SImode
, mode
, "_q_qtou");
18167 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "_q_itoq");
18168 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "_q_utoq");
18173 rs6000_init_libfuncs (void)
18175 /* __float128 support. */
18176 if (TARGET_FLOAT128_TYPE
)
18178 init_float128_ibm (IFmode
);
18179 init_float128_ieee (KFmode
);
18182 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18183 if (TARGET_LONG_DOUBLE_128
)
18185 if (!TARGET_IEEEQUAD
)
18186 init_float128_ibm (TFmode
);
18188 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18190 init_float128_ieee (TFmode
);
18194 /* Emit a potentially record-form instruction, setting DST from SRC.
18195 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18196 signed comparison of DST with zero. If DOT is 1, the generated RTL
18197 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18198 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18199 a separate COMPARE. */
18202 rs6000_emit_dot_insn (rtx dst
, rtx src
, int dot
, rtx ccreg
)
18206 emit_move_insn (dst
, src
);
18210 if (cc_reg_not_cr0_operand (ccreg
, CCmode
))
18212 emit_move_insn (dst
, src
);
18213 emit_move_insn (ccreg
, gen_rtx_COMPARE (CCmode
, dst
, const0_rtx
));
18217 rtx ccset
= gen_rtx_SET (ccreg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
));
18220 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, dst
);
18221 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, clobber
)));
18225 rtx set
= gen_rtx_SET (dst
, src
);
18226 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, set
)));
18231 /* A validation routine: say whether CODE, a condition code, and MODE
18232 match. The other alternatives either don't make sense or should
18233 never be generated. */
18236 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
18238 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
18239 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
18240 && GET_MODE_CLASS (mode
) == MODE_CC
);
18242 /* These don't make sense. */
18243 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
18244 || mode
!= CCUNSmode
);
18246 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
18247 || mode
== CCUNSmode
);
18249 gcc_assert (mode
== CCFPmode
18250 || (code
!= ORDERED
&& code
!= UNORDERED
18251 && code
!= UNEQ
&& code
!= LTGT
18252 && code
!= UNGT
&& code
!= UNLT
18253 && code
!= UNGE
&& code
!= UNLE
));
18255 /* These should never be generated except for
18256 flag_finite_math_only. */
18257 gcc_assert (mode
!= CCFPmode
18258 || flag_finite_math_only
18259 || (code
!= LE
&& code
!= GE
18260 && code
!= UNEQ
&& code
!= LTGT
18261 && code
!= UNGT
&& code
!= UNLT
));
18263 /* These are invalid; the information is not there. */
18264 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
18268 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18269 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18270 not zero, store there the bit offset (counted from the right) where
18271 the single stretch of 1 bits begins; and similarly for B, the bit
18272 offset where it ends. */
18275 rs6000_is_valid_mask (rtx mask
, int *b
, int *e
, machine_mode mode
)
18277 unsigned HOST_WIDE_INT val
= INTVAL (mask
);
18278 unsigned HOST_WIDE_INT bit
;
18280 int n
= GET_MODE_PRECISION (mode
);
18282 if (mode
!= DImode
&& mode
!= SImode
)
18285 if (INTVAL (mask
) >= 0)
18288 ne
= exact_log2 (bit
);
18289 nb
= exact_log2 (val
+ bit
);
18291 else if (val
+ 1 == 0)
18300 nb
= exact_log2 (bit
);
18301 ne
= exact_log2 (val
+ bit
);
18306 ne
= exact_log2 (bit
);
18307 if (val
+ bit
== 0)
18315 if (nb
< 0 || ne
< 0 || nb
>= n
|| ne
>= n
)
18326 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18327 or rldicr instruction, to implement an AND with it in mode MODE. */
18330 rs6000_is_valid_and_mask (rtx mask
, machine_mode mode
)
18334 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18337 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18339 if (mode
== DImode
)
18340 return (ne
== 0 || nb
== 63 || (nb
< 32 && ne
<= nb
));
18342 /* For SImode, rlwinm can do everything. */
18343 if (mode
== SImode
)
18344 return (nb
< 32 && ne
< 32);
18349 /* Return the instruction template for an AND with mask in mode MODE, with
18350 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18353 rs6000_insn_for_and_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18357 if (!rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
))
18358 gcc_unreachable ();
18360 if (mode
== DImode
&& ne
== 0)
18362 operands
[3] = GEN_INT (63 - nb
);
18364 return "rldicl. %0,%1,0,%3";
18365 return "rldicl %0,%1,0,%3";
18368 if (mode
== DImode
&& nb
== 63)
18370 operands
[3] = GEN_INT (63 - ne
);
18372 return "rldicr. %0,%1,0,%3";
18373 return "rldicr %0,%1,0,%3";
18376 if (nb
< 32 && ne
< 32)
18378 operands
[3] = GEN_INT (31 - nb
);
18379 operands
[4] = GEN_INT (31 - ne
);
18381 return "rlwinm. %0,%1,0,%3,%4";
18382 return "rlwinm %0,%1,0,%3,%4";
18385 gcc_unreachable ();
18388 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18389 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18390 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18393 rs6000_is_valid_shift_mask (rtx mask
, rtx shift
, machine_mode mode
)
18397 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18400 int n
= GET_MODE_PRECISION (mode
);
18403 if (CONST_INT_P (XEXP (shift
, 1)))
18405 sh
= INTVAL (XEXP (shift
, 1));
18406 if (sh
< 0 || sh
>= n
)
18410 rtx_code code
= GET_CODE (shift
);
18412 /* Convert any shift by 0 to a rotate, to simplify below code. */
18416 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18417 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18419 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18425 /* DImode rotates need rld*. */
18426 if (mode
== DImode
&& code
== ROTATE
)
18427 return (nb
== 63 || ne
== 0 || ne
== sh
);
18429 /* SImode rotates need rlw*. */
18430 if (mode
== SImode
&& code
== ROTATE
)
18431 return (nb
< 32 && ne
< 32 && sh
< 32);
18433 /* Wrap-around masks are only okay for rotates. */
18437 /* Variable shifts are only okay for rotates. */
18441 /* Don't allow ASHIFT if the mask is wrong for that. */
18442 if (code
== ASHIFT
&& ne
< sh
)
18445 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18446 if the mask is wrong for that. */
18447 if (nb
< 32 && ne
< 32 && sh
< 32
18448 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18451 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18452 if the mask is wrong for that. */
18453 if (code
== LSHIFTRT
)
18455 if (nb
== 63 || ne
== 0 || ne
== sh
)
18456 return !(code
== LSHIFTRT
&& nb
>= sh
);
18461 /* Return the instruction template for a shift with mask in mode MODE, with
18462 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18465 rs6000_insn_for_shift_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18469 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18470 gcc_unreachable ();
18472 if (mode
== DImode
&& ne
== 0)
18474 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18475 operands
[2] = GEN_INT (64 - INTVAL (operands
[2]));
18476 operands
[3] = GEN_INT (63 - nb
);
18478 return "rld%I2cl. %0,%1,%2,%3";
18479 return "rld%I2cl %0,%1,%2,%3";
18482 if (mode
== DImode
&& nb
== 63)
18484 operands
[3] = GEN_INT (63 - ne
);
18486 return "rld%I2cr. %0,%1,%2,%3";
18487 return "rld%I2cr %0,%1,%2,%3";
18491 && GET_CODE (operands
[4]) != LSHIFTRT
18492 && CONST_INT_P (operands
[2])
18493 && ne
== INTVAL (operands
[2]))
18495 operands
[3] = GEN_INT (63 - nb
);
18497 return "rld%I2c. %0,%1,%2,%3";
18498 return "rld%I2c %0,%1,%2,%3";
18501 if (nb
< 32 && ne
< 32)
18503 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18504 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
18505 operands
[3] = GEN_INT (31 - nb
);
18506 operands
[4] = GEN_INT (31 - ne
);
18507 /* This insn can also be a 64-bit rotate with mask that really makes
18508 it just a shift right (with mask); the %h below are to adjust for
18509 that situation (shift count is >= 32 in that case). */
18511 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18512 return "rlw%I2nm %0,%1,%h2,%3,%4";
18515 gcc_unreachable ();
18518 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18519 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18520 ASHIFT, or LSHIFTRT) in mode MODE. */
18523 rs6000_is_valid_insert_mask (rtx mask
, rtx shift
, machine_mode mode
)
18527 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18530 int n
= GET_MODE_PRECISION (mode
);
18532 int sh
= INTVAL (XEXP (shift
, 1));
18533 if (sh
< 0 || sh
>= n
)
18536 rtx_code code
= GET_CODE (shift
);
18538 /* Convert any shift by 0 to a rotate, to simplify below code. */
18542 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18543 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18545 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18551 /* DImode rotates need rldimi. */
18552 if (mode
== DImode
&& code
== ROTATE
)
18555 /* SImode rotates need rlwimi. */
18556 if (mode
== SImode
&& code
== ROTATE
)
18557 return (nb
< 32 && ne
< 32 && sh
< 32);
18559 /* Wrap-around masks are only okay for rotates. */
18563 /* Don't allow ASHIFT if the mask is wrong for that. */
18564 if (code
== ASHIFT
&& ne
< sh
)
18567 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18568 if the mask is wrong for that. */
18569 if (nb
< 32 && ne
< 32 && sh
< 32
18570 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18573 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18574 if the mask is wrong for that. */
18575 if (code
== LSHIFTRT
)
18578 return !(code
== LSHIFTRT
&& nb
>= sh
);
18583 /* Return the instruction template for an insert with mask in mode MODE, with
18584 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18587 rs6000_insn_for_insert_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18591 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18592 gcc_unreachable ();
18594 /* Prefer rldimi because rlwimi is cracked. */
18595 if (TARGET_POWERPC64
18596 && (!dot
|| mode
== DImode
)
18597 && GET_CODE (operands
[4]) != LSHIFTRT
18598 && ne
== INTVAL (operands
[2]))
18600 operands
[3] = GEN_INT (63 - nb
);
18602 return "rldimi. %0,%1,%2,%3";
18603 return "rldimi %0,%1,%2,%3";
18606 if (nb
< 32 && ne
< 32)
18608 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18609 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
18610 operands
[3] = GEN_INT (31 - nb
);
18611 operands
[4] = GEN_INT (31 - ne
);
18613 return "rlwimi. %0,%1,%2,%3,%4";
18614 return "rlwimi %0,%1,%2,%3,%4";
18617 gcc_unreachable ();
18620 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18621 using two machine instructions. */
18624 rs6000_is_valid_2insn_and (rtx c
, machine_mode mode
)
18626 /* There are two kinds of AND we can handle with two insns:
18627 1) those we can do with two rl* insn;
18630 We do not handle that last case yet. */
18632 /* If there is just one stretch of ones, we can do it. */
18633 if (rs6000_is_valid_mask (c
, NULL
, NULL
, mode
))
18636 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18637 one insn, we can do the whole thing with two. */
18638 unsigned HOST_WIDE_INT val
= INTVAL (c
);
18639 unsigned HOST_WIDE_INT bit1
= val
& -val
;
18640 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
18641 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
18642 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
18643 return rs6000_is_valid_and_mask (GEN_INT (val
+ bit3
- bit2
), mode
);
18646 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18647 If EXPAND is true, split rotate-and-mask instructions we generate to
18648 their constituent parts as well (this is used during expand); if DOT
18649 is 1, make the last insn a record-form instruction clobbering the
18650 destination GPR and setting the CC reg (from operands[3]); if 2, set
18651 that GPR as well as the CC reg. */
18654 rs6000_emit_2insn_and (machine_mode mode
, rtx
*operands
, bool expand
, int dot
)
18656 gcc_assert (!(expand
&& dot
));
18658 unsigned HOST_WIDE_INT val
= INTVAL (operands
[2]);
18660 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18661 shift right. This generates better code than doing the masks without
18662 shifts, or shifting first right and then left. */
18664 if (rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
) && nb
>= ne
)
18666 gcc_assert (mode
== DImode
);
18668 int shift
= 63 - nb
;
18671 rtx tmp1
= gen_reg_rtx (DImode
);
18672 rtx tmp2
= gen_reg_rtx (DImode
);
18673 emit_insn (gen_ashldi3 (tmp1
, operands
[1], GEN_INT (shift
)));
18674 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (val
<< shift
)));
18675 emit_insn (gen_lshrdi3 (operands
[0], tmp2
, GEN_INT (shift
)));
18679 rtx tmp
= gen_rtx_ASHIFT (mode
, operands
[1], GEN_INT (shift
));
18680 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (val
<< shift
));
18681 emit_move_insn (operands
[0], tmp
);
18682 tmp
= gen_rtx_LSHIFTRT (mode
, operands
[0], GEN_INT (shift
));
18683 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18688 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18689 that does the rest. */
18690 unsigned HOST_WIDE_INT bit1
= val
& -val
;
18691 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
18692 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
18693 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
18695 unsigned HOST_WIDE_INT mask1
= -bit3
+ bit2
- 1;
18696 unsigned HOST_WIDE_INT mask2
= val
+ bit3
- bit2
;
18698 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2
), mode
));
18700 /* Two "no-rotate"-and-mask instructions, for SImode. */
18701 if (rs6000_is_valid_and_mask (GEN_INT (mask1
), mode
))
18703 gcc_assert (mode
== SImode
);
18705 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
18706 rtx tmp
= gen_rtx_AND (mode
, operands
[1], GEN_INT (mask1
));
18707 emit_move_insn (reg
, tmp
);
18708 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
18709 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18713 gcc_assert (mode
== DImode
);
18715 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18716 insns; we have to do the first in SImode, because it wraps. */
18717 if (mask2
<= 0xffffffff
18718 && rs6000_is_valid_and_mask (GEN_INT (mask1
), SImode
))
18720 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
18721 rtx tmp
= gen_rtx_AND (SImode
, gen_lowpart (SImode
, operands
[1]),
18723 rtx reg_low
= gen_lowpart (SImode
, reg
);
18724 emit_move_insn (reg_low
, tmp
);
18725 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
18726 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18730 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18731 at the top end), rotate back and clear the other hole. */
18732 int right
= exact_log2 (bit3
);
18733 int left
= 64 - right
;
18735 /* Rotate the mask too. */
18736 mask1
= (mask1
>> right
) | ((bit2
- 1) << left
);
18740 rtx tmp1
= gen_reg_rtx (DImode
);
18741 rtx tmp2
= gen_reg_rtx (DImode
);
18742 rtx tmp3
= gen_reg_rtx (DImode
);
18743 emit_insn (gen_rotldi3 (tmp1
, operands
[1], GEN_INT (left
)));
18744 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (mask1
)));
18745 emit_insn (gen_rotldi3 (tmp3
, tmp2
, GEN_INT (right
)));
18746 emit_insn (gen_anddi3 (operands
[0], tmp3
, GEN_INT (mask2
)));
18750 rtx tmp
= gen_rtx_ROTATE (mode
, operands
[1], GEN_INT (left
));
18751 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask1
));
18752 emit_move_insn (operands
[0], tmp
);
18753 tmp
= gen_rtx_ROTATE (mode
, operands
[0], GEN_INT (right
));
18754 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask2
));
18755 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18759 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18760 for lfq and stfq insns iff the registers are hard registers. */
18763 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
18765 /* We might have been passed a SUBREG. */
18766 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
18769 /* We might have been passed non floating point registers. */
18770 if (!FP_REGNO_P (REGNO (reg1
))
18771 || !FP_REGNO_P (REGNO (reg2
)))
18774 return (REGNO (reg1
) == REGNO (reg2
) - 1);
18777 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18778 addr1 and addr2 must be in consecutive memory locations
18779 (addr2 == addr1 + 8). */
18782 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
18785 unsigned int reg1
, reg2
;
18786 int offset1
, offset2
;
18788 /* The mems cannot be volatile. */
18789 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
18792 addr1
= XEXP (mem1
, 0);
18793 addr2
= XEXP (mem2
, 0);
18795 /* Extract an offset (if used) from the first addr. */
18796 if (GET_CODE (addr1
) == PLUS
)
18798 /* If not a REG, return zero. */
18799 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
18803 reg1
= REGNO (XEXP (addr1
, 0));
18804 /* The offset must be constant! */
18805 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
18807 offset1
= INTVAL (XEXP (addr1
, 1));
18810 else if (GET_CODE (addr1
) != REG
)
18814 reg1
= REGNO (addr1
);
18815 /* This was a simple (mem (reg)) expression. Offset is 0. */
18819 /* And now for the second addr. */
18820 if (GET_CODE (addr2
) == PLUS
)
18822 /* If not a REG, return zero. */
18823 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
18827 reg2
= REGNO (XEXP (addr2
, 0));
18828 /* The offset must be constant. */
18829 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
18831 offset2
= INTVAL (XEXP (addr2
, 1));
18834 else if (GET_CODE (addr2
) != REG
)
18838 reg2
= REGNO (addr2
);
18839 /* This was a simple (mem (reg)) expression. Offset is 0. */
18843 /* Both of these must have the same base register. */
18847 /* The offset for the second addr must be 8 more than the first addr. */
18848 if (offset2
!= offset1
+ 8)
18851 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18856 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18857 need to use DDmode, in all other cases we can use the same mode. */
18858 static machine_mode
18859 rs6000_secondary_memory_needed_mode (machine_mode mode
)
18861 if (lra_in_progress
&& mode
== SDmode
)
18866 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18867 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18868 only work on the traditional altivec registers, note if an altivec register
18871 static enum rs6000_reg_type
18872 register_to_reg_type (rtx reg
, bool *is_altivec
)
18874 HOST_WIDE_INT regno
;
18875 enum reg_class rclass
;
18877 if (GET_CODE (reg
) == SUBREG
)
18878 reg
= SUBREG_REG (reg
);
18881 return NO_REG_TYPE
;
18883 regno
= REGNO (reg
);
18884 if (regno
>= FIRST_PSEUDO_REGISTER
)
18886 if (!lra_in_progress
&& !reload_completed
)
18887 return PSEUDO_REG_TYPE
;
18889 regno
= true_regnum (reg
);
18890 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
18891 return PSEUDO_REG_TYPE
;
18894 gcc_assert (regno
>= 0);
18896 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
18897 *is_altivec
= true;
18899 rclass
= rs6000_regno_regclass
[regno
];
18900 return reg_class_to_reg_type
[(int)rclass
];
18903 /* Helper function to return the cost of adding a TOC entry address. */
18906 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
18910 if (TARGET_CMODEL
!= CMODEL_SMALL
)
18911 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
18914 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
18919 /* Helper function for rs6000_secondary_reload to determine whether the memory
18920 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18921 needs reloading. Return negative if the memory is not handled by the memory
18922 helper functions and to try a different reload method, 0 if no additional
18923 instructions are need, and positive to give the extra cost for the
18927 rs6000_secondary_reload_memory (rtx addr
,
18928 enum reg_class rclass
,
18931 int extra_cost
= 0;
18932 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
18933 addr_mask_type addr_mask
;
18934 const char *type
= NULL
;
18935 const char *fail_msg
= NULL
;
18937 if (GPR_REG_CLASS_P (rclass
))
18938 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
18940 else if (rclass
== FLOAT_REGS
)
18941 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
18943 else if (rclass
== ALTIVEC_REGS
)
18944 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
18946 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18947 else if (rclass
== VSX_REGS
)
18948 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
18949 & ~RELOAD_REG_AND_M16
);
18951 /* If the register allocator hasn't made up its mind yet on the register
18952 class to use, settle on defaults to use. */
18953 else if (rclass
== NO_REGS
)
18955 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
]
18956 & ~RELOAD_REG_AND_M16
);
18958 if ((addr_mask
& RELOAD_REG_MULTIPLE
) != 0)
18959 addr_mask
&= ~(RELOAD_REG_INDEXED
18960 | RELOAD_REG_PRE_INCDEC
18961 | RELOAD_REG_PRE_MODIFY
);
18967 /* If the register isn't valid in this register class, just return now. */
18968 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
18970 if (TARGET_DEBUG_ADDR
)
18973 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18974 "not valid in class\n",
18975 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
18982 switch (GET_CODE (addr
))
18984 /* Does the register class supports auto update forms for this mode? We
18985 don't need a scratch register, since the powerpc only supports
18986 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18989 reg
= XEXP (addr
, 0);
18990 if (!base_reg_operand (addr
, GET_MODE (reg
)))
18992 fail_msg
= "no base register #1";
18996 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
19004 reg
= XEXP (addr
, 0);
19005 plus_arg1
= XEXP (addr
, 1);
19006 if (!base_reg_operand (reg
, GET_MODE (reg
))
19007 || GET_CODE (plus_arg1
) != PLUS
19008 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
19010 fail_msg
= "bad PRE_MODIFY";
19014 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
19021 /* Do we need to simulate AND -16 to clear the bottom address bits used
19022 in VMX load/stores? Only allow the AND for vector sizes. */
19024 and_arg
= XEXP (addr
, 0);
19025 if (GET_MODE_SIZE (mode
) != 16
19026 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
19027 || INTVAL (XEXP (addr
, 1)) != -16)
19029 fail_msg
= "bad Altivec AND #1";
19033 if (rclass
!= ALTIVEC_REGS
)
19035 if (legitimate_indirect_address_p (and_arg
, false))
19038 else if (legitimate_indexed_address_p (and_arg
, false))
19043 fail_msg
= "bad Altivec AND #2";
19051 /* If this is an indirect address, make sure it is a base register. */
19054 if (!legitimate_indirect_address_p (addr
, false))
19061 /* If this is an indexed address, make sure the register class can handle
19062 indexed addresses for this mode. */
19064 plus_arg0
= XEXP (addr
, 0);
19065 plus_arg1
= XEXP (addr
, 1);
19067 /* (plus (plus (reg) (constant)) (constant)) is generated during
19068 push_reload processing, so handle it now. */
19069 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
19071 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19078 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19079 push_reload processing, so handle it now. */
19080 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
19082 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19085 type
= "indexed #2";
19089 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
19091 fail_msg
= "no base register #2";
19095 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
19097 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
19098 || !legitimate_indexed_address_p (addr
, false))
19105 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0
19106 && CONST_INT_P (plus_arg1
))
19108 if (!quad_address_offset_p (INTVAL (plus_arg1
)))
19111 type
= "vector d-form offset";
19115 /* Make sure the register class can handle offset addresses. */
19116 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
19118 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19121 type
= "offset #2";
19127 fail_msg
= "bad PLUS";
19134 /* Quad offsets are restricted and can't handle normal addresses. */
19135 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19138 type
= "vector d-form lo_sum";
19141 else if (!legitimate_lo_sum_address_p (mode
, addr
, false))
19143 fail_msg
= "bad LO_SUM";
19147 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19154 /* Static addresses need to create a TOC entry. */
19158 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19161 type
= "vector d-form lo_sum #2";
19167 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
19171 /* TOC references look like offsetable memory. */
19173 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
19175 fail_msg
= "bad UNSPEC";
19179 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19182 type
= "vector d-form lo_sum #3";
19185 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19188 type
= "toc reference";
19194 fail_msg
= "bad address";
19199 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
19201 if (extra_cost
< 0)
19203 "rs6000_secondary_reload_memory error: mode = %s, "
19204 "class = %s, addr_mask = '%s', %s\n",
19205 GET_MODE_NAME (mode
),
19206 reg_class_names
[rclass
],
19207 rs6000_debug_addr_mask (addr_mask
, false),
19208 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
19212 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19213 "addr_mask = '%s', extra cost = %d, %s\n",
19214 GET_MODE_NAME (mode
),
19215 reg_class_names
[rclass
],
19216 rs6000_debug_addr_mask (addr_mask
, false),
19218 (type
) ? type
: "<none>");
19226 /* Helper function for rs6000_secondary_reload to return true if a move to a
19227 different register classe is really a simple move. */
19230 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
19231 enum rs6000_reg_type from_type
,
19234 int size
= GET_MODE_SIZE (mode
);
19236 /* Add support for various direct moves available. In this function, we only
19237 look at cases where we don't need any extra registers, and one or more
19238 simple move insns are issued. Originally small integers are not allowed
19239 in FPR/VSX registers. Single precision binary floating is not a simple
19240 move because we need to convert to the single precision memory layout.
19241 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19242 need special direct move handling, which we do not support yet. */
19243 if (TARGET_DIRECT_MOVE
19244 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19245 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19247 if (TARGET_POWERPC64
)
19249 /* ISA 2.07: MTVSRD or MVFVSRD. */
19253 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19254 if (size
== 16 && TARGET_P9_VECTOR
&& mode
!= TDmode
)
19258 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19259 if (TARGET_P8_VECTOR
)
19261 if (mode
== SImode
)
19264 if (TARGET_P9_VECTOR
&& (mode
== HImode
|| mode
== QImode
))
19268 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19269 if (mode
== SDmode
)
19273 /* Power6+: MFTGPR or MFFGPR. */
19274 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
19275 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
19276 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19279 /* Move to/from SPR. */
19280 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
19281 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
19282 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19288 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19289 special direct moves that involve allocating an extra register, return the
19290 insn code of the helper function if there is such a function or
19291 CODE_FOR_nothing if not. */
19294 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
19295 enum rs6000_reg_type from_type
,
19297 secondary_reload_info
*sri
,
19301 enum insn_code icode
= CODE_FOR_nothing
;
19303 int size
= GET_MODE_SIZE (mode
);
19305 if (TARGET_POWERPC64
&& size
== 16)
19307 /* Handle moving 128-bit values from GPRs to VSX point registers on
19308 ISA 2.07 (power8, power9) when running in 64-bit mode using
19309 XXPERMDI to glue the two 64-bit values back together. */
19310 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19312 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
19313 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19316 /* Handle moving 128-bit values from VSX point registers to GPRs on
19317 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19318 bottom 64-bit value. */
19319 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19321 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
19322 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19326 else if (TARGET_POWERPC64
&& mode
== SFmode
)
19328 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19330 cost
= 3; /* xscvdpspn, mfvsrd, and. */
19331 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19334 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19336 cost
= 2; /* mtvsrz, xscvspdpn. */
19337 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19341 else if (!TARGET_POWERPC64
&& size
== 8)
19343 /* Handle moving 64-bit values from GPRs to floating point registers on
19344 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19345 32-bit values back together. Altivec register classes must be handled
19346 specially since a different instruction is used, and the secondary
19347 reload support requires a single instruction class in the scratch
19348 register constraint. However, right now TFmode is not allowed in
19349 Altivec registers, so the pattern will never match. */
19350 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
19352 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
19353 icode
= reg_addr
[mode
].reload_fpr_gpr
;
19357 if (icode
!= CODE_FOR_nothing
)
19362 sri
->icode
= icode
;
19363 sri
->extra_cost
= cost
;
19370 /* Return whether a move between two register classes can be done either
19371 directly (simple move) or via a pattern that uses a single extra temporary
19372 (using ISA 2.07's direct move in this case. */
19375 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
19376 enum rs6000_reg_type from_type
,
19378 secondary_reload_info
*sri
,
19381 /* Fall back to load/store reloads if either type is not a register. */
19382 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
19385 /* If we haven't allocated registers yet, assume the move can be done for the
19386 standard register types. */
19387 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
19388 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
19389 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
19392 /* Moves to the same set of registers is a simple move for non-specialized
19394 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
19397 /* Check whether a simple move can be done directly. */
19398 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
19402 sri
->icode
= CODE_FOR_nothing
;
19403 sri
->extra_cost
= 0;
19408 /* Now check if we can do it in a few steps. */
19409 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
19413 /* Inform reload about cases where moving X with a mode MODE to a register in
19414 RCLASS requires an extra scratch or immediate register. Return the class
19415 needed for the immediate register.
19417 For VSX and Altivec, we may need a register to convert sp+offset into
19420 For misaligned 64-bit gpr loads and stores we need a register to
19421 convert an offset address to indirect. */
19424 rs6000_secondary_reload (bool in_p
,
19426 reg_class_t rclass_i
,
19428 secondary_reload_info
*sri
)
19430 enum reg_class rclass
= (enum reg_class
) rclass_i
;
19431 reg_class_t ret
= ALL_REGS
;
19432 enum insn_code icode
;
19433 bool default_p
= false;
19434 bool done_p
= false;
19436 /* Allow subreg of memory before/during reload. */
19437 bool memory_p
= (MEM_P (x
)
19438 || (!reload_completed
&& GET_CODE (x
) == SUBREG
19439 && MEM_P (SUBREG_REG (x
))));
19441 sri
->icode
= CODE_FOR_nothing
;
19442 sri
->t_icode
= CODE_FOR_nothing
;
19443 sri
->extra_cost
= 0;
19445 ? reg_addr
[mode
].reload_load
19446 : reg_addr
[mode
].reload_store
);
19448 if (REG_P (x
) || register_operand (x
, mode
))
19450 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
19451 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
19452 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
19455 std::swap (to_type
, from_type
);
19457 /* Can we do a direct move of some sort? */
19458 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
19461 icode
= (enum insn_code
)sri
->icode
;
19468 /* Make sure 0.0 is not reloaded or forced into memory. */
19469 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
19476 /* If this is a scalar floating point value and we want to load it into the
19477 traditional Altivec registers, do it via a move via a traditional floating
19478 point register, unless we have D-form addressing. Also make sure that
19479 non-zero constants use a FPR. */
19480 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
19481 && !mode_supports_vmx_dform (mode
)
19482 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
19483 && (memory_p
|| (GET_CODE (x
) == CONST_DOUBLE
)))
19490 /* Handle reload of load/stores if we have reload helper functions. */
19491 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
19493 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
19496 if (extra_cost
>= 0)
19500 if (extra_cost
> 0)
19502 sri
->extra_cost
= extra_cost
;
19503 sri
->icode
= icode
;
19508 /* Handle unaligned loads and stores of integer registers. */
19509 if (!done_p
&& TARGET_POWERPC64
19510 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19512 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
19514 rtx addr
= XEXP (x
, 0);
19515 rtx off
= address_offset (addr
);
19517 if (off
!= NULL_RTX
)
19519 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19520 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19522 /* We need a secondary reload when our legitimate_address_p
19523 says the address is good (as otherwise the entire address
19524 will be reloaded), and the offset is not a multiple of
19525 four or we have an address wrap. Address wrap will only
19526 occur for LO_SUMs since legitimate_offset_address_p
19527 rejects addresses for 16-byte mems that will wrap. */
19528 if (GET_CODE (addr
) == LO_SUM
19529 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19530 && ((offset
& 3) != 0
19531 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
19532 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
19533 && (offset
& 3) != 0))
19535 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19537 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
19538 : CODE_FOR_reload_di_load
);
19540 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
19541 : CODE_FOR_reload_di_store
);
19542 sri
->extra_cost
= 2;
19553 if (!done_p
&& !TARGET_POWERPC64
19554 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19556 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
19558 rtx addr
= XEXP (x
, 0);
19559 rtx off
= address_offset (addr
);
19561 if (off
!= NULL_RTX
)
19563 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19564 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19566 /* We need a secondary reload when our legitimate_address_p
19567 says the address is good (as otherwise the entire address
19568 will be reloaded), and we have a wrap.
19570 legitimate_lo_sum_address_p allows LO_SUM addresses to
19571 have any offset so test for wrap in the low 16 bits.
19573 legitimate_offset_address_p checks for the range
19574 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19575 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19576 [0x7ff4,0x7fff] respectively, so test for the
19577 intersection of these ranges, [0x7ffc,0x7fff] and
19578 [0x7ff4,0x7ff7] respectively.
19580 Note that the address we see here may have been
19581 manipulated by legitimize_reload_address. */
19582 if (GET_CODE (addr
) == LO_SUM
19583 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
19584 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
19587 sri
->icode
= CODE_FOR_reload_si_load
;
19589 sri
->icode
= CODE_FOR_reload_si_store
;
19590 sri
->extra_cost
= 2;
19605 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
19607 gcc_assert (ret
!= ALL_REGS
);
19609 if (TARGET_DEBUG_ADDR
)
19612 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19614 reg_class_names
[ret
],
19615 in_p
? "true" : "false",
19616 reg_class_names
[rclass
],
19617 GET_MODE_NAME (mode
));
19619 if (reload_completed
)
19620 fputs (", after reload", stderr
);
19623 fputs (", done_p not set", stderr
);
19626 fputs (", default secondary reload", stderr
);
19628 if (sri
->icode
!= CODE_FOR_nothing
)
19629 fprintf (stderr
, ", reload func = %s, extra cost = %d",
19630 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
19632 else if (sri
->extra_cost
> 0)
19633 fprintf (stderr
, ", extra cost = %d", sri
->extra_cost
);
19635 fputs ("\n", stderr
);
19642 /* Better tracing for rs6000_secondary_reload_inner. */
19645 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
19650 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
19652 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
19653 store_p
? "store" : "load");
19656 set
= gen_rtx_SET (mem
, reg
);
19658 set
= gen_rtx_SET (reg
, mem
);
19660 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
19661 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
19664 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
19665 ATTRIBUTE_NORETURN
;
19668 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
19671 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
19672 gcc_unreachable ();
19675 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19676 reload helper functions. These were identified in
19677 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19678 reload, it calls the insns:
19679 reload_<RELOAD:mode>_<P:mptrsize>_store
19680 reload_<RELOAD:mode>_<P:mptrsize>_load
19682 which in turn calls this function, to do whatever is necessary to create
19683 valid addresses. */
19686 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
19688 int regno
= true_regnum (reg
);
19689 machine_mode mode
= GET_MODE (reg
);
19690 addr_mask_type addr_mask
;
19693 rtx op_reg
, op0
, op1
;
19698 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
|| !MEM_P (mem
)
19699 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
19700 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19702 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
19703 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
19705 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
19706 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
19708 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
19709 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
19712 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19714 /* Make sure the mode is valid in this register class. */
19715 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
19716 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19718 if (TARGET_DEBUG_ADDR
)
19719 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
19721 new_addr
= addr
= XEXP (mem
, 0);
19722 switch (GET_CODE (addr
))
19724 /* Does the register class support auto update forms for this mode? If
19725 not, do the update now. We don't need a scratch register, since the
19726 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19729 op_reg
= XEXP (addr
, 0);
19730 if (!base_reg_operand (op_reg
, Pmode
))
19731 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19733 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
19735 int delta
= GET_MODE_SIZE (mode
);
19736 if (GET_CODE (addr
) == PRE_DEC
)
19738 emit_insn (gen_add2_insn (op_reg
, GEN_INT (delta
)));
19744 op0
= XEXP (addr
, 0);
19745 op1
= XEXP (addr
, 1);
19746 if (!base_reg_operand (op0
, Pmode
)
19747 || GET_CODE (op1
) != PLUS
19748 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
19749 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19751 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
19753 emit_insn (gen_rtx_SET (op0
, op1
));
19758 /* Do we need to simulate AND -16 to clear the bottom address bits used
19759 in VMX load/stores? */
19761 op0
= XEXP (addr
, 0);
19762 op1
= XEXP (addr
, 1);
19763 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
19765 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
19768 else if (GET_CODE (op1
) == PLUS
)
19770 emit_insn (gen_rtx_SET (scratch
, op1
));
19775 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19777 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
19778 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
19779 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
19780 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
19781 new_addr
= scratch
;
19785 /* If this is an indirect address, make sure it is a base register. */
19788 if (!base_reg_operand (addr
, GET_MODE (addr
)))
19790 emit_insn (gen_rtx_SET (scratch
, addr
));
19791 new_addr
= scratch
;
19795 /* If this is an indexed address, make sure the register class can handle
19796 indexed addresses for this mode. */
19798 op0
= XEXP (addr
, 0);
19799 op1
= XEXP (addr
, 1);
19800 if (!base_reg_operand (op0
, Pmode
))
19801 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19803 else if (int_reg_operand (op1
, Pmode
))
19805 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19807 emit_insn (gen_rtx_SET (scratch
, addr
));
19808 new_addr
= scratch
;
19812 else if (mode_supports_dq_form (mode
) && CONST_INT_P (op1
))
19814 if (((addr_mask
& RELOAD_REG_QUAD_OFFSET
) == 0)
19815 || !quad_address_p (addr
, mode
, false))
19817 emit_insn (gen_rtx_SET (scratch
, addr
));
19818 new_addr
= scratch
;
19822 /* Make sure the register class can handle offset addresses. */
19823 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
19825 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19827 emit_insn (gen_rtx_SET (scratch
, addr
));
19828 new_addr
= scratch
;
19833 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19838 op0
= XEXP (addr
, 0);
19839 op1
= XEXP (addr
, 1);
19840 if (!base_reg_operand (op0
, Pmode
))
19841 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19843 else if (int_reg_operand (op1
, Pmode
))
19845 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19847 emit_insn (gen_rtx_SET (scratch
, addr
));
19848 new_addr
= scratch
;
19852 /* Quad offsets are restricted and can't handle normal addresses. */
19853 else if (mode_supports_dq_form (mode
))
19855 emit_insn (gen_rtx_SET (scratch
, addr
));
19856 new_addr
= scratch
;
19859 /* Make sure the register class can handle offset addresses. */
19860 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
19862 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19864 emit_insn (gen_rtx_SET (scratch
, addr
));
19865 new_addr
= scratch
;
19870 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19877 rs6000_emit_move (scratch
, addr
, Pmode
);
19878 new_addr
= scratch
;
19882 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19885 /* Adjust the address if it changed. */
19886 if (addr
!= new_addr
)
19888 mem
= replace_equiv_address_nv (mem
, new_addr
);
19889 if (TARGET_DEBUG_ADDR
)
19890 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19893 /* Now create the move. */
19895 emit_insn (gen_rtx_SET (mem
, reg
));
19897 emit_insn (gen_rtx_SET (reg
, mem
));
19902 /* Convert reloads involving 64-bit gprs and misaligned offset
19903 addressing, or multiple 32-bit gprs and offsets that are too large,
19904 to use indirect addressing. */
19907 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
19909 int regno
= true_regnum (reg
);
19910 enum reg_class rclass
;
19912 rtx scratch_or_premodify
= scratch
;
19914 if (TARGET_DEBUG_ADDR
)
19916 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
19917 store_p
? "store" : "load");
19918 fprintf (stderr
, "reg:\n");
19920 fprintf (stderr
, "mem:\n");
19922 fprintf (stderr
, "scratch:\n");
19923 debug_rtx (scratch
);
19926 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
19927 gcc_assert (GET_CODE (mem
) == MEM
);
19928 rclass
= REGNO_REG_CLASS (regno
);
19929 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
19930 addr
= XEXP (mem
, 0);
19932 if (GET_CODE (addr
) == PRE_MODIFY
)
19934 gcc_assert (REG_P (XEXP (addr
, 0))
19935 && GET_CODE (XEXP (addr
, 1)) == PLUS
19936 && XEXP (XEXP (addr
, 1), 0) == XEXP (addr
, 0));
19937 scratch_or_premodify
= XEXP (addr
, 0);
19938 addr
= XEXP (addr
, 1);
19940 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
19942 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
19944 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
19946 /* Now create the move. */
19948 emit_insn (gen_rtx_SET (mem
, reg
));
19950 emit_insn (gen_rtx_SET (reg
, mem
));
19955 /* Given an rtx X being reloaded into a reg required to be
19956 in class CLASS, return the class of reg to actually use.
19957 In general this is just CLASS; but on some machines
19958 in some cases it is preferable to use a more restrictive class.
19960 On the RS/6000, we have to return NO_REGS when we want to reload a
19961 floating-point CONST_DOUBLE to force it to be copied to memory.
19963 We also don't want to reload integer values into floating-point
19964 registers if we can at all help it. In fact, this can
19965 cause reload to die, if it tries to generate a reload of CTR
19966 into a FP register and discovers it doesn't have the memory location
19969 ??? Would it be a good idea to have reload do the converse, that is
19970 try to reload floating modes into FP registers if possible?
19973 static enum reg_class
19974 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
19976 machine_mode mode
= GET_MODE (x
);
19977 bool is_constant
= CONSTANT_P (x
);
19979 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19980 reload class for it. */
19981 if ((rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
19982 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
) == 0)
19985 if ((rclass
== FLOAT_REGS
|| rclass
== VSX_REGS
)
19986 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
] & RELOAD_REG_VALID
) == 0)
19989 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19990 the reloading of address expressions using PLUS into floating point
19992 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
19996 /* Zero is always allowed in all VSX registers. */
19997 if (x
== CONST0_RTX (mode
))
20000 /* If this is a vector constant that can be formed with a few Altivec
20001 instructions, we want altivec registers. */
20002 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
20003 return ALTIVEC_REGS
;
20005 /* If this is an integer constant that can easily be loaded into
20006 vector registers, allow it. */
20007 if (CONST_INT_P (x
))
20009 HOST_WIDE_INT value
= INTVAL (x
);
20011 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20012 2.06 can generate it in the Altivec registers with
20016 if (TARGET_P8_VECTOR
)
20018 else if (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
20019 return ALTIVEC_REGS
;
20024 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20025 a sign extend in the Altivec registers. */
20026 if (IN_RANGE (value
, -128, 127) && TARGET_P9_VECTOR
20027 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
))
20028 return ALTIVEC_REGS
;
20031 /* Force constant to memory. */
20035 /* D-form addressing can easily reload the value. */
20036 if (mode_supports_vmx_dform (mode
)
20037 || mode_supports_dq_form (mode
))
20040 /* If this is a scalar floating point value and we don't have D-form
20041 addressing, prefer the traditional floating point registers so that we
20042 can use D-form (register+offset) addressing. */
20043 if (rclass
== VSX_REGS
20044 && (mode
== SFmode
|| GET_MODE_SIZE (mode
) == 8))
20047 /* Prefer the Altivec registers if Altivec is handling the vector
20048 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20050 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
20051 || mode
== V1TImode
)
20052 return ALTIVEC_REGS
;
20057 if (is_constant
|| GET_CODE (x
) == PLUS
)
20059 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
20060 return GENERAL_REGS
;
20061 if (reg_class_subset_p (BASE_REGS
, rclass
))
20066 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
20067 return GENERAL_REGS
;
20072 /* Debug version of rs6000_preferred_reload_class. */
20073 static enum reg_class
20074 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
20076 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
20079 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20081 reg_class_names
[ret
], reg_class_names
[rclass
],
20082 GET_MODE_NAME (GET_MODE (x
)));
20088 /* If we are copying between FP or AltiVec registers and anything else, we need
20089 a memory location. The exception is when we are targeting ppc64 and the
20090 move to/from fpr to gpr instructions are available. Also, under VSX, you
20091 can copy vector registers from the FP register set to the Altivec register
20092 set and vice versa. */
20095 rs6000_secondary_memory_needed (machine_mode mode
,
20096 reg_class_t from_class
,
20097 reg_class_t to_class
)
20099 enum rs6000_reg_type from_type
, to_type
;
20100 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
20101 || (to_class
== ALTIVEC_REGS
));
20103 /* If a simple/direct move is available, we don't need secondary memory */
20104 from_type
= reg_class_to_reg_type
[(int)from_class
];
20105 to_type
= reg_class_to_reg_type
[(int)to_class
];
20107 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
20108 (secondary_reload_info
*)0, altivec_p
))
20111 /* If we have a floating point or vector register class, we need to use
20112 memory to transfer the data. */
20113 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
20119 /* Debug version of rs6000_secondary_memory_needed. */
20121 rs6000_debug_secondary_memory_needed (machine_mode mode
,
20122 reg_class_t from_class
,
20123 reg_class_t to_class
)
20125 bool ret
= rs6000_secondary_memory_needed (mode
, from_class
, to_class
);
20128 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20129 "to_class = %s, mode = %s\n",
20130 ret
? "true" : "false",
20131 reg_class_names
[from_class
],
20132 reg_class_names
[to_class
],
20133 GET_MODE_NAME (mode
));
20138 /* Return the register class of a scratch register needed to copy IN into
20139 or out of a register in RCLASS in MODE. If it can be done directly,
20140 NO_REGS is returned. */
20142 static enum reg_class
20143 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
20148 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
20150 && MACHOPIC_INDIRECT
20154 /* We cannot copy a symbolic operand directly into anything
20155 other than BASE_REGS for TARGET_ELF. So indicate that a
20156 register from BASE_REGS is needed as an intermediate
20159 On Darwin, pic addresses require a load from memory, which
20160 needs a base register. */
20161 if (rclass
!= BASE_REGS
20162 && (GET_CODE (in
) == SYMBOL_REF
20163 || GET_CODE (in
) == HIGH
20164 || GET_CODE (in
) == LABEL_REF
20165 || GET_CODE (in
) == CONST
))
20169 if (GET_CODE (in
) == REG
)
20171 regno
= REGNO (in
);
20172 if (regno
>= FIRST_PSEUDO_REGISTER
)
20174 regno
= true_regnum (in
);
20175 if (regno
>= FIRST_PSEUDO_REGISTER
)
20179 else if (GET_CODE (in
) == SUBREG
)
20181 regno
= true_regnum (in
);
20182 if (regno
>= FIRST_PSEUDO_REGISTER
)
20188 /* If we have VSX register moves, prefer moving scalar values between
20189 Altivec registers and GPR by going via an FPR (and then via memory)
20190 instead of reloading the secondary memory address for Altivec moves. */
20192 && GET_MODE_SIZE (mode
) < 16
20193 && !mode_supports_vmx_dform (mode
)
20194 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
20195 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
20196 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
20197 && (regno
>= 0 && INT_REGNO_P (regno
)))))
20200 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20202 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
20203 || (regno
>= 0 && INT_REGNO_P (regno
)))
20206 /* Constants, memory, and VSX registers can go into VSX registers (both the
20207 traditional floating point and the altivec registers). */
20208 if (rclass
== VSX_REGS
20209 && (regno
== -1 || VSX_REGNO_P (regno
)))
20212 /* Constants, memory, and FP registers can go into FP registers. */
20213 if ((regno
== -1 || FP_REGNO_P (regno
))
20214 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
20215 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
20217 /* Memory, and AltiVec registers can go into AltiVec registers. */
20218 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
20219 && rclass
== ALTIVEC_REGS
)
20222 /* We can copy among the CR registers. */
20223 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
20224 && regno
>= 0 && CR_REGNO_P (regno
))
20227 /* Otherwise, we need GENERAL_REGS. */
20228 return GENERAL_REGS
;
20231 /* Debug version of rs6000_secondary_reload_class. */
20232 static enum reg_class
20233 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
20234 machine_mode mode
, rtx in
)
20236 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
20238 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20239 "mode = %s, input rtx:\n",
20240 reg_class_names
[ret
], reg_class_names
[rclass
],
20241 GET_MODE_NAME (mode
));
20247 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20250 rs6000_can_change_mode_class (machine_mode from
,
20252 reg_class_t rclass
)
20254 unsigned from_size
= GET_MODE_SIZE (from
);
20255 unsigned to_size
= GET_MODE_SIZE (to
);
20257 if (from_size
!= to_size
)
20259 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
20261 if (reg_classes_intersect_p (xclass
, rclass
))
20263 unsigned to_nregs
= hard_regno_nregs (FIRST_FPR_REGNO
, to
);
20264 unsigned from_nregs
= hard_regno_nregs (FIRST_FPR_REGNO
, from
);
20265 bool to_float128_vector_p
= FLOAT128_VECTOR_P (to
);
20266 bool from_float128_vector_p
= FLOAT128_VECTOR_P (from
);
20268 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20269 single register under VSX because the scalar part of the register
20270 is in the upper 64-bits, and not the lower 64-bits. Types like
20271 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20272 IEEE floating point can't overlap, and neither can small
20275 if (to_float128_vector_p
&& from_float128_vector_p
)
20278 else if (to_float128_vector_p
|| from_float128_vector_p
)
20281 /* TDmode in floating-mode registers must always go into a register
20282 pair with the most significant word in the even-numbered register
20283 to match ISA requirements. In little-endian mode, this does not
20284 match subreg numbering, so we cannot allow subregs. */
20285 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
20288 if (from_size
< 8 || to_size
< 8)
20291 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
20294 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
20303 /* Since the VSX register set includes traditional floating point registers
20304 and altivec registers, just check for the size being different instead of
20305 trying to check whether the modes are vector modes. Otherwise it won't
20306 allow say DF and DI to change classes. For types like TFmode and TDmode
20307 that take 2 64-bit registers, rather than a single 128-bit register, don't
20308 allow subregs of those types to other 128 bit types. */
20309 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
20311 unsigned num_regs
= (from_size
+ 15) / 16;
20312 if (hard_regno_nregs (FIRST_FPR_REGNO
, to
) > num_regs
20313 || hard_regno_nregs (FIRST_FPR_REGNO
, from
) > num_regs
)
20316 return (from_size
== 8 || from_size
== 16);
20319 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
20320 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
20326 /* Debug version of rs6000_can_change_mode_class. */
20328 rs6000_debug_can_change_mode_class (machine_mode from
,
20330 reg_class_t rclass
)
20332 bool ret
= rs6000_can_change_mode_class (from
, to
, rclass
);
20335 "rs6000_can_change_mode_class, return %s, from = %s, "
20336 "to = %s, rclass = %s\n",
20337 ret
? "true" : "false",
20338 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
20339 reg_class_names
[rclass
]);
20344 /* Return a string to do a move operation of 128 bits of data. */
20347 rs6000_output_move_128bit (rtx operands
[])
20349 rtx dest
= operands
[0];
20350 rtx src
= operands
[1];
20351 machine_mode mode
= GET_MODE (dest
);
20354 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
20355 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
20359 dest_regno
= REGNO (dest
);
20360 dest_gpr_p
= INT_REGNO_P (dest_regno
);
20361 dest_fp_p
= FP_REGNO_P (dest_regno
);
20362 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
20363 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
20368 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
20373 src_regno
= REGNO (src
);
20374 src_gpr_p
= INT_REGNO_P (src_regno
);
20375 src_fp_p
= FP_REGNO_P (src_regno
);
20376 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
20377 src_vsx_p
= src_fp_p
| src_vmx_p
;
20382 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
20385 /* Register moves. */
20386 if (dest_regno
>= 0 && src_regno
>= 0)
20393 if (TARGET_DIRECT_MOVE_128
&& src_vsx_p
)
20394 return (WORDS_BIG_ENDIAN
20395 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20396 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20398 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
20402 else if (TARGET_VSX
&& dest_vsx_p
)
20405 return "xxlor %x0,%x1,%x1";
20407 else if (TARGET_DIRECT_MOVE_128
&& src_gpr_p
)
20408 return (WORDS_BIG_ENDIAN
20409 ? "mtvsrdd %x0,%1,%L1"
20410 : "mtvsrdd %x0,%L1,%1");
20412 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
20416 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
20417 return "vor %0,%1,%1";
20419 else if (dest_fp_p
&& src_fp_p
)
20424 else if (dest_regno
>= 0 && MEM_P (src
))
20428 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20434 else if (TARGET_ALTIVEC
&& dest_vmx_p
20435 && altivec_indexed_or_indirect_operand (src
, mode
))
20436 return "lvx %0,%y1";
20438 else if (TARGET_VSX
&& dest_vsx_p
)
20440 if (mode_supports_dq_form (mode
)
20441 && quad_address_p (XEXP (src
, 0), mode
, true))
20442 return "lxv %x0,%1";
20444 else if (TARGET_P9_VECTOR
)
20445 return "lxvx %x0,%y1";
20447 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20448 return "lxvw4x %x0,%y1";
20451 return "lxvd2x %x0,%y1";
20454 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
20455 return "lvx %0,%y1";
20457 else if (dest_fp_p
)
20462 else if (src_regno
>= 0 && MEM_P (dest
))
20466 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20467 return "stq %1,%0";
20472 else if (TARGET_ALTIVEC
&& src_vmx_p
20473 && altivec_indexed_or_indirect_operand (dest
, mode
))
20474 return "stvx %1,%y0";
20476 else if (TARGET_VSX
&& src_vsx_p
)
20478 if (mode_supports_dq_form (mode
)
20479 && quad_address_p (XEXP (dest
, 0), mode
, true))
20480 return "stxv %x1,%0";
20482 else if (TARGET_P9_VECTOR
)
20483 return "stxvx %x1,%y0";
20485 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20486 return "stxvw4x %x1,%y0";
20489 return "stxvd2x %x1,%y0";
20492 else if (TARGET_ALTIVEC
&& src_vmx_p
)
20493 return "stvx %1,%y0";
20500 else if (dest_regno
>= 0
20501 && (GET_CODE (src
) == CONST_INT
20502 || GET_CODE (src
) == CONST_WIDE_INT
20503 || GET_CODE (src
) == CONST_DOUBLE
20504 || GET_CODE (src
) == CONST_VECTOR
))
20509 else if ((dest_vmx_p
&& TARGET_ALTIVEC
)
20510 || (dest_vsx_p
&& TARGET_VSX
))
20511 return output_vec_const_move (operands
);
20514 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest
, src
));
20517 /* Validate a 128-bit move. */
20519 rs6000_move_128bit_ok_p (rtx operands
[])
20521 machine_mode mode
= GET_MODE (operands
[0]);
20522 return (gpc_reg_operand (operands
[0], mode
)
20523 || gpc_reg_operand (operands
[1], mode
));
20526 /* Return true if a 128-bit move needs to be split. */
20528 rs6000_split_128bit_ok_p (rtx operands
[])
20530 if (!reload_completed
)
20533 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
20536 if (quad_load_store_p (operands
[0], operands
[1]))
20543 /* Given a comparison operation, return the bit number in CCR to test. We
20544 know this is a valid comparison.
20546 SCC_P is 1 if this is for an scc. That means that %D will have been
20547 used instead of %C, so the bits will be in different places.
20549 Return -1 if OP isn't a valid comparison for some reason. */
20552 ccr_bit (rtx op
, int scc_p
)
20554 enum rtx_code code
= GET_CODE (op
);
20555 machine_mode cc_mode
;
20560 if (!COMPARISON_P (op
))
20563 reg
= XEXP (op
, 0);
20565 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
20567 cc_mode
= GET_MODE (reg
);
20568 cc_regnum
= REGNO (reg
);
20569 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
20571 validate_condition_mode (code
, cc_mode
);
20573 /* When generating a sCOND operation, only positive conditions are
20576 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
20577 || code
== GTU
|| code
== LTU
);
20582 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
20584 return base_bit
+ 2;
20585 case GT
: case GTU
: case UNLE
:
20586 return base_bit
+ 1;
20587 case LT
: case LTU
: case UNGE
:
20589 case ORDERED
: case UNORDERED
:
20590 return base_bit
+ 3;
20593 /* If scc, we will have done a cror to put the bit in the
20594 unordered position. So test that bit. For integer, this is ! LT
20595 unless this is an scc insn. */
20596 return scc_p
? base_bit
+ 3 : base_bit
;
20599 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
20602 gcc_unreachable ();
20606 /* Return the GOT register. */
20609 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
20611 /* The second flow pass currently (June 1999) can't update
20612 regs_ever_live without disturbing other parts of the compiler, so
20613 update it here to make the prolog/epilogue code happy. */
20614 if (!can_create_pseudo_p ()
20615 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
20616 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
20618 crtl
->uses_pic_offset_table
= 1;
20620 return pic_offset_table_rtx
;
20623 static rs6000_stack_t stack_info
;
20625 /* Function to init struct machine_function.
20626 This will be called, via a pointer variable,
20627 from push_function_context. */
20629 static struct machine_function
*
20630 rs6000_init_machine_status (void)
20632 stack_info
.reload_completed
= 0;
20633 return ggc_cleared_alloc
<machine_function
> ();
20636 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
20638 /* Write out a function code label. */
20641 rs6000_output_function_entry (FILE *file
, const char *fname
)
20643 if (fname
[0] != '.')
20645 switch (DEFAULT_ABI
)
20648 gcc_unreachable ();
20654 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
20664 RS6000_OUTPUT_BASENAME (file
, fname
);
20667 /* Print an operand. Recognize special options, documented below. */
20670 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20671 only introduced by the linker, when applying the sda21
20673 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20674 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20676 #define SMALL_DATA_RELOC "sda21"
20677 #define SMALL_DATA_REG 0
20681 print_operand (FILE *file
, rtx x
, int code
)
20684 unsigned HOST_WIDE_INT uval
;
20688 /* %a is output_address. */
20690 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20694 /* Like 'J' but get to the GT bit only. */
20697 output_operand_lossage ("invalid %%D value");
20701 /* Bit 1 is GT bit. */
20702 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
20704 /* Add one for shift count in rlinm for scc. */
20705 fprintf (file
, "%d", i
+ 1);
20709 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20712 output_operand_lossage ("invalid %%e value");
20717 if ((uval
& 0xffff) == 0 && uval
!= 0)
20722 /* X is a CR register. Print the number of the EQ bit of the CR */
20723 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20724 output_operand_lossage ("invalid %%E value");
20726 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
20730 /* X is a CR register. Print the shift count needed to move it
20731 to the high-order four bits. */
20732 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20733 output_operand_lossage ("invalid %%f value");
20735 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
20739 /* Similar, but print the count for the rotate in the opposite
20741 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20742 output_operand_lossage ("invalid %%F value");
20744 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
20748 /* X is a constant integer. If it is negative, print "m",
20749 otherwise print "z". This is to make an aze or ame insn. */
20750 if (GET_CODE (x
) != CONST_INT
)
20751 output_operand_lossage ("invalid %%G value");
20752 else if (INTVAL (x
) >= 0)
20759 /* If constant, output low-order five bits. Otherwise, write
20762 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
20764 print_operand (file
, x
, 0);
20768 /* If constant, output low-order six bits. Otherwise, write
20771 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
20773 print_operand (file
, x
, 0);
20777 /* Print `i' if this is a constant, else nothing. */
20783 /* Write the bit number in CCR for jump. */
20784 i
= ccr_bit (x
, 0);
20786 output_operand_lossage ("invalid %%j code");
20788 fprintf (file
, "%d", i
);
20792 /* Similar, but add one for shift count in rlinm for scc and pass
20793 scc flag to `ccr_bit'. */
20794 i
= ccr_bit (x
, 1);
20796 output_operand_lossage ("invalid %%J code");
20798 /* If we want bit 31, write a shift count of zero, not 32. */
20799 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
20803 /* X must be a constant. Write the 1's complement of the
20806 output_operand_lossage ("invalid %%k value");
20808 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
20812 /* X must be a symbolic constant on ELF. Write an
20813 expression suitable for an 'addi' that adds in the low 16
20814 bits of the MEM. */
20815 if (GET_CODE (x
) == CONST
)
20817 if (GET_CODE (XEXP (x
, 0)) != PLUS
20818 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
20819 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
20820 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
20821 output_operand_lossage ("invalid %%K value");
20823 print_operand_address (file
, x
);
20824 fputs ("@l", file
);
20827 /* %l is output_asm_label. */
20830 /* Write second word of DImode or DFmode reference. Works on register
20831 or non-indexed memory only. */
20833 fputs (reg_names
[REGNO (x
) + 1], file
);
20834 else if (MEM_P (x
))
20836 machine_mode mode
= GET_MODE (x
);
20837 /* Handle possible auto-increment. Since it is pre-increment and
20838 we have already done it, we can just use an offset of word. */
20839 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
20840 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
20841 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
20843 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
20844 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
20847 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
,
20851 if (small_data_operand (x
, GET_MODE (x
)))
20852 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
20853 reg_names
[SMALL_DATA_REG
]);
20857 case 'N': /* Unused */
20858 /* Write the number of elements in the vector times 4. */
20859 if (GET_CODE (x
) != PARALLEL
)
20860 output_operand_lossage ("invalid %%N value");
20862 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
20865 case 'O': /* Unused */
20866 /* Similar, but subtract 1 first. */
20867 if (GET_CODE (x
) != PARALLEL
)
20868 output_operand_lossage ("invalid %%O value");
20870 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
20874 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20877 || (i
= exact_log2 (INTVAL (x
))) < 0)
20878 output_operand_lossage ("invalid %%p value");
20880 fprintf (file
, "%d", i
);
20884 /* The operand must be an indirect memory reference. The result
20885 is the register name. */
20886 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
20887 || REGNO (XEXP (x
, 0)) >= 32)
20888 output_operand_lossage ("invalid %%P value");
20890 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
20894 /* This outputs the logical code corresponding to a boolean
20895 expression. The expression may have one or both operands
20896 negated (if one, only the first one). For condition register
20897 logical operations, it will also treat the negated
20898 CR codes as NOTs, but not handle NOTs of them. */
20900 const char *const *t
= 0;
20902 enum rtx_code code
= GET_CODE (x
);
20903 static const char * const tbl
[3][3] = {
20904 { "and", "andc", "nor" },
20905 { "or", "orc", "nand" },
20906 { "xor", "eqv", "xor" } };
20910 else if (code
== IOR
)
20912 else if (code
== XOR
)
20915 output_operand_lossage ("invalid %%q value");
20917 if (GET_CODE (XEXP (x
, 0)) != NOT
)
20921 if (GET_CODE (XEXP (x
, 1)) == NOT
)
20932 if (! TARGET_MFCRF
)
20938 /* X is a CR register. Print the mask for `mtcrf'. */
20939 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20940 output_operand_lossage ("invalid %%R value");
20942 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
20946 /* Low 5 bits of 32 - value */
20948 output_operand_lossage ("invalid %%s value");
20950 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
20954 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20955 if (!REG_P (x
) || GET_MODE (x
) != CCmode
)
20957 output_operand_lossage ("invalid %%t value");
20961 /* Bit 3 is OV bit. */
20962 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
20964 /* If we want bit 31, write a shift count of zero, not 32. */
20965 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
20969 /* Print the symbolic name of a branch target register. */
20970 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PLTSEQ
)
20971 x
= XVECEXP (x
, 0, 0);
20972 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
20973 && REGNO (x
) != CTR_REGNO
))
20974 output_operand_lossage ("invalid %%T value");
20975 else if (REGNO (x
) == LR_REGNO
)
20976 fputs ("lr", file
);
20978 fputs ("ctr", file
);
20982 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20983 for use in unsigned operand. */
20986 output_operand_lossage ("invalid %%u value");
20991 if ((uval
& 0xffff) == 0)
20994 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
20998 /* High-order 16 bits of constant for use in signed operand. */
21000 output_operand_lossage ("invalid %%v value");
21002 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
21003 (INTVAL (x
) >> 16) & 0xffff);
21007 /* Print `u' if this has an auto-increment or auto-decrement. */
21009 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
21010 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
21011 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
21016 /* Print the trap code for this operand. */
21017 switch (GET_CODE (x
))
21020 fputs ("eq", file
); /* 4 */
21023 fputs ("ne", file
); /* 24 */
21026 fputs ("lt", file
); /* 16 */
21029 fputs ("le", file
); /* 20 */
21032 fputs ("gt", file
); /* 8 */
21035 fputs ("ge", file
); /* 12 */
21038 fputs ("llt", file
); /* 2 */
21041 fputs ("lle", file
); /* 6 */
21044 fputs ("lgt", file
); /* 1 */
21047 fputs ("lge", file
); /* 5 */
21050 output_operand_lossage ("invalid %%V value");
21055 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21058 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
21059 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
21061 print_operand (file
, x
, 0);
21065 /* X is a FPR or Altivec register used in a VSX context. */
21066 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
21067 output_operand_lossage ("invalid %%x value");
21070 int reg
= REGNO (x
);
21071 int vsx_reg
= (FP_REGNO_P (reg
)
21073 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
21075 #ifdef TARGET_REGNAMES
21076 if (TARGET_REGNAMES
)
21077 fprintf (file
, "%%vs%d", vsx_reg
);
21080 fprintf (file
, "%d", vsx_reg
);
21086 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
21087 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
21088 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
21093 /* Like 'L', for third word of TImode/PTImode */
21095 fputs (reg_names
[REGNO (x
) + 2], file
);
21096 else if (MEM_P (x
))
21098 machine_mode mode
= GET_MODE (x
);
21099 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21100 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21101 output_address (mode
, plus_constant (Pmode
,
21102 XEXP (XEXP (x
, 0), 0), 8));
21103 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21104 output_address (mode
, plus_constant (Pmode
,
21105 XEXP (XEXP (x
, 0), 0), 8));
21107 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 8), 0));
21108 if (small_data_operand (x
, GET_MODE (x
)))
21109 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21110 reg_names
[SMALL_DATA_REG
]);
21115 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PLTSEQ
)
21116 x
= XVECEXP (x
, 0, 1);
21117 /* X is a SYMBOL_REF. Write out the name preceded by a
21118 period and without any trailing data in brackets. Used for function
21119 names. If we are configured for System V (or the embedded ABI) on
21120 the PowerPC, do not emit the period, since those systems do not use
21121 TOCs and the like. */
21122 if (!SYMBOL_REF_P (x
))
21124 output_operand_lossage ("invalid %%z value");
21128 /* For macho, check to see if we need a stub. */
21131 const char *name
= XSTR (x
, 0);
21133 if (darwin_emit_branch_islands
21134 && MACHOPIC_INDIRECT
21135 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
21136 name
= machopic_indirection_name (x
, /*stub_p=*/true);
21138 assemble_name (file
, name
);
21140 else if (!DOT_SYMBOLS
)
21141 assemble_name (file
, XSTR (x
, 0));
21143 rs6000_output_function_entry (file
, XSTR (x
, 0));
21147 /* Like 'L', for last word of TImode/PTImode. */
21149 fputs (reg_names
[REGNO (x
) + 3], file
);
21150 else if (MEM_P (x
))
21152 machine_mode mode
= GET_MODE (x
);
21153 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21154 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21155 output_address (mode
, plus_constant (Pmode
,
21156 XEXP (XEXP (x
, 0), 0), 12));
21157 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21158 output_address (mode
, plus_constant (Pmode
,
21159 XEXP (XEXP (x
, 0), 0), 12));
21161 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 12), 0));
21162 if (small_data_operand (x
, GET_MODE (x
)))
21163 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21164 reg_names
[SMALL_DATA_REG
]);
21168 /* Print AltiVec memory operand. */
21173 gcc_assert (MEM_P (x
));
21177 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x
))
21178 && GET_CODE (tmp
) == AND
21179 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
21180 && INTVAL (XEXP (tmp
, 1)) == -16)
21181 tmp
= XEXP (tmp
, 0);
21182 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
21183 && GET_CODE (tmp
) == PRE_MODIFY
)
21184 tmp
= XEXP (tmp
, 1);
21186 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
21189 if (GET_CODE (tmp
) != PLUS
21190 || !REG_P (XEXP (tmp
, 0))
21191 || !REG_P (XEXP (tmp
, 1)))
21193 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21197 if (REGNO (XEXP (tmp
, 0)) == 0)
21198 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
21199 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
21201 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
21202 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
21209 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
21210 else if (MEM_P (x
))
21212 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21213 know the width from the mode. */
21214 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
21215 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
21216 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21217 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21218 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
21219 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21220 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21221 output_address (GET_MODE (x
), XEXP (XEXP (x
, 0), 1));
21223 output_address (GET_MODE (x
), XEXP (x
, 0));
21225 else if (toc_relative_expr_p (x
, false,
21226 &tocrel_base_oac
, &tocrel_offset_oac
))
21227 /* This hack along with a corresponding hack in
21228 rs6000_output_addr_const_extra arranges to output addends
21229 where the assembler expects to find them. eg.
21230 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21231 without this hack would be output as "x@toc+4". We
21233 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21234 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
21235 output_addr_const (file
, XVECEXP (x
, 0, 0));
21236 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PLTSEQ
)
21237 output_addr_const (file
, XVECEXP (x
, 0, 1));
21239 output_addr_const (file
, x
);
21243 if (const char *name
= get_some_local_dynamic_name ())
21244 assemble_name (file
, name
);
21246 output_operand_lossage ("'%%&' used without any "
21247 "local dynamic TLS references");
21251 output_operand_lossage ("invalid %%xn code");
21255 /* Print the address of an operand. */
21258 print_operand_address (FILE *file
, rtx x
)
21261 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
21262 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
21263 || GET_CODE (x
) == LABEL_REF
)
21265 output_addr_const (file
, x
);
21266 if (small_data_operand (x
, GET_MODE (x
)))
21267 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21268 reg_names
[SMALL_DATA_REG
]);
21270 gcc_assert (!TARGET_TOC
);
21272 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21273 && REG_P (XEXP (x
, 1)))
21275 if (REGNO (XEXP (x
, 0)) == 0)
21276 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
21277 reg_names
[ REGNO (XEXP (x
, 0)) ]);
21279 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
21280 reg_names
[ REGNO (XEXP (x
, 1)) ]);
21282 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21283 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
21284 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
21285 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
21287 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21288 && CONSTANT_P (XEXP (x
, 1)))
21290 fprintf (file
, "lo16(");
21291 output_addr_const (file
, XEXP (x
, 1));
21292 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21296 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21297 && CONSTANT_P (XEXP (x
, 1)))
21299 output_addr_const (file
, XEXP (x
, 1));
21300 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21303 else if (toc_relative_expr_p (x
, false, &tocrel_base_oac
, &tocrel_offset_oac
))
21305 /* This hack along with a corresponding hack in
21306 rs6000_output_addr_const_extra arranges to output addends
21307 where the assembler expects to find them. eg.
21309 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21310 without this hack would be output as "x@toc+8@l(9)". We
21311 want "x+8@toc@l(9)". */
21312 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21313 if (GET_CODE (x
) == LO_SUM
)
21314 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
21316 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base_oac
, 0, 1))]);
21319 output_addr_const (file
, x
);
21322 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21325 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
21327 if (GET_CODE (x
) == UNSPEC
)
21328 switch (XINT (x
, 1))
21330 case UNSPEC_TOCREL
:
21331 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
21332 && REG_P (XVECEXP (x
, 0, 1))
21333 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
21334 output_addr_const (file
, XVECEXP (x
, 0, 0));
21335 if (x
== tocrel_base_oac
&& tocrel_offset_oac
!= const0_rtx
)
21337 if (INTVAL (tocrel_offset_oac
) >= 0)
21338 fprintf (file
, "+");
21339 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset_oac
));
21341 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
21344 assemble_name (file
, toc_label_name
);
21347 else if (TARGET_ELF
)
21348 fputs ("@toc", file
);
21352 case UNSPEC_MACHOPIC_OFFSET
:
21353 output_addr_const (file
, XVECEXP (x
, 0, 0));
21355 machopic_output_function_base_name (file
);
21362 /* Target hook for assembling integer objects. The PowerPC version has
21363 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21364 is defined. It also needs to handle DI-mode objects on 64-bit
21368 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
21370 #ifdef RELOCATABLE_NEEDS_FIXUP
21371 /* Special handling for SI values. */
21372 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
21374 static int recurse
= 0;
21376 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21377 the .fixup section. Since the TOC section is already relocated, we
21378 don't need to mark it here. We used to skip the text section, but it
21379 should never be valid for relocated addresses to be placed in the text
21381 if (DEFAULT_ABI
== ABI_V4
21382 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
21383 && in_section
!= toc_section
21385 && !CONST_SCALAR_INT_P (x
)
21391 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
21393 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
21394 fprintf (asm_out_file
, "\t.long\t(");
21395 output_addr_const (asm_out_file
, x
);
21396 fprintf (asm_out_file
, ")@fixup\n");
21397 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
21398 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
21399 fprintf (asm_out_file
, "\t.long\t");
21400 assemble_name (asm_out_file
, buf
);
21401 fprintf (asm_out_file
, "\n\t.previous\n");
21405 /* Remove initial .'s to turn a -mcall-aixdesc function
21406 address into the address of the descriptor, not the function
21408 else if (GET_CODE (x
) == SYMBOL_REF
21409 && XSTR (x
, 0)[0] == '.'
21410 && DEFAULT_ABI
== ABI_AIX
)
21412 const char *name
= XSTR (x
, 0);
21413 while (*name
== '.')
21416 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
21420 #endif /* RELOCATABLE_NEEDS_FIXUP */
21421 return default_assemble_integer (x
, size
, aligned_p
);
21424 /* Return a template string for assembly to emit when making an
21425 external call. FUNOP is the call mem argument operand number. */
21427 static const char *
21428 rs6000_call_template_1 (rtx
*operands
, unsigned int funop
, bool sibcall
)
21430 /* -Wformat-overflow workaround, without which gcc thinks that %u
21431 might produce 10 digits. */
21432 gcc_assert (funop
<= MAX_RECOG_OPERANDS
);
21436 if (TARGET_TLS_MARKERS
&& GET_CODE (operands
[funop
+ 1]) == UNSPEC
)
21438 if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSGD
)
21439 sprintf (arg
, "(%%%u@tlsgd)", funop
+ 1);
21440 else if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSLD
)
21441 sprintf (arg
, "(%%&@tlsld)");
21443 gcc_unreachable ();
21446 /* The magic 32768 offset here corresponds to the offset of
21447 r30 in .got2, as given by LCTOC1. See sysv4.h:toc_section. */
21449 sprintf (z
, "%%z%u%s", funop
,
21450 (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
== 2
21453 static char str
[32]; /* 2 spare */
21454 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21455 sprintf (str
, "b%s %s%s%s", sibcall
? "" : "l", z
, arg
,
21456 sibcall
? "" : "\n\tnop");
21457 else if (DEFAULT_ABI
== ABI_V4
)
21458 sprintf (str
, "b%s %s%s%s", sibcall
? "" : "l", z
, arg
,
21459 flag_pic
? "@plt" : "");
21461 gcc_unreachable ();
21466 rs6000_call_template (rtx
*operands
, unsigned int funop
)
21468 return rs6000_call_template_1 (operands
, funop
, false);
21472 rs6000_sibcall_template (rtx
*operands
, unsigned int funop
)
21474 return rs6000_call_template_1 (operands
, funop
, true);
21477 /* As above, for indirect calls. */
21479 static const char *
21480 rs6000_indirect_call_template_1 (rtx
*operands
, unsigned int funop
,
21483 /* -Wformat-overflow workaround, without which gcc thinks that %u
21484 might produce 10 digits. */
21485 gcc_assert (funop
<= MAX_RECOG_OPERANDS
);
21487 static char str
[144]; /* 1 spare */
21489 const char *ptrload
= TARGET_64BIT
? "d" : "wz";
21491 if (DEFAULT_ABI
== ABI_AIX
)
21494 ptrload
, funop
+ 2);
21496 /* We don't need the extra code to stop indirect call speculation if
21498 bool speculate
= (TARGET_MACHO
21499 || rs6000_speculate_indirect_jumps
21500 || (REG_P (operands
[funop
])
21501 && REGNO (operands
[funop
]) == LR_REGNO
));
21503 if (!TARGET_MACHO
&& HAVE_AS_PLTSEQ
&& GET_CODE (operands
[funop
]) == UNSPEC
)
21505 const char *rel64
= TARGET_64BIT
? "64" : "";
21508 if (GET_CODE (operands
[funop
+ 1]) == UNSPEC
)
21510 if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSGD
)
21511 sprintf (tls
, ".reloc .,R_PPC%s_TLSGD,%%%u\n\t",
21513 else if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSLD
)
21514 sprintf (tls
, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21517 gcc_unreachable ();
21520 const char *addend
= (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
21521 && flag_pic
== 2 ? "+32768" : "");
21525 "%s.reloc .,R_PPC%s_PLTSEQ,%%z%u%s\n\t",
21526 tls
, rel64
, funop
, addend
);
21527 s
+= sprintf (s
, "crset 2\n\t");
21530 "%s.reloc .,R_PPC%s_PLTCALL,%%z%u%s\n\t",
21531 tls
, rel64
, funop
, addend
);
21533 else if (!speculate
)
21534 s
+= sprintf (s
, "crset 2\n\t");
21536 if (DEFAULT_ABI
== ABI_AIX
)
21542 funop
, ptrload
, funop
+ 3);
21547 funop
, ptrload
, funop
+ 3);
21549 else if (DEFAULT_ABI
== ABI_ELFv2
)
21555 funop
, ptrload
, funop
+ 2);
21560 funop
, ptrload
, funop
+ 2);
21567 funop
, sibcall
? "" : "l");
21571 funop
, sibcall
? "" : "l", sibcall
? "\n\tb $" : "");
21577 rs6000_indirect_call_template (rtx
*operands
, unsigned int funop
)
21579 return rs6000_indirect_call_template_1 (operands
, funop
, false);
21583 rs6000_indirect_sibcall_template (rtx
*operands
, unsigned int funop
)
21585 return rs6000_indirect_call_template_1 (operands
, funop
, true);
21589 /* Output indirect call insns.
21590 WHICH is 0 for tocsave, 1 for plt16_ha, 2 for plt16_lo, 3 for mtctr. */
21592 rs6000_pltseq_template (rtx
*operands
, int which
)
21594 const char *rel64
= TARGET_64BIT
? "64" : "";
21597 if (GET_CODE (operands
[3]) == UNSPEC
)
21599 if (XINT (operands
[3], 1) == UNSPEC_TLSGD
)
21600 sprintf (tls
, ".reloc .,R_PPC%s_TLSGD,%%3\n\t",
21602 else if (XINT (operands
[3], 1) == UNSPEC_TLSLD
)
21603 sprintf (tls
, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21606 gcc_unreachable ();
21609 gcc_assert (DEFAULT_ABI
== ABI_ELFv2
|| DEFAULT_ABI
== ABI_V4
);
21610 static char str
[96]; /* 15 spare */
21611 const char *off
= WORDS_BIG_ENDIAN
? "+2" : "";
21612 const char *addend
= (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
21613 && flag_pic
== 2 ? "+32768" : "");
21618 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2\n\t"
21620 tls
, rel64
, TARGET_64BIT
? "d 2,24(1)" : "w 2,12(1)");
21623 if (DEFAULT_ABI
== ABI_V4
&& !flag_pic
)
21625 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2\n\t"
21630 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2%s\n\t"
21632 tls
, off
, rel64
, addend
);
21636 "%s.reloc .%s,R_PPC%s_PLT16_LO%s,%%z2%s\n\t"
21638 tls
, off
, rel64
, TARGET_64BIT
? "_DS" : "", addend
,
21639 TARGET_64BIT
? "d" : "wz");
21643 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2%s\n\t"
21645 tls
, rel64
, addend
);
21648 gcc_unreachable ();
21654 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21655 /* Emit an assembler directive to set symbol visibility for DECL to
21656 VISIBILITY_TYPE. */
21659 rs6000_assemble_visibility (tree decl
, int vis
)
21664 /* Functions need to have their entry point symbol visibility set as
21665 well as their descriptor symbol visibility. */
21666 if (DEFAULT_ABI
== ABI_AIX
21668 && TREE_CODE (decl
) == FUNCTION_DECL
)
21670 static const char * const visibility_types
[] = {
21671 NULL
, "protected", "hidden", "internal"
21674 const char *name
, *type
;
21676 name
= ((* targetm
.strip_name_encoding
)
21677 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
21678 type
= visibility_types
[vis
];
21680 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
21681 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
21684 default_assemble_visibility (decl
, vis
);
21689 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
21691 /* Reversal of FP compares takes care -- an ordered compare
21692 becomes an unordered compare and vice versa. */
21693 if (mode
== CCFPmode
21694 && (!flag_finite_math_only
21695 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
21696 || code
== UNEQ
|| code
== LTGT
))
21697 return reverse_condition_maybe_unordered (code
);
21699 return reverse_condition (code
);
21702 /* Generate a compare for CODE. Return a brand-new rtx that
21703 represents the result of the compare. */
21706 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
21708 machine_mode comp_mode
;
21709 rtx compare_result
;
21710 enum rtx_code code
= GET_CODE (cmp
);
21711 rtx op0
= XEXP (cmp
, 0);
21712 rtx op1
= XEXP (cmp
, 1);
21714 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
21715 comp_mode
= CCmode
;
21716 else if (FLOAT_MODE_P (mode
))
21717 comp_mode
= CCFPmode
;
21718 else if (code
== GTU
|| code
== LTU
21719 || code
== GEU
|| code
== LEU
)
21720 comp_mode
= CCUNSmode
;
21721 else if ((code
== EQ
|| code
== NE
)
21722 && unsigned_reg_p (op0
)
21723 && (unsigned_reg_p (op1
)
21724 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
21725 /* These are unsigned values, perhaps there will be a later
21726 ordering compare that can be shared with this one. */
21727 comp_mode
= CCUNSmode
;
21729 comp_mode
= CCmode
;
21731 /* If we have an unsigned compare, make sure we don't have a signed value as
21733 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
21734 && INTVAL (op1
) < 0)
21736 op0
= copy_rtx_if_shared (op0
);
21737 op1
= force_reg (GET_MODE (op0
), op1
);
21738 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
21741 /* First, the compare. */
21742 compare_result
= gen_reg_rtx (comp_mode
);
21744 /* IEEE 128-bit support in VSX registers when we do not have hardware
21746 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
21748 rtx libfunc
= NULL_RTX
;
21749 bool check_nan
= false;
21756 libfunc
= optab_libfunc (eq_optab
, mode
);
21761 libfunc
= optab_libfunc (ge_optab
, mode
);
21766 libfunc
= optab_libfunc (le_optab
, mode
);
21771 libfunc
= optab_libfunc (unord_optab
, mode
);
21772 code
= (code
== UNORDERED
) ? NE
: EQ
;
21778 libfunc
= optab_libfunc (ge_optab
, mode
);
21779 code
= (code
== UNGE
) ? GE
: GT
;
21785 libfunc
= optab_libfunc (le_optab
, mode
);
21786 code
= (code
== UNLE
) ? LE
: LT
;
21792 libfunc
= optab_libfunc (eq_optab
, mode
);
21793 code
= (code
= UNEQ
) ? EQ
: NE
;
21797 gcc_unreachable ();
21800 gcc_assert (libfunc
);
21803 dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
21804 SImode
, op0
, mode
, op1
, mode
);
21806 /* The library signals an exception for signalling NaNs, so we need to
21807 handle isgreater, etc. by first checking isordered. */
21810 rtx ne_rtx
, normal_dest
, unord_dest
;
21811 rtx unord_func
= optab_libfunc (unord_optab
, mode
);
21812 rtx join_label
= gen_label_rtx ();
21813 rtx join_ref
= gen_rtx_LABEL_REF (VOIDmode
, join_label
);
21814 rtx unord_cmp
= gen_reg_rtx (comp_mode
);
21817 /* Test for either value being a NaN. */
21818 gcc_assert (unord_func
);
21819 unord_dest
= emit_library_call_value (unord_func
, NULL_RTX
, LCT_CONST
,
21820 SImode
, op0
, mode
, op1
, mode
);
21822 /* Set value (0) if either value is a NaN, and jump to the join
21824 dest
= gen_reg_rtx (SImode
);
21825 emit_move_insn (dest
, const1_rtx
);
21826 emit_insn (gen_rtx_SET (unord_cmp
,
21827 gen_rtx_COMPARE (comp_mode
, unord_dest
,
21830 ne_rtx
= gen_rtx_NE (comp_mode
, unord_cmp
, const0_rtx
);
21831 emit_jump_insn (gen_rtx_SET (pc_rtx
,
21832 gen_rtx_IF_THEN_ELSE (VOIDmode
, ne_rtx
,
21836 /* Do the normal comparison, knowing that the values are not
21838 normal_dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
21839 SImode
, op0
, mode
, op1
, mode
);
21841 emit_insn (gen_cstoresi4 (dest
,
21842 gen_rtx_fmt_ee (code
, SImode
, normal_dest
,
21844 normal_dest
, const0_rtx
));
21846 /* Join NaN and non-Nan paths. Compare dest against 0. */
21847 emit_label (join_label
);
21851 emit_insn (gen_rtx_SET (compare_result
,
21852 gen_rtx_COMPARE (comp_mode
, dest
, const0_rtx
)));
21857 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21858 CLOBBERs to match cmptf_internal2 pattern. */
21859 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
21860 && FLOAT128_IBM_P (GET_MODE (op0
))
21861 && TARGET_HARD_FLOAT
)
21862 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
21864 gen_rtx_SET (compare_result
,
21865 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
21866 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21867 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21868 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21869 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21870 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21871 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21872 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21873 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21874 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
21875 else if (GET_CODE (op1
) == UNSPEC
21876 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
21878 rtx op1b
= XVECEXP (op1
, 0, 0);
21879 comp_mode
= CCEQmode
;
21880 compare_result
= gen_reg_rtx (CCEQmode
);
21882 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
21884 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
21887 emit_insn (gen_rtx_SET (compare_result
,
21888 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
21891 /* Some kinds of FP comparisons need an OR operation;
21892 under flag_finite_math_only we don't bother. */
21893 if (FLOAT_MODE_P (mode
)
21894 && (!FLOAT128_IEEE_P (mode
) || TARGET_FLOAT128_HW
)
21895 && !flag_finite_math_only
21896 && (code
== LE
|| code
== GE
21897 || code
== UNEQ
|| code
== LTGT
21898 || code
== UNGT
|| code
== UNLT
))
21900 enum rtx_code or1
, or2
;
21901 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
21902 rtx or_result
= gen_reg_rtx (CCEQmode
);
21906 case LE
: or1
= LT
; or2
= EQ
; break;
21907 case GE
: or1
= GT
; or2
= EQ
; break;
21908 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
21909 case LTGT
: or1
= LT
; or2
= GT
; break;
21910 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
21911 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
21912 default: gcc_unreachable ();
21914 validate_condition_mode (or1
, comp_mode
);
21915 validate_condition_mode (or2
, comp_mode
);
21916 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
21917 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
21918 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
21919 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
21921 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
21923 compare_result
= or_result
;
21927 validate_condition_mode (code
, GET_MODE (compare_result
));
21929 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
21933 /* Return the diagnostic message string if the binary operation OP is
21934 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21937 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED
,
21941 machine_mode mode1
= TYPE_MODE (type1
);
21942 machine_mode mode2
= TYPE_MODE (type2
);
21944 /* For complex modes, use the inner type. */
21945 if (COMPLEX_MODE_P (mode1
))
21946 mode1
= GET_MODE_INNER (mode1
);
21948 if (COMPLEX_MODE_P (mode2
))
21949 mode2
= GET_MODE_INNER (mode2
);
21951 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21952 double to intermix unless -mfloat128-convert. */
21953 if (mode1
== mode2
)
21956 if (!TARGET_FLOAT128_CVT
)
21958 if ((mode1
== KFmode
&& mode2
== IFmode
)
21959 || (mode1
== IFmode
&& mode2
== KFmode
))
21960 return N_("__float128 and __ibm128 cannot be used in the same "
21963 if (TARGET_IEEEQUAD
21964 && ((mode1
== IFmode
&& mode2
== TFmode
)
21965 || (mode1
== TFmode
&& mode2
== IFmode
)))
21966 return N_("__ibm128 and long double cannot be used in the same "
21969 if (!TARGET_IEEEQUAD
21970 && ((mode1
== KFmode
&& mode2
== TFmode
)
21971 || (mode1
== TFmode
&& mode2
== KFmode
)))
21972 return N_("__float128 and long double cannot be used in the same "
21980 /* Expand floating point conversion to/from __float128 and __ibm128. */
21983 rs6000_expand_float128_convert (rtx dest
, rtx src
, bool unsigned_p
)
21985 machine_mode dest_mode
= GET_MODE (dest
);
21986 machine_mode src_mode
= GET_MODE (src
);
21987 convert_optab cvt
= unknown_optab
;
21988 bool do_move
= false;
21989 rtx libfunc
= NULL_RTX
;
21991 typedef rtx (*rtx_2func_t
) (rtx
, rtx
);
21992 rtx_2func_t hw_convert
= (rtx_2func_t
)0;
21996 rtx_2func_t from_df
;
21997 rtx_2func_t from_sf
;
21998 rtx_2func_t from_si_sign
;
21999 rtx_2func_t from_si_uns
;
22000 rtx_2func_t from_di_sign
;
22001 rtx_2func_t from_di_uns
;
22004 rtx_2func_t to_si_sign
;
22005 rtx_2func_t to_si_uns
;
22006 rtx_2func_t to_di_sign
;
22007 rtx_2func_t to_di_uns
;
22008 } hw_conversions
[2] = {
22009 /* convertions to/from KFmode */
22011 gen_extenddfkf2_hw
, /* KFmode <- DFmode. */
22012 gen_extendsfkf2_hw
, /* KFmode <- SFmode. */
22013 gen_float_kfsi2_hw
, /* KFmode <- SImode (signed). */
22014 gen_floatuns_kfsi2_hw
, /* KFmode <- SImode (unsigned). */
22015 gen_float_kfdi2_hw
, /* KFmode <- DImode (signed). */
22016 gen_floatuns_kfdi2_hw
, /* KFmode <- DImode (unsigned). */
22017 gen_trunckfdf2_hw
, /* DFmode <- KFmode. */
22018 gen_trunckfsf2_hw
, /* SFmode <- KFmode. */
22019 gen_fix_kfsi2_hw
, /* SImode <- KFmode (signed). */
22020 gen_fixuns_kfsi2_hw
, /* SImode <- KFmode (unsigned). */
22021 gen_fix_kfdi2_hw
, /* DImode <- KFmode (signed). */
22022 gen_fixuns_kfdi2_hw
, /* DImode <- KFmode (unsigned). */
22025 /* convertions to/from TFmode */
22027 gen_extenddftf2_hw
, /* TFmode <- DFmode. */
22028 gen_extendsftf2_hw
, /* TFmode <- SFmode. */
22029 gen_float_tfsi2_hw
, /* TFmode <- SImode (signed). */
22030 gen_floatuns_tfsi2_hw
, /* TFmode <- SImode (unsigned). */
22031 gen_float_tfdi2_hw
, /* TFmode <- DImode (signed). */
22032 gen_floatuns_tfdi2_hw
, /* TFmode <- DImode (unsigned). */
22033 gen_trunctfdf2_hw
, /* DFmode <- TFmode. */
22034 gen_trunctfsf2_hw
, /* SFmode <- TFmode. */
22035 gen_fix_tfsi2_hw
, /* SImode <- TFmode (signed). */
22036 gen_fixuns_tfsi2_hw
, /* SImode <- TFmode (unsigned). */
22037 gen_fix_tfdi2_hw
, /* DImode <- TFmode (signed). */
22038 gen_fixuns_tfdi2_hw
, /* DImode <- TFmode (unsigned). */
22042 if (dest_mode
== src_mode
)
22043 gcc_unreachable ();
22045 /* Eliminate memory operations. */
22047 src
= force_reg (src_mode
, src
);
22051 rtx tmp
= gen_reg_rtx (dest_mode
);
22052 rs6000_expand_float128_convert (tmp
, src
, unsigned_p
);
22053 rs6000_emit_move (dest
, tmp
, dest_mode
);
22057 /* Convert to IEEE 128-bit floating point. */
22058 if (FLOAT128_IEEE_P (dest_mode
))
22060 if (dest_mode
== KFmode
)
22062 else if (dest_mode
== TFmode
)
22065 gcc_unreachable ();
22071 hw_convert
= hw_conversions
[kf_or_tf
].from_df
;
22076 hw_convert
= hw_conversions
[kf_or_tf
].from_sf
;
22082 if (FLOAT128_IBM_P (src_mode
))
22091 cvt
= ufloat_optab
;
22092 hw_convert
= hw_conversions
[kf_or_tf
].from_si_uns
;
22096 cvt
= sfloat_optab
;
22097 hw_convert
= hw_conversions
[kf_or_tf
].from_si_sign
;
22104 cvt
= ufloat_optab
;
22105 hw_convert
= hw_conversions
[kf_or_tf
].from_di_uns
;
22109 cvt
= sfloat_optab
;
22110 hw_convert
= hw_conversions
[kf_or_tf
].from_di_sign
;
22115 gcc_unreachable ();
22119 /* Convert from IEEE 128-bit floating point. */
22120 else if (FLOAT128_IEEE_P (src_mode
))
22122 if (src_mode
== KFmode
)
22124 else if (src_mode
== TFmode
)
22127 gcc_unreachable ();
22133 hw_convert
= hw_conversions
[kf_or_tf
].to_df
;
22138 hw_convert
= hw_conversions
[kf_or_tf
].to_sf
;
22144 if (FLOAT128_IBM_P (dest_mode
))
22154 hw_convert
= hw_conversions
[kf_or_tf
].to_si_uns
;
22159 hw_convert
= hw_conversions
[kf_or_tf
].to_si_sign
;
22167 hw_convert
= hw_conversions
[kf_or_tf
].to_di_uns
;
22172 hw_convert
= hw_conversions
[kf_or_tf
].to_di_sign
;
22177 gcc_unreachable ();
22181 /* Both IBM format. */
22182 else if (FLOAT128_IBM_P (dest_mode
) && FLOAT128_IBM_P (src_mode
))
22186 gcc_unreachable ();
22188 /* Handle conversion between TFmode/KFmode/IFmode. */
22190 emit_insn (gen_rtx_SET (dest
, gen_rtx_FLOAT_EXTEND (dest_mode
, src
)));
22192 /* Handle conversion if we have hardware support. */
22193 else if (TARGET_FLOAT128_HW
&& hw_convert
)
22194 emit_insn ((hw_convert
) (dest
, src
));
22196 /* Call an external function to do the conversion. */
22197 else if (cvt
!= unknown_optab
)
22199 libfunc
= convert_optab_libfunc (cvt
, dest_mode
, src_mode
);
22200 gcc_assert (libfunc
!= NULL_RTX
);
22202 dest2
= emit_library_call_value (libfunc
, dest
, LCT_CONST
, dest_mode
,
22205 gcc_assert (dest2
!= NULL_RTX
);
22206 if (!rtx_equal_p (dest
, dest2
))
22207 emit_move_insn (dest
, dest2
);
22211 gcc_unreachable ();
22217 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22218 can be used as that dest register. Return the dest register. */
22221 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
22223 if (op2
== const0_rtx
)
22226 if (GET_CODE (scratch
) == SCRATCH
)
22227 scratch
= gen_reg_rtx (mode
);
22229 if (logical_operand (op2
, mode
))
22230 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
22232 emit_insn (gen_rtx_SET (scratch
,
22233 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
22239 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
22242 machine_mode op_mode
;
22243 enum rtx_code cond_code
;
22244 rtx result
= operands
[0];
22246 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
22247 cond_code
= GET_CODE (condition_rtx
);
22249 if (cond_code
== NE
22250 || cond_code
== GE
|| cond_code
== LE
22251 || cond_code
== GEU
|| cond_code
== LEU
22252 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
22254 rtx not_result
= gen_reg_rtx (CCEQmode
);
22255 rtx not_op
, rev_cond_rtx
;
22256 machine_mode cc_mode
;
22258 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
22260 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
22261 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
22262 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
22263 emit_insn (gen_rtx_SET (not_result
, not_op
));
22264 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
22267 op_mode
= GET_MODE (XEXP (operands
[1], 0));
22268 if (op_mode
== VOIDmode
)
22269 op_mode
= GET_MODE (XEXP (operands
[1], 1));
22271 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
22273 PUT_MODE (condition_rtx
, DImode
);
22274 convert_move (result
, condition_rtx
, 0);
22278 PUT_MODE (condition_rtx
, SImode
);
22279 emit_insn (gen_rtx_SET (result
, condition_rtx
));
22283 /* Emit a branch of kind CODE to location LOC. */
22286 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
22288 rtx condition_rtx
, loc_ref
;
22290 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
22291 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
22292 emit_jump_insn (gen_rtx_SET (pc_rtx
,
22293 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
22294 loc_ref
, pc_rtx
)));
22297 /* Return the string to output a conditional branch to LABEL, which is
22298 the operand template of the label, or NULL if the branch is really a
22299 conditional return.
22301 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22302 condition code register and its mode specifies what kind of
22303 comparison we made.
22305 REVERSED is nonzero if we should reverse the sense of the comparison.
22307 INSN is the insn. */
22310 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
22312 static char string
[64];
22313 enum rtx_code code
= GET_CODE (op
);
22314 rtx cc_reg
= XEXP (op
, 0);
22315 machine_mode mode
= GET_MODE (cc_reg
);
22316 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
22317 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
22318 int really_reversed
= reversed
^ need_longbranch
;
22324 validate_condition_mode (code
, mode
);
22326 /* Work out which way this really branches. We could use
22327 reverse_condition_maybe_unordered here always but this
22328 makes the resulting assembler clearer. */
22329 if (really_reversed
)
22331 /* Reversal of FP compares takes care -- an ordered compare
22332 becomes an unordered compare and vice versa. */
22333 if (mode
== CCFPmode
)
22334 code
= reverse_condition_maybe_unordered (code
);
22336 code
= reverse_condition (code
);
22341 /* Not all of these are actually distinct opcodes, but
22342 we distinguish them for clarity of the resulting assembler. */
22343 case NE
: case LTGT
:
22344 ccode
= "ne"; break;
22345 case EQ
: case UNEQ
:
22346 ccode
= "eq"; break;
22348 ccode
= "ge"; break;
22349 case GT
: case GTU
: case UNGT
:
22350 ccode
= "gt"; break;
22352 ccode
= "le"; break;
22353 case LT
: case LTU
: case UNLT
:
22354 ccode
= "lt"; break;
22355 case UNORDERED
: ccode
= "un"; break;
22356 case ORDERED
: ccode
= "nu"; break;
22357 case UNGE
: ccode
= "nl"; break;
22358 case UNLE
: ccode
= "ng"; break;
22360 gcc_unreachable ();
22363 /* Maybe we have a guess as to how likely the branch is. */
22365 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
22366 if (note
!= NULL_RTX
)
22368 /* PROB is the difference from 50%. */
22369 int prob
= profile_probability::from_reg_br_prob_note (XINT (note
, 0))
22370 .to_reg_br_prob_base () - REG_BR_PROB_BASE
/ 2;
22372 /* Only hint for highly probable/improbable branches on newer cpus when
22373 we have real profile data, as static prediction overrides processor
22374 dynamic prediction. For older cpus we may as well always hint, but
22375 assume not taken for branches that are very close to 50% as a
22376 mispredicted taken branch is more expensive than a
22377 mispredicted not-taken branch. */
22378 if (rs6000_always_hint
22379 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
22380 && (profile_status_for_fn (cfun
) != PROFILE_GUESSED
)
22381 && br_prob_note_reliable_p (note
)))
22383 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
22384 && ((prob
> 0) ^ need_longbranch
))
22392 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
22394 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
22396 /* We need to escape any '%' characters in the reg_names string.
22397 Assume they'd only be the first character.... */
22398 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
22400 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
22404 /* If the branch distance was too far, we may have to use an
22405 unconditional branch to go the distance. */
22406 if (need_longbranch
)
22407 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
22409 s
+= sprintf (s
, ",%s", label
);
22415 /* Return insn for VSX or Altivec comparisons. */
22418 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
22421 machine_mode mode
= GET_MODE (op0
);
22429 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
22440 mask
= gen_reg_rtx (mode
);
22441 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
22448 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22449 DMODE is expected destination mode. This is a recursive function. */
22452 rs6000_emit_vector_compare (enum rtx_code rcode
,
22454 machine_mode dmode
)
22457 bool swap_operands
= false;
22458 bool try_again
= false;
22460 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
22461 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
22463 /* See if the comparison works as is. */
22464 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22472 swap_operands
= true;
22477 swap_operands
= true;
22485 /* Invert condition and try again.
22486 e.g., A != B becomes ~(A==B). */
22488 enum rtx_code rev_code
;
22489 enum insn_code nor_code
;
22492 rev_code
= reverse_condition_maybe_unordered (rcode
);
22493 if (rev_code
== UNKNOWN
)
22496 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
22497 if (nor_code
== CODE_FOR_nothing
)
22500 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
22504 mask
= gen_reg_rtx (dmode
);
22505 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
22513 /* Try GT/GTU/LT/LTU OR EQ */
22516 enum insn_code ior_code
;
22517 enum rtx_code new_code
;
22538 gcc_unreachable ();
22541 ior_code
= optab_handler (ior_optab
, dmode
);
22542 if (ior_code
== CODE_FOR_nothing
)
22545 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
22549 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
22553 mask
= gen_reg_rtx (dmode
);
22554 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
22565 std::swap (op0
, op1
);
22567 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22572 /* You only get two chances. */
22576 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22577 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22578 operands for the relation operation COND. */
22581 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
22582 rtx cond
, rtx cc_op0
, rtx cc_op1
)
22584 machine_mode dest_mode
= GET_MODE (dest
);
22585 machine_mode mask_mode
= GET_MODE (cc_op0
);
22586 enum rtx_code rcode
= GET_CODE (cond
);
22587 machine_mode cc_mode
= CCmode
;
22590 bool invert_move
= false;
22592 if (VECTOR_UNIT_NONE_P (dest_mode
))
22595 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
22596 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
22600 /* Swap operands if we can, and fall back to doing the operation as
22601 specified, and doing a NOR to invert the test. */
22607 /* Invert condition and try again.
22608 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22609 invert_move
= true;
22610 rcode
= reverse_condition_maybe_unordered (rcode
);
22611 if (rcode
== UNKNOWN
)
22617 if (GET_MODE_CLASS (mask_mode
) == MODE_VECTOR_INT
)
22619 /* Invert condition to avoid compound test. */
22620 invert_move
= true;
22621 rcode
= reverse_condition (rcode
);
22629 /* Mark unsigned tests with CCUNSmode. */
22630 cc_mode
= CCUNSmode
;
22632 /* Invert condition to avoid compound test if necessary. */
22633 if (rcode
== GEU
|| rcode
== LEU
)
22635 invert_move
= true;
22636 rcode
= reverse_condition (rcode
);
22644 /* Get the vector mask for the given relational operations. */
22645 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
22651 std::swap (op_true
, op_false
);
22653 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22654 if (GET_MODE_CLASS (dest_mode
) == MODE_VECTOR_INT
22655 && (GET_CODE (op_true
) == CONST_VECTOR
22656 || GET_CODE (op_false
) == CONST_VECTOR
))
22658 rtx constant_0
= CONST0_RTX (dest_mode
);
22659 rtx constant_m1
= CONSTM1_RTX (dest_mode
);
22661 if (op_true
== constant_m1
&& op_false
== constant_0
)
22663 emit_move_insn (dest
, mask
);
22667 else if (op_true
== constant_0
&& op_false
== constant_m1
)
22669 emit_insn (gen_rtx_SET (dest
, gen_rtx_NOT (dest_mode
, mask
)));
22673 /* If we can't use the vector comparison directly, perhaps we can use
22674 the mask for the true or false fields, instead of loading up a
22676 if (op_true
== constant_m1
)
22679 if (op_false
== constant_0
)
22683 if (!REG_P (op_true
) && !SUBREG_P (op_true
))
22684 op_true
= force_reg (dest_mode
, op_true
);
22686 if (!REG_P (op_false
) && !SUBREG_P (op_false
))
22687 op_false
= force_reg (dest_mode
, op_false
);
22689 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
22690 CONST0_RTX (dest_mode
));
22691 emit_insn (gen_rtx_SET (dest
,
22692 gen_rtx_IF_THEN_ELSE (dest_mode
,
22699 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22700 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22701 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22702 hardware has no such operation. */
22705 rs6000_emit_p9_fp_minmax (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22707 enum rtx_code code
= GET_CODE (op
);
22708 rtx op0
= XEXP (op
, 0);
22709 rtx op1
= XEXP (op
, 1);
22710 machine_mode compare_mode
= GET_MODE (op0
);
22711 machine_mode result_mode
= GET_MODE (dest
);
22712 bool max_p
= false;
22714 if (result_mode
!= compare_mode
)
22717 if (code
== GE
|| code
== GT
)
22719 else if (code
== LE
|| code
== LT
)
22724 if (rtx_equal_p (op0
, true_cond
) && rtx_equal_p (op1
, false_cond
))
22727 else if (rtx_equal_p (op1
, true_cond
) && rtx_equal_p (op0
, false_cond
))
22733 rs6000_emit_minmax (dest
, max_p
? SMAX
: SMIN
, op0
, op1
);
22737 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22738 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22739 operands of the last comparison is nonzero/true, FALSE_COND if it is
22740 zero/false. Return 0 if the hardware has no such operation. */
22743 rs6000_emit_p9_fp_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22745 enum rtx_code code
= GET_CODE (op
);
22746 rtx op0
= XEXP (op
, 0);
22747 rtx op1
= XEXP (op
, 1);
22748 machine_mode result_mode
= GET_MODE (dest
);
22753 if (!can_create_pseudo_p ())
22766 code
= swap_condition (code
);
22767 std::swap (op0
, op1
);
22774 /* Generate: [(parallel [(set (dest)
22775 (if_then_else (op (cmp1) (cmp2))
22778 (clobber (scratch))])]. */
22780 compare_rtx
= gen_rtx_fmt_ee (code
, CCFPmode
, op0
, op1
);
22781 cmove_rtx
= gen_rtx_SET (dest
,
22782 gen_rtx_IF_THEN_ELSE (result_mode
,
22787 clobber_rtx
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (V2DImode
));
22788 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22789 gen_rtvec (2, cmove_rtx
, clobber_rtx
)));
22794 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22795 operands of the last comparison is nonzero/true, FALSE_COND if it
22796 is zero/false. Return 0 if the hardware has no such operation. */
22799 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22801 enum rtx_code code
= GET_CODE (op
);
22802 rtx op0
= XEXP (op
, 0);
22803 rtx op1
= XEXP (op
, 1);
22804 machine_mode compare_mode
= GET_MODE (op0
);
22805 machine_mode result_mode
= GET_MODE (dest
);
22807 bool is_against_zero
;
22809 /* These modes should always match. */
22810 if (GET_MODE (op1
) != compare_mode
22811 /* In the isel case however, we can use a compare immediate, so
22812 op1 may be a small constant. */
22813 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
22815 if (GET_MODE (true_cond
) != result_mode
)
22817 if (GET_MODE (false_cond
) != result_mode
)
22820 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22821 if (TARGET_P9_MINMAX
22822 && (compare_mode
== SFmode
|| compare_mode
== DFmode
)
22823 && (result_mode
== SFmode
|| result_mode
== DFmode
))
22825 if (rs6000_emit_p9_fp_minmax (dest
, op
, true_cond
, false_cond
))
22828 if (rs6000_emit_p9_fp_cmove (dest
, op
, true_cond
, false_cond
))
22832 /* Don't allow using floating point comparisons for integer results for
22834 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
22837 /* First, work out if the hardware can do this at all, or
22838 if it's too slow.... */
22839 if (!FLOAT_MODE_P (compare_mode
))
22842 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
22846 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
22848 /* A floating-point subtract might overflow, underflow, or produce
22849 an inexact result, thus changing the floating-point flags, so it
22850 can't be generated if we care about that. It's safe if one side
22851 of the construct is zero, since then no subtract will be
22853 if (SCALAR_FLOAT_MODE_P (compare_mode
)
22854 && flag_trapping_math
&& ! is_against_zero
)
22857 /* Eliminate half of the comparisons by switching operands, this
22858 makes the remaining code simpler. */
22859 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
22860 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
22862 code
= reverse_condition_maybe_unordered (code
);
22864 true_cond
= false_cond
;
22868 /* UNEQ and LTGT take four instructions for a comparison with zero,
22869 it'll probably be faster to use a branch here too. */
22870 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
22873 /* We're going to try to implement comparisons by performing
22874 a subtract, then comparing against zero. Unfortunately,
22875 Inf - Inf is NaN which is not zero, and so if we don't
22876 know that the operand is finite and the comparison
22877 would treat EQ different to UNORDERED, we can't do it. */
22878 if (HONOR_INFINITIES (compare_mode
)
22879 && code
!= GT
&& code
!= UNGE
22880 && (GET_CODE (op1
) != CONST_DOUBLE
22881 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1
)))
22882 /* Constructs of the form (a OP b ? a : b) are safe. */
22883 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
22884 || (! rtx_equal_p (op0
, true_cond
)
22885 && ! rtx_equal_p (op1
, true_cond
))))
22888 /* At this point we know we can use fsel. */
22890 /* Reduce the comparison to a comparison against zero. */
22891 if (! is_against_zero
)
22893 temp
= gen_reg_rtx (compare_mode
);
22894 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
22896 op1
= CONST0_RTX (compare_mode
);
22899 /* If we don't care about NaNs we can reduce some of the comparisons
22900 down to faster ones. */
22901 if (! HONOR_NANS (compare_mode
))
22907 true_cond
= false_cond
;
22920 /* Now, reduce everything down to a GE. */
22927 temp
= gen_reg_rtx (compare_mode
);
22928 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
22933 temp
= gen_reg_rtx (compare_mode
);
22934 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
22939 temp
= gen_reg_rtx (compare_mode
);
22940 emit_insn (gen_rtx_SET (temp
,
22941 gen_rtx_NEG (compare_mode
,
22942 gen_rtx_ABS (compare_mode
, op0
))));
22947 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22948 temp
= gen_reg_rtx (result_mode
);
22949 emit_insn (gen_rtx_SET (temp
,
22950 gen_rtx_IF_THEN_ELSE (result_mode
,
22951 gen_rtx_GE (VOIDmode
,
22953 true_cond
, false_cond
)));
22954 false_cond
= true_cond
;
22957 temp
= gen_reg_rtx (compare_mode
);
22958 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
22963 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22964 temp
= gen_reg_rtx (result_mode
);
22965 emit_insn (gen_rtx_SET (temp
,
22966 gen_rtx_IF_THEN_ELSE (result_mode
,
22967 gen_rtx_GE (VOIDmode
,
22969 true_cond
, false_cond
)));
22970 true_cond
= false_cond
;
22973 temp
= gen_reg_rtx (compare_mode
);
22974 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
22979 gcc_unreachable ();
22982 emit_insn (gen_rtx_SET (dest
,
22983 gen_rtx_IF_THEN_ELSE (result_mode
,
22984 gen_rtx_GE (VOIDmode
,
22986 true_cond
, false_cond
)));
22990 /* Same as above, but for ints (isel). */
22993 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22995 rtx condition_rtx
, cr
;
22996 machine_mode mode
= GET_MODE (dest
);
22997 enum rtx_code cond_code
;
22998 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
23001 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
23004 /* We still have to do the compare, because isel doesn't do a
23005 compare, it just looks at the CRx bits set by a previous compare
23007 condition_rtx
= rs6000_generate_compare (op
, mode
);
23008 cond_code
= GET_CODE (condition_rtx
);
23009 cr
= XEXP (condition_rtx
, 0);
23010 signedp
= GET_MODE (cr
) == CCmode
;
23012 isel_func
= (mode
== SImode
23013 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
23014 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
23018 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
23019 /* isel handles these directly. */
23023 /* We need to swap the sense of the comparison. */
23025 std::swap (false_cond
, true_cond
);
23026 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
23031 false_cond
= force_reg (mode
, false_cond
);
23032 if (true_cond
!= const0_rtx
)
23033 true_cond
= force_reg (mode
, true_cond
);
23035 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
23041 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
23043 machine_mode mode
= GET_MODE (op0
);
23047 /* VSX/altivec have direct min/max insns. */
23048 if ((code
== SMAX
|| code
== SMIN
)
23049 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
23050 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
23052 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
23056 if (code
== SMAX
|| code
== SMIN
)
23061 if (code
== SMAX
|| code
== UMAX
)
23062 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
23063 op0
, op1
, mode
, 0);
23065 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
23066 op1
, op0
, mode
, 0);
23067 gcc_assert (target
);
23068 if (target
!= dest
)
23069 emit_move_insn (dest
, target
);
23072 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23073 COND is true. Mark the jump as unlikely to be taken. */
23076 emit_unlikely_jump (rtx cond
, rtx label
)
23078 rtx x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
23079 rtx_insn
*insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
23080 add_reg_br_prob_note (insn
, profile_probability::very_unlikely ());
23083 /* A subroutine of the atomic operation splitters. Emit a load-locked
23084 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23085 the zero_extend operation. */
23088 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
23090 rtx (*fn
) (rtx
, rtx
) = NULL
;
23095 fn
= gen_load_lockedqi
;
23098 fn
= gen_load_lockedhi
;
23101 if (GET_MODE (mem
) == QImode
)
23102 fn
= gen_load_lockedqi_si
;
23103 else if (GET_MODE (mem
) == HImode
)
23104 fn
= gen_load_lockedhi_si
;
23106 fn
= gen_load_lockedsi
;
23109 fn
= gen_load_lockeddi
;
23112 fn
= gen_load_lockedti
;
23115 gcc_unreachable ();
23117 emit_insn (fn (reg
, mem
));
23120 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23121 instruction in MODE. */
23124 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
23126 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
23131 fn
= gen_store_conditionalqi
;
23134 fn
= gen_store_conditionalhi
;
23137 fn
= gen_store_conditionalsi
;
23140 fn
= gen_store_conditionaldi
;
23143 fn
= gen_store_conditionalti
;
23146 gcc_unreachable ();
23149 /* Emit sync before stwcx. to address PPC405 Erratum. */
23150 if (PPC405_ERRATUM77
)
23151 emit_insn (gen_hwsync ());
23153 emit_insn (fn (res
, mem
, val
));
23156 /* Expand barriers before and after a load_locked/store_cond sequence. */
23159 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
23161 rtx addr
= XEXP (mem
, 0);
23163 if (!legitimate_indirect_address_p (addr
, reload_completed
)
23164 && !legitimate_indexed_address_p (addr
, reload_completed
))
23166 addr
= force_reg (Pmode
, addr
);
23167 mem
= replace_equiv_address_nv (mem
, addr
);
23172 case MEMMODEL_RELAXED
:
23173 case MEMMODEL_CONSUME
:
23174 case MEMMODEL_ACQUIRE
:
23176 case MEMMODEL_RELEASE
:
23177 case MEMMODEL_ACQ_REL
:
23178 emit_insn (gen_lwsync ());
23180 case MEMMODEL_SEQ_CST
:
23181 emit_insn (gen_hwsync ());
23184 gcc_unreachable ();
23190 rs6000_post_atomic_barrier (enum memmodel model
)
23194 case MEMMODEL_RELAXED
:
23195 case MEMMODEL_CONSUME
:
23196 case MEMMODEL_RELEASE
:
23198 case MEMMODEL_ACQUIRE
:
23199 case MEMMODEL_ACQ_REL
:
23200 case MEMMODEL_SEQ_CST
:
23201 emit_insn (gen_isync ());
23204 gcc_unreachable ();
23208 /* A subroutine of the various atomic expanders. For sub-word operations,
23209 we must adjust things to operate on SImode. Given the original MEM,
23210 return a new aligned memory. Also build and return the quantities by
23211 which to shift and mask. */
23214 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
23216 rtx addr
, align
, shift
, mask
, mem
;
23217 HOST_WIDE_INT shift_mask
;
23218 machine_mode mode
= GET_MODE (orig_mem
);
23220 /* For smaller modes, we have to implement this via SImode. */
23221 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
23223 addr
= XEXP (orig_mem
, 0);
23224 addr
= force_reg (GET_MODE (addr
), addr
);
23226 /* Aligned memory containing subword. Generate a new memory. We
23227 do not want any of the existing MEM_ATTR data, as we're now
23228 accessing memory outside the original object. */
23229 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
23230 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23231 mem
= gen_rtx_MEM (SImode
, align
);
23232 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
23233 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
23234 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
23236 /* Shift amount for subword relative to aligned word. */
23237 shift
= gen_reg_rtx (SImode
);
23238 addr
= gen_lowpart (SImode
, addr
);
23239 rtx tmp
= gen_reg_rtx (SImode
);
23240 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
23241 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
23242 if (BYTES_BIG_ENDIAN
)
23243 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
23244 shift
, 1, OPTAB_LIB_WIDEN
);
23247 /* Mask for insertion. */
23248 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
23249 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23255 /* A subroutine of the various atomic expanders. For sub-word operands,
23256 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23259 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
23263 x
= gen_reg_rtx (SImode
);
23264 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
23265 gen_rtx_NOT (SImode
, mask
),
23268 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
23273 /* A subroutine of the various atomic expanders. For sub-word operands,
23274 extract WIDE to NARROW via SHIFT. */
23277 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
23279 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
23280 wide
, 1, OPTAB_LIB_WIDEN
);
23281 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
23284 /* Expand an atomic compare and swap operation. */
23287 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
23289 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
23290 rtx label1
, label2
, x
, mask
, shift
;
23291 machine_mode mode
, orig_mode
;
23292 enum memmodel mod_s
, mod_f
;
23295 boolval
= operands
[0];
23296 retval
= operands
[1];
23298 oldval
= operands
[3];
23299 newval
= operands
[4];
23300 is_weak
= (INTVAL (operands
[5]) != 0);
23301 mod_s
= memmodel_base (INTVAL (operands
[6]));
23302 mod_f
= memmodel_base (INTVAL (operands
[7]));
23303 orig_mode
= mode
= GET_MODE (mem
);
23305 mask
= shift
= NULL_RTX
;
23306 if (mode
== QImode
|| mode
== HImode
)
23308 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23309 lwarx and shift/mask operations. With power8, we need to do the
23310 comparison in SImode, but the store is still done in QI/HImode. */
23311 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
23313 if (!TARGET_SYNC_HI_QI
)
23315 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23317 /* Shift and mask OLDVAL into position with the word. */
23318 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
23319 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23321 /* Shift and mask NEWVAL into position within the word. */
23322 newval
= convert_modes (SImode
, mode
, newval
, 1);
23323 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
23324 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23327 /* Prepare to adjust the return value. */
23328 retval
= gen_reg_rtx (SImode
);
23331 else if (reg_overlap_mentioned_p (retval
, oldval
))
23332 oldval
= copy_to_reg (oldval
);
23334 if (mode
!= TImode
&& !reg_or_short_operand (oldval
, mode
))
23335 oldval
= copy_to_mode_reg (mode
, oldval
);
23337 if (reg_overlap_mentioned_p (retval
, newval
))
23338 newval
= copy_to_reg (newval
);
23340 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
23345 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23346 emit_label (XEXP (label1
, 0));
23348 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23350 emit_load_locked (mode
, retval
, mem
);
23354 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
23355 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23357 cond
= gen_reg_rtx (CCmode
);
23358 /* If we have TImode, synthesize a comparison. */
23359 if (mode
!= TImode
)
23360 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
23363 rtx xor1_result
= gen_reg_rtx (DImode
);
23364 rtx xor2_result
= gen_reg_rtx (DImode
);
23365 rtx or_result
= gen_reg_rtx (DImode
);
23366 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
23367 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
23368 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
23369 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
23371 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
23372 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
23373 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
23374 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
23377 emit_insn (gen_rtx_SET (cond
, x
));
23379 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23380 emit_unlikely_jump (x
, label2
);
23384 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
23386 emit_store_conditional (orig_mode
, cond
, mem
, x
);
23390 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23391 emit_unlikely_jump (x
, label1
);
23394 if (!is_mm_relaxed (mod_f
))
23395 emit_label (XEXP (label2
, 0));
23397 rs6000_post_atomic_barrier (mod_s
);
23399 if (is_mm_relaxed (mod_f
))
23400 emit_label (XEXP (label2
, 0));
23403 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
23404 else if (mode
!= GET_MODE (operands
[1]))
23405 convert_move (operands
[1], retval
, 1);
23407 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23408 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
23409 emit_insn (gen_rtx_SET (boolval
, x
));
23412 /* Expand an atomic exchange operation. */
23415 rs6000_expand_atomic_exchange (rtx operands
[])
23417 rtx retval
, mem
, val
, cond
;
23419 enum memmodel model
;
23420 rtx label
, x
, mask
, shift
;
23422 retval
= operands
[0];
23425 model
= memmodel_base (INTVAL (operands
[3]));
23426 mode
= GET_MODE (mem
);
23428 mask
= shift
= NULL_RTX
;
23429 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
23431 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23433 /* Shift and mask VAL into position with the word. */
23434 val
= convert_modes (SImode
, mode
, val
, 1);
23435 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23436 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23438 /* Prepare to adjust the return value. */
23439 retval
= gen_reg_rtx (SImode
);
23443 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23445 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23446 emit_label (XEXP (label
, 0));
23448 emit_load_locked (mode
, retval
, mem
);
23452 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
23454 cond
= gen_reg_rtx (CCmode
);
23455 emit_store_conditional (mode
, cond
, mem
, x
);
23457 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23458 emit_unlikely_jump (x
, label
);
23460 rs6000_post_atomic_barrier (model
);
23463 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
23466 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23467 to perform. MEM is the memory on which to operate. VAL is the second
23468 operand of the binary operator. BEFORE and AFTER are optional locations to
23469 return the value of MEM either before of after the operation. MODEL_RTX
23470 is a CONST_INT containing the memory model to use. */
23473 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
23474 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
23476 enum memmodel model
= memmodel_base (INTVAL (model_rtx
));
23477 machine_mode mode
= GET_MODE (mem
);
23478 machine_mode store_mode
= mode
;
23479 rtx label
, x
, cond
, mask
, shift
;
23480 rtx before
= orig_before
, after
= orig_after
;
23482 mask
= shift
= NULL_RTX
;
23483 /* On power8, we want to use SImode for the operation. On previous systems,
23484 use the operation in a subword and shift/mask to get the proper byte or
23486 if (mode
== QImode
|| mode
== HImode
)
23488 if (TARGET_SYNC_HI_QI
)
23490 val
= convert_modes (SImode
, mode
, val
, 1);
23492 /* Prepare to adjust the return value. */
23493 before
= gen_reg_rtx (SImode
);
23495 after
= gen_reg_rtx (SImode
);
23500 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23502 /* Shift and mask VAL into position with the word. */
23503 val
= convert_modes (SImode
, mode
, val
, 1);
23504 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23505 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23511 /* We've already zero-extended VAL. That is sufficient to
23512 make certain that it does not affect other bits. */
23517 /* If we make certain that all of the other bits in VAL are
23518 set, that will be sufficient to not affect other bits. */
23519 x
= gen_rtx_NOT (SImode
, mask
);
23520 x
= gen_rtx_IOR (SImode
, x
, val
);
23521 emit_insn (gen_rtx_SET (val
, x
));
23528 /* These will all affect bits outside the field and need
23529 adjustment via MASK within the loop. */
23533 gcc_unreachable ();
23536 /* Prepare to adjust the return value. */
23537 before
= gen_reg_rtx (SImode
);
23539 after
= gen_reg_rtx (SImode
);
23540 store_mode
= mode
= SImode
;
23544 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23546 label
= gen_label_rtx ();
23547 emit_label (label
);
23548 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
23550 if (before
== NULL_RTX
)
23551 before
= gen_reg_rtx (mode
);
23553 emit_load_locked (mode
, before
, mem
);
23557 x
= expand_simple_binop (mode
, AND
, before
, val
,
23558 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23559 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
23563 after
= expand_simple_binop (mode
, code
, before
, val
,
23564 after
, 1, OPTAB_LIB_WIDEN
);
23570 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
23571 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23572 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
23574 else if (store_mode
!= mode
)
23575 x
= convert_modes (store_mode
, mode
, x
, 1);
23577 cond
= gen_reg_rtx (CCmode
);
23578 emit_store_conditional (store_mode
, cond
, mem
, x
);
23580 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23581 emit_unlikely_jump (x
, label
);
23583 rs6000_post_atomic_barrier (model
);
23587 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23588 then do the calcuations in a SImode register. */
23590 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
23592 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
23594 else if (store_mode
!= mode
)
23596 /* QImode/HImode on machines with lbarx/lharx where we do the native
23597 operation and then do the calcuations in a SImode register. */
23599 convert_move (orig_before
, before
, 1);
23601 convert_move (orig_after
, after
, 1);
23603 else if (orig_after
&& after
!= orig_after
)
23604 emit_move_insn (orig_after
, after
);
23607 /* Emit instructions to move SRC to DST. Called by splitters for
23608 multi-register moves. It will emit at most one instruction for
23609 each register that is accessed; that is, it won't emit li/lis pairs
23610 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23614 rs6000_split_multireg_move (rtx dst
, rtx src
)
23616 /* The register number of the first register being moved. */
23618 /* The mode that is to be moved. */
23620 /* The mode that the move is being done in, and its size. */
23621 machine_mode reg_mode
;
23623 /* The number of registers that will be moved. */
23626 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
23627 mode
= GET_MODE (dst
);
23628 nregs
= hard_regno_nregs (reg
, mode
);
23629 if (FP_REGNO_P (reg
))
23630 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
23631 (TARGET_HARD_FLOAT
? DFmode
: SFmode
);
23632 else if (ALTIVEC_REGNO_P (reg
))
23633 reg_mode
= V16QImode
;
23635 reg_mode
= word_mode
;
23636 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
23638 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
23640 /* TDmode residing in FP registers is special, since the ISA requires that
23641 the lower-numbered word of a register pair is always the most significant
23642 word, even in little-endian mode. This does not match the usual subreg
23643 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23644 the appropriate constituent registers "by hand" in little-endian mode.
23646 Note we do not need to check for destructive overlap here since TDmode
23647 can only reside in even/odd register pairs. */
23648 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
23653 for (i
= 0; i
< nregs
; i
++)
23655 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
23656 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
23658 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
23659 i
* reg_mode_size
);
23661 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
23662 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
23664 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
23665 i
* reg_mode_size
);
23667 emit_insn (gen_rtx_SET (p_dst
, p_src
));
23673 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
23675 /* Move register range backwards, if we might have destructive
23678 for (i
= nregs
- 1; i
>= 0; i
--)
23679 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
23680 i
* reg_mode_size
),
23681 simplify_gen_subreg (reg_mode
, src
, mode
,
23682 i
* reg_mode_size
)));
23688 bool used_update
= false;
23689 rtx restore_basereg
= NULL_RTX
;
23691 if (MEM_P (src
) && INT_REGNO_P (reg
))
23695 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
23696 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
23699 breg
= XEXP (XEXP (src
, 0), 0);
23700 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
23701 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
23702 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
23703 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
23704 src
= replace_equiv_address (src
, breg
);
23706 else if (! rs6000_offsettable_memref_p (src
, reg_mode
, true))
23708 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
23710 rtx basereg
= XEXP (XEXP (src
, 0), 0);
23713 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
23714 emit_insn (gen_rtx_SET (ndst
,
23715 gen_rtx_MEM (reg_mode
,
23717 used_update
= true;
23720 emit_insn (gen_rtx_SET (basereg
,
23721 XEXP (XEXP (src
, 0), 1)));
23722 src
= replace_equiv_address (src
, basereg
);
23726 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
23727 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
23728 src
= replace_equiv_address (src
, basereg
);
23732 breg
= XEXP (src
, 0);
23733 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
23734 breg
= XEXP (breg
, 0);
23736 /* If the base register we are using to address memory is
23737 also a destination reg, then change that register last. */
23739 && REGNO (breg
) >= REGNO (dst
)
23740 && REGNO (breg
) < REGNO (dst
) + nregs
)
23741 j
= REGNO (breg
) - REGNO (dst
);
23743 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
23747 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
23748 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
23751 breg
= XEXP (XEXP (dst
, 0), 0);
23752 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
23753 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
23754 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
23756 /* We have to update the breg before doing the store.
23757 Use store with update, if available. */
23761 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
23762 emit_insn (TARGET_32BIT
23763 ? (TARGET_POWERPC64
23764 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
23765 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
23766 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
23767 used_update
= true;
23770 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
23771 dst
= replace_equiv_address (dst
, breg
);
23773 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
, true)
23774 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
23776 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
23778 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
23781 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
23782 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
23785 used_update
= true;
23788 emit_insn (gen_rtx_SET (basereg
,
23789 XEXP (XEXP (dst
, 0), 1)));
23790 dst
= replace_equiv_address (dst
, basereg
);
23794 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
23795 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
23796 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
23798 && REG_P (offsetreg
)
23799 && REGNO (basereg
) != REGNO (offsetreg
));
23800 if (REGNO (basereg
) == 0)
23802 rtx tmp
= offsetreg
;
23803 offsetreg
= basereg
;
23806 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
23807 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
23808 dst
= replace_equiv_address (dst
, basereg
);
23811 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
23812 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
, true));
23815 for (i
= 0; i
< nregs
; i
++)
23817 /* Calculate index to next subword. */
23822 /* If compiler already emitted move of first word by
23823 store with update, no need to do anything. */
23824 if (j
== 0 && used_update
)
23827 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
23828 j
* reg_mode_size
),
23829 simplify_gen_subreg (reg_mode
, src
, mode
,
23830 j
* reg_mode_size
)));
23832 if (restore_basereg
!= NULL_RTX
)
23833 emit_insn (restore_basereg
);
23838 /* This page contains routines that are used to determine what the
23839 function prologue and epilogue code will do and write them out. */
23841 /* Determine whether the REG is really used. */
23844 save_reg_p (int reg
)
23846 /* We need to mark the PIC offset register live for the same conditions
23847 as it is set up, or otherwise it won't be saved before we clobber it. */
23849 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
&& !TARGET_SINGLE_PIC_BASE
)
23851 /* When calling eh_return, we must return true for all the cases
23852 where conditional_register_usage marks the PIC offset reg
23854 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
23855 && (crtl
->calls_eh_return
23856 || df_regs_ever_live_p (reg
)
23857 || !constant_pool_empty_p ()))
23860 if ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
23865 return !call_used_regs
[reg
] && df_regs_ever_live_p (reg
);
23868 /* Return the first fixed-point register that is required to be
23869 saved. 32 if none. */
23872 first_reg_to_save (void)
23876 /* Find lowest numbered live register. */
23877 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
23878 if (save_reg_p (first_reg
))
23883 && crtl
->uses_pic_offset_table
23884 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
23885 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
23891 /* Similar, for FP regs. */
23894 first_fp_reg_to_save (void)
23898 /* Find lowest numbered live register. */
23899 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
23900 if (save_reg_p (first_reg
))
23906 /* Similar, for AltiVec regs. */
23909 first_altivec_reg_to_save (void)
23913 /* Stack frame remains as is unless we are in AltiVec ABI. */
23914 if (! TARGET_ALTIVEC_ABI
)
23915 return LAST_ALTIVEC_REGNO
+ 1;
23917 /* On Darwin, the unwind routines are compiled without
23918 TARGET_ALTIVEC, and use save_world to save/restore the
23919 altivec registers when necessary. */
23920 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
23921 && ! TARGET_ALTIVEC
)
23922 return FIRST_ALTIVEC_REGNO
+ 20;
23924 /* Find lowest numbered live register. */
23925 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23926 if (save_reg_p (i
))
23932 /* Return a 32-bit mask of the AltiVec registers we need to set in
23933 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23934 the 32-bit word is 0. */
23936 static unsigned int
23937 compute_vrsave_mask (void)
23939 unsigned int i
, mask
= 0;
23941 /* On Darwin, the unwind routines are compiled without
23942 TARGET_ALTIVEC, and use save_world to save/restore the
23943 call-saved altivec registers when necessary. */
23944 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
23945 && ! TARGET_ALTIVEC
)
23948 /* First, find out if we use _any_ altivec registers. */
23949 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23950 if (df_regs_ever_live_p (i
))
23951 mask
|= ALTIVEC_REG_BIT (i
);
23956 /* Next, remove the argument registers from the set. These must
23957 be in the VRSAVE mask set by the caller, so we don't need to add
23958 them in again. More importantly, the mask we compute here is
23959 used to generate CLOBBERs in the set_vrsave insn, and we do not
23960 wish the argument registers to die. */
23961 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
23962 mask
&= ~ALTIVEC_REG_BIT (i
);
23964 /* Similarly, remove the return value from the set. */
23967 diddle_return_value (is_altivec_return_reg
, &yes
);
23969 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
23975 /* For a very restricted set of circumstances, we can cut down the
23976 size of prologues/epilogues by calling our own save/restore-the-world
23980 compute_save_world_info (rs6000_stack_t
*info
)
23982 info
->world_save_p
= 1;
23984 = (WORLD_SAVE_P (info
)
23985 && DEFAULT_ABI
== ABI_DARWIN
23986 && !cfun
->has_nonlocal_label
23987 && info
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
23988 && info
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
23989 && info
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
23990 && info
->cr_save_p
);
23992 /* This will not work in conjunction with sibcalls. Make sure there
23993 are none. (This check is expensive, but seldom executed.) */
23994 if (WORLD_SAVE_P (info
))
23997 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
23998 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
24000 info
->world_save_p
= 0;
24005 if (WORLD_SAVE_P (info
))
24007 /* Even if we're not touching VRsave, make sure there's room on the
24008 stack for it, if it looks like we're calling SAVE_WORLD, which
24009 will attempt to save it. */
24010 info
->vrsave_size
= 4;
24012 /* If we are going to save the world, we need to save the link register too. */
24013 info
->lr_save_p
= 1;
24015 /* "Save" the VRsave register too if we're saving the world. */
24016 if (info
->vrsave_mask
== 0)
24017 info
->vrsave_mask
= compute_vrsave_mask ();
24019 /* Because the Darwin register save/restore routines only handle
24020 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24022 gcc_assert (info
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
24023 && (info
->first_altivec_reg_save
24024 >= FIRST_SAVED_ALTIVEC_REGNO
));
24032 is_altivec_return_reg (rtx reg
, void *xyes
)
24034 bool *yes
= (bool *) xyes
;
24035 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
24040 /* Return whether REG is a global user reg or has been specifed by
24041 -ffixed-REG. We should not restore these, and so cannot use
24042 lmw or out-of-line restore functions if there are any. We also
24043 can't save them (well, emit frame notes for them), because frame
24044 unwinding during exception handling will restore saved registers. */
24047 fixed_reg_p (int reg
)
24049 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24050 backend sets it, overriding anything the user might have given. */
24051 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
24052 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
)
24053 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
24054 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
24057 return fixed_regs
[reg
];
24060 /* Determine the strategy for savings/restoring registers. */
24063 SAVE_MULTIPLE
= 0x1,
24064 SAVE_INLINE_GPRS
= 0x2,
24065 SAVE_INLINE_FPRS
= 0x4,
24066 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x8,
24067 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x10,
24068 SAVE_INLINE_VRS
= 0x20,
24069 REST_MULTIPLE
= 0x100,
24070 REST_INLINE_GPRS
= 0x200,
24071 REST_INLINE_FPRS
= 0x400,
24072 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x800,
24073 REST_INLINE_VRS
= 0x1000
24077 rs6000_savres_strategy (rs6000_stack_t
*info
,
24078 bool using_static_chain_p
)
24082 /* Select between in-line and out-of-line save and restore of regs.
24083 First, all the obvious cases where we don't use out-of-line. */
24084 if (crtl
->calls_eh_return
24085 || cfun
->machine
->ra_need_lr
)
24086 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
24087 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
24088 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
24090 if (info
->first_gp_reg_save
== 32)
24091 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24093 if (info
->first_fp_reg_save
== 64)
24094 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24096 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1)
24097 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24099 /* Define cutoff for using out-of-line functions to save registers. */
24100 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
24102 if (!optimize_size
)
24104 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24105 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24106 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24110 /* Prefer out-of-line restore if it will exit. */
24111 if (info
->first_fp_reg_save
> 61)
24112 strategy
|= SAVE_INLINE_FPRS
;
24113 if (info
->first_gp_reg_save
> 29)
24115 if (info
->first_fp_reg_save
== 64)
24116 strategy
|= SAVE_INLINE_GPRS
;
24118 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24120 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
24121 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24124 else if (DEFAULT_ABI
== ABI_DARWIN
)
24126 if (info
->first_fp_reg_save
> 60)
24127 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24128 if (info
->first_gp_reg_save
> 29)
24129 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24130 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24134 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
24135 if ((flag_shrink_wrap_separate
&& optimize_function_for_speed_p (cfun
))
24136 || info
->first_fp_reg_save
> 61)
24137 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24138 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24139 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24142 /* Don't bother to try to save things out-of-line if r11 is occupied
24143 by the static chain. It would require too much fiddling and the
24144 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24145 pointer on Darwin, and AIX uses r1 or r12. */
24146 if (using_static_chain_p
24147 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
24148 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
24150 | SAVE_INLINE_VRS
);
24152 /* Don't ever restore fixed regs. That means we can't use the
24153 out-of-line register restore functions if a fixed reg is in the
24154 range of regs restored. */
24155 if (!(strategy
& REST_INLINE_FPRS
))
24156 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
24159 strategy
|= REST_INLINE_FPRS
;
24163 /* We can only use the out-of-line routines to restore fprs if we've
24164 saved all the registers from first_fp_reg_save in the prologue.
24165 Otherwise, we risk loading garbage. Of course, if we have saved
24166 out-of-line then we know we haven't skipped any fprs. */
24167 if ((strategy
& SAVE_INLINE_FPRS
)
24168 && !(strategy
& REST_INLINE_FPRS
))
24169 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
24170 if (!save_reg_p (i
))
24172 strategy
|= REST_INLINE_FPRS
;
24176 /* Similarly, for altivec regs. */
24177 if (!(strategy
& REST_INLINE_VRS
))
24178 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
24181 strategy
|= REST_INLINE_VRS
;
24185 if ((strategy
& SAVE_INLINE_VRS
)
24186 && !(strategy
& REST_INLINE_VRS
))
24187 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
24188 if (!save_reg_p (i
))
24190 strategy
|= REST_INLINE_VRS
;
24194 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24195 saved is an out-of-line save or restore. Set up the value for
24196 the next test (excluding out-of-line gprs). */
24197 bool lr_save_p
= (info
->lr_save_p
24198 || !(strategy
& SAVE_INLINE_FPRS
)
24199 || !(strategy
& SAVE_INLINE_VRS
)
24200 || !(strategy
& REST_INLINE_FPRS
)
24201 || !(strategy
& REST_INLINE_VRS
));
24203 if (TARGET_MULTIPLE
24204 && !TARGET_POWERPC64
24205 && info
->first_gp_reg_save
< 31
24206 && !(flag_shrink_wrap
24207 && flag_shrink_wrap_separate
24208 && optimize_function_for_speed_p (cfun
)))
24211 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24212 if (save_reg_p (i
))
24216 /* Don't use store multiple if only one reg needs to be
24217 saved. This can occur for example when the ABI_V4 pic reg
24218 (r30) needs to be saved to make calls, but r31 is not
24220 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24223 /* Prefer store multiple for saves over out-of-line
24224 routines, since the store-multiple instruction will
24225 always be smaller. */
24226 strategy
|= SAVE_INLINE_GPRS
| SAVE_MULTIPLE
;
24228 /* The situation is more complicated with load multiple.
24229 We'd prefer to use the out-of-line routines for restores,
24230 since the "exit" out-of-line routines can handle the
24231 restore of LR and the frame teardown. However if doesn't
24232 make sense to use the out-of-line routine if that is the
24233 only reason we'd need to save LR, and we can't use the
24234 "exit" out-of-line gpr restore if we have saved some
24235 fprs; In those cases it is advantageous to use load
24236 multiple when available. */
24237 if (info
->first_fp_reg_save
!= 64 || !lr_save_p
)
24238 strategy
|= REST_INLINE_GPRS
| REST_MULTIPLE
;
24242 /* Using the "exit" out-of-line routine does not improve code size
24243 if using it would require lr to be saved and if only saving one
24245 else if (!lr_save_p
&& info
->first_gp_reg_save
> 29)
24246 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24248 /* Don't ever restore fixed regs. */
24249 if ((strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
24250 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24251 if (fixed_reg_p (i
))
24253 strategy
|= REST_INLINE_GPRS
;
24254 strategy
&= ~REST_MULTIPLE
;
24258 /* We can only use load multiple or the out-of-line routines to
24259 restore gprs if we've saved all the registers from
24260 first_gp_reg_save. Otherwise, we risk loading garbage.
24261 Of course, if we have saved out-of-line or used stmw then we know
24262 we haven't skipped any gprs. */
24263 if ((strategy
& (SAVE_INLINE_GPRS
| SAVE_MULTIPLE
)) == SAVE_INLINE_GPRS
24264 && (strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
24265 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24266 if (!save_reg_p (i
))
24268 strategy
|= REST_INLINE_GPRS
;
24269 strategy
&= ~REST_MULTIPLE
;
24273 if (TARGET_ELF
&& TARGET_64BIT
)
24275 if (!(strategy
& SAVE_INLINE_FPRS
))
24276 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
24277 else if (!(strategy
& SAVE_INLINE_GPRS
)
24278 && info
->first_fp_reg_save
== 64)
24279 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
24281 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
24282 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
24284 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
24285 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
24290 /* Calculate the stack information for the current function. This is
24291 complicated by having two separate calling sequences, the AIX calling
24292 sequence and the V.4 calling sequence.
24294 AIX (and Darwin/Mac OS X) stack frames look like:
24296 SP----> +---------------------------------------+
24297 | back chain to caller | 0 0
24298 +---------------------------------------+
24299 | saved CR | 4 8 (8-11)
24300 +---------------------------------------+
24302 +---------------------------------------+
24303 | reserved for compilers | 12 24
24304 +---------------------------------------+
24305 | reserved for binders | 16 32
24306 +---------------------------------------+
24307 | saved TOC pointer | 20 40
24308 +---------------------------------------+
24309 | Parameter save area (+padding*) (P) | 24 48
24310 +---------------------------------------+
24311 | Alloca space (A) | 24+P etc.
24312 +---------------------------------------+
24313 | Local variable space (L) | 24+P+A
24314 +---------------------------------------+
24315 | Float/int conversion temporary (X) | 24+P+A+L
24316 +---------------------------------------+
24317 | Save area for AltiVec registers (W) | 24+P+A+L+X
24318 +---------------------------------------+
24319 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24320 +---------------------------------------+
24321 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24322 +---------------------------------------+
24323 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24324 +---------------------------------------+
24325 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24326 +---------------------------------------+
24327 old SP->| back chain to caller's caller |
24328 +---------------------------------------+
24330 * If the alloca area is present, the parameter save area is
24331 padded so that the former starts 16-byte aligned.
24333 The required alignment for AIX configurations is two words (i.e., 8
24336 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24338 SP----> +---------------------------------------+
24339 | Back chain to caller | 0
24340 +---------------------------------------+
24341 | Save area for CR | 8
24342 +---------------------------------------+
24344 +---------------------------------------+
24345 | Saved TOC pointer | 24
24346 +---------------------------------------+
24347 | Parameter save area (+padding*) (P) | 32
24348 +---------------------------------------+
24349 | Alloca space (A) | 32+P
24350 +---------------------------------------+
24351 | Local variable space (L) | 32+P+A
24352 +---------------------------------------+
24353 | Save area for AltiVec registers (W) | 32+P+A+L
24354 +---------------------------------------+
24355 | AltiVec alignment padding (Y) | 32+P+A+L+W
24356 +---------------------------------------+
24357 | Save area for GP registers (G) | 32+P+A+L+W+Y
24358 +---------------------------------------+
24359 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24360 +---------------------------------------+
24361 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24362 +---------------------------------------+
24364 * If the alloca area is present, the parameter save area is
24365 padded so that the former starts 16-byte aligned.
24367 V.4 stack frames look like:
24369 SP----> +---------------------------------------+
24370 | back chain to caller | 0
24371 +---------------------------------------+
24372 | caller's saved LR | 4
24373 +---------------------------------------+
24374 | Parameter save area (+padding*) (P) | 8
24375 +---------------------------------------+
24376 | Alloca space (A) | 8+P
24377 +---------------------------------------+
24378 | Varargs save area (V) | 8+P+A
24379 +---------------------------------------+
24380 | Local variable space (L) | 8+P+A+V
24381 +---------------------------------------+
24382 | Float/int conversion temporary (X) | 8+P+A+V+L
24383 +---------------------------------------+
24384 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24385 +---------------------------------------+
24386 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24387 +---------------------------------------+
24388 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24389 +---------------------------------------+
24390 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24391 +---------------------------------------+
24392 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24393 +---------------------------------------+
24394 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24395 +---------------------------------------+
24396 old SP->| back chain to caller's caller |
24397 +---------------------------------------+
24399 * If the alloca area is present and the required alignment is
24400 16 bytes, the parameter save area is padded so that the
24401 alloca area starts 16-byte aligned.
24403 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24404 given. (But note below and in sysv4.h that we require only 8 and
24405 may round up the size of our stack frame anyways. The historical
24406 reason is early versions of powerpc-linux which didn't properly
24407 align the stack at program startup. A happy side-effect is that
24408 -mno-eabi libraries can be used with -meabi programs.)
24410 The EABI configuration defaults to the V.4 layout. However,
24411 the stack alignment requirements may differ. If -mno-eabi is not
24412 given, the required stack alignment is 8 bytes; if -mno-eabi is
24413 given, the required alignment is 16 bytes. (But see V.4 comment
24416 #ifndef ABI_STACK_BOUNDARY
24417 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24420 static rs6000_stack_t
*
24421 rs6000_stack_info (void)
24423 /* We should never be called for thunks, we are not set up for that. */
24424 gcc_assert (!cfun
->is_thunk
);
24426 rs6000_stack_t
*info
= &stack_info
;
24427 int reg_size
= TARGET_32BIT
? 4 : 8;
24432 HOST_WIDE_INT non_fixed_size
;
24433 bool using_static_chain_p
;
24435 if (reload_completed
&& info
->reload_completed
)
24438 memset (info
, 0, sizeof (*info
));
24439 info
->reload_completed
= reload_completed
;
24441 /* Select which calling sequence. */
24442 info
->abi
= DEFAULT_ABI
;
24444 /* Calculate which registers need to be saved & save area size. */
24445 info
->first_gp_reg_save
= first_reg_to_save ();
24446 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24447 even if it currently looks like we won't. Reload may need it to
24448 get at a constant; if so, it will have already created a constant
24449 pool entry for it. */
24450 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
24451 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
24452 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
24453 && crtl
->uses_const_pool
24454 && info
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
24455 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
24457 first_gp
= info
->first_gp_reg_save
;
24459 info
->gp_size
= reg_size
* (32 - first_gp
);
24461 info
->first_fp_reg_save
= first_fp_reg_to_save ();
24462 info
->fp_size
= 8 * (64 - info
->first_fp_reg_save
);
24464 info
->first_altivec_reg_save
= first_altivec_reg_to_save ();
24465 info
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
24466 - info
->first_altivec_reg_save
);
24468 /* Does this function call anything? */
24469 info
->calls_p
= (!crtl
->is_leaf
|| cfun
->machine
->ra_needs_full_frame
);
24471 /* Determine if we need to save the condition code registers. */
24472 if (save_reg_p (CR2_REGNO
)
24473 || save_reg_p (CR3_REGNO
)
24474 || save_reg_p (CR4_REGNO
))
24476 info
->cr_save_p
= 1;
24477 if (DEFAULT_ABI
== ABI_V4
)
24478 info
->cr_size
= reg_size
;
24481 /* If the current function calls __builtin_eh_return, then we need
24482 to allocate stack space for registers that will hold data for
24483 the exception handler. */
24484 if (crtl
->calls_eh_return
)
24487 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
24490 ehrd_size
= i
* UNITS_PER_WORD
;
24495 /* In the ELFv2 ABI, we also need to allocate space for separate
24496 CR field save areas if the function calls __builtin_eh_return. */
24497 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24499 /* This hard-codes that we have three call-saved CR fields. */
24500 ehcr_size
= 3 * reg_size
;
24501 /* We do *not* use the regular CR save mechanism. */
24502 info
->cr_save_p
= 0;
24507 /* Determine various sizes. */
24508 info
->reg_size
= reg_size
;
24509 info
->fixed_size
= RS6000_SAVE_AREA
;
24510 info
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
24511 if (cfun
->calls_alloca
)
24513 RS6000_ALIGN (crtl
->outgoing_args_size
+ info
->fixed_size
,
24514 STACK_BOUNDARY
/ BITS_PER_UNIT
) - info
->fixed_size
;
24516 info
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
24517 TARGET_ALTIVEC
? 16 : 8);
24518 if (FRAME_GROWS_DOWNWARD
)
24520 += RS6000_ALIGN (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
,
24521 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
24522 - (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
);
24524 if (TARGET_ALTIVEC_ABI
)
24525 info
->vrsave_mask
= compute_vrsave_mask ();
24527 if (TARGET_ALTIVEC_VRSAVE
&& info
->vrsave_mask
)
24528 info
->vrsave_size
= 4;
24530 compute_save_world_info (info
);
24532 /* Calculate the offsets. */
24533 switch (DEFAULT_ABI
)
24537 gcc_unreachable ();
24542 info
->fp_save_offset
= -info
->fp_size
;
24543 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24545 if (TARGET_ALTIVEC_ABI
)
24547 info
->vrsave_save_offset
= info
->gp_save_offset
- info
->vrsave_size
;
24549 /* Align stack so vector save area is on a quadword boundary.
24550 The padding goes above the vectors. */
24551 if (info
->altivec_size
!= 0)
24552 info
->altivec_padding_size
= info
->vrsave_save_offset
& 0xF;
24554 info
->altivec_save_offset
= info
->vrsave_save_offset
24555 - info
->altivec_padding_size
24556 - info
->altivec_size
;
24557 gcc_assert (info
->altivec_size
== 0
24558 || info
->altivec_save_offset
% 16 == 0);
24560 /* Adjust for AltiVec case. */
24561 info
->ehrd_offset
= info
->altivec_save_offset
- ehrd_size
;
24564 info
->ehrd_offset
= info
->gp_save_offset
- ehrd_size
;
24566 info
->ehcr_offset
= info
->ehrd_offset
- ehcr_size
;
24567 info
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
24568 info
->lr_save_offset
= 2*reg_size
;
24572 info
->fp_save_offset
= -info
->fp_size
;
24573 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24574 info
->cr_save_offset
= info
->gp_save_offset
- info
->cr_size
;
24576 if (TARGET_ALTIVEC_ABI
)
24578 info
->vrsave_save_offset
= info
->cr_save_offset
- info
->vrsave_size
;
24580 /* Align stack so vector save area is on a quadword boundary. */
24581 if (info
->altivec_size
!= 0)
24582 info
->altivec_padding_size
= 16 - (-info
->vrsave_save_offset
% 16);
24584 info
->altivec_save_offset
= info
->vrsave_save_offset
24585 - info
->altivec_padding_size
24586 - info
->altivec_size
;
24588 /* Adjust for AltiVec case. */
24589 info
->ehrd_offset
= info
->altivec_save_offset
;
24592 info
->ehrd_offset
= info
->cr_save_offset
;
24594 info
->ehrd_offset
-= ehrd_size
;
24595 info
->lr_save_offset
= reg_size
;
24598 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
24599 info
->save_size
= RS6000_ALIGN (info
->fp_size
24601 + info
->altivec_size
24602 + info
->altivec_padding_size
24606 + info
->vrsave_size
,
24609 non_fixed_size
= info
->vars_size
+ info
->parm_size
+ info
->save_size
;
24611 info
->total_size
= RS6000_ALIGN (non_fixed_size
+ info
->fixed_size
,
24612 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
24614 /* Determine if we need to save the link register. */
24616 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24618 && !TARGET_PROFILE_KERNEL
)
24619 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
24620 #ifdef TARGET_RELOCATABLE
24621 || (DEFAULT_ABI
== ABI_V4
24622 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
24623 && !constant_pool_empty_p ())
24625 || rs6000_ra_ever_killed ())
24626 info
->lr_save_p
= 1;
24628 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
24629 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
24630 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
24631 info
->savres_strategy
= rs6000_savres_strategy (info
, using_static_chain_p
);
24633 if (!(info
->savres_strategy
& SAVE_INLINE_GPRS
)
24634 || !(info
->savres_strategy
& SAVE_INLINE_FPRS
)
24635 || !(info
->savres_strategy
& SAVE_INLINE_VRS
)
24636 || !(info
->savres_strategy
& REST_INLINE_GPRS
)
24637 || !(info
->savres_strategy
& REST_INLINE_FPRS
)
24638 || !(info
->savres_strategy
& REST_INLINE_VRS
))
24639 info
->lr_save_p
= 1;
24641 if (info
->lr_save_p
)
24642 df_set_regs_ever_live (LR_REGNO
, true);
24644 /* Determine if we need to allocate any stack frame:
24646 For AIX we need to push the stack if a frame pointer is needed
24647 (because the stack might be dynamically adjusted), if we are
24648 debugging, if we make calls, or if the sum of fp_save, gp_save,
24649 and local variables are more than the space needed to save all
24650 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24651 + 18*8 = 288 (GPR13 reserved).
24653 For V.4 we don't have the stack cushion that AIX uses, but assume
24654 that the debugger can handle stackless frames. */
24659 else if (DEFAULT_ABI
== ABI_V4
)
24660 info
->push_p
= non_fixed_size
!= 0;
24662 else if (frame_pointer_needed
)
24665 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
24669 info
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
24675 debug_stack_info (rs6000_stack_t
*info
)
24677 const char *abi_string
;
24680 info
= rs6000_stack_info ();
24682 fprintf (stderr
, "\nStack information for function %s:\n",
24683 ((current_function_decl
&& DECL_NAME (current_function_decl
))
24684 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
24689 default: abi_string
= "Unknown"; break;
24690 case ABI_NONE
: abi_string
= "NONE"; break;
24691 case ABI_AIX
: abi_string
= "AIX"; break;
24692 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
24693 case ABI_DARWIN
: abi_string
= "Darwin"; break;
24694 case ABI_V4
: abi_string
= "V.4"; break;
24697 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
24699 if (TARGET_ALTIVEC_ABI
)
24700 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
24702 if (info
->first_gp_reg_save
!= 32)
24703 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
24705 if (info
->first_fp_reg_save
!= 64)
24706 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
24708 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
24709 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
24710 info
->first_altivec_reg_save
);
24712 if (info
->lr_save_p
)
24713 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
24715 if (info
->cr_save_p
)
24716 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
24718 if (info
->vrsave_mask
)
24719 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
24722 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
24725 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
24728 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
24731 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
24733 if (info
->altivec_size
)
24734 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
24735 info
->altivec_save_offset
);
24737 if (info
->vrsave_size
)
24738 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
24739 info
->vrsave_save_offset
);
24741 if (info
->lr_save_p
)
24742 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
24744 if (info
->cr_save_p
)
24745 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
24747 if (info
->varargs_save_offset
)
24748 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
24750 if (info
->total_size
)
24751 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
24754 if (info
->vars_size
)
24755 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
24758 if (info
->parm_size
)
24759 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
24761 if (info
->fixed_size
)
24762 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
24765 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
24768 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
24770 if (info
->altivec_size
)
24771 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
24773 if (info
->vrsave_size
)
24774 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
24776 if (info
->altivec_padding_size
)
24777 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
24778 info
->altivec_padding_size
);
24781 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
24783 if (info
->save_size
)
24784 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
24786 if (info
->reg_size
!= 4)
24787 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
24789 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
24791 fprintf (stderr
, "\n");
24795 rs6000_return_addr (int count
, rtx frame
)
24797 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24798 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24800 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
24802 cfun
->machine
->ra_needs_full_frame
= 1;
24805 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24806 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24807 frame
= stack_pointer_rtx
;
24808 rtx prev_frame_addr
= memory_address (Pmode
, frame
);
24809 rtx prev_frame
= copy_to_reg (gen_rtx_MEM (Pmode
, prev_frame_addr
));
24810 rtx lr_save_off
= plus_constant (Pmode
,
24811 prev_frame
, RETURN_ADDRESS_OFFSET
);
24812 rtx lr_save_addr
= memory_address (Pmode
, lr_save_off
);
24813 return gen_rtx_MEM (Pmode
, lr_save_addr
);
24816 cfun
->machine
->ra_need_lr
= 1;
24817 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
24820 /* Say whether a function is a candidate for sibcall handling or not. */
24823 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
24827 /* The sibcall epilogue may clobber the static chain register.
24828 ??? We could work harder and avoid that, but it's probably
24829 not worth the hassle in practice. */
24830 if (CALL_EXPR_STATIC_CHAIN (exp
))
24834 fntype
= TREE_TYPE (decl
);
24836 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
24838 /* We can't do it if the called function has more vector parameters
24839 than the current function; there's nowhere to put the VRsave code. */
24840 if (TARGET_ALTIVEC_ABI
24841 && TARGET_ALTIVEC_VRSAVE
24842 && !(decl
&& decl
== current_function_decl
))
24844 function_args_iterator args_iter
;
24848 /* Functions with vector parameters are required to have a
24849 prototype, so the argument type info must be available
24851 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
24852 if (TREE_CODE (type
) == VECTOR_TYPE
24853 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
24856 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
24857 if (TREE_CODE (type
) == VECTOR_TYPE
24858 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
24865 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24866 functions, because the callee may have a different TOC pointer to
24867 the caller and there's no way to ensure we restore the TOC when
24868 we return. With the secure-plt SYSV ABI we can't make non-local
24869 calls when -fpic/PIC because the plt call stubs use r30. */
24870 if (DEFAULT_ABI
== ABI_DARWIN
24871 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24873 && !DECL_EXTERNAL (decl
)
24874 && !DECL_WEAK (decl
)
24875 && (*targetm
.binds_local_p
) (decl
))
24876 || (DEFAULT_ABI
== ABI_V4
24877 && (!TARGET_SECURE_PLT
24880 && (*targetm
.binds_local_p
) (decl
)))))
24882 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
24884 if (!lookup_attribute ("longcall", attr_list
)
24885 || lookup_attribute ("shortcall", attr_list
))
24893 rs6000_ra_ever_killed (void)
24899 if (cfun
->is_thunk
)
24902 if (cfun
->machine
->lr_save_state
)
24903 return cfun
->machine
->lr_save_state
- 1;
24905 /* regs_ever_live has LR marked as used if any sibcalls are present,
24906 but this should not force saving and restoring in the
24907 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24908 clobbers LR, so that is inappropriate. */
24910 /* Also, the prologue can generate a store into LR that
24911 doesn't really count, like this:
24914 bcl to set PIC register
24918 When we're called from the epilogue, we need to avoid counting
24919 this as a store. */
24921 push_topmost_sequence ();
24922 top
= get_insns ();
24923 pop_topmost_sequence ();
24924 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
24926 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
24932 if (!SIBLING_CALL_P (insn
))
24935 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
24937 else if (set_of (reg
, insn
) != NULL_RTX
24938 && !prologue_epilogue_contains (insn
))
24945 /* Emit instructions needed to load the TOC register.
24946 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24947 a constant pool; or for SVR4 -fpic. */
24950 rs6000_emit_load_toc_table (int fromprolog
)
24953 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
24955 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
24958 rtx lab
, tmp1
, tmp2
, got
;
24960 lab
= gen_label_rtx ();
24961 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
24962 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
24965 got
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
24969 got
= rs6000_got_sym ();
24970 tmp1
= tmp2
= dest
;
24973 tmp1
= gen_reg_rtx (Pmode
);
24974 tmp2
= gen_reg_rtx (Pmode
);
24976 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
24977 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
24978 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
24979 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
24981 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
24983 emit_insn (gen_load_toc_v4_pic_si ());
24984 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
24986 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
24989 rtx temp0
= (fromprolog
24990 ? gen_rtx_REG (Pmode
, 0)
24991 : gen_reg_rtx (Pmode
));
24997 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
24998 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25000 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
25001 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25003 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
25004 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25005 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
25011 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25013 lab
= gen_label_rtx ();
25014 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
25015 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25016 if (TARGET_LINK_STACK
)
25017 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
25018 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
25020 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
25022 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
25024 /* This is for AIX code running in non-PIC ELF32. */
25025 rtx realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25028 emit_insn (gen_elf_high (dest
, realsym
));
25029 emit_insn (gen_elf_low (dest
, dest
, realsym
));
25033 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
25036 emit_insn (gen_load_toc_aix_si (dest
));
25038 emit_insn (gen_load_toc_aix_di (dest
));
25042 /* Emit instructions to restore the link register after determining where
25043 its value has been stored. */
25046 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
25048 rs6000_stack_t
*info
= rs6000_stack_info ();
25051 operands
[0] = source
;
25052 operands
[1] = scratch
;
25054 if (info
->lr_save_p
)
25056 rtx frame_rtx
= stack_pointer_rtx
;
25057 HOST_WIDE_INT sp_offset
= 0;
25060 if (frame_pointer_needed
25061 || cfun
->calls_alloca
25062 || info
->total_size
> 32767)
25064 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
25065 emit_move_insn (operands
[1], tmp
);
25066 frame_rtx
= operands
[1];
25068 else if (info
->push_p
)
25069 sp_offset
= info
->total_size
;
25071 tmp
= plus_constant (Pmode
, frame_rtx
,
25072 info
->lr_save_offset
+ sp_offset
);
25073 tmp
= gen_frame_mem (Pmode
, tmp
);
25074 emit_move_insn (tmp
, operands
[0]);
25077 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
25079 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25080 state of lr_save_p so any change from here on would be a bug. In
25081 particular, stop rs6000_ra_ever_killed from considering the SET
25082 of lr we may have added just above. */
25083 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
25086 static GTY(()) alias_set_type set
= -1;
25089 get_TOC_alias_set (void)
25092 set
= new_alias_set ();
25096 /* This returns nonzero if the current function uses the TOC. This is
25097 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25098 is generated by the ABI_V4 load_toc_* patterns.
25099 Return 2 instead of 1 if the load_toc_* pattern is in the function
25100 partition that doesn't start the function. */
25108 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
25112 rtx pat
= PATTERN (insn
);
25115 if (GET_CODE (pat
) == PARALLEL
)
25116 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
25118 rtx sub
= XVECEXP (pat
, 0, i
);
25119 if (GET_CODE (sub
) == USE
)
25121 sub
= XEXP (sub
, 0);
25122 if (GET_CODE (sub
) == UNSPEC
25123 && XINT (sub
, 1) == UNSPEC_TOC
)
25128 else if (crtl
->has_bb_partition
25130 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
25138 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
25140 rtx tocrel
, tocreg
, hi
;
25142 if (TARGET_DEBUG_ADDR
)
25144 if (GET_CODE (symbol
) == SYMBOL_REF
)
25145 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25149 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
25150 GET_RTX_NAME (GET_CODE (symbol
)));
25151 debug_rtx (symbol
);
25155 if (!can_create_pseudo_p ())
25156 df_set_regs_ever_live (TOC_REGISTER
, true);
25158 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
25159 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
25160 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
25163 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
25164 if (largetoc_reg
!= NULL
)
25166 emit_move_insn (largetoc_reg
, hi
);
25169 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
25172 /* Issue assembly directives that create a reference to the given DWARF
25173 FRAME_TABLE_LABEL from the current function section. */
25175 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
25177 fprintf (asm_out_file
, "\t.ref %s\n",
25178 (* targetm
.strip_name_encoding
) (frame_table_label
));
25181 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25182 and the change to the stack pointer. */
25185 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
25192 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
25193 if (hard_frame_needed
)
25194 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
25195 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
25196 || (hard_frame_needed
25197 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
25200 p
= rtvec_alloc (i
);
25203 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
25204 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
25207 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
25210 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25211 and set the appropriate attributes for the generated insn. Return the
25212 first insn which adjusts the stack pointer or the last insn before
25213 the stack adjustment loop.
25215 SIZE_INT is used to create the CFI note for the allocation.
25217 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25218 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25220 ORIG_SP contains the backchain value that must be stored at *sp. */
25223 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int
, rtx orig_sp
)
25227 rtx size_rtx
= GEN_INT (-size_int
);
25228 if (size_int
> 32767)
25230 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
25231 /* Need a note here so that try_split doesn't get confused. */
25232 if (get_last_insn () == NULL_RTX
)
25233 emit_note (NOTE_INSN_DELETED
);
25234 insn
= emit_move_insn (tmp_reg
, size_rtx
);
25235 try_split (PATTERN (insn
), insn
, 0);
25236 size_rtx
= tmp_reg
;
25239 if (Pmode
== SImode
)
25240 insn
= emit_insn (gen_movsi_update_stack (stack_pointer_rtx
,
25245 insn
= emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx
,
25249 rtx par
= PATTERN (insn
);
25250 gcc_assert (GET_CODE (par
) == PARALLEL
);
25251 rtx set
= XVECEXP (par
, 0, 0);
25252 gcc_assert (GET_CODE (set
) == SET
);
25253 rtx mem
= SET_DEST (set
);
25254 gcc_assert (MEM_P (mem
));
25255 MEM_NOTRAP_P (mem
) = 1;
25256 set_mem_alias_set (mem
, get_frame_alias_set ());
25258 RTX_FRAME_RELATED_P (insn
) = 1;
25259 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25260 gen_rtx_SET (stack_pointer_rtx
,
25261 gen_rtx_PLUS (Pmode
,
25263 GEN_INT (-size_int
))));
25265 /* Emit a blockage to ensure the allocation/probing insns are
25266 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25267 note for similar reasons. */
25268 if (flag_stack_clash_protection
)
25270 add_reg_note (insn
, REG_STACK_CHECK
, const0_rtx
);
25271 emit_insn (gen_blockage ());
25277 static HOST_WIDE_INT
25278 get_stack_clash_protection_probe_interval (void)
25280 return (HOST_WIDE_INT_1U
25281 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
));
25284 static HOST_WIDE_INT
25285 get_stack_clash_protection_guard_size (void)
25287 return (HOST_WIDE_INT_1U
25288 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE
));
25291 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25292 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25294 COPY_REG, if non-null, should contain a copy of the original
25295 stack pointer at exit from this function.
25297 This is subtly different than the Ada probing in that it tries hard to
25298 prevent attacks that jump the stack guard. Thus it is never allowed to
25299 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25300 space without a suitable probe. */
25302 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size
,
25305 rtx orig_sp
= copy_reg
;
25307 HOST_WIDE_INT probe_interval
= get_stack_clash_protection_probe_interval ();
25309 /* Round the size down to a multiple of PROBE_INTERVAL. */
25310 HOST_WIDE_INT rounded_size
= ROUND_DOWN (orig_size
, probe_interval
);
25312 /* If explicitly requested,
25313 or the rounded size is not the same as the original size
25314 or the the rounded size is greater than a page,
25315 then we will need a copy of the original stack pointer. */
25316 if (rounded_size
!= orig_size
25317 || rounded_size
> probe_interval
25320 /* If the caller did not request a copy of the incoming stack
25321 pointer, then we use r0 to hold the copy. */
25323 orig_sp
= gen_rtx_REG (Pmode
, 0);
25324 emit_move_insn (orig_sp
, stack_pointer_rtx
);
25327 /* There's three cases here.
25329 One is a single probe which is the most common and most efficiently
25330 implemented as it does not have to have a copy of the original
25331 stack pointer if there are no residuals.
25333 Second is unrolled allocation/probes which we use if there's just
25334 a few of them. It needs to save the original stack pointer into a
25335 temporary for use as a source register in the allocation/probe.
25337 Last is a loop. This is the most uncommon case and least efficient. */
25338 rtx_insn
*retval
= NULL
;
25339 if (rounded_size
== probe_interval
)
25341 retval
= rs6000_emit_allocate_stack_1 (probe_interval
, stack_pointer_rtx
);
25343 dump_stack_clash_frame_info (PROBE_INLINE
, rounded_size
!= orig_size
);
25345 else if (rounded_size
<= 8 * probe_interval
)
25347 /* The ABI requires using the store with update insns to allocate
25348 space and store the backchain into the stack
25350 So we save the current stack pointer into a temporary, then
25351 emit the store-with-update insns to store the saved stack pointer
25352 into the right location in each new page. */
25353 for (int i
= 0; i
< rounded_size
; i
+= probe_interval
)
25356 = rs6000_emit_allocate_stack_1 (probe_interval
, orig_sp
);
25358 /* Save the first stack adjustment in RETVAL. */
25363 dump_stack_clash_frame_info (PROBE_INLINE
, rounded_size
!= orig_size
);
25367 /* Compute the ending address. */
25369 = copy_reg
? gen_rtx_REG (Pmode
, 0) : gen_rtx_REG (Pmode
, 12);
25370 rtx rs
= GEN_INT (-rounded_size
);
25372 if (add_operand (rs
, Pmode
))
25373 insn
= emit_insn (gen_add3_insn (end_addr
, stack_pointer_rtx
, rs
));
25376 emit_move_insn (end_addr
, GEN_INT (-rounded_size
));
25377 insn
= emit_insn (gen_add3_insn (end_addr
, end_addr
,
25378 stack_pointer_rtx
));
25379 /* Describe the effect of INSN to the CFI engine. */
25380 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25381 gen_rtx_SET (end_addr
,
25382 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
25385 RTX_FRAME_RELATED_P (insn
) = 1;
25387 /* Emit the loop. */
25389 retval
= emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx
,
25390 stack_pointer_rtx
, orig_sp
,
25393 retval
= emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx
,
25394 stack_pointer_rtx
, orig_sp
,
25396 RTX_FRAME_RELATED_P (retval
) = 1;
25397 /* Describe the effect of INSN to the CFI engine. */
25398 add_reg_note (retval
, REG_FRAME_RELATED_EXPR
,
25399 gen_rtx_SET (stack_pointer_rtx
, end_addr
));
25401 /* Emit a blockage to ensure the allocation/probing insns are
25402 not optimized, combined, removed, etc. Other cases handle this
25403 within their call to rs6000_emit_allocate_stack_1. */
25404 emit_insn (gen_blockage ());
25406 dump_stack_clash_frame_info (PROBE_LOOP
, rounded_size
!= orig_size
);
25409 if (orig_size
!= rounded_size
)
25411 /* Allocate (and implicitly probe) any residual space. */
25412 HOST_WIDE_INT residual
= orig_size
- rounded_size
;
25414 rtx_insn
*insn
= rs6000_emit_allocate_stack_1 (residual
, orig_sp
);
25416 /* If the residual was the only allocation, then we can return the
25417 allocating insn. */
25425 /* Emit the correct code for allocating stack space, as insns.
25426 If COPY_REG, make sure a copy of the old frame is left there.
25427 The generated code may use hard register 0 as a temporary. */
25430 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
25433 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
25434 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
25435 rtx todec
= gen_int_mode (-size
, Pmode
);
25437 if (INTVAL (todec
) != -size
)
25439 warning (0, "stack frame too large");
25440 emit_insn (gen_trap ());
25444 if (crtl
->limit_stack
)
25446 if (REG_P (stack_limit_rtx
)
25447 && REGNO (stack_limit_rtx
) > 1
25448 && REGNO (stack_limit_rtx
) <= 31)
25451 = gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
));
25454 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
, const0_rtx
));
25456 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
25458 && DEFAULT_ABI
== ABI_V4
25461 rtx toload
= gen_rtx_CONST (VOIDmode
,
25462 gen_rtx_PLUS (Pmode
,
25466 emit_insn (gen_elf_high (tmp_reg
, toload
));
25467 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
25468 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
25472 warning (0, "stack limit expression is not supported");
25475 if (flag_stack_clash_protection
)
25477 if (size
< get_stack_clash_protection_guard_size ())
25478 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME
, true);
25481 rtx_insn
*insn
= rs6000_emit_probe_stack_range_stack_clash (size
,
25484 /* If we asked for a copy with an offset, then we still need add in
25486 if (copy_reg
&& copy_off
)
25487 emit_insn (gen_add3_insn (copy_reg
, copy_reg
, GEN_INT (copy_off
)));
25495 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
25497 emit_move_insn (copy_reg
, stack_reg
);
25500 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25501 it now and set the alias set/attributes. The above gen_*_update
25502 calls will generate a PARALLEL with the MEM set being the first
25504 insn
= rs6000_emit_allocate_stack_1 (size
, stack_reg
);
25508 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25510 #if PROBE_INTERVAL > 32768
25511 #error Cannot use indexed addressing mode for stack probing
25514 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25515 inclusive. These are offsets from the current stack pointer. */
25518 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
25520 /* See if we have a constant small number of probes to generate. If so,
25521 that's the easy case. */
25522 if (first
+ size
<= 32768)
25526 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25527 it exceeds SIZE. If only one probe is needed, this will not
25528 generate any code. Then probe at FIRST + SIZE. */
25529 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
25530 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25533 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25537 /* Otherwise, do the same as above, but in a loop. Note that we must be
25538 extra careful with variables wrapping around because we might be at
25539 the very top (or the very bottom) of the address space and we have
25540 to be able to handle this case properly; in particular, we use an
25541 equality test for the loop condition. */
25544 HOST_WIDE_INT rounded_size
;
25545 rtx r12
= gen_rtx_REG (Pmode
, 12);
25546 rtx r0
= gen_rtx_REG (Pmode
, 0);
25548 /* Sanity check for the addressing mode we're going to use. */
25549 gcc_assert (first
<= 32768);
25551 /* Step 1: round SIZE to the previous multiple of the interval. */
25553 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
25556 /* Step 2: compute initial and final value of the loop counter. */
25558 /* TEST_ADDR = SP + FIRST. */
25559 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
25562 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25563 if (rounded_size
> 32768)
25565 emit_move_insn (r0
, GEN_INT (-rounded_size
));
25566 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
25569 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
25573 /* Step 3: the loop
25577 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25580 while (TEST_ADDR != LAST_ADDR)
25582 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25583 until it is equal to ROUNDED_SIZE. */
25586 emit_insn (gen_probe_stack_rangedi (r12
, r12
, stack_pointer_rtx
, r0
));
25588 emit_insn (gen_probe_stack_rangesi (r12
, r12
, stack_pointer_rtx
, r0
));
25591 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25592 that SIZE is equal to ROUNDED_SIZE. */
25594 if (size
!= rounded_size
)
25595 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
25599 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25600 addresses, not offsets. */
25602 static const char *
25603 output_probe_stack_range_1 (rtx reg1
, rtx reg2
)
25605 static int labelno
= 0;
25609 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
25612 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
25614 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25616 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
25617 output_asm_insn ("addi %0,%0,%1", xops
);
25619 /* Probe at TEST_ADDR. */
25620 xops
[1] = gen_rtx_REG (Pmode
, 0);
25621 output_asm_insn ("stw %1,0(%0)", xops
);
25623 /* Test if TEST_ADDR == LAST_ADDR. */
25626 output_asm_insn ("cmpd 0,%0,%1", xops
);
25628 output_asm_insn ("cmpw 0,%0,%1", xops
);
25631 fputs ("\tbne 0,", asm_out_file
);
25632 assemble_name_raw (asm_out_file
, loop_lab
);
25633 fputc ('\n', asm_out_file
);
25638 /* This function is called when rs6000_frame_related is processing
25639 SETs within a PARALLEL, and returns whether the REGNO save ought to
25640 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25641 for out-of-line register save functions, store multiple, and the
25642 Darwin world_save. They may contain registers that don't really
25646 interesting_frame_related_regno (unsigned int regno
)
25648 /* Saves apparently of r0 are actually saving LR. It doesn't make
25649 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25650 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25651 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25652 as frame related. */
25655 /* If we see CR2 then we are here on a Darwin world save. Saves of
25656 CR2 signify the whole CR is being saved. This is a long-standing
25657 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25658 that CR needs to be saved. */
25659 if (regno
== CR2_REGNO
)
25661 /* Omit frame info for any user-defined global regs. If frame info
25662 is supplied for them, frame unwinding will restore a user reg.
25663 Also omit frame info for any reg we don't need to save, as that
25664 bloats frame info and can cause problems with shrink wrapping.
25665 Since global regs won't be seen as needing to be saved, both of
25666 these conditions are covered by save_reg_p. */
25667 return save_reg_p (regno
);
25670 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25671 addresses, not offsets.
25673 REG2 contains the backchain that must be stored into *sp at each allocation.
25675 This is subtly different than the Ada probing above in that it tries hard
25676 to prevent attacks that jump the stack guard. Thus, it is never allowed
25677 to allocate more than PROBE_INTERVAL bytes of stack space without a
25680 static const char *
25681 output_probe_stack_range_stack_clash (rtx reg1
, rtx reg2
, rtx reg3
)
25683 static int labelno
= 0;
25687 HOST_WIDE_INT probe_interval
= get_stack_clash_protection_probe_interval ();
25689 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
25691 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
25693 /* This allocates and probes. */
25696 xops
[2] = GEN_INT (-probe_interval
);
25698 output_asm_insn ("stdu %1,%2(%0)", xops
);
25700 output_asm_insn ("stwu %1,%2(%0)", xops
);
25702 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25706 output_asm_insn ("cmpd 0,%0,%1", xops
);
25708 output_asm_insn ("cmpw 0,%0,%1", xops
);
25710 fputs ("\tbne 0,", asm_out_file
);
25711 assemble_name_raw (asm_out_file
, loop_lab
);
25712 fputc ('\n', asm_out_file
);
25717 /* Wrapper around the output_probe_stack_range routines. */
25719 output_probe_stack_range (rtx reg1
, rtx reg2
, rtx reg3
)
25721 if (flag_stack_clash_protection
)
25722 return output_probe_stack_range_stack_clash (reg1
, reg2
, reg3
);
25724 return output_probe_stack_range_1 (reg1
, reg3
);
25727 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25728 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25729 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25730 deduce these equivalences by itself so it wasn't necessary to hold
25731 its hand so much. Don't be tempted to always supply d2_f_d_e with
25732 the actual cfa register, ie. r31 when we are using a hard frame
25733 pointer. That fails when saving regs off r1, and sched moves the
25734 r31 setup past the reg saves. */
25737 rs6000_frame_related (rtx_insn
*insn
, rtx reg
, HOST_WIDE_INT val
,
25738 rtx reg2
, rtx repl2
)
25742 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
25744 gcc_checking_assert (val
== 0);
25748 repl
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
25751 rtx pat
= PATTERN (insn
);
25752 if (!repl
&& !reg2
)
25754 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25755 if (GET_CODE (pat
) == PARALLEL
)
25756 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
25757 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
25759 rtx set
= XVECEXP (pat
, 0, i
);
25761 if (!REG_P (SET_SRC (set
))
25762 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
25763 RTX_FRAME_RELATED_P (set
) = 1;
25765 RTX_FRAME_RELATED_P (insn
) = 1;
25769 /* We expect that 'pat' is either a SET or a PARALLEL containing
25770 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25771 are important so they all have to be marked RTX_FRAME_RELATED_P.
25772 Call simplify_replace_rtx on the SETs rather than the whole insn
25773 so as to leave the other stuff alone (for example USE of r12). */
25775 set_used_flags (pat
);
25776 if (GET_CODE (pat
) == SET
)
25779 pat
= simplify_replace_rtx (pat
, reg
, repl
);
25781 pat
= simplify_replace_rtx (pat
, reg2
, repl2
);
25783 else if (GET_CODE (pat
) == PARALLEL
)
25785 pat
= shallow_copy_rtx (pat
);
25786 XVEC (pat
, 0) = shallow_copy_rtvec (XVEC (pat
, 0));
25788 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
25789 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
25791 rtx set
= XVECEXP (pat
, 0, i
);
25794 set
= simplify_replace_rtx (set
, reg
, repl
);
25796 set
= simplify_replace_rtx (set
, reg2
, repl2
);
25797 XVECEXP (pat
, 0, i
) = set
;
25799 if (!REG_P (SET_SRC (set
))
25800 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
25801 RTX_FRAME_RELATED_P (set
) = 1;
25805 gcc_unreachable ();
25807 RTX_FRAME_RELATED_P (insn
) = 1;
25808 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, copy_rtx_if_shared (pat
));
25813 /* Returns an insn that has a vrsave set operation with the
25814 appropriate CLOBBERs. */
25817 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
25820 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
25821 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
25824 = gen_rtx_SET (vrsave
,
25825 gen_rtx_UNSPEC_VOLATILE (SImode
,
25826 gen_rtvec (2, reg
, vrsave
),
25827 UNSPECV_SET_VRSAVE
));
25831 /* We need to clobber the registers in the mask so the scheduler
25832 does not move sets to VRSAVE before sets of AltiVec registers.
25834 However, if the function receives nonlocal gotos, reload will set
25835 all call saved registers live. We will end up with:
25837 (set (reg 999) (mem))
25838 (parallel [ (set (reg vrsave) (unspec blah))
25839 (clobber (reg 999))])
25841 The clobber will cause the store into reg 999 to be dead, and
25842 flow will attempt to delete an epilogue insn. In this case, we
25843 need an unspec use/set of the register. */
25845 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25846 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
25848 if (!epiloguep
|| call_used_regs
[i
])
25849 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
25850 gen_rtx_REG (V4SImode
, i
));
25853 rtx reg
= gen_rtx_REG (V4SImode
, i
);
25856 = gen_rtx_SET (reg
,
25857 gen_rtx_UNSPEC (V4SImode
,
25858 gen_rtvec (1, reg
), 27));
25862 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
25864 for (i
= 0; i
< nclobs
; ++i
)
25865 XVECEXP (insn
, 0, i
) = clobs
[i
];
25871 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
25875 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
25876 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
25877 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
25881 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
25883 return gen_frame_set (reg
, frame_reg
, offset
, false);
25887 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
25889 return gen_frame_set (reg
, frame_reg
, offset
, true);
25892 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25893 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25896 emit_frame_save (rtx frame_reg
, machine_mode mode
,
25897 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
25901 /* Some cases that need register indexed addressing. */
25902 gcc_checking_assert (!(TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
25903 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
)));
25905 reg
= gen_rtx_REG (mode
, regno
);
25906 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
25907 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
25908 NULL_RTX
, NULL_RTX
);
25911 /* Emit an offset memory reference suitable for a frame store, while
25912 converting to a valid addressing mode. */
25915 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
25917 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, GEN_INT (offset
)));
25920 #ifndef TARGET_FIX_AND_CONTINUE
25921 #define TARGET_FIX_AND_CONTINUE 0
25924 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25925 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25926 #define LAST_SAVRES_REGISTER 31
25927 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25938 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
25940 /* Temporary holding space for an out-of-line register save/restore
25942 static char savres_routine_name
[30];
25944 /* Return the name for an out-of-line register save/restore routine.
25945 We are saving/restoring GPRs if GPR is true. */
25948 rs6000_savres_routine_name (int regno
, int sel
)
25950 const char *prefix
= "";
25951 const char *suffix
= "";
25953 /* Different targets are supposed to define
25954 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25955 routine name could be defined with:
25957 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25959 This is a nice idea in practice, but in reality, things are
25960 complicated in several ways:
25962 - ELF targets have save/restore routines for GPRs.
25964 - PPC64 ELF targets have routines for save/restore of GPRs that
25965 differ in what they do with the link register, so having a set
25966 prefix doesn't work. (We only use one of the save routines at
25967 the moment, though.)
25969 - PPC32 elf targets have "exit" versions of the restore routines
25970 that restore the link register and can save some extra space.
25971 These require an extra suffix. (There are also "tail" versions
25972 of the restore routines and "GOT" versions of the save routines,
25973 but we don't generate those at present. Same problems apply,
25976 We deal with all this by synthesizing our own prefix/suffix and
25977 using that for the simple sprintf call shown above. */
25978 if (DEFAULT_ABI
== ABI_V4
)
25983 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
25984 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
25985 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
25986 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
25987 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25988 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
25992 if ((sel
& SAVRES_LR
))
25995 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25997 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25998 /* No out-of-line save/restore routines for GPRs on AIX. */
25999 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
26003 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
26004 prefix
= ((sel
& SAVRES_SAVE
)
26005 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
26006 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
26007 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
26009 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26010 if ((sel
& SAVRES_LR
))
26011 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
26015 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
26016 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
26019 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26020 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
26025 if (DEFAULT_ABI
== ABI_DARWIN
)
26027 /* The Darwin approach is (slightly) different, in order to be
26028 compatible with code generated by the system toolchain. There is a
26029 single symbol for the start of save sequence, and the code here
26030 embeds an offset into that code on the basis of the first register
26032 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
26033 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
26034 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
26035 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
26036 (regno
- 13) * 4, prefix
, regno
);
26037 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
26038 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
26039 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
26040 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26041 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
26042 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
26047 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
26049 return savres_routine_name
;
26052 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26053 We are saving/restoring GPRs if GPR is true. */
26056 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
26058 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26059 ? info
->first_gp_reg_save
26060 : (sel
& SAVRES_REG
) == SAVRES_FPR
26061 ? info
->first_fp_reg_save
- 32
26062 : (sel
& SAVRES_REG
) == SAVRES_VR
26063 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
26068 /* Don't generate bogus routine names. */
26069 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
26070 && regno
<= LAST_SAVRES_REGISTER
26071 && select
>= 0 && select
<= 12);
26073 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
26079 name
= rs6000_savres_routine_name (regno
, sel
);
26081 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
26082 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
26083 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
26089 /* Emit a sequence of insns, including a stack tie if needed, for
26090 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26091 reset the stack pointer, but move the base of the frame into
26092 reg UPDT_REGNO for use by out-of-line register restore routines. */
26095 rs6000_emit_stack_reset (rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
26096 unsigned updt_regno
)
26098 /* If there is nothing to do, don't do anything. */
26099 if (frame_off
== 0 && REGNO (frame_reg_rtx
) == updt_regno
)
26102 rtx updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
26104 /* This blockage is needed so that sched doesn't decide to move
26105 the sp change before the register restores. */
26106 if (DEFAULT_ABI
== ABI_V4
)
26107 return emit_insn (gen_stack_restore_tie (updt_reg_rtx
, frame_reg_rtx
,
26108 GEN_INT (frame_off
)));
26110 /* If we are restoring registers out-of-line, we will be using the
26111 "exit" variants of the restore routines, which will reset the
26112 stack for us. But we do need to point updt_reg into the
26113 right place for those routines. */
26114 if (frame_off
!= 0)
26115 return emit_insn (gen_add3_insn (updt_reg_rtx
,
26116 frame_reg_rtx
, GEN_INT (frame_off
)));
26118 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
26123 /* Return the register number used as a pointer by out-of-line
26124 save/restore functions. */
26126 static inline unsigned
26127 ptr_regno_for_savres (int sel
)
26129 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26130 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
26131 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
26134 /* Construct a parallel rtx describing the effect of a call to an
26135 out-of-line register save/restore routine, and emit the insn
26136 or jump_insn as appropriate. */
26139 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
26140 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
26141 machine_mode reg_mode
, int sel
)
26144 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
26145 int reg_size
= GET_MODE_SIZE (reg_mode
);
26152 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26153 ? info
->first_gp_reg_save
26154 : (sel
& SAVRES_REG
) == SAVRES_FPR
26155 ? info
->first_fp_reg_save
26156 : (sel
& SAVRES_REG
) == SAVRES_VR
26157 ? info
->first_altivec_reg_save
26159 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26161 : (sel
& SAVRES_REG
) == SAVRES_FPR
26163 : (sel
& SAVRES_REG
) == SAVRES_VR
26164 ? LAST_ALTIVEC_REGNO
+ 1
26166 n_regs
= end_reg
- start_reg
;
26167 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
26168 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
26171 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26172 RTVEC_ELT (p
, offset
++) = ret_rtx
;
26174 RTVEC_ELT (p
, offset
++)
26175 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
26177 sym
= rs6000_savres_routine_sym (info
, sel
);
26178 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
26180 use_reg
= ptr_regno_for_savres (sel
);
26181 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26183 /* Vector regs are saved/restored using [reg+reg] addressing. */
26184 RTVEC_ELT (p
, offset
++)
26185 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
26186 RTVEC_ELT (p
, offset
++)
26187 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
26190 RTVEC_ELT (p
, offset
++)
26191 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
26193 for (i
= 0; i
< end_reg
- start_reg
; i
++)
26194 RTVEC_ELT (p
, i
+ offset
)
26195 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
26196 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
26197 (sel
& SAVRES_SAVE
) != 0);
26199 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26200 RTVEC_ELT (p
, i
+ offset
)
26201 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
26203 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
26205 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26207 insn
= emit_jump_insn (par
);
26208 JUMP_LABEL (insn
) = ret_rtx
;
26211 insn
= emit_insn (par
);
26215 /* Emit prologue code to store CR fields that need to be saved into REG. This
26216 function should only be called when moving the non-volatile CRs to REG, it
26217 is not a general purpose routine to move the entire set of CRs to REG.
26218 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26222 rs6000_emit_prologue_move_from_cr (rtx reg
)
26224 /* Only the ELFv2 ABI allows storing only selected fields. */
26225 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
26227 int i
, cr_reg
[8], count
= 0;
26229 /* Collect CR fields that must be saved. */
26230 for (i
= 0; i
< 8; i
++)
26231 if (save_reg_p (CR0_REGNO
+ i
))
26232 cr_reg
[count
++] = i
;
26234 /* If it's just a single one, use mfcrf. */
26237 rtvec p
= rtvec_alloc (1);
26238 rtvec r
= rtvec_alloc (2);
26239 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
26240 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
26242 = gen_rtx_SET (reg
,
26243 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
26245 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26249 /* ??? It might be better to handle count == 2 / 3 cases here
26250 as well, using logical operations to combine the values. */
26253 emit_insn (gen_prologue_movesi_from_cr (reg
));
26256 /* Return whether the split-stack arg pointer (r12) is used. */
26259 split_stack_arg_pointer_used_p (void)
26261 /* If the pseudo holding the arg pointer is no longer a pseudo,
26262 then the arg pointer is used. */
26263 if (cfun
->machine
->split_stack_arg_pointer
!= NULL_RTX
26264 && (!REG_P (cfun
->machine
->split_stack_arg_pointer
)
26265 || (REGNO (cfun
->machine
->split_stack_arg_pointer
)
26266 < FIRST_PSEUDO_REGISTER
)))
26269 /* Unfortunately we also need to do some code scanning, since
26270 r12 may have been substituted for the pseudo. */
26272 basic_block bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
;
26273 FOR_BB_INSNS (bb
, insn
)
26274 if (NONDEBUG_INSN_P (insn
))
26276 /* A call destroys r12. */
26281 FOR_EACH_INSN_USE (use
, insn
)
26283 rtx x
= DF_REF_REG (use
);
26284 if (REG_P (x
) && REGNO (x
) == 12)
26288 FOR_EACH_INSN_DEF (def
, insn
)
26290 rtx x
= DF_REF_REG (def
);
26291 if (REG_P (x
) && REGNO (x
) == 12)
26295 return bitmap_bit_p (DF_LR_OUT (bb
), 12);
26298 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26301 rs6000_global_entry_point_needed_p (void)
26303 /* Only needed for the ELFv2 ABI. */
26304 if (DEFAULT_ABI
!= ABI_ELFv2
)
26307 /* With -msingle-pic-base, we assume the whole program shares the same
26308 TOC, so no global entry point prologues are needed anywhere. */
26309 if (TARGET_SINGLE_PIC_BASE
)
26312 /* Ensure we have a global entry point for thunks. ??? We could
26313 avoid that if the target routine doesn't need a global entry point,
26314 but we do not know whether this is the case at this point. */
26315 if (cfun
->is_thunk
)
26318 /* For regular functions, rs6000_emit_prologue sets this flag if the
26319 routine ever uses the TOC pointer. */
26320 return cfun
->machine
->r2_setup_needed
;
26323 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26325 rs6000_get_separate_components (void)
26327 rs6000_stack_t
*info
= rs6000_stack_info ();
26329 if (WORLD_SAVE_P (info
))
26332 gcc_assert (!(info
->savres_strategy
& SAVE_MULTIPLE
)
26333 && !(info
->savres_strategy
& REST_MULTIPLE
));
26335 /* Component 0 is the save/restore of LR (done via GPR0).
26336 Component 2 is the save of the TOC (GPR2).
26337 Components 13..31 are the save/restore of GPR13..GPR31.
26338 Components 46..63 are the save/restore of FPR14..FPR31. */
26340 cfun
->machine
->n_components
= 64;
26342 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26343 bitmap_clear (components
);
26345 int reg_size
= TARGET_32BIT
? 4 : 8;
26346 int fp_reg_size
= 8;
26348 /* The GPRs we need saved to the frame. */
26349 if ((info
->savres_strategy
& SAVE_INLINE_GPRS
)
26350 && (info
->savres_strategy
& REST_INLINE_GPRS
))
26352 int offset
= info
->gp_save_offset
;
26354 offset
+= info
->total_size
;
26356 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26358 if (IN_RANGE (offset
, -0x8000, 0x7fff)
26359 && save_reg_p (regno
))
26360 bitmap_set_bit (components
, regno
);
26362 offset
+= reg_size
;
26366 /* Don't mess with the hard frame pointer. */
26367 if (frame_pointer_needed
)
26368 bitmap_clear_bit (components
, HARD_FRAME_POINTER_REGNUM
);
26370 /* Don't mess with the fixed TOC register. */
26371 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
26372 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
26373 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
26374 bitmap_clear_bit (components
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
26376 /* The FPRs we need saved to the frame. */
26377 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
)
26378 && (info
->savres_strategy
& REST_INLINE_FPRS
))
26380 int offset
= info
->fp_save_offset
;
26382 offset
+= info
->total_size
;
26384 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26386 if (IN_RANGE (offset
, -0x8000, 0x7fff) && save_reg_p (regno
))
26387 bitmap_set_bit (components
, regno
);
26389 offset
+= fp_reg_size
;
26393 /* Optimize LR save and restore if we can. This is component 0. Any
26394 out-of-line register save/restore routines need LR. */
26395 if (info
->lr_save_p
26396 && !(flag_pic
&& (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
26397 && (info
->savres_strategy
& SAVE_INLINE_GPRS
)
26398 && (info
->savres_strategy
& REST_INLINE_GPRS
)
26399 && (info
->savres_strategy
& SAVE_INLINE_FPRS
)
26400 && (info
->savres_strategy
& REST_INLINE_FPRS
)
26401 && (info
->savres_strategy
& SAVE_INLINE_VRS
)
26402 && (info
->savres_strategy
& REST_INLINE_VRS
))
26404 int offset
= info
->lr_save_offset
;
26406 offset
+= info
->total_size
;
26407 if (IN_RANGE (offset
, -0x8000, 0x7fff))
26408 bitmap_set_bit (components
, 0);
26411 /* Optimize saving the TOC. This is component 2. */
26412 if (cfun
->machine
->save_toc_in_prologue
)
26413 bitmap_set_bit (components
, 2);
26418 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26420 rs6000_components_for_bb (basic_block bb
)
26422 rs6000_stack_t
*info
= rs6000_stack_info ();
26424 bitmap in
= DF_LIVE_IN (bb
);
26425 bitmap gen
= &DF_LIVE_BB_INFO (bb
)->gen
;
26426 bitmap kill
= &DF_LIVE_BB_INFO (bb
)->kill
;
26428 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26429 bitmap_clear (components
);
26431 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26434 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26435 if (bitmap_bit_p (in
, regno
)
26436 || bitmap_bit_p (gen
, regno
)
26437 || bitmap_bit_p (kill
, regno
))
26438 bitmap_set_bit (components
, regno
);
26441 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26442 if (bitmap_bit_p (in
, regno
)
26443 || bitmap_bit_p (gen
, regno
)
26444 || bitmap_bit_p (kill
, regno
))
26445 bitmap_set_bit (components
, regno
);
26447 /* The link register. */
26448 if (bitmap_bit_p (in
, LR_REGNO
)
26449 || bitmap_bit_p (gen
, LR_REGNO
)
26450 || bitmap_bit_p (kill
, LR_REGNO
))
26451 bitmap_set_bit (components
, 0);
26453 /* The TOC save. */
26454 if (bitmap_bit_p (in
, TOC_REGNUM
)
26455 || bitmap_bit_p (gen
, TOC_REGNUM
)
26456 || bitmap_bit_p (kill
, TOC_REGNUM
))
26457 bitmap_set_bit (components
, 2);
26462 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26464 rs6000_disqualify_components (sbitmap components
, edge e
,
26465 sbitmap edge_components
, bool /*is_prologue*/)
26467 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26468 live where we want to place that code. */
26469 if (bitmap_bit_p (edge_components
, 0)
26470 && bitmap_bit_p (DF_LIVE_IN (e
->dest
), 0))
26473 fprintf (dump_file
, "Disqualifying LR because GPR0 is live "
26474 "on entry to bb %d\n", e
->dest
->index
);
26475 bitmap_clear_bit (components
, 0);
26479 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26481 rs6000_emit_prologue_components (sbitmap components
)
26483 rs6000_stack_t
*info
= rs6000_stack_info ();
26484 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26485 ? HARD_FRAME_POINTER_REGNUM
26486 : STACK_POINTER_REGNUM
);
26488 machine_mode reg_mode
= Pmode
;
26489 int reg_size
= TARGET_32BIT
? 4 : 8;
26490 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26491 int fp_reg_size
= 8;
26493 /* Prologue for LR. */
26494 if (bitmap_bit_p (components
, 0))
26496 rtx lr
= gen_rtx_REG (reg_mode
, LR_REGNO
);
26497 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26498 rtx_insn
*insn
= emit_move_insn (reg
, lr
);
26499 RTX_FRAME_RELATED_P (insn
) = 1;
26500 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (reg
, lr
));
26502 int offset
= info
->lr_save_offset
;
26504 offset
+= info
->total_size
;
26506 insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26507 RTX_FRAME_RELATED_P (insn
) = 1;
26508 rtx mem
= copy_rtx (SET_DEST (single_set (insn
)));
26509 add_reg_note (insn
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, lr
));
26512 /* Prologue for TOC. */
26513 if (bitmap_bit_p (components
, 2))
26515 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
26516 rtx sp_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26517 emit_insn (gen_frame_store (reg
, sp_reg
, RS6000_TOC_SAVE_SLOT
));
26520 /* Prologue for the GPRs. */
26521 int offset
= info
->gp_save_offset
;
26523 offset
+= info
->total_size
;
26525 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26527 if (bitmap_bit_p (components
, i
))
26529 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26530 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26531 RTX_FRAME_RELATED_P (insn
) = 1;
26532 rtx set
= copy_rtx (single_set (insn
));
26533 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26536 offset
+= reg_size
;
26539 /* Prologue for the FPRs. */
26540 offset
= info
->fp_save_offset
;
26542 offset
+= info
->total_size
;
26544 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26546 if (bitmap_bit_p (components
, i
))
26548 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26549 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26550 RTX_FRAME_RELATED_P (insn
) = 1;
26551 rtx set
= copy_rtx (single_set (insn
));
26552 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26555 offset
+= fp_reg_size
;
26559 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26561 rs6000_emit_epilogue_components (sbitmap components
)
26563 rs6000_stack_t
*info
= rs6000_stack_info ();
26564 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26565 ? HARD_FRAME_POINTER_REGNUM
26566 : STACK_POINTER_REGNUM
);
26568 machine_mode reg_mode
= Pmode
;
26569 int reg_size
= TARGET_32BIT
? 4 : 8;
26571 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26572 int fp_reg_size
= 8;
26574 /* Epilogue for the FPRs. */
26575 int offset
= info
->fp_save_offset
;
26577 offset
+= info
->total_size
;
26579 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26581 if (bitmap_bit_p (components
, i
))
26583 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26584 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26585 RTX_FRAME_RELATED_P (insn
) = 1;
26586 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26589 offset
+= fp_reg_size
;
26592 /* Epilogue for the GPRs. */
26593 offset
= info
->gp_save_offset
;
26595 offset
+= info
->total_size
;
26597 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26599 if (bitmap_bit_p (components
, i
))
26601 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26602 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26603 RTX_FRAME_RELATED_P (insn
) = 1;
26604 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26607 offset
+= reg_size
;
26610 /* Epilogue for LR. */
26611 if (bitmap_bit_p (components
, 0))
26613 int offset
= info
->lr_save_offset
;
26615 offset
+= info
->total_size
;
26617 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26618 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26620 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
26621 insn
= emit_move_insn (lr
, reg
);
26622 RTX_FRAME_RELATED_P (insn
) = 1;
26623 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
26627 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26629 rs6000_set_handled_components (sbitmap components
)
26631 rs6000_stack_t
*info
= rs6000_stack_info ();
26633 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26634 if (bitmap_bit_p (components
, i
))
26635 cfun
->machine
->gpr_is_wrapped_separately
[i
] = true;
26637 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26638 if (bitmap_bit_p (components
, i
))
26639 cfun
->machine
->fpr_is_wrapped_separately
[i
- 32] = true;
26641 if (bitmap_bit_p (components
, 0))
26642 cfun
->machine
->lr_is_wrapped_separately
= true;
26644 if (bitmap_bit_p (components
, 2))
26645 cfun
->machine
->toc_is_wrapped_separately
= true;
26648 /* VRSAVE is a bit vector representing which AltiVec registers
26649 are used. The OS uses this to determine which vector
26650 registers to save on a context switch. We need to save
26651 VRSAVE on the stack frame, add whatever AltiVec registers we
26652 used in this function, and do the corresponding magic in the
26655 emit_vrsave_prologue (rs6000_stack_t
*info
, int save_regno
,
26656 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26658 /* Get VRSAVE into a GPR. */
26659 rtx reg
= gen_rtx_REG (SImode
, save_regno
);
26660 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
26662 emit_insn (gen_get_vrsave_internal (reg
));
26664 emit_insn (gen_rtx_SET (reg
, vrsave
));
26667 int offset
= info
->vrsave_save_offset
+ frame_off
;
26668 emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
26670 /* Include the registers in the mask. */
26671 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT (info
->vrsave_mask
)));
26673 emit_insn (generate_set_vrsave (reg
, info
, 0));
26676 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26677 called, it left the arg pointer to the old stack in r29. Otherwise, the
26678 arg pointer is the top of the current frame. */
26680 emit_split_stack_prologue (rs6000_stack_t
*info
, rtx_insn
*sp_adjust
,
26681 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26683 cfun
->machine
->split_stack_argp_used
= true;
26687 rtx r12
= gen_rtx_REG (Pmode
, 12);
26688 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26689 rtx set_r12
= gen_rtx_SET (r12
, sp_reg_rtx
);
26690 emit_insn_before (set_r12
, sp_adjust
);
26692 else if (frame_off
!= 0 || REGNO (frame_reg_rtx
) != 12)
26694 rtx r12
= gen_rtx_REG (Pmode
, 12);
26695 if (frame_off
== 0)
26696 emit_move_insn (r12
, frame_reg_rtx
);
26698 emit_insn (gen_add3_insn (r12
, frame_reg_rtx
, GEN_INT (frame_off
)));
26703 rtx r12
= gen_rtx_REG (Pmode
, 12);
26704 rtx r29
= gen_rtx_REG (Pmode
, 29);
26705 rtx cr7
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
26706 rtx not_more
= gen_label_rtx ();
26709 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
26710 gen_rtx_GEU (VOIDmode
, cr7
, const0_rtx
),
26711 gen_rtx_LABEL_REF (VOIDmode
, not_more
),
26713 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
26714 JUMP_LABEL (jump
) = not_more
;
26715 LABEL_NUSES (not_more
) += 1;
26716 emit_move_insn (r12
, r29
);
26717 emit_label (not_more
);
26721 /* Emit function prologue as insns. */
26724 rs6000_emit_prologue (void)
26726 rs6000_stack_t
*info
= rs6000_stack_info ();
26727 machine_mode reg_mode
= Pmode
;
26728 int reg_size
= TARGET_32BIT
? 4 : 8;
26729 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26730 int fp_reg_size
= 8;
26731 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26732 rtx frame_reg_rtx
= sp_reg_rtx
;
26733 unsigned int cr_save_regno
;
26734 rtx cr_save_rtx
= NULL_RTX
;
26737 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
26738 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
26739 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
26740 int using_split_stack
= (flag_split_stack
26741 && (lookup_attribute ("no_split_stack",
26742 DECL_ATTRIBUTES (cfun
->decl
))
26745 /* Offset to top of frame for frame_reg and sp respectively. */
26746 HOST_WIDE_INT frame_off
= 0;
26747 HOST_WIDE_INT sp_off
= 0;
26748 /* sp_adjust is the stack adjusting instruction, tracked so that the
26749 insn setting up the split-stack arg pointer can be emitted just
26750 prior to it, when r12 is not used here for other purposes. */
26751 rtx_insn
*sp_adjust
= 0;
26754 /* Track and check usage of r0, r11, r12. */
26755 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
26756 #define START_USE(R) do \
26758 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26759 reg_inuse |= 1 << (R); \
26761 #define END_USE(R) do \
26763 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26764 reg_inuse &= ~(1 << (R)); \
26766 #define NOT_INUSE(R) do \
26768 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26771 #define START_USE(R) do {} while (0)
26772 #define END_USE(R) do {} while (0)
26773 #define NOT_INUSE(R) do {} while (0)
26776 if (DEFAULT_ABI
== ABI_ELFv2
26777 && !TARGET_SINGLE_PIC_BASE
)
26779 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
26781 /* With -mminimal-toc we may generate an extra use of r2 below. */
26782 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
26783 && !constant_pool_empty_p ())
26784 cfun
->machine
->r2_setup_needed
= true;
26788 if (flag_stack_usage_info
)
26789 current_function_static_stack_size
= info
->total_size
;
26791 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
26793 HOST_WIDE_INT size
= info
->total_size
;
26795 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
26797 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
26798 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26799 size
- get_stack_check_protect ());
26802 rs6000_emit_probe_stack_range (get_stack_check_protect (), size
);
26805 if (TARGET_FIX_AND_CONTINUE
)
26807 /* gdb on darwin arranges to forward a function from the old
26808 address by modifying the first 5 instructions of the function
26809 to branch to the overriding function. This is necessary to
26810 permit function pointers that point to the old function to
26811 actually forward to the new function. */
26812 emit_insn (gen_nop ());
26813 emit_insn (gen_nop ());
26814 emit_insn (gen_nop ());
26815 emit_insn (gen_nop ());
26816 emit_insn (gen_nop ());
26819 /* Handle world saves specially here. */
26820 if (WORLD_SAVE_P (info
))
26827 /* save_world expects lr in r0. */
26828 reg0
= gen_rtx_REG (Pmode
, 0);
26829 if (info
->lr_save_p
)
26831 insn
= emit_move_insn (reg0
,
26832 gen_rtx_REG (Pmode
, LR_REGNO
));
26833 RTX_FRAME_RELATED_P (insn
) = 1;
26836 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26837 assumptions about the offsets of various bits of the stack
26839 gcc_assert (info
->gp_save_offset
== -220
26840 && info
->fp_save_offset
== -144
26841 && info
->lr_save_offset
== 8
26842 && info
->cr_save_offset
== 4
26845 && (!crtl
->calls_eh_return
26846 || info
->ehrd_offset
== -432)
26847 && info
->vrsave_save_offset
== -224
26848 && info
->altivec_save_offset
== -416);
26850 treg
= gen_rtx_REG (SImode
, 11);
26851 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
26853 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26854 in R11. It also clobbers R12, so beware! */
26856 /* Preserve CR2 for save_world prologues */
26858 sz
+= 32 - info
->first_gp_reg_save
;
26859 sz
+= 64 - info
->first_fp_reg_save
;
26860 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
26861 p
= rtvec_alloc (sz
);
26863 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
26864 gen_rtx_REG (SImode
,
26866 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
26867 gen_rtx_SYMBOL_REF (Pmode
,
26869 /* We do floats first so that the instruction pattern matches
26871 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
26873 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
26874 info
->first_fp_reg_save
+ i
),
26876 info
->fp_save_offset
+ frame_off
+ 8 * i
);
26877 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
26879 = gen_frame_store (gen_rtx_REG (V4SImode
,
26880 info
->first_altivec_reg_save
+ i
),
26882 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
26883 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26885 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26887 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
26889 /* CR register traditionally saved as CR2. */
26891 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
26892 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
26893 /* Explain about use of R0. */
26894 if (info
->lr_save_p
)
26896 = gen_frame_store (reg0
,
26897 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
26898 /* Explain what happens to the stack pointer. */
26900 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
26901 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
26904 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26905 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
26906 treg
, GEN_INT (-info
->total_size
));
26907 sp_off
= frame_off
= info
->total_size
;
26910 strategy
= info
->savres_strategy
;
26912 /* For V.4, update stack before we do any saving and set back pointer. */
26913 if (! WORLD_SAVE_P (info
)
26915 && (DEFAULT_ABI
== ABI_V4
26916 || crtl
->calls_eh_return
))
26918 bool need_r11
= (!(strategy
& SAVE_INLINE_FPRS
)
26919 || !(strategy
& SAVE_INLINE_GPRS
)
26920 || !(strategy
& SAVE_INLINE_VRS
));
26921 int ptr_regno
= -1;
26922 rtx ptr_reg
= NULL_RTX
;
26925 if (info
->total_size
< 32767)
26926 frame_off
= info
->total_size
;
26929 else if (info
->cr_save_p
26931 || info
->first_fp_reg_save
< 64
26932 || info
->first_gp_reg_save
< 32
26933 || info
->altivec_size
!= 0
26934 || info
->vrsave_size
!= 0
26935 || crtl
->calls_eh_return
)
26939 /* The prologue won't be saving any regs so there is no need
26940 to set up a frame register to access any frame save area.
26941 We also won't be using frame_off anywhere below, but set
26942 the correct value anyway to protect against future
26943 changes to this function. */
26944 frame_off
= info
->total_size
;
26946 if (ptr_regno
!= -1)
26948 /* Set up the frame offset to that needed by the first
26949 out-of-line save function. */
26950 START_USE (ptr_regno
);
26951 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26952 frame_reg_rtx
= ptr_reg
;
26953 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
26954 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
26955 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
26956 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
26957 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
26958 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
26959 frame_off
= -ptr_off
;
26961 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
26963 if (REGNO (frame_reg_rtx
) == 12)
26965 sp_off
= info
->total_size
;
26966 if (frame_reg_rtx
!= sp_reg_rtx
)
26967 rs6000_emit_stack_tie (frame_reg_rtx
, false);
26970 /* If we use the link register, get it into r0. */
26971 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
26972 && !cfun
->machine
->lr_is_wrapped_separately
)
26974 rtx addr
, reg
, mem
;
26976 reg
= gen_rtx_REG (Pmode
, 0);
26978 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
26979 RTX_FRAME_RELATED_P (insn
) = 1;
26981 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
26982 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
26984 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
26985 GEN_INT (info
->lr_save_offset
+ frame_off
));
26986 mem
= gen_rtx_MEM (Pmode
, addr
);
26987 /* This should not be of rs6000_sr_alias_set, because of
26988 __builtin_return_address. */
26990 insn
= emit_move_insn (mem
, reg
);
26991 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
26992 NULL_RTX
, NULL_RTX
);
26997 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26998 r12 will be needed by out-of-line gpr save. */
26999 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27000 && !(strategy
& (SAVE_INLINE_GPRS
27001 | SAVE_NOINLINE_GPRS_SAVES_LR
))
27003 if (!WORLD_SAVE_P (info
)
27005 && REGNO (frame_reg_rtx
) != cr_save_regno
27006 && !(using_static_chain_p
&& cr_save_regno
== 11)
27007 && !(using_split_stack
&& cr_save_regno
== 12 && sp_adjust
))
27009 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
27010 START_USE (cr_save_regno
);
27011 rs6000_emit_prologue_move_from_cr (cr_save_rtx
);
27014 /* Do any required saving of fpr's. If only one or two to save, do
27015 it ourselves. Otherwise, call function. */
27016 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
27018 int offset
= info
->fp_save_offset
+ frame_off
;
27019 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
27022 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
27023 emit_frame_save (frame_reg_rtx
, fp_reg_mode
, i
, offset
,
27024 sp_off
- frame_off
);
27026 offset
+= fp_reg_size
;
27029 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
27031 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
27032 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27033 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27034 rtx ptr_reg
= frame_reg_rtx
;
27036 if (REGNO (frame_reg_rtx
) == ptr_regno
)
27037 gcc_checking_assert (frame_off
== 0);
27040 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27041 NOT_INUSE (ptr_regno
);
27042 emit_insn (gen_add3_insn (ptr_reg
,
27043 frame_reg_rtx
, GEN_INT (frame_off
)));
27045 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
27046 info
->fp_save_offset
,
27047 info
->lr_save_offset
,
27049 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
27050 NULL_RTX
, NULL_RTX
);
27055 /* Save GPRs. This is done as a PARALLEL if we are using
27056 the store-multiple instructions. */
27057 if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
27059 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
27060 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
27061 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27062 rtx ptr_reg
= frame_reg_rtx
;
27063 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
27064 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
27067 if (ptr_regno
== 12)
27070 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27072 /* Need to adjust r11 (r12) if we saved any FPRs. */
27073 if (end_save
+ frame_off
!= 0)
27075 rtx offset
= GEN_INT (end_save
+ frame_off
);
27078 frame_off
= -end_save
;
27080 NOT_INUSE (ptr_regno
);
27081 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27083 else if (!ptr_set_up
)
27085 NOT_INUSE (ptr_regno
);
27086 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27088 ptr_off
= -end_save
;
27089 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
27090 info
->gp_save_offset
+ ptr_off
,
27091 info
->lr_save_offset
+ ptr_off
,
27093 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
27094 NULL_RTX
, NULL_RTX
);
27098 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_MULTIPLE
))
27102 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
27103 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
27105 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
27107 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
27108 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27109 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27110 NULL_RTX
, NULL_RTX
);
27112 else if (!WORLD_SAVE_P (info
))
27114 int offset
= info
->gp_save_offset
+ frame_off
;
27115 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
27118 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
27119 emit_frame_save (frame_reg_rtx
, reg_mode
, i
, offset
,
27120 sp_off
- frame_off
);
27122 offset
+= reg_size
;
27126 if (crtl
->calls_eh_return
)
27133 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
27134 if (regno
== INVALID_REGNUM
)
27138 p
= rtvec_alloc (i
);
27142 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
27143 if (regno
== INVALID_REGNUM
)
27147 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
27149 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
27150 RTVEC_ELT (p
, i
) = set
;
27151 RTX_FRAME_RELATED_P (set
) = 1;
27154 insn
= emit_insn (gen_blockage ());
27155 RTX_FRAME_RELATED_P (insn
) = 1;
27156 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
27159 /* In AIX ABI we need to make sure r2 is really saved. */
27160 if (TARGET_AIX
&& crtl
->calls_eh_return
)
27162 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
27163 rtx join_insn
, note
;
27164 rtx_insn
*save_insn
;
27165 long toc_restore_insn
;
27167 tmp_reg
= gen_rtx_REG (Pmode
, 11);
27168 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
27169 if (using_static_chain_p
)
27172 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
27176 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
27177 /* Peek at instruction to which this function returns. If it's
27178 restoring r2, then we know we've already saved r2. We can't
27179 unconditionally save r2 because the value we have will already
27180 be updated if we arrived at this function via a plt call or
27181 toc adjusting stub. */
27182 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
27183 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
27184 + RS6000_TOC_SAVE_SLOT
);
27185 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
27186 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
27187 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
27188 validate_condition_mode (EQ
, CCUNSmode
);
27189 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
27190 emit_insn (gen_rtx_SET (compare_result
,
27191 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
27192 toc_save_done
= gen_label_rtx ();
27193 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
27194 gen_rtx_EQ (VOIDmode
, compare_result
,
27196 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
27198 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
27199 JUMP_LABEL (jump
) = toc_save_done
;
27200 LABEL_NUSES (toc_save_done
) += 1;
27202 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
27203 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
27204 sp_off
- frame_off
);
27206 emit_label (toc_save_done
);
27208 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27209 have a CFG that has different saves along different paths.
27210 Move the note to a dummy blockage insn, which describes that
27211 R2 is unconditionally saved after the label. */
27212 /* ??? An alternate representation might be a special insn pattern
27213 containing both the branch and the store. That might let the
27214 code that minimizes the number of DW_CFA_advance opcodes better
27215 freedom in placing the annotations. */
27216 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
27218 remove_note (save_insn
, note
);
27220 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
27221 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
27222 RTX_FRAME_RELATED_P (save_insn
) = 0;
27224 join_insn
= emit_insn (gen_blockage ());
27225 REG_NOTES (join_insn
) = note
;
27226 RTX_FRAME_RELATED_P (join_insn
) = 1;
27228 if (using_static_chain_p
)
27230 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
27237 /* Save CR if we use any that must be preserved. */
27238 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
27240 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27241 GEN_INT (info
->cr_save_offset
+ frame_off
));
27242 rtx mem
= gen_frame_mem (SImode
, addr
);
27244 /* If we didn't copy cr before, do so now using r0. */
27245 if (cr_save_rtx
== NULL_RTX
)
27248 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
27249 rs6000_emit_prologue_move_from_cr (cr_save_rtx
);
27252 /* Saving CR requires a two-instruction sequence: one instruction
27253 to move the CR to a general-purpose register, and a second
27254 instruction that stores the GPR to memory.
27256 We do not emit any DWARF CFI records for the first of these,
27257 because we cannot properly represent the fact that CR is saved in
27258 a register. One reason is that we cannot express that multiple
27259 CR fields are saved; another reason is that on 64-bit, the size
27260 of the CR register in DWARF (4 bytes) differs from the size of
27261 a general-purpose register.
27263 This means if any intervening instruction were to clobber one of
27264 the call-saved CR fields, we'd have incorrect CFI. To prevent
27265 this from happening, we mark the store to memory as a use of
27266 those CR fields, which prevents any such instruction from being
27267 scheduled in between the two instructions. */
27272 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
27273 for (i
= 0; i
< 8; i
++)
27274 if (save_reg_p (CR0_REGNO
+ i
))
27275 crsave_v
[n_crsave
++]
27276 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
27278 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
27279 gen_rtvec_v (n_crsave
, crsave_v
)));
27280 END_USE (REGNO (cr_save_rtx
));
27282 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27283 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27284 so we need to construct a frame expression manually. */
27285 RTX_FRAME_RELATED_P (insn
) = 1;
27287 /* Update address to be stack-pointer relative, like
27288 rs6000_frame_related would do. */
27289 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
27290 GEN_INT (info
->cr_save_offset
+ sp_off
));
27291 mem
= gen_frame_mem (SImode
, addr
);
27293 if (DEFAULT_ABI
== ABI_ELFv2
)
27295 /* In the ELFv2 ABI we generate separate CFI records for each
27296 CR field that was actually saved. They all point to the
27297 same 32-bit stack slot. */
27301 for (i
= 0; i
< 8; i
++)
27302 if (save_reg_p (CR0_REGNO
+ i
))
27305 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27307 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
27311 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27312 gen_rtx_PARALLEL (VOIDmode
,
27313 gen_rtvec_v (n_crframe
, crframe
)));
27317 /* In other ABIs, by convention, we use a single CR regnum to
27318 represent the fact that all call-saved CR fields are saved.
27319 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27320 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
27321 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
27325 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27326 *separate* slots if the routine calls __builtin_eh_return, so
27327 that they can be independently restored by the unwinder. */
27328 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
27330 int i
, cr_off
= info
->ehcr_offset
;
27333 /* ??? We might get better performance by using multiple mfocrf
27335 crsave
= gen_rtx_REG (SImode
, 0);
27336 emit_insn (gen_prologue_movesi_from_cr (crsave
));
27338 for (i
= 0; i
< 8; i
++)
27339 if (!call_used_regs
[CR0_REGNO
+ i
])
27341 rtvec p
= rtvec_alloc (2);
27343 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
27345 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
27347 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27349 RTX_FRAME_RELATED_P (insn
) = 1;
27350 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27351 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
27352 sp_reg_rtx
, cr_off
+ sp_off
));
27354 cr_off
+= reg_size
;
27358 /* If we are emitting stack probes, but allocate no stack, then
27359 just note that in the dump file. */
27360 if (flag_stack_clash_protection
27363 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME
, false);
27365 /* Update stack and set back pointer unless this is V.4,
27366 for which it was done previously. */
27367 if (!WORLD_SAVE_P (info
) && info
->push_p
27368 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
27370 rtx ptr_reg
= NULL
;
27373 /* If saving altivec regs we need to be able to address all save
27374 locations using a 16-bit offset. */
27375 if ((strategy
& SAVE_INLINE_VRS
) == 0
27376 || (info
->altivec_size
!= 0
27377 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
27378 + info
->total_size
- frame_off
) > 32767)
27379 || (info
->vrsave_size
!= 0
27380 && (info
->vrsave_save_offset
27381 + info
->total_size
- frame_off
) > 32767))
27383 int sel
= SAVRES_SAVE
| SAVRES_VR
;
27384 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27386 if (using_static_chain_p
27387 && ptr_regno
== STATIC_CHAIN_REGNUM
)
27389 if (REGNO (frame_reg_rtx
) != ptr_regno
)
27390 START_USE (ptr_regno
);
27391 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27392 frame_reg_rtx
= ptr_reg
;
27393 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
27394 frame_off
= -ptr_off
;
27396 else if (REGNO (frame_reg_rtx
) == 1)
27397 frame_off
= info
->total_size
;
27398 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
27400 if (REGNO (frame_reg_rtx
) == 12)
27402 sp_off
= info
->total_size
;
27403 if (frame_reg_rtx
!= sp_reg_rtx
)
27404 rs6000_emit_stack_tie (frame_reg_rtx
, false);
27407 /* Set frame pointer, if needed. */
27408 if (frame_pointer_needed
)
27410 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
27412 RTX_FRAME_RELATED_P (insn
) = 1;
27415 /* Save AltiVec registers if needed. Save here because the red zone does
27416 not always include AltiVec registers. */
27417 if (!WORLD_SAVE_P (info
)
27418 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
27420 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
27422 /* Oddly, the vector save/restore functions point r0 at the end
27423 of the save area, then use r11 or r12 to load offsets for
27424 [reg+reg] addressing. */
27425 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
27426 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
27427 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
27429 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
27431 if (scratch_regno
== 12)
27433 if (end_save
+ frame_off
!= 0)
27435 rtx offset
= GEN_INT (end_save
+ frame_off
);
27437 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27440 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27442 ptr_off
= -end_save
;
27443 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
27444 info
->altivec_save_offset
+ ptr_off
,
27445 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
27446 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
27447 NULL_RTX
, NULL_RTX
);
27448 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
27450 /* The oddity mentioned above clobbered our frame reg. */
27451 emit_move_insn (frame_reg_rtx
, ptr_reg
);
27452 frame_off
= ptr_off
;
27455 else if (!WORLD_SAVE_P (info
)
27456 && info
->altivec_size
!= 0)
27460 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
27461 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
27463 rtx areg
, savereg
, mem
;
27464 HOST_WIDE_INT offset
;
27466 offset
= (info
->altivec_save_offset
+ frame_off
27467 + 16 * (i
- info
->first_altivec_reg_save
));
27469 savereg
= gen_rtx_REG (V4SImode
, i
);
27471 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
27473 mem
= gen_frame_mem (V4SImode
,
27474 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27475 GEN_INT (offset
)));
27476 insn
= emit_insn (gen_rtx_SET (mem
, savereg
));
27482 areg
= gen_rtx_REG (Pmode
, 0);
27483 emit_move_insn (areg
, GEN_INT (offset
));
27485 /* AltiVec addressing mode is [reg+reg]. */
27486 mem
= gen_frame_mem (V4SImode
,
27487 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
27489 /* Rather than emitting a generic move, force use of the stvx
27490 instruction, which we always want on ISA 2.07 (power8) systems.
27491 In particular we don't want xxpermdi/stxvd2x for little
27493 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
27496 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27497 areg
, GEN_INT (offset
));
27501 /* VRSAVE is a bit vector representing which AltiVec registers
27502 are used. The OS uses this to determine which vector
27503 registers to save on a context switch. We need to save
27504 VRSAVE on the stack frame, add whatever AltiVec registers we
27505 used in this function, and do the corresponding magic in the
27508 if (!WORLD_SAVE_P (info
) && info
->vrsave_size
!= 0)
27510 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27511 be using r12 as frame_reg_rtx and r11 as the static chain
27512 pointer for nested functions. */
27513 int save_regno
= 12;
27514 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27515 && !using_static_chain_p
)
27517 else if (using_split_stack
|| REGNO (frame_reg_rtx
) == 12)
27520 if (using_static_chain_p
)
27523 NOT_INUSE (save_regno
);
27525 emit_vrsave_prologue (info
, save_regno
, frame_off
, frame_reg_rtx
);
27528 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27529 if (!TARGET_SINGLE_PIC_BASE
27530 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
27531 && !constant_pool_empty_p ())
27532 || (DEFAULT_ABI
== ABI_V4
27533 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
27534 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
27536 /* If emit_load_toc_table will use the link register, we need to save
27537 it. We use R12 for this purpose because emit_load_toc_table
27538 can use register 0. This allows us to use a plain 'blr' to return
27539 from the procedure more often. */
27540 int save_LR_around_toc_setup
= (TARGET_ELF
27541 && DEFAULT_ABI
== ABI_V4
27543 && ! info
->lr_save_p
27544 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
27545 if (save_LR_around_toc_setup
)
27547 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27548 rtx tmp
= gen_rtx_REG (Pmode
, 12);
27551 insn
= emit_move_insn (tmp
, lr
);
27552 RTX_FRAME_RELATED_P (insn
) = 1;
27554 rs6000_emit_load_toc_table (TRUE
);
27556 insn
= emit_move_insn (lr
, tmp
);
27557 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27558 RTX_FRAME_RELATED_P (insn
) = 1;
27561 rs6000_emit_load_toc_table (TRUE
);
27565 if (!TARGET_SINGLE_PIC_BASE
27566 && DEFAULT_ABI
== ABI_DARWIN
27567 && flag_pic
&& crtl
->uses_pic_offset_table
)
27569 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27570 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
27572 /* Save and restore LR locally around this call (in R0). */
27573 if (!info
->lr_save_p
)
27574 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
27576 emit_insn (gen_load_macho_picbase (src
));
27578 emit_move_insn (gen_rtx_REG (Pmode
,
27579 RS6000_PIC_OFFSET_TABLE_REGNUM
),
27582 if (!info
->lr_save_p
)
27583 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
27587 /* If we need to, save the TOC register after doing the stack setup.
27588 Do not emit eh frame info for this save. The unwinder wants info,
27589 conceptually attached to instructions in this function, about
27590 register values in the caller of this function. This R2 may have
27591 already been changed from the value in the caller.
27592 We don't attempt to write accurate DWARF EH frame info for R2
27593 because code emitted by gcc for a (non-pointer) function call
27594 doesn't save and restore R2. Instead, R2 is managed out-of-line
27595 by a linker generated plt call stub when the function resides in
27596 a shared library. This behavior is costly to describe in DWARF,
27597 both in terms of the size of DWARF info and the time taken in the
27598 unwinder to interpret it. R2 changes, apart from the
27599 calls_eh_return case earlier in this function, are handled by
27600 linux-unwind.h frob_update_context. */
27601 if (rs6000_save_toc_in_prologue_p ()
27602 && !cfun
->machine
->toc_is_wrapped_separately
)
27604 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
27605 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
27608 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27609 if (using_split_stack
&& split_stack_arg_pointer_used_p ())
27610 emit_split_stack_prologue (info
, sp_adjust
, frame_off
, frame_reg_rtx
);
27613 /* Output .extern statements for the save/restore routines we use. */
27616 rs6000_output_savres_externs (FILE *file
)
27618 rs6000_stack_t
*info
= rs6000_stack_info ();
27620 if (TARGET_DEBUG_STACK
)
27621 debug_stack_info (info
);
27623 /* Write .extern for any function we will call to save and restore
27625 if (info
->first_fp_reg_save
< 64
27630 int regno
= info
->first_fp_reg_save
- 32;
27632 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
27634 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
27635 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27636 name
= rs6000_savres_routine_name (regno
, sel
);
27637 fprintf (file
, "\t.extern %s\n", name
);
27639 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
27641 bool lr
= (info
->savres_strategy
27642 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
27643 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27644 name
= rs6000_savres_routine_name (regno
, sel
);
27645 fprintf (file
, "\t.extern %s\n", name
);
27650 /* Write function prologue. */
27653 rs6000_output_function_prologue (FILE *file
)
27655 if (!cfun
->is_thunk
)
27656 rs6000_output_savres_externs (file
);
27658 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27659 immediately after the global entry point label. */
27660 if (rs6000_global_entry_point_needed_p ())
27662 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
27664 (*targetm
.asm_out
.internal_label
) (file
, "LCF", rs6000_pic_labelno
);
27666 if (TARGET_CMODEL
!= CMODEL_LARGE
)
27668 /* In the small and medium code models, we assume the TOC is less
27669 2 GB away from the text section, so it can be computed via the
27670 following two-instruction sequence. */
27673 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27674 fprintf (file
, "0:\taddis 2,12,.TOC.-");
27675 assemble_name (file
, buf
);
27676 fprintf (file
, "@ha\n");
27677 fprintf (file
, "\taddi 2,2,.TOC.-");
27678 assemble_name (file
, buf
);
27679 fprintf (file
, "@l\n");
27683 /* In the large code model, we allow arbitrary offsets between the
27684 TOC and the text section, so we have to load the offset from
27685 memory. The data field is emitted directly before the global
27686 entry point in rs6000_elf_declare_function_name. */
27689 #ifdef HAVE_AS_ENTRY_MARKERS
27690 /* If supported by the linker, emit a marker relocation. If the
27691 total code size of the final executable or shared library
27692 happens to fit into 2 GB after all, the linker will replace
27693 this code sequence with the sequence for the small or medium
27695 fprintf (file
, "\t.reloc .,R_PPC64_ENTRY\n");
27697 fprintf (file
, "\tld 2,");
27698 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
27699 assemble_name (file
, buf
);
27700 fprintf (file
, "-");
27701 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27702 assemble_name (file
, buf
);
27703 fprintf (file
, "(12)\n");
27704 fprintf (file
, "\tadd 2,2,12\n");
27707 fputs ("\t.localentry\t", file
);
27708 assemble_name (file
, name
);
27709 fputs (",.-", file
);
27710 assemble_name (file
, name
);
27711 fputs ("\n", file
);
27714 /* Output -mprofile-kernel code. This needs to be done here instead of
27715 in output_function_profile since it must go after the ELFv2 ABI
27716 local entry point. */
27717 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
27719 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
27720 gcc_assert (!TARGET_32BIT
);
27722 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
27724 /* In the ELFv2 ABI we have no compiler stack word. It must be
27725 the resposibility of _mcount to preserve the static chain
27726 register if required. */
27727 if (DEFAULT_ABI
!= ABI_ELFv2
27728 && cfun
->static_chain_decl
!= NULL
)
27730 asm_fprintf (file
, "\tstd %s,24(%s)\n",
27731 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27732 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27733 asm_fprintf (file
, "\tld %s,24(%s)\n",
27734 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27737 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27740 rs6000_pic_labelno
++;
27743 /* -mprofile-kernel code calls mcount before the function prolog,
27744 so a profiled leaf function should stay a leaf function. */
27746 rs6000_keep_leaf_when_profiled ()
27748 return TARGET_PROFILE_KERNEL
;
27751 /* Non-zero if vmx regs are restored before the frame pop, zero if
27752 we restore after the pop when possible. */
27753 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27755 /* Restoring cr is a two step process: loading a reg from the frame
27756 save, then moving the reg to cr. For ABI_V4 we must let the
27757 unwinder know that the stack location is no longer valid at or
27758 before the stack deallocation, but we can't emit a cfa_restore for
27759 cr at the stack deallocation like we do for other registers.
27760 The trouble is that it is possible for the move to cr to be
27761 scheduled after the stack deallocation. So say exactly where cr
27762 is located on each of the two insns. */
27765 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
27767 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
27768 rtx reg
= gen_rtx_REG (SImode
, regno
);
27769 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
27771 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
27773 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
27774 rtx set
= gen_rtx_SET (reg
, cr
);
27776 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
27777 RTX_FRAME_RELATED_P (insn
) = 1;
27782 /* Reload CR from REG. */
27785 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
27790 if (using_mfcr_multiple
)
27792 for (i
= 0; i
< 8; i
++)
27793 if (save_reg_p (CR0_REGNO
+ i
))
27795 gcc_assert (count
);
27798 if (using_mfcr_multiple
&& count
> 1)
27804 p
= rtvec_alloc (count
);
27807 for (i
= 0; i
< 8; i
++)
27808 if (save_reg_p (CR0_REGNO
+ i
))
27810 rtvec r
= rtvec_alloc (2);
27811 RTVEC_ELT (r
, 0) = reg
;
27812 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
27813 RTVEC_ELT (p
, ndx
) =
27814 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
27815 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
27818 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27819 gcc_assert (ndx
== count
);
27821 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27822 CR field separately. */
27823 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
27825 for (i
= 0; i
< 8; i
++)
27826 if (save_reg_p (CR0_REGNO
+ i
))
27827 add_reg_note (insn
, REG_CFA_RESTORE
,
27828 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27830 RTX_FRAME_RELATED_P (insn
) = 1;
27834 for (i
= 0; i
< 8; i
++)
27835 if (save_reg_p (CR0_REGNO
+ i
))
27837 rtx insn
= emit_insn (gen_movsi_to_cr_one
27838 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
27840 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27841 CR field separately, attached to the insn that in fact
27842 restores this particular CR field. */
27843 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
27845 add_reg_note (insn
, REG_CFA_RESTORE
,
27846 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27848 RTX_FRAME_RELATED_P (insn
) = 1;
27852 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27853 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
27854 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
27856 rtx_insn
*insn
= get_last_insn ();
27857 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
27859 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
27860 RTX_FRAME_RELATED_P (insn
) = 1;
27864 /* Like cr, the move to lr instruction can be scheduled after the
27865 stack deallocation, but unlike cr, its stack frame save is still
27866 valid. So we only need to emit the cfa_restore on the correct
27870 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
27872 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
27873 rtx reg
= gen_rtx_REG (Pmode
, regno
);
27875 emit_move_insn (reg
, mem
);
27879 restore_saved_lr (int regno
, bool exit_func
)
27881 rtx reg
= gen_rtx_REG (Pmode
, regno
);
27882 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27883 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
27885 if (!exit_func
&& flag_shrink_wrap
)
27887 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27888 RTX_FRAME_RELATED_P (insn
) = 1;
27893 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
27895 if (DEFAULT_ABI
== ABI_ELFv2
)
27898 for (i
= 0; i
< 8; i
++)
27899 if (save_reg_p (CR0_REGNO
+ i
))
27901 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
27902 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
27906 else if (info
->cr_save_p
)
27907 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27908 gen_rtx_REG (SImode
, CR2_REGNO
),
27911 if (info
->lr_save_p
)
27912 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27913 gen_rtx_REG (Pmode
, LR_REGNO
),
27915 return cfa_restores
;
27918 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27919 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27920 below stack pointer not cloberred by signals. */
27923 offset_below_red_zone_p (HOST_WIDE_INT offset
)
27925 return offset
< (DEFAULT_ABI
== ABI_V4
27927 : TARGET_32BIT
? -220 : -288);
27930 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27933 emit_cfa_restores (rtx cfa_restores
)
27935 rtx_insn
*insn
= get_last_insn ();
27936 rtx
*loc
= ®_NOTES (insn
);
27939 loc
= &XEXP (*loc
, 1);
27940 *loc
= cfa_restores
;
27941 RTX_FRAME_RELATED_P (insn
) = 1;
27944 /* Emit function epilogue as insns. */
27947 rs6000_emit_epilogue (int sibcall
)
27949 rs6000_stack_t
*info
;
27950 int restoring_GPRs_inline
;
27951 int restoring_FPRs_inline
;
27952 int using_load_multiple
;
27953 int using_mtcr_multiple
;
27954 int use_backchain_to_restore_sp
;
27957 HOST_WIDE_INT frame_off
= 0;
27958 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
27959 rtx frame_reg_rtx
= sp_reg_rtx
;
27960 rtx cfa_restores
= NULL_RTX
;
27962 rtx cr_save_reg
= NULL_RTX
;
27963 machine_mode reg_mode
= Pmode
;
27964 int reg_size
= TARGET_32BIT
? 4 : 8;
27965 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
27966 int fp_reg_size
= 8;
27969 unsigned ptr_regno
;
27971 info
= rs6000_stack_info ();
27973 strategy
= info
->savres_strategy
;
27974 using_load_multiple
= strategy
& REST_MULTIPLE
;
27975 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
27976 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
27977 using_mtcr_multiple
= (rs6000_tune
== PROCESSOR_PPC601
27978 || rs6000_tune
== PROCESSOR_PPC603
27979 || rs6000_tune
== PROCESSOR_PPC750
27981 /* Restore via the backchain when we have a large frame, since this
27982 is more efficient than an addis, addi pair. The second condition
27983 here will not trigger at the moment; We don't actually need a
27984 frame pointer for alloca, but the generic parts of the compiler
27985 give us one anyway. */
27986 use_backchain_to_restore_sp
= (info
->total_size
+ (info
->lr_save_p
27987 ? info
->lr_save_offset
27989 || (cfun
->calls_alloca
27990 && !frame_pointer_needed
));
27991 restore_lr
= (info
->lr_save_p
27992 && (restoring_FPRs_inline
27993 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
27994 && (restoring_GPRs_inline
27995 || info
->first_fp_reg_save
< 64)
27996 && !cfun
->machine
->lr_is_wrapped_separately
);
27999 if (WORLD_SAVE_P (info
))
28003 const char *alloc_rname
;
28006 /* eh_rest_world_r10 will return to the location saved in the LR
28007 stack slot (which is not likely to be our caller.)
28008 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28009 rest_world is similar, except any R10 parameter is ignored.
28010 The exception-handling stuff that was here in 2.95 is no
28011 longer necessary. */
28014 + 32 - info
->first_gp_reg_save
28015 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
28016 + 63 + 1 - info
->first_fp_reg_save
);
28018 strcpy (rname
, ((crtl
->calls_eh_return
) ?
28019 "*eh_rest_world_r10" : "*rest_world"));
28020 alloc_rname
= ggc_strdup (rname
);
28023 RTVEC_ELT (p
, j
++) = ret_rtx
;
28025 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
28026 /* The instruction pattern requires a clobber here;
28027 it is shared with the restVEC helper. */
28029 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
28032 /* CR register traditionally saved as CR2. */
28033 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
28035 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
28036 if (flag_shrink_wrap
)
28038 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
28039 gen_rtx_REG (Pmode
, LR_REGNO
),
28041 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28045 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28047 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
28049 = gen_frame_load (reg
,
28050 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
28051 if (flag_shrink_wrap
28052 && save_reg_p (info
->first_gp_reg_save
+ i
))
28053 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28055 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
28057 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
28059 = gen_frame_load (reg
,
28060 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
28061 if (flag_shrink_wrap
28062 && save_reg_p (info
->first_altivec_reg_save
+ i
))
28063 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28065 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
28067 rtx reg
= gen_rtx_REG (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
28068 info
->first_fp_reg_save
+ i
);
28070 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
28071 if (flag_shrink_wrap
28072 && save_reg_p (info
->first_fp_reg_save
+ i
))
28073 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28076 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
28078 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
28080 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
28082 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
28084 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
28085 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28087 if (flag_shrink_wrap
)
28089 REG_NOTES (insn
) = cfa_restores
;
28090 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28091 RTX_FRAME_RELATED_P (insn
) = 1;
28096 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28098 frame_off
= info
->total_size
;
28100 /* Restore AltiVec registers if we must do so before adjusting the
28102 if (info
->altivec_size
!= 0
28103 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28104 || (DEFAULT_ABI
!= ABI_V4
28105 && offset_below_red_zone_p (info
->altivec_save_offset
))))
28108 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
28110 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
28111 if (use_backchain_to_restore_sp
)
28113 int frame_regno
= 11;
28115 if ((strategy
& REST_INLINE_VRS
) == 0)
28117 /* Of r11 and r12, select the one not clobbered by an
28118 out-of-line restore function for the frame register. */
28119 frame_regno
= 11 + 12 - scratch_regno
;
28121 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
28122 emit_move_insn (frame_reg_rtx
,
28123 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28126 else if (frame_pointer_needed
)
28127 frame_reg_rtx
= hard_frame_pointer_rtx
;
28129 if ((strategy
& REST_INLINE_VRS
) == 0)
28131 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28133 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28134 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28136 if (end_save
+ frame_off
!= 0)
28138 rtx offset
= GEN_INT (end_save
+ frame_off
);
28140 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28143 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28145 ptr_off
= -end_save
;
28146 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28147 info
->altivec_save_offset
+ ptr_off
,
28148 0, V4SImode
, SAVRES_VR
);
28152 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28153 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28155 rtx addr
, areg
, mem
, insn
;
28156 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28157 HOST_WIDE_INT offset
28158 = (info
->altivec_save_offset
+ frame_off
28159 + 16 * (i
- info
->first_altivec_reg_save
));
28161 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
28163 mem
= gen_frame_mem (V4SImode
,
28164 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28165 GEN_INT (offset
)));
28166 insn
= gen_rtx_SET (reg
, mem
);
28170 areg
= gen_rtx_REG (Pmode
, 0);
28171 emit_move_insn (areg
, GEN_INT (offset
));
28173 /* AltiVec addressing mode is [reg+reg]. */
28174 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
28175 mem
= gen_frame_mem (V4SImode
, addr
);
28177 /* Rather than emitting a generic move, force use of the
28178 lvx instruction, which we always want. In particular we
28179 don't want lxvd2x/xxpermdi for little endian. */
28180 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
28183 (void) emit_insn (insn
);
28187 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28188 if (((strategy
& REST_INLINE_VRS
) == 0
28189 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
28190 && (flag_shrink_wrap
28191 || (offset_below_red_zone_p
28192 (info
->altivec_save_offset
28193 + 16 * (i
- info
->first_altivec_reg_save
))))
28196 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28197 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28201 /* Restore VRSAVE if we must do so before adjusting the stack. */
28202 if (info
->vrsave_size
!= 0
28203 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28204 || (DEFAULT_ABI
!= ABI_V4
28205 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
28209 if (frame_reg_rtx
== sp_reg_rtx
)
28211 if (use_backchain_to_restore_sp
)
28213 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28214 emit_move_insn (frame_reg_rtx
,
28215 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28218 else if (frame_pointer_needed
)
28219 frame_reg_rtx
= hard_frame_pointer_rtx
;
28222 reg
= gen_rtx_REG (SImode
, 12);
28223 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28224 info
->vrsave_save_offset
+ frame_off
));
28226 emit_insn (generate_set_vrsave (reg
, info
, 1));
28230 /* If we have a large stack frame, restore the old stack pointer
28231 using the backchain. */
28232 if (use_backchain_to_restore_sp
)
28234 if (frame_reg_rtx
== sp_reg_rtx
)
28236 /* Under V.4, don't reset the stack pointer until after we're done
28237 loading the saved registers. */
28238 if (DEFAULT_ABI
== ABI_V4
)
28239 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28241 insn
= emit_move_insn (frame_reg_rtx
,
28242 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28245 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28246 && DEFAULT_ABI
== ABI_V4
)
28247 /* frame_reg_rtx has been set up by the altivec restore. */
28251 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
28252 frame_reg_rtx
= sp_reg_rtx
;
28255 /* If we have a frame pointer, we can restore the old stack pointer
28257 else if (frame_pointer_needed
)
28259 frame_reg_rtx
= sp_reg_rtx
;
28260 if (DEFAULT_ABI
== ABI_V4
)
28261 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28262 /* Prevent reordering memory accesses against stack pointer restore. */
28263 else if (cfun
->calls_alloca
28264 || offset_below_red_zone_p (-info
->total_size
))
28265 rs6000_emit_stack_tie (frame_reg_rtx
, true);
28267 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
28268 GEN_INT (info
->total_size
)));
28271 else if (info
->push_p
28272 && DEFAULT_ABI
!= ABI_V4
28273 && !crtl
->calls_eh_return
)
28275 /* Prevent reordering memory accesses against stack pointer restore. */
28276 if (cfun
->calls_alloca
28277 || offset_below_red_zone_p (-info
->total_size
))
28278 rs6000_emit_stack_tie (frame_reg_rtx
, false);
28279 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
28280 GEN_INT (info
->total_size
)));
28283 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
28287 REG_NOTES (insn
) = cfa_restores
;
28288 cfa_restores
= NULL_RTX
;
28290 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28291 RTX_FRAME_RELATED_P (insn
) = 1;
28294 /* Restore AltiVec registers if we have not done so already. */
28295 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28296 && info
->altivec_size
!= 0
28297 && (DEFAULT_ABI
== ABI_V4
28298 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
28302 if ((strategy
& REST_INLINE_VRS
) == 0)
28304 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28306 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28307 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
28308 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28310 if (end_save
+ frame_off
!= 0)
28312 rtx offset
= GEN_INT (end_save
+ frame_off
);
28314 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28317 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28319 ptr_off
= -end_save
;
28320 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28321 info
->altivec_save_offset
+ ptr_off
,
28322 0, V4SImode
, SAVRES_VR
);
28323 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
28325 /* Frame reg was clobbered by out-of-line save. Restore it
28326 from ptr_reg, and if we are calling out-of-line gpr or
28327 fpr restore set up the correct pointer and offset. */
28328 unsigned newptr_regno
= 1;
28329 if (!restoring_GPRs_inline
)
28331 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28332 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28333 newptr_regno
= ptr_regno_for_savres (sel
);
28334 end_save
= info
->gp_save_offset
+ info
->gp_size
;
28336 else if (!restoring_FPRs_inline
)
28338 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
28339 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28340 newptr_regno
= ptr_regno_for_savres (sel
);
28341 end_save
= info
->fp_save_offset
+ info
->fp_size
;
28344 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
28345 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
28347 if (end_save
+ ptr_off
!= 0)
28349 rtx offset
= GEN_INT (end_save
+ ptr_off
);
28351 frame_off
= -end_save
;
28353 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
28356 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
28361 frame_off
= ptr_off
;
28362 emit_move_insn (frame_reg_rtx
, ptr_reg
);
28368 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28369 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28371 rtx addr
, areg
, mem
, insn
;
28372 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28373 HOST_WIDE_INT offset
28374 = (info
->altivec_save_offset
+ frame_off
28375 + 16 * (i
- info
->first_altivec_reg_save
));
28377 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
28379 mem
= gen_frame_mem (V4SImode
,
28380 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28381 GEN_INT (offset
)));
28382 insn
= gen_rtx_SET (reg
, mem
);
28386 areg
= gen_rtx_REG (Pmode
, 0);
28387 emit_move_insn (areg
, GEN_INT (offset
));
28389 /* AltiVec addressing mode is [reg+reg]. */
28390 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
28391 mem
= gen_frame_mem (V4SImode
, addr
);
28393 /* Rather than emitting a generic move, force use of the
28394 lvx instruction, which we always want. In particular we
28395 don't want lxvd2x/xxpermdi for little endian. */
28396 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
28399 (void) emit_insn (insn
);
28403 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28404 if (((strategy
& REST_INLINE_VRS
) == 0
28405 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
28406 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28409 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28410 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28414 /* Restore VRSAVE if we have not done so already. */
28415 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28416 && info
->vrsave_size
!= 0
28417 && (DEFAULT_ABI
== ABI_V4
28418 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
28422 reg
= gen_rtx_REG (SImode
, 12);
28423 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28424 info
->vrsave_save_offset
+ frame_off
));
28426 emit_insn (generate_set_vrsave (reg
, info
, 1));
28429 /* If we exit by an out-of-line restore function on ABI_V4 then that
28430 function will deallocate the stack, so we don't need to worry
28431 about the unwinder restoring cr from an invalid stack frame
28433 exit_func
= (!restoring_FPRs_inline
28434 || (!restoring_GPRs_inline
28435 && info
->first_fp_reg_save
== 64));
28437 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28438 *separate* slots if the routine calls __builtin_eh_return, so
28439 that they can be independently restored by the unwinder. */
28440 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
28442 int i
, cr_off
= info
->ehcr_offset
;
28444 for (i
= 0; i
< 8; i
++)
28445 if (!call_used_regs
[CR0_REGNO
+ i
])
28447 rtx reg
= gen_rtx_REG (SImode
, 0);
28448 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28449 cr_off
+ frame_off
));
28451 insn
= emit_insn (gen_movsi_to_cr_one
28452 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
28454 if (!exit_func
&& flag_shrink_wrap
)
28456 add_reg_note (insn
, REG_CFA_RESTORE
,
28457 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
28459 RTX_FRAME_RELATED_P (insn
) = 1;
28462 cr_off
+= reg_size
;
28466 /* Get the old lr if we saved it. If we are restoring registers
28467 out-of-line, then the out-of-line routines can do this for us. */
28468 if (restore_lr
&& restoring_GPRs_inline
)
28469 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28471 /* Get the old cr if we saved it. */
28472 if (info
->cr_save_p
)
28474 unsigned cr_save_regno
= 12;
28476 if (!restoring_GPRs_inline
)
28478 /* Ensure we don't use the register used by the out-of-line
28479 gpr register restore below. */
28480 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28481 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28482 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
28484 if (gpr_ptr_regno
== 12)
28485 cr_save_regno
= 11;
28486 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
28488 else if (REGNO (frame_reg_rtx
) == 12)
28489 cr_save_regno
= 11;
28491 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
28492 info
->cr_save_offset
+ frame_off
,
28496 /* Set LR here to try to overlap restores below. */
28497 if (restore_lr
&& restoring_GPRs_inline
)
28498 restore_saved_lr (0, exit_func
);
28500 /* Load exception handler data registers, if needed. */
28501 if (crtl
->calls_eh_return
)
28503 unsigned int i
, regno
;
28507 rtx reg
= gen_rtx_REG (reg_mode
, 2);
28508 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28509 frame_off
+ RS6000_TOC_SAVE_SLOT
));
28516 regno
= EH_RETURN_DATA_REGNO (i
);
28517 if (regno
== INVALID_REGNUM
)
28520 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
28521 info
->ehrd_offset
+ frame_off
28522 + reg_size
* (int) i
);
28524 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
28528 /* Restore GPRs. This is done as a PARALLEL if we are using
28529 the load-multiple instructions. */
28530 if (!restoring_GPRs_inline
)
28532 /* We are jumping to an out-of-line function. */
28534 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
28535 bool can_use_exit
= end_save
== 0;
28536 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
28539 /* Emit stack reset code if we need it. */
28540 ptr_regno
= ptr_regno_for_savres (sel
);
28541 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28543 rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28544 else if (end_save
+ frame_off
!= 0)
28545 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
28546 GEN_INT (end_save
+ frame_off
)));
28547 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
28548 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28549 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28550 frame_off
= -end_save
;
28552 if (can_use_exit
&& info
->cr_save_p
)
28553 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
28555 ptr_off
= -end_save
;
28556 rs6000_emit_savres_rtx (info
, ptr_reg
,
28557 info
->gp_save_offset
+ ptr_off
,
28558 info
->lr_save_offset
+ ptr_off
,
28561 else if (using_load_multiple
)
28564 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
28565 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28567 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
28569 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
28570 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28574 int offset
= info
->gp_save_offset
+ frame_off
;
28575 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28578 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28580 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28581 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28584 offset
+= reg_size
;
28588 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28590 /* If the frame pointer was used then we can't delay emitting
28591 a REG_CFA_DEF_CFA note. This must happen on the insn that
28592 restores the frame pointer, r31. We may have already emitted
28593 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28594 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28595 be harmless if emitted. */
28596 if (frame_pointer_needed
)
28598 insn
= get_last_insn ();
28599 add_reg_note (insn
, REG_CFA_DEF_CFA
,
28600 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
28601 RTX_FRAME_RELATED_P (insn
) = 1;
28604 /* Set up cfa_restores. We always need these when
28605 shrink-wrapping. If not shrink-wrapping then we only need
28606 the cfa_restore when the stack location is no longer valid.
28607 The cfa_restores must be emitted on or before the insn that
28608 invalidates the stack, and of course must not be emitted
28609 before the insn that actually does the restore. The latter
28610 is why it is a bad idea to emit the cfa_restores as a group
28611 on the last instruction here that actually does a restore:
28612 That insn may be reordered with respect to others doing
28614 if (flag_shrink_wrap
28615 && !restoring_GPRs_inline
28616 && info
->first_fp_reg_save
== 64)
28617 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28619 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28621 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28623 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28624 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28628 if (!restoring_GPRs_inline
28629 && info
->first_fp_reg_save
== 64)
28631 /* We are jumping to an out-of-line function. */
28633 emit_cfa_restores (cfa_restores
);
28637 if (restore_lr
&& !restoring_GPRs_inline
)
28639 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28640 restore_saved_lr (0, exit_func
);
28643 /* Restore fpr's if we need to do it without calling a function. */
28644 if (restoring_FPRs_inline
)
28646 int offset
= info
->fp_save_offset
+ frame_off
;
28647 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
28650 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
28652 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
28653 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28654 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28655 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
28659 offset
+= fp_reg_size
;
28663 /* If we saved cr, restore it here. Just those that were used. */
28664 if (info
->cr_save_p
)
28665 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
28667 /* If this is V.4, unwind the stack pointer after all of the loads
28668 have been done, or set up r11 if we are restoring fp out of line. */
28670 if (!restoring_FPRs_inline
)
28672 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28673 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28674 ptr_regno
= ptr_regno_for_savres (sel
);
28677 insn
= rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28678 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28681 if (insn
&& restoring_FPRs_inline
)
28685 REG_NOTES (insn
) = cfa_restores
;
28686 cfa_restores
= NULL_RTX
;
28688 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28689 RTX_FRAME_RELATED_P (insn
) = 1;
28692 if (crtl
->calls_eh_return
)
28694 rtx sa
= EH_RETURN_STACKADJ_RTX
;
28695 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
28698 if (!sibcall
&& restoring_FPRs_inline
)
28702 /* We can't hang the cfa_restores off a simple return,
28703 since the shrink-wrap code sometimes uses an existing
28704 return. This means there might be a path from
28705 pre-prologue code to this return, and dwarf2cfi code
28706 wants the eh_frame unwinder state to be the same on
28707 all paths to any point. So we need to emit the
28708 cfa_restores before the return. For -m64 we really
28709 don't need epilogue cfa_restores at all, except for
28710 this irritating dwarf2cfi with shrink-wrap
28711 requirement; The stack red-zone means eh_frame info
28712 from the prologue telling the unwinder to restore
28713 from the stack is perfectly good right to the end of
28715 emit_insn (gen_blockage ());
28716 emit_cfa_restores (cfa_restores
);
28717 cfa_restores
= NULL_RTX
;
28720 emit_jump_insn (targetm
.gen_simple_return ());
28723 if (!sibcall
&& !restoring_FPRs_inline
)
28725 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28726 rtvec p
= rtvec_alloc (3 + !!lr
+ 64 - info
->first_fp_reg_save
);
28728 RTVEC_ELT (p
, elt
++) = ret_rtx
;
28730 RTVEC_ELT (p
, elt
++)
28731 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
28733 /* We have to restore more than two FP registers, so branch to the
28734 restore function. It will return to our caller. */
28739 if (flag_shrink_wrap
)
28740 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28742 sym
= rs6000_savres_routine_sym (info
, SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
28743 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, sym
);
28744 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
28745 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
28747 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
28749 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
28751 RTVEC_ELT (p
, elt
++)
28752 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
28753 if (flag_shrink_wrap
28754 && save_reg_p (info
->first_fp_reg_save
+ i
))
28755 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28758 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28764 /* Ensure the cfa_restores are hung off an insn that won't
28765 be reordered above other restores. */
28766 emit_insn (gen_blockage ());
28768 emit_cfa_restores (cfa_restores
);
28772 /* Write function epilogue. */
28775 rs6000_output_function_epilogue (FILE *file
)
28778 macho_branch_islands ();
28781 rtx_insn
*insn
= get_last_insn ();
28782 rtx_insn
*deleted_debug_label
= NULL
;
28784 /* Mach-O doesn't support labels at the end of objects, so if
28785 it looks like we might want one, take special action.
28787 First, collect any sequence of deleted debug labels. */
28790 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
28792 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28793 notes only, instead set their CODE_LABEL_NUMBER to -1,
28794 otherwise there would be code generation differences
28795 in between -g and -g0. */
28796 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
28797 deleted_debug_label
= insn
;
28798 insn
= PREV_INSN (insn
);
28801 /* Second, if we have:
28804 then this needs to be detected, so skip past the barrier. */
28806 if (insn
&& BARRIER_P (insn
))
28807 insn
= PREV_INSN (insn
);
28809 /* Up to now we've only seen notes or barriers. */
28814 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
))
28815 /* Trailing label: <barrier>. */
28816 fputs ("\tnop\n", file
);
28819 /* Lastly, see if we have a completely empty function body. */
28820 while (insn
&& ! INSN_P (insn
))
28821 insn
= PREV_INSN (insn
);
28822 /* If we don't find any insns, we've got an empty function body;
28823 I.e. completely empty - without a return or branch. This is
28824 taken as the case where a function body has been removed
28825 because it contains an inline __builtin_unreachable(). GCC
28826 states that reaching __builtin_unreachable() means UB so we're
28827 not obliged to do anything special; however, we want
28828 non-zero-sized function bodies. To meet this, and help the
28829 user out, let's trap the case. */
28831 fputs ("\ttrap\n", file
);
28834 else if (deleted_debug_label
)
28835 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
28836 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
28837 CODE_LABEL_NUMBER (insn
) = -1;
28841 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28844 We don't output a traceback table if -finhibit-size-directive was
28845 used. The documentation for -finhibit-size-directive reads
28846 ``don't output a @code{.size} assembler directive, or anything
28847 else that would cause trouble if the function is split in the
28848 middle, and the two halves are placed at locations far apart in
28849 memory.'' The traceback table has this property, since it
28850 includes the offset from the start of the function to the
28851 traceback table itself.
28853 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28854 different traceback table. */
28855 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28856 && ! flag_inhibit_size_directive
28857 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
28859 const char *fname
= NULL
;
28860 const char *language_string
= lang_hooks
.name
;
28861 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
28863 int optional_tbtab
;
28864 rs6000_stack_t
*info
= rs6000_stack_info ();
28866 if (rs6000_traceback
== traceback_full
)
28867 optional_tbtab
= 1;
28868 else if (rs6000_traceback
== traceback_part
)
28869 optional_tbtab
= 0;
28871 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
28873 if (optional_tbtab
)
28875 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
28876 while (*fname
== '.') /* V.4 encodes . in the name */
28879 /* Need label immediately before tbtab, so we can compute
28880 its offset from the function start. */
28881 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
28882 ASM_OUTPUT_LABEL (file
, fname
);
28885 /* The .tbtab pseudo-op can only be used for the first eight
28886 expressions, since it can't handle the possibly variable
28887 length fields that follow. However, if you omit the optional
28888 fields, the assembler outputs zeros for all optional fields
28889 anyways, giving each variable length field is minimum length
28890 (as defined in sys/debug.h). Thus we can not use the .tbtab
28891 pseudo-op at all. */
28893 /* An all-zero word flags the start of the tbtab, for debuggers
28894 that have to find it by searching forward from the entry
28895 point or from the current pc. */
28896 fputs ("\t.long 0\n", file
);
28898 /* Tbtab format type. Use format type 0. */
28899 fputs ("\t.byte 0,", file
);
28901 /* Language type. Unfortunately, there does not seem to be any
28902 official way to discover the language being compiled, so we
28903 use language_string.
28904 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28905 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28906 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28907 numbers either, so for now use 0. */
28909 || ! strcmp (language_string
, "GNU GIMPLE")
28910 || ! strcmp (language_string
, "GNU Go")
28911 || ! strcmp (language_string
, "GNU D")
28912 || ! strcmp (language_string
, "libgccjit"))
28914 else if (! strcmp (language_string
, "GNU F77")
28915 || lang_GNU_Fortran ())
28917 else if (! strcmp (language_string
, "GNU Ada"))
28919 else if (lang_GNU_CXX ()
28920 || ! strcmp (language_string
, "GNU Objective-C++"))
28922 else if (! strcmp (language_string
, "GNU Java"))
28924 else if (! strcmp (language_string
, "GNU Objective-C"))
28927 gcc_unreachable ();
28928 fprintf (file
, "%d,", i
);
28930 /* 8 single bit fields: global linkage (not set for C extern linkage,
28931 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28932 from start of procedure stored in tbtab, internal function, function
28933 has controlled storage, function has no toc, function uses fp,
28934 function logs/aborts fp operations. */
28935 /* Assume that fp operations are used if any fp reg must be saved. */
28936 fprintf (file
, "%d,",
28937 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
28939 /* 6 bitfields: function is interrupt handler, name present in
28940 proc table, function calls alloca, on condition directives
28941 (controls stack walks, 3 bits), saves condition reg, saves
28943 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28944 set up as a frame pointer, even when there is no alloca call. */
28945 fprintf (file
, "%d,",
28946 ((optional_tbtab
<< 6)
28947 | ((optional_tbtab
& frame_pointer_needed
) << 5)
28948 | (info
->cr_save_p
<< 1)
28949 | (info
->lr_save_p
)));
28951 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28953 fprintf (file
, "%d,",
28954 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
28956 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28957 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
28959 if (optional_tbtab
)
28961 /* Compute the parameter info from the function decl argument
28964 int next_parm_info_bit
= 31;
28966 for (decl
= DECL_ARGUMENTS (current_function_decl
);
28967 decl
; decl
= DECL_CHAIN (decl
))
28969 rtx parameter
= DECL_INCOMING_RTL (decl
);
28970 machine_mode mode
= GET_MODE (parameter
);
28972 if (GET_CODE (parameter
) == REG
)
28974 if (SCALAR_FLOAT_MODE_P (mode
))
28997 gcc_unreachable ();
29000 /* If only one bit will fit, don't or in this entry. */
29001 if (next_parm_info_bit
> 0)
29002 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
29003 next_parm_info_bit
-= 2;
29007 fixed_parms
+= ((GET_MODE_SIZE (mode
)
29008 + (UNITS_PER_WORD
- 1))
29010 next_parm_info_bit
-= 1;
29016 /* Number of fixed point parameters. */
29017 /* This is actually the number of words of fixed point parameters; thus
29018 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29019 fprintf (file
, "%d,", fixed_parms
);
29021 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29023 /* This is actually the number of fp registers that hold parameters;
29024 and thus the maximum value is 13. */
29025 /* Set parameters on stack bit if parameters are not in their original
29026 registers, regardless of whether they are on the stack? Xlc
29027 seems to set the bit when not optimizing. */
29028 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
29030 if (optional_tbtab
)
29032 /* Optional fields follow. Some are variable length. */
29034 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29035 float, 11 double float. */
29036 /* There is an entry for each parameter in a register, in the order
29037 that they occur in the parameter list. Any intervening arguments
29038 on the stack are ignored. If the list overflows a long (max
29039 possible length 34 bits) then completely leave off all elements
29041 /* Only emit this long if there was at least one parameter. */
29042 if (fixed_parms
|| float_parms
)
29043 fprintf (file
, "\t.long %d\n", parm_info
);
29045 /* Offset from start of code to tb table. */
29046 fputs ("\t.long ", file
);
29047 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
29048 RS6000_OUTPUT_BASENAME (file
, fname
);
29050 rs6000_output_function_entry (file
, fname
);
29053 /* Interrupt handler mask. */
29054 /* Omit this long, since we never set the interrupt handler bit
29057 /* Number of CTL (controlled storage) anchors. */
29058 /* Omit this long, since the has_ctl bit is never set above. */
29060 /* Displacement into stack of each CTL anchor. */
29061 /* Omit this list of longs, because there are no CTL anchors. */
29063 /* Length of function name. */
29066 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
29068 /* Function name. */
29069 assemble_string (fname
, strlen (fname
));
29071 /* Register for alloca automatic storage; this is always reg 31.
29072 Only emit this if the alloca bit was set above. */
29073 if (frame_pointer_needed
)
29074 fputs ("\t.byte 31\n", file
);
29076 fputs ("\t.align 2\n", file
);
29080 /* Arrange to define .LCTOC1 label, if not already done. */
29084 if (!toc_initialized
)
29086 switch_to_section (toc_section
);
29087 switch_to_section (current_function_section ());
29092 /* -fsplit-stack support. */
29094 /* A SYMBOL_REF for __morestack. */
29095 static GTY(()) rtx morestack_ref
;
29098 gen_add3_const (rtx rt
, rtx ra
, long c
)
29101 return gen_adddi3 (rt
, ra
, GEN_INT (c
));
29103 return gen_addsi3 (rt
, ra
, GEN_INT (c
));
29106 /* Emit -fsplit-stack prologue, which goes before the regular function
29107 prologue (at local entry point in the case of ELFv2). */
29110 rs6000_expand_split_stack_prologue (void)
29112 rs6000_stack_t
*info
= rs6000_stack_info ();
29113 unsigned HOST_WIDE_INT allocate
;
29114 long alloc_hi
, alloc_lo
;
29115 rtx r0
, r1
, r12
, lr
, ok_label
, compare
, jump
, call_fusage
;
29118 gcc_assert (flag_split_stack
&& reload_completed
);
29123 if (global_regs
[29])
29125 error ("%qs uses register r29", "-fsplit-stack");
29126 inform (DECL_SOURCE_LOCATION (global_regs_decl
[29]),
29127 "conflicts with %qD", global_regs_decl
[29]);
29130 allocate
= info
->total_size
;
29131 if (allocate
> (unsigned HOST_WIDE_INT
) 1 << 31)
29133 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
29136 if (morestack_ref
== NULL_RTX
)
29138 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
29139 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
29140 | SYMBOL_FLAG_FUNCTION
);
29143 r0
= gen_rtx_REG (Pmode
, 0);
29144 r1
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29145 r12
= gen_rtx_REG (Pmode
, 12);
29146 emit_insn (gen_load_split_stack_limit (r0
));
29147 /* Always emit two insns here to calculate the requested stack,
29148 so that the linker can edit them when adjusting size for calling
29149 non-split-stack code. */
29150 alloc_hi
= (-allocate
+ 0x8000) & ~0xffffL
;
29151 alloc_lo
= -allocate
- alloc_hi
;
29154 emit_insn (gen_add3_const (r12
, r1
, alloc_hi
));
29156 emit_insn (gen_add3_const (r12
, r12
, alloc_lo
));
29158 emit_insn (gen_nop ());
29162 emit_insn (gen_add3_const (r12
, r1
, alloc_lo
));
29163 emit_insn (gen_nop ());
29166 compare
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
29167 emit_insn (gen_rtx_SET (compare
, gen_rtx_COMPARE (CCUNSmode
, r12
, r0
)));
29168 ok_label
= gen_label_rtx ();
29169 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
29170 gen_rtx_GEU (VOIDmode
, compare
, const0_rtx
),
29171 gen_rtx_LABEL_REF (VOIDmode
, ok_label
),
29173 insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
29174 JUMP_LABEL (insn
) = ok_label
;
29175 /* Mark the jump as very likely to be taken. */
29176 add_reg_br_prob_note (insn
, profile_probability::very_likely ());
29178 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
29179 insn
= emit_move_insn (r0
, lr
);
29180 RTX_FRAME_RELATED_P (insn
) = 1;
29181 insn
= emit_insn (gen_frame_store (r0
, r1
, info
->lr_save_offset
));
29182 RTX_FRAME_RELATED_P (insn
) = 1;
29184 insn
= emit_call_insn (gen_call (gen_rtx_MEM (SImode
, morestack_ref
),
29185 const0_rtx
, const0_rtx
));
29186 call_fusage
= NULL_RTX
;
29187 use_reg (&call_fusage
, r12
);
29188 /* Say the call uses r0, even though it doesn't, to stop regrename
29189 from twiddling with the insns saving lr, trashing args for cfun.
29190 The insns restoring lr are similarly protected by making
29191 split_stack_return use r0. */
29192 use_reg (&call_fusage
, r0
);
29193 add_function_usage_to (insn
, call_fusage
);
29194 /* Indicate that this function can't jump to non-local gotos. */
29195 make_reg_eh_region_note_nothrow_nononlocal (insn
);
29196 emit_insn (gen_frame_load (r0
, r1
, info
->lr_save_offset
));
29197 insn
= emit_move_insn (lr
, r0
);
29198 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
29199 RTX_FRAME_RELATED_P (insn
) = 1;
29200 emit_insn (gen_split_stack_return ());
29202 emit_label (ok_label
);
29203 LABEL_NUSES (ok_label
) = 1;
29206 /* Return the internal arg pointer used for function incoming
29207 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29208 to copy it to a pseudo in order for it to be preserved over calls
29209 and suchlike. We'd really like to use a pseudo here for the
29210 internal arg pointer but data-flow analysis is not prepared to
29211 accept pseudos as live at the beginning of a function. */
29214 rs6000_internal_arg_pointer (void)
29216 if (flag_split_stack
29217 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
29221 if (cfun
->machine
->split_stack_arg_pointer
== NULL_RTX
)
29225 cfun
->machine
->split_stack_arg_pointer
= gen_reg_rtx (Pmode
);
29226 REG_POINTER (cfun
->machine
->split_stack_arg_pointer
) = 1;
29228 /* Put the pseudo initialization right after the note at the
29229 beginning of the function. */
29230 pat
= gen_rtx_SET (cfun
->machine
->split_stack_arg_pointer
,
29231 gen_rtx_REG (Pmode
, 12));
29232 push_topmost_sequence ();
29233 emit_insn_after (pat
, get_insns ());
29234 pop_topmost_sequence ();
29236 rtx ret
= plus_constant (Pmode
, cfun
->machine
->split_stack_arg_pointer
,
29237 FIRST_PARM_OFFSET (current_function_decl
));
29238 return copy_to_reg (ret
);
29240 return virtual_incoming_args_rtx
;
29243 /* We may have to tell the dataflow pass that the split stack prologue
29244 is initializing a register. */
29247 rs6000_live_on_entry (bitmap regs
)
29249 if (flag_split_stack
)
29250 bitmap_set_bit (regs
, 12);
29253 /* Emit -fsplit-stack dynamic stack allocation space check. */
29256 rs6000_split_stack_space_check (rtx size
, rtx label
)
29258 rtx sp
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29259 rtx limit
= gen_reg_rtx (Pmode
);
29260 rtx requested
= gen_reg_rtx (Pmode
);
29261 rtx cmp
= gen_reg_rtx (CCUNSmode
);
29264 emit_insn (gen_load_split_stack_limit (limit
));
29265 if (CONST_INT_P (size
))
29266 emit_insn (gen_add3_insn (requested
, sp
, GEN_INT (-INTVAL (size
))));
29269 size
= force_reg (Pmode
, size
);
29270 emit_move_insn (requested
, gen_rtx_MINUS (Pmode
, sp
, size
));
29272 emit_insn (gen_rtx_SET (cmp
, gen_rtx_COMPARE (CCUNSmode
, requested
, limit
)));
29273 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
29274 gen_rtx_GEU (VOIDmode
, cmp
, const0_rtx
),
29275 gen_rtx_LABEL_REF (VOIDmode
, label
),
29277 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
29278 JUMP_LABEL (jump
) = label
;
29281 /* A C compound statement that outputs the assembler code for a thunk
29282 function, used to implement C++ virtual function calls with
29283 multiple inheritance. The thunk acts as a wrapper around a virtual
29284 function, adjusting the implicit object parameter before handing
29285 control off to the real function.
29287 First, emit code to add the integer DELTA to the location that
29288 contains the incoming first argument. Assume that this argument
29289 contains a pointer, and is the one used to pass the `this' pointer
29290 in C++. This is the incoming argument *before* the function
29291 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29292 values of all other incoming arguments.
29294 After the addition, emit code to jump to FUNCTION, which is a
29295 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29296 not touch the return address. Hence returning from FUNCTION will
29297 return to whoever called the current `thunk'.
29299 The effect must be as if FUNCTION had been called directly with the
29300 adjusted first argument. This macro is responsible for emitting
29301 all of the code for a thunk function; output_function_prologue()
29302 and output_function_epilogue() are not invoked.
29304 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29305 been extracted from it.) It might possibly be useful on some
29306 targets, but probably not.
29308 If you do not define this macro, the target-independent code in the
29309 C++ frontend will generate a less efficient heavyweight thunk that
29310 calls FUNCTION instead of jumping to it. The generic approach does
29311 not support varargs. */
29314 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
29315 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
29318 rtx this_rtx
, funexp
;
29321 reload_completed
= 1;
29322 epilogue_completed
= 1;
29324 /* Mark the end of the (empty) prologue. */
29325 emit_note (NOTE_INSN_PROLOGUE_END
);
29327 /* Find the "this" pointer. If the function returns a structure,
29328 the structure return pointer is in r3. */
29329 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
29330 this_rtx
= gen_rtx_REG (Pmode
, 4);
29332 this_rtx
= gen_rtx_REG (Pmode
, 3);
29334 /* Apply the constant offset, if required. */
29336 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
29338 /* Apply the offset from the vtable, if required. */
29341 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
29342 rtx tmp
= gen_rtx_REG (Pmode
, 12);
29344 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
29345 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
29347 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
29348 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
29352 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
29354 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
29356 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
29359 /* Generate a tail call to the target function. */
29360 if (!TREE_USED (function
))
29362 assemble_external (function
);
29363 TREE_USED (function
) = 1;
29365 funexp
= XEXP (DECL_RTL (function
), 0);
29366 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
29369 if (MACHOPIC_INDIRECT
)
29370 funexp
= machopic_indirect_call_target (funexp
);
29373 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29374 generate sibcall RTL explicitly. */
29375 insn
= emit_call_insn (
29376 gen_rtx_PARALLEL (VOIDmode
,
29378 gen_rtx_CALL (VOIDmode
,
29379 funexp
, const0_rtx
),
29380 gen_rtx_USE (VOIDmode
, const0_rtx
),
29381 simple_return_rtx
)));
29382 SIBLING_CALL_P (insn
) = 1;
29385 /* Run just enough of rest_of_compilation to get the insns emitted.
29386 There's not really enough bulk here to make other passes such as
29387 instruction scheduling worth while. Note that use_thunk calls
29388 assemble_start_function and assemble_end_function. */
29389 insn
= get_insns ();
29390 shorten_branches (insn
);
29391 final_start_function (insn
, file
, 1);
29392 final (insn
, file
, 1);
29393 final_end_function ();
29395 reload_completed
= 0;
29396 epilogue_completed
= 0;
29399 /* A quick summary of the various types of 'constant-pool tables'
29402 Target Flags Name One table per
29403 AIX (none) AIX TOC object file
29404 AIX -mfull-toc AIX TOC object file
29405 AIX -mminimal-toc AIX minimal TOC translation unit
29406 SVR4/EABI (none) SVR4 SDATA object file
29407 SVR4/EABI -fpic SVR4 pic object file
29408 SVR4/EABI -fPIC SVR4 PIC translation unit
29409 SVR4/EABI -mrelocatable EABI TOC function
29410 SVR4/EABI -maix AIX TOC object file
29411 SVR4/EABI -maix -mminimal-toc
29412 AIX minimal TOC translation unit
29414 Name Reg. Set by entries contains:
29415 made by addrs? fp? sum?
29417 AIX TOC 2 crt0 as Y option option
29418 AIX minimal TOC 30 prolog gcc Y Y option
29419 SVR4 SDATA 13 crt0 gcc N Y N
29420 SVR4 pic 30 prolog ld Y not yet N
29421 SVR4 PIC 30 prolog gcc Y option option
29422 EABI TOC 30 prolog gcc Y option option
29426 /* Hash functions for the hash table. */
29429 rs6000_hash_constant (rtx k
)
29431 enum rtx_code code
= GET_CODE (k
);
29432 machine_mode mode
= GET_MODE (k
);
29433 unsigned result
= (code
<< 3) ^ mode
;
29434 const char *format
;
29437 format
= GET_RTX_FORMAT (code
);
29438 flen
= strlen (format
);
29444 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
29446 case CONST_WIDE_INT
:
29449 flen
= CONST_WIDE_INT_NUNITS (k
);
29450 for (i
= 0; i
< flen
; i
++)
29451 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
29456 if (mode
!= VOIDmode
)
29457 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
29469 for (; fidx
< flen
; fidx
++)
29470 switch (format
[fidx
])
29475 const char *str
= XSTR (k
, fidx
);
29476 len
= strlen (str
);
29477 result
= result
* 613 + len
;
29478 for (i
= 0; i
< len
; i
++)
29479 result
= result
* 613 + (unsigned) str
[i
];
29484 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
29488 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
29491 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
29492 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
29496 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
29497 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
29504 gcc_unreachable ();
29511 toc_hasher::hash (toc_hash_struct
*thc
)
29513 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
29516 /* Compare H1 and H2 for equivalence. */
29519 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
29524 if (h1
->key_mode
!= h2
->key_mode
)
29527 return rtx_equal_p (r1
, r2
);
29530 /* These are the names given by the C++ front-end to vtables, and
29531 vtable-like objects. Ideally, this logic should not be here;
29532 instead, there should be some programmatic way of inquiring as
29533 to whether or not an object is a vtable. */
29535 #define VTABLE_NAME_P(NAME) \
29536 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29537 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29538 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29539 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29540 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29542 #ifdef NO_DOLLAR_IN_LABEL
29543 /* Return a GGC-allocated character string translating dollar signs in
29544 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29547 rs6000_xcoff_strip_dollar (const char *name
)
29553 q
= (const char *) strchr (name
, '$');
29555 if (q
== 0 || q
== name
)
29558 len
= strlen (name
);
29559 strip
= XALLOCAVEC (char, len
+ 1);
29560 strcpy (strip
, name
);
29561 p
= strip
+ (q
- name
);
29565 p
= strchr (p
+ 1, '$');
29568 return ggc_alloc_string (strip
, len
);
29573 rs6000_output_symbol_ref (FILE *file
, rtx x
)
29575 const char *name
= XSTR (x
, 0);
29577 /* Currently C++ toc references to vtables can be emitted before it
29578 is decided whether the vtable is public or private. If this is
29579 the case, then the linker will eventually complain that there is
29580 a reference to an unknown section. Thus, for vtables only,
29581 we emit the TOC reference to reference the identifier and not the
29583 if (VTABLE_NAME_P (name
))
29585 RS6000_OUTPUT_BASENAME (file
, name
);
29588 assemble_name (file
, name
);
29591 /* Output a TOC entry. We derive the entry name from what is being
29595 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
29598 const char *name
= buf
;
29600 HOST_WIDE_INT offset
= 0;
29602 gcc_assert (!TARGET_NO_TOC
);
29604 /* When the linker won't eliminate them, don't output duplicate
29605 TOC entries (this happens on AIX if there is any kind of TOC,
29606 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29608 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
29610 struct toc_hash_struct
*h
;
29612 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29613 time because GGC is not initialized at that point. */
29614 if (toc_hash_table
== NULL
)
29615 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
29617 h
= ggc_alloc
<toc_hash_struct
> ();
29619 h
->key_mode
= mode
;
29620 h
->labelno
= labelno
;
29622 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
29623 if (*found
== NULL
)
29625 else /* This is indeed a duplicate.
29626 Set this label equal to that label. */
29628 fputs ("\t.set ", file
);
29629 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29630 fprintf (file
, "%d,", labelno
);
29631 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29632 fprintf (file
, "%d\n", ((*found
)->labelno
));
29635 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
29636 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
29637 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
29639 fputs ("\t.set ", file
);
29640 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29641 fprintf (file
, "%d,", labelno
);
29642 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29643 fprintf (file
, "%d\n", ((*found
)->labelno
));
29650 /* If we're going to put a double constant in the TOC, make sure it's
29651 aligned properly when strict alignment is on. */
29652 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
29653 && STRICT_ALIGNMENT
29654 && GET_MODE_BITSIZE (mode
) >= 64
29655 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
29656 ASM_OUTPUT_ALIGN (file
, 3);
29659 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
29661 /* Handle FP constants specially. Note that if we have a minimal
29662 TOC, things we put here aren't actually in the TOC, so we can allow
29664 if (GET_CODE (x
) == CONST_DOUBLE
&&
29665 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
29666 || GET_MODE (x
) == IFmode
|| GET_MODE (x
) == KFmode
))
29670 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29671 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29673 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29677 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29678 fputs (DOUBLE_INT_ASM_OP
, file
);
29680 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29681 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29682 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29683 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
29684 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29685 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
29686 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
29687 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
29692 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29693 fputs ("\t.long ", file
);
29695 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29696 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29697 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29698 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29699 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29700 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29704 else if (GET_CODE (x
) == CONST_DOUBLE
&&
29705 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
29709 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29710 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29712 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29716 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29717 fputs (DOUBLE_INT_ASM_OP
, file
);
29719 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29720 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29721 fprintf (file
, "0x%lx%08lx\n",
29722 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29723 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
29728 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29729 fputs ("\t.long ", file
);
29731 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29732 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29733 fprintf (file
, "0x%lx,0x%lx\n",
29734 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29738 else if (GET_CODE (x
) == CONST_DOUBLE
&&
29739 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
29743 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29744 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29746 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29750 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29751 fputs (DOUBLE_INT_ASM_OP
, file
);
29753 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
29754 if (WORDS_BIG_ENDIAN
)
29755 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
29757 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
29762 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29763 fputs ("\t.long ", file
);
29765 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
29766 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
29770 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
29772 unsigned HOST_WIDE_INT low
;
29773 HOST_WIDE_INT high
;
29775 low
= INTVAL (x
) & 0xffffffff;
29776 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
29778 /* TOC entries are always Pmode-sized, so when big-endian
29779 smaller integer constants in the TOC need to be padded.
29780 (This is still a win over putting the constants in
29781 a separate constant pool, because then we'd have
29782 to have both a TOC entry _and_ the actual constant.)
29784 For a 32-bit target, CONST_INT values are loaded and shifted
29785 entirely within `low' and can be stored in one TOC entry. */
29787 /* It would be easy to make this work, but it doesn't now. */
29788 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
29790 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
29793 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
29794 high
= (HOST_WIDE_INT
) low
>> 32;
29800 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29801 fputs (DOUBLE_INT_ASM_OP
, file
);
29803 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
29804 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29805 fprintf (file
, "0x%lx%08lx\n",
29806 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29811 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
29813 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29814 fputs ("\t.long ", file
);
29816 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
29817 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29818 fprintf (file
, "0x%lx,0x%lx\n",
29819 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29823 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29824 fputs ("\t.long ", file
);
29826 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
29827 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
29833 if (GET_CODE (x
) == CONST
)
29835 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
29836 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
29838 base
= XEXP (XEXP (x
, 0), 0);
29839 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
29842 switch (GET_CODE (base
))
29845 name
= XSTR (base
, 0);
29849 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
29850 CODE_LABEL_NUMBER (XEXP (base
, 0)));
29854 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
29858 gcc_unreachable ();
29861 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29862 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
29865 fputs ("\t.tc ", file
);
29866 RS6000_OUTPUT_BASENAME (file
, name
);
29869 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
29871 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
29873 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29874 after other TOC symbols, reducing overflow of small TOC access
29875 to [TC] symbols. */
29876 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
29877 ? "[TE]," : "[TC],", file
);
29880 /* Currently C++ toc references to vtables can be emitted before it
29881 is decided whether the vtable is public or private. If this is
29882 the case, then the linker will eventually complain that there is
29883 a TOC reference to an unknown section. Thus, for vtables only,
29884 we emit the TOC reference to reference the symbol and not the
29886 if (VTABLE_NAME_P (name
))
29888 RS6000_OUTPUT_BASENAME (file
, name
);
29890 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
29891 else if (offset
> 0)
29892 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
29895 output_addr_const (file
, x
);
29898 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
)
29900 switch (SYMBOL_REF_TLS_MODEL (base
))
29904 case TLS_MODEL_LOCAL_EXEC
:
29905 fputs ("@le", file
);
29907 case TLS_MODEL_INITIAL_EXEC
:
29908 fputs ("@ie", file
);
29910 /* Use global-dynamic for local-dynamic. */
29911 case TLS_MODEL_GLOBAL_DYNAMIC
:
29912 case TLS_MODEL_LOCAL_DYNAMIC
:
29914 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
29915 fputs ("\t.tc .", file
);
29916 RS6000_OUTPUT_BASENAME (file
, name
);
29917 fputs ("[TC],", file
);
29918 output_addr_const (file
, x
);
29919 fputs ("@m", file
);
29922 gcc_unreachable ();
29930 /* Output an assembler pseudo-op to write an ASCII string of N characters
29931 starting at P to FILE.
29933 On the RS/6000, we have to do this using the .byte operation and
29934 write out special characters outside the quoted string.
29935 Also, the assembler is broken; very long strings are truncated,
29936 so we must artificially break them up early. */
29939 output_ascii (FILE *file
, const char *p
, int n
)
29942 int i
, count_string
;
29943 const char *for_string
= "\t.byte \"";
29944 const char *for_decimal
= "\t.byte ";
29945 const char *to_close
= NULL
;
29948 for (i
= 0; i
< n
; i
++)
29951 if (c
>= ' ' && c
< 0177)
29954 fputs (for_string
, file
);
29957 /* Write two quotes to get one. */
29965 for_decimal
= "\"\n\t.byte ";
29969 if (count_string
>= 512)
29971 fputs (to_close
, file
);
29973 for_string
= "\t.byte \"";
29974 for_decimal
= "\t.byte ";
29982 fputs (for_decimal
, file
);
29983 fprintf (file
, "%d", c
);
29985 for_string
= "\n\t.byte \"";
29986 for_decimal
= ", ";
29992 /* Now close the string if we have written one. Then end the line. */
29994 fputs (to_close
, file
);
29997 /* Generate a unique section name for FILENAME for a section type
29998 represented by SECTION_DESC. Output goes into BUF.
30000 SECTION_DESC can be any string, as long as it is different for each
30001 possible section type.
30003 We name the section in the same manner as xlc. The name begins with an
30004 underscore followed by the filename (after stripping any leading directory
30005 names) with the last period replaced by the string SECTION_DESC. If
30006 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30010 rs6000_gen_section_name (char **buf
, const char *filename
,
30011 const char *section_desc
)
30013 const char *q
, *after_last_slash
, *last_period
= 0;
30017 after_last_slash
= filename
;
30018 for (q
= filename
; *q
; q
++)
30021 after_last_slash
= q
+ 1;
30022 else if (*q
== '.')
30026 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
30027 *buf
= (char *) xmalloc (len
);
30032 for (q
= after_last_slash
; *q
; q
++)
30034 if (q
== last_period
)
30036 strcpy (p
, section_desc
);
30037 p
+= strlen (section_desc
);
30041 else if (ISALNUM (*q
))
30045 if (last_period
== 0)
30046 strcpy (p
, section_desc
);
30051 /* Emit profile function. */
30054 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
30056 /* Non-standard profiling for kernels, which just saves LR then calls
30057 _mcount without worrying about arg saves. The idea is to change
30058 the function prologue as little as possible as it isn't easy to
30059 account for arg save/restore code added just for _mcount. */
30060 if (TARGET_PROFILE_KERNEL
)
30063 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
30065 #ifndef NO_PROFILE_COUNTERS
30066 # define NO_PROFILE_COUNTERS 0
30068 if (NO_PROFILE_COUNTERS
)
30069 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
30070 LCT_NORMAL
, VOIDmode
);
30074 const char *label_name
;
30077 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
30078 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
30079 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
30081 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
30082 LCT_NORMAL
, VOIDmode
, fun
, Pmode
);
30085 else if (DEFAULT_ABI
== ABI_DARWIN
)
30087 const char *mcount_name
= RS6000_MCOUNT
;
30088 int caller_addr_regno
= LR_REGNO
;
30090 /* Be conservative and always set this, at least for now. */
30091 crtl
->uses_pic_offset_table
= 1;
30094 /* For PIC code, set up a stub and collect the caller's address
30095 from r0, which is where the prologue puts it. */
30096 if (MACHOPIC_INDIRECT
30097 && crtl
->uses_pic_offset_table
)
30098 caller_addr_regno
= 0;
30100 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
30101 LCT_NORMAL
, VOIDmode
,
30102 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
30106 /* Write function profiler code. */
30109 output_function_profiler (FILE *file
, int labelno
)
30113 switch (DEFAULT_ABI
)
30116 gcc_unreachable ();
30121 warning (0, "no profiling of 64-bit code for this ABI");
30124 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
30125 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
30126 if (NO_PROFILE_COUNTERS
)
30128 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30129 reg_names
[0], reg_names
[1]);
30131 else if (TARGET_SECURE_PLT
&& flag_pic
)
30133 if (TARGET_LINK_STACK
)
30136 get_ppc476_thunk_name (name
);
30137 asm_fprintf (file
, "\tbl %s\n", name
);
30140 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
30141 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30142 reg_names
[0], reg_names
[1]);
30143 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
30144 asm_fprintf (file
, "\taddis %s,%s,",
30145 reg_names
[12], reg_names
[12]);
30146 assemble_name (file
, buf
);
30147 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
30148 assemble_name (file
, buf
);
30149 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
30151 else if (flag_pic
== 1)
30153 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
30154 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30155 reg_names
[0], reg_names
[1]);
30156 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
30157 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
30158 assemble_name (file
, buf
);
30159 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
30161 else if (flag_pic
> 1)
30163 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30164 reg_names
[0], reg_names
[1]);
30165 /* Now, we need to get the address of the label. */
30166 if (TARGET_LINK_STACK
)
30169 get_ppc476_thunk_name (name
);
30170 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
30171 assemble_name (file
, buf
);
30172 fputs ("-.\n1:", file
);
30173 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
30174 asm_fprintf (file
, "\taddi %s,%s,4\n",
30175 reg_names
[11], reg_names
[11]);
30179 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
30180 assemble_name (file
, buf
);
30181 fputs ("-.\n1:", file
);
30182 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
30184 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
30185 reg_names
[0], reg_names
[11]);
30186 asm_fprintf (file
, "\tadd %s,%s,%s\n",
30187 reg_names
[0], reg_names
[0], reg_names
[11]);
30191 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
30192 assemble_name (file
, buf
);
30193 fputs ("@ha\n", file
);
30194 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30195 reg_names
[0], reg_names
[1]);
30196 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
30197 assemble_name (file
, buf
);
30198 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
30201 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30202 fprintf (file
, "\tbl %s%s\n",
30203 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
30209 /* Don't do anything, done in output_profile_hook (). */
30216 /* The following variable value is the last issued insn. */
30218 static rtx_insn
*last_scheduled_insn
;
30220 /* The following variable helps to balance issuing of load and
30221 store instructions */
30223 static int load_store_pendulum
;
30225 /* The following variable helps pair divide insns during scheduling. */
30226 static int divide_cnt
;
30227 /* The following variable helps pair and alternate vector and vector load
30228 insns during scheduling. */
30229 static int vec_pairing
;
30232 /* Power4 load update and store update instructions are cracked into a
30233 load or store and an integer insn which are executed in the same cycle.
30234 Branches have their own dispatch slot which does not count against the
30235 GCC issue rate, but it changes the program flow so there are no other
30236 instructions to issue in this cycle. */
30239 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
30241 last_scheduled_insn
= insn
;
30242 if (GET_CODE (PATTERN (insn
)) == USE
30243 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30245 cached_can_issue_more
= more
;
30246 return cached_can_issue_more
;
30249 if (insn_terminates_group_p (insn
, current_group
))
30251 cached_can_issue_more
= 0;
30252 return cached_can_issue_more
;
30255 /* If no reservation, but reach here */
30256 if (recog_memoized (insn
) < 0)
30259 if (rs6000_sched_groups
)
30261 if (is_microcoded_insn (insn
))
30262 cached_can_issue_more
= 0;
30263 else if (is_cracked_insn (insn
))
30264 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
30266 cached_can_issue_more
= more
- 1;
30268 return cached_can_issue_more
;
30271 if (rs6000_tune
== PROCESSOR_CELL
&& is_nonpipeline_insn (insn
))
30274 cached_can_issue_more
= more
- 1;
30275 return cached_can_issue_more
;
30279 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
30281 int r
= rs6000_variable_issue_1 (insn
, more
);
30283 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
30287 /* Adjust the cost of a scheduling dependency. Return the new cost of
30288 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30291 rs6000_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
30294 enum attr_type attr_type
;
30296 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
30303 /* Data dependency; DEP_INSN writes a register that INSN reads
30304 some cycles later. */
30306 /* Separate a load from a narrower, dependent store. */
30307 if ((rs6000_sched_groups
|| rs6000_tune
== PROCESSOR_POWER9
)
30308 && GET_CODE (PATTERN (insn
)) == SET
30309 && GET_CODE (PATTERN (dep_insn
)) == SET
30310 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
30311 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
30312 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
30313 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
30316 attr_type
= get_attr_type (insn
);
30321 /* Tell the first scheduling pass about the latency between
30322 a mtctr and bctr (and mtlr and br/blr). The first
30323 scheduling pass will not know about this latency since
30324 the mtctr instruction, which has the latency associated
30325 to it, will be generated by reload. */
30328 /* Leave some extra cycles between a compare and its
30329 dependent branch, to inhibit expensive mispredicts. */
30330 if ((rs6000_tune
== PROCESSOR_PPC603
30331 || rs6000_tune
== PROCESSOR_PPC604
30332 || rs6000_tune
== PROCESSOR_PPC604e
30333 || rs6000_tune
== PROCESSOR_PPC620
30334 || rs6000_tune
== PROCESSOR_PPC630
30335 || rs6000_tune
== PROCESSOR_PPC750
30336 || rs6000_tune
== PROCESSOR_PPC7400
30337 || rs6000_tune
== PROCESSOR_PPC7450
30338 || rs6000_tune
== PROCESSOR_PPCE5500
30339 || rs6000_tune
== PROCESSOR_PPCE6500
30340 || rs6000_tune
== PROCESSOR_POWER4
30341 || rs6000_tune
== PROCESSOR_POWER5
30342 || rs6000_tune
== PROCESSOR_POWER7
30343 || rs6000_tune
== PROCESSOR_POWER8
30344 || rs6000_tune
== PROCESSOR_POWER9
30345 || rs6000_tune
== PROCESSOR_CELL
)
30346 && recog_memoized (dep_insn
)
30347 && (INSN_CODE (dep_insn
) >= 0))
30349 switch (get_attr_type (dep_insn
))
30352 case TYPE_FPCOMPARE
:
30353 case TYPE_CR_LOGICAL
:
30357 if (get_attr_dot (dep_insn
) == DOT_YES
)
30362 if (get_attr_dot (dep_insn
) == DOT_YES
30363 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
30374 if ((rs6000_tune
== PROCESSOR_POWER6
)
30375 && recog_memoized (dep_insn
)
30376 && (INSN_CODE (dep_insn
) >= 0))
30379 if (GET_CODE (PATTERN (insn
)) != SET
)
30380 /* If this happens, we have to extend this to schedule
30381 optimally. Return default for now. */
30384 /* Adjust the cost for the case where the value written
30385 by a fixed point operation is used as the address
30386 gen value on a store. */
30387 switch (get_attr_type (dep_insn
))
30392 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30393 return get_attr_sign_extend (dep_insn
)
30394 == SIGN_EXTEND_YES
? 6 : 4;
30399 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30400 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30410 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30418 if (get_attr_update (dep_insn
) == UPDATE_YES
30419 && ! rs6000_store_data_bypass_p (dep_insn
, insn
))
30425 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30431 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30432 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30442 if ((rs6000_tune
== PROCESSOR_POWER6
)
30443 && recog_memoized (dep_insn
)
30444 && (INSN_CODE (dep_insn
) >= 0))
30447 /* Adjust the cost for the case where the value written
30448 by a fixed point instruction is used within the address
30449 gen portion of a subsequent load(u)(x) */
30450 switch (get_attr_type (dep_insn
))
30455 if (set_to_load_agen (dep_insn
, insn
))
30456 return get_attr_sign_extend (dep_insn
)
30457 == SIGN_EXTEND_YES
? 6 : 4;
30462 if (set_to_load_agen (dep_insn
, insn
))
30463 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30473 if (set_to_load_agen (dep_insn
, insn
))
30481 if (get_attr_update (dep_insn
) == UPDATE_YES
30482 && set_to_load_agen (dep_insn
, insn
))
30488 if (set_to_load_agen (dep_insn
, insn
))
30494 if (set_to_load_agen (dep_insn
, insn
))
30495 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30505 if ((rs6000_tune
== PROCESSOR_POWER6
)
30506 && get_attr_update (insn
) == UPDATE_NO
30507 && recog_memoized (dep_insn
)
30508 && (INSN_CODE (dep_insn
) >= 0)
30509 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
30516 /* Fall out to return default cost. */
30520 case REG_DEP_OUTPUT
:
30521 /* Output dependency; DEP_INSN writes a register that INSN writes some
30523 if ((rs6000_tune
== PROCESSOR_POWER6
)
30524 && recog_memoized (dep_insn
)
30525 && (INSN_CODE (dep_insn
) >= 0))
30527 attr_type
= get_attr_type (insn
);
30532 case TYPE_FPSIMPLE
:
30533 if (get_attr_type (dep_insn
) == TYPE_FP
30534 || get_attr_type (dep_insn
) == TYPE_FPSIMPLE
)
30538 if (get_attr_update (insn
) == UPDATE_NO
30539 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
30546 /* Fall through, no cost for output dependency. */
30550 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30555 gcc_unreachable ();
30561 /* Debug version of rs6000_adjust_cost. */
30564 rs6000_debug_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
30565 int cost
, unsigned int dw
)
30567 int ret
= rs6000_adjust_cost (insn
, dep_type
, dep_insn
, cost
, dw
);
30575 default: dep
= "unknown depencency"; break;
30576 case REG_DEP_TRUE
: dep
= "data dependency"; break;
30577 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
30578 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
30582 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30583 "%s, insn:\n", ret
, cost
, dep
);
30591 /* The function returns a true if INSN is microcoded.
30592 Return false otherwise. */
30595 is_microcoded_insn (rtx_insn
*insn
)
30597 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30598 || GET_CODE (PATTERN (insn
)) == USE
30599 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30602 if (rs6000_tune
== PROCESSOR_CELL
)
30603 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
30605 if (rs6000_sched_groups
30606 && (rs6000_tune
== PROCESSOR_POWER4
|| rs6000_tune
== PROCESSOR_POWER5
))
30608 enum attr_type type
= get_attr_type (insn
);
30609 if ((type
== TYPE_LOAD
30610 && get_attr_update (insn
) == UPDATE_YES
30611 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
30612 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
30613 && get_attr_update (insn
) == UPDATE_YES
30614 && get_attr_indexed (insn
) == INDEXED_YES
)
30615 || type
== TYPE_MFCR
)
30622 /* The function returns true if INSN is cracked into 2 instructions
30623 by the processor (and therefore occupies 2 issue slots). */
30626 is_cracked_insn (rtx_insn
*insn
)
30628 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30629 || GET_CODE (PATTERN (insn
)) == USE
30630 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30633 if (rs6000_sched_groups
30634 && (rs6000_tune
== PROCESSOR_POWER4
|| rs6000_tune
== PROCESSOR_POWER5
))
30636 enum attr_type type
= get_attr_type (insn
);
30637 if ((type
== TYPE_LOAD
30638 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
30639 && get_attr_update (insn
) == UPDATE_NO
)
30640 || (type
== TYPE_LOAD
30641 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
30642 && get_attr_update (insn
) == UPDATE_YES
30643 && get_attr_indexed (insn
) == INDEXED_NO
)
30644 || (type
== TYPE_STORE
30645 && get_attr_update (insn
) == UPDATE_YES
30646 && get_attr_indexed (insn
) == INDEXED_NO
)
30647 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
30648 && get_attr_update (insn
) == UPDATE_YES
)
30649 || (type
== TYPE_CR_LOGICAL
30650 && get_attr_cr_logical_3op (insn
) == CR_LOGICAL_3OP_YES
)
30651 || (type
== TYPE_EXTS
30652 && get_attr_dot (insn
) == DOT_YES
)
30653 || (type
== TYPE_SHIFT
30654 && get_attr_dot (insn
) == DOT_YES
30655 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
30656 || (type
== TYPE_MUL
30657 && get_attr_dot (insn
) == DOT_YES
)
30658 || type
== TYPE_DIV
30659 || (type
== TYPE_INSERT
30660 && get_attr_size (insn
) == SIZE_32
))
30667 /* The function returns true if INSN can be issued only from
30668 the branch slot. */
30671 is_branch_slot_insn (rtx_insn
*insn
)
30673 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30674 || GET_CODE (PATTERN (insn
)) == USE
30675 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30678 if (rs6000_sched_groups
)
30680 enum attr_type type
= get_attr_type (insn
);
30681 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
30689 /* The function returns true if out_inst sets a value that is
30690 used in the address generation computation of in_insn */
30692 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
30694 rtx out_set
, in_set
;
30696 /* For performance reasons, only handle the simple case where
30697 both loads are a single_set. */
30698 out_set
= single_set (out_insn
);
30701 in_set
= single_set (in_insn
);
30703 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
30709 /* Try to determine base/offset/size parts of the given MEM.
30710 Return true if successful, false if all the values couldn't
30713 This function only looks for REG or REG+CONST address forms.
30714 REG+REG address form will return false. */
30717 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
30718 HOST_WIDE_INT
*size
)
30721 if MEM_SIZE_KNOWN_P (mem
)
30722 *size
= MEM_SIZE (mem
);
30726 addr_rtx
= (XEXP (mem
, 0));
30727 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
30728 addr_rtx
= XEXP (addr_rtx
, 1);
30731 while (GET_CODE (addr_rtx
) == PLUS
30732 && CONST_INT_P (XEXP (addr_rtx
, 1)))
30734 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
30735 addr_rtx
= XEXP (addr_rtx
, 0);
30737 if (!REG_P (addr_rtx
))
30744 /* The function returns true if the target storage location of
30745 mem1 is adjacent to the target storage location of mem2 */
30746 /* Return 1 if memory locations are adjacent. */
30749 adjacent_mem_locations (rtx mem1
, rtx mem2
)
30752 HOST_WIDE_INT off1
, size1
, off2
, size2
;
30754 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
30755 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
30756 return ((REGNO (reg1
) == REGNO (reg2
))
30757 && ((off1
+ size1
== off2
)
30758 || (off2
+ size2
== off1
)));
30763 /* This function returns true if it can be determined that the two MEM
30764 locations overlap by at least 1 byte based on base reg/offset/size. */
30767 mem_locations_overlap (rtx mem1
, rtx mem2
)
30770 HOST_WIDE_INT off1
, size1
, off2
, size2
;
30772 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
30773 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
30774 return ((REGNO (reg1
) == REGNO (reg2
))
30775 && (((off1
<= off2
) && (off1
+ size1
> off2
))
30776 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
30781 /* A C statement (sans semicolon) to update the integer scheduling
30782 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30783 INSN earlier, reduce the priority to execute INSN later. Do not
30784 define this macro if you do not need to adjust the scheduling
30785 priorities of insns. */
30788 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
30790 rtx load_mem
, str_mem
;
30791 /* On machines (like the 750) which have asymmetric integer units,
30792 where one integer unit can do multiply and divides and the other
30793 can't, reduce the priority of multiply/divide so it is scheduled
30794 before other integer operations. */
30797 if (! INSN_P (insn
))
30800 if (GET_CODE (PATTERN (insn
)) == USE
)
30803 switch (rs6000_tune
) {
30804 case PROCESSOR_PPC750
:
30805 switch (get_attr_type (insn
))
30812 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
30813 priority
, priority
);
30814 if (priority
>= 0 && priority
< 0x01000000)
30821 if (insn_must_be_first_in_group (insn
)
30822 && reload_completed
30823 && current_sched_info
->sched_max_insns_priority
30824 && rs6000_sched_restricted_insns_priority
)
30827 /* Prioritize insns that can be dispatched only in the first
30829 if (rs6000_sched_restricted_insns_priority
== 1)
30830 /* Attach highest priority to insn. This means that in
30831 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30832 precede 'priority' (critical path) considerations. */
30833 return current_sched_info
->sched_max_insns_priority
;
30834 else if (rs6000_sched_restricted_insns_priority
== 2)
30835 /* Increase priority of insn by a minimal amount. This means that in
30836 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30837 considerations precede dispatch-slot restriction considerations. */
30838 return (priority
+ 1);
30841 if (rs6000_tune
== PROCESSOR_POWER6
30842 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
30843 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
30844 /* Attach highest priority to insn if the scheduler has just issued two
30845 stores and this instruction is a load, or two loads and this instruction
30846 is a store. Power6 wants loads and stores scheduled alternately
30848 return current_sched_info
->sched_max_insns_priority
;
30853 /* Return true if the instruction is nonpipelined on the Cell. */
30855 is_nonpipeline_insn (rtx_insn
*insn
)
30857 enum attr_type type
;
30858 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30859 || GET_CODE (PATTERN (insn
)) == USE
30860 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30863 type
= get_attr_type (insn
);
30864 if (type
== TYPE_MUL
30865 || type
== TYPE_DIV
30866 || type
== TYPE_SDIV
30867 || type
== TYPE_DDIV
30868 || type
== TYPE_SSQRT
30869 || type
== TYPE_DSQRT
30870 || type
== TYPE_MFCR
30871 || type
== TYPE_MFCRF
30872 || type
== TYPE_MFJMPR
)
30880 /* Return how many instructions the machine can issue per cycle. */
30883 rs6000_issue_rate (void)
30885 /* Unless scheduling for register pressure, use issue rate of 1 for
30886 first scheduling pass to decrease degradation. */
30887 if (!reload_completed
&& !flag_sched_pressure
)
30890 switch (rs6000_tune
) {
30891 case PROCESSOR_RS64A
:
30892 case PROCESSOR_PPC601
: /* ? */
30893 case PROCESSOR_PPC7450
:
30895 case PROCESSOR_PPC440
:
30896 case PROCESSOR_PPC603
:
30897 case PROCESSOR_PPC750
:
30898 case PROCESSOR_PPC7400
:
30899 case PROCESSOR_PPC8540
:
30900 case PROCESSOR_PPC8548
:
30901 case PROCESSOR_CELL
:
30902 case PROCESSOR_PPCE300C2
:
30903 case PROCESSOR_PPCE300C3
:
30904 case PROCESSOR_PPCE500MC
:
30905 case PROCESSOR_PPCE500MC64
:
30906 case PROCESSOR_PPCE5500
:
30907 case PROCESSOR_PPCE6500
:
30908 case PROCESSOR_TITAN
:
30910 case PROCESSOR_PPC476
:
30911 case PROCESSOR_PPC604
:
30912 case PROCESSOR_PPC604e
:
30913 case PROCESSOR_PPC620
:
30914 case PROCESSOR_PPC630
:
30916 case PROCESSOR_POWER4
:
30917 case PROCESSOR_POWER5
:
30918 case PROCESSOR_POWER6
:
30919 case PROCESSOR_POWER7
:
30921 case PROCESSOR_POWER8
:
30923 case PROCESSOR_POWER9
:
30930 /* Return how many instructions to look ahead for better insn
30934 rs6000_use_sched_lookahead (void)
30936 switch (rs6000_tune
)
30938 case PROCESSOR_PPC8540
:
30939 case PROCESSOR_PPC8548
:
30942 case PROCESSOR_CELL
:
30943 return (reload_completed
? 8 : 0);
30950 /* We are choosing insn from the ready queue. Return zero if INSN can be
30953 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
30955 if (ready_index
== 0)
30958 if (rs6000_tune
!= PROCESSOR_CELL
)
30961 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
30963 if (!reload_completed
30964 || is_nonpipeline_insn (insn
)
30965 || is_microcoded_insn (insn
))
30971 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30972 and return true. */
30975 find_mem_ref (rtx pat
, rtx
*mem_ref
)
30980 /* stack_tie does not produce any real memory traffic. */
30981 if (tie_operand (pat
, VOIDmode
))
30984 if (GET_CODE (pat
) == MEM
)
30990 /* Recursively process the pattern. */
30991 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
30993 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
30997 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
31000 else if (fmt
[i
] == 'E')
31001 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
31003 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
31011 /* Determine if PAT is a PATTERN of a load insn. */
31014 is_load_insn1 (rtx pat
, rtx
*load_mem
)
31016 if (!pat
|| pat
== NULL_RTX
)
31019 if (GET_CODE (pat
) == SET
)
31020 return find_mem_ref (SET_SRC (pat
), load_mem
);
31022 if (GET_CODE (pat
) == PARALLEL
)
31026 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
31027 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
31034 /* Determine if INSN loads from memory. */
31037 is_load_insn (rtx insn
, rtx
*load_mem
)
31039 if (!insn
|| !INSN_P (insn
))
31045 return is_load_insn1 (PATTERN (insn
), load_mem
);
31048 /* Determine if PAT is a PATTERN of a store insn. */
31051 is_store_insn1 (rtx pat
, rtx
*str_mem
)
31053 if (!pat
|| pat
== NULL_RTX
)
31056 if (GET_CODE (pat
) == SET
)
31057 return find_mem_ref (SET_DEST (pat
), str_mem
);
31059 if (GET_CODE (pat
) == PARALLEL
)
31063 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
31064 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
31071 /* Determine if INSN stores to memory. */
31074 is_store_insn (rtx insn
, rtx
*str_mem
)
31076 if (!insn
|| !INSN_P (insn
))
31079 return is_store_insn1 (PATTERN (insn
), str_mem
);
31082 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31085 is_power9_pairable_vec_type (enum attr_type type
)
31089 case TYPE_VECSIMPLE
:
31090 case TYPE_VECCOMPLEX
:
31094 case TYPE_VECFLOAT
:
31096 case TYPE_VECDOUBLE
:
31104 /* Returns whether the dependence between INSN and NEXT is considered
31105 costly by the given target. */
31108 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
31112 rtx load_mem
, str_mem
;
31114 /* If the flag is not enabled - no dependence is considered costly;
31115 allow all dependent insns in the same group.
31116 This is the most aggressive option. */
31117 if (rs6000_sched_costly_dep
== no_dep_costly
)
31120 /* If the flag is set to 1 - a dependence is always considered costly;
31121 do not allow dependent instructions in the same group.
31122 This is the most conservative option. */
31123 if (rs6000_sched_costly_dep
== all_deps_costly
)
31126 insn
= DEP_PRO (dep
);
31127 next
= DEP_CON (dep
);
31129 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
31130 && is_load_insn (next
, &load_mem
)
31131 && is_store_insn (insn
, &str_mem
))
31132 /* Prevent load after store in the same group. */
31135 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
31136 && is_load_insn (next
, &load_mem
)
31137 && is_store_insn (insn
, &str_mem
)
31138 && DEP_TYPE (dep
) == REG_DEP_TRUE
31139 && mem_locations_overlap(str_mem
, load_mem
))
31140 /* Prevent load after store in the same group if it is a true
31144 /* The flag is set to X; dependences with latency >= X are considered costly,
31145 and will not be scheduled in the same group. */
31146 if (rs6000_sched_costly_dep
<= max_dep_latency
31147 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
31153 /* Return the next insn after INSN that is found before TAIL is reached,
31154 skipping any "non-active" insns - insns that will not actually occupy
31155 an issue slot. Return NULL_RTX if such an insn is not found. */
31158 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
31160 if (insn
== NULL_RTX
|| insn
== tail
)
31165 insn
= NEXT_INSN (insn
);
31166 if (insn
== NULL_RTX
|| insn
== tail
)
31170 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
31171 || (NONJUMP_INSN_P (insn
)
31172 && GET_CODE (PATTERN (insn
)) != USE
31173 && GET_CODE (PATTERN (insn
)) != CLOBBER
31174 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
31180 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31183 power9_sched_reorder2 (rtx_insn
**ready
, int lastpos
)
31188 enum attr_type type
, type2
;
31190 type
= get_attr_type (last_scheduled_insn
);
31192 /* Try to issue fixed point divides back-to-back in pairs so they will be
31193 routed to separate execution units and execute in parallel. */
31194 if (type
== TYPE_DIV
&& divide_cnt
== 0)
31196 /* First divide has been scheduled. */
31199 /* Scan the ready list looking for another divide, if found move it
31200 to the end of the list so it is chosen next. */
31204 if (recog_memoized (ready
[pos
]) >= 0
31205 && get_attr_type (ready
[pos
]) == TYPE_DIV
)
31208 for (i
= pos
; i
< lastpos
; i
++)
31209 ready
[i
] = ready
[i
+ 1];
31210 ready
[lastpos
] = tmp
;
31218 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31221 /* The best dispatch throughput for vector and vector load insns can be
31222 achieved by interleaving a vector and vector load such that they'll
31223 dispatch to the same superslice. If this pairing cannot be achieved
31224 then it is best to pair vector insns together and vector load insns
31227 To aid in this pairing, vec_pairing maintains the current state with
31228 the following values:
31230 0 : Initial state, no vecload/vector pairing has been started.
31232 1 : A vecload or vector insn has been issued and a candidate for
31233 pairing has been found and moved to the end of the ready
31235 if (type
== TYPE_VECLOAD
)
31237 /* Issued a vecload. */
31238 if (vec_pairing
== 0)
31240 int vecload_pos
= -1;
31241 /* We issued a single vecload, look for a vector insn to pair it
31242 with. If one isn't found, try to pair another vecload. */
31246 if (recog_memoized (ready
[pos
]) >= 0)
31248 type2
= get_attr_type (ready
[pos
]);
31249 if (is_power9_pairable_vec_type (type2
))
31251 /* Found a vector insn to pair with, move it to the
31252 end of the ready list so it is scheduled next. */
31254 for (i
= pos
; i
< lastpos
; i
++)
31255 ready
[i
] = ready
[i
+ 1];
31256 ready
[lastpos
] = tmp
;
31258 return cached_can_issue_more
;
31260 else if (type2
== TYPE_VECLOAD
&& vecload_pos
== -1)
31261 /* Remember position of first vecload seen. */
31266 if (vecload_pos
>= 0)
31268 /* Didn't find a vector to pair with but did find a vecload,
31269 move it to the end of the ready list. */
31270 tmp
= ready
[vecload_pos
];
31271 for (i
= vecload_pos
; i
< lastpos
; i
++)
31272 ready
[i
] = ready
[i
+ 1];
31273 ready
[lastpos
] = tmp
;
31275 return cached_can_issue_more
;
31279 else if (is_power9_pairable_vec_type (type
))
31281 /* Issued a vector operation. */
31282 if (vec_pairing
== 0)
31285 /* We issued a single vector insn, look for a vecload to pair it
31286 with. If one isn't found, try to pair another vector. */
31290 if (recog_memoized (ready
[pos
]) >= 0)
31292 type2
= get_attr_type (ready
[pos
]);
31293 if (type2
== TYPE_VECLOAD
)
31295 /* Found a vecload insn to pair with, move it to the
31296 end of the ready list so it is scheduled next. */
31298 for (i
= pos
; i
< lastpos
; i
++)
31299 ready
[i
] = ready
[i
+ 1];
31300 ready
[lastpos
] = tmp
;
31302 return cached_can_issue_more
;
31304 else if (is_power9_pairable_vec_type (type2
)
31306 /* Remember position of first vector insn seen. */
31313 /* Didn't find a vecload to pair with but did find a vector
31314 insn, move it to the end of the ready list. */
31315 tmp
= ready
[vec_pos
];
31316 for (i
= vec_pos
; i
< lastpos
; i
++)
31317 ready
[i
] = ready
[i
+ 1];
31318 ready
[lastpos
] = tmp
;
31320 return cached_can_issue_more
;
31325 /* We've either finished a vec/vecload pair, couldn't find an insn to
31326 continue the current pair, or the last insn had nothing to do with
31327 with pairing. In any case, reset the state. */
31331 return cached_can_issue_more
;
31334 /* We are about to begin issuing insns for this clock cycle. */
31337 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
31338 rtx_insn
**ready ATTRIBUTE_UNUSED
,
31339 int *pn_ready ATTRIBUTE_UNUSED
,
31340 int clock_var ATTRIBUTE_UNUSED
)
31342 int n_ready
= *pn_ready
;
31345 fprintf (dump
, "// rs6000_sched_reorder :\n");
31347 /* Reorder the ready list, if the second to last ready insn
31348 is a nonepipeline insn. */
31349 if (rs6000_tune
== PROCESSOR_CELL
&& n_ready
> 1)
31351 if (is_nonpipeline_insn (ready
[n_ready
- 1])
31352 && (recog_memoized (ready
[n_ready
- 2]) > 0))
31353 /* Simply swap first two insns. */
31354 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
31357 if (rs6000_tune
== PROCESSOR_POWER6
)
31358 load_store_pendulum
= 0;
31360 return rs6000_issue_rate ();
31363 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31366 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
31367 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
31370 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
31372 /* For Power6, we need to handle some special cases to try and keep the
31373 store queue from overflowing and triggering expensive flushes.
31375 This code monitors how load and store instructions are being issued
31376 and skews the ready list one way or the other to increase the likelihood
31377 that a desired instruction is issued at the proper time.
31379 A couple of things are done. First, we maintain a "load_store_pendulum"
31380 to track the current state of load/store issue.
31382 - If the pendulum is at zero, then no loads or stores have been
31383 issued in the current cycle so we do nothing.
31385 - If the pendulum is 1, then a single load has been issued in this
31386 cycle and we attempt to locate another load in the ready list to
31389 - If the pendulum is -2, then two stores have already been
31390 issued in this cycle, so we increase the priority of the first load
31391 in the ready list to increase it's likelihood of being chosen first
31394 - If the pendulum is -1, then a single store has been issued in this
31395 cycle and we attempt to locate another store in the ready list to
31396 issue with it, preferring a store to an adjacent memory location to
31397 facilitate store pairing in the store queue.
31399 - If the pendulum is 2, then two loads have already been
31400 issued in this cycle, so we increase the priority of the first store
31401 in the ready list to increase it's likelihood of being chosen first
31404 - If the pendulum < -2 or > 2, then do nothing.
31406 Note: This code covers the most common scenarios. There exist non
31407 load/store instructions which make use of the LSU and which
31408 would need to be accounted for to strictly model the behavior
31409 of the machine. Those instructions are currently unaccounted
31410 for to help minimize compile time overhead of this code.
31412 if (rs6000_tune
== PROCESSOR_POWER6
&& last_scheduled_insn
)
31417 rtx load_mem
, str_mem
;
31419 if (is_store_insn (last_scheduled_insn
, &str_mem
))
31420 /* Issuing a store, swing the load_store_pendulum to the left */
31421 load_store_pendulum
--;
31422 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
31423 /* Issuing a load, swing the load_store_pendulum to the right */
31424 load_store_pendulum
++;
31426 return cached_can_issue_more
;
31428 /* If the pendulum is balanced, or there is only one instruction on
31429 the ready list, then all is well, so return. */
31430 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
31431 return cached_can_issue_more
;
31433 if (load_store_pendulum
== 1)
31435 /* A load has been issued in this cycle. Scan the ready list
31436 for another load to issue with it */
31441 if (is_load_insn (ready
[pos
], &load_mem
))
31443 /* Found a load. Move it to the head of the ready list,
31444 and adjust it's priority so that it is more likely to
31447 for (i
=pos
; i
<*pn_ready
-1; i
++)
31448 ready
[i
] = ready
[i
+ 1];
31449 ready
[*pn_ready
-1] = tmp
;
31451 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31452 INSN_PRIORITY (tmp
)++;
31458 else if (load_store_pendulum
== -2)
31460 /* Two stores have been issued in this cycle. Increase the
31461 priority of the first load in the ready list to favor it for
31462 issuing in the next cycle. */
31467 if (is_load_insn (ready
[pos
], &load_mem
)
31469 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31471 INSN_PRIORITY (ready
[pos
])++;
31473 /* Adjust the pendulum to account for the fact that a load
31474 was found and increased in priority. This is to prevent
31475 increasing the priority of multiple loads */
31476 load_store_pendulum
--;
31483 else if (load_store_pendulum
== -1)
31485 /* A store has been issued in this cycle. Scan the ready list for
31486 another store to issue with it, preferring a store to an adjacent
31488 int first_store_pos
= -1;
31494 if (is_store_insn (ready
[pos
], &str_mem
))
31497 /* Maintain the index of the first store found on the
31499 if (first_store_pos
== -1)
31500 first_store_pos
= pos
;
31502 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
31503 && adjacent_mem_locations (str_mem
, str_mem2
))
31505 /* Found an adjacent store. Move it to the head of the
31506 ready list, and adjust it's priority so that it is
31507 more likely to stay there */
31509 for (i
=pos
; i
<*pn_ready
-1; i
++)
31510 ready
[i
] = ready
[i
+ 1];
31511 ready
[*pn_ready
-1] = tmp
;
31513 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31514 INSN_PRIORITY (tmp
)++;
31516 first_store_pos
= -1;
31524 if (first_store_pos
>= 0)
31526 /* An adjacent store wasn't found, but a non-adjacent store was,
31527 so move the non-adjacent store to the front of the ready
31528 list, and adjust its priority so that it is more likely to
31530 tmp
= ready
[first_store_pos
];
31531 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
31532 ready
[i
] = ready
[i
+ 1];
31533 ready
[*pn_ready
-1] = tmp
;
31534 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31535 INSN_PRIORITY (tmp
)++;
31538 else if (load_store_pendulum
== 2)
31540 /* Two loads have been issued in this cycle. Increase the priority
31541 of the first store in the ready list to favor it for issuing in
31547 if (is_store_insn (ready
[pos
], &str_mem
)
31549 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31551 INSN_PRIORITY (ready
[pos
])++;
31553 /* Adjust the pendulum to account for the fact that a store
31554 was found and increased in priority. This is to prevent
31555 increasing the priority of multiple stores */
31556 load_store_pendulum
++;
31565 /* Do Power9 dependent reordering if necessary. */
31566 if (rs6000_tune
== PROCESSOR_POWER9
&& last_scheduled_insn
31567 && recog_memoized (last_scheduled_insn
) >= 0)
31568 return power9_sched_reorder2 (ready
, *pn_ready
- 1);
31570 return cached_can_issue_more
;
31573 /* Return whether the presence of INSN causes a dispatch group termination
31574 of group WHICH_GROUP.
31576 If WHICH_GROUP == current_group, this function will return true if INSN
31577 causes the termination of the current group (i.e, the dispatch group to
31578 which INSN belongs). This means that INSN will be the last insn in the
31579 group it belongs to.
31581 If WHICH_GROUP == previous_group, this function will return true if INSN
31582 causes the termination of the previous group (i.e, the dispatch group that
31583 precedes the group to which INSN belongs). This means that INSN will be
31584 the first insn in the group it belongs to). */
31587 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
31594 first
= insn_must_be_first_in_group (insn
);
31595 last
= insn_must_be_last_in_group (insn
);
31600 if (which_group
== current_group
)
31602 else if (which_group
== previous_group
)
31610 insn_must_be_first_in_group (rtx_insn
*insn
)
31612 enum attr_type type
;
31616 || DEBUG_INSN_P (insn
)
31617 || GET_CODE (PATTERN (insn
)) == USE
31618 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31621 switch (rs6000_tune
)
31623 case PROCESSOR_POWER5
:
31624 if (is_cracked_insn (insn
))
31627 case PROCESSOR_POWER4
:
31628 if (is_microcoded_insn (insn
))
31631 if (!rs6000_sched_groups
)
31634 type
= get_attr_type (insn
);
31641 case TYPE_CR_LOGICAL
:
31654 case PROCESSOR_POWER6
:
31655 type
= get_attr_type (insn
);
31664 case TYPE_FPCOMPARE
:
31675 if (get_attr_dot (insn
) == DOT_NO
31676 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31681 if (get_attr_size (insn
) == SIZE_32
)
31689 if (get_attr_update (insn
) == UPDATE_YES
)
31697 case PROCESSOR_POWER7
:
31698 type
= get_attr_type (insn
);
31702 case TYPE_CR_LOGICAL
:
31716 if (get_attr_dot (insn
) == DOT_YES
)
31721 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31722 || get_attr_update (insn
) == UPDATE_YES
)
31729 if (get_attr_update (insn
) == UPDATE_YES
)
31737 case PROCESSOR_POWER8
:
31738 type
= get_attr_type (insn
);
31742 case TYPE_CR_LOGICAL
:
31750 case TYPE_VECSTORE
:
31757 if (get_attr_dot (insn
) == DOT_YES
)
31762 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31763 || get_attr_update (insn
) == UPDATE_YES
)
31768 if (get_attr_update (insn
) == UPDATE_YES
31769 && get_attr_indexed (insn
) == INDEXED_YES
)
31785 insn_must_be_last_in_group (rtx_insn
*insn
)
31787 enum attr_type type
;
31791 || DEBUG_INSN_P (insn
)
31792 || GET_CODE (PATTERN (insn
)) == USE
31793 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31796 switch (rs6000_tune
) {
31797 case PROCESSOR_POWER4
:
31798 case PROCESSOR_POWER5
:
31799 if (is_microcoded_insn (insn
))
31802 if (is_branch_slot_insn (insn
))
31806 case PROCESSOR_POWER6
:
31807 type
= get_attr_type (insn
);
31815 case TYPE_FPCOMPARE
:
31826 if (get_attr_dot (insn
) == DOT_NO
31827 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31832 if (get_attr_size (insn
) == SIZE_32
)
31840 case PROCESSOR_POWER7
:
31841 type
= get_attr_type (insn
);
31851 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31852 && get_attr_update (insn
) == UPDATE_YES
)
31857 if (get_attr_update (insn
) == UPDATE_YES
31858 && get_attr_indexed (insn
) == INDEXED_YES
)
31866 case PROCESSOR_POWER8
:
31867 type
= get_attr_type (insn
);
31879 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31880 && get_attr_update (insn
) == UPDATE_YES
)
31885 if (get_attr_update (insn
) == UPDATE_YES
31886 && get_attr_indexed (insn
) == INDEXED_YES
)
31901 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31902 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31905 is_costly_group (rtx
*group_insns
, rtx next_insn
)
31908 int issue_rate
= rs6000_issue_rate ();
31910 for (i
= 0; i
< issue_rate
; i
++)
31912 sd_iterator_def sd_it
;
31914 rtx insn
= group_insns
[i
];
31919 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
31921 rtx next
= DEP_CON (dep
);
31923 if (next
== next_insn
31924 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
31932 /* Utility of the function redefine_groups.
31933 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31934 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31935 to keep it "far" (in a separate group) from GROUP_INSNS, following
31936 one of the following schemes, depending on the value of the flag
31937 -minsert_sched_nops = X:
31938 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31939 in order to force NEXT_INSN into a separate group.
31940 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31941 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31942 insertion (has a group just ended, how many vacant issue slots remain in the
31943 last group, and how many dispatch groups were encountered so far). */
31946 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
31947 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
31952 int issue_rate
= rs6000_issue_rate ();
31953 bool end
= *group_end
;
31956 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
31957 return can_issue_more
;
31959 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
31960 return can_issue_more
;
31962 force
= is_costly_group (group_insns
, next_insn
);
31964 return can_issue_more
;
31966 if (sched_verbose
> 6)
31967 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
31968 *group_count
,can_issue_more
);
31970 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
31973 can_issue_more
= 0;
31975 /* Since only a branch can be issued in the last issue_slot, it is
31976 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31977 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31978 in this case the last nop will start a new group and the branch
31979 will be forced to the new group. */
31980 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
31983 /* Do we have a special group ending nop? */
31984 if (rs6000_tune
== PROCESSOR_POWER6
|| rs6000_tune
== PROCESSOR_POWER7
31985 || rs6000_tune
== PROCESSOR_POWER8
)
31987 nop
= gen_group_ending_nop ();
31988 emit_insn_before (nop
, next_insn
);
31989 can_issue_more
= 0;
31992 while (can_issue_more
> 0)
31995 emit_insn_before (nop
, next_insn
);
32003 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
32005 int n_nops
= rs6000_sched_insert_nops
;
32007 /* Nops can't be issued from the branch slot, so the effective
32008 issue_rate for nops is 'issue_rate - 1'. */
32009 if (can_issue_more
== 0)
32010 can_issue_more
= issue_rate
;
32012 if (can_issue_more
== 0)
32014 can_issue_more
= issue_rate
- 1;
32017 for (i
= 0; i
< issue_rate
; i
++)
32019 group_insns
[i
] = 0;
32026 emit_insn_before (nop
, next_insn
);
32027 if (can_issue_more
== issue_rate
- 1) /* new group begins */
32030 if (can_issue_more
== 0)
32032 can_issue_more
= issue_rate
- 1;
32035 for (i
= 0; i
< issue_rate
; i
++)
32037 group_insns
[i
] = 0;
32043 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32046 /* Is next_insn going to start a new group? */
32049 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
32050 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
32051 || (can_issue_more
< issue_rate
&&
32052 insn_terminates_group_p (next_insn
, previous_group
)));
32053 if (*group_end
&& end
)
32056 if (sched_verbose
> 6)
32057 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
32058 *group_count
, can_issue_more
);
32059 return can_issue_more
;
32062 return can_issue_more
;
32065 /* This function tries to synch the dispatch groups that the compiler "sees"
32066 with the dispatch groups that the processor dispatcher is expected to
32067 form in practice. It tries to achieve this synchronization by forcing the
32068 estimated processor grouping on the compiler (as opposed to the function
32069 'pad_goups' which tries to force the scheduler's grouping on the processor).
32071 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32072 examines the (estimated) dispatch groups that will be formed by the processor
32073 dispatcher. It marks these group boundaries to reflect the estimated
32074 processor grouping, overriding the grouping that the scheduler had marked.
32075 Depending on the value of the flag '-minsert-sched-nops' this function can
32076 force certain insns into separate groups or force a certain distance between
32077 them by inserting nops, for example, if there exists a "costly dependence"
32080 The function estimates the group boundaries that the processor will form as
32081 follows: It keeps track of how many vacant issue slots are available after
32082 each insn. A subsequent insn will start a new group if one of the following
32084 - no more vacant issue slots remain in the current dispatch group.
32085 - only the last issue slot, which is the branch slot, is vacant, but the next
32086 insn is not a branch.
32087 - only the last 2 or less issue slots, including the branch slot, are vacant,
32088 which means that a cracked insn (which occupies two issue slots) can't be
32089 issued in this group.
32090 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32091 start a new group. */
32094 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
32097 rtx_insn
*insn
, *next_insn
;
32099 int can_issue_more
;
32102 int group_count
= 0;
32106 issue_rate
= rs6000_issue_rate ();
32107 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
32108 for (i
= 0; i
< issue_rate
; i
++)
32110 group_insns
[i
] = 0;
32112 can_issue_more
= issue_rate
;
32114 insn
= get_next_active_insn (prev_head_insn
, tail
);
32117 while (insn
!= NULL_RTX
)
32119 slot
= (issue_rate
- can_issue_more
);
32120 group_insns
[slot
] = insn
;
32122 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
32123 if (insn_terminates_group_p (insn
, current_group
))
32124 can_issue_more
= 0;
32126 next_insn
= get_next_active_insn (insn
, tail
);
32127 if (next_insn
== NULL_RTX
)
32128 return group_count
+ 1;
32130 /* Is next_insn going to start a new group? */
32132 = (can_issue_more
== 0
32133 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
32134 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
32135 || (can_issue_more
< issue_rate
&&
32136 insn_terminates_group_p (next_insn
, previous_group
)));
32138 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
32139 next_insn
, &group_end
, can_issue_more
,
32145 can_issue_more
= 0;
32146 for (i
= 0; i
< issue_rate
; i
++)
32148 group_insns
[i
] = 0;
32152 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
32153 PUT_MODE (next_insn
, VOIDmode
);
32154 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
32155 PUT_MODE (next_insn
, TImode
);
32158 if (can_issue_more
== 0)
32159 can_issue_more
= issue_rate
;
32162 return group_count
;
32165 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32166 dispatch group boundaries that the scheduler had marked. Pad with nops
32167 any dispatch groups which have vacant issue slots, in order to force the
32168 scheduler's grouping on the processor dispatcher. The function
32169 returns the number of dispatch groups found. */
32172 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
32175 rtx_insn
*insn
, *next_insn
;
32178 int can_issue_more
;
32180 int group_count
= 0;
32182 /* Initialize issue_rate. */
32183 issue_rate
= rs6000_issue_rate ();
32184 can_issue_more
= issue_rate
;
32186 insn
= get_next_active_insn (prev_head_insn
, tail
);
32187 next_insn
= get_next_active_insn (insn
, tail
);
32189 while (insn
!= NULL_RTX
)
32192 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
32194 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
32196 if (next_insn
== NULL_RTX
)
32201 /* If the scheduler had marked group termination at this location
32202 (between insn and next_insn), and neither insn nor next_insn will
32203 force group termination, pad the group with nops to force group
32206 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
32207 && !insn_terminates_group_p (insn
, current_group
)
32208 && !insn_terminates_group_p (next_insn
, previous_group
))
32210 if (!is_branch_slot_insn (next_insn
))
32213 while (can_issue_more
)
32216 emit_insn_before (nop
, next_insn
);
32221 can_issue_more
= issue_rate
;
32226 next_insn
= get_next_active_insn (insn
, tail
);
32229 return group_count
;
32232 /* We're beginning a new block. Initialize data structures as necessary. */
32235 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
32236 int sched_verbose ATTRIBUTE_UNUSED
,
32237 int max_ready ATTRIBUTE_UNUSED
)
32239 last_scheduled_insn
= NULL
;
32240 load_store_pendulum
= 0;
32245 /* The following function is called at the end of scheduling BB.
32246 After reload, it inserts nops at insn group bundling. */
32249 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
32254 fprintf (dump
, "=== Finishing schedule.\n");
32256 if (reload_completed
&& rs6000_sched_groups
)
32258 /* Do not run sched_finish hook when selective scheduling enabled. */
32259 if (sel_sched_p ())
32262 if (rs6000_sched_insert_nops
== sched_finish_none
)
32265 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
32266 n_groups
= pad_groups (dump
, sched_verbose
,
32267 current_sched_info
->prev_head
,
32268 current_sched_info
->next_tail
);
32270 n_groups
= redefine_groups (dump
, sched_verbose
,
32271 current_sched_info
->prev_head
,
32272 current_sched_info
->next_tail
);
32274 if (sched_verbose
>= 6)
32276 fprintf (dump
, "ngroups = %d\n", n_groups
);
32277 print_rtl (dump
, current_sched_info
->prev_head
);
32278 fprintf (dump
, "Done finish_sched\n");
32283 struct rs6000_sched_context
32285 short cached_can_issue_more
;
32286 rtx_insn
*last_scheduled_insn
;
32287 int load_store_pendulum
;
32292 typedef struct rs6000_sched_context rs6000_sched_context_def
;
32293 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
32295 /* Allocate store for new scheduling context. */
32297 rs6000_alloc_sched_context (void)
32299 return xmalloc (sizeof (rs6000_sched_context_def
));
32302 /* If CLEAN_P is true then initializes _SC with clean data,
32303 and from the global context otherwise. */
32305 rs6000_init_sched_context (void *_sc
, bool clean_p
)
32307 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32311 sc
->cached_can_issue_more
= 0;
32312 sc
->last_scheduled_insn
= NULL
;
32313 sc
->load_store_pendulum
= 0;
32314 sc
->divide_cnt
= 0;
32315 sc
->vec_pairing
= 0;
32319 sc
->cached_can_issue_more
= cached_can_issue_more
;
32320 sc
->last_scheduled_insn
= last_scheduled_insn
;
32321 sc
->load_store_pendulum
= load_store_pendulum
;
32322 sc
->divide_cnt
= divide_cnt
;
32323 sc
->vec_pairing
= vec_pairing
;
32327 /* Sets the global scheduling context to the one pointed to by _SC. */
32329 rs6000_set_sched_context (void *_sc
)
32331 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32333 gcc_assert (sc
!= NULL
);
32335 cached_can_issue_more
= sc
->cached_can_issue_more
;
32336 last_scheduled_insn
= sc
->last_scheduled_insn
;
32337 load_store_pendulum
= sc
->load_store_pendulum
;
32338 divide_cnt
= sc
->divide_cnt
;
32339 vec_pairing
= sc
->vec_pairing
;
32344 rs6000_free_sched_context (void *_sc
)
32346 gcc_assert (_sc
!= NULL
);
32352 rs6000_sched_can_speculate_insn (rtx_insn
*insn
)
32354 switch (get_attr_type (insn
))
32369 /* Length in units of the trampoline for entering a nested function. */
32372 rs6000_trampoline_size (void)
32376 switch (DEFAULT_ABI
)
32379 gcc_unreachable ();
32382 ret
= (TARGET_32BIT
) ? 12 : 24;
32386 gcc_assert (!TARGET_32BIT
);
32392 ret
= (TARGET_32BIT
) ? 40 : 48;
32399 /* Emit RTL insns to initialize the variable parts of a trampoline.
32400 FNADDR is an RTX for the address of the function's pure code.
32401 CXT is an RTX for the static chain value for the function. */
32404 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
32406 int regsize
= (TARGET_32BIT
) ? 4 : 8;
32407 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
32408 rtx ctx_reg
= force_reg (Pmode
, cxt
);
32409 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
32411 switch (DEFAULT_ABI
)
32414 gcc_unreachable ();
32416 /* Under AIX, just build the 3 word function descriptor */
32419 rtx fnmem
, fn_reg
, toc_reg
;
32421 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32422 error ("you cannot take the address of a nested function if you use "
32423 "the %qs option", "-mno-pointers-to-nested-functions");
32425 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
32426 fn_reg
= gen_reg_rtx (Pmode
);
32427 toc_reg
= gen_reg_rtx (Pmode
);
32429 /* Macro to shorten the code expansions below. */
32430 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32432 m_tramp
= replace_equiv_address (m_tramp
, addr
);
32434 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
32435 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
32436 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
32437 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
32438 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
32444 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32448 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
32449 LCT_NORMAL
, VOIDmode
,
32451 GEN_INT (rs6000_trampoline_size ()), SImode
,
32459 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32460 identifier as an argument, so the front end shouldn't look it up. */
32463 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
32465 return is_attribute_p ("altivec", attr_id
);
32468 /* Handle the "altivec" attribute. The attribute may have
32469 arguments as follows:
32471 __attribute__((altivec(vector__)))
32472 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32473 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32475 and may appear more than once (e.g., 'vector bool char') in a
32476 given declaration. */
32479 rs6000_handle_altivec_attribute (tree
*node
,
32480 tree name ATTRIBUTE_UNUSED
,
32482 int flags ATTRIBUTE_UNUSED
,
32483 bool *no_add_attrs
)
32485 tree type
= *node
, result
= NULL_TREE
;
32489 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
32490 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
32491 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
32494 while (POINTER_TYPE_P (type
)
32495 || TREE_CODE (type
) == FUNCTION_TYPE
32496 || TREE_CODE (type
) == METHOD_TYPE
32497 || TREE_CODE (type
) == ARRAY_TYPE
)
32498 type
= TREE_TYPE (type
);
32500 mode
= TYPE_MODE (type
);
32502 /* Check for invalid AltiVec type qualifiers. */
32503 if (type
== long_double_type_node
)
32504 error ("use of %<long double%> in AltiVec types is invalid");
32505 else if (type
== boolean_type_node
)
32506 error ("use of boolean types in AltiVec types is invalid");
32507 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
32508 error ("use of %<complex%> in AltiVec types is invalid");
32509 else if (DECIMAL_FLOAT_MODE_P (mode
))
32510 error ("use of decimal floating point types in AltiVec types is invalid");
32511 else if (!TARGET_VSX
)
32513 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
32516 error ("use of %<long%> in AltiVec types is invalid for "
32517 "64-bit code without %qs", "-mvsx");
32518 else if (rs6000_warn_altivec_long
)
32519 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32522 else if (type
== long_long_unsigned_type_node
32523 || type
== long_long_integer_type_node
)
32524 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32526 else if (type
== double_type_node
)
32527 error ("use of %<double%> in AltiVec types is invalid without %qs",
32531 switch (altivec_type
)
32534 unsigned_p
= TYPE_UNSIGNED (type
);
32538 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
32541 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
32544 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
32547 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
32550 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
32552 case E_SFmode
: result
= V4SF_type_node
; break;
32553 case E_DFmode
: result
= V2DF_type_node
; break;
32554 /* If the user says 'vector int bool', we may be handed the 'bool'
32555 attribute _before_ the 'vector' attribute, and so select the
32556 proper type in the 'b' case below. */
32557 case E_V4SImode
: case E_V8HImode
: case E_V16QImode
: case E_V4SFmode
:
32558 case E_V2DImode
: case E_V2DFmode
:
32566 case E_DImode
: case E_V2DImode
: result
= bool_V2DI_type_node
; break;
32567 case E_SImode
: case E_V4SImode
: result
= bool_V4SI_type_node
; break;
32568 case E_HImode
: case E_V8HImode
: result
= bool_V8HI_type_node
; break;
32569 case E_QImode
: case E_V16QImode
: result
= bool_V16QI_type_node
;
32576 case E_V8HImode
: result
= pixel_V8HI_type_node
;
32582 /* Propagate qualifiers attached to the element type
32583 onto the vector type. */
32584 if (result
&& result
!= type
&& TYPE_QUALS (type
))
32585 result
= build_qualified_type (result
, TYPE_QUALS (type
));
32587 *no_add_attrs
= true; /* No need to hang on to the attribute. */
32590 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
32595 /* AltiVec defines five built-in scalar types that serve as vector
32596 elements; we must teach the compiler how to mangle them. The 128-bit
32597 floating point mangling is target-specific as well. */
32599 static const char *
32600 rs6000_mangle_type (const_tree type
)
32602 type
= TYPE_MAIN_VARIANT (type
);
32604 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
32605 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
32608 if (type
== bool_char_type_node
) return "U6__boolc";
32609 if (type
== bool_short_type_node
) return "U6__bools";
32610 if (type
== pixel_type_node
) return "u7__pixel";
32611 if (type
== bool_int_type_node
) return "U6__booli";
32612 if (type
== bool_long_long_type_node
) return "U6__boolx";
32614 if (SCALAR_FLOAT_TYPE_P (type
) && FLOAT128_IBM_P (TYPE_MODE (type
)))
32616 if (SCALAR_FLOAT_TYPE_P (type
) && FLOAT128_IEEE_P (TYPE_MODE (type
)))
32617 return ieee128_mangling_gcc_8_1
? "U10__float128" : "u9__ieee128";
32619 /* For all other types, use the default mangling. */
32623 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32624 struct attribute_spec.handler. */
32627 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
32628 tree args ATTRIBUTE_UNUSED
,
32629 int flags ATTRIBUTE_UNUSED
,
32630 bool *no_add_attrs
)
32632 if (TREE_CODE (*node
) != FUNCTION_TYPE
32633 && TREE_CODE (*node
) != FIELD_DECL
32634 && TREE_CODE (*node
) != TYPE_DECL
)
32636 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
32638 *no_add_attrs
= true;
32644 /* Set longcall attributes on all functions declared when
32645 rs6000_default_long_calls is true. */
32647 rs6000_set_default_type_attributes (tree type
)
32649 if (rs6000_default_long_calls
32650 && (TREE_CODE (type
) == FUNCTION_TYPE
32651 || TREE_CODE (type
) == METHOD_TYPE
))
32652 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
32654 TYPE_ATTRIBUTES (type
));
32657 darwin_set_default_type_attributes (type
);
32661 /* Return a reference suitable for calling a function with the
32662 longcall attribute. */
32665 rs6000_longcall_ref (rtx call_ref
, rtx arg
)
32667 /* System V adds '.' to the internal name, so skip them. */
32668 const char *call_name
= XSTR (call_ref
, 0);
32669 if (*call_name
== '.')
32671 while (*call_name
== '.')
32674 tree node
= get_identifier (call_name
);
32675 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
32679 && TARGET_TLS_MARKERS
32680 && (DEFAULT_ABI
== ABI_ELFv2
|| DEFAULT_ABI
== ABI_V4
))
32682 rtx base
= const0_rtx
;
32684 if (DEFAULT_ABI
== ABI_ELFv2
)
32686 base
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
32692 base
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
32695 /* Reg must match that used by linker PLT stubs. For ELFv2, r12
32696 may be used by a function global entry point. For SysV4, r11
32697 is used by __glink_PLTresolve lazy resolver entry. */
32698 rtx reg
= gen_rtx_REG (Pmode
, regno
);
32699 rtx hi
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (3, base
, call_ref
, arg
),
32701 rtx lo
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (3, reg
, call_ref
, arg
),
32703 emit_insn (gen_rtx_SET (reg
, hi
));
32704 emit_insn (gen_rtx_SET (reg
, lo
));
32708 return force_reg (Pmode
, call_ref
);
32711 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32712 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32715 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32716 struct attribute_spec.handler. */
32718 rs6000_handle_struct_attribute (tree
*node
, tree name
,
32719 tree args ATTRIBUTE_UNUSED
,
32720 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
32723 if (DECL_P (*node
))
32725 if (TREE_CODE (*node
) == TYPE_DECL
)
32726 type
= &TREE_TYPE (*node
);
32731 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
32732 || TREE_CODE (*type
) == UNION_TYPE
)))
32734 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
32735 *no_add_attrs
= true;
32738 else if ((is_attribute_p ("ms_struct", name
)
32739 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
32740 || ((is_attribute_p ("gcc_struct", name
)
32741 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
32743 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
32745 *no_add_attrs
= true;
32752 rs6000_ms_bitfield_layout_p (const_tree record_type
)
32754 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
32755 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
32756 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
32759 #ifdef USING_ELFOS_H
32761 /* A get_unnamed_section callback, used for switching to toc_section. */
32764 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
32766 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
32767 && TARGET_MINIMAL_TOC
)
32769 if (!toc_initialized
)
32771 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
32772 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32773 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
32774 fprintf (asm_out_file
, "\t.tc ");
32775 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
32776 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32777 fprintf (asm_out_file
, "\n");
32779 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32780 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32781 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32782 fprintf (asm_out_file
, " = .+32768\n");
32783 toc_initialized
= 1;
32786 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32788 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
32790 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
32791 if (!toc_initialized
)
32793 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32794 toc_initialized
= 1;
32799 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32800 if (!toc_initialized
)
32802 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32803 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32804 fprintf (asm_out_file
, " = .+32768\n");
32805 toc_initialized
= 1;
32810 /* Implement TARGET_ASM_INIT_SECTIONS. */
32813 rs6000_elf_asm_init_sections (void)
32816 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
32819 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
32820 SDATA2_SECTION_ASM_OP
);
32823 /* Implement TARGET_SELECT_RTX_SECTION. */
32826 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
32827 unsigned HOST_WIDE_INT align
)
32829 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
32830 return toc_section
;
32832 return default_elf_select_rtx_section (mode
, x
, align
);
32835 /* For a SYMBOL_REF, set generic flags and then perform some
32836 target-specific processing.
32838 When the AIX ABI is requested on a non-AIX system, replace the
32839 function name with the real name (with a leading .) rather than the
32840 function descriptor name. This saves a lot of overriding code to
32841 read the prefixes. */
32843 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
32845 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
32847 default_encode_section_info (decl
, rtl
, first
);
32850 && TREE_CODE (decl
) == FUNCTION_DECL
32852 && DEFAULT_ABI
== ABI_AIX
)
32854 rtx sym_ref
= XEXP (rtl
, 0);
32855 size_t len
= strlen (XSTR (sym_ref
, 0));
32856 char *str
= XALLOCAVEC (char, len
+ 2);
32858 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
32859 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
32864 compare_section_name (const char *section
, const char *templ
)
32868 len
= strlen (templ
);
32869 return (strncmp (section
, templ
, len
) == 0
32870 && (section
[len
] == 0 || section
[len
] == '.'));
32874 rs6000_elf_in_small_data_p (const_tree decl
)
32876 if (rs6000_sdata
== SDATA_NONE
)
32879 /* We want to merge strings, so we never consider them small data. */
32880 if (TREE_CODE (decl
) == STRING_CST
)
32883 /* Functions are never in the small data area. */
32884 if (TREE_CODE (decl
) == FUNCTION_DECL
)
32887 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
32889 const char *section
= DECL_SECTION_NAME (decl
);
32890 if (compare_section_name (section
, ".sdata")
32891 || compare_section_name (section
, ".sdata2")
32892 || compare_section_name (section
, ".gnu.linkonce.s")
32893 || compare_section_name (section
, ".sbss")
32894 || compare_section_name (section
, ".sbss2")
32895 || compare_section_name (section
, ".gnu.linkonce.sb")
32896 || strcmp (section
, ".PPC.EMB.sdata0") == 0
32897 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
32902 /* If we are told not to put readonly data in sdata, then don't. */
32903 if (TREE_READONLY (decl
) && rs6000_sdata
!= SDATA_EABI
32904 && !rs6000_readonly_in_sdata
)
32907 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
32910 && size
<= g_switch_value
32911 /* If it's not public, and we're not going to reference it there,
32912 there's no need to put it in the small data section. */
32913 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
32920 #endif /* USING_ELFOS_H */
32922 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32925 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
32927 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
32930 /* Do not place thread-local symbols refs in the object blocks. */
32933 rs6000_use_blocks_for_decl_p (const_tree decl
)
32935 return !DECL_THREAD_LOCAL_P (decl
);
32938 /* Return a REG that occurs in ADDR with coefficient 1.
32939 ADDR can be effectively incremented by incrementing REG.
32941 r0 is special and we must not select it as an address
32942 register by this routine since our caller will try to
32943 increment the returned register via an "la" instruction. */
32946 find_addr_reg (rtx addr
)
32948 while (GET_CODE (addr
) == PLUS
)
32950 if (GET_CODE (XEXP (addr
, 0)) == REG
32951 && REGNO (XEXP (addr
, 0)) != 0)
32952 addr
= XEXP (addr
, 0);
32953 else if (GET_CODE (XEXP (addr
, 1)) == REG
32954 && REGNO (XEXP (addr
, 1)) != 0)
32955 addr
= XEXP (addr
, 1);
32956 else if (CONSTANT_P (XEXP (addr
, 0)))
32957 addr
= XEXP (addr
, 1);
32958 else if (CONSTANT_P (XEXP (addr
, 1)))
32959 addr
= XEXP (addr
, 0);
32961 gcc_unreachable ();
32963 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
32968 rs6000_fatal_bad_address (rtx op
)
32970 fatal_insn ("bad address", op
);
32975 typedef struct branch_island_d
{
32976 tree function_name
;
32982 static vec
<branch_island
, va_gc
> *branch_islands
;
32984 /* Remember to generate a branch island for far calls to the given
32988 add_compiler_branch_island (tree label_name
, tree function_name
,
32991 branch_island bi
= {function_name
, label_name
, line_number
};
32992 vec_safe_push (branch_islands
, bi
);
32995 /* Generate far-jump branch islands for everything recorded in
32996 branch_islands. Invoked immediately after the last instruction of
32997 the epilogue has been emitted; the branch islands must be appended
32998 to, and contiguous with, the function body. Mach-O stubs are
32999 generated in machopic_output_stub(). */
33002 macho_branch_islands (void)
33006 while (!vec_safe_is_empty (branch_islands
))
33008 branch_island
*bi
= &branch_islands
->last ();
33009 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
33010 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
33011 char name_buf
[512];
33012 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33013 if (name
[0] == '*' || name
[0] == '&')
33014 strcpy (name_buf
, name
+1);
33018 strcpy (name_buf
+1, name
);
33020 strcpy (tmp_buf
, "\n");
33021 strcat (tmp_buf
, label
);
33022 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33023 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
33024 dbxout_stabd (N_SLINE
, bi
->line_number
);
33025 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33028 if (TARGET_LINK_STACK
)
33031 get_ppc476_thunk_name (name
);
33032 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
33033 strcat (tmp_buf
, name
);
33034 strcat (tmp_buf
, "\n");
33035 strcat (tmp_buf
, label
);
33036 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
33040 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
33041 strcat (tmp_buf
, label
);
33042 strcat (tmp_buf
, "_pic\n");
33043 strcat (tmp_buf
, label
);
33044 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
33047 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
33048 strcat (tmp_buf
, name_buf
);
33049 strcat (tmp_buf
, " - ");
33050 strcat (tmp_buf
, label
);
33051 strcat (tmp_buf
, "_pic)\n");
33053 strcat (tmp_buf
, "\tmtlr r0\n");
33055 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
33056 strcat (tmp_buf
, name_buf
);
33057 strcat (tmp_buf
, " - ");
33058 strcat (tmp_buf
, label
);
33059 strcat (tmp_buf
, "_pic)\n");
33061 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
33065 strcat (tmp_buf
, ":\nlis r12,hi16(");
33066 strcat (tmp_buf
, name_buf
);
33067 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
33068 strcat (tmp_buf
, name_buf
);
33069 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
33071 output_asm_insn (tmp_buf
, 0);
33072 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33073 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
33074 dbxout_stabd (N_SLINE
, bi
->line_number
);
33075 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33076 branch_islands
->pop ();
33080 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33081 already there or not. */
33084 no_previous_def (tree function_name
)
33089 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
33090 if (function_name
== bi
->function_name
)
33095 /* GET_PREV_LABEL gets the label name from the previous definition of
33099 get_prev_label (tree function_name
)
33104 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
33105 if (function_name
== bi
->function_name
)
33106 return bi
->label_name
;
33110 /* INSN is either a function call or a millicode call. It may have an
33111 unconditional jump in its delay slot.
33113 CALL_DEST is the routine we are calling. */
33116 macho_call_template (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
33117 int cookie_operand_number
)
33119 static char buf
[256];
33120 if (darwin_emit_branch_islands
33121 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
33122 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
33125 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
33127 if (no_previous_def (funname
))
33129 rtx label_rtx
= gen_label_rtx ();
33130 char *label_buf
, temp_buf
[256];
33131 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
33132 CODE_LABEL_NUMBER (label_rtx
));
33133 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
33134 labelname
= get_identifier (label_buf
);
33135 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
33138 labelname
= get_prev_label (funname
);
33140 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
33141 instruction will reach 'foo', otherwise link as 'bl L42'".
33142 "L42" should be a 'branch island', that will do a far jump to
33143 'foo'. Branch islands are generated in
33144 macho_branch_islands(). */
33145 sprintf (buf
, "jbsr %%z%d,%.246s",
33146 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
33149 sprintf (buf
, "bl %%z%d", dest_operand_number
);
33153 /* Generate PIC and indirect symbol stubs. */
33156 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
33158 unsigned int length
;
33159 char *symbol_name
, *lazy_ptr_name
;
33160 char *local_label_0
;
33161 static int label
= 0;
33163 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33164 symb
= (*targetm
.strip_name_encoding
) (symb
);
33167 length
= strlen (symb
);
33168 symbol_name
= XALLOCAVEC (char, length
+ 32);
33169 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
33171 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
33172 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
33175 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
33177 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
33181 fprintf (file
, "\t.align 5\n");
33183 fprintf (file
, "%s:\n", stub
);
33184 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33187 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33188 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
33190 fprintf (file
, "\tmflr r0\n");
33191 if (TARGET_LINK_STACK
)
33194 get_ppc476_thunk_name (name
);
33195 fprintf (file
, "\tbl %s\n", name
);
33196 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
33200 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
33201 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
33203 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
33204 lazy_ptr_name
, local_label_0
);
33205 fprintf (file
, "\tmtlr r0\n");
33206 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
33207 (TARGET_64BIT
? "ldu" : "lwzu"),
33208 lazy_ptr_name
, local_label_0
);
33209 fprintf (file
, "\tmtctr r12\n");
33210 fprintf (file
, "\tbctr\n");
33214 fprintf (file
, "\t.align 4\n");
33216 fprintf (file
, "%s:\n", stub
);
33217 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33219 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
33220 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
33221 (TARGET_64BIT
? "ldu" : "lwzu"),
33223 fprintf (file
, "\tmtctr r12\n");
33224 fprintf (file
, "\tbctr\n");
33227 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
33228 fprintf (file
, "%s:\n", lazy_ptr_name
);
33229 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33230 fprintf (file
, "%sdyld_stub_binding_helper\n",
33231 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
33234 /* Legitimize PIC addresses. If the address is already
33235 position-independent, we return ORIG. Newly generated
33236 position-independent addresses go into a reg. This is REG if non
33237 zero, otherwise we allocate register(s) as necessary. */
33239 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33242 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
33247 if (reg
== NULL
&& !reload_completed
)
33248 reg
= gen_reg_rtx (Pmode
);
33250 if (GET_CODE (orig
) == CONST
)
33254 if (GET_CODE (XEXP (orig
, 0)) == PLUS
33255 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
33258 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
33260 /* Use a different reg for the intermediate value, as
33261 it will be marked UNCHANGING. */
33262 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
33263 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
33266 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
33269 if (GET_CODE (offset
) == CONST_INT
)
33271 if (SMALL_INT (offset
))
33272 return plus_constant (Pmode
, base
, INTVAL (offset
));
33273 else if (!reload_completed
)
33274 offset
= force_reg (Pmode
, offset
);
33277 rtx mem
= force_const_mem (Pmode
, orig
);
33278 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
33281 return gen_rtx_PLUS (Pmode
, base
, offset
);
33284 /* Fall back on generic machopic code. */
33285 return machopic_legitimize_pic_address (orig
, mode
, reg
);
33288 /* Output a .machine directive for the Darwin assembler, and call
33289 the generic start_file routine. */
33292 rs6000_darwin_file_start (void)
33294 static const struct
33298 HOST_WIDE_INT if_set
;
33300 { "ppc64", "ppc64", MASK_64BIT
},
33301 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
33302 { "power4", "ppc970", 0 },
33303 { "G5", "ppc970", 0 },
33304 { "7450", "ppc7450", 0 },
33305 { "7400", "ppc7400", MASK_ALTIVEC
},
33306 { "G4", "ppc7400", 0 },
33307 { "750", "ppc750", 0 },
33308 { "740", "ppc750", 0 },
33309 { "G3", "ppc750", 0 },
33310 { "604e", "ppc604e", 0 },
33311 { "604", "ppc604", 0 },
33312 { "603e", "ppc603", 0 },
33313 { "603", "ppc603", 0 },
33314 { "601", "ppc601", 0 },
33315 { NULL
, "ppc", 0 } };
33316 const char *cpu_id
= "";
33319 rs6000_file_start ();
33320 darwin_file_start ();
33322 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33324 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
33325 cpu_id
= rs6000_default_cpu
;
33327 if (global_options_set
.x_rs6000_cpu_index
)
33328 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
33330 /* Look through the mapping array. Pick the first name that either
33331 matches the argument, has a bit set in IF_SET that is also set
33332 in the target flags, or has a NULL name. */
33335 while (mapping
[i
].arg
!= NULL
33336 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
33337 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
33340 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
33343 #endif /* TARGET_MACHO */
33347 rs6000_elf_reloc_rw_mask (void)
33351 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
33357 /* Record an element in the table of global constructors. SYMBOL is
33358 a SYMBOL_REF of the function to be called; PRIORITY is a number
33359 between 0 and MAX_INIT_PRIORITY.
33361 This differs from default_named_section_asm_out_constructor in
33362 that we have special handling for -mrelocatable. */
33364 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
33366 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
33368 const char *section
= ".ctors";
33371 if (priority
!= DEFAULT_INIT_PRIORITY
)
33373 sprintf (buf
, ".ctors.%.5u",
33374 /* Invert the numbering so the linker puts us in the proper
33375 order; constructors are run from right to left, and the
33376 linker sorts in increasing order. */
33377 MAX_INIT_PRIORITY
- priority
);
33381 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33382 assemble_align (POINTER_SIZE
);
33384 if (DEFAULT_ABI
== ABI_V4
33385 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33387 fputs ("\t.long (", asm_out_file
);
33388 output_addr_const (asm_out_file
, symbol
);
33389 fputs (")@fixup\n", asm_out_file
);
33392 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33395 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
33397 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
33399 const char *section
= ".dtors";
33402 if (priority
!= DEFAULT_INIT_PRIORITY
)
33404 sprintf (buf
, ".dtors.%.5u",
33405 /* Invert the numbering so the linker puts us in the proper
33406 order; constructors are run from right to left, and the
33407 linker sorts in increasing order. */
33408 MAX_INIT_PRIORITY
- priority
);
33412 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33413 assemble_align (POINTER_SIZE
);
33415 if (DEFAULT_ABI
== ABI_V4
33416 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33418 fputs ("\t.long (", asm_out_file
);
33419 output_addr_const (asm_out_file
, symbol
);
33420 fputs (")@fixup\n", asm_out_file
);
33423 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33427 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
33429 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
33431 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
33432 ASM_OUTPUT_LABEL (file
, name
);
33433 fputs (DOUBLE_INT_ASM_OP
, file
);
33434 rs6000_output_function_entry (file
, name
);
33435 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
33438 fputs ("\t.size\t", file
);
33439 assemble_name (file
, name
);
33440 fputs (",24\n\t.type\t.", file
);
33441 assemble_name (file
, name
);
33442 fputs (",@function\n", file
);
33443 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
33445 fputs ("\t.globl\t.", file
);
33446 assemble_name (file
, name
);
33451 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33452 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33453 rs6000_output_function_entry (file
, name
);
33454 fputs (":\n", file
);
33459 if (DEFAULT_ABI
== ABI_V4
33460 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
33461 && !TARGET_SECURE_PLT
33462 && (!constant_pool_empty_p () || crtl
->profile
)
33463 && (uses_toc
= uses_TOC ()))
33468 switch_to_other_text_partition ();
33469 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33471 fprintf (file
, "\t.long ");
33472 assemble_name (file
, toc_label_name
);
33475 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33476 assemble_name (file
, buf
);
33479 switch_to_other_text_partition ();
33482 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33483 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33485 if (TARGET_CMODEL
== CMODEL_LARGE
&& rs6000_global_entry_point_needed_p ())
33489 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33491 fprintf (file
, "\t.quad .TOC.-");
33492 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33493 assemble_name (file
, buf
);
33497 if (DEFAULT_ABI
== ABI_AIX
)
33499 const char *desc_name
, *orig_name
;
33501 orig_name
= (*targetm
.strip_name_encoding
) (name
);
33502 desc_name
= orig_name
;
33503 while (*desc_name
== '.')
33506 if (TREE_PUBLIC (decl
))
33507 fprintf (file
, "\t.globl %s\n", desc_name
);
33509 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
33510 fprintf (file
, "%s:\n", desc_name
);
33511 fprintf (file
, "\t.long %s\n", orig_name
);
33512 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
33513 fputs ("\t.long 0\n", file
);
33514 fprintf (file
, "\t.previous\n");
33516 ASM_OUTPUT_LABEL (file
, name
);
33519 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
33521 rs6000_elf_file_end (void)
33523 #ifdef HAVE_AS_GNU_ATTRIBUTE
33524 /* ??? The value emitted depends on options active at file end.
33525 Assume anyone using #pragma or attributes that might change
33526 options knows what they are doing. */
33527 if ((TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
33528 && rs6000_passes_float
)
33532 if (TARGET_HARD_FLOAT
)
33536 if (rs6000_passes_long_double
)
33538 if (!TARGET_LONG_DOUBLE_128
)
33540 else if (TARGET_IEEEQUAD
)
33545 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", fp
);
33547 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
33549 if (rs6000_passes_vector
)
33550 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
33551 (TARGET_ALTIVEC_ABI
? 2 : 1));
33552 if (rs6000_returns_struct
)
33553 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
33554 aix_struct_return
? 2 : 1);
33557 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33558 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
33559 file_end_indicate_exec_stack ();
33562 if (flag_split_stack
)
33563 file_end_indicate_split_stack ();
33567 /* We have expanded a CPU builtin, so we need to emit a reference to
33568 the special symbol that LIBC uses to declare it supports the
33569 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33570 switch_to_section (data_section
);
33571 fprintf (asm_out_file
, "\t.align %u\n", TARGET_32BIT
? 2 : 3);
33572 fprintf (asm_out_file
, "\t%s %s\n",
33573 TARGET_32BIT
? ".long" : ".quad", tcb_verification_symbol
);
33580 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33581 #define HAVE_XCOFF_DWARF_EXTRAS 0
33584 static enum unwind_info_type
33585 rs6000_xcoff_debug_unwind_info (void)
33591 rs6000_xcoff_asm_output_anchor (rtx symbol
)
33595 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
33596 SYMBOL_REF_BLOCK_OFFSET (symbol
));
33597 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
33598 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
33599 fprintf (asm_out_file
, ",");
33600 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
33601 fprintf (asm_out_file
, "\n");
33605 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
33607 fputs (GLOBAL_ASM_OP
, stream
);
33608 RS6000_OUTPUT_BASENAME (stream
, name
);
33609 putc ('\n', stream
);
33612 /* A get_unnamed_decl callback, used for read-only sections. PTR
33613 points to the section string variable. */
33616 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
33618 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
33619 *(const char *const *) directive
,
33620 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33623 /* Likewise for read-write sections. */
33626 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
33628 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
33629 *(const char *const *) directive
,
33630 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33634 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
33636 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
33637 *(const char *const *) directive
,
33638 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33641 /* A get_unnamed_section callback, used for switching to toc_section. */
33644 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
33646 if (TARGET_MINIMAL_TOC
)
33648 /* toc_section is always selected at least once from
33649 rs6000_xcoff_file_start, so this is guaranteed to
33650 always be defined once and only once in each file. */
33651 if (!toc_initialized
)
33653 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
33654 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
33655 toc_initialized
= 1;
33657 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
33658 (TARGET_32BIT
? "" : ",3"));
33661 fputs ("\t.toc\n", asm_out_file
);
33664 /* Implement TARGET_ASM_INIT_SECTIONS. */
33667 rs6000_xcoff_asm_init_sections (void)
33669 read_only_data_section
33670 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33671 &xcoff_read_only_section_name
);
33673 private_data_section
33674 = get_unnamed_section (SECTION_WRITE
,
33675 rs6000_xcoff_output_readwrite_section_asm_op
,
33676 &xcoff_private_data_section_name
);
33679 = get_unnamed_section (SECTION_TLS
,
33680 rs6000_xcoff_output_tls_section_asm_op
,
33681 &xcoff_tls_data_section_name
);
33683 tls_private_data_section
33684 = get_unnamed_section (SECTION_TLS
,
33685 rs6000_xcoff_output_tls_section_asm_op
,
33686 &xcoff_private_data_section_name
);
33688 read_only_private_data_section
33689 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33690 &xcoff_private_data_section_name
);
33693 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
33695 readonly_data_section
= read_only_data_section
;
33699 rs6000_xcoff_reloc_rw_mask (void)
33705 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
33706 tree decl ATTRIBUTE_UNUSED
)
33709 static const char * const suffix
[5] = { "PR", "RO", "RW", "TL", "XO" };
33711 if (flags
& SECTION_EXCLUDE
)
33713 else if (flags
& SECTION_DEBUG
)
33715 fprintf (asm_out_file
, "\t.dwsect %s\n", name
);
33718 else if (flags
& SECTION_CODE
)
33720 else if (flags
& SECTION_TLS
)
33722 else if (flags
& SECTION_WRITE
)
33727 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
33728 (flags
& SECTION_CODE
) ? "." : "",
33729 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
33732 #define IN_NAMED_SECTION(DECL) \
33733 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33734 && DECL_SECTION_NAME (DECL) != NULL)
33737 rs6000_xcoff_select_section (tree decl
, int reloc
,
33738 unsigned HOST_WIDE_INT align
)
33740 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33742 if (align
> BIGGEST_ALIGNMENT
)
33744 resolve_unique_section (decl
, reloc
, true);
33745 if (IN_NAMED_SECTION (decl
))
33746 return get_named_section (decl
, NULL
, reloc
);
33749 if (decl_readonly_section (decl
, reloc
))
33751 if (TREE_PUBLIC (decl
))
33752 return read_only_data_section
;
33754 return read_only_private_data_section
;
33759 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
33761 if (TREE_PUBLIC (decl
))
33762 return tls_data_section
;
33763 else if (bss_initializer_p (decl
))
33765 /* Convert to COMMON to emit in BSS. */
33766 DECL_COMMON (decl
) = 1;
33767 return tls_comm_section
;
33770 return tls_private_data_section
;
33774 if (TREE_PUBLIC (decl
))
33775 return data_section
;
33777 return private_data_section
;
33782 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
33786 /* Use select_section for private data and uninitialized data with
33787 alignment <= BIGGEST_ALIGNMENT. */
33788 if (!TREE_PUBLIC (decl
)
33789 || DECL_COMMON (decl
)
33790 || (DECL_INITIAL (decl
) == NULL_TREE
33791 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
33792 || DECL_INITIAL (decl
) == error_mark_node
33793 || (flag_zero_initialized_in_bss
33794 && initializer_zerop (DECL_INITIAL (decl
))))
33797 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
33798 name
= (*targetm
.strip_name_encoding
) (name
);
33799 set_decl_section_name (decl
, name
);
33802 /* Select section for constant in constant pool.
33804 On RS/6000, all constants are in the private read-only data area.
33805 However, if this is being placed in the TOC it must be output as a
33809 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
33810 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
33812 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
33813 return toc_section
;
33815 return read_only_private_data_section
;
33818 /* Remove any trailing [DS] or the like from the symbol name. */
33820 static const char *
33821 rs6000_xcoff_strip_name_encoding (const char *name
)
33826 len
= strlen (name
);
33827 if (name
[len
- 1] == ']')
33828 return ggc_alloc_string (name
, len
- 4);
33833 /* Section attributes. AIX is always PIC. */
33835 static unsigned int
33836 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
33838 unsigned int align
;
33839 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
33841 /* Align to at least UNIT size. */
33842 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
33843 align
= MIN_UNITS_PER_WORD
;
33845 /* Increase alignment of large objects if not already stricter. */
33846 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
33847 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
33848 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
33850 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
33853 /* Output at beginning of assembler file.
33855 Initialize the section names for the RS/6000 at this point.
33857 Specify filename, including full path, to assembler.
33859 We want to go into the TOC section so at least one .toc will be emitted.
33860 Also, in order to output proper .bs/.es pairs, we need at least one static
33861 [RW] section emitted.
33863 Finally, declare mcount when profiling to make the assembler happy. */
33866 rs6000_xcoff_file_start (void)
33868 rs6000_gen_section_name (&xcoff_bss_section_name
,
33869 main_input_filename
, ".bss_");
33870 rs6000_gen_section_name (&xcoff_private_data_section_name
,
33871 main_input_filename
, ".rw_");
33872 rs6000_gen_section_name (&xcoff_read_only_section_name
,
33873 main_input_filename
, ".ro_");
33874 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
33875 main_input_filename
, ".tls_");
33876 rs6000_gen_section_name (&xcoff_tbss_section_name
,
33877 main_input_filename
, ".tbss_[UL]");
33879 fputs ("\t.file\t", asm_out_file
);
33880 output_quoted_string (asm_out_file
, main_input_filename
);
33881 fputc ('\n', asm_out_file
);
33882 if (write_symbols
!= NO_DEBUG
)
33883 switch_to_section (private_data_section
);
33884 switch_to_section (toc_section
);
33885 switch_to_section (text_section
);
33887 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
33888 rs6000_file_start ();
33891 /* Output at end of assembler file.
33892 On the RS/6000, referencing data should automatically pull in text. */
33895 rs6000_xcoff_file_end (void)
33897 switch_to_section (text_section
);
33898 fputs ("_section_.text:\n", asm_out_file
);
33899 switch_to_section (data_section
);
33900 fputs (TARGET_32BIT
33901 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33905 struct declare_alias_data
33908 bool function_descriptor
;
33911 /* Declare alias N. A helper function for for_node_and_aliases. */
33914 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
33916 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
33917 /* Main symbol is output specially, because varasm machinery does part of
33918 the job for us - we do not need to declare .globl/lglobs and such. */
33919 if (!n
->alias
|| n
->weakref
)
33922 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
33925 /* Prevent assemble_alias from trying to use .set pseudo operation
33926 that does not behave as expected by the middle-end. */
33927 TREE_ASM_WRITTEN (n
->decl
) = true;
33929 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
33930 char *buffer
= (char *) alloca (strlen (name
) + 2);
33932 int dollar_inside
= 0;
33934 strcpy (buffer
, name
);
33935 p
= strchr (buffer
, '$');
33939 p
= strchr (p
+ 1, '$');
33941 if (TREE_PUBLIC (n
->decl
))
33943 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
33945 if (dollar_inside
) {
33946 if (data
->function_descriptor
)
33947 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33948 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33950 if (data
->function_descriptor
)
33952 fputs ("\t.globl .", data
->file
);
33953 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33954 putc ('\n', data
->file
);
33956 fputs ("\t.globl ", data
->file
);
33957 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33958 putc ('\n', data
->file
);
33960 #ifdef ASM_WEAKEN_DECL
33961 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
33962 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
33969 if (data
->function_descriptor
)
33970 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33971 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33973 if (data
->function_descriptor
)
33975 fputs ("\t.lglobl .", data
->file
);
33976 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33977 putc ('\n', data
->file
);
33979 fputs ("\t.lglobl ", data
->file
);
33980 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33981 putc ('\n', data
->file
);
33983 if (data
->function_descriptor
)
33984 fputs (".", data
->file
);
33985 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33986 fputs (":\n", data
->file
);
33991 #ifdef HAVE_GAS_HIDDEN
33992 /* Helper function to calculate visibility of a DECL
33993 and return the value as a const string. */
33995 static const char *
33996 rs6000_xcoff_visibility (tree decl
)
33998 static const char * const visibility_types
[] = {
33999 "", ",protected", ",hidden", ",internal"
34002 enum symbol_visibility vis
= DECL_VISIBILITY (decl
);
34003 return visibility_types
[vis
];
34008 /* This macro produces the initial definition of a function name.
34009 On the RS/6000, we need to place an extra '.' in the function name and
34010 output the function descriptor.
34011 Dollar signs are converted to underscores.
34013 The csect for the function will have already been created when
34014 text_section was selected. We do have to go back to that csect, however.
34016 The third and fourth parameters to the .function pseudo-op (16 and 044)
34017 are placeholders which no longer have any use.
34019 Because AIX assembler's .set command has unexpected semantics, we output
34020 all aliases as alternative labels in front of the definition. */
34023 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
34025 char *buffer
= (char *) alloca (strlen (name
) + 1);
34027 int dollar_inside
= 0;
34028 struct declare_alias_data data
= {file
, false};
34030 strcpy (buffer
, name
);
34031 p
= strchr (buffer
, '$');
34035 p
= strchr (p
+ 1, '$');
34037 if (TREE_PUBLIC (decl
))
34039 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
34041 if (dollar_inside
) {
34042 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
34043 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
34045 fputs ("\t.globl .", file
);
34046 RS6000_OUTPUT_BASENAME (file
, buffer
);
34047 #ifdef HAVE_GAS_HIDDEN
34048 fputs (rs6000_xcoff_visibility (decl
), file
);
34055 if (dollar_inside
) {
34056 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
34057 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
34059 fputs ("\t.lglobl .", file
);
34060 RS6000_OUTPUT_BASENAME (file
, buffer
);
34063 fputs ("\t.csect ", file
);
34064 RS6000_OUTPUT_BASENAME (file
, buffer
);
34065 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
34066 RS6000_OUTPUT_BASENAME (file
, buffer
);
34067 fputs (":\n", file
);
34068 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
34070 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
34071 RS6000_OUTPUT_BASENAME (file
, buffer
);
34072 fputs (", TOC[tc0], 0\n", file
);
34074 switch_to_section (function_section (decl
));
34076 RS6000_OUTPUT_BASENAME (file
, buffer
);
34077 fputs (":\n", file
);
34078 data
.function_descriptor
= true;
34079 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
34081 if (!DECL_IGNORED_P (decl
))
34083 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
34084 xcoffout_declare_function (file
, decl
, buffer
);
34085 else if (write_symbols
== DWARF2_DEBUG
)
34087 name
= (*targetm
.strip_name_encoding
) (name
);
34088 fprintf (file
, "\t.function .%s,.%s,2,0\n", name
, name
);
34095 /* Output assembly language to globalize a symbol from a DECL,
34096 possibly with visibility. */
34099 rs6000_xcoff_asm_globalize_decl_name (FILE *stream
, tree decl
)
34101 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
34102 fputs (GLOBAL_ASM_OP
, stream
);
34103 RS6000_OUTPUT_BASENAME (stream
, name
);
34104 #ifdef HAVE_GAS_HIDDEN
34105 fputs (rs6000_xcoff_visibility (decl
), stream
);
34107 putc ('\n', stream
);
34110 /* Output assembly language to define a symbol as COMMON from a DECL,
34111 possibly with visibility. */
34114 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream
,
34115 tree decl ATTRIBUTE_UNUSED
,
34117 unsigned HOST_WIDE_INT size
,
34118 unsigned HOST_WIDE_INT align
)
34120 unsigned HOST_WIDE_INT align2
= 2;
34123 align2
= floor_log2 (align
/ BITS_PER_UNIT
);
34127 fputs (COMMON_ASM_OP
, stream
);
34128 RS6000_OUTPUT_BASENAME (stream
, name
);
34131 "," HOST_WIDE_INT_PRINT_UNSIGNED
"," HOST_WIDE_INT_PRINT_UNSIGNED
,
34134 #ifdef HAVE_GAS_HIDDEN
34136 fputs (rs6000_xcoff_visibility (decl
), stream
);
34138 putc ('\n', stream
);
34141 /* This macro produces the initial definition of a object (variable) name.
34142 Because AIX assembler's .set command has unexpected semantics, we output
34143 all aliases as alternative labels in front of the definition. */
34146 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
34148 struct declare_alias_data data
= {file
, false};
34149 RS6000_OUTPUT_BASENAME (file
, name
);
34150 fputs (":\n", file
);
34151 symtab_node::get_create (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
34155 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34158 rs6000_asm_output_dwarf_pcrel (FILE *file
, int size
, const char *label
)
34160 fputs (integer_asm_op (size
, FALSE
), file
);
34161 assemble_name (file
, label
);
34162 fputs ("-$", file
);
34165 /* Output a symbol offset relative to the dbase for the current object.
34166 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34169 __gcc_unwind_dbase is embedded in all executables/libraries through
34170 libgcc/config/rs6000/crtdbase.S. */
34173 rs6000_asm_output_dwarf_datarel (FILE *file
, int size
, const char *label
)
34175 fputs (integer_asm_op (size
, FALSE
), file
);
34176 assemble_name (file
, label
);
34177 fputs("-__gcc_unwind_dbase", file
);
34182 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
34186 const char *symname
;
34188 default_encode_section_info (decl
, rtl
, first
);
34190 /* Careful not to prod global register variables. */
34193 symbol
= XEXP (rtl
, 0);
34194 if (GET_CODE (symbol
) != SYMBOL_REF
)
34197 flags
= SYMBOL_REF_FLAGS (symbol
);
34199 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
34200 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
34202 SYMBOL_REF_FLAGS (symbol
) = flags
;
34204 /* Append mapping class to extern decls. */
34205 symname
= XSTR (symbol
, 0);
34206 if (decl
/* sync condition with assemble_external () */
34207 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
34208 && ((TREE_CODE (decl
) == VAR_DECL
&& !DECL_THREAD_LOCAL_P (decl
))
34209 || TREE_CODE (decl
) == FUNCTION_DECL
)
34210 && symname
[strlen (symname
) - 1] != ']')
34212 char *newname
= (char *) alloca (strlen (symname
) + 5);
34213 strcpy (newname
, symname
);
34214 strcat (newname
, (TREE_CODE (decl
) == FUNCTION_DECL
34215 ? "[DS]" : "[UA]"));
34216 XSTR (symbol
, 0) = ggc_strdup (newname
);
34219 #endif /* HAVE_AS_TLS */
34220 #endif /* TARGET_XCOFF */
34223 rs6000_asm_weaken_decl (FILE *stream
, tree decl
,
34224 const char *name
, const char *val
)
34226 fputs ("\t.weak\t", stream
);
34227 RS6000_OUTPUT_BASENAME (stream
, name
);
34228 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
34229 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
34232 fputs ("[DS]", stream
);
34233 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34235 fputs (rs6000_xcoff_visibility (decl
), stream
);
34237 fputs ("\n\t.weak\t.", stream
);
34238 RS6000_OUTPUT_BASENAME (stream
, name
);
34240 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34242 fputs (rs6000_xcoff_visibility (decl
), stream
);
34244 fputc ('\n', stream
);
34247 #ifdef ASM_OUTPUT_DEF
34248 ASM_OUTPUT_DEF (stream
, name
, val
);
34250 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
34251 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
34253 fputs ("\t.set\t.", stream
);
34254 RS6000_OUTPUT_BASENAME (stream
, name
);
34255 fputs (",.", stream
);
34256 RS6000_OUTPUT_BASENAME (stream
, val
);
34257 fputc ('\n', stream
);
34263 /* Return true if INSN should not be copied. */
34266 rs6000_cannot_copy_insn_p (rtx_insn
*insn
)
34268 return recog_memoized (insn
) >= 0
34269 && get_attr_cannot_copy (insn
);
34272 /* Compute a (partial) cost for rtx X. Return true if the complete
34273 cost has been computed, and false if subexpressions should be
34274 scanned. In either case, *TOTAL contains the cost result. */
34277 rs6000_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
34278 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
34280 int code
= GET_CODE (x
);
34284 /* On the RS/6000, if it is valid in the insn, it is free. */
34286 if (((outer_code
== SET
34287 || outer_code
== PLUS
34288 || outer_code
== MINUS
)
34289 && (satisfies_constraint_I (x
)
34290 || satisfies_constraint_L (x
)))
34291 || (outer_code
== AND
34292 && (satisfies_constraint_K (x
)
34294 ? satisfies_constraint_L (x
)
34295 : satisfies_constraint_J (x
))))
34296 || ((outer_code
== IOR
|| outer_code
== XOR
)
34297 && (satisfies_constraint_K (x
)
34299 ? satisfies_constraint_L (x
)
34300 : satisfies_constraint_J (x
))))
34301 || outer_code
== ASHIFT
34302 || outer_code
== ASHIFTRT
34303 || outer_code
== LSHIFTRT
34304 || outer_code
== ROTATE
34305 || outer_code
== ROTATERT
34306 || outer_code
== ZERO_EXTRACT
34307 || (outer_code
== MULT
34308 && satisfies_constraint_I (x
))
34309 || ((outer_code
== DIV
|| outer_code
== UDIV
34310 || outer_code
== MOD
|| outer_code
== UMOD
)
34311 && exact_log2 (INTVAL (x
)) >= 0)
34312 || (outer_code
== COMPARE
34313 && (satisfies_constraint_I (x
)
34314 || satisfies_constraint_K (x
)))
34315 || ((outer_code
== EQ
|| outer_code
== NE
)
34316 && (satisfies_constraint_I (x
)
34317 || satisfies_constraint_K (x
)
34319 ? satisfies_constraint_L (x
)
34320 : satisfies_constraint_J (x
))))
34321 || (outer_code
== GTU
34322 && satisfies_constraint_I (x
))
34323 || (outer_code
== LTU
34324 && satisfies_constraint_P (x
)))
34329 else if ((outer_code
== PLUS
34330 && reg_or_add_cint_operand (x
, VOIDmode
))
34331 || (outer_code
== MINUS
34332 && reg_or_sub_cint_operand (x
, VOIDmode
))
34333 || ((outer_code
== SET
34334 || outer_code
== IOR
34335 || outer_code
== XOR
)
34337 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
34339 *total
= COSTS_N_INSNS (1);
34345 case CONST_WIDE_INT
:
34349 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34353 /* When optimizing for size, MEM should be slightly more expensive
34354 than generating address, e.g., (plus (reg) (const)).
34355 L1 cache latency is about two instructions. */
34356 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34357 if (rs6000_slow_unaligned_access (mode
, MEM_ALIGN (x
)))
34358 *total
+= COSTS_N_INSNS (100);
34367 if (FLOAT_MODE_P (mode
))
34368 *total
= rs6000_cost
->fp
;
34370 *total
= COSTS_N_INSNS (1);
34374 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
34375 && satisfies_constraint_I (XEXP (x
, 1)))
34377 if (INTVAL (XEXP (x
, 1)) >= -256
34378 && INTVAL (XEXP (x
, 1)) <= 255)
34379 *total
= rs6000_cost
->mulsi_const9
;
34381 *total
= rs6000_cost
->mulsi_const
;
34383 else if (mode
== SFmode
)
34384 *total
= rs6000_cost
->fp
;
34385 else if (FLOAT_MODE_P (mode
))
34386 *total
= rs6000_cost
->dmul
;
34387 else if (mode
== DImode
)
34388 *total
= rs6000_cost
->muldi
;
34390 *total
= rs6000_cost
->mulsi
;
34394 if (mode
== SFmode
)
34395 *total
= rs6000_cost
->fp
;
34397 *total
= rs6000_cost
->dmul
;
34402 if (FLOAT_MODE_P (mode
))
34404 *total
= mode
== DFmode
? rs6000_cost
->ddiv
34405 : rs6000_cost
->sdiv
;
34412 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
34413 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
34415 if (code
== DIV
|| code
== MOD
)
34417 *total
= COSTS_N_INSNS (2);
34420 *total
= COSTS_N_INSNS (1);
34424 if (GET_MODE (XEXP (x
, 1)) == DImode
)
34425 *total
= rs6000_cost
->divdi
;
34427 *total
= rs6000_cost
->divsi
;
34429 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34430 if (!TARGET_MODULO
&& (code
== MOD
|| code
== UMOD
))
34431 *total
+= COSTS_N_INSNS (2);
34435 *total
= COSTS_N_INSNS (TARGET_CTZ
? 1 : 4);
34439 *total
= COSTS_N_INSNS (4);
34443 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
34447 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
34451 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
34454 *total
= COSTS_N_INSNS (1);
34458 if (CONST_INT_P (XEXP (x
, 1)))
34460 rtx left
= XEXP (x
, 0);
34461 rtx_code left_code
= GET_CODE (left
);
34463 /* rotate-and-mask: 1 insn. */
34464 if ((left_code
== ROTATE
34465 || left_code
== ASHIFT
34466 || left_code
== LSHIFTRT
)
34467 && rs6000_is_valid_shift_mask (XEXP (x
, 1), left
, mode
))
34469 *total
= rtx_cost (XEXP (left
, 0), mode
, left_code
, 0, speed
);
34470 if (!CONST_INT_P (XEXP (left
, 1)))
34471 *total
+= rtx_cost (XEXP (left
, 1), SImode
, left_code
, 1, speed
);
34472 *total
+= COSTS_N_INSNS (1);
34476 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34477 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
34478 if (rs6000_is_valid_and_mask (XEXP (x
, 1), mode
)
34479 || (val
& 0xffff) == val
34480 || (val
& 0xffff0000) == val
34481 || ((val
& 0xffff) == 0 && mode
== SImode
))
34483 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34484 *total
+= COSTS_N_INSNS (1);
34489 if (rs6000_is_valid_2insn_and (XEXP (x
, 1), mode
))
34491 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34492 *total
+= COSTS_N_INSNS (2);
34497 *total
= COSTS_N_INSNS (1);
34502 *total
= COSTS_N_INSNS (1);
34508 *total
= COSTS_N_INSNS (1);
34512 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34513 the sign extend and shift separately within the insn. */
34514 if (TARGET_EXTSWSLI
&& mode
== DImode
34515 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
34516 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == SImode
)
34527 /* Handle mul_highpart. */
34528 if (outer_code
== TRUNCATE
34529 && GET_CODE (XEXP (x
, 0)) == MULT
)
34531 if (mode
== DImode
)
34532 *total
= rs6000_cost
->muldi
;
34534 *total
= rs6000_cost
->mulsi
;
34537 else if (outer_code
== AND
)
34540 *total
= COSTS_N_INSNS (1);
34545 if (GET_CODE (XEXP (x
, 0)) == MEM
)
34548 *total
= COSTS_N_INSNS (1);
34554 if (!FLOAT_MODE_P (mode
))
34556 *total
= COSTS_N_INSNS (1);
34562 case UNSIGNED_FLOAT
:
34565 case FLOAT_TRUNCATE
:
34566 *total
= rs6000_cost
->fp
;
34570 if (mode
== DFmode
)
34571 *total
= rs6000_cost
->sfdf_convert
;
34573 *total
= rs6000_cost
->fp
;
34577 switch (XINT (x
, 1))
34580 *total
= rs6000_cost
->fp
;
34592 *total
= COSTS_N_INSNS (1);
34595 else if (FLOAT_MODE_P (mode
) && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
)
34597 *total
= rs6000_cost
->fp
;
34606 /* Carry bit requires mode == Pmode.
34607 NEG or PLUS already counted so only add one. */
34609 && (outer_code
== NEG
|| outer_code
== PLUS
))
34611 *total
= COSTS_N_INSNS (1);
34619 if (outer_code
== SET
)
34621 if (XEXP (x
, 1) == const0_rtx
)
34623 *total
= COSTS_N_INSNS (2);
34628 *total
= COSTS_N_INSNS (3);
34633 if (outer_code
== COMPARE
)
34647 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34650 rs6000_debug_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
34651 int opno
, int *total
, bool speed
)
34653 bool ret
= rs6000_rtx_costs (x
, mode
, outer_code
, opno
, total
, speed
);
34656 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34657 "opno = %d, total = %d, speed = %s, x:\n",
34658 ret
? "complete" : "scan inner",
34659 GET_MODE_NAME (mode
),
34660 GET_RTX_NAME (outer_code
),
34663 speed
? "true" : "false");
34671 rs6000_insn_cost (rtx_insn
*insn
, bool speed
)
34673 if (recog_memoized (insn
) < 0)
34677 return get_attr_length (insn
);
34679 int cost
= get_attr_cost (insn
);
34683 int n
= get_attr_length (insn
) / 4;
34684 enum attr_type type
= get_attr_type (insn
);
34691 cost
= COSTS_N_INSNS (n
+ 1);
34695 switch (get_attr_size (insn
))
34698 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi_const9
;
34701 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi_const
;
34704 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi
;
34707 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->muldi
;
34710 gcc_unreachable ();
34714 switch (get_attr_size (insn
))
34717 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->divsi
;
34720 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->divdi
;
34723 gcc_unreachable ();
34728 cost
= n
* rs6000_cost
->fp
;
34731 cost
= n
* rs6000_cost
->dmul
;
34734 cost
= n
* rs6000_cost
->sdiv
;
34737 cost
= n
* rs6000_cost
->ddiv
;
34744 cost
= COSTS_N_INSNS (n
+ 2);
34748 cost
= COSTS_N_INSNS (n
);
34754 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34757 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
34758 addr_space_t as
, bool speed
)
34760 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
34762 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34763 ret
, speed
? "true" : "false");
34770 /* A C expression returning the cost of moving data from a register of class
34771 CLASS1 to one of CLASS2. */
34774 rs6000_register_move_cost (machine_mode mode
,
34775 reg_class_t from
, reg_class_t to
)
34779 if (TARGET_DEBUG_COST
)
34782 /* Moves from/to GENERAL_REGS. */
34783 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
34784 || reg_classes_intersect_p (from
, GENERAL_REGS
))
34786 reg_class_t rclass
= from
;
34788 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
34791 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
34792 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
34793 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
34795 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34797 else if (rclass
== CR_REGS
)
34800 /* For those processors that have slow LR/CTR moves, make them more
34801 expensive than memory in order to bias spills to memory .*/
34802 else if ((rs6000_tune
== PROCESSOR_POWER6
34803 || rs6000_tune
== PROCESSOR_POWER7
34804 || rs6000_tune
== PROCESSOR_POWER8
34805 || rs6000_tune
== PROCESSOR_POWER9
)
34806 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
34807 ret
= 6 * hard_regno_nregs (0, mode
);
34810 /* A move will cost one instruction per GPR moved. */
34811 ret
= 2 * hard_regno_nregs (0, mode
);
34814 /* If we have VSX, we can easily move between FPR or Altivec registers. */
34815 else if (VECTOR_MEM_VSX_P (mode
)
34816 && reg_classes_intersect_p (to
, VSX_REGS
)
34817 && reg_classes_intersect_p (from
, VSX_REGS
))
34818 ret
= 2 * hard_regno_nregs (FIRST_FPR_REGNO
, mode
);
34820 /* Moving between two similar registers is just one instruction. */
34821 else if (reg_classes_intersect_p (to
, from
))
34822 ret
= (FLOAT128_2REG_P (mode
)) ? 4 : 2;
34824 /* Everything else has to go through GENERAL_REGS. */
34826 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
34827 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
34829 if (TARGET_DEBUG_COST
)
34831 if (dbg_cost_ctrl
== 1)
34833 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
34834 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
34835 reg_class_names
[to
]);
34842 /* A C expressions returning the cost of moving data of MODE from a register to
34846 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
34847 bool in ATTRIBUTE_UNUSED
)
34851 if (TARGET_DEBUG_COST
)
34854 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
34855 ret
= 4 * hard_regno_nregs (0, mode
);
34856 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
34857 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
34858 ret
= 4 * hard_regno_nregs (32, mode
);
34859 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
34860 ret
= 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO
, mode
);
34862 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
34864 if (TARGET_DEBUG_COST
)
34866 if (dbg_cost_ctrl
== 1)
34868 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34869 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
34876 /* Returns a code for a target-specific builtin that implements
34877 reciprocal of the function, or NULL_TREE if not available. */
34880 rs6000_builtin_reciprocal (tree fndecl
)
34882 switch (DECL_FUNCTION_CODE (fndecl
))
34884 case VSX_BUILTIN_XVSQRTDP
:
34885 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
34888 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
34890 case VSX_BUILTIN_XVSQRTSP
:
34891 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
34894 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
34901 /* Load up a constant. If the mode is a vector mode, splat the value across
34902 all of the vector elements. */
34905 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
34909 if (mode
== SFmode
|| mode
== DFmode
)
34911 rtx d
= const_double_from_real_value (dconst
, mode
);
34912 reg
= force_reg (mode
, d
);
34914 else if (mode
== V4SFmode
)
34916 rtx d
= const_double_from_real_value (dconst
, SFmode
);
34917 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
34918 reg
= gen_reg_rtx (mode
);
34919 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
34921 else if (mode
== V2DFmode
)
34923 rtx d
= const_double_from_real_value (dconst
, DFmode
);
34924 rtvec v
= gen_rtvec (2, d
, d
);
34925 reg
= gen_reg_rtx (mode
);
34926 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
34929 gcc_unreachable ();
34934 /* Generate an FMA instruction. */
34937 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
34939 machine_mode mode
= GET_MODE (target
);
34942 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
34943 gcc_assert (dst
!= NULL
);
34946 emit_move_insn (target
, dst
);
34949 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34952 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
34954 machine_mode mode
= GET_MODE (dst
);
34957 /* This is a tad more complicated, since the fnma_optab is for
34958 a different expression: fma(-m1, m2, a), which is the same
34959 thing except in the case of signed zeros.
34961 Fortunately we know that if FMA is supported that FNMSUB is
34962 also supported in the ISA. Just expand it directly. */
34964 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
34966 r
= gen_rtx_NEG (mode
, a
);
34967 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
34968 r
= gen_rtx_NEG (mode
, r
);
34969 emit_insn (gen_rtx_SET (dst
, r
));
34972 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34973 add a reg_note saying that this was a division. Support both scalar and
34974 vector divide. Assumes no trapping math and finite arguments. */
34977 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
34979 machine_mode mode
= GET_MODE (dst
);
34980 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
34983 /* Low precision estimates guarantee 5 bits of accuracy. High
34984 precision estimates guarantee 14 bits of accuracy. SFmode
34985 requires 23 bits of accuracy. DFmode requires 52 bits of
34986 accuracy. Each pass at least doubles the accuracy, leading
34987 to the following. */
34988 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
34989 if (mode
== DFmode
|| mode
== V2DFmode
)
34992 enum insn_code code
= optab_handler (smul_optab
, mode
);
34993 insn_gen_fn gen_mul
= GEN_FCN (code
);
34995 gcc_assert (code
!= CODE_FOR_nothing
);
34997 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
34999 /* x0 = 1./d estimate */
35000 x0
= gen_reg_rtx (mode
);
35001 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
35004 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35007 /* e0 = 1. - d * x0 */
35008 e0
= gen_reg_rtx (mode
);
35009 rs6000_emit_nmsub (e0
, d
, x0
, one
);
35011 /* x1 = x0 + e0 * x0 */
35012 x1
= gen_reg_rtx (mode
);
35013 rs6000_emit_madd (x1
, e0
, x0
, x0
);
35015 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
35016 ++i
, xprev
= xnext
, eprev
= enext
) {
35018 /* enext = eprev * eprev */
35019 enext
= gen_reg_rtx (mode
);
35020 emit_insn (gen_mul (enext
, eprev
, eprev
));
35022 /* xnext = xprev + enext * xprev */
35023 xnext
= gen_reg_rtx (mode
);
35024 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
35030 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35032 /* u = n * xprev */
35033 u
= gen_reg_rtx (mode
);
35034 emit_insn (gen_mul (u
, n
, xprev
));
35036 /* v = n - (d * u) */
35037 v
= gen_reg_rtx (mode
);
35038 rs6000_emit_nmsub (v
, d
, u
, n
);
35040 /* dst = (v * xprev) + u */
35041 rs6000_emit_madd (dst
, v
, xprev
, u
);
35044 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
35047 /* Goldschmidt's Algorithm for single/double-precision floating point
35048 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35051 rs6000_emit_swsqrt (rtx dst
, rtx src
, bool recip
)
35053 machine_mode mode
= GET_MODE (src
);
35054 rtx e
= gen_reg_rtx (mode
);
35055 rtx g
= gen_reg_rtx (mode
);
35056 rtx h
= gen_reg_rtx (mode
);
35058 /* Low precision estimates guarantee 5 bits of accuracy. High
35059 precision estimates guarantee 14 bits of accuracy. SFmode
35060 requires 23 bits of accuracy. DFmode requires 52 bits of
35061 accuracy. Each pass at least doubles the accuracy, leading
35062 to the following. */
35063 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
35064 if (mode
== DFmode
|| mode
== V2DFmode
)
35069 enum insn_code code
= optab_handler (smul_optab
, mode
);
35070 insn_gen_fn gen_mul
= GEN_FCN (code
);
35072 gcc_assert (code
!= CODE_FOR_nothing
);
35074 mhalf
= rs6000_load_constant_and_splat (mode
, dconsthalf
);
35076 /* e = rsqrt estimate */
35077 emit_insn (gen_rtx_SET (e
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
35080 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35083 rtx zero
= force_reg (mode
, CONST0_RTX (mode
));
35085 if (mode
== SFmode
)
35087 rtx target
= emit_conditional_move (e
, GT
, src
, zero
, mode
,
35090 emit_move_insn (e
, target
);
35094 rtx cond
= gen_rtx_GT (VOIDmode
, e
, zero
);
35095 rs6000_emit_vector_cond_expr (e
, e
, zero
, cond
, src
, zero
);
35099 /* g = sqrt estimate. */
35100 emit_insn (gen_mul (g
, e
, src
));
35101 /* h = 1/(2*sqrt) estimate. */
35102 emit_insn (gen_mul (h
, e
, mhalf
));
35108 rtx t
= gen_reg_rtx (mode
);
35109 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
35110 /* Apply correction directly to 1/rsqrt estimate. */
35111 rs6000_emit_madd (dst
, e
, t
, e
);
35115 for (i
= 0; i
< passes
; i
++)
35117 rtx t1
= gen_reg_rtx (mode
);
35118 rtx g1
= gen_reg_rtx (mode
);
35119 rtx h1
= gen_reg_rtx (mode
);
35121 rs6000_emit_nmsub (t1
, g
, h
, mhalf
);
35122 rs6000_emit_madd (g1
, g
, t1
, g
);
35123 rs6000_emit_madd (h1
, h
, t1
, h
);
35128 /* Multiply by 2 for 1/rsqrt. */
35129 emit_insn (gen_add3_insn (dst
, h
, h
));
35134 rtx t
= gen_reg_rtx (mode
);
35135 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
35136 rs6000_emit_madd (dst
, g
, t
, g
);
35142 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35143 (Power7) targets. DST is the target, and SRC is the argument operand. */
35146 rs6000_emit_popcount (rtx dst
, rtx src
)
35148 machine_mode mode
= GET_MODE (dst
);
35151 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35152 if (TARGET_POPCNTD
)
35154 if (mode
== SImode
)
35155 emit_insn (gen_popcntdsi2 (dst
, src
));
35157 emit_insn (gen_popcntddi2 (dst
, src
));
35161 tmp1
= gen_reg_rtx (mode
);
35163 if (mode
== SImode
)
35165 emit_insn (gen_popcntbsi2 (tmp1
, src
));
35166 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
35168 tmp2
= force_reg (SImode
, tmp2
);
35169 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
35173 emit_insn (gen_popcntbdi2 (tmp1
, src
));
35174 tmp2
= expand_mult (DImode
, tmp1
,
35175 GEN_INT ((HOST_WIDE_INT
)
35176 0x01010101 << 32 | 0x01010101),
35178 tmp2
= force_reg (DImode
, tmp2
);
35179 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
35184 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35185 target, and SRC is the argument operand. */
35188 rs6000_emit_parity (rtx dst
, rtx src
)
35190 machine_mode mode
= GET_MODE (dst
);
35193 tmp
= gen_reg_rtx (mode
);
35195 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35198 if (mode
== SImode
)
35200 emit_insn (gen_popcntbsi2 (tmp
, src
));
35201 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
35205 emit_insn (gen_popcntbdi2 (tmp
, src
));
35206 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
35211 if (mode
== SImode
)
35213 /* Is mult+shift >= shift+xor+shift+xor? */
35214 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
35216 rtx tmp1
, tmp2
, tmp3
, tmp4
;
35218 tmp1
= gen_reg_rtx (SImode
);
35219 emit_insn (gen_popcntbsi2 (tmp1
, src
));
35221 tmp2
= gen_reg_rtx (SImode
);
35222 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
35223 tmp3
= gen_reg_rtx (SImode
);
35224 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
35226 tmp4
= gen_reg_rtx (SImode
);
35227 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
35228 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
35231 rs6000_emit_popcount (tmp
, src
);
35232 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
35236 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35237 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
35239 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
35241 tmp1
= gen_reg_rtx (DImode
);
35242 emit_insn (gen_popcntbdi2 (tmp1
, src
));
35244 tmp2
= gen_reg_rtx (DImode
);
35245 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
35246 tmp3
= gen_reg_rtx (DImode
);
35247 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
35249 tmp4
= gen_reg_rtx (DImode
);
35250 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
35251 tmp5
= gen_reg_rtx (DImode
);
35252 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
35254 tmp6
= gen_reg_rtx (DImode
);
35255 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
35256 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
35259 rs6000_emit_popcount (tmp
, src
);
35260 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
35264 /* Expand an Altivec constant permutation for little endian mode.
35265 OP0 and OP1 are the input vectors and TARGET is the output vector.
35266 SEL specifies the constant permutation vector.
35268 There are two issues: First, the two input operands must be
35269 swapped so that together they form a double-wide array in LE
35270 order. Second, the vperm instruction has surprising behavior
35271 in LE mode: it interprets the elements of the source vectors
35272 in BE mode ("left to right") and interprets the elements of
35273 the destination vector in LE mode ("right to left"). To
35274 correct for this, we must subtract each element of the permute
35275 control vector from 31.
35277 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35278 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35279 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35280 serve as the permute control vector. Then, in BE mode,
35284 places the desired result in vr9. However, in LE mode the
35285 vector contents will be
35287 vr10 = 00000003 00000002 00000001 00000000
35288 vr11 = 00000007 00000006 00000005 00000004
35290 The result of the vperm using the same permute control vector is
35292 vr9 = 05000000 07000000 01000000 03000000
35294 That is, the leftmost 4 bytes of vr10 are interpreted as the
35295 source for the rightmost 4 bytes of vr9, and so on.
35297 If we change the permute control vector to
35299 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35307 vr9 = 00000006 00000004 00000002 00000000. */
35310 altivec_expand_vec_perm_const_le (rtx target
, rtx op0
, rtx op1
,
35311 const vec_perm_indices
&sel
)
35315 rtx constv
, unspec
;
35317 /* Unpack and adjust the constant selector. */
35318 for (i
= 0; i
< 16; ++i
)
35320 unsigned int elt
= 31 - (sel
[i
] & 31);
35321 perm
[i
] = GEN_INT (elt
);
35324 /* Expand to a permute, swapping the inputs and using the
35325 adjusted selector. */
35327 op0
= force_reg (V16QImode
, op0
);
35329 op1
= force_reg (V16QImode
, op1
);
35331 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
35332 constv
= force_reg (V16QImode
, constv
);
35333 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
35335 if (!REG_P (target
))
35337 rtx tmp
= gen_reg_rtx (V16QImode
);
35338 emit_move_insn (tmp
, unspec
);
35342 emit_move_insn (target
, unspec
);
35345 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35346 permute control vector. But here it's not a constant, so we must
35347 generate a vector NAND or NOR to do the adjustment. */
35350 altivec_expand_vec_perm_le (rtx operands
[4])
35352 rtx notx
, iorx
, unspec
;
35353 rtx target
= operands
[0];
35354 rtx op0
= operands
[1];
35355 rtx op1
= operands
[2];
35356 rtx sel
= operands
[3];
35358 rtx norreg
= gen_reg_rtx (V16QImode
);
35359 machine_mode mode
= GET_MODE (target
);
35361 /* Get everything in regs so the pattern matches. */
35363 op0
= force_reg (mode
, op0
);
35365 op1
= force_reg (mode
, op1
);
35367 sel
= force_reg (V16QImode
, sel
);
35368 if (!REG_P (target
))
35369 tmp
= gen_reg_rtx (mode
);
35371 if (TARGET_P9_VECTOR
)
35373 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, sel
),
35378 /* Invert the selector with a VNAND if available, else a VNOR.
35379 The VNAND is preferred for future fusion opportunities. */
35380 notx
= gen_rtx_NOT (V16QImode
, sel
);
35381 iorx
= (TARGET_P8_VECTOR
35382 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
35383 : gen_rtx_AND (V16QImode
, notx
, notx
));
35384 emit_insn (gen_rtx_SET (norreg
, iorx
));
35386 /* Permute with operands reversed and adjusted selector. */
35387 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
35391 /* Copy into target, possibly by way of a register. */
35392 if (!REG_P (target
))
35394 emit_move_insn (tmp
, unspec
);
35398 emit_move_insn (target
, unspec
);
35401 /* Expand an Altivec constant permutation. Return true if we match
35402 an efficient implementation; false to fall back to VPERM.
35404 OP0 and OP1 are the input vectors and TARGET is the output vector.
35405 SEL specifies the constant permutation vector. */
35408 altivec_expand_vec_perm_const (rtx target
, rtx op0
, rtx op1
,
35409 const vec_perm_indices
&sel
)
35411 struct altivec_perm_insn
{
35412 HOST_WIDE_INT mask
;
35413 enum insn_code impl
;
35414 unsigned char perm
[16];
35416 static const struct altivec_perm_insn patterns
[] = {
35417 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
35418 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35419 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
35420 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35421 { OPTION_MASK_ALTIVEC
,
35422 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
35423 : CODE_FOR_altivec_vmrglb_direct
),
35424 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35425 { OPTION_MASK_ALTIVEC
,
35426 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
35427 : CODE_FOR_altivec_vmrglh_direct
),
35428 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35429 { OPTION_MASK_ALTIVEC
,
35430 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
35431 : CODE_FOR_altivec_vmrglw_direct
),
35432 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35433 { OPTION_MASK_ALTIVEC
,
35434 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
35435 : CODE_FOR_altivec_vmrghb_direct
),
35436 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35437 { OPTION_MASK_ALTIVEC
,
35438 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
35439 : CODE_FOR_altivec_vmrghh_direct
),
35440 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35441 { OPTION_MASK_ALTIVEC
,
35442 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
35443 : CODE_FOR_altivec_vmrghw_direct
),
35444 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35445 { OPTION_MASK_P8_VECTOR
,
35446 (BYTES_BIG_ENDIAN
? CODE_FOR_p8_vmrgew_v4sf_direct
35447 : CODE_FOR_p8_vmrgow_v4sf_direct
),
35448 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35449 { OPTION_MASK_P8_VECTOR
,
35450 (BYTES_BIG_ENDIAN
? CODE_FOR_p8_vmrgow_v4sf_direct
35451 : CODE_FOR_p8_vmrgew_v4sf_direct
),
35452 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35455 unsigned int i
, j
, elt
, which
;
35456 unsigned char perm
[16];
35460 /* Unpack the constant selector. */
35461 for (i
= which
= 0; i
< 16; ++i
)
35464 which
|= (elt
< 16 ? 1 : 2);
35468 /* Simplify the constant selector based on operands. */
35472 gcc_unreachable ();
35476 if (!rtx_equal_p (op0
, op1
))
35481 for (i
= 0; i
< 16; ++i
)
35493 /* Look for splat patterns. */
35498 for (i
= 0; i
< 16; ++i
)
35499 if (perm
[i
] != elt
)
35503 if (!BYTES_BIG_ENDIAN
)
35505 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
35511 for (i
= 0; i
< 16; i
+= 2)
35512 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
35516 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
35517 x
= gen_reg_rtx (V8HImode
);
35518 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
35520 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35527 for (i
= 0; i
< 16; i
+= 4)
35529 || perm
[i
+ 1] != elt
+ 1
35530 || perm
[i
+ 2] != elt
+ 2
35531 || perm
[i
+ 3] != elt
+ 3)
35535 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
35536 x
= gen_reg_rtx (V4SImode
);
35537 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
35539 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35545 /* Look for merge and pack patterns. */
35546 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
35550 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
35553 elt
= patterns
[j
].perm
[0];
35554 if (perm
[0] == elt
)
35556 else if (perm
[0] == elt
+ 16)
35560 for (i
= 1; i
< 16; ++i
)
35562 elt
= patterns
[j
].perm
[i
];
35564 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
35565 else if (one_vec
&& elt
>= 16)
35567 if (perm
[i
] != elt
)
35572 enum insn_code icode
= patterns
[j
].impl
;
35573 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
35574 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
35576 /* For little-endian, don't use vpkuwum and vpkuhum if the
35577 underlying vector type is not V4SI and V8HI, respectively.
35578 For example, using vpkuwum with a V8HI picks up the even
35579 halfwords (BE numbering) when the even halfwords (LE
35580 numbering) are what we need. */
35581 if (!BYTES_BIG_ENDIAN
35582 && icode
== CODE_FOR_altivec_vpkuwum_direct
35583 && ((GET_CODE (op0
) == REG
35584 && GET_MODE (op0
) != V4SImode
)
35585 || (GET_CODE (op0
) == SUBREG
35586 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
35588 if (!BYTES_BIG_ENDIAN
35589 && icode
== CODE_FOR_altivec_vpkuhum_direct
35590 && ((GET_CODE (op0
) == REG
35591 && GET_MODE (op0
) != V8HImode
)
35592 || (GET_CODE (op0
) == SUBREG
35593 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
35596 /* For little-endian, the two input operands must be swapped
35597 (or swapped back) to ensure proper right-to-left numbering
35599 if (swapped
^ !BYTES_BIG_ENDIAN
)
35600 std::swap (op0
, op1
);
35601 if (imode
!= V16QImode
)
35603 op0
= gen_lowpart (imode
, op0
);
35604 op1
= gen_lowpart (imode
, op1
);
35606 if (omode
== V16QImode
)
35609 x
= gen_reg_rtx (omode
);
35610 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
35611 if (omode
!= V16QImode
)
35612 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35617 if (!BYTES_BIG_ENDIAN
)
35619 altivec_expand_vec_perm_const_le (target
, op0
, op1
, sel
);
35626 /* Expand a VSX Permute Doubleword constant permutation.
35627 Return true if we match an efficient implementation. */
35630 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
35631 unsigned char perm0
, unsigned char perm1
)
35635 /* If both selectors come from the same operand, fold to single op. */
35636 if ((perm0
& 2) == (perm1
& 2))
35643 /* If both operands are equal, fold to simpler permutation. */
35644 if (rtx_equal_p (op0
, op1
))
35647 perm1
= (perm1
& 1) + 2;
35649 /* If the first selector comes from the second operand, swap. */
35650 else if (perm0
& 2)
35656 std::swap (op0
, op1
);
35658 /* If the second selector does not come from the second operand, fail. */
35659 else if ((perm1
& 2) == 0)
35663 if (target
!= NULL
)
35665 machine_mode vmode
, dmode
;
35668 vmode
= GET_MODE (target
);
35669 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
35670 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4).require ();
35671 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
35672 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
35673 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
35674 emit_insn (gen_rtx_SET (target
, x
));
35679 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35682 rs6000_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
,
35683 rtx op1
, const vec_perm_indices
&sel
)
35685 bool testing_p
= !target
;
35687 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35688 if (TARGET_ALTIVEC
&& testing_p
)
35691 /* Check for ps_merge* or xxpermdi insns. */
35692 if ((vmode
== V2DFmode
|| vmode
== V2DImode
) && VECTOR_MEM_VSX_P (vmode
))
35696 op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
35697 op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
35699 if (rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, sel
[0], sel
[1]))
35703 if (TARGET_ALTIVEC
)
35705 /* Force the target-independent code to lower to V16QImode. */
35706 if (vmode
!= V16QImode
)
35708 if (altivec_expand_vec_perm_const (target
, op0
, op1
, sel
))
35715 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35716 OP0 and OP1 are the input vectors and TARGET is the output vector.
35717 PERM specifies the constant permutation vector. */
35720 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
35721 machine_mode vmode
, const vec_perm_builder
&perm
)
35723 rtx x
= expand_vec_perm_const (vmode
, op0
, op1
, perm
, BLKmode
, target
);
35725 emit_move_insn (target
, x
);
35728 /* Expand an extract even operation. */
35731 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
35733 machine_mode vmode
= GET_MODE (target
);
35734 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
35735 vec_perm_builder
perm (nelt
, nelt
, 1);
35737 for (i
= 0; i
< nelt
; i
++)
35738 perm
.quick_push (i
* 2);
35740 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, perm
);
35743 /* Expand a vector interleave operation. */
35746 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
35748 machine_mode vmode
= GET_MODE (target
);
35749 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
35750 vec_perm_builder
perm (nelt
, nelt
, 1);
35752 high
= (highp
? 0 : nelt
/ 2);
35753 for (i
= 0; i
< nelt
/ 2; i
++)
35755 perm
.quick_push (i
+ high
);
35756 perm
.quick_push (i
+ nelt
+ high
);
35759 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, perm
);
35762 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35764 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
35766 HOST_WIDE_INT
hwi_scale (scale
);
35767 REAL_VALUE_TYPE r_pow
;
35768 rtvec v
= rtvec_alloc (2);
35770 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
35771 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
35772 elt
= const_double_from_real_value (r_pow
, DFmode
);
35773 RTVEC_ELT (v
, 0) = elt
;
35774 RTVEC_ELT (v
, 1) = elt
;
35775 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
35776 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
35779 /* Return an RTX representing where to find the function value of a
35780 function returning MODE. */
35782 rs6000_complex_function_value (machine_mode mode
)
35784 unsigned int regno
;
35786 machine_mode inner
= GET_MODE_INNER (mode
);
35787 unsigned int inner_bytes
= GET_MODE_UNIT_SIZE (mode
);
35789 if (TARGET_FLOAT128_TYPE
35791 || (mode
== TCmode
&& TARGET_IEEEQUAD
)))
35792 regno
= ALTIVEC_ARG_RETURN
;
35794 else if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35795 regno
= FP_ARG_RETURN
;
35799 regno
= GP_ARG_RETURN
;
35801 /* 32-bit is OK since it'll go in r3/r4. */
35802 if (TARGET_32BIT
&& inner_bytes
>= 4)
35803 return gen_rtx_REG (mode
, regno
);
35806 if (inner_bytes
>= 8)
35807 return gen_rtx_REG (mode
, regno
);
35809 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
35811 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
35812 GEN_INT (inner_bytes
));
35813 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
35816 /* Return an rtx describing a return value of MODE as a PARALLEL
35817 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35818 stride REG_STRIDE. */
35821 rs6000_parallel_return (machine_mode mode
,
35822 int n_elts
, machine_mode elt_mode
,
35823 unsigned int regno
, unsigned int reg_stride
)
35825 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
35828 for (i
= 0; i
< n_elts
; i
++)
35830 rtx r
= gen_rtx_REG (elt_mode
, regno
);
35831 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
35832 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
35833 regno
+= reg_stride
;
35839 /* Target hook for TARGET_FUNCTION_VALUE.
35841 An integer value is in r3 and a floating-point value is in fp1,
35842 unless -msoft-float. */
35845 rs6000_function_value (const_tree valtype
,
35846 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
35847 bool outgoing ATTRIBUTE_UNUSED
)
35850 unsigned int regno
;
35851 machine_mode elt_mode
;
35854 /* Special handling for structs in darwin64. */
35856 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
35858 CUMULATIVE_ARGS valcum
;
35862 valcum
.fregno
= FP_ARG_MIN_REG
;
35863 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
35864 /* Do a trial code generation as if this were going to be passed as
35865 an argument; if any part goes in memory, we return NULL. */
35866 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
35869 /* Otherwise fall through to standard ABI rules. */
35872 mode
= TYPE_MODE (valtype
);
35874 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35875 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
35877 int first_reg
, n_regs
;
35879 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode
))
35881 /* _Decimal128 must use even/odd register pairs. */
35882 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35883 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
35887 first_reg
= ALTIVEC_ARG_RETURN
;
35891 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
35894 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35895 if (TARGET_32BIT
&& TARGET_POWERPC64
)
35904 int count
= GET_MODE_SIZE (mode
) / 4;
35905 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
35908 if ((INTEGRAL_TYPE_P (valtype
)
35909 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
35910 || POINTER_TYPE_P (valtype
))
35911 mode
= TARGET_32BIT
? SImode
: DImode
;
35913 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35914 /* _Decimal128 must use an even/odd register pair. */
35915 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35916 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
35917 && !FLOAT128_VECTOR_P (mode
))
35918 regno
= FP_ARG_RETURN
;
35919 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
35920 && targetm
.calls
.split_complex_arg
)
35921 return rs6000_complex_function_value (mode
);
35922 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35923 return register is used in both cases, and we won't see V2DImode/V2DFmode
35924 for pure altivec, combine the two cases. */
35925 else if ((TREE_CODE (valtype
) == VECTOR_TYPE
|| FLOAT128_VECTOR_P (mode
))
35926 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
35927 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
35928 regno
= ALTIVEC_ARG_RETURN
;
35930 regno
= GP_ARG_RETURN
;
35932 return gen_rtx_REG (mode
, regno
);
35935 /* Define how to find the value returned by a library function
35936 assuming the value has mode MODE. */
35938 rs6000_libcall_value (machine_mode mode
)
35940 unsigned int regno
;
35942 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35943 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
35944 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
35946 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35947 /* _Decimal128 must use an even/odd register pair. */
35948 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35949 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && TARGET_HARD_FLOAT
)
35950 regno
= FP_ARG_RETURN
;
35951 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35952 return register is used in both cases, and we won't see V2DImode/V2DFmode
35953 for pure altivec, combine the two cases. */
35954 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
35955 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
35956 regno
= ALTIVEC_ARG_RETURN
;
35957 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
35958 return rs6000_complex_function_value (mode
);
35960 regno
= GP_ARG_RETURN
;
35962 return gen_rtx_REG (mode
, regno
);
35965 /* Compute register pressure classes. We implement the target hook to avoid
35966 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
35967 lead to incorrect estimates of number of available registers and therefor
35968 increased register pressure/spill. */
35970 rs6000_compute_pressure_classes (enum reg_class
*pressure_classes
)
35975 pressure_classes
[n
++] = GENERAL_REGS
;
35977 pressure_classes
[n
++] = VSX_REGS
;
35980 if (TARGET_ALTIVEC
)
35981 pressure_classes
[n
++] = ALTIVEC_REGS
;
35982 if (TARGET_HARD_FLOAT
)
35983 pressure_classes
[n
++] = FLOAT_REGS
;
35985 pressure_classes
[n
++] = CR_REGS
;
35986 pressure_classes
[n
++] = SPECIAL_REGS
;
35991 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35992 Frame pointer elimination is automatically handled.
35994 For the RS/6000, if frame pointer elimination is being done, we would like
35995 to convert ap into fp, not sp.
35997 We need r30 if -mminimal-toc was specified, and there are constant pool
36001 rs6000_can_eliminate (const int from
, const int to
)
36003 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
36004 ? ! frame_pointer_needed
36005 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
36006 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
36007 || constant_pool_empty_p ()
36011 /* Define the offset between two registers, FROM to be eliminated and its
36012 replacement TO, at the start of a routine. */
36014 rs6000_initial_elimination_offset (int from
, int to
)
36016 rs6000_stack_t
*info
= rs6000_stack_info ();
36017 HOST_WIDE_INT offset
;
36019 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
36020 offset
= info
->push_p
? 0 : -info
->total_size
;
36021 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
36023 offset
= info
->push_p
? 0 : -info
->total_size
;
36024 if (FRAME_GROWS_DOWNWARD
)
36025 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
36027 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
36028 offset
= FRAME_GROWS_DOWNWARD
36029 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
36031 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
36032 offset
= info
->total_size
;
36033 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
36034 offset
= info
->push_p
? info
->total_size
: 0;
36035 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
36038 gcc_unreachable ();
36043 /* Fill in sizes of registers used by unwinder. */
36046 rs6000_init_dwarf_reg_sizes_extra (tree address
)
36048 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
36051 machine_mode mode
= TYPE_MODE (char_type_node
);
36052 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
36053 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
36054 rtx value
= gen_int_mode (16, mode
);
36056 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36057 The unwinder still needs to know the size of Altivec registers. */
36059 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
36061 int column
= DWARF_REG_TO_UNWIND_COLUMN
36062 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
36063 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
36065 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
36070 /* Map internal gcc register numbers to debug format register numbers.
36071 FORMAT specifies the type of debug register number to use:
36072 0 -- debug information, except for frame-related sections
36073 1 -- DWARF .debug_frame section
36074 2 -- DWARF .eh_frame section */
36077 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
36079 /* Except for the above, we use the internal number for non-DWARF
36080 debug information, and also for .eh_frame. */
36081 if ((format
== 0 && write_symbols
!= DWARF2_DEBUG
) || format
== 2)
36084 /* On some platforms, we use the standard DWARF register
36085 numbering for .debug_info and .debug_frame. */
36086 #ifdef RS6000_USE_DWARF_NUMBERING
36089 if (regno
== LR_REGNO
)
36091 if (regno
== CTR_REGNO
)
36093 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36094 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36095 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36096 to the DWARF reg for CR. */
36097 if (format
== 1 && regno
== CR2_REGNO
)
36099 if (CR_REGNO_P (regno
))
36100 return regno
- CR0_REGNO
+ 86;
36101 if (regno
== CA_REGNO
)
36102 return 101; /* XER */
36103 if (ALTIVEC_REGNO_P (regno
))
36104 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
36105 if (regno
== VRSAVE_REGNO
)
36107 if (regno
== VSCR_REGNO
)
36113 /* target hook eh_return_filter_mode */
36114 static scalar_int_mode
36115 rs6000_eh_return_filter_mode (void)
36117 return TARGET_32BIT
? SImode
: word_mode
;
36120 /* Target hook for translate_mode_attribute. */
36121 static machine_mode
36122 rs6000_translate_mode_attribute (machine_mode mode
)
36124 if ((FLOAT128_IEEE_P (mode
)
36125 && ieee128_float_type_node
== long_double_type_node
)
36126 || (FLOAT128_IBM_P (mode
)
36127 && ibm128_float_type_node
== long_double_type_node
))
36128 return COMPLEX_MODE_P (mode
) ? E_TCmode
: E_TFmode
;
36132 /* Target hook for scalar_mode_supported_p. */
36134 rs6000_scalar_mode_supported_p (scalar_mode mode
)
36136 /* -m32 does not support TImode. This is the default, from
36137 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36138 same ABI as for -m32. But default_scalar_mode_supported_p allows
36139 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36140 for -mpowerpc64. */
36141 if (TARGET_32BIT
&& mode
== TImode
)
36144 if (DECIMAL_FLOAT_MODE_P (mode
))
36145 return default_decimal_float_supported_p ();
36146 else if (TARGET_FLOAT128_TYPE
&& (mode
== KFmode
|| mode
== IFmode
))
36149 return default_scalar_mode_supported_p (mode
);
36152 /* Target hook for vector_mode_supported_p. */
36154 rs6000_vector_mode_supported_p (machine_mode mode
)
36156 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36157 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36159 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
) && !FLOAT128_IEEE_P (mode
))
36166 /* Target hook for floatn_mode. */
36167 static opt_scalar_float_mode
36168 rs6000_floatn_mode (int n
, bool extended
)
36178 if (TARGET_FLOAT128_TYPE
)
36179 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36181 return opt_scalar_float_mode ();
36184 return opt_scalar_float_mode ();
36187 /* Those are the only valid _FloatNx types. */
36188 gcc_unreachable ();
36202 if (TARGET_FLOAT128_TYPE
)
36203 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36205 return opt_scalar_float_mode ();
36208 return opt_scalar_float_mode ();
36214 /* Target hook for c_mode_for_suffix. */
36215 static machine_mode
36216 rs6000_c_mode_for_suffix (char suffix
)
36218 if (TARGET_FLOAT128_TYPE
)
36220 if (suffix
== 'q' || suffix
== 'Q')
36221 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36223 /* At the moment, we are not defining a suffix for IBM extended double.
36224 If/when the default for -mabi=ieeelongdouble is changed, and we want
36225 to support __ibm128 constants in legacy library code, we may need to
36226 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36227 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36228 __float80 constants. */
36234 /* Target hook for invalid_arg_for_unprototyped_fn. */
36235 static const char *
36236 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
36238 return (!rs6000_darwin64_abi
36240 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
36241 && (funcdecl
== NULL_TREE
36242 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
36243 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
36244 ? N_("AltiVec argument passed to unprototyped function")
36248 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36249 setup by using __stack_chk_fail_local hidden function instead of
36250 calling __stack_chk_fail directly. Otherwise it is better to call
36251 __stack_chk_fail directly. */
36253 static tree ATTRIBUTE_UNUSED
36254 rs6000_stack_protect_fail (void)
36256 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
36257 ? default_hidden_stack_protect_fail ()
36258 : default_external_stack_protect_fail ();
36261 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36264 static unsigned HOST_WIDE_INT
36265 rs6000_asan_shadow_offset (void)
36267 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
36271 /* Mask options that we want to support inside of attribute((target)) and
36272 #pragma GCC target operations. Note, we do not include things like
36273 64/32-bit, endianness, hard/soft floating point, etc. that would have
36274 different calling sequences. */
36276 struct rs6000_opt_mask
{
36277 const char *name
; /* option name */
36278 HOST_WIDE_INT mask
; /* mask to set */
36279 bool invert
; /* invert sense of mask */
36280 bool valid_target
; /* option is a target option */
36283 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
36285 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
36286 { "cmpb", OPTION_MASK_CMPB
, false, true },
36287 { "crypto", OPTION_MASK_CRYPTO
, false, true },
36288 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
36289 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
36290 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX
,
36292 { "float128", OPTION_MASK_FLOAT128_KEYWORD
, false, true },
36293 { "float128-hardware", OPTION_MASK_FLOAT128_HW
, false, true },
36294 { "fprnd", OPTION_MASK_FPRND
, false, true },
36295 { "hard-dfp", OPTION_MASK_DFP
, false, true },
36296 { "htm", OPTION_MASK_HTM
, false, true },
36297 { "isel", OPTION_MASK_ISEL
, false, true },
36298 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
36299 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
36300 { "modulo", OPTION_MASK_MODULO
, false, true },
36301 { "mulhw", OPTION_MASK_MULHW
, false, true },
36302 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
36303 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
36304 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
36305 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
36306 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
36307 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
36308 { "power9-minmax", OPTION_MASK_P9_MINMAX
, false, true },
36309 { "power9-misc", OPTION_MASK_P9_MISC
, false, true },
36310 { "power9-vector", OPTION_MASK_P9_VECTOR
, false, true },
36311 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
36312 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
36313 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
36314 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
36315 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
36316 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
36317 { "string", 0, false, true },
36318 { "update", OPTION_MASK_NO_UPDATE
, true , true },
36319 { "vsx", OPTION_MASK_VSX
, false, true },
36320 #ifdef OPTION_MASK_64BIT
36322 { "aix64", OPTION_MASK_64BIT
, false, false },
36323 { "aix32", OPTION_MASK_64BIT
, true, false },
36325 { "64", OPTION_MASK_64BIT
, false, false },
36326 { "32", OPTION_MASK_64BIT
, true, false },
36329 #ifdef OPTION_MASK_EABI
36330 { "eabi", OPTION_MASK_EABI
, false, false },
36332 #ifdef OPTION_MASK_LITTLE_ENDIAN
36333 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
36334 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
36336 #ifdef OPTION_MASK_RELOCATABLE
36337 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
36339 #ifdef OPTION_MASK_STRICT_ALIGN
36340 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
36342 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
36343 { "string", 0, false, false },
36346 /* Builtin mask mapping for printing the flags. */
36347 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
36349 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
36350 { "vsx", RS6000_BTM_VSX
, false, false },
36351 { "fre", RS6000_BTM_FRE
, false, false },
36352 { "fres", RS6000_BTM_FRES
, false, false },
36353 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
36354 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
36355 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
36356 { "cell", RS6000_BTM_CELL
, false, false },
36357 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
36358 { "power9-vector", RS6000_BTM_P9_VECTOR
, false, false },
36359 { "power9-misc", RS6000_BTM_P9_MISC
, false, false },
36360 { "crypto", RS6000_BTM_CRYPTO
, false, false },
36361 { "htm", RS6000_BTM_HTM
, false, false },
36362 { "hard-dfp", RS6000_BTM_DFP
, false, false },
36363 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
36364 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
36365 { "powerpc64", RS6000_BTM_POWERPC64
, false, false },
36366 { "float128", RS6000_BTM_FLOAT128
, false, false },
36367 { "float128-hw", RS6000_BTM_FLOAT128_HW
,false, false },
36370 /* Option variables that we want to support inside attribute((target)) and
36371 #pragma GCC target operations. */
36373 struct rs6000_opt_var
{
36374 const char *name
; /* option name */
36375 size_t global_offset
; /* offset of the option in global_options. */
36376 size_t target_offset
; /* offset of the option in target options. */
36379 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
36382 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
36383 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
36384 { "avoid-indexed-addresses",
36385 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
36386 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
36388 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
36389 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
36390 { "optimize-swaps",
36391 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
36392 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
36393 { "allow-movmisalign",
36394 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
36395 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
36397 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
36398 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
36400 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
36401 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
36402 { "align-branch-targets",
36403 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
36404 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
36406 offsetof (struct gcc_options
, x_tls_markers
),
36407 offsetof (struct cl_target_option
, x_tls_markers
), },
36409 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36410 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36412 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36413 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36414 { "speculate-indirect-jumps",
36415 offsetof (struct gcc_options
, x_rs6000_speculate_indirect_jumps
),
36416 offsetof (struct cl_target_option
, x_rs6000_speculate_indirect_jumps
), },
36419 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36420 parsing. Return true if there were no errors. */
36423 rs6000_inner_target_options (tree args
, bool attr_p
)
36427 if (args
== NULL_TREE
)
36430 else if (TREE_CODE (args
) == STRING_CST
)
36432 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36435 while ((q
= strtok (p
, ",")) != NULL
)
36437 bool error_p
= false;
36438 bool not_valid_p
= false;
36439 const char *cpu_opt
= NULL
;
36442 if (strncmp (q
, "cpu=", 4) == 0)
36444 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
36445 if (cpu_index
>= 0)
36446 rs6000_cpu_index
= cpu_index
;
36453 else if (strncmp (q
, "tune=", 5) == 0)
36455 int tune_index
= rs6000_cpu_name_lookup (q
+5);
36456 if (tune_index
>= 0)
36457 rs6000_tune_index
= tune_index
;
36467 bool invert
= false;
36471 if (strncmp (r
, "no-", 3) == 0)
36477 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
36478 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
36480 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
36482 if (!rs6000_opt_masks
[i
].valid_target
)
36483 not_valid_p
= true;
36487 rs6000_isa_flags_explicit
|= mask
;
36489 /* VSX needs altivec, so -mvsx automagically sets
36490 altivec and disables -mavoid-indexed-addresses. */
36493 if (mask
== OPTION_MASK_VSX
)
36495 mask
|= OPTION_MASK_ALTIVEC
;
36496 TARGET_AVOID_XFORM
= 0;
36500 if (rs6000_opt_masks
[i
].invert
)
36504 rs6000_isa_flags
&= ~mask
;
36506 rs6000_isa_flags
|= mask
;
36511 if (error_p
&& !not_valid_p
)
36513 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
36514 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
36516 size_t j
= rs6000_opt_vars
[i
].global_offset
;
36517 *((int *) ((char *)&global_options
+ j
)) = !invert
;
36519 not_valid_p
= false;
36527 const char *eprefix
, *esuffix
;
36532 eprefix
= "__attribute__((__target__(";
36537 eprefix
= "#pragma GCC target ";
36542 error ("invalid cpu %qs for %s%qs%s", cpu_opt
, eprefix
,
36544 else if (not_valid_p
)
36545 error ("%s%qs%s is not allowed", eprefix
, q
, esuffix
);
36547 error ("%s%qs%s is invalid", eprefix
, q
, esuffix
);
36552 else if (TREE_CODE (args
) == TREE_LIST
)
36556 tree value
= TREE_VALUE (args
);
36559 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
36563 args
= TREE_CHAIN (args
);
36565 while (args
!= NULL_TREE
);
36570 error ("attribute %<target%> argument not a string");
36577 /* Print out the target options as a list for -mdebug=target. */
36580 rs6000_debug_target_options (tree args
, const char *prefix
)
36582 if (args
== NULL_TREE
)
36583 fprintf (stderr
, "%s<NULL>", prefix
);
36585 else if (TREE_CODE (args
) == STRING_CST
)
36587 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36590 while ((q
= strtok (p
, ",")) != NULL
)
36593 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
36598 else if (TREE_CODE (args
) == TREE_LIST
)
36602 tree value
= TREE_VALUE (args
);
36605 rs6000_debug_target_options (value
, prefix
);
36608 args
= TREE_CHAIN (args
);
36610 while (args
!= NULL_TREE
);
36614 gcc_unreachable ();
36620 /* Hook to validate attribute((target("..."))). */
36623 rs6000_valid_attribute_p (tree fndecl
,
36624 tree
ARG_UNUSED (name
),
36628 struct cl_target_option cur_target
;
36631 tree new_target
, new_optimize
;
36632 tree func_optimize
;
36634 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
36636 if (TARGET_DEBUG_TARGET
)
36638 tree tname
= DECL_NAME (fndecl
);
36639 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
36641 fprintf (stderr
, "function: %.*s\n",
36642 (int) IDENTIFIER_LENGTH (tname
),
36643 IDENTIFIER_POINTER (tname
));
36645 fprintf (stderr
, "function: unknown\n");
36647 fprintf (stderr
, "args:");
36648 rs6000_debug_target_options (args
, " ");
36649 fprintf (stderr
, "\n");
36652 fprintf (stderr
, "flags: 0x%x\n", flags
);
36654 fprintf (stderr
, "--------------------\n");
36657 /* attribute((target("default"))) does nothing, beyond
36658 affecting multi-versioning. */
36659 if (TREE_VALUE (args
)
36660 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
36661 && TREE_CHAIN (args
) == NULL_TREE
36662 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args
)), "default") == 0)
36665 old_optimize
= build_optimization_node (&global_options
);
36666 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
36668 /* If the function changed the optimization levels as well as setting target
36669 options, start with the optimizations specified. */
36670 if (func_optimize
&& func_optimize
!= old_optimize
)
36671 cl_optimization_restore (&global_options
,
36672 TREE_OPTIMIZATION (func_optimize
));
36674 /* The target attributes may also change some optimization flags, so update
36675 the optimization options if necessary. */
36676 cl_target_option_save (&cur_target
, &global_options
);
36677 rs6000_cpu_index
= rs6000_tune_index
= -1;
36678 ret
= rs6000_inner_target_options (args
, true);
36680 /* Set up any additional state. */
36683 ret
= rs6000_option_override_internal (false);
36684 new_target
= build_target_option_node (&global_options
);
36689 new_optimize
= build_optimization_node (&global_options
);
36696 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
36698 if (old_optimize
!= new_optimize
)
36699 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
36702 cl_target_option_restore (&global_options
, &cur_target
);
36704 if (old_optimize
!= new_optimize
)
36705 cl_optimization_restore (&global_options
,
36706 TREE_OPTIMIZATION (old_optimize
));
36712 /* Hook to validate the current #pragma GCC target and set the state, and
36713 update the macros based on what was changed. If ARGS is NULL, then
36714 POP_TARGET is used to reset the options. */
36717 rs6000_pragma_target_parse (tree args
, tree pop_target
)
36719 tree prev_tree
= build_target_option_node (&global_options
);
36721 struct cl_target_option
*prev_opt
, *cur_opt
;
36722 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
36723 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
36725 if (TARGET_DEBUG_TARGET
)
36727 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
36728 fprintf (stderr
, "args:");
36729 rs6000_debug_target_options (args
, " ");
36730 fprintf (stderr
, "\n");
36734 fprintf (stderr
, "pop_target:\n");
36735 debug_tree (pop_target
);
36738 fprintf (stderr
, "pop_target: <NULL>\n");
36740 fprintf (stderr
, "--------------------\n");
36745 cur_tree
= ((pop_target
)
36747 : target_option_default_node
);
36748 cl_target_option_restore (&global_options
,
36749 TREE_TARGET_OPTION (cur_tree
));
36753 rs6000_cpu_index
= rs6000_tune_index
= -1;
36754 if (!rs6000_inner_target_options (args
, false)
36755 || !rs6000_option_override_internal (false)
36756 || (cur_tree
= build_target_option_node (&global_options
))
36759 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
36760 fprintf (stderr
, "invalid pragma\n");
36766 target_option_current_node
= cur_tree
;
36767 rs6000_activate_target_options (target_option_current_node
);
36769 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36770 change the macros that are defined. */
36771 if (rs6000_target_modify_macros_ptr
)
36773 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
36774 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
36775 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
36777 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
36778 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
36779 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
36781 diff_bumask
= (prev_bumask
^ cur_bumask
);
36782 diff_flags
= (prev_flags
^ cur_flags
);
36784 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
36786 /* Delete old macros. */
36787 rs6000_target_modify_macros_ptr (false,
36788 prev_flags
& diff_flags
,
36789 prev_bumask
& diff_bumask
);
36791 /* Define new macros. */
36792 rs6000_target_modify_macros_ptr (true,
36793 cur_flags
& diff_flags
,
36794 cur_bumask
& diff_bumask
);
36802 /* Remember the last target of rs6000_set_current_function. */
36803 static GTY(()) tree rs6000_previous_fndecl
;
36805 /* Restore target's globals from NEW_TREE and invalidate the
36806 rs6000_previous_fndecl cache. */
36809 rs6000_activate_target_options (tree new_tree
)
36811 cl_target_option_restore (&global_options
, TREE_TARGET_OPTION (new_tree
));
36812 if (TREE_TARGET_GLOBALS (new_tree
))
36813 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
36814 else if (new_tree
== target_option_default_node
)
36815 restore_target_globals (&default_target_globals
);
36817 TREE_TARGET_GLOBALS (new_tree
) = save_target_globals_default_opts ();
36818 rs6000_previous_fndecl
= NULL_TREE
;
36821 /* Establish appropriate back-end context for processing the function
36822 FNDECL. The argument might be NULL to indicate processing at top
36823 level, outside of any function scope. */
36825 rs6000_set_current_function (tree fndecl
)
36827 if (TARGET_DEBUG_TARGET
)
36829 fprintf (stderr
, "\n==================== rs6000_set_current_function");
36832 fprintf (stderr
, ", fndecl %s (%p)",
36833 (DECL_NAME (fndecl
)
36834 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
36835 : "<unknown>"), (void *)fndecl
);
36837 if (rs6000_previous_fndecl
)
36838 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
36840 fprintf (stderr
, "\n");
36843 /* Only change the context if the function changes. This hook is called
36844 several times in the course of compiling a function, and we don't want to
36845 slow things down too much or call target_reinit when it isn't safe. */
36846 if (fndecl
== rs6000_previous_fndecl
)
36850 if (rs6000_previous_fndecl
== NULL_TREE
)
36851 old_tree
= target_option_current_node
;
36852 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
))
36853 old_tree
= DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
);
36855 old_tree
= target_option_default_node
;
36858 if (fndecl
== NULL_TREE
)
36860 if (old_tree
!= target_option_current_node
)
36861 new_tree
= target_option_current_node
;
36863 new_tree
= NULL_TREE
;
36867 new_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
36868 if (new_tree
== NULL_TREE
)
36869 new_tree
= target_option_default_node
;
36872 if (TARGET_DEBUG_TARGET
)
36876 fprintf (stderr
, "\nnew fndecl target specific options:\n");
36877 debug_tree (new_tree
);
36882 fprintf (stderr
, "\nold fndecl target specific options:\n");
36883 debug_tree (old_tree
);
36886 if (old_tree
!= NULL_TREE
|| new_tree
!= NULL_TREE
)
36887 fprintf (stderr
, "--------------------\n");
36890 if (new_tree
&& old_tree
!= new_tree
)
36891 rs6000_activate_target_options (new_tree
);
36894 rs6000_previous_fndecl
= fndecl
;
36898 /* Save the current options */
36901 rs6000_function_specific_save (struct cl_target_option
*ptr
,
36902 struct gcc_options
*opts
)
36904 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
36905 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
36908 /* Restore the current options */
36911 rs6000_function_specific_restore (struct gcc_options
*opts
,
36912 struct cl_target_option
*ptr
)
36915 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
36916 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
36917 (void) rs6000_option_override_internal (false);
36920 /* Print the current options */
36923 rs6000_function_specific_print (FILE *file
, int indent
,
36924 struct cl_target_option
*ptr
)
36926 rs6000_print_isa_options (file
, indent
, "Isa options set",
36927 ptr
->x_rs6000_isa_flags
);
36929 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
36930 ptr
->x_rs6000_isa_flags_explicit
);
36933 /* Helper function to print the current isa or misc options on a line. */
36936 rs6000_print_options_internal (FILE *file
,
36938 const char *string
,
36939 HOST_WIDE_INT flags
,
36940 const char *prefix
,
36941 const struct rs6000_opt_mask
*opts
,
36942 size_t num_elements
)
36945 size_t start_column
= 0;
36947 size_t max_column
= 120;
36948 size_t prefix_len
= strlen (prefix
);
36949 size_t comma_len
= 0;
36950 const char *comma
= "";
36953 start_column
+= fprintf (file
, "%*s", indent
, "");
36957 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
36961 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
36963 /* Print the various mask options. */
36964 cur_column
= start_column
;
36965 for (i
= 0; i
< num_elements
; i
++)
36967 bool invert
= opts
[i
].invert
;
36968 const char *name
= opts
[i
].name
;
36969 const char *no_str
= "";
36970 HOST_WIDE_INT mask
= opts
[i
].mask
;
36971 size_t len
= comma_len
+ prefix_len
+ strlen (name
);
36975 if ((flags
& mask
) == 0)
36978 len
+= sizeof ("no-") - 1;
36986 if ((flags
& mask
) != 0)
36989 len
+= sizeof ("no-") - 1;
36996 if (cur_column
> max_column
)
36998 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
36999 cur_column
= start_column
+ len
;
37003 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
, name
);
37005 comma_len
= sizeof (", ") - 1;
37008 fputs ("\n", file
);
37011 /* Helper function to print the current isa options on a line. */
37014 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
37015 HOST_WIDE_INT flags
)
37017 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
37018 &rs6000_opt_masks
[0],
37019 ARRAY_SIZE (rs6000_opt_masks
));
37023 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
37024 HOST_WIDE_INT flags
)
37026 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
37027 &rs6000_builtin_mask_names
[0],
37028 ARRAY_SIZE (rs6000_builtin_mask_names
));
37031 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37032 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37033 -mupper-regs-df, etc.).
37035 If the user used -mno-power8-vector, we need to turn off all of the implicit
37036 ISA 2.07 and 3.0 options that relate to the vector unit.
37038 If the user used -mno-power9-vector, we need to turn off all of the implicit
37039 ISA 3.0 options that relate to the vector unit.
37041 This function does not handle explicit options such as the user specifying
37042 -mdirect-move. These are handled in rs6000_option_override_internal, and
37043 the appropriate error is given if needed.
37045 We return a mask of all of the implicit options that should not be enabled
37048 static HOST_WIDE_INT
37049 rs6000_disable_incompatible_switches (void)
37051 HOST_WIDE_INT ignore_masks
= rs6000_isa_flags_explicit
;
37054 static const struct {
37055 const HOST_WIDE_INT no_flag
; /* flag explicitly turned off. */
37056 const HOST_WIDE_INT dep_flags
; /* flags that depend on this option. */
37057 const char *const name
; /* name of the switch. */
37059 { OPTION_MASK_P9_VECTOR
, OTHER_P9_VECTOR_MASKS
, "power9-vector" },
37060 { OPTION_MASK_P8_VECTOR
, OTHER_P8_VECTOR_MASKS
, "power8-vector" },
37061 { OPTION_MASK_VSX
, OTHER_VSX_VECTOR_MASKS
, "vsx" },
37064 for (i
= 0; i
< ARRAY_SIZE (flags
); i
++)
37066 HOST_WIDE_INT no_flag
= flags
[i
].no_flag
;
37068 if ((rs6000_isa_flags
& no_flag
) == 0
37069 && (rs6000_isa_flags_explicit
& no_flag
) != 0)
37071 HOST_WIDE_INT dep_flags
= flags
[i
].dep_flags
;
37072 HOST_WIDE_INT set_flags
= (rs6000_isa_flags_explicit
37078 for (j
= 0; j
< ARRAY_SIZE (rs6000_opt_masks
); j
++)
37079 if ((set_flags
& rs6000_opt_masks
[j
].mask
) != 0)
37081 set_flags
&= ~rs6000_opt_masks
[j
].mask
;
37082 error ("%<-mno-%s%> turns off %<-m%s%>",
37084 rs6000_opt_masks
[j
].name
);
37087 gcc_assert (!set_flags
);
37090 rs6000_isa_flags
&= ~dep_flags
;
37091 ignore_masks
|= no_flag
| dep_flags
;
37095 return ignore_masks
;
37099 /* Helper function for printing the function name when debugging. */
37101 static const char *
37102 get_decl_name (tree fn
)
37109 name
= DECL_NAME (fn
);
37111 return "<no-name>";
37113 return IDENTIFIER_POINTER (name
);
37116 /* Return the clone id of the target we are compiling code for in a target
37117 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37118 the priority list for the target clones (ordered from lowest to
37122 rs6000_clone_priority (tree fndecl
)
37124 tree fn_opts
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
37125 HOST_WIDE_INT isa_masks
;
37126 int ret
= CLONE_DEFAULT
;
37127 tree attrs
= lookup_attribute ("target", DECL_ATTRIBUTES (fndecl
));
37128 const char *attrs_str
= NULL
;
37130 attrs
= TREE_VALUE (TREE_VALUE (attrs
));
37131 attrs_str
= TREE_STRING_POINTER (attrs
);
37133 /* Return priority zero for default function. Return the ISA needed for the
37134 function if it is not the default. */
37135 if (strcmp (attrs_str
, "default") != 0)
37137 if (fn_opts
== NULL_TREE
)
37138 fn_opts
= target_option_default_node
;
37140 if (!fn_opts
|| !TREE_TARGET_OPTION (fn_opts
))
37141 isa_masks
= rs6000_isa_flags
;
37143 isa_masks
= TREE_TARGET_OPTION (fn_opts
)->x_rs6000_isa_flags
;
37145 for (ret
= CLONE_MAX
- 1; ret
!= 0; ret
--)
37146 if ((rs6000_clone_map
[ret
].isa_mask
& isa_masks
) != 0)
37150 if (TARGET_DEBUG_TARGET
)
37151 fprintf (stderr
, "rs6000_get_function_version_priority (%s) => %d\n",
37152 get_decl_name (fndecl
), ret
);
37157 /* This compares the priority of target features in function DECL1 and DECL2.
37158 It returns positive value if DECL1 is higher priority, negative value if
37159 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37160 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37163 rs6000_compare_version_priority (tree decl1
, tree decl2
)
37165 int priority1
= rs6000_clone_priority (decl1
);
37166 int priority2
= rs6000_clone_priority (decl2
);
37167 int ret
= priority1
- priority2
;
37169 if (TARGET_DEBUG_TARGET
)
37170 fprintf (stderr
, "rs6000_compare_version_priority (%s, %s) => %d\n",
37171 get_decl_name (decl1
), get_decl_name (decl2
), ret
);
37176 /* Make a dispatcher declaration for the multi-versioned function DECL.
37177 Calls to DECL function will be replaced with calls to the dispatcher
37178 by the front-end. Returns the decl of the dispatcher function. */
37181 rs6000_get_function_versions_dispatcher (void *decl
)
37183 tree fn
= (tree
) decl
;
37184 struct cgraph_node
*node
= NULL
;
37185 struct cgraph_node
*default_node
= NULL
;
37186 struct cgraph_function_version_info
*node_v
= NULL
;
37187 struct cgraph_function_version_info
*first_v
= NULL
;
37189 tree dispatch_decl
= NULL
;
37191 struct cgraph_function_version_info
*default_version_info
= NULL
;
37192 gcc_assert (fn
!= NULL
&& DECL_FUNCTION_VERSIONED (fn
));
37194 if (TARGET_DEBUG_TARGET
)
37195 fprintf (stderr
, "rs6000_get_function_versions_dispatcher (%s)\n",
37196 get_decl_name (fn
));
37198 node
= cgraph_node::get (fn
);
37199 gcc_assert (node
!= NULL
);
37201 node_v
= node
->function_version ();
37202 gcc_assert (node_v
!= NULL
);
37204 if (node_v
->dispatcher_resolver
!= NULL
)
37205 return node_v
->dispatcher_resolver
;
37207 /* Find the default version and make it the first node. */
37209 /* Go to the beginning of the chain. */
37210 while (first_v
->prev
!= NULL
)
37211 first_v
= first_v
->prev
;
37213 default_version_info
= first_v
;
37214 while (default_version_info
!= NULL
)
37216 const tree decl2
= default_version_info
->this_node
->decl
;
37217 if (is_function_default_version (decl2
))
37219 default_version_info
= default_version_info
->next
;
37222 /* If there is no default node, just return NULL. */
37223 if (default_version_info
== NULL
)
37226 /* Make default info the first node. */
37227 if (first_v
!= default_version_info
)
37229 default_version_info
->prev
->next
= default_version_info
->next
;
37230 if (default_version_info
->next
)
37231 default_version_info
->next
->prev
= default_version_info
->prev
;
37232 first_v
->prev
= default_version_info
;
37233 default_version_info
->next
= first_v
;
37234 default_version_info
->prev
= NULL
;
37237 default_node
= default_version_info
->this_node
;
37239 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37240 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
37241 "target_clones attribute needs GLIBC (2.23 and newer) that "
37242 "exports hardware capability bits");
37245 if (targetm
.has_ifunc_p ())
37247 struct cgraph_function_version_info
*it_v
= NULL
;
37248 struct cgraph_node
*dispatcher_node
= NULL
;
37249 struct cgraph_function_version_info
*dispatcher_version_info
= NULL
;
37251 /* Right now, the dispatching is done via ifunc. */
37252 dispatch_decl
= make_dispatcher_decl (default_node
->decl
);
37254 dispatcher_node
= cgraph_node::get_create (dispatch_decl
);
37255 gcc_assert (dispatcher_node
!= NULL
);
37256 dispatcher_node
->dispatcher_function
= 1;
37257 dispatcher_version_info
37258 = dispatcher_node
->insert_new_function_version ();
37259 dispatcher_version_info
->next
= default_version_info
;
37260 dispatcher_node
->definition
= 1;
37262 /* Set the dispatcher for all the versions. */
37263 it_v
= default_version_info
;
37264 while (it_v
!= NULL
)
37266 it_v
->dispatcher_resolver
= dispatch_decl
;
37272 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
37273 "multiversioning needs ifunc which is not supported "
37278 return dispatch_decl
;
37281 /* Make the resolver function decl to dispatch the versions of a multi-
37282 versioned function, DEFAULT_DECL. Create an empty basic block in the
37283 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37287 make_resolver_func (const tree default_decl
,
37288 const tree dispatch_decl
,
37289 basic_block
*empty_bb
)
37291 /* Make the resolver function static. The resolver function returns
37293 tree decl_name
= clone_function_name_numbered (default_decl
, "resolver");
37294 const char *resolver_name
= IDENTIFIER_POINTER (decl_name
);
37295 tree type
= build_function_type_list (ptr_type_node
, NULL_TREE
);
37296 tree decl
= build_fn_decl (resolver_name
, type
);
37297 SET_DECL_ASSEMBLER_NAME (decl
, decl_name
);
37299 DECL_NAME (decl
) = decl_name
;
37300 TREE_USED (decl
) = 1;
37301 DECL_ARTIFICIAL (decl
) = 1;
37302 DECL_IGNORED_P (decl
) = 0;
37303 TREE_PUBLIC (decl
) = 0;
37304 DECL_UNINLINABLE (decl
) = 1;
37306 /* Resolver is not external, body is generated. */
37307 DECL_EXTERNAL (decl
) = 0;
37308 DECL_EXTERNAL (dispatch_decl
) = 0;
37310 DECL_CONTEXT (decl
) = NULL_TREE
;
37311 DECL_INITIAL (decl
) = make_node (BLOCK
);
37312 DECL_STATIC_CONSTRUCTOR (decl
) = 0;
37314 /* Build result decl and add to function_decl. */
37315 tree t
= build_decl (UNKNOWN_LOCATION
, RESULT_DECL
, NULL_TREE
, ptr_type_node
);
37316 DECL_ARTIFICIAL (t
) = 1;
37317 DECL_IGNORED_P (t
) = 1;
37318 DECL_RESULT (decl
) = t
;
37320 gimplify_function_tree (decl
);
37321 push_cfun (DECL_STRUCT_FUNCTION (decl
));
37322 *empty_bb
= init_lowered_empty_function (decl
, false,
37323 profile_count::uninitialized ());
37325 cgraph_node::add_new_function (decl
, true);
37326 symtab
->call_cgraph_insertion_hooks (cgraph_node::get_create (decl
));
37330 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37331 DECL_ATTRIBUTES (dispatch_decl
)
37332 = make_attribute ("ifunc", resolver_name
, DECL_ATTRIBUTES (dispatch_decl
));
37334 cgraph_node::create_same_body_alias (dispatch_decl
, decl
);
37339 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37340 return a pointer to VERSION_DECL if we are running on a machine that
37341 supports the index CLONE_ISA hardware architecture bits. This function will
37342 be called during version dispatch to decide which function version to
37343 execute. It returns the basic block at the end, to which more conditions
37347 add_condition_to_bb (tree function_decl
, tree version_decl
,
37348 int clone_isa
, basic_block new_bb
)
37350 push_cfun (DECL_STRUCT_FUNCTION (function_decl
));
37352 gcc_assert (new_bb
!= NULL
);
37353 gimple_seq gseq
= bb_seq (new_bb
);
37356 tree convert_expr
= build1 (CONVERT_EXPR
, ptr_type_node
,
37357 build_fold_addr_expr (version_decl
));
37358 tree result_var
= create_tmp_var (ptr_type_node
);
37359 gimple
*convert_stmt
= gimple_build_assign (result_var
, convert_expr
);
37360 gimple
*return_stmt
= gimple_build_return (result_var
);
37362 if (clone_isa
== CLONE_DEFAULT
)
37364 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37365 gimple_seq_add_stmt (&gseq
, return_stmt
);
37366 set_bb_seq (new_bb
, gseq
);
37367 gimple_set_bb (convert_stmt
, new_bb
);
37368 gimple_set_bb (return_stmt
, new_bb
);
37373 tree bool_zero
= build_int_cst (bool_int_type_node
, 0);
37374 tree cond_var
= create_tmp_var (bool_int_type_node
);
37375 tree predicate_decl
= rs6000_builtin_decls
[(int) RS6000_BUILTIN_CPU_SUPPORTS
];
37376 const char *arg_str
= rs6000_clone_map
[clone_isa
].name
;
37377 tree predicate_arg
= build_string_literal (strlen (arg_str
) + 1, arg_str
);
37378 gimple
*call_cond_stmt
= gimple_build_call (predicate_decl
, 1, predicate_arg
);
37379 gimple_call_set_lhs (call_cond_stmt
, cond_var
);
37381 gimple_set_block (call_cond_stmt
, DECL_INITIAL (function_decl
));
37382 gimple_set_bb (call_cond_stmt
, new_bb
);
37383 gimple_seq_add_stmt (&gseq
, call_cond_stmt
);
37385 gimple
*if_else_stmt
= gimple_build_cond (NE_EXPR
, cond_var
, bool_zero
,
37386 NULL_TREE
, NULL_TREE
);
37387 gimple_set_block (if_else_stmt
, DECL_INITIAL (function_decl
));
37388 gimple_set_bb (if_else_stmt
, new_bb
);
37389 gimple_seq_add_stmt (&gseq
, if_else_stmt
);
37391 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37392 gimple_seq_add_stmt (&gseq
, return_stmt
);
37393 set_bb_seq (new_bb
, gseq
);
37395 basic_block bb1
= new_bb
;
37396 edge e12
= split_block (bb1
, if_else_stmt
);
37397 basic_block bb2
= e12
->dest
;
37398 e12
->flags
&= ~EDGE_FALLTHRU
;
37399 e12
->flags
|= EDGE_TRUE_VALUE
;
37401 edge e23
= split_block (bb2
, return_stmt
);
37402 gimple_set_bb (convert_stmt
, bb2
);
37403 gimple_set_bb (return_stmt
, bb2
);
37405 basic_block bb3
= e23
->dest
;
37406 make_edge (bb1
, bb3
, EDGE_FALSE_VALUE
);
37409 make_edge (bb2
, EXIT_BLOCK_PTR_FOR_FN (cfun
), 0);
37415 /* This function generates the dispatch function for multi-versioned functions.
37416 DISPATCH_DECL is the function which will contain the dispatch logic.
37417 FNDECLS are the function choices for dispatch, and is a tree chain.
37418 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37419 code is generated. */
37422 dispatch_function_versions (tree dispatch_decl
,
37424 basic_block
*empty_bb
)
37428 vec
<tree
> *fndecls
;
37429 tree clones
[CLONE_MAX
];
37431 if (TARGET_DEBUG_TARGET
)
37432 fputs ("dispatch_function_versions, top\n", stderr
);
37434 gcc_assert (dispatch_decl
!= NULL
37435 && fndecls_p
!= NULL
37436 && empty_bb
!= NULL
);
37438 /* fndecls_p is actually a vector. */
37439 fndecls
= static_cast<vec
<tree
> *> (fndecls_p
);
37441 /* At least one more version other than the default. */
37442 gcc_assert (fndecls
->length () >= 2);
37444 /* The first version in the vector is the default decl. */
37445 memset ((void *) clones
, '\0', sizeof (clones
));
37446 clones
[CLONE_DEFAULT
] = (*fndecls
)[0];
37448 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37449 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37450 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37451 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37452 to insert the code here to do the call. */
37454 for (ix
= 1; fndecls
->iterate (ix
, &ele
); ++ix
)
37456 int priority
= rs6000_clone_priority (ele
);
37457 if (!clones
[priority
])
37458 clones
[priority
] = ele
;
37461 for (ix
= CLONE_MAX
- 1; ix
>= 0; ix
--)
37464 if (TARGET_DEBUG_TARGET
)
37465 fprintf (stderr
, "dispatch_function_versions, clone %d, %s\n",
37466 ix
, get_decl_name (clones
[ix
]));
37468 *empty_bb
= add_condition_to_bb (dispatch_decl
, clones
[ix
], ix
,
37475 /* Generate the dispatching code body to dispatch multi-versioned function
37476 DECL. The target hook is called to process the "target" attributes and
37477 provide the code to dispatch the right function at run-time. NODE points
37478 to the dispatcher decl whose body will be created. */
37481 rs6000_generate_version_dispatcher_body (void *node_p
)
37484 basic_block empty_bb
;
37485 struct cgraph_node
*node
= (cgraph_node
*) node_p
;
37486 struct cgraph_function_version_info
*ninfo
= node
->function_version ();
37488 if (ninfo
->dispatcher_resolver
)
37489 return ninfo
->dispatcher_resolver
;
37491 /* node is going to be an alias, so remove the finalized bit. */
37492 node
->definition
= false;
37494 /* The first version in the chain corresponds to the default version. */
37495 ninfo
->dispatcher_resolver
= resolver
37496 = make_resolver_func (ninfo
->next
->this_node
->decl
, node
->decl
, &empty_bb
);
37498 if (TARGET_DEBUG_TARGET
)
37499 fprintf (stderr
, "rs6000_get_function_versions_dispatcher, %s\n",
37500 get_decl_name (resolver
));
37502 push_cfun (DECL_STRUCT_FUNCTION (resolver
));
37503 auto_vec
<tree
, 2> fn_ver_vec
;
37505 for (struct cgraph_function_version_info
*vinfo
= ninfo
->next
;
37507 vinfo
= vinfo
->next
)
37509 struct cgraph_node
*version
= vinfo
->this_node
;
37510 /* Check for virtual functions here again, as by this time it should
37511 have been determined if this function needs a vtable index or
37512 not. This happens for methods in derived classes that override
37513 virtual methods in base classes but are not explicitly marked as
37515 if (DECL_VINDEX (version
->decl
))
37516 sorry ("Virtual function multiversioning not supported");
37518 fn_ver_vec
.safe_push (version
->decl
);
37521 dispatch_function_versions (resolver
, &fn_ver_vec
, &empty_bb
);
37522 cgraph_edge::rebuild_edges ();
37528 /* Hook to determine if one function can safely inline another. */
37531 rs6000_can_inline_p (tree caller
, tree callee
)
37534 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
37535 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
37537 /* If callee has no option attributes, then it is ok to inline. */
37541 /* If caller has no option attributes, but callee does then it is not ok to
37543 else if (!caller_tree
)
37548 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
37549 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
37551 /* Callee's options should a subset of the caller's, i.e. a vsx function
37552 can inline an altivec function but a non-vsx function can't inline a
37554 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
37555 == callee_opts
->x_rs6000_isa_flags
)
37559 if (TARGET_DEBUG_TARGET
)
37560 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37561 get_decl_name (caller
), get_decl_name (callee
),
37562 (ret
? "can" : "cannot"));
37567 /* Allocate a stack temp and fixup the address so it meets the particular
37568 memory requirements (either offetable or REG+REG addressing). */
37571 rs6000_allocate_stack_temp (machine_mode mode
,
37572 bool offsettable_p
,
37575 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
37576 rtx addr
= XEXP (stack
, 0);
37577 int strict_p
= reload_completed
;
37579 if (!legitimate_indirect_address_p (addr
, strict_p
))
37582 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
37583 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37585 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
37586 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37592 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37593 convert to such a form to deal with memory reference instructions
37594 like STFIWX and LDBRX that only take reg+reg addressing. */
37597 rs6000_force_indexed_or_indirect_mem (rtx x
)
37599 machine_mode mode
= GET_MODE (x
);
37601 gcc_assert (MEM_P (x
));
37602 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x
, mode
))
37604 rtx addr
= XEXP (x
, 0);
37605 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
37607 rtx reg
= XEXP (addr
, 0);
37608 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
37609 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
37610 gcc_assert (REG_P (reg
));
37611 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
37614 else if (GET_CODE (addr
) == PRE_MODIFY
)
37616 rtx reg
= XEXP (addr
, 0);
37617 rtx expr
= XEXP (addr
, 1);
37618 gcc_assert (REG_P (reg
));
37619 gcc_assert (GET_CODE (expr
) == PLUS
);
37620 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
37624 x
= replace_equiv_address (x
, force_reg (Pmode
, addr
));
37630 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37632 On the RS/6000, all integer constants are acceptable, most won't be valid
37633 for particular insns, though. Only easy FP constants are acceptable. */
37636 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
37638 if (TARGET_ELF
&& tls_referenced_p (x
))
37641 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
37642 || GET_MODE (x
) == VOIDmode
37643 || (TARGET_POWERPC64
&& mode
== DImode
)
37644 || easy_fp_constant (x
, mode
)
37645 || easy_vector_constant (x
, mode
));
37649 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37652 chain_already_loaded (rtx_insn
*last
)
37654 for (; last
!= NULL
; last
= PREV_INSN (last
))
37656 if (NONJUMP_INSN_P (last
))
37658 rtx patt
= PATTERN (last
);
37660 if (GET_CODE (patt
) == SET
)
37662 rtx lhs
= XEXP (patt
, 0);
37664 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
37672 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37675 rs6000_call_aix (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
37677 rtx func
= func_desc
;
37678 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
37679 rtx toc_load
= NULL_RTX
;
37680 rtx toc_restore
= NULL_RTX
;
37682 rtx abi_reg
= NULL_RTX
;
37688 tlsarg
= global_tlsarg
;
37690 /* Handle longcall attributes. */
37691 if ((INTVAL (cookie
) & CALL_LONG
) != 0
37692 && GET_CODE (func_desc
) == SYMBOL_REF
)
37693 func
= rs6000_longcall_ref (func_desc
, tlsarg
);
37695 /* Handle indirect calls. */
37696 if (GET_CODE (func
) != SYMBOL_REF
37697 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func
)))
37699 /* Save the TOC into its reserved slot before the call,
37700 and prepare to restore it after the call. */
37701 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
37702 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
37703 gen_rtvec (1, stack_toc_offset
),
37705 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
37707 /* Can we optimize saving the TOC in the prologue or
37708 do we need to do it at every call? */
37709 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
37710 cfun
->machine
->save_toc_in_prologue
= true;
37713 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
37714 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
37715 gen_rtx_PLUS (Pmode
, stack_ptr
,
37716 stack_toc_offset
));
37717 MEM_VOLATILE_P (stack_toc_mem
) = 1;
37719 && TARGET_TLS_MARKERS
37720 && DEFAULT_ABI
== ABI_ELFv2
37721 && GET_CODE (func_desc
) == SYMBOL_REF
)
37723 rtvec v
= gen_rtvec (3, toc_reg
, func_desc
, tlsarg
);
37724 rtx mark_toc_reg
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37725 emit_insn (gen_rtx_SET (stack_toc_mem
, mark_toc_reg
));
37728 emit_move_insn (stack_toc_mem
, toc_reg
);
37731 if (DEFAULT_ABI
== ABI_ELFv2
)
37733 /* A function pointer in the ELFv2 ABI is just a plain address, but
37734 the ABI requires it to be loaded into r12 before the call. */
37735 func_addr
= gen_rtx_REG (Pmode
, 12);
37736 if (!rtx_equal_p (func_addr
, func
))
37737 emit_move_insn (func_addr
, func
);
37738 abi_reg
= func_addr
;
37739 /* Indirect calls via CTR are strongly preferred over indirect
37740 calls via LR, so move the address there. Needed to mark
37741 this insn for linker plt sequence editing too. */
37742 func_addr
= gen_rtx_REG (Pmode
, CTR_REGNO
);
37744 && TARGET_TLS_MARKERS
37745 && GET_CODE (func_desc
) == SYMBOL_REF
)
37747 rtvec v
= gen_rtvec (3, abi_reg
, func_desc
, tlsarg
);
37748 rtx mark_func
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37749 emit_insn (gen_rtx_SET (func_addr
, mark_func
));
37750 v
= gen_rtvec (2, func_addr
, func_desc
);
37751 func_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37754 emit_move_insn (func_addr
, abi_reg
);
37758 /* A function pointer under AIX is a pointer to a data area whose
37759 first word contains the actual address of the function, whose
37760 second word contains a pointer to its TOC, and whose third word
37761 contains a value to place in the static chain register (r11).
37762 Note that if we load the static chain, our "trampoline" need
37763 not have any executable code. */
37765 /* Load up address of the actual function. */
37766 func
= force_reg (Pmode
, func
);
37767 func_addr
= gen_reg_rtx (Pmode
);
37768 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func
));
37770 /* Indirect calls via CTR are strongly preferred over indirect
37771 calls via LR, so move the address there. */
37772 rtx ctr_reg
= gen_rtx_REG (Pmode
, CTR_REGNO
);
37773 emit_move_insn (ctr_reg
, func_addr
);
37774 func_addr
= ctr_reg
;
37776 /* Prepare to load the TOC of the called function. Note that the
37777 TOC load must happen immediately before the actual call so
37778 that unwinding the TOC registers works correctly. See the
37779 comment in frob_update_context. */
37780 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
37781 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
37782 gen_rtx_PLUS (Pmode
, func
,
37784 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
37786 /* If we have a static chain, load it up. But, if the call was
37787 originally direct, the 3rd word has not been written since no
37788 trampoline has been built, so we ought not to load it, lest we
37789 override a static chain value. */
37790 if (!(GET_CODE (func_desc
) == SYMBOL_REF
37791 && SYMBOL_REF_FUNCTION_P (func_desc
))
37792 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37793 && !chain_already_loaded (get_current_sequence ()->next
->last
))
37795 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
37796 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
37797 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
37798 gen_rtx_PLUS (Pmode
, func
,
37800 emit_move_insn (sc_reg
, func_sc_mem
);
37807 /* Direct calls use the TOC: for local calls, the callee will
37808 assume the TOC register is set; for non-local calls, the
37809 PLT stub needs the TOC register. */
37814 /* Create the call. */
37815 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), tlsarg
);
37816 if (value
!= NULL_RTX
)
37817 call
[0] = gen_rtx_SET (value
, call
[0]);
37821 call
[n_call
++] = toc_load
;
37823 call
[n_call
++] = toc_restore
;
37825 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
37827 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
37828 insn
= emit_call_insn (insn
);
37830 /* Mention all registers defined by the ABI to hold information
37831 as uses in CALL_INSN_FUNCTION_USAGE. */
37833 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
37836 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37839 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
37844 gcc_assert (INTVAL (cookie
) == 0);
37847 tlsarg
= global_tlsarg
;
37849 /* Create the call. */
37850 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), tlsarg
);
37851 if (value
!= NULL_RTX
)
37852 call
[0] = gen_rtx_SET (value
, call
[0]);
37854 call
[1] = simple_return_rtx
;
37856 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
37857 insn
= emit_call_insn (insn
);
37859 /* Note use of the TOC register. */
37860 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
37863 /* Expand code to perform a call under the SYSV4 ABI. */
37866 rs6000_call_sysv (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
37868 rtx func
= func_desc
;
37872 rtx abi_reg
= NULL_RTX
;
37875 tlsarg
= global_tlsarg
;
37877 /* Handle longcall attributes. */
37878 if ((INTVAL (cookie
) & CALL_LONG
) != 0
37879 && GET_CODE (func_desc
) == SYMBOL_REF
)
37881 func
= rs6000_longcall_ref (func_desc
, tlsarg
);
37882 /* If the longcall was implemented using PLT16 relocs, then r11
37883 needs to be valid at the call for lazy linking. */
37885 && TARGET_TLS_MARKERS
)
37889 /* Handle indirect calls. */
37890 if (GET_CODE (func
) != SYMBOL_REF
)
37892 func
= force_reg (Pmode
, func
);
37894 /* Indirect calls via CTR are strongly preferred over indirect
37895 calls via LR, so move the address there. Needed to mark
37896 this insn for linker plt sequence editing too. */
37897 func_addr
= gen_rtx_REG (Pmode
, CTR_REGNO
);
37899 && TARGET_TLS_MARKERS
37900 && GET_CODE (func_desc
) == SYMBOL_REF
)
37902 rtvec v
= gen_rtvec (3, func
, func_desc
, tlsarg
);
37903 rtx mark_func
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37904 emit_insn (gen_rtx_SET (func_addr
, mark_func
));
37905 v
= gen_rtvec (2, func_addr
, func_desc
);
37906 func_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37909 emit_move_insn (func_addr
, func
);
37914 /* Create the call. */
37915 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), tlsarg
);
37916 if (value
!= NULL_RTX
)
37917 call
[0] = gen_rtx_SET (value
, call
[0]);
37919 unsigned int mask
= CALL_V4_SET_FP_ARGS
| CALL_V4_CLEAR_FP_ARGS
;
37920 call
[1] = gen_rtx_USE (VOIDmode
, GEN_INT (INTVAL (cookie
) & mask
));
37922 call
[2] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
37924 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (3, call
));
37925 insn
= emit_call_insn (insn
);
37927 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
37930 /* Expand code to perform a sibling call under the SysV4 ABI. */
37933 rs6000_sibcall_sysv (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
37935 rtx func
= func_desc
;
37939 rtx abi_reg
= NULL_RTX
;
37942 tlsarg
= global_tlsarg
;
37944 /* Handle longcall attributes. */
37945 if ((INTVAL (cookie
) & CALL_LONG
) != 0
37946 && GET_CODE (func_desc
) == SYMBOL_REF
)
37948 func
= rs6000_longcall_ref (func_desc
, tlsarg
);
37949 /* If the longcall was implemented using PLT16 relocs, then r11
37950 needs to be valid at the call for lazy linking. */
37952 && TARGET_TLS_MARKERS
)
37956 /* Handle indirect calls. */
37957 if (GET_CODE (func
) != SYMBOL_REF
)
37959 func
= force_reg (Pmode
, func
);
37961 /* Indirect sibcalls must go via CTR. Needed to mark
37962 this insn for linker plt sequence editing too. */
37963 func_addr
= gen_rtx_REG (Pmode
, CTR_REGNO
);
37965 && TARGET_TLS_MARKERS
37966 && GET_CODE (func_desc
) == SYMBOL_REF
)
37968 rtvec v
= gen_rtvec (3, func
, func_desc
, tlsarg
);
37969 rtx mark_func
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37970 emit_insn (gen_rtx_SET (func_addr
, mark_func
));
37971 v
= gen_rtvec (2, func_addr
, func_desc
);
37972 func_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37975 emit_move_insn (func_addr
, func
);
37980 /* Create the call. */
37981 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), tlsarg
);
37982 if (value
!= NULL_RTX
)
37983 call
[0] = gen_rtx_SET (value
, call
[0]);
37985 unsigned int mask
= CALL_V4_SET_FP_ARGS
| CALL_V4_CLEAR_FP_ARGS
;
37986 call
[1] = gen_rtx_USE (VOIDmode
, GEN_INT (INTVAL (cookie
) & mask
));
37987 call
[2] = simple_return_rtx
;
37989 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (3, call
));
37990 insn
= emit_call_insn (insn
);
37992 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
37995 /* Return whether we need to always update the saved TOC pointer when we update
37996 the stack pointer. */
37999 rs6000_save_toc_in_prologue_p (void)
38001 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
38004 #ifdef HAVE_GAS_HIDDEN
38005 # define USE_HIDDEN_LINKONCE 1
38007 # define USE_HIDDEN_LINKONCE 0
38010 /* Fills in the label name that should be used for a 476 link stack thunk. */
38013 get_ppc476_thunk_name (char name
[32])
38015 gcc_assert (TARGET_LINK_STACK
);
38017 if (USE_HIDDEN_LINKONCE
)
38018 sprintf (name
, "__ppc476.get_thunk");
38020 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
38023 /* This function emits the simple thunk routine that is used to preserve
38024 the link stack on the 476 cpu. */
38026 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
38028 rs6000_code_end (void)
38033 if (!TARGET_LINK_STACK
)
38036 get_ppc476_thunk_name (name
);
38038 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
38039 build_function_type_list (void_type_node
, NULL_TREE
));
38040 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
38041 NULL_TREE
, void_type_node
);
38042 TREE_PUBLIC (decl
) = 1;
38043 TREE_STATIC (decl
) = 1;
38046 if (USE_HIDDEN_LINKONCE
&& !TARGET_XCOFF
)
38048 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
38049 targetm
.asm_out
.unique_section (decl
, 0);
38050 switch_to_section (get_named_section (decl
, NULL
, 0));
38051 DECL_WEAK (decl
) = 1;
38052 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
38053 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
38054 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
38055 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
38060 switch_to_section (text_section
);
38061 ASM_OUTPUT_LABEL (asm_out_file
, name
);
38064 DECL_INITIAL (decl
) = make_node (BLOCK
);
38065 current_function_decl
= decl
;
38066 allocate_struct_function (decl
, false);
38067 init_function_start (decl
);
38068 first_function_block_is_cold
= false;
38069 /* Make sure unwind info is emitted for the thunk if needed. */
38070 final_start_function (emit_barrier (), asm_out_file
, 1);
38072 fputs ("\tblr\n", asm_out_file
);
38074 final_end_function ();
38075 init_insn_lengths ();
38076 free_after_compilation (cfun
);
38078 current_function_decl
= NULL
;
38081 /* Add r30 to hard reg set if the prologue sets it up and it is not
38082 pic_offset_table_rtx. */
38085 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
38087 if (!TARGET_SINGLE_PIC_BASE
38089 && TARGET_MINIMAL_TOC
38090 && !constant_pool_empty_p ())
38091 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
38092 if (cfun
->machine
->split_stack_argp_used
)
38093 add_to_hard_reg_set (&set
->set
, Pmode
, 12);
38095 /* Make sure the hard reg set doesn't include r2, which was possibly added
38096 via PIC_OFFSET_TABLE_REGNUM. */
38098 remove_from_hard_reg_set (&set
->set
, Pmode
, TOC_REGNUM
);
38102 /* Helper function for rs6000_split_logical to emit a logical instruction after
38103 spliting the operation to single GPR registers.
38105 DEST is the destination register.
38106 OP1 and OP2 are the input source registers.
38107 CODE is the base operation (AND, IOR, XOR, NOT).
38108 MODE is the machine mode.
38109 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38110 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38111 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38114 rs6000_split_logical_inner (rtx dest
,
38117 enum rtx_code code
,
38119 bool complement_final_p
,
38120 bool complement_op1_p
,
38121 bool complement_op2_p
)
38125 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38126 if (op2
&& GET_CODE (op2
) == CONST_INT
38127 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
38128 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
38130 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
38131 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
38133 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38138 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
38142 else if (value
== mask
)
38144 if (!rtx_equal_p (dest
, op1
))
38145 emit_insn (gen_rtx_SET (dest
, op1
));
38150 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38151 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38152 else if (code
== IOR
|| code
== XOR
)
38156 if (!rtx_equal_p (dest
, op1
))
38157 emit_insn (gen_rtx_SET (dest
, op1
));
38163 if (code
== AND
&& mode
== SImode
38164 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
38166 emit_insn (gen_andsi3 (dest
, op1
, op2
));
38170 if (complement_op1_p
)
38171 op1
= gen_rtx_NOT (mode
, op1
);
38173 if (complement_op2_p
)
38174 op2
= gen_rtx_NOT (mode
, op2
);
38176 /* For canonical RTL, if only one arm is inverted it is the first. */
38177 if (!complement_op1_p
&& complement_op2_p
)
38178 std::swap (op1
, op2
);
38180 bool_rtx
= ((code
== NOT
)
38181 ? gen_rtx_NOT (mode
, op1
)
38182 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
38184 if (complement_final_p
)
38185 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
38187 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
38190 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38191 operations are split immediately during RTL generation to allow for more
38192 optimizations of the AND/IOR/XOR.
38194 OPERANDS is an array containing the destination and two input operands.
38195 CODE is the base operation (AND, IOR, XOR, NOT).
38196 MODE is the machine mode.
38197 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38198 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38199 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38200 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38201 formation of the AND instructions. */
38204 rs6000_split_logical_di (rtx operands
[3],
38205 enum rtx_code code
,
38206 bool complement_final_p
,
38207 bool complement_op1_p
,
38208 bool complement_op2_p
)
38210 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
38211 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
38212 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
38213 enum hi_lo
{ hi
= 0, lo
= 1 };
38214 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
38217 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
38218 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
38219 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
38220 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
38223 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
38226 if (GET_CODE (operands
[2]) != CONST_INT
)
38228 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
38229 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
38233 HOST_WIDE_INT value
= INTVAL (operands
[2]);
38234 HOST_WIDE_INT value_hi_lo
[2];
38236 gcc_assert (!complement_final_p
);
38237 gcc_assert (!complement_op1_p
);
38238 gcc_assert (!complement_op2_p
);
38240 value_hi_lo
[hi
] = value
>> 32;
38241 value_hi_lo
[lo
] = value
& lower_32bits
;
38243 for (i
= 0; i
< 2; i
++)
38245 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
38247 if (sub_value
& sign_bit
)
38248 sub_value
|= upper_32bits
;
38250 op2_hi_lo
[i
] = GEN_INT (sub_value
);
38252 /* If this is an AND instruction, check to see if we need to load
38253 the value in a register. */
38254 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
38255 && !and_operand (op2_hi_lo
[i
], SImode
))
38256 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
38261 for (i
= 0; i
< 2; i
++)
38263 /* Split large IOR/XOR operations. */
38264 if ((code
== IOR
|| code
== XOR
)
38265 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
38266 && !complement_final_p
38267 && !complement_op1_p
38268 && !complement_op2_p
38269 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
38271 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
38272 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
38273 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
38274 rtx tmp
= gen_reg_rtx (SImode
);
38276 /* Make sure the constant is sign extended. */
38277 if ((hi_16bits
& sign_bit
) != 0)
38278 hi_16bits
|= upper_32bits
;
38280 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
38281 code
, SImode
, false, false, false);
38283 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
38284 code
, SImode
, false, false, false);
38287 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
38288 code
, SImode
, complement_final_p
,
38289 complement_op1_p
, complement_op2_p
);
38295 /* Split the insns that make up boolean operations operating on multiple GPR
38296 registers. The boolean MD patterns ensure that the inputs either are
38297 exactly the same as the output registers, or there is no overlap.
38299 OPERANDS is an array containing the destination and two input operands.
38300 CODE is the base operation (AND, IOR, XOR, NOT).
38301 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38302 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38303 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38306 rs6000_split_logical (rtx operands
[3],
38307 enum rtx_code code
,
38308 bool complement_final_p
,
38309 bool complement_op1_p
,
38310 bool complement_op2_p
)
38312 machine_mode mode
= GET_MODE (operands
[0]);
38313 machine_mode sub_mode
;
38315 int sub_size
, regno0
, regno1
, nregs
, i
;
38317 /* If this is DImode, use the specialized version that can run before
38318 register allocation. */
38319 if (mode
== DImode
&& !TARGET_POWERPC64
)
38321 rs6000_split_logical_di (operands
, code
, complement_final_p
,
38322 complement_op1_p
, complement_op2_p
);
38328 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
38329 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
38330 sub_size
= GET_MODE_SIZE (sub_mode
);
38331 regno0
= REGNO (op0
);
38332 regno1
= REGNO (op1
);
38334 gcc_assert (reload_completed
);
38335 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38336 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38338 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
38339 gcc_assert (nregs
> 1);
38341 if (op2
&& REG_P (op2
))
38342 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38344 for (i
= 0; i
< nregs
; i
++)
38346 int offset
= i
* sub_size
;
38347 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
38348 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
38349 rtx sub_op2
= ((code
== NOT
)
38351 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
38353 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
38354 complement_final_p
, complement_op1_p
,
38362 /* Return true if the peephole2 can combine a load involving a combination of
38363 an addis instruction and a load with an offset that can be fused together on
38367 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
38368 rtx addis_value
, /* addis value. */
38369 rtx target
, /* target register that is loaded. */
38370 rtx mem
) /* bottom part of the memory addr. */
38375 /* Validate arguments. */
38376 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
38379 if (!base_reg_operand (target
, GET_MODE (target
)))
38382 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
38385 /* Allow sign/zero extension. */
38386 if (GET_CODE (mem
) == ZERO_EXTEND
38387 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
38388 mem
= XEXP (mem
, 0);
38393 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
38396 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
38397 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
38400 /* Validate that the register used to load the high value is either the
38401 register being loaded, or we can safely replace its use.
38403 This function is only called from the peephole2 pass and we assume that
38404 there are 2 instructions in the peephole (addis and load), so we want to
38405 check if the target register was not used in the memory address and the
38406 register to hold the addis result is dead after the peephole. */
38407 if (REGNO (addis_reg
) != REGNO (target
))
38409 if (reg_mentioned_p (target
, mem
))
38412 if (!peep2_reg_dead_p (2, addis_reg
))
38415 /* If the target register being loaded is the stack pointer, we must
38416 avoid loading any other value into it, even temporarily. */
38417 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
38421 base_reg
= XEXP (addr
, 0);
38422 return REGNO (addis_reg
) == REGNO (base_reg
);
38425 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38426 sequence. We adjust the addis register to use the target register. If the
38427 load sign extends, we adjust the code to do the zero extending load, and an
38428 explicit sign extension later since the fusion only covers zero extending
38432 operands[0] register set with addis (to be replaced with target)
38433 operands[1] value set via addis
38434 operands[2] target register being loaded
38435 operands[3] D-form memory reference using operands[0]. */
38438 expand_fusion_gpr_load (rtx
*operands
)
38440 rtx addis_value
= operands
[1];
38441 rtx target
= operands
[2];
38442 rtx orig_mem
= operands
[3];
38443 rtx new_addr
, new_mem
, orig_addr
, offset
;
38444 enum rtx_code plus_or_lo_sum
;
38445 machine_mode target_mode
= GET_MODE (target
);
38446 machine_mode extend_mode
= target_mode
;
38447 machine_mode ptr_mode
= Pmode
;
38448 enum rtx_code extend
= UNKNOWN
;
38450 if (GET_CODE (orig_mem
) == ZERO_EXTEND
38451 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
38453 extend
= GET_CODE (orig_mem
);
38454 orig_mem
= XEXP (orig_mem
, 0);
38455 target_mode
= GET_MODE (orig_mem
);
38458 gcc_assert (MEM_P (orig_mem
));
38460 orig_addr
= XEXP (orig_mem
, 0);
38461 plus_or_lo_sum
= GET_CODE (orig_addr
);
38462 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
38464 offset
= XEXP (orig_addr
, 1);
38465 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
38466 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
38468 if (extend
!= UNKNOWN
)
38469 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
38471 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
38472 UNSPEC_FUSION_GPR
);
38473 emit_insn (gen_rtx_SET (target
, new_mem
));
38475 if (extend
== SIGN_EXTEND
)
38477 int sub_off
= ((BYTES_BIG_ENDIAN
)
38478 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
38481 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
38483 emit_insn (gen_rtx_SET (target
,
38484 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
38490 /* Emit the addis instruction that will be part of a fused instruction
38494 emit_fusion_addis (rtx target
, rtx addis_value
)
38497 const char *addis_str
= NULL
;
38499 /* Emit the addis instruction. */
38500 fuse_ops
[0] = target
;
38501 if (satisfies_constraint_L (addis_value
))
38503 fuse_ops
[1] = addis_value
;
38504 addis_str
= "lis %0,%v1";
38507 else if (GET_CODE (addis_value
) == PLUS
)
38509 rtx op0
= XEXP (addis_value
, 0);
38510 rtx op1
= XEXP (addis_value
, 1);
38512 if (REG_P (op0
) && CONST_INT_P (op1
)
38513 && satisfies_constraint_L (op1
))
38517 addis_str
= "addis %0,%1,%v2";
38521 else if (GET_CODE (addis_value
) == HIGH
)
38523 rtx value
= XEXP (addis_value
, 0);
38524 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
38526 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
38527 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
38529 addis_str
= "addis %0,%2,%1@toc@ha";
38531 else if (TARGET_XCOFF
)
38532 addis_str
= "addis %0,%1@u(%2)";
38535 gcc_unreachable ();
38538 else if (GET_CODE (value
) == PLUS
)
38540 rtx op0
= XEXP (value
, 0);
38541 rtx op1
= XEXP (value
, 1);
38543 if (GET_CODE (op0
) == UNSPEC
38544 && XINT (op0
, 1) == UNSPEC_TOCREL
38545 && CONST_INT_P (op1
))
38547 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
38548 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
38551 addis_str
= "addis %0,%2,%1+%3@toc@ha";
38553 else if (TARGET_XCOFF
)
38554 addis_str
= "addis %0,%1+%3@u(%2)";
38557 gcc_unreachable ();
38561 else if (satisfies_constraint_L (value
))
38563 fuse_ops
[1] = value
;
38564 addis_str
= "lis %0,%v1";
38567 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
38569 fuse_ops
[1] = value
;
38570 addis_str
= "lis %0,%1@ha";
38575 fatal_insn ("Could not generate addis value for fusion", addis_value
);
38577 output_asm_insn (addis_str
, fuse_ops
);
38580 /* Emit a D-form load or store instruction that is the second instruction
38581 of a fusion sequence. */
38584 emit_fusion_load (rtx load_reg
, rtx addis_reg
, rtx offset
, const char *insn_str
)
38587 char insn_template
[80];
38589 fuse_ops
[0] = load_reg
;
38590 fuse_ops
[1] = addis_reg
;
38592 if (CONST_INT_P (offset
) && satisfies_constraint_I (offset
))
38594 sprintf (insn_template
, "%s %%0,%%2(%%1)", insn_str
);
38595 fuse_ops
[2] = offset
;
38596 output_asm_insn (insn_template
, fuse_ops
);
38599 else if (GET_CODE (offset
) == UNSPEC
38600 && XINT (offset
, 1) == UNSPEC_TOCREL
)
38603 sprintf (insn_template
, "%s %%0,%%2@toc@l(%%1)", insn_str
);
38605 else if (TARGET_XCOFF
)
38606 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
38609 gcc_unreachable ();
38611 fuse_ops
[2] = XVECEXP (offset
, 0, 0);
38612 output_asm_insn (insn_template
, fuse_ops
);
38615 else if (GET_CODE (offset
) == PLUS
38616 && GET_CODE (XEXP (offset
, 0)) == UNSPEC
38617 && XINT (XEXP (offset
, 0), 1) == UNSPEC_TOCREL
38618 && CONST_INT_P (XEXP (offset
, 1)))
38620 rtx tocrel_unspec
= XEXP (offset
, 0);
38622 sprintf (insn_template
, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str
);
38624 else if (TARGET_XCOFF
)
38625 sprintf (insn_template
, "%s %%0,%%2+%%3@l(%%1)", insn_str
);
38628 gcc_unreachable ();
38630 fuse_ops
[2] = XVECEXP (tocrel_unspec
, 0, 0);
38631 fuse_ops
[3] = XEXP (offset
, 1);
38632 output_asm_insn (insn_template
, fuse_ops
);
38635 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (offset
))
38637 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
38639 fuse_ops
[2] = offset
;
38640 output_asm_insn (insn_template
, fuse_ops
);
38644 fatal_insn ("Unable to generate load/store offset for fusion", offset
);
38649 /* Given an address, convert it into the addis and load offset parts. Addresses
38650 created during the peephole2 process look like:
38651 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38652 (unspec [(...)] UNSPEC_TOCREL)) */
38655 fusion_split_address (rtx addr
, rtx
*p_hi
, rtx
*p_lo
)
38659 if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
38661 hi
= XEXP (addr
, 0);
38662 lo
= XEXP (addr
, 1);
38665 gcc_unreachable ();
38671 /* Return a string to fuse an addis instruction with a gpr load to the same
38672 register that we loaded up the addis instruction. The address that is used
38673 is the logical address that was formed during peephole2:
38674 (lo_sum (high) (low-part))
38676 The code is complicated, so we call output_asm_insn directly, and just
38680 emit_fusion_gpr_load (rtx target
, rtx mem
)
38685 const char *load_str
= NULL
;
38688 if (GET_CODE (mem
) == ZERO_EXTEND
)
38689 mem
= XEXP (mem
, 0);
38691 gcc_assert (REG_P (target
) && MEM_P (mem
));
38693 addr
= XEXP (mem
, 0);
38694 fusion_split_address (addr
, &addis_value
, &load_offset
);
38696 /* Now emit the load instruction to the same register. */
38697 mode
= GET_MODE (mem
);
38715 gcc_assert (TARGET_POWERPC64
);
38720 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target
, mem
));
38723 /* Emit the addis instruction. */
38724 emit_fusion_addis (target
, addis_value
);
38726 /* Emit the D-form load instruction. */
38727 emit_fusion_load (target
, target
, load_offset
, load_str
);
38733 #ifdef RS6000_GLIBC_ATOMIC_FENV
38734 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38735 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
38738 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38741 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
38743 if (!TARGET_HARD_FLOAT
)
38745 #ifdef RS6000_GLIBC_ATOMIC_FENV
38746 if (atomic_hold_decl
== NULL_TREE
)
38749 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38750 get_identifier ("__atomic_feholdexcept"),
38751 build_function_type_list (void_type_node
,
38752 double_ptr_type_node
,
38754 TREE_PUBLIC (atomic_hold_decl
) = 1;
38755 DECL_EXTERNAL (atomic_hold_decl
) = 1;
38758 if (atomic_clear_decl
== NULL_TREE
)
38761 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38762 get_identifier ("__atomic_feclearexcept"),
38763 build_function_type_list (void_type_node
,
38765 TREE_PUBLIC (atomic_clear_decl
) = 1;
38766 DECL_EXTERNAL (atomic_clear_decl
) = 1;
38769 tree const_double
= build_qualified_type (double_type_node
,
38771 tree const_double_ptr
= build_pointer_type (const_double
);
38772 if (atomic_update_decl
== NULL_TREE
)
38775 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38776 get_identifier ("__atomic_feupdateenv"),
38777 build_function_type_list (void_type_node
,
38780 TREE_PUBLIC (atomic_update_decl
) = 1;
38781 DECL_EXTERNAL (atomic_update_decl
) = 1;
38784 tree fenv_var
= create_tmp_var_raw (double_type_node
);
38785 TREE_ADDRESSABLE (fenv_var
) = 1;
38786 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
38788 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
38789 *clear
= build_call_expr (atomic_clear_decl
, 0);
38790 *update
= build_call_expr (atomic_update_decl
, 1,
38791 fold_convert (const_double_ptr
, fenv_addr
));
38796 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
38797 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
38798 tree call_mffs
= build_call_expr (mffs
, 0);
38800 /* Generates the equivalent of feholdexcept (&fenv_var)
38802 *fenv_var = __builtin_mffs ();
38804 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38805 __builtin_mtfsf (0xff, fenv_hold); */
38807 /* Mask to clear everything except for the rounding modes and non-IEEE
38808 arithmetic flag. */
38809 const unsigned HOST_WIDE_INT hold_exception_mask
=
38810 HOST_WIDE_INT_C (0xffffffff00000007);
38812 tree fenv_var
= create_tmp_var_raw (double_type_node
);
38814 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
38816 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
38817 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
38818 build_int_cst (uint64_type_node
,
38819 hold_exception_mask
));
38821 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38824 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
38825 build_int_cst (unsigned_type_node
, 0xff),
38828 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
38830 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38832 double fenv_clear = __builtin_mffs ();
38833 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38834 __builtin_mtfsf (0xff, fenv_clear); */
38836 /* Mask to clear everything except for the rounding modes and non-IEEE
38837 arithmetic flag. */
38838 const unsigned HOST_WIDE_INT clear_exception_mask
=
38839 HOST_WIDE_INT_C (0xffffffff00000000);
38841 tree fenv_clear
= create_tmp_var_raw (double_type_node
);
38843 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
38845 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
38846 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
38848 build_int_cst (uint64_type_node
,
38849 clear_exception_mask
));
38851 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38852 fenv_clear_llu_and
);
38854 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
38855 build_int_cst (unsigned_type_node
, 0xff),
38858 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
38860 /* Generates the equivalent of feupdateenv (&fenv_var)
38862 double old_fenv = __builtin_mffs ();
38863 double fenv_update;
38864 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38865 (*(uint64_t*)fenv_var 0x1ff80fff);
38866 __builtin_mtfsf (0xff, fenv_update); */
38868 const unsigned HOST_WIDE_INT update_exception_mask
=
38869 HOST_WIDE_INT_C (0xffffffff1fffff00);
38870 const unsigned HOST_WIDE_INT new_exception_mask
=
38871 HOST_WIDE_INT_C (0x1ff80fff);
38873 tree old_fenv
= create_tmp_var_raw (double_type_node
);
38874 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
38876 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
38877 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
38878 build_int_cst (uint64_type_node
,
38879 update_exception_mask
));
38881 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
38882 build_int_cst (uint64_type_node
,
38883 new_exception_mask
));
38885 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
38886 old_llu_and
, new_llu_and
);
38888 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38891 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
38892 build_int_cst (unsigned_type_node
, 0xff),
38893 fenv_update_mtfsf
);
38895 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
38899 rs6000_generate_float2_double_code (rtx dst
, rtx src1
, rtx src2
)
38901 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
38903 rtx_tmp0
= gen_reg_rtx (V2DFmode
);
38904 rtx_tmp1
= gen_reg_rtx (V2DFmode
);
38906 /* The destination of the vmrgew instruction layout is:
38907 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38908 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38909 vmrgew instruction will be correct. */
38910 if (BYTES_BIG_ENDIAN
)
38912 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0
, src1
, src2
,
38914 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1
, src1
, src2
,
38919 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0
, src1
, src2
, GEN_INT (3)));
38920 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1
, src1
, src2
, GEN_INT (0)));
38923 rtx_tmp2
= gen_reg_rtx (V4SFmode
);
38924 rtx_tmp3
= gen_reg_rtx (V4SFmode
);
38926 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2
, rtx_tmp0
));
38927 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3
, rtx_tmp1
));
38929 if (BYTES_BIG_ENDIAN
)
38930 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp2
, rtx_tmp3
));
38932 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp3
, rtx_tmp2
));
38936 rs6000_generate_float2_code (bool signed_convert
, rtx dst
, rtx src1
, rtx src2
)
38938 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
38940 rtx_tmp0
= gen_reg_rtx (V2DImode
);
38941 rtx_tmp1
= gen_reg_rtx (V2DImode
);
38943 /* The destination of the vmrgew instruction layout is:
38944 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38945 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38946 vmrgew instruction will be correct. */
38947 if (BYTES_BIG_ENDIAN
)
38949 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
38950 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
38954 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0
, src1
, src2
, GEN_INT (3)));
38955 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1
, src1
, src2
, GEN_INT (0)));
38958 rtx_tmp2
= gen_reg_rtx (V4SFmode
);
38959 rtx_tmp3
= gen_reg_rtx (V4SFmode
);
38961 if (signed_convert
)
38963 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2
, rtx_tmp0
));
38964 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3
, rtx_tmp1
));
38968 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2
, rtx_tmp0
));
38969 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3
, rtx_tmp1
));
38972 if (BYTES_BIG_ENDIAN
)
38973 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp2
, rtx_tmp3
));
38975 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp3
, rtx_tmp2
));
38979 rs6000_generate_vsigned2_code (bool signed_convert
, rtx dst
, rtx src1
,
38982 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
38984 rtx_tmp0
= gen_reg_rtx (V2DFmode
);
38985 rtx_tmp1
= gen_reg_rtx (V2DFmode
);
38987 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
38988 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
38990 rtx_tmp2
= gen_reg_rtx (V4SImode
);
38991 rtx_tmp3
= gen_reg_rtx (V4SImode
);
38993 if (signed_convert
)
38995 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2
, rtx_tmp0
));
38996 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3
, rtx_tmp1
));
39000 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2
, rtx_tmp0
));
39001 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3
, rtx_tmp1
));
39004 emit_insn (gen_p8_vmrgew_v4si (dst
, rtx_tmp2
, rtx_tmp3
));
39007 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39010 rs6000_optab_supported_p (int op
, machine_mode mode1
, machine_mode
,
39011 optimization_type opt_type
)
39016 return (opt_type
== OPTIMIZE_FOR_SPEED
39017 && RS6000_RECIP_AUTO_RSQRTE_P (mode1
));
39024 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39026 static HOST_WIDE_INT
39027 rs6000_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
39029 if (TREE_CODE (exp
) == STRING_CST
39030 && (STRICT_ALIGNMENT
|| !optimize_size
))
39031 return MAX (align
, BITS_PER_WORD
);
39035 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39037 static HOST_WIDE_INT
39038 rs6000_starting_frame_offset (void)
39040 if (FRAME_GROWS_DOWNWARD
)
39042 return RS6000_STARTING_FRAME_OFFSET
;
39046 /* Create an alias for a mangled name where we have changed the mangling (in
39047 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
39048 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
39050 #if TARGET_ELF && RS6000_WEAK
39052 rs6000_globalize_decl_name (FILE * stream
, tree decl
)
39054 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
39056 targetm
.asm_out
.globalize_label (stream
, name
);
39058 if (rs6000_passes_ieee128
&& name
[0] == '_' && name
[1] == 'Z')
39060 tree save_asm_name
= DECL_ASSEMBLER_NAME (decl
);
39061 const char *old_name
;
39063 ieee128_mangling_gcc_8_1
= true;
39064 lang_hooks
.set_decl_assembler_name (decl
);
39065 old_name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
39066 SET_DECL_ASSEMBLER_NAME (decl
, save_asm_name
);
39067 ieee128_mangling_gcc_8_1
= false;
39069 if (strcmp (name
, old_name
) != 0)
39071 fprintf (stream
, "\t.weak %s\n", old_name
);
39072 fprintf (stream
, "\t.set %s,%s\n", old_name
, name
);
39079 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
39080 function names from <foo>l to <foo>f128 if the default long double type is
39081 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
39082 include file switches the names on systems that support long double as IEEE
39083 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
39084 In the future, glibc will export names like __ieee128_sinf128 and we can
39085 switch to using those instead of using sinf128, which pollutes the user's
39088 This will switch the names for Fortran math functions as well (which doesn't
39089 use math.h). However, Fortran needs other changes to the compiler and
39090 library before you can switch the real*16 type at compile time.
39092 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
39093 only do this if the default is that long double is IBM extended double, and
39094 the user asked for IEEE 128-bit. */
39097 rs6000_mangle_decl_assembler_name (tree decl
, tree id
)
39099 if (!TARGET_IEEEQUAD_DEFAULT
&& TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
39100 && TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_IS_BUILTIN (decl
) )
39102 size_t len
= IDENTIFIER_LENGTH (id
);
39103 const char *name
= IDENTIFIER_POINTER (id
);
39105 if (name
[len
- 1] == 'l')
39107 bool uses_ieee128_p
= false;
39108 tree type
= TREE_TYPE (decl
);
39109 machine_mode ret_mode
= TYPE_MODE (type
);
39111 /* See if the function returns a IEEE 128-bit floating point type or
39113 if (ret_mode
== TFmode
|| ret_mode
== TCmode
)
39114 uses_ieee128_p
= true;
39117 function_args_iterator args_iter
;
39120 /* See if the function passes a IEEE 128-bit floating point type
39121 or complex type. */
39122 FOREACH_FUNCTION_ARGS (type
, arg
, args_iter
)
39124 machine_mode arg_mode
= TYPE_MODE (arg
);
39125 if (arg_mode
== TFmode
|| arg_mode
== TCmode
)
39127 uses_ieee128_p
= true;
39133 /* If we passed or returned an IEEE 128-bit floating point type,
39134 change the name. */
39135 if (uses_ieee128_p
)
39137 char *name2
= (char *) alloca (len
+ 4);
39138 memcpy (name2
, name
, len
- 1);
39139 strcpy (name2
+ len
- 1, "f128");
39140 id
= get_identifier (name2
);
39149 struct gcc_target targetm
= TARGET_INITIALIZER
;
39151 #include "gt-rs6000.h"