1 @c Copyright (C) 2006 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
5 @c This file is generated automatically using gcc/config/arm/neon-docgen.ml
6 @c Please do not edit manually.
7 @subsubsection Addition
10 @item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
11 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
16 @item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
17 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
22 @item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
23 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
28 @item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
29 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
34 @item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
35 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
40 @item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
41 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
46 @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
47 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
52 @item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
53 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
58 @item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
59 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
64 @item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
65 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
70 @item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
71 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
76 @item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
77 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
82 @item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
83 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
88 @item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
89 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
94 @item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
95 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
100 @item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
101 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
106 @item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
107 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
112 @item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
113 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
118 @item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
119 @*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
124 @item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
125 @*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
130 @item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
131 @*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
136 @item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
137 @*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
142 @item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
143 @*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
148 @item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
149 @*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
154 @item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
155 @*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
160 @item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
161 @*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
166 @item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
167 @*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
172 @item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
173 @*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
178 @item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
179 @*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
184 @item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
185 @*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
190 @item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
191 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
196 @item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
197 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
202 @item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
203 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
208 @item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
209 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
214 @item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
215 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
220 @item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
221 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
226 @item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
227 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
232 @item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
233 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
238 @item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
239 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
244 @item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
245 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
250 @item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
251 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
256 @item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
257 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
262 @item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
263 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
268 @item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
269 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
274 @item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
275 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
280 @item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
281 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
286 @item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
287 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
292 @item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
293 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
298 @item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
299 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
304 @item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
305 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
310 @item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
311 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
316 @item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
317 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
322 @item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
323 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
328 @item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
329 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
334 @item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
335 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
340 @item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
341 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
346 @item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
347 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
352 @item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
353 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
358 @item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
359 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
364 @item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
365 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
370 @item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
371 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
376 @item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
377 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
382 @item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
383 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
388 @item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
389 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
394 @item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
395 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
400 @item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
401 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
406 @item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
407 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
412 @item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
413 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
418 @item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
419 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
424 @item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
425 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
430 @item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
431 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
436 @item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
437 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
442 @item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
443 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
448 @item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
449 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
454 @item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
455 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
460 @item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
461 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
466 @item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
467 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
472 @item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
473 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
478 @item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
479 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
484 @item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
485 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
490 @item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
491 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
496 @item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
497 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
503 @subsubsection Multiplication
506 @item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
507 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
512 @item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
513 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
518 @item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
519 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
524 @item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
525 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
530 @item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
531 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
536 @item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
537 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
542 @item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
543 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
548 @item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
549 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
554 @item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
555 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
560 @item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
561 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
566 @item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
567 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
572 @item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
573 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
578 @item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
579 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
584 @item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
585 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
590 @item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
591 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
596 @item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
597 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
602 @item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
603 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
608 @item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
609 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
614 @item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
615 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
620 @item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
621 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
626 @item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
627 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
632 @item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
633 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
638 @item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
639 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
644 @item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
645 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
650 @item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
651 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
656 @item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
657 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
662 @item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
663 @*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
668 @item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
669 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
674 @item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
675 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
680 @item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
681 @*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
686 @item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
687 @*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
692 @item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
693 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
698 @item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
699 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
705 @subsubsection Multiply-accumulate
708 @item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
709 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
714 @item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
715 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
720 @item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
721 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
726 @item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
727 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
732 @item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
733 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
738 @item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
739 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
744 @item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
745 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
750 @item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
751 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
756 @item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
757 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
762 @item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
763 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
768 @item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
769 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
774 @item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
775 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
780 @item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
781 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
786 @item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
787 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
792 @item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
793 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
798 @item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
799 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
804 @item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
805 @*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
810 @item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
811 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
816 @item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
817 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
822 @item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
823 @*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
828 @item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
829 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
834 @item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
835 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
841 @subsubsection Multiply-subtract
844 @item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
845 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
850 @item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
851 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
856 @item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
857 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
862 @item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
863 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
868 @item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
869 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
874 @item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
875 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
880 @item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
881 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
886 @item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
887 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
892 @item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
893 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
898 @item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
899 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
904 @item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
905 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
910 @item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
911 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
916 @item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
917 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
922 @item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
923 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
928 @item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
929 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
934 @item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
935 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
940 @item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
941 @*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
946 @item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
947 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
952 @item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
953 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
958 @item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
959 @*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
964 @item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
965 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
970 @item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
971 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
977 @subsubsection Subtraction
980 @item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
981 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
986 @item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
987 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
992 @item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
993 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
998 @item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
999 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1004 @item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
1005 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1010 @item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
1011 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1016 @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1017 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
1022 @item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1023 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
1028 @item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1029 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1034 @item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
1035 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1040 @item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
1041 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1046 @item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
1047 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1052 @item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
1053 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1058 @item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
1059 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1064 @item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
1065 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1070 @item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
1071 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1076 @item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
1077 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1082 @item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
1083 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
1088 @item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
1089 @*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
1094 @item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
1095 @*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
1100 @item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
1101 @*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
1106 @item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
1107 @*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
1112 @item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
1113 @*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
1118 @item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
1119 @*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
1124 @item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
1125 @*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
1130 @item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
1131 @*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
1136 @item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
1137 @*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
1142 @item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
1143 @*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
1148 @item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
1149 @*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
1154 @item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
1155 @*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
1160 @item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
1161 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
1166 @item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
1167 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
1172 @item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
1173 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
1178 @item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
1179 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
1184 @item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
1185 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
1190 @item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
1191 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
1196 @item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
1197 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
1202 @item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
1203 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
1208 @item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
1209 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
1214 @item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
1215 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
1220 @item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
1221 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
1226 @item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
1227 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
1232 @item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
1233 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
1238 @item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
1239 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
1244 @item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
1245 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
1250 @item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
1251 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
1256 @item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
1257 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
1262 @item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
1263 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
1268 @item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
1269 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
1274 @item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
1275 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
1280 @item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
1281 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
1286 @item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
1287 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
1292 @item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
1293 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
1298 @item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
1299 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
1304 @item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
1305 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
1310 @item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
1311 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
1316 @item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
1317 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
1322 @item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
1323 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
1328 @item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
1329 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1334 @item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
1335 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1340 @item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
1341 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1346 @item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
1347 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1352 @item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
1353 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1358 @item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
1359 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1364 @item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
1365 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1370 @item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
1371 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1376 @item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
1377 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1382 @item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
1383 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1388 @item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
1389 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1394 @item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
1395 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1401 @subsubsection Comparison (equal-to)
1404 @item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
1405 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1410 @item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
1411 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1416 @item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
1417 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1422 @item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
1423 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1428 @item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
1429 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1434 @item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
1435 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1440 @item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
1441 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
1446 @item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
1447 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1452 @item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
1453 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1458 @item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
1459 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1464 @item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
1465 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1470 @item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
1471 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1476 @item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
1477 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1482 @item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
1483 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1488 @item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
1489 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
1494 @item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
1495 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1501 @subsubsection Comparison (greater-than-or-equal-to)
1504 @item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
1505 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1510 @item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
1511 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1516 @item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
1517 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1522 @item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
1523 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1528 @item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
1529 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1534 @item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
1535 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1540 @item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
1541 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1546 @item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
1547 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1552 @item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
1553 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1558 @item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
1559 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1564 @item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
1565 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1570 @item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
1571 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1576 @item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
1577 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1582 @item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
1583 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1589 @subsubsection Comparison (less-than-or-equal-to)
1592 @item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
1593 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1598 @item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
1599 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1604 @item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
1605 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1610 @item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
1611 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1616 @item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
1617 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1622 @item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
1623 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1628 @item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
1629 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1634 @item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
1635 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1640 @item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
1641 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1646 @item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
1647 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1652 @item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
1653 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1658 @item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
1659 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1664 @item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
1665 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1670 @item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
1671 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1677 @subsubsection Comparison (greater-than)
1680 @item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
1681 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1686 @item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
1687 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1692 @item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
1693 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1698 @item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
1699 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1704 @item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
1705 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1710 @item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
1711 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1716 @item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
1717 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1722 @item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
1723 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1728 @item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
1729 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1734 @item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
1735 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1740 @item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
1741 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1746 @item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
1747 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1752 @item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
1753 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1758 @item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
1759 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1765 @subsubsection Comparison (less-than)
1768 @item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
1769 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1774 @item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
1775 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1780 @item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
1781 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1786 @item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
1787 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1792 @item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
1793 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1798 @item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
1799 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1804 @item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
1805 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1810 @item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
1811 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1816 @item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
1817 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1822 @item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
1823 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1828 @item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
1829 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1834 @item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
1835 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1840 @item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
1841 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1846 @item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
1847 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1853 @subsubsection Comparison (absolute greater-than-or-equal-to)
1856 @item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
1857 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1862 @item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
1863 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1869 @subsubsection Comparison (absolute less-than-or-equal-to)
1872 @item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
1873 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1878 @item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
1879 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1885 @subsubsection Comparison (absolute greater-than)
1888 @item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
1889 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1894 @item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
1895 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1901 @subsubsection Comparison (absolute less-than)
1904 @item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
1905 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1910 @item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
1911 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1917 @subsubsection Test bits
1920 @item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
1921 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1926 @item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
1927 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1932 @item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
1933 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1938 @item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
1939 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1944 @item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
1945 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1950 @item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
1951 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1956 @item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
1957 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1962 @item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
1963 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1968 @item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
1969 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1974 @item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
1975 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1980 @item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
1981 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1986 @item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
1987 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1992 @item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
1993 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1998 @item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
1999 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2005 @subsubsection Absolute difference
2008 @item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
2009 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
2014 @item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
2015 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
2020 @item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
2021 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
2026 @item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
2027 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
2032 @item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
2033 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
2038 @item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
2039 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
2044 @item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
2045 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
2050 @item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
2051 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
2056 @item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
2057 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
2062 @item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
2063 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
2068 @item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
2069 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
2074 @item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
2075 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
2080 @item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
2081 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
2086 @item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
2087 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
2092 @item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
2093 @*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
2098 @item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
2099 @*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
2104 @item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
2105 @*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
2110 @item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
2111 @*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
2116 @item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
2117 @*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
2122 @item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
2123 @*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
2129 @subsubsection Absolute difference and accumulate
2132 @item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
2133 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
2138 @item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
2139 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
2144 @item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
2145 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
2150 @item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
2151 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
2156 @item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
2157 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
2162 @item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
2163 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
2168 @item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2169 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
2174 @item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
2175 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
2180 @item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
2181 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
2186 @item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
2187 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
2192 @item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
2193 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
2198 @item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
2199 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
2204 @item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
2205 @*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
2210 @item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
2211 @*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
2216 @item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
2217 @*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
2222 @item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
2223 @*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
2228 @item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
2229 @*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
2234 @item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
2235 @*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
2241 @subsubsection Maximum
2244 @item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
2245 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
2250 @item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
2251 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
2256 @item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
2257 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
2262 @item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
2263 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
2268 @item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
2269 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
2274 @item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
2275 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
2280 @item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
2281 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
2286 @item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
2287 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
2292 @item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
2293 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
2298 @item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
2299 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
2304 @item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
2305 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
2310 @item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
2311 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
2316 @item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
2317 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
2322 @item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
2323 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
2329 @subsubsection Minimum
2332 @item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
2333 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
2338 @item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
2339 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
2344 @item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
2345 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
2350 @item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
2351 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
2356 @item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
2357 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
2362 @item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
2363 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
2368 @item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
2369 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
2374 @item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
2375 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
2380 @item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
2381 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
2386 @item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
2387 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
2392 @item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
2393 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
2398 @item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
2399 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
2404 @item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
2405 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
2410 @item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
2411 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
2417 @subsubsection Pairwise add
2420 @item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
2421 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2426 @item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
2427 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2432 @item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
2433 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2438 @item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
2439 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2444 @item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
2445 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2450 @item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
2451 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2456 @item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
2457 @*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
2462 @item uint64x1_t vpaddl_u32 (uint32x2_t)
2463 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
2468 @item uint32x2_t vpaddl_u16 (uint16x4_t)
2469 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
2474 @item uint16x4_t vpaddl_u8 (uint8x8_t)
2475 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
2480 @item int64x1_t vpaddl_s32 (int32x2_t)
2481 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
2486 @item int32x2_t vpaddl_s16 (int16x4_t)
2487 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
2492 @item int16x4_t vpaddl_s8 (int8x8_t)
2493 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
2498 @item uint64x2_t vpaddlq_u32 (uint32x4_t)
2499 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
2504 @item uint32x4_t vpaddlq_u16 (uint16x8_t)
2505 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
2510 @item uint16x8_t vpaddlq_u8 (uint8x16_t)
2511 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
2516 @item int64x2_t vpaddlq_s32 (int32x4_t)
2517 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
2522 @item int32x4_t vpaddlq_s16 (int16x8_t)
2523 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
2528 @item int16x8_t vpaddlq_s8 (int8x16_t)
2529 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
2535 @subsubsection Pairwise add, single_opcode widen and accumulate
2538 @item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
2539 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
2544 @item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
2545 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
2550 @item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
2551 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
2556 @item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
2557 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
2562 @item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
2563 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
2568 @item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
2569 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
2574 @item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
2575 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
2580 @item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
2581 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
2586 @item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
2587 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
2592 @item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
2593 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
2598 @item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
2599 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
2604 @item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
2605 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
2611 @subsubsection Folding maximum
2614 @item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
2615 @*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
2620 @item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
2621 @*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
2626 @item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
2627 @*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
2632 @item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
2633 @*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
2638 @item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
2639 @*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
2644 @item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
2645 @*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
2650 @item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
2651 @*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
2657 @subsubsection Folding minimum
2660 @item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
2661 @*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
2666 @item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
2667 @*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
2672 @item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
2673 @*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
2678 @item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
2679 @*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
2684 @item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
2685 @*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
2690 @item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
2691 @*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
2696 @item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
2697 @*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
2703 @subsubsection Reciprocal step
2706 @item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
2707 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
2712 @item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
2713 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
2718 @item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
2719 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
2724 @item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
2725 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
2731 @subsubsection Vector shift left
2734 @item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
2735 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
2740 @item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
2741 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
2746 @item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
2747 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
2752 @item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
2753 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
2758 @item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
2759 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
2764 @item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
2765 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
2770 @item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
2771 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
2776 @item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
2777 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
2782 @item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
2783 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
2788 @item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
2789 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
2794 @item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
2795 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
2800 @item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
2801 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
2806 @item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
2807 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
2812 @item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
2813 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
2818 @item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
2819 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
2824 @item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
2825 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
2830 @item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
2831 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
2836 @item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
2837 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
2842 @item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
2843 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
2848 @item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
2849 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
2854 @item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
2855 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
2860 @item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
2861 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
2866 @item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
2867 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
2872 @item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
2873 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
2878 @item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
2879 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
2884 @item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
2885 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
2890 @item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
2891 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
2896 @item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
2897 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
2902 @item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
2903 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
2908 @item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
2909 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
2914 @item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
2915 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
2920 @item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
2921 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
2926 @item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
2927 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
2932 @item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
2933 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
2938 @item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
2939 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
2944 @item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
2945 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
2950 @item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
2951 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
2956 @item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
2957 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
2962 @item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
2963 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
2968 @item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
2969 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
2974 @item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
2975 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
2980 @item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
2981 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
2986 @item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
2987 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
2992 @item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
2993 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
2998 @item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
2999 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
3004 @item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
3005 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
3010 @item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
3011 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
3016 @item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
3017 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
3022 @item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
3023 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
3028 @item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
3029 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
3034 @item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
3035 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
3040 @item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
3041 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
3046 @item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
3047 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
3052 @item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
3053 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
3058 @item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
3059 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
3064 @item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
3065 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
3070 @item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
3071 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
3076 @item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
3077 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
3082 @item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
3083 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3088 @item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
3089 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3094 @item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
3095 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3100 @item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
3101 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3106 @item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
3107 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3112 @item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
3113 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3119 @subsubsection Vector shift left by constant
3122 @item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
3123 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3128 @item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
3129 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3134 @item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
3135 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3140 @item int32x2_t vshl_n_s32 (int32x2_t, const int)
3141 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3146 @item int16x4_t vshl_n_s16 (int16x4_t, const int)
3147 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3152 @item int8x8_t vshl_n_s8 (int8x8_t, const int)
3153 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3158 @item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
3159 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3164 @item int64x1_t vshl_n_s64 (int64x1_t, const int)
3165 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3170 @item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
3171 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3176 @item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
3177 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3182 @item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
3183 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3188 @item int32x4_t vshlq_n_s32 (int32x4_t, const int)
3189 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3194 @item int16x8_t vshlq_n_s16 (int16x8_t, const int)
3195 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3200 @item int8x16_t vshlq_n_s8 (int8x16_t, const int)
3201 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3206 @item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
3207 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3212 @item int64x2_t vshlq_n_s64 (int64x2_t, const int)
3213 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3218 @item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
3219 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
3224 @item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
3225 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
3230 @item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
3231 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
3236 @item int32x2_t vqshl_n_s32 (int32x2_t, const int)
3237 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
3242 @item int16x4_t vqshl_n_s16 (int16x4_t, const int)
3243 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
3248 @item int8x8_t vqshl_n_s8 (int8x8_t, const int)
3249 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
3254 @item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
3255 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
3260 @item int64x1_t vqshl_n_s64 (int64x1_t, const int)
3261 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
3266 @item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
3267 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
3272 @item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
3273 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
3278 @item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
3279 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
3284 @item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
3285 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
3290 @item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
3291 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
3296 @item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
3297 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
3302 @item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
3303 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
3308 @item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
3309 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
3314 @item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
3315 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
3320 @item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
3321 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
3326 @item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
3327 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
3332 @item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
3333 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
3338 @item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
3339 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
3344 @item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
3345 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
3350 @item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
3351 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
3356 @item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
3357 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
3362 @item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
3363 @*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
3368 @item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
3369 @*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
3374 @item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
3375 @*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
3380 @item int64x2_t vshll_n_s32 (int32x2_t, const int)
3381 @*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
3386 @item int32x4_t vshll_n_s16 (int16x4_t, const int)
3387 @*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
3392 @item int16x8_t vshll_n_s8 (int8x8_t, const int)
3393 @*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
3399 @subsubsection Vector shift right by constant
3402 @item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
3403 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
3408 @item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
3409 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
3414 @item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
3415 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
3420 @item int32x2_t vshr_n_s32 (int32x2_t, const int)
3421 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
3426 @item int16x4_t vshr_n_s16 (int16x4_t, const int)
3427 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
3432 @item int8x8_t vshr_n_s8 (int8x8_t, const int)
3433 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
3438 @item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
3439 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
3444 @item int64x1_t vshr_n_s64 (int64x1_t, const int)
3445 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
3450 @item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
3451 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
3456 @item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
3457 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
3462 @item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
3463 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
3468 @item int32x4_t vshrq_n_s32 (int32x4_t, const int)
3469 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
3474 @item int16x8_t vshrq_n_s16 (int16x8_t, const int)
3475 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
3480 @item int8x16_t vshrq_n_s8 (int8x16_t, const int)
3481 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
3486 @item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
3487 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
3492 @item int64x2_t vshrq_n_s64 (int64x2_t, const int)
3493 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
3498 @item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
3499 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
3504 @item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
3505 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
3510 @item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
3511 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
3516 @item int32x2_t vrshr_n_s32 (int32x2_t, const int)
3517 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
3522 @item int16x4_t vrshr_n_s16 (int16x4_t, const int)
3523 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
3528 @item int8x8_t vrshr_n_s8 (int8x8_t, const int)
3529 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
3534 @item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
3535 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
3540 @item int64x1_t vrshr_n_s64 (int64x1_t, const int)
3541 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
3546 @item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
3547 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
3552 @item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
3553 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
3558 @item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
3559 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
3564 @item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
3565 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
3570 @item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
3571 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
3576 @item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
3577 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
3582 @item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
3583 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
3588 @item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
3589 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
3594 @item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
3595 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3600 @item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
3601 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3606 @item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
3607 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3612 @item int32x2_t vshrn_n_s64 (int64x2_t, const int)
3613 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3618 @item int16x4_t vshrn_n_s32 (int32x4_t, const int)
3619 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3624 @item int8x8_t vshrn_n_s16 (int16x8_t, const int)
3625 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3630 @item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
3631 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3636 @item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
3637 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3642 @item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
3643 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3648 @item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
3649 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3654 @item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
3655 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3660 @item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
3661 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3666 @item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
3667 @*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3672 @item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
3673 @*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3678 @item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
3679 @*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3684 @item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
3685 @*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3690 @item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
3691 @*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3696 @item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
3697 @*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3702 @item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
3703 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3708 @item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
3709 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3714 @item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
3715 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3720 @item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
3721 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3726 @item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
3727 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3732 @item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
3733 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3738 @item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
3739 @*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3744 @item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
3745 @*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3750 @item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
3751 @*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3756 @item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
3757 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3762 @item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
3763 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3768 @item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
3769 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3775 @subsubsection Vector shift right by constant and accumulate
3778 @item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3779 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
3784 @item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3785 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
3790 @item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3791 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
3796 @item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
3797 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
3802 @item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
3803 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
3808 @item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
3809 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
3814 @item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3815 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
3820 @item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
3821 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
3826 @item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3827 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
3832 @item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3833 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
3838 @item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3839 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
3844 @item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
3845 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
3850 @item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
3851 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
3856 @item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
3857 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
3862 @item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3863 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
3868 @item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
3869 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
3874 @item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3875 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
3880 @item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3881 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
3886 @item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3887 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
3892 @item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
3893 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
3898 @item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
3899 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
3904 @item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
3905 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
3910 @item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3911 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
3916 @item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
3917 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
3922 @item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3923 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
3928 @item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3929 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
3934 @item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3935 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
3940 @item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
3941 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
3946 @item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
3947 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
3952 @item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
3953 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
3958 @item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3959 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
3964 @item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
3965 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
3971 @subsubsection Vector shift right and insert
3974 @item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
3975 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3980 @item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
3981 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
3986 @item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
3987 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
3992 @item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
3993 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3998 @item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
3999 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4004 @item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
4005 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4010 @item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
4011 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4016 @item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
4017 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4022 @item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
4023 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4028 @item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
4029 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4034 @item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
4035 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4040 @item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
4041 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4046 @item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
4047 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4052 @item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
4053 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4058 @item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
4059 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4064 @item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
4065 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4070 @item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
4071 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4076 @item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
4077 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4082 @item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
4083 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4088 @item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
4089 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4095 @subsubsection Vector shift left and insert
4098 @item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
4099 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4104 @item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
4105 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4110 @item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
4111 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4116 @item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
4117 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4122 @item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
4123 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4128 @item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
4129 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4134 @item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
4135 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4140 @item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
4141 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4146 @item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
4147 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4152 @item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
4153 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4158 @item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
4159 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4164 @item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
4165 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4170 @item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
4171 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4176 @item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
4177 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4182 @item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
4183 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4188 @item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
4189 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4194 @item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
4195 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4200 @item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
4201 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4206 @item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
4207 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4212 @item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
4213 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4219 @subsubsection Absolute value
4222 @item float32x2_t vabs_f32 (float32x2_t)
4223 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
4228 @item int32x2_t vabs_s32 (int32x2_t)
4229 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
4234 @item int16x4_t vabs_s16 (int16x4_t)
4235 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
4240 @item int8x8_t vabs_s8 (int8x8_t)
4241 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
4246 @item float32x4_t vabsq_f32 (float32x4_t)
4247 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
4252 @item int32x4_t vabsq_s32 (int32x4_t)
4253 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
4258 @item int16x8_t vabsq_s16 (int16x8_t)
4259 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
4264 @item int8x16_t vabsq_s8 (int8x16_t)
4265 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
4270 @item int32x2_t vqabs_s32 (int32x2_t)
4271 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
4276 @item int16x4_t vqabs_s16 (int16x4_t)
4277 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
4282 @item int8x8_t vqabs_s8 (int8x8_t)
4283 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
4288 @item int32x4_t vqabsq_s32 (int32x4_t)
4289 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
4294 @item int16x8_t vqabsq_s16 (int16x8_t)
4295 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
4300 @item int8x16_t vqabsq_s8 (int8x16_t)
4301 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
4307 @subsubsection Negation
4310 @item float32x2_t vneg_f32 (float32x2_t)
4311 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
4316 @item int32x2_t vneg_s32 (int32x2_t)
4317 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
4322 @item int16x4_t vneg_s16 (int16x4_t)
4323 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
4328 @item int8x8_t vneg_s8 (int8x8_t)
4329 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
4334 @item float32x4_t vnegq_f32 (float32x4_t)
4335 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
4340 @item int32x4_t vnegq_s32 (int32x4_t)
4341 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
4346 @item int16x8_t vnegq_s16 (int16x8_t)
4347 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
4352 @item int8x16_t vnegq_s8 (int8x16_t)
4353 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
4358 @item int32x2_t vqneg_s32 (int32x2_t)
4359 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
4364 @item int16x4_t vqneg_s16 (int16x4_t)
4365 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
4370 @item int8x8_t vqneg_s8 (int8x8_t)
4371 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
4376 @item int32x4_t vqnegq_s32 (int32x4_t)
4377 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
4382 @item int16x8_t vqnegq_s16 (int16x8_t)
4383 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
4388 @item int8x16_t vqnegq_s8 (int8x16_t)
4389 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
4395 @subsubsection Bitwise not
4398 @item uint32x2_t vmvn_u32 (uint32x2_t)
4399 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4404 @item uint16x4_t vmvn_u16 (uint16x4_t)
4405 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4410 @item uint8x8_t vmvn_u8 (uint8x8_t)
4411 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4416 @item int32x2_t vmvn_s32 (int32x2_t)
4417 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4422 @item int16x4_t vmvn_s16 (int16x4_t)
4423 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4428 @item int8x8_t vmvn_s8 (int8x8_t)
4429 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4434 @item poly8x8_t vmvn_p8 (poly8x8_t)
4435 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4440 @item uint32x4_t vmvnq_u32 (uint32x4_t)
4441 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4446 @item uint16x8_t vmvnq_u16 (uint16x8_t)
4447 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4452 @item uint8x16_t vmvnq_u8 (uint8x16_t)
4453 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4458 @item int32x4_t vmvnq_s32 (int32x4_t)
4459 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4464 @item int16x8_t vmvnq_s16 (int16x8_t)
4465 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4470 @item int8x16_t vmvnq_s8 (int8x16_t)
4471 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4476 @item poly8x16_t vmvnq_p8 (poly8x16_t)
4477 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4483 @subsubsection Count leading sign bits
4486 @item int32x2_t vcls_s32 (int32x2_t)
4487 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
4492 @item int16x4_t vcls_s16 (int16x4_t)
4493 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
4498 @item int8x8_t vcls_s8 (int8x8_t)
4499 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
4504 @item int32x4_t vclsq_s32 (int32x4_t)
4505 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
4510 @item int16x8_t vclsq_s16 (int16x8_t)
4511 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
4516 @item int8x16_t vclsq_s8 (int8x16_t)
4517 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
4523 @subsubsection Count leading zeros
4526 @item uint32x2_t vclz_u32 (uint32x2_t)
4527 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4532 @item uint16x4_t vclz_u16 (uint16x4_t)
4533 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4538 @item uint8x8_t vclz_u8 (uint8x8_t)
4539 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4544 @item int32x2_t vclz_s32 (int32x2_t)
4545 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4550 @item int16x4_t vclz_s16 (int16x4_t)
4551 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4556 @item int8x8_t vclz_s8 (int8x8_t)
4557 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4562 @item uint32x4_t vclzq_u32 (uint32x4_t)
4563 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4568 @item uint16x8_t vclzq_u16 (uint16x8_t)
4569 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4574 @item uint8x16_t vclzq_u8 (uint8x16_t)
4575 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4580 @item int32x4_t vclzq_s32 (int32x4_t)
4581 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4586 @item int16x8_t vclzq_s16 (int16x8_t)
4587 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4592 @item int8x16_t vclzq_s8 (int8x16_t)
4593 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4599 @subsubsection Count number of set bits
4602 @item uint8x8_t vcnt_u8 (uint8x8_t)
4603 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4608 @item int8x8_t vcnt_s8 (int8x8_t)
4609 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4614 @item poly8x8_t vcnt_p8 (poly8x8_t)
4615 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4620 @item uint8x16_t vcntq_u8 (uint8x16_t)
4621 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4626 @item int8x16_t vcntq_s8 (int8x16_t)
4627 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4632 @item poly8x16_t vcntq_p8 (poly8x16_t)
4633 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4639 @subsubsection Reciprocal estimate
4642 @item float32x2_t vrecpe_f32 (float32x2_t)
4643 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
4648 @item uint32x2_t vrecpe_u32 (uint32x2_t)
4649 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
4654 @item float32x4_t vrecpeq_f32 (float32x4_t)
4655 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
4660 @item uint32x4_t vrecpeq_u32 (uint32x4_t)
4661 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
4667 @subsubsection Reciprocal square-root estimate
4670 @item float32x2_t vrsqrte_f32 (float32x2_t)
4671 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
4676 @item uint32x2_t vrsqrte_u32 (uint32x2_t)
4677 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
4682 @item float32x4_t vrsqrteq_f32 (float32x4_t)
4683 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
4688 @item uint32x4_t vrsqrteq_u32 (uint32x4_t)
4689 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
4695 @subsubsection Get lanes from a vector
4698 @item uint32_t vget_lane_u32 (uint32x2_t, const int)
4699 @*@emph{Form of expected instruction(s):} @code{vmov.u32 @var{r0}, @var{d0}[@var{0}]}
4704 @item uint16_t vget_lane_u16 (uint16x4_t, const int)
4705 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4710 @item uint8_t vget_lane_u8 (uint8x8_t, const int)
4711 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4716 @item int32_t vget_lane_s32 (int32x2_t, const int)
4717 @*@emph{Form of expected instruction(s):} @code{vmov.s32 @var{r0}, @var{d0}[@var{0}]}
4722 @item int16_t vget_lane_s16 (int16x4_t, const int)
4723 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4728 @item int8_t vget_lane_s8 (int8x8_t, const int)
4729 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4734 @item float32_t vget_lane_f32 (float32x2_t, const int)
4735 @*@emph{Form of expected instruction(s):} @code{vmov.f32 @var{r0}, @var{d0}[@var{0}]}
4740 @item poly16_t vget_lane_p16 (poly16x4_t, const int)
4741 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4746 @item poly8_t vget_lane_p8 (poly8x8_t, const int)
4747 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4752 @item uint64_t vget_lane_u64 (uint64x1_t, const int)
4753 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4758 @item int64_t vget_lane_s64 (int64x1_t, const int)
4759 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4764 @item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
4765 @*@emph{Form of expected instruction(s):} @code{vmov.u32 @var{r0}, @var{d0}[@var{0}]}
4770 @item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
4771 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4776 @item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
4777 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4782 @item int32_t vgetq_lane_s32 (int32x4_t, const int)
4783 @*@emph{Form of expected instruction(s):} @code{vmov.s32 @var{r0}, @var{d0}[@var{0}]}
4788 @item int16_t vgetq_lane_s16 (int16x8_t, const int)
4789 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4794 @item int8_t vgetq_lane_s8 (int8x16_t, const int)
4795 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4800 @item float32_t vgetq_lane_f32 (float32x4_t, const int)
4801 @*@emph{Form of expected instruction(s):} @code{vmov.f32 @var{r0}, @var{d0}[@var{0}]}
4806 @item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
4807 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4812 @item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
4813 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4818 @item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
4819 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4824 @item int64_t vgetq_lane_s64 (int64x2_t, const int)
4825 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4831 @subsubsection Set lanes in a vector
4834 @item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
4835 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4840 @item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
4841 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4846 @item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
4847 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4852 @item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
4853 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4858 @item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
4859 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4864 @item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
4865 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4870 @item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
4871 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4876 @item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
4877 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4882 @item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
4883 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4888 @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
4889 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4894 @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
4895 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4900 @item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
4901 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4906 @item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
4907 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4912 @item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
4913 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4918 @item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
4919 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4924 @item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
4925 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4930 @item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
4931 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4936 @item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
4937 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4942 @item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
4943 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4948 @item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
4949 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4954 @item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
4955 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4960 @item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
4961 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4967 @subsubsection Create vector from literal bit pattern
4970 @item uint32x2_t vcreate_u32 (uint64_t)
4975 @item uint16x4_t vcreate_u16 (uint64_t)
4980 @item uint8x8_t vcreate_u8 (uint64_t)
4985 @item int32x2_t vcreate_s32 (uint64_t)
4990 @item int16x4_t vcreate_s16 (uint64_t)
4995 @item int8x8_t vcreate_s8 (uint64_t)
5000 @item uint64x1_t vcreate_u64 (uint64_t)
5005 @item int64x1_t vcreate_s64 (uint64_t)
5010 @item float32x2_t vcreate_f32 (uint64_t)
5015 @item poly16x4_t vcreate_p16 (uint64_t)
5020 @item poly8x8_t vcreate_p8 (uint64_t)
5026 @subsubsection Set all lanes to the same value
5029 @item uint32x2_t vdup_n_u32 (uint32_t)
5030 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5035 @item uint16x4_t vdup_n_u16 (uint16_t)
5036 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5041 @item uint8x8_t vdup_n_u8 (uint8_t)
5042 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5047 @item int32x2_t vdup_n_s32 (int32_t)
5048 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5053 @item int16x4_t vdup_n_s16 (int16_t)
5054 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5059 @item int8x8_t vdup_n_s8 (int8_t)
5060 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5065 @item float32x2_t vdup_n_f32 (float32_t)
5066 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5071 @item poly16x4_t vdup_n_p16 (poly16_t)
5072 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5077 @item poly8x8_t vdup_n_p8 (poly8_t)
5078 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5083 @item uint64x1_t vdup_n_u64 (uint64_t)
5084 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5089 @item int64x1_t vdup_n_s64 (int64_t)
5090 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5095 @item uint32x4_t vdupq_n_u32 (uint32_t)
5096 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5101 @item uint16x8_t vdupq_n_u16 (uint16_t)
5102 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5107 @item uint8x16_t vdupq_n_u8 (uint8_t)
5108 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5113 @item int32x4_t vdupq_n_s32 (int32_t)
5114 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5119 @item int16x8_t vdupq_n_s16 (int16_t)
5120 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5125 @item int8x16_t vdupq_n_s8 (int8_t)
5126 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5131 @item float32x4_t vdupq_n_f32 (float32_t)
5132 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5137 @item poly16x8_t vdupq_n_p16 (poly16_t)
5138 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5143 @item poly8x16_t vdupq_n_p8 (poly8_t)
5144 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5149 @item uint64x2_t vdupq_n_u64 (uint64_t)
5150 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5155 @item int64x2_t vdupq_n_s64 (int64_t)
5156 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5161 @item uint32x2_t vmov_n_u32 (uint32_t)
5162 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5167 @item uint16x4_t vmov_n_u16 (uint16_t)
5168 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5173 @item uint8x8_t vmov_n_u8 (uint8_t)
5174 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5179 @item int32x2_t vmov_n_s32 (int32_t)
5180 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5185 @item int16x4_t vmov_n_s16 (int16_t)
5186 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5191 @item int8x8_t vmov_n_s8 (int8_t)
5192 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5197 @item float32x2_t vmov_n_f32 (float32_t)
5198 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5203 @item poly16x4_t vmov_n_p16 (poly16_t)
5204 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5209 @item poly8x8_t vmov_n_p8 (poly8_t)
5210 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5215 @item uint64x1_t vmov_n_u64 (uint64_t)
5216 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5221 @item int64x1_t vmov_n_s64 (int64_t)
5222 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5227 @item uint32x4_t vmovq_n_u32 (uint32_t)
5228 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5233 @item uint16x8_t vmovq_n_u16 (uint16_t)
5234 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5239 @item uint8x16_t vmovq_n_u8 (uint8_t)
5240 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5245 @item int32x4_t vmovq_n_s32 (int32_t)
5246 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5251 @item int16x8_t vmovq_n_s16 (int16_t)
5252 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5257 @item int8x16_t vmovq_n_s8 (int8_t)
5258 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5263 @item float32x4_t vmovq_n_f32 (float32_t)
5264 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5269 @item poly16x8_t vmovq_n_p16 (poly16_t)
5270 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5275 @item poly8x16_t vmovq_n_p8 (poly8_t)
5276 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5281 @item uint64x2_t vmovq_n_u64 (uint64_t)
5282 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5287 @item int64x2_t vmovq_n_s64 (int64_t)
5288 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5293 @item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
5294 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5299 @item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
5300 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5305 @item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
5306 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5311 @item int32x2_t vdup_lane_s32 (int32x2_t, const int)
5312 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5317 @item int16x4_t vdup_lane_s16 (int16x4_t, const int)
5318 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5323 @item int8x8_t vdup_lane_s8 (int8x8_t, const int)
5324 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5329 @item float32x2_t vdup_lane_f32 (float32x2_t, const int)
5330 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5335 @item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
5336 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5341 @item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
5342 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5347 @item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
5352 @item int64x1_t vdup_lane_s64 (int64x1_t, const int)
5357 @item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
5358 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5363 @item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
5364 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5369 @item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
5370 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5375 @item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
5376 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5381 @item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
5382 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5387 @item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
5388 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5393 @item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
5394 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5399 @item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
5400 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5405 @item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
5406 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5411 @item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
5416 @item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
5422 @subsubsection Combining vectors
5425 @item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
5430 @item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
5435 @item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
5440 @item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
5445 @item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
5450 @item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
5455 @item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
5460 @item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
5465 @item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
5470 @item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
5475 @item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
5481 @subsubsection Splitting vectors
5484 @item uint32x2_t vget_high_u32 (uint32x4_t)
5489 @item uint16x4_t vget_high_u16 (uint16x8_t)
5494 @item uint8x8_t vget_high_u8 (uint8x16_t)
5499 @item int32x2_t vget_high_s32 (int32x4_t)
5504 @item int16x4_t vget_high_s16 (int16x8_t)
5509 @item int8x8_t vget_high_s8 (int8x16_t)
5514 @item uint64x1_t vget_high_u64 (uint64x2_t)
5519 @item int64x1_t vget_high_s64 (int64x2_t)
5524 @item float32x2_t vget_high_f32 (float32x4_t)
5529 @item poly16x4_t vget_high_p16 (poly16x8_t)
5534 @item poly8x8_t vget_high_p8 (poly8x16_t)
5539 @item uint32x2_t vget_low_u32 (uint32x4_t)
5540 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5545 @item uint16x4_t vget_low_u16 (uint16x8_t)
5546 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5551 @item uint8x8_t vget_low_u8 (uint8x16_t)
5552 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5557 @item int32x2_t vget_low_s32 (int32x4_t)
5558 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5563 @item int16x4_t vget_low_s16 (int16x8_t)
5564 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5569 @item int8x8_t vget_low_s8 (int8x16_t)
5570 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5575 @item uint64x1_t vget_low_u64 (uint64x2_t)
5576 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5581 @item int64x1_t vget_low_s64 (int64x2_t)
5582 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5587 @item float32x2_t vget_low_f32 (float32x4_t)
5588 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5593 @item poly16x4_t vget_low_p16 (poly16x8_t)
5594 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5599 @item poly8x8_t vget_low_p8 (poly8x16_t)
5600 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5606 @subsubsection Conversions
5609 @item float32x2_t vcvt_f32_u32 (uint32x2_t)
5610 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
5615 @item float32x2_t vcvt_f32_s32 (int32x2_t)
5616 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
5621 @item uint32x2_t vcvt_u32_f32 (float32x2_t)
5622 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
5627 @item int32x2_t vcvt_s32_f32 (float32x2_t)
5628 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
5633 @item float32x4_t vcvtq_f32_u32 (uint32x4_t)
5634 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
5639 @item float32x4_t vcvtq_f32_s32 (int32x4_t)
5640 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
5645 @item uint32x4_t vcvtq_u32_f32 (float32x4_t)
5646 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
5651 @item int32x4_t vcvtq_s32_f32 (float32x4_t)
5652 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
5657 @item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
5658 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
5663 @item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
5664 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
5669 @item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
5670 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
5675 @item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
5676 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
5681 @item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
5682 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
5687 @item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
5688 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
5693 @item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
5694 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
5699 @item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
5700 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
5706 @subsubsection Move, single_opcode narrowing
5709 @item uint32x2_t vmovn_u64 (uint64x2_t)
5710 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5715 @item uint16x4_t vmovn_u32 (uint32x4_t)
5716 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5721 @item uint8x8_t vmovn_u16 (uint16x8_t)
5722 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5727 @item int32x2_t vmovn_s64 (int64x2_t)
5728 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5733 @item int16x4_t vmovn_s32 (int32x4_t)
5734 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5739 @item int8x8_t vmovn_s16 (int16x8_t)
5740 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5745 @item uint32x2_t vqmovn_u64 (uint64x2_t)
5746 @*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
5751 @item uint16x4_t vqmovn_u32 (uint32x4_t)
5752 @*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
5757 @item uint8x8_t vqmovn_u16 (uint16x8_t)
5758 @*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
5763 @item int32x2_t vqmovn_s64 (int64x2_t)
5764 @*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
5769 @item int16x4_t vqmovn_s32 (int32x4_t)
5770 @*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
5775 @item int8x8_t vqmovn_s16 (int16x8_t)
5776 @*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
5781 @item uint32x2_t vqmovun_s64 (int64x2_t)
5782 @*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
5787 @item uint16x4_t vqmovun_s32 (int32x4_t)
5788 @*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
5793 @item uint8x8_t vqmovun_s16 (int16x8_t)
5794 @*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
5800 @subsubsection Move, single_opcode long
5803 @item uint64x2_t vmovl_u32 (uint32x2_t)
5804 @*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
5809 @item uint32x4_t vmovl_u16 (uint16x4_t)
5810 @*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
5815 @item uint16x8_t vmovl_u8 (uint8x8_t)
5816 @*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
5821 @item int64x2_t vmovl_s32 (int32x2_t)
5822 @*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
5827 @item int32x4_t vmovl_s16 (int16x4_t)
5828 @*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
5833 @item int16x8_t vmovl_s8 (int8x8_t)
5834 @*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
5840 @subsubsection Table lookup
5843 @item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
5844 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5849 @item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
5850 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5855 @item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
5856 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5861 @item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
5862 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5867 @item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
5868 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5873 @item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
5874 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5879 @item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
5880 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5885 @item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
5886 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5891 @item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
5892 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5897 @item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
5898 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5903 @item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
5904 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5909 @item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
5910 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5916 @subsubsection Extended table lookup
5919 @item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
5920 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5925 @item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
5926 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5931 @item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
5932 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5937 @item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
5938 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5943 @item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
5944 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5949 @item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
5950 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5955 @item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
5956 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5961 @item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
5962 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5967 @item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
5968 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5973 @item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
5974 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5979 @item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
5980 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5985 @item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
5986 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5992 @subsubsection Multiply, lane
5995 @item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
5996 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6001 @item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
6002 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6007 @item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
6008 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6013 @item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
6014 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6019 @item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
6020 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6025 @item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
6026 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6031 @item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
6032 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6037 @item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
6038 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6043 @item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
6044 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6049 @item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
6050 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6056 @subsubsection Long multiply, lane
6059 @item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
6060 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6065 @item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
6066 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6071 @item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
6072 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6077 @item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
6078 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6084 @subsubsection Saturating doubling long multiply, lane
6087 @item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
6088 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6093 @item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
6094 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6100 @subsubsection Saturating doubling multiply high, lane
6103 @item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6104 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6109 @item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6110 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6115 @item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6116 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6121 @item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6122 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6127 @item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6128 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6133 @item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6134 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6139 @item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6140 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6145 @item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6146 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6152 @subsubsection Multiply-accumulate, lane
6155 @item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6156 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6161 @item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6162 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6167 @item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6168 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6173 @item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6174 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6179 @item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6180 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6185 @item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6186 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6191 @item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6192 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6197 @item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6198 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6203 @item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6204 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6209 @item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6210 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6215 @item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6216 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6221 @item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6222 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6227 @item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6228 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6233 @item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6234 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6239 @item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6240 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6245 @item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6246 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6252 @subsubsection Multiply-subtract, lane
6255 @item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6256 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6261 @item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6262 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6267 @item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6268 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6273 @item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6274 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6279 @item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6280 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6285 @item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6286 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6291 @item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6292 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6297 @item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6298 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6303 @item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6304 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6309 @item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6310 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6315 @item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6316 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6321 @item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6322 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6327 @item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6328 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6333 @item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6334 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6339 @item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6340 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6345 @item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6346 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6352 @subsubsection Vector multiply by scalar
6355 @item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
6356 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6361 @item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
6362 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6367 @item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
6368 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6373 @item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
6374 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6379 @item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
6380 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6385 @item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
6386 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6391 @item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
6392 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6397 @item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
6398 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6403 @item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
6404 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6409 @item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
6410 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6416 @subsubsection Vector long multiply by scalar
6419 @item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
6420 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6425 @item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
6426 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6431 @item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
6432 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6437 @item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
6438 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6444 @subsubsection Vector saturating doubling long multiply by scalar
6447 @item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
6448 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6453 @item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
6454 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6460 @subsubsection Vector saturating doubling multiply high by scalar
6463 @item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
6464 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6469 @item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
6470 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6475 @item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
6476 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6481 @item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
6482 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6487 @item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
6488 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6493 @item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
6494 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6499 @item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
6500 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6505 @item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
6506 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6512 @subsubsection Vector multiply-accumulate by scalar
6515 @item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
6516 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6521 @item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6522 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6527 @item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6528 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6533 @item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
6534 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6539 @item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
6540 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6545 @item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
6546 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6551 @item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6552 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6557 @item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6558 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6563 @item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
6564 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6569 @item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
6570 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6575 @item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6576 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6581 @item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6582 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6587 @item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6588 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6593 @item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6594 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6599 @item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6600 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6605 @item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6606 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6612 @subsubsection Vector multiply-subtract by scalar
6615 @item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
6616 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6621 @item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6622 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6627 @item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6628 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6633 @item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
6634 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6639 @item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
6640 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6645 @item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
6646 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6651 @item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6652 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6657 @item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6658 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6663 @item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
6664 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6669 @item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
6670 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6675 @item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6676 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6681 @item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6682 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6687 @item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6688 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6693 @item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6694 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6699 @item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6700 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6705 @item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6706 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6712 @subsubsection Vector extract
6715 @item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
6716 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6721 @item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
6722 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6727 @item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
6728 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6733 @item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
6734 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6739 @item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
6740 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6745 @item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
6746 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6751 @item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
6752 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6757 @item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
6758 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6763 @item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
6764 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6769 @item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
6770 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6775 @item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
6776 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6781 @item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
6782 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6787 @item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
6788 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6793 @item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
6794 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6799 @item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
6800 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6805 @item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
6806 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6811 @item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
6812 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6817 @item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
6818 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6823 @item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
6824 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6829 @item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
6830 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6835 @item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
6836 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6841 @item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
6842 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6848 @subsubsection Reverse elements
6851 @item uint32x2_t vrev64_u32 (uint32x2_t)
6852 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6857 @item uint16x4_t vrev64_u16 (uint16x4_t)
6858 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6863 @item uint8x8_t vrev64_u8 (uint8x8_t)
6864 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6869 @item int32x2_t vrev64_s32 (int32x2_t)
6870 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6875 @item int16x4_t vrev64_s16 (int16x4_t)
6876 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6881 @item int8x8_t vrev64_s8 (int8x8_t)
6882 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6887 @item float32x2_t vrev64_f32 (float32x2_t)
6888 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6893 @item poly16x4_t vrev64_p16 (poly16x4_t)
6894 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6899 @item poly8x8_t vrev64_p8 (poly8x8_t)
6900 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6905 @item uint32x4_t vrev64q_u32 (uint32x4_t)
6906 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6911 @item uint16x8_t vrev64q_u16 (uint16x8_t)
6912 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6917 @item uint8x16_t vrev64q_u8 (uint8x16_t)
6918 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6923 @item int32x4_t vrev64q_s32 (int32x4_t)
6924 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6929 @item int16x8_t vrev64q_s16 (int16x8_t)
6930 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6935 @item int8x16_t vrev64q_s8 (int8x16_t)
6936 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6941 @item float32x4_t vrev64q_f32 (float32x4_t)
6942 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6947 @item poly16x8_t vrev64q_p16 (poly16x8_t)
6948 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6953 @item poly8x16_t vrev64q_p8 (poly8x16_t)
6954 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6959 @item uint16x4_t vrev32_u16 (uint16x4_t)
6960 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6965 @item int16x4_t vrev32_s16 (int16x4_t)
6966 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6971 @item uint8x8_t vrev32_u8 (uint8x8_t)
6972 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6977 @item int8x8_t vrev32_s8 (int8x8_t)
6978 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6983 @item poly16x4_t vrev32_p16 (poly16x4_t)
6984 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6989 @item poly8x8_t vrev32_p8 (poly8x8_t)
6990 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6995 @item uint16x8_t vrev32q_u16 (uint16x8_t)
6996 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7001 @item int16x8_t vrev32q_s16 (int16x8_t)
7002 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7007 @item uint8x16_t vrev32q_u8 (uint8x16_t)
7008 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7013 @item int8x16_t vrev32q_s8 (int8x16_t)
7014 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7019 @item poly16x8_t vrev32q_p16 (poly16x8_t)
7020 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7025 @item poly8x16_t vrev32q_p8 (poly8x16_t)
7026 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7031 @item uint8x8_t vrev16_u8 (uint8x8_t)
7032 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7037 @item int8x8_t vrev16_s8 (int8x8_t)
7038 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7043 @item poly8x8_t vrev16_p8 (poly8x8_t)
7044 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7049 @item uint8x16_t vrev16q_u8 (uint8x16_t)
7050 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7055 @item int8x16_t vrev16q_s8 (int8x16_t)
7056 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7061 @item poly8x16_t vrev16q_p8 (poly8x16_t)
7062 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7068 @subsubsection Bit selection
7071 @item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
7072 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7077 @item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
7078 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7083 @item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
7084 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7089 @item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
7090 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7095 @item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
7096 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7101 @item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
7102 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7107 @item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
7108 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7113 @item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
7114 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7119 @item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
7120 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7125 @item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
7126 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7131 @item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
7132 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7137 @item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
7138 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7143 @item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
7144 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7149 @item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
7150 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7155 @item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
7156 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7161 @item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
7162 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7167 @item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
7168 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7173 @item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
7174 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7179 @item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
7180 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7185 @item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
7186 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7191 @item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
7192 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7197 @item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
7198 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7204 @subsubsection Transpose elements
7207 @item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
7208 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7213 @item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
7214 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7219 @item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
7220 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7225 @item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
7226 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7231 @item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
7232 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7237 @item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
7238 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7243 @item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
7244 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7249 @item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
7250 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7255 @item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
7256 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7261 @item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
7262 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7267 @item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
7268 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7273 @item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
7274 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7279 @item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
7280 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7285 @item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
7286 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7291 @item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
7292 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7297 @item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
7298 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7303 @item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
7304 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7309 @item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
7310 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7316 @subsubsection Zip elements
7319 @item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
7320 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7325 @item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
7326 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7331 @item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
7332 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7337 @item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
7338 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7343 @item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
7344 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7349 @item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
7350 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7355 @item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
7356 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7361 @item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
7362 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7367 @item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
7368 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7373 @item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
7374 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7379 @item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
7380 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7385 @item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
7386 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7391 @item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
7392 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7397 @item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
7398 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7403 @item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
7404 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7409 @item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
7410 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7415 @item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
7416 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7421 @item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
7422 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7428 @subsubsection Unzip elements
7431 @item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
7432 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7437 @item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
7438 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7443 @item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
7444 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7449 @item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
7450 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7455 @item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
7456 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7461 @item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
7462 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7467 @item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
7468 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7473 @item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
7474 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7479 @item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
7480 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7485 @item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
7486 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7491 @item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
7492 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7497 @item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
7498 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7503 @item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
7504 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7509 @item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
7510 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7515 @item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
7516 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7521 @item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
7522 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7527 @item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
7528 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7533 @item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
7534 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7540 @subsubsection Element/structure loads, VLD1 variants
7543 @item uint32x2_t vld1_u32 (const uint32_t *)
7544 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7549 @item uint16x4_t vld1_u16 (const uint16_t *)
7550 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7555 @item uint8x8_t vld1_u8 (const uint8_t *)
7556 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7561 @item int32x2_t vld1_s32 (const int32_t *)
7562 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7567 @item int16x4_t vld1_s16 (const int16_t *)
7568 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7573 @item int8x8_t vld1_s8 (const int8_t *)
7574 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7579 @item uint64x1_t vld1_u64 (const uint64_t *)
7580 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7585 @item int64x1_t vld1_s64 (const int64_t *)
7586 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7591 @item float32x2_t vld1_f32 (const float32_t *)
7592 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7597 @item poly16x4_t vld1_p16 (const poly16_t *)
7598 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7603 @item poly8x8_t vld1_p8 (const poly8_t *)
7604 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7609 @item uint32x4_t vld1q_u32 (const uint32_t *)
7610 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7615 @item uint16x8_t vld1q_u16 (const uint16_t *)
7616 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7621 @item uint8x16_t vld1q_u8 (const uint8_t *)
7622 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7627 @item int32x4_t vld1q_s32 (const int32_t *)
7628 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7633 @item int16x8_t vld1q_s16 (const int16_t *)
7634 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7639 @item int8x16_t vld1q_s8 (const int8_t *)
7640 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7645 @item uint64x2_t vld1q_u64 (const uint64_t *)
7646 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7651 @item int64x2_t vld1q_s64 (const int64_t *)
7652 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7657 @item float32x4_t vld1q_f32 (const float32_t *)
7658 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7663 @item poly16x8_t vld1q_p16 (const poly16_t *)
7664 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7669 @item poly8x16_t vld1q_p8 (const poly8_t *)
7670 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7675 @item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
7676 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7681 @item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
7682 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7687 @item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
7688 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7693 @item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
7694 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7699 @item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
7700 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7705 @item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
7706 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7711 @item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
7712 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7717 @item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
7718 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7723 @item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
7724 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7729 @item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
7730 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7735 @item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
7736 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7741 @item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
7742 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7747 @item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
7748 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7753 @item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
7754 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7759 @item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
7760 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7765 @item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
7766 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7771 @item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
7772 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7777 @item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
7778 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7783 @item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
7784 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7789 @item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
7790 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7795 @item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
7796 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7801 @item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
7802 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7807 @item uint32x2_t vld1_dup_u32 (const uint32_t *)
7808 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7813 @item uint16x4_t vld1_dup_u16 (const uint16_t *)
7814 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7819 @item uint8x8_t vld1_dup_u8 (const uint8_t *)
7820 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7825 @item int32x2_t vld1_dup_s32 (const int32_t *)
7826 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7831 @item int16x4_t vld1_dup_s16 (const int16_t *)
7832 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7837 @item int8x8_t vld1_dup_s8 (const int8_t *)
7838 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7843 @item float32x2_t vld1_dup_f32 (const float32_t *)
7844 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7849 @item poly16x4_t vld1_dup_p16 (const poly16_t *)
7850 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7855 @item poly8x8_t vld1_dup_p8 (const poly8_t *)
7856 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7861 @item uint64x1_t vld1_dup_u64 (const uint64_t *)
7862 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7867 @item int64x1_t vld1_dup_s64 (const int64_t *)
7868 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7873 @item uint32x4_t vld1q_dup_u32 (const uint32_t *)
7874 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7879 @item uint16x8_t vld1q_dup_u16 (const uint16_t *)
7880 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7885 @item uint8x16_t vld1q_dup_u8 (const uint8_t *)
7886 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7891 @item int32x4_t vld1q_dup_s32 (const int32_t *)
7892 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7897 @item int16x8_t vld1q_dup_s16 (const int16_t *)
7898 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7903 @item int8x16_t vld1q_dup_s8 (const int8_t *)
7904 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7909 @item float32x4_t vld1q_dup_f32 (const float32_t *)
7910 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7915 @item poly16x8_t vld1q_dup_p16 (const poly16_t *)
7916 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7921 @item poly8x16_t vld1q_dup_p8 (const poly8_t *)
7922 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7927 @item uint64x2_t vld1q_dup_u64 (const uint64_t *)
7928 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7933 @item int64x2_t vld1q_dup_s64 (const int64_t *)
7934 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7940 @subsubsection Element/structure stores, VST1 variants
7943 @item void vst1_u32 (uint32_t *, uint32x2_t)
7944 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7949 @item void vst1_u16 (uint16_t *, uint16x4_t)
7950 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7955 @item void vst1_u8 (uint8_t *, uint8x8_t)
7956 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7961 @item void vst1_s32 (int32_t *, int32x2_t)
7962 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7967 @item void vst1_s16 (int16_t *, int16x4_t)
7968 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7973 @item void vst1_s8 (int8_t *, int8x8_t)
7974 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7979 @item void vst1_u64 (uint64_t *, uint64x1_t)
7980 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7985 @item void vst1_s64 (int64_t *, int64x1_t)
7986 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7991 @item void vst1_f32 (float32_t *, float32x2_t)
7992 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7997 @item void vst1_p16 (poly16_t *, poly16x4_t)
7998 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8003 @item void vst1_p8 (poly8_t *, poly8x8_t)
8004 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8009 @item void vst1q_u32 (uint32_t *, uint32x4_t)
8010 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8015 @item void vst1q_u16 (uint16_t *, uint16x8_t)
8016 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8021 @item void vst1q_u8 (uint8_t *, uint8x16_t)
8022 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8027 @item void vst1q_s32 (int32_t *, int32x4_t)
8028 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8033 @item void vst1q_s16 (int16_t *, int16x8_t)
8034 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8039 @item void vst1q_s8 (int8_t *, int8x16_t)
8040 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8045 @item void vst1q_u64 (uint64_t *, uint64x2_t)
8046 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8051 @item void vst1q_s64 (int64_t *, int64x2_t)
8052 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8057 @item void vst1q_f32 (float32_t *, float32x4_t)
8058 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8063 @item void vst1q_p16 (poly16_t *, poly16x8_t)
8064 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8069 @item void vst1q_p8 (poly8_t *, poly8x16_t)
8070 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8075 @item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
8076 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8081 @item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
8082 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8087 @item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
8088 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8093 @item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
8094 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8099 @item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
8100 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8105 @item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
8106 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8111 @item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
8112 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8117 @item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
8118 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8123 @item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
8124 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8129 @item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
8130 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8135 @item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
8136 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8141 @item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
8142 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8147 @item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
8148 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8153 @item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
8154 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8159 @item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
8160 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8165 @item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
8166 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8171 @item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
8172 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8177 @item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
8178 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8183 @item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
8184 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8189 @item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
8190 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8195 @item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
8196 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8201 @item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
8202 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8208 @subsubsection Element/structure loads, VLD2 variants
8211 @item uint32x2x2_t vld2_u32 (const uint32_t *)
8212 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8217 @item uint16x4x2_t vld2_u16 (const uint16_t *)
8218 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8223 @item uint8x8x2_t vld2_u8 (const uint8_t *)
8224 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8229 @item int32x2x2_t vld2_s32 (const int32_t *)
8230 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8235 @item int16x4x2_t vld2_s16 (const int16_t *)
8236 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8241 @item int8x8x2_t vld2_s8 (const int8_t *)
8242 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8247 @item float32x2x2_t vld2_f32 (const float32_t *)
8248 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8253 @item poly16x4x2_t vld2_p16 (const poly16_t *)
8254 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8259 @item poly8x8x2_t vld2_p8 (const poly8_t *)
8260 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8265 @item uint64x1x2_t vld2_u64 (const uint64_t *)
8266 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8271 @item int64x1x2_t vld2_s64 (const int64_t *)
8272 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8277 @item uint32x4x2_t vld2q_u32 (const uint32_t *)
8278 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8283 @item uint16x8x2_t vld2q_u16 (const uint16_t *)
8284 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8289 @item uint8x16x2_t vld2q_u8 (const uint8_t *)
8290 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8295 @item int32x4x2_t vld2q_s32 (const int32_t *)
8296 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8301 @item int16x8x2_t vld2q_s16 (const int16_t *)
8302 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8307 @item int8x16x2_t vld2q_s8 (const int8_t *)
8308 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8313 @item float32x4x2_t vld2q_f32 (const float32_t *)
8314 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8319 @item poly16x8x2_t vld2q_p16 (const poly16_t *)
8320 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8325 @item poly8x16x2_t vld2q_p8 (const poly8_t *)
8326 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8331 @item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
8332 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8337 @item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
8338 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8343 @item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
8344 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8349 @item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
8350 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8355 @item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
8356 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8361 @item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
8362 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8367 @item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
8368 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8373 @item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
8374 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8379 @item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
8380 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8385 @item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
8386 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8391 @item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
8392 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8397 @item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
8398 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8403 @item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
8404 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8409 @item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
8410 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8415 @item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
8416 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8421 @item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
8422 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8427 @item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
8428 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8433 @item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
8434 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8439 @item int32x2x2_t vld2_dup_s32 (const int32_t *)
8440 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8445 @item int16x4x2_t vld2_dup_s16 (const int16_t *)
8446 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8451 @item int8x8x2_t vld2_dup_s8 (const int8_t *)
8452 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8457 @item float32x2x2_t vld2_dup_f32 (const float32_t *)
8458 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8463 @item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
8464 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8469 @item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
8470 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8475 @item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
8476 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8481 @item int64x1x2_t vld2_dup_s64 (const int64_t *)
8482 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8488 @subsubsection Element/structure stores, VST2 variants
8491 @item void vst2_u32 (uint32_t *, uint32x2x2_t)
8492 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8497 @item void vst2_u16 (uint16_t *, uint16x4x2_t)
8498 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8503 @item void vst2_u8 (uint8_t *, uint8x8x2_t)
8504 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8509 @item void vst2_s32 (int32_t *, int32x2x2_t)
8510 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8515 @item void vst2_s16 (int16_t *, int16x4x2_t)
8516 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8521 @item void vst2_s8 (int8_t *, int8x8x2_t)
8522 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8527 @item void vst2_f32 (float32_t *, float32x2x2_t)
8528 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8533 @item void vst2_p16 (poly16_t *, poly16x4x2_t)
8534 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8539 @item void vst2_p8 (poly8_t *, poly8x8x2_t)
8540 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8545 @item void vst2_u64 (uint64_t *, uint64x1x2_t)
8546 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8551 @item void vst2_s64 (int64_t *, int64x1x2_t)
8552 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8557 @item void vst2q_u32 (uint32_t *, uint32x4x2_t)
8558 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8563 @item void vst2q_u16 (uint16_t *, uint16x8x2_t)
8564 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8569 @item void vst2q_u8 (uint8_t *, uint8x16x2_t)
8570 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8575 @item void vst2q_s32 (int32_t *, int32x4x2_t)
8576 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8581 @item void vst2q_s16 (int16_t *, int16x8x2_t)
8582 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8587 @item void vst2q_s8 (int8_t *, int8x16x2_t)
8588 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8593 @item void vst2q_f32 (float32_t *, float32x4x2_t)
8594 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8599 @item void vst2q_p16 (poly16_t *, poly16x8x2_t)
8600 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8605 @item void vst2q_p8 (poly8_t *, poly8x16x2_t)
8606 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8611 @item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
8612 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8617 @item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
8618 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8623 @item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
8624 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8629 @item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
8630 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8635 @item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
8636 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8641 @item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
8642 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8647 @item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
8648 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8653 @item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
8654 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8659 @item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
8660 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8665 @item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
8666 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8671 @item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
8672 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8677 @item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
8678 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8683 @item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
8684 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8689 @item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
8690 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8695 @item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
8696 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8702 @subsubsection Element/structure loads, VLD3 variants
8705 @item uint32x2x3_t vld3_u32 (const uint32_t *)
8706 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8711 @item uint16x4x3_t vld3_u16 (const uint16_t *)
8712 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8717 @item uint8x8x3_t vld3_u8 (const uint8_t *)
8718 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8723 @item int32x2x3_t vld3_s32 (const int32_t *)
8724 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8729 @item int16x4x3_t vld3_s16 (const int16_t *)
8730 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8735 @item int8x8x3_t vld3_s8 (const int8_t *)
8736 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8741 @item float32x2x3_t vld3_f32 (const float32_t *)
8742 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8747 @item poly16x4x3_t vld3_p16 (const poly16_t *)
8748 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8753 @item poly8x8x3_t vld3_p8 (const poly8_t *)
8754 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8759 @item uint64x1x3_t vld3_u64 (const uint64_t *)
8760 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8765 @item int64x1x3_t vld3_s64 (const int64_t *)
8766 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8771 @item uint32x4x3_t vld3q_u32 (const uint32_t *)
8772 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8777 @item uint16x8x3_t vld3q_u16 (const uint16_t *)
8778 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8783 @item uint8x16x3_t vld3q_u8 (const uint8_t *)
8784 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8789 @item int32x4x3_t vld3q_s32 (const int32_t *)
8790 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8795 @item int16x8x3_t vld3q_s16 (const int16_t *)
8796 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8801 @item int8x16x3_t vld3q_s8 (const int8_t *)
8802 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8807 @item float32x4x3_t vld3q_f32 (const float32_t *)
8808 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8813 @item poly16x8x3_t vld3q_p16 (const poly16_t *)
8814 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8819 @item poly8x16x3_t vld3q_p8 (const poly8_t *)
8820 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8825 @item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
8826 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8831 @item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
8832 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8837 @item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
8838 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8843 @item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
8844 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8849 @item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
8850 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8855 @item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
8856 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8861 @item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
8862 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8867 @item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
8868 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8873 @item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
8874 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8879 @item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
8880 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8885 @item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
8886 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8891 @item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
8892 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8897 @item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
8898 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8903 @item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
8904 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8909 @item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
8910 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8915 @item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
8916 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8921 @item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
8922 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8927 @item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
8928 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8933 @item int32x2x3_t vld3_dup_s32 (const int32_t *)
8934 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8939 @item int16x4x3_t vld3_dup_s16 (const int16_t *)
8940 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8945 @item int8x8x3_t vld3_dup_s8 (const int8_t *)
8946 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8951 @item float32x2x3_t vld3_dup_f32 (const float32_t *)
8952 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8957 @item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
8958 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8963 @item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
8964 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8969 @item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
8970 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8975 @item int64x1x3_t vld3_dup_s64 (const int64_t *)
8976 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8982 @subsubsection Element/structure stores, VST3 variants
8985 @item void vst3_u32 (uint32_t *, uint32x2x3_t)
8986 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8991 @item void vst3_u16 (uint16_t *, uint16x4x3_t)
8992 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8997 @item void vst3_u8 (uint8_t *, uint8x8x3_t)
8998 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9003 @item void vst3_s32 (int32_t *, int32x2x3_t)
9004 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9009 @item void vst3_s16 (int16_t *, int16x4x3_t)
9010 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9015 @item void vst3_s8 (int8_t *, int8x8x3_t)
9016 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9021 @item void vst3_f32 (float32_t *, float32x2x3_t)
9022 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9027 @item void vst3_p16 (poly16_t *, poly16x4x3_t)
9028 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9033 @item void vst3_p8 (poly8_t *, poly8x8x3_t)
9034 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9039 @item void vst3_u64 (uint64_t *, uint64x1x3_t)
9040 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9045 @item void vst3_s64 (int64_t *, int64x1x3_t)
9046 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9051 @item void vst3q_u32 (uint32_t *, uint32x4x3_t)
9052 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9057 @item void vst3q_u16 (uint16_t *, uint16x8x3_t)
9058 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9063 @item void vst3q_u8 (uint8_t *, uint8x16x3_t)
9064 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9069 @item void vst3q_s32 (int32_t *, int32x4x3_t)
9070 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9075 @item void vst3q_s16 (int16_t *, int16x8x3_t)
9076 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9081 @item void vst3q_s8 (int8_t *, int8x16x3_t)
9082 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9087 @item void vst3q_f32 (float32_t *, float32x4x3_t)
9088 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9093 @item void vst3q_p16 (poly16_t *, poly16x8x3_t)
9094 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9099 @item void vst3q_p8 (poly8_t *, poly8x16x3_t)
9100 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9105 @item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
9106 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9111 @item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
9112 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9117 @item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
9118 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9123 @item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
9124 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9129 @item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
9130 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9135 @item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
9136 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9141 @item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
9142 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9147 @item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
9148 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9153 @item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
9154 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9159 @item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
9160 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9165 @item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
9166 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9171 @item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
9172 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9177 @item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
9178 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9183 @item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
9184 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9189 @item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
9190 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9196 @subsubsection Element/structure loads, VLD4 variants
9199 @item uint32x2x4_t vld4_u32 (const uint32_t *)
9200 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9205 @item uint16x4x4_t vld4_u16 (const uint16_t *)
9206 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9211 @item uint8x8x4_t vld4_u8 (const uint8_t *)
9212 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9217 @item int32x2x4_t vld4_s32 (const int32_t *)
9218 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9223 @item int16x4x4_t vld4_s16 (const int16_t *)
9224 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9229 @item int8x8x4_t vld4_s8 (const int8_t *)
9230 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9235 @item float32x2x4_t vld4_f32 (const float32_t *)
9236 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9241 @item poly16x4x4_t vld4_p16 (const poly16_t *)
9242 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9247 @item poly8x8x4_t vld4_p8 (const poly8_t *)
9248 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9253 @item uint64x1x4_t vld4_u64 (const uint64_t *)
9254 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9259 @item int64x1x4_t vld4_s64 (const int64_t *)
9260 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9265 @item uint32x4x4_t vld4q_u32 (const uint32_t *)
9266 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9271 @item uint16x8x4_t vld4q_u16 (const uint16_t *)
9272 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9277 @item uint8x16x4_t vld4q_u8 (const uint8_t *)
9278 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9283 @item int32x4x4_t vld4q_s32 (const int32_t *)
9284 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9289 @item int16x8x4_t vld4q_s16 (const int16_t *)
9290 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9295 @item int8x16x4_t vld4q_s8 (const int8_t *)
9296 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9301 @item float32x4x4_t vld4q_f32 (const float32_t *)
9302 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9307 @item poly16x8x4_t vld4q_p16 (const poly16_t *)
9308 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9313 @item poly8x16x4_t vld4q_p8 (const poly8_t *)
9314 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9319 @item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
9320 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9325 @item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
9326 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9331 @item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
9332 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9337 @item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
9338 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9343 @item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
9344 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9349 @item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
9350 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9355 @item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
9356 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9361 @item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
9362 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9367 @item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
9368 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9373 @item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
9374 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9379 @item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
9380 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9385 @item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
9386 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9391 @item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
9392 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9397 @item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
9398 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9403 @item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
9404 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9409 @item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
9410 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9415 @item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
9416 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9421 @item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
9422 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9427 @item int32x2x4_t vld4_dup_s32 (const int32_t *)
9428 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9433 @item int16x4x4_t vld4_dup_s16 (const int16_t *)
9434 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9439 @item int8x8x4_t vld4_dup_s8 (const int8_t *)
9440 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9445 @item float32x2x4_t vld4_dup_f32 (const float32_t *)
9446 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9451 @item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
9452 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9457 @item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
9458 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9463 @item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
9464 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9469 @item int64x1x4_t vld4_dup_s64 (const int64_t *)
9470 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9476 @subsubsection Element/structure stores, VST4 variants
9479 @item void vst4_u32 (uint32_t *, uint32x2x4_t)
9480 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9485 @item void vst4_u16 (uint16_t *, uint16x4x4_t)
9486 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9491 @item void vst4_u8 (uint8_t *, uint8x8x4_t)
9492 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9497 @item void vst4_s32 (int32_t *, int32x2x4_t)
9498 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9503 @item void vst4_s16 (int16_t *, int16x4x4_t)
9504 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9509 @item void vst4_s8 (int8_t *, int8x8x4_t)
9510 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9515 @item void vst4_f32 (float32_t *, float32x2x4_t)
9516 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9521 @item void vst4_p16 (poly16_t *, poly16x4x4_t)
9522 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9527 @item void vst4_p8 (poly8_t *, poly8x8x4_t)
9528 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9533 @item void vst4_u64 (uint64_t *, uint64x1x4_t)
9534 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9539 @item void vst4_s64 (int64_t *, int64x1x4_t)
9540 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9545 @item void vst4q_u32 (uint32_t *, uint32x4x4_t)
9546 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9551 @item void vst4q_u16 (uint16_t *, uint16x8x4_t)
9552 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9557 @item void vst4q_u8 (uint8_t *, uint8x16x4_t)
9558 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9563 @item void vst4q_s32 (int32_t *, int32x4x4_t)
9564 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9569 @item void vst4q_s16 (int16_t *, int16x8x4_t)
9570 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9575 @item void vst4q_s8 (int8_t *, int8x16x4_t)
9576 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9581 @item void vst4q_f32 (float32_t *, float32x4x4_t)
9582 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9587 @item void vst4q_p16 (poly16_t *, poly16x8x4_t)
9588 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9593 @item void vst4q_p8 (poly8_t *, poly8x16x4_t)
9594 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9599 @item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
9600 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9605 @item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
9606 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9611 @item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
9612 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9617 @item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
9618 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9623 @item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
9624 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9629 @item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
9630 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9635 @item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
9636 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9641 @item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
9642 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9647 @item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
9648 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9653 @item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
9654 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9659 @item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
9660 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9665 @item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
9666 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9671 @item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
9672 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9677 @item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
9678 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9683 @item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
9684 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9690 @subsubsection Logical operations (AND)
9693 @item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
9694 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9699 @item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
9700 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9705 @item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
9706 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9711 @item int32x2_t vand_s32 (int32x2_t, int32x2_t)
9712 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9717 @item int16x4_t vand_s16 (int16x4_t, int16x4_t)
9718 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9723 @item int8x8_t vand_s8 (int8x8_t, int8x8_t)
9724 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9729 @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
9730 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9735 @item int64x1_t vand_s64 (int64x1_t, int64x1_t)
9736 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9741 @item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
9742 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9747 @item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
9748 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9753 @item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
9754 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9759 @item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
9760 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9765 @item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
9766 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9771 @item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
9772 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9777 @item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
9778 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9783 @item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
9784 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9790 @subsubsection Logical operations (OR)
9793 @item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
9794 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9799 @item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
9800 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9805 @item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
9806 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9811 @item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
9812 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9817 @item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
9818 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9823 @item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
9824 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9829 @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
9830 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9835 @item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
9836 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9841 @item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
9842 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9847 @item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
9848 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9853 @item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
9854 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9859 @item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
9860 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9865 @item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
9866 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9871 @item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
9872 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9877 @item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
9878 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9883 @item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
9884 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9890 @subsubsection Logical operations (exclusive OR)
9893 @item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
9894 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9899 @item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
9900 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9905 @item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
9906 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9911 @item int32x2_t veor_s32 (int32x2_t, int32x2_t)
9912 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9917 @item int16x4_t veor_s16 (int16x4_t, int16x4_t)
9918 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9923 @item int8x8_t veor_s8 (int8x8_t, int8x8_t)
9924 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9929 @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
9930 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9935 @item int64x1_t veor_s64 (int64x1_t, int64x1_t)
9936 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9941 @item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
9942 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9947 @item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
9948 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9953 @item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
9954 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9959 @item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
9960 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9965 @item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
9966 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9971 @item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
9972 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9977 @item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
9978 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9983 @item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
9984 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9990 @subsubsection Logical operations (AND-NOT)
9993 @item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
9994 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9999 @item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
10000 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10005 @item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
10006 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10011 @item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
10012 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10017 @item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
10018 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10023 @item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
10024 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10029 @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
10030 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10035 @item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
10036 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10041 @item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
10042 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10047 @item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
10048 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10053 @item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
10054 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10059 @item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
10060 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10065 @item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
10066 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10071 @item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
10072 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10077 @item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
10078 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10083 @item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
10084 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10090 @subsubsection Logical operations (OR-NOT)
10093 @item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
10094 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10099 @item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
10100 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10105 @item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
10106 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10111 @item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
10112 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10117 @item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
10118 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10123 @item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
10124 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10129 @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
10130 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10135 @item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
10136 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10141 @item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
10142 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10147 @item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
10148 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10153 @item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
10154 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10159 @item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
10160 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10165 @item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
10166 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10171 @item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
10172 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10177 @item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
10178 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10183 @item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
10184 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10190 @subsubsection Reinterpret casts
10193 @item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
10198 @item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
10203 @item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
10208 @item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
10213 @item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
10218 @item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
10223 @item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
10228 @item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
10233 @item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
10238 @item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
10243 @item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
10248 @item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
10253 @item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
10258 @item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
10263 @item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
10268 @item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
10273 @item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
10278 @item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
10283 @item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
10288 @item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
10293 @item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
10298 @item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
10303 @item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
10308 @item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
10313 @item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
10318 @item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
10323 @item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
10328 @item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
10333 @item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
10338 @item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
10343 @item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
10348 @item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
10353 @item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
10358 @item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
10363 @item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
10368 @item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
10373 @item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
10378 @item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
10383 @item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
10388 @item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
10393 @item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
10398 @item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
10403 @item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
10408 @item float32x2_t vreinterpret_f32_s32 (int32x2_t)
10413 @item float32x2_t vreinterpret_f32_s16 (int16x4_t)
10418 @item float32x2_t vreinterpret_f32_s8 (int8x8_t)
10423 @item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
10428 @item float32x2_t vreinterpret_f32_s64 (int64x1_t)
10433 @item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
10438 @item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
10443 @item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
10448 @item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
10453 @item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
10458 @item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
10463 @item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
10468 @item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
10473 @item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
10478 @item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
10483 @item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
10488 @item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
10493 @item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
10498 @item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
10503 @item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
10508 @item int64x1_t vreinterpret_s64_s32 (int32x2_t)
10513 @item int64x1_t vreinterpret_s64_s16 (int16x4_t)
10518 @item int64x1_t vreinterpret_s64_s8 (int8x8_t)
10523 @item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
10528 @item int64x1_t vreinterpret_s64_f32 (float32x2_t)
10533 @item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
10538 @item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
10543 @item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
10548 @item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
10553 @item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
10558 @item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
10563 @item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
10568 @item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
10573 @item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
10578 @item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
10583 @item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
10588 @item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
10593 @item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
10598 @item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
10603 @item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
10608 @item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
10613 @item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
10618 @item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
10623 @item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
10628 @item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
10633 @item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
10638 @item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
10643 @item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
10648 @item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
10653 @item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
10658 @item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
10663 @item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
10668 @item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
10673 @item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
10678 @item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
10683 @item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
10688 @item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
10693 @item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
10698 @item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
10703 @item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
10708 @item int8x8_t vreinterpret_s8_s32 (int32x2_t)
10713 @item int8x8_t vreinterpret_s8_s16 (int16x4_t)
10718 @item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
10723 @item int8x8_t vreinterpret_s8_s64 (int64x1_t)
10728 @item int8x8_t vreinterpret_s8_f32 (float32x2_t)
10733 @item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
10738 @item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
10743 @item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
10748 @item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
10753 @item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
10758 @item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
10763 @item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
10768 @item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
10773 @item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
10778 @item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
10783 @item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
10788 @item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
10793 @item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
10798 @item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
10803 @item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
10808 @item int16x4_t vreinterpret_s16_s32 (int32x2_t)
10813 @item int16x4_t vreinterpret_s16_s8 (int8x8_t)
10818 @item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
10823 @item int16x4_t vreinterpret_s16_s64 (int64x1_t)
10828 @item int16x4_t vreinterpret_s16_f32 (float32x2_t)
10833 @item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
10838 @item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
10843 @item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
10848 @item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
10853 @item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
10858 @item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
10863 @item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
10868 @item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
10873 @item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
10878 @item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
10883 @item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
10888 @item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
10893 @item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
10898 @item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
10903 @item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
10908 @item int32x2_t vreinterpret_s32_s16 (int16x4_t)
10913 @item int32x2_t vreinterpret_s32_s8 (int8x8_t)
10918 @item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
10923 @item int32x2_t vreinterpret_s32_s64 (int64x1_t)
10928 @item int32x2_t vreinterpret_s32_f32 (float32x2_t)
10933 @item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
10938 @item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
10943 @item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
10948 @item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
10953 @item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
10958 @item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
10963 @item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
10968 @item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
10973 @item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
10978 @item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
10983 @item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
10988 @item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
10993 @item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
10998 @item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
11003 @item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
11008 @item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
11013 @item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
11018 @item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
11023 @item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
11028 @item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
11033 @item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
11038 @item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
11043 @item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
11048 @item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
11053 @item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
11058 @item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
11063 @item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
11068 @item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
11073 @item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
11078 @item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
11083 @item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
11088 @item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
11093 @item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
11098 @item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
11103 @item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
11108 @item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
11113 @item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
11118 @item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
11123 @item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
11128 @item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
11133 @item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
11138 @item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
11143 @item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
11148 @item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
11153 @item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
11158 @item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
11163 @item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
11168 @item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
11173 @item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
11178 @item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
11183 @item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
11188 @item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
11193 @item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
11198 @item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
11203 @item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
11208 @item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
11213 @item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
11218 @item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
11223 @item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
11228 @item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
11233 @item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
11238 @item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
11243 @item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
11248 @item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
11253 @item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
11258 @item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
11263 @item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
11268 @item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
11273 @item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
11278 @item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
11283 @item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
11288 @item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)