1 ; Options of Andes NDS32 cpu for GNU compiler
2 ; Copyright (C) 2012-2017 Free Software Foundation, Inc.
3 ; Contributed by Andes Technology Corporation.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it
8 ; under the terms of the GNU General Public License as published
9 ; by the Free Software Foundation; either version 3, or (at your
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14 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ; License for more details.
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19 ; <http://www.gnu.org/licenses/>.
22 config/nds32/nds32-opts.h
24 ; ---------------------------------------------------------------
25 ; The following options are designed for aliasing and compatibility options.
28 Target RejectNegative Alias(mbig-endian)
29 Generate code in big-endian mode.
32 Target RejectNegative Alias(mlittle-endian)
33 Generate code in little-endian mode.
35 ; ---------------------------------------------------------------
38 Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
39 Use reduced-set registers for register allocation.
42 Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
43 Use full-set registers for register allocation.
45 ; ---------------------------------------------------------------
48 Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
49 Generate code in big-endian mode.
52 Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
53 Generate code in little-endian mode.
57 Target Report Mask(CMOV)
58 Generate conditional move instructions.
61 Target Report Mask(EXT_PERF)
62 Generate performance extension instructions.
65 Target Report Mask(EXT_PERF2)
66 Generate performance extension version 2 instructions.
69 Target Report Mask(EXT_STRING)
70 Generate string extension instructions.
73 Target Report Mask(V3PUSH)
74 Generate v3 push25/pop25 instructions.
77 Target Report Mask(16_BIT)
78 Generate 16-bit instructions.
81 Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
82 Specify the size of each interrupt vector, which must be 4 or 16.
85 Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
86 Specify the size of each cache block, which must be a power of 2 between 4 and 512.
89 Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
90 Specify the name of the target architecture.
93 Name(nds32_arch_type) Type(enum nds32_arch_type)
94 Known arch types (for use with the -march= option):
97 Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
100 Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
103 Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
106 Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_MEDIUM)
107 Specify the address generation strategy for code model.
110 Name(nds32_cmodel_type) Type(enum nds32_cmodel_type)
111 Known cmodel types (for use with the -mcmodel= option):
114 Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL)
117 Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM)
120 Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE)
124 Enable constructor/destructor feature.
128 Guide linker to relax instructions.