1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a i387 or SSE fp register.
21 (define_predicate "any_fp_register_operand"
22 (and (match_code "reg")
23 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
25 ;; Return true if OP is an i387 fp register.
26 (define_predicate "fp_register_operand"
27 (and (match_code "reg")
28 (match_test "STACK_REGNO_P (REGNO (op))")))
30 ;; True if the operand is a GENERAL class register.
31 (define_predicate "general_reg_operand"
32 (and (match_code "reg")
33 (match_test "GENERAL_REGNO_P (REGNO (op))")))
35 ;; True if the operand is a nonimmediate operand with GENERAL class register.
36 (define_predicate "nonimmediate_gr_operand"
37 (if_then_else (match_code "reg")
38 (match_test "GENERAL_REGNO_P (REGNO (op))")
39 (match_operand 0 "nonimmediate_operand")))
41 ;; True if the operand is a general operand with GENERAL class register.
42 (define_predicate "general_gr_operand"
43 (if_then_else (match_code "reg")
44 (match_test "GENERAL_REGNO_P (REGNO (op))")
45 (match_operand 0 "general_operand")))
47 ;; True if the operand is an MMX register.
48 (define_predicate "mmx_reg_operand"
49 (and (match_code "reg")
50 (match_test "MMX_REGNO_P (REGNO (op))")))
52 ;; True if the operand is an SSE register.
53 (define_predicate "sse_reg_operand"
54 (and (match_code "reg")
55 (match_test "SSE_REGNO_P (REGNO (op))")))
57 ;; True if the operand is an AVX-512 new register.
58 (define_predicate "ext_sse_reg_operand"
59 (and (match_code "reg")
60 (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
62 ;; Return true if op is a QImode register.
63 (define_predicate "any_QIreg_operand"
64 (and (match_code "reg")
65 (match_test "ANY_QI_REGNO_P (REGNO (op))")))
67 ;; Return true if op is one of QImode registers: %[abcd][hl].
68 (define_predicate "QIreg_operand"
69 (and (match_code "reg")
70 (match_test "QI_REGNO_P (REGNO (op))")))
72 ;; Return true if op is a QImode register operand other than %[abcd][hl].
73 (define_predicate "ext_QIreg_operand"
74 (and (match_test "TARGET_64BIT")
76 (not (match_test "QI_REGNO_P (REGNO (op))"))))
78 ;; Return true if op is the AX register.
79 (define_predicate "ax_reg_operand"
80 (and (match_code "reg")
81 (match_test "REGNO (op) == AX_REG")))
83 ;; Return true if op is the flags register.
84 (define_predicate "flags_reg_operand"
85 (and (match_code "reg")
86 (match_test "REGNO (op) == FLAGS_REG")))
88 ;; Match a DI, SI or HImode register for a zero_extract.
89 (define_special_predicate "ext_register_operand"
90 (and (match_operand 0 "register_operand")
91 (ior (and (match_test "TARGET_64BIT")
92 (match_test "GET_MODE (op) == DImode"))
93 (match_test "GET_MODE (op) == SImode")
94 (match_test "GET_MODE (op) == HImode"))))
96 ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
97 (define_predicate "register_ssemem_operand"
99 (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
100 (match_operand 0 "nonimmediate_operand")
101 (match_operand 0 "register_operand")))
103 ;; Match nonimmediate operands, but exclude memory operands
104 ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled.
105 (define_predicate "nonimm_ssenomem_operand"
107 (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
108 (not (match_test "TARGET_MIX_SSE_I387")))
109 (match_operand 0 "register_operand")
110 (match_operand 0 "nonimmediate_operand")))
112 ;; The above predicate, suitable for x87 arithmetic operators.
113 (define_predicate "x87nonimm_ssenomem_operand"
115 (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
116 (not (match_test "TARGET_MIX_SSE_I387 && X87_ENABLE_ARITH (mode)")))
117 (match_operand 0 "register_operand")
118 (match_operand 0 "nonimmediate_operand")))
120 ;; Match register operands, include memory operand for TARGET_SSE4_1.
121 (define_predicate "register_sse4nonimm_operand"
122 (if_then_else (match_test "TARGET_SSE4_1")
123 (match_operand 0 "nonimmediate_operand")
124 (match_operand 0 "register_operand")))
126 ;; Return true if VALUE is symbol reference
127 (define_predicate "symbol_operand"
128 (match_code "symbol_ref"))
130 ;; Return true if VALUE can be stored in a sign extended immediate field.
131 (define_predicate "x86_64_immediate_operand"
132 (match_code "const_int,symbol_ref,label_ref,const")
135 return immediate_operand (op, mode);
137 switch (GET_CODE (op))
141 HOST_WIDE_INT val = INTVAL (op);
142 return trunc_int_for_mode (val, SImode) == val;
145 /* TLS symbols are not constant. */
146 if (SYMBOL_REF_TLS_MODEL (op))
149 /* Load the external function address via the GOT slot. */
150 if (ix86_force_load_from_GOT_p (op))
153 /* For certain code models, the symbolic references are known to fit.
154 in CM_SMALL_PIC model we know it fits if it is local to the shared
155 library. Don't count TLS SYMBOL_REFs here, since they should fit
156 only if inside of UNSPEC handled below. */
157 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
158 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
161 /* For certain code models, the code is near as well. */
162 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
163 || ix86_cmodel == CM_KERNEL);
166 /* We also may accept the offsetted memory references in certain
168 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
169 switch (XINT (XEXP (op, 0), 1))
171 case UNSPEC_GOTPCREL:
173 case UNSPEC_GOTNTPOFF:
180 if (GET_CODE (XEXP (op, 0)) == PLUS)
182 rtx op1 = XEXP (XEXP (op, 0), 0);
183 rtx op2 = XEXP (XEXP (op, 0), 1);
185 if (ix86_cmodel == CM_LARGE)
187 if (!CONST_INT_P (op2))
190 HOST_WIDE_INT offset = INTVAL (op2);
191 if (trunc_int_for_mode (offset, SImode) != offset)
194 switch (GET_CODE (op1))
197 /* TLS symbols are not constant. */
198 if (SYMBOL_REF_TLS_MODEL (op1))
201 /* Load the external function address via the GOT slot. */
202 if (ix86_force_load_from_GOT_p (op1))
205 /* For CM_SMALL assume that latest object is 16MB before
206 end of 31bits boundary. We may also accept pretty
207 large negative constants knowing that all objects are
208 in the positive half of address space. */
209 if ((ix86_cmodel == CM_SMALL
210 || (ix86_cmodel == CM_MEDIUM
211 && !SYMBOL_REF_FAR_ADDR_P (op1)))
212 && offset < 16*1024*1024)
214 /* For CM_KERNEL we know that all object resist in the
215 negative half of 32bits address space. We may not
216 accept negative offsets, since they may be just off
217 and we may accept pretty large positive ones. */
218 if (ix86_cmodel == CM_KERNEL
224 /* These conditions are similar to SYMBOL_REF ones, just the
225 constraints for code models differ. */
226 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
227 && offset < 16*1024*1024)
229 if (ix86_cmodel == CM_KERNEL
235 switch (XINT (op1, 1))
256 ;; Return true if VALUE can be stored in the zero extended immediate field.
257 (define_predicate "x86_64_zext_immediate_operand"
258 (match_code "const_int,symbol_ref,label_ref,const")
260 switch (GET_CODE (op))
263 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
266 /* TLS symbols are not constant. */
267 if (SYMBOL_REF_TLS_MODEL (op))
270 /* Load the external function address via the GOT slot. */
271 if (ix86_force_load_from_GOT_p (op))
274 /* For certain code models, the symbolic references are known to fit. */
275 return (ix86_cmodel == CM_SMALL
276 || (ix86_cmodel == CM_MEDIUM
277 && !SYMBOL_REF_FAR_ADDR_P (op)));
280 /* For certain code models, the code is near as well. */
281 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
284 /* We also may accept the offsetted memory references in certain
286 if (GET_CODE (XEXP (op, 0)) == PLUS)
288 rtx op1 = XEXP (XEXP (op, 0), 0);
289 rtx op2 = XEXP (XEXP (op, 0), 1);
291 if (ix86_cmodel == CM_LARGE)
293 if (!CONST_INT_P (op2))
296 HOST_WIDE_INT offset = INTVAL (op2);
297 if (trunc_int_for_mode (offset, SImode) != offset)
300 switch (GET_CODE (op1))
303 /* TLS symbols are not constant. */
304 if (SYMBOL_REF_TLS_MODEL (op1))
307 /* Load the external function address via the GOT slot. */
308 if (ix86_force_load_from_GOT_p (op1))
311 /* For small code model we may accept pretty large positive
312 offsets, since one bit is available for free. Negative
313 offsets are limited by the size of NULL pointer area
314 specified by the ABI. */
315 if ((ix86_cmodel == CM_SMALL
316 || (ix86_cmodel == CM_MEDIUM
317 && !SYMBOL_REF_FAR_ADDR_P (op1)))
318 && offset > -0x10000)
320 /* ??? For the kernel, we may accept adjustment of
321 -0x10000000, since we know that it will just convert
322 negative address space to positive, but perhaps this
323 is not worthwhile. */
327 /* These conditions are similar to SYMBOL_REF ones, just the
328 constraints for code models differ. */
329 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
330 && offset > -0x10000)
346 ;; Return true if VALUE is a constant integer whose low and high words satisfy
347 ;; x86_64_immediate_operand.
348 (define_predicate "x86_64_hilo_int_operand"
349 (match_code "const_int,const_wide_int")
351 switch (GET_CODE (op))
354 return x86_64_immediate_operand (op, mode);
357 gcc_assert (CONST_WIDE_INT_NUNITS (op) == 2);
358 return (x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, 0)),
360 && x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op,
369 ;; Return true if VALUE is a constant integer whose value is
370 ;; x86_64_immediate_operand value zero extended from word mode to mode.
371 (define_predicate "x86_64_dwzext_immediate_operand"
372 (match_code "const_int,const_wide_int")
374 switch (GET_CODE (op))
378 return UINTVAL (op) <= HOST_WIDE_INT_UC (0xffffffff);
379 return UINTVAL (op) <= HOST_WIDE_INT_UC (0x7fffffff);
384 return (CONST_WIDE_INT_NUNITS (op) == 2
385 && CONST_WIDE_INT_ELT (op, 1) == 0
386 && (trunc_int_for_mode (CONST_WIDE_INT_ELT (op, 0), SImode)
387 == (HOST_WIDE_INT) CONST_WIDE_INT_ELT (op, 0)));
394 ;; Return true if size of VALUE can be stored in a sign
395 ;; extended immediate field.
396 (define_predicate "x86_64_immediate_size_operand"
397 (and (match_code "symbol_ref")
398 (ior (not (match_test "TARGET_64BIT"))
399 (match_test "ix86_cmodel == CM_SMALL")
400 (match_test "ix86_cmodel == CM_KERNEL"))))
402 ;; Return true if OP is general operand representable on x86_64.
403 (define_predicate "x86_64_general_operand"
404 (if_then_else (match_test "TARGET_64BIT")
405 (ior (match_operand 0 "nonimmediate_operand")
406 (match_operand 0 "x86_64_immediate_operand"))
407 (match_operand 0 "general_operand")))
409 ;; Return true if OP's both words are general operands representable
411 (define_predicate "x86_64_hilo_general_operand"
412 (if_then_else (match_test "TARGET_64BIT")
413 (ior (match_operand 0 "nonimmediate_operand")
414 (match_operand 0 "x86_64_hilo_int_operand"))
415 (match_operand 0 "general_operand")))
417 ;; Return true if OP is non-VOIDmode general operand representable
418 ;; on x86_64. This predicate is used in sign-extending conversion
419 ;; operations that require non-VOIDmode immediate operands.
420 (define_predicate "x86_64_sext_operand"
421 (and (match_test "GET_MODE (op) != VOIDmode")
422 (match_operand 0 "x86_64_general_operand")))
424 ;; Return true if OP is non-VOIDmode general operand. This predicate
425 ;; is used in sign-extending conversion operations that require
426 ;; non-VOIDmode immediate operands.
427 (define_predicate "sext_operand"
428 (and (match_test "GET_MODE (op) != VOIDmode")
429 (match_operand 0 "general_operand")))
431 ;; Return true if OP is representable on x86_64 as zero-extended operand.
432 ;; This predicate is used in zero-extending conversion operations that
433 ;; require non-VOIDmode immediate operands.
434 (define_predicate "x86_64_zext_operand"
435 (if_then_else (match_test "TARGET_64BIT")
436 (ior (match_operand 0 "nonimmediate_operand")
437 (and (match_operand 0 "x86_64_zext_immediate_operand")
438 (match_test "GET_MODE (op) != VOIDmode")))
439 (match_operand 0 "nonimmediate_operand")))
441 ;; Return true if OP is general operand representable on x86_64
442 ;; as either sign extended or zero extended constant.
443 (define_predicate "x86_64_szext_general_operand"
444 (if_then_else (match_test "TARGET_64BIT")
445 (ior (match_operand 0 "nonimmediate_operand")
446 (match_operand 0 "x86_64_immediate_operand")
447 (match_operand 0 "x86_64_zext_immediate_operand"))
448 (match_operand 0 "general_operand")))
450 ;; Return true if OP is nonmemory operand representable on x86_64.
451 (define_predicate "x86_64_nonmemory_operand"
452 (if_then_else (match_test "TARGET_64BIT")
453 (ior (match_operand 0 "register_operand")
454 (match_operand 0 "x86_64_immediate_operand"))
455 (match_operand 0 "nonmemory_operand")))
457 ;; Return true if OP is nonmemory operand representable on x86_64.
458 (define_predicate "x86_64_szext_nonmemory_operand"
459 (if_then_else (match_test "TARGET_64BIT")
460 (ior (match_operand 0 "register_operand")
461 (match_operand 0 "x86_64_immediate_operand")
462 (match_operand 0 "x86_64_zext_immediate_operand"))
463 (match_operand 0 "nonmemory_operand")))
465 ;; Return true when operand is PIC expression that can be computed by lea
467 (define_predicate "pic_32bit_operand"
468 (match_code "const,symbol_ref,label_ref")
473 /* Rule out relocations that translate into 64bit constants. */
474 if (TARGET_64BIT && GET_CODE (op) == CONST)
477 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
479 if (GET_CODE (op) == UNSPEC
480 && (XINT (op, 1) == UNSPEC_GOTOFF
481 || XINT (op, 1) == UNSPEC_GOT))
485 return symbolic_operand (op, mode);
488 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
489 (define_predicate "x86_64_movabs_operand"
490 (and (match_operand 0 "nonmemory_operand")
491 (not (match_operand 0 "pic_32bit_operand"))))
493 ;; Return true if OP is either a symbol reference or a sum of a symbol
494 ;; reference and a constant.
495 (define_predicate "symbolic_operand"
496 (match_code "symbol_ref,label_ref,const")
498 switch (GET_CODE (op))
506 if (GET_CODE (op) == SYMBOL_REF
507 || GET_CODE (op) == LABEL_REF
508 || (GET_CODE (op) == UNSPEC
509 && (XINT (op, 1) == UNSPEC_GOT
510 || XINT (op, 1) == UNSPEC_GOTOFF
511 || XINT (op, 1) == UNSPEC_PCREL
512 || XINT (op, 1) == UNSPEC_GOTPCREL)))
514 if (GET_CODE (op) != PLUS
515 || !CONST_INT_P (XEXP (op, 1)))
519 if (GET_CODE (op) == SYMBOL_REF
520 || GET_CODE (op) == LABEL_REF)
522 /* Only @GOTOFF gets offsets. */
523 if (GET_CODE (op) != UNSPEC
524 || XINT (op, 1) != UNSPEC_GOTOFF)
527 op = XVECEXP (op, 0, 0);
528 if (GET_CODE (op) == SYMBOL_REF
529 || GET_CODE (op) == LABEL_REF)
538 ;; Return true if OP is a symbolic operand that resolves locally.
539 (define_predicate "local_symbolic_operand"
540 (match_code "const,label_ref,symbol_ref")
542 if (GET_CODE (op) == CONST
543 && GET_CODE (XEXP (op, 0)) == PLUS
544 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
545 op = XEXP (XEXP (op, 0), 0);
547 if (GET_CODE (op) == LABEL_REF)
550 if (GET_CODE (op) != SYMBOL_REF)
553 if (SYMBOL_REF_TLS_MODEL (op))
556 /* Dll-imported symbols are always external. */
557 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
559 if (SYMBOL_REF_LOCAL_P (op))
562 /* There is, however, a not insubstantial body of code in the rest of
563 the compiler that assumes it can just stick the results of
564 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
565 /* ??? This is a hack. Should update the body of the compiler to
566 always create a DECL an invoke targetm.encode_section_info. */
567 if (strncmp (XSTR (op, 0), internal_label_prefix,
568 internal_label_prefix_len) == 0)
574 ;; Test for a legitimate @GOTOFF operand.
576 ;; VxWorks does not impose a fixed gap between segments; the run-time
577 ;; gap can be different from the object-file gap. We therefore can't
578 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
579 ;; same segment as the GOT. Unfortunately, the flexibility of linker
580 ;; scripts means that we can't be sure of that in general, so assume
581 ;; that @GOTOFF is never valid on VxWorks.
582 (define_predicate "gotoff_operand"
583 (and (not (match_test "TARGET_VXWORKS_RTP"))
584 (match_operand 0 "local_symbolic_operand")))
586 ;; Test for various thread-local symbols.
587 (define_special_predicate "tls_symbolic_operand"
588 (and (match_code "symbol_ref")
589 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
591 (define_special_predicate "tls_modbase_operand"
592 (and (match_code "symbol_ref")
593 (match_test "op == ix86_tls_module_base ()")))
595 (define_predicate "tls_address_pattern"
596 (and (match_code "set,parallel,unspec,unspec_volatile")
597 (match_test "ix86_tls_address_pattern_p (op)")))
599 ;; Test for a pc-relative call operand
600 (define_predicate "constant_call_address_operand"
601 (match_code "symbol_ref")
603 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
604 || flag_force_indirect_call)
606 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
611 ;; P6 processors will jump to the address after the decrement when %esp
612 ;; is used as a call operand, so they will execute return address as a code.
613 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
615 (define_predicate "call_register_no_elim_operand"
616 (match_operand 0 "register_operand")
619 op = SUBREG_REG (op);
621 if (!TARGET_64BIT && op == stack_pointer_rtx)
624 return register_no_elim_operand (op, mode);
627 ;; True for any non-virtual or eliminable register. Used in places where
628 ;; instantiation of such a register may cause the pattern to not be recognized.
629 (define_predicate "register_no_elim_operand"
630 (match_operand 0 "register_operand")
633 op = SUBREG_REG (op);
634 return !(op == arg_pointer_rtx
635 || op == frame_pointer_rtx
636 || IN_RANGE (REGNO (op),
637 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
640 ;; Similarly, but include the stack pointer. This is used to prevent esp
641 ;; from being used as an index reg.
642 (define_predicate "index_register_operand"
643 (match_operand 0 "register_operand")
646 op = SUBREG_REG (op);
647 if (reload_completed)
648 return REG_OK_FOR_INDEX_STRICT_P (op);
650 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
653 ;; Return false if this is any eliminable register. Otherwise general_operand.
654 (define_predicate "general_no_elim_operand"
655 (if_then_else (match_code "reg,subreg")
656 (match_operand 0 "register_no_elim_operand")
657 (match_operand 0 "general_operand")))
659 ;; Return false if this is any eliminable register. Otherwise
660 ;; register_operand or a constant.
661 (define_predicate "nonmemory_no_elim_operand"
662 (ior (match_operand 0 "register_no_elim_operand")
663 (match_operand 0 "immediate_operand")))
665 ;; Test for a valid operand for indirect branch.
666 (define_predicate "indirect_branch_operand"
667 (ior (match_operand 0 "register_operand")
668 (and (not (match_test "TARGET_X32"))
669 (match_operand 0 "memory_operand"))))
671 ;; Return true if OP is a memory operands that can be used in sibcalls.
672 ;; Since sibcall never returns, we can only use call-clobbered register
673 ;; as GOT base. Allow GOT slot here only with pseudo register as GOT
674 ;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32
675 ;; and *sibcall_value_GOT_32 patterns.
676 (define_predicate "sibcall_memory_operand"
677 (match_operand 0 "memory_operand")
682 if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0)))
684 int regno = REGNO (XEXP (op, 0));
685 if (!HARD_REGISTER_NUM_P (regno) || call_used_regs[regno])
688 if (GOT32_symbol_operand (op, VOIDmode))
695 ;; Return true if OP is a GOT memory operand.
696 (define_predicate "GOT_memory_operand"
697 (match_operand 0 "memory_operand")
700 return (GET_CODE (op) == CONST
701 && GET_CODE (XEXP (op, 0)) == UNSPEC
702 && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL);
705 ;; Test for a valid operand for a call instruction.
706 ;; Allow constant call address operands in Pmode only.
707 (define_special_predicate "call_insn_operand"
708 (ior (match_test "constant_call_address_operand
709 (op, mode == VOIDmode ? mode : Pmode)")
710 (match_operand 0 "call_register_no_elim_operand")
711 (ior (and (not (match_test "TARGET_X32"))
712 (match_operand 0 "memory_operand"))
713 (and (match_test "TARGET_X32 && Pmode == DImode")
714 (match_operand 0 "GOT_memory_operand")))))
716 ;; Similarly, but for tail calls, in which we cannot allow memory references.
717 (define_special_predicate "sibcall_insn_operand"
718 (ior (match_test "constant_call_address_operand
719 (op, mode == VOIDmode ? mode : Pmode)")
720 (match_operand 0 "register_no_elim_operand")
721 (ior (and (not (match_test "TARGET_X32"))
722 (match_operand 0 "sibcall_memory_operand"))
723 (and (match_test "TARGET_X32 && Pmode == DImode")
724 (match_operand 0 "GOT_memory_operand")))))
726 ;; Return true if OP is a 32-bit GOT symbol operand.
727 (define_predicate "GOT32_symbol_operand"
728 (match_test "GET_CODE (op) == CONST
729 && GET_CODE (XEXP (op, 0)) == UNSPEC
730 && XINT (XEXP (op, 0), 1) == UNSPEC_GOT"))
732 ;; Match exactly zero.
733 (define_predicate "const0_operand"
734 (match_code "const_int,const_double,const_vector")
736 if (mode == VOIDmode)
737 mode = GET_MODE (op);
738 return op == CONST0_RTX (mode);
741 ;; Match one or a vector with all elements equal to one.
742 (define_predicate "const1_operand"
743 (match_code "const_int,const_double,const_vector")
745 if (mode == VOIDmode)
746 mode = GET_MODE (op);
747 return op == CONST1_RTX (mode);
751 (define_predicate "constm1_operand"
752 (and (match_code "const_int")
753 (match_test "op == constm1_rtx")))
755 ;; Match exactly eight.
756 (define_predicate "const8_operand"
757 (and (match_code "const_int")
758 (match_test "INTVAL (op) == 8")))
760 ;; Match exactly 128.
761 (define_predicate "const128_operand"
762 (and (match_code "const_int")
763 (match_test "INTVAL (op) == 128")))
765 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
766 (define_predicate "const_32bit_mask"
767 (and (match_code "const_int")
768 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
769 == (HOST_WIDE_INT) 0xffffffff")))
771 ;; Match 2, 4, or 8. Used for leal multiplicands.
772 (define_predicate "const248_operand"
773 (match_code "const_int")
775 HOST_WIDE_INT i = INTVAL (op);
776 return i == 2 || i == 4 || i == 8;
779 ;; Match 1, 2, or 3. Used for lea shift amounts.
780 (define_predicate "const123_operand"
781 (match_code "const_int")
783 HOST_WIDE_INT i = INTVAL (op);
784 return i == 1 || i == 2 || i == 3;
787 ;; Match 2, 3, 6, or 7
788 (define_predicate "const2367_operand"
789 (match_code "const_int")
791 HOST_WIDE_INT i = INTVAL (op);
792 return i == 2 || i == 3 || i == 6 || i == 7;
795 ;; Match 1, 2, 4, or 8
796 (define_predicate "const1248_operand"
797 (match_code "const_int")
799 HOST_WIDE_INT i = INTVAL (op);
800 return i == 1 || i == 2 || i == 4 || i == 8;
803 ;; Match 3, 5, or 9. Used for leal multiplicands.
804 (define_predicate "const359_operand"
805 (match_code "const_int")
807 HOST_WIDE_INT i = INTVAL (op);
808 return i == 3 || i == 5 || i == 9;
811 ;; Match 4 or 8 to 11. Used for embeded rounding.
812 (define_predicate "const_4_or_8_to_11_operand"
813 (match_code "const_int")
815 HOST_WIDE_INT i = INTVAL (op);
816 return i == 4 || (i >= 8 && i <= 11);
819 ;; Match 4 or 8. Used for SAE.
820 (define_predicate "const48_operand"
821 (match_code "const_int")
823 HOST_WIDE_INT i = INTVAL (op);
824 return i == 4 || i == 8;
828 (define_predicate "const_0_to_1_operand"
829 (and (match_code "const_int")
830 (ior (match_test "op == const0_rtx")
831 (match_test "op == const1_rtx"))))
834 (define_predicate "const_0_to_3_operand"
835 (and (match_code "const_int")
836 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
839 (define_predicate "const_0_to_4_operand"
840 (and (match_code "const_int")
841 (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
844 (define_predicate "const_0_to_5_operand"
845 (and (match_code "const_int")
846 (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
849 (define_predicate "const_0_to_7_operand"
850 (and (match_code "const_int")
851 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
854 (define_predicate "const_0_to_15_operand"
855 (and (match_code "const_int")
856 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
859 (define_predicate "const_0_to_31_operand"
860 (and (match_code "const_int")
861 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
864 (define_predicate "const_0_to_63_operand"
865 (and (match_code "const_int")
866 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
869 (define_predicate "const_0_to_255_operand"
870 (and (match_code "const_int")
871 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
873 ;; Match (0 to 255) * 8
874 (define_predicate "const_0_to_255_mul_8_operand"
875 (match_code "const_int")
877 unsigned HOST_WIDE_INT val = INTVAL (op);
878 return val <= 255*8 && val % 8 == 0;
881 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
882 ;; for shift & compare patterns, as shifting by 0 does not change flags).
883 (define_predicate "const_1_to_31_operand"
884 (and (match_code "const_int")
885 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
887 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
888 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
889 (define_predicate "const_1_to_63_operand"
890 (and (match_code "const_int")
891 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
894 (define_predicate "const_2_to_3_operand"
895 (and (match_code "const_int")
896 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
899 (define_predicate "const_4_to_5_operand"
900 (and (match_code "const_int")
901 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
904 (define_predicate "const_4_to_7_operand"
905 (and (match_code "const_int")
906 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
909 (define_predicate "const_6_to_7_operand"
910 (and (match_code "const_int")
911 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
914 (define_predicate "const_8_to_9_operand"
915 (and (match_code "const_int")
916 (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
919 (define_predicate "const_8_to_11_operand"
920 (and (match_code "const_int")
921 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
924 (define_predicate "const_8_to_15_operand"
925 (and (match_code "const_int")
926 (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
929 (define_predicate "const_10_to_11_operand"
930 (and (match_code "const_int")
931 (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
934 (define_predicate "const_12_to_13_operand"
935 (and (match_code "const_int")
936 (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
939 (define_predicate "const_12_to_15_operand"
940 (and (match_code "const_int")
941 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
944 (define_predicate "const_14_to_15_operand"
945 (and (match_code "const_int")
946 (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
949 (define_predicate "const_16_to_19_operand"
950 (and (match_code "const_int")
951 (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
954 (define_predicate "const_16_to_31_operand"
955 (and (match_code "const_int")
956 (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
959 (define_predicate "const_20_to_23_operand"
960 (and (match_code "const_int")
961 (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
964 (define_predicate "const_24_to_27_operand"
965 (and (match_code "const_int")
966 (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
969 (define_predicate "const_28_to_31_operand"
970 (and (match_code "const_int")
971 (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
973 ;; True if this is a constant appropriate for an increment or decrement.
974 (define_predicate "incdec_operand"
975 (match_code "const_int")
977 /* On Pentium4, the inc and dec operations causes extra dependency on flag
978 registers, since carry flag is not set. */
979 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
981 return op == const1_rtx || op == constm1_rtx;
984 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
985 (define_predicate "reg_or_pm1_operand"
986 (ior (match_operand 0 "register_operand")
987 (and (match_code "const_int")
988 (ior (match_test "op == const1_rtx")
989 (match_test "op == constm1_rtx")))))
991 ;; True if OP is acceptable as operand of DImode shift expander.
992 (define_predicate "shiftdi_operand"
993 (if_then_else (match_test "TARGET_64BIT")
994 (match_operand 0 "nonimmediate_operand")
995 (match_operand 0 "register_operand")))
997 (define_predicate "ashldi_input_operand"
998 (if_then_else (match_test "TARGET_64BIT")
999 (match_operand 0 "nonimmediate_operand")
1000 (match_operand 0 "reg_or_pm1_operand")))
1002 ;; Return true if OP is a vector load from the constant pool with just
1003 ;; the first element nonzero.
1004 (define_predicate "zero_extended_scalar_load_operand"
1008 op = avoid_constant_pool_reference (op);
1010 if (GET_CODE (op) != CONST_VECTOR)
1013 n_elts = CONST_VECTOR_NUNITS (op);
1015 for (n_elts--; n_elts > 0; n_elts--)
1017 rtx elt = CONST_VECTOR_ELT (op, n_elts);
1018 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
1024 /* Return true if operand is a vector constant that is all ones. */
1025 (define_predicate "vector_all_ones_operand"
1026 (and (match_code "const_vector")
1027 (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
1028 (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
1030 ; Return true when OP is operand acceptable for vector memory operand.
1031 ; Only AVX can have misaligned memory operand.
1032 (define_predicate "vector_memory_operand"
1033 (and (match_operand 0 "memory_operand")
1034 (ior (match_test "TARGET_AVX")
1035 (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))))
1037 ; Return true when OP is register_operand or vector_memory_operand.
1038 (define_predicate "vector_operand"
1039 (ior (match_operand 0 "register_operand")
1040 (match_operand 0 "vector_memory_operand")))
1042 ; Return true when OP is operand acceptable for standard SSE move.
1043 (define_predicate "vector_move_operand"
1044 (ior (match_operand 0 "nonimmediate_operand")
1045 (match_operand 0 "const0_operand")))
1047 ;; Return true when OP is either nonimmediate operand, or any
1049 (define_predicate "nonimmediate_or_const_vector_operand"
1050 (ior (match_operand 0 "nonimmediate_operand")
1051 (match_code "const_vector")))
1053 ;; Return true when OP is nonimmediate or standard SSE constant.
1054 (define_predicate "nonimmediate_or_sse_const_operand"
1055 (ior (match_operand 0 "nonimmediate_operand")
1056 (match_test "standard_sse_constant_p (op, mode)")))
1058 ;; Return true if OP is a register or a zero.
1059 (define_predicate "reg_or_0_operand"
1060 (ior (match_operand 0 "register_operand")
1061 (match_operand 0 "const0_operand")))
1063 (define_predicate "norex_memory_operand"
1064 (and (match_operand 0 "memory_operand")
1065 (not (match_test "x86_extended_reg_mentioned_p (op)"))))
1067 ;; Return true for RTX codes that force SImode address.
1068 (define_predicate "SImode_address_operand"
1069 (match_code "subreg,zero_extend,and"))
1071 ;; Return true if op is a valid address for LEA, and does not contain
1072 ;; a segment override. Defined as a special predicate to allow
1073 ;; mode-less const_int operands pass to address_operand.
1074 (define_special_predicate "address_no_seg_operand"
1075 (match_test "address_operand (op, VOIDmode)")
1077 struct ix86_address parts;
1080 if (!CONST_INT_P (op)
1082 && GET_MODE (op) != mode)
1085 ok = ix86_decompose_address (op, &parts);
1087 return parts.seg == ADDR_SPACE_GENERIC;
1090 ;; Return true if op if a valid base register, displacement or
1091 ;; sum of base register and displacement for VSIB addressing.
1092 (define_predicate "vsib_address_operand"
1093 (match_test "address_operand (op, VOIDmode)")
1095 struct ix86_address parts;
1099 ok = ix86_decompose_address (op, &parts);
1101 if (parts.index || parts.seg != ADDR_SPACE_GENERIC)
1104 /* VSIB addressing doesn't support (%rip). */
1108 if (GET_CODE (disp) == CONST)
1110 disp = XEXP (disp, 0);
1111 if (GET_CODE (disp) == PLUS)
1112 disp = XEXP (disp, 0);
1113 if (GET_CODE (disp) == UNSPEC)
1114 switch (XINT (disp, 1))
1116 case UNSPEC_GOTPCREL:
1118 case UNSPEC_GOTNTPOFF:
1124 && (GET_CODE (disp) == SYMBOL_REF
1125 || GET_CODE (disp) == LABEL_REF))
1132 ;; Return true if op is valid MPX address operand without base
1133 (define_predicate "address_mpx_no_base_operand"
1134 (match_test "address_operand (op, VOIDmode)")
1136 struct ix86_address parts;
1139 ok = ix86_decompose_address (op, &parts);
1142 if (parts.index && parts.base)
1145 if (parts.seg != ADDR_SPACE_GENERIC)
1148 /* Do not support (%rip). */
1149 if (parts.disp && flag_pic && TARGET_64BIT
1150 && SYMBOLIC_CONST (parts.disp))
1152 if (GET_CODE (parts.disp) != CONST
1153 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1154 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1155 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1156 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1157 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF))
1164 ;; Return true if op is valid MPX address operand without index
1165 (define_predicate "address_mpx_no_index_operand"
1166 (match_test "address_operand (op, VOIDmode)")
1168 struct ix86_address parts;
1171 ok = ix86_decompose_address (op, &parts);
1177 if (parts.seg != ADDR_SPACE_GENERIC)
1180 /* Do not support (%rip). */
1181 if (parts.disp && flag_pic && TARGET_64BIT
1182 && SYMBOLIC_CONST (parts.disp)
1183 && (GET_CODE (parts.disp) != CONST
1184 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1185 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1186 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1187 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1188 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF)))
1194 (define_predicate "vsib_mem_operator"
1197 (define_predicate "bnd_mem_operator"
1200 ;; Return true if the rtx is known to be at least 32 bits aligned.
1201 (define_predicate "aligned_operand"
1202 (match_operand 0 "general_operand")
1204 struct ix86_address parts;
1207 /* Registers and immediate operands are always "aligned". */
1211 /* All patterns using aligned_operand on memory operands ends up
1212 in promoting memory operand to 64bit and thus causing memory mismatch. */
1213 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1216 /* Don't even try to do any aligned optimizations with volatiles. */
1217 if (MEM_VOLATILE_P (op))
1220 if (MEM_ALIGN (op) >= 32)
1225 /* Pushes and pops are only valid on the stack pointer. */
1226 if (GET_CODE (op) == PRE_DEC
1227 || GET_CODE (op) == POST_INC)
1230 /* Decode the address. */
1231 ok = ix86_decompose_address (op, &parts);
1234 if (parts.base && SUBREG_P (parts.base))
1235 parts.base = SUBREG_REG (parts.base);
1236 if (parts.index && SUBREG_P (parts.index))
1237 parts.index = SUBREG_REG (parts.index);
1239 /* Look for some component that isn't known to be aligned. */
1242 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1247 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1252 if (!CONST_INT_P (parts.disp)
1253 || (INTVAL (parts.disp) & 3))
1257 /* Didn't find one -- this must be an aligned address. */
1261 ;; Return true if OP is memory operand with a displacement.
1262 (define_predicate "memory_displacement_operand"
1263 (match_operand 0 "memory_operand")
1265 struct ix86_address parts;
1268 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1270 return parts.disp != NULL_RTX;
1273 ;; Return true if OP is memory operand with a displacement only.
1274 (define_predicate "memory_displacement_only_operand"
1275 (match_operand 0 "memory_operand")
1277 struct ix86_address parts;
1283 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1286 if (parts.base || parts.index)
1289 return parts.disp != NULL_RTX;
1292 ;; Return true if OP is memory operand that cannot be represented
1293 ;; by the modRM array.
1294 (define_predicate "long_memory_operand"
1295 (and (match_operand 0 "memory_operand")
1296 (match_test "memory_address_length (op, false)")))
1298 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1299 (define_predicate "fcmov_comparison_operator"
1300 (match_operand 0 "comparison_operator")
1302 machine_mode inmode = GET_MODE (XEXP (op, 0));
1303 enum rtx_code code = GET_CODE (op);
1305 if (inmode == CCFPmode)
1307 if (!ix86_trivial_fp_comparison_operator (op, mode))
1309 code = ix86_fp_compare_code_to_integer (code);
1311 /* i387 supports just limited amount of conditional codes. */
1314 case LTU: case GTU: case LEU: case GEU:
1315 if (inmode == CCmode || inmode == CCFPmode || inmode == CCCmode)
1318 case ORDERED: case UNORDERED:
1326 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1327 ;; The first set are supported directly; the second set can't be done with
1328 ;; full IEEE support, i.e. NaNs.
1330 (define_predicate "sse_comparison_operator"
1331 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1332 (and (match_test "TARGET_AVX")
1333 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1335 (define_predicate "ix86_comparison_int_operator"
1336 (match_code "ne,eq,ge,gt,le,lt"))
1338 (define_predicate "ix86_comparison_uns_operator"
1339 (match_code "ne,eq,geu,gtu,leu,ltu"))
1341 (define_predicate "bt_comparison_operator"
1342 (match_code "ne,eq"))
1344 ;; Return true if OP is a valid comparison operator in valid mode.
1345 (define_predicate "ix86_comparison_operator"
1346 (match_operand 0 "comparison_operator")
1348 machine_mode inmode = GET_MODE (XEXP (op, 0));
1349 enum rtx_code code = GET_CODE (op);
1351 if (inmode == CCFPmode)
1352 return ix86_trivial_fp_comparison_operator (op, mode);
1357 if (inmode == CCGZmode)
1361 if (inmode == CCmode || inmode == CCGCmode
1362 || inmode == CCGOCmode || inmode == CCNOmode || inmode == CCGZmode)
1366 if (inmode == CCGZmode)
1370 if (inmode == CCmode || inmode == CCCmode || inmode == CCGZmode)
1373 case ORDERED: case UNORDERED:
1374 if (inmode == CCmode)
1378 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1386 ;; Return true if OP is a valid comparison operator
1387 ;; testing carry flag to be set.
1388 (define_predicate "ix86_carry_flag_operator"
1389 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1391 machine_mode inmode = GET_MODE (XEXP (op, 0));
1392 enum rtx_code code = GET_CODE (op);
1394 if (inmode == CCFPmode)
1396 if (!ix86_trivial_fp_comparison_operator (op, mode))
1398 code = ix86_fp_compare_code_to_integer (code);
1400 else if (inmode == CCCmode)
1401 return code == LTU || code == GTU;
1402 else if (inmode != CCmode)
1408 ;; Return true if this comparison only requires testing one flag bit.
1409 (define_predicate "ix86_trivial_fp_comparison_operator"
1410 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1412 ;; Return true if we know how to do this comparison. Others require
1413 ;; testing more than one flag bit, and we let the generic middle-end
1415 (define_predicate "ix86_fp_comparison_operator"
1416 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1417 == IX86_FPCMP_ARITH")
1418 (match_operand 0 "comparison_operator")
1419 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1421 ;; Nearly general operand, but accept any const_double, since we wish
1422 ;; to be able to drop them into memory rather than have them get pulled
1424 (define_predicate "cmp_fp_expander_operand"
1425 (ior (match_code "const_double")
1426 (match_operand 0 "general_operand")))
1428 ;; Return true if this is a valid binary floating-point operation.
1429 (define_predicate "binary_fp_operator"
1430 (match_code "plus,minus,mult,div"))
1432 ;; Return true if this is a multiply operation.
1433 (define_predicate "mult_operator"
1434 (match_code "mult"))
1436 ;; Return true if this is a division operation.
1437 (define_predicate "div_operator"
1440 ;; Return true if this is a plus, minus, and, ior or xor operation.
1441 (define_predicate "plusminuslogic_operator"
1442 (match_code "plus,minus,and,ior,xor"))
1444 ;; Return true for ARITHMETIC_P.
1445 (define_predicate "arith_or_logical_operator"
1446 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1447 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1449 ;; Return true for COMMUTATIVE_P.
1450 (define_predicate "commutative_operator"
1451 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1453 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1454 (define_predicate "promotable_binary_operator"
1455 (ior (match_code "plus,minus,and,ior,xor,ashift")
1456 (and (match_code "mult")
1457 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1459 (define_predicate "compare_operator"
1460 (match_code "compare"))
1462 (define_predicate "absneg_operator"
1463 (match_code "abs,neg"))
1465 ;; Return true if OP is a memory operand, aligned to
1466 ;; less than its natural alignment.
1467 (define_predicate "misaligned_operand"
1468 (and (match_code "mem")
1469 (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)")))
1471 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1472 (define_predicate "emms_operation"
1473 (match_code "parallel")
1477 if (XVECLEN (op, 0) != 17)
1480 for (i = 0; i < 8; i++)
1482 rtx elt = XVECEXP (op, 0, i+1);
1484 if (GET_CODE (elt) != CLOBBER
1485 || GET_CODE (SET_DEST (elt)) != REG
1486 || GET_MODE (SET_DEST (elt)) != XFmode
1487 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1490 elt = XVECEXP (op, 0, i+9);
1492 if (GET_CODE (elt) != CLOBBER
1493 || GET_CODE (SET_DEST (elt)) != REG
1494 || GET_MODE (SET_DEST (elt)) != DImode
1495 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1501 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1502 (define_predicate "vzeroall_operation"
1503 (match_code "parallel")
1505 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1507 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1510 for (i = 0; i < nregs; i++)
1512 rtx elt = XVECEXP (op, 0, i+1);
1514 if (GET_CODE (elt) != SET
1515 || GET_CODE (SET_DEST (elt)) != REG
1516 || GET_MODE (SET_DEST (elt)) != V8SImode
1517 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1518 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1524 ;; return true if OP is a vzeroupper operation.
1525 (define_predicate "vzeroupper_operation"
1526 (and (match_code "unspec_volatile")
1527 (match_test "XINT (op, 1) == UNSPECV_VZEROUPPER")))
1529 ;; Return true if OP is an addsub vec_merge operation
1530 (define_predicate "addsub_vm_operator"
1531 (match_code "vec_merge")
1542 if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1544 else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1549 mask = INTVAL (XEXP (op, 2));
1550 nunits = GET_MODE_NUNITS (mode);
1552 for (elt = 0; elt < nunits; elt++)
1554 /* bit clear: take from op0, set: take from op1 */
1555 int bit = !(mask & (HOST_WIDE_INT_1U << elt));
1557 if (bit != ((elt & 1) ^ swapped))
1564 ;; Return true if OP is an addsub vec_select/vec_concat operation
1565 (define_predicate "addsub_vs_operator"
1566 (and (match_code "vec_select")
1567 (match_code "vec_concat" "0"))
1573 op0 = XEXP (XEXP (op, 0), 0);
1574 op1 = XEXP (XEXP (op, 0), 1);
1577 if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1579 else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1584 nunits = GET_MODE_NUNITS (mode);
1585 if (XVECLEN (XEXP (op, 1), 0) != nunits)
1588 /* We already checked that permutation is suitable for addsub,
1589 so only look at the first element of the parallel. */
1590 elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0));
1592 return elt == (swapped ? nunits : 0);
1595 ;; Return true if OP is a parallel for an addsub vec_select.
1596 (define_predicate "addsub_vs_parallel"
1597 (and (match_code "parallel")
1598 (match_code "const_int" "a"))
1600 int nelt = XVECLEN (op, 0);
1606 /* Check that the permutation is suitable for addsub.
1607 For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */
1608 elt = INTVAL (XVECEXP (op, 0, 0));
1611 for (i = 1; i < nelt; ++i)
1612 if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt))
1615 else if (elt == nelt)
1617 for (i = 1; i < nelt; ++i)
1618 if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt))
1627 ;; Return true if OP is a parallel for a vbroadcast permute.
1628 (define_predicate "avx_vbroadcast_operand"
1629 (and (match_code "parallel")
1630 (match_code "const_int" "a"))
1632 rtx elt = XVECEXP (op, 0, 0);
1633 int i, nelt = XVECLEN (op, 0);
1635 /* Don't bother checking there are the right number of operands,
1636 merely that they're all identical. */
1637 for (i = 1; i < nelt; ++i)
1638 if (XVECEXP (op, 0, i) != elt)
1643 ;; Return true if OP is a parallel for a palignr permute.
1644 (define_predicate "palignr_operand"
1645 (and (match_code "parallel")
1646 (match_code "const_int" "a"))
1648 int elt = INTVAL (XVECEXP (op, 0, 0));
1649 int i, nelt = XVECLEN (op, 0);
1651 /* Check that an order in the permutation is suitable for palignr.
1652 For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
1653 for (i = 1; i < nelt; ++i)
1654 if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
1659 ;; Return true if OP is a proper third operand to vpblendw256.
1660 (define_predicate "avx2_pblendw_operand"
1661 (match_code "const_int")
1663 HOST_WIDE_INT val = INTVAL (op);
1664 HOST_WIDE_INT low = val & 0xff;
1665 return val == ((low << 8) | low);
1668 ;; Return true if OP is vector_operand or CONST_VECTOR.
1669 (define_predicate "general_vector_operand"
1670 (ior (match_operand 0 "vector_operand")
1671 (match_code "const_vector")))
1673 ;; Return true if OP is either -1 constant or stored in register.
1674 (define_predicate "register_or_constm1_operand"
1675 (ior (match_operand 0 "register_operand")
1676 (and (match_code "const_int")
1677 (match_test "op == constm1_rtx"))))
1679 ;; Return true if the vector ends with between 12 and 18 register saves using
1680 ;; RAX as the base address.
1681 (define_predicate "save_multiple"
1682 (match_code "parallel")
1684 const unsigned len = XVECLEN (op, 0);
1687 /* Starting from end of vector, count register saves. */
1688 for (i = 0; i < len; ++i)
1690 rtx src, dest, addr;
1691 rtx e = XVECEXP (op, 0, len - 1 - i);
1693 if (GET_CODE (e) != SET)
1697 dest = SET_DEST (e);
1699 if (!REG_P (src) || !MEM_P (dest))
1702 addr = XEXP (dest, 0);
1704 /* Good if dest address is in RAX. */
1705 if (REG_P (addr) && REGNO (addr) == AX_REG)
1708 /* Good if dest address is offset of RAX. */
1709 if (GET_CODE (addr) == PLUS
1710 && REG_P (XEXP (addr, 0))
1711 && REGNO (XEXP (addr, 0)) == AX_REG)
1716 return (i >= 12 && i <= 18);
1720 ;; Return true if the vector ends with between 12 and 18 register loads using
1721 ;; RSI as the base address.
1722 (define_predicate "restore_multiple"
1723 (match_code "parallel")
1725 const unsigned len = XVECLEN (op, 0);
1728 /* Starting from end of vector, count register restores. */
1729 for (i = 0; i < len; ++i)
1731 rtx src, dest, addr;
1732 rtx e = XVECEXP (op, 0, len - 1 - i);
1734 if (GET_CODE (e) != SET)
1738 dest = SET_DEST (e);
1740 if (!MEM_P (src) || !REG_P (dest))
1743 addr = XEXP (src, 0);
1745 /* Good if src address is in RSI. */
1746 if (REG_P (addr) && REGNO (addr) == SI_REG)
1749 /* Good if src address is offset of RSI. */
1750 if (GET_CODE (addr) == PLUS
1751 && REG_P (XEXP (addr, 0))
1752 && REGNO (XEXP (addr, 0)) == SI_REG)
1757 return (i >= 12 && i <= 18);