1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
35 #include "rtl-error.h"
37 #include "addresses.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 struct target_reload default_target_reload
;
81 struct target_reload
*this_target_reload
= &default_target_reload
;
84 #define spill_indirect_levels \
85 (this_target_reload->x_spill_indirect_levels)
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx
*reg_last_reload_reg
;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static regset_head reg_has_output_reload
;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload
;
99 /* Widest width in which each pseudo reg is referred to (via subreg). */
100 static unsigned int *reg_max_ref_width
;
102 /* Vector to remember old contents of reg_renumber before spilling. */
103 static short *reg_old_renumber
;
105 /* During reload_as_needed, element N contains the last pseudo regno reloaded
106 into hard register N. If that pseudo reg occupied more than one register,
107 reg_reloaded_contents points to that pseudo for each spill register in
108 use; all of these must remain set for an inheritance to occur. */
109 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
111 /* During reload_as_needed, element N contains the insn for which
112 hard register N was last used. Its contents are significant only
113 when reg_reloaded_valid is set for this register. */
114 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
116 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
117 static HARD_REG_SET reg_reloaded_valid
;
118 /* Indicate if the register was dead at the end of the reload.
119 This is only valid if reg_reloaded_contents is set and valid. */
120 static HARD_REG_SET reg_reloaded_dead
;
122 /* Indicate whether the register's current value is one that is not
123 safe to retain across a call, even for registers that are normally
124 call-saved. This is only meaningful for members of reg_reloaded_valid. */
125 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
127 /* Number of spill-regs so far; number of valid elements of spill_regs. */
130 /* In parallel with spill_regs, contains REG rtx's for those regs.
131 Holds the last rtx used for any given reg, or 0 if it has never
132 been used for spilling yet. This rtx is reused, provided it has
134 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
136 /* In parallel with spill_regs, contains nonzero for a spill reg
137 that was stored after the last time it was used.
138 The precise value is the insn generated to do the store. */
139 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
141 /* This is the register that was stored with spill_reg_store. This is a
142 copy of reload_out / reload_out_reg when the value was stored; if
143 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
144 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs.
151 ?!? This is no longer accurate. */
152 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
154 /* This reg set indicates registers that can't be used as spill registers for
155 the currently processed insn. These are the hard registers which are live
156 during the insn, but not allocated to pseudos, as well as fixed
158 static HARD_REG_SET bad_spill_regs
;
160 /* These are the hard registers that can't be used as spill register for any
161 insn. This includes registers used for user variables and registers that
162 we can't eliminate. A register that appears in this set also can't be used
163 to retry register allocation. */
164 static HARD_REG_SET bad_spill_regs_global
;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `n_spills' is the number of
168 elements that are actually valid; new ones are added at the end.
170 Both spill_regs and spill_reg_order are used on two occasions:
171 once during find_reload_regs, where they keep track of the spill registers
172 for a single insn, but also during reload_as_needed where they show all
173 the registers ever used by reload. For the latter case, the information
174 is calculated during finish_spills. */
175 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
177 /* This vector of reg sets indicates, for each pseudo, which hard registers
178 may not be used for retrying global allocation because the register was
179 formerly spilled from one of them. If we allowed reallocating a pseudo to
180 a register that it was already allocated to, reload might not
182 static HARD_REG_SET
*pseudo_previous_regs
;
184 /* This vector of reg sets indicates, for each pseudo, which hard
185 registers may not be used for retrying global allocation because they
186 are used as spill registers during one of the insns in which the
188 static HARD_REG_SET
*pseudo_forbidden_regs
;
190 /* All hard regs that have been used as spill registers for any insn are
191 marked in this set. */
192 static HARD_REG_SET used_spill_regs
;
194 /* Index of last register assigned as a spill register. We allocate in
195 a round-robin fashion. */
196 static int last_spill_reg
;
198 /* Record the stack slot for each spilled hard register. */
199 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
201 /* Width allocated so far for that stack slot. */
202 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
204 /* Record which pseudos needed to be spilled. */
205 static regset_head spilled_pseudos
;
207 /* Record which pseudos changed their allocation in finish_spills. */
208 static regset_head changed_allocation_pseudos
;
210 /* Used for communication between order_regs_for_reload and count_pseudo.
211 Used to avoid counting one pseudo twice. */
212 static regset_head pseudos_counted
;
214 /* First uid used by insns created by reload in this function.
215 Used in find_equiv_reg. */
216 int reload_first_uid
;
218 /* Flag set by local-alloc or global-alloc if anything is live in
219 a call-clobbered reg across calls. */
220 int caller_save_needed
;
222 /* Set to 1 while reload_as_needed is operating.
223 Required by some machines to handle any generated moves differently. */
224 int reload_in_progress
= 0;
226 /* This obstack is used for allocation of rtl during register elimination.
227 The allocated storage can be freed once find_reloads has processed the
229 static struct obstack reload_obstack
;
231 /* Points to the beginning of the reload_obstack. All insn_chain structures
232 are allocated first. */
233 static char *reload_startobj
;
235 /* The point after all insn_chain structures. Used to quickly deallocate
236 memory allocated in copy_reloads during calculate_needs_all_insns. */
237 static char *reload_firstobj
;
239 /* This points before all local rtl generated by register elimination.
240 Used to quickly free all memory after processing one insn. */
241 static char *reload_insn_firstobj
;
243 /* List of insn_chain instructions, one for every insn that reload needs to
245 struct insn_chain
*reload_insn_chain
;
247 /* TRUE if we potentially left dead insns in the insn stream and want to
248 run DCE immediately after reload, FALSE otherwise. */
249 static bool need_dce
;
251 /* List of all insns needing reloads. */
252 static struct insn_chain
*insns_need_reload
;
254 /* This structure is used to record information about register eliminations.
255 Each array entry describes one possible way of eliminating a register
256 in favor of another. If there is more than one way of eliminating a
257 particular register, the most preferred should be specified first. */
261 int from
; /* Register number to be eliminated. */
262 int to
; /* Register number used as replacement. */
263 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
264 int can_eliminate
; /* Nonzero if this elimination can be done. */
265 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
266 target hook in previous scan over insns
268 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
269 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
270 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
271 rtx from_rtx
; /* REG rtx for the register to be eliminated.
272 We cannot simply compare the number since
273 we might then spuriously replace a hard
274 register corresponding to a pseudo
275 assigned to the reg to be eliminated. */
276 rtx to_rtx
; /* REG rtx for the replacement. */
279 static struct elim_table
*reg_eliminate
= 0;
281 /* This is an intermediate structure to initialize the table. It has
282 exactly the members provided by ELIMINABLE_REGS. */
283 static const struct elim_table_1
287 } reg_eliminate_1
[] =
289 /* If a set of eliminable registers was specified, define the table from it.
290 Otherwise, default to the normal case of the frame pointer being
291 replaced by the stack pointer. */
293 #ifdef ELIMINABLE_REGS
296 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
299 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
301 /* Record the number of pending eliminations that have an offset not equal
302 to their initial offset. If nonzero, we use a new copy of each
303 replacement result in any insns encountered. */
304 int num_not_at_initial_offset
;
306 /* Count the number of registers that we may be able to eliminate. */
307 static int num_eliminable
;
308 /* And the number of registers that are equivalent to a constant that
309 can be eliminated to frame_pointer / arg_pointer + constant. */
310 static int num_eliminable_invariants
;
312 /* For each label, we record the offset of each elimination. If we reach
313 a label by more than one path and an offset differs, we cannot do the
314 elimination. This information is indexed by the difference of the
315 number of the label and the first label number. We can't offset the
316 pointer itself as this can cause problems on machines with segmented
317 memory. The first table is an array of flags that records whether we
318 have yet encountered a label and the second table is an array of arrays,
319 one entry in the latter array for each elimination. */
321 static int first_label_num
;
322 static char *offsets_known_at
;
323 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
325 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
327 /* Stack of addresses where an rtx has been changed. We can undo the
328 changes by popping items off the stack and restoring the original
329 value at each location.
331 We use this simplistic undo capability rather than copy_rtx as copy_rtx
332 will not make a deep copy of a normally sharable rtx, such as
333 (const (plus (symbol_ref) (const_int))). If such an expression appears
334 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
335 rtx expression would be changed. See PR 42431. */
338 static vec
<rtx_p
> substitute_stack
;
340 /* Number of labels in the current function. */
342 static int num_labels
;
344 static void replace_pseudos_in (rtx
*, machine_mode
, rtx
);
345 static void maybe_fix_stack_asms (void);
346 static void copy_reloads (struct insn_chain
*);
347 static void calculate_needs_all_insns (int);
348 static int find_reg (struct insn_chain
*, int);
349 static void find_reload_regs (struct insn_chain
*);
350 static void select_reload_regs (void);
351 static void delete_caller_save_insns (void);
353 static void spill_failure (rtx_insn
*, enum reg_class
);
354 static void count_spilled_pseudo (int, int, int);
355 static void delete_dead_insn (rtx_insn
*);
356 static void alter_reg (int, int, bool);
357 static void set_label_offsets (rtx
, rtx_insn
*, int);
358 static void check_eliminable_occurrences (rtx
);
359 static void elimination_effects (rtx
, machine_mode
);
360 static rtx
eliminate_regs_1 (rtx
, machine_mode
, rtx
, bool, bool);
361 static int eliminate_regs_in_insn (rtx_insn
*, int);
362 static void update_eliminable_offsets (void);
363 static void mark_not_eliminable (rtx
, const_rtx
, void *);
364 static void set_initial_elim_offsets (void);
365 static bool verify_initial_elim_offsets (void);
366 static void set_initial_label_offsets (void);
367 static void set_offsets_for_label (rtx_insn
*);
368 static void init_eliminable_invariants (rtx_insn
*, bool);
369 static void init_elim_table (void);
370 static void free_reg_equiv (void);
371 static void update_eliminables (HARD_REG_SET
*);
372 static bool update_eliminables_and_spill (void);
373 static void elimination_costs_in_insn (rtx_insn
*);
374 static void spill_hard_reg (unsigned int, int);
375 static int finish_spills (int);
376 static void scan_paradoxical_subregs (rtx
);
377 static void count_pseudo (int);
378 static void order_regs_for_reload (struct insn_chain
*);
379 static void reload_as_needed (int);
380 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
381 static void forget_marked_reloads (regset
);
382 static int reload_reg_class_lower (const void *, const void *);
383 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
385 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
387 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
388 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
390 static int free_for_value_p (int, machine_mode
, int, enum reload_type
,
392 static int allocate_reload_reg (struct insn_chain
*, int, int);
393 static int conflicts_with_override (rtx
);
394 static void failed_reload (rtx_insn
*, int);
395 static int set_reload_reg (int, int);
396 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
397 static void choose_reload_regs (struct insn_chain
*);
398 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
400 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
402 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
403 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
404 static void emit_reload_insns (struct insn_chain
*);
405 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
406 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
407 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
408 static void inc_for_reload (rtx
, rtx
, rtx
, int);
409 static void add_auto_inc_notes (rtx_insn
*, rtx
);
410 static void substitute (rtx
*, const_rtx
, rtx
);
411 static bool gen_reload_chain_without_interm_reg_p (int, int);
412 static int reloads_conflict (int, int);
413 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
414 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
416 /* Initialize the reload pass. This is called at the beginning of compilation
417 and may be called again if the target is reinitialized. */
424 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
425 Set spill_indirect_levels to the number of levels such addressing is
426 permitted, zero if it is not permitted at all. */
429 = gen_rtx_MEM (Pmode
,
432 LAST_VIRTUAL_REGISTER
+ 1),
433 gen_int_mode (4, Pmode
)));
434 spill_indirect_levels
= 0;
436 while (memory_address_p (QImode
, tem
))
438 spill_indirect_levels
++;
439 tem
= gen_rtx_MEM (Pmode
, tem
);
442 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
444 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
445 indirect_symref_ok
= memory_address_p (QImode
, tem
);
447 /* See if reg+reg is a valid (and offsettable) address. */
449 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
451 tem
= gen_rtx_PLUS (Pmode
,
452 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
453 gen_rtx_REG (Pmode
, i
));
455 /* This way, we make sure that reg+reg is an offsettable address. */
456 tem
= plus_constant (Pmode
, tem
, 4);
458 if (memory_address_p (QImode
, tem
))
460 double_reg_address_ok
= 1;
465 /* Initialize obstack for our rtl allocation. */
466 if (reload_startobj
== NULL
)
468 gcc_obstack_init (&reload_obstack
);
469 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
472 INIT_REG_SET (&spilled_pseudos
);
473 INIT_REG_SET (&changed_allocation_pseudos
);
474 INIT_REG_SET (&pseudos_counted
);
477 /* List of insn chains that are currently unused. */
478 static struct insn_chain
*unused_insn_chains
= 0;
480 /* Allocate an empty insn_chain structure. */
482 new_insn_chain (void)
484 struct insn_chain
*c
;
486 if (unused_insn_chains
== 0)
488 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
489 INIT_REG_SET (&c
->live_throughout
);
490 INIT_REG_SET (&c
->dead_or_set
);
494 c
= unused_insn_chains
;
495 unused_insn_chains
= c
->next
;
497 c
->is_caller_save_insn
= 0;
498 c
->need_operand_change
= 0;
504 /* Small utility function to set all regs in hard reg set TO which are
505 allocated to pseudos in regset FROM. */
508 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
511 reg_set_iterator rsi
;
513 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
515 int r
= reg_renumber
[regno
];
519 /* reload_combine uses the information from DF_LIVE_IN,
520 which might still contain registers that have not
521 actually been allocated since they have an
523 gcc_assert (ira_conflicts_p
|| reload_completed
);
526 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
530 /* Replace all pseudos found in LOC with their corresponding
534 replace_pseudos_in (rtx
*loc
, machine_mode mem_mode
, rtx usage
)
547 unsigned int regno
= REGNO (x
);
549 if (regno
< FIRST_PSEUDO_REGISTER
)
552 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
556 replace_pseudos_in (loc
, mem_mode
, usage
);
560 if (reg_equiv_constant (regno
))
561 *loc
= reg_equiv_constant (regno
);
562 else if (reg_equiv_invariant (regno
))
563 *loc
= reg_equiv_invariant (regno
);
564 else if (reg_equiv_mem (regno
))
565 *loc
= reg_equiv_mem (regno
);
566 else if (reg_equiv_address (regno
))
567 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
570 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
571 || REGNO (regno_reg_rtx
[regno
]) != regno
);
572 *loc
= regno_reg_rtx
[regno
];
577 else if (code
== MEM
)
579 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
583 /* Process each of our operands recursively. */
584 fmt
= GET_RTX_FORMAT (code
);
585 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
587 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
588 else if (*fmt
== 'E')
589 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
590 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
593 /* Determine if the current function has an exception receiver block
594 that reaches the exit block via non-exceptional edges */
597 has_nonexceptional_receiver (void)
601 basic_block
*tos
, *worklist
, bb
;
603 /* If we're not optimizing, then just err on the safe side. */
607 /* First determine which blocks can reach exit via normal paths. */
608 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
610 FOR_EACH_BB_FN (bb
, cfun
)
611 bb
->flags
&= ~BB_REACHABLE
;
613 /* Place the exit block on our worklist. */
614 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
615 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
617 /* Iterate: find everything reachable from what we've already seen. */
618 while (tos
!= worklist
)
622 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
623 if (!(e
->flags
& EDGE_ABNORMAL
))
625 basic_block src
= e
->src
;
627 if (!(src
->flags
& BB_REACHABLE
))
629 src
->flags
|= BB_REACHABLE
;
636 /* Now see if there's a reachable block with an exceptional incoming
638 FOR_EACH_BB_FN (bb
, cfun
)
639 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
642 /* No exceptional block reached exit unexceptionally. */
646 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
647 zero elements) to MAX_REG_NUM elements.
649 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
651 grow_reg_equivs (void)
653 int old_size
= vec_safe_length (reg_equivs
);
654 int max_regno
= max_reg_num ();
658 memset (&ze
, 0, sizeof (reg_equivs_t
));
659 vec_safe_reserve (reg_equivs
, max_regno
);
660 for (i
= old_size
; i
< max_regno
; i
++)
661 reg_equivs
->quick_insert (i
, ze
);
665 /* Global variables used by reload and its subroutines. */
667 /* The current basic block while in calculate_elim_costs_all_insns. */
668 static basic_block elim_bb
;
670 /* Set during calculate_needs if an insn needs register elimination. */
671 static int something_needs_elimination
;
672 /* Set during calculate_needs if an insn needs an operand changed. */
673 static int something_needs_operands_changed
;
674 /* Set by alter_regs if we spilled a register to the stack. */
675 static bool something_was_spilled
;
677 /* Nonzero means we couldn't get enough spill regs. */
680 /* Temporary array of pseudo-register number. */
681 static int *temp_pseudo_reg_arr
;
683 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
684 If that insn didn't set the register (i.e., it copied the register to
685 memory), just delete that insn instead of the equivalencing insn plus
686 anything now dead. If we call delete_dead_insn on that insn, we may
687 delete the insn that actually sets the register if the register dies
688 there and that is incorrect. */
692 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
694 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
697 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
699 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
701 /* If we already deleted the insn or if it may trap, we can't
702 delete it. The latter case shouldn't happen, but can
703 if an insn has a variable address, gets a REG_EH_REGION
704 note added to it, and then gets converted into a load
705 from a constant address. */
706 if (NOTE_P (equiv_insn
)
707 || can_throw_internal (equiv_insn
))
709 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
710 delete_dead_insn (equiv_insn
);
712 SET_INSN_DELETED (equiv_insn
);
718 /* Return true if remove_init_insns will delete INSN. */
720 will_delete_init_insn_p (rtx_insn
*insn
)
722 rtx set
= single_set (insn
);
723 if (!set
|| !REG_P (SET_DEST (set
)))
725 unsigned regno
= REGNO (SET_DEST (set
));
727 if (can_throw_internal (insn
))
730 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
733 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
735 rtx equiv_insn
= XEXP (list
, 0);
736 if (equiv_insn
== insn
)
742 /* Main entry point for the reload pass.
744 FIRST is the first insn of the function being compiled.
746 GLOBAL nonzero means we were called from global_alloc
747 and should attempt to reallocate any pseudoregs that we
748 displace from hard regs we will use for reloads.
749 If GLOBAL is zero, we do not have enough information to do that,
750 so any pseudo reg that is spilled must go to the stack.
752 Return value is TRUE if reload likely left dead insns in the
753 stream and a DCE pass should be run to elimiante them. Else the
754 return value is FALSE. */
757 reload (rtx_insn
*first
, int global
)
761 struct elim_table
*ep
;
765 /* Make sure even insns with volatile mem refs are recognizable. */
770 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
772 /* Make sure that the last insn in the chain
773 is not something that needs reloading. */
774 emit_note (NOTE_INSN_DELETED
);
776 /* Enable find_equiv_reg to distinguish insns made by reload. */
777 reload_first_uid
= get_max_uid ();
779 #ifdef SECONDARY_MEMORY_NEEDED
780 /* Initialize the secondary memory table. */
781 clear_secondary_mem ();
784 /* We don't have a stack slot for any spill reg yet. */
785 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
786 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
788 /* Initialize the save area information for caller-save, in case some
792 /* Compute which hard registers are now in use
793 as homes for pseudo registers.
794 This is done here rather than (eg) in global_alloc
795 because this point is reached even if not optimizing. */
796 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
799 /* A function that has a nonlocal label that can reach the exit
800 block via non-exceptional paths must save all call-saved
802 if (cfun
->has_nonlocal_label
803 && has_nonexceptional_receiver ())
804 crtl
->saves_all_registers
= 1;
806 if (crtl
->saves_all_registers
)
807 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
808 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
809 df_set_regs_ever_live (i
, true);
811 /* Find all the pseudo registers that didn't get hard regs
812 but do have known equivalent constants or memory slots.
813 These include parameters (known equivalent to parameter slots)
814 and cse'd or loop-moved constant memory addresses.
816 Record constant equivalents in reg_equiv_constant
817 so they will be substituted by find_reloads.
818 Record memory equivalents in reg_mem_equiv so they can
819 be substituted eventually by altering the REG-rtx's. */
822 reg_old_renumber
= XCNEWVEC (short, max_regno
);
823 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
824 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
825 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
827 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
829 init_eliminable_invariants (first
, true);
832 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
833 stack slots to the pseudos that lack hard regs or equivalents.
834 Do not touch virtual registers. */
836 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
837 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
838 temp_pseudo_reg_arr
[n
++] = i
;
841 /* Ask IRA to order pseudo-registers for better stack slot
843 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
845 for (i
= 0; i
< n
; i
++)
846 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
848 /* If we have some registers we think can be eliminated, scan all insns to
849 see if there is an insn that sets one of these registers to something
850 other than itself plus a constant. If so, the register cannot be
851 eliminated. Doing this scan here eliminates an extra pass through the
852 main reload loop in the most common case where register elimination
854 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
856 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
858 maybe_fix_stack_asms ();
860 insns_need_reload
= 0;
861 something_needs_elimination
= 0;
863 /* Initialize to -1, which means take the first spill register. */
866 /* Spill any hard regs that we know we can't eliminate. */
867 CLEAR_HARD_REG_SET (used_spill_regs
);
868 /* There can be multiple ways to eliminate a register;
869 they should be listed adjacently.
870 Elimination for any register fails only if all possible ways fail. */
871 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
874 int can_eliminate
= 0;
877 can_eliminate
|= ep
->can_eliminate
;
880 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
882 spill_hard_reg (from
, 1);
885 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
)
886 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
888 finish_spills (global
);
890 /* From now on, we may need to generate moves differently. We may also
891 allow modifications of insns which cause them to not be recognized.
892 Any such modifications will be cleaned up during reload itself. */
893 reload_in_progress
= 1;
895 /* This loop scans the entire function each go-round
896 and repeats until one repetition spills no additional hard regs. */
899 int something_changed
;
900 HOST_WIDE_INT starting_frame_size
;
902 starting_frame_size
= get_frame_size ();
903 something_was_spilled
= false;
905 set_initial_elim_offsets ();
906 set_initial_label_offsets ();
908 /* For each pseudo register that has an equivalent location defined,
909 try to eliminate any eliminable registers (such as the frame pointer)
910 assuming initial offsets for the replacement register, which
913 If the resulting location is directly addressable, substitute
914 the MEM we just got directly for the old REG.
916 If it is not addressable but is a constant or the sum of a hard reg
917 and constant, it is probably not addressable because the constant is
918 out of range, in that case record the address; we will generate
919 hairy code to compute the address in a register each time it is
920 needed. Similarly if it is a hard register, but one that is not
921 valid as an address register.
923 If the location is not addressable, but does not have one of the
924 above forms, assign a stack slot. We have to do this to avoid the
925 potential of producing lots of reloads if, e.g., a location involves
926 a pseudo that didn't get a hard register and has an equivalent memory
927 location that also involves a pseudo that didn't get a hard register.
929 Perhaps at some point we will improve reload_when_needed handling
930 so this problem goes away. But that's very hairy. */
932 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
933 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
935 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
938 if (strict_memory_address_addr_space_p
939 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
941 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
942 else if (CONSTANT_P (XEXP (x
, 0))
943 || (REG_P (XEXP (x
, 0))
944 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
945 || (GET_CODE (XEXP (x
, 0)) == PLUS
946 && REG_P (XEXP (XEXP (x
, 0), 0))
947 && (REGNO (XEXP (XEXP (x
, 0), 0))
948 < FIRST_PSEUDO_REGISTER
)
949 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
950 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
953 /* Make a new stack slot. Then indicate that something
954 changed so we go back and recompute offsets for
955 eliminable registers because the allocation of memory
956 below might change some offset. reg_equiv_{mem,address}
957 will be set up for this pseudo on the next pass around
959 reg_equiv_memory_loc (i
) = 0;
960 reg_equiv_init (i
) = 0;
961 alter_reg (i
, -1, true);
965 if (caller_save_needed
)
968 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
970 /* If we have a stack frame, we must align it now. The
971 stack size may be a part of the offset computation for
972 register elimination. So if this changes the stack size,
973 then repeat the elimination bookkeeping. We don't
974 realign when there is no stack, as that will cause a
975 stack frame when none is needed should
976 STARTING_FRAME_OFFSET not be already aligned to
978 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
980 /* If we allocated another stack slot, redo elimination bookkeeping. */
981 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
983 if (update_eliminables_and_spill ())
988 if (caller_save_needed
)
990 save_call_clobbered_regs ();
991 /* That might have allocated new insn_chain structures. */
992 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
995 calculate_needs_all_insns (global
);
997 if (! ira_conflicts_p
)
998 /* Don't do it for IRA. We need this info because we don't
999 change live_throughout and dead_or_set for chains when IRA
1001 CLEAR_REG_SET (&spilled_pseudos
);
1003 something_changed
= 0;
1005 /* If we allocated any new memory locations, make another pass
1006 since it might have changed elimination offsets. */
1007 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
1008 something_changed
= 1;
1010 /* Even if the frame size remained the same, we might still have
1011 changed elimination offsets, e.g. if find_reloads called
1012 force_const_mem requiring the back end to allocate a constant
1013 pool base register that needs to be saved on the stack. */
1014 else if (!verify_initial_elim_offsets ())
1015 something_changed
= 1;
1017 if (update_eliminables_and_spill ())
1020 something_changed
= 1;
1024 select_reload_regs ();
1027 if (insns_need_reload
)
1028 something_changed
|= finish_spills (global
);
1031 if (! something_changed
)
1034 if (caller_save_needed
)
1035 delete_caller_save_insns ();
1037 obstack_free (&reload_obstack
, reload_firstobj
);
1040 /* If global-alloc was run, notify it of any register eliminations we have
1043 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1044 if (ep
->can_eliminate
)
1045 mark_elimination (ep
->from
, ep
->to
);
1047 remove_init_insns ();
1049 /* Use the reload registers where necessary
1050 by generating move instructions to move the must-be-register
1051 values into or out of the reload registers. */
1053 if (insns_need_reload
!= 0 || something_needs_elimination
1054 || something_needs_operands_changed
)
1056 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1058 reload_as_needed (global
);
1060 gcc_assert (old_frame_size
== get_frame_size ());
1062 gcc_assert (verify_initial_elim_offsets ());
1065 /* If we were able to eliminate the frame pointer, show that it is no
1066 longer live at the start of any basic block. If it ls live by
1067 virtue of being in a pseudo, that pseudo will be marked live
1068 and hence the frame pointer will be known to be live via that
1071 if (! frame_pointer_needed
)
1072 FOR_EACH_BB_FN (bb
, cfun
)
1073 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1075 /* Come here (with failure set nonzero) if we can't get enough spill
1079 CLEAR_REG_SET (&changed_allocation_pseudos
);
1080 CLEAR_REG_SET (&spilled_pseudos
);
1081 reload_in_progress
= 0;
1083 /* Now eliminate all pseudo regs by modifying them into
1084 their equivalent memory references.
1085 The REG-rtx's for the pseudos are modified in place,
1086 so all insns that used to refer to them now refer to memory.
1088 For a reg that has a reg_equiv_address, all those insns
1089 were changed by reloading so that no insns refer to it any longer;
1090 but the DECL_RTL of a variable decl may refer to it,
1091 and if so this causes the debugging info to mention the variable. */
1093 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1097 if (reg_equiv_mem (i
))
1098 addr
= XEXP (reg_equiv_mem (i
), 0);
1100 if (reg_equiv_address (i
))
1101 addr
= reg_equiv_address (i
);
1105 if (reg_renumber
[i
] < 0)
1107 rtx reg
= regno_reg_rtx
[i
];
1109 REG_USERVAR_P (reg
) = 0;
1110 PUT_CODE (reg
, MEM
);
1111 XEXP (reg
, 0) = addr
;
1112 if (reg_equiv_memory_loc (i
))
1113 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1115 MEM_ATTRS (reg
) = 0;
1116 MEM_NOTRAP_P (reg
) = 1;
1118 else if (reg_equiv_mem (i
))
1119 XEXP (reg_equiv_mem (i
), 0) = addr
;
1122 /* We don't want complex addressing modes in debug insns
1123 if simpler ones will do, so delegitimize equivalences
1125 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1127 rtx reg
= regno_reg_rtx
[i
];
1131 if (reg_equiv_constant (i
))
1132 equiv
= reg_equiv_constant (i
);
1133 else if (reg_equiv_invariant (i
))
1134 equiv
= reg_equiv_invariant (i
);
1135 else if (reg
&& MEM_P (reg
))
1136 equiv
= targetm
.delegitimize_address (reg
);
1137 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1143 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1145 insn
= DF_REF_INSN (use
);
1147 /* Make sure the next ref is for a different instruction,
1148 so that we're not affected by the rescan. */
1149 next
= DF_REF_NEXT_REG (use
);
1150 while (next
&& DF_REF_INSN (next
) == insn
)
1151 next
= DF_REF_NEXT_REG (next
);
1153 if (DEBUG_INSN_P (insn
))
1157 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1158 df_insn_rescan_debug_internal (insn
);
1161 INSN_VAR_LOCATION_LOC (insn
)
1162 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1169 /* We must set reload_completed now since the cleanup_subreg_operands call
1170 below will re-recognize each insn and reload may have generated insns
1171 which are only valid during and after reload. */
1172 reload_completed
= 1;
1174 /* Make a pass over all the insns and delete all USEs which we inserted
1175 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1176 notes. Delete all CLOBBER insns, except those that refer to the return
1177 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1178 from misarranging variable-array code, and simplify (subreg (reg))
1179 operands. Strip and regenerate REG_INC notes that may have been moved
1182 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1188 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1189 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1191 if ((GET_CODE (PATTERN (insn
)) == USE
1192 /* We mark with QImode USEs introduced by reload itself. */
1193 && (GET_MODE (insn
) == QImode
1194 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1195 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1196 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1197 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1198 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1199 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1200 != stack_pointer_rtx
))
1201 && (!REG_P (XEXP (PATTERN (insn
), 0))
1202 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1208 /* Some CLOBBERs may survive until here and still reference unassigned
1209 pseudos with const equivalent, which may in turn cause ICE in later
1210 passes if the reference remains in place. */
1211 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1212 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1213 VOIDmode
, PATTERN (insn
));
1215 /* Discard obvious no-ops, even without -O. This optimization
1216 is fast and doesn't interfere with debugging. */
1217 if (NONJUMP_INSN_P (insn
)
1218 && GET_CODE (PATTERN (insn
)) == SET
1219 && REG_P (SET_SRC (PATTERN (insn
)))
1220 && REG_P (SET_DEST (PATTERN (insn
)))
1221 && (REGNO (SET_SRC (PATTERN (insn
)))
1222 == REGNO (SET_DEST (PATTERN (insn
)))))
1228 pnote
= ®_NOTES (insn
);
1231 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1232 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1233 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1234 *pnote
= XEXP (*pnote
, 1);
1236 pnote
= &XEXP (*pnote
, 1);
1240 add_auto_inc_notes (insn
, PATTERN (insn
));
1242 /* Simplify (subreg (reg)) if it appears as an operand. */
1243 cleanup_subreg_operands (insn
);
1245 /* Clean up invalid ASMs so that they don't confuse later passes.
1247 if (asm_noperands (PATTERN (insn
)) >= 0)
1249 extract_insn (insn
);
1250 if (!constrain_operands (1, get_enabled_alternatives (insn
)))
1252 error_for_asm (insn
,
1253 "%<asm%> operand has impossible constraints");
1260 free (temp_pseudo_reg_arr
);
1262 /* Indicate that we no longer have known memory locations or constants. */
1265 free (reg_max_ref_width
);
1266 free (reg_old_renumber
);
1267 free (pseudo_previous_regs
);
1268 free (pseudo_forbidden_regs
);
1270 CLEAR_HARD_REG_SET (used_spill_regs
);
1271 for (i
= 0; i
< n_spills
; i
++)
1272 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1274 /* Free all the insn_chain structures at once. */
1275 obstack_free (&reload_obstack
, reload_startobj
);
1276 unused_insn_chains
= 0;
1278 inserted
= fixup_abnormal_edges ();
1280 /* We've possibly turned single trapping insn into multiple ones. */
1281 if (cfun
->can_throw_non_call_exceptions
)
1283 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
1284 bitmap_ones (blocks
);
1285 find_many_sub_basic_blocks (blocks
);
1289 commit_edge_insertions ();
1291 /* Replacing pseudos with their memory equivalents might have
1292 created shared rtx. Subsequent passes would get confused
1293 by this, so unshare everything here. */
1294 unshare_all_rtl_again (first
);
1296 #ifdef STACK_BOUNDARY
1297 /* init_emit has set the alignment of the hard frame pointer
1298 to STACK_BOUNDARY. It is very likely no longer valid if
1299 the hard frame pointer was used for register allocation. */
1300 if (!frame_pointer_needed
)
1301 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1304 substitute_stack
.release ();
1306 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1308 reload_completed
= !failure
;
1313 /* Yet another special case. Unfortunately, reg-stack forces people to
1314 write incorrect clobbers in asm statements. These clobbers must not
1315 cause the register to appear in bad_spill_regs, otherwise we'll call
1316 fatal_insn later. We clear the corresponding regnos in the live
1317 register sets to avoid this.
1318 The whole thing is rather sick, I'm afraid. */
1321 maybe_fix_stack_asms (void)
1324 const char *constraints
[MAX_RECOG_OPERANDS
];
1325 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1326 struct insn_chain
*chain
;
1328 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1331 HARD_REG_SET clobbered
, allowed
;
1334 if (! INSN_P (chain
->insn
)
1335 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1337 pat
= PATTERN (chain
->insn
);
1338 if (GET_CODE (pat
) != PARALLEL
)
1341 CLEAR_HARD_REG_SET (clobbered
);
1342 CLEAR_HARD_REG_SET (allowed
);
1344 /* First, make a mask of all stack regs that are clobbered. */
1345 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1347 rtx t
= XVECEXP (pat
, 0, i
);
1348 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1349 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1352 /* Get the operand values and constraints out of the insn. */
1353 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1354 constraints
, operand_mode
, NULL
);
1356 /* For every operand, see what registers are allowed. */
1357 for (i
= 0; i
< noperands
; i
++)
1359 const char *p
= constraints
[i
];
1360 /* For every alternative, we compute the class of registers allowed
1361 for reloading in CLS, and merge its contents into the reg set
1363 int cls
= (int) NO_REGS
;
1369 if (c
== '\0' || c
== ',' || c
== '#')
1371 /* End of one alternative - mark the regs in the current
1372 class, and reset the class. */
1373 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1379 } while (c
!= '\0' && c
!= ',');
1388 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1392 enum constraint_num cn
= lookup_constraint (p
);
1393 if (insn_extra_address_constraint (cn
))
1394 cls
= (int) reg_class_subunion
[cls
]
1395 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1398 cls
= (int) reg_class_subunion
[cls
]
1399 [reg_class_for_constraint (cn
)];
1402 p
+= CONSTRAINT_LEN (c
, p
);
1405 /* Those of the registers which are clobbered, but allowed by the
1406 constraints, must be usable as reload registers. So clear them
1407 out of the life information. */
1408 AND_HARD_REG_SET (allowed
, clobbered
);
1409 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1410 if (TEST_HARD_REG_BIT (allowed
, i
))
1412 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1413 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1420 /* Copy the global variables n_reloads and rld into the corresponding elts
1423 copy_reloads (struct insn_chain
*chain
)
1425 chain
->n_reloads
= n_reloads
;
1426 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1427 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1428 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1431 /* Walk the chain of insns, and determine for each whether it needs reloads
1432 and/or eliminations. Build the corresponding insns_need_reload list, and
1433 set something_needs_elimination as appropriate. */
1435 calculate_needs_all_insns (int global
)
1437 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1438 struct insn_chain
*chain
, *next
= 0;
1440 something_needs_elimination
= 0;
1442 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1443 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1445 rtx_insn
*insn
= chain
->insn
;
1449 /* Clear out the shortcuts. */
1450 chain
->n_reloads
= 0;
1451 chain
->need_elim
= 0;
1452 chain
->need_reload
= 0;
1453 chain
->need_operand_change
= 0;
1455 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1456 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1457 what effects this has on the known offsets at labels. */
1459 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1460 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1461 set_label_offsets (insn
, insn
, 0);
1465 rtx old_body
= PATTERN (insn
);
1466 int old_code
= INSN_CODE (insn
);
1467 rtx old_notes
= REG_NOTES (insn
);
1468 int did_elimination
= 0;
1469 int operands_changed
= 0;
1471 /* Skip insns that only set an equivalence. */
1472 if (will_delete_init_insn_p (insn
))
1475 /* If needed, eliminate any eliminable registers. */
1476 if (num_eliminable
|| num_eliminable_invariants
)
1477 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1479 /* Analyze the instruction. */
1480 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1481 global
, spill_reg_order
);
1483 /* If a no-op set needs more than one reload, this is likely
1484 to be something that needs input address reloads. We
1485 can't get rid of this cleanly later, and it is of no use
1486 anyway, so discard it now.
1487 We only do this when expensive_optimizations is enabled,
1488 since this complements reload inheritance / output
1489 reload deletion, and it can make debugging harder. */
1490 if (flag_expensive_optimizations
&& n_reloads
> 1)
1492 rtx set
= single_set (insn
);
1495 ((SET_SRC (set
) == SET_DEST (set
)
1496 && REG_P (SET_SRC (set
))
1497 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1498 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1499 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1500 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1501 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1502 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1503 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1504 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1506 if (ira_conflicts_p
)
1507 /* Inform IRA about the insn deletion. */
1508 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1509 REGNO (SET_SRC (set
)));
1511 /* Delete it from the reload chain. */
1513 chain
->prev
->next
= next
;
1515 reload_insn_chain
= next
;
1517 next
->prev
= chain
->prev
;
1518 chain
->next
= unused_insn_chains
;
1519 unused_insn_chains
= chain
;
1524 update_eliminable_offsets ();
1526 /* Remember for later shortcuts which insns had any reloads or
1527 register eliminations. */
1528 chain
->need_elim
= did_elimination
;
1529 chain
->need_reload
= n_reloads
> 0;
1530 chain
->need_operand_change
= operands_changed
;
1532 /* Discard any register replacements done. */
1533 if (did_elimination
)
1535 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1536 PATTERN (insn
) = old_body
;
1537 INSN_CODE (insn
) = old_code
;
1538 REG_NOTES (insn
) = old_notes
;
1539 something_needs_elimination
= 1;
1542 something_needs_operands_changed
|= operands_changed
;
1546 copy_reloads (chain
);
1547 *pprev_reload
= chain
;
1548 pprev_reload
= &chain
->next_need_reload
;
1555 /* This function is called from the register allocator to set up estimates
1556 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1557 an invariant. The structure is similar to calculate_needs_all_insns. */
1560 calculate_elim_costs_all_insns (void)
1562 int *reg_equiv_init_cost
;
1566 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1568 init_eliminable_invariants (get_insns (), false);
1570 set_initial_elim_offsets ();
1571 set_initial_label_offsets ();
1573 FOR_EACH_BB_FN (bb
, cfun
)
1578 FOR_BB_INSNS (bb
, insn
)
1580 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1581 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1582 what effects this has on the known offsets at labels. */
1584 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1585 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1586 set_label_offsets (insn
, insn
, 0);
1590 rtx set
= single_set (insn
);
1592 /* Skip insns that only set an equivalence. */
1593 if (set
&& REG_P (SET_DEST (set
))
1594 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1595 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1596 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1598 unsigned regno
= REGNO (SET_DEST (set
));
1599 rtx_insn_list
*init
= reg_equiv_init (regno
);
1602 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1604 machine_mode mode
= GET_MODE (SET_DEST (set
));
1605 int cost
= set_src_cost (t
, mode
,
1606 optimize_bb_for_speed_p (bb
));
1607 int freq
= REG_FREQ_FROM_BB (bb
);
1609 reg_equiv_init_cost
[regno
] = cost
* freq
;
1613 /* If needed, eliminate any eliminable registers. */
1614 if (num_eliminable
|| num_eliminable_invariants
)
1615 elimination_costs_in_insn (insn
);
1618 update_eliminable_offsets ();
1622 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1624 if (reg_equiv_invariant (i
))
1626 if (reg_equiv_init (i
))
1628 int cost
= reg_equiv_init_cost
[i
];
1631 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1633 ira_adjust_equiv_reg_cost (i
, cost
);
1639 "Reg %d had equivalence, but can't be eliminated\n",
1641 ira_adjust_equiv_reg_cost (i
, 0);
1646 free (reg_equiv_init_cost
);
1647 free (offsets_known_at
);
1650 offsets_known_at
= NULL
;
1653 /* Comparison function for qsort to decide which of two reloads
1654 should be handled first. *P1 and *P2 are the reload numbers. */
1657 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1659 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1662 /* Consider required reloads before optional ones. */
1663 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1667 /* Count all solitary classes before non-solitary ones. */
1668 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1669 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1673 /* Aside from solitaires, consider all multi-reg groups first. */
1674 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1678 /* Consider reloads in order of increasing reg-class number. */
1679 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1683 /* If reloads are equally urgent, sort by reload number,
1684 so that the results of qsort leave nothing to chance. */
1688 /* The cost of spilling each hard reg. */
1689 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1691 /* When spilling multiple hard registers, we use SPILL_COST for the first
1692 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1693 only the first hard reg for a multi-reg pseudo. */
1694 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1696 /* Map of hard regno to pseudo regno currently occupying the hard
1698 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1700 /* Update the spill cost arrays, considering that pseudo REG is live. */
1703 count_pseudo (int reg
)
1705 int freq
= REG_FREQ (reg
);
1706 int r
= reg_renumber
[reg
];
1709 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1710 if (ira_conflicts_p
&& r
< 0)
1713 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1714 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1717 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1719 gcc_assert (r
>= 0);
1721 spill_add_cost
[r
] += freq
;
1722 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1725 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1726 spill_cost
[r
+ nregs
] += freq
;
1730 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1731 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1734 order_regs_for_reload (struct insn_chain
*chain
)
1737 HARD_REG_SET used_by_pseudos
;
1738 HARD_REG_SET used_by_pseudos2
;
1739 reg_set_iterator rsi
;
1741 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1743 memset (spill_cost
, 0, sizeof spill_cost
);
1744 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1745 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1746 hard_regno_to_pseudo_regno
[i
] = -1;
1748 /* Count number of uses of each hard reg by pseudo regs allocated to it
1749 and then order them by decreasing use. First exclude hard registers
1750 that are live in or across this insn. */
1752 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1753 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1754 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1755 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1757 /* Now find out which pseudos are allocated to it, and update
1759 CLEAR_REG_SET (&pseudos_counted
);
1761 EXECUTE_IF_SET_IN_REG_SET
1762 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1766 EXECUTE_IF_SET_IN_REG_SET
1767 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1771 CLEAR_REG_SET (&pseudos_counted
);
1774 /* Vector of reload-numbers showing the order in which the reloads should
1776 static short reload_order
[MAX_RELOADS
];
1778 /* This is used to keep track of the spill regs used in one insn. */
1779 static HARD_REG_SET used_spill_regs_local
;
1781 /* We decided to spill hard register SPILLED, which has a size of
1782 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1783 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1784 update SPILL_COST/SPILL_ADD_COST. */
1787 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1789 int freq
= REG_FREQ (reg
);
1790 int r
= reg_renumber
[reg
];
1793 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1794 if (ira_conflicts_p
&& r
< 0)
1797 gcc_assert (r
>= 0);
1799 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1801 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1802 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1805 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1807 spill_add_cost
[r
] -= freq
;
1810 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1811 spill_cost
[r
+ nregs
] -= freq
;
1815 /* Find reload register to use for reload number ORDER. */
1818 find_reg (struct insn_chain
*chain
, int order
)
1820 int rnum
= reload_order
[order
];
1821 struct reload
*rl
= rld
+ rnum
;
1822 int best_cost
= INT_MAX
;
1824 unsigned int i
, j
, n
;
1826 HARD_REG_SET not_usable
;
1827 HARD_REG_SET used_by_other_reload
;
1828 reg_set_iterator rsi
;
1829 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1830 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1832 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1833 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1834 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1836 CLEAR_HARD_REG_SET (used_by_other_reload
);
1837 for (k
= 0; k
< order
; k
++)
1839 int other
= reload_order
[k
];
1841 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1842 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1843 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1846 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1848 #ifdef REG_ALLOC_ORDER
1849 unsigned int regno
= reg_alloc_order
[i
];
1851 unsigned int regno
= i
;
1854 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1855 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1856 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1858 int this_cost
= spill_cost
[regno
];
1860 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1862 for (j
= 1; j
< this_nregs
; j
++)
1864 this_cost
+= spill_add_cost
[regno
+ j
];
1865 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1866 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1872 if (ira_conflicts_p
)
1874 /* Ask IRA to find a better pseudo-register for
1876 for (n
= j
= 0; j
< this_nregs
; j
++)
1878 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1882 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1883 regno_pseudo_regs
[n
++] = r
;
1885 regno_pseudo_regs
[n
++] = -1;
1887 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1888 best_regno_pseudo_regs
,
1895 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1896 if (regno_pseudo_regs
[j
] < 0)
1903 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1905 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1907 if (this_cost
< best_cost
1908 /* Among registers with equal cost, prefer caller-saved ones, or
1909 use REG_ALLOC_ORDER if it is defined. */
1910 || (this_cost
== best_cost
1911 #ifdef REG_ALLOC_ORDER
1912 && (inv_reg_alloc_order
[regno
]
1913 < inv_reg_alloc_order
[best_reg
])
1915 && call_used_regs
[regno
]
1916 && ! call_used_regs
[best_reg
]
1921 best_cost
= this_cost
;
1929 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1931 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1932 rl
->regno
= best_reg
;
1934 EXECUTE_IF_SET_IN_REG_SET
1935 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1937 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1940 EXECUTE_IF_SET_IN_REG_SET
1941 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1943 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1946 for (i
= 0; i
< rl
->nregs
; i
++)
1948 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1949 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1950 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1951 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1956 /* Find more reload regs to satisfy the remaining need of an insn, which
1958 Do it by ascending class number, since otherwise a reg
1959 might be spilled for a big class and might fail to count
1960 for a smaller class even though it belongs to that class. */
1963 find_reload_regs (struct insn_chain
*chain
)
1967 /* In order to be certain of getting the registers we need,
1968 we must sort the reloads into order of increasing register class.
1969 Then our grabbing of reload registers will parallel the process
1970 that provided the reload registers. */
1971 for (i
= 0; i
< chain
->n_reloads
; i
++)
1973 /* Show whether this reload already has a hard reg. */
1974 if (chain
->rld
[i
].reg_rtx
)
1976 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1977 chain
->rld
[i
].regno
= regno
;
1979 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1982 chain
->rld
[i
].regno
= -1;
1983 reload_order
[i
] = i
;
1986 n_reloads
= chain
->n_reloads
;
1987 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1989 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1992 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1994 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1996 /* Compute the order of preference for hard registers to spill. */
1998 order_regs_for_reload (chain
);
2000 for (i
= 0; i
< n_reloads
; i
++)
2002 int r
= reload_order
[i
];
2004 /* Ignore reloads that got marked inoperative. */
2005 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2006 && ! rld
[r
].optional
2007 && rld
[r
].regno
== -1)
2008 if (! find_reg (chain
, i
))
2011 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2012 spill_failure (chain
->insn
, rld
[r
].rclass
);
2018 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2019 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2021 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2025 select_reload_regs (void)
2027 struct insn_chain
*chain
;
2029 /* Try to satisfy the needs for each insn. */
2030 for (chain
= insns_need_reload
; chain
!= 0;
2031 chain
= chain
->next_need_reload
)
2032 find_reload_regs (chain
);
2035 /* Delete all insns that were inserted by emit_caller_save_insns during
2038 delete_caller_save_insns (void)
2040 struct insn_chain
*c
= reload_insn_chain
;
2044 while (c
!= 0 && c
->is_caller_save_insn
)
2046 struct insn_chain
*next
= c
->next
;
2047 rtx_insn
*insn
= c
->insn
;
2049 if (c
== reload_insn_chain
)
2050 reload_insn_chain
= next
;
2054 next
->prev
= c
->prev
;
2056 c
->prev
->next
= next
;
2057 c
->next
= unused_insn_chains
;
2058 unused_insn_chains
= c
;
2066 /* Handle the failure to find a register to spill.
2067 INSN should be one of the insns which needed this particular spill reg. */
2070 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2072 if (asm_noperands (PATTERN (insn
)) >= 0)
2073 error_for_asm (insn
, "can%'t find a register in class %qs while "
2074 "reloading %<asm%>",
2075 reg_class_names
[rclass
]);
2078 error ("unable to find a register to spill in class %qs",
2079 reg_class_names
[rclass
]);
2083 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2084 debug_reload_to_stream (dump_file
);
2086 fatal_insn ("this is the insn:", insn
);
2090 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2091 data that is dead in INSN. */
2094 delete_dead_insn (rtx_insn
*insn
)
2096 rtx_insn
*prev
= prev_active_insn (insn
);
2099 /* If the previous insn sets a register that dies in our insn make
2100 a note that we want to run DCE immediately after reload.
2102 We used to delete the previous insn & recurse, but that's wrong for
2103 block local equivalences. Instead of trying to figure out the exact
2104 circumstances where we can delete the potentially dead insns, just
2105 let DCE do the job. */
2106 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2107 && GET_CODE (PATTERN (prev
)) == SET
2108 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2109 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2110 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2111 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2114 SET_INSN_DELETED (insn
);
2117 /* Modify the home of pseudo-reg I.
2118 The new home is present in reg_renumber[I].
2120 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2121 or it may be -1, meaning there is none or it is not relevant.
2122 This is used so that all pseudos spilled from a given hard reg
2123 can share one stack slot. */
2126 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2128 /* When outputting an inline function, this can happen
2129 for a reg that isn't actually used. */
2130 if (regno_reg_rtx
[i
] == 0)
2133 /* If the reg got changed to a MEM at rtl-generation time,
2135 if (!REG_P (regno_reg_rtx
[i
]))
2138 /* Modify the reg-rtx to contain the new hard reg
2139 number or else to contain its pseudo reg number. */
2140 SET_REGNO (regno_reg_rtx
[i
],
2141 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2143 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2144 allocate a stack slot for it. */
2146 if (reg_renumber
[i
] < 0
2147 && REG_N_REFS (i
) > 0
2148 && reg_equiv_constant (i
) == 0
2149 && (reg_equiv_invariant (i
) == 0
2150 || reg_equiv_init (i
) == 0)
2151 && reg_equiv_memory_loc (i
) == 0)
2154 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2155 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2156 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2157 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2158 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2161 something_was_spilled
= true;
2163 if (ira_conflicts_p
)
2165 /* Mark the spill for IRA. */
2166 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2168 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2174 /* Each pseudo reg has an inherent size which comes from its own mode,
2175 and a total size which provides room for paradoxical subregs
2176 which refer to the pseudo reg in wider modes.
2178 We can use a slot already allocated if it provides both
2179 enough inherent space and enough total space.
2180 Otherwise, we allocate a new slot, making sure that it has no less
2181 inherent space, and no less total space, then the previous slot. */
2182 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2186 /* No known place to spill from => no slot to reuse. */
2187 x
= assign_stack_local (mode
, total_size
,
2188 min_align
> inherent_align
2189 || total_size
> inherent_size
? -1 : 0);
2193 /* Cancel the big-endian correction done in assign_stack_local.
2194 Get the address of the beginning of the slot. This is so we
2195 can do a big-endian correction unconditionally below. */
2196 if (BYTES_BIG_ENDIAN
)
2198 adjust
= inherent_size
- total_size
;
2201 = adjust_address_nv (x
, mode_for_size (total_size
2207 if (! dont_share_p
&& ira_conflicts_p
)
2208 /* Inform IRA about allocation a new stack slot. */
2209 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2212 /* Reuse a stack slot if possible. */
2213 else if (spill_stack_slot
[from_reg
] != 0
2214 && spill_stack_slot_width
[from_reg
] >= total_size
2215 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2217 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2218 x
= spill_stack_slot
[from_reg
];
2220 /* Allocate a bigger slot. */
2223 /* Compute maximum size needed, both for inherent size
2224 and for total size. */
2227 if (spill_stack_slot
[from_reg
])
2229 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2231 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2232 if (spill_stack_slot_width
[from_reg
] > total_size
)
2233 total_size
= spill_stack_slot_width
[from_reg
];
2234 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2235 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2238 /* Make a slot with that size. */
2239 x
= assign_stack_local (mode
, total_size
,
2240 min_align
> inherent_align
2241 || total_size
> inherent_size
? -1 : 0);
2244 /* Cancel the big-endian correction done in assign_stack_local.
2245 Get the address of the beginning of the slot. This is so we
2246 can do a big-endian correction unconditionally below. */
2247 if (BYTES_BIG_ENDIAN
)
2249 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2252 = adjust_address_nv (x
, mode_for_size (total_size
2258 spill_stack_slot
[from_reg
] = stack_slot
;
2259 spill_stack_slot_width
[from_reg
] = total_size
;
2262 /* On a big endian machine, the "address" of the slot
2263 is the address of the low part that fits its inherent mode. */
2264 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2265 adjust
+= (total_size
- inherent_size
);
2267 /* If we have any adjustment to make, or if the stack slot is the
2268 wrong mode, make a new stack slot. */
2269 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2271 /* Set all of the memory attributes as appropriate for a spill. */
2272 set_mem_attrs_for_spill (x
);
2274 /* Save the stack slot for later. */
2275 reg_equiv_memory_loc (i
) = x
;
2279 /* Mark the slots in regs_ever_live for the hard regs used by
2280 pseudo-reg number REGNO, accessed in MODE. */
2283 mark_home_live_1 (int regno
, machine_mode mode
)
2287 i
= reg_renumber
[regno
];
2290 lim
= end_hard_regno (mode
, i
);
2292 df_set_regs_ever_live (i
++, true);
2295 /* Mark the slots in regs_ever_live for the hard regs
2296 used by pseudo-reg number REGNO. */
2299 mark_home_live (int regno
)
2301 if (reg_renumber
[regno
] >= 0)
2302 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2305 /* This function handles the tracking of elimination offsets around branches.
2307 X is a piece of RTL being scanned.
2309 INSN is the insn that it came from, if any.
2311 INITIAL_P is nonzero if we are to set the offset to be the initial
2312 offset and zero if we are setting the offset of the label to be the
2316 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2318 enum rtx_code code
= GET_CODE (x
);
2321 struct elim_table
*p
;
2326 if (LABEL_REF_NONLOCAL_P (x
))
2329 x
= LABEL_REF_LABEL (x
);
2334 /* If we know nothing about this label, set the desired offsets. Note
2335 that this sets the offset at a label to be the offset before a label
2336 if we don't know anything about the label. This is not correct for
2337 the label after a BARRIER, but is the best guess we can make. If
2338 we guessed wrong, we will suppress an elimination that might have
2339 been possible had we been able to guess correctly. */
2341 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2343 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2344 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2345 = (initial_p
? reg_eliminate
[i
].initial_offset
2346 : reg_eliminate
[i
].offset
);
2347 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2350 /* Otherwise, if this is the definition of a label and it is
2351 preceded by a BARRIER, set our offsets to the known offset of
2355 && (tem
= prev_nonnote_insn (insn
)) != 0
2357 set_offsets_for_label (insn
);
2359 /* If neither of the above cases is true, compare each offset
2360 with those previously recorded and suppress any eliminations
2361 where the offsets disagree. */
2363 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2364 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2365 != (initial_p
? reg_eliminate
[i
].initial_offset
2366 : reg_eliminate
[i
].offset
))
2367 reg_eliminate
[i
].can_eliminate
= 0;
2371 case JUMP_TABLE_DATA
:
2372 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2376 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2382 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2383 to indirectly and hence must have all eliminations at their
2385 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2386 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2387 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2393 /* Each of the labels in the parallel or address vector must be
2394 at their initial offsets. We want the first field for PARALLEL
2395 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2397 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2398 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2403 /* We only care about setting PC. If the source is not RETURN,
2404 IF_THEN_ELSE, or a label, disable any eliminations not at
2405 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2406 isn't one of those possibilities. For branches to a label,
2407 call ourselves recursively.
2409 Note that this can disable elimination unnecessarily when we have
2410 a non-local goto since it will look like a non-constant jump to
2411 someplace in the current function. This isn't a significant
2412 problem since such jumps will normally be when all elimination
2413 pairs are back to their initial offsets. */
2415 if (SET_DEST (x
) != pc_rtx
)
2418 switch (GET_CODE (SET_SRC (x
)))
2425 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2429 tem
= XEXP (SET_SRC (x
), 1);
2430 if (GET_CODE (tem
) == LABEL_REF
)
2431 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2432 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2435 tem
= XEXP (SET_SRC (x
), 2);
2436 if (GET_CODE (tem
) == LABEL_REF
)
2437 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2438 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2446 /* If we reach here, all eliminations must be at their initial
2447 offset because we are doing a jump to a variable address. */
2448 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2449 if (p
->offset
!= p
->initial_offset
)
2450 p
->can_eliminate
= 0;
2458 /* This function examines every reg that occurs in X and adjusts the
2459 costs for its elimination which are gathered by IRA. INSN is the
2460 insn in which X occurs. We do not recurse into MEM expressions. */
2463 note_reg_elim_costly (const_rtx x
, rtx insn
)
2465 subrtx_iterator::array_type array
;
2466 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2468 const_rtx x
= *iter
;
2470 iter
.skip_subrtxes ();
2472 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2473 && reg_equiv_init (REGNO (x
))
2474 && reg_equiv_invariant (REGNO (x
)))
2476 rtx t
= reg_equiv_invariant (REGNO (x
));
2477 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2478 int cost
= set_src_cost (new_rtx
, Pmode
,
2479 optimize_bb_for_speed_p (elim_bb
));
2480 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2483 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2488 /* Scan X and replace any eliminable registers (such as fp) with a
2489 replacement (such as sp), plus an offset.
2491 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2492 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2493 MEM, we are allowed to replace a sum of a register and the constant zero
2494 with the register, which we cannot do outside a MEM. In addition, we need
2495 to record the fact that a register is referenced outside a MEM.
2497 If INSN is an insn, it is the insn containing X. If we replace a REG
2498 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2499 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2500 the REG is being modified.
2502 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2503 That's used when we eliminate in expressions stored in notes.
2504 This means, do not set ref_outside_mem even if the reference
2507 If FOR_COSTS is true, we are being called before reload in order to
2508 estimate the costs of keeping registers with an equivalence unallocated.
2510 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2511 replacements done assuming all offsets are at their initial values. If
2512 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2513 encounter, return the actual location so that find_reloads will do
2514 the proper thing. */
2517 eliminate_regs_1 (rtx x
, machine_mode mem_mode
, rtx insn
,
2518 bool may_use_invariant
, bool for_costs
)
2520 enum rtx_code code
= GET_CODE (x
);
2521 struct elim_table
*ep
;
2528 if (! current_function_decl
)
2548 /* First handle the case where we encounter a bare register that
2549 is eliminable. Replace it with a PLUS. */
2550 if (regno
< FIRST_PSEUDO_REGISTER
)
2552 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2554 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2555 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2558 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2560 && reg_equiv_invariant (regno
))
2562 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2563 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2564 mem_mode
, insn
, true, for_costs
);
2565 /* There exists at least one use of REGNO that cannot be
2566 eliminated. Prevent the defining insn from being deleted. */
2567 reg_equiv_init (regno
) = NULL
;
2569 alter_reg (regno
, -1, true);
2573 /* You might think handling MINUS in a manner similar to PLUS is a
2574 good idea. It is not. It has been tried multiple times and every
2575 time the change has had to have been reverted.
2577 Other parts of reload know a PLUS is special (gen_reload for example)
2578 and require special code to handle code a reloaded PLUS operand.
2580 Also consider backends where the flags register is clobbered by a
2581 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2582 lea instruction comes to mind). If we try to reload a MINUS, we
2583 may kill the flags register that was holding a useful value.
2585 So, please before trying to handle MINUS, consider reload as a
2586 whole instead of this little section as well as the backend issues. */
2588 /* If this is the sum of an eliminable register and a constant, rework
2590 if (REG_P (XEXP (x
, 0))
2591 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2592 && CONSTANT_P (XEXP (x
, 1)))
2594 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2596 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2598 /* The only time we want to replace a PLUS with a REG (this
2599 occurs when the constant operand of the PLUS is the negative
2600 of the offset) is when we are inside a MEM. We won't want
2601 to do so at other times because that would change the
2602 structure of the insn in a way that reload can't handle.
2603 We special-case the commonest situation in
2604 eliminate_regs_in_insn, so just replace a PLUS with a
2605 PLUS here, unless inside a MEM. */
2606 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2607 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2610 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2611 plus_constant (Pmode
, XEXP (x
, 1),
2612 ep
->previous_offset
));
2615 /* If the register is not eliminable, we are done since the other
2616 operand is a constant. */
2620 /* If this is part of an address, we want to bring any constant to the
2621 outermost PLUS. We will do this by doing register replacement in
2622 our operands and seeing if a constant shows up in one of them.
2624 Note that there is no risk of modifying the structure of the insn,
2625 since we only get called for its operands, thus we are either
2626 modifying the address inside a MEM, or something like an address
2627 operand of a load-address insn. */
2630 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2632 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2635 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2637 /* If one side is a PLUS and the other side is a pseudo that
2638 didn't get a hard register but has a reg_equiv_constant,
2639 we must replace the constant here since it may no longer
2640 be in the position of any operand. */
2641 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2642 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2643 && reg_renumber
[REGNO (new1
)] < 0
2645 && reg_equiv_constant (REGNO (new1
)) != 0)
2646 new1
= reg_equiv_constant (REGNO (new1
));
2647 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2648 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2649 && reg_renumber
[REGNO (new0
)] < 0
2650 && reg_equiv_constant (REGNO (new0
)) != 0)
2651 new0
= reg_equiv_constant (REGNO (new0
));
2653 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2655 /* As above, if we are not inside a MEM we do not want to
2656 turn a PLUS into something else. We might try to do so here
2657 for an addition of 0 if we aren't optimizing. */
2658 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2659 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2667 /* If this is the product of an eliminable register and a
2668 constant, apply the distribute law and move the constant out
2669 so that we have (plus (mult ..) ..). This is needed in order
2670 to keep load-address insns valid. This case is pathological.
2671 We ignore the possibility of overflow here. */
2672 if (REG_P (XEXP (x
, 0))
2673 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2674 && CONST_INT_P (XEXP (x
, 1)))
2675 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2677 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2680 /* Refs inside notes or in DEBUG_INSNs don't count for
2682 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2683 || GET_CODE (insn
) == INSN_LIST
2684 || DEBUG_INSN_P (insn
))))
2685 ep
->ref_outside_mem
= 1;
2688 plus_constant (Pmode
,
2689 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2690 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2697 /* See comments before PLUS about handling MINUS. */
2699 case DIV
: case UDIV
:
2700 case MOD
: case UMOD
:
2701 case AND
: case IOR
: case XOR
:
2702 case ROTATERT
: case ROTATE
:
2703 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2705 case GE
: case GT
: case GEU
: case GTU
:
2706 case LE
: case LT
: case LEU
: case LTU
:
2708 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2710 rtx new1
= XEXP (x
, 1)
2711 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2714 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2715 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2720 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2723 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2725 if (new_rtx
!= XEXP (x
, 0))
2727 /* If this is a REG_DEAD note, it is not valid anymore.
2728 Using the eliminated version could result in creating a
2729 REG_DEAD note for the stack or frame pointer. */
2730 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2732 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2736 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2744 /* Now do eliminations in the rest of the chain. If this was
2745 an EXPR_LIST, this might result in allocating more memory than is
2746 strictly needed, but it simplifies the code. */
2749 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2751 if (new_rtx
!= XEXP (x
, 1))
2753 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2761 /* We do not support elimination of a register that is modified.
2762 elimination_effects has already make sure that this does not
2768 /* We do not support elimination of a register that is modified.
2769 elimination_effects has already make sure that this does not
2770 happen. The only remaining case we need to consider here is
2771 that the increment value may be an eliminable register. */
2772 if (GET_CODE (XEXP (x
, 1)) == PLUS
2773 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2775 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2776 insn
, true, for_costs
);
2778 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2779 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2780 gen_rtx_PLUS (GET_MODE (x
),
2781 XEXP (x
, 0), new_rtx
));
2785 case STRICT_LOW_PART
:
2787 case SIGN_EXTEND
: case ZERO_EXTEND
:
2788 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2789 case FLOAT
: case FIX
:
2790 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2799 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2801 if (new_rtx
!= XEXP (x
, 0))
2802 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2806 /* Similar to above processing, but preserve SUBREG_BYTE.
2807 Convert (subreg (mem)) to (mem) if not paradoxical.
2808 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2809 pseudo didn't get a hard reg, we must replace this with the
2810 eliminated version of the memory location because push_reload
2811 may do the replacement in certain circumstances. */
2812 if (REG_P (SUBREG_REG (x
))
2813 && !paradoxical_subreg_p (x
)
2815 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2817 new_rtx
= SUBREG_REG (x
);
2820 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2822 if (new_rtx
!= SUBREG_REG (x
))
2824 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2825 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2828 && ((x_size
< new_size
2829 #if WORD_REGISTER_OPERATIONS
2830 /* On these machines, combine can create rtl of the form
2831 (set (subreg:m1 (reg:m2 R) 0) ...)
2832 where m1 < m2, and expects something interesting to
2833 happen to the entire word. Moreover, it will use the
2834 (reg:m2 R) later, expecting all bits to be preserved.
2835 So if the number of words is the same, preserve the
2836 subreg so that push_reload can see it. */
2837 && ! ((x_size
- 1) / UNITS_PER_WORD
2838 == (new_size
-1 ) / UNITS_PER_WORD
)
2841 || x_size
== new_size
)
2843 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2845 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2851 /* Our only special processing is to pass the mode of the MEM to our
2852 recursive call and copy the flags. While we are here, handle this
2853 case more efficiently. */
2855 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2858 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2859 && !memory_address_p (GET_MODE (x
), new_rtx
))
2860 note_reg_elim_costly (XEXP (x
, 0), insn
);
2862 return replace_equiv_address_nv (x
, new_rtx
);
2865 /* Handle insn_list USE that a call to a pure function may generate. */
2866 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2868 if (new_rtx
!= XEXP (x
, 0))
2869 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2874 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2884 /* Process each of our operands recursively. If any have changed, make a
2886 fmt
= GET_RTX_FORMAT (code
);
2887 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2891 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2893 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2895 x
= shallow_copy_rtx (x
);
2898 XEXP (x
, i
) = new_rtx
;
2900 else if (*fmt
== 'E')
2903 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2905 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2907 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2909 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2913 x
= shallow_copy_rtx (x
);
2916 XVEC (x
, i
) = new_v
;
2919 XVECEXP (x
, i
, j
) = new_rtx
;
2928 eliminate_regs (rtx x
, machine_mode mem_mode
, rtx insn
)
2930 if (reg_eliminate
== NULL
)
2932 gcc_assert (targetm
.no_register_allocation
);
2935 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2938 /* Scan rtx X for modifications of elimination target registers. Update
2939 the table of eliminables to reflect the changed state. MEM_MODE is
2940 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2943 elimination_effects (rtx x
, machine_mode mem_mode
)
2945 enum rtx_code code
= GET_CODE (x
);
2946 struct elim_table
*ep
;
2968 /* First handle the case where we encounter a bare register that
2969 is eliminable. Replace it with a PLUS. */
2970 if (regno
< FIRST_PSEUDO_REGISTER
)
2972 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2974 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2977 ep
->ref_outside_mem
= 1;
2982 else if (reg_renumber
[regno
] < 0
2984 && reg_equiv_constant (regno
)
2985 && ! function_invariant_p (reg_equiv_constant (regno
)))
2986 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
2995 /* If we modify the source of an elimination rule, disable it. */
2996 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2997 if (ep
->from_rtx
== XEXP (x
, 0))
2998 ep
->can_eliminate
= 0;
3000 /* If we modify the target of an elimination rule by adding a constant,
3001 update its offset. If we modify the target in any other way, we'll
3002 have to disable the rule as well. */
3003 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3004 if (ep
->to_rtx
== XEXP (x
, 0))
3006 int size
= GET_MODE_SIZE (mem_mode
);
3008 /* If more bytes than MEM_MODE are pushed, account for them. */
3009 #ifdef PUSH_ROUNDING
3010 if (ep
->to_rtx
== stack_pointer_rtx
)
3011 size
= PUSH_ROUNDING (size
);
3013 if (code
== PRE_DEC
|| code
== POST_DEC
)
3015 else if (code
== PRE_INC
|| code
== POST_INC
)
3017 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3019 if (GET_CODE (XEXP (x
, 1)) == PLUS
3020 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3021 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3022 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3024 ep
->can_eliminate
= 0;
3028 /* These two aren't unary operators. */
3029 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3032 /* Fall through to generic unary operation case. */
3033 case STRICT_LOW_PART
:
3035 case SIGN_EXTEND
: case ZERO_EXTEND
:
3036 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3037 case FLOAT
: case FIX
:
3038 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3047 elimination_effects (XEXP (x
, 0), mem_mode
);
3051 if (REG_P (SUBREG_REG (x
))
3052 && (GET_MODE_SIZE (GET_MODE (x
))
3053 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3055 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3058 elimination_effects (SUBREG_REG (x
), mem_mode
);
3062 /* If using a register that is the source of an eliminate we still
3063 think can be performed, note it cannot be performed since we don't
3064 know how this register is used. */
3065 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3066 if (ep
->from_rtx
== XEXP (x
, 0))
3067 ep
->can_eliminate
= 0;
3069 elimination_effects (XEXP (x
, 0), mem_mode
);
3073 /* If clobbering a register that is the replacement register for an
3074 elimination we still think can be performed, note that it cannot
3075 be performed. Otherwise, we need not be concerned about it. */
3076 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3077 if (ep
->to_rtx
== XEXP (x
, 0))
3078 ep
->can_eliminate
= 0;
3080 elimination_effects (XEXP (x
, 0), mem_mode
);
3084 /* Check for setting a register that we know about. */
3085 if (REG_P (SET_DEST (x
)))
3087 /* See if this is setting the replacement register for an
3090 If DEST is the hard frame pointer, we do nothing because we
3091 assume that all assignments to the frame pointer are for
3092 non-local gotos and are being done at a time when they are valid
3093 and do not disturb anything else. Some machines want to
3094 eliminate a fake argument pointer (or even a fake frame pointer)
3095 with either the real frame or the stack pointer. Assignments to
3096 the hard frame pointer must not prevent this elimination. */
3098 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3100 if (ep
->to_rtx
== SET_DEST (x
)
3101 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3103 /* If it is being incremented, adjust the offset. Otherwise,
3104 this elimination can't be done. */
3105 rtx src
= SET_SRC (x
);
3107 if (GET_CODE (src
) == PLUS
3108 && XEXP (src
, 0) == SET_DEST (x
)
3109 && CONST_INT_P (XEXP (src
, 1)))
3110 ep
->offset
-= INTVAL (XEXP (src
, 1));
3112 ep
->can_eliminate
= 0;
3116 elimination_effects (SET_DEST (x
), VOIDmode
);
3117 elimination_effects (SET_SRC (x
), VOIDmode
);
3121 /* Our only special processing is to pass the mode of the MEM to our
3123 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3130 fmt
= GET_RTX_FORMAT (code
);
3131 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3134 elimination_effects (XEXP (x
, i
), mem_mode
);
3135 else if (*fmt
== 'E')
3136 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3137 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3141 /* Descend through rtx X and verify that no references to eliminable registers
3142 remain. If any do remain, mark the involved register as not
3146 check_eliminable_occurrences (rtx x
)
3155 code
= GET_CODE (x
);
3157 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3159 struct elim_table
*ep
;
3161 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3162 if (ep
->from_rtx
== x
)
3163 ep
->can_eliminate
= 0;
3167 fmt
= GET_RTX_FORMAT (code
);
3168 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3171 check_eliminable_occurrences (XEXP (x
, i
));
3172 else if (*fmt
== 'E')
3175 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3176 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3181 /* Scan INSN and eliminate all eliminable registers in it.
3183 If REPLACE is nonzero, do the replacement destructively. Also
3184 delete the insn as dead it if it is setting an eliminable register.
3186 If REPLACE is zero, do all our allocations in reload_obstack.
3188 If no eliminations were done and this insn doesn't require any elimination
3189 processing (these are not identical conditions: it might be updating sp,
3190 but not referencing fp; this needs to be seen during reload_as_needed so
3191 that the offset between fp and sp can be taken into consideration), zero
3192 is returned. Otherwise, 1 is returned. */
3195 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3197 int icode
= recog_memoized (insn
);
3198 rtx old_body
= PATTERN (insn
);
3199 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3200 rtx old_set
= single_set (insn
);
3204 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3205 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3206 struct elim_table
*ep
;
3207 rtx plus_src
, plus_cst_src
;
3209 if (! insn_is_asm
&& icode
< 0)
3211 gcc_assert (DEBUG_INSN_P (insn
)
3212 || GET_CODE (PATTERN (insn
)) == USE
3213 || GET_CODE (PATTERN (insn
)) == CLOBBER
3214 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3215 if (DEBUG_INSN_P (insn
))
3216 INSN_VAR_LOCATION_LOC (insn
)
3217 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3221 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3222 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3224 /* Check for setting an eliminable register. */
3225 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3226 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3228 /* If this is setting the frame pointer register to the
3229 hardware frame pointer register and this is an elimination
3230 that will be done (tested above), this insn is really
3231 adjusting the frame pointer downward to compensate for
3232 the adjustment done before a nonlocal goto. */
3233 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3234 && ep
->from
== FRAME_POINTER_REGNUM
3235 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3237 rtx base
= SET_SRC (old_set
);
3238 rtx_insn
*base_insn
= insn
;
3239 HOST_WIDE_INT offset
= 0;
3241 while (base
!= ep
->to_rtx
)
3243 rtx_insn
*prev_insn
;
3246 if (GET_CODE (base
) == PLUS
3247 && CONST_INT_P (XEXP (base
, 1)))
3249 offset
+= INTVAL (XEXP (base
, 1));
3250 base
= XEXP (base
, 0);
3252 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3253 && (prev_set
= single_set (prev_insn
)) != 0
3254 && rtx_equal_p (SET_DEST (prev_set
), base
))
3256 base
= SET_SRC (prev_set
);
3257 base_insn
= prev_insn
;
3263 if (base
== ep
->to_rtx
)
3265 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3266 offset
- ep
->offset
);
3268 new_body
= old_body
;
3271 new_body
= copy_insn (old_body
);
3272 if (REG_NOTES (insn
))
3273 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3275 PATTERN (insn
) = new_body
;
3276 old_set
= single_set (insn
);
3278 /* First see if this insn remains valid when we
3279 make the change. If not, keep the INSN_CODE
3280 the same and let reload fit it up. */
3281 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3282 validate_change (insn
, &SET_DEST (old_set
),
3284 if (! apply_change_group ())
3286 SET_SRC (old_set
) = src
;
3287 SET_DEST (old_set
) = ep
->to_rtx
;
3295 /* In this case this insn isn't serving a useful purpose. We
3296 will delete it in reload_as_needed once we know that this
3297 elimination is, in fact, being done.
3299 If REPLACE isn't set, we can't delete this insn, but needn't
3300 process it since it won't be used unless something changes. */
3303 delete_dead_insn (insn
);
3311 /* We allow one special case which happens to work on all machines we
3312 currently support: a single set with the source or a REG_EQUAL
3313 note being a PLUS of an eliminable register and a constant. */
3314 plus_src
= plus_cst_src
= 0;
3315 if (old_set
&& REG_P (SET_DEST (old_set
)))
3317 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3318 plus_src
= SET_SRC (old_set
);
3319 /* First see if the source is of the form (plus (...) CST). */
3321 && CONST_INT_P (XEXP (plus_src
, 1)))
3322 plus_cst_src
= plus_src
;
3323 else if (REG_P (SET_SRC (old_set
))
3326 /* Otherwise, see if we have a REG_EQUAL note of the form
3327 (plus (...) CST). */
3329 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3331 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3332 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3333 && GET_CODE (XEXP (links
, 0)) == PLUS
3334 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3336 plus_cst_src
= XEXP (links
, 0);
3342 /* Check that the first operand of the PLUS is a hard reg or
3343 the lowpart subreg of one. */
3346 rtx reg
= XEXP (plus_cst_src
, 0);
3347 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3348 reg
= SUBREG_REG (reg
);
3350 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3356 rtx reg
= XEXP (plus_cst_src
, 0);
3357 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3359 if (GET_CODE (reg
) == SUBREG
)
3360 reg
= SUBREG_REG (reg
);
3362 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3363 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3365 rtx to_rtx
= ep
->to_rtx
;
3366 offset
+= ep
->offset
;
3367 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3369 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3370 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3372 /* If we have a nonzero offset, and the source is already
3373 a simple REG, the following transformation would
3374 increase the cost of the insn by replacing a simple REG
3375 with (plus (reg sp) CST). So try only when we already
3376 had a PLUS before. */
3377 if (offset
== 0 || plus_src
)
3379 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3382 new_body
= old_body
;
3385 new_body
= copy_insn (old_body
);
3386 if (REG_NOTES (insn
))
3387 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3389 PATTERN (insn
) = new_body
;
3390 old_set
= single_set (insn
);
3392 /* First see if this insn remains valid when we make the
3393 change. If not, try to replace the whole pattern with
3394 a simple set (this may help if the original insn was a
3395 PARALLEL that was only recognized as single_set due to
3396 REG_UNUSED notes). If this isn't valid either, keep
3397 the INSN_CODE the same and let reload fix it up. */
3398 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3400 rtx new_pat
= gen_rtx_SET (SET_DEST (old_set
), new_src
);
3402 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3403 SET_SRC (old_set
) = new_src
;
3410 /* This can't have an effect on elimination offsets, so skip right
3416 /* Determine the effects of this insn on elimination offsets. */
3417 elimination_effects (old_body
, VOIDmode
);
3419 /* Eliminate all eliminable registers occurring in operands that
3420 can be handled by reload. */
3421 extract_insn (insn
);
3422 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3424 orig_operand
[i
] = recog_data
.operand
[i
];
3425 substed_operand
[i
] = recog_data
.operand
[i
];
3427 /* For an asm statement, every operand is eliminable. */
3428 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3430 bool is_set_src
, in_plus
;
3432 /* Check for setting a register that we know about. */
3433 if (recog_data
.operand_type
[i
] != OP_IN
3434 && REG_P (orig_operand
[i
]))
3436 /* If we are assigning to a register that can be eliminated, it
3437 must be as part of a PARALLEL, since the code above handles
3438 single SETs. We must indicate that we can no longer
3439 eliminate this reg. */
3440 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3442 if (ep
->from_rtx
== orig_operand
[i
])
3443 ep
->can_eliminate
= 0;
3446 /* Companion to the above plus substitution, we can allow
3447 invariants as the source of a plain move. */
3450 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3454 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3455 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3459 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3460 replace
? insn
: NULL_RTX
,
3461 is_set_src
|| in_plus
, false);
3462 if (substed_operand
[i
] != orig_operand
[i
])
3464 /* Terminate the search in check_eliminable_occurrences at
3466 *recog_data
.operand_loc
[i
] = 0;
3468 /* If an output operand changed from a REG to a MEM and INSN is an
3469 insn, write a CLOBBER insn. */
3470 if (recog_data
.operand_type
[i
] != OP_IN
3471 && REG_P (orig_operand
[i
])
3472 && MEM_P (substed_operand
[i
])
3474 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3478 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3479 *recog_data
.dup_loc
[i
]
3480 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3482 /* If any eliminable remain, they aren't eliminable anymore. */
3483 check_eliminable_occurrences (old_body
);
3485 /* Substitute the operands; the new values are in the substed_operand
3487 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3488 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3489 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3490 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3492 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3493 re-recognize the insn. We do this in case we had a simple addition
3494 but now can do this as a load-address. This saves an insn in this
3496 If re-recognition fails, the old insn code number will still be used,
3497 and some register operands may have changed into PLUS expressions.
3498 These will be handled by find_reloads by loading them into a register
3503 /* If we aren't replacing things permanently and we changed something,
3504 make another copy to ensure that all the RTL is new. Otherwise
3505 things can go wrong if find_reload swaps commutative operands
3506 and one is inside RTL that has been copied while the other is not. */
3507 new_body
= old_body
;
3510 new_body
= copy_insn (old_body
);
3511 if (REG_NOTES (insn
))
3512 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3514 PATTERN (insn
) = new_body
;
3516 /* If we had a move insn but now we don't, rerecognize it. This will
3517 cause spurious re-recognition if the old move had a PARALLEL since
3518 the new one still will, but we can't call single_set without
3519 having put NEW_BODY into the insn and the re-recognition won't
3520 hurt in this rare case. */
3521 /* ??? Why this huge if statement - why don't we just rerecognize the
3525 && ((REG_P (SET_SRC (old_set
))
3526 && (GET_CODE (new_body
) != SET
3527 || !REG_P (SET_SRC (new_body
))))
3528 /* If this was a load from or store to memory, compare
3529 the MEM in recog_data.operand to the one in the insn.
3530 If they are not equal, then rerecognize the insn. */
3532 && ((MEM_P (SET_SRC (old_set
))
3533 && SET_SRC (old_set
) != recog_data
.operand
[1])
3534 || (MEM_P (SET_DEST (old_set
))
3535 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3536 /* If this was an add insn before, rerecognize. */
3537 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3539 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3541 INSN_CODE (insn
) = new_icode
;
3545 /* Restore the old body. If there were any changes to it, we made a copy
3546 of it while the changes were still in place, so we'll correctly return
3547 a modified insn below. */
3550 /* Restore the old body. */
3551 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3552 /* Restoring a top-level match_parallel would clobber the new_body
3553 we installed in the insn. */
3554 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3555 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3556 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3557 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3560 /* Update all elimination pairs to reflect the status after the current
3561 insn. The changes we make were determined by the earlier call to
3562 elimination_effects.
3564 We also detect cases where register elimination cannot be done,
3565 namely, if a register would be both changed and referenced outside a MEM
3566 in the resulting insn since such an insn is often undefined and, even if
3567 not, we cannot know what meaning will be given to it. Note that it is
3568 valid to have a register used in an address in an insn that changes it
3569 (presumably with a pre- or post-increment or decrement).
3571 If anything changes, return nonzero. */
3573 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3575 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3576 ep
->can_eliminate
= 0;
3578 ep
->ref_outside_mem
= 0;
3580 if (ep
->previous_offset
!= ep
->offset
)
3585 /* If we changed something, perform elimination in REG_NOTES. This is
3586 needed even when REPLACE is zero because a REG_DEAD note might refer
3587 to a register that we eliminate and could cause a different number
3588 of spill registers to be needed in the final reload pass than in
3590 if (val
&& REG_NOTES (insn
) != 0)
3592 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3598 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3599 register allocator. INSN is the instruction we need to examine, we perform
3600 eliminations in its operands and record cases where eliminating a reg with
3601 an invariant equivalence would add extra cost. */
3603 #pragma GCC diagnostic push
3604 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3606 elimination_costs_in_insn (rtx_insn
*insn
)
3608 int icode
= recog_memoized (insn
);
3609 rtx old_body
= PATTERN (insn
);
3610 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3611 rtx old_set
= single_set (insn
);
3613 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3614 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3615 struct elim_table
*ep
;
3616 rtx plus_src
, plus_cst_src
;
3619 if (! insn_is_asm
&& icode
< 0)
3621 gcc_assert (DEBUG_INSN_P (insn
)
3622 || GET_CODE (PATTERN (insn
)) == USE
3623 || GET_CODE (PATTERN (insn
)) == CLOBBER
3624 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3628 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3629 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3631 /* Check for setting an eliminable register. */
3632 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3633 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3637 /* We allow one special case which happens to work on all machines we
3638 currently support: a single set with the source or a REG_EQUAL
3639 note being a PLUS of an eliminable register and a constant. */
3640 plus_src
= plus_cst_src
= 0;
3642 if (old_set
&& REG_P (SET_DEST (old_set
)))
3645 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3646 plus_src
= SET_SRC (old_set
);
3647 /* First see if the source is of the form (plus (...) CST). */
3649 && CONST_INT_P (XEXP (plus_src
, 1)))
3650 plus_cst_src
= plus_src
;
3651 else if (REG_P (SET_SRC (old_set
))
3654 /* Otherwise, see if we have a REG_EQUAL note of the form
3655 (plus (...) CST). */
3657 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3659 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3660 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3661 && GET_CODE (XEXP (links
, 0)) == PLUS
3662 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3664 plus_cst_src
= XEXP (links
, 0);
3671 /* Determine the effects of this insn on elimination offsets. */
3672 elimination_effects (old_body
, VOIDmode
);
3674 /* Eliminate all eliminable registers occurring in operands that
3675 can be handled by reload. */
3676 extract_insn (insn
);
3677 int n_dups
= recog_data
.n_dups
;
3678 for (i
= 0; i
< n_dups
; i
++)
3679 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3681 int n_operands
= recog_data
.n_operands
;
3682 for (i
= 0; i
< n_operands
; i
++)
3684 orig_operand
[i
] = recog_data
.operand
[i
];
3686 /* For an asm statement, every operand is eliminable. */
3687 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3689 bool is_set_src
, in_plus
;
3691 /* Check for setting a register that we know about. */
3692 if (recog_data
.operand_type
[i
] != OP_IN
3693 && REG_P (orig_operand
[i
]))
3695 /* If we are assigning to a register that can be eliminated, it
3696 must be as part of a PARALLEL, since the code above handles
3697 single SETs. We must indicate that we can no longer
3698 eliminate this reg. */
3699 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3701 if (ep
->from_rtx
== orig_operand
[i
])
3702 ep
->can_eliminate
= 0;
3705 /* Companion to the above plus substitution, we can allow
3706 invariants as the source of a plain move. */
3708 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3710 if (is_set_src
&& !sets_reg_p
)
3711 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3713 if (plus_src
&& sets_reg_p
3714 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3715 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3718 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3720 is_set_src
|| in_plus
, true);
3721 /* Terminate the search in check_eliminable_occurrences at
3723 *recog_data
.operand_loc
[i
] = 0;
3727 for (i
= 0; i
< n_dups
; i
++)
3728 *recog_data
.dup_loc
[i
]
3729 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3731 /* If any eliminable remain, they aren't eliminable anymore. */
3732 check_eliminable_occurrences (old_body
);
3734 /* Restore the old body. */
3735 for (i
= 0; i
< n_operands
; i
++)
3736 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3737 for (i
= 0; i
< n_dups
; i
++)
3738 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3740 /* Update all elimination pairs to reflect the status after the current
3741 insn. The changes we make were determined by the earlier call to
3742 elimination_effects. */
3744 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3746 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3747 ep
->can_eliminate
= 0;
3749 ep
->ref_outside_mem
= 0;
3754 #pragma GCC diagnostic pop
3756 /* Loop through all elimination pairs.
3757 Recalculate the number not at initial offset.
3759 Compute the maximum offset (minimum offset if the stack does not
3760 grow downward) for each elimination pair. */
3763 update_eliminable_offsets (void)
3765 struct elim_table
*ep
;
3767 num_not_at_initial_offset
= 0;
3768 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3770 ep
->previous_offset
= ep
->offset
;
3771 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3772 num_not_at_initial_offset
++;
3776 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3777 replacement we currently believe is valid, mark it as not eliminable if X
3778 modifies DEST in any way other than by adding a constant integer to it.
3780 If DEST is the frame pointer, we do nothing because we assume that
3781 all assignments to the hard frame pointer are nonlocal gotos and are being
3782 done at a time when they are valid and do not disturb anything else.
3783 Some machines want to eliminate a fake argument pointer with either the
3784 frame or stack pointer. Assignments to the hard frame pointer must not
3785 prevent this elimination.
3787 Called via note_stores from reload before starting its passes to scan
3788 the insns of the function. */
3791 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3795 /* A SUBREG of a hard register here is just changing its mode. We should
3796 not see a SUBREG of an eliminable hard register, but check just in
3798 if (GET_CODE (dest
) == SUBREG
)
3799 dest
= SUBREG_REG (dest
);
3801 if (dest
== hard_frame_pointer_rtx
)
3804 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3805 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3806 && (GET_CODE (x
) != SET
3807 || GET_CODE (SET_SRC (x
)) != PLUS
3808 || XEXP (SET_SRC (x
), 0) != dest
3809 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3811 reg_eliminate
[i
].can_eliminate_previous
3812 = reg_eliminate
[i
].can_eliminate
= 0;
3817 /* Verify that the initial elimination offsets did not change since the
3818 last call to set_initial_elim_offsets. This is used to catch cases
3819 where something illegal happened during reload_as_needed that could
3820 cause incorrect code to be generated if we did not check for it. */
3823 verify_initial_elim_offsets (void)
3827 if (!num_eliminable
)
3830 #ifdef ELIMINABLE_REGS
3832 struct elim_table
*ep
;
3834 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3836 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3837 if (t
!= ep
->initial_offset
)
3842 INITIAL_FRAME_POINTER_OFFSET (t
);
3843 if (t
!= reg_eliminate
[0].initial_offset
)
3850 /* Reset all offsets on eliminable registers to their initial values. */
3853 set_initial_elim_offsets (void)
3855 struct elim_table
*ep
= reg_eliminate
;
3857 #ifdef ELIMINABLE_REGS
3858 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3860 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3861 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3864 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3865 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3868 num_not_at_initial_offset
= 0;
3871 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3874 set_initial_eh_label_offset (rtx label
)
3876 set_label_offsets (label
, NULL
, 1);
3879 /* Initialize the known label offsets.
3880 Set a known offset for each forced label to be at the initial offset
3881 of each elimination. We do this because we assume that all
3882 computed jumps occur from a location where each elimination is
3883 at its initial offset.
3884 For all other labels, show that we don't know the offsets. */
3887 set_initial_label_offsets (void)
3889 memset (offsets_known_at
, 0, num_labels
);
3893 FOR_EACH_VEC_SAFE_ELT (forced_labels
, i
, insn
)
3894 set_label_offsets (insn
, NULL
, 1);
3896 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3898 set_label_offsets (x
->insn (), NULL
, 1);
3900 for_each_eh_label (set_initial_eh_label_offset
);
3903 /* Set all elimination offsets to the known values for the code label given
3907 set_offsets_for_label (rtx_insn
*insn
)
3910 int label_nr
= CODE_LABEL_NUMBER (insn
);
3911 struct elim_table
*ep
;
3913 num_not_at_initial_offset
= 0;
3914 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3916 ep
->offset
= ep
->previous_offset
3917 = offsets_at
[label_nr
- first_label_num
][i
];
3918 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3919 num_not_at_initial_offset
++;
3923 /* See if anything that happened changes which eliminations are valid.
3924 For example, on the SPARC, whether or not the frame pointer can
3925 be eliminated can depend on what registers have been used. We need
3926 not check some conditions again (such as flag_omit_frame_pointer)
3927 since they can't have changed. */
3930 update_eliminables (HARD_REG_SET
*pset
)
3932 int previous_frame_pointer_needed
= frame_pointer_needed
;
3933 struct elim_table
*ep
;
3935 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3936 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3937 && targetm
.frame_pointer_required ())
3938 #ifdef ELIMINABLE_REGS
3939 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3942 ep
->can_eliminate
= 0;
3944 /* Look for the case where we have discovered that we can't replace
3945 register A with register B and that means that we will now be
3946 trying to replace register A with register C. This means we can
3947 no longer replace register C with register B and we need to disable
3948 such an elimination, if it exists. This occurs often with A == ap,
3949 B == sp, and C == fp. */
3951 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3953 struct elim_table
*op
;
3956 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3958 /* Find the current elimination for ep->from, if there is a
3960 for (op
= reg_eliminate
;
3961 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3962 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3968 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3970 for (op
= reg_eliminate
;
3971 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3972 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3973 op
->can_eliminate
= 0;
3977 /* See if any registers that we thought we could eliminate the previous
3978 time are no longer eliminable. If so, something has changed and we
3979 must spill the register. Also, recompute the number of eliminable
3980 registers and see if the frame pointer is needed; it is if there is
3981 no elimination of the frame pointer that we can perform. */
3983 frame_pointer_needed
= 1;
3984 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3986 if (ep
->can_eliminate
3987 && ep
->from
== FRAME_POINTER_REGNUM
3988 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3989 && (! SUPPORTS_STACK_ALIGNMENT
3990 || ! crtl
->stack_realign_needed
))
3991 frame_pointer_needed
= 0;
3993 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3995 ep
->can_eliminate_previous
= 0;
3996 SET_HARD_REG_BIT (*pset
, ep
->from
);
4001 /* If we didn't need a frame pointer last time, but we do now, spill
4002 the hard frame pointer. */
4003 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4004 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4007 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4008 Return true iff a register was spilled. */
4011 update_eliminables_and_spill (void)
4014 bool did_spill
= false;
4015 HARD_REG_SET to_spill
;
4016 CLEAR_HARD_REG_SET (to_spill
);
4017 update_eliminables (&to_spill
);
4018 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
4020 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4021 if (TEST_HARD_REG_BIT (to_spill
, i
))
4023 spill_hard_reg (i
, 1);
4026 /* Regardless of the state of spills, if we previously had
4027 a register that we thought we could eliminate, but now can
4028 not eliminate, we must run another pass.
4030 Consider pseudos which have an entry in reg_equiv_* which
4031 reference an eliminable register. We must make another pass
4032 to update reg_equiv_* so that we do not substitute in the
4033 old value from when we thought the elimination could be
4039 /* Return true if X is used as the target register of an elimination. */
4042 elimination_target_reg_p (rtx x
)
4044 struct elim_table
*ep
;
4046 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4047 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4053 /* Initialize the table of registers to eliminate.
4054 Pre-condition: global flag frame_pointer_needed has been set before
4055 calling this function. */
4058 init_elim_table (void)
4060 struct elim_table
*ep
;
4061 #ifdef ELIMINABLE_REGS
4062 const struct elim_table_1
*ep1
;
4066 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4070 #ifdef ELIMINABLE_REGS
4071 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4072 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4074 ep
->from
= ep1
->from
;
4076 ep
->can_eliminate
= ep
->can_eliminate_previous
4077 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4078 && ! (ep
->to
== STACK_POINTER_REGNUM
4079 && frame_pointer_needed
4080 && (! SUPPORTS_STACK_ALIGNMENT
4081 || ! stack_realign_fp
)));
4084 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4085 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4086 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4087 = ! frame_pointer_needed
;
4090 /* Count the number of eliminable registers and build the FROM and TO
4091 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4092 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4093 We depend on this. */
4094 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4096 num_eliminable
+= ep
->can_eliminate
;
4097 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4098 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4102 /* Find all the pseudo registers that didn't get hard regs
4103 but do have known equivalent constants or memory slots.
4104 These include parameters (known equivalent to parameter slots)
4105 and cse'd or loop-moved constant memory addresses.
4107 Record constant equivalents in reg_equiv_constant
4108 so they will be substituted by find_reloads.
4109 Record memory equivalents in reg_mem_equiv so they can
4110 be substituted eventually by altering the REG-rtx's. */
4113 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4120 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4122 reg_max_ref_width
= NULL
;
4124 num_eliminable_invariants
= 0;
4126 first_label_num
= get_first_label_num ();
4127 num_labels
= max_label_num () - first_label_num
;
4129 /* Allocate the tables used to store offset information at labels. */
4130 offsets_known_at
= XNEWVEC (char, num_labels
);
4131 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4133 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4134 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4135 find largest such for each pseudo. FIRST is the head of the insn
4138 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4140 rtx set
= single_set (insn
);
4142 /* We may introduce USEs that we want to remove at the end, so
4143 we'll mark them with QImode. Make sure there are no
4144 previously-marked insns left by say regmove. */
4145 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4146 && GET_MODE (insn
) != VOIDmode
)
4147 PUT_MODE (insn
, VOIDmode
);
4149 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4150 scan_paradoxical_subregs (PATTERN (insn
));
4152 if (set
!= 0 && REG_P (SET_DEST (set
)))
4154 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4160 i
= REGNO (SET_DEST (set
));
4163 if (i
<= LAST_VIRTUAL_REGISTER
)
4166 /* If flag_pic and we have constant, verify it's legitimate. */
4168 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4170 /* It can happen that a REG_EQUIV note contains a MEM
4171 that is not a legitimate memory operand. As later
4172 stages of reload assume that all addresses found
4173 in the reg_equiv_* arrays were originally legitimate,
4174 we ignore such REG_EQUIV notes. */
4175 if (memory_operand (x
, VOIDmode
))
4177 /* Always unshare the equivalence, so we can
4178 substitute into this insn without touching the
4180 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4182 else if (function_invariant_p (x
))
4186 mode
= GET_MODE (SET_DEST (set
));
4187 if (GET_CODE (x
) == PLUS
)
4189 /* This is PLUS of frame pointer and a constant,
4190 and might be shared. Unshare it. */
4191 reg_equiv_invariant (i
) = copy_rtx (x
);
4192 num_eliminable_invariants
++;
4194 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4196 reg_equiv_invariant (i
) = x
;
4197 num_eliminable_invariants
++;
4199 else if (targetm
.legitimate_constant_p (mode
, x
))
4200 reg_equiv_constant (i
) = x
;
4203 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4204 if (! reg_equiv_memory_loc (i
))
4205 reg_equiv_init (i
) = NULL
;
4210 reg_equiv_init (i
) = NULL
;
4215 reg_equiv_init (i
) = NULL
;
4220 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4221 if (reg_equiv_init (i
))
4223 fprintf (dump_file
, "init_insns for %u: ", i
);
4224 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4225 fprintf (dump_file
, "\n");
4229 /* Indicate that we no longer have known memory locations or constants.
4230 Free all data involved in tracking these. */
4233 free_reg_equiv (void)
4237 free (offsets_known_at
);
4240 offsets_known_at
= 0;
4242 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4243 if (reg_equiv_alt_mem_list (i
))
4244 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4245 vec_free (reg_equivs
);
4248 /* Kick all pseudos out of hard register REGNO.
4250 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4251 because we found we can't eliminate some register. In the case, no pseudos
4252 are allowed to be in the register, even if they are only in a block that
4253 doesn't require spill registers, unlike the case when we are spilling this
4254 hard reg to produce another spill register.
4256 Return nonzero if any pseudos needed to be kicked out. */
4259 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4265 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4266 df_set_regs_ever_live (regno
, true);
4269 /* Spill every pseudo reg that was allocated to this reg
4270 or to something that overlaps this reg. */
4272 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4273 if (reg_renumber
[i
] >= 0
4274 && (unsigned int) reg_renumber
[i
] <= regno
4275 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4276 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4279 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4280 insns that need reloads, this function is used to actually spill pseudo
4281 registers and try to reallocate them. It also sets up the spill_regs
4282 array for use by choose_reload_regs.
4284 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4285 that we displace from hard registers. */
4288 finish_spills (int global
)
4290 struct insn_chain
*chain
;
4291 int something_changed
= 0;
4293 reg_set_iterator rsi
;
4295 /* Build the spill_regs array for the function. */
4296 /* If there are some registers still to eliminate and one of the spill regs
4297 wasn't ever used before, additional stack space may have to be
4298 allocated to store this register. Thus, we may have changed the offset
4299 between the stack and frame pointers, so mark that something has changed.
4301 One might think that we need only set VAL to 1 if this is a call-used
4302 register. However, the set of registers that must be saved by the
4303 prologue is not identical to the call-used set. For example, the
4304 register used by the call insn for the return PC is a call-used register,
4305 but must be saved by the prologue. */
4308 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4309 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4311 spill_reg_order
[i
] = n_spills
;
4312 spill_regs
[n_spills
++] = i
;
4313 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4314 something_changed
= 1;
4315 df_set_regs_ever_live (i
, true);
4318 spill_reg_order
[i
] = -1;
4320 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4321 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4323 /* Record the current hard register the pseudo is allocated to
4324 in pseudo_previous_regs so we avoid reallocating it to the
4325 same hard reg in a later pass. */
4326 gcc_assert (reg_renumber
[i
] >= 0);
4328 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4329 /* Mark it as no longer having a hard register home. */
4330 reg_renumber
[i
] = -1;
4331 if (ira_conflicts_p
)
4332 /* Inform IRA about the change. */
4333 ira_mark_allocation_change (i
);
4334 /* We will need to scan everything again. */
4335 something_changed
= 1;
4338 /* Retry global register allocation if possible. */
4339 if (global
&& ira_conflicts_p
)
4343 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4344 /* For every insn that needs reloads, set the registers used as spill
4345 regs in pseudo_forbidden_regs for every pseudo live across the
4347 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4349 EXECUTE_IF_SET_IN_REG_SET
4350 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4352 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4353 chain
->used_spill_regs
);
4355 EXECUTE_IF_SET_IN_REG_SET
4356 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4358 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4359 chain
->used_spill_regs
);
4363 /* Retry allocating the pseudos spilled in IRA and the
4364 reload. For each reg, merge the various reg sets that
4365 indicate which hard regs can't be used, and call
4366 ira_reassign_pseudos. */
4367 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4368 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4370 if (reg_renumber
[i
] < 0)
4371 temp_pseudo_reg_arr
[n
++] = i
;
4373 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4375 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4376 bad_spill_regs_global
,
4377 pseudo_forbidden_regs
, pseudo_previous_regs
,
4379 something_changed
= 1;
4381 /* Fix up the register information in the insn chain.
4382 This involves deleting those of the spilled pseudos which did not get
4383 a new hard register home from the live_{before,after} sets. */
4384 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4386 HARD_REG_SET used_by_pseudos
;
4387 HARD_REG_SET used_by_pseudos2
;
4389 if (! ira_conflicts_p
)
4391 /* Don't do it for IRA because IRA and the reload still can
4392 assign hard registers to the spilled pseudos on next
4393 reload iterations. */
4394 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4395 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4397 /* Mark any unallocated hard regs as available for spills. That
4398 makes inheritance work somewhat better. */
4399 if (chain
->need_reload
)
4401 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4402 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4403 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4405 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4406 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4407 /* Value of chain->used_spill_regs from previous iteration
4408 may be not included in the value calculated here because
4409 of possible removing caller-saves insns (see function
4410 delete_caller_save_insns. */
4411 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4412 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4416 CLEAR_REG_SET (&changed_allocation_pseudos
);
4417 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4418 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4420 int regno
= reg_renumber
[i
];
4421 if (reg_old_renumber
[i
] == regno
)
4424 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4426 alter_reg (i
, reg_old_renumber
[i
], false);
4427 reg_old_renumber
[i
] = regno
;
4431 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4433 fprintf (dump_file
, " Register %d now in %d.\n\n",
4434 i
, reg_renumber
[i
]);
4438 return something_changed
;
4441 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4444 scan_paradoxical_subregs (rtx x
)
4448 enum rtx_code code
= GET_CODE (x
);
4464 if (REG_P (SUBREG_REG (x
))
4465 && (GET_MODE_SIZE (GET_MODE (x
))
4466 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4468 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4469 = GET_MODE_SIZE (GET_MODE (x
));
4470 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4478 fmt
= GET_RTX_FORMAT (code
);
4479 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4482 scan_paradoxical_subregs (XEXP (x
, i
));
4483 else if (fmt
[i
] == 'E')
4486 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4487 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4492 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4493 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4494 and apply the corresponding narrowing subreg to *OTHER_PTR.
4495 Return true if the operands were changed, false otherwise. */
4498 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4500 rtx op
, inner
, other
, tem
;
4503 if (!paradoxical_subreg_p (op
))
4505 inner
= SUBREG_REG (op
);
4508 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4512 /* If the lowpart operation turned a hard register into a subreg,
4513 rather than simplifying it to another hard register, then the
4514 mode change cannot be properly represented. For example, OTHER
4515 might be valid in its current mode, but not in the new one. */
4516 if (GET_CODE (tem
) == SUBREG
4518 && HARD_REGISTER_P (other
))
4526 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4527 examine all of the reload insns between PREV and NEXT exclusive, and
4528 annotate all that may trap. */
4531 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4533 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4536 if (!insn_could_throw_p (insn
))
4537 remove_note (insn
, note
);
4538 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4541 /* Reload pseudo-registers into hard regs around each insn as needed.
4542 Additional register load insns are output before the insn that needs it
4543 and perhaps store insns after insns that modify the reloaded pseudo reg.
4545 reg_last_reload_reg and reg_reloaded_contents keep track of
4546 which registers are already available in reload registers.
4547 We update these for the reloads that we perform,
4548 as the insns are scanned. */
4551 reload_as_needed (int live_known
)
4553 struct insn_chain
*chain
;
4559 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4560 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4561 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4562 INIT_REG_SET (®_has_output_reload
);
4563 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4564 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4566 set_initial_elim_offsets ();
4568 /* Generate a marker insn that we will move around. */
4569 marker
= emit_note (NOTE_INSN_DELETED
);
4570 unlink_insn_chain (marker
, marker
);
4572 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4575 rtx_insn
*insn
= chain
->insn
;
4576 rtx_insn
*old_next
= NEXT_INSN (insn
);
4578 rtx_insn
*old_prev
= PREV_INSN (insn
);
4581 if (will_delete_init_insn_p (insn
))
4584 /* If we pass a label, copy the offsets from the label information
4585 into the current offsets of each elimination. */
4587 set_offsets_for_label (insn
);
4589 else if (INSN_P (insn
))
4591 regset_head regs_to_forget
;
4592 INIT_REG_SET (®s_to_forget
);
4593 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4595 /* If this is a USE and CLOBBER of a MEM, ensure that any
4596 references to eliminable registers have been removed. */
4598 if ((GET_CODE (PATTERN (insn
)) == USE
4599 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4600 && MEM_P (XEXP (PATTERN (insn
), 0)))
4601 XEXP (XEXP (PATTERN (insn
), 0), 0)
4602 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4603 GET_MODE (XEXP (PATTERN (insn
), 0)),
4606 /* If we need to do register elimination processing, do so.
4607 This might delete the insn, in which case we are done. */
4608 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4610 eliminate_regs_in_insn (insn
, 1);
4613 update_eliminable_offsets ();
4614 CLEAR_REG_SET (®s_to_forget
);
4619 /* If need_elim is nonzero but need_reload is zero, one might think
4620 that we could simply set n_reloads to 0. However, find_reloads
4621 could have done some manipulation of the insn (such as swapping
4622 commutative operands), and these manipulations are lost during
4623 the first pass for every insn that needs register elimination.
4624 So the actions of find_reloads must be redone here. */
4626 if (! chain
->need_elim
&& ! chain
->need_reload
4627 && ! chain
->need_operand_change
)
4629 /* First find the pseudo regs that must be reloaded for this insn.
4630 This info is returned in the tables reload_... (see reload.h).
4631 Also modify the body of INSN by substituting RELOAD
4632 rtx's for those pseudo regs. */
4635 CLEAR_REG_SET (®_has_output_reload
);
4636 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4638 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4644 rtx_insn
*next
= NEXT_INSN (insn
);
4646 /* ??? PREV can get deleted by reload inheritance.
4647 Work around this by emitting a marker note. */
4648 prev
= PREV_INSN (insn
);
4649 reorder_insns_nobb (marker
, marker
, prev
);
4651 /* Now compute which reload regs to reload them into. Perhaps
4652 reusing reload regs from previous insns, or else output
4653 load insns to reload them. Maybe output store insns too.
4654 Record the choices of reload reg in reload_reg_rtx. */
4655 choose_reload_regs (chain
);
4657 /* Generate the insns to reload operands into or out of
4658 their reload regs. */
4659 emit_reload_insns (chain
);
4661 /* Substitute the chosen reload regs from reload_reg_rtx
4662 into the insn's body (or perhaps into the bodies of other
4663 load and store insn that we just made for reloading
4664 and that we moved the structure into). */
4665 subst_reloads (insn
);
4667 prev
= PREV_INSN (marker
);
4668 unlink_insn_chain (marker
, marker
);
4670 /* Adjust the exception region notes for loads and stores. */
4671 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4672 fixup_eh_region_note (insn
, prev
, next
);
4674 /* Adjust the location of REG_ARGS_SIZE. */
4675 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4678 remove_note (insn
, p
);
4679 fixup_args_size_notes (prev
, PREV_INSN (next
),
4680 INTVAL (XEXP (p
, 0)));
4683 /* If this was an ASM, make sure that all the reload insns
4684 we have generated are valid. If not, give an error
4686 if (asm_noperands (PATTERN (insn
)) >= 0)
4687 for (rtx_insn
*p
= NEXT_INSN (prev
);
4690 if (p
!= insn
&& INSN_P (p
)
4691 && GET_CODE (PATTERN (p
)) != USE
4692 && (recog_memoized (p
) < 0
4693 || (extract_insn (p
),
4694 !(constrain_operands (1,
4695 get_enabled_alternatives (p
))))))
4697 error_for_asm (insn
,
4698 "%<asm%> operand requires "
4699 "impossible reload");
4704 if (num_eliminable
&& chain
->need_elim
)
4705 update_eliminable_offsets ();
4707 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4708 is no longer validly lying around to save a future reload.
4709 Note that this does not detect pseudos that were reloaded
4710 for this insn in order to be stored in
4711 (obeying register constraints). That is correct; such reload
4712 registers ARE still valid. */
4713 forget_marked_reloads (®s_to_forget
);
4714 CLEAR_REG_SET (®s_to_forget
);
4716 /* There may have been CLOBBER insns placed after INSN. So scan
4717 between INSN and NEXT and use them to forget old reloads. */
4718 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4719 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4720 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4723 /* Likewise for regs altered by auto-increment in this insn.
4724 REG_INC notes have been changed by reloading:
4725 find_reloads_address_1 records substitutions for them,
4726 which have been performed by subst_reloads above. */
4727 for (i
= n_reloads
- 1; i
>= 0; i
--)
4729 rtx in_reg
= rld
[i
].in_reg
;
4732 enum rtx_code code
= GET_CODE (in_reg
);
4733 /* PRE_INC / PRE_DEC will have the reload register ending up
4734 with the same value as the stack slot, but that doesn't
4735 hold true for POST_INC / POST_DEC. Either we have to
4736 convert the memory access to a true POST_INC / POST_DEC,
4737 or we can't use the reload register for inheritance. */
4738 if ((code
== POST_INC
|| code
== POST_DEC
)
4739 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4740 REGNO (rld
[i
].reg_rtx
))
4741 /* Make sure it is the inc/dec pseudo, and not
4742 some other (e.g. output operand) pseudo. */
4743 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4744 == REGNO (XEXP (in_reg
, 0))))
4747 rtx reload_reg
= rld
[i
].reg_rtx
;
4748 machine_mode mode
= GET_MODE (reload_reg
);
4752 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4754 /* We really want to ignore REG_INC notes here, so
4755 use PATTERN (p) as argument to reg_set_p . */
4756 if (reg_set_p (reload_reg
, PATTERN (p
)))
4758 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4764 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4766 validate_replace_rtx_group (reload_reg
,
4768 n
= verify_changes (0);
4770 /* We must also verify that the constraints
4771 are met after the replacement. Make sure
4772 extract_insn is only called for an insn
4773 where the replacements were found to be
4778 n
= constrain_operands (1,
4779 get_enabled_alternatives (p
));
4782 /* If the constraints were not met, then
4783 undo the replacement, else confirm it. */
4787 confirm_change_group ();
4793 add_reg_note (p
, REG_INC
, reload_reg
);
4794 /* Mark this as having an output reload so that the
4795 REG_INC processing code below won't invalidate
4796 the reload for inheritance. */
4797 SET_HARD_REG_BIT (reg_is_output_reload
,
4798 REGNO (reload_reg
));
4799 SET_REGNO_REG_SET (®_has_output_reload
,
4800 REGNO (XEXP (in_reg
, 0)));
4803 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4806 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4807 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4808 REGNO (rld
[i
].reg_rtx
))
4809 /* Make sure it is the inc/dec pseudo, and not
4810 some other (e.g. output operand) pseudo. */
4811 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4812 == REGNO (XEXP (in_reg
, 0))))
4814 SET_HARD_REG_BIT (reg_is_output_reload
,
4815 REGNO (rld
[i
].reg_rtx
));
4816 SET_REGNO_REG_SET (®_has_output_reload
,
4817 REGNO (XEXP (in_reg
, 0)));
4819 else if (code
== PRE_INC
|| code
== PRE_DEC
4820 || code
== POST_INC
|| code
== POST_DEC
)
4822 int in_regno
= REGNO (XEXP (in_reg
, 0));
4824 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4827 bool forget_p
= true;
4829 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4830 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4833 for (rtx_insn
*x
= (old_prev
?
4834 NEXT_INSN (old_prev
) : insn
);
4837 if (x
== reg_reloaded_insn
[in_hard_regno
])
4843 /* If for some reasons, we didn't set up
4844 reg_last_reload_reg in this insn,
4845 invalidate inheritance from previous
4846 insns for the incremented/decremented
4847 register. Such registers will be not in
4848 reg_has_output_reload. Invalidate it
4849 also if the corresponding element in
4850 reg_reloaded_insn is also
4853 forget_old_reloads_1 (XEXP (in_reg
, 0),
4859 /* If a pseudo that got a hard register is auto-incremented,
4860 we must purge records of copying it into pseudos without
4862 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4863 if (REG_NOTE_KIND (x
) == REG_INC
)
4865 /* See if this pseudo reg was reloaded in this insn.
4866 If so, its last-reload info is still valid
4867 because it is based on this insn's reload. */
4868 for (i
= 0; i
< n_reloads
; i
++)
4869 if (rld
[i
].out
== XEXP (x
, 0))
4873 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4877 /* A reload reg's contents are unknown after a label. */
4879 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4881 /* Don't assume a reload reg is still good after a call insn
4882 if it is a call-used reg, or if it contains a value that will
4883 be partially clobbered by the call. */
4884 else if (CALL_P (insn
))
4886 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4887 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4889 /* If this is a call to a setjmp-type function, we must not
4890 reuse any reload reg contents across the call; that will
4891 just be clobbered by other uses of the register in later
4892 code, before the longjmp. */
4893 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4894 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4899 free (reg_last_reload_reg
);
4900 CLEAR_REG_SET (®_has_output_reload
);
4903 /* Discard all record of any value reloaded from X,
4904 or reloaded in X from someplace else;
4905 unless X is an output reload reg of the current insn.
4907 X may be a hard reg (the reload reg)
4908 or it may be a pseudo reg that was reloaded from.
4910 When DATA is non-NULL just mark the registers in regset
4911 to be forgotten later. */
4914 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4919 regset regs
= (regset
) data
;
4921 /* note_stores does give us subregs of hard regs,
4922 subreg_regno_offset requires a hard reg. */
4923 while (GET_CODE (x
) == SUBREG
)
4925 /* We ignore the subreg offset when calculating the regno,
4926 because we are using the entire underlying hard register
4936 if (regno
>= FIRST_PSEUDO_REGISTER
)
4942 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4943 /* Storing into a spilled-reg invalidates its contents.
4944 This can happen if a block-local pseudo is allocated to that reg
4945 and it wasn't spilled because this block's total need is 0.
4946 Then some insn might have an optional reload and use this reg. */
4948 for (i
= 0; i
< nr
; i
++)
4949 /* But don't do this if the reg actually serves as an output
4950 reload reg in the current instruction. */
4952 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4954 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4955 spill_reg_store
[regno
+ i
] = 0;
4961 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4964 /* Since value of X has changed,
4965 forget any value previously copied from it. */
4968 /* But don't forget a copy if this is the output reload
4969 that establishes the copy's validity. */
4971 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4972 reg_last_reload_reg
[regno
+ nr
] = 0;
4976 /* Forget the reloads marked in regset by previous function. */
4978 forget_marked_reloads (regset regs
)
4981 reg_set_iterator rsi
;
4982 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4984 if (reg
< FIRST_PSEUDO_REGISTER
4985 /* But don't do this if the reg actually serves as an output
4986 reload reg in the current instruction. */
4988 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4990 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4991 spill_reg_store
[reg
] = 0;
4994 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4995 reg_last_reload_reg
[reg
] = 0;
4999 /* The following HARD_REG_SETs indicate when each hard register is
5000 used for a reload of various parts of the current insn. */
5002 /* If reg is unavailable for all reloads. */
5003 static HARD_REG_SET reload_reg_unavailable
;
5004 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5005 static HARD_REG_SET reload_reg_used
;
5006 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5007 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5008 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5009 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5010 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5011 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5012 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5013 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5014 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5015 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5016 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5017 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5018 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5019 static HARD_REG_SET reload_reg_used_in_op_addr
;
5020 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5021 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5022 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5023 static HARD_REG_SET reload_reg_used_in_insn
;
5024 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5025 static HARD_REG_SET reload_reg_used_in_other_addr
;
5027 /* If reg is in use as a reload reg for any sort of reload. */
5028 static HARD_REG_SET reload_reg_used_at_all
;
5030 /* If reg is use as an inherited reload. We just mark the first register
5032 static HARD_REG_SET reload_reg_used_for_inherit
;
5034 /* Records which hard regs are used in any way, either as explicit use or
5035 by being allocated to a pseudo during any point of the current insn. */
5036 static HARD_REG_SET reg_used_in_insn
;
5038 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5039 TYPE. MODE is used to indicate how many consecutive regs are
5043 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5049 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5052 case RELOAD_FOR_INPUT_ADDRESS
:
5053 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5056 case RELOAD_FOR_INPADDR_ADDRESS
:
5057 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5060 case RELOAD_FOR_OUTPUT_ADDRESS
:
5061 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5064 case RELOAD_FOR_OUTADDR_ADDRESS
:
5065 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5068 case RELOAD_FOR_OPERAND_ADDRESS
:
5069 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5072 case RELOAD_FOR_OPADDR_ADDR
:
5073 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5076 case RELOAD_FOR_OTHER_ADDRESS
:
5077 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5080 case RELOAD_FOR_INPUT
:
5081 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5084 case RELOAD_FOR_OUTPUT
:
5085 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5088 case RELOAD_FOR_INSN
:
5089 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5093 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5096 /* Similarly, but show REGNO is no longer in use for a reload. */
5099 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5100 enum reload_type type
, machine_mode mode
)
5102 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5103 unsigned int start_regno
, end_regno
, r
;
5105 /* A complication is that for some reload types, inheritance might
5106 allow multiple reloads of the same types to share a reload register.
5107 We set check_opnum if we have to check only reloads with the same
5108 operand number, and check_any if we have to check all reloads. */
5109 int check_opnum
= 0;
5111 HARD_REG_SET
*used_in_set
;
5116 used_in_set
= &reload_reg_used
;
5119 case RELOAD_FOR_INPUT_ADDRESS
:
5120 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5123 case RELOAD_FOR_INPADDR_ADDRESS
:
5125 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5128 case RELOAD_FOR_OUTPUT_ADDRESS
:
5129 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5132 case RELOAD_FOR_OUTADDR_ADDRESS
:
5134 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5137 case RELOAD_FOR_OPERAND_ADDRESS
:
5138 used_in_set
= &reload_reg_used_in_op_addr
;
5141 case RELOAD_FOR_OPADDR_ADDR
:
5143 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5146 case RELOAD_FOR_OTHER_ADDRESS
:
5147 used_in_set
= &reload_reg_used_in_other_addr
;
5151 case RELOAD_FOR_INPUT
:
5152 used_in_set
= &reload_reg_used_in_input
[opnum
];
5155 case RELOAD_FOR_OUTPUT
:
5156 used_in_set
= &reload_reg_used_in_output
[opnum
];
5159 case RELOAD_FOR_INSN
:
5160 used_in_set
= &reload_reg_used_in_insn
;
5165 /* We resolve conflicts with remaining reloads of the same type by
5166 excluding the intervals of reload registers by them from the
5167 interval of freed reload registers. Since we only keep track of
5168 one set of interval bounds, we might have to exclude somewhat
5169 more than what would be necessary if we used a HARD_REG_SET here.
5170 But this should only happen very infrequently, so there should
5171 be no reason to worry about it. */
5173 start_regno
= regno
;
5174 end_regno
= regno
+ nregs
;
5175 if (check_opnum
|| check_any
)
5177 for (i
= n_reloads
- 1; i
>= 0; i
--)
5179 if (rld
[i
].when_needed
== type
5180 && (check_any
|| rld
[i
].opnum
== opnum
)
5183 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5184 unsigned int conflict_end
5185 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5187 /* If there is an overlap with the first to-be-freed register,
5188 adjust the interval start. */
5189 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5190 start_regno
= conflict_end
;
5191 /* Otherwise, if there is a conflict with one of the other
5192 to-be-freed registers, adjust the interval end. */
5193 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5194 end_regno
= conflict_start
;
5199 for (r
= start_regno
; r
< end_regno
; r
++)
5200 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5203 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5204 specified by OPNUM and TYPE. */
5207 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5211 /* In use for a RELOAD_OTHER means it's not available for anything. */
5212 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5213 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5219 /* In use for anything means we can't use it for RELOAD_OTHER. */
5220 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5221 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5222 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5223 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5226 for (i
= 0; i
< reload_n_operands
; i
++)
5227 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5228 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5229 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5230 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5231 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5232 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5237 case RELOAD_FOR_INPUT
:
5238 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5239 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5242 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5245 /* If it is used for some other input, can't use it. */
5246 for (i
= 0; i
< reload_n_operands
; i
++)
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5250 /* If it is used in a later operand's address, can't use it. */
5251 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5252 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5253 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5258 case RELOAD_FOR_INPUT_ADDRESS
:
5259 /* Can't use a register if it is used for an input address for this
5260 operand or used as an input in an earlier one. */
5261 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5262 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5265 for (i
= 0; i
< opnum
; i
++)
5266 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5271 case RELOAD_FOR_INPADDR_ADDRESS
:
5272 /* Can't use a register if it is used for an input address
5273 for this operand or used as an input in an earlier
5275 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5278 for (i
= 0; i
< opnum
; i
++)
5279 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5284 case RELOAD_FOR_OUTPUT_ADDRESS
:
5285 /* Can't use a register if it is used for an output address for this
5286 operand or used as an output in this or a later operand. Note
5287 that multiple output operands are emitted in reverse order, so
5288 the conflicting ones are those with lower indices. */
5289 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5292 for (i
= 0; i
<= opnum
; i
++)
5293 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5298 case RELOAD_FOR_OUTADDR_ADDRESS
:
5299 /* Can't use a register if it is used for an output address
5300 for this operand or used as an output in this or a
5301 later operand. Note that multiple output operands are
5302 emitted in reverse order, so the conflicting ones are
5303 those with lower indices. */
5304 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5307 for (i
= 0; i
<= opnum
; i
++)
5308 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5313 case RELOAD_FOR_OPERAND_ADDRESS
:
5314 for (i
= 0; i
< reload_n_operands
; i
++)
5315 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5318 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5319 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5321 case RELOAD_FOR_OPADDR_ADDR
:
5322 for (i
= 0; i
< reload_n_operands
; i
++)
5323 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5326 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5328 case RELOAD_FOR_OUTPUT
:
5329 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5330 outputs, or an operand address for this or an earlier output.
5331 Note that multiple output operands are emitted in reverse order,
5332 so the conflicting ones are those with higher indices. */
5333 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5336 for (i
= 0; i
< reload_n_operands
; i
++)
5337 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5340 for (i
= opnum
; i
< reload_n_operands
; i
++)
5341 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5342 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5347 case RELOAD_FOR_INSN
:
5348 for (i
= 0; i
< reload_n_operands
; i
++)
5349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5350 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5353 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5354 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5356 case RELOAD_FOR_OTHER_ADDRESS
:
5357 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5364 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5365 the number RELOADNUM, is still available in REGNO at the end of the insn.
5367 We can assume that the reload reg was already tested for availability
5368 at the time it is needed, and we should not check this again,
5369 in case the reg has already been marked in use. */
5372 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5374 int opnum
= rld
[reloadnum
].opnum
;
5375 enum reload_type type
= rld
[reloadnum
].when_needed
;
5378 /* See if there is a reload with the same type for this operand, using
5379 the same register. This case is not handled by the code below. */
5380 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5385 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5387 reg
= rld
[i
].reg_rtx
;
5388 if (reg
== NULL_RTX
)
5390 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5391 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5398 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5399 its value must reach the end. */
5402 /* If this use is for part of the insn,
5403 its value reaches if no subsequent part uses the same register.
5404 Just like the above function, don't try to do this with lots
5407 case RELOAD_FOR_OTHER_ADDRESS
:
5408 /* Here we check for everything else, since these don't conflict
5409 with anything else and everything comes later. */
5411 for (i
= 0; i
< reload_n_operands
; i
++)
5412 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5413 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5414 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5416 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5417 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5420 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5421 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5422 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5423 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5425 case RELOAD_FOR_INPUT_ADDRESS
:
5426 case RELOAD_FOR_INPADDR_ADDRESS
:
5427 /* Similar, except that we check only for this and subsequent inputs
5428 and the address of only subsequent inputs and we do not need
5429 to check for RELOAD_OTHER objects since they are known not to
5432 for (i
= opnum
; i
< reload_n_operands
; i
++)
5433 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5436 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5437 could be killed if the register is also used by reload with type
5438 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5439 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5440 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5443 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5444 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5445 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5448 for (i
= 0; i
< reload_n_operands
; i
++)
5449 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5450 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5451 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5454 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5457 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5458 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5459 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5461 case RELOAD_FOR_INPUT
:
5462 /* Similar to input address, except we start at the next operand for
5463 both input and input address and we do not check for
5464 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5467 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5468 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5469 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5470 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5473 /* ... fall through ... */
5475 case RELOAD_FOR_OPERAND_ADDRESS
:
5476 /* Check outputs and their addresses. */
5478 for (i
= 0; i
< reload_n_operands
; i
++)
5479 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5480 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5481 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5484 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5486 case RELOAD_FOR_OPADDR_ADDR
:
5487 for (i
= 0; i
< reload_n_operands
; i
++)
5488 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5489 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5490 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5493 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5494 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5495 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5497 case RELOAD_FOR_INSN
:
5498 /* These conflict with other outputs with RELOAD_OTHER. So
5499 we need only check for output addresses. */
5501 opnum
= reload_n_operands
;
5505 case RELOAD_FOR_OUTPUT
:
5506 case RELOAD_FOR_OUTPUT_ADDRESS
:
5507 case RELOAD_FOR_OUTADDR_ADDRESS
:
5508 /* We already know these can't conflict with a later output. So the
5509 only thing to check are later output addresses.
5510 Note that multiple output operands are emitted in reverse order,
5511 so the conflicting ones are those with lower indices. */
5512 for (i
= 0; i
< opnum
; i
++)
5513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5514 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5517 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5518 could be killed if the register is also used by reload with type
5519 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5520 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5521 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5531 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5532 every register in REG. */
5535 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5539 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5540 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5546 /* Returns whether R1 and R2 are uniquely chained: the value of one
5547 is used by the other, and that value is not used by any other
5548 reload for this insn. This is used to partially undo the decision
5549 made in find_reloads when in the case of multiple
5550 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5551 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5552 reloads. This code tries to avoid the conflict created by that
5553 change. It might be cleaner to explicitly keep track of which
5554 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5555 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5556 this after the fact. */
5558 reloads_unique_chain_p (int r1
, int r2
)
5562 /* We only check input reloads. */
5563 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5566 /* Avoid anything with output reloads. */
5567 if (rld
[r1
].out
|| rld
[r2
].out
)
5570 /* "chained" means one reload is a component of the other reload,
5571 not the same as the other reload. */
5572 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5573 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5574 || rld
[r1
].optional
|| rld
[r2
].optional
5575 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5576 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5579 /* The following loop assumes that r1 is the reload that feeds r2. */
5583 for (i
= 0; i
< n_reloads
; i
++)
5584 /* Look for input reloads that aren't our two */
5585 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5587 /* If our reload is mentioned at all, it isn't a simple chain. */
5588 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5594 /* The recursive function change all occurrences of WHAT in *WHERE
5597 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5606 if (*where
== what
|| rtx_equal_p (*where
, what
))
5608 /* Record the location of the changed rtx. */
5609 substitute_stack
.safe_push (where
);
5614 code
= GET_CODE (*where
);
5615 fmt
= GET_RTX_FORMAT (code
);
5616 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5622 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5623 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5625 else if (fmt
[i
] == 'e')
5626 substitute (&XEXP (*where
, i
), what
, repl
);
5630 /* The function returns TRUE if chain of reload R1 and R2 (in any
5631 order) can be evaluated without usage of intermediate register for
5632 the reload containing another reload. It is important to see
5633 gen_reload to understand what the function is trying to do. As an
5634 example, let us have reload chain
5637 r1: <something> + const
5639 and reload R2 got reload reg HR. The function returns true if
5640 there is a correct insn HR = HR + <something>. Otherwise,
5641 gen_reload will use intermediate register (and this is the reload
5642 reg for R1) to reload <something>.
5644 We need this function to find a conflict for chain reloads. In our
5645 example, if HR = HR + <something> is incorrect insn, then we cannot
5646 use HR as a reload register for R2. If we do use it then we get a
5655 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5657 /* Assume other cases in gen_reload are not possible for
5658 chain reloads or do need an intermediate hard registers. */
5663 rtx_insn
*last
= get_last_insn ();
5665 /* Make r2 a component of r1. */
5666 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5669 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5670 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5671 gcc_assert (regno
>= 0);
5672 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5674 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5676 /* If IN is a paradoxical SUBREG, remove it and try to put the
5677 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5678 strip_paradoxical_subreg (&in
, &out
);
5680 if (GET_CODE (in
) == PLUS
5681 && (REG_P (XEXP (in
, 0))
5682 || GET_CODE (XEXP (in
, 0)) == SUBREG
5683 || MEM_P (XEXP (in
, 0)))
5684 && (REG_P (XEXP (in
, 1))
5685 || GET_CODE (XEXP (in
, 1)) == SUBREG
5686 || CONSTANT_P (XEXP (in
, 1))
5687 || MEM_P (XEXP (in
, 1))))
5689 insn
= emit_insn (gen_rtx_SET (out
, in
));
5690 code
= recog_memoized (insn
);
5695 extract_insn (insn
);
5696 /* We want constrain operands to treat this insn strictly in
5697 its validity determination, i.e., the way it would after
5698 reload has completed. */
5699 result
= constrain_operands (1, get_enabled_alternatives (insn
));
5702 delete_insns_since (last
);
5705 /* Restore the original value at each changed address within R1. */
5706 while (!substitute_stack
.is_empty ())
5708 rtx
*where
= substitute_stack
.pop ();
5709 *where
= rld
[r2
].in
;
5715 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5718 This function uses the same algorithm as reload_reg_free_p above. */
5721 reloads_conflict (int r1
, int r2
)
5723 enum reload_type r1_type
= rld
[r1
].when_needed
;
5724 enum reload_type r2_type
= rld
[r2
].when_needed
;
5725 int r1_opnum
= rld
[r1
].opnum
;
5726 int r2_opnum
= rld
[r2
].opnum
;
5728 /* RELOAD_OTHER conflicts with everything. */
5729 if (r2_type
== RELOAD_OTHER
)
5732 /* Otherwise, check conflicts differently for each type. */
5736 case RELOAD_FOR_INPUT
:
5737 return (r2_type
== RELOAD_FOR_INSN
5738 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5739 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5740 || r2_type
== RELOAD_FOR_INPUT
5741 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5742 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5743 && r2_opnum
> r1_opnum
));
5745 case RELOAD_FOR_INPUT_ADDRESS
:
5746 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5747 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5749 case RELOAD_FOR_INPADDR_ADDRESS
:
5750 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5751 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5753 case RELOAD_FOR_OUTPUT_ADDRESS
:
5754 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5755 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5757 case RELOAD_FOR_OUTADDR_ADDRESS
:
5758 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5759 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5761 case RELOAD_FOR_OPERAND_ADDRESS
:
5762 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5763 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5764 && (!reloads_unique_chain_p (r1
, r2
)
5765 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5767 case RELOAD_FOR_OPADDR_ADDR
:
5768 return (r2_type
== RELOAD_FOR_INPUT
5769 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5771 case RELOAD_FOR_OUTPUT
:
5772 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5773 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5774 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5775 && r2_opnum
>= r1_opnum
));
5777 case RELOAD_FOR_INSN
:
5778 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5779 || r2_type
== RELOAD_FOR_INSN
5780 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5782 case RELOAD_FOR_OTHER_ADDRESS
:
5783 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5793 /* Indexed by reload number, 1 if incoming value
5794 inherited from previous insns. */
5795 static char reload_inherited
[MAX_RELOADS
];
5797 /* For an inherited reload, this is the insn the reload was inherited from,
5798 if we know it. Otherwise, this is 0. */
5799 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5801 /* If nonzero, this is a place to get the value of the reload,
5802 rather than using reload_in. */
5803 static rtx reload_override_in
[MAX_RELOADS
];
5805 /* For each reload, the hard register number of the register used,
5806 or -1 if we did not need a register for this reload. */
5807 static int reload_spill_index
[MAX_RELOADS
];
5809 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5810 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5812 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5813 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5815 /* Subroutine of free_for_value_p, used to check a single register.
5816 START_REGNO is the starting regno of the full reload register
5817 (possibly comprising multiple hard registers) that we are considering. */
5820 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5821 enum reload_type type
, rtx value
, rtx out
,
5822 int reloadnum
, int ignore_address_reloads
)
5825 /* Set if we see an input reload that must not share its reload register
5826 with any new earlyclobber, but might otherwise share the reload
5827 register with an output or input-output reload. */
5828 int check_earlyclobber
= 0;
5832 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5835 if (out
== const0_rtx
)
5841 /* We use some pseudo 'time' value to check if the lifetimes of the
5842 new register use would overlap with the one of a previous reload
5843 that is not read-only or uses a different value.
5844 The 'time' used doesn't have to be linear in any shape or form, just
5846 Some reload types use different 'buckets' for each operand.
5847 So there are MAX_RECOG_OPERANDS different time values for each
5849 We compute TIME1 as the time when the register for the prospective
5850 new reload ceases to be live, and TIME2 for each existing
5851 reload as the time when that the reload register of that reload
5853 Where there is little to be gained by exact lifetime calculations,
5854 we just make conservative assumptions, i.e. a longer lifetime;
5855 this is done in the 'default:' cases. */
5858 case RELOAD_FOR_OTHER_ADDRESS
:
5859 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5860 time1
= copy
? 0 : 1;
5863 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5865 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5866 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5867 respectively, to the time values for these, we get distinct time
5868 values. To get distinct time values for each operand, we have to
5869 multiply opnum by at least three. We round that up to four because
5870 multiply by four is often cheaper. */
5871 case RELOAD_FOR_INPADDR_ADDRESS
:
5872 time1
= opnum
* 4 + 2;
5874 case RELOAD_FOR_INPUT_ADDRESS
:
5875 time1
= opnum
* 4 + 3;
5877 case RELOAD_FOR_INPUT
:
5878 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5879 executes (inclusive). */
5880 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5882 case RELOAD_FOR_OPADDR_ADDR
:
5884 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5885 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5887 case RELOAD_FOR_OPERAND_ADDRESS
:
5888 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5890 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5892 case RELOAD_FOR_OUTADDR_ADDRESS
:
5893 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5895 case RELOAD_FOR_OUTPUT_ADDRESS
:
5896 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5899 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5902 for (i
= 0; i
< n_reloads
; i
++)
5904 rtx reg
= rld
[i
].reg_rtx
;
5905 if (reg
&& REG_P (reg
)
5906 && ((unsigned) regno
- true_regnum (reg
)
5907 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5910 rtx other_input
= rld
[i
].in
;
5912 /* If the other reload loads the same input value, that
5913 will not cause a conflict only if it's loading it into
5914 the same register. */
5915 if (true_regnum (reg
) != start_regno
)
5916 other_input
= NULL_RTX
;
5917 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5918 || rld
[i
].out
|| out
)
5921 switch (rld
[i
].when_needed
)
5923 case RELOAD_FOR_OTHER_ADDRESS
:
5926 case RELOAD_FOR_INPADDR_ADDRESS
:
5927 /* find_reloads makes sure that a
5928 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5929 by at most one - the first -
5930 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5931 address reload is inherited, the address address reload
5932 goes away, so we can ignore this conflict. */
5933 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5934 && ignore_address_reloads
5935 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5936 Then the address address is still needed to store
5937 back the new address. */
5938 && ! rld
[reloadnum
].out
)
5940 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5941 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5943 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5944 && ignore_address_reloads
5945 /* Unless we are reloading an auto_inc expression. */
5946 && ! rld
[reloadnum
].out
)
5948 time2
= rld
[i
].opnum
* 4 + 2;
5950 case RELOAD_FOR_INPUT_ADDRESS
:
5951 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5952 && ignore_address_reloads
5953 && ! rld
[reloadnum
].out
)
5955 time2
= rld
[i
].opnum
* 4 + 3;
5957 case RELOAD_FOR_INPUT
:
5958 time2
= rld
[i
].opnum
* 4 + 4;
5959 check_earlyclobber
= 1;
5961 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5962 == MAX_RECOG_OPERAND * 4 */
5963 case RELOAD_FOR_OPADDR_ADDR
:
5964 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5965 && ignore_address_reloads
5966 && ! rld
[reloadnum
].out
)
5968 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5970 case RELOAD_FOR_OPERAND_ADDRESS
:
5971 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5972 check_earlyclobber
= 1;
5974 case RELOAD_FOR_INSN
:
5975 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5977 case RELOAD_FOR_OUTPUT
:
5978 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5979 instruction is executed. */
5980 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5982 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5983 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5985 case RELOAD_FOR_OUTADDR_ADDRESS
:
5986 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5987 && ignore_address_reloads
5988 && ! rld
[reloadnum
].out
)
5990 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5992 case RELOAD_FOR_OUTPUT_ADDRESS
:
5993 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5996 /* If there is no conflict in the input part, handle this
5997 like an output reload. */
5998 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
6000 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6001 /* Earlyclobbered outputs must conflict with inputs. */
6002 if (earlyclobber_operand_p (rld
[i
].out
))
6003 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6008 /* RELOAD_OTHER might be live beyond instruction execution,
6009 but this is not obvious when we set time2 = 1. So check
6010 here if there might be a problem with the new reload
6011 clobbering the register used by the RELOAD_OTHER. */
6019 && (! rld
[i
].in
|| rld
[i
].out
6020 || ! rtx_equal_p (other_input
, value
)))
6021 || (out
&& rld
[reloadnum
].out_reg
6022 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6028 /* Earlyclobbered outputs must conflict with inputs. */
6029 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6035 /* Return 1 if the value in reload reg REGNO, as used by a reload
6036 needed for the part of the insn specified by OPNUM and TYPE,
6037 may be used to load VALUE into it.
6039 MODE is the mode in which the register is used, this is needed to
6040 determine how many hard regs to test.
6042 Other read-only reloads with the same value do not conflict
6043 unless OUT is nonzero and these other reloads have to live while
6044 output reloads live.
6045 If OUT is CONST0_RTX, this is a special case: it means that the
6046 test should not be for using register REGNO as reload register, but
6047 for copying from register REGNO into the reload register.
6049 RELOADNUM is the number of the reload we want to load this value for;
6050 a reload does not conflict with itself.
6052 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6053 reloads that load an address for the very reload we are considering.
6055 The caller has to make sure that there is no conflict with the return
6059 free_for_value_p (int regno
, machine_mode mode
, int opnum
,
6060 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6061 int ignore_address_reloads
)
6063 int nregs
= hard_regno_nregs
[regno
][mode
];
6065 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6066 value
, out
, reloadnum
,
6067 ignore_address_reloads
))
6072 /* Return nonzero if the rtx X is invariant over the current function. */
6073 /* ??? Actually, the places where we use this expect exactly what is
6074 tested here, and not everything that is function invariant. In
6075 particular, the frame pointer and arg pointer are special cased;
6076 pic_offset_table_rtx is not, and we must not spill these things to
6080 function_invariant_p (const_rtx x
)
6084 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6086 if (GET_CODE (x
) == PLUS
6087 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6088 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6093 /* Determine whether the reload reg X overlaps any rtx'es used for
6094 overriding inheritance. Return nonzero if so. */
6097 conflicts_with_override (rtx x
)
6100 for (i
= 0; i
< n_reloads
; i
++)
6101 if (reload_override_in
[i
]
6102 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6107 /* Give an error message saying we failed to find a reload for INSN,
6108 and clear out reload R. */
6110 failed_reload (rtx_insn
*insn
, int r
)
6112 if (asm_noperands (PATTERN (insn
)) < 0)
6113 /* It's the compiler's fault. */
6114 fatal_insn ("could not find a spill register", insn
);
6116 /* It's the user's fault; the operand's mode and constraint
6117 don't match. Disable this reload so we don't crash in final. */
6118 error_for_asm (insn
,
6119 "%<asm%> operand constraint incompatible with operand size");
6123 rld
[r
].optional
= 1;
6124 rld
[r
].secondary_p
= 1;
6127 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6128 for reload R. If it's valid, get an rtx for it. Return nonzero if
6131 set_reload_reg (int i
, int r
)
6133 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6135 int regno ATTRIBUTE_UNUSED
;
6136 rtx reg
= spill_reg_rtx
[i
];
6138 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6139 spill_reg_rtx
[i
] = reg
6140 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6142 regno
= true_regnum (reg
);
6144 /* Detect when the reload reg can't hold the reload mode.
6145 This used to be one `if', but Sequent compiler can't handle that. */
6146 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6148 machine_mode test_mode
= VOIDmode
;
6150 test_mode
= GET_MODE (rld
[r
].in
);
6151 /* If rld[r].in has VOIDmode, it means we will load it
6152 in whatever mode the reload reg has: to wit, rld[r].mode.
6153 We have already tested that for validity. */
6154 /* Aside from that, we need to test that the expressions
6155 to reload from or into have modes which are valid for this
6156 reload register. Otherwise the reload insns would be invalid. */
6157 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6158 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6159 if (! (rld
[r
].out
!= 0
6160 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6162 /* The reg is OK. */
6165 /* Mark as in use for this insn the reload regs we use
6167 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6168 rld
[r
].when_needed
, rld
[r
].mode
);
6170 rld
[r
].reg_rtx
= reg
;
6171 reload_spill_index
[r
] = spill_regs
[i
];
6178 /* Find a spill register to use as a reload register for reload R.
6179 LAST_RELOAD is nonzero if this is the last reload for the insn being
6182 Set rld[R].reg_rtx to the register allocated.
6184 We return 1 if successful, or 0 if we couldn't find a spill reg and
6185 we didn't change anything. */
6188 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6193 /* If we put this reload ahead, thinking it is a group,
6194 then insist on finding a group. Otherwise we can grab a
6195 reg that some other reload needs.
6196 (That can happen when we have a 68000 DATA_OR_FP_REG
6197 which is a group of data regs or one fp reg.)
6198 We need not be so restrictive if there are no more reloads
6201 ??? Really it would be nicer to have smarter handling
6202 for that kind of reg class, where a problem like this is normal.
6203 Perhaps those classes should be avoided for reloading
6204 by use of more alternatives. */
6206 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6208 /* If we want a single register and haven't yet found one,
6209 take any reg in the right class and not in use.
6210 If we want a consecutive group, here is where we look for it.
6212 We use three passes so we can first look for reload regs to
6213 reuse, which are already in use for other reloads in this insn,
6214 and only then use additional registers which are not "bad", then
6215 finally any register.
6217 I think that maximizing reuse is needed to make sure we don't
6218 run out of reload regs. Suppose we have three reloads, and
6219 reloads A and B can share regs. These need two regs.
6220 Suppose A and B are given different regs.
6221 That leaves none for C. */
6222 for (pass
= 0; pass
< 3; pass
++)
6224 /* I is the index in spill_regs.
6225 We advance it round-robin between insns to use all spill regs
6226 equally, so that inherited reloads have a chance
6227 of leapfrogging each other. */
6231 for (count
= 0; count
< n_spills
; count
++)
6233 int rclass
= (int) rld
[r
].rclass
;
6239 regnum
= spill_regs
[i
];
6241 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6244 /* We check reload_reg_used to make sure we
6245 don't clobber the return register. */
6246 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6247 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6248 rld
[r
].when_needed
, rld
[r
].in
,
6250 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6251 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6252 /* Look first for regs to share, then for unshared. But
6253 don't share regs used for inherited reloads; they are
6254 the ones we want to preserve. */
6256 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6258 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6261 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6263 /* During the second pass we want to avoid reload registers
6264 which are "bad" for this reload. */
6266 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6269 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6270 (on 68000) got us two FP regs. If NR is 1,
6271 we would reject both of them. */
6274 /* If we need only one reg, we have already won. */
6277 /* But reject a single reg if we demand a group. */
6282 /* Otherwise check that as many consecutive regs as we need
6283 are available here. */
6286 int regno
= regnum
+ nr
- 1;
6287 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6288 && spill_reg_order
[regno
] >= 0
6289 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6290 rld
[r
].when_needed
)))
6299 /* If we found something on the current pass, omit later passes. */
6300 if (count
< n_spills
)
6304 /* We should have found a spill register by now. */
6305 if (count
>= n_spills
)
6308 /* I is the index in SPILL_REG_RTX of the reload register we are to
6309 allocate. Get an rtx for it and find its register number. */
6311 return set_reload_reg (i
, r
);
6314 /* Initialize all the tables needed to allocate reload registers.
6315 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6316 is the array we use to restore the reg_rtx field for every reload. */
6319 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6323 for (i
= 0; i
< n_reloads
; i
++)
6324 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6326 memset (reload_inherited
, 0, MAX_RELOADS
);
6327 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6328 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6330 CLEAR_HARD_REG_SET (reload_reg_used
);
6331 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6332 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6333 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6334 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6335 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6337 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6340 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6341 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6342 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6343 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6344 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6345 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6348 for (i
= 0; i
< reload_n_operands
; i
++)
6350 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6351 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6352 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6353 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6354 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6355 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6358 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6360 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6362 for (i
= 0; i
< n_reloads
; i
++)
6363 /* If we have already decided to use a certain register,
6364 don't use it in another way. */
6366 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6367 rld
[i
].when_needed
, rld
[i
].mode
);
6370 #ifdef SECONDARY_MEMORY_NEEDED
6371 /* If X is not a subreg, return it unmodified. If it is a subreg,
6372 look up whether we made a replacement for the SUBREG_REG. Return
6373 either the replacement or the SUBREG_REG. */
6376 replaced_subreg (rtx x
)
6378 if (GET_CODE (x
) == SUBREG
)
6379 return find_replacement (&SUBREG_REG (x
));
6384 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6385 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6386 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6387 otherwise it is NULL. */
6390 compute_reload_subreg_offset (machine_mode outermode
,
6392 machine_mode innermode
)
6395 machine_mode middlemode
;
6398 return subreg_lowpart_offset (outermode
, innermode
);
6400 outer_offset
= SUBREG_BYTE (subreg
);
6401 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6403 /* If SUBREG is paradoxical then return the normal lowpart offset
6404 for OUTERMODE and INNERMODE. Our caller has already checked
6405 that OUTERMODE fits in INNERMODE. */
6406 if (outer_offset
== 0
6407 && GET_MODE_SIZE (outermode
) > GET_MODE_SIZE (middlemode
))
6408 return subreg_lowpart_offset (outermode
, innermode
);
6410 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6411 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6412 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6415 /* Assign hard reg targets for the pseudo-registers we must reload
6416 into hard regs for this insn.
6417 Also output the instructions to copy them in and out of the hard regs.
6419 For machines with register classes, we are responsible for
6420 finding a reload reg in the proper class. */
6423 choose_reload_regs (struct insn_chain
*chain
)
6425 rtx_insn
*insn
= chain
->insn
;
6427 unsigned int max_group_size
= 1;
6428 enum reg_class group_class
= NO_REGS
;
6429 int pass
, win
, inheritance
;
6431 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6433 /* In order to be certain of getting the registers we need,
6434 we must sort the reloads into order of increasing register class.
6435 Then our grabbing of reload registers will parallel the process
6436 that provided the reload registers.
6438 Also note whether any of the reloads wants a consecutive group of regs.
6439 If so, record the maximum size of the group desired and what
6440 register class contains all the groups needed by this insn. */
6442 for (j
= 0; j
< n_reloads
; j
++)
6444 reload_order
[j
] = j
;
6445 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6447 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6448 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6449 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6452 reload_spill_index
[j
] = -1;
6454 if (rld
[j
].nregs
> 1)
6456 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6458 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6461 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6465 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6467 /* If -O, try first with inheritance, then turning it off.
6468 If not -O, don't do inheritance.
6469 Using inheritance when not optimizing leads to paradoxes
6470 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6471 because one side of the comparison might be inherited. */
6473 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6475 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6477 /* Process the reloads in order of preference just found.
6478 Beyond this point, subregs can be found in reload_reg_rtx.
6480 This used to look for an existing reloaded home for all of the
6481 reloads, and only then perform any new reloads. But that could lose
6482 if the reloads were done out of reg-class order because a later
6483 reload with a looser constraint might have an old home in a register
6484 needed by an earlier reload with a tighter constraint.
6486 To solve this, we make two passes over the reloads, in the order
6487 described above. In the first pass we try to inherit a reload
6488 from a previous insn. If there is a later reload that needs a
6489 class that is a proper subset of the class being processed, we must
6490 also allocate a spill register during the first pass.
6492 Then make a second pass over the reloads to allocate any reloads
6493 that haven't been given registers yet. */
6495 for (j
= 0; j
< n_reloads
; j
++)
6497 int r
= reload_order
[j
];
6498 rtx search_equiv
= NULL_RTX
;
6500 /* Ignore reloads that got marked inoperative. */
6501 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6502 && ! rld
[r
].secondary_p
)
6505 /* If find_reloads chose to use reload_in or reload_out as a reload
6506 register, we don't need to chose one. Otherwise, try even if it
6507 found one since we might save an insn if we find the value lying
6509 Try also when reload_in is a pseudo without a hard reg. */
6510 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6511 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6512 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6513 && !MEM_P (rld
[r
].in
)
6514 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6517 #if 0 /* No longer needed for correct operation.
6518 It might give better code, or might not; worth an experiment? */
6519 /* If this is an optional reload, we can't inherit from earlier insns
6520 until we are sure that any non-optional reloads have been allocated.
6521 The following code takes advantage of the fact that optional reloads
6522 are at the end of reload_order. */
6523 if (rld
[r
].optional
!= 0)
6524 for (i
= 0; i
< j
; i
++)
6525 if ((rld
[reload_order
[i
]].out
!= 0
6526 || rld
[reload_order
[i
]].in
!= 0
6527 || rld
[reload_order
[i
]].secondary_p
)
6528 && ! rld
[reload_order
[i
]].optional
6529 && rld
[reload_order
[i
]].reg_rtx
== 0)
6530 allocate_reload_reg (chain
, reload_order
[i
], 0);
6533 /* First see if this pseudo is already available as reloaded
6534 for a previous insn. We cannot try to inherit for reloads
6535 that are smaller than the maximum number of registers needed
6536 for groups unless the register we would allocate cannot be used
6539 We could check here to see if this is a secondary reload for
6540 an object that is already in a register of the desired class.
6541 This would avoid the need for the secondary reload register.
6542 But this is complex because we can't easily determine what
6543 objects might want to be loaded via this reload. So let a
6544 register be allocated here. In `emit_reload_insns' we suppress
6545 one of the loads in the case described above. */
6551 machine_mode mode
= VOIDmode
;
6552 rtx subreg
= NULL_RTX
;
6556 else if (REG_P (rld
[r
].in
))
6558 regno
= REGNO (rld
[r
].in
);
6559 mode
= GET_MODE (rld
[r
].in
);
6561 else if (REG_P (rld
[r
].in_reg
))
6563 regno
= REGNO (rld
[r
].in_reg
);
6564 mode
= GET_MODE (rld
[r
].in_reg
);
6566 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6567 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6569 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6570 if (regno
< FIRST_PSEUDO_REGISTER
)
6571 regno
= subreg_regno (rld
[r
].in_reg
);
6574 subreg
= rld
[r
].in_reg
;
6575 byte
= SUBREG_BYTE (subreg
);
6577 mode
= GET_MODE (rld
[r
].in_reg
);
6580 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6581 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6583 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6584 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6585 rld
[r
].out
= rld
[r
].in
;
6589 /* This won't work, since REGNO can be a pseudo reg number.
6590 Also, it takes much more hair to keep track of all the things
6591 that can invalidate an inherited reload of part of a pseudoreg. */
6592 else if (GET_CODE (rld
[r
].in
) == SUBREG
6593 && REG_P (SUBREG_REG (rld
[r
].in
)))
6594 regno
= subreg_regno (rld
[r
].in
);
6598 && reg_last_reload_reg
[regno
] != 0
6599 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6600 >= GET_MODE_SIZE (mode
) + byte
)
6601 #ifdef CANNOT_CHANGE_MODE_CLASS
6602 /* Verify that the register it's in can be used in
6604 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6605 GET_MODE (reg_last_reload_reg
[regno
]),
6610 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6611 rtx last_reg
= reg_last_reload_reg
[regno
];
6613 i
= REGNO (last_reg
);
6614 byte
= compute_reload_subreg_offset (mode
,
6616 GET_MODE (last_reg
));
6617 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6618 last_class
= REGNO_REG_CLASS (i
);
6620 if (reg_reloaded_contents
[i
] == regno
6621 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6622 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6623 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6624 /* Even if we can't use this register as a reload
6625 register, we might use it for reload_override_in,
6626 if copying it to the desired class is cheap
6628 || ((register_move_cost (mode
, last_class
, rclass
)
6629 < memory_move_cost (mode
, rclass
, true))
6630 && (secondary_reload_class (1, rclass
, mode
,
6633 #ifdef SECONDARY_MEMORY_NEEDED
6634 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6639 && (rld
[r
].nregs
== max_group_size
6640 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6642 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6643 rld
[r
].when_needed
, rld
[r
].in
,
6646 /* If a group is needed, verify that all the subsequent
6647 registers still have their values intact. */
6648 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6651 for (k
= 1; k
< nr
; k
++)
6652 if (reg_reloaded_contents
[i
+ k
] != regno
6653 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6661 last_reg
= (GET_MODE (last_reg
) == mode
6662 ? last_reg
: gen_rtx_REG (mode
, i
));
6665 for (k
= 0; k
< nr
; k
++)
6666 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6669 /* We found a register that contains the
6670 value we need. If this register is the
6671 same as an `earlyclobber' operand of the
6672 current insn, just mark it as a place to
6673 reload from since we can't use it as the
6674 reload register itself. */
6676 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6677 if (reg_overlap_mentioned_for_reload_p
6678 (reg_last_reload_reg
[regno
],
6679 reload_earlyclobbers
[i1
]))
6682 if (i1
!= n_earlyclobbers
6683 || ! (free_for_value_p (i
, rld
[r
].mode
,
6685 rld
[r
].when_needed
, rld
[r
].in
,
6687 /* Don't use it if we'd clobber a pseudo reg. */
6688 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6690 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6691 /* Don't clobber the frame pointer. */
6692 || (i
== HARD_FRAME_POINTER_REGNUM
6693 && frame_pointer_needed
6695 /* Don't really use the inherited spill reg
6696 if we need it wider than we've got it. */
6697 || (GET_MODE_SIZE (rld
[r
].mode
)
6698 > GET_MODE_SIZE (mode
))
6701 /* If find_reloads chose reload_out as reload
6702 register, stay with it - that leaves the
6703 inherited register for subsequent reloads. */
6704 || (rld
[r
].out
&& rld
[r
].reg_rtx
6705 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6707 if (! rld
[r
].optional
)
6709 reload_override_in
[r
] = last_reg
;
6710 reload_inheritance_insn
[r
]
6711 = reg_reloaded_insn
[i
];
6717 /* We can use this as a reload reg. */
6718 /* Mark the register as in use for this part of
6720 mark_reload_reg_in_use (i
,
6724 rld
[r
].reg_rtx
= last_reg
;
6725 reload_inherited
[r
] = 1;
6726 reload_inheritance_insn
[r
]
6727 = reg_reloaded_insn
[i
];
6728 reload_spill_index
[r
] = i
;
6729 for (k
= 0; k
< nr
; k
++)
6730 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6738 /* Here's another way to see if the value is already lying around. */
6741 && ! reload_inherited
[r
]
6743 && (CONSTANT_P (rld
[r
].in
)
6744 || GET_CODE (rld
[r
].in
) == PLUS
6745 || REG_P (rld
[r
].in
)
6746 || MEM_P (rld
[r
].in
))
6747 && (rld
[r
].nregs
== max_group_size
6748 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6749 search_equiv
= rld
[r
].in
;
6754 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6755 -1, NULL
, 0, rld
[r
].mode
);
6761 regno
= REGNO (equiv
);
6764 /* This must be a SUBREG of a hard register.
6765 Make a new REG since this might be used in an
6766 address and not all machines support SUBREGs
6768 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6769 regno
= subreg_regno (equiv
);
6770 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6771 /* If we choose EQUIV as the reload register, but the
6772 loop below decides to cancel the inheritance, we'll
6773 end up reloading EQUIV in rld[r].mode, not the mode
6774 it had originally. That isn't safe when EQUIV isn't
6775 available as a spill register since its value might
6776 still be live at this point. */
6777 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6778 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6783 /* If we found a spill reg, reject it unless it is free
6784 and of the desired class. */
6788 int bad_for_class
= 0;
6789 int max_regno
= regno
+ rld
[r
].nregs
;
6791 for (i
= regno
; i
< max_regno
; i
++)
6793 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6795 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6800 && ! free_for_value_p (regno
, rld
[r
].mode
,
6801 rld
[r
].opnum
, rld
[r
].when_needed
,
6802 rld
[r
].in
, rld
[r
].out
, r
, 1))
6807 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6810 /* We found a register that contains the value we need.
6811 If this register is the same as an `earlyclobber' operand
6812 of the current insn, just mark it as a place to reload from
6813 since we can't use it as the reload register itself. */
6816 for (i
= 0; i
< n_earlyclobbers
; i
++)
6817 if (reg_overlap_mentioned_for_reload_p (equiv
,
6818 reload_earlyclobbers
[i
]))
6820 if (! rld
[r
].optional
)
6821 reload_override_in
[r
] = equiv
;
6826 /* If the equiv register we have found is explicitly clobbered
6827 in the current insn, it depends on the reload type if we
6828 can use it, use it for reload_override_in, or not at all.
6829 In particular, we then can't use EQUIV for a
6830 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6834 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6835 switch (rld
[r
].when_needed
)
6837 case RELOAD_FOR_OTHER_ADDRESS
:
6838 case RELOAD_FOR_INPADDR_ADDRESS
:
6839 case RELOAD_FOR_INPUT_ADDRESS
:
6840 case RELOAD_FOR_OPADDR_ADDR
:
6843 case RELOAD_FOR_INPUT
:
6844 case RELOAD_FOR_OPERAND_ADDRESS
:
6845 if (! rld
[r
].optional
)
6846 reload_override_in
[r
] = equiv
;
6852 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6853 switch (rld
[r
].when_needed
)
6855 case RELOAD_FOR_OTHER_ADDRESS
:
6856 case RELOAD_FOR_INPADDR_ADDRESS
:
6857 case RELOAD_FOR_INPUT_ADDRESS
:
6858 case RELOAD_FOR_OPADDR_ADDR
:
6859 case RELOAD_FOR_OPERAND_ADDRESS
:
6860 case RELOAD_FOR_INPUT
:
6863 if (! rld
[r
].optional
)
6864 reload_override_in
[r
] = equiv
;
6872 /* If we found an equivalent reg, say no code need be generated
6873 to load it, and use it as our reload reg. */
6875 && (regno
!= HARD_FRAME_POINTER_REGNUM
6876 || !frame_pointer_needed
))
6878 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6880 rld
[r
].reg_rtx
= equiv
;
6881 reload_spill_index
[r
] = regno
;
6882 reload_inherited
[r
] = 1;
6884 /* If reg_reloaded_valid is not set for this register,
6885 there might be a stale spill_reg_store lying around.
6886 We must clear it, since otherwise emit_reload_insns
6887 might delete the store. */
6888 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6889 spill_reg_store
[regno
] = NULL
;
6890 /* If any of the hard registers in EQUIV are spill
6891 registers, mark them as in use for this insn. */
6892 for (k
= 0; k
< nr
; k
++)
6894 i
= spill_reg_order
[regno
+ k
];
6897 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6900 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6907 /* If we found a register to use already, or if this is an optional
6908 reload, we are done. */
6909 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6913 /* No longer needed for correct operation. Might or might
6914 not give better code on the average. Want to experiment? */
6916 /* See if there is a later reload that has a class different from our
6917 class that intersects our class or that requires less register
6918 than our reload. If so, we must allocate a register to this
6919 reload now, since that reload might inherit a previous reload
6920 and take the only available register in our class. Don't do this
6921 for optional reloads since they will force all previous reloads
6922 to be allocated. Also don't do this for reloads that have been
6925 for (i
= j
+ 1; i
< n_reloads
; i
++)
6927 int s
= reload_order
[i
];
6929 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6930 && ! rld
[s
].secondary_p
)
6934 if ((rld
[s
].rclass
!= rld
[r
].rclass
6935 && reg_classes_intersect_p (rld
[r
].rclass
,
6937 || rld
[s
].nregs
< rld
[r
].nregs
)
6944 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6948 /* Now allocate reload registers for anything non-optional that
6949 didn't get one yet. */
6950 for (j
= 0; j
< n_reloads
; j
++)
6952 int r
= reload_order
[j
];
6954 /* Ignore reloads that got marked inoperative. */
6955 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6958 /* Skip reloads that already have a register allocated or are
6960 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6963 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6967 /* If that loop got all the way, we have won. */
6974 /* Loop around and try without any inheritance. */
6979 /* First undo everything done by the failed attempt
6980 to allocate with inheritance. */
6981 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6983 /* Some sanity tests to verify that the reloads found in the first
6984 pass are identical to the ones we have now. */
6985 gcc_assert (chain
->n_reloads
== n_reloads
);
6987 for (i
= 0; i
< n_reloads
; i
++)
6989 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6991 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6992 for (j
= 0; j
< n_spills
; j
++)
6993 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6994 if (! set_reload_reg (j
, i
))
6995 failed_reload (chain
->insn
, i
);
6999 /* If we thought we could inherit a reload, because it seemed that
7000 nothing else wanted the same reload register earlier in the insn,
7001 verify that assumption, now that all reloads have been assigned.
7002 Likewise for reloads where reload_override_in has been set. */
7004 /* If doing expensive optimizations, do one preliminary pass that doesn't
7005 cancel any inheritance, but removes reloads that have been needed only
7006 for reloads that we know can be inherited. */
7007 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
7009 for (j
= 0; j
< n_reloads
; j
++)
7011 int r
= reload_order
[j
];
7013 #ifdef SECONDARY_MEMORY_NEEDED
7016 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
7017 check_reg
= rld
[r
].reg_rtx
;
7018 else if (reload_override_in
[r
]
7019 && (REG_P (reload_override_in
[r
])
7020 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
7021 check_reg
= reload_override_in
[r
];
7024 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
7025 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
7026 (reload_inherited
[r
]
7027 ? rld
[r
].out
: const0_rtx
),
7032 reload_inherited
[r
] = 0;
7033 reload_override_in
[r
] = 0;
7035 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7036 reload_override_in, then we do not need its related
7037 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7038 likewise for other reload types.
7039 We handle this by removing a reload when its only replacement
7040 is mentioned in reload_in of the reload we are going to inherit.
7041 A special case are auto_inc expressions; even if the input is
7042 inherited, we still need the address for the output. We can
7043 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7044 If we succeeded removing some reload and we are doing a preliminary
7045 pass just to remove such reloads, make another pass, since the
7046 removal of one reload might allow us to inherit another one. */
7048 && rld
[r
].out
!= rld
[r
].in
7049 && remove_address_replacements (rld
[r
].in
))
7054 #ifdef SECONDARY_MEMORY_NEEDED
7055 /* If we needed a memory location for the reload, we also have to
7056 remove its related reloads. */
7058 && rld
[r
].out
!= rld
[r
].in
7059 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7060 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7061 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7062 rld
[r
].rclass
, rld
[r
].inmode
)
7063 && remove_address_replacements
7064 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7065 rld
[r
].when_needed
)))
7074 /* Now that reload_override_in is known valid,
7075 actually override reload_in. */
7076 for (j
= 0; j
< n_reloads
; j
++)
7077 if (reload_override_in
[j
])
7078 rld
[j
].in
= reload_override_in
[j
];
7080 /* If this reload won't be done because it has been canceled or is
7081 optional and not inherited, clear reload_reg_rtx so other
7082 routines (such as subst_reloads) don't get confused. */
7083 for (j
= 0; j
< n_reloads
; j
++)
7084 if (rld
[j
].reg_rtx
!= 0
7085 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7086 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7087 && ! rld
[j
].secondary_p
)))
7089 int regno
= true_regnum (rld
[j
].reg_rtx
);
7091 if (spill_reg_order
[regno
] >= 0)
7092 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7093 rld
[j
].when_needed
, rld
[j
].mode
);
7095 reload_spill_index
[j
] = -1;
7098 /* Record which pseudos and which spill regs have output reloads. */
7099 for (j
= 0; j
< n_reloads
; j
++)
7101 int r
= reload_order
[j
];
7103 i
= reload_spill_index
[r
];
7105 /* I is nonneg if this reload uses a register.
7106 If rld[r].reg_rtx is 0, this is an optional reload
7107 that we opted to ignore. */
7108 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7109 && rld
[r
].reg_rtx
!= 0)
7111 int nregno
= REGNO (rld
[r
].out_reg
);
7114 if (nregno
< FIRST_PSEUDO_REGISTER
)
7115 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7118 SET_REGNO_REG_SET (®_has_output_reload
,
7122 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7124 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7125 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7126 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7131 /* Deallocate the reload register for reload R. This is called from
7132 remove_address_replacements. */
7135 deallocate_reload_reg (int r
)
7139 if (! rld
[r
].reg_rtx
)
7141 regno
= true_regnum (rld
[r
].reg_rtx
);
7143 if (spill_reg_order
[regno
] >= 0)
7144 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7146 reload_spill_index
[r
] = -1;
7149 /* These arrays are filled by emit_reload_insns and its subroutines. */
7150 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7151 static rtx_insn
*other_input_address_reload_insns
= 0;
7152 static rtx_insn
*other_input_reload_insns
= 0;
7153 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7154 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7155 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7156 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7157 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7158 static rtx_insn
*operand_reload_insns
= 0;
7159 static rtx_insn
*other_operand_reload_insns
= 0;
7160 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7162 /* Values to be put in spill_reg_store are put here first. Instructions
7163 must only be placed here if the associated reload register reaches
7164 the end of the instruction's reload sequence. */
7165 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7166 static HARD_REG_SET reg_reloaded_died
;
7168 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7169 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7170 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7171 adjusted register, and return true. Otherwise, return false. */
7173 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7174 enum reg_class new_class
,
7175 machine_mode new_mode
)
7180 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7182 unsigned regno
= REGNO (reg
);
7184 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7186 if (GET_MODE (reg
) != new_mode
)
7188 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7190 if (hard_regno_nregs
[regno
][new_mode
]
7191 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7193 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7201 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7202 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7203 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7204 adjusted register, and return true. Otherwise, return false. */
7206 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7207 enum insn_code icode
)
7210 enum reg_class new_class
= scratch_reload_class (icode
);
7211 machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7213 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7214 new_class
, new_mode
);
7217 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7218 has the number J. OLD contains the value to be used as input. */
7221 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7224 rtx_insn
*insn
= chain
->insn
;
7226 rtx oldequiv_reg
= 0;
7232 /* delete_output_reload is only invoked properly if old contains
7233 the original pseudo register. Since this is replaced with a
7234 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7235 find the pseudo in RELOAD_IN_REG. This is also used to
7236 determine whether a secondary reload is needed. */
7237 if (reload_override_in
[j
]
7238 && (REG_P (rl
->in_reg
)
7239 || (GET_CODE (rl
->in_reg
) == SUBREG
7240 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7247 else if (REG_P (oldequiv
))
7248 oldequiv_reg
= oldequiv
;
7249 else if (GET_CODE (oldequiv
) == SUBREG
)
7250 oldequiv_reg
= SUBREG_REG (oldequiv
);
7252 reloadreg
= reload_reg_rtx_for_input
[j
];
7253 mode
= GET_MODE (reloadreg
);
7255 /* If we are reloading from a register that was recently stored in
7256 with an output-reload, see if we can prove there was
7257 actually no need to store the old value in it. */
7259 if (optimize
&& REG_P (oldequiv
)
7260 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7261 && spill_reg_store
[REGNO (oldequiv
)]
7263 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7264 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7266 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7268 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7271 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7272 oldequiv
= SUBREG_REG (oldequiv
);
7273 if (GET_MODE (oldequiv
) != VOIDmode
7274 && mode
!= GET_MODE (oldequiv
))
7275 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7277 /* Switch to the right place to emit the reload insns. */
7278 switch (rl
->when_needed
)
7281 where
= &other_input_reload_insns
;
7283 case RELOAD_FOR_INPUT
:
7284 where
= &input_reload_insns
[rl
->opnum
];
7286 case RELOAD_FOR_INPUT_ADDRESS
:
7287 where
= &input_address_reload_insns
[rl
->opnum
];
7289 case RELOAD_FOR_INPADDR_ADDRESS
:
7290 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7292 case RELOAD_FOR_OUTPUT_ADDRESS
:
7293 where
= &output_address_reload_insns
[rl
->opnum
];
7295 case RELOAD_FOR_OUTADDR_ADDRESS
:
7296 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7298 case RELOAD_FOR_OPERAND_ADDRESS
:
7299 where
= &operand_reload_insns
;
7301 case RELOAD_FOR_OPADDR_ADDR
:
7302 where
= &other_operand_reload_insns
;
7304 case RELOAD_FOR_OTHER_ADDRESS
:
7305 where
= &other_input_address_reload_insns
;
7311 push_to_sequence (*where
);
7313 /* Auto-increment addresses must be reloaded in a special way. */
7314 if (rl
->out
&& ! rl
->out_reg
)
7316 /* We are not going to bother supporting the case where a
7317 incremented register can't be copied directly from
7318 OLDEQUIV since this seems highly unlikely. */
7319 gcc_assert (rl
->secondary_in_reload
< 0);
7321 if (reload_inherited
[j
])
7322 oldequiv
= reloadreg
;
7324 old
= XEXP (rl
->in_reg
, 0);
7326 /* Prevent normal processing of this reload. */
7328 /* Output a special code sequence for this case. */
7329 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7332 /* If we are reloading a pseudo-register that was set by the previous
7333 insn, see if we can get rid of that pseudo-register entirely
7334 by redirecting the previous insn into our reload register. */
7336 else if (optimize
&& REG_P (old
)
7337 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7338 && dead_or_set_p (insn
, old
)
7339 /* This is unsafe if some other reload
7340 uses the same reg first. */
7341 && ! conflicts_with_override (reloadreg
)
7342 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7343 rl
->when_needed
, old
, rl
->out
, j
, 0))
7345 rtx_insn
*temp
= PREV_INSN (insn
);
7346 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7347 temp
= PREV_INSN (temp
);
7349 && NONJUMP_INSN_P (temp
)
7350 && GET_CODE (PATTERN (temp
)) == SET
7351 && SET_DEST (PATTERN (temp
)) == old
7352 /* Make sure we can access insn_operand_constraint. */
7353 && asm_noperands (PATTERN (temp
)) < 0
7354 /* This is unsafe if operand occurs more than once in current
7355 insn. Perhaps some occurrences aren't reloaded. */
7356 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7358 rtx old
= SET_DEST (PATTERN (temp
));
7359 /* Store into the reload register instead of the pseudo. */
7360 SET_DEST (PATTERN (temp
)) = reloadreg
;
7362 /* Verify that resulting insn is valid.
7364 Note that we have replaced the destination of TEMP with
7365 RELOADREG. If TEMP references RELOADREG within an
7366 autoincrement addressing mode, then the resulting insn
7367 is ill-formed and we must reject this optimization. */
7368 extract_insn (temp
);
7369 if (constrain_operands (1, get_enabled_alternatives (temp
))
7370 && (!AUTO_INC_DEC
|| ! find_reg_note (temp
, REG_INC
, reloadreg
)))
7372 /* If the previous insn is an output reload, the source is
7373 a reload register, and its spill_reg_store entry will
7374 contain the previous destination. This is now
7376 if (REG_P (SET_SRC (PATTERN (temp
)))
7377 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7379 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7380 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7383 /* If these are the only uses of the pseudo reg,
7384 pretend for GDB it lives in the reload reg we used. */
7385 if (REG_N_DEATHS (REGNO (old
)) == 1
7386 && REG_N_SETS (REGNO (old
)) == 1)
7388 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7389 if (ira_conflicts_p
)
7390 /* Inform IRA about the change. */
7391 ira_mark_allocation_change (REGNO (old
));
7392 alter_reg (REGNO (old
), -1, false);
7396 /* Adjust any debug insns between temp and insn. */
7397 while ((temp
= NEXT_INSN (temp
)) != insn
)
7398 if (DEBUG_INSN_P (temp
))
7399 INSN_VAR_LOCATION_LOC (temp
)
7400 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp
),
7403 gcc_assert (NOTE_P (temp
));
7407 SET_DEST (PATTERN (temp
)) = old
;
7412 /* We can't do that, so output an insn to load RELOADREG. */
7414 /* If we have a secondary reload, pick up the secondary register
7415 and icode, if any. If OLDEQUIV and OLD are different or
7416 if this is an in-out reload, recompute whether or not we
7417 still need a secondary register and what the icode should
7418 be. If we still need a secondary register and the class or
7419 icode is different, go back to reloading from OLD if using
7420 OLDEQUIV means that we got the wrong type of register. We
7421 cannot have different class or icode due to an in-out reload
7422 because we don't make such reloads when both the input and
7423 output need secondary reload registers. */
7425 if (! special
&& rl
->secondary_in_reload
>= 0)
7427 rtx second_reload_reg
= 0;
7428 rtx third_reload_reg
= 0;
7429 int secondary_reload
= rl
->secondary_in_reload
;
7430 rtx real_oldequiv
= oldequiv
;
7433 enum insn_code icode
;
7434 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7436 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7437 and similarly for OLD.
7438 See comments in get_secondary_reload in reload.c. */
7439 /* If it is a pseudo that cannot be replaced with its
7440 equivalent MEM, we must fall back to reload_in, which
7441 will have all the necessary substitutions registered.
7442 Likewise for a pseudo that can't be replaced with its
7443 equivalent constant.
7445 Take extra care for subregs of such pseudos. Note that
7446 we cannot use reg_equiv_mem in this case because it is
7447 not in the right mode. */
7450 if (GET_CODE (tmp
) == SUBREG
)
7451 tmp
= SUBREG_REG (tmp
);
7453 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7454 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7455 || reg_equiv_constant (REGNO (tmp
)) != 0))
7457 if (! reg_equiv_mem (REGNO (tmp
))
7458 || num_not_at_initial_offset
7459 || GET_CODE (oldequiv
) == SUBREG
)
7460 real_oldequiv
= rl
->in
;
7462 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7466 if (GET_CODE (tmp
) == SUBREG
)
7467 tmp
= SUBREG_REG (tmp
);
7469 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7470 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7471 || reg_equiv_constant (REGNO (tmp
)) != 0))
7473 if (! reg_equiv_mem (REGNO (tmp
))
7474 || num_not_at_initial_offset
7475 || GET_CODE (old
) == SUBREG
)
7478 real_old
= reg_equiv_mem (REGNO (tmp
));
7481 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7482 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7484 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7486 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7487 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7488 /* We'd have to add more code for quartary reloads. */
7489 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7491 icode
= rl
->secondary_in_icode
;
7493 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7494 || (rl
->in
!= 0 && rl
->out
!= 0))
7496 secondary_reload_info sri
, sri2
;
7497 enum reg_class new_class
, new_t_class
;
7499 sri
.icode
= CODE_FOR_nothing
;
7500 sri
.prev_sri
= NULL
;
7502 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7506 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7507 second_reload_reg
= 0;
7508 else if (new_class
== NO_REGS
)
7510 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7512 (enum insn_code
) sri
.icode
))
7514 icode
= (enum insn_code
) sri
.icode
;
7515 third_reload_reg
= 0;
7520 real_oldequiv
= real_old
;
7523 else if (sri
.icode
!= CODE_FOR_nothing
)
7524 /* We currently lack a way to express this in reloads. */
7528 sri2
.icode
= CODE_FOR_nothing
;
7529 sri2
.prev_sri
= &sri
;
7531 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7534 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7536 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7540 third_reload_reg
= 0;
7541 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7546 real_oldequiv
= real_old
;
7549 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7551 rtx intermediate
= second_reload_reg
;
7553 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7555 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7559 second_reload_reg
= intermediate
;
7560 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7565 real_oldequiv
= real_old
;
7568 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7570 rtx intermediate
= second_reload_reg
;
7572 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7574 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7577 second_reload_reg
= intermediate
;
7578 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7583 real_oldequiv
= real_old
;
7588 /* This could be handled more intelligently too. */
7590 real_oldequiv
= real_old
;
7595 /* If we still need a secondary reload register, check
7596 to see if it is being used as a scratch or intermediate
7597 register and generate code appropriately. If we need
7598 a scratch register, use REAL_OLDEQUIV since the form of
7599 the insn may depend on the actual address if it is
7602 if (second_reload_reg
)
7604 if (icode
!= CODE_FOR_nothing
)
7606 /* We'd have to add extra code to handle this case. */
7607 gcc_assert (!third_reload_reg
);
7609 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7610 second_reload_reg
));
7615 /* See if we need a scratch register to load the
7616 intermediate register (a tertiary reload). */
7617 if (tertiary_icode
!= CODE_FOR_nothing
)
7619 emit_insn ((GEN_FCN (tertiary_icode
)
7620 (second_reload_reg
, real_oldequiv
,
7621 third_reload_reg
)));
7623 else if (third_reload_reg
)
7625 gen_reload (third_reload_reg
, real_oldequiv
,
7628 gen_reload (second_reload_reg
, third_reload_reg
,
7633 gen_reload (second_reload_reg
, real_oldequiv
,
7637 oldequiv
= second_reload_reg
;
7642 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7644 rtx real_oldequiv
= oldequiv
;
7646 if ((REG_P (oldequiv
)
7647 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7648 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7649 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7650 || (GET_CODE (oldequiv
) == SUBREG
7651 && REG_P (SUBREG_REG (oldequiv
))
7652 && (REGNO (SUBREG_REG (oldequiv
))
7653 >= FIRST_PSEUDO_REGISTER
)
7654 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7655 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7656 || (CONSTANT_P (oldequiv
)
7657 && (targetm
.preferred_reload_class (oldequiv
,
7658 REGNO_REG_CLASS (REGNO (reloadreg
)))
7660 real_oldequiv
= rl
->in
;
7661 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7665 if (cfun
->can_throw_non_call_exceptions
)
7666 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7668 /* End this sequence. */
7669 *where
= get_insns ();
7672 /* Update reload_override_in so that delete_address_reloads_1
7673 can see the actual register usage. */
7675 reload_override_in
[j
] = oldequiv
;
7678 /* Generate insns to for the output reload RL, which is for the insn described
7679 by CHAIN and has the number J. */
7681 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7685 rtx_insn
*insn
= chain
->insn
;
7692 if (rl
->when_needed
== RELOAD_OTHER
)
7695 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7697 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7698 mode
= GET_MODE (rl_reg_rtx
);
7700 reloadreg
= rl_reg_rtx
;
7702 /* If we need two reload regs, set RELOADREG to the intermediate
7703 one, since it will be stored into OLD. We might need a secondary
7704 register only for an input reload, so check again here. */
7706 if (rl
->secondary_out_reload
>= 0)
7709 int secondary_reload
= rl
->secondary_out_reload
;
7710 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7712 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7713 && reg_equiv_mem (REGNO (old
)) != 0)
7714 real_old
= reg_equiv_mem (REGNO (old
));
7716 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7718 rtx second_reloadreg
= reloadreg
;
7719 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7721 /* See if RELOADREG is to be used as a scratch register
7722 or as an intermediate register. */
7723 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7725 /* We'd have to add extra code to handle this case. */
7726 gcc_assert (tertiary_reload
< 0);
7728 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7729 (real_old
, second_reloadreg
, reloadreg
)));
7734 /* See if we need both a scratch and intermediate reload
7737 enum insn_code tertiary_icode
7738 = rld
[secondary_reload
].secondary_out_icode
;
7740 /* We'd have to add more code for quartary reloads. */
7741 gcc_assert (tertiary_reload
< 0
7742 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7744 if (GET_MODE (reloadreg
) != mode
)
7745 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7747 if (tertiary_icode
!= CODE_FOR_nothing
)
7749 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7751 /* Copy primary reload reg to secondary reload reg.
7752 (Note that these have been swapped above, then
7753 secondary reload reg to OLD using our insn.) */
7755 /* If REAL_OLD is a paradoxical SUBREG, remove it
7756 and try to put the opposite SUBREG on
7758 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7760 gen_reload (reloadreg
, second_reloadreg
,
7761 rl
->opnum
, rl
->when_needed
);
7762 emit_insn ((GEN_FCN (tertiary_icode
)
7763 (real_old
, reloadreg
, third_reloadreg
)));
7769 /* Copy between the reload regs here and then to
7772 gen_reload (reloadreg
, second_reloadreg
,
7773 rl
->opnum
, rl
->when_needed
);
7774 if (tertiary_reload
>= 0)
7776 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7778 gen_reload (third_reloadreg
, reloadreg
,
7779 rl
->opnum
, rl
->when_needed
);
7780 reloadreg
= third_reloadreg
;
7787 /* Output the last reload insn. */
7792 /* Don't output the last reload if OLD is not the dest of
7793 INSN and is in the src and is clobbered by INSN. */
7794 if (! flag_expensive_optimizations
7796 || !(set
= single_set (insn
))
7797 || rtx_equal_p (old
, SET_DEST (set
))
7798 || !reg_mentioned_p (old
, SET_SRC (set
))
7799 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7800 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7801 gen_reload (old
, reloadreg
, rl
->opnum
,
7805 /* Look at all insns we emitted, just to be safe. */
7806 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7809 rtx pat
= PATTERN (p
);
7811 /* If this output reload doesn't come from a spill reg,
7812 clear any memory of reloaded copies of the pseudo reg.
7813 If this output reload comes from a spill reg,
7814 reg_has_output_reload will make this do nothing. */
7815 note_stores (pat
, forget_old_reloads_1
, NULL
);
7817 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7819 rtx set
= single_set (insn
);
7820 if (reload_spill_index
[j
] < 0
7822 && SET_SRC (set
) == rl_reg_rtx
)
7824 int src
= REGNO (SET_SRC (set
));
7826 reload_spill_index
[j
] = src
;
7827 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7828 if (find_regno_note (insn
, REG_DEAD
, src
))
7829 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7831 if (HARD_REGISTER_P (rl_reg_rtx
))
7833 int s
= rl
->secondary_out_reload
;
7834 set
= single_set (p
);
7835 /* If this reload copies only to the secondary reload
7836 register, the secondary reload does the actual
7838 if (s
>= 0 && set
== NULL_RTX
)
7839 /* We can't tell what function the secondary reload
7840 has and where the actual store to the pseudo is
7841 made; leave new_spill_reg_store alone. */
7844 && SET_SRC (set
) == rl_reg_rtx
7845 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7847 /* Usually the next instruction will be the
7848 secondary reload insn; if we can confirm
7849 that it is, setting new_spill_reg_store to
7850 that insn will allow an extra optimization. */
7851 rtx s_reg
= rld
[s
].reg_rtx
;
7852 rtx_insn
*next
= NEXT_INSN (p
);
7853 rld
[s
].out
= rl
->out
;
7854 rld
[s
].out_reg
= rl
->out_reg
;
7855 set
= single_set (next
);
7856 if (set
&& SET_SRC (set
) == s_reg
7857 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7859 SET_HARD_REG_BIT (reg_is_output_reload
,
7861 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7864 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7865 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7870 if (rl
->when_needed
== RELOAD_OTHER
)
7872 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7873 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7876 output_reload_insns
[rl
->opnum
] = get_insns ();
7878 if (cfun
->can_throw_non_call_exceptions
)
7879 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7884 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7885 and has the number J. */
7887 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7889 rtx_insn
*insn
= chain
->insn
;
7890 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7891 ? rl
->in_reg
: rl
->in
);
7892 rtx reg_rtx
= rl
->reg_rtx
;
7898 /* Determine the mode to reload in.
7899 This is very tricky because we have three to choose from.
7900 There is the mode the insn operand wants (rl->inmode).
7901 There is the mode of the reload register RELOADREG.
7902 There is the intrinsic mode of the operand, which we could find
7903 by stripping some SUBREGs.
7904 It turns out that RELOADREG's mode is irrelevant:
7905 we can change that arbitrarily.
7907 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7908 then the reload reg may not support QImode moves, so use SImode.
7909 If foo is in memory due to spilling a pseudo reg, this is safe,
7910 because the QImode value is in the least significant part of a
7911 slot big enough for a SImode. If foo is some other sort of
7912 memory reference, then it is impossible to reload this case,
7913 so previous passes had better make sure this never happens.
7915 Then consider a one-word union which has SImode and one of its
7916 members is a float, being fetched as (SUBREG:SF union:SI).
7917 We must fetch that as SFmode because we could be loading into
7918 a float-only register. In this case OLD's mode is correct.
7920 Consider an immediate integer: it has VOIDmode. Here we need
7921 to get a mode from something else.
7923 In some cases, there is a fourth mode, the operand's
7924 containing mode. If the insn specifies a containing mode for
7925 this operand, it overrides all others.
7927 I am not sure whether the algorithm here is always right,
7928 but it does the right things in those cases. */
7930 mode
= GET_MODE (old
);
7931 if (mode
== VOIDmode
)
7934 /* We cannot use gen_lowpart_common since it can do the wrong thing
7935 when REG_RTX has a multi-word mode. Note that REG_RTX must
7936 always be a REG here. */
7937 if (GET_MODE (reg_rtx
) != mode
)
7938 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7940 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7943 /* AUTO_INC reloads need to be handled even if inherited. We got an
7944 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7945 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7946 && ! rtx_equal_p (reg_rtx
, old
)
7948 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7950 /* When inheriting a wider reload, we have a MEM in rl->in,
7951 e.g. inheriting a SImode output reload for
7952 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7953 if (optimize
&& reload_inherited
[j
] && rl
->in
7955 && MEM_P (rl
->in_reg
)
7956 && reload_spill_index
[j
] >= 0
7957 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7958 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7960 /* If we are reloading a register that was recently stored in with an
7961 output-reload, see if we can prove there was
7962 actually no need to store the old value in it. */
7965 && (reload_inherited
[j
] || reload_override_in
[j
])
7968 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7970 /* There doesn't seem to be any reason to restrict this to pseudos
7971 and doing so loses in the case where we are copying from a
7972 register of the wrong class. */
7973 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7975 /* The insn might have already some references to stackslots
7976 replaced by MEMs, while reload_out_reg still names the
7978 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7979 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7980 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7983 /* Do output reloading for reload RL, which is for the insn described by
7984 CHAIN and has the number J.
7985 ??? At some point we need to support handling output reloads of
7986 JUMP_INSNs or insns that set cc0. */
7988 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7991 rtx_insn
*insn
= chain
->insn
;
7992 /* If this is an output reload that stores something that is
7993 not loaded in this same reload, see if we can eliminate a previous
7995 rtx pseudo
= rl
->out_reg
;
7996 rtx reg_rtx
= rl
->reg_rtx
;
7998 if (rl
->out
&& reg_rtx
)
8002 /* Determine the mode to reload in.
8003 See comments above (for input reloading). */
8004 mode
= GET_MODE (rl
->out
);
8005 if (mode
== VOIDmode
)
8007 /* VOIDmode should never happen for an output. */
8008 if (asm_noperands (PATTERN (insn
)) < 0)
8009 /* It's the compiler's fault. */
8010 fatal_insn ("VOIDmode on an output", insn
);
8011 error_for_asm (insn
, "output operand is constant in %<asm%>");
8012 /* Prevent crash--use something we know is valid. */
8014 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
8016 if (GET_MODE (reg_rtx
) != mode
)
8017 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
8019 reload_reg_rtx_for_output
[j
] = reg_rtx
;
8024 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
8025 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
8026 && reg_last_reload_reg
[REGNO (pseudo
)])
8028 int pseudo_no
= REGNO (pseudo
);
8029 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
8031 /* We don't need to test full validity of last_regno for
8032 inherit here; we only want to know if the store actually
8033 matches the pseudo. */
8034 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8035 && reg_reloaded_contents
[last_regno
] == pseudo_no
8036 && spill_reg_store
[last_regno
]
8037 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8038 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8044 || rtx_equal_p (old
, reg_rtx
))
8047 /* An output operand that dies right away does need a reload,
8048 but need not be copied from it. Show the new location in the
8050 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8051 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8053 XEXP (note
, 0) = reg_rtx
;
8056 /* Likewise for a SUBREG of an operand that dies. */
8057 else if (GET_CODE (old
) == SUBREG
8058 && REG_P (SUBREG_REG (old
))
8059 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8062 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8065 else if (GET_CODE (old
) == SCRATCH
)
8066 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8067 but we don't want to make an output reload. */
8070 /* If is a JUMP_INSN, we can't support output reloads yet. */
8071 gcc_assert (NONJUMP_INSN_P (insn
));
8073 emit_output_reload_insns (chain
, rld
+ j
, j
);
8076 /* A reload copies values of MODE from register SRC to register DEST.
8077 Return true if it can be treated for inheritance purposes like a
8078 group of reloads, each one reloading a single hard register. The
8079 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8080 occupy the same number of hard registers. */
8083 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8084 int src ATTRIBUTE_UNUSED
,
8085 machine_mode mode ATTRIBUTE_UNUSED
)
8087 #ifdef CANNOT_CHANGE_MODE_CLASS
8088 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8089 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8095 /* Output insns to reload values in and out of the chosen reload regs. */
8098 emit_reload_insns (struct insn_chain
*chain
)
8100 rtx_insn
*insn
= chain
->insn
;
8104 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8106 for (j
= 0; j
< reload_n_operands
; j
++)
8107 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8108 = inpaddr_address_reload_insns
[j
]
8109 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8110 = outaddr_address_reload_insns
[j
]
8111 = other_output_reload_insns
[j
] = 0;
8112 other_input_address_reload_insns
= 0;
8113 other_input_reload_insns
= 0;
8114 operand_reload_insns
= 0;
8115 other_operand_reload_insns
= 0;
8117 /* Dump reloads into the dump file. */
8120 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8121 debug_reload_to_stream (dump_file
);
8124 for (j
= 0; j
< n_reloads
; j
++)
8125 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8129 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8130 new_spill_reg_store
[i
] = 0;
8133 /* Now output the instructions to copy the data into and out of the
8134 reload registers. Do these in the order that the reloads were reported,
8135 since reloads of base and index registers precede reloads of operands
8136 and the operands may need the base and index registers reloaded. */
8138 for (j
= 0; j
< n_reloads
; j
++)
8140 do_input_reload (chain
, rld
+ j
, j
);
8141 do_output_reload (chain
, rld
+ j
, j
);
8144 /* Now write all the insns we made for reloads in the order expected by
8145 the allocation functions. Prior to the insn being reloaded, we write
8146 the following reloads:
8148 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8150 RELOAD_OTHER reloads.
8152 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8153 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8154 RELOAD_FOR_INPUT reload for the operand.
8156 RELOAD_FOR_OPADDR_ADDRS reloads.
8158 RELOAD_FOR_OPERAND_ADDRESS reloads.
8160 After the insn being reloaded, we write the following:
8162 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8163 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8164 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8165 reloads for the operand. The RELOAD_OTHER output reloads are
8166 output in descending order by reload number. */
8168 emit_insn_before (other_input_address_reload_insns
, insn
);
8169 emit_insn_before (other_input_reload_insns
, insn
);
8171 for (j
= 0; j
< reload_n_operands
; j
++)
8173 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8174 emit_insn_before (input_address_reload_insns
[j
], insn
);
8175 emit_insn_before (input_reload_insns
[j
], insn
);
8178 emit_insn_before (other_operand_reload_insns
, insn
);
8179 emit_insn_before (operand_reload_insns
, insn
);
8181 for (j
= 0; j
< reload_n_operands
; j
++)
8183 rtx_insn
*x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8184 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8185 x
= emit_insn_after (output_reload_insns
[j
], x
);
8186 emit_insn_after (other_output_reload_insns
[j
], x
);
8189 /* For all the spill regs newly reloaded in this instruction,
8190 record what they were reloaded from, so subsequent instructions
8191 can inherit the reloads.
8193 Update spill_reg_store for the reloads of this insn.
8194 Copy the elements that were updated in the loop above. */
8196 for (j
= 0; j
< n_reloads
; j
++)
8198 int r
= reload_order
[j
];
8199 int i
= reload_spill_index
[r
];
8201 /* If this is a non-inherited input reload from a pseudo, we must
8202 clear any memory of a previous store to the same pseudo. Only do
8203 something if there will not be an output reload for the pseudo
8205 if (rld
[r
].in_reg
!= 0
8206 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8208 rtx reg
= rld
[r
].in_reg
;
8210 if (GET_CODE (reg
) == SUBREG
)
8211 reg
= SUBREG_REG (reg
);
8214 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8215 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8217 int nregno
= REGNO (reg
);
8219 if (reg_last_reload_reg
[nregno
])
8221 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8223 if (reg_reloaded_contents
[last_regno
] == nregno
)
8224 spill_reg_store
[last_regno
] = 0;
8229 /* I is nonneg if this reload used a register.
8230 If rld[r].reg_rtx is 0, this is an optional reload
8231 that we opted to ignore. */
8233 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8235 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8238 /* For a multi register reload, we need to check if all or part
8239 of the value lives to the end. */
8240 for (k
= 0; k
< nr
; k
++)
8241 if (reload_reg_reaches_end_p (i
+ k
, r
))
8242 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8244 /* Maybe the spill reg contains a copy of reload_out. */
8246 && (REG_P (rld
[r
].out
)
8248 ? REG_P (rld
[r
].out_reg
)
8249 /* The reload value is an auto-modification of
8250 some kind. For PRE_INC, POST_INC, PRE_DEC
8251 and POST_DEC, we record an equivalence
8252 between the reload register and the operand
8253 on the optimistic assumption that we can make
8254 the equivalence hold. reload_as_needed must
8255 then either make it hold or invalidate the
8258 PRE_MODIFY and POST_MODIFY addresses are reloaded
8259 somewhat differently, and allowing them here leads
8261 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8262 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8266 reg
= reload_reg_rtx_for_output
[r
];
8267 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8269 machine_mode mode
= GET_MODE (reg
);
8270 int regno
= REGNO (reg
);
8271 int nregs
= hard_regno_nregs
[regno
][mode
];
8272 rtx out
= (REG_P (rld
[r
].out
)
8276 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8277 int out_regno
= REGNO (out
);
8278 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8279 : hard_regno_nregs
[out_regno
][mode
]);
8282 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8283 spill_reg_stored_to
[regno
] = out
;
8284 reg_last_reload_reg
[out_regno
] = reg
;
8286 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8287 && nregs
== out_nregs
8288 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8290 /* If OUT_REGNO is a hard register, it may occupy more than
8291 one register. If it does, say what is in the
8292 rest of the registers assuming that both registers
8293 agree on how many words the object takes. If not,
8294 invalidate the subsequent registers. */
8296 if (HARD_REGISTER_NUM_P (out_regno
))
8297 for (k
= 1; k
< out_nregs
; k
++)
8298 reg_last_reload_reg
[out_regno
+ k
]
8299 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8301 /* Now do the inverse operation. */
8302 for (k
= 0; k
< nregs
; k
++)
8304 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8305 reg_reloaded_contents
[regno
+ k
]
8306 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8309 reg_reloaded_insn
[regno
+ k
] = insn
;
8310 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8311 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8312 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8315 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8320 /* Maybe the spill reg contains a copy of reload_in. Only do
8321 something if there will not be an output reload for
8322 the register being reloaded. */
8323 else if (rld
[r
].out_reg
== 0
8325 && ((REG_P (rld
[r
].in
)
8326 && !HARD_REGISTER_P (rld
[r
].in
)
8327 && !REGNO_REG_SET_P (®_has_output_reload
,
8329 || (REG_P (rld
[r
].in_reg
)
8330 && !REGNO_REG_SET_P (®_has_output_reload
,
8331 REGNO (rld
[r
].in_reg
))))
8332 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8336 reg
= reload_reg_rtx_for_input
[r
];
8337 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8347 mode
= GET_MODE (reg
);
8348 regno
= REGNO (reg
);
8349 nregs
= hard_regno_nregs
[regno
][mode
];
8350 if (REG_P (rld
[r
].in
)
8351 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8353 else if (REG_P (rld
[r
].in_reg
))
8356 in
= XEXP (rld
[r
].in_reg
, 0);
8357 in_regno
= REGNO (in
);
8359 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8360 : hard_regno_nregs
[in_regno
][mode
]);
8362 reg_last_reload_reg
[in_regno
] = reg
;
8364 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8365 && nregs
== in_nregs
8366 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8368 if (HARD_REGISTER_NUM_P (in_regno
))
8369 for (k
= 1; k
< in_nregs
; k
++)
8370 reg_last_reload_reg
[in_regno
+ k
]
8371 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8373 /* Unless we inherited this reload, show we haven't
8374 recently done a store.
8375 Previous stores of inherited auto_inc expressions
8376 also have to be discarded. */
8377 if (! reload_inherited
[r
]
8378 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8379 spill_reg_store
[regno
] = 0;
8381 for (k
= 0; k
< nregs
; k
++)
8383 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8384 reg_reloaded_contents
[regno
+ k
]
8385 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8388 reg_reloaded_insn
[regno
+ k
] = insn
;
8389 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8390 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8391 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8394 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8401 /* The following if-statement was #if 0'd in 1.34 (or before...).
8402 It's reenabled in 1.35 because supposedly nothing else
8403 deals with this problem. */
8405 /* If a register gets output-reloaded from a non-spill register,
8406 that invalidates any previous reloaded copy of it.
8407 But forget_old_reloads_1 won't get to see it, because
8408 it thinks only about the original insn. So invalidate it here.
8409 Also do the same thing for RELOAD_OTHER constraints where the
8410 output is discarded. */
8412 && ((rld
[r
].out
!= 0
8413 && (REG_P (rld
[r
].out
)
8414 || (MEM_P (rld
[r
].out
)
8415 && REG_P (rld
[r
].out_reg
))))
8416 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8417 && REG_P (rld
[r
].out_reg
))))
8419 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8420 ? rld
[r
].out
: rld
[r
].out_reg
);
8421 int out_regno
= REGNO (out
);
8422 machine_mode mode
= GET_MODE (out
);
8424 /* REG_RTX is now set or clobbered by the main instruction.
8425 As the comment above explains, forget_old_reloads_1 only
8426 sees the original instruction, and there is no guarantee
8427 that the original instruction also clobbered REG_RTX.
8428 For example, if find_reloads sees that the input side of
8429 a matched operand pair dies in this instruction, it may
8430 use the input register as the reload register.
8432 Calling forget_old_reloads_1 is a waste of effort if
8433 REG_RTX is also the output register.
8435 If we know that REG_RTX holds the value of a pseudo
8436 register, the code after the call will record that fact. */
8437 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8438 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8440 if (!HARD_REGISTER_NUM_P (out_regno
))
8443 rtx_insn
*store_insn
= NULL
;
8445 reg_last_reload_reg
[out_regno
] = 0;
8447 /* If we can find a hard register that is stored, record
8448 the storing insn so that we may delete this insn with
8449 delete_output_reload. */
8450 src_reg
= reload_reg_rtx_for_output
[r
];
8454 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8455 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8461 /* If this is an optional reload, try to find the
8462 source reg from an input reload. */
8463 rtx set
= single_set (insn
);
8464 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8468 src_reg
= SET_SRC (set
);
8470 for (k
= 0; k
< n_reloads
; k
++)
8472 if (rld
[k
].in
== src_reg
)
8474 src_reg
= reload_reg_rtx_for_input
[k
];
8480 if (src_reg
&& REG_P (src_reg
)
8481 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8483 int src_regno
, src_nregs
, k
;
8486 gcc_assert (GET_MODE (src_reg
) == mode
);
8487 src_regno
= REGNO (src_reg
);
8488 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8489 /* The place where to find a death note varies with
8490 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8491 necessarily checked exactly in the code that moves
8492 notes, so just check both locations. */
8493 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8494 if (! note
&& store_insn
)
8495 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8496 for (k
= 0; k
< src_nregs
; k
++)
8498 spill_reg_store
[src_regno
+ k
] = store_insn
;
8499 spill_reg_stored_to
[src_regno
+ k
] = out
;
8500 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8501 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8502 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8503 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8504 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8506 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8509 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8511 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8513 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8515 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8517 reg_last_reload_reg
[out_regno
] = src_reg
;
8518 /* We have to set reg_has_output_reload here, or else
8519 forget_old_reloads_1 will clear reg_last_reload_reg
8521 SET_REGNO_REG_SET (®_has_output_reload
,
8527 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8529 for (k
= 0; k
< out_nregs
; k
++)
8530 reg_last_reload_reg
[out_regno
+ k
] = 0;
8534 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8537 /* Go through the motions to emit INSN and test if it is strictly valid.
8538 Return the emitted insn if valid, else return NULL. */
8541 emit_insn_if_valid_for_reload (rtx pat
)
8543 rtx_insn
*last
= get_last_insn ();
8546 rtx_insn
*insn
= emit_insn (pat
);
8547 code
= recog_memoized (insn
);
8551 extract_insn (insn
);
8552 /* We want constrain operands to treat this insn strictly in its
8553 validity determination, i.e., the way it would after reload has
8555 if (constrain_operands (1, get_enabled_alternatives (insn
)))
8559 delete_insns_since (last
);
8563 /* Emit code to perform a reload from IN (which may be a reload register) to
8564 OUT (which may also be a reload register). IN or OUT is from operand
8565 OPNUM with reload type TYPE.
8567 Returns first insn emitted. */
8570 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8572 rtx_insn
*last
= get_last_insn ();
8574 #ifdef SECONDARY_MEMORY_NEEDED
8578 /* If IN is a paradoxical SUBREG, remove it and try to put the
8579 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8580 if (!strip_paradoxical_subreg (&in
, &out
))
8581 strip_paradoxical_subreg (&out
, &in
);
8583 /* How to do this reload can get quite tricky. Normally, we are being
8584 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8585 register that didn't get a hard register. In that case we can just
8586 call emit_move_insn.
8588 We can also be asked to reload a PLUS that adds a register or a MEM to
8589 another register, constant or MEM. This can occur during frame pointer
8590 elimination and while reloading addresses. This case is handled by
8591 trying to emit a single insn to perform the add. If it is not valid,
8592 we use a two insn sequence.
8594 Or we can be asked to reload an unary operand that was a fragment of
8595 an addressing mode, into a register. If it isn't recognized as-is,
8596 we try making the unop operand and the reload-register the same:
8597 (set reg:X (unop:X expr:Y))
8598 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8600 Finally, we could be called to handle an 'o' constraint by putting
8601 an address into a register. In that case, we first try to do this
8602 with a named pattern of "reload_load_address". If no such pattern
8603 exists, we just emit a SET insn and hope for the best (it will normally
8604 be valid on machines that use 'o').
8606 This entire process is made complex because reload will never
8607 process the insns we generate here and so we must ensure that
8608 they will fit their constraints and also by the fact that parts of
8609 IN might be being reloaded separately and replaced with spill registers.
8610 Because of this, we are, in some sense, just guessing the right approach
8611 here. The one listed above seems to work.
8613 ??? At some point, this whole thing needs to be rethought. */
8615 if (GET_CODE (in
) == PLUS
8616 && (REG_P (XEXP (in
, 0))
8617 || GET_CODE (XEXP (in
, 0)) == SUBREG
8618 || MEM_P (XEXP (in
, 0)))
8619 && (REG_P (XEXP (in
, 1))
8620 || GET_CODE (XEXP (in
, 1)) == SUBREG
8621 || CONSTANT_P (XEXP (in
, 1))
8622 || MEM_P (XEXP (in
, 1))))
8624 /* We need to compute the sum of a register or a MEM and another
8625 register, constant, or MEM, and put it into the reload
8626 register. The best possible way of doing this is if the machine
8627 has a three-operand ADD insn that accepts the required operands.
8629 The simplest approach is to try to generate such an insn and see if it
8630 is recognized and matches its constraints. If so, it can be used.
8632 It might be better not to actually emit the insn unless it is valid,
8633 but we need to pass the insn as an operand to `recog' and
8634 `extract_insn' and it is simpler to emit and then delete the insn if
8635 not valid than to dummy things up. */
8639 enum insn_code code
;
8641 op0
= find_replacement (&XEXP (in
, 0));
8642 op1
= find_replacement (&XEXP (in
, 1));
8644 /* Since constraint checking is strict, commutativity won't be
8645 checked, so we need to do that here to avoid spurious failure
8646 if the add instruction is two-address and the second operand
8647 of the add is the same as the reload reg, which is frequently
8648 the case. If the insn would be A = B + A, rearrange it so
8649 it will be A = A + B as constrain_operands expects. */
8651 if (REG_P (XEXP (in
, 1))
8652 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8653 tem
= op0
, op0
= op1
, op1
= tem
;
8655 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8656 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8658 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8662 /* If that failed, we must use a conservative two-insn sequence.
8664 Use a move to copy one operand into the reload register. Prefer
8665 to reload a constant, MEM or pseudo since the move patterns can
8666 handle an arbitrary operand. If OP1 is not a constant, MEM or
8667 pseudo and OP1 is not a valid operand for an add instruction, then
8670 After reloading one of the operands into the reload register, add
8671 the reload register to the output register.
8673 If there is another way to do this for a specific machine, a
8674 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8677 code
= optab_handler (add_optab
, GET_MODE (out
));
8679 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8681 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8682 || (code
!= CODE_FOR_nothing
8683 && !insn_operand_matches (code
, 2, op1
)))
8684 tem
= op0
, op0
= op1
, op1
= tem
;
8686 gen_reload (out
, op0
, opnum
, type
);
8688 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8689 This fixes a problem on the 32K where the stack pointer cannot
8690 be used as an operand of an add insn. */
8692 if (rtx_equal_p (op0
, op1
))
8695 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8698 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8699 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8703 /* If that failed, copy the address register to the reload register.
8704 Then add the constant to the reload register. */
8706 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8707 gen_reload (out
, op1
, opnum
, type
);
8708 insn
= emit_insn (gen_add2_insn (out
, op0
));
8709 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8712 #ifdef SECONDARY_MEMORY_NEEDED
8713 /* If we need a memory location to do the move, do it that way. */
8714 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8715 (REG_P (tem1
) && REG_P (tem2
)))
8716 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8717 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8718 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8719 REGNO_REG_CLASS (REGNO (tem2
)),
8722 /* Get the memory to use and rewrite both registers to its mode. */
8723 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8725 if (GET_MODE (loc
) != GET_MODE (out
))
8726 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8728 if (GET_MODE (loc
) != GET_MODE (in
))
8729 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8731 gen_reload (loc
, in
, opnum
, type
);
8732 gen_reload (out
, loc
, opnum
, type
);
8735 else if (REG_P (out
) && UNARY_P (in
))
8742 op1
= find_replacement (&XEXP (in
, 0));
8743 if (op1
!= XEXP (in
, 0))
8744 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8746 /* First, try a plain SET. */
8747 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8751 /* If that failed, move the inner operand to the reload
8752 register, and try the same unop with the inner expression
8753 replaced with the reload register. */
8755 if (GET_MODE (op1
) != GET_MODE (out
))
8756 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8760 gen_reload (out_moded
, op1
, opnum
, type
);
8762 insn
= gen_rtx_SET (out
, gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8764 insn
= emit_insn_if_valid_for_reload (insn
);
8767 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8768 return as_a
<rtx_insn
*> (insn
);
8771 fatal_insn ("failure trying to reload:", set
);
8773 /* If IN is a simple operand, use gen_move_insn. */
8774 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8776 tem
= emit_insn (gen_move_insn (out
, in
));
8777 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8778 mark_jump_label (in
, tem
, 0);
8781 else if (targetm
.have_reload_load_address ())
8782 emit_insn (targetm
.gen_reload_load_address (out
, in
));
8784 /* Otherwise, just write (set OUT IN) and hope for the best. */
8786 emit_insn (gen_rtx_SET (out
, in
));
8788 /* Return the first insn emitted.
8789 We can not just return get_last_insn, because there may have
8790 been multiple instructions emitted. Also note that gen_move_insn may
8791 emit more than one insn itself, so we can not assume that there is one
8792 insn emitted per emit_insn_before call. */
8794 return last
? NEXT_INSN (last
) : get_insns ();
8797 /* Delete a previously made output-reload whose result we now believe
8798 is not needed. First we double-check.
8800 INSN is the insn now being processed.
8801 LAST_RELOAD_REG is the hard register number for which we want to delete
8802 the last output reload.
8803 J is the reload-number that originally used REG. The caller has made
8804 certain that reload J doesn't use REG any longer for input.
8805 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8808 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8811 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8812 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8815 int n_inherited
= 0;
8820 /* It is possible that this reload has been only used to set another reload
8821 we eliminated earlier and thus deleted this instruction too. */
8822 if (output_reload_insn
->deleted ())
8825 /* Get the raw pseudo-register referred to. */
8827 while (GET_CODE (reg
) == SUBREG
)
8828 reg
= SUBREG_REG (reg
);
8829 substed
= reg_equiv_memory_loc (REGNO (reg
));
8831 /* This is unsafe if the operand occurs more often in the current
8832 insn than it is inherited. */
8833 for (k
= n_reloads
- 1; k
>= 0; k
--)
8835 rtx reg2
= rld
[k
].in
;
8838 if (MEM_P (reg2
) || reload_override_in
[k
])
8839 reg2
= rld
[k
].in_reg
;
8841 if (AUTO_INC_DEC
&& rld
[k
].out
&& ! rld
[k
].out_reg
)
8842 reg2
= XEXP (rld
[k
].in_reg
, 0);
8844 while (GET_CODE (reg2
) == SUBREG
)
8845 reg2
= SUBREG_REG (reg2
);
8846 if (rtx_equal_p (reg2
, reg
))
8848 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8854 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8855 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8856 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8859 n_occurrences
+= count_occurrences (PATTERN (insn
),
8860 eliminate_regs (substed
, VOIDmode
,
8862 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8864 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8865 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8867 if (n_occurrences
> n_inherited
)
8870 regno
= REGNO (reg
);
8871 if (regno
>= FIRST_PSEUDO_REGISTER
)
8874 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8876 /* If the pseudo-reg we are reloading is no longer referenced
8877 anywhere between the store into it and here,
8878 and we're within the same basic block, then the value can only
8879 pass through the reload reg and end up here.
8880 Otherwise, give up--return. */
8881 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8882 i1
!= insn
; i1
= NEXT_INSN (i1
))
8884 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8886 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8887 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8889 /* If this is USE in front of INSN, we only have to check that
8890 there are no more references than accounted for by inheritance. */
8891 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8893 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8894 i1
= NEXT_INSN (i1
);
8896 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8902 /* We will be deleting the insn. Remove the spill reg information. */
8903 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8905 spill_reg_store
[last_reload_reg
+ k
] = 0;
8906 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8909 /* The caller has already checked that REG dies or is set in INSN.
8910 It has also checked that we are optimizing, and thus some
8911 inaccuracies in the debugging information are acceptable.
8912 So we could just delete output_reload_insn. But in some cases
8913 we can improve the debugging information without sacrificing
8914 optimization - maybe even improving the code: See if the pseudo
8915 reg has been completely replaced with reload regs. If so, delete
8916 the store insn and forget we had a stack slot for the pseudo. */
8917 if (rld
[j
].out
!= rld
[j
].in
8918 && REG_N_DEATHS (REGNO (reg
)) == 1
8919 && REG_N_SETS (REGNO (reg
)) == 1
8920 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8921 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8925 /* We know that it was used only between here and the beginning of
8926 the current basic block. (We also know that the last use before
8927 INSN was the output reload we are thinking of deleting, but never
8928 mind that.) Search that range; see if any ref remains. */
8929 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8931 rtx set
= single_set (i2
);
8933 /* Uses which just store in the pseudo don't count,
8934 since if they are the only uses, they are dead. */
8935 if (set
!= 0 && SET_DEST (set
) == reg
)
8937 if (LABEL_P (i2
) || JUMP_P (i2
))
8939 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8940 && reg_mentioned_p (reg
, PATTERN (i2
)))
8942 /* Some other ref remains; just delete the output reload we
8944 delete_address_reloads (output_reload_insn
, insn
);
8945 delete_insn (output_reload_insn
);
8950 /* Delete the now-dead stores into this pseudo. Note that this
8951 loop also takes care of deleting output_reload_insn. */
8952 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8954 rtx set
= single_set (i2
);
8956 if (set
!= 0 && SET_DEST (set
) == reg
)
8958 delete_address_reloads (i2
, insn
);
8961 if (LABEL_P (i2
) || JUMP_P (i2
))
8965 /* For the debugging info, say the pseudo lives in this reload reg. */
8966 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8967 if (ira_conflicts_p
)
8968 /* Inform IRA about the change. */
8969 ira_mark_allocation_change (REGNO (reg
));
8970 alter_reg (REGNO (reg
), -1, false);
8974 delete_address_reloads (output_reload_insn
, insn
);
8975 delete_insn (output_reload_insn
);
8979 /* We are going to delete DEAD_INSN. Recursively delete loads of
8980 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8981 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8983 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
8985 rtx set
= single_set (dead_insn
);
8987 rtx_insn
*prev
, *next
;
8990 rtx dst
= SET_DEST (set
);
8992 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8994 /* If we deleted the store from a reloaded post_{in,de}c expression,
8995 we can delete the matching adds. */
8996 prev
= PREV_INSN (dead_insn
);
8997 next
= NEXT_INSN (dead_insn
);
8998 if (! prev
|| ! next
)
9000 set
= single_set (next
);
9001 set2
= single_set (prev
);
9003 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
9004 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
9005 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
9007 dst
= SET_DEST (set
);
9008 if (! rtx_equal_p (dst
, SET_DEST (set2
))
9009 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
9010 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
9011 || (INTVAL (XEXP (SET_SRC (set
), 1))
9012 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
9014 delete_related_insns (prev
);
9015 delete_related_insns (next
);
9018 /* Subfunction of delete_address_reloads: process registers found in X. */
9020 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
9022 rtx_insn
*prev
, *i2
;
9025 enum rtx_code code
= GET_CODE (x
);
9029 const char *fmt
= GET_RTX_FORMAT (code
);
9030 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9033 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9034 else if (fmt
[i
] == 'E')
9036 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9037 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9044 if (spill_reg_order
[REGNO (x
)] < 0)
9047 /* Scan backwards for the insn that sets x. This might be a way back due
9049 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9051 code
= GET_CODE (prev
);
9052 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9056 if (reg_set_p (x
, PATTERN (prev
)))
9058 if (reg_referenced_p (x
, PATTERN (prev
)))
9061 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9063 /* Check that PREV only sets the reload register. */
9064 set
= single_set (prev
);
9067 dst
= SET_DEST (set
);
9069 || ! rtx_equal_p (dst
, x
))
9071 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9073 /* Check if DST was used in a later insn -
9074 it might have been inherited. */
9075 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9081 if (reg_referenced_p (dst
, PATTERN (i2
)))
9083 /* If there is a reference to the register in the current insn,
9084 it might be loaded in a non-inherited reload. If no other
9085 reload uses it, that means the register is set before
9087 if (i2
== current_insn
)
9089 for (j
= n_reloads
- 1; j
>= 0; j
--)
9090 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9091 || reload_override_in
[j
] == dst
)
9093 for (j
= n_reloads
- 1; j
>= 0; j
--)
9094 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9103 /* If DST is still live at CURRENT_INSN, check if it is used for
9104 any reload. Note that even if CURRENT_INSN sets DST, we still
9105 have to check the reloads. */
9106 if (i2
== current_insn
)
9108 for (j
= n_reloads
- 1; j
>= 0; j
--)
9109 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9110 || reload_override_in
[j
] == dst
)
9112 /* ??? We can't finish the loop here, because dst might be
9113 allocated to a pseudo in this block if no reload in this
9114 block needs any of the classes containing DST - see
9115 spill_hard_reg. There is no easy way to tell this, so we
9116 have to scan till the end of the basic block. */
9118 if (reg_set_p (dst
, PATTERN (i2
)))
9122 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9123 reg_reloaded_contents
[REGNO (dst
)] = -1;
9127 /* Output reload-insns to reload VALUE into RELOADREG.
9128 VALUE is an autoincrement or autodecrement RTX whose operand
9129 is a register or memory location;
9130 so reloading involves incrementing that location.
9131 IN is either identical to VALUE, or some cheaper place to reload from.
9133 INC_AMOUNT is the number to increment or decrement by (always positive).
9134 This cannot be deduced from VALUE. */
9137 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9139 /* REG or MEM to be copied and incremented. */
9140 rtx incloc
= find_replacement (&XEXP (value
, 0));
9141 /* Nonzero if increment after copying. */
9142 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9143 || GET_CODE (value
) == POST_MODIFY
);
9148 rtx real_in
= in
== value
? incloc
: in
;
9150 /* No hard register is equivalent to this register after
9151 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9152 we could inc/dec that register as well (maybe even using it for
9153 the source), but I'm not sure it's worth worrying about. */
9155 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9157 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9159 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9160 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9164 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9165 inc_amount
= -inc_amount
;
9167 inc
= GEN_INT (inc_amount
);
9170 /* If this is post-increment, first copy the location to the reload reg. */
9171 if (post
&& real_in
!= reloadreg
)
9172 emit_insn (gen_move_insn (reloadreg
, real_in
));
9176 /* See if we can directly increment INCLOC. Use a method similar to
9177 that in gen_reload. */
9179 last
= get_last_insn ();
9180 add_insn
= emit_insn (gen_rtx_SET (incloc
,
9181 gen_rtx_PLUS (GET_MODE (incloc
),
9184 code
= recog_memoized (add_insn
);
9187 extract_insn (add_insn
);
9188 if (constrain_operands (1, get_enabled_alternatives (add_insn
)))
9190 /* If this is a pre-increment and we have incremented the value
9191 where it lives, copy the incremented value to RELOADREG to
9192 be used as an address. */
9195 emit_insn (gen_move_insn (reloadreg
, incloc
));
9199 delete_insns_since (last
);
9202 /* If couldn't do the increment directly, must increment in RELOADREG.
9203 The way we do this depends on whether this is pre- or post-increment.
9204 For pre-increment, copy INCLOC to the reload register, increment it
9205 there, then save back. */
9209 if (in
!= reloadreg
)
9210 emit_insn (gen_move_insn (reloadreg
, real_in
));
9211 emit_insn (gen_add2_insn (reloadreg
, inc
));
9212 emit_insn (gen_move_insn (incloc
, reloadreg
));
9217 Because this might be a jump insn or a compare, and because RELOADREG
9218 may not be available after the insn in an input reload, we must do
9219 the incrementation before the insn being reloaded for.
9221 We have already copied IN to RELOADREG. Increment the copy in
9222 RELOADREG, save that back, then decrement RELOADREG so it has
9223 the original value. */
9225 emit_insn (gen_add2_insn (reloadreg
, inc
));
9226 emit_insn (gen_move_insn (incloc
, reloadreg
));
9227 if (CONST_INT_P (inc
))
9228 emit_insn (gen_add2_insn (reloadreg
,
9229 gen_int_mode (-INTVAL (inc
),
9230 GET_MODE (reloadreg
))));
9232 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9237 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9239 enum rtx_code code
= GET_CODE (x
);
9243 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9245 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9249 /* Scan all the operand sub-expressions. */
9250 fmt
= GET_RTX_FORMAT (code
);
9251 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9254 add_auto_inc_notes (insn
, XEXP (x
, i
));
9255 else if (fmt
[i
] == 'E')
9256 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9257 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));