1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
33 #include "stringpool.h"
39 #include "diagnostic-core.h"
41 #include "fold-const.h"
42 #include "stor-layout.h"
46 #include "insn-attr.h"
50 #include "common/common-target.h"
52 #include "langhooks.h"
55 #include "tree-pass.h"
59 /* This file should be included last. */
60 #include "target-def.h"
64 struct processor_costs
{
68 /* Integer signed load */
71 /* Integer zeroed load */
77 /* fmov, fneg, fabs */
81 const int float_plusminus
;
87 const int float_cmove
;
93 const int float_div_sf
;
96 const int float_div_df
;
99 const int float_sqrt_sf
;
102 const int float_sqrt_df
;
110 /* integer multiply cost for each bit set past the most
111 significant 3, so the formula for multiply cost becomes:
114 highest_bit = highest_clear_bit(rs1);
116 highest_bit = highest_set_bit(rs1);
119 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
121 A value of zero indicates that the multiply costs is fixed,
123 const int int_mul_bit_factor
;
134 /* penalty for shifts, due to scheduling rules etc. */
135 const int shift_penalty
;
139 struct processor_costs cypress_costs
= {
140 COSTS_N_INSNS (2), /* int load */
141 COSTS_N_INSNS (2), /* int signed load */
142 COSTS_N_INSNS (2), /* int zeroed load */
143 COSTS_N_INSNS (2), /* float load */
144 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
145 COSTS_N_INSNS (5), /* fadd, fsub */
146 COSTS_N_INSNS (1), /* fcmp */
147 COSTS_N_INSNS (1), /* fmov, fmovr */
148 COSTS_N_INSNS (7), /* fmul */
149 COSTS_N_INSNS (37), /* fdivs */
150 COSTS_N_INSNS (37), /* fdivd */
151 COSTS_N_INSNS (63), /* fsqrts */
152 COSTS_N_INSNS (63), /* fsqrtd */
153 COSTS_N_INSNS (1), /* imul */
154 COSTS_N_INSNS (1), /* imulX */
155 0, /* imul bit factor */
156 COSTS_N_INSNS (1), /* idiv */
157 COSTS_N_INSNS (1), /* idivX */
158 COSTS_N_INSNS (1), /* movcc/movr */
159 0, /* shift penalty */
163 struct processor_costs supersparc_costs
= {
164 COSTS_N_INSNS (1), /* int load */
165 COSTS_N_INSNS (1), /* int signed load */
166 COSTS_N_INSNS (1), /* int zeroed load */
167 COSTS_N_INSNS (0), /* float load */
168 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
169 COSTS_N_INSNS (3), /* fadd, fsub */
170 COSTS_N_INSNS (3), /* fcmp */
171 COSTS_N_INSNS (1), /* fmov, fmovr */
172 COSTS_N_INSNS (3), /* fmul */
173 COSTS_N_INSNS (6), /* fdivs */
174 COSTS_N_INSNS (9), /* fdivd */
175 COSTS_N_INSNS (12), /* fsqrts */
176 COSTS_N_INSNS (12), /* fsqrtd */
177 COSTS_N_INSNS (4), /* imul */
178 COSTS_N_INSNS (4), /* imulX */
179 0, /* imul bit factor */
180 COSTS_N_INSNS (4), /* idiv */
181 COSTS_N_INSNS (4), /* idivX */
182 COSTS_N_INSNS (1), /* movcc/movr */
183 1, /* shift penalty */
187 struct processor_costs hypersparc_costs
= {
188 COSTS_N_INSNS (1), /* int load */
189 COSTS_N_INSNS (1), /* int signed load */
190 COSTS_N_INSNS (1), /* int zeroed load */
191 COSTS_N_INSNS (1), /* float load */
192 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
193 COSTS_N_INSNS (1), /* fadd, fsub */
194 COSTS_N_INSNS (1), /* fcmp */
195 COSTS_N_INSNS (1), /* fmov, fmovr */
196 COSTS_N_INSNS (1), /* fmul */
197 COSTS_N_INSNS (8), /* fdivs */
198 COSTS_N_INSNS (12), /* fdivd */
199 COSTS_N_INSNS (17), /* fsqrts */
200 COSTS_N_INSNS (17), /* fsqrtd */
201 COSTS_N_INSNS (17), /* imul */
202 COSTS_N_INSNS (17), /* imulX */
203 0, /* imul bit factor */
204 COSTS_N_INSNS (17), /* idiv */
205 COSTS_N_INSNS (17), /* idivX */
206 COSTS_N_INSNS (1), /* movcc/movr */
207 0, /* shift penalty */
211 struct processor_costs leon_costs
= {
212 COSTS_N_INSNS (1), /* int load */
213 COSTS_N_INSNS (1), /* int signed load */
214 COSTS_N_INSNS (1), /* int zeroed load */
215 COSTS_N_INSNS (1), /* float load */
216 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
217 COSTS_N_INSNS (1), /* fadd, fsub */
218 COSTS_N_INSNS (1), /* fcmp */
219 COSTS_N_INSNS (1), /* fmov, fmovr */
220 COSTS_N_INSNS (1), /* fmul */
221 COSTS_N_INSNS (15), /* fdivs */
222 COSTS_N_INSNS (15), /* fdivd */
223 COSTS_N_INSNS (23), /* fsqrts */
224 COSTS_N_INSNS (23), /* fsqrtd */
225 COSTS_N_INSNS (5), /* imul */
226 COSTS_N_INSNS (5), /* imulX */
227 0, /* imul bit factor */
228 COSTS_N_INSNS (5), /* idiv */
229 COSTS_N_INSNS (5), /* idivX */
230 COSTS_N_INSNS (1), /* movcc/movr */
231 0, /* shift penalty */
235 struct processor_costs leon3_costs
= {
236 COSTS_N_INSNS (1), /* int load */
237 COSTS_N_INSNS (1), /* int signed load */
238 COSTS_N_INSNS (1), /* int zeroed load */
239 COSTS_N_INSNS (1), /* float load */
240 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
241 COSTS_N_INSNS (1), /* fadd, fsub */
242 COSTS_N_INSNS (1), /* fcmp */
243 COSTS_N_INSNS (1), /* fmov, fmovr */
244 COSTS_N_INSNS (1), /* fmul */
245 COSTS_N_INSNS (14), /* fdivs */
246 COSTS_N_INSNS (15), /* fdivd */
247 COSTS_N_INSNS (22), /* fsqrts */
248 COSTS_N_INSNS (23), /* fsqrtd */
249 COSTS_N_INSNS (5), /* imul */
250 COSTS_N_INSNS (5), /* imulX */
251 0, /* imul bit factor */
252 COSTS_N_INSNS (35), /* idiv */
253 COSTS_N_INSNS (35), /* idivX */
254 COSTS_N_INSNS (1), /* movcc/movr */
255 0, /* shift penalty */
259 struct processor_costs sparclet_costs
= {
260 COSTS_N_INSNS (3), /* int load */
261 COSTS_N_INSNS (3), /* int signed load */
262 COSTS_N_INSNS (1), /* int zeroed load */
263 COSTS_N_INSNS (1), /* float load */
264 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
265 COSTS_N_INSNS (1), /* fadd, fsub */
266 COSTS_N_INSNS (1), /* fcmp */
267 COSTS_N_INSNS (1), /* fmov, fmovr */
268 COSTS_N_INSNS (1), /* fmul */
269 COSTS_N_INSNS (1), /* fdivs */
270 COSTS_N_INSNS (1), /* fdivd */
271 COSTS_N_INSNS (1), /* fsqrts */
272 COSTS_N_INSNS (1), /* fsqrtd */
273 COSTS_N_INSNS (5), /* imul */
274 COSTS_N_INSNS (5), /* imulX */
275 0, /* imul bit factor */
276 COSTS_N_INSNS (5), /* idiv */
277 COSTS_N_INSNS (5), /* idivX */
278 COSTS_N_INSNS (1), /* movcc/movr */
279 0, /* shift penalty */
283 struct processor_costs ultrasparc_costs
= {
284 COSTS_N_INSNS (2), /* int load */
285 COSTS_N_INSNS (3), /* int signed load */
286 COSTS_N_INSNS (2), /* int zeroed load */
287 COSTS_N_INSNS (2), /* float load */
288 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
289 COSTS_N_INSNS (4), /* fadd, fsub */
290 COSTS_N_INSNS (1), /* fcmp */
291 COSTS_N_INSNS (2), /* fmov, fmovr */
292 COSTS_N_INSNS (4), /* fmul */
293 COSTS_N_INSNS (13), /* fdivs */
294 COSTS_N_INSNS (23), /* fdivd */
295 COSTS_N_INSNS (13), /* fsqrts */
296 COSTS_N_INSNS (23), /* fsqrtd */
297 COSTS_N_INSNS (4), /* imul */
298 COSTS_N_INSNS (4), /* imulX */
299 2, /* imul bit factor */
300 COSTS_N_INSNS (37), /* idiv */
301 COSTS_N_INSNS (68), /* idivX */
302 COSTS_N_INSNS (2), /* movcc/movr */
303 2, /* shift penalty */
307 struct processor_costs ultrasparc3_costs
= {
308 COSTS_N_INSNS (2), /* int load */
309 COSTS_N_INSNS (3), /* int signed load */
310 COSTS_N_INSNS (3), /* int zeroed load */
311 COSTS_N_INSNS (2), /* float load */
312 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
313 COSTS_N_INSNS (4), /* fadd, fsub */
314 COSTS_N_INSNS (5), /* fcmp */
315 COSTS_N_INSNS (3), /* fmov, fmovr */
316 COSTS_N_INSNS (4), /* fmul */
317 COSTS_N_INSNS (17), /* fdivs */
318 COSTS_N_INSNS (20), /* fdivd */
319 COSTS_N_INSNS (20), /* fsqrts */
320 COSTS_N_INSNS (29), /* fsqrtd */
321 COSTS_N_INSNS (6), /* imul */
322 COSTS_N_INSNS (6), /* imulX */
323 0, /* imul bit factor */
324 COSTS_N_INSNS (40), /* idiv */
325 COSTS_N_INSNS (71), /* idivX */
326 COSTS_N_INSNS (2), /* movcc/movr */
327 0, /* shift penalty */
331 struct processor_costs niagara_costs
= {
332 COSTS_N_INSNS (3), /* int load */
333 COSTS_N_INSNS (3), /* int signed load */
334 COSTS_N_INSNS (3), /* int zeroed load */
335 COSTS_N_INSNS (9), /* float load */
336 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
337 COSTS_N_INSNS (8), /* fadd, fsub */
338 COSTS_N_INSNS (26), /* fcmp */
339 COSTS_N_INSNS (8), /* fmov, fmovr */
340 COSTS_N_INSNS (29), /* fmul */
341 COSTS_N_INSNS (54), /* fdivs */
342 COSTS_N_INSNS (83), /* fdivd */
343 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
344 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
345 COSTS_N_INSNS (11), /* imul */
346 COSTS_N_INSNS (11), /* imulX */
347 0, /* imul bit factor */
348 COSTS_N_INSNS (72), /* idiv */
349 COSTS_N_INSNS (72), /* idivX */
350 COSTS_N_INSNS (1), /* movcc/movr */
351 0, /* shift penalty */
355 struct processor_costs niagara2_costs
= {
356 COSTS_N_INSNS (3), /* int load */
357 COSTS_N_INSNS (3), /* int signed load */
358 COSTS_N_INSNS (3), /* int zeroed load */
359 COSTS_N_INSNS (3), /* float load */
360 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
361 COSTS_N_INSNS (6), /* fadd, fsub */
362 COSTS_N_INSNS (6), /* fcmp */
363 COSTS_N_INSNS (6), /* fmov, fmovr */
364 COSTS_N_INSNS (6), /* fmul */
365 COSTS_N_INSNS (19), /* fdivs */
366 COSTS_N_INSNS (33), /* fdivd */
367 COSTS_N_INSNS (19), /* fsqrts */
368 COSTS_N_INSNS (33), /* fsqrtd */
369 COSTS_N_INSNS (5), /* imul */
370 COSTS_N_INSNS (5), /* imulX */
371 0, /* imul bit factor */
372 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
373 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
374 COSTS_N_INSNS (1), /* movcc/movr */
375 0, /* shift penalty */
379 struct processor_costs niagara3_costs
= {
380 COSTS_N_INSNS (3), /* int load */
381 COSTS_N_INSNS (3), /* int signed load */
382 COSTS_N_INSNS (3), /* int zeroed load */
383 COSTS_N_INSNS (3), /* float load */
384 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
385 COSTS_N_INSNS (9), /* fadd, fsub */
386 COSTS_N_INSNS (9), /* fcmp */
387 COSTS_N_INSNS (9), /* fmov, fmovr */
388 COSTS_N_INSNS (9), /* fmul */
389 COSTS_N_INSNS (23), /* fdivs */
390 COSTS_N_INSNS (37), /* fdivd */
391 COSTS_N_INSNS (23), /* fsqrts */
392 COSTS_N_INSNS (37), /* fsqrtd */
393 COSTS_N_INSNS (9), /* imul */
394 COSTS_N_INSNS (9), /* imulX */
395 0, /* imul bit factor */
396 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
397 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
398 COSTS_N_INSNS (1), /* movcc/movr */
399 0, /* shift penalty */
403 struct processor_costs niagara4_costs
= {
404 COSTS_N_INSNS (5), /* int load */
405 COSTS_N_INSNS (5), /* int signed load */
406 COSTS_N_INSNS (5), /* int zeroed load */
407 COSTS_N_INSNS (5), /* float load */
408 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
409 COSTS_N_INSNS (11), /* fadd, fsub */
410 COSTS_N_INSNS (11), /* fcmp */
411 COSTS_N_INSNS (11), /* fmov, fmovr */
412 COSTS_N_INSNS (11), /* fmul */
413 COSTS_N_INSNS (24), /* fdivs */
414 COSTS_N_INSNS (37), /* fdivd */
415 COSTS_N_INSNS (24), /* fsqrts */
416 COSTS_N_INSNS (37), /* fsqrtd */
417 COSTS_N_INSNS (12), /* imul */
418 COSTS_N_INSNS (12), /* imulX */
419 0, /* imul bit factor */
420 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
421 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
422 COSTS_N_INSNS (1), /* movcc/movr */
423 0, /* shift penalty */
427 struct processor_costs niagara7_costs
= {
428 COSTS_N_INSNS (5), /* int load */
429 COSTS_N_INSNS (5), /* int signed load */
430 COSTS_N_INSNS (5), /* int zeroed load */
431 COSTS_N_INSNS (5), /* float load */
432 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
433 COSTS_N_INSNS (11), /* fadd, fsub */
434 COSTS_N_INSNS (11), /* fcmp */
435 COSTS_N_INSNS (11), /* fmov, fmovr */
436 COSTS_N_INSNS (11), /* fmul */
437 COSTS_N_INSNS (24), /* fdivs */
438 COSTS_N_INSNS (37), /* fdivd */
439 COSTS_N_INSNS (24), /* fsqrts */
440 COSTS_N_INSNS (37), /* fsqrtd */
441 COSTS_N_INSNS (12), /* imul */
442 COSTS_N_INSNS (12), /* imulX */
443 0, /* imul bit factor */
444 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
445 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
446 COSTS_N_INSNS (1), /* movcc/movr */
447 0, /* shift penalty */
450 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
452 #ifdef HAVE_AS_RELAX_OPTION
453 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
454 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
455 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
456 somebody does not branch between the sethi and jmp. */
457 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
459 #define LEAF_SIBCALL_SLOT_RESERVED_P \
460 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
463 /* Vector to say how input registers are mapped to output registers.
464 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
465 eliminate it. You must use -fomit-frame-pointer to get that. */
466 char leaf_reg_remap
[] =
467 { 0, 1, 2, 3, 4, 5, 6, 7,
468 -1, -1, -1, -1, -1, -1, 14, -1,
469 -1, -1, -1, -1, -1, -1, -1, -1,
470 8, 9, 10, 11, 12, 13, -1, 15,
472 32, 33, 34, 35, 36, 37, 38, 39,
473 40, 41, 42, 43, 44, 45, 46, 47,
474 48, 49, 50, 51, 52, 53, 54, 55,
475 56, 57, 58, 59, 60, 61, 62, 63,
476 64, 65, 66, 67, 68, 69, 70, 71,
477 72, 73, 74, 75, 76, 77, 78, 79,
478 80, 81, 82, 83, 84, 85, 86, 87,
479 88, 89, 90, 91, 92, 93, 94, 95,
480 96, 97, 98, 99, 100, 101, 102};
482 /* Vector, indexed by hard register number, which contains 1
483 for a register that is allowable in a candidate for leaf
484 function treatment. */
485 char sparc_leaf_regs
[] =
486 { 1, 1, 1, 1, 1, 1, 1, 1,
487 0, 0, 0, 0, 0, 0, 1, 0,
488 0, 0, 0, 0, 0, 0, 0, 0,
489 1, 1, 1, 1, 1, 1, 0, 1,
490 1, 1, 1, 1, 1, 1, 1, 1,
491 1, 1, 1, 1, 1, 1, 1, 1,
492 1, 1, 1, 1, 1, 1, 1, 1,
493 1, 1, 1, 1, 1, 1, 1, 1,
494 1, 1, 1, 1, 1, 1, 1, 1,
495 1, 1, 1, 1, 1, 1, 1, 1,
496 1, 1, 1, 1, 1, 1, 1, 1,
497 1, 1, 1, 1, 1, 1, 1, 1,
498 1, 1, 1, 1, 1, 1, 1};
500 struct GTY(()) machine_function
502 /* Size of the frame of the function. */
503 HOST_WIDE_INT frame_size
;
505 /* Size of the frame of the function minus the register window save area
506 and the outgoing argument area. */
507 HOST_WIDE_INT apparent_frame_size
;
509 /* Register we pretend the frame pointer is allocated to. Normally, this
510 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
511 record "offset" separately as it may be too big for (reg + disp). */
513 HOST_WIDE_INT frame_base_offset
;
515 /* Number of global or FP registers to be saved (as 4-byte quantities). */
516 int n_global_fp_regs
;
518 /* True if the current function is leaf and uses only leaf regs,
519 so that the SPARC leaf function optimization can be applied.
520 Private version of crtl->uses_only_leaf_regs, see
521 sparc_expand_prologue for the rationale. */
524 /* True if the prologue saves local or in registers. */
525 bool save_local_in_regs_p
;
527 /* True if the data calculated by sparc_expand_prologue are valid. */
528 bool prologue_data_valid_p
;
531 #define sparc_frame_size cfun->machine->frame_size
532 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
533 #define sparc_frame_base_reg cfun->machine->frame_base_reg
534 #define sparc_frame_base_offset cfun->machine->frame_base_offset
535 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
536 #define sparc_leaf_function_p cfun->machine->leaf_function_p
537 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
538 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
540 /* 1 if the next opcode is to be specially indented. */
541 int sparc_indent_opcode
= 0;
543 static void sparc_option_override (void);
544 static void sparc_init_modes (void);
545 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
546 const_tree
, bool, bool, int *, int *);
548 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
549 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
551 static void sparc_emit_set_const32 (rtx
, rtx
);
552 static void sparc_emit_set_const64 (rtx
, rtx
);
553 static void sparc_output_addr_vec (rtx
);
554 static void sparc_output_addr_diff_vec (rtx
);
555 static void sparc_output_deferred_case_vectors (void);
556 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
557 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
558 static rtx
sparc_builtin_saveregs (void);
559 static int epilogue_renumber (rtx
*, int);
560 static bool sparc_assemble_integer (rtx
, unsigned int, int);
561 static int set_extends (rtx_insn
*);
562 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
563 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
564 #ifdef TARGET_SOLARIS
565 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
566 tree
) ATTRIBUTE_UNUSED
;
568 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
569 static int sparc_issue_rate (void);
570 static void sparc_sched_init (FILE *, int, int);
571 static int sparc_use_sched_lookahead (void);
573 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
574 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
575 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
576 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
577 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
579 static bool sparc_function_ok_for_sibcall (tree
, tree
);
580 static void sparc_init_libfuncs (void);
581 static void sparc_init_builtins (void);
582 static void sparc_fpu_init_builtins (void);
583 static void sparc_vis_init_builtins (void);
584 static tree
sparc_builtin_decl (unsigned, bool);
585 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
586 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
587 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
588 HOST_WIDE_INT
, tree
);
589 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
590 HOST_WIDE_INT
, const_tree
);
591 static struct machine_function
* sparc_init_machine_status (void);
592 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
593 static rtx
sparc_tls_get_addr (void);
594 static rtx
sparc_tls_got (void);
595 static int sparc_register_move_cost (machine_mode
,
596 reg_class_t
, reg_class_t
);
597 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
598 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
599 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
600 static bool sparc_function_value_regno_p (const unsigned int);
601 static rtx
sparc_struct_value_rtx (tree
, int);
602 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
603 int *, const_tree
, int);
604 static bool sparc_return_in_memory (const_tree
, const_tree
);
605 static bool sparc_strict_argument_naming (cumulative_args_t
);
606 static void sparc_va_start (tree
, rtx
);
607 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
608 static bool sparc_vector_mode_supported_p (machine_mode
);
609 static bool sparc_tls_referenced_p (rtx
);
610 static rtx
sparc_legitimize_tls_address (rtx
);
611 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
612 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
613 static rtx
sparc_delegitimize_address (rtx
);
614 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
615 static bool sparc_pass_by_reference (cumulative_args_t
,
616 machine_mode
, const_tree
, bool);
617 static void sparc_function_arg_advance (cumulative_args_t
,
618 machine_mode
, const_tree
, bool);
619 static rtx
sparc_function_arg_1 (cumulative_args_t
,
620 machine_mode
, const_tree
, bool, bool);
621 static rtx
sparc_function_arg (cumulative_args_t
,
622 machine_mode
, const_tree
, bool);
623 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
624 machine_mode
, const_tree
, bool);
625 static unsigned int sparc_function_arg_boundary (machine_mode
,
627 static int sparc_arg_partial_bytes (cumulative_args_t
,
628 machine_mode
, tree
, bool);
629 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
630 static void sparc_file_end (void);
631 static bool sparc_frame_pointer_required (void);
632 static bool sparc_can_eliminate (const int, const int);
633 static rtx
sparc_builtin_setjmp_frame_value (void);
634 static void sparc_conditional_register_usage (void);
635 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
636 static const char *sparc_mangle_type (const_tree
);
638 static void sparc_trampoline_init (rtx
, tree
, rtx
);
639 static machine_mode
sparc_preferred_simd_mode (machine_mode
);
640 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
641 static bool sparc_print_operand_punct_valid_p (unsigned char);
642 static void sparc_print_operand (FILE *, rtx
, int);
643 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
644 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
646 secondary_reload_info
*);
647 static machine_mode
sparc_cstore_mode (enum insn_code icode
);
648 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
650 #ifdef SUBTARGET_ATTRIBUTE_TABLE
651 /* Table of valid machine attributes. */
652 static const struct attribute_spec sparc_attribute_table
[] =
654 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
656 SUBTARGET_ATTRIBUTE_TABLE
,
657 { NULL
, 0, 0, false, false, false, NULL
, false }
661 /* Option handling. */
664 enum cmodel sparc_cmodel
;
666 char sparc_hard_reg_printed
[8];
668 /* Initialize the GCC target structure. */
670 /* The default is to use .half rather than .short for aligned HI objects. */
671 #undef TARGET_ASM_ALIGNED_HI_OP
672 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
674 #undef TARGET_ASM_UNALIGNED_HI_OP
675 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
676 #undef TARGET_ASM_UNALIGNED_SI_OP
677 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
678 #undef TARGET_ASM_UNALIGNED_DI_OP
679 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
681 /* The target hook has to handle DI-mode values. */
682 #undef TARGET_ASM_INTEGER
683 #define TARGET_ASM_INTEGER sparc_assemble_integer
685 #undef TARGET_ASM_FUNCTION_PROLOGUE
686 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
687 #undef TARGET_ASM_FUNCTION_EPILOGUE
688 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
690 #undef TARGET_SCHED_ADJUST_COST
691 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
692 #undef TARGET_SCHED_ISSUE_RATE
693 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
694 #undef TARGET_SCHED_INIT
695 #define TARGET_SCHED_INIT sparc_sched_init
696 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
697 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
699 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
700 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
702 #undef TARGET_INIT_LIBFUNCS
703 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
705 #undef TARGET_LEGITIMIZE_ADDRESS
706 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
707 #undef TARGET_DELEGITIMIZE_ADDRESS
708 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
709 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
710 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
712 #undef TARGET_INIT_BUILTINS
713 #define TARGET_INIT_BUILTINS sparc_init_builtins
714 #undef TARGET_BUILTIN_DECL
715 #define TARGET_BUILTIN_DECL sparc_builtin_decl
716 #undef TARGET_EXPAND_BUILTIN
717 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
718 #undef TARGET_FOLD_BUILTIN
719 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
722 #undef TARGET_HAVE_TLS
723 #define TARGET_HAVE_TLS true
726 #undef TARGET_CANNOT_FORCE_CONST_MEM
727 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
729 #undef TARGET_ASM_OUTPUT_MI_THUNK
730 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
731 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
732 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
734 #undef TARGET_RTX_COSTS
735 #define TARGET_RTX_COSTS sparc_rtx_costs
736 #undef TARGET_ADDRESS_COST
737 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
738 #undef TARGET_REGISTER_MOVE_COST
739 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
741 #undef TARGET_PROMOTE_FUNCTION_MODE
742 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
744 #undef TARGET_FUNCTION_VALUE
745 #define TARGET_FUNCTION_VALUE sparc_function_value
746 #undef TARGET_LIBCALL_VALUE
747 #define TARGET_LIBCALL_VALUE sparc_libcall_value
748 #undef TARGET_FUNCTION_VALUE_REGNO_P
749 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
751 #undef TARGET_STRUCT_VALUE_RTX
752 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
753 #undef TARGET_RETURN_IN_MEMORY
754 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
755 #undef TARGET_MUST_PASS_IN_STACK
756 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
757 #undef TARGET_PASS_BY_REFERENCE
758 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
759 #undef TARGET_ARG_PARTIAL_BYTES
760 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
761 #undef TARGET_FUNCTION_ARG_ADVANCE
762 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
763 #undef TARGET_FUNCTION_ARG
764 #define TARGET_FUNCTION_ARG sparc_function_arg
765 #undef TARGET_FUNCTION_INCOMING_ARG
766 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
767 #undef TARGET_FUNCTION_ARG_BOUNDARY
768 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
770 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
771 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
772 #undef TARGET_STRICT_ARGUMENT_NAMING
773 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
775 #undef TARGET_EXPAND_BUILTIN_VA_START
776 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
777 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
778 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
780 #undef TARGET_VECTOR_MODE_SUPPORTED_P
781 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
783 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
784 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
786 #ifdef SUBTARGET_INSERT_ATTRIBUTES
787 #undef TARGET_INSERT_ATTRIBUTES
788 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
791 #ifdef SUBTARGET_ATTRIBUTE_TABLE
792 #undef TARGET_ATTRIBUTE_TABLE
793 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
796 #undef TARGET_OPTION_OVERRIDE
797 #define TARGET_OPTION_OVERRIDE sparc_option_override
799 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
800 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
801 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
804 #undef TARGET_ASM_FILE_END
805 #define TARGET_ASM_FILE_END sparc_file_end
807 #undef TARGET_FRAME_POINTER_REQUIRED
808 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
810 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
811 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
813 #undef TARGET_CAN_ELIMINATE
814 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
816 #undef TARGET_PREFERRED_RELOAD_CLASS
817 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
819 #undef TARGET_SECONDARY_RELOAD
820 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
822 #undef TARGET_CONDITIONAL_REGISTER_USAGE
823 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
825 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
826 #undef TARGET_MANGLE_TYPE
827 #define TARGET_MANGLE_TYPE sparc_mangle_type
830 #undef TARGET_LEGITIMATE_ADDRESS_P
831 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
833 #undef TARGET_LEGITIMATE_CONSTANT_P
834 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
836 #undef TARGET_TRAMPOLINE_INIT
837 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
839 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
840 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
841 #undef TARGET_PRINT_OPERAND
842 #define TARGET_PRINT_OPERAND sparc_print_operand
843 #undef TARGET_PRINT_OPERAND_ADDRESS
844 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
846 /* The value stored by LDSTUB. */
847 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
848 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
850 #undef TARGET_CSTORE_MODE
851 #define TARGET_CSTORE_MODE sparc_cstore_mode
853 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
854 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
856 struct gcc_target targetm
= TARGET_INITIALIZER
;
858 /* Return the memory reference contained in X if any, zero otherwise. */
863 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
872 /* We use a machine specific pass to enable workarounds for errata.
873 We need to have the (essentially) final form of the insn stream in order
874 to properly detect the various hazards. Therefore, this machine specific
875 pass runs as late as possible. The pass is inserted in the pass pipeline
876 at the end of sparc_option_override. */
879 sparc_do_work_around_errata (void)
881 rtx_insn
*insn
, *next
;
883 /* Force all instructions to be split into their final form. */
884 split_all_insns_noflow ();
886 /* Now look for specific patterns in the insn stream. */
887 for (insn
= get_insns (); insn
; insn
= next
)
889 bool insert_nop
= false;
892 /* Look into the instruction in a delay slot. */
893 if (NONJUMP_INSN_P (insn
))
894 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
895 insn
= seq
->insn (1);
897 /* Look for a single-word load into an odd-numbered FP register. */
899 && NONJUMP_INSN_P (insn
)
900 && (set
= single_set (insn
)) != NULL_RTX
901 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
902 && MEM_P (SET_SRC (set
))
903 && REG_P (SET_DEST (set
))
904 && REGNO (SET_DEST (set
)) > 31
905 && REGNO (SET_DEST (set
)) % 2 != 0)
907 /* The wrong dependency is on the enclosing double register. */
908 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
909 unsigned int src1
, src2
, dest
;
912 next
= next_active_insn (insn
);
915 /* If the insn is a branch, then it cannot be problematic. */
916 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
920 code
= INSN_CODE (next
);
924 case CODE_FOR_adddf3
:
925 case CODE_FOR_subdf3
:
926 case CODE_FOR_muldf3
:
927 case CODE_FOR_divdf3
:
928 dest
= REGNO (recog_data
.operand
[0]);
929 src1
= REGNO (recog_data
.operand
[1]);
930 src2
= REGNO (recog_data
.operand
[2]);
935 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
936 if ((src1
== x
|| src2
== x
)
937 && (dest
== src1
|| dest
== src2
))
944 FPOPd %fx, %fx, %fx */
947 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
952 case CODE_FOR_sqrtdf2
:
953 dest
= REGNO (recog_data
.operand
[0]);
954 src1
= REGNO (recog_data
.operand
[1]);
958 if (src1
== x
&& dest
== src1
)
967 /* Look for a single-word load into an integer register. */
968 else if (sparc_fix_ut699
969 && NONJUMP_INSN_P (insn
)
970 && (set
= single_set (insn
)) != NULL_RTX
971 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
972 && mem_ref (SET_SRC (set
)) != NULL_RTX
973 && REG_P (SET_DEST (set
))
974 && REGNO (SET_DEST (set
)) < 32)
976 /* There is no problem if the second memory access has a data
977 dependency on the first single-cycle load. */
978 rtx x
= SET_DEST (set
);
980 next
= next_active_insn (insn
);
983 /* If the insn is a branch, then it cannot be problematic. */
984 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
987 /* Look for a second memory access to/from an integer register. */
988 if ((set
= single_set (next
)) != NULL_RTX
)
990 rtx src
= SET_SRC (set
);
991 rtx dest
= SET_DEST (set
);
994 /* LDD is affected. */
995 if ((mem
= mem_ref (src
)) != NULL_RTX
998 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1001 /* STD is *not* affected. */
1002 else if (MEM_P (dest
)
1003 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1004 && (src
== CONST0_RTX (GET_MODE (dest
))
1007 && REGNO (src
) != REGNO (x
)))
1008 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1013 /* Look for a single-word load/operation into an FP register. */
1014 else if (sparc_fix_ut699
1015 && NONJUMP_INSN_P (insn
)
1016 && (set
= single_set (insn
)) != NULL_RTX
1017 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1018 && REG_P (SET_DEST (set
))
1019 && REGNO (SET_DEST (set
)) > 31)
1021 /* Number of instructions in the problematic window. */
1022 const int n_insns
= 4;
1023 /* The problematic combination is with the sibling FP register. */
1024 const unsigned int x
= REGNO (SET_DEST (set
));
1025 const unsigned int y
= x
^ 1;
1029 next
= next_active_insn (insn
);
1032 /* If the insn is a branch, then it cannot be problematic. */
1033 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1036 /* Look for a second load/operation into the sibling FP register. */
1037 if (!((set
= single_set (next
)) != NULL_RTX
1038 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1039 && REG_P (SET_DEST (set
))
1040 && REGNO (SET_DEST (set
)) == y
))
1043 /* Look for a (possible) store from the FP register in the next N
1044 instructions, but bail out if it is again modified or if there
1045 is a store from the sibling FP register before this store. */
1046 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1050 after
= next_active_insn (after
);
1054 /* This is a branch with an empty delay slot. */
1055 if (!NONJUMP_INSN_P (after
))
1062 /* This is a branch with a filled delay slot. */
1063 else if (rtx_sequence
*seq
=
1064 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1069 after
= seq
->insn (1);
1071 /* This is a regular instruction. */
1075 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1077 const rtx src
= SET_SRC (set
);
1078 const rtx dest
= SET_DEST (set
);
1079 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1081 /* If the FP register is again modified before the store,
1082 then the store isn't affected. */
1084 && (REGNO (dest
) == x
1085 || (REGNO (dest
) == y
&& size
== 8)))
1088 if (MEM_P (dest
) && REG_P (src
))
1090 /* If there is a store from the sibling FP register
1091 before the store, then the store is not affected. */
1092 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1095 /* Otherwise, the store is affected. */
1096 if (REGNO (src
) == x
&& size
== 4)
1104 /* If we have a branch in the first M instructions, then we
1105 cannot see the (M+2)th instruction so we play safe. */
1106 if (branch_p
&& i
<= (n_insns
- 2))
1115 next
= NEXT_INSN (insn
);
1118 emit_insn_before (gen_nop (), next
);
1126 const pass_data pass_data_work_around_errata
=
1128 RTL_PASS
, /* type */
1129 "errata", /* name */
1130 OPTGROUP_NONE
, /* optinfo_flags */
1131 TV_MACH_DEP
, /* tv_id */
1132 0, /* properties_required */
1133 0, /* properties_provided */
1134 0, /* properties_destroyed */
1135 0, /* todo_flags_start */
1136 0, /* todo_flags_finish */
1139 class pass_work_around_errata
: public rtl_opt_pass
1142 pass_work_around_errata(gcc::context
*ctxt
)
1143 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1146 /* opt_pass methods: */
1147 virtual bool gate (function
*)
1149 /* The only errata we handle are those of the AT697F and UT699. */
1150 return sparc_fix_at697f
!= 0 || sparc_fix_ut699
!= 0;
1153 virtual unsigned int execute (function
*)
1155 return sparc_do_work_around_errata ();
1158 }; // class pass_work_around_errata
1163 make_pass_work_around_errata (gcc::context
*ctxt
)
1165 return new pass_work_around_errata (ctxt
);
1168 /* Helpers for TARGET_DEBUG_OPTIONS. */
1170 dump_target_flag_bits (const int flags
)
1172 if (flags
& MASK_64BIT
)
1173 fprintf (stderr
, "64BIT ");
1174 if (flags
& MASK_APP_REGS
)
1175 fprintf (stderr
, "APP_REGS ");
1176 if (flags
& MASK_FASTER_STRUCTS
)
1177 fprintf (stderr
, "FASTER_STRUCTS ");
1178 if (flags
& MASK_FLAT
)
1179 fprintf (stderr
, "FLAT ");
1180 if (flags
& MASK_FMAF
)
1181 fprintf (stderr
, "FMAF ");
1182 if (flags
& MASK_FPU
)
1183 fprintf (stderr
, "FPU ");
1184 if (flags
& MASK_HARD_QUAD
)
1185 fprintf (stderr
, "HARD_QUAD ");
1186 if (flags
& MASK_POPC
)
1187 fprintf (stderr
, "POPC ");
1188 if (flags
& MASK_PTR64
)
1189 fprintf (stderr
, "PTR64 ");
1190 if (flags
& MASK_STACK_BIAS
)
1191 fprintf (stderr
, "STACK_BIAS ");
1192 if (flags
& MASK_UNALIGNED_DOUBLES
)
1193 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1194 if (flags
& MASK_V8PLUS
)
1195 fprintf (stderr
, "V8PLUS ");
1196 if (flags
& MASK_VIS
)
1197 fprintf (stderr
, "VIS ");
1198 if (flags
& MASK_VIS2
)
1199 fprintf (stderr
, "VIS2 ");
1200 if (flags
& MASK_VIS3
)
1201 fprintf (stderr
, "VIS3 ");
1202 if (flags
& MASK_VIS4
)
1203 fprintf (stderr
, "VIS4 ");
1204 if (flags
& MASK_CBCOND
)
1205 fprintf (stderr
, "CBCOND ");
1206 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1207 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1208 if (flags
& MASK_SPARCLET
)
1209 fprintf (stderr
, "SPARCLET ");
1210 if (flags
& MASK_SPARCLITE
)
1211 fprintf (stderr
, "SPARCLITE ");
1212 if (flags
& MASK_V8
)
1213 fprintf (stderr
, "V8 ");
1214 if (flags
& MASK_V9
)
1215 fprintf (stderr
, "V9 ");
1219 dump_target_flags (const char *prefix
, const int flags
)
1221 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1222 dump_target_flag_bits (flags
);
1223 fprintf(stderr
, "]\n");
1226 /* Validate and override various options, and do some machine dependent
1230 sparc_option_override (void)
1232 static struct code_model
{
1233 const char *const name
;
1234 const enum cmodel value
;
1235 } const cmodels
[] = {
1237 { "medlow", CM_MEDLOW
},
1238 { "medmid", CM_MEDMID
},
1239 { "medany", CM_MEDANY
},
1240 { "embmedany", CM_EMBMEDANY
},
1241 { NULL
, (enum cmodel
) 0 }
1243 const struct code_model
*cmodel
;
1244 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1245 static struct cpu_default
{
1247 const enum processor_type processor
;
1248 } const cpu_default
[] = {
1249 /* There must be one entry here for each TARGET_CPU value. */
1250 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1251 { TARGET_CPU_v8
, PROCESSOR_V8
},
1252 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1253 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1254 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1255 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1256 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1257 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1258 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1259 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1260 { TARGET_CPU_v9
, PROCESSOR_V9
},
1261 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1262 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1263 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1264 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1265 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1266 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1267 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1268 { -1, PROCESSOR_V7
}
1270 const struct cpu_default
*def
;
1271 /* Table of values for -m{cpu,tune}=. This must match the order of
1272 the enum processor_type in sparc-opts.h. */
1273 static struct cpu_table
{
1274 const char *const name
;
1277 } const cpu_table
[] = {
1278 { "v7", MASK_ISA
, 0 },
1279 { "cypress", MASK_ISA
, 0 },
1280 { "v8", MASK_ISA
, MASK_V8
},
1281 /* TI TMS390Z55 supersparc */
1282 { "supersparc", MASK_ISA
, MASK_V8
},
1283 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
1284 { "leon", MASK_ISA
, MASK_V8
|MASK_LEON
|MASK_FPU
},
1285 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
|MASK_FPU
},
1286 { "leon3v7", MASK_ISA
, MASK_LEON3
|MASK_FPU
},
1287 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1288 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1289 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1290 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1291 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
1292 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1293 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1294 /* TEMIC sparclet */
1295 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1296 { "v9", MASK_ISA
, MASK_V9
},
1297 /* UltraSPARC I, II, IIi */
1298 { "ultrasparc", MASK_ISA
,
1299 /* Although insns using %y are deprecated, it is a clear win. */
1300 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1301 /* UltraSPARC III */
1302 /* ??? Check if %y issue still holds true. */
1303 { "ultrasparc3", MASK_ISA
,
1304 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1306 { "niagara", MASK_ISA
,
1307 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1309 { "niagara2", MASK_ISA
,
1310 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1312 { "niagara3", MASK_ISA
,
1313 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
1315 { "niagara4", MASK_ISA
,
1316 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1318 { "niagara7", MASK_ISA
,
1319 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
},
1321 const struct cpu_table
*cpu
;
1325 if (sparc_debug_string
!= NULL
)
1330 p
= ASTRDUP (sparc_debug_string
);
1331 while ((q
= strtok (p
, ",")) != NULL
)
1345 if (! strcmp (q
, "all"))
1346 mask
= MASK_DEBUG_ALL
;
1347 else if (! strcmp (q
, "options"))
1348 mask
= MASK_DEBUG_OPTIONS
;
1350 error ("unknown -mdebug-%s switch", q
);
1353 sparc_debug
&= ~mask
;
1355 sparc_debug
|= mask
;
1359 if (TARGET_DEBUG_OPTIONS
)
1361 dump_target_flags("Initial target_flags", target_flags
);
1362 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1365 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1366 SUBTARGET_OVERRIDE_OPTIONS
;
1369 #ifndef SPARC_BI_ARCH
1370 /* Check for unsupported architecture size. */
1371 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1372 error ("%s is not supported by this configuration",
1373 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1376 /* We force all 64bit archs to use 128 bit long double */
1377 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
1379 error ("-mlong-double-64 not allowed with -m64");
1380 target_flags
|= MASK_LONG_DOUBLE_128
;
1383 /* Code model selection. */
1384 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1386 #ifdef SPARC_BI_ARCH
1388 sparc_cmodel
= CM_32
;
1391 if (sparc_cmodel_string
!= NULL
)
1395 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1396 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1398 if (cmodel
->name
== NULL
)
1399 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1401 sparc_cmodel
= cmodel
->value
;
1404 error ("-mcmodel= is not supported on 32 bit systems");
1407 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1408 for (i
= 8; i
< 16; i
++)
1409 if (!call_used_regs
[i
])
1411 error ("-fcall-saved-REG is not supported for out registers");
1412 call_used_regs
[i
] = 1;
1415 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
1417 /* Set the default CPU. */
1418 if (!global_options_set
.x_sparc_cpu_and_features
)
1420 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1421 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1423 gcc_assert (def
->cpu
!= -1);
1424 sparc_cpu_and_features
= def
->processor
;
1427 if (!global_options_set
.x_sparc_cpu
)
1428 sparc_cpu
= sparc_cpu_and_features
;
1430 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1432 if (TARGET_DEBUG_OPTIONS
)
1434 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1435 fprintf (stderr
, "sparc_cpu: %s\n",
1436 cpu_table
[(int) sparc_cpu
].name
);
1437 dump_target_flags ("cpu->disable", cpu
->disable
);
1438 dump_target_flags ("cpu->enable", cpu
->enable
);
1441 target_flags
&= ~cpu
->disable
;
1442 target_flags
|= (cpu
->enable
1443 #ifndef HAVE_AS_FMAF_HPC_VIS3
1444 & ~(MASK_FMAF
| MASK_VIS3
)
1446 #ifndef HAVE_AS_SPARC4
1449 #ifndef HAVE_AS_SPARC5_VIS4
1452 #ifndef HAVE_AS_LEON
1453 & ~(MASK_LEON
| MASK_LEON3
)
1457 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1458 the processor default. */
1459 if (target_flags_explicit
& MASK_FPU
)
1460 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
1462 /* -mvis2 implies -mvis */
1464 target_flags
|= MASK_VIS
;
1466 /* -mvis3 implies -mvis2 and -mvis */
1468 target_flags
|= MASK_VIS2
| MASK_VIS
;
1470 /* -mvis4 implies -mvis3, -mvis2 and -mvis */
1472 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1474 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4 or -mfmaf if FPU is
1477 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1480 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1482 -m64 also implies v9. */
1483 if (TARGET_VIS
|| TARGET_ARCH64
)
1485 target_flags
|= MASK_V9
;
1486 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1489 /* -mvis also implies -mv8plus on 32-bit */
1490 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1491 target_flags
|= MASK_V8PLUS
;
1493 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1494 if (TARGET_V9
&& TARGET_ARCH32
)
1495 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1497 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1498 if (! TARGET_V9
|| TARGET_ARCH64
)
1499 target_flags
&= ~MASK_V8PLUS
;
1501 /* Don't use stack biasing in 32 bit mode. */
1503 target_flags
&= ~MASK_STACK_BIAS
;
1505 /* Supply a default value for align_functions. */
1506 if (align_functions
== 0
1507 && (sparc_cpu
== PROCESSOR_ULTRASPARC
1508 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1509 || sparc_cpu
== PROCESSOR_NIAGARA
1510 || sparc_cpu
== PROCESSOR_NIAGARA2
1511 || sparc_cpu
== PROCESSOR_NIAGARA3
1512 || sparc_cpu
== PROCESSOR_NIAGARA4
1513 || sparc_cpu
== PROCESSOR_NIAGARA7
))
1514 align_functions
= 32;
1516 /* Validate PCC_STRUCT_RETURN. */
1517 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1518 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1520 /* Only use .uaxword when compiling for a 64-bit target. */
1522 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1524 /* Do various machine dependent initializations. */
1525 sparc_init_modes ();
1527 /* Set up function hooks. */
1528 init_machine_status
= sparc_init_machine_status
;
1533 case PROCESSOR_CYPRESS
:
1534 sparc_costs
= &cypress_costs
;
1537 case PROCESSOR_SPARCLITE
:
1538 case PROCESSOR_SUPERSPARC
:
1539 sparc_costs
= &supersparc_costs
;
1541 case PROCESSOR_F930
:
1542 case PROCESSOR_F934
:
1543 case PROCESSOR_HYPERSPARC
:
1544 case PROCESSOR_SPARCLITE86X
:
1545 sparc_costs
= &hypersparc_costs
;
1547 case PROCESSOR_LEON
:
1548 sparc_costs
= &leon_costs
;
1550 case PROCESSOR_LEON3
:
1551 case PROCESSOR_LEON3V7
:
1552 sparc_costs
= &leon3_costs
;
1554 case PROCESSOR_SPARCLET
:
1555 case PROCESSOR_TSC701
:
1556 sparc_costs
= &sparclet_costs
;
1559 case PROCESSOR_ULTRASPARC
:
1560 sparc_costs
= &ultrasparc_costs
;
1562 case PROCESSOR_ULTRASPARC3
:
1563 sparc_costs
= &ultrasparc3_costs
;
1565 case PROCESSOR_NIAGARA
:
1566 sparc_costs
= &niagara_costs
;
1568 case PROCESSOR_NIAGARA2
:
1569 sparc_costs
= &niagara2_costs
;
1571 case PROCESSOR_NIAGARA3
:
1572 sparc_costs
= &niagara3_costs
;
1574 case PROCESSOR_NIAGARA4
:
1575 sparc_costs
= &niagara4_costs
;
1577 case PROCESSOR_NIAGARA7
:
1578 sparc_costs
= &niagara7_costs
;
1580 case PROCESSOR_NATIVE
:
1584 if (sparc_memory_model
== SMM_DEFAULT
)
1586 /* Choose the memory model for the operating system. */
1587 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1588 if (os_default
!= SMM_DEFAULT
)
1589 sparc_memory_model
= os_default
;
1590 /* Choose the most relaxed model for the processor. */
1592 sparc_memory_model
= SMM_RMO
;
1593 else if (TARGET_LEON3
)
1594 sparc_memory_model
= SMM_TSO
;
1595 else if (TARGET_LEON
)
1596 sparc_memory_model
= SMM_SC
;
1598 sparc_memory_model
= SMM_PSO
;
1600 sparc_memory_model
= SMM_SC
;
1603 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1604 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1605 target_flags
|= MASK_LONG_DOUBLE_128
;
1608 if (TARGET_DEBUG_OPTIONS
)
1609 dump_target_flags ("Final target_flags", target_flags
);
1611 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
1612 can run at the same time. More important, it is the threshold
1613 defining when additional prefetches will be dropped by the
1616 The UltraSPARC-III features a documented prefetch queue with a
1617 size of 8. Additional prefetches issued in the cpu are
1620 Niagara processors are different. In these processors prefetches
1621 are handled much like regular loads. The L1 miss buffer is 32
1622 entries, but prefetches start getting affected when 30 entries
1623 become occupied. That occupation could be a mix of regular loads
1624 and prefetches though. And that buffer is shared by all threads.
1625 Once the threshold is reached, if the core is running a single
1626 thread the prefetch will retry. If more than one thread is
1627 running, the prefetch will be dropped.
1629 All this makes it very difficult to determine how many
1630 simultaneous prefetches can be issued simultaneously, even in a
1631 single-threaded program. Experimental results show that setting
1632 this parameter to 32 works well when the number of threads is not
1634 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1635 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1636 || sparc_cpu
== PROCESSOR_NIAGARA
1637 || sparc_cpu
== PROCESSOR_NIAGARA2
1638 || sparc_cpu
== PROCESSOR_NIAGARA3
1639 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1641 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1642 ? 8 : (sparc_cpu
== PROCESSOR_NIAGARA7
1644 global_options
.x_param_values
,
1645 global_options_set
.x_param_values
);
1647 /* For PARAM_L1_CACHE_LINE_SIZE we use the default 32 bytes (see
1648 params.def), so no maybe_set_param_value is needed.
1650 The Oracle SPARC Architecture (previously the UltraSPARC
1651 Architecture) specification states that when a PREFETCH[A]
1652 instruction is executed an implementation-specific amount of data
1653 is prefetched, and that it is at least 64 bytes long (aligned to
1656 However, this is not correct. The M7 (and implementations prior
1657 to that) does not guarantee a 64B prefetch into a cache if the
1658 line size is smaller. A single cache line is all that is ever
1659 prefetched. So for the M7, where the L1D$ has 32B lines and the
1660 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
1661 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
1662 is a read_n prefetch, which is the only type which allocates to
1665 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
1666 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
1667 Niagara processors feature a L1D$ of 16KB. */
1668 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
1669 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1670 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1671 || sparc_cpu
== PROCESSOR_NIAGARA
1672 || sparc_cpu
== PROCESSOR_NIAGARA2
1673 || sparc_cpu
== PROCESSOR_NIAGARA3
1674 || sparc_cpu
== PROCESSOR_NIAGARA4
1675 || sparc_cpu
== PROCESSOR_NIAGARA7
)
1677 global_options
.x_param_values
,
1678 global_options_set
.x_param_values
);
1681 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
1682 that 512 is the default in params.def. */
1683 maybe_set_param_value (PARAM_L2_CACHE_SIZE
,
1684 (sparc_cpu
== PROCESSOR_NIAGARA4
1685 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
1687 global_options
.x_param_values
,
1688 global_options_set
.x_param_values
);
1691 /* Disable save slot sharing for call-clobbered registers by default.
1692 The IRA sharing algorithm works on single registers only and this
1693 pessimizes for double floating-point registers. */
1694 if (!global_options_set
.x_flag_ira_share_save_slots
)
1695 flag_ira_share_save_slots
= 0;
1697 /* We register a machine specific pass to work around errata, if any.
1698 The pass mut be scheduled as late as possible so that we have the
1699 (essentially) final form of the insn stream to work on.
1700 Registering the pass must be done at start up. It's convenient to
1702 opt_pass
*errata_pass
= make_pass_work_around_errata (g
);
1703 struct register_pass_info insert_pass_work_around_errata
=
1705 errata_pass
, /* pass */
1706 "dbr", /* reference_pass_name */
1707 1, /* ref_pass_instance_number */
1708 PASS_POS_INSERT_AFTER
/* po_op */
1710 register_pass (&insert_pass_work_around_errata
);
1713 /* Miscellaneous utilities. */
1715 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1716 or branch on register contents instructions. */
1719 v9_regcmp_p (enum rtx_code code
)
1721 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1722 || code
== LE
|| code
== GT
);
1725 /* Nonzero if OP is a floating point constant which can
1726 be loaded into an integer register using a single
1727 sethi instruction. */
1732 if (GET_CODE (op
) == CONST_DOUBLE
)
1736 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1737 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1743 /* Nonzero if OP is a floating point constant which can
1744 be loaded into an integer register using a single
1750 if (GET_CODE (op
) == CONST_DOUBLE
)
1754 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1755 return SPARC_SIMM13_P (i
);
1761 /* Nonzero if OP is a floating point constant which can
1762 be loaded into an integer register using a high/losum
1763 instruction sequence. */
1766 fp_high_losum_p (rtx op
)
1768 /* The constraints calling this should only be in
1769 SFmode move insns, so any constant which cannot
1770 be moved using a single insn will do. */
1771 if (GET_CODE (op
) == CONST_DOUBLE
)
1775 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1776 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1782 /* Return true if the address of LABEL can be loaded by means of the
1783 mov{si,di}_pic_label_ref patterns in PIC mode. */
1786 can_use_mov_pic_label_ref (rtx label
)
1788 /* VxWorks does not impose a fixed gap between segments; the run-time
1789 gap can be different from the object-file gap. We therefore can't
1790 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1791 are absolutely sure that X is in the same segment as the GOT.
1792 Unfortunately, the flexibility of linker scripts means that we
1793 can't be sure of that in general, so assume that GOT-relative
1794 accesses are never valid on VxWorks. */
1795 if (TARGET_VXWORKS_RTP
)
1798 /* Similarly, if the label is non-local, it might end up being placed
1799 in a different section than the current one; now mov_pic_label_ref
1800 requires the label and the code to be in the same section. */
1801 if (LABEL_REF_NONLOCAL_P (label
))
1804 /* Finally, if we are reordering basic blocks and partition into hot
1805 and cold sections, this might happen for any label. */
1806 if (flag_reorder_blocks_and_partition
)
1812 /* Expand a move instruction. Return true if all work is done. */
1815 sparc_expand_move (machine_mode mode
, rtx
*operands
)
1817 /* Handle sets of MEM first. */
1818 if (GET_CODE (operands
[0]) == MEM
)
1820 /* 0 is a register (or a pair of registers) on SPARC. */
1821 if (register_or_zero_operand (operands
[1], mode
))
1824 if (!reload_in_progress
)
1826 operands
[0] = validize_mem (operands
[0]);
1827 operands
[1] = force_reg (mode
, operands
[1]);
1831 /* Fixup TLS cases. */
1833 && CONSTANT_P (operands
[1])
1834 && sparc_tls_referenced_p (operands
[1]))
1836 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1840 /* Fixup PIC cases. */
1841 if (flag_pic
&& CONSTANT_P (operands
[1]))
1843 if (pic_address_needs_scratch (operands
[1]))
1844 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1846 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1847 if (GET_CODE (operands
[1]) == LABEL_REF
1848 && can_use_mov_pic_label_ref (operands
[1]))
1852 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1858 gcc_assert (TARGET_ARCH64
);
1859 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1864 if (symbolic_operand (operands
[1], mode
))
1867 = sparc_legitimize_pic_address (operands
[1],
1869 ? operands
[0] : NULL_RTX
);
1874 /* If we are trying to toss an integer constant into FP registers,
1875 or loading a FP or vector constant, force it into memory. */
1876 if (CONSTANT_P (operands
[1])
1877 && REG_P (operands
[0])
1878 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1879 || SCALAR_FLOAT_MODE_P (mode
)
1880 || VECTOR_MODE_P (mode
)))
1882 /* emit_group_store will send such bogosity to us when it is
1883 not storing directly into memory. So fix this up to avoid
1884 crashes in output_constant_pool. */
1885 if (operands
[1] == const0_rtx
)
1886 operands
[1] = CONST0_RTX (mode
);
1888 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1889 always other regs. */
1890 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1891 && (const_zero_operand (operands
[1], mode
)
1892 || const_all_ones_operand (operands
[1], mode
)))
1895 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1896 /* We are able to build any SF constant in integer registers
1897 with at most 2 instructions. */
1899 /* And any DF constant in integer registers. */
1901 && ! can_create_pseudo_p ())))
1904 operands
[1] = force_const_mem (mode
, operands
[1]);
1905 if (!reload_in_progress
)
1906 operands
[1] = validize_mem (operands
[1]);
1910 /* Accept non-constants and valid constants unmodified. */
1911 if (!CONSTANT_P (operands
[1])
1912 || GET_CODE (operands
[1]) == HIGH
1913 || input_operand (operands
[1], mode
))
1919 /* All QImode constants require only one insn, so proceed. */
1924 sparc_emit_set_const32 (operands
[0], operands
[1]);
1928 /* input_operand should have filtered out 32-bit mode. */
1929 sparc_emit_set_const64 (operands
[0], operands
[1]);
1935 /* TImode isn't available in 32-bit mode. */
1936 split_double (operands
[1], &high
, &low
);
1937 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
1939 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
1951 /* Load OP1, a 32-bit constant, into OP0, a register.
1952 We know it can't be done in one insn when we get
1953 here, the move expander guarantees this. */
1956 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1958 machine_mode mode
= GET_MODE (op0
);
1961 if (can_create_pseudo_p ())
1962 temp
= gen_reg_rtx (mode
);
1964 if (GET_CODE (op1
) == CONST_INT
)
1966 gcc_assert (!small_int_operand (op1
, mode
)
1967 && !const_high_operand (op1
, mode
));
1969 /* Emit them as real moves instead of a HIGH/LO_SUM,
1970 this way CSE can see everything and reuse intermediate
1971 values if it wants. */
1972 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
1973 & ~(HOST_WIDE_INT
) 0x3ff)));
1975 emit_insn (gen_rtx_SET (op0
,
1976 gen_rtx_IOR (mode
, temp
,
1977 GEN_INT (INTVAL (op1
) & 0x3ff))));
1981 /* A symbol, emit in the traditional way. */
1982 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
1983 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1987 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1988 If TEMP is nonzero, we are forbidden to use any other scratch
1989 registers. Otherwise, we are allowed to generate them as needed.
1991 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1992 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1995 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1997 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
2000 if (temp
&& GET_MODE (temp
) == TImode
)
2003 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2006 /* SPARC-V9 code-model support. */
2007 switch (sparc_cmodel
)
2010 /* The range spanned by all instructions in the object is less
2011 than 2^31 bytes (2GB) and the distance from any instruction
2012 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2013 than 2^31 bytes (2GB).
2015 The executable must be in the low 4TB of the virtual address
2018 sethi %hi(symbol), %temp1
2019 or %temp1, %lo(symbol), %reg */
2021 temp1
= temp
; /* op0 is allowed. */
2023 temp1
= gen_reg_rtx (DImode
);
2025 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2026 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2030 /* The range spanned by all instructions in the object is less
2031 than 2^31 bytes (2GB) and the distance from any instruction
2032 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2033 than 2^31 bytes (2GB).
2035 The executable must be in the low 16TB of the virtual address
2038 sethi %h44(symbol), %temp1
2039 or %temp1, %m44(symbol), %temp2
2040 sllx %temp2, 12, %temp3
2041 or %temp3, %l44(symbol), %reg */
2046 temp3
= temp
; /* op0 is allowed. */
2050 temp1
= gen_reg_rtx (DImode
);
2051 temp2
= gen_reg_rtx (DImode
);
2052 temp3
= gen_reg_rtx (DImode
);
2055 emit_insn (gen_seth44 (temp1
, op1
));
2056 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2057 emit_insn (gen_rtx_SET (temp3
,
2058 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2059 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2063 /* The range spanned by all instructions in the object is less
2064 than 2^31 bytes (2GB) and the distance from any instruction
2065 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2066 than 2^31 bytes (2GB).
2068 The executable can be placed anywhere in the virtual address
2071 sethi %hh(symbol), %temp1
2072 sethi %lm(symbol), %temp2
2073 or %temp1, %hm(symbol), %temp3
2074 sllx %temp3, 32, %temp4
2075 or %temp4, %temp2, %temp5
2076 or %temp5, %lo(symbol), %reg */
2079 /* It is possible that one of the registers we got for operands[2]
2080 might coincide with that of operands[0] (which is why we made
2081 it TImode). Pick the other one to use as our scratch. */
2082 if (rtx_equal_p (temp
, op0
))
2084 gcc_assert (ti_temp
);
2085 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2088 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2095 temp1
= gen_reg_rtx (DImode
);
2096 temp2
= gen_reg_rtx (DImode
);
2097 temp3
= gen_reg_rtx (DImode
);
2098 temp4
= gen_reg_rtx (DImode
);
2099 temp5
= gen_reg_rtx (DImode
);
2102 emit_insn (gen_sethh (temp1
, op1
));
2103 emit_insn (gen_setlm (temp2
, op1
));
2104 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2105 emit_insn (gen_rtx_SET (temp4
,
2106 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2107 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2108 emit_insn (gen_setlo (op0
, temp5
, op1
));
2112 /* Old old old backwards compatibility kruft here.
2113 Essentially it is MEDLOW with a fixed 64-bit
2114 virtual base added to all data segment addresses.
2115 Text-segment stuff is computed like MEDANY, we can't
2116 reuse the code above because the relocation knobs
2119 Data segment: sethi %hi(symbol), %temp1
2120 add %temp1, EMBMEDANY_BASE_REG, %temp2
2121 or %temp2, %lo(symbol), %reg */
2122 if (data_segment_operand (op1
, GET_MODE (op1
)))
2126 temp1
= temp
; /* op0 is allowed. */
2131 temp1
= gen_reg_rtx (DImode
);
2132 temp2
= gen_reg_rtx (DImode
);
2135 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2136 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2137 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2140 /* Text segment: sethi %uhi(symbol), %temp1
2141 sethi %hi(symbol), %temp2
2142 or %temp1, %ulo(symbol), %temp3
2143 sllx %temp3, 32, %temp4
2144 or %temp4, %temp2, %temp5
2145 or %temp5, %lo(symbol), %reg */
2150 /* It is possible that one of the registers we got for operands[2]
2151 might coincide with that of operands[0] (which is why we made
2152 it TImode). Pick the other one to use as our scratch. */
2153 if (rtx_equal_p (temp
, op0
))
2155 gcc_assert (ti_temp
);
2156 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2159 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2166 temp1
= gen_reg_rtx (DImode
);
2167 temp2
= gen_reg_rtx (DImode
);
2168 temp3
= gen_reg_rtx (DImode
);
2169 temp4
= gen_reg_rtx (DImode
);
2170 temp5
= gen_reg_rtx (DImode
);
2173 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2174 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2175 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2176 emit_insn (gen_rtx_SET (temp4
,
2177 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2178 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2179 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2188 /* These avoid problems when cross compiling. If we do not
2189 go through all this hair then the optimizer will see
2190 invalid REG_EQUAL notes or in some cases none at all. */
2191 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2192 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2193 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2194 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2196 /* The optimizer is not to assume anything about exactly
2197 which bits are set for a HIGH, they are unspecified.
2198 Unfortunately this leads to many missed optimizations
2199 during CSE. We mask out the non-HIGH bits, and matches
2200 a plain movdi, to alleviate this problem. */
2202 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2204 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2208 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2210 return gen_rtx_SET (dest
, GEN_INT (val
));
2214 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2216 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2220 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2222 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2225 /* Worker routines for 64-bit constant formation on arch64.
2226 One of the key things to be doing in these emissions is
2227 to create as many temp REGs as possible. This makes it
2228 possible for half-built constants to be used later when
2229 such values are similar to something required later on.
2230 Without doing this, the optimizer cannot see such
2233 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2234 unsigned HOST_WIDE_INT
, int);
2237 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2238 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2240 unsigned HOST_WIDE_INT high_bits
;
2243 high_bits
= (~low_bits
) & 0xffffffff;
2245 high_bits
= low_bits
;
2247 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2250 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2254 /* If we are XOR'ing with -1, then we should emit a one's complement
2255 instead. This way the combiner will notice logical operations
2256 such as ANDN later on and substitute. */
2257 if ((low_bits
& 0x3ff) == 0x3ff)
2259 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2263 emit_insn (gen_rtx_SET (op0
,
2264 gen_safe_XOR64 (temp
,
2265 (-(HOST_WIDE_INT
)0x400
2266 | (low_bits
& 0x3ff)))));
2271 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2272 unsigned HOST_WIDE_INT
, int);
2275 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2276 unsigned HOST_WIDE_INT high_bits
,
2277 unsigned HOST_WIDE_INT low_immediate
,
2282 if ((high_bits
& 0xfffffc00) != 0)
2284 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2285 if ((high_bits
& ~0xfffffc00) != 0)
2286 emit_insn (gen_rtx_SET (op0
,
2287 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2293 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2297 /* Now shift it up into place. */
2298 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2299 GEN_INT (shift_count
))));
2301 /* If there is a low immediate part piece, finish up by
2302 putting that in as well. */
2303 if (low_immediate
!= 0)
2304 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2307 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2308 unsigned HOST_WIDE_INT
);
2310 /* Full 64-bit constant decomposition. Even though this is the
2311 'worst' case, we still optimize a few things away. */
2313 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2314 unsigned HOST_WIDE_INT high_bits
,
2315 unsigned HOST_WIDE_INT low_bits
)
2319 if (can_create_pseudo_p ())
2320 sub_temp
= gen_reg_rtx (DImode
);
2322 if ((high_bits
& 0xfffffc00) != 0)
2324 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2325 if ((high_bits
& ~0xfffffc00) != 0)
2326 emit_insn (gen_rtx_SET (sub_temp
,
2327 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2333 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2337 if (can_create_pseudo_p ())
2339 rtx temp2
= gen_reg_rtx (DImode
);
2340 rtx temp3
= gen_reg_rtx (DImode
);
2341 rtx temp4
= gen_reg_rtx (DImode
);
2343 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2346 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2347 if ((low_bits
& ~0xfffffc00) != 0)
2349 emit_insn (gen_rtx_SET (temp3
,
2350 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2351 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2355 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2360 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2361 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2362 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2365 /* We are in the middle of reload, so this is really
2366 painful. However we do still make an attempt to
2367 avoid emitting truly stupid code. */
2368 if (low1
!= const0_rtx
)
2370 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2371 GEN_INT (to_shift
))));
2372 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2380 if (low2
!= const0_rtx
)
2382 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2383 GEN_INT (to_shift
))));
2384 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2392 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2393 GEN_INT (to_shift
))));
2394 if (low3
!= const0_rtx
)
2395 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2400 /* Analyze a 64-bit constant for certain properties. */
2401 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2402 unsigned HOST_WIDE_INT
,
2403 int *, int *, int *);
2406 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2407 unsigned HOST_WIDE_INT low_bits
,
2408 int *hbsp
, int *lbsp
, int *abbasp
)
2410 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2413 lowest_bit_set
= highest_bit_set
= -1;
2417 if ((lowest_bit_set
== -1)
2418 && ((low_bits
>> i
) & 1))
2420 if ((highest_bit_set
== -1)
2421 && ((high_bits
>> (32 - i
- 1)) & 1))
2422 highest_bit_set
= (64 - i
- 1);
2425 && ((highest_bit_set
== -1)
2426 || (lowest_bit_set
== -1)));
2432 if ((lowest_bit_set
== -1)
2433 && ((high_bits
>> i
) & 1))
2434 lowest_bit_set
= i
+ 32;
2435 if ((highest_bit_set
== -1)
2436 && ((low_bits
>> (32 - i
- 1)) & 1))
2437 highest_bit_set
= 32 - i
- 1;
2440 && ((highest_bit_set
== -1)
2441 || (lowest_bit_set
== -1)));
2443 /* If there are no bits set this should have gone out
2444 as one instruction! */
2445 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2446 all_bits_between_are_set
= 1;
2447 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2451 if ((low_bits
& (1 << i
)) != 0)
2456 if ((high_bits
& (1 << (i
- 32))) != 0)
2459 all_bits_between_are_set
= 0;
2462 *hbsp
= highest_bit_set
;
2463 *lbsp
= lowest_bit_set
;
2464 *abbasp
= all_bits_between_are_set
;
2467 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2470 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2471 unsigned HOST_WIDE_INT low_bits
)
2473 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2476 || high_bits
== 0xffffffff)
2479 analyze_64bit_constant (high_bits
, low_bits
,
2480 &highest_bit_set
, &lowest_bit_set
,
2481 &all_bits_between_are_set
);
2483 if ((highest_bit_set
== 63
2484 || lowest_bit_set
== 0)
2485 && all_bits_between_are_set
!= 0)
2488 if ((highest_bit_set
- lowest_bit_set
) < 21)
2494 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2495 unsigned HOST_WIDE_INT
,
2498 static unsigned HOST_WIDE_INT
2499 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2500 unsigned HOST_WIDE_INT low_bits
,
2501 int lowest_bit_set
, int shift
)
2503 HOST_WIDE_INT hi
, lo
;
2505 if (lowest_bit_set
< 32)
2507 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2508 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2513 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2515 gcc_assert (! (hi
& lo
));
2519 /* Here we are sure to be arch64 and this is an integer constant
2520 being loaded into a register. Emit the most efficient
2521 insn sequence possible. Detection of all the 1-insn cases
2522 has been done already. */
2524 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2526 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2527 int lowest_bit_set
, highest_bit_set
;
2528 int all_bits_between_are_set
;
2531 /* Sanity check that we know what we are working with. */
2532 gcc_assert (TARGET_ARCH64
2533 && (GET_CODE (op0
) == SUBREG
2534 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2536 if (! can_create_pseudo_p ())
2539 if (GET_CODE (op1
) != CONST_INT
)
2541 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2546 temp
= gen_reg_rtx (DImode
);
2548 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2549 low_bits
= (INTVAL (op1
) & 0xffffffff);
2551 /* low_bits bits 0 --> 31
2552 high_bits bits 32 --> 63 */
2554 analyze_64bit_constant (high_bits
, low_bits
,
2555 &highest_bit_set
, &lowest_bit_set
,
2556 &all_bits_between_are_set
);
2558 /* First try for a 2-insn sequence. */
2560 /* These situations are preferred because the optimizer can
2561 * do more things with them:
2563 * sllx %reg, shift, %reg
2565 * srlx %reg, shift, %reg
2566 * 3) mov some_small_const, %reg
2567 * sllx %reg, shift, %reg
2569 if (((highest_bit_set
== 63
2570 || lowest_bit_set
== 0)
2571 && all_bits_between_are_set
!= 0)
2572 || ((highest_bit_set
- lowest_bit_set
) < 12))
2574 HOST_WIDE_INT the_const
= -1;
2575 int shift
= lowest_bit_set
;
2577 if ((highest_bit_set
!= 63
2578 && lowest_bit_set
!= 0)
2579 || all_bits_between_are_set
== 0)
2582 create_simple_focus_bits (high_bits
, low_bits
,
2585 else if (lowest_bit_set
== 0)
2586 shift
= -(63 - highest_bit_set
);
2588 gcc_assert (SPARC_SIMM13_P (the_const
));
2589 gcc_assert (shift
!= 0);
2591 emit_insn (gen_safe_SET64 (temp
, the_const
));
2593 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
2596 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
2597 GEN_INT (-shift
))));
2601 /* Now a range of 22 or less bits set somewhere.
2602 * 1) sethi %hi(focus_bits), %reg
2603 * sllx %reg, shift, %reg
2604 * 2) sethi %hi(focus_bits), %reg
2605 * srlx %reg, shift, %reg
2607 if ((highest_bit_set
- lowest_bit_set
) < 21)
2609 unsigned HOST_WIDE_INT focus_bits
=
2610 create_simple_focus_bits (high_bits
, low_bits
,
2611 lowest_bit_set
, 10);
2613 gcc_assert (SPARC_SETHI_P (focus_bits
));
2614 gcc_assert (lowest_bit_set
!= 10);
2616 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2618 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2619 if (lowest_bit_set
< 10)
2620 emit_insn (gen_rtx_SET (op0
,
2621 gen_rtx_LSHIFTRT (DImode
, temp
,
2622 GEN_INT (10 - lowest_bit_set
))));
2623 else if (lowest_bit_set
> 10)
2624 emit_insn (gen_rtx_SET (op0
,
2625 gen_rtx_ASHIFT (DImode
, temp
,
2626 GEN_INT (lowest_bit_set
- 10))));
2630 /* 1) sethi %hi(low_bits), %reg
2631 * or %reg, %lo(low_bits), %reg
2632 * 2) sethi %hi(~low_bits), %reg
2633 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2636 || high_bits
== 0xffffffff)
2638 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2639 (high_bits
== 0xffffffff));
2643 /* Now, try 3-insn sequences. */
2645 /* 1) sethi %hi(high_bits), %reg
2646 * or %reg, %lo(high_bits), %reg
2647 * sllx %reg, 32, %reg
2651 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2655 /* We may be able to do something quick
2656 when the constant is negated, so try that. */
2657 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2658 (~low_bits
) & 0xfffffc00))
2660 /* NOTE: The trailing bits get XOR'd so we need the
2661 non-negated bits, not the negated ones. */
2662 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2664 if ((((~high_bits
) & 0xffffffff) == 0
2665 && ((~low_bits
) & 0x80000000) == 0)
2666 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2667 && ((~low_bits
) & 0x80000000) != 0))
2669 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2671 if ((SPARC_SETHI_P (fast_int
)
2672 && (~high_bits
& 0xffffffff) == 0)
2673 || SPARC_SIMM13_P (fast_int
))
2674 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2676 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2681 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2682 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2683 sparc_emit_set_const64 (temp
, negated_const
);
2686 /* If we are XOR'ing with -1, then we should emit a one's complement
2687 instead. This way the combiner will notice logical operations
2688 such as ANDN later on and substitute. */
2689 if (trailing_bits
== 0x3ff)
2691 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2695 emit_insn (gen_rtx_SET (op0
,
2696 gen_safe_XOR64 (temp
,
2697 (-0x400 | trailing_bits
))));
2702 /* 1) sethi %hi(xxx), %reg
2703 * or %reg, %lo(xxx), %reg
2704 * sllx %reg, yyy, %reg
2706 * ??? This is just a generalized version of the low_bits==0
2707 * thing above, FIXME...
2709 if ((highest_bit_set
- lowest_bit_set
) < 32)
2711 unsigned HOST_WIDE_INT focus_bits
=
2712 create_simple_focus_bits (high_bits
, low_bits
,
2715 /* We can't get here in this state. */
2716 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2718 /* So what we know is that the set bits straddle the
2719 middle of the 64-bit word. */
2720 sparc_emit_set_const64_quick2 (op0
, temp
,
2726 /* 1) sethi %hi(high_bits), %reg
2727 * or %reg, %lo(high_bits), %reg
2728 * sllx %reg, 32, %reg
2729 * or %reg, low_bits, %reg
2731 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
2733 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2737 /* The easiest way when all else fails, is full decomposition. */
2738 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2741 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2742 return the mode to be used for the comparison. For floating-point,
2743 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2744 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2745 processing is needed. */
2748 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2750 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2776 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2777 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2779 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2780 return CCX_NOOVmode
;
2786 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2793 /* Emit the compare insn and return the CC reg for a CODE comparison
2794 with operands X and Y. */
2797 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2802 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2805 mode
= SELECT_CC_MODE (code
, x
, y
);
2807 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2808 fcc regs (cse can't tell they're really call clobbered regs and will
2809 remove a duplicate comparison even if there is an intervening function
2810 call - it will then try to reload the cc reg via an int reg which is why
2811 we need the movcc patterns). It is possible to provide the movcc
2812 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2813 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2814 to tell cse that CCFPE mode registers (even pseudos) are call
2817 /* ??? This is an experiment. Rather than making changes to cse which may
2818 or may not be easy/clean, we do our own cse. This is possible because
2819 we will generate hard registers. Cse knows they're call clobbered (it
2820 doesn't know the same thing about pseudos). If we guess wrong, no big
2821 deal, but if we win, great! */
2823 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2824 #if 1 /* experiment */
2827 /* We cycle through the registers to ensure they're all exercised. */
2828 static int next_fcc_reg
= 0;
2829 /* Previous x,y for each fcc reg. */
2830 static rtx prev_args
[4][2];
2832 /* Scan prev_args for x,y. */
2833 for (reg
= 0; reg
< 4; reg
++)
2834 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2839 prev_args
[reg
][0] = x
;
2840 prev_args
[reg
][1] = y
;
2841 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2843 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2846 cc_reg
= gen_reg_rtx (mode
);
2847 #endif /* ! experiment */
2848 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2849 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2851 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2853 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2854 will only result in an unrecognizable insn so no point in asserting. */
2855 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2861 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2864 gen_compare_reg (rtx cmp
)
2866 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2869 /* This function is used for v9 only.
2870 DEST is the target of the Scc insn.
2871 CODE is the code for an Scc's comparison.
2872 X and Y are the values we compare.
2874 This function is needed to turn
2877 (gt (reg:CCX 100 %icc)
2881 (gt:DI (reg:CCX 100 %icc)
2884 IE: The instruction recognizer needs to see the mode of the comparison to
2885 find the right instruction. We could use "gt:DI" right in the
2886 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2889 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2892 && (GET_MODE (x
) == DImode
2893 || GET_MODE (dest
) == DImode
))
2896 /* Try to use the movrCC insns. */
2898 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2900 && v9_regcmp_p (compare_code
))
2905 /* Special case for op0 != 0. This can be done with one instruction if
2908 if (compare_code
== NE
2909 && GET_MODE (dest
) == DImode
2910 && rtx_equal_p (op0
, dest
))
2912 emit_insn (gen_rtx_SET (dest
,
2913 gen_rtx_IF_THEN_ELSE (DImode
,
2914 gen_rtx_fmt_ee (compare_code
, DImode
,
2921 if (reg_overlap_mentioned_p (dest
, op0
))
2923 /* Handle the case where dest == x.
2924 We "early clobber" the result. */
2925 op0
= gen_reg_rtx (GET_MODE (x
));
2926 emit_move_insn (op0
, x
);
2929 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
2930 if (GET_MODE (op0
) != DImode
)
2932 temp
= gen_reg_rtx (DImode
);
2933 convert_move (temp
, op0
, 0);
2937 emit_insn (gen_rtx_SET (dest
,
2938 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2939 gen_rtx_fmt_ee (compare_code
, DImode
,
2947 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2950 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2951 && GET_MODE (x
) != CCX_NOOVmode
);
2953 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
2954 emit_insn (gen_rtx_SET (dest
,
2955 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2956 gen_rtx_fmt_ee (compare_code
,
2957 GET_MODE (x
), x
, y
),
2958 const1_rtx
, dest
)));
2964 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2965 without jumps using the addx/subx instructions. */
2968 emit_scc_insn (rtx operands
[])
2975 /* The quad-word fp compare library routines all return nonzero to indicate
2976 true, which is different from the equivalent libgcc routines, so we must
2977 handle them specially here. */
2978 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2980 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2981 GET_CODE (operands
[1]));
2982 operands
[2] = XEXP (operands
[1], 0);
2983 operands
[3] = XEXP (operands
[1], 1);
2986 code
= GET_CODE (operands
[1]);
2990 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2991 more applications). The exception to this is "reg != 0" which can
2992 be done in one instruction on v9 (so we do it). */
2995 if (GET_MODE (x
) == SImode
)
2999 pat
= gen_seqsidi_special (operands
[0], x
, y
);
3001 pat
= gen_seqsisi_special (operands
[0], x
, y
);
3005 else if (GET_MODE (x
) == DImode
)
3007 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
3015 if (GET_MODE (x
) == SImode
)
3019 pat
= gen_snesidi_special (operands
[0], x
, y
);
3021 pat
= gen_snesisi_special (operands
[0], x
, y
);
3025 else if (GET_MODE (x
) == DImode
)
3029 pat
= gen_snedi_special_vis3 (operands
[0], x
, y
);
3031 pat
= gen_snedi_special (operands
[0], x
, y
);
3039 && GET_MODE (x
) == DImode
3041 && (code
== GTU
|| code
== LTU
))
3042 && gen_v9_scc (operands
[0], code
, x
, y
))
3045 /* We can do LTU and GEU using the addx/subx instructions too. And
3046 for GTU/LEU, if both operands are registers swap them and fall
3047 back to the easy case. */
3048 if (code
== GTU
|| code
== LEU
)
3050 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3051 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3056 code
= swap_condition (code
);
3061 || (!TARGET_VIS3
&& code
== GEU
))
3063 emit_insn (gen_rtx_SET (operands
[0],
3064 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3065 gen_compare_reg_1 (code
, x
, y
),
3070 /* All the posibilities to use addx/subx based sequences has been
3071 exhausted, try for a 3 instruction sequence using v9 conditional
3073 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3076 /* Nope, do branches. */
3080 /* Emit a conditional jump insn for the v9 architecture using comparison code
3081 CODE and jump target LABEL.
3082 This function exists to take advantage of the v9 brxx insns. */
3085 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3087 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3088 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3089 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3091 gen_rtx_LABEL_REF (VOIDmode
, label
),
3095 /* Emit a conditional jump insn for the UA2011 architecture using
3096 comparison code CODE and jump target LABEL. This function exists
3097 to take advantage of the UA2011 Compare and Branch insns. */
3100 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3104 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3105 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3107 gen_rtx_LABEL_REF (VOIDmode
, label
),
3110 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3114 emit_conditional_branch_insn (rtx operands
[])
3116 /* The quad-word fp compare library routines all return nonzero to indicate
3117 true, which is different from the equivalent libgcc routines, so we must
3118 handle them specially here. */
3119 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3121 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3122 GET_CODE (operands
[0]));
3123 operands
[1] = XEXP (operands
[0], 0);
3124 operands
[2] = XEXP (operands
[0], 1);
3127 /* If we can tell early on that the comparison is against a constant
3128 that won't fit in the 5-bit signed immediate field of a cbcond,
3129 use one of the other v9 conditional branch sequences. */
3131 && GET_CODE (operands
[1]) == REG
3132 && (GET_MODE (operands
[1]) == SImode
3133 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3134 && (GET_CODE (operands
[2]) != CONST_INT
3135 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3137 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3141 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3142 && GET_CODE (operands
[1]) == REG
3143 && GET_MODE (operands
[1]) == DImode
)
3145 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3149 operands
[1] = gen_compare_reg (operands
[0]);
3150 operands
[2] = const0_rtx
;
3151 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3152 operands
[1], operands
[2]);
3153 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3158 /* Generate a DFmode part of a hard TFmode register.
3159 REG is the TFmode hard register, LOW is 1 for the
3160 low 64bit of the register and 0 otherwise.
3163 gen_df_reg (rtx reg
, int low
)
3165 int regno
= REGNO (reg
);
3167 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3168 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3169 return gen_rtx_REG (DFmode
, regno
);
3172 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3173 Unlike normal calls, TFmode operands are passed by reference. It is
3174 assumed that no more than 3 operands are required. */
3177 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3179 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3182 /* We only expect to be called for conversions, unary, and binary ops. */
3183 gcc_assert (nargs
== 2 || nargs
== 3);
3185 for (i
= 0; i
< nargs
; ++i
)
3187 rtx this_arg
= operands
[i
];
3190 /* TFmode arguments and return values are passed by reference. */
3191 if (GET_MODE (this_arg
) == TFmode
)
3193 int force_stack_temp
;
3195 force_stack_temp
= 0;
3196 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3197 force_stack_temp
= 1;
3199 if (GET_CODE (this_arg
) == MEM
3200 && ! force_stack_temp
)
3202 tree expr
= MEM_EXPR (this_arg
);
3204 mark_addressable (expr
);
3205 this_arg
= XEXP (this_arg
, 0);
3207 else if (CONSTANT_P (this_arg
)
3208 && ! force_stack_temp
)
3210 this_slot
= force_const_mem (TFmode
, this_arg
);
3211 this_arg
= XEXP (this_slot
, 0);
3215 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3217 /* Operand 0 is the return value. We'll copy it out later. */
3219 emit_move_insn (this_slot
, this_arg
);
3221 ret_slot
= this_slot
;
3223 this_arg
= XEXP (this_slot
, 0);
3230 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3232 if (GET_MODE (operands
[0]) == TFmode
)
3235 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
3236 arg
[0], GET_MODE (arg
[0]),
3237 arg
[1], GET_MODE (arg
[1]));
3239 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
3240 arg
[0], GET_MODE (arg
[0]),
3241 arg
[1], GET_MODE (arg
[1]),
3242 arg
[2], GET_MODE (arg
[2]));
3245 emit_move_insn (operands
[0], ret_slot
);
3251 gcc_assert (nargs
== 2);
3253 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3254 GET_MODE (operands
[0]), 1,
3255 arg
[1], GET_MODE (arg
[1]));
3257 if (ret
!= operands
[0])
3258 emit_move_insn (operands
[0], ret
);
3262 /* Expand soft-float TFmode calls to sparc abi routines. */
3265 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3287 emit_soft_tfmode_libcall (func
, 3, operands
);
3291 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3295 gcc_assert (code
== SQRT
);
3298 emit_soft_tfmode_libcall (func
, 2, operands
);
3302 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3309 switch (GET_MODE (operands
[1]))
3322 case FLOAT_TRUNCATE
:
3323 switch (GET_MODE (operands
[0]))
3337 switch (GET_MODE (operands
[1]))
3342 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3352 case UNSIGNED_FLOAT
:
3353 switch (GET_MODE (operands
[1]))
3358 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3369 switch (GET_MODE (operands
[0]))
3383 switch (GET_MODE (operands
[0]))
3400 emit_soft_tfmode_libcall (func
, 2, operands
);
3403 /* Expand a hard-float tfmode operation. All arguments must be in
3407 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3411 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3413 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3414 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3418 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3419 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3420 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3421 operands
[1], operands
[2]);
3424 if (register_operand (operands
[0], VOIDmode
))
3427 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3429 emit_insn (gen_rtx_SET (dest
, op
));
3431 if (dest
!= operands
[0])
3432 emit_move_insn (operands
[0], dest
);
3436 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3438 if (TARGET_HARD_QUAD
)
3439 emit_hard_tfmode_operation (code
, operands
);
3441 emit_soft_tfmode_binop (code
, operands
);
3445 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3447 if (TARGET_HARD_QUAD
)
3448 emit_hard_tfmode_operation (code
, operands
);
3450 emit_soft_tfmode_unop (code
, operands
);
3454 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3456 if (TARGET_HARD_QUAD
)
3457 emit_hard_tfmode_operation (code
, operands
);
3459 emit_soft_tfmode_cvt (code
, operands
);
3462 /* Return nonzero if a branch/jump/call instruction will be emitting
3463 nop into its delay slot. */
3466 empty_delay_slot (rtx_insn
*insn
)
3470 /* If no previous instruction (should not happen), return true. */
3471 if (PREV_INSN (insn
) == NULL
)
3474 seq
= NEXT_INSN (PREV_INSN (insn
));
3475 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3481 /* Return nonzero if we should emit a nop after a cbcond instruction.
3482 The cbcond instruction does not have a delay slot, however there is
3483 a severe performance penalty if a control transfer appears right
3484 after a cbcond. Therefore we emit a nop when we detect this
3488 emit_cbcond_nop (rtx insn
)
3490 rtx next
= next_active_insn (insn
);
3495 if (NONJUMP_INSN_P (next
)
3496 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3497 next
= XVECEXP (PATTERN (next
), 0, 0);
3498 else if (CALL_P (next
)
3499 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3501 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3503 if (GET_CODE (delay
) == RETURN
)
3505 /* It's a sibling call. Do not emit the nop if we're going
3506 to emit something other than the jump itself as the first
3507 instruction of the sibcall sequence. */
3508 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3513 if (NONJUMP_INSN_P (next
))
3519 /* Return nonzero if TRIAL can go into the call delay slot. */
3522 eligible_for_call_delay (rtx_insn
*trial
)
3526 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3530 call __tls_get_addr, %tgd_call (foo)
3531 add %l7, %o0, %o0, %tgd_add (foo)
3532 while Sun as/ld does not. */
3533 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3536 pat
= PATTERN (trial
);
3538 /* We must reject tgd_add{32|64}, i.e.
3539 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3540 and tldm_add{32|64}, i.e.
3541 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3543 if (GET_CODE (pat
) == SET
3544 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3546 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3548 if (GET_CODE (unspec
) == UNSPEC
3549 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3550 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3557 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3558 instruction. RETURN_P is true if the v9 variant 'return' is to be
3559 considered in the test too.
3561 TRIAL must be a SET whose destination is a REG appropriate for the
3562 'restore' instruction or, if RETURN_P is true, for the 'return'
3566 eligible_for_restore_insn (rtx trial
, bool return_p
)
3568 rtx pat
= PATTERN (trial
);
3569 rtx src
= SET_SRC (pat
);
3570 bool src_is_freg
= false;
3573 /* Since we now can do moves between float and integer registers when
3574 VIS3 is enabled, we have to catch this case. We can allow such
3575 moves when doing a 'return' however. */
3577 if (GET_CODE (src_reg
) == SUBREG
)
3578 src_reg
= SUBREG_REG (src_reg
);
3579 if (GET_CODE (src_reg
) == REG
3580 && SPARC_FP_REG_P (REGNO (src_reg
)))
3583 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3584 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3585 && arith_operand (src
, GET_MODE (src
))
3589 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3591 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3594 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3595 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3596 && arith_double_operand (src
, GET_MODE (src
))
3598 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3600 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3601 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3604 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3605 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3608 /* If we have the 'return' instruction, anything that does not use
3609 local or output registers and can go into a delay slot wins. */
3610 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
3613 /* The 'restore src1,src2,dest' pattern for SImode. */
3614 else if (GET_CODE (src
) == PLUS
3615 && register_operand (XEXP (src
, 0), SImode
)
3616 && arith_operand (XEXP (src
, 1), SImode
))
3619 /* The 'restore src1,src2,dest' pattern for DImode. */
3620 else if (GET_CODE (src
) == PLUS
3621 && register_operand (XEXP (src
, 0), DImode
)
3622 && arith_double_operand (XEXP (src
, 1), DImode
))
3625 /* The 'restore src1,%lo(src2),dest' pattern. */
3626 else if (GET_CODE (src
) == LO_SUM
3627 && ! TARGET_CM_MEDMID
3628 && ((register_operand (XEXP (src
, 0), SImode
)
3629 && immediate_operand (XEXP (src
, 1), SImode
))
3631 && register_operand (XEXP (src
, 0), DImode
)
3632 && immediate_operand (XEXP (src
, 1), DImode
))))
3635 /* The 'restore src,src,dest' pattern. */
3636 else if (GET_CODE (src
) == ASHIFT
3637 && (register_operand (XEXP (src
, 0), SImode
)
3638 || register_operand (XEXP (src
, 0), DImode
))
3639 && XEXP (src
, 1) == const1_rtx
)
3645 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3648 eligible_for_return_delay (rtx_insn
*trial
)
3653 /* If the function uses __builtin_eh_return, the eh_return machinery
3654 occupies the delay slot. */
3655 if (crtl
->calls_eh_return
)
3658 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3661 /* In the case of a leaf or flat function, anything can go into the slot. */
3662 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3665 if (!NONJUMP_INSN_P (trial
))
3668 pat
= PATTERN (trial
);
3669 if (GET_CODE (pat
) == PARALLEL
)
3675 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3677 rtx expr
= XVECEXP (pat
, 0, i
);
3678 if (GET_CODE (expr
) != SET
)
3680 if (GET_CODE (SET_DEST (expr
)) != REG
)
3682 regno
= REGNO (SET_DEST (expr
));
3683 if (regno
>= 8 && regno
< 24)
3686 return !epilogue_renumber (&pat
, 1);
3689 if (GET_CODE (pat
) != SET
)
3692 if (GET_CODE (SET_DEST (pat
)) != REG
)
3695 regno
= REGNO (SET_DEST (pat
));
3697 /* Otherwise, only operations which can be done in tandem with
3698 a `restore' or `return' insn can go into the delay slot. */
3699 if (regno
>= 8 && regno
< 24)
3702 /* If this instruction sets up floating point register and we have a return
3703 instruction, it can probably go in. But restore will not work
3705 if (! SPARC_INT_REG_P (regno
))
3706 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
3708 return eligible_for_restore_insn (trial
, true);
3711 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3714 eligible_for_sibcall_delay (rtx_insn
*trial
)
3718 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3721 if (!NONJUMP_INSN_P (trial
))
3724 pat
= PATTERN (trial
);
3726 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3728 /* If the tail call is done using the call instruction,
3729 we have to restore %o7 in the delay slot. */
3730 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3733 /* %g1 is used to build the function address */
3734 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3740 if (GET_CODE (pat
) != SET
)
3743 /* Otherwise, only operations which can be done in tandem with
3744 a `restore' insn can go into the delay slot. */
3745 if (GET_CODE (SET_DEST (pat
)) != REG
3746 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3747 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3750 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3752 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3755 return eligible_for_restore_insn (trial
, false);
3758 /* Determine if it's legal to put X into the constant pool. This
3759 is not possible if X contains the address of a symbol that is
3760 not constant (TLS) or not known at final link time (PIC). */
3763 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
3765 switch (GET_CODE (x
))
3768 case CONST_WIDE_INT
:
3771 /* Accept all non-symbolic constants. */
3775 /* Labels are OK iff we are non-PIC. */
3776 return flag_pic
!= 0;
3779 /* 'Naked' TLS symbol references are never OK,
3780 non-TLS symbols are OK iff we are non-PIC. */
3781 if (SYMBOL_REF_TLS_MODEL (x
))
3784 return flag_pic
!= 0;
3787 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3790 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3791 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3799 /* Global Offset Table support. */
3800 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3801 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3803 /* Return the SYMBOL_REF for the Global Offset Table. */
3805 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3810 if (!sparc_got_symbol
)
3811 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3813 return sparc_got_symbol
;
3816 /* Ensure that we are not using patterns that are not OK with PIC. */
3826 op
= recog_data
.operand
[i
];
3827 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3828 && (GET_CODE (op
) != CONST
3829 || (GET_CODE (XEXP (op
, 0)) == MINUS
3830 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3831 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3838 /* Return true if X is an address which needs a temporary register when
3839 reloaded while generating PIC code. */
3842 pic_address_needs_scratch (rtx x
)
3844 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3845 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3846 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3847 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3848 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3854 /* Determine if a given RTX is a valid constant. We already know this
3855 satisfies CONSTANT_P. */
3858 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
3860 switch (GET_CODE (x
))
3864 if (sparc_tls_referenced_p (x
))
3869 /* Floating point constants are generally not ok.
3870 The only exception is 0.0 and all-ones in VIS. */
3872 && SCALAR_FLOAT_MODE_P (mode
)
3873 && (const_zero_operand (x
, mode
)
3874 || const_all_ones_operand (x
, mode
)))
3880 /* Vector constants are generally not ok.
3881 The only exception is 0 or -1 in VIS. */
3883 && (const_zero_operand (x
, mode
)
3884 || const_all_ones_operand (x
, mode
)))
3896 /* Determine if a given RTX is a valid constant address. */
3899 constant_address_p (rtx x
)
3901 switch (GET_CODE (x
))
3909 if (flag_pic
&& pic_address_needs_scratch (x
))
3911 return sparc_legitimate_constant_p (Pmode
, x
);
3914 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3921 /* Nonzero if the constant value X is a legitimate general operand
3922 when generating PIC code. It is given that flag_pic is on and
3923 that X satisfies CONSTANT_P. */
3926 legitimate_pic_operand_p (rtx x
)
3928 if (pic_address_needs_scratch (x
))
3930 if (sparc_tls_referenced_p (x
))
3935 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3937 && INTVAL (X) >= -0x1000 \
3938 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
3940 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3942 && INTVAL (X) >= -0x1000 \
3943 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
3945 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3947 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3948 ordinarily. This changes a bit when generating PIC. */
3951 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
3953 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3955 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3957 else if (GET_CODE (addr
) == PLUS
)
3959 rs1
= XEXP (addr
, 0);
3960 rs2
= XEXP (addr
, 1);
3962 /* Canonicalize. REG comes first, if there are no regs,
3963 LO_SUM comes first. */
3965 && GET_CODE (rs1
) != SUBREG
3967 || GET_CODE (rs2
) == SUBREG
3968 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3970 rs1
= XEXP (addr
, 1);
3971 rs2
= XEXP (addr
, 0);
3975 && rs1
== pic_offset_table_rtx
3977 && GET_CODE (rs2
) != SUBREG
3978 && GET_CODE (rs2
) != LO_SUM
3979 && GET_CODE (rs2
) != MEM
3980 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3981 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3982 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3984 || GET_CODE (rs1
) == SUBREG
)
3985 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3990 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3991 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3993 /* We prohibit REG + REG for TFmode when there are no quad move insns
3994 and we consequently need to split. We do this because REG+REG
3995 is not an offsettable address. If we get the situation in reload
3996 where source and destination of a movtf pattern are both MEMs with
3997 REG+REG address, then only one of them gets converted to an
3998 offsettable address. */
4000 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4003 /* Likewise for TImode, but in all cases. */
4007 /* We prohibit REG + REG on ARCH32 if not optimizing for
4008 DFmode/DImode because then mem_min_alignment is likely to be zero
4009 after reload and the forced split would lack a matching splitter
4011 if (TARGET_ARCH32
&& !optimize
4012 && (mode
== DFmode
|| mode
== DImode
))
4015 else if (USE_AS_OFFSETABLE_LO10
4016 && GET_CODE (rs1
) == LO_SUM
4018 && ! TARGET_CM_MEDMID
4019 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4022 imm1
= XEXP (rs1
, 1);
4023 rs1
= XEXP (rs1
, 0);
4024 if (!CONSTANT_P (imm1
)
4025 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4029 else if (GET_CODE (addr
) == LO_SUM
)
4031 rs1
= XEXP (addr
, 0);
4032 imm1
= XEXP (addr
, 1);
4034 if (!CONSTANT_P (imm1
)
4035 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4038 /* We can't allow TFmode in 32-bit mode, because an offset greater
4039 than the alignment (8) may cause the LO_SUM to overflow. */
4040 if (mode
== TFmode
&& TARGET_ARCH32
)
4043 /* During reload, accept the HIGH+LO_SUM construct generated by
4044 sparc_legitimize_reload_address. */
4045 if (reload_in_progress
4046 && GET_CODE (rs1
) == HIGH
4047 && XEXP (rs1
, 0) == imm1
)
4050 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4055 if (GET_CODE (rs1
) == SUBREG
)
4056 rs1
= SUBREG_REG (rs1
);
4062 if (GET_CODE (rs2
) == SUBREG
)
4063 rs2
= SUBREG_REG (rs2
);
4070 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4071 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4076 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4077 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4078 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4080 && (! SPARC_INT_REG_P (REGNO (rs2
))
4081 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4082 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4088 /* Return the SYMBOL_REF for the tls_get_addr function. */
4090 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4093 sparc_tls_get_addr (void)
4095 if (!sparc_tls_symbol
)
4096 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4098 return sparc_tls_symbol
;
4101 /* Return the Global Offset Table to be used in TLS mode. */
4104 sparc_tls_got (void)
4106 /* In PIC mode, this is just the PIC offset table. */
4109 crtl
->uses_pic_offset_table
= 1;
4110 return pic_offset_table_rtx
;
4113 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4114 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4115 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4117 load_got_register ();
4118 return global_offset_table_rtx
;
4121 /* In all other cases, we load a new pseudo with the GOT symbol. */
4122 return copy_to_reg (sparc_got ());
4125 /* Return true if X contains a thread-local symbol. */
4128 sparc_tls_referenced_p (rtx x
)
4130 if (!TARGET_HAVE_TLS
)
4133 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4134 x
= XEXP (XEXP (x
, 0), 0);
4136 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4139 /* That's all we handle in sparc_legitimize_tls_address for now. */
4143 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4144 this (thread-local) address. */
4147 sparc_legitimize_tls_address (rtx addr
)
4149 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4152 gcc_assert (can_create_pseudo_p ());
4154 if (GET_CODE (addr
) == SYMBOL_REF
)
4155 switch (SYMBOL_REF_TLS_MODEL (addr
))
4157 case TLS_MODEL_GLOBAL_DYNAMIC
:
4159 temp1
= gen_reg_rtx (SImode
);
4160 temp2
= gen_reg_rtx (SImode
);
4161 ret
= gen_reg_rtx (Pmode
);
4162 o0
= gen_rtx_REG (Pmode
, 8);
4163 got
= sparc_tls_got ();
4164 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4165 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4168 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4169 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4174 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4175 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4178 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4179 insn
= get_insns ();
4181 emit_libcall_block (insn
, ret
, o0
, addr
);
4184 case TLS_MODEL_LOCAL_DYNAMIC
:
4186 temp1
= gen_reg_rtx (SImode
);
4187 temp2
= gen_reg_rtx (SImode
);
4188 temp3
= gen_reg_rtx (Pmode
);
4189 ret
= gen_reg_rtx (Pmode
);
4190 o0
= gen_rtx_REG (Pmode
, 8);
4191 got
= sparc_tls_got ();
4192 emit_insn (gen_tldm_hi22 (temp1
));
4193 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4196 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4197 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4202 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4203 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4206 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4207 insn
= get_insns ();
4209 emit_libcall_block (insn
, temp3
, o0
,
4210 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4211 UNSPEC_TLSLD_BASE
));
4212 temp1
= gen_reg_rtx (SImode
);
4213 temp2
= gen_reg_rtx (SImode
);
4214 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4215 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4217 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4219 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4222 case TLS_MODEL_INITIAL_EXEC
:
4223 temp1
= gen_reg_rtx (SImode
);
4224 temp2
= gen_reg_rtx (SImode
);
4225 temp3
= gen_reg_rtx (Pmode
);
4226 got
= sparc_tls_got ();
4227 emit_insn (gen_tie_hi22 (temp1
, addr
));
4228 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4230 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4232 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4235 ret
= gen_reg_rtx (Pmode
);
4237 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4240 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4244 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4247 case TLS_MODEL_LOCAL_EXEC
:
4248 temp1
= gen_reg_rtx (Pmode
);
4249 temp2
= gen_reg_rtx (Pmode
);
4252 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4253 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4257 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4258 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4260 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4267 else if (GET_CODE (addr
) == CONST
)
4271 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4273 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4274 offset
= XEXP (XEXP (addr
, 0), 1);
4276 base
= force_operand (base
, NULL_RTX
);
4277 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4278 offset
= force_reg (Pmode
, offset
);
4279 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4283 gcc_unreachable (); /* for now ... */
4288 /* Legitimize PIC addresses. If the address is already position-independent,
4289 we return ORIG. Newly generated position-independent addresses go into a
4290 reg. This is REG if nonzero, otherwise we allocate register(s) as
4294 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4296 bool gotdata_op
= false;
4298 if (GET_CODE (orig
) == SYMBOL_REF
4299 /* See the comment in sparc_expand_move. */
4300 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4302 rtx pic_ref
, address
;
4307 gcc_assert (can_create_pseudo_p ());
4308 reg
= gen_reg_rtx (Pmode
);
4313 /* If not during reload, allocate another temp reg here for loading
4314 in the address, so that these instructions can be optimized
4316 rtx temp_reg
= (! can_create_pseudo_p ()
4317 ? reg
: gen_reg_rtx (Pmode
));
4319 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4320 won't get confused into thinking that these two instructions
4321 are loading in the true address of the symbol. If in the
4322 future a PIC rtx exists, that should be used instead. */
4325 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4326 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4330 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4331 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4339 crtl
->uses_pic_offset_table
= 1;
4343 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4344 pic_offset_table_rtx
,
4347 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4348 pic_offset_table_rtx
,
4354 = gen_const_mem (Pmode
,
4355 gen_rtx_PLUS (Pmode
,
4356 pic_offset_table_rtx
, address
));
4357 insn
= emit_move_insn (reg
, pic_ref
);
4360 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4362 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4365 else if (GET_CODE (orig
) == CONST
)
4369 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4370 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4375 gcc_assert (can_create_pseudo_p ());
4376 reg
= gen_reg_rtx (Pmode
);
4379 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4380 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4381 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4382 base
== reg
? NULL_RTX
: reg
);
4384 if (GET_CODE (offset
) == CONST_INT
)
4386 if (SMALL_INT (offset
))
4387 return plus_constant (Pmode
, base
, INTVAL (offset
));
4388 else if (can_create_pseudo_p ())
4389 offset
= force_reg (Pmode
, offset
);
4391 /* If we reach here, then something is seriously wrong. */
4394 return gen_rtx_PLUS (Pmode
, base
, offset
);
4396 else if (GET_CODE (orig
) == LABEL_REF
)
4397 /* ??? We ought to be checking that the register is live instead, in case
4398 it is eliminated. */
4399 crtl
->uses_pic_offset_table
= 1;
4404 /* Try machine-dependent ways of modifying an illegitimate address X
4405 to be legitimate. If we find one, return the new, valid address.
4407 OLDX is the address as it was before break_out_memory_refs was called.
4408 In some cases it is useful to look at this to decide what needs to be done.
4410 MODE is the mode of the operand pointed to by X.
4412 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4415 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4420 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4421 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4422 force_operand (XEXP (x
, 0), NULL_RTX
));
4423 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4424 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4425 force_operand (XEXP (x
, 1), NULL_RTX
));
4426 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4427 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4429 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4430 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4431 force_operand (XEXP (x
, 1), NULL_RTX
));
4433 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4436 if (sparc_tls_referenced_p (x
))
4437 x
= sparc_legitimize_tls_address (x
);
4439 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4440 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4441 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4442 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4443 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4444 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4445 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4446 else if (GET_CODE (x
) == SYMBOL_REF
4447 || GET_CODE (x
) == CONST
4448 || GET_CODE (x
) == LABEL_REF
)
4449 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4454 /* Delegitimize an address that was legitimized by the above function. */
4457 sparc_delegitimize_address (rtx x
)
4459 x
= delegitimize_mem_from_attrs (x
);
4461 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4462 switch (XINT (XEXP (x
, 1), 1))
4464 case UNSPEC_MOVE_PIC
:
4466 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4467 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4473 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4474 if (GET_CODE (x
) == MINUS
4475 && REG_P (XEXP (x
, 0))
4476 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4477 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4478 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4479 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4481 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4482 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4488 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4489 replace the input X, or the original X if no replacement is called for.
4490 The output parameter *WIN is 1 if the calling macro should goto WIN,
4493 For SPARC, we wish to handle addresses by splitting them into
4494 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4495 This cuts the number of extra insns by one.
4497 Do nothing when generating PIC code and the address is a symbolic
4498 operand or requires a scratch register. */
4501 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
4502 int opnum
, int type
,
4503 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4505 /* Decompose SImode constants into HIGH+LO_SUM. */
4507 && (mode
!= TFmode
|| TARGET_ARCH64
)
4508 && GET_MODE (x
) == SImode
4509 && GET_CODE (x
) != LO_SUM
4510 && GET_CODE (x
) != HIGH
4511 && sparc_cmodel
<= CM_MEDLOW
4513 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4515 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4516 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4517 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4518 opnum
, (enum reload_type
)type
);
4523 /* We have to recognize what we have already generated above. */
4524 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4526 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4527 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4528 opnum
, (enum reload_type
)type
);
4537 /* Return true if ADDR (a legitimate address expression)
4538 has an effect that depends on the machine mode it is used for.
4544 is not equivalent to
4546 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4548 because [%l7+a+1] is interpreted as the address of (a+1). */
4552 sparc_mode_dependent_address_p (const_rtx addr
,
4553 addr_space_t as ATTRIBUTE_UNUSED
)
4555 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4557 rtx op0
= XEXP (addr
, 0);
4558 rtx op1
= XEXP (addr
, 1);
4559 if (op0
== pic_offset_table_rtx
4560 && symbolic_operand (op1
, VOIDmode
))
4567 #ifdef HAVE_GAS_HIDDEN
4568 # define USE_HIDDEN_LINKONCE 1
4570 # define USE_HIDDEN_LINKONCE 0
4574 get_pc_thunk_name (char name
[32], unsigned int regno
)
4576 const char *reg_name
= reg_names
[regno
];
4578 /* Skip the leading '%' as that cannot be used in a
4582 if (USE_HIDDEN_LINKONCE
)
4583 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4585 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4588 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4591 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4593 int orig_flag_pic
= flag_pic
;
4596 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4599 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4601 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4602 flag_pic
= orig_flag_pic
;
4607 /* Emit code to load the GOT register. */
4610 load_got_register (void)
4612 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4613 if (!global_offset_table_rtx
)
4614 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4616 if (TARGET_VXWORKS_RTP
)
4617 emit_insn (gen_vxworks_load_got ());
4620 /* The GOT symbol is subject to a PC-relative relocation so we need a
4621 helper function to add the PC value and thus get the final value. */
4622 if (!got_helper_rtx
)
4625 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4626 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4629 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4631 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4634 /* Need to emit this whether or not we obey regdecls,
4635 since setjmp/longjmp can cause life info to screw up.
4636 ??? In the case where we don't obey regdecls, this is not sufficient
4637 since we may not fall out the bottom. */
4638 emit_use (global_offset_table_rtx
);
4641 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4642 address of the call target. */
4645 sparc_emit_call_insn (rtx pat
, rtx addr
)
4649 insn
= emit_call_insn (pat
);
4651 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4652 if (TARGET_VXWORKS_RTP
4654 && GET_CODE (addr
) == SYMBOL_REF
4655 && (SYMBOL_REF_DECL (addr
)
4656 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4657 : !SYMBOL_REF_LOCAL_P (addr
)))
4659 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4660 crtl
->uses_pic_offset_table
= 1;
4664 /* Return 1 if RTX is a MEM which is known to be aligned to at
4665 least a DESIRED byte boundary. */
4668 mem_min_alignment (rtx mem
, int desired
)
4670 rtx addr
, base
, offset
;
4672 /* If it's not a MEM we can't accept it. */
4673 if (GET_CODE (mem
) != MEM
)
4677 if (!TARGET_UNALIGNED_DOUBLES
4678 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4681 /* ??? The rest of the function predates MEM_ALIGN so
4682 there is probably a bit of redundancy. */
4683 addr
= XEXP (mem
, 0);
4684 base
= offset
= NULL_RTX
;
4685 if (GET_CODE (addr
) == PLUS
)
4687 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4689 base
= XEXP (addr
, 0);
4691 /* What we are saying here is that if the base
4692 REG is aligned properly, the compiler will make
4693 sure any REG based index upon it will be so
4695 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4696 offset
= XEXP (addr
, 1);
4698 offset
= const0_rtx
;
4701 else if (GET_CODE (addr
) == REG
)
4704 offset
= const0_rtx
;
4707 if (base
!= NULL_RTX
)
4709 int regno
= REGNO (base
);
4711 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4713 /* Check if the compiler has recorded some information
4714 about the alignment of the base REG. If reload has
4715 completed, we already matched with proper alignments.
4716 If not running global_alloc, reload might give us
4717 unaligned pointer to local stack though. */
4719 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4720 || (optimize
&& reload_completed
))
4721 && (INTVAL (offset
) & (desired
- 1)) == 0)
4726 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4730 else if (! TARGET_UNALIGNED_DOUBLES
4731 || CONSTANT_P (addr
)
4732 || GET_CODE (addr
) == LO_SUM
)
4734 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4735 is true, in which case we can only assume that an access is aligned if
4736 it is to a constant address, or the address involves a LO_SUM. */
4740 /* An obviously unaligned address. */
4745 /* Vectors to keep interesting information about registers where it can easily
4746 be got. We used to use the actual mode value as the bit number, but there
4747 are more than 32 modes now. Instead we use two tables: one indexed by
4748 hard register number, and one indexed by mode. */
4750 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4751 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4752 mapped into one sparc_mode_class mode. */
4754 enum sparc_mode_class
{
4755 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4756 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4760 /* Modes for single-word and smaller quantities. */
4762 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4764 /* Modes for double-word and smaller quantities. */
4765 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4767 /* Modes for quad-word and smaller quantities. */
4768 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4770 /* Modes for 8-word and smaller quantities. */
4771 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4773 /* Modes for single-float quantities. */
4774 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4776 /* Modes for double-float and smaller quantities. */
4777 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4779 /* Modes for quad-float and smaller quantities. */
4780 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4782 /* Modes for quad-float pairs and smaller quantities. */
4783 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4785 /* Modes for double-float only quantities. */
4786 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4788 /* Modes for quad-float and double-float only quantities. */
4789 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4791 /* Modes for quad-float pairs and double-float only quantities. */
4792 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4794 /* Modes for condition codes. */
4795 #define CC_MODES (1 << (int) CC_MODE)
4796 #define CCFP_MODES (1 << (int) CCFP_MODE)
4798 /* Value is 1 if register/mode pair is acceptable on sparc.
4800 The funny mixture of D and T modes is because integer operations
4801 do not specially operate on tetra quantities, so non-quad-aligned
4802 registers can hold quadword quantities (except %o4 and %i4 because
4803 they cross fixed registers).
4805 ??? Note that, despite the settings, non-double-aligned parameter
4806 registers can hold double-word quantities in 32-bit mode. */
4808 /* This points to either the 32 bit or the 64 bit version. */
4809 const int *hard_regno_mode_classes
;
4811 static const int hard_32bit_mode_classes
[] = {
4812 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4813 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4814 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4815 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4817 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4818 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4819 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4820 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4822 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4823 and none can hold SFmode/SImode values. */
4824 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4825 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4826 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4827 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4830 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4832 /* %icc, %sfp, %gsr */
4833 CC_MODES
, 0, D_MODES
4836 static const int hard_64bit_mode_classes
[] = {
4837 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4838 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4839 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4840 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4842 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4843 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4844 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4845 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4847 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4848 and none can hold SFmode/SImode values. */
4849 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4850 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4851 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4852 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4855 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4857 /* %icc, %sfp, %gsr */
4858 CC_MODES
, 0, D_MODES
4861 int sparc_mode_class
[NUM_MACHINE_MODES
];
4863 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4866 sparc_init_modes (void)
4870 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4872 machine_mode m
= (machine_mode
) i
;
4873 unsigned int size
= GET_MODE_SIZE (m
);
4875 switch (GET_MODE_CLASS (m
))
4878 case MODE_PARTIAL_INT
:
4879 case MODE_COMPLEX_INT
:
4881 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
4883 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4885 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4886 else if (size
== 16)
4887 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4888 else if (size
== 32)
4889 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4891 sparc_mode_class
[i
] = 0;
4893 case MODE_VECTOR_INT
:
4895 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4897 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4899 sparc_mode_class
[i
] = 0;
4902 case MODE_COMPLEX_FLOAT
:
4904 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4906 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4907 else if (size
== 16)
4908 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4909 else if (size
== 32)
4910 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4912 sparc_mode_class
[i
] = 0;
4915 if (m
== CCFPmode
|| m
== CCFPEmode
)
4916 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4918 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4921 sparc_mode_class
[i
] = 0;
4927 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4929 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4931 /* Initialize the array used by REGNO_REG_CLASS. */
4932 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4934 if (i
< 16 && TARGET_V8PLUS
)
4935 sparc_regno_reg_class
[i
] = I64_REGS
;
4936 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4937 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4939 sparc_regno_reg_class
[i
] = FP_REGS
;
4941 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4943 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4945 sparc_regno_reg_class
[i
] = NO_REGS
;
4949 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4952 save_global_or_fp_reg_p (unsigned int regno
,
4953 int leaf_function ATTRIBUTE_UNUSED
)
4955 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4958 /* Return whether the return address register (%i7) is needed. */
4961 return_addr_reg_needed_p (int leaf_function
)
4963 /* If it is live, for example because of __builtin_return_address (0). */
4964 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4967 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4969 /* Loading the GOT register clobbers %o7. */
4970 || crtl
->uses_pic_offset_table
4971 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4977 /* Return whether REGNO, a local or in register, must be saved/restored. */
4980 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4982 /* General case: call-saved registers live at some point. */
4983 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4986 /* Frame pointer register (%fp) if needed. */
4987 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4990 /* Return address register (%i7) if needed. */
4991 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4994 /* GOT register (%l7) if needed. */
4995 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4998 /* If the function accesses prior frames, the frame pointer and the return
4999 address of the previous frame must be saved on the stack. */
5000 if (crtl
->accesses_prior_frames
5001 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5007 /* Compute the frame size required by the function. This function is called
5008 during the reload pass and also by sparc_expand_prologue. */
5011 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5013 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5014 int args_size
, n_global_fp_regs
= 0;
5015 bool save_local_in_regs_p
= false;
5018 /* If the function allocates dynamic stack space, the dynamic offset is
5019 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5020 if (leaf_function
&& !cfun
->calls_alloca
)
5023 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5025 /* Calculate space needed for global registers. */
5028 for (i
= 0; i
< 8; i
++)
5029 if (save_global_or_fp_reg_p (i
, 0))
5030 n_global_fp_regs
+= 2;
5034 for (i
= 0; i
< 8; i
+= 2)
5035 if (save_global_or_fp_reg_p (i
, 0)
5036 || save_global_or_fp_reg_p (i
+ 1, 0))
5037 n_global_fp_regs
+= 2;
5040 /* In the flat window model, find out which local and in registers need to
5041 be saved. We don't reserve space in the current frame for them as they
5042 will be spilled into the register window save area of the caller's frame.
5043 However, as soon as we use this register window save area, we must create
5044 that of the current frame to make it the live one. */
5046 for (i
= 16; i
< 32; i
++)
5047 if (save_local_or_in_reg_p (i
, leaf_function
))
5049 save_local_in_regs_p
= true;
5053 /* Calculate space needed for FP registers. */
5054 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5055 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5056 n_global_fp_regs
+= 2;
5059 && n_global_fp_regs
== 0
5061 && !save_local_in_regs_p
)
5062 frame_size
= apparent_frame_size
= 0;
5065 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5066 apparent_frame_size
= ROUND_UP (size
- STARTING_FRAME_OFFSET
, 8);
5067 apparent_frame_size
+= n_global_fp_regs
* 4;
5069 /* We need to add the size of the outgoing argument area. */
5070 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5072 /* And that of the register window save area. */
5073 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5075 /* Finally, bump to the appropriate alignment. */
5076 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5079 /* Set up values for use in prologue and epilogue. */
5080 sparc_frame_size
= frame_size
;
5081 sparc_apparent_frame_size
= apparent_frame_size
;
5082 sparc_n_global_fp_regs
= n_global_fp_regs
;
5083 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5088 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5091 sparc_initial_elimination_offset (int to
)
5095 if (to
== STACK_POINTER_REGNUM
)
5096 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5100 offset
+= SPARC_STACK_BIAS
;
5104 /* Output any necessary .register pseudo-ops. */
5107 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5109 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5115 /* Check if %g[2367] were used without
5116 .register being printed for them already. */
5117 for (i
= 2; i
< 8; i
++)
5119 if (df_regs_ever_live_p (i
)
5120 && ! sparc_hard_reg_printed
[i
])
5122 sparc_hard_reg_printed
[i
] = 1;
5123 /* %g7 is used as TLS base register, use #ignore
5124 for it instead of #scratch. */
5125 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5126 i
== 7 ? "ignore" : "scratch");
5133 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5135 #if PROBE_INTERVAL > 4096
5136 #error Cannot use indexed addressing mode for stack probing
5139 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5140 inclusive. These are offsets from the current stack pointer.
5142 Note that we don't use the REG+REG addressing mode for the probes because
5143 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5144 so the advantages of having a single code win here. */
5147 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5149 rtx g1
= gen_rtx_REG (Pmode
, 1);
5151 /* See if we have a constant small number of probes to generate. If so,
5152 that's the easy case. */
5153 if (size
<= PROBE_INTERVAL
)
5155 emit_move_insn (g1
, GEN_INT (first
));
5156 emit_insn (gen_rtx_SET (g1
,
5157 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5158 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5161 /* The run-time loop is made up of 9 insns in the generic case while the
5162 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5163 else if (size
<= 4 * PROBE_INTERVAL
)
5167 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5168 emit_insn (gen_rtx_SET (g1
,
5169 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5170 emit_stack_probe (g1
);
5172 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5173 it exceeds SIZE. If only two probes are needed, this will not
5174 generate any code. Then probe at FIRST + SIZE. */
5175 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5177 emit_insn (gen_rtx_SET (g1
,
5178 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5179 emit_stack_probe (g1
);
5182 emit_stack_probe (plus_constant (Pmode
, g1
,
5183 (i
- PROBE_INTERVAL
) - size
));
5186 /* Otherwise, do the same as above, but in a loop. Note that we must be
5187 extra careful with variables wrapping around because we might be at
5188 the very top (or the very bottom) of the address space and we have
5189 to be able to handle this case properly; in particular, we use an
5190 equality test for the loop condition. */
5193 HOST_WIDE_INT rounded_size
;
5194 rtx g4
= gen_rtx_REG (Pmode
, 4);
5196 emit_move_insn (g1
, GEN_INT (first
));
5199 /* Step 1: round SIZE to the previous multiple of the interval. */
5201 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5202 emit_move_insn (g4
, GEN_INT (rounded_size
));
5205 /* Step 2: compute initial and final value of the loop counter. */
5207 /* TEST_ADDR = SP + FIRST. */
5208 emit_insn (gen_rtx_SET (g1
,
5209 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5211 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5212 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5217 while (TEST_ADDR != LAST_ADDR)
5219 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5223 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5224 until it is equal to ROUNDED_SIZE. */
5227 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5229 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5232 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5233 that SIZE is equal to ROUNDED_SIZE. */
5235 if (size
!= rounded_size
)
5236 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5239 /* Make sure nothing is scheduled before we are done. */
5240 emit_insn (gen_blockage ());
5243 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5244 absolute addresses. */
5247 output_probe_stack_range (rtx reg1
, rtx reg2
)
5249 static int labelno
= 0;
5253 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5256 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5258 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5260 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5261 output_asm_insn ("add\t%0, %1, %0", xops
);
5263 /* Test if TEST_ADDR == LAST_ADDR. */
5265 output_asm_insn ("cmp\t%0, %1", xops
);
5267 /* Probe at TEST_ADDR and branch. */
5269 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5271 fputs ("\tbne\t", asm_out_file
);
5272 assemble_name_raw (asm_out_file
, loop_lab
);
5273 fputc ('\n', asm_out_file
);
5274 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5275 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5280 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5281 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5282 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5283 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5284 the action to be performed if it returns false. Return the new offset. */
5286 typedef bool (*sorr_pred_t
) (unsigned int, int);
5287 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5290 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5291 int offset
, int leaf_function
, sorr_pred_t save_p
,
5292 sorr_act_t action_true
, sorr_act_t action_false
)
5298 if (TARGET_ARCH64
&& high
<= 32)
5302 for (i
= low
; i
< high
; i
++)
5304 if (save_p (i
, leaf_function
))
5306 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5308 if (action_true
== SORR_SAVE
)
5310 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5311 RTX_FRAME_RELATED_P (insn
) = 1;
5313 else /* action_true == SORR_RESTORE */
5315 /* The frame pointer must be restored last since its old
5316 value may be used as base address for the frame. This
5317 is problematic in 64-bit mode only because of the lack
5318 of double-word load instruction. */
5319 if (i
== HARD_FRAME_POINTER_REGNUM
)
5322 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5326 else if (action_false
== SORR_ADVANCE
)
5332 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5333 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5338 for (i
= low
; i
< high
; i
+= 2)
5340 bool reg0
= save_p (i
, leaf_function
);
5341 bool reg1
= save_p (i
+ 1, leaf_function
);
5347 mode
= SPARC_INT_REG_P (i
) ? DImode
: DFmode
;
5352 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5357 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5363 if (action_false
== SORR_ADVANCE
)
5368 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5369 if (action_true
== SORR_SAVE
)
5371 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5372 RTX_FRAME_RELATED_P (insn
) = 1;
5376 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5378 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5379 RTX_FRAME_RELATED_P (set1
) = 1;
5381 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5383 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5384 RTX_FRAME_RELATED_P (set2
) = 1;
5385 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5386 gen_rtx_PARALLEL (VOIDmode
,
5387 gen_rtvec (2, set1
, set2
)));
5390 else /* action_true == SORR_RESTORE */
5391 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5393 /* Bump and round down to double word
5394 in case we already bumped by 4. */
5395 offset
= ROUND_DOWN (offset
+ 8, 8);
5402 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5405 emit_adjust_base_to_offset (rtx base
, int offset
)
5407 /* ??? This might be optimized a little as %g1 might already have a
5408 value close enough that a single add insn will do. */
5409 /* ??? Although, all of this is probably only a temporary fix because
5410 if %g1 can hold a function result, then sparc_expand_epilogue will
5411 lose (the result will be clobbered). */
5412 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5413 emit_move_insn (new_base
, GEN_INT (offset
));
5414 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5418 /* Emit code to save/restore call-saved global and FP registers. */
5421 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5423 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5425 base
= emit_adjust_base_to_offset (base
, offset
);
5430 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5431 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5432 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5433 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5436 /* Emit code to save/restore call-saved local and in registers. */
5439 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5441 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5443 base
= emit_adjust_base_to_offset (base
, offset
);
5447 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5448 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5451 /* Emit a window_save insn. */
5454 emit_window_save (rtx increment
)
5456 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5457 RTX_FRAME_RELATED_P (insn
) = 1;
5459 /* The incoming return address (%o7) is saved in %i7. */
5460 add_reg_note (insn
, REG_CFA_REGISTER
,
5461 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5463 INCOMING_RETURN_ADDR_REGNUM
)));
5465 /* The window save event. */
5466 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5468 /* The CFA is %fp, the hard frame pointer. */
5469 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5470 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5471 INCOMING_FRAME_SP_OFFSET
));
5476 /* Generate an increment for the stack pointer. */
5479 gen_stack_pointer_inc (rtx increment
)
5481 return gen_rtx_SET (stack_pointer_rtx
,
5482 gen_rtx_PLUS (Pmode
,
5487 /* Expand the function prologue. The prologue is responsible for reserving
5488 storage for the frame, saving the call-saved registers and loading the
5489 GOT register if needed. */
5492 sparc_expand_prologue (void)
5497 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5498 on the final value of the flag means deferring the prologue/epilogue
5499 expansion until just before the second scheduling pass, which is too
5500 late to emit multiple epilogues or return insns.
5502 Of course we are making the assumption that the value of the flag
5503 will not change between now and its final value. Of the three parts
5504 of the formula, only the last one can reasonably vary. Let's take a
5505 closer look, after assuming that the first two ones are set to true
5506 (otherwise the last value is effectively silenced).
5508 If only_leaf_regs_used returns false, the global predicate will also
5509 be false so the actual frame size calculated below will be positive.
5510 As a consequence, the save_register_window insn will be emitted in
5511 the instruction stream; now this insn explicitly references %fp
5512 which is not a leaf register so only_leaf_regs_used will always
5513 return false subsequently.
5515 If only_leaf_regs_used returns true, we hope that the subsequent
5516 optimization passes won't cause non-leaf registers to pop up. For
5517 example, the regrename pass has special provisions to not rename to
5518 non-leaf registers in a leaf function. */
5519 sparc_leaf_function_p
5520 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5522 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5524 if (flag_stack_usage_info
)
5525 current_function_static_stack_size
= size
;
5527 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5529 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5531 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5532 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5533 size
- STACK_CHECK_PROTECT
);
5536 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5541 else if (sparc_leaf_function_p
)
5543 rtx size_int_rtx
= GEN_INT (-size
);
5546 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5547 else if (size
<= 8192)
5549 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5550 RTX_FRAME_RELATED_P (insn
) = 1;
5552 /* %sp is still the CFA register. */
5553 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5557 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5558 emit_move_insn (size_rtx
, size_int_rtx
);
5559 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5560 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5561 gen_stack_pointer_inc (size_int_rtx
));
5564 RTX_FRAME_RELATED_P (insn
) = 1;
5568 rtx size_int_rtx
= GEN_INT (-size
);
5571 emit_window_save (size_int_rtx
);
5572 else if (size
<= 8192)
5574 emit_window_save (GEN_INT (-4096));
5576 /* %sp is not the CFA register anymore. */
5577 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5579 /* Make sure no %fp-based store is issued until after the frame is
5580 established. The offset between the frame pointer and the stack
5581 pointer is calculated relative to the value of the stack pointer
5582 at the end of the function prologue, and moving instructions that
5583 access the stack via the frame pointer between the instructions
5584 that decrement the stack pointer could result in accessing the
5585 register window save area, which is volatile. */
5586 emit_insn (gen_frame_blockage ());
5590 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5591 emit_move_insn (size_rtx
, size_int_rtx
);
5592 emit_window_save (size_rtx
);
5596 if (sparc_leaf_function_p
)
5598 sparc_frame_base_reg
= stack_pointer_rtx
;
5599 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5603 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5604 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5607 if (sparc_n_global_fp_regs
> 0)
5608 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5609 sparc_frame_base_offset
5610 - sparc_apparent_frame_size
,
5613 /* Load the GOT register if needed. */
5614 if (crtl
->uses_pic_offset_table
)
5615 load_got_register ();
5617 /* Advertise that the data calculated just above are now valid. */
5618 sparc_prologue_data_valid_p
= true;
5621 /* Expand the function prologue. The prologue is responsible for reserving
5622 storage for the frame, saving the call-saved registers and loading the
5623 GOT register if needed. */
5626 sparc_flat_expand_prologue (void)
5631 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5633 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5635 if (flag_stack_usage_info
)
5636 current_function_static_stack_size
= size
;
5638 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5640 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5642 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5643 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5644 size
- STACK_CHECK_PROTECT
);
5647 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5650 if (sparc_save_local_in_regs_p
)
5651 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5658 rtx size_int_rtx
, size_rtx
;
5660 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5662 /* We establish the frame (i.e. decrement the stack pointer) first, even
5663 if we use a frame pointer, because we cannot clobber any call-saved
5664 registers, including the frame pointer, if we haven't created a new
5665 register save area, for the sake of compatibility with the ABI. */
5667 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5668 else if (size
<= 8192 && !frame_pointer_needed
)
5670 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5671 RTX_FRAME_RELATED_P (insn
) = 1;
5672 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5676 size_rtx
= gen_rtx_REG (Pmode
, 1);
5677 emit_move_insn (size_rtx
, size_int_rtx
);
5678 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5679 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5680 gen_stack_pointer_inc (size_int_rtx
));
5682 RTX_FRAME_RELATED_P (insn
) = 1;
5684 /* Ensure nothing is scheduled until after the frame is established. */
5685 emit_insn (gen_blockage ());
5687 if (frame_pointer_needed
)
5689 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
5690 gen_rtx_MINUS (Pmode
,
5693 RTX_FRAME_RELATED_P (insn
) = 1;
5695 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5696 gen_rtx_SET (hard_frame_pointer_rtx
,
5697 plus_constant (Pmode
, stack_pointer_rtx
,
5701 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5703 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5704 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5706 insn
= emit_move_insn (i7
, o7
);
5707 RTX_FRAME_RELATED_P (insn
) = 1;
5709 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
5711 /* Prevent this instruction from ever being considered dead,
5712 even if this function has no epilogue. */
5717 if (frame_pointer_needed
)
5719 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5720 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5724 sparc_frame_base_reg
= stack_pointer_rtx
;
5725 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5728 if (sparc_n_global_fp_regs
> 0)
5729 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5730 sparc_frame_base_offset
5731 - sparc_apparent_frame_size
,
5734 /* Load the GOT register if needed. */
5735 if (crtl
->uses_pic_offset_table
)
5736 load_got_register ();
5738 /* Advertise that the data calculated just above are now valid. */
5739 sparc_prologue_data_valid_p
= true;
5742 /* This function generates the assembly code for function entry, which boils
5743 down to emitting the necessary .register directives. */
5746 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5748 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5750 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5752 sparc_output_scratch_registers (file
);
5755 /* Expand the function epilogue, either normal or part of a sibcall.
5756 We emit all the instructions except the return or the call. */
5759 sparc_expand_epilogue (bool for_eh
)
5761 HOST_WIDE_INT size
= sparc_frame_size
;
5763 if (sparc_n_global_fp_regs
> 0)
5764 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5765 sparc_frame_base_offset
5766 - sparc_apparent_frame_size
,
5769 if (size
== 0 || for_eh
)
5771 else if (sparc_leaf_function_p
)
5774 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5775 else if (size
<= 8192)
5777 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5778 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5782 rtx reg
= gen_rtx_REG (Pmode
, 1);
5783 emit_move_insn (reg
, GEN_INT (size
));
5784 emit_insn (gen_stack_pointer_inc (reg
));
5789 /* Expand the function epilogue, either normal or part of a sibcall.
5790 We emit all the instructions except the return or the call. */
5793 sparc_flat_expand_epilogue (bool for_eh
)
5795 HOST_WIDE_INT size
= sparc_frame_size
;
5797 if (sparc_n_global_fp_regs
> 0)
5798 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5799 sparc_frame_base_offset
5800 - sparc_apparent_frame_size
,
5803 /* If we have a frame pointer, we'll need both to restore it before the
5804 frame is destroyed and use its current value in destroying the frame.
5805 Since we don't have an atomic way to do that in the flat window model,
5806 we save the current value into a temporary register (%g1). */
5807 if (frame_pointer_needed
&& !for_eh
)
5808 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5810 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5811 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5812 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5814 if (sparc_save_local_in_regs_p
)
5815 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5816 sparc_frame_base_offset
,
5819 if (size
== 0 || for_eh
)
5821 else if (frame_pointer_needed
)
5823 /* Make sure the frame is destroyed after everything else is done. */
5824 emit_insn (gen_blockage ());
5826 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5831 emit_insn (gen_blockage ());
5834 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5835 else if (size
<= 8192)
5837 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5838 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5842 rtx reg
= gen_rtx_REG (Pmode
, 1);
5843 emit_move_insn (reg
, GEN_INT (size
));
5844 emit_insn (gen_stack_pointer_inc (reg
));
5849 /* Return true if it is appropriate to emit `return' instructions in the
5850 body of a function. */
5853 sparc_can_use_return_insn_p (void)
5855 return sparc_prologue_data_valid_p
5856 && sparc_n_global_fp_regs
== 0
5858 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5859 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5862 /* This function generates the assembly code for function exit. */
5865 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5867 /* If the last two instructions of a function are "call foo; dslot;"
5868 the return address might point to the first instruction in the next
5869 function and we have to output a dummy nop for the sake of sane
5870 backtraces in such cases. This is pointless for sibling calls since
5871 the return address is explicitly adjusted. */
5873 rtx insn
, last_real_insn
;
5875 insn
= get_last_insn ();
5877 last_real_insn
= prev_real_insn (insn
);
5879 && NONJUMP_INSN_P (last_real_insn
)
5880 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5881 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5884 && CALL_P (last_real_insn
)
5885 && !SIBLING_CALL_P (last_real_insn
))
5886 fputs("\tnop\n", file
);
5888 sparc_output_deferred_case_vectors ();
5891 /* Output a 'restore' instruction. */
5894 output_restore (rtx pat
)
5900 fputs ("\t restore\n", asm_out_file
);
5904 gcc_assert (GET_CODE (pat
) == SET
);
5906 operands
[0] = SET_DEST (pat
);
5907 pat
= SET_SRC (pat
);
5909 switch (GET_CODE (pat
))
5912 operands
[1] = XEXP (pat
, 0);
5913 operands
[2] = XEXP (pat
, 1);
5914 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5917 operands
[1] = XEXP (pat
, 0);
5918 operands
[2] = XEXP (pat
, 1);
5919 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5922 operands
[1] = XEXP (pat
, 0);
5923 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5924 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5928 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5933 /* Output a return. */
5936 output_return (rtx_insn
*insn
)
5938 if (crtl
->calls_eh_return
)
5940 /* If the function uses __builtin_eh_return, the eh_return
5941 machinery occupies the delay slot. */
5942 gcc_assert (!final_sequence
);
5944 if (flag_delayed_branch
)
5946 if (!TARGET_FLAT
&& TARGET_V9
)
5947 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5951 fputs ("\trestore\n", asm_out_file
);
5953 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5956 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5961 fputs ("\trestore\n", asm_out_file
);
5963 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5964 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5967 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5969 /* This is a leaf or flat function so we don't have to bother restoring
5970 the register window, which frees us from dealing with the convoluted
5971 semantics of restore/return. We simply output the jump to the
5972 return address and the insn in the delay slot (if any). */
5974 return "jmp\t%%o7+%)%#";
5978 /* This is a regular function so we have to restore the register window.
5979 We may have a pending insn for the delay slot, which will be either
5980 combined with the 'restore' instruction or put in the delay slot of
5981 the 'return' instruction. */
5987 delay
= NEXT_INSN (insn
);
5990 pat
= PATTERN (delay
);
5992 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5994 epilogue_renumber (&pat
, 0);
5995 return "return\t%%i7+%)%#";
5999 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6000 output_restore (pat
);
6001 PATTERN (delay
) = gen_blockage ();
6002 INSN_CODE (delay
) = -1;
6007 /* The delay slot is empty. */
6009 return "return\t%%i7+%)\n\t nop";
6010 else if (flag_delayed_branch
)
6011 return "jmp\t%%i7+%)\n\t restore";
6013 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6020 /* Output a sibling call. */
6023 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6027 gcc_assert (flag_delayed_branch
);
6029 operands
[0] = call_operand
;
6031 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6033 /* This is a leaf or flat function so we don't have to bother restoring
6034 the register window. We simply output the jump to the function and
6035 the insn in the delay slot (if any). */
6037 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6040 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6043 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6044 it into branch if possible. */
6045 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6050 /* This is a regular function so we have to restore the register window.
6051 We may have a pending insn for the delay slot, which will be combined
6052 with the 'restore' instruction. */
6054 output_asm_insn ("call\t%a0, 0", operands
);
6058 rtx_insn
*delay
= NEXT_INSN (insn
);
6061 output_restore (PATTERN (delay
));
6063 PATTERN (delay
) = gen_blockage ();
6064 INSN_CODE (delay
) = -1;
6067 output_restore (NULL_RTX
);
6073 /* Functions for handling argument passing.
6075 For 32-bit, the first 6 args are normally in registers and the rest are
6076 pushed. Any arg that starts within the first 6 words is at least
6077 partially passed in a register unless its data type forbids.
6079 For 64-bit, the argument registers are laid out as an array of 16 elements
6080 and arguments are added sequentially. The first 6 int args and up to the
6081 first 16 fp args (depending on size) are passed in regs.
6083 Slot Stack Integral Float Float in structure Double Long Double
6084 ---- ----- -------- ----- ------------------ ------ -----------
6085 15 [SP+248] %f31 %f30,%f31 %d30
6086 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6087 13 [SP+232] %f27 %f26,%f27 %d26
6088 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6089 11 [SP+216] %f23 %f22,%f23 %d22
6090 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6091 9 [SP+200] %f19 %f18,%f19 %d18
6092 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6093 7 [SP+184] %f15 %f14,%f15 %d14
6094 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6095 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6096 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6097 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6098 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6099 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6100 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6102 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6104 Integral arguments are always passed as 64-bit quantities appropriately
6107 Passing of floating point values is handled as follows.
6108 If a prototype is in scope:
6109 If the value is in a named argument (i.e. not a stdarg function or a
6110 value not part of the `...') then the value is passed in the appropriate
6112 If the value is part of the `...' and is passed in one of the first 6
6113 slots then the value is passed in the appropriate int reg.
6114 If the value is part of the `...' and is not passed in one of the first 6
6115 slots then the value is passed in memory.
6116 If a prototype is not in scope:
6117 If the value is one of the first 6 arguments the value is passed in the
6118 appropriate integer reg and the appropriate fp reg.
6119 If the value is not one of the first 6 arguments the value is passed in
6120 the appropriate fp reg and in memory.
6123 Summary of the calling conventions implemented by GCC on the SPARC:
6126 size argument return value
6128 small integer <4 int. reg. int. reg.
6129 word 4 int. reg. int. reg.
6130 double word 8 int. reg. int. reg.
6132 _Complex small integer <8 int. reg. int. reg.
6133 _Complex word 8 int. reg. int. reg.
6134 _Complex double word 16 memory int. reg.
6136 vector integer <=8 int. reg. FP reg.
6137 vector integer >8 memory memory
6139 float 4 int. reg. FP reg.
6140 double 8 int. reg. FP reg.
6141 long double 16 memory memory
6143 _Complex float 8 memory FP reg.
6144 _Complex double 16 memory FP reg.
6145 _Complex long double 32 memory FP reg.
6147 vector float any memory memory
6149 aggregate any memory memory
6154 size argument return value
6156 small integer <8 int. reg. int. reg.
6157 word 8 int. reg. int. reg.
6158 double word 16 int. reg. int. reg.
6160 _Complex small integer <16 int. reg. int. reg.
6161 _Complex word 16 int. reg. int. reg.
6162 _Complex double word 32 memory int. reg.
6164 vector integer <=16 FP reg. FP reg.
6165 vector integer 16<s<=32 memory FP reg.
6166 vector integer >32 memory memory
6168 float 4 FP reg. FP reg.
6169 double 8 FP reg. FP reg.
6170 long double 16 FP reg. FP reg.
6172 _Complex float 8 FP reg. FP reg.
6173 _Complex double 16 FP reg. FP reg.
6174 _Complex long double 32 memory FP reg.
6176 vector float <=16 FP reg. FP reg.
6177 vector float 16<s<=32 memory FP reg.
6178 vector float >32 memory memory
6180 aggregate <=16 reg. reg.
6181 aggregate 16<s<=32 memory reg.
6182 aggregate >32 memory memory
6186 Note #1: complex floating-point types follow the extended SPARC ABIs as
6187 implemented by the Sun compiler.
6189 Note #2: integral vector types follow the scalar floating-point types
6190 conventions to match what is implemented by the Sun VIS SDK.
6192 Note #3: floating-point vector types follow the aggregate types
6196 /* Maximum number of int regs for args. */
6197 #define SPARC_INT_ARG_MAX 6
6198 /* Maximum number of fp regs for args. */
6199 #define SPARC_FP_ARG_MAX 16
6200 /* Number of words (partially) occupied for a given size in units. */
6201 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6203 /* Handle the INIT_CUMULATIVE_ARGS macro.
6204 Initialize a variable CUM of type CUMULATIVE_ARGS
6205 for a call to a function whose data type is FNTYPE.
6206 For a library call, FNTYPE is 0. */
6209 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6212 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6213 cum
->libcall_p
= !fntype
;
6216 /* Handle promotion of pointer and integer arguments. */
6219 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6220 int *punsignedp
, const_tree
, int)
6222 if (type
&& POINTER_TYPE_P (type
))
6224 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6228 /* Integral arguments are passed as full words, as per the ABI. */
6229 if (GET_MODE_CLASS (mode
) == MODE_INT
6230 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6236 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6239 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6241 return TARGET_ARCH64
? true : false;
6244 /* Traverse the record TYPE recursively and call FUNC on its fields.
6245 NAMED is true if this is for a named parameter. DATA is passed
6246 to FUNC for each field. OFFSET is the starting position and
6247 PACKED is true if we are inside a packed record. */
6249 template <typename T
, void Func (const_tree
, HOST_WIDE_INT
, bool, T
*)>
6251 traverse_record_type (const_tree type
, bool named
, T
*data
,
6252 HOST_WIDE_INT offset
= 0, bool packed
= false)
6254 /* The ABI obviously doesn't specify how packed structures are passed.
6255 These are passed in integer regs if possible, otherwise memory. */
6257 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6258 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6264 /* Walk the real fields, but skip those with no size or a zero size.
6265 ??? Fields with variable offset are handled as having zero offset. */
6266 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6267 if (TREE_CODE (field
) == FIELD_DECL
)
6269 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6272 HOST_WIDE_INT bitpos
= offset
;
6273 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6274 bitpos
+= int_bit_position (field
);
6276 tree field_type
= TREE_TYPE (field
);
6277 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6278 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6283 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6284 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6290 /* Handle recursive register classifying for structure layout. */
6294 bool int_regs
; /* true if field eligible to int registers. */
6295 bool fp_regs
; /* true if field eligible to FP registers. */
6296 bool fp_regs_in_first_word
; /* true if such field in first word. */
6299 /* A subroutine of function_arg_slotno. Classify the field. */
6302 classify_registers (const_tree
, HOST_WIDE_INT bitpos
, bool fp
,
6303 classify_data_t
*data
)
6307 data
->fp_regs
= true;
6308 if (bitpos
< BITS_PER_WORD
)
6309 data
->fp_regs_in_first_word
= true;
6312 data
->int_regs
= true;
6315 /* Compute the slot number to pass an argument in.
6316 Return the slot number or -1 if passing on the stack.
6318 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6319 the preceding args and about the function being called.
6320 MODE is the argument's machine mode.
6321 TYPE is the data type of the argument (as a tree).
6322 This is null for libcalls where that information may
6324 NAMED is nonzero if this argument is a named parameter
6325 (otherwise it is an extra parameter matching an ellipsis).
6326 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6327 *PREGNO records the register number to use if scalar type.
6328 *PPADDING records the amount of padding needed in words. */
6331 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6332 const_tree type
, bool named
, bool incoming
,
6333 int *pregno
, int *ppadding
)
6335 int regbase
= (incoming
6336 ? SPARC_INCOMING_INT_ARG_FIRST
6337 : SPARC_OUTGOING_INT_ARG_FIRST
);
6338 int slotno
= cum
->words
;
6339 enum mode_class mclass
;
6344 if (type
&& TREE_ADDRESSABLE (type
))
6350 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6353 /* For SPARC64, objects requiring 16-byte alignment get it. */
6355 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6356 && (slotno
& 1) != 0)
6357 slotno
++, *ppadding
= 1;
6359 mclass
= GET_MODE_CLASS (mode
);
6360 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6362 /* Vector types deserve special treatment because they are
6363 polymorphic wrt their mode, depending upon whether VIS
6364 instructions are enabled. */
6365 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6367 /* The SPARC port defines no floating-point vector modes. */
6368 gcc_assert (mode
== BLKmode
);
6372 /* Integral vector types should either have a vector
6373 mode or an integral mode, because we are guaranteed
6374 by pass_by_reference that their size is not greater
6375 than 16 bytes and TImode is 16-byte wide. */
6376 gcc_assert (mode
!= BLKmode
);
6378 /* Vector integers are handled like floats according to
6380 mclass
= MODE_FLOAT
;
6387 case MODE_COMPLEX_FLOAT
:
6388 case MODE_VECTOR_INT
:
6389 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6391 /* If all arg slots are filled, then must pass on stack. */
6392 if (slotno
>= SPARC_FP_ARG_MAX
)
6395 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6396 /* Arguments filling only one single FP register are
6397 right-justified in the outer double FP register. */
6398 if (GET_MODE_SIZE (mode
) <= 4)
6405 case MODE_COMPLEX_INT
:
6406 /* If all arg slots are filled, then must pass on stack. */
6407 if (slotno
>= SPARC_INT_ARG_MAX
)
6410 regno
= regbase
+ slotno
;
6414 if (mode
== VOIDmode
)
6415 /* MODE is VOIDmode when generating the actual call. */
6418 gcc_assert (mode
== BLKmode
);
6422 || (TREE_CODE (type
) != RECORD_TYPE
6423 && TREE_CODE (type
) != VECTOR_TYPE
))
6425 /* If all arg slots are filled, then must pass on stack. */
6426 if (slotno
>= SPARC_INT_ARG_MAX
)
6429 regno
= regbase
+ slotno
;
6431 else /* TARGET_ARCH64 && type */
6433 /* If all arg slots are filled, then must pass on stack. */
6434 if (slotno
>= SPARC_FP_ARG_MAX
)
6437 if (TREE_CODE (type
) == RECORD_TYPE
)
6439 classify_data_t data
= { false, false, false };
6440 traverse_record_type
<classify_data_t
, classify_registers
>
6441 (type
, named
, &data
);
6443 /* If all slots are filled except for the last one, but there
6444 is no FP field in the first word, then must pass on stack. */
6446 && !data
.fp_regs_in_first_word
6447 && slotno
>= SPARC_FP_ARG_MAX
- 1)
6450 /* If there are only int args and all int slots are filled,
6451 then must pass on stack. */
6454 && slotno
>= SPARC_INT_ARG_MAX
)
6458 /* PREGNO isn't set since both int and FP regs can be used. */
6471 /* Handle recursive register counting/assigning for structure layout. */
6475 int slotno
; /* slot number of the argument. */
6476 int regbase
; /* regno of the base register. */
6477 int intoffset
; /* offset of the first pending integer field. */
6478 int nregs
; /* number of words passed in registers. */
6479 bool stack
; /* true if part of the argument is on the stack. */
6480 rtx ret
; /* return expression being built. */
6483 /* A subroutine of function_arg_record_value. Compute the number of integer
6484 registers to be assigned between PARMS->intoffset and BITPOS. Return
6485 true if at least one integer register is assigned or false otherwise. */
6488 compute_int_layout (HOST_WIDE_INT bitpos
, assign_data_t
*data
, int *pnregs
)
6490 if (data
->intoffset
< 0)
6493 const int intoffset
= data
->intoffset
;
6494 data
->intoffset
= -1;
6496 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6497 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
6498 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
6499 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
6501 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
6503 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
6505 /* We need to pass this field (partly) on the stack. */
6516 /* A subroutine of function_arg_record_value. Compute the number and the mode
6517 of the FP registers to be assigned for FIELD. Return true if at least one
6518 FP register is assigned or false otherwise. */
6521 compute_fp_layout (const_tree field
, HOST_WIDE_INT bitpos
,
6522 assign_data_t
*data
,
6523 int *pnregs
, machine_mode
*pmode
)
6525 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6526 machine_mode mode
= DECL_MODE (field
);
6529 /* Slots are counted as words while regs are counted as having the size of
6530 the (inner) mode. */
6531 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
&& mode
== BLKmode
)
6533 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6534 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6536 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6538 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6544 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
6546 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
6548 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
6549 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
6551 /* We need to pass this field (partly) on the stack. */
6563 /* A subroutine of function_arg_record_value. Count the number of registers
6564 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
6567 count_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6568 assign_data_t
*data
)
6575 if (compute_int_layout (bitpos
, data
, &nregs
))
6576 data
->nregs
+= nregs
;
6578 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6579 data
->nregs
+= nregs
;
6583 if (data
->intoffset
< 0)
6584 data
->intoffset
= bitpos
;
6588 /* A subroutine of function_arg_record_value. Assign the bits of the
6589 structure between PARMS->intoffset and BITPOS to integer registers. */
6592 assign_int_registers (HOST_WIDE_INT bitpos
, assign_data_t
*data
)
6594 int intoffset
= data
->intoffset
;
6598 if (!compute_int_layout (bitpos
, data
, &nregs
))
6601 /* If this is the trailing part of a word, only load that much into
6602 the register. Otherwise load the whole register. Note that in
6603 the latter case we may pick up unwanted bits. It's not a problem
6604 at the moment but may wish to revisit. */
6605 if (intoffset
% BITS_PER_WORD
!= 0)
6606 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
6611 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6612 unsigned int regno
= data
->regbase
+ this_slotno
;
6613 intoffset
/= BITS_PER_UNIT
;
6617 rtx reg
= gen_rtx_REG (mode
, regno
);
6618 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6619 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6623 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
6625 while (--nregs
> 0);
6628 /* A subroutine of function_arg_record_value. Assign FIELD at position
6629 BITPOS to FP registers. */
6632 assign_fp_registers (const_tree field
, HOST_WIDE_INT bitpos
,
6633 assign_data_t
*data
)
6638 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6641 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6642 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6643 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6645 int pos
= bitpos
/ BITS_PER_UNIT
;
6649 rtx reg
= gen_rtx_REG (mode
, regno
);
6650 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6651 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6653 regno
+= GET_MODE_SIZE (mode
) / 4;
6654 pos
+= GET_MODE_SIZE (mode
);
6656 while (--nregs
> 0);
6659 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
6660 the structure between PARMS->intoffset and BITPOS to registers. */
6663 assign_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6664 assign_data_t
*data
)
6668 assign_int_registers (bitpos
, data
);
6670 assign_fp_registers (field
, bitpos
, data
);
6674 if (data
->intoffset
< 0)
6675 data
->intoffset
= bitpos
;
6679 /* Used by function_arg and sparc_function_value_1 to implement the complex
6680 conventions of the 64-bit ABI for passing and returning structures.
6681 Return an expression valid as a return value for the FUNCTION_ARG
6682 and TARGET_FUNCTION_VALUE.
6684 TYPE is the data type of the argument (as a tree).
6685 This is null for libcalls where that information may
6687 MODE is the argument's machine mode.
6688 SLOTNO is the index number of the argument's slot in the parameter array.
6689 NAMED is true if this argument is a named parameter
6690 (otherwise it is an extra parameter matching an ellipsis).
6691 REGBASE is the regno of the base register for the parameter array. */
6694 function_arg_record_value (const_tree type
, machine_mode mode
,
6695 int slotno
, bool named
, int regbase
)
6697 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6701 data
.slotno
= slotno
;
6702 data
.regbase
= regbase
;
6704 /* Count how many registers we need. */
6708 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
6710 /* Take into account pending integer fields. */
6711 if (compute_int_layout (typesize
* BITS_PER_UNIT
, &data
, &nregs
))
6712 data
.nregs
+= nregs
;
6714 /* Allocate the vector and handle some annoying special cases. */
6719 /* ??? Empty structure has no value? Duh? */
6722 /* Though there's nothing really to store, return a word register
6723 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6724 leads to breakage due to the fact that there are zero bytes to
6726 return gen_rtx_REG (mode
, regbase
);
6729 /* ??? C++ has structures with no fields, and yet a size. Give up
6730 for now and pass everything back in integer registers. */
6731 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6732 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6733 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6736 gcc_assert (nregs
> 0);
6738 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
6740 /* If at least one field must be passed on the stack, generate
6741 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6742 also be passed on the stack. We can't do much better because the
6743 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6744 of structures for which the fields passed exclusively in registers
6745 are not at the beginning of the structure. */
6747 XVECEXP (data
.ret
, 0, 0)
6748 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6750 /* Assign the registers. */
6753 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
6755 /* Assign pending integer fields. */
6756 assign_int_registers (typesize
* BITS_PER_UNIT
, &data
);
6758 gcc_assert (data
.nregs
== nregs
);
6763 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6764 of the 64-bit ABI for passing and returning unions.
6765 Return an expression valid as a return value for the FUNCTION_ARG
6766 and TARGET_FUNCTION_VALUE.
6768 SIZE is the size in bytes of the union.
6769 MODE is the argument's machine mode.
6770 REGNO is the hard register the union will be passed in. */
6773 function_arg_union_value (int size
, machine_mode mode
, int slotno
,
6776 int nwords
= CEIL_NWORDS (size
), i
;
6779 /* See comment in previous function for empty structures. */
6781 return gen_rtx_REG (mode
, regno
);
6783 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6786 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6788 for (i
= 0; i
< nwords
; i
++)
6790 /* Unions are passed left-justified. */
6791 XVECEXP (regs
, 0, i
)
6792 = gen_rtx_EXPR_LIST (VOIDmode
,
6793 gen_rtx_REG (word_mode
, regno
),
6794 GEN_INT (UNITS_PER_WORD
* i
));
6801 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6802 for passing and returning BLKmode vectors.
6803 Return an expression valid as a return value for the FUNCTION_ARG
6804 and TARGET_FUNCTION_VALUE.
6806 SIZE is the size in bytes of the vector.
6807 REGNO is the FP hard register the vector will be passed in. */
6810 function_arg_vector_value (int size
, int regno
)
6812 const int nregs
= MAX (1, size
/ 8);
6813 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6816 XVECEXP (regs
, 0, 0)
6817 = gen_rtx_EXPR_LIST (VOIDmode
,
6818 gen_rtx_REG (SImode
, regno
),
6821 for (int i
= 0; i
< nregs
; i
++)
6822 XVECEXP (regs
, 0, i
)
6823 = gen_rtx_EXPR_LIST (VOIDmode
,
6824 gen_rtx_REG (DImode
, regno
+ 2*i
),
6830 /* Determine where to put an argument to a function.
6831 Value is zero to push the argument on the stack,
6832 or a hard register in which to store the argument.
6834 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6835 the preceding args and about the function being called.
6836 MODE is the argument's machine mode.
6837 TYPE is the data type of the argument (as a tree).
6838 This is null for libcalls where that information may
6840 NAMED is true if this argument is a named parameter
6841 (otherwise it is an extra parameter matching an ellipsis).
6842 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6843 TARGET_FUNCTION_INCOMING_ARG. */
6846 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
6847 const_tree type
, bool named
, bool incoming
)
6849 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6851 int regbase
= (incoming
6852 ? SPARC_INCOMING_INT_ARG_FIRST
6853 : SPARC_OUTGOING_INT_ARG_FIRST
);
6854 int slotno
, regno
, padding
;
6855 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6857 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming
,
6862 /* Vector types deserve special treatment because they are polymorphic wrt
6863 their mode, depending upon whether VIS instructions are enabled. */
6864 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6866 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6867 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6868 || (TARGET_ARCH64
&& size
<= 16));
6870 if (mode
== BLKmode
)
6871 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
+ 2*slotno
);
6873 mclass
= MODE_FLOAT
;
6877 return gen_rtx_REG (mode
, regno
);
6879 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6880 and are promoted to registers if possible. */
6881 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6883 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6884 gcc_assert (size
<= 16);
6886 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6889 /* Unions up to 16 bytes in size are passed in integer registers. */
6890 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6892 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6893 gcc_assert (size
<= 16);
6895 return function_arg_union_value (size
, mode
, slotno
, regno
);
6898 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6899 but also have the slot allocated for them.
6900 If no prototype is in scope fp values in register slots get passed
6901 in two places, either fp regs and int regs or fp regs and memory. */
6902 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6903 && SPARC_FP_REG_P (regno
))
6905 rtx reg
= gen_rtx_REG (mode
, regno
);
6906 if (cum
->prototype_p
|| cum
->libcall_p
)
6912 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6916 /* On incoming, we don't need to know that the value
6917 is passed in %f0 and %i0, and it confuses other parts
6918 causing needless spillage even on the simplest cases. */
6922 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6923 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6925 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6926 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6928 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6932 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6933 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6934 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6939 /* All other aggregate types are passed in an integer register in a mode
6940 corresponding to the size of the type. */
6941 else if (type
&& AGGREGATE_TYPE_P (type
))
6943 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6944 gcc_assert (size
<= 16);
6946 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6949 return gen_rtx_REG (mode
, regno
);
6952 /* Handle the TARGET_FUNCTION_ARG target hook. */
6955 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
6956 const_tree type
, bool named
)
6958 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6961 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6964 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
6965 const_tree type
, bool named
)
6967 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6970 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6973 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
6975 return ((TARGET_ARCH64
6976 && (GET_MODE_ALIGNMENT (mode
) == 128
6977 || (type
&& TYPE_ALIGN (type
) == 128)))
6982 /* For an arg passed partly in registers and partly in memory,
6983 this is the number of bytes of registers used.
6984 For args passed entirely in registers or entirely in memory, zero.
6986 Any arg that starts in the first 6 regs but won't entirely fit in them
6987 needs partial registers on v8. On v9, structures with integer
6988 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6989 values that begin in the last fp reg [where "last fp reg" varies with the
6990 mode] will be split between that reg and memory. */
6993 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
6994 tree type
, bool named
)
6996 int slotno
, regno
, padding
;
6998 /* We pass false for incoming here, it doesn't matter. */
6999 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7000 false, ®no
, &padding
);
7007 if ((slotno
+ (mode
== BLKmode
7008 ? CEIL_NWORDS (int_size_in_bytes (type
))
7009 : CEIL_NWORDS (GET_MODE_SIZE (mode
))))
7010 > SPARC_INT_ARG_MAX
)
7011 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7015 /* We are guaranteed by pass_by_reference that the size of the
7016 argument is not greater than 16 bytes, so we only need to return
7017 one word if the argument is partially passed in registers. */
7019 if (type
&& AGGREGATE_TYPE_P (type
))
7021 int size
= int_size_in_bytes (type
);
7023 if (size
> UNITS_PER_WORD
7024 && (slotno
== SPARC_INT_ARG_MAX
- 1
7025 || slotno
== SPARC_FP_ARG_MAX
- 1))
7026 return UNITS_PER_WORD
;
7028 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7029 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7030 && ! (TARGET_FPU
&& named
)))
7032 /* The complex types are passed as packed types. */
7033 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7034 && slotno
== SPARC_INT_ARG_MAX
- 1)
7035 return UNITS_PER_WORD
;
7037 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7039 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7041 return UNITS_PER_WORD
;
7048 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7049 Specify whether to pass the argument by reference. */
7052 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7053 machine_mode mode
, const_tree type
,
7054 bool named ATTRIBUTE_UNUSED
)
7057 /* Original SPARC 32-bit ABI says that structures and unions,
7058 and quad-precision floats are passed by reference. For Pascal,
7059 also pass arrays by reference. All other base types are passed
7062 Extended ABI (as implemented by the Sun compiler) says that all
7063 complex floats are passed by reference. Pass complex integers
7064 in registers up to 8 bytes. More generally, enforce the 2-word
7065 cap for passing arguments in registers.
7067 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7068 integers are passed like floats of the same size, that is in
7069 registers up to 8 bytes. Pass all vector floats by reference
7070 like structure and unions. */
7071 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7073 /* Catch CDImode, TFmode, DCmode and TCmode. */
7074 || GET_MODE_SIZE (mode
) > 8
7076 && TREE_CODE (type
) == VECTOR_TYPE
7077 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7079 /* Original SPARC 64-bit ABI says that structures and unions
7080 smaller than 16 bytes are passed in registers, as well as
7081 all other base types.
7083 Extended ABI (as implemented by the Sun compiler) says that
7084 complex floats are passed in registers up to 16 bytes. Pass
7085 all complex integers in registers up to 16 bytes. More generally,
7086 enforce the 2-word cap for passing arguments in registers.
7088 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7089 integers are passed like floats of the same size, that is in
7090 registers (up to 16 bytes). Pass all vector floats like structure
7093 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7094 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7095 /* Catch CTImode and TCmode. */
7096 || GET_MODE_SIZE (mode
) > 16);
7099 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7100 Update the data in CUM to advance over an argument
7101 of mode MODE and data type TYPE.
7102 TYPE is null for libcalls where that information may not be available. */
7105 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7106 const_tree type
, bool named
)
7108 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7111 /* We pass false for incoming here, it doesn't matter. */
7112 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7114 /* If argument requires leading padding, add it. */
7115 cum
->words
+= padding
;
7118 cum
->words
+= (mode
== BLKmode
7119 ? CEIL_NWORDS (int_size_in_bytes (type
))
7120 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7123 if (type
&& AGGREGATE_TYPE_P (type
))
7125 int size
= int_size_in_bytes (type
);
7129 else if (size
<= 16)
7131 else /* passed by reference */
7135 cum
->words
+= (mode
== BLKmode
7136 ? CEIL_NWORDS (int_size_in_bytes (type
))
7137 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7141 /* Handle the FUNCTION_ARG_PADDING macro.
7142 For the 64 bit ABI structs are always stored left shifted in their
7146 function_arg_padding (machine_mode mode
, const_tree type
)
7148 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7151 /* Fall back to the default. */
7152 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7155 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7156 Specify whether to return the return value in memory. */
7159 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7162 /* Original SPARC 32-bit ABI says that structures and unions,
7163 and quad-precision floats are returned in memory. All other
7164 base types are returned in registers.
7166 Extended ABI (as implemented by the Sun compiler) says that
7167 all complex floats are returned in registers (8 FP registers
7168 at most for '_Complex long double'). Return all complex integers
7169 in registers (4 at most for '_Complex long long').
7171 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7172 integers are returned like floats of the same size, that is in
7173 registers up to 8 bytes and in memory otherwise. Return all
7174 vector floats in memory like structure and unions; note that
7175 they always have BLKmode like the latter. */
7176 return (TYPE_MODE (type
) == BLKmode
7177 || TYPE_MODE (type
) == TFmode
7178 || (TREE_CODE (type
) == VECTOR_TYPE
7179 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7181 /* Original SPARC 64-bit ABI says that structures and unions
7182 smaller than 32 bytes are returned in registers, as well as
7183 all other base types.
7185 Extended ABI (as implemented by the Sun compiler) says that all
7186 complex floats are returned in registers (8 FP registers at most
7187 for '_Complex long double'). Return all complex integers in
7188 registers (4 at most for '_Complex TItype').
7190 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7191 integers are returned like floats of the same size, that is in
7192 registers. Return all vector floats like structure and unions;
7193 note that they always have BLKmode like the latter. */
7194 return (TYPE_MODE (type
) == BLKmode
7195 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7198 /* Handle the TARGET_STRUCT_VALUE target hook.
7199 Return where to find the structure return value address. */
7202 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7211 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7212 STRUCT_VALUE_OFFSET
));
7214 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7215 STRUCT_VALUE_OFFSET
));
7217 /* Only follow the SPARC ABI for fixed-size structure returns.
7218 Variable size structure returns are handled per the normal
7219 procedures in GCC. This is enabled by -mstd-struct-return */
7221 && sparc_std_struct_return
7222 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7223 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7225 /* We must check and adjust the return address, as it is optional
7226 as to whether the return object is really provided. */
7227 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7228 rtx scratch
= gen_reg_rtx (SImode
);
7229 rtx_code_label
*endlab
= gen_label_rtx ();
7231 /* Calculate the return object size. */
7232 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7233 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7234 /* Construct a temporary return value. */
7236 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7238 /* Implement SPARC 32-bit psABI callee return struct checking:
7240 Fetch the instruction where we will return to and see if
7241 it's an unimp instruction (the most significant 10 bits
7243 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7244 plus_constant (Pmode
,
7246 /* Assume the size is valid and pre-adjust. */
7247 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7248 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7250 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7251 /* Write the address of the memory pointed to by temp_val into
7252 the memory pointed to by mem. */
7253 emit_move_insn (mem
, XEXP (temp_val
, 0));
7254 emit_label (endlab
);
7261 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7262 For v9, function return values are subject to the same rules as arguments,
7263 except that up to 32 bytes may be returned in registers. */
7266 sparc_function_value_1 (const_tree type
, machine_mode mode
,
7269 /* Beware that the two values are swapped here wrt function_arg. */
7270 int regbase
= (outgoing
7271 ? SPARC_INCOMING_INT_ARG_FIRST
7272 : SPARC_OUTGOING_INT_ARG_FIRST
);
7273 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7276 /* Vector types deserve special treatment because they are polymorphic wrt
7277 their mode, depending upon whether VIS instructions are enabled. */
7278 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7280 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7281 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7282 || (TARGET_ARCH64
&& size
<= 32));
7284 if (mode
== BLKmode
)
7285 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
);
7287 mclass
= MODE_FLOAT
;
7290 if (TARGET_ARCH64
&& type
)
7292 /* Structures up to 32 bytes in size are returned in registers. */
7293 if (TREE_CODE (type
) == RECORD_TYPE
)
7295 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7296 gcc_assert (size
<= 32);
7298 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7301 /* Unions up to 32 bytes in size are returned in integer registers. */
7302 else if (TREE_CODE (type
) == UNION_TYPE
)
7304 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7305 gcc_assert (size
<= 32);
7307 return function_arg_union_value (size
, mode
, 0, regbase
);
7310 /* Objects that require it are returned in FP registers. */
7311 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7314 /* All other aggregate types are returned in an integer register in a
7315 mode corresponding to the size of the type. */
7316 else if (AGGREGATE_TYPE_P (type
))
7318 /* All other aggregate types are passed in an integer register
7319 in a mode corresponding to the size of the type. */
7320 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7321 gcc_assert (size
<= 32);
7323 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7325 /* ??? We probably should have made the same ABI change in
7326 3.4.0 as the one we made for unions. The latter was
7327 required by the SCD though, while the former is not
7328 specified, so we favored compatibility and efficiency.
7330 Now we're stuck for aggregates larger than 16 bytes,
7331 because OImode vanished in the meantime. Let's not
7332 try to be unduly clever, and simply follow the ABI
7333 for unions in that case. */
7334 if (mode
== BLKmode
)
7335 return function_arg_union_value (size
, mode
, 0, regbase
);
7340 /* We should only have pointer and integer types at this point. This
7341 must match sparc_promote_function_mode. */
7342 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7346 /* We should only have pointer and integer types at this point, except with
7347 -freg-struct-return. This must match sparc_promote_function_mode. */
7348 else if (TARGET_ARCH32
7349 && !(type
&& AGGREGATE_TYPE_P (type
))
7350 && mclass
== MODE_INT
7351 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7354 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7355 regno
= SPARC_FP_ARG_FIRST
;
7359 return gen_rtx_REG (mode
, regno
);
7362 /* Handle TARGET_FUNCTION_VALUE.
7363 On the SPARC, the value is found in the first "output" register, but the
7364 called function leaves it in the first "input" register. */
7367 sparc_function_value (const_tree valtype
,
7368 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7371 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7374 /* Handle TARGET_LIBCALL_VALUE. */
7377 sparc_libcall_value (machine_mode mode
,
7378 const_rtx fun ATTRIBUTE_UNUSED
)
7380 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7383 /* Handle FUNCTION_VALUE_REGNO_P.
7384 On the SPARC, the first "output" reg is used for integer values, and the
7385 first floating point register is used for floating point values. */
7388 sparc_function_value_regno_p (const unsigned int regno
)
7390 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7393 /* Do what is necessary for `va_start'. We look at the current function
7394 to determine if stdarg or varargs is used and return the address of
7395 the first unnamed parameter. */
7398 sparc_builtin_saveregs (void)
7400 int first_reg
= crtl
->args
.info
.words
;
7404 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7405 emit_move_insn (gen_rtx_MEM (word_mode
,
7406 gen_rtx_PLUS (Pmode
,
7408 GEN_INT (FIRST_PARM_OFFSET (0)
7411 gen_rtx_REG (word_mode
,
7412 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7414 address
= gen_rtx_PLUS (Pmode
,
7416 GEN_INT (FIRST_PARM_OFFSET (0)
7417 + UNITS_PER_WORD
* first_reg
));
7422 /* Implement `va_start' for stdarg. */
7425 sparc_va_start (tree valist
, rtx nextarg
)
7427 nextarg
= expand_builtin_saveregs ();
7428 std_expand_builtin_va_start (valist
, nextarg
);
7431 /* Implement `va_arg' for stdarg. */
7434 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7437 HOST_WIDE_INT size
, rsize
, align
;
7440 tree ptrtype
= build_pointer_type (type
);
7442 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7445 size
= rsize
= UNITS_PER_WORD
;
7451 size
= int_size_in_bytes (type
);
7452 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7457 /* For SPARC64, objects requiring 16-byte alignment get it. */
7458 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7459 align
= 2 * UNITS_PER_WORD
;
7461 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7462 are left-justified in their slots. */
7463 if (AGGREGATE_TYPE_P (type
))
7466 size
= rsize
= UNITS_PER_WORD
;
7476 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7477 incr
= fold_convert (sizetype
, incr
);
7478 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7480 incr
= fold_convert (ptr_type_node
, incr
);
7483 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7486 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7487 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7491 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7492 addr
= build_va_arg_indirect_ref (addr
);
7495 /* If the address isn't aligned properly for the type, we need a temporary.
7496 FIXME: This is inefficient, usually we can do this in registers. */
7497 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7499 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7500 tree dest_addr
= build_fold_addr_expr (tmp
);
7501 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7502 3, dest_addr
, addr
, size_int (rsize
));
7503 TREE_ADDRESSABLE (tmp
) = 1;
7504 gimplify_and_add (copy
, pre_p
);
7509 addr
= fold_convert (ptrtype
, addr
);
7511 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7512 gimplify_assign (valist
, incr
, post_p
);
7514 return build_va_arg_indirect_ref (addr
);
7517 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7518 Specify whether the vector mode is supported by the hardware. */
7521 sparc_vector_mode_supported_p (machine_mode mode
)
7523 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7526 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7529 sparc_preferred_simd_mode (machine_mode mode
)
7547 /* Return the string to output an unconditional branch to LABEL, which is
7548 the operand number of the label.
7550 DEST is the destination insn (i.e. the label), INSN is the source. */
7553 output_ubranch (rtx dest
, rtx_insn
*insn
)
7555 static char string
[64];
7556 bool v9_form
= false;
7560 /* Even if we are trying to use cbcond for this, evaluate
7561 whether we can use V9 branches as our backup plan. */
7564 if (INSN_ADDRESSES_SET_P ())
7565 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7566 - INSN_ADDRESSES (INSN_UID (insn
)));
7568 /* Leave some instructions for "slop". */
7569 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7574 bool emit_nop
= emit_cbcond_nop (insn
);
7578 if (delta
< -500 || delta
> 500)
7584 rval
= "ba,a,pt\t%%xcc, %l0";
7591 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7593 rval
= "cwbe\t%%g0, %%g0, %l0";
7599 strcpy (string
, "ba%*,pt\t%%xcc, ");
7601 strcpy (string
, "b%*\t");
7603 p
= strchr (string
, '\0');
7614 /* Return the string to output a conditional branch to LABEL, which is
7615 the operand number of the label. OP is the conditional expression.
7616 XEXP (OP, 0) is assumed to be a condition code register (integer or
7617 floating point) and its mode specifies what kind of comparison we made.
7619 DEST is the destination insn (i.e. the label), INSN is the source.
7621 REVERSED is nonzero if we should reverse the sense of the comparison.
7623 ANNUL is nonzero if we should generate an annulling branch. */
7626 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7629 static char string
[64];
7630 enum rtx_code code
= GET_CODE (op
);
7631 rtx cc_reg
= XEXP (op
, 0);
7632 machine_mode mode
= GET_MODE (cc_reg
);
7633 const char *labelno
, *branch
;
7634 int spaces
= 8, far
;
7637 /* v9 branches are limited to +-1MB. If it is too far away,
7650 fbne,a,pn %fcc2, .LC29
7658 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7661 /* Reversal of FP compares takes care -- an ordered compare
7662 becomes an unordered compare and vice versa. */
7663 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7664 code
= reverse_condition_maybe_unordered (code
);
7666 code
= reverse_condition (code
);
7669 /* Start by writing the branch condition. */
7670 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7721 /* ??? !v9: FP branches cannot be preceded by another floating point
7722 insn. Because there is currently no concept of pre-delay slots,
7723 we can fix this only by always emitting a nop before a floating
7728 strcpy (string
, "nop\n\t");
7729 strcat (string
, branch
);
7742 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7754 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7775 strcpy (string
, branch
);
7777 spaces
-= strlen (branch
);
7778 p
= strchr (string
, '\0');
7780 /* Now add the annulling, the label, and a possible noop. */
7793 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7795 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7796 - INSN_ADDRESSES (INSN_UID (insn
)));
7797 /* Leave some instructions for "slop". */
7798 if (delta
< -260000 || delta
>= 260000)
7802 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7804 static char v9_fcc_labelno
[] = "%%fccX, ";
7805 /* Set the char indicating the number of the fcc reg to use. */
7806 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7807 labelno
= v9_fcc_labelno
;
7810 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7814 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7816 labelno
= "%%xcc, ";
7821 labelno
= "%%icc, ";
7826 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7829 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7842 strcpy (p
, labelno
);
7843 p
= strchr (p
, '\0');
7846 strcpy (p
, ".+12\n\t nop\n\tb\t");
7847 /* Skip the next insn if requested or
7848 if we know that it will be a nop. */
7849 if (annul
|| ! final_sequence
)
7863 /* Emit a library call comparison between floating point X and Y.
7864 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7865 Return the new operator to be used in the comparison sequence.
7867 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7868 values as arguments instead of the TFmode registers themselves,
7869 that's why we cannot call emit_float_lib_cmp. */
7872 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7875 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7877 enum rtx_code new_comparison
;
7882 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7886 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7890 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7894 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7898 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7902 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7913 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7924 tree expr
= MEM_EXPR (x
);
7926 mark_addressable (expr
);
7931 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7932 emit_move_insn (slot0
, x
);
7937 tree expr
= MEM_EXPR (y
);
7939 mark_addressable (expr
);
7944 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7945 emit_move_insn (slot1
, y
);
7948 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7949 emit_library_call (libfunc
, LCT_NORMAL
,
7951 XEXP (slot0
, 0), Pmode
,
7952 XEXP (slot1
, 0), Pmode
);
7957 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7958 emit_library_call (libfunc
, LCT_NORMAL
,
7960 x
, TFmode
, y
, TFmode
);
7965 /* Immediately move the result of the libcall into a pseudo
7966 register so reload doesn't clobber the value if it needs
7967 the return register for a spill reg. */
7968 result
= gen_reg_rtx (mode
);
7969 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7974 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7977 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7978 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7981 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7982 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7984 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7986 tem
= gen_reg_rtx (mode
);
7988 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7990 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7991 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7994 tem
= gen_reg_rtx (mode
);
7996 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7998 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7999 tem2
= gen_reg_rtx (mode
);
8001 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8003 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8004 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8005 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8011 /* Generate an unsigned DImode to FP conversion. This is the same code
8012 optabs would emit if we didn't have TFmode patterns. */
8015 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8017 rtx i0
, i1
, f0
, in
, out
;
8020 in
= force_reg (DImode
, operands
[1]);
8021 rtx_code_label
*neglab
= gen_label_rtx ();
8022 rtx_code_label
*donelab
= gen_label_rtx ();
8023 i0
= gen_reg_rtx (DImode
);
8024 i1
= gen_reg_rtx (DImode
);
8025 f0
= gen_reg_rtx (mode
);
8027 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8029 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8030 emit_jump_insn (gen_jump (donelab
));
8033 emit_label (neglab
);
8035 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8036 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8037 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8038 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8039 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8041 emit_label (donelab
);
8044 /* Generate an FP to unsigned DImode conversion. This is the same code
8045 optabs would emit if we didn't have TFmode patterns. */
8048 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8050 rtx i0
, i1
, f0
, in
, out
, limit
;
8053 in
= force_reg (mode
, operands
[1]);
8054 rtx_code_label
*neglab
= gen_label_rtx ();
8055 rtx_code_label
*donelab
= gen_label_rtx ();
8056 i0
= gen_reg_rtx (DImode
);
8057 i1
= gen_reg_rtx (DImode
);
8058 limit
= gen_reg_rtx (mode
);
8059 f0
= gen_reg_rtx (mode
);
8061 emit_move_insn (limit
,
8062 const_double_from_real_value (
8063 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8064 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8066 emit_insn (gen_rtx_SET (out
,
8067 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8068 emit_jump_insn (gen_jump (donelab
));
8071 emit_label (neglab
);
8073 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8074 emit_insn (gen_rtx_SET (i0
,
8075 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8076 emit_insn (gen_movdi (i1
, const1_rtx
));
8077 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8078 emit_insn (gen_xordi3 (out
, i0
, i1
));
8080 emit_label (donelab
);
8083 /* Return the string to output a compare and branch instruction to DEST.
8084 DEST is the destination insn (i.e. the label), INSN is the source,
8085 and OP is the conditional expression. */
8088 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8090 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8091 enum rtx_code code
= GET_CODE (op
);
8092 const char *cond_str
, *tmpl
;
8093 int far
, emit_nop
, len
;
8094 static char string
[64];
8097 /* Compare and Branch is limited to +-2KB. If it is too far away,
8109 len
= get_attr_length (insn
);
8112 emit_nop
= len
== 2;
8115 code
= reverse_condition (code
);
8117 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8130 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8145 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8173 int veryfar
= 1, delta
;
8175 if (INSN_ADDRESSES_SET_P ())
8177 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8178 - INSN_ADDRESSES (INSN_UID (insn
)));
8179 /* Leave some instructions for "slop". */
8180 if (delta
>= -260000 && delta
< 260000)
8185 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8187 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8192 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8194 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8197 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8202 /* Return the string to output a conditional branch to LABEL, testing
8203 register REG. LABEL is the operand number of the label; REG is the
8204 operand number of the reg. OP is the conditional expression. The mode
8205 of REG says what kind of comparison we made.
8207 DEST is the destination insn (i.e. the label), INSN is the source.
8209 REVERSED is nonzero if we should reverse the sense of the comparison.
8211 ANNUL is nonzero if we should generate an annulling branch. */
8214 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8215 int annul
, rtx_insn
*insn
)
8217 static char string
[64];
8218 enum rtx_code code
= GET_CODE (op
);
8219 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8224 /* branch on register are limited to +-128KB. If it is too far away,
8237 brgez,a,pn %o1, .LC29
8243 ba,pt %xcc, .LC29 */
8245 far
= get_attr_length (insn
) >= 3;
8247 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8249 code
= reverse_condition (code
);
8251 /* Only 64 bit versions of these instructions exist. */
8252 gcc_assert (mode
== DImode
);
8254 /* Start by writing the branch condition. */
8259 strcpy (string
, "brnz");
8263 strcpy (string
, "brz");
8267 strcpy (string
, "brgez");
8271 strcpy (string
, "brlz");
8275 strcpy (string
, "brlez");
8279 strcpy (string
, "brgz");
8286 p
= strchr (string
, '\0');
8288 /* Now add the annulling, reg, label, and nop. */
8295 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8298 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
8303 *p
= p
< string
+ 8 ? '\t' : ' ';
8311 int veryfar
= 1, delta
;
8313 if (INSN_ADDRESSES_SET_P ())
8315 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8316 - INSN_ADDRESSES (INSN_UID (insn
)));
8317 /* Leave some instructions for "slop". */
8318 if (delta
>= -260000 && delta
< 260000)
8322 strcpy (p
, ".+12\n\t nop\n\t");
8323 /* Skip the next insn if requested or
8324 if we know that it will be a nop. */
8325 if (annul
|| ! final_sequence
)
8335 strcpy (p
, "ba,pt\t%%xcc, ");
8349 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8350 Such instructions cannot be used in the delay slot of return insn on v9.
8351 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8355 epilogue_renumber (register rtx
*where
, int test
)
8357 register const char *fmt
;
8359 register enum rtx_code code
;
8364 code
= GET_CODE (*where
);
8369 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8371 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8372 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8377 case CONST_WIDE_INT
:
8381 /* Do not replace the frame pointer with the stack pointer because
8382 it can cause the delayed instruction to load below the stack.
8383 This occurs when instructions like:
8385 (set (reg/i:SI 24 %i0)
8386 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8387 (const_int -20 [0xffffffec])) 0))
8389 are in the return delayed slot. */
8391 if (GET_CODE (XEXP (*where
, 0)) == REG
8392 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8393 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8394 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8399 if (SPARC_STACK_BIAS
8400 && GET_CODE (XEXP (*where
, 0)) == REG
8401 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8409 fmt
= GET_RTX_FORMAT (code
);
8411 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8416 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8417 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8420 else if (fmt
[i
] == 'e'
8421 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8427 /* Leaf functions and non-leaf functions have different needs. */
8430 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8433 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8435 static const int *const reg_alloc_orders
[] = {
8436 reg_leaf_alloc_order
,
8437 reg_nonleaf_alloc_order
};
8440 order_regs_for_local_alloc (void)
8442 static int last_order_nonleaf
= 1;
8444 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8446 last_order_nonleaf
= !last_order_nonleaf
;
8447 memcpy ((char *) reg_alloc_order
,
8448 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8449 FIRST_PSEUDO_REGISTER
* sizeof (int));
8453 /* Return 1 if REG and MEM are legitimate enough to allow the various
8454 mem<-->reg splits to be run. */
8457 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
8459 /* Punt if we are here by mistake. */
8460 gcc_assert (reload_completed
);
8462 /* We must have an offsettable memory reference. */
8463 if (! offsettable_memref_p (mem
))
8466 /* If we have legitimate args for ldd/std, we do not want
8467 the split to happen. */
8468 if ((REGNO (reg
) % 2) == 0
8469 && mem_min_alignment (mem
, 8))
8476 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8479 sparc_split_regreg_legitimate (rtx reg1
, rtx reg2
)
8483 if (GET_CODE (reg1
) == SUBREG
)
8484 reg1
= SUBREG_REG (reg1
);
8485 if (GET_CODE (reg1
) != REG
)
8487 regno1
= REGNO (reg1
);
8489 if (GET_CODE (reg2
) == SUBREG
)
8490 reg2
= SUBREG_REG (reg2
);
8491 if (GET_CODE (reg2
) != REG
)
8493 regno2
= REGNO (reg2
);
8495 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8500 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8501 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8508 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8509 This makes them candidates for using ldd and std insns.
8511 Note reg1 and reg2 *must* be hard registers. */
8514 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8516 /* We might have been passed a SUBREG. */
8517 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8520 if (REGNO (reg1
) % 2 != 0)
8523 /* Integer ldd is deprecated in SPARC V9 */
8524 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8527 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8530 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8533 This can only happen when addr1 and addr2, the addresses in mem1
8534 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8535 addr1 must also be aligned on a 64-bit boundary.
8537 Also iff dependent_reg_rtx is not null it should not be used to
8538 compute the address for mem1, i.e. we cannot optimize a sequence
8550 But, note that the transformation from:
8555 is perfectly fine. Thus, the peephole2 patterns always pass us
8556 the destination register of the first load, never the second one.
8558 For stores we don't have a similar problem, so dependent_reg_rtx is
8562 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8566 HOST_WIDE_INT offset1
;
8568 /* The mems cannot be volatile. */
8569 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8572 /* MEM1 should be aligned on a 64-bit boundary. */
8573 if (MEM_ALIGN (mem1
) < 64)
8576 addr1
= XEXP (mem1
, 0);
8577 addr2
= XEXP (mem2
, 0);
8579 /* Extract a register number and offset (if used) from the first addr. */
8580 if (GET_CODE (addr1
) == PLUS
)
8582 /* If not a REG, return zero. */
8583 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8587 reg1
= REGNO (XEXP (addr1
, 0));
8588 /* The offset must be constant! */
8589 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8591 offset1
= INTVAL (XEXP (addr1
, 1));
8594 else if (GET_CODE (addr1
) != REG
)
8598 reg1
= REGNO (addr1
);
8599 /* This was a simple (mem (reg)) expression. Offset is 0. */
8603 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8604 if (GET_CODE (addr2
) != PLUS
)
8607 if (GET_CODE (XEXP (addr2
, 0)) != REG
8608 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8611 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8614 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8617 /* The first offset must be evenly divisible by 8 to ensure the
8618 address is 64 bit aligned. */
8619 if (offset1
% 8 != 0)
8622 /* The offset for the second addr must be 4 more than the first addr. */
8623 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8626 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8631 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8634 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
8636 rtx x
= widen_memory_access (mem1
, mode
, 0);
8637 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
8641 /* Return 1 if reg is a pseudo, or is the first register in
8642 a hard register pair. This makes it suitable for use in
8643 ldd and std insns. */
8646 register_ok_for_ldd (rtx reg
)
8648 /* We might have been passed a SUBREG. */
8652 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8653 return (REGNO (reg
) % 2 == 0);
8658 /* Return 1 if OP, a MEM, has an address which is known to be
8659 aligned to an 8-byte boundary. */
8662 memory_ok_for_ldd (rtx op
)
8664 /* In 64-bit mode, we assume that the address is word-aligned. */
8665 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8668 if (! can_create_pseudo_p ()
8669 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8675 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8678 sparc_print_operand_punct_valid_p (unsigned char code
)
8691 /* Implement TARGET_PRINT_OPERAND.
8692 Print operand X (an rtx) in assembler syntax to file FILE.
8693 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8694 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8697 sparc_print_operand (FILE *file
, rtx x
, int code
)
8702 /* Output an insn in a delay slot. */
8704 sparc_indent_opcode
= 1;
8706 fputs ("\n\t nop", file
);
8709 /* Output an annul flag if there's nothing for the delay slot and we
8710 are optimizing. This is always used with '(' below.
8711 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8712 this is a dbx bug. So, we only do this when optimizing.
8713 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8714 Always emit a nop in case the next instruction is a branch. */
8715 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8719 /* Output a 'nop' if there's nothing for the delay slot and we are
8720 not optimizing. This is always used with '*' above. */
8721 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8722 fputs ("\n\t nop", file
);
8723 else if (final_sequence
)
8724 sparc_indent_opcode
= 1;
8727 /* Output the right displacement from the saved PC on function return.
8728 The caller may have placed an "unimp" insn immediately after the call
8729 so we have to account for it. This insn is used in the 32-bit ABI
8730 when calling a function that returns a non zero-sized structure. The
8731 64-bit ABI doesn't have it. Be careful to have this test be the same
8732 as that for the call. The exception is when sparc_std_struct_return
8733 is enabled, the psABI is followed exactly and the adjustment is made
8734 by the code in sparc_struct_value_rtx. The call emitted is the same
8735 when sparc_std_struct_return is enabled. */
8737 && cfun
->returns_struct
8738 && !sparc_std_struct_return
8739 && DECL_SIZE (DECL_RESULT (current_function_decl
))
8740 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
8742 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
8748 /* Output the Embedded Medium/Anywhere code model base register. */
8749 fputs (EMBMEDANY_BASE_REG
, file
);
8752 /* Print some local dynamic TLS name. */
8753 if (const char *name
= get_some_local_dynamic_name ())
8754 assemble_name (file
, name
);
8756 output_operand_lossage ("'%%&' used without any "
8757 "local dynamic TLS references");
8761 /* Adjust the operand to take into account a RESTORE operation. */
8762 if (GET_CODE (x
) == CONST_INT
)
8764 else if (GET_CODE (x
) != REG
)
8765 output_operand_lossage ("invalid %%Y operand");
8766 else if (REGNO (x
) < 8)
8767 fputs (reg_names
[REGNO (x
)], file
);
8768 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
8769 fputs (reg_names
[REGNO (x
)-16], file
);
8771 output_operand_lossage ("invalid %%Y operand");
8774 /* Print out the low order register name of a register pair. */
8775 if (WORDS_BIG_ENDIAN
)
8776 fputs (reg_names
[REGNO (x
)+1], file
);
8778 fputs (reg_names
[REGNO (x
)], file
);
8781 /* Print out the high order register name of a register pair. */
8782 if (WORDS_BIG_ENDIAN
)
8783 fputs (reg_names
[REGNO (x
)], file
);
8785 fputs (reg_names
[REGNO (x
)+1], file
);
8788 /* Print out the second register name of a register pair or quad.
8789 I.e., R (%o0) => %o1. */
8790 fputs (reg_names
[REGNO (x
)+1], file
);
8793 /* Print out the third register name of a register quad.
8794 I.e., S (%o0) => %o2. */
8795 fputs (reg_names
[REGNO (x
)+2], file
);
8798 /* Print out the fourth register name of a register quad.
8799 I.e., T (%o0) => %o3. */
8800 fputs (reg_names
[REGNO (x
)+3], file
);
8803 /* Print a condition code register. */
8804 if (REGNO (x
) == SPARC_ICC_REG
)
8806 /* We don't handle CC[X]_NOOVmode because they're not supposed
8808 if (GET_MODE (x
) == CCmode
)
8809 fputs ("%icc", file
);
8810 else if (GET_MODE (x
) == CCXmode
)
8811 fputs ("%xcc", file
);
8816 /* %fccN register */
8817 fputs (reg_names
[REGNO (x
)], file
);
8820 /* Print the operand's address only. */
8821 output_address (GET_MODE (x
), XEXP (x
, 0));
8824 /* In this case we need a register. Use %g0 if the
8825 operand is const0_rtx. */
8827 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
8829 fputs ("%g0", file
);
8836 switch (GET_CODE (x
))
8838 case IOR
: fputs ("or", file
); break;
8839 case AND
: fputs ("and", file
); break;
8840 case XOR
: fputs ("xor", file
); break;
8841 default: output_operand_lossage ("invalid %%A operand");
8846 switch (GET_CODE (x
))
8848 case IOR
: fputs ("orn", file
); break;
8849 case AND
: fputs ("andn", file
); break;
8850 case XOR
: fputs ("xnor", file
); break;
8851 default: output_operand_lossage ("invalid %%B operand");
8855 /* This is used by the conditional move instructions. */
8858 enum rtx_code rc
= GET_CODE (x
);
8862 case NE
: fputs ("ne", file
); break;
8863 case EQ
: fputs ("e", file
); break;
8864 case GE
: fputs ("ge", file
); break;
8865 case GT
: fputs ("g", file
); break;
8866 case LE
: fputs ("le", file
); break;
8867 case LT
: fputs ("l", file
); break;
8868 case GEU
: fputs ("geu", file
); break;
8869 case GTU
: fputs ("gu", file
); break;
8870 case LEU
: fputs ("leu", file
); break;
8871 case LTU
: fputs ("lu", file
); break;
8872 case LTGT
: fputs ("lg", file
); break;
8873 case UNORDERED
: fputs ("u", file
); break;
8874 case ORDERED
: fputs ("o", file
); break;
8875 case UNLT
: fputs ("ul", file
); break;
8876 case UNLE
: fputs ("ule", file
); break;
8877 case UNGT
: fputs ("ug", file
); break;
8878 case UNGE
: fputs ("uge", file
); break;
8879 case UNEQ
: fputs ("ue", file
); break;
8880 default: output_operand_lossage ("invalid %%C operand");
8885 /* This are used by the movr instruction pattern. */
8888 enum rtx_code rc
= GET_CODE (x
);
8891 case NE
: fputs ("ne", file
); break;
8892 case EQ
: fputs ("e", file
); break;
8893 case GE
: fputs ("gez", file
); break;
8894 case LT
: fputs ("lz", file
); break;
8895 case LE
: fputs ("lez", file
); break;
8896 case GT
: fputs ("gz", file
); break;
8897 default: output_operand_lossage ("invalid %%D operand");
8904 /* Print a sign-extended character. */
8905 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8906 fprintf (file
, "%d", i
);
8911 /* Operand must be a MEM; write its address. */
8912 if (GET_CODE (x
) != MEM
)
8913 output_operand_lossage ("invalid %%f operand");
8914 output_address (GET_MODE (x
), XEXP (x
, 0));
8919 /* Print a sign-extended 32-bit value. */
8921 if (GET_CODE(x
) == CONST_INT
)
8925 output_operand_lossage ("invalid %%s operand");
8928 i
= trunc_int_for_mode (i
, SImode
);
8929 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8934 /* Do nothing special. */
8938 /* Undocumented flag. */
8939 output_operand_lossage ("invalid operand output code");
8942 if (GET_CODE (x
) == REG
)
8943 fputs (reg_names
[REGNO (x
)], file
);
8944 else if (GET_CODE (x
) == MEM
)
8947 /* Poor Sun assembler doesn't understand absolute addressing. */
8948 if (CONSTANT_P (XEXP (x
, 0)))
8949 fputs ("%g0+", file
);
8950 output_address (GET_MODE (x
), XEXP (x
, 0));
8953 else if (GET_CODE (x
) == HIGH
)
8955 fputs ("%hi(", file
);
8956 output_addr_const (file
, XEXP (x
, 0));
8959 else if (GET_CODE (x
) == LO_SUM
)
8961 sparc_print_operand (file
, XEXP (x
, 0), 0);
8962 if (TARGET_CM_MEDMID
)
8963 fputs ("+%l44(", file
);
8965 fputs ("+%lo(", file
);
8966 output_addr_const (file
, XEXP (x
, 1));
8969 else if (GET_CODE (x
) == CONST_DOUBLE
)
8970 output_operand_lossage ("floating-point constant not a valid immediate operand");
8972 output_addr_const (file
, x
);
8975 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8978 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
8980 register rtx base
, index
= 0;
8982 register rtx addr
= x
;
8985 fputs (reg_names
[REGNO (addr
)], file
);
8986 else if (GET_CODE (addr
) == PLUS
)
8988 if (CONST_INT_P (XEXP (addr
, 0)))
8989 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8990 else if (CONST_INT_P (XEXP (addr
, 1)))
8991 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8993 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8994 if (GET_CODE (base
) == LO_SUM
)
8996 gcc_assert (USE_AS_OFFSETABLE_LO10
8998 && ! TARGET_CM_MEDMID
);
8999 output_operand (XEXP (base
, 0), 0);
9000 fputs ("+%lo(", file
);
9001 output_address (VOIDmode
, XEXP (base
, 1));
9002 fprintf (file
, ")+%d", offset
);
9006 fputs (reg_names
[REGNO (base
)], file
);
9008 fprintf (file
, "%+d", offset
);
9009 else if (REG_P (index
))
9010 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9011 else if (GET_CODE (index
) == SYMBOL_REF
9012 || GET_CODE (index
) == LABEL_REF
9013 || GET_CODE (index
) == CONST
)
9014 fputc ('+', file
), output_addr_const (file
, index
);
9015 else gcc_unreachable ();
9018 else if (GET_CODE (addr
) == MINUS
9019 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9021 output_addr_const (file
, XEXP (addr
, 0));
9023 output_addr_const (file
, XEXP (addr
, 1));
9024 fputs ("-.)", file
);
9026 else if (GET_CODE (addr
) == LO_SUM
)
9028 output_operand (XEXP (addr
, 0), 0);
9029 if (TARGET_CM_MEDMID
)
9030 fputs ("+%l44(", file
);
9032 fputs ("+%lo(", file
);
9033 output_address (VOIDmode
, XEXP (addr
, 1));
9037 && GET_CODE (addr
) == CONST
9038 && GET_CODE (XEXP (addr
, 0)) == MINUS
9039 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9040 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9041 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9043 addr
= XEXP (addr
, 0);
9044 output_addr_const (file
, XEXP (addr
, 0));
9045 /* Group the args of the second CONST in parenthesis. */
9047 /* Skip past the second CONST--it does nothing for us. */
9048 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9049 /* Close the parenthesis. */
9054 output_addr_const (file
, addr
);
9058 /* Target hook for assembling integer objects. The sparc version has
9059 special handling for aligned DI-mode objects. */
9062 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9064 /* ??? We only output .xword's for symbols and only then in environments
9065 where the assembler can handle them. */
9066 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9070 assemble_integer_with_op ("\t.xword\t", x
);
9075 assemble_aligned_integer (4, const0_rtx
);
9076 assemble_aligned_integer (4, x
);
9080 return default_assemble_integer (x
, size
, aligned_p
);
9083 /* Return the value of a code used in the .proc pseudo-op that says
9084 what kind of result this function returns. For non-C types, we pick
9085 the closest C type. */
9087 #ifndef SHORT_TYPE_SIZE
9088 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9091 #ifndef INT_TYPE_SIZE
9092 #define INT_TYPE_SIZE BITS_PER_WORD
9095 #ifndef LONG_TYPE_SIZE
9096 #define LONG_TYPE_SIZE BITS_PER_WORD
9099 #ifndef LONG_LONG_TYPE_SIZE
9100 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9103 #ifndef FLOAT_TYPE_SIZE
9104 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9107 #ifndef DOUBLE_TYPE_SIZE
9108 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9111 #ifndef LONG_DOUBLE_TYPE_SIZE
9112 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9116 sparc_type_code (register tree type
)
9118 register unsigned long qualifiers
= 0;
9119 register unsigned shift
;
9121 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9122 setting more, since some assemblers will give an error for this. Also,
9123 we must be careful to avoid shifts of 32 bits or more to avoid getting
9124 unpredictable results. */
9126 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9128 switch (TREE_CODE (type
))
9134 qualifiers
|= (3 << shift
);
9139 qualifiers
|= (2 << shift
);
9143 case REFERENCE_TYPE
:
9145 qualifiers
|= (1 << shift
);
9149 return (qualifiers
| 8);
9152 case QUAL_UNION_TYPE
:
9153 return (qualifiers
| 9);
9156 return (qualifiers
| 10);
9159 return (qualifiers
| 16);
9162 /* If this is a range type, consider it to be the underlying
9164 if (TREE_TYPE (type
) != 0)
9167 /* Carefully distinguish all the standard types of C,
9168 without messing up if the language is not C. We do this by
9169 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9170 look at both the names and the above fields, but that's redundant.
9171 Any type whose size is between two C types will be considered
9172 to be the wider of the two types. Also, we do not have a
9173 special code to use for "long long", so anything wider than
9174 long is treated the same. Note that we can't distinguish
9175 between "int" and "long" in this code if they are the same
9176 size, but that's fine, since neither can the assembler. */
9178 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9179 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9181 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9182 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9184 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9185 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9188 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9191 /* If this is a range type, consider it to be the underlying
9193 if (TREE_TYPE (type
) != 0)
9196 /* Carefully distinguish all the standard types of C,
9197 without messing up if the language is not C. */
9199 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9200 return (qualifiers
| 6);
9203 return (qualifiers
| 7);
9205 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9206 /* ??? We need to distinguish between double and float complex types,
9207 but I don't know how yet because I can't reach this code from
9208 existing front-ends. */
9209 return (qualifiers
| 7); /* Who knows? */
9212 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9218 gcc_unreachable (); /* Not a type! */
9225 /* Nested function support. */
9227 /* Emit RTL insns to initialize the variable parts of a trampoline.
9228 FNADDR is an RTX for the address of the function's pure code.
9229 CXT is an RTX for the static chain value for the function.
9231 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9232 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9233 (to store insns). This is a bit excessive. Perhaps a different
9234 mechanism would be better here.
9236 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9239 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9241 /* SPARC 32-bit trampoline:
9244 sethi %hi(static), %g2
9246 or %g2, %lo(static), %g2
9248 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9249 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9253 (adjust_address (m_tramp
, SImode
, 0),
9254 expand_binop (SImode
, ior_optab
,
9255 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9256 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9257 NULL_RTX
, 1, OPTAB_DIRECT
));
9260 (adjust_address (m_tramp
, SImode
, 4),
9261 expand_binop (SImode
, ior_optab
,
9262 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9263 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9264 NULL_RTX
, 1, OPTAB_DIRECT
));
9267 (adjust_address (m_tramp
, SImode
, 8),
9268 expand_binop (SImode
, ior_optab
,
9269 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9270 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9271 NULL_RTX
, 1, OPTAB_DIRECT
));
9274 (adjust_address (m_tramp
, SImode
, 12),
9275 expand_binop (SImode
, ior_optab
,
9276 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9277 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9278 NULL_RTX
, 1, OPTAB_DIRECT
));
9280 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9281 aligned on a 16 byte boundary so one flush clears it all. */
9282 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9283 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9284 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9285 && sparc_cpu
!= PROCESSOR_NIAGARA
9286 && sparc_cpu
!= PROCESSOR_NIAGARA2
9287 && sparc_cpu
!= PROCESSOR_NIAGARA3
9288 && sparc_cpu
!= PROCESSOR_NIAGARA4
9289 && sparc_cpu
!= PROCESSOR_NIAGARA7
)
9290 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9292 /* Call __enable_execute_stack after writing onto the stack to make sure
9293 the stack address is accessible. */
9294 #ifdef HAVE_ENABLE_EXECUTE_STACK
9295 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9296 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9301 /* The 64-bit version is simpler because it makes more sense to load the
9302 values as "immediate" data out of the trampoline. It's also easier since
9303 we can read the PC without clobbering a register. */
9306 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9308 /* SPARC 64-bit trampoline:
9317 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9318 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9319 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9320 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9321 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9322 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9323 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9324 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9325 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9326 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9327 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9329 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9330 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9331 && sparc_cpu
!= PROCESSOR_NIAGARA
9332 && sparc_cpu
!= PROCESSOR_NIAGARA2
9333 && sparc_cpu
!= PROCESSOR_NIAGARA3
9334 && sparc_cpu
!= PROCESSOR_NIAGARA4
9335 && sparc_cpu
!= PROCESSOR_NIAGARA7
)
9336 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9338 /* Call __enable_execute_stack after writing onto the stack to make sure
9339 the stack address is accessible. */
9340 #ifdef HAVE_ENABLE_EXECUTE_STACK
9341 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9342 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9346 /* Worker for TARGET_TRAMPOLINE_INIT. */
9349 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9351 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9352 cxt
= force_reg (Pmode
, cxt
);
9354 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9356 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9359 /* Adjust the cost of a scheduling dependency. Return the new cost of
9360 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9363 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
9366 enum attr_type insn_type
;
9368 if (recog_memoized (insn
) < 0)
9371 insn_type
= get_attr_type (insn
);
9375 /* Data dependency; DEP_INSN writes a register that INSN reads some
9378 /* if a load, then the dependence must be on the memory address;
9379 add an extra "cycle". Note that the cost could be two cycles
9380 if the reg was written late in an instruction group; we ca not tell
9382 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9385 /* Get the delay only if the address of the store is the dependence. */
9386 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9388 rtx pat
= PATTERN(insn
);
9389 rtx dep_pat
= PATTERN (dep_insn
);
9391 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9392 return cost
; /* This should not happen! */
9394 /* The dependency between the two instructions was on the data that
9395 is being stored. Assume that this implies that the address of the
9396 store is not dependent. */
9397 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9400 return cost
+ 3; /* An approximation. */
9403 /* A shift instruction cannot receive its data from an instruction
9404 in the same cycle; add a one cycle penalty. */
9405 if (insn_type
== TYPE_SHIFT
)
9406 return cost
+ 3; /* Split before cascade into shift. */
9410 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9411 INSN writes some cycles later. */
9413 /* These are only significant for the fpu unit; writing a fp reg before
9414 the fpu has finished with it stalls the processor. */
9416 /* Reusing an integer register causes no problems. */
9417 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9425 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
9428 enum attr_type insn_type
, dep_type
;
9429 rtx pat
= PATTERN(insn
);
9430 rtx dep_pat
= PATTERN (dep_insn
);
9432 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9435 insn_type
= get_attr_type (insn
);
9436 dep_type
= get_attr_type (dep_insn
);
9441 /* Data dependency; DEP_INSN writes a register that INSN reads some
9448 /* Get the delay iff the address of the store is the dependence. */
9449 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9452 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9459 /* If a load, then the dependence must be on the memory address. If
9460 the addresses aren't equal, then it might be a false dependency */
9461 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9463 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9464 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9465 || GET_CODE (SET_SRC (pat
)) != MEM
9466 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9467 XEXP (SET_SRC (pat
), 0)))
9475 /* Compare to branch latency is 0. There is no benefit from
9476 separating compare and branch. */
9477 if (dep_type
== TYPE_COMPARE
)
9479 /* Floating point compare to branch latency is less than
9480 compare to conditional move. */
9481 if (dep_type
== TYPE_FPCMP
)
9490 /* Anti-dependencies only penalize the fpu unit. */
9491 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9503 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
9508 case PROCESSOR_SUPERSPARC
:
9509 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9511 case PROCESSOR_HYPERSPARC
:
9512 case PROCESSOR_SPARCLITE86X
:
9513 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9522 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9523 int sched_verbose ATTRIBUTE_UNUSED
,
9524 int max_ready ATTRIBUTE_UNUSED
)
9528 sparc_use_sched_lookahead (void)
9530 if (sparc_cpu
== PROCESSOR_NIAGARA
9531 || sparc_cpu
== PROCESSOR_NIAGARA2
9532 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9534 if (sparc_cpu
== PROCESSOR_NIAGARA4
9535 || sparc_cpu
== PROCESSOR_NIAGARA7
)
9537 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9538 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9540 if ((1 << sparc_cpu
) &
9541 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9542 (1 << PROCESSOR_SPARCLITE86X
)))
9548 sparc_issue_rate (void)
9552 case PROCESSOR_NIAGARA
:
9553 case PROCESSOR_NIAGARA2
:
9554 case PROCESSOR_NIAGARA3
:
9557 case PROCESSOR_NIAGARA4
:
9558 case PROCESSOR_NIAGARA7
:
9560 /* Assume V9 processors are capable of at least dual-issue. */
9562 case PROCESSOR_SUPERSPARC
:
9564 case PROCESSOR_HYPERSPARC
:
9565 case PROCESSOR_SPARCLITE86X
:
9567 case PROCESSOR_ULTRASPARC
:
9568 case PROCESSOR_ULTRASPARC3
:
9574 set_extends (rtx_insn
*insn
)
9576 register rtx pat
= PATTERN (insn
);
9578 switch (GET_CODE (SET_SRC (pat
)))
9580 /* Load and some shift instructions zero extend. */
9583 /* sethi clears the high bits */
9585 /* LO_SUM is used with sethi. sethi cleared the high
9586 bits and the values used with lo_sum are positive */
9588 /* Store flag stores 0 or 1 */
9598 rtx op0
= XEXP (SET_SRC (pat
), 0);
9599 rtx op1
= XEXP (SET_SRC (pat
), 1);
9600 if (GET_CODE (op1
) == CONST_INT
)
9601 return INTVAL (op1
) >= 0;
9602 if (GET_CODE (op0
) != REG
)
9604 if (sparc_check_64 (op0
, insn
) == 1)
9606 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9611 rtx op0
= XEXP (SET_SRC (pat
), 0);
9612 rtx op1
= XEXP (SET_SRC (pat
), 1);
9613 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
9615 if (GET_CODE (op1
) == CONST_INT
)
9616 return INTVAL (op1
) >= 0;
9617 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9620 return GET_MODE (SET_SRC (pat
)) == SImode
;
9621 /* Positive integers leave the high bits zero. */
9623 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
9626 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
9628 return sparc_check_64 (SET_SRC (pat
), insn
);
9634 /* We _ought_ to have only one kind per function, but... */
9635 static GTY(()) rtx sparc_addr_diff_list
;
9636 static GTY(()) rtx sparc_addr_list
;
9639 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
9641 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9643 sparc_addr_diff_list
9644 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
9646 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
9650 sparc_output_addr_vec (rtx vec
)
9652 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9653 int idx
, vlen
= XVECLEN (body
, 0);
9655 #ifdef ASM_OUTPUT_ADDR_VEC_START
9656 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9659 #ifdef ASM_OUTPUT_CASE_LABEL
9660 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9663 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9666 for (idx
= 0; idx
< vlen
; idx
++)
9668 ASM_OUTPUT_ADDR_VEC_ELT
9669 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9672 #ifdef ASM_OUTPUT_ADDR_VEC_END
9673 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9678 sparc_output_addr_diff_vec (rtx vec
)
9680 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9681 rtx base
= XEXP (XEXP (body
, 0), 0);
9682 int idx
, vlen
= XVECLEN (body
, 1);
9684 #ifdef ASM_OUTPUT_ADDR_VEC_START
9685 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9688 #ifdef ASM_OUTPUT_CASE_LABEL
9689 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9692 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9695 for (idx
= 0; idx
< vlen
; idx
++)
9697 ASM_OUTPUT_ADDR_DIFF_ELT
9700 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
9701 CODE_LABEL_NUMBER (base
));
9704 #ifdef ASM_OUTPUT_ADDR_VEC_END
9705 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9710 sparc_output_deferred_case_vectors (void)
9715 if (sparc_addr_list
== NULL_RTX
9716 && sparc_addr_diff_list
== NULL_RTX
)
9719 /* Align to cache line in the function's code section. */
9720 switch_to_section (current_function_section ());
9722 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9724 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
9726 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
9727 sparc_output_addr_vec (XEXP (t
, 0));
9728 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
9729 sparc_output_addr_diff_vec (XEXP (t
, 0));
9731 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
9734 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9735 unknown. Return 1 if the high bits are zero, -1 if the register is
9738 sparc_check_64 (rtx x
, rtx_insn
*insn
)
9740 /* If a register is set only once it is safe to ignore insns this
9741 code does not know how to handle. The loop will either recognize
9742 the single set and return the correct value or fail to recognize
9747 gcc_assert (GET_CODE (x
) == REG
);
9749 if (GET_MODE (x
) == DImode
)
9750 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
9752 if (flag_expensive_optimizations
9753 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
9759 insn
= get_last_insn_anywhere ();
9764 while ((insn
= PREV_INSN (insn
)))
9766 switch (GET_CODE (insn
))
9779 rtx pat
= PATTERN (insn
);
9780 if (GET_CODE (pat
) != SET
)
9782 if (rtx_equal_p (x
, SET_DEST (pat
)))
9783 return set_extends (insn
);
9784 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
9785 return set_extends (insn
);
9786 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
9794 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9795 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9798 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
9800 static char asm_code
[60];
9802 /* The scratch register is only required when the destination
9803 register is not a 64-bit global or out register. */
9804 if (which_alternative
!= 2)
9805 operands
[3] = operands
[0];
9807 /* We can only shift by constants <= 63. */
9808 if (GET_CODE (operands
[2]) == CONST_INT
)
9809 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
9811 if (GET_CODE (operands
[1]) == CONST_INT
)
9813 output_asm_insn ("mov\t%1, %3", operands
);
9817 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
9818 if (sparc_check_64 (operands
[1], insn
) <= 0)
9819 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
9820 output_asm_insn ("or\t%L1, %3, %3", operands
);
9823 strcpy (asm_code
, opcode
);
9825 if (which_alternative
!= 2)
9826 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9829 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9832 /* Output rtl to increment the profiler label LABELNO
9833 for profiling a function entry. */
9836 sparc_profile_hook (int labelno
)
9841 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
9842 if (NO_PROFILE_COUNTERS
)
9844 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
9848 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
9849 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
9850 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
9854 #ifdef TARGET_SOLARIS
9855 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9858 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9859 tree decl ATTRIBUTE_UNUSED
)
9861 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9863 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9867 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9869 if (!(flags
& SECTION_DEBUG
))
9870 fputs (",#alloc", asm_out_file
);
9871 if (flags
& SECTION_WRITE
)
9872 fputs (",#write", asm_out_file
);
9873 if (flags
& SECTION_TLS
)
9874 fputs (",#tls", asm_out_file
);
9875 if (flags
& SECTION_CODE
)
9876 fputs (",#execinstr", asm_out_file
);
9878 if (flags
& SECTION_NOTYPE
)
9880 else if (flags
& SECTION_BSS
)
9881 fputs (",#nobits", asm_out_file
);
9883 fputs (",#progbits", asm_out_file
);
9885 fputc ('\n', asm_out_file
);
9887 #endif /* TARGET_SOLARIS */
9889 /* We do not allow indirect calls to be optimized into sibling calls.
9891 We cannot use sibling calls when delayed branches are disabled
9892 because they will likely require the call delay slot to be filled.
9894 Also, on SPARC 32-bit we cannot emit a sibling call when the
9895 current function returns a structure. This is because the "unimp
9896 after call" convention would cause the callee to return to the
9897 wrong place. The generic code already disallows cases where the
9898 function being called returns a structure.
9900 It may seem strange how this last case could occur. Usually there
9901 is code after the call which jumps to epilogue code which dumps the
9902 return value into the struct return area. That ought to invalidate
9903 the sibling call right? Well, in the C++ case we can end up passing
9904 the pointer to the struct return area to a constructor (which returns
9905 void) and then nothing else happens. Such a sibling call would look
9906 valid without the added check here.
9908 VxWorks PIC PLT entries require the global pointer to be initialized
9909 on entry. We therefore can't emit sibling calls to them. */
9911 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9914 && flag_delayed_branch
9915 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9916 && !(TARGET_VXWORKS_RTP
9918 && !targetm
.binds_local_p (decl
)));
9921 /* libfunc renaming. */
9924 sparc_init_libfuncs (void)
9928 /* Use the subroutines that Sun's library provides for integer
9929 multiply and divide. The `*' prevents an underscore from
9930 being prepended by the compiler. .umul is a little faster
9932 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9933 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9934 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9935 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9936 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9938 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9939 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9940 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9941 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9942 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9943 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9945 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9946 is because with soft-float, the SFmode and DFmode sqrt
9947 instructions will be absent, and the compiler will notice and
9948 try to use the TFmode sqrt instruction for calls to the
9949 builtin function sqrt, but this fails. */
9951 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9953 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9954 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9955 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9956 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9957 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9958 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9960 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9961 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9962 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9963 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9965 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9966 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9967 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9968 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9970 if (DITF_CONVERSION_LIBFUNCS
)
9972 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9973 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9974 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9975 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9978 if (SUN_CONVERSION_LIBFUNCS
)
9980 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9981 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9982 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9983 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9988 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9989 do not exist in the library. Make sure the compiler does not
9990 emit calls to them by accident. (It should always use the
9991 hardware instructions.) */
9992 set_optab_libfunc (smul_optab
, SImode
, 0);
9993 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9994 set_optab_libfunc (udiv_optab
, SImode
, 0);
9995 set_optab_libfunc (smod_optab
, SImode
, 0);
9996 set_optab_libfunc (umod_optab
, SImode
, 0);
9998 if (SUN_INTEGER_MULTIPLY_64
)
10000 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10001 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10002 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10003 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10004 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10007 if (SUN_CONVERSION_LIBFUNCS
)
10009 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10010 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10011 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10012 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10017 /* SPARC builtins. */
10018 enum sparc_builtins
10020 /* FPU builtins. */
10021 SPARC_BUILTIN_LDFSR
,
10022 SPARC_BUILTIN_STFSR
,
10024 /* VIS 1.0 builtins. */
10025 SPARC_BUILTIN_FPACK16
,
10026 SPARC_BUILTIN_FPACK32
,
10027 SPARC_BUILTIN_FPACKFIX
,
10028 SPARC_BUILTIN_FEXPAND
,
10029 SPARC_BUILTIN_FPMERGE
,
10030 SPARC_BUILTIN_FMUL8X16
,
10031 SPARC_BUILTIN_FMUL8X16AU
,
10032 SPARC_BUILTIN_FMUL8X16AL
,
10033 SPARC_BUILTIN_FMUL8SUX16
,
10034 SPARC_BUILTIN_FMUL8ULX16
,
10035 SPARC_BUILTIN_FMULD8SUX16
,
10036 SPARC_BUILTIN_FMULD8ULX16
,
10037 SPARC_BUILTIN_FALIGNDATAV4HI
,
10038 SPARC_BUILTIN_FALIGNDATAV8QI
,
10039 SPARC_BUILTIN_FALIGNDATAV2SI
,
10040 SPARC_BUILTIN_FALIGNDATADI
,
10041 SPARC_BUILTIN_WRGSR
,
10042 SPARC_BUILTIN_RDGSR
,
10043 SPARC_BUILTIN_ALIGNADDR
,
10044 SPARC_BUILTIN_ALIGNADDRL
,
10045 SPARC_BUILTIN_PDIST
,
10046 SPARC_BUILTIN_EDGE8
,
10047 SPARC_BUILTIN_EDGE8L
,
10048 SPARC_BUILTIN_EDGE16
,
10049 SPARC_BUILTIN_EDGE16L
,
10050 SPARC_BUILTIN_EDGE32
,
10051 SPARC_BUILTIN_EDGE32L
,
10052 SPARC_BUILTIN_FCMPLE16
,
10053 SPARC_BUILTIN_FCMPLE32
,
10054 SPARC_BUILTIN_FCMPNE16
,
10055 SPARC_BUILTIN_FCMPNE32
,
10056 SPARC_BUILTIN_FCMPGT16
,
10057 SPARC_BUILTIN_FCMPGT32
,
10058 SPARC_BUILTIN_FCMPEQ16
,
10059 SPARC_BUILTIN_FCMPEQ32
,
10060 SPARC_BUILTIN_FPADD16
,
10061 SPARC_BUILTIN_FPADD16S
,
10062 SPARC_BUILTIN_FPADD32
,
10063 SPARC_BUILTIN_FPADD32S
,
10064 SPARC_BUILTIN_FPSUB16
,
10065 SPARC_BUILTIN_FPSUB16S
,
10066 SPARC_BUILTIN_FPSUB32
,
10067 SPARC_BUILTIN_FPSUB32S
,
10068 SPARC_BUILTIN_ARRAY8
,
10069 SPARC_BUILTIN_ARRAY16
,
10070 SPARC_BUILTIN_ARRAY32
,
10072 /* VIS 2.0 builtins. */
10073 SPARC_BUILTIN_EDGE8N
,
10074 SPARC_BUILTIN_EDGE8LN
,
10075 SPARC_BUILTIN_EDGE16N
,
10076 SPARC_BUILTIN_EDGE16LN
,
10077 SPARC_BUILTIN_EDGE32N
,
10078 SPARC_BUILTIN_EDGE32LN
,
10079 SPARC_BUILTIN_BMASK
,
10080 SPARC_BUILTIN_BSHUFFLEV4HI
,
10081 SPARC_BUILTIN_BSHUFFLEV8QI
,
10082 SPARC_BUILTIN_BSHUFFLEV2SI
,
10083 SPARC_BUILTIN_BSHUFFLEDI
,
10085 /* VIS 3.0 builtins. */
10086 SPARC_BUILTIN_CMASK8
,
10087 SPARC_BUILTIN_CMASK16
,
10088 SPARC_BUILTIN_CMASK32
,
10089 SPARC_BUILTIN_FCHKSM16
,
10090 SPARC_BUILTIN_FSLL16
,
10091 SPARC_BUILTIN_FSLAS16
,
10092 SPARC_BUILTIN_FSRL16
,
10093 SPARC_BUILTIN_FSRA16
,
10094 SPARC_BUILTIN_FSLL32
,
10095 SPARC_BUILTIN_FSLAS32
,
10096 SPARC_BUILTIN_FSRL32
,
10097 SPARC_BUILTIN_FSRA32
,
10098 SPARC_BUILTIN_PDISTN
,
10099 SPARC_BUILTIN_FMEAN16
,
10100 SPARC_BUILTIN_FPADD64
,
10101 SPARC_BUILTIN_FPSUB64
,
10102 SPARC_BUILTIN_FPADDS16
,
10103 SPARC_BUILTIN_FPADDS16S
,
10104 SPARC_BUILTIN_FPSUBS16
,
10105 SPARC_BUILTIN_FPSUBS16S
,
10106 SPARC_BUILTIN_FPADDS32
,
10107 SPARC_BUILTIN_FPADDS32S
,
10108 SPARC_BUILTIN_FPSUBS32
,
10109 SPARC_BUILTIN_FPSUBS32S
,
10110 SPARC_BUILTIN_FUCMPLE8
,
10111 SPARC_BUILTIN_FUCMPNE8
,
10112 SPARC_BUILTIN_FUCMPGT8
,
10113 SPARC_BUILTIN_FUCMPEQ8
,
10114 SPARC_BUILTIN_FHADDS
,
10115 SPARC_BUILTIN_FHADDD
,
10116 SPARC_BUILTIN_FHSUBS
,
10117 SPARC_BUILTIN_FHSUBD
,
10118 SPARC_BUILTIN_FNHADDS
,
10119 SPARC_BUILTIN_FNHADDD
,
10120 SPARC_BUILTIN_UMULXHI
,
10121 SPARC_BUILTIN_XMULX
,
10122 SPARC_BUILTIN_XMULXHI
,
10124 /* VIS 4.0 builtins. */
10125 SPARC_BUILTIN_FPADD8
,
10126 SPARC_BUILTIN_FPADDS8
,
10127 SPARC_BUILTIN_FPADDUS8
,
10128 SPARC_BUILTIN_FPADDUS16
,
10129 SPARC_BUILTIN_FPCMPLE8
,
10130 SPARC_BUILTIN_FPCMPGT8
,
10131 SPARC_BUILTIN_FPCMPULE16
,
10132 SPARC_BUILTIN_FPCMPUGT16
,
10133 SPARC_BUILTIN_FPCMPULE32
,
10134 SPARC_BUILTIN_FPCMPUGT32
,
10135 SPARC_BUILTIN_FPMAX8
,
10136 SPARC_BUILTIN_FPMAX16
,
10137 SPARC_BUILTIN_FPMAX32
,
10138 SPARC_BUILTIN_FPMAXU8
,
10139 SPARC_BUILTIN_FPMAXU16
,
10140 SPARC_BUILTIN_FPMAXU32
,
10141 SPARC_BUILTIN_FPMIN8
,
10142 SPARC_BUILTIN_FPMIN16
,
10143 SPARC_BUILTIN_FPMIN32
,
10144 SPARC_BUILTIN_FPMINU8
,
10145 SPARC_BUILTIN_FPMINU16
,
10146 SPARC_BUILTIN_FPMINU32
,
10147 SPARC_BUILTIN_FPSUB8
,
10148 SPARC_BUILTIN_FPSUBS8
,
10149 SPARC_BUILTIN_FPSUBUS8
,
10150 SPARC_BUILTIN_FPSUBUS16
,
10155 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10156 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10158 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10159 function decl or NULL_TREE if the builtin was not added. */
10162 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10166 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10170 sparc_builtins
[code
] = t
;
10171 sparc_builtins_icode
[code
] = icode
;
10177 /* Likewise, but also marks the function as "const". */
10180 def_builtin_const (const char *name
, enum insn_code icode
,
10181 enum sparc_builtins code
, tree type
)
10183 tree t
= def_builtin (name
, icode
, code
, type
);
10186 TREE_READONLY (t
) = 1;
10191 /* Implement the TARGET_INIT_BUILTINS target hook.
10192 Create builtin functions for special SPARC instructions. */
10195 sparc_init_builtins (void)
10198 sparc_fpu_init_builtins ();
10201 sparc_vis_init_builtins ();
10204 /* Create builtin functions for FPU instructions. */
10207 sparc_fpu_init_builtins (void)
10210 = build_function_type_list (void_type_node
,
10211 build_pointer_type (unsigned_type_node
), 0);
10212 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10213 SPARC_BUILTIN_LDFSR
, ftype
);
10214 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10215 SPARC_BUILTIN_STFSR
, ftype
);
10218 /* Create builtin functions for VIS instructions. */
10221 sparc_vis_init_builtins (void)
10223 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10224 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10225 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10226 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10227 tree v2si
= build_vector_type (intSI_type_node
, 2);
10228 tree v1si
= build_vector_type (intSI_type_node
, 1);
10230 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10231 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10232 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10233 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10234 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10235 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10236 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10237 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10238 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10239 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10240 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10241 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10242 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10243 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10244 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10246 intDI_type_node
, 0);
10247 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10249 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10251 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10253 intDI_type_node
, 0);
10254 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10256 intSI_type_node
, 0);
10257 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10259 intSI_type_node
, 0);
10260 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10262 intDI_type_node
, 0);
10263 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10266 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10269 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10271 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10273 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10275 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10277 tree void_ftype_di
= build_function_type_list (void_type_node
,
10278 intDI_type_node
, 0);
10279 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10280 void_type_node
, 0);
10281 tree void_ftype_si
= build_function_type_list (void_type_node
,
10282 intSI_type_node
, 0);
10283 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10285 float_type_node
, 0);
10286 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10288 double_type_node
, 0);
10290 /* Packing and expanding vectors. */
10291 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10292 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10293 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10294 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10295 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10296 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10297 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10298 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10299 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10300 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10302 /* Multiplications. */
10303 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10304 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10305 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10306 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10307 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10308 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10309 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10310 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10311 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10312 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
10313 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
10314 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
10315 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
10316 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
10318 /* Data aligning. */
10319 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
10320 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
10321 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
10322 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
10323 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
10324 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
10325 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
10326 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
10328 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
10329 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
10330 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
10331 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
10335 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
10336 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
10337 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
10338 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
10342 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
10343 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
10344 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
10345 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
10348 /* Pixel distance. */
10349 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
10350 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
10352 /* Edge handling. */
10355 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
10356 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
10357 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
10358 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
10359 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
10360 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
10361 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
10362 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
10363 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
10364 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
10365 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
10366 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
10370 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
10371 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
10372 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
10373 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
10374 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
10375 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
10376 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
10377 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
10378 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
10379 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
10380 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
10381 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
10384 /* Pixel compare. */
10387 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
10388 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
10389 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
10390 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
10391 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
10392 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
10393 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
10394 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
10395 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
10396 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
10397 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
10398 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
10399 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
10400 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
10401 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
10402 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
10406 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
10407 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
10408 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
10409 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
10410 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
10411 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
10412 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
10413 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
10414 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
10415 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
10416 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
10417 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
10418 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
10419 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
10420 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
10421 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
10424 /* Addition and subtraction. */
10425 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
10426 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
10427 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
10428 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
10429 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
10430 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
10431 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
10432 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
10433 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
10434 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
10435 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
10436 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
10437 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
10438 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
10439 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
10440 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
10442 /* Three-dimensional array addressing. */
10445 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
10446 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
10447 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
10448 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
10449 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
10450 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
10454 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
10455 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
10456 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
10457 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
10458 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
10459 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
10464 /* Edge handling. */
10467 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
10468 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
10469 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
10470 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
10471 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
10472 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
10473 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
10474 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
10475 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
10476 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
10477 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
10478 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
10482 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
10483 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
10484 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
10485 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
10486 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
10487 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
10488 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
10489 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
10490 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
10491 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
10492 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
10493 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
10496 /* Byte mask and shuffle. */
10498 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
10499 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
10501 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
10502 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
10503 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
10504 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
10505 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
10506 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
10507 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
10508 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
10509 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
10510 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
10517 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
10518 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
10519 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
10520 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
10521 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
10522 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
10526 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
10527 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
10528 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
10529 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
10530 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
10531 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
10534 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
10535 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
10537 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
10538 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
10539 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
10540 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
10541 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
10542 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
10543 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
10544 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
10545 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
10546 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
10547 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
10548 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
10549 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
10550 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
10551 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
10552 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
10555 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
10556 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
10558 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
10559 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
10561 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
10562 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
10563 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
10564 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
10565 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
10566 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
10568 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
10569 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
10570 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
10571 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
10572 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
10573 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
10574 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
10575 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
10576 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
10577 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
10578 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
10579 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
10580 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
10581 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
10582 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
10583 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
10587 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
10588 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
10589 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
10590 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
10591 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
10592 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
10593 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
10594 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
10598 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
10599 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
10600 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
10601 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
10602 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
10603 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
10604 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
10605 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
10608 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
10609 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
10610 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
10611 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
10612 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
10613 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
10614 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
10615 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
10616 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
10617 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
10618 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
10619 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
10621 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
10622 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
10623 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
10624 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
10625 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
10626 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
10631 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
10632 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
10633 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
10634 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
10635 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
10636 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
10637 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
10638 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
10643 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
10644 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
10645 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
10646 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
10647 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
10648 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
10649 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
10650 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
10651 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
10652 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
10653 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
10654 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
10658 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
10659 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
10660 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
10661 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
10662 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
10663 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
10664 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
10665 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
10666 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
10667 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
10668 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
10669 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
10672 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
10673 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
10674 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
10675 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
10676 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
10677 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
10678 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
10679 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
10680 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
10681 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
10682 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
10683 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
10684 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
10685 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
10686 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
10687 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
10688 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
10689 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
10690 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
10691 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
10692 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
10693 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
10694 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
10695 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
10696 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
10697 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
10698 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
10699 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
10700 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
10701 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
10702 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
10703 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
10707 /* Implement TARGET_BUILTIN_DECL hook. */
10710 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10712 if (code
>= SPARC_BUILTIN_MAX
)
10713 return error_mark_node
;
10715 return sparc_builtins
[code
];
10718 /* Implemented TARGET_EXPAND_BUILTIN hook. */
10721 sparc_expand_builtin (tree exp
, rtx target
,
10722 rtx subtarget ATTRIBUTE_UNUSED
,
10723 machine_mode tmode ATTRIBUTE_UNUSED
,
10724 int ignore ATTRIBUTE_UNUSED
)
10726 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10727 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10728 enum insn_code icode
= sparc_builtins_icode
[code
];
10729 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10730 call_expr_arg_iterator iter
;
10737 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10739 || GET_MODE (target
) != tmode
10740 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10741 op
[0] = gen_reg_rtx (tmode
);
10746 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10748 const struct insn_operand_data
*insn_op
;
10751 if (arg
== error_mark_node
)
10755 idx
= arg_count
- !nonvoid
;
10756 insn_op
= &insn_data
[icode
].operand
[idx
];
10757 op
[arg_count
] = expand_normal (arg
);
10759 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
10761 if (!address_operand (op
[arg_count
], SImode
))
10763 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
10764 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
10766 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
10769 else if (insn_op
->mode
== V1DImode
10770 && GET_MODE (op
[arg_count
]) == DImode
)
10771 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
10773 else if (insn_op
->mode
== V1SImode
10774 && GET_MODE (op
[arg_count
]) == SImode
)
10775 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
10777 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
10779 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
10785 pat
= GEN_FCN (icode
) (op
[0]);
10789 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10791 pat
= GEN_FCN (icode
) (op
[1]);
10794 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
10797 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
10800 gcc_unreachable ();
10808 return (nonvoid
? op
[0] : const0_rtx
);
10811 /* Return the upper 16 bits of the 8x16 multiplication. */
10814 sparc_vis_mul8x16 (int e8
, int e16
)
10816 return (e8
* e16
+ 128) / 256;
10819 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10820 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10823 sparc_handle_vis_mul8x16 (tree
*n_elts
, enum sparc_builtins fncode
,
10824 tree inner_type
, tree cst0
, tree cst1
)
10826 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
10831 case SPARC_BUILTIN_FMUL8X16
:
10832 for (i
= 0; i
< num
; ++i
)
10835 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10836 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
10837 n_elts
[i
] = build_int_cst (inner_type
, val
);
10841 case SPARC_BUILTIN_FMUL8X16AU
:
10842 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
10844 for (i
= 0; i
< num
; ++i
)
10847 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10849 n_elts
[i
] = build_int_cst (inner_type
, val
);
10853 case SPARC_BUILTIN_FMUL8X16AL
:
10854 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
10856 for (i
= 0; i
< num
; ++i
)
10859 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10861 n_elts
[i
] = build_int_cst (inner_type
, val
);
10866 gcc_unreachable ();
10870 /* Implement TARGET_FOLD_BUILTIN hook.
10872 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10873 result of the function call is ignored. NULL_TREE is returned if the
10874 function could not be folded. */
10877 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
10878 tree
*args
, bool ignore
)
10880 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10881 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
10882 tree arg0
, arg1
, arg2
;
10887 case SPARC_BUILTIN_LDFSR
:
10888 case SPARC_BUILTIN_STFSR
:
10889 case SPARC_BUILTIN_ALIGNADDR
:
10890 case SPARC_BUILTIN_WRGSR
:
10891 case SPARC_BUILTIN_BMASK
:
10892 case SPARC_BUILTIN_CMASK8
:
10893 case SPARC_BUILTIN_CMASK16
:
10894 case SPARC_BUILTIN_CMASK32
:
10898 return build_zero_cst (rtype
);
10903 case SPARC_BUILTIN_FEXPAND
:
10907 if (TREE_CODE (arg0
) == VECTOR_CST
)
10909 tree inner_type
= TREE_TYPE (rtype
);
10913 n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10914 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10915 n_elts
[i
] = build_int_cst (inner_type
,
10917 (VECTOR_CST_ELT (arg0
, i
)) << 4);
10918 return build_vector (rtype
, n_elts
);
10922 case SPARC_BUILTIN_FMUL8X16
:
10923 case SPARC_BUILTIN_FMUL8X16AU
:
10924 case SPARC_BUILTIN_FMUL8X16AL
:
10930 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10932 tree inner_type
= TREE_TYPE (rtype
);
10933 tree
*n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10934 sparc_handle_vis_mul8x16 (n_elts
, code
, inner_type
, arg0
, arg1
);
10935 return build_vector (rtype
, n_elts
);
10939 case SPARC_BUILTIN_FPMERGE
:
10945 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10947 tree
*n_elts
= XALLOCAVEC (tree
, 2 * VECTOR_CST_NELTS (arg0
));
10949 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10951 n_elts
[2*i
] = VECTOR_CST_ELT (arg0
, i
);
10952 n_elts
[2*i
+1] = VECTOR_CST_ELT (arg1
, i
);
10955 return build_vector (rtype
, n_elts
);
10959 case SPARC_BUILTIN_PDIST
:
10960 case SPARC_BUILTIN_PDISTN
:
10965 if (code
== SPARC_BUILTIN_PDIST
)
10971 arg2
= integer_zero_node
;
10973 if (TREE_CODE (arg0
) == VECTOR_CST
10974 && TREE_CODE (arg1
) == VECTOR_CST
10975 && TREE_CODE (arg2
) == INTEGER_CST
)
10977 bool overflow
= false;
10978 widest_int result
= wi::to_widest (arg2
);
10982 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10984 tree e0
= VECTOR_CST_ELT (arg0
, i
);
10985 tree e1
= VECTOR_CST_ELT (arg1
, i
);
10987 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
10989 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
10990 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
10991 if (wi::neg_p (tmp
))
10992 tmp
= wi::neg (tmp
, &neg2_ovf
);
10995 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
10996 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
10999 gcc_assert (!overflow
);
11001 return wide_int_to_tree (rtype
, result
);
11011 /* ??? This duplicates information provided to the compiler by the
11012 ??? scheduler description. Some day, teach genautomata to output
11013 ??? the latencies and then CSE will just use that. */
11016 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
11017 int opno ATTRIBUTE_UNUSED
,
11018 int *total
, bool speed ATTRIBUTE_UNUSED
)
11020 int code
= GET_CODE (x
);
11021 bool float_mode_p
= FLOAT_MODE_P (mode
);
11032 case CONST_WIDE_INT
:
11034 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
11036 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
11055 /* If outer-code was a sign or zero extension, a cost
11056 of COSTS_N_INSNS (1) was already added in. This is
11057 why we are subtracting it back out. */
11058 if (outer_code
== ZERO_EXTEND
)
11060 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11062 else if (outer_code
== SIGN_EXTEND
)
11064 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11066 else if (float_mode_p
)
11068 *total
= sparc_costs
->float_load
;
11072 *total
= sparc_costs
->int_load
;
11080 *total
= sparc_costs
->float_plusminus
;
11082 *total
= COSTS_N_INSNS (1);
11089 gcc_assert (float_mode_p
);
11090 *total
= sparc_costs
->float_mul
;
11093 if (GET_CODE (sub
) == NEG
)
11094 sub
= XEXP (sub
, 0);
11095 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
11098 if (GET_CODE (sub
) == NEG
)
11099 sub
= XEXP (sub
, 0);
11100 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
11106 *total
= sparc_costs
->float_mul
;
11107 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
11108 *total
= COSTS_N_INSNS (25);
11114 if (sparc_costs
->int_mul_bit_factor
)
11118 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11120 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11121 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11129 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11130 bit_cost
= COSTS_N_INSNS (bit_cost
);
11133 if (mode
== DImode
|| !TARGET_HARD_MUL
)
11134 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11136 *total
= sparc_costs
->int_mul
+ bit_cost
;
11143 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
11152 if (mode
== DFmode
)
11153 *total
= sparc_costs
->float_div_df
;
11155 *total
= sparc_costs
->float_div_sf
;
11159 if (mode
== DImode
)
11160 *total
= sparc_costs
->int_divX
;
11162 *total
= sparc_costs
->int_div
;
11167 if (! float_mode_p
)
11169 *total
= COSTS_N_INSNS (1);
11176 case UNSIGNED_FLOAT
:
11180 case FLOAT_TRUNCATE
:
11181 *total
= sparc_costs
->float_move
;
11185 if (mode
== DFmode
)
11186 *total
= sparc_costs
->float_sqrt_df
;
11188 *total
= sparc_costs
->float_sqrt_sf
;
11193 *total
= sparc_costs
->float_cmp
;
11195 *total
= COSTS_N_INSNS (1);
11200 *total
= sparc_costs
->float_cmove
;
11202 *total
= sparc_costs
->int_cmove
;
11206 /* Handle the NAND vector patterns. */
11207 if (sparc_vector_mode_supported_p (mode
)
11208 && GET_CODE (XEXP (x
, 0)) == NOT
11209 && GET_CODE (XEXP (x
, 1)) == NOT
)
11211 *total
= COSTS_N_INSNS (1);
11222 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11225 general_or_i64_p (reg_class_t rclass
)
11227 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
11230 /* Implement TARGET_REGISTER_MOVE_COST. */
11233 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
11234 reg_class_t from
, reg_class_t to
)
11236 bool need_memory
= false;
11238 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
11239 need_memory
= true;
11240 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
11241 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
11245 int size
= GET_MODE_SIZE (mode
);
11246 if (size
== 8 || size
== 4)
11248 if (! TARGET_ARCH32
|| size
== 4)
11254 need_memory
= true;
11259 if (sparc_cpu
== PROCESSOR_ULTRASPARC
11260 || sparc_cpu
== PROCESSOR_ULTRASPARC3
11261 || sparc_cpu
== PROCESSOR_NIAGARA
11262 || sparc_cpu
== PROCESSOR_NIAGARA2
11263 || sparc_cpu
== PROCESSOR_NIAGARA3
11264 || sparc_cpu
== PROCESSOR_NIAGARA4
11265 || sparc_cpu
== PROCESSOR_NIAGARA7
)
11274 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11275 This is achieved by means of a manual dynamic stack space allocation in
11276 the current frame. We make the assumption that SEQ doesn't contain any
11277 function calls, with the possible exception of calls to the GOT helper. */
11280 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
11282 /* We must preserve the lowest 16 words for the register save area. */
11283 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
11284 /* We really need only 2 words of fresh stack space. */
11285 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
11288 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11289 SPARC_STACK_BIAS
+ offset
));
11291 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
11292 emit_insn (gen_rtx_SET (slot
, reg
));
11294 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
11298 emit_insn (gen_rtx_SET (reg2
,
11299 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
11300 emit_insn (gen_rtx_SET (reg
, slot
));
11301 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
11304 /* Output the assembler code for a thunk function. THUNK_DECL is the
11305 declaration for the thunk function itself, FUNCTION is the decl for
11306 the target function. DELTA is an immediate constant offset to be
11307 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11308 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11311 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11312 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11315 rtx this_rtx
, funexp
;
11317 unsigned int int_arg_first
;
11319 reload_completed
= 1;
11320 epilogue_completed
= 1;
11322 emit_note (NOTE_INSN_PROLOGUE_END
);
11326 sparc_leaf_function_p
= 1;
11328 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11330 else if (flag_delayed_branch
)
11332 /* We will emit a regular sibcall below, so we need to instruct
11333 output_sibcall that we are in a leaf function. */
11334 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
11336 /* This will cause final.c to invoke leaf_renumber_regs so we
11337 must behave as if we were in a not-yet-leafified function. */
11338 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
11342 /* We will emit the sibcall manually below, so we will need to
11343 manually spill non-leaf registers. */
11344 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
11346 /* We really are in a leaf function. */
11347 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11350 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11351 returns a structure, the structure return pointer is there instead. */
11353 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11354 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
11356 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
11358 /* Add DELTA. When possible use a plain add, otherwise load it into
11359 a register first. */
11362 rtx delta_rtx
= GEN_INT (delta
);
11364 if (! SPARC_SIMM13_P (delta
))
11366 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11367 emit_move_insn (scratch
, delta_rtx
);
11368 delta_rtx
= scratch
;
11371 /* THIS_RTX += DELTA. */
11372 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
11375 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11378 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
11379 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11381 gcc_assert (vcall_offset
< 0);
11383 /* SCRATCH = *THIS_RTX. */
11384 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
11386 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11387 may not have any available scratch register at this point. */
11388 if (SPARC_SIMM13_P (vcall_offset
))
11390 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11391 else if (! fixed_regs
[5]
11392 /* The below sequence is made up of at least 2 insns,
11393 while the default method may need only one. */
11394 && vcall_offset
< -8192)
11396 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
11397 emit_move_insn (scratch2
, vcall_offset_rtx
);
11398 vcall_offset_rtx
= scratch2
;
11402 rtx increment
= GEN_INT (-4096);
11404 /* VCALL_OFFSET is a negative number whose typical range can be
11405 estimated as -32768..0 in 32-bit mode. In almost all cases
11406 it is therefore cheaper to emit multiple add insns than
11407 spilling and loading the constant into a register (at least
11409 while (! SPARC_SIMM13_P (vcall_offset
))
11411 emit_insn (gen_add2_insn (scratch
, increment
));
11412 vcall_offset
+= 4096;
11414 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
11417 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11418 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
11419 gen_rtx_PLUS (Pmode
,
11421 vcall_offset_rtx
)));
11423 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11424 emit_insn (gen_add2_insn (this_rtx
, scratch
));
11427 /* Generate a tail call to the target function. */
11428 if (! TREE_USED (function
))
11430 assemble_external (function
);
11431 TREE_USED (function
) = 1;
11433 funexp
= XEXP (DECL_RTL (function
), 0);
11435 if (flag_delayed_branch
)
11437 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
11438 insn
= emit_call_insn (gen_sibcall (funexp
));
11439 SIBLING_CALL_P (insn
) = 1;
11443 /* The hoops we have to jump through in order to generate a sibcall
11444 without using delay slots... */
11445 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
11449 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
11451 load_got_register (); /* clobbers %o7 */
11452 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
11453 seq
= get_insns ();
11455 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
11457 else if (TARGET_ARCH32
)
11459 emit_insn (gen_rtx_SET (scratch
,
11460 gen_rtx_HIGH (SImode
, funexp
)));
11461 emit_insn (gen_rtx_SET (scratch
,
11462 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
11464 else /* TARGET_ARCH64 */
11466 switch (sparc_cmodel
)
11470 /* The destination can serve as a temporary. */
11471 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
11476 /* The destination cannot serve as a temporary. */
11477 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
11479 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
11480 seq
= get_insns ();
11482 emit_and_preserve (seq
, spill_reg
, 0);
11486 gcc_unreachable ();
11490 emit_jump_insn (gen_indirect_jump (scratch
));
11495 /* Run just enough of rest_of_compilation to get the insns emitted.
11496 There's not really enough bulk here to make other passes such as
11497 instruction scheduling worth while. Note that use_thunk calls
11498 assemble_start_function and assemble_end_function. */
11499 insn
= get_insns ();
11500 shorten_branches (insn
);
11501 final_start_function (insn
, file
, 1);
11502 final (insn
, file
, 1);
11503 final_end_function ();
11505 reload_completed
= 0;
11506 epilogue_completed
= 0;
11509 /* Return true if sparc_output_mi_thunk would be able to output the
11510 assembler code for the thunk function specified by the arguments
11511 it is passed, and false otherwise. */
11513 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
11514 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
11515 HOST_WIDE_INT vcall_offset
,
11516 const_tree function ATTRIBUTE_UNUSED
)
11518 /* Bound the loop used in the default method above. */
11519 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
11522 /* How to allocate a 'struct machine_function'. */
11524 static struct machine_function
*
11525 sparc_init_machine_status (void)
11527 return ggc_cleared_alloc
<machine_function
> ();
11530 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11531 We need to emit DTP-relative relocations. */
11534 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
11539 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
11542 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
11545 gcc_unreachable ();
11547 output_addr_const (file
, x
);
11551 /* Do whatever processing is required at the end of a file. */
11554 sparc_file_end (void)
11556 /* If we need to emit the special GOT helper function, do so now. */
11557 if (got_helper_rtx
)
11559 const char *name
= XSTR (got_helper_rtx
, 0);
11560 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
11561 #ifdef DWARF2_UNWIND_INFO
11565 if (USE_HIDDEN_LINKONCE
)
11567 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
11568 get_identifier (name
),
11569 build_function_type_list (void_type_node
,
11571 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
11572 NULL_TREE
, void_type_node
);
11573 TREE_PUBLIC (decl
) = 1;
11574 TREE_STATIC (decl
) = 1;
11575 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
11576 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
11577 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
11578 resolve_unique_section (decl
, 0, flag_function_sections
);
11579 allocate_struct_function (decl
, true);
11580 cfun
->is_thunk
= 1;
11581 current_function_decl
= decl
;
11582 init_varasm_status ();
11583 assemble_start_function (decl
, name
);
11587 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
11588 switch_to_section (text_section
);
11590 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
11591 ASM_OUTPUT_LABEL (asm_out_file
, name
);
11594 #ifdef DWARF2_UNWIND_INFO
11595 do_cfi
= dwarf2out_do_cfi_asm ();
11597 fprintf (asm_out_file
, "\t.cfi_startproc\n");
11599 if (flag_delayed_branch
)
11600 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11601 reg_name
, reg_name
);
11603 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11604 reg_name
, reg_name
);
11605 #ifdef DWARF2_UNWIND_INFO
11607 fprintf (asm_out_file
, "\t.cfi_endproc\n");
11611 if (NEED_INDICATE_EXEC_STACK
)
11612 file_end_indicate_exec_stack ();
11614 #ifdef TARGET_SOLARIS
11615 solaris_file_end ();
11619 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11620 /* Implement TARGET_MANGLE_TYPE. */
11622 static const char *
11623 sparc_mangle_type (const_tree type
)
11626 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
11627 && TARGET_LONG_DOUBLE_128
)
11630 /* For all other types, use normal C++ mangling. */
11635 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11636 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11637 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11640 sparc_emit_membar_for_model (enum memmodel model
,
11641 int load_store
, int before_after
)
11643 /* Bits for the MEMBAR mmask field. */
11644 const int LoadLoad
= 1;
11645 const int StoreLoad
= 2;
11646 const int LoadStore
= 4;
11647 const int StoreStore
= 8;
11649 int mm
= 0, implied
= 0;
11651 switch (sparc_memory_model
)
11654 /* Sequential Consistency. All memory transactions are immediately
11655 visible in sequential execution order. No barriers needed. */
11656 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
11660 /* Total Store Ordering: all memory transactions with store semantics
11661 are followed by an implied StoreStore. */
11662 implied
|= StoreStore
;
11664 /* If we're not looking for a raw barrer (before+after), then atomic
11665 operations get the benefit of being both load and store. */
11666 if (load_store
== 3 && before_after
== 1)
11667 implied
|= StoreLoad
;
11671 /* Partial Store Ordering: all memory transactions with load semantics
11672 are followed by an implied LoadLoad | LoadStore. */
11673 implied
|= LoadLoad
| LoadStore
;
11675 /* If we're not looking for a raw barrer (before+after), then atomic
11676 operations get the benefit of being both load and store. */
11677 if (load_store
== 3 && before_after
== 2)
11678 implied
|= StoreLoad
| StoreStore
;
11682 /* Relaxed Memory Ordering: no implicit bits. */
11686 gcc_unreachable ();
11689 if (before_after
& 1)
11691 if (is_mm_release (model
) || is_mm_acq_rel (model
)
11692 || is_mm_seq_cst (model
))
11694 if (load_store
& 1)
11695 mm
|= LoadLoad
| StoreLoad
;
11696 if (load_store
& 2)
11697 mm
|= LoadStore
| StoreStore
;
11700 if (before_after
& 2)
11702 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
11703 || is_mm_seq_cst (model
))
11705 if (load_store
& 1)
11706 mm
|= LoadLoad
| LoadStore
;
11707 if (load_store
& 2)
11708 mm
|= StoreLoad
| StoreStore
;
11712 /* Remove the bits implied by the system memory model. */
11715 /* For raw barriers (before+after), always emit a barrier.
11716 This will become a compile-time barrier if needed. */
11717 if (mm
|| before_after
== 3)
11718 emit_insn (gen_membar (GEN_INT (mm
)));
11721 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11722 compare and swap on the word containing the byte or half-word. */
11725 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
11726 rtx oldval
, rtx newval
)
11728 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
11729 rtx addr
= gen_reg_rtx (Pmode
);
11730 rtx off
= gen_reg_rtx (SImode
);
11731 rtx oldv
= gen_reg_rtx (SImode
);
11732 rtx newv
= gen_reg_rtx (SImode
);
11733 rtx oldvalue
= gen_reg_rtx (SImode
);
11734 rtx newvalue
= gen_reg_rtx (SImode
);
11735 rtx res
= gen_reg_rtx (SImode
);
11736 rtx resv
= gen_reg_rtx (SImode
);
11737 rtx memsi
, val
, mask
, cc
;
11739 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
11741 if (Pmode
!= SImode
)
11742 addr1
= gen_lowpart (SImode
, addr1
);
11743 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
11745 memsi
= gen_rtx_MEM (SImode
, addr
);
11746 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
11747 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
11749 val
= copy_to_reg (memsi
);
11751 emit_insn (gen_rtx_SET (off
,
11752 gen_rtx_XOR (SImode
, off
,
11753 GEN_INT (GET_MODE (mem
) == QImode
11756 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
11758 if (GET_MODE (mem
) == QImode
)
11759 mask
= force_reg (SImode
, GEN_INT (0xff));
11761 mask
= force_reg (SImode
, GEN_INT (0xffff));
11763 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
11765 emit_insn (gen_rtx_SET (val
,
11766 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11769 oldval
= gen_lowpart (SImode
, oldval
);
11770 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
11772 newval
= gen_lowpart_common (SImode
, newval
);
11773 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
11775 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
11777 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
11779 rtx_code_label
*end_label
= gen_label_rtx ();
11780 rtx_code_label
*loop_label
= gen_label_rtx ();
11781 emit_label (loop_label
);
11783 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
11785 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
11787 emit_move_insn (bool_result
, const1_rtx
);
11789 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
11791 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
11793 emit_insn (gen_rtx_SET (resv
,
11794 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11797 emit_move_insn (bool_result
, const0_rtx
);
11799 cc
= gen_compare_reg_1 (NE
, resv
, val
);
11800 emit_insn (gen_rtx_SET (val
, resv
));
11802 /* Use cbranchcc4 to separate the compare and branch! */
11803 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
11804 cc
, const0_rtx
, loop_label
));
11806 emit_label (end_label
);
11808 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
11810 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
11812 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
11815 /* Expand code to perform a compare-and-swap. */
11818 sparc_expand_compare_and_swap (rtx operands
[])
11820 rtx bval
, retval
, mem
, oldval
, newval
;
11822 enum memmodel model
;
11824 bval
= operands
[0];
11825 retval
= operands
[1];
11827 oldval
= operands
[3];
11828 newval
= operands
[4];
11829 model
= (enum memmodel
) INTVAL (operands
[6]);
11830 mode
= GET_MODE (mem
);
11832 sparc_emit_membar_for_model (model
, 3, 1);
11834 if (reg_overlap_mentioned_p (retval
, oldval
))
11835 oldval
= copy_to_reg (oldval
);
11837 if (mode
== QImode
|| mode
== HImode
)
11838 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
11841 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
11844 if (mode
== SImode
)
11845 gen
= gen_atomic_compare_and_swapsi_1
;
11847 gen
= gen_atomic_compare_and_swapdi_1
;
11848 emit_insn (gen (retval
, mem
, oldval
, newval
));
11850 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
11852 convert_move (bval
, x
, 1);
11855 sparc_emit_membar_for_model (model
, 3, 2);
11859 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
11863 sel
= gen_lowpart (DImode
, sel
);
11867 /* inp = xxxxxxxAxxxxxxxB */
11868 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11869 NULL_RTX
, 1, OPTAB_DIRECT
);
11870 /* t_1 = ....xxxxxxxAxxx. */
11871 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11872 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
11873 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11874 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
11875 /* sel = .......B */
11876 /* t_1 = ...A.... */
11877 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11878 /* sel = ...A...B */
11879 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
11880 /* sel = AAAABBBB * 4 */
11881 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
11882 /* sel = { A*4, A*4+1, A*4+2, ... } */
11886 /* inp = xxxAxxxBxxxCxxxD */
11887 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11888 NULL_RTX
, 1, OPTAB_DIRECT
);
11889 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11890 NULL_RTX
, 1, OPTAB_DIRECT
);
11891 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
11892 NULL_RTX
, 1, OPTAB_DIRECT
);
11893 /* t_1 = ..xxxAxxxBxxxCxx */
11894 /* t_2 = ....xxxAxxxBxxxC */
11895 /* t_3 = ......xxxAxxxBxx */
11896 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11898 NULL_RTX
, 1, OPTAB_DIRECT
);
11899 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11901 NULL_RTX
, 1, OPTAB_DIRECT
);
11902 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
11903 GEN_INT (0x070000),
11904 NULL_RTX
, 1, OPTAB_DIRECT
);
11905 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
11906 GEN_INT (0x07000000),
11907 NULL_RTX
, 1, OPTAB_DIRECT
);
11908 /* sel = .......D */
11909 /* t_1 = .....C.. */
11910 /* t_2 = ...B.... */
11911 /* t_3 = .A...... */
11912 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11913 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
11914 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
11915 /* sel = .A.B.C.D */
11916 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
11917 /* sel = AABBCCDD * 2 */
11918 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
11919 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11923 /* input = xAxBxCxDxExFxGxH */
11924 sel
= expand_simple_binop (DImode
, AND
, sel
,
11925 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
11927 NULL_RTX
, 1, OPTAB_DIRECT
);
11928 /* sel = .A.B.C.D.E.F.G.H */
11929 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
11930 NULL_RTX
, 1, OPTAB_DIRECT
);
11931 /* t_1 = ..A.B.C.D.E.F.G. */
11932 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11933 NULL_RTX
, 1, OPTAB_DIRECT
);
11934 /* sel = .AABBCCDDEEFFGGH */
11935 sel
= expand_simple_binop (DImode
, AND
, sel
,
11936 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
11938 NULL_RTX
, 1, OPTAB_DIRECT
);
11939 /* sel = ..AB..CD..EF..GH */
11940 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11941 NULL_RTX
, 1, OPTAB_DIRECT
);
11942 /* t_1 = ....AB..CD..EF.. */
11943 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11944 NULL_RTX
, 1, OPTAB_DIRECT
);
11945 /* sel = ..ABABCDCDEFEFGH */
11946 sel
= expand_simple_binop (DImode
, AND
, sel
,
11947 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
11948 NULL_RTX
, 1, OPTAB_DIRECT
);
11949 /* sel = ....ABCD....EFGH */
11950 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11951 NULL_RTX
, 1, OPTAB_DIRECT
);
11952 /* t_1 = ........ABCD.... */
11953 sel
= gen_lowpart (SImode
, sel
);
11954 t_1
= gen_lowpart (SImode
, t_1
);
11958 gcc_unreachable ();
11961 /* Always perform the final addition/merge within the bmask insn. */
11962 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, t_1
));
11965 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11968 sparc_frame_pointer_required (void)
11970 /* If the stack pointer is dynamically modified in the function, it cannot
11971 serve as the frame pointer. */
11972 if (cfun
->calls_alloca
)
11975 /* If the function receives nonlocal gotos, it needs to save the frame
11976 pointer in the nonlocal_goto_save_area object. */
11977 if (cfun
->has_nonlocal_label
)
11980 /* In flat mode, that's it. */
11984 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11985 return !(crtl
->is_leaf
&& only_leaf_regs_used ());
11988 /* The way this is structured, we can't eliminate SFP in favor of SP
11989 if the frame pointer is required: we want to use the SFP->HFP elimination
11990 in that case. But the test in update_eliminables doesn't know we are
11991 assuming below that we only do the former elimination. */
11994 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
11996 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
11999 /* Return the hard frame pointer directly to bypass the stack bias. */
12002 sparc_builtin_setjmp_frame_value (void)
12004 return hard_frame_pointer_rtx
;
12007 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12008 they won't be allocated. */
12011 sparc_conditional_register_usage (void)
12013 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
12015 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12016 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12018 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12019 /* then honor it. */
12020 if (TARGET_ARCH32
&& fixed_regs
[5])
12022 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12027 for (regno
= SPARC_FIRST_V9_FP_REG
;
12028 regno
<= SPARC_LAST_V9_FP_REG
;
12030 fixed_regs
[regno
] = 1;
12031 /* %fcc0 is used by v8 and v9. */
12032 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12033 regno
<= SPARC_LAST_V9_FCC_REG
;
12035 fixed_regs
[regno
] = 1;
12040 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12041 fixed_regs
[regno
] = 1;
12043 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12044 /* then honor it. Likewise with g3 and g4. */
12045 if (fixed_regs
[2] == 2)
12046 fixed_regs
[2] = ! TARGET_APP_REGS
;
12047 if (fixed_regs
[3] == 2)
12048 fixed_regs
[3] = ! TARGET_APP_REGS
;
12049 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12050 fixed_regs
[4] = ! TARGET_APP_REGS
;
12051 else if (TARGET_CM_EMBMEDANY
)
12053 else if (fixed_regs
[4] == 2)
12058 /* Disable leaf functions. */
12059 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12060 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12061 leaf_reg_remap
[regno
] = regno
;
12064 global_regs
[SPARC_GSR_REG
] = 1;
12067 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12069 - We can't load constants into FP registers.
12070 - We can't load FP constants into integer registers when soft-float,
12071 because there is no soft-float pattern with a r/F constraint.
12072 - We can't load FP constants into integer registers for TFmode unless
12073 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12074 - Try and reload integer constants (symbolic or otherwise) back into
12075 registers directly, rather than having them dumped to memory. */
12078 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12080 machine_mode mode
= GET_MODE (x
);
12081 if (CONSTANT_P (x
))
12083 if (FP_REG_CLASS_P (rclass
)
12084 || rclass
== GENERAL_OR_FP_REGS
12085 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12086 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12087 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12090 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12091 return GENERAL_REGS
;
12093 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12095 if (! FP_REG_CLASS_P (rclass
)
12096 || !(const_zero_operand (x
, mode
)
12097 || const_all_ones_operand (x
, mode
)))
12104 && (rclass
== EXTRA_FP_REGS
12105 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12107 int regno
= true_regnum (x
);
12109 if (SPARC_INT_REG_P (regno
))
12110 return (rclass
== EXTRA_FP_REGS
12111 ? FP_REGS
: GENERAL_OR_FP_REGS
);
12117 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12118 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12121 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
12125 gcc_assert (! TARGET_ARCH64
);
12127 if (sparc_check_64 (operands
[1], insn
) <= 0)
12128 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
12129 if (which_alternative
== 1)
12130 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
12131 if (GET_CODE (operands
[2]) == CONST_INT
)
12133 if (which_alternative
== 1)
12135 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12136 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
12137 output_asm_insn (mulstr
, operands
);
12138 return "srlx\t%L0, 32, %H0";
12142 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12143 output_asm_insn ("or\t%L1, %3, %3", operands
);
12144 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
12145 output_asm_insn (mulstr
, operands
);
12146 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12147 return "mov\t%3, %L0";
12150 else if (rtx_equal_p (operands
[1], operands
[2]))
12152 if (which_alternative
== 1)
12154 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12155 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
12156 output_asm_insn (mulstr
, operands
);
12157 return "srlx\t%L0, 32, %H0";
12161 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12162 output_asm_insn ("or\t%L1, %3, %3", operands
);
12163 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
12164 output_asm_insn (mulstr
, operands
);
12165 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12166 return "mov\t%3, %L0";
12169 if (sparc_check_64 (operands
[2], insn
) <= 0)
12170 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
12171 if (which_alternative
== 1)
12173 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12174 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
12175 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
12176 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
12177 output_asm_insn (mulstr
, operands
);
12178 return "srlx\t%L0, 32, %H0";
12182 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12183 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
12184 output_asm_insn ("or\t%L1, %3, %3", operands
);
12185 output_asm_insn ("or\t%L2, %4, %4", operands
);
12186 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
12187 output_asm_insn (mulstr
, operands
);
12188 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12189 return "mov\t%3, %L0";
12193 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12194 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12195 and INNER_MODE are the modes describing TARGET. */
12198 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
12199 machine_mode inner_mode
)
12201 rtx t1
, final_insn
, sel
;
12204 t1
= gen_reg_rtx (mode
);
12206 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
12207 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
12212 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
12213 bmask
= 0x45674567;
12216 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
12217 bmask
= 0x67676767;
12220 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
12221 bmask
= 0x77777777;
12224 gcc_unreachable ();
12227 sel
= force_reg (SImode
, GEN_INT (bmask
));
12228 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, const0_rtx
));
12229 emit_insn (final_insn
);
12232 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12233 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12236 vector_init_fpmerge (rtx target
, rtx elt
)
12238 rtx t1
, t2
, t2_low
, t3
, t3_low
;
12240 t1
= gen_reg_rtx (V4QImode
);
12241 elt
= convert_modes (SImode
, QImode
, elt
, true);
12242 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12244 t2
= gen_reg_rtx (V8QImode
);
12245 t2_low
= gen_lowpart (V4QImode
, t2
);
12246 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
12248 t3
= gen_reg_rtx (V8QImode
);
12249 t3_low
= gen_lowpart (V4QImode
, t3
);
12250 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
12252 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
12255 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12256 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12259 vector_init_faligndata (rtx target
, rtx elt
)
12261 rtx t1
= gen_reg_rtx (V4HImode
);
12264 elt
= convert_modes (SImode
, HImode
, elt
, true);
12265 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12267 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
12268 force_reg (SImode
, GEN_INT (6)),
12271 for (i
= 0; i
< 4; i
++)
12272 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
12275 /* Emit code to initialize TARGET to values for individual fields VALS. */
12278 sparc_expand_vector_init (rtx target
, rtx vals
)
12280 const machine_mode mode
= GET_MODE (target
);
12281 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
12282 const int n_elts
= GET_MODE_NUNITS (mode
);
12288 for (i
= 0; i
< n_elts
; i
++)
12290 rtx x
= XVECEXP (vals
, 0, i
);
12291 if (!CONSTANT_P (x
))
12294 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
12300 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
12304 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
12306 if (GET_MODE_SIZE (inner_mode
) == 4)
12308 emit_move_insn (gen_lowpart (SImode
, target
),
12309 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
12312 else if (GET_MODE_SIZE (inner_mode
) == 8)
12314 emit_move_insn (gen_lowpart (DImode
, target
),
12315 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
12319 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
12320 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
12322 emit_move_insn (gen_highpart (word_mode
, target
),
12323 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
12324 emit_move_insn (gen_lowpart (word_mode
, target
),
12325 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
12329 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
12333 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
12336 if (mode
== V8QImode
)
12338 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
12341 if (mode
== V4HImode
)
12343 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
12348 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
12349 for (i
= 0; i
< n_elts
; i
++)
12350 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
12351 i
* GET_MODE_SIZE (inner_mode
)),
12352 XVECEXP (vals
, 0, i
));
12353 emit_move_insn (target
, mem
);
12356 /* Implement TARGET_SECONDARY_RELOAD. */
12359 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
12360 machine_mode mode
, secondary_reload_info
*sri
)
12362 enum reg_class rclass
= (enum reg_class
) rclass_i
;
12364 sri
->icode
= CODE_FOR_nothing
;
12365 sri
->extra_cost
= 0;
12367 /* We need a temporary when loading/storing a HImode/QImode value
12368 between memory and the FPU registers. This can happen when combine puts
12369 a paradoxical subreg in a float/fix conversion insn. */
12370 if (FP_REG_CLASS_P (rclass
)
12371 && (mode
== HImode
|| mode
== QImode
)
12372 && (GET_CODE (x
) == MEM
12373 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
12374 && true_regnum (x
) == -1)))
12375 return GENERAL_REGS
;
12377 /* On 32-bit we need a temporary when loading/storing a DFmode value
12378 between unaligned memory and the upper FPU registers. */
12380 && rclass
== EXTRA_FP_REGS
12382 && GET_CODE (x
) == MEM
12383 && ! mem_min_alignment (x
, 8))
12386 if (((TARGET_CM_MEDANY
12387 && symbolic_operand (x
, mode
))
12388 || (TARGET_CM_EMBMEDANY
12389 && text_segment_operand (x
, mode
)))
12393 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
12395 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
12399 if (TARGET_VIS3
&& TARGET_ARCH32
)
12401 int regno
= true_regnum (x
);
12403 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12404 to move 8-byte values in 4-byte pieces. This only works via
12405 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12406 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12407 an FP_REGS intermediate move. */
12408 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
12409 || ((general_or_i64_p (rclass
)
12410 || rclass
== GENERAL_OR_FP_REGS
)
12411 && SPARC_FP_REG_P (regno
)))
12413 sri
->extra_cost
= 2;
12421 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12422 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12425 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
12427 enum rtx_code rc
= GET_CODE (operands
[1]);
12428 machine_mode cmp_mode
;
12429 rtx cc_reg
, dst
, cmp
;
12432 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
12435 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
12436 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
12438 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
12439 rc
= GET_CODE (cmp
);
12442 if (! rtx_equal_p (operands
[2], dst
)
12443 && ! rtx_equal_p (operands
[3], dst
))
12445 if (reg_overlap_mentioned_p (dst
, cmp
))
12446 dst
= gen_reg_rtx (mode
);
12448 emit_move_insn (dst
, operands
[3]);
12450 else if (operands
[2] == dst
)
12452 operands
[2] = operands
[3];
12454 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
12455 rc
= reverse_condition_maybe_unordered (rc
);
12457 rc
= reverse_condition (rc
);
12460 if (XEXP (cmp
, 1) == const0_rtx
12461 && GET_CODE (XEXP (cmp
, 0)) == REG
12462 && cmp_mode
== DImode
12463 && v9_regcmp_p (rc
))
12464 cc_reg
= XEXP (cmp
, 0);
12466 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
12468 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
12470 emit_insn (gen_rtx_SET (dst
,
12471 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
12473 if (dst
!= operands
[0])
12474 emit_move_insn (operands
[0], dst
);
12479 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
12480 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
12481 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
12482 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
12483 code to be used for the condition mask. */
12486 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
12488 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
12489 enum rtx_code code
= GET_CODE (operands
[3]);
12491 mask
= gen_reg_rtx (Pmode
);
12492 cop0
= operands
[4];
12493 cop1
= operands
[5];
12494 if (code
== LT
|| code
== GE
)
12498 code
= swap_condition (code
);
12499 t
= cop0
; cop0
= cop1
; cop1
= t
;
12502 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
12504 fcmp
= gen_rtx_UNSPEC (Pmode
,
12505 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
12508 cmask
= gen_rtx_UNSPEC (DImode
,
12509 gen_rtvec (2, mask
, gsr
),
12512 bshuf
= gen_rtx_UNSPEC (mode
,
12513 gen_rtvec (3, operands
[1], operands
[2], gsr
),
12516 emit_insn (gen_rtx_SET (mask
, fcmp
));
12517 emit_insn (gen_rtx_SET (gsr
, cmask
));
12519 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
12522 /* On sparc, any mode which naturally allocates into the float
12523 registers should return 4 here. */
12526 sparc_regmode_natural_size (machine_mode mode
)
12528 int size
= UNITS_PER_WORD
;
12532 enum mode_class mclass
= GET_MODE_CLASS (mode
);
12534 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
12541 /* Return TRUE if it is a good idea to tie two pseudo registers
12542 when one has mode MODE1 and one has mode MODE2.
12543 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12544 for any hard reg, then this must be FALSE for correct output.
12546 For V9 we have to deal with the fact that only the lower 32 floating
12547 point registers are 32-bit addressable. */
12550 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
12552 enum mode_class mclass1
, mclass2
;
12553 unsigned short size1
, size2
;
12555 if (mode1
== mode2
)
12558 mclass1
= GET_MODE_CLASS (mode1
);
12559 mclass2
= GET_MODE_CLASS (mode2
);
12560 if (mclass1
!= mclass2
)
12566 /* Classes are the same and we are V9 so we have to deal with upper
12567 vs. lower floating point registers. If one of the modes is a
12568 4-byte mode, and the other is not, we have to mark them as not
12569 tieable because only the lower 32 floating point register are
12570 addressable 32-bits at a time.
12572 We can't just test explicitly for SFmode, otherwise we won't
12573 cover the vector mode cases properly. */
12575 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
12578 size1
= GET_MODE_SIZE (mode1
);
12579 size2
= GET_MODE_SIZE (mode2
);
12580 if ((size1
> 4 && size2
== 4)
12581 || (size2
> 4 && size1
== 4))
12587 /* Implement TARGET_CSTORE_MODE. */
12589 static machine_mode
12590 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
12592 return (TARGET_ARCH64
? DImode
: SImode
);
12595 /* Return the compound expression made of T1 and T2. */
12598 compound_expr (tree t1
, tree t2
)
12600 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
12603 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
12606 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
12611 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
12612 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
12614 /* We generate the equivalent of feholdexcept (&fenv_var):
12616 unsigned int fenv_var;
12617 __builtin_store_fsr (&fenv_var);
12619 unsigned int tmp1_var;
12620 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
12622 __builtin_load_fsr (&tmp1_var); */
12624 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
12625 TREE_ADDRESSABLE (fenv_var
) = 1;
12626 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
12627 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
12629 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
12630 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
12632 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
12633 TREE_ADDRESSABLE (tmp1_var
) = 1;
12634 tree masked_fenv_var
12635 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
12636 build_int_cst (unsigned_type_node
,
12637 ~(accrued_exception_mask
| trap_enable_mask
)));
12639 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
12640 NULL_TREE
, NULL_TREE
);
12642 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
12643 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
12644 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12646 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
12648 /* We reload the value of tmp1_var to clear the exceptions:
12650 __builtin_load_fsr (&tmp1_var); */
12652 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12654 /* We generate the equivalent of feupdateenv (&fenv_var):
12656 unsigned int tmp2_var;
12657 __builtin_store_fsr (&tmp2_var);
12659 __builtin_load_fsr (&fenv_var);
12661 if (SPARC_LOW_FE_EXCEPT_VALUES)
12663 __atomic_feraiseexcept ((int) tmp2_var); */
12665 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
12666 TREE_ADDRESSABLE (tmp2_var
) = 1;
12667 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
12669 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
12670 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
12672 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
12674 tree atomic_feraiseexcept
12675 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
12677 = build_call_expr (atomic_feraiseexcept
, 1,
12678 fold_convert (integer_type_node
, tmp2_var
));
12680 if (SPARC_LOW_FE_EXCEPT_VALUES
)
12682 tree shifted_tmp2_var
12683 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
12684 build_int_cst (unsigned_type_node
, 5));
12686 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
12687 update_call
= compound_expr (update_shift
, update_call
);
12691 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
12694 #include "gt-sparc.h"