1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
79 ;; Virtual FPSCR - bits that are used by FP ops.
82 ;; Virtual FPSCR - bits that are updated by FP ops.
111 (FPSCR_PR 524288) ;; 1 << 19
112 (FPSCR_SZ 1048576) ;; 1 << 20
113 (FPSCR_FR 2097152) ;; 1 << 21
116 (define_c_enum "unspec" [
117 ;; These are used with unspec.
146 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
148 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
152 UNSPEC_GOTOFFFUNCDESC
154 UNSPEC_BUILTIN_STRLEN
157 (define_c_enum "unspecv" [
158 ;; These are used with unspec_volatile.
175 ;; -------------------------------------------------------------------------
177 ;; -------------------------------------------------------------------------
182 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a"
183 (const (symbol_ref "sh_cpu_attr")))
185 (define_attr "endian" "big,little"
186 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
187 (const_string "little") (const_string "big"))))
189 ;; Indicate if the default fpu mode is single precision.
190 (define_attr "fpu_single" "yes,no"
191 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
192 (const_string "yes") (const_string "no"))))
194 (define_attr "fmovd" "yes,no"
195 (const (if_then_else (symbol_ref "TARGET_FMOVD")
196 (const_string "yes") (const_string "no"))))
198 (define_attr "pipe_model" "sh1,sh4"
200 (cond [(symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
201 (const_string "sh1"))))
203 ;; cbranch conditional branch instructions
204 ;; jump unconditional jumps
205 ;; arith ordinary arithmetic
206 ;; arith3 a compound insn that behaves similarly to a sequence of
207 ;; three insns of type arith
208 ;; arith3b like above, but might end with a redirected branch
210 ;; load_si Likewise, SImode variant for general register.
211 ;; fload Likewise, but load to fp register.
213 ;; fstore floating point register to memory
214 ;; move general purpose register to register
215 ;; movi8 8-bit immediate to general purpose register
216 ;; mt_group other sh4 mt instructions
217 ;; fmove register to register, floating point
218 ;; smpy word precision integer multiply
219 ;; dmpy longword or doublelongword precision integer multiply
221 ;; pload load of pr reg, which can't be put into delay slot of rts
222 ;; prset copy register to pr reg, ditto
223 ;; pstore store of pr reg, which can't be put into delay slot of jsr
224 ;; prget copy pr to register, ditto
225 ;; pcload pc relative load of constant value
226 ;; pcfload Likewise, but load to fp register.
227 ;; pcload_si Likewise, SImode variant for general register.
228 ;; rte return from exception
229 ;; sfunc special function call with known used registers
230 ;; call function call
232 ;; fpscr_toggle toggle a bit in the fpscr
233 ;; fdiv floating point divide (or square root)
234 ;; gp_fpul move from general purpose register to fpul
235 ;; fpul_gp move from fpul to general purpose register
236 ;; mac_gp move from mac[lh] to general purpose register
237 ;; gp_mac move from general purpose register to mac[lh]
238 ;; mac_mem move from mac[lh] to memory
239 ;; mem_mac move from memory to mac[lh]
240 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
241 ;; ftrc_s fix_truncsfsi2_i4
242 ;; dfdiv double precision floating point divide (or square root)
243 ;; cwb ic_invalidate_line_i
244 ;; movua SH4a unaligned load
245 ;; fsrra square root reciprocal approximate
246 ;; fsca sine and cosine approximate
247 ;; tls_load load TLS related address
248 ;; nil no-op move, will be deleted.
251 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
252 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
253 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
254 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
255 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
257 (const_string "other"))
259 ;; We define a new attribute namely "insn_class".We use
260 ;; this for the DFA based pipeline description.
262 ;; mt_group SH4 "mt" group instructions.
264 ;; ex_group SH4 "ex" group instructions.
266 ;; ls_group SH4 "ls" group instructions.
268 (define_attr "insn_class"
269 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
270 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
271 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
272 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
273 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
274 (eq_attr "type" "cbranch,jump") (const_string "br_group")
275 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
276 (const_string "fe_group")
277 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
278 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
279 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
280 (const_string "none")))
282 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
283 ;; so these do not belong in an insn group, although they are modeled
284 ;; with their own define_insn_reservations.
286 ;; Indicate what precision must be selected in fpscr for this insn, if any.
287 (define_attr "fp_mode" "single,double,none" (const_string "none"))
289 ;; Indicate if the fpu mode is set by this instruction
290 ;; "unknown" must have the value as "none" in fp_mode, and means
291 ;; that the instruction/abi has left the processor in an unknown
293 ;; "none" means that nothing has changed and no mode is set.
294 ;; This attribute is only used for the Renesas ABI.
295 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
297 ; If a conditional branch destination is within -252..258 bytes away
298 ; from the instruction it can be 2 bytes long. Something in the
299 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
300 ; branches are initially assumed to be 16 bytes long.
301 ; In machine_dependent_reorg, we split all branches that are longer than
304 ;; The maximum range used for SImode constant pool entries is 1018. A final
305 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
306 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
307 ;; instruction around the pool table, 2 bytes of alignment before the table,
308 ;; and 30 bytes of alignment after the table. That gives a maximum total
309 ;; pool size of 1058 bytes.
310 ;; Worst case code/pool content size ratio is 1:2 (using asms).
311 ;; Thus, in the worst case, there is one instruction in front of a maximum
312 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
313 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
314 ;; If we have a forward branch, the initial table will be put after the
315 ;; unconditional branch.
317 ;; ??? We could do much better by keeping track of the actual pcloads within
318 ;; the branch range and in the pcload range in front of the branch range.
320 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
322 (define_attr "short_cbranch_p" "no,yes"
323 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
325 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
327 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
329 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
331 ] (const_string "no")))
333 (define_attr "med_branch_p" "no,yes"
334 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
337 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
339 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
342 ] (const_string "no")))
344 (define_attr "med_cbranch_p" "no,yes"
345 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
348 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
350 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
353 ] (const_string "no")))
355 (define_attr "braf_branch_p" "no,yes"
356 (cond [(match_test "! TARGET_SH2")
358 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
361 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
366 ] (const_string "no")))
368 (define_attr "braf_cbranch_p" "no,yes"
369 (cond [(match_test "! TARGET_SH2")
371 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
374 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
379 ] (const_string "no")))
381 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
382 ;; For wider ranges, we need a combination of a code and a data part.
383 ;; If we can get a scratch register for a long range jump, the code
384 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
385 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
386 ;; long; otherwise, it must be 6 bytes long.
388 ;; All other instructions are two bytes long by default.
390 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
391 ;; but getattrtab doesn't understand this.
392 (define_attr "length" ""
393 (cond [(eq_attr "type" "cbranch")
394 (cond [(eq_attr "short_cbranch_p" "yes")
396 (eq_attr "med_cbranch_p" "yes")
398 (eq_attr "braf_cbranch_p" "yes")
400 ;; ??? using pc is not computed transitively.
401 (ne (match_dup 0) (match_dup 0))
403 (match_test "flag_pic")
406 (eq_attr "type" "jump")
407 (cond [(eq_attr "med_branch_p" "yes")
409 (and (match_test "prev_nonnote_insn (insn)")
410 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
412 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
413 (symbol_ref "code_for_indirect_jump_scratch"))))
414 (cond [(eq_attr "braf_branch_p" "yes")
416 (not (match_test "flag_pic"))
418 (match_test "TARGET_SH2")
419 (const_int 10)] (const_int 18))
420 (eq_attr "braf_branch_p" "yes")
422 ;; ??? using pc is not computed transitively.
423 (ne (match_dup 0) (match_dup 0))
425 (match_test "flag_pic")
430 ;; DFA descriptions for the pipelines
435 (include "iterators.md")
436 (include "predicates.md")
437 (include "constraints.md")
439 ;; Definitions for filling delay slots
441 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
443 (define_attr "banked" "yes,no"
444 (cond [(match_test "sh_loads_bankedreg_p (insn)")
445 (const_string "yes")]
446 (const_string "no")))
448 ;; ??? This should be (nil) instead of (const_int 0)
449 (define_attr "hit_stack" "yes,no"
450 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
452 (const_string "yes")))
454 (define_attr "interrupt_function" "no,yes"
455 (const (symbol_ref "current_function_interrupt")))
457 (define_attr "in_delay_slot" "yes,no"
458 (cond [(eq_attr "type" "cbranch") (const_string "no")
459 (eq_attr "type" "pcload,pcload_si") (const_string "no")
460 (eq_attr "type" "fpscr_toggle") (const_string "no")
461 (eq_attr "needs_delay_slot" "yes") (const_string "no")
462 (eq_attr "length" "2") (const_string "yes")
463 ] (const_string "no")))
465 (define_attr "cond_delay_slot" "yes,no"
466 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
467 ] (const_string "no")))
469 (define_attr "is_sfunc" ""
470 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
472 ;; SH4 Double-precision computation with double-precision result -
473 ;; the two halves are ready at different times.
474 (define_attr "dfp_comp" "yes,no"
475 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
476 (const_string "no")))
478 ;; Insns for which the latency of a preceding fp insn is decreased by one.
479 (define_attr "late_fp_use" "yes,no" (const_string "no"))
480 ;; And feeding insns for which this relevant.
481 (define_attr "any_fp_comp" "yes,no"
482 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
483 (const_string "yes")]
484 (const_string "no")))
486 (define_attr "any_int_load" "yes,no"
487 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
488 (const_string "yes")]
489 (const_string "no")))
491 (define_attr "highpart" "user, ignore, extend, depend, must_split"
492 (const_string "user"))
495 (eq_attr "needs_delay_slot" "yes")
496 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
498 ;; Since a normal return (rts) implicitly uses the PR register,
499 ;; we can't allow PR register loads in an rts delay slot.
500 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
501 ;; stack, and thus we can't put a pop instruction in its delay slot.
502 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
503 ;; pop instruction can go in the delay slot, unless it references a banked
504 ;; register (the register bank is switched by rte).
506 (eq_attr "type" "return")
507 [(and (eq_attr "in_delay_slot" "yes")
508 (ior (and (eq_attr "interrupt_function" "no")
509 (eq_attr "type" "!pload,prset"))
510 (and (eq_attr "interrupt_function" "yes")
511 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
512 (eq_attr "banked" "no"))))
515 ;; Since a call implicitly uses the PR register, we can't allow
516 ;; a PR register store in a jsr delay slot.
519 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
520 [(and (eq_attr "in_delay_slot" "yes")
521 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
523 ;; Conditional branches with delay slots are available starting with SH2.
524 ;; If zero displacement conditional branches are fast, disable the delay
525 ;; slot if the branch jumps over only one 2-byte insn.
527 (and (eq_attr "type" "cbranch")
528 (match_test "TARGET_SH2")
529 (not (and (match_test "TARGET_ZDCBRANCH")
530 (match_test "sh_cbranch_distance (insn, 4) == 2"))))
531 [(eq_attr "cond_delay_slot" "yes") (nil) (nil)])
533 ;; -------------------------------------------------------------------------
534 ;; SImode signed integer comparisons
535 ;; -------------------------------------------------------------------------
537 ;; Patterns to generate the tst instruction which are usually formed by
539 ;; The canonical form here being used is (eq (and (op) (op)) 0).
540 ;; For some bit patterns, such as contiguous bits, we also must accept
541 ;; zero_extract forms. Single bit tests are also handled via zero_extract
542 ;; patterns in the 'bit field extract patterns' section. All variants
543 ;; are eventually converted to the 'tstsi_t' insn.
544 ;; As long as pseudos can be created (before RA), 'tstsi_t' will also accept
545 ;; constants that won't fit into 8 bits. After having captured the constant
546 ;; we can decide better whether/how to load it into a register and do other
547 ;; post-combine optimizations such as bypassing sign/zero extensions.
548 (define_insn_and_split "tstsi_t"
550 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "%z,r")
551 (match_operand:SI 1 "arith_or_int_operand" "K08,?r"))
554 && (can_create_pseudo_p () || arith_reg_operand (operands[1], SImode)
555 || satisfies_constraint_K08 (operands[1]))"
557 "TARGET_SH1 && can_create_pseudo_p () && CONST_INT_P (operands[1])
558 && !sh_in_recog_treg_set_expr ()"
561 gcc_assert (CONST_INT_P (operands[1]));
563 HOST_WIDE_INT op1val = INTVAL (operands[1]);
564 bool op0_dead_after_this =
565 sh_reg_dead_or_unused_after_insn (curr_insn, REGNO (operands[0]));
571 "tstsi_t: trying to optimize const_int 0x%08x\n",
574 /* See if we can convert a test with a reg and a constant into
575 something simpler, if the reg is known to be zero or sign
577 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
579 if (eop0.ext_code != UNKNOWN)
581 /* Adjust the constant, trying to eliminate bits that are not
582 contributing to the result. */
583 if (eop0.from_mode == QImode)
585 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFFFF80)
587 else if (eop0.from_mode == HImode)
589 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFF8000)
590 ? 0x8000 : 0)) & 0xFFFF;
593 fprintf (dump_file, "tstsi_t: using effective const_int: 0x%08x\n",
596 /* Try to bypass the sign/zero extension first if op0 dies after
598 if (op0_dead_after_this && eop0.can_use_as_unextended_reg ())
601 fprintf (dump_file, "tstsi_t: bypassing sign/zero extension\n");
603 operands[0] = eop0.use_as_unextended_reg (curr_insn);
605 else if ((eop0.from_mode == QImode && op1val == 0xFF)
606 || (eop0.from_mode == HImode && op1val == 0xFFFF))
609 fprintf (dump_file, "tstsi_t: converting to cmpeqsi_t\n");
610 emit_insn (gen_cmpeqsi_t (eop0.use_as_extended_reg (curr_insn),
614 else if (eop0.ext_code == SIGN_EXTEND
615 && ((eop0.from_mode == QImode && op1val == 0x80)
616 || (eop0.from_mode == HImode && op1val == 0x8000)))
619 fprintf (dump_file, "tstsi_t: converting to cmpgesi_t\n");
620 emit_insn (gen_cmpgesi_t (eop0.use_as_extended_reg (curr_insn),
624 else if (!CONST_OK_FOR_K08 (op1val))
627 fprintf (dump_file, "tstsi_t: converting const_int to signed "
630 /* If here we haven't done anything yet. Convert the constant
631 to a signed value to reduce the constant pool size. */
632 operands[0] = eop0.use_as_extended_reg (curr_insn);
634 if (eop0.from_mode == QImode)
635 op1val |= (op1val & 0x80) ? 0xFFFFFFFFFFFFFF00LL : 0;
636 else if (eop0.from_mode == HImode)
637 op1val |= (op1val & 0x8000) ? 0xFFFFFFFFFFFF0000LL : 0;
640 operands[0] = eop0.use_as_extended_reg (curr_insn);
645 fprintf (dump_file, "tstsi_t: using const_int 0x%08x\n",
648 /* Try to fit the constant into 8 bits by shuffling the value in the
650 Doing that usually results in smaller code as the constants in the
651 pools are avoided (32 bit constant = load + constant = 6 bytes).
652 However, if the constant load (LS insn) can be hoisted insn dependencies
653 can be avoided and chances for parallel execution increase. The common
659 FIXME: For now we do that only when optimizing for size until there is
662 FIXME: If there are multiple tst insns in the block with the same
663 constant, avoid the #imm variant to avoid R0 loads. Use the 'tst Rn,Rm'
664 variant instead and load the constant into a reg. For that we'd need
665 to do some analysis. */
667 if (CONST_OK_FOR_K08 (op1val))
671 else if ((op1val & 0xFFFF) == 0
672 && CONST_OK_FOR_K08 (op1val >> 16) && optimize_size)
674 /* Use a swap.w insn to do a shift + reg copy (to R0) in one insn. */
675 op1val = op1val >> 16;
676 rtx r = gen_reg_rtx (SImode);
677 emit_insn (gen_rotlsi3_16 (r, operands[0]));
680 else if ((op1val & 0xFF) == 0
681 && CONST_OK_FOR_K08 (op1val >> 8) && optimize_size)
683 /* Use a swap.b insn to do a shift + reg copy (to R0) in one insn. */
684 op1val = op1val >> 8;
685 rtx r = gen_reg_rtx (SImode);
686 emit_insn (gen_swapbsi2 (r, operands[0]));
689 else if ((op1val & 3) == 0
690 && CONST_OK_FOR_K08 (op1val >> 2) && optimize_size)
692 op1val = op1val >> 2;
693 rtx r = gen_reg_rtx (SImode);
694 emit_insn (gen_lshrsi3_k (r, operands[0], GEN_INT (2)));
697 else if ((op1val & 1) == 0
698 && CONST_OK_FOR_K08 (op1val >> 1) && optimize_size)
700 op1val = op1val >> 1;
701 rtx r = gen_reg_rtx (SImode);
702 emit_insn (gen_shlr (r, operands[0]));
706 operands[1] = GEN_INT (op1val);
708 if (!satisfies_constraint_K08 (operands[1]))
709 operands[1] = force_reg (SImode, operands[1]);
711 emit_insn (gen_tstsi_t (operands[0], operands[1]));
714 [(set_attr "type" "mt_group")])
716 ;; This pattern is used by combine when testing QI/HImode subregs with a
717 ;; negative constant. Ignore high bits by masking them out in the constant.
718 (define_insn_and_split "*tst<mode>_t"
721 (and:QIHI (match_operand:QIHI 0 "arith_reg_operand")
722 (match_operand 1 "const_int_operand")) 0)
724 "TARGET_SH1 && can_create_pseudo_p ()"
728 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
730 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
731 operands[1] = GEN_INT (INTVAL (operands[1])
732 & (<MODE>mode == HImode ? 0xFFFF : 0xFF));
735 ;; This pattern might be risky because it also tests the upper bits and not
736 ;; only the subreg. We have to check whether the operands have been sign
737 ;; or zero extended. In the worst case, a zero extension has to be inserted
738 ;; to mask out the unwanted bits.
739 (define_insn_and_split "*tst<mode>_t_subregs"
743 (and:SI (match_operand:SI 0 "arith_reg_operand")
744 (match_operand:SI 1 "arith_reg_operand")) <lowpart_le>)
746 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()"
748 "&& !sh_in_recog_treg_set_expr ()"
751 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_le>, operands);
755 (define_insn_and_split "*tst<mode>_t_subregs"
759 (and:SI (match_operand:SI 0 "arith_reg_operand")
760 (match_operand:SI 1 "arith_reg_operand")) <lowpart_be>)
762 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()"
764 "&& !sh_in_recog_treg_set_expr ()"
767 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_be>, operands);
771 ;; Extract contiguous bits and compare them against zero.
772 ;; Notice that this will not be used for single bits. Special single bit
773 ;; extraction patterns are in the 'bit field extract patterns' section.
774 (define_insn_and_split "*tst<mode>_t_zero_extract"
776 (eq:SI (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
777 (match_operand 1 "const_int_operand")
778 (match_operand 2 "const_int_operand"))
780 "TARGET_SH1 && can_create_pseudo_p ()"
784 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
786 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
787 if (GET_MODE (operands[0]) != SImode)
788 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
791 ;; Convert '(reg << shift) & mask' into 'reg & (mask >> shift)'.
792 ;; The shifted-out bits in the mask will always be zero, since the
793 ;; shifted-in bits in the reg will also be always zero.
794 (define_insn_and_split "*tstsi_t_shift_mask"
796 (eq:SI (and:SI (ashift:SI (match_operand:SI 0 "arith_reg_operand")
797 (match_operand 1 "const_int_operand"))
798 (match_operand 2 "const_int_operand"))
800 "TARGET_SH1 && can_create_pseudo_p ()"
804 (eq:SI (and:SI (match_dup 0) (match_dup 2)) (const_int 0)))]
806 operands[2] = GEN_INT (INTVAL (operands[2]) >> INTVAL (operands[1]));
809 (define_insn "cmpeqsi_t"
811 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
812 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
818 [(set_attr "type" "mt_group")])
820 ;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn.
821 ;; Try to fix that in the split1 pass by looking for the previous set
822 ;; of the tested op. Also see if there is a preceeding sign/zero
823 ;; extension that can be avoided.
826 (eq:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
827 "TARGET_SH1 && can_create_pseudo_p () && optimize
828 && !sh_in_recog_treg_set_expr ()"
829 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
832 fprintf (dump_file, "cmpeqsi_t: trying to optimize const_int 0\n");
834 /* If the tested reg is not dead after this insn, it's probably used by
835 something else after the comparison. It's probably better to leave
837 if (find_regno_note (curr_insn, REG_DEAD, REGNO (operands[0])) == NULL_RTX)
840 /* FIXME: Maybe also search the predecessor basic blocks to catch
842 set_of_reg op = sh_find_set_of_reg (operands[0], curr_insn,
843 prev_nonnote_insn_bb);
845 if (op.set_src != NULL && GET_CODE (op.set_src) == AND
846 && !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn))
849 fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n",
852 if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode)
853 && (arith_reg_operand (XEXP (op.set_src, 1), SImode)
854 || CONST_INT_P (XEXP (op.set_src, 1)))))
857 /* Assume that the operands of the andsi insn are compatible with the
858 operands of the tstsi_t insn, which is generally the case. */
860 fprintf (dump_file, "cmpeqsi_t: replacing with tstsi_t\n");
861 emit_insn (gen_tstsi_t (XEXP (op.set_src, 0), XEXP (op.set_src, 1)));
865 /* Converting HImode into tests against 0xFFFF tends to increase the code
866 size, as it will create constant pool entries. Disable it for now. */
867 const bool enable_himode = false;
869 /* FIXME: try to keep the (eq (reg) (const_int 0)). Even if the zero
870 extended reg is used after this insn, if we know that _before_ the zero
871 extension the value was loaded via sign extending mem load, we can just
872 use the value of the mem load directly. */
873 sh_extending_set_of_reg eop = sh_find_extending_set_of_reg (operands[0],
876 if (eop.ext_code != UNKNOWN
877 && (eop.from_mode == QImode || (eop.from_mode == HImode && enable_himode))
878 && eop.can_use_as_unextended_reg ()
879 && !reg_used_between_p (operands[0], eop.insn, curr_insn))
881 /* Bypass the sign/zero extension and test against the bit mask, but
882 only if it's the only use of the sign/zero extracted value.
883 Otherwise we'd be introducing new constants in the pool. */
885 fprintf (dump_file, "cmpeqsi_t: bypassing sign/zero extension in "
886 "insn %d and using tstsi_t\n", INSN_UID (op.insn));
888 emit_insn (gen_tstsi_t (
889 eop.use_as_unextended_reg (curr_insn),
890 GEN_INT (eop.from_mode == QImode ? 0xFF : 0xFFFF)));
895 fprintf (dump_file, "cmpeqsi_t: nothing optimized\n");
899 (define_insn "cmpgtsi_t"
901 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
902 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
907 [(set_attr "type" "mt_group")])
909 (define_insn "cmpgesi_t"
911 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
912 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
917 [(set_attr "type" "mt_group")])
919 ;; Recombine a cmp/pz followed by a nott into a shll.
920 ;; On non-SH2A recombine a cmp/pz followed by a movrt into shll-movt.
921 ;; On SH2A cmp/pz-movrt is slightly better, as it does not mutate the input.
924 (ge:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
926 "TARGET_SH1 && can_create_pseudo_p () && optimize
927 && !sh_in_recog_treg_set_expr ()"
931 fprintf (dump_file, "cmpgesi_t: trying to optimize for const_int 0\n");
933 rtx_insn* i = next_nonnote_insn_bb (curr_insn);
937 fprintf (dump_file, "cmpgesi_t: following insn is \n");
938 print_rtl_single (dump_file, i);
939 fprintf (dump_file, "\n");
942 if (sh_is_nott_insn (i))
946 "cmpgesi_t: replacing (cmp/pz, nott) with (shll)\n");
947 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
948 set_insn_deleted (i);
952 /* On non-SH2A negc is used as movrt replacement, which sets T = 1.
953 Thus we can remove it only if T is marked as dead afterwards. */
954 if (rtx dest_reg = !TARGET_SH2A
955 && sh_reg_dead_or_unused_after_insn (i, T_REG)
956 ? sh_movrt_set_dest (i) : NULL)
960 "cmpgesi_t: replacing (cmp/pz, movrt) with (shll, movt)\n");
961 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
962 add_reg_note (emit_insn (gen_movt (dest_reg, get_t_reg_rtx ())),
963 REG_DEAD, get_t_reg_rtx ());
964 set_insn_deleted (i);
969 fprintf (dump_file, "cmpgesi_t: nothing optimized\n");
974 ;; FIXME: This is actually wrong. There is no way to literally move a
975 ;; general reg to t reg. Luckily, it seems that this pattern will be only
976 ;; used when the general reg is known be either '0' or '1' during combine.
977 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
978 ;; Due to interactions with other patterns, combine fails to pick the latter
979 ;; and invert the dependent logic.
980 (define_insn "*negtstsi"
981 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
982 "TARGET_SH1 && !sh_in_recog_treg_set_expr ()"
984 [(set_attr "type" "mt_group")])
986 ;; Some integer sign comparison patterns can be realized with the div0s insn.
987 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
989 ;; The 'cmp_div0s' pattern is our canonical form, into which all the other
990 ;; variations are converted. The negative forms will split into a trailing
991 ;; nott sequence, which will be eliminated either by the
992 ;; 'any_treg_expr_to_reg' pattern, or by the 'sh_treg_combine' pass.
993 (define_insn "cmp_div0s"
995 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
996 (match_operand:SI 1 "arith_reg_operand" "r"))
1000 [(set_attr "type" "arith")])
1002 (define_insn_and_split "*cmp_div0s_1"
1003 [(set (reg:SI T_REG)
1004 (xor:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1006 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1008 "TARGET_SH1 && can_create_pseudo_p ()"
1011 [(set (reg:SI T_REG)
1012 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1014 (define_insn_and_split "*cmp_div0s_2"
1015 [(set (reg:SI T_REG)
1016 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1018 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1020 "TARGET_SH1 && can_create_pseudo_p ()"
1023 [(set (reg:SI T_REG)
1024 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1026 (define_insn_and_split "*cmp_div0s_3"
1027 [(set (reg:SI T_REG)
1028 (eq:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1030 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1032 "TARGET_SH1 && can_create_pseudo_p ()"
1035 [(set (reg:SI T_REG)
1036 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1037 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1039 (define_insn_and_split "*cmp_div0s_4"
1040 [(set (reg:SI T_REG)
1041 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1042 (match_operand:SI 1 "arith_reg_operand"))
1044 "TARGET_SH1 && can_create_pseudo_p ()"
1047 [(set (reg:SI T_REG)
1048 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1049 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1051 (define_insn_and_split "*cmp_div0s_5"
1052 [(set (reg:SI T_REG)
1053 (xor:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1055 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1057 "TARGET_SH1 && can_create_pseudo_p ()"
1060 [(set (reg:SI T_REG)
1061 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1062 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1064 (define_insn_and_split "*cmp_div0s_6"
1065 [(set (reg:SI T_REG)
1066 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1068 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1070 "TARGET_SH1 && can_create_pseudo_p ()"
1073 [(set (reg:SI T_REG)
1074 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1075 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1077 ;; In some cases, it might be shorter to get a tested bit into bit 31 and
1078 ;; use div0s. Otherwise it's usually better to just leave the xor and tst
1079 ;; sequence. The only thing we can try to do here is avoiding the large
1081 (define_insn_and_split "*cmp_div0s_7"
1082 [(set (reg:SI T_REG)
1083 (zero_extract:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1084 (match_operand:SI 1 "arith_reg_operand"))
1086 (match_operand 2 "const_int_operand")))]
1087 "TARGET_SH1 && can_create_pseudo_p ()
1088 && (INTVAL (operands[2]) == 7 || INTVAL (operands[2]) == 15
1089 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1090 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1095 const int bitpos = INTVAL (operands[2]);
1097 rtx op0 = gen_reg_rtx (SImode);
1098 rtx op1 = gen_reg_rtx (SImode);
1100 if (bitpos == 23 || bitpos == 30 || bitpos == 29)
1102 emit_insn (gen_ashlsi3 (op0, operands[0], GEN_INT (31 - bitpos)));
1103 emit_insn (gen_ashlsi3 (op1, operands[1], GEN_INT (31 - bitpos)));
1105 else if (bitpos == 15)
1107 emit_insn (gen_extendhisi2 (op0, gen_lowpart (HImode, operands[0])));
1108 emit_insn (gen_extendhisi2 (op1, gen_lowpart (HImode, operands[1])));
1110 else if (bitpos == 7)
1112 emit_insn (gen_extendqisi2 (op0, gen_lowpart (QImode, operands[0])));
1113 emit_insn (gen_extendqisi2 (op1, gen_lowpart (QImode, operands[1])));
1115 else if (bitpos == 31)
1123 emit_insn (gen_cmp_div0s (op0, op1));
1127 ;; For bits 0..7 using a xor and tst #imm,r0 sequence seems to be better.
1128 ;; Thus allow the following patterns only for higher bit positions where
1129 ;; we it's more likely to save the large tst constant.
1130 (define_insn_and_split "*cmp_div0s_8"
1131 [(set (reg:SI T_REG)
1132 (eq:SI (zero_extract:SI (match_operand:SI 0 "arith_reg_operand")
1134 (match_operand 2 "const_int_operand"))
1135 (zero_extract:SI (match_operand:SI 1 "arith_reg_operand")
1138 "TARGET_SH1 && can_create_pseudo_p ()
1139 && (INTVAL (operands[2]) == 15
1140 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1141 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1144 [(set (reg:SI T_REG)
1145 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1146 (const_int 1) (match_dup 2)))
1147 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1149 (define_insn_and_split "*cmp_div0s_9"
1150 [(set (reg:SI T_REG)
1151 (zero_extract:SI (xor:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1152 (match_operand:SI 1 "arith_reg_operand"))
1153 (match_operand 2 "const_int_operand"))
1155 (match_operand 3 "const_int_operand")))]
1156 "TARGET_SH1 && can_create_pseudo_p ()
1157 && (INTVAL (operands[2]) & 0xFFFFFFFF) == (1U << INTVAL (operands[3]))
1158 && (INTVAL (operands[3]) == 15
1159 || INTVAL (operands[3]) == 23 || INTVAL (operands[3]) == 29
1160 || INTVAL (operands[3]) == 30 || INTVAL (operands[3]) == 31)"
1163 [(set (reg:SI T_REG)
1164 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1165 (const_int 1) (match_dup 3)))
1166 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1168 ;; -------------------------------------------------------------------------
1169 ;; SImode compare and branch
1170 ;; -------------------------------------------------------------------------
1172 (define_expand "cbranchsi4"
1174 (if_then_else (match_operator 0 "comparison_operator"
1175 [(match_operand:SI 1 "arith_operand" "")
1176 (match_operand:SI 2 "arith_operand" "")])
1177 (label_ref (match_operand 3 "" ""))
1179 (clobber (reg:SI T_REG))]
1180 "can_create_pseudo_p ()"
1182 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
1186 ;; Combine patterns to invert compare and branch operations for which we
1187 ;; don't have actual comparison insns. These patterns are used in cases
1188 ;; which appear after the initial cbranchsi expansion, which also does
1189 ;; some condition inversion.
1192 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
1193 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1194 (label_ref (match_operand 2))
1196 (clobber (reg:SI T_REG))]
1198 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
1199 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1200 (label_ref (match_dup 2))
1203 ;; FIXME: These don't seem to have any effect on the generated cbranch code
1204 ;; anymore, but only on some register allocation choices.
1207 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1208 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1209 (label_ref (match_operand 2))
1211 (clobber (reg:SI T_REG))]
1213 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1214 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1215 (label_ref (match_dup 2))
1220 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1221 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1222 (label_ref (match_operand 2))
1224 (clobber (reg:SI T_REG))]
1226 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1227 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1228 (label_ref (match_dup 2))
1233 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1234 (match_operand:SI 1 "arith_reg_operand" ""))
1235 (label_ref (match_operand 2))
1237 (clobber (reg:SI T_REG))]
1239 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1240 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1241 (label_ref (match_dup 2))
1246 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1247 (match_operand:SI 1 "arith_reg_operand" ""))
1248 (label_ref (match_operand 2))
1250 (clobber (reg:SI T_REG))]
1252 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1253 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1254 (label_ref (match_dup 2))
1257 ;; -------------------------------------------------------------------------
1258 ;; SImode unsigned integer comparisons
1259 ;; -------------------------------------------------------------------------
1261 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1262 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1263 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1264 ;; handled here, something else would just load a '0' into the second operand
1265 ;; and do the comparison. We can do slightly better by just setting the
1267 (define_insn_and_split "cmpgeusi_t"
1268 [(set (reg:SI T_REG)
1269 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1270 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1273 "&& satisfies_constraint_Z (operands[1])"
1274 [(set (reg:SI T_REG) (const_int 1))]
1276 [(set_attr "type" "mt_group")])
1278 (define_insn "cmpgtusi_t"
1279 [(set (reg:SI T_REG)
1280 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1281 (match_operand:SI 1 "arith_reg_operand" "r")))]
1284 [(set_attr "type" "mt_group")])
1286 ;; -------------------------------------------------------------------------
1287 ;; DImode compare and branch
1288 ;; -------------------------------------------------------------------------
1290 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1291 ;; Therefore, we aim to have a set of three branches that go straight to the
1292 ;; destination, i.e. only one of them is taken at any one time.
1293 ;; This mechanism should also be slightly better for the sh4-200.
1295 (define_expand "cbranchdi4"
1297 (if_then_else (match_operator 0 "comparison_operator"
1298 [(match_operand:DI 1 "arith_operand")
1299 (match_operand:DI 2 "arith_operand")])
1300 (label_ref (match_operand 3))
1302 (clobber (reg:SI T_REG))]
1303 "TARGET_SH2 && can_create_pseudo_p ()"
1305 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1310 ;; -------------------------------------------------------------------------
1311 ;; DImode signed integer comparisons
1312 ;; -------------------------------------------------------------------------
1315 [(set (reg:SI T_REG)
1316 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1317 (match_operand:DI 1 "arith_operand" "r"))
1321 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1324 [(set_attr "length" "6")
1325 (set_attr "type" "arith3b")])
1327 (define_insn "cmpeqdi_t"
1328 [(set (reg:SI T_REG)
1329 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1330 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1333 static const char* alt[] =
1340 "cmp/eq %S1,%S0" "\n"
1342 " cmp/eq %R1,%R0" "\n"
1345 return alt[which_alternative];
1347 [(set_attr "length" "6")
1348 (set_attr "type" "arith3b")])
1351 [(set (reg:SI T_REG)
1352 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1353 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1354 ;; If we applied this split when not optimizing, it would only be
1355 ;; applied during the machine-dependent reorg, when no new basic blocks
1357 "TARGET_SH1 && reload_completed && optimize"
1358 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1359 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1360 (label_ref (match_dup 6))
1362 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1365 operands[2] = gen_highpart (SImode, operands[0]);
1366 operands[3] = operands[1] == const0_rtx
1368 : gen_highpart (SImode, operands[1]);
1369 operands[4] = gen_lowpart (SImode, operands[0]);
1370 operands[5] = gen_lowpart (SImode, operands[1]);
1371 operands[6] = gen_label_rtx ();
1374 (define_insn "cmpgtdi_t"
1375 [(set (reg:SI T_REG)
1376 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1377 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1380 static const char* alt[] =
1382 "cmp/eq %S1,%S0" "\n"
1384 " cmp/gt %S1,%S0" "\n"
1385 " cmp/hi %R1,%R0" "\n"
1391 " cmp/hi %S0,%R0" "\n"
1394 return alt[which_alternative];
1396 [(set_attr "length" "8")
1397 (set_attr "type" "arith3")])
1399 (define_insn "cmpgedi_t"
1400 [(set (reg:SI T_REG)
1401 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1402 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1405 static const char* alt[] =
1407 "cmp/eq %S1,%S0" "\n"
1409 " cmp/ge %S1,%S0" "\n"
1410 " cmp/hs %R1,%R0" "\n"
1415 return alt[which_alternative];
1417 [(set_attr "length" "8,2")
1418 (set_attr "type" "arith3,mt_group")])
1420 ;; -------------------------------------------------------------------------
1421 ;; DImode unsigned integer comparisons
1422 ;; -------------------------------------------------------------------------
1424 (define_insn "cmpgeudi_t"
1425 [(set (reg:SI T_REG)
1426 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1427 (match_operand:DI 1 "arith_reg_operand" "r")))]
1430 return "cmp/eq %S1,%S0" "\n"
1432 " cmp/hs %S1,%S0" "\n"
1433 " cmp/hs %R1,%R0" "\n"
1436 [(set_attr "length" "8")
1437 (set_attr "type" "arith3")])
1439 (define_insn "cmpgtudi_t"
1440 [(set (reg:SI T_REG)
1441 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1442 (match_operand:DI 1 "arith_reg_operand" "r")))]
1445 return "cmp/eq %S1,%S0" "\n"
1447 " cmp/hi %S1,%S0" "\n"
1448 " cmp/hi %R1,%R0" "\n"
1451 [(set_attr "length" "8")
1452 (set_attr "type" "arith3")])
1454 ;; -------------------------------------------------------------------------
1455 ;; Conditional move instructions
1456 ;; -------------------------------------------------------------------------
1458 (define_insn "*movsicc_t_false"
1459 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1460 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1461 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1462 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1463 "TARGET_PRETEND_CMOVE
1464 && (arith_reg_operand (operands[1], SImode)
1465 || (immediate_operand (operands[1], SImode)
1466 && satisfies_constraint_I08 (operands[1])))"
1472 [(set_attr "type" "mt_group,arith") ;; poor approximation
1473 (set_attr "length" "4")])
1475 (define_insn "*movsicc_t_true"
1476 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1477 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1478 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1479 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1480 "TARGET_PRETEND_CMOVE
1481 && (arith_reg_operand (operands[1], SImode)
1482 || (immediate_operand (operands[1], SImode)
1483 && satisfies_constraint_I08 (operands[1])))"
1489 [(set_attr "type" "mt_group,arith") ;; poor approximation
1490 (set_attr "length" "4")])
1492 (define_expand "movsicc"
1493 [(set (match_operand:SI 0 "arith_reg_dest" "")
1494 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1495 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1496 (match_operand:SI 3 "arith_reg_operand" "")))]
1497 "TARGET_PRETEND_CMOVE"
1499 rtx_code code = GET_CODE (operands[1]);
1500 rtx_code new_code = code;
1501 rtx op0 = XEXP (operands[1], 0);
1502 rtx op1 = XEXP (operands[1], 1);
1504 if (! currently_expanding_to_rtl)
1509 case LT: case LE: case LEU: case LTU:
1510 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1513 new_code = reverse_condition (code);
1515 case EQ: case GT: case GE: case GEU: case GTU:
1521 sh_emit_scc_to_t (new_code, op0, op1);
1522 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1523 gen_rtx_REG (SImode, T_REG), const0_rtx);
1526 ;; -------------------------------------------------------------------------
1527 ;; Addition instructions
1528 ;; -------------------------------------------------------------------------
1530 (define_insn_and_split "adddi3"
1531 [(set (match_operand:DI 0 "arith_reg_dest")
1532 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1533 (match_operand:DI 2 "arith_reg_operand")))
1534 (clobber (reg:SI T_REG))]
1537 "&& can_create_pseudo_p ()"
1540 emit_insn (gen_clrt ());
1541 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1542 gen_lowpart (SImode, operands[1]),
1543 gen_lowpart (SImode, operands[2])));
1544 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1545 gen_highpart (SImode, operands[1]),
1546 gen_highpart (SImode, operands[2])));
1551 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1552 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1553 (match_operand:SI 2 "arith_reg_operand" "r"))
1556 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1559 [(set_attr "type" "arith")])
1561 ;; A simplified version of the addc insn, where the exact value of the
1562 ;; T bit doesn't matter. This is easier for combine to pick up.
1563 ;; We allow a reg or 0 for one of the operands in order to be able to
1564 ;; do 'reg + T' sequences.
1565 (define_insn_and_split "*addc"
1566 [(set (match_operand:SI 0 "arith_reg_dest")
1567 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1568 (match_operand:SI 2 "arith_reg_or_0_operand"))
1569 (match_operand 3 "treg_set_expr")))
1570 (clobber (reg:SI T_REG))]
1571 "TARGET_SH1 && can_create_pseudo_p ()"
1576 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1577 if (ti.has_trailing_nott ())
1579 if (operands[2] == const0_rtx)
1581 /* op1 + 0 + (1 - T) = op1 + 1 - T = op1 - (-1) - T */
1582 remove_insn (ti.trailing_nott ());
1583 emit_insn (gen_subc (operands[0], operands[1],
1584 force_reg (SImode, GEN_INT (-1))));
1587 else if (!TARGET_SH2A)
1589 /* op1 + op2 + (1 - T) = op1 - (0 - op2 - 1) - T = op1 - ~op2 - T
1590 On SH2A keep the nott insn, because nott-addc sequence doesn't
1591 mutate the inputs. */
1592 remove_insn (ti.trailing_nott ());
1593 rtx tmp = gen_reg_rtx (SImode);
1594 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1595 emit_insn (gen_subc (operands[0], operands[1], tmp));
1600 emit_insn (gen_addc (operands[0], operands[1],
1601 force_reg (SImode, operands[2])));
1605 (define_insn_and_split "*addc"
1606 [(set (match_operand:SI 0 "arith_reg_dest")
1607 (plus:SI (plus:SI (match_operand 1 "treg_set_expr")
1608 (match_operand:SI 2 "arith_reg_operand"))
1609 (match_operand:SI 3 "arith_reg_operand")))
1610 (clobber (reg:SI T_REG))]
1611 "TARGET_SH1 && can_create_pseudo_p ()"
1614 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1616 (clobber (reg:SI T_REG))])])
1618 (define_insn_and_split "*addc"
1619 [(set (match_operand:SI 0 "arith_reg_dest")
1620 (plus:SI (match_operand 1 "treg_set_expr")
1621 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1622 (match_operand:SI 3 "arith_reg_operand"))))
1623 (clobber (reg:SI T_REG))]
1624 "TARGET_SH1 && can_create_pseudo_p ()"
1627 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1629 (clobber (reg:SI T_REG))])])
1631 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1632 ;; matched. Split this up into a simple sub add sequence, as this will save
1633 ;; us one sett insn.
1634 (define_insn_and_split "*minus_plus_one"
1635 [(set (match_operand:SI 0 "arith_reg_dest" "")
1636 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1637 (match_operand:SI 2 "arith_reg_operand" ""))
1642 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1643 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1646 ;; The tree optimiziers canonicalize
1651 ;; On SH2A an add-bclr sequence will be used to handle this.
1652 ;; On non-SH2A re-emit the add-and sequence to improve register utilization.
1653 (define_insn_and_split "*round_int_even"
1654 [(set (match_operand:SI 0 "arith_reg_dest")
1655 (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1658 "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p ()
1659 && !reg_overlap_mentioned_p (operands[0], operands[1])"
1662 [(set (match_dup 0) (const_int -2))
1663 (set (match_dup 2) (plus:SI (match_dup 1) (const_int 1)))
1664 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))]
1666 operands[2] = gen_reg_rtx (SImode);
1669 ;; If the *round_int_even pattern is combined with another plus,
1670 ;; convert it into an addc pattern to emit an shlr-addc sequence.
1671 ;; This split is taken by combine on non-SH2A and SH2A.
1673 [(set (match_operand:SI 0 "arith_reg_dest")
1674 (plus:SI (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1677 (match_operand:SI 2 "arith_reg_operand")))]
1678 "TARGET_SH1 && can_create_pseudo_p ()"
1679 [(parallel [(set (match_dup 0)
1680 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1681 (and:SI (match_dup 1) (const_int 1))))
1682 (clobber (reg:SI T_REG))])])
1684 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1685 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1686 ;; operation, as opposed to sequences such as
1690 ;; Even if the constant is not CSE-ed, a sequence such as
1693 ;; can be scheduled much better since the load of the constant can be
1694 ;; done earlier, before any comparison insns that store the result in
1696 ;; However, avoid things like 'reg + 1', which would expand into a
1697 ;; 3 insn sequence, instead of add #imm8.
1698 (define_insn_and_split "*addc_t_r"
1699 [(set (match_operand:SI 0 "arith_reg_dest")
1700 (plus:SI (match_operand 1 "treg_set_expr_not_const01")
1701 (match_operand:SI 2 "arith_reg_operand")))
1702 (clobber (reg:SI T_REG))]
1703 "TARGET_SH1 && can_create_pseudo_p ()"
1706 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (const_int 0))
1708 (clobber (reg:SI T_REG))])])
1710 (define_insn_and_split "*addc_r_t"
1711 [(set (match_operand:SI 0 "arith_reg_dest")
1712 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1713 (match_operand 2 "treg_set_expr_not_const01")))
1714 (clobber (reg:SI T_REG))]
1715 "TARGET_SH1 && can_create_pseudo_p ()"
1718 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (const_int 0))
1720 (clobber (reg:SI T_REG))])])
1722 ;; Convert '2 * reg + T' into 'reg + reg + T'.
1723 (define_insn_and_split "*addc_2r_t"
1724 [(set (match_operand:SI 0 "arith_reg_dest")
1725 (plus:SI (match_operand 1 "treg_set_expr")
1726 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
1728 (clobber (reg:SI T_REG))]
1729 "TARGET_SH1 && can_create_pseudo_p ()"
1732 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 2))
1734 (clobber (reg:SI T_REG))])])
1736 (define_insn_and_split "*addc_2r_t"
1737 [(set (match_operand:SI 0 "arith_reg_dest")
1738 (plus:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
1740 (match_operand 2 "treg_set_expr")))
1741 (clobber (reg:SI T_REG))]
1742 "TARGET_SH1 && can_create_pseudo_p ()"
1745 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1747 (clobber (reg:SI T_REG))])])
1749 ;; Convert '(op2 + T) - op3' into 'op2 + (-op3) + T'
1750 (define_insn_and_split "*addc_negreg_t"
1751 [(set (match_operand:SI 0 "arith_reg_dest")
1752 (minus:SI (plus:SI (match_operand 1 "treg_set_expr")
1753 (match_operand:SI 2 "arith_reg_operand"))
1754 (match_operand:SI 3 "arith_reg_operand")))
1755 (clobber (reg:SI T_REG))]
1756 "TARGET_SH1 && can_create_pseudo_p ()"
1759 [(set (match_dup 4) (neg:SI (match_dup 3)))
1760 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 4))
1762 (clobber (reg:SI T_REG))])]
1764 operands[4] = gen_reg_rtx (SImode);
1767 (define_expand "addsi3"
1768 [(set (match_operand:SI 0 "arith_reg_dest")
1769 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1770 (match_operand:SI 2 "arith_or_int_operand")))]
1773 if (!arith_operand (operands[2], SImode))
1775 if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1]))
1777 emit_insn (gen_addsi3_scr (operands[0], operands[1], operands[2]));
1783 ;; The *addsi3_compact is made an insn_and_split and accepts actually
1784 ;; impossible constraints to make LRA's register elimination work well on SH.
1785 ;; The problem is that LRA expects something like
1786 ;; (set rA (plus rB (const_int N)))
1787 ;; to work. We can do that, but we have to split out an additional reg-reg
1788 ;; copy or constant load before the actual add insn.
1789 ;; Use u constraint for that case to avoid the invalid value in the stack
1791 ;; This also results in better code when LRA is not used. However, we have
1792 ;; to use different sets of patterns and the order of these patterns is
1794 ;; In some cases the constant zero might end up in operands[2] of the
1795 ;; patterns. We have to accept that and convert it into a reg-reg move.
1796 (define_insn_and_split "*addsi3_compact_lra"
1797 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u")
1798 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1799 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
1800 "TARGET_SH1 && sh_lra_p ()
1801 && (! reg_overlap_mentioned_p (operands[0], operands[1])
1802 || arith_operand (operands[2], SImode))"
1806 "&& reload_completed
1807 && ! reg_overlap_mentioned_p (operands[0], operands[1])"
1808 [(set (match_dup 0) (match_dup 2))
1809 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
1811 /* Prefer 'mov r0,r1; add #imm8,r1' over 'mov #imm8,r1; add r0,r1' */
1812 if (satisfies_constraint_I08 (operands[2]))
1813 std::swap (operands[1], operands[2]);
1815 [(set_attr "type" "arith")])
1817 (define_insn_and_split "addsi3_scr"
1818 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u,&u")
1819 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r,r")
1820 (match_operand:SI 2 "arith_or_int_operand" "rI08,r,n")))
1821 (clobber (match_scratch:SI 3 "=X,X,&u"))]
1827 "&& reload_completed"
1828 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1830 if (operands[2] == const0_rtx)
1832 emit_move_insn (operands[0], operands[1]);
1836 if (CONST_INT_P (operands[2]) && !satisfies_constraint_I08 (operands[2]))
1838 if (reg_overlap_mentioned_p (operands[0], operands[1]))
1840 emit_move_insn (operands[3], operands[2]);
1841 emit_move_insn (operands[0], operands[1]);
1842 operands[2] = operands[3];
1846 emit_move_insn (operands[0], operands[2]);
1847 operands[2] = operands[1];
1850 else if (!reg_overlap_mentioned_p (operands[0], operands[1]))
1852 if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1853 emit_move_insn (operands[0], operands[1]);
1855 operands[2] = operands[1];
1858 [(set_attr "type" "arith")])
1860 ;; Old reload might generate add insns directly (not through the expander) for
1861 ;; address register calculations when reloading, in which case it won't try
1862 ;; the addsi_scr pattern. Because reload will sometimes try to validate
1863 ;; the generated insns and their constraints, this pattern must be
1864 ;; recognizable during and after reload. However, when reload generates
1865 ;; address register calculations for the stack pointer, we don't allow this
1866 ;; pattern. This will make reload prefer using indexed @(reg + reg) address
1867 ;; modes when the displacement of a @(disp + reg) doesn't fit.
1868 (define_insn_and_split "*addsi3"
1869 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1870 (plus:SI (match_operand:SI 1 "arith_reg_operand" "r")
1871 (match_operand:SI 2 "arith_or_int_operand" "rn")))]
1872 "TARGET_SH1 && !sh_lra_p ()
1873 && (reload_completed || reload_in_progress)
1874 && !reg_overlap_mentioned_p (operands[0], operands[1])
1875 && (!reload_in_progress
1876 || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG)
1877 && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))"
1880 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1882 if (operands[2] == const0_rtx)
1884 emit_move_insn (operands[0], operands[1]);
1888 if (CONST_INT_P (operands[2]))
1890 if (satisfies_constraint_I08 (operands[2]))
1891 emit_move_insn (operands[0], operands[1]);
1894 emit_move_insn (operands[0], operands[2]);
1895 operands[2] = operands[1];
1898 else if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1899 emit_move_insn (operands[0], operands[1]);
1901 operands[2] = operands[1];
1904 (define_insn_and_split "*addsi3"
1905 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1906 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1907 (match_operand:SI 2 "arith_operand" "rI08,Z")))]
1908 "TARGET_SH1 && !sh_lra_p ()"
1912 "&& operands[2] == const0_rtx"
1913 [(set (match_dup 0) (match_dup 1))]
1916 [(set_attr "type" "arith")])
1918 ;; -------------------------------------------------------------------------
1919 ;; Subtraction instructions
1920 ;; -------------------------------------------------------------------------
1922 (define_insn_and_split "subdi3"
1923 [(set (match_operand:DI 0 "arith_reg_dest")
1924 (minus:DI (match_operand:DI 1 "arith_reg_operand")
1925 (match_operand:DI 2 "arith_reg_operand")))
1926 (clobber (reg:SI T_REG))]
1929 "&& can_create_pseudo_p ()"
1932 emit_insn (gen_clrt ());
1933 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
1934 gen_lowpart (SImode, operands[1]),
1935 gen_lowpart (SImode, operands[2])));
1936 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
1937 gen_highpart (SImode, operands[1]),
1938 gen_highpart (SImode, operands[2])));
1943 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1944 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1945 (match_operand:SI 2 "arith_reg_operand" "r"))
1948 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1953 [(set_attr "type" "arith")])
1955 ;; A simplified version of the subc insn, where the exact value of the
1956 ;; T bit doesn't matter. This is easier for combine to pick up.
1957 ;; We allow a reg or 0 for one of the operands in order to be able to
1958 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
1960 (define_insn_and_split "*subc"
1961 [(set (match_operand:SI 0 "arith_reg_dest")
1962 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
1963 (match_operand:SI 2 "arith_reg_or_0_operand"))
1964 (match_operand 3 "treg_set_expr")))
1965 (clobber (reg:SI T_REG))]
1966 "TARGET_SH1 && can_create_pseudo_p ()"
1971 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1972 if (ti.has_trailing_nott ())
1974 if (operands[2] == const0_rtx)
1976 /* op1 - (1 - T) = op1 - 1 + T = op1 + (-1) + T */
1977 remove_insn (ti.trailing_nott ());
1978 emit_insn (gen_addc (operands[0], operands[1],
1979 force_reg (SImode, GEN_INT (-1))));
1982 else if (!TARGET_SH2A)
1984 /* op1 - op2 - (1 - T) = op1 + (0 - op2 - 1) + T = op1 + ~op2 + T
1985 On SH2A keep the nott insn, because nott-subc sequence doesn't
1986 mutate the inputs. */
1987 remove_insn (ti.trailing_nott ());
1988 rtx tmp = gen_reg_rtx (SImode);
1989 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1990 emit_insn (gen_addc (operands[0], operands[1], tmp));
1995 emit_insn (gen_subc (operands[0], operands[1],
1996 force_reg (SImode, operands[2])));
2000 ;; Convert reg - T - reg = reg - reg - T
2001 (define_insn_and_split "*subc"
2002 [(set (match_operand:SI 0 "arith_reg_dest")
2003 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2004 (match_operand 2 "treg_set_expr"))
2005 (match_operand:SI 3 "arith_reg_operand")))
2006 (clobber (reg:SI T_REG))]
2007 "TARGET_SH1 && can_create_pseudo_p ()"
2010 [(parallel [(set (match_dup 0)
2011 (minus:SI (minus:SI (match_dup 1) (match_dup 3))
2013 (clobber (reg:SI T_REG))])])
2015 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2016 ;; better, if the sett insn can be done early.
2017 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2018 (define_insn_and_split "*subc"
2019 [(set (match_operand:SI 0 "arith_reg_dest" "")
2020 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2021 (match_operand:SI 2 "arith_reg_operand" "")))
2022 (clobber (reg:SI T_REG))]
2023 "TARGET_SH1 && can_create_pseudo_p ()"
2026 [(parallel [(set (match_dup 0)
2027 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2029 (clobber (reg:SI T_REG))])])
2031 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2032 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2033 ;; operation, as opposed to sequences such as
2037 ;; Even if the constant is not CSE-ed, a sequence such as
2040 ;; can be scheduled much better since the load of the constant can be
2041 ;; done earlier, before any comparison insns that store the result in
2043 ;; However, avoid things like 'reg - 1', which would expand into a
2044 ;; 3 insn sequence, instead of add #imm8.
2045 (define_insn_and_split "*subc"
2046 [(set (match_operand:SI 0 "arith_reg_dest" "")
2047 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2048 (match_operand 2 "treg_set_expr_not_const01")))
2049 (clobber (reg:SI T_REG))]
2050 "TARGET_SH1 && can_create_pseudo_p ()"
2053 [(parallel [(set (match_dup 0)
2054 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2056 (clobber (reg:SI T_REG))])])
2059 ;; (1 - T) - op2 = 1 - op2 - T
2060 (define_insn_and_split "*subc_negt_reg"
2061 [(set (match_operand:SI 0 "arith_reg_dest")
2062 (minus:SI (match_operand 1 "treg_set_expr_not_const01")
2063 (match_operand:SI 2 "arith_reg_operand")))
2064 (clobber (reg:SI T_REG))]
2065 "TARGET_SH1 && can_create_pseudo_p ()"
2070 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
2071 if (ti.remove_trailing_nott ())
2073 /* (1 - T) - op2 = 1 - op2 - T */
2074 emit_insn (gen_subc (operands[0],
2075 force_reg (SImode, GEN_INT (1)), operands[2]));
2079 /* T - op2: use movt,sub sequence. */
2080 rtx tmp = gen_reg_rtx (SImode);
2081 emit_insn (gen_movt (tmp, get_t_reg_rtx ()));
2082 emit_insn (gen_subsi3 (operands[0], tmp, operands[2]));
2088 ;; op1 - (1 - T) + op3 = op1 - 1 + T + op3
2089 ;; (op1 - T) + op3 = op1 - (-op3) - T
2090 (define_insn_and_split "*subc_negreg_t"
2091 [(set (match_operand:SI 0 "arith_reg_dest")
2092 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2093 (match_operand 2 "treg_set_expr"))
2094 (match_operand:SI 3 "arith_reg_operand")))
2095 (clobber (reg:SI T_REG))]
2096 "TARGET_SH1 && can_create_pseudo_p ()"
2101 sh_treg_insns ti = sh_split_treg_set_expr (operands[2], curr_insn);
2102 if (ti.remove_trailing_nott ())
2104 /* op1 - (1 - T) + op3 = (op1 - 1) + op3 + T */
2105 rtx tmp = gen_reg_rtx (SImode);
2106 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-1)));
2107 emit_insn (gen_addc (operands[0], tmp, operands[3]));
2111 /* (op1 - T) + op3' = 'op1 - (-op3) - T */
2112 rtx tmp = gen_reg_rtx (SImode);
2113 emit_insn (gen_negsi2 (tmp, operands[3]));
2114 emit_insn (gen_subc (operands[0], operands[1], tmp));
2119 (define_insn "*subsi3_internal"
2120 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2121 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2122 (match_operand:SI 2 "arith_reg_operand" "r")))]
2125 [(set_attr "type" "arith")])
2132 ;; since this will sometimes save one instruction.
2133 ;; Otherwise we might get a sequence like
2137 ;; if the source and dest regs are the same.
2138 (define_expand "subsi3"
2139 [(set (match_operand:SI 0 "arith_reg_operand" "")
2140 (minus:SI (match_operand:SI 1 "arith_operand" "")
2141 (match_operand:SI 2 "arith_reg_operand" "")))]
2144 if (CONST_INT_P (operands[1]))
2146 emit_insn (gen_negsi2 (operands[0], operands[2]));
2147 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2152 ;; -------------------------------------------------------------------------
2153 ;; Division instructions
2154 ;; -------------------------------------------------------------------------
2156 ;; We take advantage of the library routines which don't clobber as many
2157 ;; registers as a normal function call would.
2159 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2160 ;; also has an effect on the register that holds the address of the sfunc.
2161 ;; To make this work, we have an extra dummy insn that shows the use
2162 ;; of this register for reorg.
2164 (define_insn "use_sfunc_addr"
2165 [(set (reg:SI PR_REG)
2166 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2167 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2169 [(set_attr "length" "0")])
2171 (define_insn "udivsi3_sh2a"
2172 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2173 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2174 (match_operand:SI 2 "arith_reg_operand" "z")))]
2177 [(set_attr "type" "arith")
2178 (set_attr "in_delay_slot" "no")])
2180 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2181 ;; hard register 0. If we used hard register 0, then the next instruction
2182 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2183 ;; gets allocated to a stack slot that needs its address reloaded, then
2184 ;; there is nothing to prevent reload from using r0 to reload the address.
2185 ;; This reload would clobber the value in r0 we are trying to store.
2186 ;; If we let reload allocate r0, then this problem can never happen.
2187 (define_insn "udivsi3_i1"
2188 [(set (match_operand:SI 0 "register_operand" "=z,z")
2189 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2190 (clobber (reg:SI T_REG))
2191 (clobber (reg:SI PR_REG))
2192 (clobber (reg:SI R1_REG))
2193 (clobber (reg:SI R4_REG))
2194 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2195 (use (match_operand 2 "" "Z,Ccl"))]
2196 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2200 [(set_attr "type" "sfunc")
2201 (set_attr "needs_delay_slot" "yes")])
2203 (define_insn "udivsi3_i4"
2204 [(set (match_operand:SI 0 "register_operand" "=y,y")
2205 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2206 (clobber (reg:SI T_REG))
2207 (clobber (reg:SI PR_REG))
2208 (clobber (reg:DF DR0_REG))
2209 (clobber (reg:DF DR2_REG))
2210 (clobber (reg:DF DR4_REG))
2211 (clobber (reg:SI R0_REG))
2212 (clobber (reg:SI R1_REG))
2213 (clobber (reg:SI R4_REG))
2214 (clobber (reg:SI R5_REG))
2215 (clobber (reg:SI FPSCR_STAT_REG))
2216 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2217 (use (match_operand 2 "" "Z,Ccl"))
2218 (use (reg:SI FPSCR_MODES_REG))]
2219 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2223 [(set_attr "type" "sfunc")
2224 (set_attr "fp_mode" "double")
2225 (set_attr "needs_delay_slot" "yes")])
2227 (define_insn "udivsi3_i4_single"
2228 [(set (match_operand:SI 0 "register_operand" "=y,y")
2229 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2230 (clobber (reg:SI T_REG))
2231 (clobber (reg:SI PR_REG))
2232 (clobber (reg:DF DR0_REG))
2233 (clobber (reg:DF DR2_REG))
2234 (clobber (reg:DF DR4_REG))
2235 (clobber (reg:SI R0_REG))
2236 (clobber (reg:SI R1_REG))
2237 (clobber (reg:SI R4_REG))
2238 (clobber (reg:SI R5_REG))
2239 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2240 (use (match_operand 2 "" "Z,Ccl"))]
2241 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2245 [(set_attr "type" "sfunc")
2246 (set_attr "needs_delay_slot" "yes")])
2248 (define_insn "udivsi3_i4_int"
2249 [(set (match_operand:SI 0 "register_operand" "=z")
2250 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2251 (clobber (reg:SI T_REG))
2252 (clobber (reg:SI R1_REG))
2253 (clobber (reg:SI PR_REG))
2254 (clobber (reg:SI MACH_REG))
2255 (clobber (reg:SI MACL_REG))
2256 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2259 [(set_attr "type" "sfunc")
2260 (set_attr "needs_delay_slot" "yes")])
2263 (define_expand "udivsi3"
2264 [(set (match_operand:SI 0 "register_operand")
2265 (udiv:SI (match_operand:SI 1 "general_operand")
2266 (match_operand:SI 2 "general_operand")))]
2271 operands[3] = gen_reg_rtx (Pmode);
2272 /* Emit the move of the address to a pseudo outside of the libcall. */
2273 if (TARGET_DIVIDE_CALL_TABLE)
2275 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2276 that causes problems when the divide code is supposed to come from a
2277 separate library. Division by zero is undefined, so dividing 1 can be
2278 implemented by comparing with the divisor. */
2279 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2281 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2282 emit_insn (gen_cstoresi4 (operands[0], test,
2283 operands[1], operands[2]));
2286 else if (operands[2] == const0_rtx)
2288 emit_move_insn (operands[0], operands[2]);
2291 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2292 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2294 else if (TARGET_DIVIDE_CALL_FP)
2296 rtx lab = function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC).lab;
2297 if (TARGET_FPU_SINGLE)
2298 last = gen_udivsi3_i4_single (operands[0], operands[3], lab);
2300 last = gen_udivsi3_i4 (operands[0], operands[3], lab);
2302 else if (TARGET_SH2A)
2304 operands[1] = force_reg (SImode, operands[1]);
2305 operands[2] = force_reg (SImode, operands[2]);
2306 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2311 rtx lab = function_symbol (operands[3], "__udivsi3", SFUNC_STATIC).lab;
2312 last = gen_udivsi3_i1 (operands[0], operands[3], lab);
2314 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2315 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2320 (define_insn "divsi3_sh2a"
2321 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2322 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2323 (match_operand:SI 2 "arith_reg_operand" "z")))]
2326 [(set_attr "type" "arith")
2327 (set_attr "in_delay_slot" "no")])
2329 (define_insn "divsi3_i1"
2330 [(set (match_operand:SI 0 "register_operand" "=z")
2331 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2332 (clobber (reg:SI T_REG))
2333 (clobber (reg:SI PR_REG))
2334 (clobber (reg:SI R1_REG))
2335 (clobber (reg:SI R2_REG))
2336 (clobber (reg:SI R3_REG))
2337 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2338 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2340 [(set_attr "type" "sfunc")
2341 (set_attr "needs_delay_slot" "yes")])
2343 (define_insn "divsi3_i4"
2344 [(set (match_operand:SI 0 "register_operand" "=y,y")
2345 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2346 (clobber (reg:SI PR_REG))
2347 (clobber (reg:DF DR0_REG))
2348 (clobber (reg:DF DR2_REG))
2349 (clobber (reg:SI FPSCR_STAT_REG))
2350 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2351 (use (match_operand 2 "" "Z,Ccl"))
2352 (use (reg:SI FPSCR_MODES_REG))]
2353 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2357 [(set_attr "type" "sfunc")
2358 (set_attr "fp_mode" "double")
2359 (set_attr "needs_delay_slot" "yes")])
2361 (define_insn "divsi3_i4_single"
2362 [(set (match_operand:SI 0 "register_operand" "=y,y")
2363 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2364 (clobber (reg:SI PR_REG))
2365 (clobber (reg:DF DR0_REG))
2366 (clobber (reg:DF DR2_REG))
2367 (clobber (reg:SI R2_REG))
2368 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2369 (use (match_operand 2 "" "Z,Ccl"))]
2370 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2374 [(set_attr "type" "sfunc")
2375 (set_attr "needs_delay_slot" "yes")])
2377 (define_insn "divsi3_i4_int"
2378 [(set (match_operand:SI 0 "register_operand" "=z")
2379 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2380 (clobber (reg:SI T_REG))
2381 (clobber (reg:SI PR_REG))
2382 (clobber (reg:SI R1_REG))
2383 (clobber (reg:SI MACH_REG))
2384 (clobber (reg:SI MACL_REG))
2385 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2388 [(set_attr "type" "sfunc")
2389 (set_attr "needs_delay_slot" "yes")])
2391 (define_expand "divsi3"
2392 [(set (match_operand:SI 0 "register_operand")
2393 (div:SI (match_operand:SI 1 "general_operand")
2394 (match_operand:SI 2 "general_operand")))]
2399 operands[3] = gen_reg_rtx (Pmode);
2400 /* Emit the move of the address to a pseudo outside of the libcall. */
2401 if (TARGET_DIVIDE_CALL_TABLE)
2403 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2404 last = gen_divsi3_i4_int (operands[0], operands[3]);
2406 else if (TARGET_DIVIDE_CALL_FP)
2408 rtx lab = function_symbol (operands[3], sh_divsi3_libfunc,
2410 if (TARGET_FPU_SINGLE)
2411 last = gen_divsi3_i4_single (operands[0], operands[3], lab);
2413 last = gen_divsi3_i4 (operands[0], operands[3], lab);
2415 else if (TARGET_SH2A)
2417 operands[1] = force_reg (SImode, operands[1]);
2418 operands[2] = force_reg (SImode, operands[2]);
2419 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2424 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2425 last = gen_divsi3_i1 (operands[0], operands[3]);
2427 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2428 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2434 ;; -------------------------------------------------------------------------
2435 ;; Multiplication instructions
2436 ;; -------------------------------------------------------------------------
2438 (define_insn_and_split "mulhisi3"
2439 [(set (match_operand:SI 0 "arith_reg_dest")
2440 (mult:SI (sign_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2441 (sign_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2442 (clobber (reg:SI MACL_REG))]
2443 "TARGET_SH1 && can_create_pseudo_p ()"
2446 [(set (reg:SI MACL_REG) (mult:SI (sign_extend:SI (match_dup 1))
2447 (sign_extend:SI (match_dup 2))))
2448 (set (match_dup 0) (reg:SI MACL_REG))])
2450 (define_insn_and_split "umulhisi3"
2451 [(set (match_operand:SI 0 "arith_reg_dest")
2452 (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2453 (zero_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2454 (clobber (reg:SI MACL_REG))]
2455 "TARGET_SH1 && can_create_pseudo_p ()"
2458 [(set (reg:SI MACL_REG) (mult:SI (zero_extend:SI (match_dup 1))
2459 (zero_extend:SI (match_dup 2))))
2460 (set (match_dup 0) (reg:SI MACL_REG))])
2462 (define_insn "umulhisi3_i"
2463 [(set (reg:SI MACL_REG)
2464 (mult:SI (zero_extend:SI
2465 (match_operand:HI 0 "arith_reg_operand" "r"))
2467 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2470 [(set_attr "type" "smpy")])
2472 (define_insn "mulhisi3_i"
2473 [(set (reg:SI MACL_REG)
2474 (mult:SI (sign_extend:SI
2475 (match_operand:HI 0 "arith_reg_operand" "r"))
2477 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2480 [(set_attr "type" "smpy")])
2483 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
2484 ;; a call to a routine which clobbers known registers.
2485 (define_insn "mulsi3_call"
2486 [(set (match_operand:SI 1 "register_operand" "=z")
2487 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2488 (clobber (reg:SI MACL_REG))
2489 (clobber (reg:SI T_REG))
2490 (clobber (reg:SI PR_REG))
2491 (clobber (reg:SI R3_REG))
2492 (clobber (reg:SI R2_REG))
2493 (clobber (reg:SI R1_REG))
2494 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
2497 [(set_attr "type" "sfunc")
2498 (set_attr "needs_delay_slot" "yes")])
2500 (define_insn "mul_r"
2501 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2502 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
2503 (match_operand:SI 2 "arith_reg_operand" "z")))]
2506 [(set_attr "type" "dmpy")])
2508 (define_insn "mul_l"
2509 [(set (reg:SI MACL_REG)
2510 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
2511 (match_operand:SI 1 "arith_reg_operand" "r")))]
2514 [(set_attr "type" "dmpy")])
2516 (define_insn_and_split "mulsi3_i"
2517 [(set (match_operand:SI 0 "arith_reg_dest")
2518 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2519 (match_operand:SI 2 "arith_reg_operand")))
2520 (clobber (reg:SI MACL_REG))]
2521 "TARGET_SH2 && can_create_pseudo_p ()"
2524 [(set (reg:SI MACL_REG) (mult:SI (match_dup 1) (match_dup 2)))
2525 (set (match_dup 0) (reg:SI MACL_REG))])
2527 (define_expand "mulsi3"
2528 [(set (match_operand:SI 0 "arith_reg_dest")
2529 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2530 (match_operand:SI 2 "arith_reg_operand")))]
2535 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2536 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2538 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym;
2540 emit_insn (gen_mulsi3_call (force_reg (SImode, sym), operands[0]));
2544 /* FIXME: For some reason, expanding the mul_l insn and the macl store
2545 insn early gives slightly better code. In particular it prevents
2546 the decrement-test loop type to be used in some cases which saves
2547 one multiplication in the loop setup code.
2549 emit_insn (gen_mulsi3_i (operands[0], operands[1], operands[2]));
2552 emit_insn (gen_mul_l (operands[1], operands[2]));
2553 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
2558 (define_insn "mulsidi3_i"
2559 [(set (reg:SI MACH_REG)
2563 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2564 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2566 (set (reg:SI MACL_REG)
2567 (mult:SI (match_dup 0)
2571 [(set_attr "type" "dmpy")])
2573 (define_expand "mulsidi3"
2574 [(set (match_operand:DI 0 "arith_reg_dest")
2575 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2576 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2579 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
2583 (define_insn_and_split "mulsidi3_compact"
2584 [(set (match_operand:DI 0 "arith_reg_dest")
2585 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2586 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2587 (clobber (reg:SI MACH_REG))
2588 (clobber (reg:SI MACL_REG))]
2589 "TARGET_SH2 && can_create_pseudo_p ()"
2594 rtx low_dst = gen_lowpart (SImode, operands[0]);
2595 rtx high_dst = gen_highpart (SImode, operands[0]);
2597 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
2599 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2600 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2601 /* We need something to tag the possible REG_EQUAL notes on to. */
2602 emit_move_insn (operands[0], operands[0]);
2606 (define_insn "umulsidi3_i"
2607 [(set (reg:SI MACH_REG)
2611 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2612 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2614 (set (reg:SI MACL_REG)
2615 (mult:SI (match_dup 0)
2619 [(set_attr "type" "dmpy")])
2621 (define_expand "umulsidi3"
2622 [(set (match_operand:DI 0 "arith_reg_dest")
2623 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2624 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2627 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
2631 (define_insn_and_split "umulsidi3_compact"
2632 [(set (match_operand:DI 0 "arith_reg_dest")
2633 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2634 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2635 (clobber (reg:SI MACH_REG))
2636 (clobber (reg:SI MACL_REG))]
2637 "TARGET_SH2 && can_create_pseudo_p ()"
2642 rtx low_dst = gen_lowpart (SImode, operands[0]);
2643 rtx high_dst = gen_highpart (SImode, operands[0]);
2645 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
2647 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2648 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2649 /* We need something to tag the possible REG_EQUAL notes on to. */
2650 emit_move_insn (operands[0], operands[0]);
2654 (define_insn "smulsi3_highpart_i"
2655 [(set (reg:SI MACH_REG)
2659 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2660 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2662 (clobber (reg:SI MACL_REG))]
2665 [(set_attr "type" "dmpy")])
2667 (define_insn_and_split "smulsi3_highpart"
2668 [(set (match_operand:SI 0 "arith_reg_dest")
2672 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2673 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2675 (clobber (reg:SI MACL_REG))
2676 (clobber (reg:SI MACH_REG))]
2677 "TARGET_SH2 && can_create_pseudo_p ()"
2682 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
2683 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2686 (define_insn "umulsi3_highpart_i"
2687 [(set (reg:SI MACH_REG)
2691 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2692 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2694 (clobber (reg:SI MACL_REG))]
2697 [(set_attr "type" "dmpy")])
2699 (define_insn_and_split "umulsi3_highpart"
2700 [(set (match_operand:SI 0 "arith_reg_dest")
2704 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2705 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2707 (clobber (reg:SI MACL_REG))]
2708 "TARGET_SH2 && can_create_pseudo_p ()"
2713 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
2714 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2717 ;; -------------------------------------------------------------------------
2718 ;; Logical operations
2719 ;; -------------------------------------------------------------------------
2721 (define_expand "andsi3"
2722 [(set (match_operand:SI 0 "arith_reg_dest")
2723 (and:SI (match_operand:SI 1 "arith_reg_operand")
2724 (match_operand:SI 2 "logical_and_operand")))]
2727 /* If it is possible to turn the and insn into a zero extension
2728 already, redundant zero extensions will be folded, which results
2730 Ideally the splitter of *andsi_compact would be enough, if redundant
2731 zero extensions were detected after the combine pass, which does not
2732 happen at the moment. */
2734 if (satisfies_constraint_Jmb (operands[2]))
2736 emit_insn (gen_zero_extendqisi2 (operands[0],
2737 gen_lowpart (QImode, operands[1])));
2740 else if (satisfies_constraint_Jmw (operands[2]))
2742 emit_insn (gen_zero_extendhisi2 (operands[0],
2743 gen_lowpart (HImode, operands[1])));
2748 (define_insn_and_split "*andsi_compact"
2749 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
2750 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
2751 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
2759 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
2761 if (satisfies_constraint_Jmb (operands[2]))
2762 operands[1] = gen_lowpart (QImode, operands[1]);
2763 else if (satisfies_constraint_Jmw (operands[2]))
2764 operands[1] = gen_lowpart (HImode, operands[1]);
2768 [(set_attr "type" "arith")])
2770 (define_insn "*andsi3_bclr"
2771 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2772 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2773 (match_operand:SI 2 "const_int_operand" "Psz")))]
2774 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
2776 [(set_attr "type" "arith")])
2778 (define_expand "iorsi3"
2779 [(set (match_operand:SI 0 "arith_reg_dest")
2780 (ior:SI (match_operand:SI 1 "arith_reg_operand")
2781 (match_operand:SI 2 "logical_operand")))])
2783 (define_insn "*iorsi3_compact"
2784 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
2785 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2786 (match_operand:SI 2 "logical_operand" "r,K08")))]
2788 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
2790 [(set_attr "type" "arith")])
2792 (define_insn "*iorsi3_bset"
2793 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2794 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2795 (match_operand:SI 2 "const_int_operand" "Pso")))]
2796 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
2798 [(set_attr "type" "arith")])
2800 (define_insn "xorsi3"
2801 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
2802 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2803 (match_operand:SI 2 "logical_operand" "K08,r")))]
2806 [(set_attr "type" "arith")])
2808 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
2809 ;; of results where one of the inputs is a T bit store. Notice that this
2810 ;; pattern must not match during reload. If reload picks this pattern it
2811 ;; will be impossible to split it afterwards.
2812 (define_insn_and_split "*logical_op_t"
2813 [(set (match_operand:SI 0 "arith_reg_dest")
2814 (match_operator:SI 3 "logical_operator"
2815 [(match_operand:SI 1 "arith_reg_operand")
2816 (match_operand:SI 2 "t_reg_operand")]))]
2817 "TARGET_SH1 && can_create_pseudo_p ()"
2820 [(set (match_dup 4) (reg:SI T_REG))
2821 (set (match_dup 0) (match_dup 3))]
2823 operands[4] = gen_reg_rtx (SImode);
2824 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2825 operands[1], operands[4]);
2828 ;; -------------------------------------------------------------------------
2829 ;; Shifts and rotates
2830 ;; -------------------------------------------------------------------------
2832 ;; Let combine see that we can get the MSB and LSB into the T bit
2833 ;; via shll and shlr. This allows it to plug it into insns that can have
2834 ;; the T bit as an input (e.g. addc).
2835 ;; On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
2836 (define_insn_and_split "*reg_lsb_t"
2837 [(set (reg:SI T_REG)
2838 (and:SI (match_operand:SI 0 "arith_reg_operand")
2840 "TARGET_SH1 && can_create_pseudo_p ()"
2845 emit_insn (TARGET_SH2A ? gen_bldsi_reg (operands[0], const0_rtx)
2846 : gen_shlr (gen_reg_rtx (SImode), operands[0]));
2849 (define_insn_and_split "*reg_msb_t"
2850 [(set (reg:SI T_REG)
2851 (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
2853 "TARGET_SH1 && can_create_pseudo_p ()"
2858 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
2861 (define_expand "rotrsi3"
2862 [(set (match_operand:SI 0 "arith_reg_dest")
2863 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
2864 (match_operand:SI 2 "const_int_operand")))]
2867 HOST_WIDE_INT ival = INTVAL (operands[2]);
2870 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
2877 (define_insn "rotrsi3_1"
2878 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2879 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2882 (and:SI (match_dup 1) (const_int 1)))]
2885 [(set_attr "type" "arith")])
2887 ;; A slimplified version of rotr for combine.
2888 (define_insn "*rotrsi3_1"
2889 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2890 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2892 (clobber (reg:SI T_REG))]
2895 [(set_attr "type" "arith")])
2897 (define_insn "rotlsi3_1"
2898 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2899 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2902 (lshiftrt:SI (match_dup 1) (const_int 31)))]
2905 [(set_attr "type" "arith")])
2907 ;; A simplified version of rotl for combine.
2908 (define_insn "*rotlsi3_1"
2909 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2910 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2912 (clobber (reg:SI T_REG))]
2915 [(set_attr "type" "arith")])
2917 (define_insn "rotlsi3_31"
2918 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2919 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2921 (clobber (reg:SI T_REG))]
2924 [(set_attr "type" "arith")])
2926 (define_insn "rotlsi3_16"
2927 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2928 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
2932 [(set_attr "type" "arith")])
2934 (define_expand "rotlsi3"
2935 [(set (match_operand:SI 0 "arith_reg_dest")
2936 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
2937 (match_operand:SI 2 "const_int_operand")))]
2940 static const char rot_tab[] = {
2941 000, 000, 000, 000, 000, 000, 010, 001,
2942 001, 001, 011, 013, 003, 003, 003, 003,
2943 003, 003, 003, 003, 003, 013, 012, 002,
2944 002, 002, 010, 000, 000, 000, 000, 000,
2947 int count = INTVAL (operands[2]);
2948 int choice = rot_tab[count];
2949 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
2955 emit_move_insn (operands[0], operands[1]);
2956 count -= (count & 16) * 2;
2959 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
2966 parts[0] = gen_reg_rtx (SImode);
2967 parts[1] = gen_reg_rtx (SImode);
2968 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
2969 emit_move_insn (parts[choice-1], operands[1]);
2970 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
2971 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
2972 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
2973 count = (count & ~16) - 8;
2977 for (; count > 0; count--)
2978 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2979 for (; count < 0; count++)
2980 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2985 (define_insn "rotlhi3_8"
2986 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
2987 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
2991 [(set_attr "type" "arith")])
2993 (define_expand "rotlhi3"
2994 [(set (match_operand:HI 0 "arith_reg_operand")
2995 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
2996 (match_operand:HI 2 "const_int_operand")))]
2999 if (INTVAL (operands[2]) != 8)
3003 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
3004 ;; They can also be used to implement things like
3006 ;; int x0 = (y >> 1) | (t << 31); // rotcr
3007 ;; int x1 = (y << 1) | t; // rotcl
3008 (define_insn "rotcr"
3009 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3010 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3012 (ashift:SI (match_operand:SI 2 "t_reg_operand")
3015 (and:SI (match_dup 1) (const_int 1)))]
3018 [(set_attr "type" "arith")])
3020 (define_insn "rotcl"
3021 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3022 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3024 (match_operand:SI 2 "t_reg_operand")))
3026 (lshiftrt:SI (match_dup 1) (const_int 31)))]
3029 [(set_attr "type" "arith")])
3031 ;; Simplified rotcr version for combine, which allows arbitrary shift
3032 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
3033 ;; directly. Otherwise we have to insert a shift in between.
3034 (define_insn_and_split "*rotcr"
3035 [(set (match_operand:SI 0 "arith_reg_dest")
3036 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_or_0_operand")
3037 (match_operand:SI 2 "const_int_operand"))
3038 (ashift:SI (match_operand 3 "arith_reg_or_treg_set_expr")
3040 (clobber (reg:SI T_REG))]
3041 "TARGET_SH1 && can_create_pseudo_p ()"
3046 rtx prev_set_t_insn = NULL_RTX;
3048 if (!arith_reg_operand (operands[3], SImode))
3050 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
3051 if (!ti.was_treg_operand ())
3052 prev_set_t_insn = ti.first_insn ();
3054 operands[3] = get_t_reg_rtx ();
3056 if (TARGET_SH2A && ti.has_trailing_nott () && operands[1] == const0_rtx)
3058 /* Convert to a movrt, rotr sequence. */
3059 remove_insn (ti.trailing_nott ());
3060 rtx tmp = gen_reg_rtx (SImode);
3061 emit_insn (gen_movnegt (tmp, get_t_reg_rtx ()));
3062 emit_insn (gen_rotrsi3_1 (operands[0], tmp));
3067 if (operands[1] == const0_rtx)
3069 operands[1] = gen_reg_rtx (SImode);
3070 emit_insn (gen_movt (operands[1], get_t_reg_rtx ()));
3073 if (INTVAL (operands[2]) > 1)
3075 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3076 rtx tmp_t_reg = NULL_RTX;
3078 /* If we're going to emit a shift sequence that clobbers the T_REG,
3079 try to find the previous insn that sets the T_REG and emit the
3080 shift insn before that insn, to remove the T_REG dependency.
3081 If the insn that sets the T_REG cannot be found, store the T_REG
3082 in a temporary reg and restore it after the shift. */
3083 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
3084 && ! sh_dynamicalize_shift_p (shift_count))
3086 if (prev_set_t_insn == NULL)
3087 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
3089 /* Skip the nott insn, which was probably inserted by the splitter
3090 of *rotcr_neg_t. Don't use one of the recog functions
3091 here during insn splitting, since that causes problems in later
3093 if (prev_set_t_insn != NULL_RTX)
3095 rtx pat = PATTERN (prev_set_t_insn);
3096 if (GET_CODE (pat) == SET
3097 && t_reg_operand (XEXP (pat, 0), SImode)
3098 && negt_reg_operand (XEXP (pat, 1), SImode))
3099 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
3102 if (! (prev_set_t_insn != NULL_RTX
3103 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3104 && ! reg_referenced_p (get_t_reg_rtx (),
3105 PATTERN (prev_set_t_insn))))
3107 prev_set_t_insn = NULL_RTX;
3108 tmp_t_reg = gen_reg_rtx (SImode);
3109 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3113 rtx shift_result = gen_reg_rtx (SImode);
3114 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
3115 operands[1] = shift_result;
3117 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3118 if (prev_set_t_insn != NULL_RTX)
3119 emit_insn_before (shift_insn, prev_set_t_insn);
3121 emit_insn (shift_insn);
3123 /* Restore T_REG if it has been saved before. */
3124 if (tmp_t_reg != NULL_RTX)
3125 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3128 /* For the rotcr insn to work, operands[3] must be in T_REG.
3129 If it is not we can get it there by shifting it right one bit.
3130 In this case T_REG is not an input for this insn, thus we don't have to
3131 pay attention as of where to insert the shlr insn. */
3132 if (! t_reg_operand (operands[3], SImode))
3134 /* We don't care about the shifted result here, only the T_REG. */
3135 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3136 operands[3] = get_t_reg_rtx ();
3139 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
3143 ;; If combine tries the same as above but with swapped operands, split
3144 ;; it so that it will try the pattern above.
3146 [(set (match_operand:SI 0 "arith_reg_dest")
3147 (ior:SI (ashift:SI (match_operand 1 "arith_reg_or_treg_set_expr")
3149 (lshiftrt:SI (match_operand:SI 2 "arith_reg_or_0_operand")
3150 (match_operand:SI 3 "const_int_operand"))))]
3151 "TARGET_SH1 && can_create_pseudo_p ()"
3152 [(parallel [(set (match_dup 0)
3153 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3154 (ashift:SI (match_dup 1) (const_int 31))))
3155 (clobber (reg:SI T_REG))])])
3157 ;; Basically the same as the rotcr pattern above, but for rotcl.
3158 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
3159 (define_insn_and_split "*rotcl"
3160 [(set (match_operand:SI 0 "arith_reg_dest")
3161 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3162 (match_operand:SI 2 "const_int_operand"))
3163 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
3165 (clobber (reg:SI T_REG))]
3168 "&& can_create_pseudo_p ()"
3171 gcc_assert (INTVAL (operands[2]) > 0);
3173 if (INTVAL (operands[2]) > 1)
3175 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3176 rtx prev_set_t_insn = NULL_RTX;
3177 rtx tmp_t_reg = NULL_RTX;
3179 /* If we're going to emit a shift sequence that clobbers the T_REG,
3180 try to find the previous insn that sets the T_REG and emit the
3181 shift insn before that insn, to remove the T_REG dependency.
3182 If the insn that sets the T_REG cannot be found, store the T_REG
3183 in a temporary reg and restore it after the shift. */
3184 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
3185 && ! sh_dynamicalize_shift_p (shift_count))
3187 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
3189 /* Skip the nott insn, which was probably inserted by the splitter
3190 of *rotcl_neg_t. Don't use one of the recog functions
3191 here during insn splitting, since that causes problems in later
3193 if (prev_set_t_insn != NULL_RTX)
3195 rtx pat = PATTERN (prev_set_t_insn);
3196 if (GET_CODE (pat) == SET
3197 && t_reg_operand (XEXP (pat, 0), SImode)
3198 && negt_reg_operand (XEXP (pat, 1), SImode))
3199 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
3202 if (! (prev_set_t_insn != NULL_RTX
3203 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3204 && ! reg_referenced_p (get_t_reg_rtx (),
3205 PATTERN (prev_set_t_insn))))
3207 prev_set_t_insn = NULL_RTX;
3208 tmp_t_reg = gen_reg_rtx (SImode);
3209 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3213 rtx shift_result = gen_reg_rtx (SImode);
3214 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
3215 operands[1] = shift_result;
3217 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3218 if (prev_set_t_insn != NULL_RTX)
3219 emit_insn_before (shift_insn, prev_set_t_insn);
3221 emit_insn (shift_insn);
3223 /* Restore T_REG if it has been saved before. */
3224 if (tmp_t_reg != NULL_RTX)
3225 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3228 /* For the rotcl insn to work, operands[3] must be in T_REG.
3229 If it is not we can get it there by shifting it right one bit.
3230 In this case T_REG is not an input for this insn, thus we don't have to
3231 pay attention as of where to insert the shlr insn. */
3232 if (! t_reg_operand (operands[3], SImode))
3234 /* We don't care about the shifted result here, only the T_REG. */
3235 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3236 operands[3] = get_t_reg_rtx ();
3239 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
3243 ;; rotcl combine pattern variations
3244 (define_insn_and_split "*rotcl"
3245 [(set (match_operand:SI 0 "arith_reg_dest")
3246 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3247 (match_operand:SI 2 "const_int_operand"))
3248 (match_operand 3 "treg_set_expr")))
3249 (clobber (reg:SI T_REG))]
3252 "&& can_create_pseudo_p ()"
3253 [(parallel [(set (match_dup 0)
3254 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3255 (and:SI (match_dup 3) (const_int 1))))
3256 (clobber (reg:SI T_REG))])]
3258 sh_split_treg_set_expr (operands[3], curr_insn);
3259 operands[3] = get_t_reg_rtx ();
3262 (define_insn_and_split "*rotcl"
3263 [(set (match_operand:SI 0 "arith_reg_dest")
3264 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
3266 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3267 (match_operand:SI 3 "const_int_operand"))))
3268 (clobber (reg:SI T_REG))]
3271 "&& can_create_pseudo_p ()"
3272 [(parallel [(set (match_dup 0)
3273 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3274 (and:SI (match_dup 1) (const_int 1))))
3275 (clobber (reg:SI T_REG))])])
3277 (define_insn_and_split "*rotcl"
3278 [(set (match_operand:SI 0 "arith_reg_dest")
3279 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3280 (match_operand:SI 2 "const_int_operand"))
3281 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3283 (clobber (reg:SI T_REG))]
3286 "&& can_create_pseudo_p ()"
3287 [(parallel [(set (match_dup 0)
3288 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3289 (and:SI (reg:SI T_REG) (const_int 1))))
3290 (clobber (reg:SI T_REG))])]
3292 /* We don't care about the result of the left shift, only the T_REG. */
3293 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3296 (define_insn_and_split "*rotcl"
3297 [(set (match_operand:SI 0 "arith_reg_dest")
3298 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3300 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3301 (match_operand:SI 2 "const_int_operand"))))
3302 (clobber (reg:SI T_REG))]
3305 "&& can_create_pseudo_p ()"
3306 [(parallel [(set (match_dup 0)
3307 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3308 (and:SI (reg:SI T_REG) (const_int 1))))
3309 (clobber (reg:SI T_REG))])]
3311 /* We don't care about the result of the left shift, only the T_REG. */
3312 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3315 (define_insn_and_split "*rotcl"
3316 [(set (match_operand:SI 0 "arith_reg_dest")
3317 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3318 (match_operand 2 "const_int_operand"))
3319 (zero_extract:SI (match_operand:SI 3 "arith_reg_operand")
3321 (match_operand 4 "const_int_operand"))))
3322 (clobber (reg:SI T_REG))]
3325 "&& can_create_pseudo_p ()"
3326 [(parallel [(set (match_dup 0)
3327 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3328 (and:SI (match_dup 5) (const_int 1))))
3329 (clobber (reg:SI T_REG))])]
3331 if (TARGET_SH2A && satisfies_constraint_K03 (operands[4]))
3333 /* On SH2A we can use the bld insn to zero extract a single bit
3335 operands[5] = get_t_reg_rtx ();
3336 emit_insn (gen_bldsi_reg (operands[3], operands[4]));
3340 /* If we can't use the bld insn we have to emit a tst + nott sequence
3341 to get the extracted bit into the T bit.
3342 This will probably be worse than pre-shifting the operand. */
3343 operands[5] = gen_reg_rtx (SImode);
3344 emit_insn (gen_lshrsi3 (operands[5], operands[3], operands[4]));
3348 ;; rotcr combine bridge pattern which will make combine try out more
3349 ;; complex patterns.
3350 (define_insn_and_split "*rotcr"
3351 [(set (match_operand:SI 0 "arith_reg_dest")
3352 (ashift:SI (match_operand 1 "treg_set_expr") (const_int 31)))]
3353 "TARGET_SH1 && can_create_pseudo_p ()"
3356 [(parallel [(set (match_dup 0)
3357 (ior:SI (lshiftrt:SI (const_int 0) (const_int 1))
3358 (ashift:SI (match_dup 1) (const_int 31))))
3359 (clobber (reg:SI T_REG))])])
3361 (define_insn_and_split "*rotcr"
3362 [(set (match_operand:SI 0 "arith_reg_dest")
3363 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
3364 (const_int -2147483648)) ;; 0xffffffff80000000
3365 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3367 (clobber (reg:SI T_REG))]
3370 "&& can_create_pseudo_p ()"
3373 rtx tmp = gen_reg_rtx (SImode);
3374 emit_insn (gen_shll (tmp, operands[1]));
3375 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
3379 (define_insn_and_split "*rotcr"
3380 [(set (match_operand:SI 0 "arith_reg_dest")
3381 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3383 (const_int -2147483648))) ;; 0xffffffff80000000
3384 (clobber (reg:SI T_REG))]
3387 "&& can_create_pseudo_p ()"
3390 emit_insn (gen_sett ());
3391 emit_insn (gen_rotcr (operands[0], operands[1], get_t_reg_rtx ()));
3395 ;; rotcr combine patterns for rotating in the negated T_REG value.
3396 (define_insn_and_split "*rotcr_neg_t"
3397 [(set (match_operand:SI 0 "arith_reg_dest")
3398 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
3399 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3400 (match_operand:SI 3 "const_int_operand"))))
3401 (clobber (reg:SI T_REG))]
3404 "&& can_create_pseudo_p ()"
3405 [(parallel [(set (match_dup 0)
3406 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3407 (ashift:SI (reg:SI T_REG) (const_int 31))))
3408 (clobber (reg:SI T_REG))])]
3410 emit_insn (gen_nott (get_t_reg_rtx ()));
3413 (define_insn_and_split "*rotcr_neg_t"
3414 [(set (match_operand:SI 0 "arith_reg_dest")
3415 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3416 (match_operand:SI 2 "const_int_operand"))
3417 (match_operand:SI 3 "negt_reg_shl31_operand")))
3418 (clobber (reg:SI T_REG))]
3421 "&& can_create_pseudo_p ()"
3422 [(parallel [(set (match_dup 0)
3423 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3424 (ashift:SI (reg:SI T_REG) (const_int 31))))
3425 (clobber (reg:SI T_REG))])]
3427 emit_insn (gen_nott (get_t_reg_rtx ()));
3430 ;; rotcl combine patterns for rotating in the negated T_REG value.
3431 ;; For some strange reason these have to be specified as splits which combine
3432 ;; will pick up. If they are specified as insn_and_split like the
3433 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
3434 ;; but not emit them on non-SH2A targets.
3436 [(set (match_operand:SI 0 "arith_reg_dest")
3437 (ior:SI (match_operand:SI 1 "negt_reg_operand")
3438 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3439 (match_operand:SI 3 "const_int_operand"))))]
3441 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3442 (parallel [(set (match_dup 0)
3443 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3444 (and:SI (reg:SI T_REG) (const_int 1))))
3445 (clobber (reg:SI T_REG))])])
3448 [(set (match_operand:SI 0 "arith_reg_dest")
3449 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3450 (match_operand:SI 3 "const_int_operand"))
3451 (match_operand:SI 1 "negt_reg_operand")))]
3453 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3454 (parallel [(set (match_dup 0)
3455 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3456 (and:SI (reg:SI T_REG) (const_int 1))))
3457 (clobber (reg:SI T_REG))])])
3459 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3460 ;; SImode shift left
3462 (define_expand "ashlsi3"
3463 [(set (match_operand:SI 0 "arith_reg_operand" "")
3464 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
3465 (match_operand:SI 2 "shift_count_operand" "")))]
3469 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3471 /* Don't force the constant into a reg yet. Some other optimizations
3472 might not see through the reg that holds the shift count. */
3475 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
3477 if (CONST_INT_P (operands[2])
3478 && sh_ashlsi_clobbers_t_reg_p (operands[2])
3479 && ! sh_dynamicalize_shift_p (operands[2]))
3481 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
3486 /* Expand a library call for the dynamic shift. */
3487 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3489 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3490 rtx funcaddr = gen_reg_rtx (Pmode);
3491 rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab;
3492 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab));
3498 (define_insn "ashlsi3_k"
3499 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3500 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
3501 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
3506 [(set_attr "type" "arith")])
3508 (define_insn_and_split "ashlsi3_d"
3509 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3510 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3511 (match_operand:SI 2 "shift_count_operand" "r")))]
3514 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3515 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3518 if (satisfies_constraint_P27 (operands[2]))
3520 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
3523 else if (! satisfies_constraint_P27 (operands[2]))
3525 /* This must happen before reload, otherwise the constant will be moved
3526 into a register due to the "r" constraint, after which this split
3527 cannot be done anymore.
3528 Unfortunately the move insn will not always be eliminated.
3529 Also, here we must not create a shift sequence that clobbers the
3531 emit_move_insn (operands[0], operands[1]);
3532 gen_shifty_op (ASHIFT, operands);
3538 [(set_attr "type" "dyn_shift")])
3540 ;; If dynamic shifts are not available use a library function.
3541 ;; By specifying the pattern we reduce the number of call clobbered regs.
3542 ;; In order to make combine understand the truncation of the shift amount
3543 ;; operand we have to allow it to use pseudo regs for the shift operands.
3544 (define_insn "ashlsi3_d_call"
3545 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
3546 (ashift:SI (reg:SI R4_REG)
3547 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
3549 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
3550 (use (match_operand 3 "" "Z,Ccl"))
3551 (clobber (reg:SI T_REG))
3552 (clobber (reg:SI PR_REG))]
3553 "TARGET_SH1 && !TARGET_DYNSHIFT"
3557 [(set_attr "type" "sfunc")
3558 (set_attr "needs_delay_slot" "yes")])
3560 (define_insn_and_split "ashlsi3_n"
3561 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3562 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3563 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
3564 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3566 "&& (reload_completed
3567 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3570 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3572 /* If this pattern was picked and dynamic shifts are supported, switch
3573 to dynamic shift pattern before reload. */
3574 operands[2] = force_reg (SImode, operands[2]);
3575 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3578 gen_shifty_op (ASHIFT, operands);
3583 (define_insn_and_split "ashlsi3_n_clobbers_t"
3584 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3585 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3586 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
3587 (clobber (reg:SI T_REG))]
3588 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
3590 "&& (reload_completed || INTVAL (operands[2]) == 31
3591 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3594 if (INTVAL (operands[2]) == 31)
3596 /* If the shift amount is 31 we split into a different sequence before
3597 reload so that it gets a chance to allocate R0 for the sequence.
3598 If it fails to do so (due to pressure on R0), it will take one insn
3599 more for the and. */
3600 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
3601 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3603 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3605 /* If this pattern was picked and dynamic shifts are supported, switch
3606 to dynamic shift pattern before reload. */
3607 operands[2] = force_reg (SImode, operands[2]);
3608 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3611 gen_shifty_op (ASHIFT, operands);
3617 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3618 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
3620 (lt:SI (match_dup 1) (const_int 0)))]
3623 [(set_attr "type" "arith")])
3625 (define_insn "*ashlsi_c_void"
3626 [(set (reg:SI T_REG)
3627 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
3628 (clobber (match_scratch:SI 1 "=0"))]
3629 "TARGET_SH1 && cse_not_expected"
3631 [(set_attr "type" "arith")])
3634 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
3636 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
3638 && peep2_reg_dead_p (2, operands[0])
3639 && peep2_reg_dead_p (2, operands[1])"
3642 emit_insn (gen_shll (operands[1], operands[1]));
3646 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3647 ;; HImode shift left
3649 (define_expand "ashlhi3"
3650 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
3651 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
3652 (match_operand:SI 2 "nonmemory_operand" "")))
3653 (clobber (reg:SI T_REG))])]
3656 if (!CONST_INT_P (operands[2]))
3658 /* It may be possible to call gen_ashlhi3 directly with more generic
3659 operands. Make sure operands[1] is a HImode register here. */
3660 if (!arith_reg_operand (operands[1], HImode))
3661 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3664 (define_insn "ashlhi3_k"
3665 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
3666 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
3667 (match_operand:HI 2 "const_int_operand" "M,P27")))]
3668 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
3672 [(set_attr "type" "arith")])
3674 (define_insn_and_split "*ashlhi3_n"
3675 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
3676 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
3677 (match_operand:HI 2 "const_int_operand" "n")))
3678 (clobber (reg:SI T_REG))]
3681 "&& reload_completed"
3682 [(use (reg:SI R0_REG))]
3684 gen_shifty_hi_op (ASHIFT, operands);
3688 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3689 ;; DImode shift left
3691 (define_expand "ashldi3"
3692 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3693 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
3694 (match_operand:DI 2 "immediate_operand" "")))
3695 (clobber (reg:SI T_REG))])]
3698 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
3700 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
3703 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
3705 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
3712 ;; Expander for DImode shift left with SImode operations.
3713 (define_expand "ashldi3_std"
3714 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3715 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
3716 (match_operand:DI 2 "const_int_operand" "n")))]
3717 "TARGET_SH1 && INTVAL (operands[2]) < 32"
3719 rtx low_src = gen_lowpart (SImode, operands[1]);
3720 rtx high_src = gen_highpart (SImode, operands[1]);
3721 rtx dst = gen_reg_rtx (DImode);
3722 rtx low_dst = gen_lowpart (SImode, dst);
3723 rtx high_dst = gen_highpart (SImode, dst);
3724 rtx tmp0 = gen_reg_rtx (SImode);
3725 rtx tmp1 = gen_reg_rtx (SImode);
3727 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
3728 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
3729 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
3730 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
3731 emit_move_insn (operands[0], dst);
3735 (define_insn_and_split "ashldi3_k"
3736 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3737 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
3739 (clobber (reg:SI T_REG))]
3742 "&& reload_completed"
3745 rtx high = gen_highpart (SImode, operands[0]);
3746 rtx low = gen_lowpart (SImode, operands[0]);
3747 emit_insn (gen_shll (low, low));
3748 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
3752 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3753 ;; SImode arithmetic shift right
3755 ;; We can't do HImode right shifts correctly unless we start out with an
3756 ;; explicit zero / sign extension; doing that would result in worse overall
3757 ;; code, so just let the machine independent code widen the mode.
3758 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
3760 (define_expand "ashrsi3"
3761 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
3762 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3763 (match_operand:SI 2 "nonmemory_operand" "")))
3764 (clobber (reg:SI T_REG))])]
3767 if (expand_ashiftrt (operands))
3774 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3775 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3778 (and:SI (match_dup 1) (const_int 1)))]
3781 [(set_attr "type" "arith")])
3783 (define_insn "ashrsi3_k"
3784 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3785 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3786 (match_operand:SI 2 "const_int_operand" "M")))
3787 (clobber (reg:SI T_REG))]
3788 "TARGET_SH1 && INTVAL (operands[2]) == 1"
3790 [(set_attr "type" "arith")])
3792 (define_insn_and_split "ashrsi2_16"
3793 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3794 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
3799 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
3800 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
3802 operands[2] = gen_lowpart (HImode, operands[0]);
3805 (define_insn_and_split "ashrsi2_31"
3806 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3807 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3809 (clobber (reg:SI T_REG))]
3815 emit_insn (gen_shll (operands[0], operands[1]));
3816 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
3820 ;; If the shift amount is changed by combine it will try to plug the
3821 ;; use on the symbol of the library function and the PR clobber.
3822 (define_insn_and_split "*ashrsi2_31"
3823 [(set (match_operand:SI 0 "arith_reg_dest")
3824 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3826 (clobber (reg:SI T_REG))
3827 (clobber (reg:SI PR_REG))
3828 (use (match_operand:SI 2 "symbol_ref_operand"))]
3832 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))
3833 (clobber (reg:SI T_REG))])])
3835 (define_insn "ashrsi3_d"
3836 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3837 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3838 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3841 [(set_attr "type" "dyn_shift")])
3843 (define_insn "ashrsi3_n"
3844 [(set (reg:SI R4_REG)
3845 (ashiftrt:SI (reg:SI R4_REG)
3846 (match_operand:SI 0 "const_int_operand" "i,i")))
3847 (clobber (reg:SI T_REG))
3848 (clobber (reg:SI PR_REG))
3849 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
3850 (use (match_operand 2 "" "Z,Ccl"))]
3855 [(set_attr "type" "sfunc")
3856 (set_attr "needs_delay_slot" "yes")])
3858 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3859 ;; DImode arithmetic shift right
3861 (define_expand "ashrdi3"
3862 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3863 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
3864 (match_operand:DI 2 "immediate_operand" "")))
3865 (clobber (reg:SI T_REG))])]
3868 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
3872 (define_insn_and_split "ashrdi3_k"
3873 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3874 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
3876 (clobber (reg:SI T_REG))]
3879 "&& reload_completed"
3882 rtx high = gen_highpart (SImode, operands[0]);
3883 rtx low = gen_lowpart (SImode, operands[0]);
3884 emit_insn (gen_shar (high, high));
3885 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
3889 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3890 ;; SImode logical shift right
3892 (define_expand "lshrsi3"
3893 [(set (match_operand:SI 0 "arith_reg_dest" "")
3894 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3895 (match_operand:SI 2 "shift_count_operand" "")))]
3898 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
3899 here, otherwise the pattern will never match due to the shift amount reg
3902 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3904 /* Don't force the constant into a reg yet. Some other optimizations
3905 might not see through the reg that holds the shift count. */
3906 if (sh_lshrsi_clobbers_t_reg_p (operands[2]))
3907 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1], operands[2]));
3909 emit_insn (gen_lshrsi3_n (operands[0], operands[1], operands[2]));
3913 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
3915 rtx neg_count = gen_reg_rtx (SImode);
3916 emit_insn (gen_negsi2 (neg_count, operands[2]));
3917 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
3921 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
3923 if (CONST_INT_P (operands[2])
3924 && sh_lshrsi_clobbers_t_reg_p (operands[2])
3925 && ! sh_dynamicalize_shift_p (operands[2]))
3927 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
3932 /* Expand a library call for the dynamic shift. */
3933 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3935 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3936 rtx funcaddr = gen_reg_rtx (Pmode);
3937 rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab;
3938 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab));
3943 (define_insn "lshrsi3_k"
3944 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3945 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3946 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
3949 [(set_attr "type" "arith")])
3951 (define_insn_and_split "lshrsi3_d"
3952 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3953 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3954 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
3957 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3958 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
3961 /* The shift count const_int is a negative value for all dynamic
3962 right shift insns. */
3963 operands[2] = GEN_INT (- INTVAL (operands[2]));
3965 if (satisfies_constraint_P27 (operands[2]))
3967 /* This will not be done for a shift amount of 1, because it would
3968 clobber the T_REG. */
3969 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
3972 else if (! satisfies_constraint_P27 (operands[2]))
3974 /* This must happen before reload, otherwise the constant will be moved
3975 into a register due to the "r" constraint, after which this split
3976 cannot be done anymore.
3977 Unfortunately the move insn will not always be eliminated.
3978 Also, here we must not create a shift sequence that clobbers the
3980 emit_move_insn (operands[0], operands[1]);
3981 gen_shifty_op (LSHIFTRT, operands);
3987 [(set_attr "type" "dyn_shift")])
3989 ;; If dynamic shifts are not available use a library function.
3990 ;; By specifying the pattern we reduce the number of call clobbered regs.
3991 ;; In order to make combine understand the truncation of the shift amount
3992 ;; operand we have to allow it to use pseudo regs for the shift operands.
3993 (define_insn "lshrsi3_d_call"
3994 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
3995 (lshiftrt:SI (reg:SI R4_REG)
3996 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
3998 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
3999 (use (match_operand 3 "" "Z,Ccl"))
4000 (clobber (reg:SI T_REG))
4001 (clobber (reg:SI PR_REG))]
4002 "TARGET_SH1 && !TARGET_DYNSHIFT"
4006 [(set_attr "type" "sfunc")
4007 (set_attr "needs_delay_slot" "yes")])
4009 (define_insn_and_split "lshrsi3_n"
4010 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4011 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4012 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
4013 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
4015 "&& (reload_completed
4016 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4019 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4021 /* If this pattern was picked and dynamic shifts are supported, switch
4022 to dynamic shift pattern before reload. */
4023 operands[2] = GEN_INT (- INTVAL (operands[2]));
4024 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4027 gen_shifty_op (LSHIFTRT, operands);
4032 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
4033 ;; the shlr pattern.
4034 (define_insn_and_split "lshrsi3_n_clobbers_t"
4035 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4036 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4037 (match_operand:SI 2 "not_p27_rshift_count_operand")))
4038 (clobber (reg:SI T_REG))]
4039 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
4041 "&& (reload_completed || INTVAL (operands[2]) == 31
4042 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4045 if (INTVAL (operands[2]) == 31)
4047 emit_insn (gen_shll (operands[0], operands[1]));
4048 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
4050 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4052 /* If this pattern was picked and dynamic shifts are supported, switch
4053 to dynamic shift pattern before reload. */
4054 operands[2] = GEN_INT (- INTVAL (operands[2]));
4055 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4058 gen_shifty_op (LSHIFTRT, operands);
4064 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4065 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4068 (and:SI (match_dup 1) (const_int 1)))]
4071 [(set_attr "type" "arith")])
4073 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4074 ;; DImode logical shift right
4076 (define_expand "lshrdi3"
4077 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4078 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4079 (match_operand:DI 2 "immediate_operand" "")))
4080 (clobber (reg:SI T_REG))])]
4083 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
4087 (define_insn_and_split "lshrdi3_k"
4088 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4089 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4091 (clobber (reg:SI T_REG))]
4094 "&& reload_completed"
4097 rtx high = gen_highpart (SImode, operands[0]);
4098 rtx low = gen_lowpart (SImode, operands[0]);
4099 emit_insn (gen_shlr (high, high));
4100 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
4104 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4105 ;; Combined left/right shifts
4108 [(set (match_operand:SI 0 "register_operand" "")
4109 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4110 (match_operand:SI 2 "const_int_operand" ""))
4111 (match_operand:SI 3 "const_int_operand" "")))]
4112 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4113 [(use (reg:SI R0_REG))]
4115 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4121 [(set (match_operand:SI 0 "register_operand" "")
4122 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4123 (match_operand:SI 2 "const_int_operand" ""))
4124 (match_operand:SI 3 "const_int_operand" "")))
4125 (clobber (reg:SI T_REG))]
4126 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4127 [(use (reg:SI R0_REG))]
4129 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4135 [(set (match_operand:SI 0 "register_operand" "=r")
4136 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4137 (match_operand:SI 2 "const_int_operand" "n"))
4138 (match_operand:SI 3 "const_int_operand" "n")))
4139 (clobber (reg:SI T_REG))]
4140 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
4142 [(set (attr "length")
4143 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4145 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4147 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4149 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
4151 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
4153 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
4155 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
4156 (const_string "16")]
4157 (const_string "18")))
4158 (set_attr "type" "arith")])
4161 [(set (match_operand:SI 0 "register_operand" "=z")
4162 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4163 (match_operand:SI 2 "const_int_operand" "n"))
4164 (match_operand:SI 3 "const_int_operand" "n")))
4165 (clobber (reg:SI T_REG))]
4166 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
4168 [(set (attr "length")
4169 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4171 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4173 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4175 (const_string "10")))
4176 (set_attr "type" "arith")])
4178 ;; shift left / and combination with a scratch register: The combine pass
4179 ;; does not accept the individual instructions, even though they are
4180 ;; cheap. But it needs a precise description so that it is usable after
4182 (define_insn "and_shl_scratch"
4183 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4187 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
4188 (match_operand:SI 2 "const_int_operand" "N,n"))
4189 (match_operand:SI 3 "" "0,r"))
4190 (match_operand:SI 4 "const_int_operand" "n,n"))
4191 (match_operand:SI 5 "const_int_operand" "n,n")))
4192 (clobber (reg:SI T_REG))]
4195 [(set (attr "length")
4196 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
4198 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
4200 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
4202 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
4203 (const_string "10")]
4204 (const_string "12")))
4205 (set_attr "type" "arith")])
4208 [(set (match_operand:SI 0 "register_operand" "")
4212 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
4213 (match_operand:SI 2 "const_int_operand" ""))
4214 (match_operand:SI 3 "register_operand" ""))
4215 (match_operand:SI 4 "const_int_operand" ""))
4216 (match_operand:SI 5 "const_int_operand" "")))
4217 (clobber (reg:SI T_REG))]
4219 [(use (reg:SI R0_REG))]
4221 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
4223 if (INTVAL (operands[2]))
4225 gen_shifty_op (LSHIFTRT, operands);
4227 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
4228 operands[2] = operands[4];
4229 gen_shifty_op (ASHIFT, operands);
4230 if (INTVAL (operands[5]))
4232 operands[2] = operands[5];
4233 gen_shifty_op (LSHIFTRT, operands);
4238 ;; signed left/right shift combination.
4240 [(set (match_operand:SI 0 "register_operand" "")
4242 (ashift:SI (match_operand:SI 1 "register_operand" "")
4243 (match_operand:SI 2 "const_int_operand" ""))
4244 (match_operand:SI 3 "const_int_operand" "")
4246 (clobber (reg:SI T_REG))]
4248 [(use (reg:SI R0_REG))]
4250 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
4255 (define_insn "shl_sext_ext"
4256 [(set (match_operand:SI 0 "register_operand" "=r")
4258 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4259 (match_operand:SI 2 "const_int_operand" "n"))
4260 (match_operand:SI 3 "const_int_operand" "n")
4262 (clobber (reg:SI T_REG))]
4263 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
4265 [(set (attr "length")
4266 (cond [(match_test "shl_sext_length (insn)")
4268 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
4270 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4272 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4274 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4276 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4278 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
4280 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
4281 (const_string "16")]
4282 (const_string "18")))
4283 (set_attr "type" "arith")])
4285 (define_insn "shl_sext_sub"
4286 [(set (match_operand:SI 0 "register_operand" "=z")
4288 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4289 (match_operand:SI 2 "const_int_operand" "n"))
4290 (match_operand:SI 3 "const_int_operand" "n")
4292 (clobber (reg:SI T_REG))]
4293 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
4295 [(set (attr "length")
4296 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4298 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4300 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4302 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4303 (const_string "12")]
4304 (const_string "14")))
4305 (set_attr "type" "arith")])
4307 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
4308 ;; shifts by 16, and allow the xtrct instruction to be generated from C
4310 (define_insn "xtrct_left"
4311 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4312 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4314 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
4318 [(set_attr "type" "arith")])
4320 (define_insn "xtrct_right"
4321 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4322 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4324 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
4328 [(set_attr "type" "arith")])
4330 ;; -------------------------------------------------------------------------
4332 ;; -------------------------------------------------------------------------
4335 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4336 (neg:SI (plus:SI (reg:SI T_REG)
4337 (match_operand:SI 1 "arith_reg_operand" "r"))))
4339 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
4343 [(set_attr "type" "arith")])
4345 ;; A simplified version of the negc insn, where the exact value of the
4346 ;; T bit doesn't matter. This is easier for combine to pick up.
4347 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
4348 ;; extra patterns for this case.
4349 (define_insn_and_split "*negc"
4350 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4351 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
4352 (match_operand 2 "treg_set_expr")))
4353 (clobber (reg:SI T_REG))]
4354 "TARGET_SH1 && can_create_pseudo_p ()"
4359 sh_split_treg_set_expr (operands[2], curr_insn);
4360 emit_insn (gen_negc (operands[0], operands[1]));
4364 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
4366 (define_insn_and_split "negdi2"
4367 [(set (match_operand:DI 0 "arith_reg_dest")
4368 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
4369 (clobber (reg:SI T_REG))]
4372 "&& can_create_pseudo_p ()"
4375 emit_insn (gen_clrt ());
4376 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4377 gen_lowpart (SImode, operands[1])));
4378 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4379 gen_highpart (SImode, operands[1])));
4383 (define_insn "negsi2"
4384 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4385 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4388 [(set_attr "type" "arith")])
4390 (define_insn_and_split "one_cmplsi2"
4391 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4392 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4395 "&& can_create_pseudo_p ()"
4396 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
4397 (set (match_dup 0) (reg:SI T_REG))]
4400 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
4403 (set (reg0) (not:SI (reg0) (reg1)))
4404 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
4405 (clobber (reg:SI T_REG))])
4407 ... match and combine the sequence manually in the split pass after the
4408 combine pass. Notice that combine does try the target pattern of this
4409 split, but if the pattern is added it interferes with other patterns, in
4410 particular with the div0s comparisons.
4411 This could also be done with a peephole but doing it here before register
4412 allocation can save one temporary.
4413 When we're here, the not:SI pattern obviously has been matched already
4414 and we only have to see whether the following insn is the left shift. */
4416 rtx_insn *i = next_nonnote_insn_bb (curr_insn);
4417 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
4420 rtx p = PATTERN (i);
4421 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
4424 rtx p0 = XVECEXP (p, 0, 0);
4425 rtx p1 = XVECEXP (p, 0, 1);
4427 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
4428 GET_CODE (p0) == SET
4429 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
4430 && REG_P (XEXP (XEXP (p0, 1), 0))
4431 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
4432 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
4433 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
4435 /* (clobber (reg:SI T_REG)) */
4436 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
4437 && REGNO (XEXP (p1, 0)) == T_REG)
4439 operands[0] = XEXP (p0, 0);
4440 set_insn_deleted (i);
4445 [(set_attr "type" "arith")])
4447 (define_insn_and_split "abs<mode>2"
4448 [(set (match_operand:SIDI 0 "arith_reg_dest")
4449 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
4450 (clobber (reg:SI T_REG))]
4453 "&& can_create_pseudo_p ()"
4456 if (<MODE>mode == SImode)
4457 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4460 rtx high_src = gen_highpart (SImode, operands[1]);
4461 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4464 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4469 (define_insn_and_split "*negabs<mode>2"
4470 [(set (match_operand:SIDI 0 "arith_reg_dest")
4471 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
4472 (clobber (reg:SI T_REG))]
4475 "&& can_create_pseudo_p ()"
4478 if (<MODE>mode == SImode)
4479 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4482 rtx high_src = gen_highpart (SImode, operands[1]);
4483 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4486 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4491 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
4492 ;; This can be used as some kind of conditional execution, which is useful
4494 ;; Actually the instruction scheduling should decide whether to use a
4495 ;; zero-offset branch or not for any generic case involving a single
4496 ;; instruction on SH4 202.
4497 (define_insn_and_split "negsi_cond"
4498 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4500 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
4501 (match_operand:SI 1 "arith_reg_operand" "0,0")
4502 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
4503 "TARGET_SH1 && TARGET_ZDCBRANCH"
4505 static const char* alt[] =
4515 return alt[which_alternative];
4517 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
4520 rtx skip_neg_label = gen_label_rtx ();
4522 emit_move_insn (operands[0], operands[1]);
4524 emit_jump_insn (INTVAL (operands[3])
4525 ? gen_branch_true (skip_neg_label)
4526 : gen_branch_false (skip_neg_label));
4528 emit_label_after (skip_neg_label,
4529 emit_insn (gen_negsi2 (operands[0], operands[1])));
4532 [(set_attr "type" "arith") ;; poor approximation
4533 (set_attr "length" "4")])
4535 (define_insn_and_split "negdi_cond"
4536 [(set (match_operand:DI 0 "arith_reg_dest")
4538 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
4539 (match_operand:DI 1 "arith_reg_operand")
4540 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
4541 (clobber (reg:SI T_REG))]
4544 "&& can_create_pseudo_p ()"
4547 rtx skip_neg_label = gen_label_rtx ();
4549 emit_move_insn (operands[0], operands[1]);
4551 emit_jump_insn (INTVAL (operands[3])
4552 ? gen_branch_true (skip_neg_label)
4553 : gen_branch_false (skip_neg_label));
4555 if (!INTVAL (operands[3]))
4556 emit_insn (gen_clrt ());
4558 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4559 gen_lowpart (SImode, operands[1])));
4560 emit_label_after (skip_neg_label,
4561 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4562 gen_highpart (SImode, operands[1]))));
4566 (define_expand "bswapsi2"
4567 [(set (match_operand:SI 0 "arith_reg_dest" "")
4568 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
4571 if (! can_create_pseudo_p ())
4575 rtx tmp0 = gen_reg_rtx (SImode);
4576 rtx tmp1 = gen_reg_rtx (SImode);
4578 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
4579 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
4580 emit_insn (gen_swapbsi2 (operands[0], tmp1));
4585 (define_insn "swapbsi2"
4586 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4587 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
4588 (const_int -65536)) ;; 0xFFFF0000
4589 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4591 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4592 (const_int 255)))))]
4595 [(set_attr "type" "arith")])
4597 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
4598 ;; partial byte swap expressions such as...
4599 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
4600 ;; ...which are currently not handled by the tree optimizers.
4601 ;; The combine pass will not initially try to combine the full expression,
4602 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
4603 ;; pattern acts as an intermediate pattern that will eventually lead combine
4604 ;; to the swapbsi2 pattern above.
4605 ;; As a side effect this also improves code that does (x & 0xFF) << 8
4606 ;; or (x << 8) & 0xFF00.
4607 (define_insn_and_split "*swapbisi2_and_shl8"
4608 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4609 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4612 (match_operand:SI 2 "arith_reg_operand" "r")))]
4613 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4615 "&& can_create_pseudo_p ()"
4618 rtx tmp0 = gen_reg_rtx (SImode);
4619 rtx tmp1 = gen_reg_rtx (SImode);
4621 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
4622 emit_insn (gen_swapbsi2 (tmp1, tmp0));
4623 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
4627 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
4628 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
4629 (define_insn_and_split "*swapbhisi2"
4630 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4631 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4634 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
4635 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4637 "&& can_create_pseudo_p ()"
4640 rtx tmp = gen_reg_rtx (SImode);
4642 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
4643 emit_insn (gen_swapbsi2 (operands[0], tmp));
4647 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
4651 ;; which can be simplified to...
4654 [(set (match_operand:SI 0 "arith_reg_dest" "")
4655 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4656 (const_int -65536)) ;; 0xFFFF0000
4657 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4659 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4661 (set (match_operand:SI 2 "arith_reg_dest" "")
4663 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
4665 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4666 (const_int -65536)) ;; 0xFFFF0000
4667 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4669 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4670 (const_int 255)))))])
4672 ;; -------------------------------------------------------------------------
4673 ;; Zero extension instructions
4674 ;; -------------------------------------------------------------------------
4676 (define_expand "zero_extend<mode>si2"
4677 [(set (match_operand:SI 0 "arith_reg_dest")
4678 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))])
4680 (define_insn_and_split "*zero_extend<mode>si2_compact"
4681 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4682 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4685 "&& can_create_pseudo_p ()"
4686 [(set (match_dup 0) (match_dup 2))]
4688 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4689 reg with a following zero extension. In the split pass after combine,
4690 try to figure out how the extended reg was set. If it originated from
4691 the T bit we can replace the zero extension with a reg move, which will
4692 be eliminated. Notice that this also helps the *cbranch_t splitter when
4693 it tries to post-combine tests and conditional branches, as it does not
4694 check for zero extensions. */
4695 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4696 if (operands[2] == NULL_RTX)
4699 [(set_attr "type" "arith")])
4701 (define_insn "zero_extendqihi2"
4702 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4703 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4706 [(set_attr "type" "arith")])
4708 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
4709 ;; They could also be used for simple memory addresses like @Rn by setting
4710 ;; the displacement value to zero. However, doing so too early results in
4711 ;; missed opportunities for other optimizations such as post-inc or index
4712 ;; addressing loads.
4713 ;; We don't allow the zero extending loads to match during RTL expansion,
4714 ;; as this would pessimize other optimization opportunities such as bit
4715 ;; extractions of unsigned mems, where the zero extraction is irrelevant.
4716 ;; If the zero extracting mem loads are emitted early it will be more
4717 ;; difficult to change them back to sign extending loads (which are preferred).
4718 ;; The combine pass will also try to combine mem loads and zero extends,
4719 ;; which is prevented by 'sh_legitimate_combined_insn'.
4720 (define_insn "*zero_extend<mode>si2_disp_mem"
4721 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4723 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
4727 movu.<bw> @(0,%t1),%0"
4728 [(set_attr "type" "load")
4729 (set_attr "length" "4")])
4731 ;; Convert the zero extending loads in sequences such as:
4732 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
4733 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4735 ;; back to sign extending loads like:
4736 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
4737 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4739 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
4740 ;; is only 2 bytes in size if the displacement is {K04|K05}.
4741 ;; If the displacement is greater it doesn't matter, so we convert anyways.
4743 [(set (match_operand:SI 0 "arith_reg_dest" "")
4744 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
4745 (set (match_operand 2 "nonimmediate_operand" "")
4746 (match_operand 3 "arith_reg_operand" ""))]
4748 && REGNO (operands[0]) == REGNO (operands[3])
4749 && peep2_reg_dead_p (2, operands[0])
4750 && GET_MODE_SIZE (GET_MODE (operands[2]))
4751 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
4752 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
4753 (set (match_dup 2) (match_dup 3))])
4755 ;; Fold sequences such as
4759 ;; movu.b @(0,r3),r7
4760 ;; This does not reduce the code size but the number of instructions is
4761 ;; halved, which results in faster code.
4763 [(set (match_operand:SI 0 "arith_reg_dest" "")
4764 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
4765 (set (match_operand:SI 2 "arith_reg_dest" "")
4766 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
4768 && GET_MODE (operands[1]) == GET_MODE (operands[3])
4769 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
4770 && REGNO (operands[0]) == REGNO (operands[3])
4771 && (REGNO (operands[2]) == REGNO (operands[0])
4772 || peep2_reg_dead_p (2, operands[0]))"
4773 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
4776 = replace_equiv_address (operands[1],
4777 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
4781 ;; -------------------------------------------------------------------------
4782 ;; Sign extension instructions
4783 ;; -------------------------------------------------------------------------
4785 ;; ??? This should be a define expand.
4786 ;; ??? Or perhaps it should be dropped?
4788 ;; convert_move generates good code for SH[1-4].
4790 (define_expand "extend<mode>si2"
4791 [(set (match_operand:SI 0 "arith_reg_dest")
4792 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
4794 (define_insn_and_split "*extend<mode>si2_compact_reg"
4795 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4796 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4799 "&& can_create_pseudo_p ()"
4800 [(set (match_dup 0) (match_dup 2))]
4802 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4803 reg with a following sign extension. In the split pass after combine,
4804 try to figure the extended reg was set. If it originated from the T
4805 bit we can replace the sign extension with a reg move, which will be
4807 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4808 if (operands[2] == NULL_RTX)
4811 [(set_attr "type" "arith")])
4813 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
4815 (define_insn "*extend<mode>si2_compact_mem_disp"
4816 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
4820 (match_operand:SI 1 "arith_reg_operand" "%r,r")
4821 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
4822 "TARGET_SH1 && ! TARGET_SH2A
4823 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
4825 mov.<bw> @(%O2,%1),%0
4827 [(set_attr "type" "load")])
4829 (define_insn "*extend<mode>si2_compact_mem_disp"
4830 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
4834 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
4835 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
4836 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
4838 mov.<bw> @(%O2,%1),%0
4840 mov.<bw> @(%O2,%1),%0"
4841 [(set_attr "type" "load")
4842 (set_attr "length" "2,2,4")])
4844 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
4845 ;; constraints, otherwise wrong code might get generated.
4846 (define_insn "*extend<mode>si2_predec"
4847 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4848 (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))]
4851 [(set_attr "type" "load")])
4853 ;; The *_snd patterns will take care of other QImode/HImode addressing
4854 ;; modes than displacement addressing. They must be defined _after_ the
4855 ;; displacement addressing patterns. Otherwise the displacement addressing
4856 ;; patterns will not be picked.
4857 (define_insn "*extend<mode>si2_compact_snd"
4858 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4860 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
4863 [(set_attr "type" "load")])
4865 (define_expand "extendqihi2"
4866 [(set (match_operand:HI 0 "arith_reg_dest")
4867 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
4870 (define_insn "*extendqihi2_compact_reg"
4871 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4872 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4875 [(set_attr "type" "arith")])
4877 ;; -------------------------------------------------------------------------
4878 ;; Move instructions
4879 ;; -------------------------------------------------------------------------
4881 (define_expand "push"
4882 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4883 (match_operand:SI 0 "register_operand"))])
4885 (define_expand "pop"
4886 [(set (match_operand:SI 0 "register_operand")
4887 (mem:SI (post_inc:SI (reg:SI SP_REG))))])
4889 (define_expand "push_e"
4890 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
4891 (match_operand:SF 0 "" ""))
4892 (use (reg:SI FPSCR_MODES_REG))
4893 (clobber (scratch:SI))])])
4895 (define_insn "push_fpul"
4896 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
4899 [(set_attr "type" "fstore")
4900 (set_attr "late_fp_use" "yes")
4901 (set_attr "hit_stack" "yes")])
4903 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
4905 (define_expand "push_4"
4906 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
4907 (match_operand:DF 0 "" ""))
4908 (use (reg:SI FPSCR_MODES_REG))
4909 (clobber (scratch:SI))])])
4911 (define_expand "pop_e"
4912 [(parallel [(set (match_operand:SF 0 "" "")
4913 (mem:SF (post_inc:SI (reg:SI SP_REG))))
4914 (use (reg:SI FPSCR_MODES_REG))
4915 (clobber (scratch:SI))])])
4917 (define_insn "pop_fpul"
4918 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
4921 [(set_attr "type" "load")
4922 (set_attr "hit_stack" "yes")])
4924 (define_expand "pop_4"
4925 [(parallel [(set (match_operand:DF 0 "" "")
4926 (mem:DF (post_inc:SI (reg:SI SP_REG))))
4927 (use (reg:SI FPSCR_MODES_REG))
4928 (clobber (scratch:SI))])])
4930 (define_expand "push_fpscr"
4937 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
4938 REG_INC, stack_pointer_rtx);
4942 (define_expand "pop_fpscr"
4949 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
4950 REG_INC, stack_pointer_rtx);
4954 ;; The clrt and sett patterns can happen as the result of optimization and
4956 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
4957 ;; In this case they might not disappear completely, because the T reg is
4958 ;; a fixed hard reg.
4959 ;; When DImode operations that use the T reg as carry/borrow are split into
4960 ;; individual SImode operations, the T reg is usually cleared before the
4961 ;; first SImode insn.
4963 [(set (reg:SI T_REG) (const_int 0))]
4966 [(set_attr "type" "mt_group")])
4969 [(set (reg:SI T_REG) (const_int 1))]
4972 [(set_attr "type" "mt_group")])
4974 ;; Use the combine pass to transform sequences such as
4978 ;; mov.l @(r0,r4),r0
4984 ;; See also PR 39423.
4985 ;; Notice that these patterns have a T_REG clobber, because the shift
4986 ;; sequence that will be split out might clobber the T_REG. Ideally, the
4987 ;; clobber would be added conditionally, depending on the result of
4988 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
4989 ;; through the ashlsi3 expander in order to get the right shift insn --
4990 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
4991 ;; FIXME: Combine never tries this kind of patterns for DImode.
4992 (define_insn_and_split "*movsi_index_disp_load"
4993 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4994 (match_operand:SI 1 "mem_index_disp_operand" "m"))
4995 (clobber (reg:SI T_REG))]
4998 "&& can_create_pseudo_p ()"
4999 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5000 (set (match_dup 0) (match_dup 7))]
5002 rtx mem = operands[1];
5003 rtx plus0_rtx = XEXP (mem, 0);
5004 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5005 rtx mult_rtx = XEXP (plus1_rtx, 0);
5007 operands[1] = XEXP (mult_rtx, 0);
5008 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5009 operands[3] = XEXP (plus1_rtx, 1);
5010 operands[4] = XEXP (plus0_rtx, 1);
5011 operands[5] = gen_reg_rtx (SImode);
5012 operands[6] = gen_reg_rtx (SImode);
5014 replace_equiv_address (mem,
5015 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5017 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
5020 (define_insn_and_split "*movhi_index_disp_load"
5021 [(set (match_operand:SI 0 "arith_reg_dest")
5022 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
5023 (clobber (reg:SI T_REG))]
5026 "&& can_create_pseudo_p ()"
5029 rtx mem = operands[1];
5030 rtx plus0_rtx = XEXP (mem, 0);
5031 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5032 rtx mult_rtx = XEXP (plus1_rtx, 0);
5034 rtx op_1 = XEXP (mult_rtx, 0);
5035 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5036 rtx op_3 = XEXP (plus1_rtx, 1);
5037 rtx op_4 = XEXP (plus0_rtx, 1);
5038 rtx op_5 = gen_reg_rtx (SImode);
5039 rtx op_6 = gen_reg_rtx (SImode);
5040 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
5042 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
5043 emit_insn (gen_addsi3 (op_6, op_5, op_3));
5045 if (<CODE> == SIGN_EXTEND)
5047 emit_insn (gen_extendhisi2 (operands[0], op_7));
5050 else if (<CODE> == ZERO_EXTEND)
5052 /* On SH2A the movu.w insn can be used for zero extending loads. */
5054 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
5057 emit_insn (gen_extendhisi2 (operands[0], op_7));
5058 emit_insn (gen_zero_extendhisi2 (operands[0],
5059 gen_lowpart (HImode, operands[0])));
5067 (define_insn_and_split "*mov<mode>_index_disp_store"
5068 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
5069 (match_operand:HISI 1 "arith_reg_operand" "r"))
5070 (clobber (reg:SI T_REG))]
5073 "&& can_create_pseudo_p ()"
5074 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5075 (set (match_dup 7) (match_dup 1))]
5077 rtx mem = operands[0];
5078 rtx plus0_rtx = XEXP (mem, 0);
5079 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5080 rtx mult_rtx = XEXP (plus1_rtx, 0);
5082 operands[0] = XEXP (mult_rtx, 0);
5083 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5084 operands[3] = XEXP (plus1_rtx, 1);
5085 operands[4] = XEXP (plus0_rtx, 1);
5086 operands[5] = gen_reg_rtx (SImode);
5087 operands[6] = gen_reg_rtx (SImode);
5089 replace_equiv_address (mem,
5090 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5092 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
5095 ;; t/r must come after r/r, lest reload will try to reload stuff like
5096 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
5097 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
5098 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5099 ;; those alternatives will not be taken, as they will be converted into
5100 ;; PC-relative loads.
5101 (define_insn "movsi_i"
5102 [(set (match_operand:SI 0 "general_movdst_operand"
5103 "=r,r, r, r, r, r,r,r,m,<,<,x,l,x,l,r")
5104 (match_operand:SI 1 "general_movsrc_operand"
5105 " Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,i"))]
5106 "TARGET_SH1 && !TARGET_FPU_ANY
5107 && (register_operand (operands[0], SImode)
5108 || register_operand (operands[1], SImode))"
5126 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5127 mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
5128 (set_attr_alternative "length"
5134 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5135 (const_int 4) (const_int 2))
5138 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5139 (const_int 4) (const_int 2))
5148 ;; t/r must come after r/r, lest reload will try to reload stuff like
5149 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
5150 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
5151 ;; will require a reload.
5152 ;; ??? We can't include f/f because we need the proper FPSCR setting when
5153 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
5154 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5155 ;; those alternatives will not be taken, as they will be converted into
5156 ;; PC-relative loads.
5157 (define_insn "movsi_ie"
5158 [(set (match_operand:SI 0 "general_movdst_operand"
5159 "=r,r, r, r, r, r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f, y,*f,y")
5160 (match_operand:SI 1 "general_movsrc_operand"
5161 " Q,r,I08,I20,I28,mr,x,l, r,x,l,r,r,>,>,>,y,i,r,y, y,*f,*f,y"))]
5162 "TARGET_SH1 && TARGET_FPU_ANY
5163 && ((register_operand (operands[0], SImode)
5164 && !fpscr_operand (operands[0], SImode))
5165 || (register_operand (operands[1], SImode)
5166 && !fpscr_operand (operands[1], SImode)))"
5191 ! move optimized away"
5192 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5193 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
5194 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
5195 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
5196 (set_attr_alternative "length"
5202 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5203 (const_int 4) (const_int 2))
5206 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5207 (const_int 4) (const_int 2))
5224 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5225 ;; those alternatives will not be taken, as they will be converted into
5226 ;; PC-relative loads.
5227 (define_insn "movsi_i_lowpart"
5228 [(set (strict_low_part
5229 (match_operand:SI 0 "general_movdst_operand"
5230 "+r,r, r, r, r, r,r,r,m,r"))
5231 (match_operand:SI 1 "general_movsrc_operand"
5232 " Q,r,I08,I20,I28,mr,x,l,r,i"))]
5234 && (register_operand (operands[0], SImode)
5235 || register_operand (operands[1], SImode))"
5247 [(set_attr "type" "pcload,move,movi8,move,move,load,mac_gp,prget,store,
5249 (set_attr_alternative "length"
5255 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5256 (const_int 4) (const_int 2))
5259 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5260 (const_int 4) (const_int 2))
5263 (define_insn_and_split "load_ra"
5264 [(set (match_operand:SI 0 "general_movdst_operand" "")
5265 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
5268 "&& ! currently_expanding_to_rtl"
5269 [(set (match_dup 0) (match_dup 1))])
5271 (define_expand "movsi"
5272 [(set (match_operand:SI 0 "general_movdst_operand" "")
5273 (match_operand:SI 1 "general_movsrc_operand" ""))]
5276 prepare_move_operands (operands, SImode);
5279 (define_expand "ic_invalidate_line"
5280 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand")
5281 (match_dup 1)] UNSPEC_ICACHE)
5282 (clobber (scratch:SI))])]
5285 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
5289 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
5290 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
5291 ;; the requirement *1*00 for associative address writes. The alignment of
5292 ;; %0 implies that its least significant bit is cleared,
5293 ;; thus we clear the V bit of a matching entry if there is one.
5294 (define_insn "ic_invalidate_line_i"
5295 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
5296 (match_operand:SI 1 "register_operand" "r")]
5298 (clobber (match_scratch:SI 2 "=&r"))]
5301 return "ocbwb @%0" "\n"
5302 " extu.w %0,%2" "\n"
5306 [(set_attr "length" "8")
5307 (set_attr "type" "cwb")])
5309 (define_insn "ic_invalidate_line_sh4a"
5310 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
5312 "TARGET_SH4A || TARGET_SH4_300"
5314 return "ocbwb @%0" "\n"
5318 [(set_attr "length" "6")
5319 (set_attr "type" "cwb")])
5321 (define_expand "mov<mode>"
5322 [(set (match_operand:QIHI 0 "general_movdst_operand")
5323 (match_operand:QIHI 1 "general_movsrc_operand"))]
5326 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
5327 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
5329 rtx reg = gen_reg_rtx(SImode);
5330 emit_move_insn (reg, operands[1]);
5331 operands[1] = gen_lowpart (<MODE>mode, reg);
5334 prepare_move_operands (operands, <MODE>mode);
5337 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
5338 ;; constraints, otherwise wrong code might get generated.
5339 (define_insn "*mov<mode>_load_predec"
5340 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
5341 (match_operand:QIHISI 1 "pre_dec_mem" "<"))]
5344 [(set_attr "type" "load")])
5346 (define_insn "*mov<mode>_store_postinc"
5347 [(set (match_operand:QIHISI 0 "post_inc_mem" "=>")
5348 (match_operand:QIHISI 1 "arith_reg_operand" "z"))]
5351 [(set_attr "type" "store")])
5353 ;; Specifying the displacement addressing load / store patterns separately
5354 ;; before the generic movqi / movhi pattern allows controlling the order
5355 ;; in which load / store insns are selected in a more fine grained way.
5356 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
5357 ;; "enabled" attribute as it is done in other targets.
5358 (define_insn "*mov<mode>_store_mem_disp04"
5360 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
5361 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
5362 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
5363 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
5365 mov.<bw> %2,@(%O1,%0)
5367 [(set_attr "type" "store")])
5369 (define_insn "*mov<mode>_store_mem_disp12"
5371 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
5372 (match_operand:SI 1 "const_int_operand" "<disp12>")))
5373 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
5374 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
5375 "mov.<bw> %2,@(%O1,%0)"
5376 [(set_attr "type" "store")
5377 (set_attr "length" "4")])
5379 (define_insn "*mov<mode>_load_mem_disp04"
5380 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
5382 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
5383 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
5384 "TARGET_SH1 && ! TARGET_SH2A
5385 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
5387 mov.<bw> @(%O2,%1),%0
5389 [(set_attr "type" "load")])
5391 (define_insn "*mov<mode>_load_mem_disp12"
5392 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
5395 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
5396 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
5397 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
5399 mov.<bw> @(%O2,%1),%0
5401 mov.<bw> @(%O2,%1),%0"
5402 [(set_attr "type" "load")
5403 (set_attr "length" "2,2,4")])
5405 ;; The order of the constraint alternatives is important here.
5406 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
5407 ;; placed into delay slots. Since there is no QImode PC relative load, the
5408 ;; Q constraint and general_movsrc_operand will reject it for QImode.
5409 ;; The Sid/Ssd alternatives should come before Sdd in order to avoid
5410 ;; a preference of using r0 als the register operand for addressing modes
5411 ;; other than displacement addressing.
5412 ;; The Sdd alternatives allow only r0 as register operand, even though on
5413 ;; SH2A any register could be allowed by switching to a 32 bit insn.
5414 ;; Generally sticking to the r0 is preferrable, since it generates smaller
5415 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
5416 (define_insn "*mov<mode>"
5417 [(set (match_operand:QIHI 0 "general_movdst_operand"
5418 "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l")
5419 (match_operand:QIHI 1 "general_movsrc_operand"
5420 "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))]
5422 && (arith_reg_operand (operands[0], <MODE>mode)
5423 || arith_reg_operand (operands[1], <MODE>mode))"
5436 [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
5437 (set (attr "length")
5438 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 4)
5439 (match_operand 1 "long_displacement_mem_operand") (const_int 4)]
5442 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
5443 ;; compiled with -m2 -ml -O3 -funroll-loops
5444 (define_insn "*movdi_i"
5445 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m, r,r,r,*!x")
5446 (match_operand:DI 1 "general_movsrc_operand" " Q,r,m,r,I08,i,x, r"))]
5448 && (arith_reg_operand (operands[0], DImode)
5449 || arith_reg_operand (operands[1], DImode))"
5451 return output_movedouble (insn, operands, DImode);
5453 [(set_attr "type" "pcload,move,load,store,move,pcload,move,move")
5454 (set (attr "length")
5455 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5456 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5459 ;; If the output is a register and the input is memory or a register, we have
5460 ;; to be careful and see which word needs to be loaded first.
5462 [(set (match_operand:DI 0 "general_movdst_operand" "")
5463 (match_operand:DI 1 "general_movsrc_operand" ""))]
5464 "TARGET_SH1 && reload_completed"
5465 [(set (match_dup 2) (match_dup 3))
5466 (set (match_dup 4) (match_dup 5))]
5470 if ((MEM_P (operands[0])
5471 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5472 || (MEM_P (operands[1])
5473 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5476 switch (GET_CODE (operands[0]))
5479 regno = REGNO (operands[0]);
5482 regno = subreg_regno (operands[0]);
5491 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5493 operands[2] = operand_subword (operands[0], 0, 0, DImode);
5494 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5495 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5496 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5500 operands[2] = operand_subword (operands[0], 1, 0, DImode);
5501 operands[3] = operand_subword (operands[1], 1, 0, DImode);
5502 operands[4] = operand_subword (operands[0], 0, 0, DImode);
5503 operands[5] = operand_subword (operands[1], 0, 0, DImode);
5506 if (operands[2] == 0 || operands[3] == 0
5507 || operands[4] == 0 || operands[5] == 0)
5511 (define_expand "movdi"
5512 [(set (match_operand:DI 0 "general_movdst_operand" "")
5513 (match_operand:DI 1 "general_movsrc_operand" ""))]
5516 prepare_move_operands (operands, DImode);
5518 /* When the dest operand is (R0, R1) register pair, split it to
5519 two movsi of which dest is R1 and R0 so as to lower R0-register
5520 pressure on the first movsi. Apply only for simple source not
5521 to make complex rtl here. */
5522 if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG
5523 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5525 emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
5526 gen_rtx_SUBREG (SImode, operands[1], 4)));
5527 emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
5528 gen_rtx_SUBREG (SImode, operands[1], 0)));
5533 ;; FIXME: This should be a define_insn_and_split.
5534 (define_insn "movdf_k"
5535 [(set (match_operand:DF 0 "general_movdst_operand" "=r, r,r,m")
5536 (match_operand:DF 1 "general_movsrc_operand" " r,FQ,m,r"))]
5538 && (!TARGET_FPU_DOUBLE || reload_completed
5539 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
5540 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
5541 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
5542 && (arith_reg_operand (operands[0], DFmode)
5543 || arith_reg_operand (operands[1], DFmode))"
5545 return output_movedouble (insn, operands, DFmode);
5547 [(set_attr "type" "move,pcload,load,store")
5548 (set (attr "length")
5549 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5550 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5553 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
5554 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
5555 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
5556 ;; the d/m/c/X alternative, which is split later into single-precision
5557 ;; instructions. And when not optimizing, no splits are done before fixing
5558 ;; up pcloads, so we need usable length information for that.
5559 ;; A DF constant load results in the following worst-case 8 byte sequence:
5564 (define_insn "movdf_i4"
5565 [(set (match_operand:DF 0 "general_movdst_operand"
5566 "=d,r, d,d,m, r,r,m,!??r,!???d")
5567 (match_operand:DF 1 "general_movsrc_operand"
5568 " d,r, F,m,d,FQ,m,r, d, r"))
5569 (use (reg:SI FPSCR_MODES_REG))
5570 (clobber (match_scratch:SI 2
5571 "=X,X,&z,X,X, X,X,X, X, X"))]
5573 && (arith_reg_operand (operands[0], DFmode)
5574 || arith_reg_operand (operands[1], DFmode))"
5576 switch (which_alternative)
5580 return "fmov %1,%0";
5581 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
5582 return "fmov %R1,%R0" "\n"
5585 return "fmov %S1,%S0" "\n"
5589 return "fmov.d %1,%0";
5594 [(set_attr_alternative "length"
5595 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
5597 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
5598 (if_then_else (match_operand 1 "displacement_mem_operand")
5599 (if_then_else (eq_attr "fmovd" "yes")
5600 (const_int 4) (const_int 8))
5601 (if_then_else (eq_attr "fmovd" "yes")
5602 (const_int 2) (const_int 4)))
5603 (if_then_else (match_operand 0 "displacement_mem_operand")
5604 (if_then_else (eq_attr "fmovd" "yes")
5605 (const_int 4) (const_int 8))
5606 (if_then_else (eq_attr "fmovd" "yes")
5607 (const_int 2) (const_int 4)))
5609 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5610 (const_int 8) (const_int 4))
5611 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5612 (const_int 8) (const_int 4))
5615 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,
5617 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
5618 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
5619 (const_string "double")
5620 (const_string "none")))])
5622 ;; Moving DFmode between fp/general registers through memory
5623 ;; (the top of the stack) is faster than moving through fpul even for
5624 ;; little endian. Because the type of an instruction is important for its
5625 ;; scheduling, it is beneficial to split these operations, rather than
5626 ;; emitting them in one single chunk, even if this will expose a stack
5627 ;; use that will prevent scheduling of other stack accesses beyond this
5630 [(set (match_operand:DF 0 "register_operand")
5631 (match_operand:DF 1 "register_operand"))
5632 (use (reg:SI FPSCR_MODES_REG))
5633 (clobber (match_scratch:SI 2))]
5634 "TARGET_FPU_DOUBLE && reload_completed
5635 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
5640 tos = gen_tmp_stack_mem (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
5641 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
5642 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5643 tos = gen_tmp_stack_mem (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
5644 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
5645 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5649 ;; local-alloc sometimes allocates scratch registers even when not required,
5650 ;; so we must be prepared to handle these.
5652 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
5654 [(set (match_operand:DF 0 "general_movdst_operand" "")
5655 (match_operand:DF 1 "general_movsrc_operand" ""))
5656 (use (reg:SI FPSCR_MODES_REG))
5657 (clobber (match_scratch:SI 2))]
5660 && true_regnum (operands[0]) < 16
5661 && true_regnum (operands[1]) < 16"
5662 [(set (match_dup 0) (match_dup 1))]
5664 /* If this was a reg <-> mem operation with base + index reg addressing,
5665 we have to handle this in a special way. */
5666 rtx mem = operands[0];
5668 if (! memory_operand (mem, DFmode))
5673 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
5674 mem = SUBREG_REG (mem);
5677 rtx addr = XEXP (mem, 0);
5678 if (GET_CODE (addr) == PLUS
5679 && REG_P (XEXP (addr, 0))
5680 && REG_P (XEXP (addr, 1)))
5683 rtx reg0 = gen_rtx_REG (Pmode, 0);
5684 rtx regop = operands[store_p], word0 ,word1;
5686 if (GET_CODE (regop) == SUBREG)
5687 alter_subreg (®op, true);
5688 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
5692 mem = copy_rtx (mem);
5693 PUT_MODE (mem, SImode);
5694 word0 = gen_rtx_SUBREG (SImode, regop, 0);
5695 alter_subreg (&word0, true);
5696 word1 = gen_rtx_SUBREG (SImode, regop, 4);
5697 alter_subreg (&word1, true);
5698 if (store_p || ! refers_to_regno_p (REGNO (word0), addr))
5701 ? gen_movsi_ie (mem, word0)
5702 : gen_movsi_ie (word0, mem));
5703 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5704 mem = copy_rtx (mem);
5706 ? gen_movsi_ie (mem, word1)
5707 : gen_movsi_ie (word1, mem));
5708 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5712 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5713 emit_insn (gen_movsi_ie (word1, mem));
5714 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5715 mem = copy_rtx (mem);
5716 emit_insn (gen_movsi_ie (word0, mem));
5723 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
5725 [(set (match_operand:DF 0 "register_operand" "")
5726 (match_operand:DF 1 "memory_operand" ""))
5727 (use (reg:SI FPSCR_MODES_REG))
5728 (clobber (reg:SI R0_REG))]
5729 "TARGET_FPU_DOUBLE && reload_completed"
5730 [(parallel [(set (match_dup 0) (match_dup 1))
5731 (use (reg:SI FPSCR_MODES_REG))
5732 (clobber (scratch:SI))])]
5735 (define_expand "reload_indf__frn"
5736 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
5737 (match_operand:DF 1 "immediate_operand" "FQ"))
5738 (use (reg:SI FPSCR_MODES_REG))
5739 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5743 (define_expand "reload_outdf__RnFRm"
5744 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
5745 (match_operand:DF 1 "register_operand" "af,r"))
5746 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
5750 ;; Simplify no-op moves.
5752 [(set (match_operand:SF 0 "register_operand" "")
5753 (match_operand:SF 1 "register_operand" ""))
5754 (use (reg:SI FPSCR_MODES_REG))
5755 (clobber (match_scratch:SI 2))]
5756 "TARGET_SH2E && reload_completed
5757 && true_regnum (operands[0]) == true_regnum (operands[1])"
5758 [(set (match_dup 0) (match_dup 0))]
5761 ;; fmovd substitute post-reload splits
5763 [(set (match_operand:DF 0 "register_operand" "")
5764 (match_operand:DF 1 "register_operand" ""))
5765 (use (reg:SI FPSCR_MODES_REG))
5766 (clobber (match_scratch:SI 2))]
5767 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
5768 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5769 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5772 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
5773 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
5774 gen_rtx_REG (SFmode, src)));
5775 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
5776 gen_rtx_REG (SFmode, src + 1)));
5781 [(set (match_operand:DF 0 "register_operand" "")
5782 (mem:DF (match_operand:SI 1 "register_operand" "")))
5783 (use (reg:SI FPSCR_MODES_REG))
5784 (clobber (match_scratch:SI 2))]
5785 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5786 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5787 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
5790 int regno = true_regnum (operands[0]);
5792 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
5794 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
5795 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5796 regno + SH_REG_MSW_OFFSET),
5798 add_reg_note (insn, REG_INC, operands[1]);
5799 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5800 regno + SH_REG_LSW_OFFSET),
5801 change_address (mem, SFmode, NULL_RTX)));
5806 [(set (match_operand:DF 0 "register_operand" "")
5807 (match_operand:DF 1 "memory_operand" ""))
5808 (use (reg:SI FPSCR_MODES_REG))
5809 (clobber (match_scratch:SI 2))]
5810 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5811 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
5814 int regno = true_regnum (operands[0]);
5816 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
5817 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5818 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5820 operands[1] = copy_rtx (mem2);
5821 addr = XEXP (mem2, 0);
5823 switch (GET_CODE (addr))
5826 /* This is complicated. If the register is an arithmetic register
5827 we can just fall through to the REG+DISP case below. Otherwise
5828 we have to use a combination of POST_INC and REG addressing... */
5829 if (! arith_reg_operand (operands[1], SFmode))
5831 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
5832 insn = emit_insn (gen_movsf_ie (reg0, mem2));
5833 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5835 emit_insn (gen_movsf_ie (reg1, operands[1]));
5837 /* If we have modified the stack pointer, the value that we have
5838 read with post-increment might be modified by an interrupt,
5839 so write it back. */
5840 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
5841 emit_insn (gen_push_e (reg0));
5843 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
5850 emit_insn (gen_movsf_ie (reg0, operands[1]));
5851 operands[1] = copy_rtx (operands[1]);
5852 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
5853 emit_insn (gen_movsf_ie (reg1, operands[1]));
5857 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
5858 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5860 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
5861 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5873 [(set (match_operand:DF 0 "memory_operand" "")
5874 (match_operand:DF 1 "register_operand" ""))
5875 (use (reg:SI FPSCR_MODES_REG))
5876 (clobber (match_scratch:SI 2))]
5877 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5878 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5881 int regno = true_regnum (operands[1]);
5883 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5884 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5886 operands[0] = copy_rtx (operands[0]);
5887 PUT_MODE (operands[0], SFmode);
5888 addr = XEXP (operands[0], 0);
5890 switch (GET_CODE (addr))
5893 /* This is complicated. If the register is an arithmetic register
5894 we can just fall through to the REG+DISP case below. Otherwise
5895 we have to use a combination of REG and PRE_DEC addressing... */
5896 if (! arith_reg_operand (operands[0], SFmode))
5898 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
5899 emit_insn (gen_movsf_ie (operands[0], reg1));
5901 operands[0] = copy_rtx (operands[0]);
5902 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
5904 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5905 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5911 /* Since REG+DISP addressing has already been decided upon by gcc
5912 we can rely upon it having chosen an arithmetic register as the
5913 register component of the address. Just emit the lower numbered
5914 register first, to the lower address, then the higher numbered
5915 register to the higher address. */
5916 emit_insn (gen_movsf_ie (operands[0], reg0));
5918 operands[0] = copy_rtx (operands[0]);
5919 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
5921 emit_insn (gen_movsf_ie (operands[0], reg1));
5925 /* This is easy. Output the word to go to the higher address
5926 first (ie the word in the higher numbered register) then the
5927 word to go to the lower address. */
5929 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
5930 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5932 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5933 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5945 ;; If the output is a register and the input is memory or a register, we have
5946 ;; to be careful and see which word needs to be loaded first.
5948 [(set (match_operand:DF 0 "general_movdst_operand" "")
5949 (match_operand:DF 1 "general_movsrc_operand" ""))]
5950 "TARGET_SH1 && reload_completed"
5951 [(set (match_dup 2) (match_dup 3))
5952 (set (match_dup 4) (match_dup 5))]
5956 if ((MEM_P (operands[0])
5957 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5958 || (MEM_P (operands[1])
5959 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5962 switch (GET_CODE (operands[0]))
5965 regno = REGNO (operands[0]);
5968 regno = subreg_regno (operands[0]);
5977 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5979 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
5980 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
5981 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
5982 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
5986 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
5987 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
5988 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
5989 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
5992 if (operands[2] == 0 || operands[3] == 0
5993 || operands[4] == 0 || operands[5] == 0)
5997 (define_expand "movdf"
5998 [(set (match_operand:DF 0 "general_movdst_operand" "")
5999 (match_operand:DF 1 "general_movsrc_operand" ""))]
6002 prepare_move_operands (operands, DFmode);
6003 if (TARGET_FPU_DOUBLE)
6005 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
6010 ;; FIXME Although the movsf_i pattern is not used when there's an FPU,
6011 ;; it somehow influences some RA choices also on FPU targets.
6012 ;; For non-FPU targets it's actually not needed.
6013 (define_insn "movsf_i"
6014 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r, r, r,m,l,r")
6015 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
6018 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
6019 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
6020 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
6021 && (arith_reg_operand (operands[0], SFmode)
6022 || arith_reg_operand (operands[1], SFmode))"
6031 [(set_attr "type" "move,move,pcload,load,store,move,move")
6032 (set_attr_alternative "length"
6035 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6036 (const_int 4) (const_int 2))
6037 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6038 (const_int 4) (const_int 2))
6039 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6040 (const_int 4) (const_int 2))
6044 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
6045 ;; update_flow_info would not know where to put REG_EQUAL notes
6046 ;; when the destination changes mode.
6047 (define_insn "movsf_ie"
6048 [(set (match_operand:SF 0 "general_movdst_operand"
6049 "=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
6050 (match_operand:SF 1 "general_movsrc_operand"
6051 " f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
6052 (use (reg:SI FPSCR_MODES_REG))
6053 (clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
6055 && (arith_reg_operand (operands[0], SFmode)
6056 || fpul_operand (operands[0], SFmode)
6057 || arith_reg_operand (operands[1], SFmode)
6058 || fpul_operand (operands[1], SFmode)
6059 || arith_reg_operand (operands[2], SImode))"
6079 ! move optimized away"
6080 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6081 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6082 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6083 (set_attr_alternative "length"
6089 (if_then_else (match_operand 1 "displacement_mem_operand")
6090 (const_int 4) (const_int 2))
6091 (if_then_else (match_operand 0 "displacement_mem_operand")
6092 (const_int 4) (const_int 2))
6094 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6095 (const_int 4) (const_int 2))
6096 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6097 (const_int 4) (const_int 2))
6107 (set_attr_alternative "fp_mode"
6108 [(if_then_else (eq_attr "fmovd" "yes")
6109 (const_string "single") (const_string "none"))
6110 (const_string "none")
6111 (const_string "single")
6112 (const_string "single")
6113 (const_string "none")
6114 (if_then_else (eq_attr "fmovd" "yes")
6115 (const_string "single") (const_string "none"))
6116 (if_then_else (eq_attr "fmovd" "yes")
6117 (const_string "single") (const_string "none"))
6118 (const_string "none")
6119 (const_string "none")
6120 (const_string "none")
6121 (const_string "none")
6122 (const_string "none")
6123 (const_string "none")
6124 (const_string "none")
6125 (const_string "none")
6126 (const_string "none")
6127 (const_string "none")
6128 (const_string "none")
6129 (const_string "none")])])
6131 (define_insn_and_split "movsf_ie_ra"
6132 [(set (match_operand:SF 0 "general_movdst_operand"
6133 "=f,r,f,f,fy,f,m, r,r,m,f,y,y,rf,r,y,<,y,y")
6134 (match_operand:SF 1 "general_movsrc_operand"
6135 " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
6136 (use (reg:SI FPSCR_MODES_REG))
6137 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r"))
6140 && (arith_reg_operand (operands[0], SFmode)
6141 || fpul_operand (operands[0], SFmode)
6142 || arith_reg_operand (operands[1], SFmode)
6143 || fpul_operand (operands[1], SFmode))"
6163 ! move optimized away"
6165 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
6168 if (! rtx_equal_p (operands[0], operands[1]))
6170 emit_insn (gen_movsf_ie (operands[2], operands[1]));
6171 emit_insn (gen_movsf_ie (operands[0], operands[2]));
6174 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6175 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6176 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6177 (set_attr_alternative "length"
6183 (if_then_else (match_operand 1 "displacement_mem_operand")
6184 (const_int 4) (const_int 2))
6185 (if_then_else (match_operand 0 "displacement_mem_operand")
6186 (const_int 4) (const_int 2))
6188 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6189 (const_int 4) (const_int 2))
6190 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6191 (const_int 4) (const_int 2))
6201 (set_attr_alternative "fp_mode"
6202 [(if_then_else (eq_attr "fmovd" "yes")
6203 (const_string "single") (const_string "none"))
6204 (const_string "none")
6205 (const_string "single")
6206 (const_string "single")
6207 (const_string "none")
6208 (if_then_else (eq_attr "fmovd" "yes")
6209 (const_string "single") (const_string "none"))
6210 (if_then_else (eq_attr "fmovd" "yes")
6211 (const_string "single") (const_string "none"))
6212 (const_string "none")
6213 (const_string "none")
6214 (const_string "none")
6215 (const_string "none")
6216 (const_string "none")
6217 (const_string "none")
6218 (const_string "none")
6219 (const_string "none")
6220 (const_string "none")
6221 (const_string "none")
6222 (const_string "none")
6223 (const_string "none")])])
6226 [(set (match_operand:SF 0 "register_operand" "")
6227 (match_operand:SF 1 "register_operand" ""))
6228 (use (reg:SI FPSCR_MODES_REG))
6229 (clobber (reg:SI FPUL_REG))]
6231 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
6232 (use (reg:SI FPSCR_MODES_REG))
6233 (clobber (scratch:SI))])
6234 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
6235 (use (reg:SI FPSCR_MODES_REG))
6236 (clobber (scratch:SI))])]
6239 (define_expand "movsf"
6240 [(set (match_operand:SF 0 "general_movdst_operand" "")
6241 (match_operand:SF 1 "general_movsrc_operand" ""))]
6244 prepare_move_operands (operands, SFmode);
6247 if (lra_in_progress)
6249 if (GET_CODE (operands[0]) == SCRATCH)
6251 emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
6255 emit_insn (gen_movsf_ie (operands[0], operands[1]));
6260 (define_expand "reload_insf__frn"
6261 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
6262 (match_operand:SF 1 "immediate_operand" "FQ"))
6263 (use (reg:SI FPSCR_MODES_REG))
6264 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6268 (define_expand "reload_insi__i_fpul"
6269 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
6270 (match_operand:SI 1 "immediate_operand" "i"))
6271 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6275 (define_insn "*movsi_y"
6276 [(set (match_operand:SI 0 "register_operand" "=y,y")
6277 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
6278 (clobber (match_scratch:SI 2 "=&z,r"))]
6280 && (reload_in_progress || reload_completed)"
6282 [(set_attr "length" "4")
6283 (set_attr "type" "pcload,move")])
6286 [(set (match_operand:SI 0 "register_operand" "")
6287 (match_operand:SI 1 "immediate_operand" ""))
6288 (clobber (match_operand:SI 2 "register_operand" ""))]
6290 [(set (match_dup 2) (match_dup 1))
6291 (set (match_dup 0) (match_dup 2))]
6294 ;; ------------------------------------------------------------------------
6295 ;; Define the real conditional branch instructions.
6296 ;; ------------------------------------------------------------------------
6298 (define_expand "branch_true"
6299 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
6300 (label_ref (match_operand 0))
6304 (define_expand "branch_false"
6305 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6306 (label_ref (match_operand 0))
6310 (define_insn_and_split "*cbranch_t"
6311 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
6312 (label_ref (match_operand 0))
6316 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
6321 /* Try to canonicalize the branch condition if it is not one of:
6322 (ne (reg:SI T_REG) (const_int 0))
6323 (eq (reg:SI T_REG) (const_int 0))
6325 Instead of splitting out a new insn, we modify the current insn's
6326 operands as needed. This preserves things such as REG_DEAD notes. */
6328 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
6329 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
6330 && XEXP (operands[1], 1) == const0_rtx)
6333 int branch_cond = sh_eval_treg_value (operands[1]);
6334 rtx new_cond_rtx = NULL_RTX;
6336 if (branch_cond == 0)
6337 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
6338 else if (branch_cond == 1)
6339 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
6341 if (new_cond_rtx != NULL_RTX)
6342 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
6343 new_cond_rtx, false);
6346 [(set_attr "type" "cbranch")])
6348 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
6349 ;; which destination is too far away.
6350 ;; The const_int_operand is distinct for each branch target; it avoids
6351 ;; unwanted matches with redundant_insn.
6352 (define_insn "block_branch_redirect"
6353 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
6356 [(set_attr "length" "0")])
6358 ;; This one has the additional purpose to record a possible scratch register
6359 ;; for the following branch.
6360 ;; ??? Unfortunately, just setting the scratch register is not good enough,
6361 ;; because the insn then might be deemed dead and deleted. And we can't
6362 ;; make the use in the jump insn explicit because that would disable
6363 ;; delay slot scheduling from the target.
6364 (define_insn "indirect_jump_scratch"
6365 [(set (match_operand:SI 0 "register_operand" "=r")
6366 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
6367 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
6370 [(set_attr "length" "0")])
6372 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
6373 ;; being pulled into the delay slot of a condbranch that has been made to
6374 ;; jump around the unconditional jump because it was out of range.
6375 (define_insn "stuff_delay_slot"
6377 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
6378 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
6381 [(set_attr "length" "0")
6382 (set_attr "cond_delay_slot" "yes")])
6384 ;; Conditional branch insns
6386 ; operand 0 is the loop count pseudo register
6387 ; operand 1 is the label to jump to at the top of the loop
6388 (define_expand "doloop_end"
6389 [(parallel [(set (pc)
6390 (if_then_else (ne:SI (match_operand:SI 0 "" "")
6392 (label_ref (match_operand 1 "" ""))
6395 (plus:SI (match_dup 0) (const_int -1)))
6396 (clobber (reg:SI T_REG))])]
6399 if (GET_MODE (operands[0]) != SImode)
6401 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
6405 (define_insn_and_split "doloop_end_split"
6407 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
6409 (label_ref (match_operand 1 "" ""))
6411 (set (match_operand:SI 0 "arith_reg_dest" "=r")
6412 (plus:SI (match_dup 2) (const_int -1)))
6413 (clobber (reg:SI T_REG))]
6417 [(parallel [(set (reg:SI T_REG)
6418 (eq:SI (match_dup 2) (const_int 1)))
6419 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
6420 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6421 (label_ref (match_dup 1))
6424 [(set_attr "type" "cbranch")])
6426 ;; ------------------------------------------------------------------------
6427 ;; Jump and linkage insns
6428 ;; ------------------------------------------------------------------------
6430 (define_insn "jump_compact"
6432 (label_ref (match_operand 0 "" "")))]
6433 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
6435 /* The length is 16 if the delay slot is unfilled. */
6436 if (get_attr_length(insn) > 4)
6437 return output_far_jump(insn, operands[0]);
6441 [(set_attr "type" "jump")
6442 (set_attr "needs_delay_slot" "yes")])
6444 (define_insn "*jump_compact_crossing"
6446 (label_ref (match_operand 0 "" "")))]
6448 && flag_reorder_blocks_and_partition
6449 && CROSSING_JUMP_P (insn)"
6451 /* The length is 16 if the delay slot is unfilled. */
6452 return output_far_jump(insn, operands[0]);
6454 [(set_attr "type" "jump")
6455 (set_attr "length" "16")])
6457 (define_expand "jump"
6459 (label_ref (match_operand 0 "" "")))]
6462 emit_jump_insn (gen_jump_compact (operands[0]));
6466 (define_insn "calli"
6467 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6468 (match_operand 1 "" ""))
6469 (use (reg:SI FPSCR_MODES_REG))
6470 (clobber (reg:SI PR_REG))]
6471 "TARGET_SH1 && !TARGET_FDPIC"
6473 if (TARGET_SH2A && dbr_sequence_length () == 0)
6478 [(set_attr "type" "call")
6479 (set (attr "fp_mode")
6480 (if_then_else (eq_attr "fpu_single" "yes")
6481 (const_string "single") (const_string "double")))
6482 (set_attr "needs_delay_slot" "yes")
6483 (set_attr "fp_set" "unknown")])
6485 (define_insn "calli_fdpic"
6486 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6488 (use (reg:SI FPSCR_MODES_REG))
6489 (use (reg:SI PIC_REG))
6490 (clobber (reg:SI PR_REG))]
6493 if (TARGET_SH2A && dbr_sequence_length () == 0)
6498 [(set_attr "type" "call")
6499 (set (attr "fp_mode")
6500 (if_then_else (eq_attr "fpu_single" "yes")
6501 (const_string "single") (const_string "double")))
6502 (set_attr "needs_delay_slot" "yes")
6503 (set_attr "fp_set" "unknown")])
6505 ;; This is TBR relative jump instruction for SH2A architecture.
6506 ;; Its use is enabled by assigning an attribute "function_vector"
6507 ;; and the vector number to a function during its declaration.
6508 (define_insn "calli_tbr_rel"
6509 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
6510 (match_operand 1 "" ""))
6511 (use (reg:SI FPSCR_MODES_REG))
6512 (clobber (reg:SI PR_REG))]
6513 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
6515 unsigned HOST_WIDE_INT vect_num;
6516 vect_num = sh2a_get_function_vector_number (operands[0]);
6517 operands[2] = GEN_INT (vect_num * 4);
6519 return "jsr/n @@(%O2,tbr)";
6521 [(set_attr "type" "call")
6522 (set (attr "fp_mode")
6523 (if_then_else (eq_attr "fpu_single" "yes")
6524 (const_string "single") (const_string "double")))
6525 (set_attr "needs_delay_slot" "no")
6526 (set_attr "fp_set" "unknown")])
6528 ;; This is a pc-rel call, using bsrf, for use with PIC.
6529 (define_insn "calli_pcrel"
6530 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6531 (match_operand 1 "" ""))
6532 (use (reg:SI FPSCR_MODES_REG))
6533 (use (reg:SI PIC_REG))
6534 (use (match_operand 2 "" ""))
6535 (clobber (reg:SI PR_REG))]
6538 return "bsrf %0" "\n"
6541 [(set_attr "type" "call")
6542 (set (attr "fp_mode")
6543 (if_then_else (eq_attr "fpu_single" "yes")
6544 (const_string "single") (const_string "double")))
6545 (set_attr "needs_delay_slot" "yes")
6546 (set_attr "fp_set" "unknown")])
6548 (define_insn_and_split "call_pcrel"
6549 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6550 (match_operand 1 "" ""))
6551 (use (reg:SI FPSCR_MODES_REG))
6552 (use (reg:SI PIC_REG))
6553 (clobber (reg:SI PR_REG))
6554 (clobber (match_scratch:SI 2 "=&r"))]
6560 rtx lab = PATTERN (gen_call_site ());
6562 sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
6563 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
6566 [(set_attr "type" "call")
6567 (set (attr "fp_mode")
6568 (if_then_else (eq_attr "fpu_single" "yes")
6569 (const_string "single") (const_string "double")))
6570 (set_attr "needs_delay_slot" "yes")
6571 (set_attr "fp_set" "unknown")])
6573 (define_insn "call_valuei"
6574 [(set (match_operand 0 "" "=rf")
6575 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6576 (match_operand 2 "" "")))
6577 (use (reg:SI FPSCR_MODES_REG))
6578 (clobber (reg:SI PR_REG))]
6579 "TARGET_SH1 && !TARGET_FDPIC"
6581 if (TARGET_SH2A && dbr_sequence_length () == 0)
6586 [(set_attr "type" "call")
6587 (set (attr "fp_mode")
6588 (if_then_else (eq_attr "fpu_single" "yes")
6589 (const_string "single") (const_string "double")))
6590 (set_attr "needs_delay_slot" "yes")
6591 (set_attr "fp_set" "unknown")])
6593 (define_insn "call_valuei_fdpic"
6594 [(set (match_operand 0 "" "=rf")
6595 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6597 (use (reg:SI FPSCR_REG))
6598 (use (reg:SI PIC_REG))
6599 (clobber (reg:SI PR_REG))]
6602 if (TARGET_SH2A && dbr_sequence_length () == 0)
6607 [(set_attr "type" "call")
6608 (set (attr "fp_mode")
6609 (if_then_else (eq_attr "fpu_single" "yes")
6610 (const_string "single") (const_string "double")))
6611 (set_attr "needs_delay_slot" "yes")
6612 (set_attr "fp_set" "unknown")])
6614 ;; This is TBR relative jump instruction for SH2A architecture.
6615 ;; Its use is enabled by assigning an attribute "function_vector"
6616 ;; and the vector number to a function during its declaration.
6617 (define_insn "call_valuei_tbr_rel"
6618 [(set (match_operand 0 "" "=rf")
6619 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6620 (match_operand 2 "" "")))
6621 (use (reg:SI FPSCR_MODES_REG))
6622 (clobber (reg:SI PR_REG))]
6623 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
6625 unsigned HOST_WIDE_INT vect_num;
6626 vect_num = sh2a_get_function_vector_number (operands[1]);
6627 operands[3] = GEN_INT (vect_num * 4);
6629 return "jsr/n @@(%O3,tbr)";
6631 [(set_attr "type" "call")
6632 (set (attr "fp_mode")
6633 (if_then_else (eq_attr "fpu_single" "yes")
6634 (const_string "single") (const_string "double")))
6635 (set_attr "needs_delay_slot" "no")
6636 (set_attr "fp_set" "unknown")])
6638 (define_insn "call_valuei_pcrel"
6639 [(set (match_operand 0 "" "=rf")
6640 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6641 (match_operand 2 "" "")))
6642 (use (reg:SI FPSCR_MODES_REG))
6643 (use (reg:SI PIC_REG))
6644 (use (match_operand 3 "" ""))
6645 (clobber (reg:SI PR_REG))]
6648 return "bsrf %1" "\n"
6651 [(set_attr "type" "call")
6652 (set (attr "fp_mode")
6653 (if_then_else (eq_attr "fpu_single" "yes")
6654 (const_string "single") (const_string "double")))
6655 (set_attr "needs_delay_slot" "yes")
6656 (set_attr "fp_set" "unknown")])
6658 (define_insn_and_split "call_value_pcrel"
6659 [(set (match_operand 0 "" "=rf")
6660 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6661 (match_operand 2 "" "")))
6662 (use (reg:SI FPSCR_MODES_REG))
6663 (use (reg:SI PIC_REG))
6664 (clobber (reg:SI PR_REG))
6665 (clobber (match_scratch:SI 3 "=&r"))]
6671 rtx lab = PATTERN (gen_call_site ());
6673 sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
6674 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
6675 operands[2], copy_rtx (lab)));
6678 [(set_attr "type" "call")
6679 (set (attr "fp_mode")
6680 (if_then_else (eq_attr "fpu_single" "yes")
6681 (const_string "single") (const_string "double")))
6682 (set_attr "needs_delay_slot" "yes")
6683 (set_attr "fp_set" "unknown")])
6685 (define_expand "call"
6686 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6687 (match_operand 1 "" ""))
6688 (match_operand 2 "" "")
6689 (use (reg:SI FPSCR_MODES_REG))
6690 (clobber (reg:SI PR_REG))])]
6695 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6696 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6699 if (!flag_pic && TARGET_SH2A
6700 && MEM_P (operands[0])
6701 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6703 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
6705 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
6710 if (flag_pic && TARGET_SH2
6711 && MEM_P (operands[0])
6712 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6714 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
6719 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6720 operands[1] = operands[2];
6725 operands[0] = sh_load_function_descriptor (operands[0]);
6726 emit_call_insn (gen_calli_fdpic (operands[0], operands[1]));
6729 emit_call_insn (gen_calli (operands[0], operands[1]));
6733 (define_expand "call_value"
6734 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6735 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6736 (match_operand 2 "" "")))
6737 (match_operand 3 "" "")
6738 (use (reg:SI FPSCR_MODES_REG))
6739 (clobber (reg:SI PR_REG))])]
6744 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6745 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6748 if (!flag_pic && TARGET_SH2A
6749 && MEM_P (operands[1])
6750 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6752 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
6754 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
6755 XEXP (operands[1], 0), operands[2]));
6759 if (flag_pic && TARGET_SH2
6760 && MEM_P (operands[1])
6761 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6763 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
6768 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
6772 operands[1] = sh_load_function_descriptor (operands[1]);
6773 emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1],
6777 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
6781 (define_insn "sibcalli"
6782 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6783 (match_operand 1 "" ""))
6784 (use (reg:SI FPSCR_MODES_REG))
6786 "TARGET_SH1 && !TARGET_FDPIC"
6788 [(set_attr "needs_delay_slot" "yes")
6789 (set (attr "fp_mode")
6790 (if_then_else (eq_attr "fpu_single" "yes")
6791 (const_string "single") (const_string "double")))
6792 (set_attr "type" "jump_ind")])
6794 (define_insn "sibcalli_fdpic"
6795 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6797 (use (reg:SI FPSCR_MODES_REG))
6798 (use (reg:SI PIC_REG))
6802 [(set_attr "needs_delay_slot" "yes")
6803 (set (attr "fp_mode")
6804 (if_then_else (eq_attr "fpu_single" "yes")
6805 (const_string "single") (const_string "double")))
6806 (set_attr "type" "jump_ind")])
6808 (define_insn "sibcalli_pcrel"
6809 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6810 (match_operand 1 "" ""))
6811 (use (match_operand 2 "" ""))
6812 (use (reg:SI FPSCR_MODES_REG))
6814 "TARGET_SH2 && !TARGET_FDPIC"
6816 return "braf %0" "\n"
6819 [(set_attr "needs_delay_slot" "yes")
6820 (set (attr "fp_mode")
6821 (if_then_else (eq_attr "fpu_single" "yes")
6822 (const_string "single") (const_string "double")))
6823 (set_attr "type" "jump_ind")])
6825 (define_insn "sibcalli_pcrel_fdpic"
6826 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6828 (use (match_operand 2))
6829 (use (reg:SI FPSCR_MODES_REG))
6830 (use (reg:SI PIC_REG))
6832 "TARGET_SH2 && TARGET_FDPIC"
6834 return "braf %0" "\n"
6837 [(set_attr "needs_delay_slot" "yes")
6838 (set (attr "fp_mode")
6839 (if_then_else (eq_attr "fpu_single" "yes")
6840 (const_string "single") (const_string "double")))
6841 (set_attr "type" "jump_ind")])
6843 ;; This uses an unspec to describe that the symbol_ref is very close.
6844 (define_insn "sibcalli_thunk"
6845 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
6847 (match_operand 1 "" ""))
6848 (use (reg:SI FPSCR_MODES_REG))
6852 [(set_attr "needs_delay_slot" "yes")
6853 (set (attr "fp_mode")
6854 (if_then_else (eq_attr "fpu_single" "yes")
6855 (const_string "single") (const_string "double")))
6856 (set_attr "type" "jump")
6857 (set_attr "length" "2")])
6859 (define_insn_and_split "sibcall_pcrel"
6860 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6861 (match_operand 1 "" ""))
6862 (use (reg:SI FPSCR_MODES_REG))
6863 (clobber (match_scratch:SI 2 "=&k"))
6865 "TARGET_SH2 && !TARGET_FDPIC"
6870 rtx lab = PATTERN (gen_call_site ());
6873 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6874 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
6876 SIBLING_CALL_P (call_insn) = 1;
6879 [(set_attr "needs_delay_slot" "yes")
6880 (set (attr "fp_mode")
6881 (if_then_else (eq_attr "fpu_single" "yes")
6882 (const_string "single") (const_string "double")))
6883 (set_attr "type" "jump_ind")])
6885 (define_insn_and_split "sibcall_pcrel_fdpic"
6886 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand"))
6888 (use (reg:SI FPSCR_MODES_REG))
6889 (use (reg:SI PIC_REG))
6890 (clobber (match_scratch:SI 2 "=k"))
6892 "TARGET_SH2 && TARGET_FDPIC"
6894 "&& reload_completed"
6897 rtx lab = PATTERN (gen_call_site ());
6899 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6900 rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1],
6902 SIBLING_CALL_P (i) = 1;
6905 [(set_attr "needs_delay_slot" "yes")
6906 (set (attr "fp_mode")
6907 (if_then_else (eq_attr "fpu_single" "yes")
6908 (const_string "single") (const_string "double")))
6909 (set_attr "type" "jump_ind")])
6911 (define_expand "sibcall"
6913 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6914 (match_operand 1 "" ""))
6915 (match_operand 2 "" "")
6916 (use (reg:SI FPSCR_MODES_REG))
6922 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6923 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6926 if (flag_pic && TARGET_SH2
6927 && MEM_P (operands[0])
6928 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6929 /* The PLT needs the PIC register, but the epilogue would have
6930 to restore it, so we can only use PC-relative PIC calls for
6931 static functions. */
6932 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
6935 emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0),
6938 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
6942 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6946 operands[0] = sh_load_function_descriptor (operands[0]);
6947 emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1]));
6950 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
6954 (define_insn "sibcall_valuei"
6955 [(set (match_operand 0 "" "=rf")
6956 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6957 (match_operand 2 "" "")))
6958 (use (reg:SI FPSCR_MODES_REG))
6960 "TARGET_SH1 && !TARGET_FDPIC"
6962 [(set_attr "needs_delay_slot" "yes")
6963 (set (attr "fp_mode")
6964 (if_then_else (eq_attr "fpu_single" "yes")
6965 (const_string "single") (const_string "double")))
6966 (set_attr "type" "jump_ind")])
6968 (define_insn "sibcall_valuei_fdpic"
6969 [(set (match_operand 0 "" "=rf")
6970 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6972 (use (reg:SI FPSCR_MODES_REG))
6973 (use (reg:SI PIC_REG))
6977 [(set_attr "needs_delay_slot" "yes")
6978 (set (attr "fp_mode")
6979 (if_then_else (eq_attr "fpu_single" "yes")
6980 (const_string "single") (const_string "double")))
6981 (set_attr "type" "jump_ind")])
6983 (define_insn "sibcall_valuei_pcrel"
6984 [(set (match_operand 0 "" "=rf")
6985 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
6986 (match_operand 2 "" "")))
6987 (use (match_operand 3 "" ""))
6988 (use (reg:SI FPSCR_MODES_REG))
6990 "TARGET_SH2 && !TARGET_FDPIC"
6992 return "braf %1" "\n"
6995 [(set_attr "needs_delay_slot" "yes")
6996 (set (attr "fp_mode")
6997 (if_then_else (eq_attr "fpu_single" "yes")
6998 (const_string "single") (const_string "double")))
6999 (set_attr "type" "jump_ind")])
7001 (define_insn "sibcall_valuei_pcrel_fdpic"
7002 [(set (match_operand 0 "" "=rf")
7003 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
7005 (use (match_operand 3))
7006 (use (reg:SI FPSCR_MODES_REG))
7007 (use (reg:SI PIC_REG))
7009 "TARGET_SH2 && TARGET_FDPIC"
7011 return "braf %1" "\n"
7014 [(set_attr "needs_delay_slot" "yes")
7015 (set (attr "fp_mode")
7016 (if_then_else (eq_attr "fpu_single" "yes")
7017 (const_string "single") (const_string "double")))
7018 (set_attr "type" "jump_ind")])
7020 ;; sibcall_value_pcrel used to have a =&k clobber for the scratch register
7021 ;; that it needs for the branch address. This causes troubles when there
7022 ;; is a big overlap of argument and return value registers. Hence, use a
7023 ;; fixed call clobbered register for the address. See also PR 67260.
7024 (define_insn_and_split "sibcall_value_pcrel"
7025 [(set (match_operand 0 "" "=rf")
7026 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
7027 (match_operand 2 "" "")))
7028 (use (reg:SI FPSCR_MODES_REG))
7029 (clobber (reg:SI R1_REG))
7031 "TARGET_SH2 && !TARGET_FDPIC"
7036 rtx lab = PATTERN (gen_call_site ());
7039 operands[3] = gen_rtx_REG (SImode, R1_REG);
7041 sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
7042 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
7046 SIBLING_CALL_P (call_insn) = 1;
7049 [(set_attr "needs_delay_slot" "yes")
7050 (set (attr "fp_mode")
7051 (if_then_else (eq_attr "fpu_single" "yes")
7052 (const_string "single") (const_string "double")))
7053 (set_attr "type" "jump_ind")])
7055 ;; Like for sibcall_value_pcrel, use a fixed call clobbered register for
7056 ;; the branch address.
7057 (define_insn_and_split "sibcall_value_pcrel_fdpic"
7058 [(set (match_operand 0 "" "=rf")
7059 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand"))
7061 (use (reg:SI FPSCR_MODES_REG))
7062 (use (reg:SI PIC_REG))
7063 (clobber (reg:SI R1_REG))
7065 "TARGET_SH2 && TARGET_FDPIC"
7067 "&& reload_completed"
7070 rtx lab = PATTERN (gen_call_site ());
7072 operands[3] = gen_rtx_REG (SImode, R1_REG);
7074 sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
7075 rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
7079 SIBLING_CALL_P (i) = 1;
7082 [(set_attr "needs_delay_slot" "yes")
7083 (set (attr "fp_mode")
7084 (if_then_else (eq_attr "fpu_single" "yes")
7085 (const_string "single") (const_string "double")))
7086 (set_attr "type" "jump_ind")])
7088 (define_expand "sibcall_value"
7090 [(set (match_operand 0 "arith_reg_operand" "")
7091 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
7092 (match_operand 2 "" "")))
7093 (match_operand 3 "" "")
7094 (use (reg:SI FPSCR_MODES_REG))
7100 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7101 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7104 if (flag_pic && TARGET_SH2
7105 && MEM_P (operands[1])
7106 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7107 /* The PLT needs the PIC register, but the epilogue would have
7108 to restore it, so we can only use PC-relative PIC calls for
7109 static functions. */
7110 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
7113 emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0],
7114 XEXP (operands[1], 0),
7117 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
7118 XEXP (operands[1], 0),
7123 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
7127 operands[1] = sh_load_function_descriptor (operands[1]);
7128 emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1],
7132 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
7136 (define_expand "sibcall_epilogue"
7140 sh_expand_epilogue (true);
7144 (define_insn "indirect_jump_compact"
7146 (match_operand:SI 0 "arith_reg_operand" "r"))]
7149 [(set_attr "needs_delay_slot" "yes")
7150 (set_attr "type" "jump_ind")])
7152 (define_expand "indirect_jump"
7154 (match_operand 0 "register_operand" ""))]
7157 if (GET_MODE (operands[0]) != Pmode)
7158 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
7161 ;; The use of operand 1 / 2 helps us distinguish case table jumps
7162 ;; which can be present in structured code from indirect jumps which can not
7163 ;; be present in structured code. This allows -fprofile-arcs to work.
7165 ;; For SH1 processors.
7166 (define_insn "casesi_jump_1"
7168 (match_operand:SI 0 "register_operand" "r"))
7169 (use (label_ref (match_operand 1 "" "")))]
7172 [(set_attr "needs_delay_slot" "yes")
7173 (set_attr "type" "jump_ind")])
7175 ;; For all later processors.
7176 (define_insn "casesi_jump_2"
7177 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
7178 (label_ref (match_operand 1 "" ""))))
7179 (use (label_ref (match_operand 2 "" "")))]
7181 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
7183 [(set_attr "needs_delay_slot" "yes")
7184 (set_attr "type" "jump_ind")])
7186 ;; Call subroutine returning any type.
7187 ;; ??? This probably doesn't work.
7188 (define_expand "untyped_call"
7189 [(parallel [(call (match_operand 0 "" "")
7191 (match_operand 1 "" "")
7192 (match_operand 2 "" "")])]
7193 "TARGET_SH2E || TARGET_SH2A"
7195 /* RA does not know that the call sets the function value registers.
7196 We avoid problems by claiming that those registers are clobbered
7198 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7199 emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i)));
7201 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7203 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7205 rtx set = XVECEXP (operands[2], 0, i);
7206 emit_move_insn (SET_DEST (set), SET_SRC (set));
7209 /* The optimizer does not know that the call sets the function value
7210 registers we stored in the result block. We avoid problems by
7211 claiming that all hard registers are used and clobbered at this
7213 emit_insn (gen_blockage ());
7218 ;; ------------------------------------------------------------------------
7220 ;; ------------------------------------------------------------------------
7223 [(set (reg:SI T_REG)
7224 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
7225 (set (match_operand:SI 0 "arith_reg_dest" "=r")
7226 (plus:SI (match_dup 1) (const_int -1)))]
7229 [(set_attr "type" "arith")])
7236 ;; Load address of a label. This is only generated by the casesi expand,
7237 ;; and by machine_dependent_reorg (fixing up fp moves).
7238 ;; This must use unspec, because this only works for labels that are
7241 [(set (reg:SI R0_REG)
7242 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
7245 [(set_attr "in_delay_slot" "no")
7246 (set_attr "type" "arith")])
7248 ;; machine_dependent_reorg will make this a `mova'.
7249 (define_insn "mova_const"
7250 [(set (reg:SI R0_REG)
7251 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
7254 [(set_attr "in_delay_slot" "no")
7255 (set_attr "type" "arith")])
7257 ;; Loads of the GOTPC relocation values must not be optimized away
7258 ;; by e.g. any kind of CSE and must stay as they are. Although there
7259 ;; are other various ways to ensure this, we use an artificial counter
7260 ;; operand to generate unique symbols.
7261 (define_expand "GOTaddr2picreg"
7262 [(set (reg:SI R0_REG)
7263 (unspec:SI [(const:SI (unspec:SI [(match_dup 2)
7264 (match_operand:SI 0 "" "")]
7265 UNSPEC_PIC))] UNSPEC_MOVA))
7267 (const:SI (unspec:SI [(match_dup 2) (match_dup 0)] UNSPEC_PIC)))
7268 (set (match_dup 1) (plus:SI (match_dup 1) (reg:SI R0_REG)))]
7271 if (TARGET_VXWORKS_RTP)
7273 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
7274 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7275 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
7281 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7282 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7286 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7287 operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
7290 ;; A helper for GOTaddr2picreg to finish up the initialization of the
7292 (define_expand "vxworks_picreg"
7293 [(set (reg:SI PIC_REG)
7294 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
7295 (set (reg:SI R0_REG)
7296 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
7297 (set (reg:SI PIC_REG)
7298 (mem:SI (reg:SI PIC_REG)))
7299 (set (reg:SI PIC_REG)
7300 (mem:SI (plus:SI (reg:SI PIC_REG)
7302 "TARGET_VXWORKS_RTP")
7304 (define_expand "builtin_setjmp_receiver"
7305 [(match_operand 0 "" "")]
7308 emit_insn (gen_GOTaddr2picreg (const0_rtx));
7312 (define_expand "call_site"
7313 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
7316 static HOST_WIDE_INT i = 0;
7317 operands[0] = GEN_INT (i);
7321 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
7322 ;; in symGOT_load expand.
7323 (define_insn_and_split "chk_guard_add"
7324 [(set (match_operand:SI 0 "register_operand" "=&r")
7325 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
7330 "TARGET_SH1 && reload_completed"
7331 [(set (match_dup 0) (reg:SI PIC_REG))
7332 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
7334 [(set_attr "type" "arith")])
7336 (define_expand "sym_label2reg"
7337 [(set (match_operand:SI 0 "" "")
7338 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7339 (const (plus:SI (match_operand:SI 2 "" "")
7344 (define_expand "symPCREL_label2reg"
7345 [(set (match_operand:SI 0 "" "")
7348 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
7349 (const:SI (plus:SI (match_operand:SI 2 "" "")
7350 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
7354 (define_expand "symGOT_load"
7355 [(set (match_dup 2) (match_operand 1 "" ""))
7356 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
7357 (set (match_operand 0 "" "") (mem (match_dup 3)))]
7361 bool stack_chk_guard_p = false;
7363 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7364 : gen_rtx_REG (Pmode, PIC_REG);
7366 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7367 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7370 && flag_stack_protect
7371 && GET_CODE (operands[1]) == CONST
7372 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
7373 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
7374 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
7375 "__stack_chk_guard") == 0)
7376 stack_chk_guard_p = true;
7378 emit_move_insn (operands[2], operands[1]);
7380 /* When stack protector inserts codes after the result is set to
7381 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
7382 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
7383 when rX is a GOT address for the guard symbol. Ugly but doesn't
7384 matter because this is a rare situation. */
7385 if (stack_chk_guard_p)
7386 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
7388 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg));
7390 /* N.B. This is not constant for a GOTPLT relocation. */
7391 mem = gen_rtx_MEM (Pmode, operands[3]);
7392 MEM_NOTRAP_P (mem) = 1;
7393 /* ??? Should we have a special alias set for the GOT? */
7394 emit_move_insn (operands[0], mem);
7399 (define_expand "sym2GOT"
7400 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
7404 (define_expand "symGOT2reg"
7405 [(match_operand 0 "" "") (match_operand 1 "" "")]
7410 gotsym = gen_sym2GOT (operands[1]);
7411 PUT_MODE (gotsym, Pmode);
7412 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7414 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7419 (define_expand "sym2GOTFUNCDESC"
7420 [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))]
7423 (define_expand "symGOTFUNCDESC2reg"
7424 [(match_operand 0) (match_operand 1)]
7427 rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]);
7428 PUT_MODE (gotsym, Pmode);
7429 rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7431 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7436 (define_expand "symGOTPLT2reg"
7437 [(match_operand 0 "" "") (match_operand 1 "" "")]
7440 rtx pltsym = gen_rtx_CONST (Pmode,
7441 gen_rtx_UNSPEC (Pmode,
7442 gen_rtvec (1, operands[1]),
7444 emit_insn (gen_symGOT_load (operands[0], pltsym));
7448 (define_expand "sym2GOTOFF"
7449 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
7453 (define_expand "symGOTOFF2reg"
7454 [(match_operand 0 "" "") (match_operand 1 "" "")]
7457 rtx gotoffsym, insn;
7458 rtx t = (!can_create_pseudo_p ()
7460 : gen_reg_rtx (GET_MODE (operands[0])));
7462 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7463 : gen_rtx_REG (Pmode, PIC_REG);
7465 gotoffsym = gen_sym2GOTOFF (operands[1]);
7466 PUT_MODE (gotoffsym, Pmode);
7467 emit_move_insn (t, gotoffsym);
7468 insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7470 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7475 (define_expand "sym2GOTOFFFUNCDESC"
7476 [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))]
7479 (define_expand "symGOTOFFFUNCDESC2reg"
7480 [(match_operand 0) (match_operand 1)]
7483 rtx picreg = sh_get_fdpic_reg_initial_val ();
7484 rtx t = !can_create_pseudo_p ()
7486 : gen_reg_rtx (GET_MODE (operands[0]));
7488 rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]);
7489 PUT_MODE (gotoffsym, Pmode);
7490 emit_move_insn (t, gotoffsym);
7491 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7495 (define_expand "symPLT_label2reg"
7496 [(set (match_operand:SI 0 "" "")
7499 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
7500 (const:SI (plus:SI (match_operand:SI 2 "" "")
7501 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
7502 ;; Even though the PIC register is not really used by the call
7503 ;; sequence in which this is expanded, the PLT code assumes the PIC
7504 ;; register is set, so we must not skip its initialization. Since
7505 ;; we only use this expand as part of calling sequences, and never
7506 ;; to take the address of a function, this is the best point to
7507 ;; insert the (use). Using the PLT to take the address of a
7508 ;; function would be wrong, not only because the PLT entry could
7509 ;; then be called from a function that doesn't initialize the PIC
7510 ;; register to the proper GOT, but also because pointers to the
7511 ;; same function might not compare equal, should they be set by
7512 ;; different shared libraries.
7513 (use (reg:SI PIC_REG))]
7517 (define_expand "sym2PIC"
7518 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
7522 ;; -------------------------------------------------------------------------
7523 ;; TLS code generation.
7525 ;; FIXME: The multi-insn asm blocks should be converted to use
7526 ;; define_insn_and_split.
7527 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
7528 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
7531 (define_insn "tls_global_dynamic"
7532 [(set (match_operand:SI 0 "register_operand" "=&z")
7533 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7536 (use (reg:SI FPSCR_MODES_REG))
7537 (use (reg:SI PIC_REG))
7538 (clobber (reg:SI PR_REG))
7539 (clobber (scratch:SI))]
7542 return "mov.l 1f,r4" "\n"
7551 "1: .long %a1@TLSGD" "\n"
7552 "2: .long __tls_get_addr@PLT" "\n"
7555 [(set_attr "type" "tls_load")
7556 (set_attr "length" "26")])
7558 (define_insn "tls_local_dynamic"
7559 [(set (match_operand:SI 0 "register_operand" "=&z")
7560 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7563 (use (reg:SI FPSCR_MODES_REG))
7564 (use (reg:SI PIC_REG))
7565 (clobber (reg:SI PR_REG))
7566 (clobber (scratch:SI))]
7569 return "mov.l 1f,r4" "\n"
7578 "1: .long %a1@TLSLDM" "\n"
7579 "2: .long __tls_get_addr@PLT" "\n"
7582 [(set_attr "type" "tls_load")
7583 (set_attr "length" "26")])
7585 (define_expand "sym2DTPOFF"
7586 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
7590 (define_expand "symDTPOFF2reg"
7591 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
7595 rtx t = (!can_create_pseudo_p ()
7597 : gen_reg_rtx (GET_MODE (operands[0])));
7599 dtpoffsym = gen_sym2DTPOFF (operands[1]);
7600 PUT_MODE (dtpoffsym, Pmode);
7601 emit_move_insn (t, dtpoffsym);
7602 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
7606 (define_expand "sym2GOTTPOFF"
7607 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
7611 (define_insn "tls_initial_exec"
7612 [(set (match_operand:SI 0 "register_operand" "=&r")
7613 (unspec:SI [(match_operand:SI 1 "" "")]
7615 (use (reg:SI GBR_REG))
7616 (use (reg:SI PIC_REG))
7617 (clobber (reg:SI R0_REG))]
7620 return "mov.l 1f,r0" "\n"
7622 " mov.l @(r0,r12),r0" "\n"
7629 [(set_attr "type" "tls_load")
7630 (set_attr "length" "16")])
7632 (define_expand "sym2TPOFF"
7633 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
7637 (define_expand "symTPOFF2reg"
7638 [(match_operand 0 "" "") (match_operand 1 "" "")]
7643 tpoffsym = gen_sym2TPOFF (operands[1]);
7644 PUT_MODE (tpoffsym, Pmode);
7645 emit_move_insn (operands[0], tpoffsym);
7649 ;;------------------------------------------------------------------------------
7650 ;; Thread pointer getter and setter.
7652 ;; On SH the thread pointer is kept in the GBR.
7653 ;; These patterns are usually expanded from the respective built-in functions.
7654 (define_expand "get_thread_pointersi"
7655 [(set (match_operand:SI 0 "arith_reg_dest") (reg:SI GBR_REG))]
7658 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
7659 (define_insn "store_gbr"
7660 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (reg:SI GBR_REG))]
7663 [(set_attr "type" "tls_load")])
7665 (define_expand "set_thread_pointersi"
7666 [(set (reg:SI GBR_REG)
7667 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand")]
7671 (define_insn "load_gbr"
7672 [(set (reg:SI GBR_REG)
7673 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand" "r")]
7677 [(set_attr "type" "move")])
7679 ;;------------------------------------------------------------------------------
7680 ;; Thread pointer relative memory loads and stores.
7682 ;; On SH there are GBR displacement address modes which can be utilized to
7683 ;; access memory behind the thread pointer.
7684 ;; Since we do not allow using GBR for general purpose memory accesses, these
7685 ;; GBR addressing modes are formed by the combine pass.
7686 ;; This could be done with fewer patterns than below by using a mem predicate
7687 ;; for the GBR mem, but then reload would try to reload addresses with a
7688 ;; zero displacement for some strange reason.
7690 (define_insn "*mov<mode>_gbr_load"
7691 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7692 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7693 (match_operand:QIHISI 1 "gbr_displacement"))))]
7695 "mov.<bwl> @(%O1,gbr),%0"
7696 [(set_attr "type" "load")])
7698 (define_insn "*mov<mode>_gbr_load"
7699 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7700 (mem:QIHISI (reg:SI GBR_REG)))]
7702 "mov.<bwl> @(0,gbr),%0"
7703 [(set_attr "type" "load")])
7705 (define_insn "*mov<mode>_gbr_load"
7706 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7708 (mem:QIHI (plus:SI (reg:SI GBR_REG)
7709 (match_operand:QIHI 1 "gbr_displacement")))))]
7711 "mov.<bw> @(%O1,gbr),%0"
7712 [(set_attr "type" "load")])
7714 (define_insn "*mov<mode>_gbr_load"
7715 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7716 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
7718 "mov.<bw> @(0,gbr),%0"
7719 [(set_attr "type" "load")])
7721 (define_insn "*mov<mode>_gbr_store"
7722 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7723 (match_operand:QIHISI 0 "gbr_displacement")))
7724 (match_operand:QIHISI 1 "register_operand" "z"))]
7726 "mov.<bwl> %1,@(%O0,gbr)"
7727 [(set_attr "type" "store")])
7729 (define_insn "*mov<mode>_gbr_store"
7730 [(set (mem:QIHISI (reg:SI GBR_REG))
7731 (match_operand:QIHISI 0 "register_operand" "z"))]
7733 "mov.<bwl> %0,@(0,gbr)"
7734 [(set_attr "type" "store")])
7736 ;; DImode memory accesses have to be split in two SImode accesses.
7737 ;; Split them before reload, so that it gets a better chance to figure out
7738 ;; how to deal with the R0 restriction for the individual SImode accesses.
7739 ;; Do not match this insn during or after reload because it can't be split
7741 (define_insn_and_split "*movdi_gbr_load"
7742 [(set (match_operand:DI 0 "arith_reg_dest")
7743 (match_operand:DI 1 "gbr_address_mem"))]
7744 "TARGET_SH1 && can_create_pseudo_p ()"
7747 [(set (match_dup 3) (match_dup 5))
7748 (set (match_dup 4) (match_dup 6))]
7750 /* Swap low/high part load order on little endian, so that the result reg
7751 of the second load can be used better. */
7752 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
7753 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7754 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7755 operands[4 - off] = gen_highpart (SImode, operands[0]);
7756 operands[6 - off] = gen_highpart (SImode, operands[1]);
7759 (define_insn_and_split "*movdi_gbr_store"
7760 [(set (match_operand:DI 0 "gbr_address_mem")
7761 (match_operand:DI 1 "register_operand"))]
7762 "TARGET_SH1 && can_create_pseudo_p ()"
7765 [(set (match_dup 3) (match_dup 5))
7766 (set (match_dup 4) (match_dup 6))]
7768 /* Swap low/high part store order on big endian, so that stores of function
7769 call results can save a reg copy. */
7770 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
7771 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7772 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7773 operands[4 - off] = gen_highpart (SImode, operands[0]);
7774 operands[6 - off] = gen_highpart (SImode, operands[1]);
7777 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
7778 ;; in particular when the displacements are in the range of the regular move
7779 ;; insns. Thus, in the first split pass after the combine pass we search
7780 ;; for missed opportunities and try to fix them up ourselves.
7781 ;; If an equivalent GBR address can be determined the load / store is split
7782 ;; into one of the GBR load / store patterns.
7783 ;; All of that must happen before reload (GBR address modes use R0 as the
7784 ;; other operand) and there's no point of doing it if the GBR is not
7785 ;; referenced in a function at all.
7787 [(set (match_operand:QIHISIDI 0 "register_operand")
7788 (match_operand:QIHISIDI 1 "memory_operand"))]
7789 "TARGET_SH1 && !reload_in_progress && !reload_completed
7790 && df_regs_ever_live_p (GBR_REG)"
7791 [(set (match_dup 0) (match_dup 1))]
7793 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7794 if (gbr_mem != NULL_RTX)
7795 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7801 [(set (match_operand:SI 0 "register_operand")
7802 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7803 "TARGET_SH1 && !reload_in_progress && !reload_completed
7804 && df_regs_ever_live_p (GBR_REG)"
7805 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
7807 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7808 if (gbr_mem != NULL_RTX)
7809 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7814 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
7815 ;; Split those so that a GBR load can be used.
7817 [(set (match_operand:SI 0 "register_operand")
7818 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7819 "TARGET_SH2A && !reload_in_progress && !reload_completed
7820 && df_regs_ever_live_p (GBR_REG)"
7821 [(set (match_dup 2) (match_dup 1))
7822 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
7824 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7825 if (gbr_mem != NULL_RTX)
7827 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
7828 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7835 [(set (match_operand:QIHISIDI 0 "memory_operand")
7836 (match_operand:QIHISIDI 1 "register_operand"))]
7837 "TARGET_SH1 && !reload_in_progress && !reload_completed
7838 && df_regs_ever_live_p (GBR_REG)"
7839 [(set (match_dup 0) (match_dup 1))]
7841 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
7842 if (gbr_mem != NULL_RTX)
7843 operands[0] = replace_equiv_address (operands[0], gbr_mem);
7848 ;;------------------------------------------------------------------------------
7849 ;; case instruction for switch statements.
7851 ;; operand 0 is index
7852 ;; operand 1 is the minimum bound
7853 ;; operand 2 is the maximum bound - minimum bound + 1
7854 ;; operand 3 is CODE_LABEL for the table;
7855 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7856 (define_expand "casesi"
7857 [(match_operand:SI 0 "arith_reg_operand" "")
7858 (match_operand:SI 1 "arith_reg_operand" "")
7859 (match_operand:SI 2 "arith_reg_operand" "")
7860 (match_operand 3 "" "") (match_operand 4 "" "")]
7863 rtx reg = gen_reg_rtx (SImode);
7864 rtx reg2 = gen_reg_rtx (SImode);
7866 operands[1] = copy_to_mode_reg (SImode, operands[1]);
7867 operands[2] = copy_to_mode_reg (SImode, operands[2]);
7868 /* If optimizing, casesi_worker depends on the mode of the instruction
7869 before label it 'uses' - operands[3]. */
7870 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
7872 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
7874 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
7876 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
7877 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
7878 operands[3], but to lab. We will fix this up in
7879 machine_dependent_reorg. */
7884 (define_expand "casesi_0"
7885 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
7886 (set (match_dup 4) (minus:SI (match_dup 4)
7887 (match_operand:SI 1 "arith_operand" "")))
7889 (gtu:SI (match_dup 4)
7890 (match_operand:SI 2 "arith_reg_operand" "")))
7892 (if_then_else (ne (reg:SI T_REG)
7894 (label_ref (match_operand 3 "" ""))
7899 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
7900 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
7901 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
7903 ;; The use on the T_REG in the casesi_worker* patterns links the bounds
7904 ;; checking insns and the table memory access. See also PR 69713.
7905 (define_insn "casesi_worker_0"
7906 [(set (match_operand:SI 0 "register_operand" "=r,r")
7907 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
7908 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7909 (clobber (match_scratch:SI 3 "=X,1"))
7910 (clobber (match_scratch:SI 4 "=&z,z"))
7911 (use (reg:SI T_REG))]
7916 [(set (match_operand:SI 0 "register_operand" "")
7917 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7918 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7919 (clobber (match_scratch:SI 3 ""))
7920 (clobber (match_scratch:SI 4))
7921 (use (reg:SI T_REG))]
7922 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
7923 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7924 (parallel [(set (match_dup 0)
7925 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7926 (label_ref (match_dup 2))] UNSPEC_CASESI))
7927 (clobber (match_dup 3))])
7928 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
7930 if (GET_CODE (operands[2]) == CODE_LABEL)
7931 LABEL_NUSES (operands[2])++;
7935 [(set (match_operand:SI 0 "register_operand" "")
7936 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7937 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7938 (clobber (match_scratch:SI 3 ""))
7939 (clobber (match_scratch:SI 4))
7940 (use (reg:SI T_REG))]
7941 "TARGET_SH2 && reload_completed"
7942 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7943 (parallel [(set (match_dup 0)
7944 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7945 (label_ref (match_dup 2))] UNSPEC_CASESI))
7946 (clobber (match_dup 3))])]
7948 if (GET_CODE (operands[2]) == CODE_LABEL)
7949 LABEL_NUSES (operands[2])++;
7952 ;; This may be replaced with casesi_worker_2 in sh_reorg for PIC.
7953 ;; The insn length is set to 8 for that case.
7954 (define_insn "casesi_worker_1"
7955 [(set (match_operand:SI 0 "register_operand" "=r,r")
7956 (unspec:SI [(reg:SI R0_REG)
7957 (match_operand:SI 1 "register_operand" "0,r")
7958 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7959 (clobber (match_scratch:SI 3 "=X,1"))]
7962 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
7964 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
7966 switch (GET_MODE (diff_vec))
7969 return "shll2 %1" "\n"
7970 " mov.l @(r0,%1),%0";
7972 return "add %1,%1" "\n"
7973 " mov.w @(r0,%1),%0";
7975 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7976 return "mov.b @(r0,%1),%0" "\n"
7979 return "mov.b @(r0,%1),%0";
7985 [(set_attr_alternative "length"
7986 [(if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))
7987 (if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))])])
7989 (define_insn "casesi_worker_2"
7990 [(set (match_operand:SI 0 "register_operand" "=r,r")
7991 (unspec:SI [(reg:SI R0_REG)
7992 (match_operand:SI 1 "register_operand" "0,r")
7993 (label_ref (match_operand 2 "" ""))
7994 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
7995 (clobber (match_operand:SI 4 "" "=X,1"))]
7996 "TARGET_SH2 && reload_completed && flag_pic"
7998 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
7999 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
8001 switch (GET_MODE (diff_vec))
8004 return "shll2 %1" "\n"
8007 " mov.l @(r0,%1),%0";
8009 return "add %1,%1" "\n"
8012 " mov.w @(r0,%1),%0";
8014 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
8015 return "add r0,%1" "\n"
8017 " mov.b @(r0,%1),%0" "\n"
8020 return "add r0,%1" "\n"
8022 " mov.b @(r0,%1),%0";
8027 [(set_attr "length" "8")])
8029 (define_expand "simple_return"
8031 "sh_can_use_simple_return_p ()")
8033 (define_expand "return"
8035 "reload_completed && epilogue_completed")
8037 (define_insn "*<code>_i"
8041 && ! sh_cfun_trap_exit_p ()"
8043 if (TARGET_SH2A && (dbr_sequence_length () == 0)
8044 && !current_function_interrupt)
8049 [(set_attr "type" "return")
8050 (set_attr "needs_delay_slot" "yes")])
8052 ;; trapa has no delay slot.
8053 (define_insn "*return_trapa"
8055 "TARGET_SH1 && reload_completed"
8057 [(set_attr "type" "return")])
8059 (define_expand "prologue"
8063 sh_expand_prologue ();
8067 (define_expand "epilogue"
8071 sh_expand_epilogue (false);
8074 (define_expand "eh_return"
8075 [(use (match_operand 0 "register_operand" ""))]
8078 emit_insn (gen_eh_set_ra_si (operands[0]));
8082 ;; Clobber the return address on the stack. We can't expand this
8083 ;; until we know where it will be put in the stack frame.
8085 (define_insn "eh_set_ra_si"
8086 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
8088 (clobber (match_scratch:SI 1 "=&r"))]
8093 [(unspec_volatile [(match_operand 0 "register_operand" "")]
8095 (clobber (match_scratch 1 ""))]
8099 sh_set_return_address (operands[0], operands[1]);
8103 (define_insn "blockage"
8104 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8107 [(set_attr "length" "0")])
8109 ;; Define movml instructions for SH2A target. Currently they are
8110 ;; used to push and pop all banked registers only.
8112 (define_insn "movml_push_banked"
8113 [(set (match_operand:SI 0 "register_operand" "=r")
8114 (plus (match_dup 0) (const_int -32)))
8115 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
8116 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
8117 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
8118 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
8119 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
8120 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
8121 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
8122 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
8123 "TARGET_SH2A && REGNO (operands[0]) == 15"
8125 [(set_attr "in_delay_slot" "no")])
8127 (define_insn "movml_pop_banked"
8128 [(set (match_operand:SI 0 "register_operand" "=r")
8129 (plus (match_dup 0) (const_int 32)))
8130 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
8131 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
8132 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
8133 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
8134 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
8135 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
8136 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
8137 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
8138 "TARGET_SH2A && REGNO (operands[0]) == 15"
8140 [(set_attr "in_delay_slot" "no")])
8142 ;; ------------------------------------------------------------------------
8144 ;; ------------------------------------------------------------------------
8147 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8148 (match_operand:SI 1 "t_reg_operand"))]
8151 [(set_attr "type" "arith")])
8153 (define_insn "movrt"
8154 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8155 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8158 [(set_attr "type" "arith")])
8160 (define_expand "cstoresi4"
8161 [(set (match_operand:SI 0 "register_operand")
8162 (match_operator:SI 1 "comparison_operator"
8163 [(match_operand:SI 2 "cmpsi_operand")
8164 (match_operand:SI 3 "arith_operand")]))]
8167 if (sh_expand_t_scc (operands))
8170 if (! currently_expanding_to_rtl)
8173 sh_emit_compare_and_set (operands, SImode);
8177 (define_expand "cstoredi4"
8178 [(set (match_operand:SI 0 "register_operand")
8179 (match_operator:SI 1 "comparison_operator"
8180 [(match_operand:DI 2 "arith_operand")
8181 (match_operand:DI 3 "arith_operand")]))]
8184 if (sh_expand_t_scc (operands))
8187 if (! currently_expanding_to_rtl)
8190 sh_emit_compare_and_set (operands, DImode);
8194 ;; Move the complement of the T reg to a reg.
8195 ;; On SH2A the movrt insn can be used.
8196 ;; On anything else than SH2A this has to be done with multiple instructions.
8197 ;; One obvious way would be:
8202 ;; However, this puts pressure on r0 in most cases and thus the following is
8208 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
8209 ;; becomes a one instruction operation. Moreover, care must be taken that
8210 ;; the insn can still be combined with inverted compare and branch code
8211 ;; around it. On the other hand, if a function returns the complement of
8212 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
8213 ;; lead to better code.
8214 (define_expand "movnegt"
8215 [(set (match_operand:SI 0 "arith_reg_dest" "")
8216 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8220 emit_insn (gen_movrt (operands[0], operands[1]));
8223 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
8224 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
8229 (define_insn_and_split "movrt_negc"
8230 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8231 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8232 (set (reg:SI T_REG) (const_int 1))
8233 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
8236 "&& !sh_in_recog_treg_set_expr ()"
8239 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8244 [(set_attr "type" "arith")])
8246 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
8247 ;; pattern can be used by the combine pass. Using a scratch reg for the
8248 ;; -1 constant results in slightly better register allocations compared to
8249 ;; generating a pseudo reg before reload.
8250 (define_insn_and_split "*movrt_negc"
8251 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8252 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8253 (clobber (match_scratch:SI 2 "=r"))
8254 (clobber (reg:SI T_REG))]
8255 "TARGET_SH1 && ! TARGET_SH2A"
8257 "&& !sh_in_recog_treg_set_expr ()"
8260 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8262 else if (reload_completed)
8264 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
8265 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
8272 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
8273 ;; clobber the T bit, which is useful when storing the T bit and the
8274 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
8275 ;; Usually we don't want this insn to be matched, except for cases where the
8276 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
8277 (define_insn_and_split "movrt_xor"
8278 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
8279 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8280 (use (reg:SI T_REG))]
8283 "&& reload_completed"
8284 [(set (match_dup 0) (reg:SI T_REG))
8285 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
8288 ;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T
8290 ;; Notice that 0 - 0x80000000 = 0x80000000.
8292 ;; Single bit tests are usually done with zero_extract. On non-SH2A this
8293 ;; will use a tst-negc sequence. On SH2A it will use a bld-addc sequence.
8294 ;; The zeroth bit requires a special pattern, otherwise we get a shlr-addc.
8295 ;; This is a special case of the generic treg_set_expr pattern and thus has
8296 ;; to come first or it will never match.
8297 (define_insn_and_split "*mov_t_msb_neg"
8298 [(set (match_operand:SI 0 "arith_reg_dest")
8299 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
8301 (const_int 2147483647)))
8302 (clobber (reg:SI T_REG))]
8305 "&& can_create_pseudo_p ()"
8306 [(parallel [(set (match_dup 0)
8307 (plus:SI (zero_extract:SI (match_dup 1)
8308 (const_int 1) (const_int 0))
8309 (const_int 2147483647)))
8310 (clobber (reg:SI T_REG))])])
8312 (define_insn_and_split "*mov_t_msb_neg"
8313 [(set (match_operand:SI 0 "arith_reg_dest")
8314 (plus:SI (match_operand 1 "treg_set_expr")
8315 (const_int 2147483647))) ;; 0x7fffffff
8316 (clobber (reg:SI T_REG))]
8319 "&& can_create_pseudo_p ()"
8322 if (negt_reg_operand (operands[1], VOIDmode))
8324 emit_insn (gen_negc (operands[0],
8325 force_reg (SImode, GEN_INT (-2147483648LL))));
8329 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8330 if (ti.remove_trailing_nott ())
8331 emit_insn (gen_negc (operands[0],
8332 force_reg (SImode, GEN_INT (-2147483648LL))));
8334 emit_insn (gen_addc (operands[0],
8335 force_reg (SImode, const0_rtx),
8336 force_reg (SImode, GEN_INT (2147483647))));
8340 (define_insn_and_split "*mov_t_msb_neg"
8341 [(set (match_operand:SI 0 "arith_reg_dest")
8342 (if_then_else:SI (match_operand 1 "treg_set_expr")
8343 (match_operand 2 "const_int_operand")
8344 (match_operand 3 "const_int_operand")))
8345 (clobber (reg:SI T_REG))]
8346 "TARGET_SH1 && can_create_pseudo_p ()
8347 && ((INTVAL (operands[2]) == -2147483648LL
8348 && INTVAL (operands[3]) == 2147483647LL)
8349 || (INTVAL (operands[2]) == 2147483647LL
8350 && INTVAL (operands[3]) == -2147483648LL))"
8355 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8357 if (INTVAL (operands[2]) == -2147483648LL)
8359 if (ti.remove_trailing_nott ())
8360 emit_insn (gen_negc (operands[0],
8361 force_reg (SImode, GEN_INT (-2147483648LL))));
8363 emit_insn (gen_addc (operands[0],
8364 force_reg (SImode, const0_rtx),
8365 force_reg (SImode, operands[3])));
8368 else if (INTVAL (operands[2]) == 2147483647LL)
8370 if (ti.remove_trailing_nott ())
8371 emit_insn (gen_addc (operands[0],
8372 force_reg (SImode, const0_rtx),
8373 force_reg (SImode, GEN_INT (2147483647LL))));
8375 emit_insn (gen_negc (operands[0],
8376 force_reg (SImode, GEN_INT (-2147483648LL))));
8383 ;; Store (negated) T bit as all zeros or ones in a reg.
8384 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
8385 ;; not Rn,Rn ! Rn = 0 - Rn
8386 (define_insn_and_split "mov_neg_si_t"
8387 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8388 (neg:SI (match_operand 1 "treg_set_expr")))]
8391 gcc_assert (t_reg_operand (operands[1], VOIDmode));
8392 return "subc %0,%0";
8394 "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
8397 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8398 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
8400 if (ti.remove_trailing_nott ())
8401 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
8405 [(set_attr "type" "arith")])
8407 ;; Invert the T bit.
8408 ;; On SH2A we can use the nott insn. On anything else this must be done with
8409 ;; multiple insns like:
8412 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
8413 ;; pass will look for this insn. Disallow using it if pseudos can't be
8415 ;; Don't split the nott inside the splitting of a treg_set_expr, or else
8416 ;; surrounding insns might not see and recombine it. Defer the splitting
8417 ;; of the nott until after the whole insn containing the treg_set_expr
8419 (define_insn_and_split "nott"
8420 [(set (reg:SI T_REG)
8421 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
8422 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
8424 gcc_assert (TARGET_SH2A);
8427 "!TARGET_SH2A && can_create_pseudo_p () && !sh_in_recog_treg_set_expr ()"
8428 [(set (match_dup 0) (reg:SI T_REG))
8429 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
8431 operands[0] = gen_reg_rtx (SImode);
8434 ;; Store T bit as MSB in a reg.
8435 ;; T = 0: 0x00000000 -> reg
8436 ;; T = 1: 0x80000000 -> reg
8437 (define_insn_and_split "*movt_msb"
8438 [(set (match_operand:SI 0 "arith_reg_dest")
8439 (mult:SI (match_operand:SI 1 "t_reg_operand")
8440 (const_int -2147483648))) ;; 0xffffffff80000000
8441 (clobber (reg:SI T_REG))]
8445 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
8447 ;; Store inverted T bit as MSB in a reg.
8448 ;; T = 0: 0x80000000 -> reg
8449 ;; T = 1: 0x00000000 -> reg
8450 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
8451 ;; On non SH2A we resort to the following sequence:
8455 ;; The T bit value will be modified during the sequence, but the rotcr insn
8456 ;; will restore its original value.
8457 (define_insn_and_split "*negt_msb"
8458 [(set (match_operand:SI 0 "arith_reg_dest")
8459 (match_operand:SI 1 "negt_reg_shl31_operand"))]
8462 "&& can_create_pseudo_p ()"
8465 rtx tmp = gen_reg_rtx (SImode);
8469 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
8470 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
8474 emit_move_insn (tmp, get_t_reg_rtx ());
8475 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
8476 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
8481 ;; The *cset_zero patterns convert optimizations such as
8482 ;; "if (test) x = 0;"
8484 ;; "x &= -(test == 0);"
8485 ;; back to conditional branch sequences if zero-displacement branches
8487 ;; FIXME: These patterns can be removed when conditional execution patterns
8488 ;; are implemented, since ifcvt will not perform these optimizations if
8489 ;; conditional execution is supported.
8490 (define_insn "*cset_zero"
8491 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8492 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
8494 (match_operand:SI 2 "arith_reg_operand" "0")))]
8495 "TARGET_SH1 && TARGET_ZDCBRANCH"
8501 [(set_attr "type" "arith") ;; poor approximation
8502 (set_attr "length" "4")])
8504 (define_insn "*cset_zero"
8505 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8506 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
8507 (match_operand:SI 2 "arith_reg_operand" "0")
8509 "TARGET_SH1 && TARGET_ZDCBRANCH"
8511 int tval = sh_eval_treg_value (operands[1]);
8516 else if (tval == false)
8523 [(set_attr "type" "arith") ;; poor approximation
8524 (set_attr "length" "4")])
8526 (define_expand "cstoresf4"
8527 [(set (match_operand:SI 0 "register_operand")
8528 (match_operator:SI 1 "ordered_comparison_operator"
8529 [(match_operand:SF 2 "arith_operand")
8530 (match_operand:SF 3 "arith_operand")]))]
8533 if (! currently_expanding_to_rtl)
8536 sh_emit_compare_and_set (operands, SFmode);
8540 (define_expand "cstoredf4"
8541 [(set (match_operand:SI 0 "register_operand")
8542 (match_operator:SI 1 "ordered_comparison_operator"
8543 [(match_operand:DF 2 "arith_operand")
8544 (match_operand:DF 3 "arith_operand")]))]
8547 if (! currently_expanding_to_rtl)
8550 sh_emit_compare_and_set (operands, DFmode);
8554 ;; Sometimes the T bit result of insns is needed in normal registers.
8555 ;; Instead of open coding all the pattern variations, use the treg_set_expr
8556 ;; predicate to match any T bit output insn and split it out after.
8557 ;; This pattern should be below all other related patterns so that it is
8558 ;; considered as a last resort option during matching. This allows
8559 ;; overriding it with special case patterns.
8560 (define_insn_and_split "any_treg_expr_to_reg"
8561 [(set (match_operand:SI 0 "arith_reg_dest")
8562 (match_operand 1 "treg_set_expr"))
8563 (clobber (reg:SI T_REG))]
8564 "TARGET_SH1 && can_create_pseudo_p ()"
8566 "&& !sh_in_recog_treg_set_expr ()"
8570 fprintf (dump_file, "splitting any_treg_expr_to_reg\n");
8572 if (t_reg_operand (operands[1], VOIDmode))
8575 fprintf (dump_file, "t_reg_operand: emitting movt\n");
8576 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8579 if (negt_reg_operand (operands[1], VOIDmode))
8582 fprintf (dump_file, "negt_reg_operand: emitting movrt\n");
8583 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8587 /* If the split out insns ended with a nott, emit a movrt sequence,
8588 otherwise a normal movt. */
8589 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8591 if (ti.remove_trailing_nott ())
8593 /* Emit this same insn_and_split again. However, the next time it
8594 is split, it will emit the actual negc/movrt insn. This gives
8595 other surrounding insns the chance to see the trailing movrt. */
8598 "any_treg_expr_to_reg: replacing trailing nott with movrt\n");
8599 i = emit_insn (gen_any_treg_expr_to_reg (
8600 operands[0], gen_rtx_XOR (SImode, get_t_reg_rtx (),
8605 i = emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8607 fprintf (dump_file, "any_treg_expr_to_reg: appending movt\n");
8610 add_reg_note (i, REG_UNUSED, get_t_reg_rtx ());
8614 ;; -------------------------------------------------------------------------
8615 ;; Instructions to cope with inline literal tables
8616 ;; -------------------------------------------------------------------------
8618 ;; 2 byte integer in line
8619 (define_insn "consttable_2"
8620 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8621 (match_operand 1 "" "")]
8625 if (operands[1] != const0_rtx)
8626 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
8629 [(set_attr "length" "2")
8630 (set_attr "in_delay_slot" "no")])
8632 ;; 4 byte integer in line
8633 (define_insn "consttable_4"
8634 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8635 (match_operand 1 "" "")]
8639 if (operands[1] != const0_rtx)
8641 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
8642 mark_symbol_refs_as_used (operands[0]);
8646 [(set_attr "length" "4")
8647 (set_attr "in_delay_slot" "no")])
8649 ;; 8 byte integer in line
8650 (define_insn "consttable_8"
8651 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8652 (match_operand 1 "" "")]
8656 if (operands[1] != const0_rtx)
8657 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
8660 [(set_attr "length" "8")
8661 (set_attr "in_delay_slot" "no")])
8663 ;; 4 byte floating point
8664 (define_insn "consttable_sf"
8665 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
8666 (match_operand 1 "" "")]
8670 if (operands[1] != const0_rtx)
8671 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8672 SFmode, GET_MODE_ALIGNMENT (SFmode));
8675 [(set_attr "length" "4")
8676 (set_attr "in_delay_slot" "no")])
8678 ;; 8 byte floating point
8679 (define_insn "consttable_df"
8680 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
8681 (match_operand 1 "" "")]
8685 if (operands[1] != const0_rtx)
8686 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8687 DFmode, GET_MODE_ALIGNMENT (DFmode));
8690 [(set_attr "length" "8")
8691 (set_attr "in_delay_slot" "no")])
8693 ;; Alignment is needed for some constant tables; it may also be added for
8694 ;; Instructions at the start of loops, or after unconditional branches.
8695 ;; ??? We would get more accurate lengths if we did instruction
8696 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
8697 ;; here is too conservative.
8699 ;; align to a two byte boundary
8700 (define_expand "align_2"
8701 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
8705 ;; Align to a four byte boundary.
8706 ;; align_4 and align_log are instructions for the starts of loops, or
8707 ;; after unconditional branches, which may take up extra room.
8708 (define_expand "align_4"
8709 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
8713 ;; Align to a cache line boundary.
8714 (define_insn "align_log"
8715 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
8718 [(set_attr "length" "0")
8719 (set_attr "in_delay_slot" "no")])
8721 ;; Emitted at the end of the literal table, used to emit the
8722 ;; 32bit branch labels if needed.
8723 (define_insn "consttable_end"
8724 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
8727 return output_jump_label_table ();
8729 [(set_attr "in_delay_slot" "no")])
8731 ;; Emitted at the end of the window in the literal table.
8732 (define_insn "consttable_window_end"
8733 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
8736 [(set_attr "length" "0")
8737 (set_attr "in_delay_slot" "no")])
8739 ;; -------------------------------------------------------------------------
8740 ;; Minimum / maximum operations.
8741 ;; -------------------------------------------------------------------------
8743 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
8744 ;; and smax standard name patterns are defined, they will be used during
8745 ;; initial expansion and combine will then be able to form the actual min-max
8747 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
8748 ;; clipped, but there is currently no way of making use of this information.
8749 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8750 (define_expand "<code>si3"
8751 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
8752 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8753 (match_operand 2 "const_int_operand")))
8754 (clobber (reg:SI T_REG))])]
8757 /* Force the comparison value into a register, because greater-than
8758 comparisons can work only on registers. Combine will be able to pick up
8759 the constant value from the REG_EQUAL note when trying to form a min-max
8761 operands[2] = force_reg (SImode, operands[2]);
8765 ;; smax (smin (...))
8767 ;; smin (smax (...))
8768 (define_insn_and_split "*clips"
8769 [(set (match_operand:SI 0 "arith_reg_dest")
8770 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
8771 (match_operand 2 "clips_max_const_int"))
8772 (match_operand 3 "clips_min_const_int")))]
8777 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
8779 (define_insn "*clips"
8780 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8781 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
8782 (match_operand 2 "clips_min_const_int"))
8783 (match_operand 3 "clips_max_const_int")))]
8786 if (INTVAL (operands[3]) == 127)
8787 return "clips.b %0";
8788 else if (INTVAL (operands[3]) == 32767)
8789 return "clips.w %0";
8793 [(set_attr "type" "arith")])
8795 ;; If the expanded smin or smax patterns were not combined, split them into
8796 ;; a compare and branch sequence, because there are no real smin or smax
8798 (define_insn_and_split "*<code>si3"
8799 [(set (match_operand:SI 0 "arith_reg_dest")
8800 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8801 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
8802 (clobber (reg:SI T_REG))]
8803 "TARGET_SH2A && can_create_pseudo_p ()"
8808 rtx skip_label = gen_label_rtx ();
8809 emit_move_insn (operands[0], operands[1]);
8811 rtx cmp_val = operands[2];
8812 if (satisfies_constraint_M (cmp_val))
8813 cmp_val = const0_rtx;
8815 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
8816 emit_jump_insn (<CODE> == SMIN
8817 ? gen_branch_false (skip_label)
8818 : gen_branch_true (skip_label));
8820 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
8824 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
8825 ;; with a register and a constant.
8826 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
8827 ;; clipped, but there is currently no way of making use of this information.
8828 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8829 (define_expand "uminsi3"
8830 [(set (match_operand:SI 0 "arith_reg_dest")
8831 (umin:SI (match_operand:SI 1 "arith_reg_operand")
8832 (match_operand 2 "const_int_operand")))]
8835 if (INTVAL (operands[2]) == 1)
8837 emit_insn (gen_clipu_one (operands[0], operands[1]));
8840 else if (! clipu_max_const_int (operands[2], VOIDmode))
8844 (define_insn "*clipu"
8845 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8846 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
8847 (match_operand 2 "clipu_max_const_int")))]
8850 if (INTVAL (operands[2]) == 255)
8851 return "clipu.b %0";
8852 else if (INTVAL (operands[2]) == 65535)
8853 return "clipu.w %0";
8857 [(set_attr "type" "arith")])
8859 (define_insn_and_split "clipu_one"
8860 [(set (match_operand:SI 0 "arith_reg_dest")
8861 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
8862 (clobber (reg:SI T_REG))]
8865 "&& can_create_pseudo_p ()"
8868 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
8869 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8873 ;; -------------------------------------------------------------------------
8875 ;; -------------------------------------------------------------------------
8877 ;; String/block move insn.
8879 (define_expand "movmemsi"
8880 [(parallel [(set (mem:BLK (match_operand:BLK 0))
8881 (mem:BLK (match_operand:BLK 1)))
8882 (use (match_operand:SI 2 "nonmemory_operand"))
8883 (use (match_operand:SI 3 "immediate_operand"))
8884 (clobber (reg:SI PR_REG))
8885 (clobber (reg:SI R4_REG))
8886 (clobber (reg:SI R5_REG))
8887 (clobber (reg:SI R0_REG))])]
8890 if (expand_block_move (operands))
8896 (define_insn "block_move_real"
8897 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8898 (mem:BLK (reg:SI R5_REG)))
8899 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8900 (use (match_operand 1 "" "Z,Ccl"))
8901 (clobber (reg:SI PR_REG))
8902 (clobber (reg:SI R0_REG))])]
8903 "TARGET_SH1 && ! TARGET_HARD_SH4"
8907 [(set_attr "type" "sfunc")
8908 (set_attr "needs_delay_slot" "yes")])
8910 (define_insn "block_lump_real"
8911 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8912 (mem:BLK (reg:SI R5_REG)))
8913 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8914 (use (match_operand 1 "" "Z,Ccl"))
8915 (use (reg:SI R6_REG))
8916 (clobber (reg:SI PR_REG))
8917 (clobber (reg:SI T_REG))
8918 (clobber (reg:SI R4_REG))
8919 (clobber (reg:SI R5_REG))
8920 (clobber (reg:SI R6_REG))
8921 (clobber (reg:SI R0_REG))])]
8922 "TARGET_SH1 && ! TARGET_HARD_SH4"
8926 [(set_attr "type" "sfunc")
8927 (set_attr "needs_delay_slot" "yes")])
8929 (define_insn "block_move_real_i4"
8930 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8931 (mem:BLK (reg:SI R5_REG)))
8932 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8933 (use (match_operand 1 "" "Z,Ccl"))
8934 (clobber (reg:SI PR_REG))
8935 (clobber (reg:SI R0_REG))
8936 (clobber (reg:SI R1_REG))
8937 (clobber (reg:SI R2_REG))])]
8942 [(set_attr "type" "sfunc")
8943 (set_attr "needs_delay_slot" "yes")])
8945 (define_insn "block_lump_real_i4"
8946 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8947 (mem:BLK (reg:SI R5_REG)))
8948 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8949 (use (match_operand 1 "" "Z,Ccl"))
8950 (use (reg:SI R6_REG))
8951 (clobber (reg:SI PR_REG))
8952 (clobber (reg:SI T_REG))
8953 (clobber (reg:SI R4_REG))
8954 (clobber (reg:SI R5_REG))
8955 (clobber (reg:SI R6_REG))
8956 (clobber (reg:SI R0_REG))
8957 (clobber (reg:SI R1_REG))
8958 (clobber (reg:SI R2_REG))
8959 (clobber (reg:SI R3_REG))])]
8964 [(set_attr "type" "sfunc")
8965 (set_attr "needs_delay_slot" "yes")])
8967 ;; byte compare pattern
8969 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
8970 (define_insn "cmpstr_t"
8971 [(set (reg:SI T_REG)
8976 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
8977 (match_operand:SI 1 "arith_reg_operand" "r"))
8978 (const_int 8) (const_int 0))
8979 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
8980 (const_int 8) (const_int 8)))
8981 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
8982 (const_int 8) (const_int 16)))
8983 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
8984 (const_int 8) (const_int 24)))
8988 [(set_attr "type" "mt_group")])
8990 (define_expand "cmpstrsi"
8991 [(set (match_operand:SI 0 "register_operand")
8992 (compare:SI (match_operand:BLK 1 "memory_operand")
8993 (match_operand:BLK 2 "memory_operand")))
8994 (use (match_operand 3 "immediate_operand"))]
8995 "TARGET_SH1 && optimize"
8997 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
9003 (define_expand "cmpstrnsi"
9004 [(set (match_operand:SI 0 "register_operand")
9005 (compare:SI (match_operand:BLK 1 "memory_operand")
9006 (match_operand:BLK 2 "memory_operand")))
9007 (use (match_operand:SI 3 "nonmemory_operand"))
9008 (use (match_operand:SI 4 "immediate_operand"))]
9009 "TARGET_SH1 && optimize"
9011 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
9017 (define_expand "strlensi"
9018 [(set (match_operand:SI 0 "register_operand")
9019 (unspec:SI [(match_operand:BLK 1 "memory_operand")
9020 (match_operand:SI 2 "immediate_operand")
9021 (match_operand:SI 3 "immediate_operand")]
9022 UNSPEC_BUILTIN_STRLEN))]
9023 "TARGET_SH1 && optimize"
9025 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
9031 (define_expand "setmemqi"
9032 [(parallel [(set (match_operand:BLK 0 "memory_operand")
9033 (match_operand 2 "const_int_operand"))
9034 (use (match_operand:QI 1 "const_int_operand"))
9035 (use (match_operand:QI 3 "const_int_operand"))])]
9036 "TARGET_SH1 && optimize"
9038 if (optimize_insn_for_size_p ())
9041 sh_expand_setmem (operands);
9046 ;; -------------------------------------------------------------------------
9047 ;; Floating point instructions.
9048 ;; -------------------------------------------------------------------------
9050 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
9051 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
9052 ;; This avoids problems with reload. As a consequence, user initiated fpscr
9053 ;; stores to memory will always be ferried through a general register.
9054 ;; User initiated fpscr loads always have to undergo bit masking to preserve
9055 ;; the current fpu mode settings for the compiler generated code. Thus such
9056 ;; fpscr loads will always have to go through general registers anyways.
9057 (define_insn "lds_fpscr"
9058 [(set (reg:SI FPSCR_REG)
9059 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
9060 (set (reg:SI FPSCR_STAT_REG)
9061 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
9062 (set (reg:SI FPSCR_MODES_REG)
9063 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9068 [(set_attr "type" "gp_fpscr,mem_fpscr")])
9070 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
9072 (define_insn "sts_fpscr"
9073 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
9075 (use (reg:SI FPSCR_STAT_REG))
9076 (use (reg:SI FPSCR_MODES_REG))]
9081 [(set_attr "type" "mac_gp,fstore")])
9083 (define_expand "set_fpscr"
9084 [(parallel [(set (reg:SI FPSCR_REG)
9085 (match_operand:SI 0 "general_operand"))
9086 (set (reg:SI FPSCR_STAT_REG)
9087 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
9090 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
9091 get the current FPSCR value first.
9092 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
9094 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
9096 rtx a = force_reg (SImode, operands[0]);
9098 rtx b = gen_reg_rtx (SImode);
9099 emit_insn (gen_sts_fpscr (b));
9101 rtx a_xor_b = gen_reg_rtx (SImode);
9102 emit_insn (gen_xorsi3 (a_xor_b, a, b));
9104 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
9105 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
9107 rtx r = gen_reg_rtx (SImode);
9108 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
9109 emit_insn (gen_lds_fpscr (r));
9114 ;; ??? This uses the fp unit, but has no type indicating that.
9115 ;; If we did that, this would either give a bogus latency or introduce
9116 ;; a bogus FIFO constraint.
9117 ;; Since this insn is currently only used for prologues/epilogues,
9118 ;; it is probably best to claim no function unit, which matches the
9120 (define_insn "toggle_sz"
9121 [(set (reg:SI FPSCR_REG)
9122 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
9123 (set (reg:SI FPSCR_MODES_REG)
9124 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9127 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
9129 ;; Toggle FPU precision PR mode.
9131 (define_insn "toggle_pr"
9132 [(set (reg:SI FPSCR_REG)
9133 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
9134 (set (reg:SI FPSCR_MODES_REG)
9135 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9138 [(set_attr "type" "fpscr_toggle")])
9140 (define_expand "addsf3"
9141 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9142 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
9143 (match_operand:SF 2 "fp_arith_reg_operand")))]
9146 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
9150 (define_insn "addsf3_i"
9151 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9152 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9153 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9154 (clobber (reg:SI FPSCR_STAT_REG))
9155 (use (reg:SI FPSCR_MODES_REG))]
9158 [(set_attr "type" "fp")
9159 (set_attr "fp_mode" "single")])
9161 (define_expand "subsf3"
9162 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9163 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9164 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9167 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
9171 (define_insn "subsf3_i"
9172 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9173 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9174 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9175 (clobber (reg:SI FPSCR_STAT_REG))
9176 (use (reg:SI FPSCR_MODES_REG))]
9179 [(set_attr "type" "fp")
9180 (set_attr "fp_mode" "single")])
9182 (define_expand "mulsf3"
9183 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9184 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9185 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9188 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
9192 (define_insn "mulsf3_i"
9193 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9194 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9195 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9196 (clobber (reg:SI FPSCR_STAT_REG))
9197 (use (reg:SI FPSCR_MODES_REG))]
9200 [(set_attr "type" "fp")
9201 (set_attr "fp_mode" "single")])
9203 ;; FMA (fused multiply-add) patterns
9204 (define_expand "fmasf4"
9205 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9206 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
9207 (match_operand:SF 2 "fp_arith_reg_operand")
9208 (match_operand:SF 3 "fp_arith_reg_operand")))]
9211 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], operands[3]));
9215 (define_insn "fmasf4_i"
9216 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9217 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
9218 (match_operand:SF 2 "fp_arith_reg_operand" "f")
9219 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
9220 (clobber (reg:SI FPSCR_STAT_REG))
9221 (use (reg:SI FPSCR_MODES_REG))]
9224 [(set_attr "type" "fp")
9225 (set_attr "fp_mode" "single")])
9227 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
9228 ;; previous transformations. If FMA is generally allowed, let the combine
9230 (define_insn_and_split "*fmasf4"
9231 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9232 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
9233 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
9234 (match_operand:SF 3 "arith_reg_operand" "0")))
9235 (clobber (reg:SI FPSCR_STAT_REG))
9236 (use (reg:SI FPSCR_MODES_REG))]
9237 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
9239 "&& can_create_pseudo_p ()"
9240 [(parallel [(set (match_dup 0)
9241 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
9242 (clobber (reg:SI FPSCR_STAT_REG))
9243 (use (reg:SI FPSCR_MODES_REG))])]
9245 /* Change 'b * a + a' into 'a * b + a'.
9246 This is better for register allocation. */
9247 if (REGNO (operands[2]) == REGNO (operands[3]))
9248 std::swap (operands[1], operands[2]);
9250 [(set_attr "type" "fp")
9251 (set_attr "fp_mode" "single")])
9253 (define_expand "divsf3"
9254 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9255 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
9256 (match_operand:SF 2 "fp_arith_reg_operand")))]
9259 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
9263 (define_insn "divsf3_i"
9264 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9265 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9266 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9267 (clobber (reg:SI FPSCR_STAT_REG))
9268 (use (reg:SI FPSCR_MODES_REG))]
9271 [(set_attr "type" "fdiv")
9272 (set_attr "fp_mode" "single")])
9274 (define_expand "floatsisf2"
9275 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9276 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
9279 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
9283 (define_insn "floatsisf2_i4"
9284 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9285 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
9286 (clobber (reg:SI FPSCR_STAT_REG))
9287 (use (reg:SI FPSCR_MODES_REG))]
9290 [(set_attr "type" "fp")
9291 (set_attr "fp_mode" "single")])
9293 (define_expand "fix_truncsfsi2"
9294 [(set (match_operand:SI 0 "fpul_operand")
9295 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand")))]
9298 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
9302 (define_insn "fix_truncsfsi2_i4"
9303 [(set (match_operand:SI 0 "fpul_operand" "=y")
9304 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9305 (clobber (reg:SI FPSCR_STAT_REG))
9306 (use (reg:SI FPSCR_MODES_REG))]
9309 [(set_attr "type" "ftrc_s")
9310 (set_attr "fp_mode" "single")])
9312 (define_insn "cmpgtsf_t"
9313 [(set (reg:SI T_REG)
9314 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9315 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9316 (clobber (reg:SI FPSCR_STAT_REG))
9317 (use (reg:SI FPSCR_MODES_REG))]
9318 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9320 [(set_attr "type" "fp_cmp")
9321 (set_attr "fp_mode" "single")])
9323 (define_insn "cmpeqsf_t"
9324 [(set (reg:SI T_REG)
9325 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9326 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9327 (clobber (reg:SI FPSCR_STAT_REG))
9328 (use (reg:SI FPSCR_MODES_REG))]
9329 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9331 [(set_attr "type" "fp_cmp")
9332 (set_attr "fp_mode" "single")])
9334 (define_insn "ieee_ccmpeqsf_t"
9335 [(set (reg:SI T_REG)
9336 (ior:SI (reg:SI T_REG)
9337 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9338 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
9339 (clobber (reg:SI FPSCR_STAT_REG))
9340 (use (reg:SI FPSCR_MODES_REG))]
9341 "TARGET_IEEE && TARGET_SH2E"
9343 return output_ieee_ccmpeq (insn, operands);
9345 [(set_attr "length" "4")
9346 (set_attr "fp_mode" "single")])
9348 (define_expand "cbranchsf4"
9350 (if_then_else (match_operator 0 "ordered_comparison_operator"
9351 [(match_operand:SF 1 "arith_operand" "")
9352 (match_operand:SF 2 "arith_operand" "")])
9353 (match_operand 3 "" "")
9357 sh_emit_compare_and_branch (operands, SFmode);
9361 (define_expand "negsf2"
9362 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9363 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9366 (define_insn "*negsf2_i"
9367 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9368 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9371 [(set_attr "type" "fmove")])
9373 (define_expand "sqrtsf2"
9374 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9375 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
9378 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
9382 (define_insn "sqrtsf2_i"
9383 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9384 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
9385 (clobber (reg:SI FPSCR_STAT_REG))
9386 (use (reg:SI FPSCR_MODES_REG))]
9389 [(set_attr "type" "fdiv")
9390 (set_attr "fp_mode" "single")])
9392 (define_insn "rsqrtsf2"
9393 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9394 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "0")]
9396 (clobber (reg:SI FPSCR_STAT_REG))
9397 (use (reg:SI FPSCR_MODES_REG))]
9398 "TARGET_FPU_ANY && TARGET_FSRRA"
9400 [(set_attr "type" "fsrra")
9401 (set_attr "fp_mode" "single")])
9403 ;; When the sincos pattern is defined, the builtin functions sin and cos
9404 ;; will be expanded to the sincos pattern and one of the output values will
9406 (define_expand "sincossf3"
9407 [(set (match_operand:SF 0 "nonimmediate_operand")
9408 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
9409 (set (match_operand:SF 1 "nonimmediate_operand")
9410 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
9411 "TARGET_FPU_ANY && TARGET_FSCA"
9413 rtx scaled = gen_reg_rtx (SFmode);
9414 rtx truncated = gen_reg_rtx (SImode);
9415 rtx fsca = gen_reg_rtx (V2SFmode);
9416 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
9418 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
9419 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
9420 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
9422 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
9423 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
9427 (define_insn_and_split "fsca"
9428 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
9430 (unspec:SF [(mult:SF
9431 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
9432 (match_operand:SF 2 "fsca_scale_factor" "i"))
9434 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
9436 (clobber (reg:SI FPSCR_STAT_REG))
9437 (use (reg:SI FPSCR_MODES_REG))]
9438 "TARGET_FPU_ANY && TARGET_FSCA"
9440 "&& !fpul_operand (operands[1], SImode)"
9443 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
9444 to a simple reg, otherwise reload will have trouble reloading the
9445 pseudo into fpul. */
9446 rtx x = XEXP (operands[1], 0);
9447 while (x != NULL_RTX && !fpul_operand (x, SImode))
9449 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
9452 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
9453 emit_insn (gen_fsca (operands[0], x, operands[2]));
9456 [(set_attr "type" "fsca")
9457 (set_attr "fp_mode" "single")])
9459 (define_expand "abssf2"
9460 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9461 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9464 (define_insn "*abssf2_i"
9465 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9466 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9469 [(set_attr "type" "fmove")])
9471 (define_expand "adddf3"
9472 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9473 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9474 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9477 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
9481 (define_insn "adddf3_i"
9482 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9483 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9484 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9485 (clobber (reg:SI FPSCR_STAT_REG))
9486 (use (reg:SI FPSCR_MODES_REG))]
9489 [(set_attr "type" "dfp_arith")
9490 (set_attr "fp_mode" "double")])
9492 (define_expand "subdf3"
9493 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9494 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9495 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9498 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
9502 (define_insn "subdf3_i"
9503 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9504 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9505 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9506 (clobber (reg:SI FPSCR_STAT_REG))
9507 (use (reg:SI FPSCR_MODES_REG))]
9510 [(set_attr "type" "dfp_arith")
9511 (set_attr "fp_mode" "double")])
9513 (define_expand "muldf3"
9514 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9515 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9516 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9519 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
9523 (define_insn "muldf3_i"
9524 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9525 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9526 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9527 (clobber (reg:SI FPSCR_STAT_REG))
9528 (use (reg:SI FPSCR_MODES_REG))]
9531 [(set_attr "type" "dfp_mul")
9532 (set_attr "fp_mode" "double")])
9534 (define_expand "divdf3"
9535 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9536 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9537 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9540 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
9544 (define_insn "divdf3_i"
9545 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9546 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9547 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9548 (clobber (reg:SI FPSCR_STAT_REG))
9549 (use (reg:SI FPSCR_MODES_REG))]
9552 [(set_attr "type" "dfdiv")
9553 (set_attr "fp_mode" "double")])
9555 (define_expand "floatsidf2"
9556 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9557 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
9560 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
9564 (define_insn "floatsidf2_i"
9565 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9566 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
9567 (clobber (reg:SI FPSCR_STAT_REG))
9568 (use (reg:SI FPSCR_MODES_REG))]
9571 [(set_attr "type" "dfp_conv")
9572 (set_attr "fp_mode" "double")])
9574 (define_expand "fix_truncdfsi2"
9575 [(set (match_operand:SI 0 "fpul_operand" "")
9576 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9579 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
9583 (define_insn "fix_truncdfsi2_i"
9584 [(set (match_operand:SI 0 "fpul_operand" "=y")
9585 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9586 (clobber (reg:SI FPSCR_STAT_REG))
9587 (use (reg:SI FPSCR_MODES_REG))]
9590 [(set_attr "type" "dfp_conv")
9591 (set_attr "dfp_comp" "no")
9592 (set_attr "fp_mode" "double")])
9594 (define_insn "cmpgtdf_t"
9595 [(set (reg:SI T_REG)
9596 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9597 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9598 (clobber (reg:SI FPSCR_STAT_REG))
9599 (use (reg:SI FPSCR_MODES_REG))]
9602 [(set_attr "type" "dfp_cmp")
9603 (set_attr "fp_mode" "double")])
9605 (define_insn "cmpeqdf_t"
9606 [(set (reg:SI T_REG)
9607 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9608 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9609 (clobber (reg:SI FPSCR_STAT_REG))
9610 (use (reg:SI FPSCR_MODES_REG))]
9613 [(set_attr "type" "dfp_cmp")
9614 (set_attr "fp_mode" "double")])
9616 (define_insn "*ieee_ccmpeqdf_t"
9617 [(set (reg:SI T_REG)
9618 (ior:SI (reg:SI T_REG)
9619 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9620 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
9621 (clobber (reg:SI FPSCR_STAT_REG))
9622 (use (reg:SI FPSCR_MODES_REG))]
9623 "TARGET_IEEE && TARGET_FPU_DOUBLE"
9625 return output_ieee_ccmpeq (insn, operands);
9627 [(set_attr "length" "4")
9628 (set_attr "fp_mode" "double")])
9630 (define_expand "cbranchdf4"
9632 (if_then_else (match_operator 0 "ordered_comparison_operator"
9633 [(match_operand:DF 1 "arith_operand" "")
9634 (match_operand:DF 2 "arith_operand" "")])
9635 (match_operand 3 "" "")
9639 sh_emit_compare_and_branch (operands, DFmode);
9643 (define_expand "negdf2"
9644 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9645 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9646 "TARGET_FPU_DOUBLE")
9648 (define_insn "*negdf2_i"
9649 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9650 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9653 [(set_attr "type" "fmove")])
9655 (define_expand "sqrtdf2"
9656 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9657 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9660 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
9664 (define_insn "sqrtdf2_i"
9665 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9666 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
9667 (clobber (reg:SI FPSCR_STAT_REG))
9668 (use (reg:SI FPSCR_MODES_REG))]
9671 [(set_attr "type" "dfdiv")
9672 (set_attr "fp_mode" "double")])
9674 (define_expand "absdf2"
9675 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9676 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9677 "TARGET_FPU_DOUBLE")
9679 (define_insn "*absdf2_i"
9680 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9681 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9684 [(set_attr "type" "fmove")])
9686 (define_expand "extendsfdf2"
9687 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9688 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
9691 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
9695 (define_insn "extendsfdf2_i4"
9696 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9697 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
9698 (clobber (reg:SI FPSCR_STAT_REG))
9699 (use (reg:SI FPSCR_MODES_REG))]
9702 [(set_attr "type" "fp")
9703 (set_attr "fp_mode" "double")])
9705 (define_expand "truncdfsf2"
9706 [(set (match_operand:SF 0 "fpul_operand" "")
9707 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9710 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
9714 (define_insn "truncdfsf2_i4"
9715 [(set (match_operand:SF 0 "fpul_operand" "=y")
9716 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9717 (clobber (reg:SI FPSCR_STAT_REG))
9718 (use (reg:SI FPSCR_MODES_REG))]
9721 [(set_attr "type" "fp")
9722 (set_attr "fp_mode" "double")])
9724 ;; -------------------------------------------------------------------------
9725 ;; Bit field extract patterns.
9726 ;; -------------------------------------------------------------------------
9728 ;; These give better code for packed bitfields, because they allow
9729 ;; auto-increment addresses to be generated.
9731 (define_expand "insv"
9732 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
9733 (match_operand:SI 1 "immediate_operand" "")
9734 (match_operand:SI 2 "immediate_operand" ""))
9735 (match_operand:SI 3 "general_operand" ""))]
9736 "TARGET_SH1 && TARGET_BIG_ENDIAN"
9738 rtx addr_target, orig_address, shift_reg, qi_val;
9739 HOST_WIDE_INT bitsize, size, v = 0;
9740 rtx x = operands[3];
9742 if (TARGET_SH2A && TARGET_BITOPS
9743 && (satisfies_constraint_Sbw (operands[0])
9744 || satisfies_constraint_Sbv (operands[0]))
9745 && satisfies_constraint_M (operands[1])
9746 && satisfies_constraint_K03 (operands[2]))
9748 if (satisfies_constraint_N (operands[3]))
9750 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
9753 else if (satisfies_constraint_M (operands[3]))
9755 emit_insn (gen_bset_m2a (operands[0], operands[2]));
9758 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
9759 && satisfies_constraint_M (operands[1]))
9761 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9764 else if (REG_P (operands[3])
9765 && satisfies_constraint_M (operands[1]))
9767 emit_insn (gen_bldsi_reg (operands[3], const0_rtx));
9768 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9772 /* ??? expmed doesn't care for non-register predicates. */
9773 if (! memory_operand (operands[0], VOIDmode)
9774 || ! immediate_operand (operands[1], VOIDmode)
9775 || ! immediate_operand (operands[2], VOIDmode)
9776 || ! general_operand (x, VOIDmode))
9778 /* If this isn't a 16 / 24 / 32 bit field, or if
9779 it doesn't start on a byte boundary, then fail. */
9780 bitsize = INTVAL (operands[1]);
9781 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
9782 || (INTVAL (operands[2]) % 8) != 0)
9786 orig_address = XEXP (operands[0], 0);
9787 shift_reg = gen_reg_rtx (SImode);
9788 if (CONST_INT_P (x))
9791 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
9795 emit_insn (gen_movsi (shift_reg, operands[3]));
9796 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9798 addr_target = copy_addr_to_reg (plus_constant (Pmode,
9799 orig_address, size - 1));
9801 operands[0] = replace_equiv_address (operands[0], addr_target);
9802 emit_insn (gen_movqi (operands[0], qi_val));
9806 if (CONST_INT_P (x))
9808 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
9811 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
9812 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9814 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
9815 emit_insn (gen_movqi (operands[0], qi_val));
9821 (define_insn "movua"
9822 [(set (match_operand:SI 0 "register_operand" "=z")
9823 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
9827 [(set_attr "type" "movua")])
9829 ;; We shouldn't need this, but cse replaces increments with references
9830 ;; to other regs before flow has a chance to create post_inc
9831 ;; addressing modes, and only postreload's cse_move2add brings the
9832 ;; increments back to a usable form.
9834 [(set (match_operand:SI 0 "register_operand" "")
9835 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
9836 (const_int 32) (const_int 0)))
9837 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9838 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
9839 [(set (match_operand:SI 0 "register_operand" "")
9840 (sign_extract:SI (mem:SI (post_inc:SI
9841 (match_operand:SI 1 "register_operand" "")))
9842 (const_int 32) (const_int 0)))]
9845 (define_expand "extv"
9846 [(set (match_operand:SI 0 "register_operand" "")
9847 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9848 (match_operand 2 "const_int_operand" "")
9849 (match_operand 3 "const_int_operand" "")))]
9850 "TARGET_SH4A || TARGET_SH2A"
9852 if (TARGET_SH2A && TARGET_BITOPS
9853 && (satisfies_constraint_Sbw (operands[1])
9854 || satisfies_constraint_Sbv (operands[1]))
9855 && satisfies_constraint_M (operands[2])
9856 && satisfies_constraint_K03 (operands[3]))
9858 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
9859 if (REGNO (operands[0]) != T_REG)
9860 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9864 && INTVAL (operands[2]) == 32
9865 && INTVAL (operands[3]) == 0
9866 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9868 rtx src = adjust_address (operands[1], BLKmode, 0);
9869 set_mem_size (src, 4);
9870 emit_insn (gen_movua (operands[0], src));
9877 (define_expand "extzv"
9878 [(set (match_operand:SI 0 "register_operand" "")
9879 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9880 (match_operand 2 "const_int_operand" "")
9881 (match_operand 3 "const_int_operand" "")))]
9882 "TARGET_SH4A || TARGET_SH2A"
9884 if (TARGET_SH2A && TARGET_BITOPS
9885 && (satisfies_constraint_Sbw (operands[1])
9886 || satisfies_constraint_Sbv (operands[1]))
9887 && satisfies_constraint_M (operands[2])
9888 && satisfies_constraint_K03 (operands[3]))
9890 emit_insn (gen_bld_m2a (operands[1], operands[3]));
9891 if (REGNO (operands[0]) != T_REG)
9892 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9896 && INTVAL (operands[2]) == 32
9897 && INTVAL (operands[3]) == 0
9898 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9900 rtx src = adjust_address (operands[1], BLKmode, 0);
9901 set_mem_size (src, 4);
9902 emit_insn (gen_movua (operands[0], src));
9909 ;; -------------------------------------------------------------------------
9910 ;; Extract negated single bit and zero extend it.
9911 ;; Generally we don't care about the exact xor const_int value, as long
9912 ;; as it contains the extracted bit. For simplicity, the pattern variations
9913 ;; that convert everything into the primary '*neg_zero_extract_0' pattern use
9914 ;; a xor const_int -1 value.
9916 (define_insn_and_split "*neg_zero_extract_0"
9917 [(set (reg:SI T_REG)
9918 (zero_extract:SI (xor:QIHISI (match_operand:QIHISI 0 "arith_reg_operand")
9919 (match_operand 1 "const_int_operand"))
9921 (match_operand 2 "const_int_operand")))]
9922 "TARGET_SH1 && can_create_pseudo_p ()
9923 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
9926 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 2))
9929 if (INTVAL (operands[2]) == 31 && <MODE>mode == SImode)
9931 /* Use cmp/pz to extract bit 31 into the T bit. */
9932 emit_insn (gen_cmpgesi_t (operands[0], const0_rtx));
9936 operands[2] = GEN_INT ((1 << INTVAL (operands[2])));
9937 if (GET_MODE (operands[0]) != SImode)
9938 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
9941 (define_insn_and_split "*neg_zero_extract_1"
9942 [(set (reg:SI T_REG)
9943 (and:SI (not:SI (match_operand:SI 0 "arith_reg_operand"))
9948 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9949 (const_int 1) (const_int 0)))])
9951 ;; x & (1 << n) == 0: 0x00000000 + 1 = 1
9952 ;; x & (1 << n) != 0: 0xFFFFFFFF + 1 = 0
9953 (define_insn_and_split "*neg_zero_extract_2"
9954 [(set (reg:SI T_REG)
9955 (plus:SI (sign_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
9957 (match_operand 1 "const_int_operand"))
9959 "TARGET_SH1 && can_create_pseudo_p ()"
9962 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9963 (const_int 1) (match_dup 1)))])
9965 ;; (signed)x >> 31 + 1 = (x >= 0) ^ 1
9966 (define_insn_and_split "*neg_zero_extract_3"
9967 [(set (reg:SI T_REG)
9968 (plus:SI (ashiftrt:SI (match_operand:SI 0 "arith_reg_operand")
9971 "TARGET_SH1 && can_create_pseudo_p ()"
9974 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9975 (const_int 1) (const_int 31)))])
9977 ;; This is required for some bit patterns of DImode subregs.
9978 ;; It looks like combine gets confused by the DImode right shift and fails
9979 ;; to simplify things.
9980 (define_insn_and_split "*neg_zero_extract_4"
9981 [(set (reg:SI T_REG)
9983 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
9984 (match_operand 1 "const_int_operand"))
9985 (match_operand 2 "const_int_operand"))
9986 (not:SI (ashift:SI (match_operand:SI 3 "arith_reg_operand")
9987 (match_operand 4 "const_int_operand"))))
9989 "TARGET_SH1 && can_create_pseudo_p ()
9990 && INTVAL (operands[4]) > 0
9991 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
9994 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9995 (const_int 1) (match_dup 2)))])
9997 (define_insn_and_split "*neg_zero_extract_5"
9998 [(set (reg:SI T_REG)
9999 (and:SI (not:SI (subreg:SI
10000 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10001 (match_operand 1 "const_int_operand"))
10004 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10005 && INTVAL (operands[1]) < 32"
10008 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10009 (const_int 1) (match_dup 1)))]
10011 operands[0] = gen_lowpart (SImode, operands[0]);
10014 (define_insn_and_split "*neg_zero_extract_6"
10015 [(set (reg:SI T_REG)
10016 (and:SI (not:SI (subreg:SI
10017 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10018 (match_operand 1 "const_int_operand"))
10021 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10022 && INTVAL (operands[1]) < 32"
10025 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10026 (const_int 1) (match_dup 1)))]
10028 operands[0] = gen_lowpart (SImode, operands[0]);
10031 ;; -------------------------------------------------------------------------
10032 ;; Extract single bit and zero extend it.
10033 ;; All patterns store the result bit in the T bit, although that is not
10034 ;; always possible to do with a single insn and a nott must be appended.
10035 ;; The trailing nott will be optimized away in most cases. E.g. if the
10036 ;; extracted bit is fed into a branch condition, the condition can be
10037 ;; inverted and the nott will be eliminated.
10038 ;; FIXME: In cases where the trailing nott can't be eliminated, try to
10039 ;; convert it into a (not, tst) sequence, which could be better on non-SH2A.
10041 ;; On SH2A the 'bld<mode>_reg' insn will be used if the bit position fits.
10042 (define_insn_and_split "*zero_extract_0"
10043 [(set (reg:SI T_REG)
10044 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
10046 (match_operand 1 "const_int_operand")))]
10047 "TARGET_SH1 && can_create_pseudo_p ()
10048 && !(TARGET_SH2A && satisfies_constraint_K03 (operands[1]))"
10051 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 1))
10053 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]
10055 if (INTVAL (operands[1]) == 31 && <MODE>mode == SImode)
10057 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
10061 operands[1] = GEN_INT (1 << INTVAL (operands[1]));
10062 if (GET_MODE (operands[0]) != SImode)
10063 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
10066 ;; This is required for some bit patterns of DImode subregs.
10067 ;; It looks like combine gets confused by the DImode right shift and fails
10068 ;; to simplify things.
10069 (define_insn_and_split "*zero_extract_1"
10070 [(set (reg:SI T_REG)
10071 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10073 (match_operand 1 "const_int_operand"))
10075 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10076 && INTVAL (operands[1]) < 32"
10079 [(set (reg:SI T_REG)
10080 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10082 (define_insn_and_split "*zero_extract_2"
10083 [(set (reg:SI T_REG)
10084 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10086 (match_operand 1 "const_int_operand"))
10088 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10089 && INTVAL (operands[1]) < 32"
10092 [(set (reg:SI T_REG)
10093 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10095 (define_insn_and_split "*zero_extract_3"
10096 [(set (match_operand:SI 0 "arith_reg_dest")
10097 (and:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
10098 (match_operand 2 "const_int_operand"))
10099 (match_operand 3 "const_int_operand")))
10100 (clobber (reg:SI T_REG))]
10101 "TARGET_SH1 && can_create_pseudo_p ()
10102 && exact_log2 (INTVAL (operands[3])) >= 0"
10107 int rshift = INTVAL (operands[2]);
10108 int lshift = exact_log2 (INTVAL (operands[3]));
10110 rtx tmp = gen_reg_rtx (SImode);
10111 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10114 gen_rtx_ZERO_EXTRACT (SImode, operands[1], const1_rtx,
10115 GEN_INT (rshift + lshift))),
10116 gen_rtx_CLOBBER (VOIDmode, get_t_reg_rtx ()))));
10117 emit_insn (gen_ashlsi3 (operands[0], tmp, GEN_INT (lshift)));
10120 ;; -------------------------------------------------------------------------
10121 ;; SH2A instructions for bitwise operations.
10122 ;; FIXME: Convert multiple instruction insns to insn_and_split.
10123 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
10125 ;; Clear a bit in a memory location.
10126 (define_insn "bclr_m2a"
10127 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10129 (not:QI (ashift:QI (const_int 1)
10130 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10132 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10135 bclr.b %1,@(0,%t0)"
10136 [(set_attr "length" "4,4")])
10138 (define_insn "bclrmem_m2a"
10139 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10140 (and:QI (match_dup 0)
10141 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
10142 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
10145 bclr.b %W1,@(0,%t0)"
10146 [(set_attr "length" "4,4")])
10148 ;; Set a bit in a memory location.
10149 (define_insn "bset_m2a"
10150 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10152 (ashift:QI (const_int 1)
10153 (match_operand:QI 1 "const_int_operand" "K03,K03"))
10155 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10158 bset.b %1,@(0,%t0)"
10159 [(set_attr "length" "4,4")])
10161 (define_insn "bsetmem_m2a"
10162 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10163 (ior:QI (match_dup 0)
10164 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
10165 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
10168 bset.b %V1,@(0,%t0)"
10169 [(set_attr "length" "4,4")])
10171 ;;; Transfer the contents of the T bit to a specified bit of memory.
10172 (define_insn "bst_m2a"
10173 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
10174 (if_then_else (eq (reg:SI T_REG) (const_int 0))
10176 (not:QI (ashift:QI (const_int 1)
10177 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10180 (ashift:QI (const_int 1) (match_dup 1))
10182 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10186 [(set_attr "length" "4")])
10188 ;; Store a specified bit of memory in the T bit.
10189 (define_insn "bld_m2a"
10190 [(set (reg:SI T_REG)
10192 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
10194 (match_operand 1 "const_int_operand" "K03,K03")))]
10195 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10199 [(set_attr "length" "4,4")])
10201 ;; Store a specified bit of memory in the T bit.
10202 (define_insn "bldsign_m2a"
10203 [(set (reg:SI T_REG)
10205 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10207 (match_operand 1 "const_int_operand" "K03,K03")))]
10208 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10212 [(set_attr "length" "4,4")])
10214 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
10215 (define_insn "bld<mode>_reg"
10216 [(set (reg:SI T_REG)
10217 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand" "r")
10219 (match_operand 1 "const_int_operand" "K03")))]
10220 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
10223 ;; Take logical and of a specified bit of memory with the T bit and
10224 ;; store its result in the T bit.
10225 (define_insn "band_m2a"
10226 [(set (reg:SI T_REG)
10227 (and:SI (reg:SI T_REG)
10229 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10231 (match_operand 1 "const_int_operand" "K03,K03"))))]
10232 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10235 band.b %1,@(0,%t0)"
10236 [(set_attr "length" "4,4")])
10238 (define_insn "bandreg_m2a"
10239 [(set (match_operand:SI 0 "register_operand" "=r,r")
10240 (and:SI (zero_extract:SI
10241 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10243 (match_operand 2 "const_int_operand" "K03,K03"))
10244 (match_operand:SI 3 "register_operand" "r,r")))]
10245 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10247 static const char* alt[] =
10249 "band.b %2,%1" "\n"
10252 "band.b %2,@(0,%t1)" "\n"
10255 return alt[which_alternative];
10257 [(set_attr "length" "6,6")])
10259 ;; Take logical or of a specified bit of memory with the T bit and
10260 ;; store its result in the T bit.
10261 (define_insn "bor_m2a"
10262 [(set (reg:SI T_REG)
10263 (ior:SI (reg:SI T_REG)
10265 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10267 (match_operand 1 "const_int_operand" "K03,K03"))))]
10268 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10272 [(set_attr "length" "4,4")])
10274 (define_insn "borreg_m2a"
10275 [(set (match_operand:SI 0 "register_operand" "=r,r")
10276 (ior:SI (zero_extract:SI
10277 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10279 (match_operand 2 "const_int_operand" "K03,K03"))
10280 (match_operand:SI 3 "register_operand" "=r,r")))]
10281 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10283 static const char* alt[] =
10288 "bor.b %2,@(0,%t1)" "\n"
10291 return alt[which_alternative];
10293 [(set_attr "length" "6,6")])
10295 ;; Take exclusive or of a specified bit of memory with the T bit and
10296 ;; store its result in the T bit.
10297 (define_insn "bxor_m2a"
10298 [(set (reg:SI T_REG)
10299 (xor:SI (reg:SI T_REG)
10301 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10303 (match_operand 1 "const_int_operand" "K03,K03"))))]
10304 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10307 bxor.b %1,@(0,%t0)"
10308 [(set_attr "length" "4,4")])
10310 (define_insn "bxorreg_m2a"
10311 [(set (match_operand:SI 0 "register_operand" "=r,r")
10312 (xor:SI (zero_extract:SI
10313 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10315 (match_operand 2 "const_int_operand" "K03,K03"))
10316 (match_operand:SI 3 "register_operand" "=r,r")))]
10317 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10319 static const char* alt[] =
10321 "bxor.b %2,%1" "\n"
10324 "bxor.b %2,@(0,%t1)" "\n"
10327 return alt[which_alternative];
10329 [(set_attr "length" "6,6")])
10331 ;; -------------------------------------------------------------------------
10333 ;; -------------------------------------------------------------------------
10334 ;; This matches cases where the bit in a memory location is set.
10336 [(set (match_operand:SI 0 "register_operand")
10337 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10339 (ior:SI (match_dup 0)
10340 (match_operand:SI 2 "const_int_operand")))
10342 (match_operand 3 "arith_reg_operand"))]
10343 "TARGET_SH2A && TARGET_BITOPS
10344 && satisfies_constraint_Pso (operands[2])
10345 && REGNO (operands[0]) == REGNO (operands[3])"
10346 [(set (match_dup 1)
10347 (ior:QI (match_dup 1) (match_dup 2)))]
10350 ;; This matches cases where the bit in a memory location is cleared.
10352 [(set (match_operand:SI 0 "register_operand")
10353 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10355 (and:SI (match_dup 0)
10356 (match_operand:SI 2 "const_int_operand")))
10358 (match_operand 3 "arith_reg_operand"))]
10359 "TARGET_SH2A && TARGET_BITOPS
10360 && satisfies_constraint_Psz (operands[2])
10361 && REGNO (operands[0]) == REGNO (operands[3])"
10362 [(set (match_dup 1)
10363 (and:QI (match_dup 1) (match_dup 2)))]
10366 ;; This matches cases where a stack pointer increment at the start of the
10367 ;; epilogue combines with a stack slot read loading the return value.
10369 [(set (match_operand:SI 0 "arith_reg_operand" "")
10370 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
10371 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
10372 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
10375 ;; See the comment on the dt combiner pattern above.
10377 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
10378 (plus:SI (match_dup 0)
10380 (set (reg:SI T_REG)
10381 (eq:SI (match_dup 0) (const_int 0)))]
10385 ;; The following peepholes fold load sequences for which reload was not
10386 ;; able to generate a displacement addressing move insn.
10387 ;; This can happen when reload has to transform a move insn
10388 ;; without displacement into one with displacement. Or when reload can't
10389 ;; fit a displacement into the insn's constraints. In the latter case, the
10390 ;; load destination reg remains at r0, which reload compensates by inserting
10391 ;; another mov insn.
10395 ;; mov.{b,w} @(r0,r15),r0
10398 ;; mov.{b,w} @(54,r15),r3
10401 [(set (match_operand:SI 0 "arith_reg_dest" "")
10402 (match_operand:SI 1 "const_int_operand" ""))
10403 (set (match_operand:SI 2 "arith_reg_dest" "")
10405 (mem:QI (plus:SI (match_dup 0)
10406 (match_operand:SI 3 "arith_reg_operand" "")))))
10407 (set (match_operand:QI 4 "arith_reg_dest" "")
10408 (match_operand:QI 5 "arith_reg_operand" ""))]
10410 && sh_legitimate_index_p (QImode, operands[1], true, true)
10411 && REGNO (operands[2]) == REGNO (operands[5])
10412 && peep2_reg_dead_p (3, operands[5])"
10413 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
10417 [(set (match_operand:SI 0 "arith_reg_dest" "")
10418 (match_operand:SI 1 "const_int_operand" ""))
10419 (set (match_operand:SI 2 "arith_reg_dest" "")
10421 (mem:HI (plus:SI (match_dup 0)
10422 (match_operand:SI 3 "arith_reg_operand" "")))))
10423 (set (match_operand:HI 4 "arith_reg_dest" "")
10424 (match_operand:HI 5 "arith_reg_operand" ""))]
10426 && sh_legitimate_index_p (HImode, operands[1], true, true)
10427 && REGNO (operands[2]) == REGNO (operands[5])
10428 && peep2_reg_dead_p (3, operands[5])"
10429 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
10434 ;; mov.{b,w} @(r0,r15),r1
10436 ;; mov.{b,w} @(54,r15),r1
10439 [(set (match_operand:SI 0 "arith_reg_dest" "")
10440 (match_operand:SI 1 "const_int_operand" ""))
10441 (set (match_operand:SI 2 "arith_reg_dest" "")
10443 (mem:QI (plus:SI (match_dup 0)
10444 (match_operand:SI 3 "arith_reg_operand" "")))))]
10446 && sh_legitimate_index_p (QImode, operands[1], true, true)
10447 && (peep2_reg_dead_p (2, operands[0])
10448 || REGNO (operands[0]) == REGNO (operands[2]))"
10449 [(set (match_dup 2)
10450 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
10454 [(set (match_operand:SI 0 "arith_reg_dest" "")
10455 (match_operand:SI 1 "const_int_operand" ""))
10456 (set (match_operand:SI 2 "arith_reg_dest" "")
10458 (mem:HI (plus:SI (match_dup 0)
10459 (match_operand:SI 3 "arith_reg_operand" "")))))]
10461 && sh_legitimate_index_p (HImode, operands[1], true, true)
10462 && (peep2_reg_dead_p (2, operands[0])
10463 || REGNO (operands[0]) == REGNO (operands[2]))"
10464 [(set (match_dup 2)
10465 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
10469 ;; mov.{b,w} @(r0,r15),r0
10472 ;; mov.{b,w} @(r0,r15),r3
10474 ;; This can happen when initially a displacement address is picked, where
10475 ;; the destination reg is fixed to r0, and then the address is transformed
10476 ;; into 'r0 + reg'.
10478 [(set (match_operand:SI 0 "arith_reg_dest" "")
10480 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10481 (match_operand:SI 2 "arith_reg_operand" "")))))
10482 (set (match_operand:QI 3 "arith_reg_dest" "")
10483 (match_operand:QI 4 "arith_reg_operand" ""))]
10485 && REGNO (operands[0]) == REGNO (operands[4])
10486 && peep2_reg_dead_p (2, operands[0])"
10487 [(set (match_dup 3)
10488 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
10492 [(set (match_operand:SI 0 "arith_reg_dest" "")
10494 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10495 (match_operand:SI 2 "arith_reg_operand" "")))))
10496 (set (match_operand:HI 3 "arith_reg_dest" "")
10497 (match_operand:HI 4 "arith_reg_operand" ""))]
10499 && REGNO (operands[0]) == REGNO (operands[4])
10500 && peep2_reg_dead_p (2, operands[0])"
10501 [(set (match_dup 3)
10502 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
10506 ;; mov b,c -> extu.bw a,c
10508 [(set (match_operand:SI 0 "arith_reg_dest")
10509 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))
10510 (set (match_operand:SI 2 "arith_reg_dest")
10512 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10513 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
10516 ;; extu.bw r1,r1 -> extu.bw r0,r1
10518 [(set (match_operand 0 "arith_reg_dest")
10519 (match_operand 1 "arith_reg_operand"))
10520 (set (match_operand:SI 2 "arith_reg_dest")
10521 (zero_extend:SI (match_operand:QIHI 3 "arith_reg_operand")))]
10523 && REGNO (operands[0]) == REGNO (operands[3])
10524 && (REGNO (operands[0]) == REGNO (operands[2])
10525 || peep2_reg_dead_p (2, operands[0]))"
10526 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))]
10528 operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
10532 ;; mov b,a -> < nop >
10534 [(set (match_operand 0 "register_operand")
10535 (match_operand 1 "register_operand"))
10536 (set (match_operand 2 "register_operand")
10537 (match_operand 3 "register_operand"))]
10539 && REGNO (operands[0]) == REGNO (operands[3])
10540 && REGNO (operands[1]) == REGNO (operands[2])
10541 && peep2_reg_dead_p (2, operands[3])"
10545 ;; and r4,r1 -> mov r1,r0
10546 ;; mov r1,r0 and #3,r0
10547 (define_code_iterator ANDIORXOR [and ior xor])
10549 [(set (match_operand:SI 0 "register_operand")
10550 (match_operand:SI 1 "const_logical_operand"))
10551 (set (match_operand:SI 2) (ANDIORXOR:SI (match_dup 2) (match_dup 0)))
10552 (set (reg:SI R0_REG) (match_dup 2))]
10554 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])"
10555 [(set (reg:SI R0_REG) (match_dup 2))
10556 (set (reg:SI R0_REG) (ANDIORXOR:SI (reg:SI R0_REG) (match_dup 1)))])
10558 ;; ... r2,r0 ... r2,r0
10559 ;; or r1,r0 -> or r0,r1
10562 (define_code_iterator ANDIORXORPLUS [and ior xor plus])
10564 [(set (match_operand:SI 0 "arith_reg_dest")
10565 (ANDIORXORPLUS:SI (match_dup 0) (match_operand:SI 1 "arith_reg_dest")))
10566 (set (match_dup 1) (match_dup 0))]
10567 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10568 [(set (match_dup 1) (ANDIORXORPLUS:SI (match_dup 1) (match_dup 0)))])
10571 ;; add #-48,r0 -> add #-48,r12
10572 ;; mov.l r0,@(4,r10) mov.l r12,@(4,r10)
10575 [(set (match_operand:SI 0 "arith_reg_dest")
10576 (match_operand:SI 1 "arith_reg_dest"))
10577 (set (match_dup 0) (plus:SI (match_dup 0)
10578 (match_operand:SI 2 "const_int_operand")))
10579 (set (match_operand:SI 3 "general_movdst_operand") (match_dup 0))]
10581 && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])"
10584 emit_insn (gen_addsi3 (operands[1], operands[1], operands[2]));
10585 sh_peephole_emit_move_insn (operands[3], operands[1]);
10588 ;; mov.l @(r0,r9),r1
10589 ;; mov r1,r0 -> mov @(r0,r9),r0
10591 [(set (match_operand:SI 0 "arith_reg_dest")
10592 (match_operand:SI 1 "general_movsrc_operand"))
10593 (set (match_operand:SI 2 "arith_reg_dest")
10595 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10598 sh_peephole_emit_move_insn (operands[2], operands[1]);
10602 [(set (match_operand:QIHI 0 "register_operand")
10603 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand"))
10604 (set (match_operand:QIHI 2 "register_operand")
10606 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10609 sh_peephole_emit_move_insn (operands[2], operands[1]);
10613 [(set (match_operand:SI 0 "arith_reg_dest")
10614 (sign_extend:SI (match_operand:QIHI 1 "movsrc_no_disp_mem_operand")))
10615 (set (match_operand:SI 2 "arith_reg_dest")
10617 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10620 sh_check_add_incdec_notes (emit_insn (gen_extend<mode>si2 (operands[2],
10621 sh_remove_overlapping_post_inc (operands[2], operands[1]))));
10624 ;; mov.w @(18,r1),r0 (r0 = HImode)
10625 ;; mov r0,r1 (r0 = r1 = HImode) mov.w @(18,r1),r0
10626 ;; ... ..,r13 (r13 = SImode) -> ... ..,r13
10627 ;; tst r1,r13 tst r0,r13
10629 [(set (match_operand 0 "arith_reg_dest")
10630 (match_operand 1 "arith_reg_dest"))
10631 (set (match_operand:SI 2 "arith_reg_dest")
10632 (match_operand:SI 3))
10633 (set (reg:SI T_REG)
10634 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10635 (match_operand:SI 5 "arith_reg_operand"))
10638 && peep2_reg_dead_p (3, operands[0])
10639 && !reg_overlap_mentioned_p (operands[0], operands[3])
10640 && (REGNO (operands[0]) == REGNO (operands[4])
10641 || REGNO (operands[0]) == REGNO (operands[5]))
10642 && (REGNO (operands[2]) == REGNO (operands[4])
10643 || REGNO (operands[2]) == REGNO (operands[5]))"
10646 if (REGNO (operands[1]) == REGNO (operands[2]))
10647 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
10649 // We don't know what the new set insn will be in detail. Just make sure
10650 // that it still can be recognized and the constraints are satisfied.
10651 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10652 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10654 recog_data_d prev_recog_data = recog_data;
10655 bool i_invalid = insn_invalid_p (i, false);
10656 recog_data = prev_recog_data;
10661 sh_check_add_incdec_notes (i);
10663 emit_insn (gen_tstsi_t (operands[2],
10664 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10667 ;; mov.w @(18,r1),r0 (r0 = HImode)
10668 ;; ... ..,r13 (r13 = SImode) mov.w @(18,r1),r0
10669 ;; mov r0,r1 (r0 = r1 = HImode) -> ... ..,r13
10670 ;; tst r1,r13 tst r0,r13
10672 [(set (match_operand:SI 2 "arith_reg_dest")
10673 (match_operand:SI 3))
10674 (set (match_operand 0 "arith_reg_dest")
10675 (match_operand 1 "arith_reg_operand"))
10676 (set (reg:SI T_REG)
10677 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10678 (match_operand:SI 5 "arith_reg_operand"))
10681 && peep2_reg_dead_p (3, operands[0])
10682 && !reg_overlap_mentioned_p (operands[0], operands[3])
10683 && (REGNO (operands[0]) == REGNO (operands[4])
10684 || REGNO (operands[0]) == REGNO (operands[5]))
10685 && (REGNO (operands[2]) == REGNO (operands[4])
10686 || REGNO (operands[2]) == REGNO (operands[5]))"
10689 // We don't know what the new set insn will be in detail. Just make sure
10690 // that it still can be recognized and the constraints are satisfied.
10691 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10692 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10694 recog_data_d prev_recog_data = recog_data;
10695 bool i_invalid = insn_invalid_p (i, false);
10696 recog_data = prev_recog_data;
10701 sh_check_add_incdec_notes (i);
10703 emit_insn (gen_tstsi_t (operands[2],
10704 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10707 ;; This is not a peephole, but it's here because it's actually supposed
10708 ;; to be one. It tries to convert a sequence such as
10709 ;; movt r2 -> movt r2
10710 ;; movt r13 mov r2,r13
10711 ;; This gives the schduler a bit more freedom to hoist a following
10712 ;; comparison insn. Moreover, it the reg-reg mov insn is MT group which has
10713 ;; better chances for parallel execution.
10714 ;; We can do this with a peephole2 pattern, but then the cprop_hardreg
10715 ;; pass will revert the change. See also PR 64331.
10716 ;; Thus do it manually in one of the split passes after register allocation.
10717 ;; Sometimes the cprop_hardreg pass might also eliminate the reg-reg copy.
10719 [(set (match_operand:SI 0 "arith_reg_dest")
10720 (match_operand:SI 1 "t_reg_operand"))]
10721 "TARGET_SH1 && reload_completed"
10722 [(set (match_dup 0) (match_dup 1))]
10724 rtx t_reg = get_t_reg_rtx ();
10726 for (rtx_insn* i = prev_nonnote_insn_bb (curr_insn); i != NULL;
10727 i = prev_nonnote_insn_bb (i))
10729 if (!INSN_P (i) || DEBUG_INSN_P (i))
10732 if (modified_in_p (t_reg, i) || BARRIER_P (i))
10735 if (sh_is_movt_insn (i))
10737 rtx r = sh_movt_set_dest (i);
10738 if (!modified_between_p (r, i, curr_insn))
10748 [(set (match_operand:SI 0 "register_operand" "=r")
10749 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10750 (set (mem:SF (match_dup 0))
10751 (match_operand:SF 2 "general_movsrc_operand" ""))]
10752 "TARGET_SH1 && REGNO (operands[0]) == 0
10753 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10754 || (GET_CODE (operands[2]) == SUBREG
10755 && REGNO (SUBREG_REG (operands[2])) < 16))
10756 && reg_unused_after (operands[0], insn)"
10757 "mov.l %2,@(%0,%1)")
10760 [(set (match_operand:SI 0 "register_operand" "=r")
10761 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10762 (set (match_operand:SF 2 "general_movdst_operand" "")
10764 (mem:SF (match_dup 0)))]
10765 "TARGET_SH1 && REGNO (operands[0]) == 0
10766 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10767 || (GET_CODE (operands[2]) == SUBREG
10768 && REGNO (SUBREG_REG (operands[2])) < 16))
10769 && reg_unused_after (operands[0], insn)"
10770 "mov.l @(%0,%1),%2")
10773 [(set (match_operand:SI 0 "register_operand" "=r")
10774 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10775 (set (mem:SF (match_dup 0))
10776 (match_operand:SF 2 "general_movsrc_operand" ""))]
10777 "TARGET_SH2E && REGNO (operands[0]) == 0
10778 && ((REG_P (operands[2])
10779 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10780 || (GET_CODE (operands[2]) == SUBREG
10781 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10782 && reg_unused_after (operands[0], insn)"
10783 "fmov{.s|} %2,@(%0,%1)")
10786 [(set (match_operand:SI 0 "register_operand" "=r")
10787 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10788 (set (match_operand:SF 2 "general_movdst_operand" "")
10790 (mem:SF (match_dup 0)))]
10791 "TARGET_SH2E && REGNO (operands[0]) == 0
10792 && ((REG_P (operands[2])
10793 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10794 || (GET_CODE (operands[2]) == SUBREG
10795 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10796 && reg_unused_after (operands[0], insn)"
10797 "fmov{.s|} @(%0,%1),%2")
10799 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
10800 (define_insn "sp_switch_1"
10801 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
10802 UNSPECV_SP_SWITCH_B))]
10805 return "mov.l r0,@-r15" "\n"
10806 " mov.l %0,r0" "\n"
10807 " mov.l @r0,r0" "\n"
10808 " mov.l r15,@-r0" "\n"
10811 [(set_attr "length" "10")])
10813 ;; Switch back to the original stack for interrupt functions with the
10814 ;; sp_switch attribute.
10815 (define_insn "sp_switch_2"
10816 [(unspec_volatile [(const_int 0)]
10817 UNSPECV_SP_SWITCH_E)]
10820 return "mov.l @r15,r15" "\n"
10823 [(set_attr "length" "4")])
10826 ;; In user mode, the "pref" instruction will raise a RADDERR exception
10827 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
10828 ;; implementation of __builtin_prefetch for VxWorks RTPs.
10829 (define_expand "prefetch"
10830 [(prefetch (match_operand 0 "address_operand" "")
10831 (match_operand:SI 1 "const_int_operand" "")
10832 (match_operand:SI 2 "const_int_operand" ""))]
10833 "(TARGET_SH2A || TARGET_SH3) && !TARGET_VXWORKS_RTP")
10835 (define_insn "*prefetch"
10836 [(prefetch (match_operand:SI 0 "register_operand" "r")
10837 (match_operand:SI 1 "const_int_operand" "n")
10838 (match_operand:SI 2 "const_int_operand" "n"))]
10839 "(TARGET_SH2A || TARGET_SH3) && ! TARGET_VXWORKS_RTP"
10841 [(set_attr "type" "other")])
10843 ;; -------------------------------------------------------------------------
10844 ;; Stack Protector Patterns
10845 ;; -------------------------------------------------------------------------
10847 (define_expand "stack_protect_set"
10848 [(set (match_operand 0 "memory_operand" "")
10849 (match_operand 1 "memory_operand" ""))]
10852 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
10856 (define_insn "stack_protect_set_si"
10857 [(set (match_operand:SI 0 "memory_operand" "=m")
10858 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10859 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10862 return "mov.l %1,%2" "\n"
10863 " mov.l %2,%0" "\n"
10866 [(set_attr "type" "other")
10867 (set_attr "length" "6")])
10869 (define_expand "stack_protect_test"
10870 [(match_operand 0 "memory_operand" "")
10871 (match_operand 1 "memory_operand" "")
10872 (match_operand 2 "" "")]
10875 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
10876 emit_jump_insn (gen_branch_true (operands[2]));
10880 (define_insn "stack_protect_test_si"
10881 [(set (reg:SI T_REG)
10882 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
10883 (match_operand:SI 1 "memory_operand" "m")]
10885 (set (match_scratch:SI 2 "=&r") (const_int 0))
10886 (set (match_scratch:SI 3 "=&r") (const_int 0))]
10889 return "mov.l %0,%2" "\n"
10890 " mov.l %1,%3" "\n"
10891 " cmp/eq %2,%3" "\n"
10895 [(set_attr "type" "other")
10896 (set_attr "length" "10")])
10898 ;; -------------------------------------------------------------------------
10899 ;; Atomic operations
10900 ;; -------------------------------------------------------------------------
10902 (include "sync.md")