1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; unsigned int i
;} old_contents
;
318 union {rtx
*r
; unsigned int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((unsigned int *,
344 static void init_reg_last_arrays
PARAMS ((void));
345 static void setup_incoming_promotions
PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
347 static int cant_combine_insn_p
PARAMS ((rtx
));
348 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
349 static int sets_function_arg_p
PARAMS ((rtx
));
350 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
351 static int contains_muldiv
PARAMS ((rtx
));
352 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
353 static void undo_all
PARAMS ((void));
354 static void undo_commit
PARAMS ((void));
355 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
356 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
357 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
358 static rtx simplify_if_then_else
PARAMS ((rtx
));
359 static rtx simplify_set
PARAMS ((rtx
));
360 static rtx simplify_logical
PARAMS ((rtx
, int));
361 static rtx expand_compound_operation
PARAMS ((rtx
));
362 static rtx expand_field_assignment
PARAMS ((rtx
));
363 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
364 rtx
, unsigned HOST_WIDE_INT
, int,
366 static rtx extract_left_shift
PARAMS ((rtx
, int));
367 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
368 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
369 unsigned HOST_WIDE_INT
*));
370 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
371 unsigned HOST_WIDE_INT
, rtx
, int));
372 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
373 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
374 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
375 static rtx make_field_assignment
PARAMS ((rtx
));
376 static rtx apply_distributive_law
PARAMS ((rtx
));
377 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
378 unsigned HOST_WIDE_INT
));
379 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
380 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
381 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
382 enum rtx_code
, HOST_WIDE_INT
,
383 enum machine_mode
, int *));
384 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
386 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
387 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
388 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
390 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
391 static void update_table_tick
PARAMS ((rtx
));
392 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
393 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
394 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
395 static void record_dead_and_set_regs
PARAMS ((rtx
));
396 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
397 static rtx get_last_value
PARAMS ((rtx
));
398 static int use_crosses_set_p
PARAMS ((rtx
, int));
399 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
400 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
401 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
402 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
403 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
404 static void distribute_links
PARAMS ((rtx
));
405 static void mark_used_regs_combine
PARAMS ((rtx
));
406 static int insn_cuid
PARAMS ((rtx
));
407 static void record_promoted_value
PARAMS ((rtx
, rtx
));
408 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
409 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into
, newval
)
424 if (oldval
== newval
)
428 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
430 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
434 buf
->old_contents
.r
= oldval
;
437 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into
, newval
)
448 unsigned int *into
, newval
;
451 unsigned int oldval
= *into
;
453 if (oldval
== newval
)
457 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
459 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
463 buf
->old_contents
.i
= oldval
;
466 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f
, nregs
)
481 register rtx insn
, next
;
486 register rtx links
, nextlinks
;
488 int new_direct_jump_p
= 0;
490 combine_attempts
= 0;
493 combine_successes
= 0;
495 combine_max_regno
= nregs
;
497 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
498 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
500 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
502 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
503 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
504 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
505 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
506 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
507 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
509 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs
* sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
522 if (INSN_UID (insn
) > i
)
525 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
528 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid
= 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn
= NULL_RTX
;
552 setup_incoming_promotions ();
554 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
555 sbitmap_zero (refresh_blocks
);
558 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
560 uid_cuid
[INSN_UID (insn
)] = ++i
;
566 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
568 record_dead_and_set_regs (insn
);
571 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
572 if (REG_NOTE_KIND (links
) == REG_INC
)
573 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
578 if (GET_CODE (insn
) == CODE_LABEL
)
582 nonzero_sign_valid
= 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block
= -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block
+ 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
602 if (GET_CODE (insn
) == CODE_LABEL
)
605 else if (INSN_P (insn
))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn
, PATTERN (insn
));
611 /* Try this insn with each insn it links back to. */
613 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
614 if ((next
= try_combine (insn
, XEXP (links
, 0),
615 NULL_RTX
, &new_direct_jump_p
)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
622 rtx link
= XEXP (links
, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in persuing this chain any further. */
626 if (GET_CODE (link
) == NOTE
)
629 for (nextlinks
= LOG_LINKS (link
);
631 nextlinks
= XEXP (nextlinks
, 1))
632 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 &new_direct_jump_p
)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn
) == JUMP_INSN
647 && (prev
= prev_nonnote_insn (insn
)) != 0
648 && GET_CODE (prev
) == INSN
649 && sets_cc0_p (PATTERN (prev
)))
651 if ((next
= try_combine (insn
, prev
,
652 NULL_RTX
, &new_direct_jump_p
)) != 0)
655 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
656 nextlinks
= XEXP (nextlinks
, 1))
657 if ((next
= try_combine (insn
, prev
,
659 &new_direct_jump_p
)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn
) == INSN
665 && (prev
= prev_nonnote_insn (insn
)) != 0
666 && GET_CODE (prev
) == INSN
667 && sets_cc0_p (PATTERN (prev
))
668 && GET_CODE (PATTERN (insn
)) == SET
669 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
671 if ((next
= try_combine (insn
, prev
,
672 NULL_RTX
, &new_direct_jump_p
)) != 0)
675 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
676 nextlinks
= XEXP (nextlinks
, 1))
677 if ((next
= try_combine (insn
, prev
,
679 &new_direct_jump_p
)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
687 if (GET_CODE (XEXP (links
, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
689 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
690 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
691 && GET_CODE (prev
) == INSN
692 && sets_cc0_p (PATTERN (prev
))
693 && (next
= try_combine (insn
, XEXP (links
, 0),
694 prev
, &new_direct_jump_p
)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
701 for (nextlinks
= XEXP (links
, 1); nextlinks
;
702 nextlinks
= XEXP (nextlinks
, 1))
703 if ((next
= try_combine (insn
, XEXP (links
, 0),
705 &new_direct_jump_p
)) != 0)
708 if (GET_CODE (insn
) != NOTE
)
709 record_dead_and_set_regs (insn
);
718 compute_bb_for_insn (get_max_uid ());
719 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
724 sbitmap_free (refresh_blocks
);
725 free (reg_nonzero_bits
);
726 free (reg_sign_bit_copies
);
727 free (reg_last_death
);
729 free (reg_last_set_value
);
730 free (reg_last_set_table_tick
);
731 free (reg_last_set_label
);
732 free (reg_last_set_invalid
);
733 free (reg_last_set_mode
);
734 free (reg_last_set_nonzero_bits
);
735 free (reg_last_set_sign_bit_copies
);
739 struct undo
*undo
, *next
;
740 for (undo
= undobuf
.frees
; undo
; undo
= next
)
748 total_attempts
+= combine_attempts
;
749 total_merges
+= combine_merges
;
750 total_extras
+= combine_extras
;
751 total_successes
+= combine_successes
;
753 nonzero_sign_valid
= 0;
755 /* Make recognizer allow volatile MEMs again. */
758 return new_direct_jump_p
;
761 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
764 init_reg_last_arrays ()
766 unsigned int nregs
= combine_max_regno
;
768 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
769 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
770 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
771 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
772 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
773 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
774 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
775 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
776 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
779 /* Set up any promoted values for incoming argument registers. */
782 setup_incoming_promotions ()
784 #ifdef PROMOTE_FUNCTION_ARGS
787 enum machine_mode mode
;
789 rtx first
= get_insns ();
791 #ifndef OUTGOING_REGNO
792 #define OUTGOING_REGNO(N) N
794 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
795 /* Check whether this register can hold an incoming pointer
796 argument. FUNCTION_ARG_REGNO_P tests outgoing register
797 numbers, so translate if necessary due to register windows. */
798 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
799 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
802 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
805 gen_rtx_CLOBBER (mode
, const0_rtx
)));
810 /* Called via note_stores. If X is a pseudo that is narrower than
811 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
813 If we are setting only a portion of X and we can't figure out what
814 portion, assume all bits will be used since we don't know what will
817 Similarly, set how many bits of X are known to be copies of the sign bit
818 at all locations in the function. This is the smallest number implied
822 set_nonzero_bits_and_sign_copies (x
, set
, data
)
825 void *data ATTRIBUTE_UNUSED
;
829 if (GET_CODE (x
) == REG
830 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
831 /* If this register is undefined at the start of the file, we can't
832 say what its contents were. */
833 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
834 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
836 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
838 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
839 reg_sign_bit_copies
[REGNO (x
)] = 1;
843 /* If this is a complex assignment, see if we can convert it into a
844 simple assignment. */
845 set
= expand_field_assignment (set
);
847 /* If this is a simple assignment, or we have a paradoxical SUBREG,
848 set what we know about X. */
850 if (SET_DEST (set
) == x
851 || (GET_CODE (SET_DEST (set
)) == SUBREG
852 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
853 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
854 && SUBREG_REG (SET_DEST (set
)) == x
))
856 rtx src
= SET_SRC (set
);
858 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
859 /* If X is narrower than a word and SRC is a non-negative
860 constant that would appear negative in the mode of X,
861 sign-extend it for use in reg_nonzero_bits because some
862 machines (maybe most) will actually do the sign-extension
863 and this is the conservative approach.
865 ??? For 2.5, try to tighten up the MD files in this regard
866 instead of this kludge. */
868 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
869 && GET_CODE (src
) == CONST_INT
871 && 0 != (INTVAL (src
)
873 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
874 src
= GEN_INT (INTVAL (src
)
875 | ((HOST_WIDE_INT
) (-1)
876 << GET_MODE_BITSIZE (GET_MODE (x
))));
879 reg_nonzero_bits
[REGNO (x
)]
880 |= nonzero_bits (src
, nonzero_bits_mode
);
881 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
882 if (reg_sign_bit_copies
[REGNO (x
)] == 0
883 || reg_sign_bit_copies
[REGNO (x
)] > num
)
884 reg_sign_bit_copies
[REGNO (x
)] = num
;
888 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
889 reg_sign_bit_copies
[REGNO (x
)] = 1;
894 /* See if INSN can be combined into I3. PRED and SUCC are optionally
895 insns that were previously combined into I3 or that will be combined
896 into the merger of INSN and I3.
898 Return 0 if the combination is not allowed for any reason.
900 If the combination is allowed, *PDEST will be set to the single
901 destination of INSN and *PSRC to the single source, and this function
905 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
908 rtx pred ATTRIBUTE_UNUSED
;
913 rtx set
= 0, src
, dest
;
918 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
919 && next_active_insn (succ
) == i3
)
920 : next_active_insn (insn
) == i3
);
922 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
923 or a PARALLEL consisting of such a SET and CLOBBERs.
925 If INSN has CLOBBER parallel parts, ignore them for our processing.
926 By definition, these happen during the execution of the insn. When it
927 is merged with another insn, all bets are off. If they are, in fact,
928 needed and aren't also supplied in I3, they may be added by
929 recog_for_combine. Otherwise, it won't match.
931 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
934 Get the source and destination of INSN. If more than one, can't
937 if (GET_CODE (PATTERN (insn
)) == SET
)
938 set
= PATTERN (insn
);
939 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
940 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
942 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
944 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
946 switch (GET_CODE (elt
))
948 /* This is important to combine floating point insns
951 /* Combining an isolated USE doesn't make sense.
952 We depend here on combinable_i3_pat to reject them. */
953 /* The code below this loop only verifies that the inputs of
954 the SET in INSN do not change. We call reg_set_between_p
955 to verify that the REG in the USE does not change betweeen
957 If the USE in INSN was for a pseudo register, the matching
958 insn pattern will likely match any register; combining this
959 with any other USE would only be safe if we knew that the
960 used registers have identical values, or if there was
961 something to tell them apart, e.g. different modes. For
962 now, we forgo such compilcated tests and simply disallow
963 combining of USES of pseudo registers with any other USE. */
964 if (GET_CODE (XEXP (elt
, 0)) == REG
965 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
967 rtx i3pat
= PATTERN (i3
);
968 int i
= XVECLEN (i3pat
, 0) - 1;
969 unsigned int regno
= REGNO (XEXP (elt
, 0));
973 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
975 if (GET_CODE (i3elt
) == USE
976 && GET_CODE (XEXP (i3elt
, 0)) == REG
977 && (REGNO (XEXP (i3elt
, 0)) == regno
978 ? reg_set_between_p (XEXP (elt
, 0),
979 PREV_INSN (insn
), i3
)
980 : regno
>= FIRST_PSEUDO_REGISTER
))
987 /* We can ignore CLOBBERs. */
992 /* Ignore SETs whose result isn't used but not those that
993 have side-effects. */
994 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
995 && ! side_effects_p (elt
))
998 /* If we have already found a SET, this is a second one and
999 so we cannot combine with this insn. */
1007 /* Anything else means we can't combine. */
1013 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1014 so don't do anything with it. */
1015 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1024 set
= expand_field_assignment (set
);
1025 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1027 /* Don't eliminate a store in the stack pointer. */
1028 if (dest
== stack_pointer_rtx
1029 /* If we couldn't eliminate a field assignment, we can't combine. */
1030 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1031 /* Don't combine with an insn that sets a register to itself if it has
1032 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1033 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1034 /* Can't merge an ASM_OPERANDS. */
1035 || GET_CODE (src
) == ASM_OPERANDS
1036 /* Can't merge a function call. */
1037 || GET_CODE (src
) == CALL
1038 /* Don't eliminate a function call argument. */
1039 || (GET_CODE (i3
) == CALL_INSN
1040 && (find_reg_fusage (i3
, USE
, dest
)
1041 || (GET_CODE (dest
) == REG
1042 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1043 && global_regs
[REGNO (dest
)])))
1044 /* Don't substitute into an incremented register. */
1045 || FIND_REG_INC_NOTE (i3
, dest
)
1046 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1048 /* Don't combine the end of a libcall into anything. */
1049 /* ??? This gives worse code, and appears to be unnecessary, since no
1050 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1051 use REG_RETVAL notes for noconflict blocks, but other code here
1052 makes sure that those insns don't disappear. */
1053 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1055 /* Make sure that DEST is not used after SUCC but before I3. */
1056 || (succ
&& ! all_adjacent
1057 && reg_used_between_p (dest
, succ
, i3
))
1058 /* Make sure that the value that is to be substituted for the register
1059 does not use any registers whose values alter in between. However,
1060 If the insns are adjacent, a use can't cross a set even though we
1061 think it might (this can happen for a sequence of insns each setting
1062 the same destination; reg_last_set of that register might point to
1063 a NOTE). If INSN has a REG_EQUIV note, the register is always
1064 equivalent to the memory so the substitution is valid even if there
1065 are intervening stores. Also, don't move a volatile asm or
1066 UNSPEC_VOLATILE across any other insns. */
1068 && (((GET_CODE (src
) != MEM
1069 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1070 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1071 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1072 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1073 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1074 better register allocation by not doing the combine. */
1075 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1076 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1077 /* Don't combine across a CALL_INSN, because that would possibly
1078 change whether the life span of some REGs crosses calls or not,
1079 and it is a pain to update that information.
1080 Exception: if source is a constant, moving it later can't hurt.
1081 Accept that special case, because it helps -fforce-addr a lot. */
1082 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1085 /* DEST must either be a REG or CC0. */
1086 if (GET_CODE (dest
) == REG
)
1088 /* If register alignment is being enforced for multi-word items in all
1089 cases except for parameters, it is possible to have a register copy
1090 insn referencing a hard register that is not allowed to contain the
1091 mode being copied and which would not be valid as an operand of most
1092 insns. Eliminate this problem by not combining with such an insn.
1094 Also, on some machines we don't want to extend the life of a hard
1097 if (GET_CODE (src
) == REG
1098 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1099 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1100 /* Don't extend the life of a hard register unless it is
1101 user variable (if we have few registers) or it can't
1102 fit into the desired register (meaning something special
1104 Also avoid substituting a return register into I3, because
1105 reload can't handle a conflict with constraints of other
1107 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1108 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1111 else if (GET_CODE (dest
) != CC0
)
1114 /* Don't substitute for a register intended as a clobberable operand.
1115 Similarly, don't substitute an expression containing a register that
1116 will be clobbered in I3. */
1117 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1118 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1119 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1120 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1122 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1125 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1126 or not), reject, unless nothing volatile comes between it and I3 */
1128 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1130 /* Make sure succ doesn't contain a volatile reference. */
1131 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1134 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1135 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1139 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1140 to be an explicit register variable, and was chosen for a reason. */
1142 if (GET_CODE (src
) == ASM_OPERANDS
1143 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1146 /* If there are any volatile insns between INSN and I3, reject, because
1147 they might affect machine state. */
1149 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1150 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1153 /* If INSN or I2 contains an autoincrement or autodecrement,
1154 make sure that register is not used between there and I3,
1155 and not already used in I3 either.
1156 Also insist that I3 not be a jump; if it were one
1157 and the incremented register were spilled, we would lose. */
1160 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1161 if (REG_NOTE_KIND (link
) == REG_INC
1162 && (GET_CODE (i3
) == JUMP_INSN
1163 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1164 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1169 /* Don't combine an insn that follows a CC0-setting insn.
1170 An insn that uses CC0 must not be separated from the one that sets it.
1171 We do, however, allow I2 to follow a CC0-setting insn if that insn
1172 is passed as I1; in that case it will be deleted also.
1173 We also allow combining in this case if all the insns are adjacent
1174 because that would leave the two CC0 insns adjacent as well.
1175 It would be more logical to test whether CC0 occurs inside I1 or I2,
1176 but that would be much slower, and this ought to be equivalent. */
1178 p
= prev_nonnote_insn (insn
);
1179 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1184 /* If we get here, we have passed all the tests and the combination is
1193 /* Check if PAT is an insn - or a part of it - used to set up an
1194 argument for a function in a hard register. */
1197 sets_function_arg_p (pat
)
1203 switch (GET_CODE (pat
))
1206 return sets_function_arg_p (PATTERN (pat
));
1209 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1210 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1216 inner_dest
= SET_DEST (pat
);
1217 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1218 || GET_CODE (inner_dest
) == SUBREG
1219 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1220 inner_dest
= XEXP (inner_dest
, 0);
1222 return (GET_CODE (inner_dest
) == REG
1223 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1224 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1233 /* LOC is the location within I3 that contains its pattern or the component
1234 of a PARALLEL of the pattern. We validate that it is valid for combining.
1236 One problem is if I3 modifies its output, as opposed to replacing it
1237 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1238 so would produce an insn that is not equivalent to the original insns.
1242 (set (reg:DI 101) (reg:DI 100))
1243 (set (subreg:SI (reg:DI 101) 0) <foo>)
1245 This is NOT equivalent to:
1247 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1248 (set (reg:DI 101) (reg:DI 100))])
1250 Not only does this modify 100 (in which case it might still be valid
1251 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1253 We can also run into a problem if I2 sets a register that I1
1254 uses and I1 gets directly substituted into I3 (not via I2). In that
1255 case, we would be getting the wrong value of I2DEST into I3, so we
1256 must reject the combination. This case occurs when I2 and I1 both
1257 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1258 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1259 of a SET must prevent combination from occurring.
1261 Before doing the above check, we first try to expand a field assignment
1262 into a set of logical operations.
1264 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1265 we place a register that is both set and used within I3. If more than one
1266 such register is detected, we fail.
1268 Return 1 if the combination is valid, zero otherwise. */
1271 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1277 rtx
*pi3dest_killed
;
1281 if (GET_CODE (x
) == SET
)
1283 rtx set
= expand_field_assignment (x
);
1284 rtx dest
= SET_DEST (set
);
1285 rtx src
= SET_SRC (set
);
1286 rtx inner_dest
= dest
;
1289 rtx inner_src
= src
;
1294 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1295 || GET_CODE (inner_dest
) == SUBREG
1296 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1297 inner_dest
= XEXP (inner_dest
, 0);
1299 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1302 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1303 || GET_CODE (inner_src
) == SUBREG
1304 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1305 inner_src
= XEXP (inner_src
, 0);
1307 /* If it is better that two different modes keep two different pseudos,
1308 avoid combining them. This avoids producing the following pattern
1310 (set (subreg:SI (reg/v:QI 21) 0)
1311 (lshiftrt:SI (reg/v:SI 20)
1313 If that were made, reload could not handle the pair of
1314 reg 20/21, since it would try to get any GENERAL_REGS
1315 but some of them don't handle QImode. */
1317 if (rtx_equal_p (inner_src
, i2dest
)
1318 && GET_CODE (inner_dest
) == REG
1319 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1323 /* Check for the case where I3 modifies its output, as
1325 if ((inner_dest
!= dest
1326 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1327 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1329 /* This is the same test done in can_combine_p except we can't test
1330 all_adjacent; we don't have to, since this instruction will stay
1331 in place, thus we are not considering increasing the lifetime of
1334 Also, if this insn sets a function argument, combining it with
1335 something that might need a spill could clobber a previous
1336 function argument; the all_adjacent test in can_combine_p also
1337 checks this; here, we do a more specific test for this case. */
1339 || (GET_CODE (inner_dest
) == REG
1340 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1341 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1342 GET_MODE (inner_dest
))))
1343 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1346 /* If DEST is used in I3, it is being killed in this insn,
1347 so record that for later.
1348 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1349 STACK_POINTER_REGNUM, since these are always considered to be
1350 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1351 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1352 && reg_referenced_p (dest
, PATTERN (i3
))
1353 && REGNO (dest
) != FRAME_POINTER_REGNUM
1354 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1355 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1357 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1358 && (REGNO (dest
) != ARG_POINTER_REGNUM
1359 || ! fixed_regs
[REGNO (dest
)])
1361 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1363 if (*pi3dest_killed
)
1366 *pi3dest_killed
= dest
;
1370 else if (GET_CODE (x
) == PARALLEL
)
1374 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1375 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1376 i1_not_in_src
, pi3dest_killed
))
1383 /* Return 1 if X is an arithmetic expression that contains a multiplication
1384 and division. We don't count multiplications by powers of two here. */
1390 switch (GET_CODE (x
))
1392 case MOD
: case DIV
: case UMOD
: case UDIV
:
1396 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1397 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1399 switch (GET_RTX_CLASS (GET_CODE (x
)))
1401 case 'c': case '<': case '2':
1402 return contains_muldiv (XEXP (x
, 0))
1403 || contains_muldiv (XEXP (x
, 1));
1406 return contains_muldiv (XEXP (x
, 0));
1414 /* Determine whether INSN can be used in a combination. Return nonzero if
1415 not. This is used in try_combine to detect early some cases where we
1416 can't perform combinations. */
1419 cant_combine_insn_p (insn
)
1425 /* If this isn't really an insn, we can't do anything.
1426 This can occur when flow deletes an insn that it has merged into an
1427 auto-increment address. */
1428 if (! INSN_P (insn
))
1431 /* Never combine loads and stores involving hard regs. The register
1432 allocator can usually handle such reg-reg moves by tying. If we allow
1433 the combiner to make substitutions of hard regs, we risk aborting in
1434 reload on machines that have SMALL_REGISTER_CLASSES.
1435 As an exception, we allow combinations involving fixed regs; these are
1436 not available to the register allocator so there's no risk involved. */
1438 set
= single_set (insn
);
1441 src
= SET_SRC (set
);
1442 dest
= SET_DEST (set
);
1443 if (GET_CODE (src
) == SUBREG
)
1444 src
= SUBREG_REG (src
);
1445 if (GET_CODE (dest
) == SUBREG
)
1446 dest
= SUBREG_REG (dest
);
1447 if (REG_P (src
) && REG_P (dest
)
1448 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1449 && ! fixed_regs
[REGNO (src
)])
1450 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1451 && ! fixed_regs
[REGNO (dest
)])))
1457 /* Try to combine the insns I1 and I2 into I3.
1458 Here I1 and I2 appear earlier than I3.
1459 I1 can be zero; then we combine just I2 into I3.
1461 It we are combining three insns and the resulting insn is not recognized,
1462 try splitting it into two insns. If that happens, I2 and I3 are retained
1463 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1466 Return 0 if the combination does not work. Then nothing is changed.
1467 If we did the combination, return the insn at which combine should
1470 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1471 new direct jump instruction. */
1474 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1475 register rtx i3
, i2
, i1
;
1476 register int *new_direct_jump_p
;
1478 /* New patterns for I3 and I2, respectively. */
1479 rtx newpat
, newi2pat
= 0;
1480 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1481 int added_sets_1
, added_sets_2
;
1482 /* Total number of SETs to put into I3. */
1484 /* Nonzero is I2's body now appears in I3. */
1486 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1487 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1488 /* Contains I3 if the destination of I3 is used in its source, which means
1489 that the old life of I3 is being killed. If that usage is placed into
1490 I2 and not in I3, a REG_DEAD note must be made. */
1491 rtx i3dest_killed
= 0;
1492 /* SET_DEST and SET_SRC of I2 and I1. */
1493 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1494 /* PATTERN (I2), or a copy of it in certain cases. */
1496 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1497 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1498 int i1_feeds_i3
= 0;
1499 /* Notes that must be added to REG_NOTES in I3 and I2. */
1500 rtx new_i3_notes
, new_i2_notes
;
1501 /* Notes that we substituted I3 into I2 instead of the normal case. */
1502 int i3_subst_into_i2
= 0;
1503 /* Notes that I1, I2 or I3 is a MULT operation. */
1511 /* Exit early if one of the insns involved can't be used for
1513 if (cant_combine_insn_p (i3
)
1514 || cant_combine_insn_p (i2
)
1515 || (i1
&& cant_combine_insn_p (i1
))
1516 /* We also can't do anything if I3 has a
1517 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1520 /* ??? This gives worse code, and appears to be unnecessary, since no
1521 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1522 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1528 undobuf
.other_insn
= 0;
1530 /* Reset the hard register usage information. */
1531 CLEAR_HARD_REG_SET (newpat_used_regs
);
1533 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1534 code below, set I1 to be the earlier of the two insns. */
1535 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1536 temp
= i1
, i1
= i2
, i2
= temp
;
1538 added_links_insn
= 0;
1540 /* First check for one important special-case that the code below will
1541 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1542 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1543 we may be able to replace that destination with the destination of I3.
1544 This occurs in the common code where we compute both a quotient and
1545 remainder into a structure, in which case we want to do the computation
1546 directly into the structure to avoid register-register copies.
1548 Note that this case handles both multiple sets in I2 and also
1549 cases where I2 has a number of CLOBBER or PARALLELs.
1551 We make very conservative checks below and only try to handle the
1552 most common cases of this. For example, we only handle the case
1553 where I2 and I3 are adjacent to avoid making difficult register
1556 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1557 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1558 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1559 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1560 && GET_CODE (PATTERN (i2
)) == PARALLEL
1561 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1562 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1563 below would need to check what is inside (and reg_overlap_mentioned_p
1564 doesn't support those codes anyway). Don't allow those destinations;
1565 the resulting insn isn't likely to be recognized anyway. */
1566 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1567 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1568 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1569 SET_DEST (PATTERN (i3
)))
1570 && next_real_insn (i2
) == i3
)
1572 rtx p2
= PATTERN (i2
);
1574 /* Make sure that the destination of I3,
1575 which we are going to substitute into one output of I2,
1576 is not used within another output of I2. We must avoid making this:
1577 (parallel [(set (mem (reg 69)) ...)
1578 (set (reg 69) ...)])
1579 which is not well-defined as to order of actions.
1580 (Besides, reload can't handle output reloads for this.)
1582 The problem can also happen if the dest of I3 is a memory ref,
1583 if another dest in I2 is an indirect memory ref. */
1584 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1585 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1586 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1587 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1588 SET_DEST (XVECEXP (p2
, 0, i
))))
1591 if (i
== XVECLEN (p2
, 0))
1592 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1593 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1594 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1595 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1600 subst_low_cuid
= INSN_CUID (i2
);
1602 added_sets_2
= added_sets_1
= 0;
1603 i2dest
= SET_SRC (PATTERN (i3
));
1605 /* Replace the dest in I2 with our dest and make the resulting
1606 insn the new pattern for I3. Then skip to where we
1607 validate the pattern. Everything was set up above. */
1608 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1609 SET_DEST (PATTERN (i3
)));
1612 i3_subst_into_i2
= 1;
1613 goto validate_replacement
;
1617 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1618 one of those words to another constant, merge them by making a new
1621 && (temp
= single_set (i2
)) != 0
1622 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1623 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1624 && GET_CODE (SET_DEST (temp
)) == REG
1625 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1626 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1627 && GET_CODE (PATTERN (i3
)) == SET
1628 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1629 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1630 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1631 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1632 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1634 HOST_WIDE_INT lo
, hi
;
1636 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1637 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1640 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1641 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1644 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1646 /* We don't handle the case of the target word being wider
1647 than a host wide int. */
1648 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1651 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1652 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1654 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1655 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1656 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1658 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1659 >> (HOST_BITS_PER_WIDE_INT
- 1));
1661 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1662 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1663 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1664 (INTVAL (SET_SRC (PATTERN (i3
)))));
1666 hi
= lo
< 0 ? -1 : 0;
1669 /* We don't handle the case of the higher word not fitting
1670 entirely in either hi or lo. */
1675 subst_low_cuid
= INSN_CUID (i2
);
1676 added_sets_2
= added_sets_1
= 0;
1677 i2dest
= SET_DEST (temp
);
1679 SUBST (SET_SRC (temp
),
1680 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1682 newpat
= PATTERN (i2
);
1683 goto validate_replacement
;
1687 /* If we have no I1 and I2 looks like:
1688 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1690 make up a dummy I1 that is
1693 (set (reg:CC X) (compare:CC Y (const_int 0)))
1695 (We can ignore any trailing CLOBBERs.)
1697 This undoes a previous combination and allows us to match a branch-and-
1700 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1701 && XVECLEN (PATTERN (i2
), 0) >= 2
1702 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1703 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1705 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1706 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1707 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1708 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1709 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1710 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1712 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1713 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1718 /* We make I1 with the same INSN_UID as I2. This gives it
1719 the same INSN_CUID for value tracking. Our fake I1 will
1720 never appear in the insn stream so giving it the same INSN_UID
1721 as I2 will not cause a problem. */
1723 subst_prev_insn
= i1
1724 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1725 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1728 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1729 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1730 SET_DEST (PATTERN (i1
)));
1735 /* Verify that I2 and I1 are valid for combining. */
1736 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1737 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1743 /* Record whether I2DEST is used in I2SRC and similarly for the other
1744 cases. Knowing this will help in register status updating below. */
1745 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1746 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1747 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1749 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1751 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1753 /* Ensure that I3's pattern can be the destination of combines. */
1754 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1755 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1762 /* See if any of the insns is a MULT operation. Unless one is, we will
1763 reject a combination that is, since it must be slower. Be conservative
1765 if (GET_CODE (i2src
) == MULT
1766 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1767 || (GET_CODE (PATTERN (i3
)) == SET
1768 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1771 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1772 We used to do this EXCEPT in one case: I3 has a post-inc in an
1773 output operand. However, that exception can give rise to insns like
1775 which is a famous insn on the PDP-11 where the value of r3 used as the
1776 source was model-dependent. Avoid this sort of thing. */
1779 if (!(GET_CODE (PATTERN (i3
)) == SET
1780 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1781 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1782 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1783 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1784 /* It's not the exception. */
1787 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1788 if (REG_NOTE_KIND (link
) == REG_INC
1789 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1791 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1798 /* See if the SETs in I1 or I2 need to be kept around in the merged
1799 instruction: whenever the value set there is still needed past I3.
1800 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1802 For the SET in I1, we have two cases: If I1 and I2 independently
1803 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1804 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1805 in I1 needs to be kept around unless I1DEST dies or is set in either
1806 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1807 I1DEST. If so, we know I1 feeds into I2. */
1809 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1812 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1813 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1815 /* If the set in I2 needs to be kept around, we must make a copy of
1816 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1817 PATTERN (I2), we are only substituting for the original I1DEST, not into
1818 an already-substituted copy. This also prevents making self-referential
1819 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1822 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1823 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1827 i2pat
= copy_rtx (i2pat
);
1831 /* Substitute in the latest insn for the regs set by the earlier ones. */
1833 maxreg
= max_reg_num ();
1837 /* It is possible that the source of I2 or I1 may be performing an
1838 unneeded operation, such as a ZERO_EXTEND of something that is known
1839 to have the high part zero. Handle that case by letting subst look at
1840 the innermost one of them.
1842 Another way to do this would be to have a function that tries to
1843 simplify a single insn instead of merging two or more insns. We don't
1844 do this because of the potential of infinite loops and because
1845 of the potential extra memory required. However, doing it the way
1846 we are is a bit of a kludge and doesn't catch all cases.
1848 But only do this if -fexpensive-optimizations since it slows things down
1849 and doesn't usually win. */
1851 if (flag_expensive_optimizations
)
1853 /* Pass pc_rtx so no substitutions are done, just simplifications.
1854 The cases that we are interested in here do not involve the few
1855 cases were is_replaced is checked. */
1858 subst_low_cuid
= INSN_CUID (i1
);
1859 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1863 subst_low_cuid
= INSN_CUID (i2
);
1864 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1869 /* Many machines that don't use CC0 have insns that can both perform an
1870 arithmetic operation and set the condition code. These operations will
1871 be represented as a PARALLEL with the first element of the vector
1872 being a COMPARE of an arithmetic operation with the constant zero.
1873 The second element of the vector will set some pseudo to the result
1874 of the same arithmetic operation. If we simplify the COMPARE, we won't
1875 match such a pattern and so will generate an extra insn. Here we test
1876 for this case, where both the comparison and the operation result are
1877 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1878 I2SRC. Later we will make the PARALLEL that contains I2. */
1880 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1881 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1882 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1883 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1885 #ifdef EXTRA_CC_MODES
1887 enum machine_mode compare_mode
;
1890 newpat
= PATTERN (i3
);
1891 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1895 #ifdef EXTRA_CC_MODES
1896 /* See if a COMPARE with the operand we substituted in should be done
1897 with the mode that is currently being used. If not, do the same
1898 processing we do in `subst' for a SET; namely, if the destination
1899 is used only once, try to replace it with a register of the proper
1900 mode and also replace the COMPARE. */
1901 if (undobuf
.other_insn
== 0
1902 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1903 &undobuf
.other_insn
))
1904 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1906 != GET_MODE (SET_DEST (newpat
))))
1908 unsigned int regno
= REGNO (SET_DEST (newpat
));
1909 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1911 if (regno
< FIRST_PSEUDO_REGISTER
1912 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1913 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1915 if (regno
>= FIRST_PSEUDO_REGISTER
)
1916 SUBST (regno_reg_rtx
[regno
], new_dest
);
1918 SUBST (SET_DEST (newpat
), new_dest
);
1919 SUBST (XEXP (*cc_use
, 0), new_dest
);
1920 SUBST (SET_SRC (newpat
),
1921 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1924 undobuf
.other_insn
= 0;
1931 n_occurrences
= 0; /* `subst' counts here */
1933 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1934 need to make a unique copy of I2SRC each time we substitute it
1935 to avoid self-referential rtl. */
1937 subst_low_cuid
= INSN_CUID (i2
);
1938 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1939 ! i1_feeds_i3
&& i1dest_in_i1src
);
1941 /* Record whether i2's body now appears within i3's body. */
1942 i2_is_used
= n_occurrences
;
1945 /* If we already got a failure, don't try to do more. Otherwise,
1946 try to substitute in I1 if we have it. */
1948 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1950 /* Before we can do this substitution, we must redo the test done
1951 above (see detailed comments there) that ensures that I1DEST
1952 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1954 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1962 subst_low_cuid
= INSN_CUID (i1
);
1963 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1966 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1967 to count all the ways that I2SRC and I1SRC can be used. */
1968 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1969 && i2_is_used
+ added_sets_2
> 1)
1970 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1971 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1973 /* Fail if we tried to make a new register (we used to abort, but there's
1974 really no reason to). */
1975 || max_reg_num () != maxreg
1976 /* Fail if we couldn't do something and have a CLOBBER. */
1977 || GET_CODE (newpat
) == CLOBBER
1978 /* Fail if this new pattern is a MULT and we didn't have one before
1979 at the outer level. */
1980 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1987 /* If the actions of the earlier insns must be kept
1988 in addition to substituting them into the latest one,
1989 we must make a new PARALLEL for the latest insn
1990 to hold additional the SETs. */
1992 if (added_sets_1
|| added_sets_2
)
1996 if (GET_CODE (newpat
) == PARALLEL
)
1998 rtvec old
= XVEC (newpat
, 0);
1999 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2000 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2001 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2002 sizeof (old
->elem
[0]) * old
->num_elem
);
2007 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2008 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2009 XVECEXP (newpat
, 0, 0) = old
;
2013 XVECEXP (newpat
, 0, --total_sets
)
2014 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2015 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2019 /* If there is no I1, use I2's body as is. We used to also not do
2020 the subst call below if I2 was substituted into I3,
2021 but that could lose a simplification. */
2023 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2025 /* See comment where i2pat is assigned. */
2026 XVECEXP (newpat
, 0, --total_sets
)
2027 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2031 /* We come here when we are replacing a destination in I2 with the
2032 destination of I3. */
2033 validate_replacement
:
2035 /* Note which hard regs this insn has as inputs. */
2036 mark_used_regs_combine (newpat
);
2038 /* Is the result of combination a valid instruction? */
2039 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2041 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2042 the second SET's destination is a register that is unused. In that case,
2043 we just need the first SET. This can occur when simplifying a divmod
2044 insn. We *must* test for this case here because the code below that
2045 splits two independent SETs doesn't handle this case correctly when it
2046 updates the register status. Also check the case where the first
2047 SET's destination is unused. That would not cause incorrect code, but
2048 does cause an unneeded insn to remain. */
2050 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2051 && XVECLEN (newpat
, 0) == 2
2052 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2053 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2054 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2055 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2056 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2057 && asm_noperands (newpat
) < 0)
2059 newpat
= XVECEXP (newpat
, 0, 0);
2060 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2063 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2064 && XVECLEN (newpat
, 0) == 2
2065 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2066 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2067 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2068 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2069 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2070 && asm_noperands (newpat
) < 0)
2072 newpat
= XVECEXP (newpat
, 0, 1);
2073 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2076 /* If we were combining three insns and the result is a simple SET
2077 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2078 insns. There are two ways to do this. It can be split using a
2079 machine-specific method (like when you have an addition of a large
2080 constant) or by combine in the function find_split_point. */
2082 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2083 && asm_noperands (newpat
) < 0)
2085 rtx m_split
, *split
;
2086 rtx ni2dest
= i2dest
;
2088 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2089 use I2DEST as a scratch register will help. In the latter case,
2090 convert I2DEST to the mode of the source of NEWPAT if we can. */
2092 m_split
= split_insns (newpat
, i3
);
2094 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2095 inputs of NEWPAT. */
2097 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2098 possible to try that as a scratch reg. This would require adding
2099 more code to make it work though. */
2101 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2103 /* If I2DEST is a hard register or the only use of a pseudo,
2104 we can change its mode. */
2105 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2106 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2107 && GET_CODE (i2dest
) == REG
2108 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2109 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2110 && ! REG_USERVAR_P (i2dest
))))
2111 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2114 m_split
= split_insns (gen_rtx_PARALLEL
2116 gen_rtvec (2, newpat
,
2117 gen_rtx_CLOBBER (VOIDmode
,
2120 /* If the split with the mode-changed register didn't work, try
2121 the original register. */
2122 if (! m_split
&& ni2dest
!= i2dest
)
2125 m_split
= split_insns (gen_rtx_PARALLEL
2127 gen_rtvec (2, newpat
,
2128 gen_rtx_CLOBBER (VOIDmode
,
2134 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2136 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2137 if (insn_code_number
>= 0)
2140 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2141 && XVECLEN (m_split
, 0) == 2
2142 && (next_real_insn (i2
) == i3
2143 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2147 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2148 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2150 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2151 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2153 /* In case we changed the mode of I2DEST, replace it in the
2154 pseudo-register table here. We can't do it above in case this
2155 code doesn't get executed and we do a split the other way. */
2157 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2158 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2160 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2162 /* If I2 or I3 has multiple SETs, we won't know how to track
2163 register status, so don't use these insns. If I2's destination
2164 is used between I2 and I3, we also can't use these insns. */
2166 if (i2_code_number
>= 0 && i2set
&& i3set
2167 && (next_real_insn (i2
) == i3
2168 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2169 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2171 if (insn_code_number
>= 0)
2174 /* It is possible that both insns now set the destination of I3.
2175 If so, we must show an extra use of it. */
2177 if (insn_code_number
>= 0)
2179 rtx new_i3_dest
= SET_DEST (i3set
);
2180 rtx new_i2_dest
= SET_DEST (i2set
);
2182 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2183 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2184 || GET_CODE (new_i3_dest
) == SUBREG
)
2185 new_i3_dest
= XEXP (new_i3_dest
, 0);
2187 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2188 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2189 || GET_CODE (new_i2_dest
) == SUBREG
)
2190 new_i2_dest
= XEXP (new_i2_dest
, 0);
2192 if (GET_CODE (new_i3_dest
) == REG
2193 && GET_CODE (new_i2_dest
) == REG
2194 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2195 REG_N_SETS (REGNO (new_i2_dest
))++;
2199 /* If we can split it and use I2DEST, go ahead and see if that
2200 helps things be recognized. Verify that none of the registers
2201 are set between I2 and I3. */
2202 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2204 && GET_CODE (i2dest
) == REG
2206 /* We need I2DEST in the proper mode. If it is a hard register
2207 or the only use of a pseudo, we can change its mode. */
2208 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2209 || GET_MODE (*split
) == VOIDmode
2210 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2211 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2212 && ! REG_USERVAR_P (i2dest
)))
2213 && (next_real_insn (i2
) == i3
2214 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2215 /* We can't overwrite I2DEST if its value is still used by
2217 && ! reg_referenced_p (i2dest
, newpat
))
2219 rtx newdest
= i2dest
;
2220 enum rtx_code split_code
= GET_CODE (*split
);
2221 enum machine_mode split_mode
= GET_MODE (*split
);
2223 /* Get NEWDEST as a register in the proper mode. We have already
2224 validated that we can do this. */
2225 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2227 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2229 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2230 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2233 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2234 an ASHIFT. This can occur if it was inside a PLUS and hence
2235 appeared to be a memory address. This is a kludge. */
2236 if (split_code
== MULT
2237 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2238 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2240 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2241 XEXP (*split
, 0), GEN_INT (i
)));
2242 /* Update split_code because we may not have a multiply
2244 split_code
= GET_CODE (*split
);
2247 #ifdef INSN_SCHEDULING
2248 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2249 be written as a ZERO_EXTEND. */
2250 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2251 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2252 SUBREG_REG (*split
)));
2255 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2256 SUBST (*split
, newdest
);
2257 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2259 /* If the split point was a MULT and we didn't have one before,
2260 don't use one now. */
2261 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2262 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2266 /* Check for a case where we loaded from memory in a narrow mode and
2267 then sign extended it, but we need both registers. In that case,
2268 we have a PARALLEL with both loads from the same memory location.
2269 We can split this into a load from memory followed by a register-register
2270 copy. This saves at least one insn, more if register allocation can
2273 We cannot do this if the destination of the second assignment is
2274 a register that we have already assumed is zero-extended. Similarly
2275 for a SUBREG of such a register. */
2277 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2278 && GET_CODE (newpat
) == PARALLEL
2279 && XVECLEN (newpat
, 0) == 2
2280 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2281 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2282 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2283 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2284 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2285 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2287 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2288 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2289 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2290 (GET_CODE (temp
) == REG
2291 && reg_nonzero_bits
[REGNO (temp
)] != 0
2292 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2293 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2294 && (reg_nonzero_bits
[REGNO (temp
)]
2295 != GET_MODE_MASK (word_mode
))))
2296 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2297 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2298 (GET_CODE (temp
) == REG
2299 && reg_nonzero_bits
[REGNO (temp
)] != 0
2300 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2301 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2302 && (reg_nonzero_bits
[REGNO (temp
)]
2303 != GET_MODE_MASK (word_mode
)))))
2304 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2305 SET_SRC (XVECEXP (newpat
, 0, 1)))
2306 && ! find_reg_note (i3
, REG_UNUSED
,
2307 SET_DEST (XVECEXP (newpat
, 0, 0))))
2311 newi2pat
= XVECEXP (newpat
, 0, 0);
2312 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2313 newpat
= XVECEXP (newpat
, 0, 1);
2314 SUBST (SET_SRC (newpat
),
2315 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2316 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2318 if (i2_code_number
>= 0)
2319 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2321 if (insn_code_number
>= 0)
2326 /* If we will be able to accept this, we have made a change to the
2327 destination of I3. This can invalidate a LOG_LINKS pointing
2328 to I3. No other part of combine.c makes such a transformation.
2330 The new I3 will have a destination that was previously the
2331 destination of I1 or I2 and which was used in i2 or I3. Call
2332 distribute_links to make a LOG_LINK from the next use of
2333 that destination. */
2335 PATTERN (i3
) = newpat
;
2336 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2338 /* I3 now uses what used to be its destination and which is
2339 now I2's destination. That means we need a LOG_LINK from
2340 I3 to I2. But we used to have one, so we still will.
2342 However, some later insn might be using I2's dest and have
2343 a LOG_LINK pointing at I3. We must remove this link.
2344 The simplest way to remove the link is to point it at I1,
2345 which we know will be a NOTE. */
2347 for (insn
= NEXT_INSN (i3
);
2348 insn
&& (this_basic_block
== n_basic_blocks
- 1
2349 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2350 insn
= NEXT_INSN (insn
))
2352 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2354 for (link
= LOG_LINKS (insn
); link
;
2355 link
= XEXP (link
, 1))
2356 if (XEXP (link
, 0) == i3
)
2357 XEXP (link
, 0) = i1
;
2365 /* Similarly, check for a case where we have a PARALLEL of two independent
2366 SETs but we started with three insns. In this case, we can do the sets
2367 as two separate insns. This case occurs when some SET allows two
2368 other insns to combine, but the destination of that SET is still live. */
2370 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2371 && GET_CODE (newpat
) == PARALLEL
2372 && XVECLEN (newpat
, 0) == 2
2373 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2374 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2375 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2376 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2379 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2381 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2382 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2383 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2384 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2385 XVECEXP (newpat
, 0, 0))
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2387 XVECEXP (newpat
, 0, 1))
2388 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2389 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2391 /* Normally, it doesn't matter which of the two is done first,
2392 but it does if one references cc0. In that case, it has to
2395 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2397 newi2pat
= XVECEXP (newpat
, 0, 0);
2398 newpat
= XVECEXP (newpat
, 0, 1);
2403 newi2pat
= XVECEXP (newpat
, 0, 1);
2404 newpat
= XVECEXP (newpat
, 0, 0);
2407 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2409 if (i2_code_number
>= 0)
2410 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2413 /* If it still isn't recognized, fail and change things back the way they
2415 if ((insn_code_number
< 0
2416 /* Is the result a reasonable ASM_OPERANDS? */
2417 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2423 /* If we had to change another insn, make sure it is valid also. */
2424 if (undobuf
.other_insn
)
2426 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2427 rtx new_other_notes
;
2430 CLEAR_HARD_REG_SET (newpat_used_regs
);
2432 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2435 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2441 PATTERN (undobuf
.other_insn
) = other_pat
;
2443 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2444 are still valid. Then add any non-duplicate notes added by
2445 recog_for_combine. */
2446 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2448 next
= XEXP (note
, 1);
2450 if (REG_NOTE_KIND (note
) == REG_UNUSED
2451 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2453 if (GET_CODE (XEXP (note
, 0)) == REG
)
2454 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2456 remove_note (undobuf
.other_insn
, note
);
2460 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2461 if (GET_CODE (XEXP (note
, 0)) == REG
)
2462 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2464 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2465 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2468 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2469 they are adjacent to each other or not. */
2471 rtx p
= prev_nonnote_insn (i3
);
2472 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2473 && sets_cc0_p (newi2pat
))
2481 /* We now know that we can do this combination. Merge the insns and
2482 update the status of registers and LOG_LINKS. */
2485 rtx i3notes
, i2notes
, i1notes
= 0;
2486 rtx i3links
, i2links
, i1links
= 0;
2489 /* Compute which registers we expect to eliminate. newi2pat may be setting
2490 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2491 same as i3dest, in which case newi2pat may be setting i1dest. */
2492 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2493 || i2dest_in_i2src
|| i2dest_in_i1src
2495 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2496 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2499 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2501 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2502 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2504 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2506 /* Ensure that we do not have something that should not be shared but
2507 occurs multiple times in the new insns. Check this by first
2508 resetting all the `used' flags and then copying anything is shared. */
2510 reset_used_flags (i3notes
);
2511 reset_used_flags (i2notes
);
2512 reset_used_flags (i1notes
);
2513 reset_used_flags (newpat
);
2514 reset_used_flags (newi2pat
);
2515 if (undobuf
.other_insn
)
2516 reset_used_flags (PATTERN (undobuf
.other_insn
));
2518 i3notes
= copy_rtx_if_shared (i3notes
);
2519 i2notes
= copy_rtx_if_shared (i2notes
);
2520 i1notes
= copy_rtx_if_shared (i1notes
);
2521 newpat
= copy_rtx_if_shared (newpat
);
2522 newi2pat
= copy_rtx_if_shared (newi2pat
);
2523 if (undobuf
.other_insn
)
2524 reset_used_flags (PATTERN (undobuf
.other_insn
));
2526 INSN_CODE (i3
) = insn_code_number
;
2527 PATTERN (i3
) = newpat
;
2528 if (undobuf
.other_insn
)
2529 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2531 /* We had one special case above where I2 had more than one set and
2532 we replaced a destination of one of those sets with the destination
2533 of I3. In that case, we have to update LOG_LINKS of insns later
2534 in this basic block. Note that this (expensive) case is rare.
2536 Also, in this case, we must pretend that all REG_NOTEs for I2
2537 actually came from I3, so that REG_UNUSED notes from I2 will be
2538 properly handled. */
2540 if (i3_subst_into_i2
)
2542 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2543 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2544 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2545 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2546 && ! find_reg_note (i2
, REG_UNUSED
,
2547 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2548 for (temp
= NEXT_INSN (i2
);
2549 temp
&& (this_basic_block
== n_basic_blocks
- 1
2550 || BLOCK_HEAD (this_basic_block
) != temp
);
2551 temp
= NEXT_INSN (temp
))
2552 if (temp
!= i3
&& INSN_P (temp
))
2553 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2554 if (XEXP (link
, 0) == i2
)
2555 XEXP (link
, 0) = i3
;
2560 while (XEXP (link
, 1))
2561 link
= XEXP (link
, 1);
2562 XEXP (link
, 1) = i2notes
;
2576 INSN_CODE (i2
) = i2_code_number
;
2577 PATTERN (i2
) = newi2pat
;
2581 PUT_CODE (i2
, NOTE
);
2582 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2583 NOTE_SOURCE_FILE (i2
) = 0;
2590 PUT_CODE (i1
, NOTE
);
2591 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2592 NOTE_SOURCE_FILE (i1
) = 0;
2595 /* Get death notes for everything that is now used in either I3 or
2596 I2 and used to die in a previous insn. If we built two new
2597 patterns, move from I1 to I2 then I2 to I3 so that we get the
2598 proper movement on registers that I2 modifies. */
2602 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2603 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2606 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2609 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2611 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2614 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2617 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2620 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2623 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2624 know these are REG_UNUSED and want them to go to the desired insn,
2625 so we always pass it as i3. We have not counted the notes in
2626 reg_n_deaths yet, so we need to do so now. */
2628 if (newi2pat
&& new_i2_notes
)
2630 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2631 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2632 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2634 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2639 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2640 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2641 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2643 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2646 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2647 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2648 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2649 in that case, it might delete I2. Similarly for I2 and I1.
2650 Show an additional death due to the REG_DEAD note we make here. If
2651 we discard it in distribute_notes, we will decrement it again. */
2655 if (GET_CODE (i3dest_killed
) == REG
)
2656 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2658 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2659 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2661 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2665 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2669 if (i2dest_in_i2src
)
2671 if (GET_CODE (i2dest
) == REG
)
2672 REG_N_DEATHS (REGNO (i2dest
))++;
2674 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2675 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2676 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2679 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2680 NULL_RTX
, NULL_RTX
);
2683 if (i1dest_in_i1src
)
2685 if (GET_CODE (i1dest
) == REG
)
2686 REG_N_DEATHS (REGNO (i1dest
))++;
2688 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2689 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2690 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2693 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2694 NULL_RTX
, NULL_RTX
);
2697 distribute_links (i3links
);
2698 distribute_links (i2links
);
2699 distribute_links (i1links
);
2701 if (GET_CODE (i2dest
) == REG
)
2704 rtx i2_insn
= 0, i2_val
= 0, set
;
2706 /* The insn that used to set this register doesn't exist, and
2707 this life of the register may not exist either. See if one of
2708 I3's links points to an insn that sets I2DEST. If it does,
2709 that is now the last known value for I2DEST. If we don't update
2710 this and I2 set the register to a value that depended on its old
2711 contents, we will get confused. If this insn is used, thing
2712 will be set correctly in combine_instructions. */
2714 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2715 if ((set
= single_set (XEXP (link
, 0))) != 0
2716 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2717 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2719 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2721 /* If the reg formerly set in I2 died only once and that was in I3,
2722 zero its use count so it won't make `reload' do any work. */
2724 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2725 && ! i2dest_in_i2src
)
2727 regno
= REGNO (i2dest
);
2728 REG_N_SETS (regno
)--;
2732 if (i1
&& GET_CODE (i1dest
) == REG
)
2735 rtx i1_insn
= 0, i1_val
= 0, set
;
2737 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2738 if ((set
= single_set (XEXP (link
, 0))) != 0
2739 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2740 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2742 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2744 regno
= REGNO (i1dest
);
2745 if (! added_sets_1
&& ! i1dest_in_i1src
)
2746 REG_N_SETS (regno
)--;
2749 /* Update reg_nonzero_bits et al for any changes that may have been made
2750 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2751 important. Because newi2pat can affect nonzero_bits of newpat */
2753 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2754 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2756 /* Set new_direct_jump_p if a new return or simple jump instruction
2759 If I3 is now an unconditional jump, ensure that it has a
2760 BARRIER following it since it may have initially been a
2761 conditional jump. It may also be the last nonnote insn. */
2763 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2765 *new_direct_jump_p
= 1;
2767 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2768 || GET_CODE (temp
) != BARRIER
)
2769 emit_barrier_after (i3
);
2773 combine_successes
++;
2776 /* Clear this here, so that subsequent get_last_value calls are not
2778 subst_prev_insn
= NULL_RTX
;
2780 if (added_links_insn
2781 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2782 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2783 return added_links_insn
;
2785 return newi2pat
? i2
: i3
;
2788 /* Undo all the modifications recorded in undobuf. */
2793 struct undo
*undo
, *next
;
2795 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2799 *undo
->where
.i
= undo
->old_contents
.i
;
2801 *undo
->where
.r
= undo
->old_contents
.r
;
2803 undo
->next
= undobuf
.frees
;
2804 undobuf
.frees
= undo
;
2809 /* Clear this here, so that subsequent get_last_value calls are not
2811 subst_prev_insn
= NULL_RTX
;
2814 /* We've committed to accepting the changes we made. Move all
2815 of the undos to the free list. */
2820 struct undo
*undo
, *next
;
2822 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2825 undo
->next
= undobuf
.frees
;
2826 undobuf
.frees
= undo
;
2832 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2833 where we have an arithmetic expression and return that point. LOC will
2836 try_combine will call this function to see if an insn can be split into
2840 find_split_point (loc
, insn
)
2845 enum rtx_code code
= GET_CODE (x
);
2847 unsigned HOST_WIDE_INT len
= 0;
2848 HOST_WIDE_INT pos
= 0;
2850 rtx inner
= NULL_RTX
;
2852 /* First special-case some codes. */
2856 #ifdef INSN_SCHEDULING
2857 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2859 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2862 return find_split_point (&SUBREG_REG (x
), insn
);
2866 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2867 using LO_SUM and HIGH. */
2868 if (GET_CODE (XEXP (x
, 0)) == CONST
2869 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2872 gen_rtx_LO_SUM (Pmode
,
2873 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2875 return &XEXP (XEXP (x
, 0), 0);
2879 /* If we have a PLUS whose second operand is a constant and the
2880 address is not valid, perhaps will can split it up using
2881 the machine-specific way to split large constants. We use
2882 the first pseudo-reg (one of the virtual regs) as a placeholder;
2883 it will not remain in the result. */
2884 if (GET_CODE (XEXP (x
, 0)) == PLUS
2885 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2886 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2888 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2889 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2892 /* This should have produced two insns, each of which sets our
2893 placeholder. If the source of the second is a valid address,
2894 we can make put both sources together and make a split point
2897 if (seq
&& XVECLEN (seq
, 0) == 2
2898 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2899 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2900 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2901 && ! reg_mentioned_p (reg
,
2902 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2903 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2904 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2905 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2906 && memory_address_p (GET_MODE (x
),
2907 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2909 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2910 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2912 /* Replace the placeholder in SRC2 with SRC1. If we can
2913 find where in SRC2 it was placed, that can become our
2914 split point and we can replace this address with SRC2.
2915 Just try two obvious places. */
2917 src2
= replace_rtx (src2
, reg
, src1
);
2919 if (XEXP (src2
, 0) == src1
)
2920 split
= &XEXP (src2
, 0);
2921 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2922 && XEXP (XEXP (src2
, 0), 0) == src1
)
2923 split
= &XEXP (XEXP (src2
, 0), 0);
2927 SUBST (XEXP (x
, 0), src2
);
2932 /* If that didn't work, perhaps the first operand is complex and
2933 needs to be computed separately, so make a split point there.
2934 This will occur on machines that just support REG + CONST
2935 and have a constant moved through some previous computation. */
2937 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2938 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2939 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2941 return &XEXP (XEXP (x
, 0), 0);
2947 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2948 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2949 we need to put the operand into a register. So split at that
2952 if (SET_DEST (x
) == cc0_rtx
2953 && GET_CODE (SET_SRC (x
)) != COMPARE
2954 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2955 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2956 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2957 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2958 return &SET_SRC (x
);
2961 /* See if we can split SET_SRC as it stands. */
2962 split
= find_split_point (&SET_SRC (x
), insn
);
2963 if (split
&& split
!= &SET_SRC (x
))
2966 /* See if we can split SET_DEST as it stands. */
2967 split
= find_split_point (&SET_DEST (x
), insn
);
2968 if (split
&& split
!= &SET_DEST (x
))
2971 /* See if this is a bitfield assignment with everything constant. If
2972 so, this is an IOR of an AND, so split it into that. */
2973 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2974 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2975 <= HOST_BITS_PER_WIDE_INT
)
2976 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2977 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2978 && GET_CODE (SET_SRC (x
)) == CONST_INT
2979 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2980 + INTVAL (XEXP (SET_DEST (x
), 2)))
2981 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2982 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2984 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2985 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2986 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2987 rtx dest
= XEXP (SET_DEST (x
), 0);
2988 enum machine_mode mode
= GET_MODE (dest
);
2989 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2991 if (BITS_BIG_ENDIAN
)
2992 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2996 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2999 gen_binary (IOR
, mode
,
3000 gen_binary (AND
, mode
, dest
,
3001 GEN_INT (~(mask
<< pos
)
3002 & GET_MODE_MASK (mode
))),
3003 GEN_INT (src
<< pos
)));
3005 SUBST (SET_DEST (x
), dest
);
3007 split
= find_split_point (&SET_SRC (x
), insn
);
3008 if (split
&& split
!= &SET_SRC (x
))
3012 /* Otherwise, see if this is an operation that we can split into two.
3013 If so, try to split that. */
3014 code
= GET_CODE (SET_SRC (x
));
3019 /* If we are AND'ing with a large constant that is only a single
3020 bit and the result is only being used in a context where we
3021 need to know if it is zero or non-zero, replace it with a bit
3022 extraction. This will avoid the large constant, which might
3023 have taken more than one insn to make. If the constant were
3024 not a valid argument to the AND but took only one insn to make,
3025 this is no worse, but if it took more than one insn, it will
3028 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3029 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3030 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3031 && GET_CODE (SET_DEST (x
)) == REG
3032 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*)0)) != 0
3033 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3034 && XEXP (*split
, 0) == SET_DEST (x
)
3035 && XEXP (*split
, 1) == const0_rtx
)
3037 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3038 XEXP (SET_SRC (x
), 0),
3039 pos
, NULL_RTX
, 1, 1, 0, 0);
3040 if (extraction
!= 0)
3042 SUBST (SET_SRC (x
), extraction
);
3043 return find_split_point (loc
, insn
);
3049 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3050 is known to be on, this can be converted into a NEG of a shift. */
3051 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3052 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3053 && 1 <= (pos
= exact_log2
3054 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3055 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3057 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3061 gen_rtx_LSHIFTRT (mode
,
3062 XEXP (SET_SRC (x
), 0),
3065 split
= find_split_point (&SET_SRC (x
), insn
);
3066 if (split
&& split
!= &SET_SRC (x
))
3072 inner
= XEXP (SET_SRC (x
), 0);
3074 /* We can't optimize if either mode is a partial integer
3075 mode as we don't know how many bits are significant
3077 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3078 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3082 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3088 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3089 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3091 inner
= XEXP (SET_SRC (x
), 0);
3092 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3093 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3095 if (BITS_BIG_ENDIAN
)
3096 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3097 unsignedp
= (code
== ZERO_EXTRACT
);
3105 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3107 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3109 /* For unsigned, we have a choice of a shift followed by an
3110 AND or two shifts. Use two shifts for field sizes where the
3111 constant might be too large. We assume here that we can
3112 always at least get 8-bit constants in an AND insn, which is
3113 true for every current RISC. */
3115 if (unsignedp
&& len
<= 8)
3120 (mode
, gen_lowpart_for_combine (mode
, inner
),
3122 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3124 split
= find_split_point (&SET_SRC (x
), insn
);
3125 if (split
&& split
!= &SET_SRC (x
))
3132 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3133 gen_rtx_ASHIFT (mode
,
3134 gen_lowpart_for_combine (mode
, inner
),
3135 GEN_INT (GET_MODE_BITSIZE (mode
)
3137 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3139 split
= find_split_point (&SET_SRC (x
), insn
);
3140 if (split
&& split
!= &SET_SRC (x
))
3145 /* See if this is a simple operation with a constant as the second
3146 operand. It might be that this constant is out of range and hence
3147 could be used as a split point. */
3148 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3149 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3150 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3151 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3152 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3153 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3154 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3156 return &XEXP (SET_SRC (x
), 1);
3158 /* Finally, see if this is a simple operation with its first operand
3159 not in a register. The operation might require this operand in a
3160 register, so return it as a split point. We can always do this
3161 because if the first operand were another operation, we would have
3162 already found it as a split point. */
3163 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3165 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3166 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3167 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3168 return &XEXP (SET_SRC (x
), 0);
3174 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3175 it is better to write this as (not (ior A B)) so we can split it.
3176 Similarly for IOR. */
3177 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3180 gen_rtx_NOT (GET_MODE (x
),
3181 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3183 XEXP (XEXP (x
, 0), 0),
3184 XEXP (XEXP (x
, 1), 0))));
3185 return find_split_point (loc
, insn
);
3188 /* Many RISC machines have a large set of logical insns. If the
3189 second operand is a NOT, put it first so we will try to split the
3190 other operand first. */
3191 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3193 rtx tem
= XEXP (x
, 0);
3194 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3195 SUBST (XEXP (x
, 1), tem
);
3203 /* Otherwise, select our actions depending on our rtx class. */
3204 switch (GET_RTX_CLASS (code
))
3206 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3208 split
= find_split_point (&XEXP (x
, 2), insn
);
3211 /* ... fall through ... */
3215 split
= find_split_point (&XEXP (x
, 1), insn
);
3218 /* ... fall through ... */
3220 /* Some machines have (and (shift ...) ...) insns. If X is not
3221 an AND, but XEXP (X, 0) is, use it as our split point. */
3222 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3223 return &XEXP (x
, 0);
3225 split
= find_split_point (&XEXP (x
, 0), insn
);
3231 /* Otherwise, we don't have a split point. */
3235 /* Throughout X, replace FROM with TO, and return the result.
3236 The result is TO if X is FROM;
3237 otherwise the result is X, but its contents may have been modified.
3238 If they were modified, a record was made in undobuf so that
3239 undo_all will (among other things) return X to its original state.
3241 If the number of changes necessary is too much to record to undo,
3242 the excess changes are not made, so the result is invalid.
3243 The changes already made can still be undone.
3244 undobuf.num_undo is incremented for such changes, so by testing that
3245 the caller can tell whether the result is valid.
3247 `n_occurrences' is incremented each time FROM is replaced.
3249 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3251 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3252 by copying if `n_occurrences' is non-zero. */
3255 subst (x
, from
, to
, in_dest
, unique_copy
)
3256 register rtx x
, from
, to
;
3260 register enum rtx_code code
= GET_CODE (x
);
3261 enum machine_mode op0_mode
= VOIDmode
;
3262 register const char *fmt
;
3263 register int len
, i
;
3266 /* Two expressions are equal if they are identical copies of a shared
3267 RTX or if they are both registers with the same register number
3270 #define COMBINE_RTX_EQUAL_P(X,Y) \
3272 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3273 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3275 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3278 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3281 /* If X and FROM are the same register but different modes, they will
3282 not have been seen as equal above. However, flow.c will make a
3283 LOG_LINKS entry for that case. If we do nothing, we will try to
3284 rerecognize our original insn and, when it succeeds, we will
3285 delete the feeding insn, which is incorrect.
3287 So force this insn not to match in this (rare) case. */
3288 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3289 && REGNO (x
) == REGNO (from
))
3290 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3292 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3293 of which may contain things that can be combined. */
3294 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3297 /* It is possible to have a subexpression appear twice in the insn.
3298 Suppose that FROM is a register that appears within TO.
3299 Then, after that subexpression has been scanned once by `subst',
3300 the second time it is scanned, TO may be found. If we were
3301 to scan TO here, we would find FROM within it and create a
3302 self-referent rtl structure which is completely wrong. */
3303 if (COMBINE_RTX_EQUAL_P (x
, to
))
3306 /* Parallel asm_operands need special attention because all of the
3307 inputs are shared across the arms. Furthermore, unsharing the
3308 rtl results in recognition failures. Failure to handle this case
3309 specially can result in circular rtl.
3311 Solve this by doing a normal pass across the first entry of the
3312 parallel, and only processing the SET_DESTs of the subsequent
3315 if (code
== PARALLEL
3316 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3317 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3319 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3321 /* If this substitution failed, this whole thing fails. */
3322 if (GET_CODE (new) == CLOBBER
3323 && XEXP (new, 0) == const0_rtx
)
3326 SUBST (XVECEXP (x
, 0, 0), new);
3328 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3330 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3332 if (GET_CODE (dest
) != REG
3333 && GET_CODE (dest
) != CC0
3334 && GET_CODE (dest
) != PC
)
3336 new = subst (dest
, from
, to
, 0, unique_copy
);
3338 /* If this substitution failed, this whole thing fails. */
3339 if (GET_CODE (new) == CLOBBER
3340 && XEXP (new, 0) == const0_rtx
)
3343 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3349 len
= GET_RTX_LENGTH (code
);
3350 fmt
= GET_RTX_FORMAT (code
);
3352 /* We don't need to process a SET_DEST that is a register, CC0,
3353 or PC, so set up to skip this common case. All other cases
3354 where we want to suppress replacing something inside a
3355 SET_SRC are handled via the IN_DEST operand. */
3357 && (GET_CODE (SET_DEST (x
)) == REG
3358 || GET_CODE (SET_DEST (x
)) == CC0
3359 || GET_CODE (SET_DEST (x
)) == PC
))
3362 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3365 op0_mode
= GET_MODE (XEXP (x
, 0));
3367 for (i
= 0; i
< len
; i
++)
3372 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3374 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3376 new = (unique_copy
&& n_occurrences
3377 ? copy_rtx (to
) : to
);
3382 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3385 /* If this substitution failed, this whole thing
3387 if (GET_CODE (new) == CLOBBER
3388 && XEXP (new, 0) == const0_rtx
)
3392 SUBST (XVECEXP (x
, i
, j
), new);
3395 else if (fmt
[i
] == 'e')
3397 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3399 /* In general, don't install a subreg involving two
3400 modes not tieable. It can worsen register
3401 allocation, and can even make invalid reload
3402 insns, since the reg inside may need to be copied
3403 from in the outside mode, and that may be invalid
3404 if it is an fp reg copied in integer mode.
3406 We allow two exceptions to this: It is valid if
3407 it is inside another SUBREG and the mode of that
3408 SUBREG and the mode of the inside of TO is
3409 tieable and it is valid if X is a SET that copies
3412 if (GET_CODE (to
) == SUBREG
3413 && ! MODES_TIEABLE_P (GET_MODE (to
),
3414 GET_MODE (SUBREG_REG (to
)))
3415 && ! (code
== SUBREG
3416 && MODES_TIEABLE_P (GET_MODE (x
),
3417 GET_MODE (SUBREG_REG (to
))))
3419 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3422 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3424 #ifdef CLASS_CANNOT_CHANGE_MODE
3426 && GET_CODE (to
) == REG
3427 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3428 && (TEST_HARD_REG_BIT
3429 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3431 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3433 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3436 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3440 /* If we are in a SET_DEST, suppress most cases unless we
3441 have gone inside a MEM, in which case we want to
3442 simplify the address. We assume here that things that
3443 are actually part of the destination have their inner
3444 parts in the first expression. This is true for SUBREG,
3445 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3446 things aside from REG and MEM that should appear in a
3448 new = subst (XEXP (x
, i
), from
, to
,
3450 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3451 || code
== ZERO_EXTRACT
))
3453 && i
== 0), unique_copy
);
3455 /* If we found that we will have to reject this combination,
3456 indicate that by returning the CLOBBER ourselves, rather than
3457 an expression containing it. This will speed things up as
3458 well as prevent accidents where two CLOBBERs are considered
3459 to be equal, thus producing an incorrect simplification. */
3461 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3464 SUBST (XEXP (x
, i
), new);
3469 /* Try to simplify X. If the simplification changed the code, it is likely
3470 that further simplification will help, so loop, but limit the number
3471 of repetitions that will be performed. */
3473 for (i
= 0; i
< 4; i
++)
3475 /* If X is sufficiently simple, don't bother trying to do anything
3477 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3478 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3480 if (GET_CODE (x
) == code
)
3483 code
= GET_CODE (x
);
3485 /* We no longer know the original mode of operand 0 since we
3486 have changed the form of X) */
3487 op0_mode
= VOIDmode
;
3493 /* Simplify X, a piece of RTL. We just operate on the expression at the
3494 outer level; call `subst' to simplify recursively. Return the new
3497 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3498 will be the iteration even if an expression with a code different from
3499 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3502 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3504 enum machine_mode op0_mode
;
3508 enum rtx_code code
= GET_CODE (x
);
3509 enum machine_mode mode
= GET_MODE (x
);
3514 /* If this is a commutative operation, put a constant last and a complex
3515 expression first. We don't need to do this for comparisons here. */
3516 if (GET_RTX_CLASS (code
) == 'c'
3517 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3518 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3519 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3520 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3521 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3522 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3525 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3526 SUBST (XEXP (x
, 1), temp
);
3529 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3530 sign extension of a PLUS with a constant, reverse the order of the sign
3531 extension and the addition. Note that this not the same as the original
3532 code, but overflow is undefined for signed values. Also note that the
3533 PLUS will have been partially moved "inside" the sign-extension, so that
3534 the first operand of X will really look like:
3535 (ashiftrt (plus (ashift A C4) C5) C4).
3537 (plus (ashiftrt (ashift A C4) C2) C4)
3538 and replace the first operand of X with that expression. Later parts
3539 of this function may simplify the expression further.
3541 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3542 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3543 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3545 We do this to simplify address expressions. */
3547 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3548 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3549 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3550 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3551 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3552 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3553 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3554 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3555 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3556 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3557 XEXP (XEXP (x
, 0), 1))) != 0)
3560 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3561 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3562 INTVAL (XEXP (XEXP (x
, 0), 1)));
3564 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3565 INTVAL (XEXP (XEXP (x
, 0), 1)));
3567 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3570 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3571 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3572 things. Check for cases where both arms are testing the same
3575 Don't do anything if all operands are very simple. */
3577 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3578 || GET_RTX_CLASS (code
) == '<')
3579 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3580 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3581 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3583 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3584 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3585 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3587 || (GET_RTX_CLASS (code
) == '1'
3588 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3589 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3590 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3593 rtx cond
, true_rtx
, false_rtx
;
3595 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3597 /* If everything is a comparison, what we have is highly unlikely
3598 to be simpler, so don't use it. */
3599 && ! (GET_RTX_CLASS (code
) == '<'
3600 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3601 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3603 rtx cop1
= const0_rtx
;
3604 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3606 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3609 /* Simplify the alternative arms; this may collapse the true and
3610 false arms to store-flag values. */
3611 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3612 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3614 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3615 is unlikely to be simpler. */
3616 if (general_operand (true_rtx
, VOIDmode
)
3617 && general_operand (false_rtx
, VOIDmode
))
3619 /* Restarting if we generate a store-flag expression will cause
3620 us to loop. Just drop through in this case. */
3622 /* If the result values are STORE_FLAG_VALUE and zero, we can
3623 just make the comparison operation. */
3624 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3625 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3626 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
)
3627 x
= gen_binary (reverse_condition (cond_code
),
3630 /* Likewise, we can make the negate of a comparison operation
3631 if the result values are - STORE_FLAG_VALUE and zero. */
3632 else if (GET_CODE (true_rtx
) == CONST_INT
3633 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3634 && false_rtx
== const0_rtx
)
3635 x
= simplify_gen_unary (NEG
, mode
,
3636 gen_binary (cond_code
, mode
, cond
,
3639 else if (GET_CODE (false_rtx
) == CONST_INT
3640 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3641 && true_rtx
== const0_rtx
)
3642 x
= simplify_gen_unary (NEG
, mode
,
3643 gen_binary (reverse_condition
3648 return gen_rtx_IF_THEN_ELSE (mode
,
3649 gen_binary (cond_code
, VOIDmode
,
3651 true_rtx
, false_rtx
);
3653 code
= GET_CODE (x
);
3654 op0_mode
= VOIDmode
;
3659 /* Try to fold this expression in case we have constants that weren't
3662 switch (GET_RTX_CLASS (code
))
3665 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3669 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3670 if (cmp_mode
== VOIDmode
)
3672 cmp_mode
= GET_MODE (XEXP (x
, 1));
3673 if (cmp_mode
== VOIDmode
)
3674 cmp_mode
= op0_mode
;
3676 temp
= simplify_relational_operation (code
, cmp_mode
,
3677 XEXP (x
, 0), XEXP (x
, 1));
3679 #ifdef FLOAT_STORE_FLAG_VALUE
3680 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3682 if (temp
== const0_rtx
)
3683 temp
= CONST0_RTX (mode
);
3685 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3691 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3695 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3696 XEXP (x
, 1), XEXP (x
, 2));
3701 x
= temp
, code
= GET_CODE (temp
);
3703 /* First see if we can apply the inverse distributive law. */
3704 if (code
== PLUS
|| code
== MINUS
3705 || code
== AND
|| code
== IOR
|| code
== XOR
)
3707 x
= apply_distributive_law (x
);
3708 code
= GET_CODE (x
);
3711 /* If CODE is an associative operation not otherwise handled, see if we
3712 can associate some operands. This can win if they are constants or
3713 if they are logically related (i.e. (a & b) & a. */
3714 if ((code
== PLUS
|| code
== MINUS
3715 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3716 || code
== DIV
|| code
== UDIV
3717 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3718 && INTEGRAL_MODE_P (mode
))
3720 if (GET_CODE (XEXP (x
, 0)) == code
)
3722 rtx other
= XEXP (XEXP (x
, 0), 0);
3723 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3724 rtx inner_op1
= XEXP (x
, 1);
3727 /* Make sure we pass the constant operand if any as the second
3728 one if this is a commutative operation. */
3729 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3731 rtx tem
= inner_op0
;
3732 inner_op0
= inner_op1
;
3735 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3736 : code
== DIV
? MULT
3737 : code
== UDIV
? MULT
3739 mode
, inner_op0
, inner_op1
);
3741 /* For commutative operations, try the other pair if that one
3743 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3745 other
= XEXP (XEXP (x
, 0), 1);
3746 inner
= simplify_binary_operation (code
, mode
,
3747 XEXP (XEXP (x
, 0), 0),
3752 return gen_binary (code
, mode
, other
, inner
);
3756 /* A little bit of algebraic simplification here. */
3760 /* Ensure that our address has any ASHIFTs converted to MULT in case
3761 address-recognizing predicates are called later. */
3762 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3763 SUBST (XEXP (x
, 0), temp
);
3767 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3768 is paradoxical. If we can't do that safely, then it becomes
3769 something nonsensical so that this combination won't take place. */
3771 if (GET_CODE (SUBREG_REG (x
)) == MEM
3772 && (GET_MODE_SIZE (mode
)
3773 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3775 rtx inner
= SUBREG_REG (x
);
3776 int offset
= SUBREG_BYTE (x
);
3777 /* Don't change the mode of the MEM
3778 if that would change the meaning of the address. */
3779 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3780 || mode_dependent_address_p (XEXP (inner
, 0)))
3781 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3783 /* Note if the plus_constant doesn't make a valid address
3784 then this combination won't be accepted. */
3785 x
= gen_rtx_MEM (mode
,
3786 plus_constant (XEXP (inner
, 0), offset
));
3787 MEM_COPY_ATTRIBUTES (x
, inner
);
3791 /* If we are in a SET_DEST, these other cases can't apply. */
3795 /* Changing mode twice with SUBREG => just change it once,
3796 or not at all if changing back to starting mode. */
3797 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3800 enum machine_mode outer_mode
, inner_mode
;
3802 /* If the innermost mode is the same as the goal mode,
3803 and the low word is being referenced in both SUBREGs,
3804 return the innermost element. */
3805 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
))))
3807 int inner_word
= SUBREG_BYTE (SUBREG_REG (x
));
3808 int outer_word
= SUBREG_BYTE (x
);
3810 inner_word
= (inner_word
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
3811 outer_word
= (outer_word
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
3814 return SUBREG_REG (SUBREG_REG (x
));
3817 outer_mode
= GET_MODE (SUBREG_REG (x
));
3818 inner_mode
= GET_MODE (SUBREG_REG (SUBREG_REG (x
)));
3819 final_offset
= SUBREG_BYTE (x
) + SUBREG_BYTE (SUBREG_REG(x
));
3821 if ((WORDS_BIG_ENDIAN
|| BYTES_BIG_ENDIAN
)
3822 && GET_MODE_SIZE (outer_mode
) > GET_MODE_SIZE (mode
)
3823 && GET_MODE_SIZE (outer_mode
) > GET_MODE_SIZE (inner_mode
))
3825 /* Inner SUBREG is paradoxical, outer is not. On big endian
3826 we have to special case this. */
3827 if (SUBREG_BYTE (SUBREG_REG (x
)))
3828 abort(); /* Can a paradoxical subreg have nonzero offset? */
3829 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3830 final_offset
= SUBREG_BYTE (x
) - GET_MODE_SIZE (outer_mode
)
3831 + GET_MODE_SIZE (inner_mode
);
3832 else if (WORDS_BIG_ENDIAN
)
3833 final_offset
= (final_offset
% UNITS_PER_WORD
)
3834 + ((SUBREG_BYTE (x
) - GET_MODE_SIZE (outer_mode
)
3835 + GET_MODE_SIZE (inner_mode
))
3836 * UNITS_PER_WORD
) / UNITS_PER_WORD
;
3838 final_offset
= ((final_offset
* UNITS_PER_WORD
)
3840 + ((SUBREG_BYTE (x
) - GET_MODE_SIZE (outer_mode
)
3841 + GET_MODE_SIZE (inner_mode
))
3845 /* The SUBREG rules are that the byte offset must be
3846 some multiple of the toplevel SUBREG's mode. */
3847 final_offset
= (final_offset
/ GET_MODE_SIZE (mode
));
3848 final_offset
= (final_offset
* GET_MODE_SIZE (mode
));
3850 SUBST_INT (SUBREG_BYTE (x
), final_offset
);
3851 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3854 /* SUBREG of a hard register => just change the register number
3855 and/or mode. If the hard register is not valid in that mode,
3856 suppress this combination. If the hard register is the stack,
3857 frame, or argument pointer, leave this as a SUBREG. */
3859 if (GET_CODE (SUBREG_REG (x
)) == REG
3860 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3861 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3862 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3863 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3865 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3866 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3868 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3870 int final_regno
= subreg_hard_regno (x
, 0);
3872 if (HARD_REGNO_MODE_OK (final_regno
, mode
))
3873 return gen_rtx_REG (mode
, final_regno
);
3875 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3878 /* For a constant, try to pick up the part we want. Handle a full
3879 word and low-order part. Only do this if we are narrowing
3880 the constant; if it is being widened, we have no idea what
3881 the extra bits will have been set to. */
3883 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3884 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3885 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3886 && GET_MODE_CLASS (mode
) == MODE_INT
)
3888 temp
= operand_subword (SUBREG_REG (x
),
3889 (SUBREG_BYTE (x
) / UNITS_PER_WORD
),
3895 /* If we want a subreg of a constant, at offset 0,
3896 take the low bits. On a little-endian machine, that's
3897 always valid. On a big-endian machine, it's valid
3898 only if the constant's mode fits in one word. Note that we
3899 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3900 if (CONSTANT_P (SUBREG_REG (x
))
3901 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3902 || ! WORDS_BIG_ENDIAN
)
3903 ? SUBREG_BYTE (x
) == 0
3905 == (GET_MODE_SIZE (op0_mode
) - GET_MODE_SIZE (mode
))))
3906 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3907 && (! WORDS_BIG_ENDIAN
3908 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3909 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3911 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3912 since we are saying that the high bits don't matter. */
3913 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3914 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3916 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
3917 && (WORDS_BIG_ENDIAN
|| SUBREG_BYTE (x
) != 0))
3918 return constant_subword (SUBREG_REG (x
),
3919 SUBREG_BYTE (x
) / UNITS_PER_WORD
, mode
);
3920 return SUBREG_REG (x
);
3923 /* Note that we cannot do any narrowing for non-constants since
3924 we might have been counting on using the fact that some bits were
3925 zero. We now do this in the SET. */
3930 /* (not (plus X -1)) can become (neg X). */
3931 if (GET_CODE (XEXP (x
, 0)) == PLUS
3932 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3933 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3935 /* Similarly, (not (neg X)) is (plus X -1). */
3936 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3937 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3939 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3940 if (GET_CODE (XEXP (x
, 0)) == XOR
3941 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3942 && (temp
= simplify_unary_operation (NOT
, mode
,
3943 XEXP (XEXP (x
, 0), 1),
3945 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3947 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3948 other than 1, but that is not valid. We could do a similar
3949 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3950 but this doesn't seem common enough to bother with. */
3951 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3952 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3953 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3955 XEXP (XEXP (x
, 0), 1));
3957 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3958 && subreg_lowpart_p (XEXP (x
, 0))
3959 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3960 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3961 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3962 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3964 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3966 x
= gen_rtx_ROTATE (inner_mode
,
3967 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3969 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3970 return gen_lowpart_for_combine (mode
, x
);
3973 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3974 reversing the comparison code if valid. */
3975 if (STORE_FLAG_VALUE
== -1
3976 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3977 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3978 XEXP (XEXP (x
, 0), 1))))
3981 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3982 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3983 perform the above simplification. */
3985 if (STORE_FLAG_VALUE
== -1
3986 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3987 && XEXP (x
, 1) == const1_rtx
3988 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3989 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3990 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3992 /* Apply De Morgan's laws to reduce number of patterns for machines
3993 with negating logical insns (and-not, nand, etc.). If result has
3994 only one NOT, put it first, since that is how the patterns are
3997 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3999 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4000 enum machine_mode op_mode
;
4002 op_mode
= GET_MODE (in1
);
4003 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4005 op_mode
= GET_MODE (in2
);
4006 if (op_mode
== VOIDmode
)
4008 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4010 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4013 in2
= in1
; in1
= tem
;
4016 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4022 /* (neg (plus X 1)) can become (not X). */
4023 if (GET_CODE (XEXP (x
, 0)) == PLUS
4024 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
4025 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
4027 /* Similarly, (neg (not X)) is (plus X 1). */
4028 if (GET_CODE (XEXP (x
, 0)) == NOT
)
4029 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
4031 /* (neg (minus X Y)) can become (minus Y X). */
4032 if (GET_CODE (XEXP (x
, 0)) == MINUS
4033 && (! FLOAT_MODE_P (mode
)
4034 /* x-y != -(y-x) with IEEE floating point. */
4035 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4036 || flag_unsafe_math_optimizations
))
4037 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4038 XEXP (XEXP (x
, 0), 0));
4040 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4041 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4042 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4043 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4045 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4046 if we can then eliminate the NEG (e.g.,
4047 if the operand is a constant). */
4049 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4051 temp
= simplify_unary_operation (NEG
, mode
,
4052 XEXP (XEXP (x
, 0), 0), mode
);
4055 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
4060 temp
= expand_compound_operation (XEXP (x
, 0));
4062 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4063 replaced by (lshiftrt X C). This will convert
4064 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4066 if (GET_CODE (temp
) == ASHIFTRT
4067 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4068 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4069 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4070 INTVAL (XEXP (temp
, 1)));
4072 /* If X has only a single bit that might be nonzero, say, bit I, convert
4073 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4074 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4075 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4076 or a SUBREG of one since we'd be making the expression more
4077 complex if it was just a register. */
4079 if (GET_CODE (temp
) != REG
4080 && ! (GET_CODE (temp
) == SUBREG
4081 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4082 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4084 rtx temp1
= simplify_shift_const
4085 (NULL_RTX
, ASHIFTRT
, mode
,
4086 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4087 GET_MODE_BITSIZE (mode
) - 1 - i
),
4088 GET_MODE_BITSIZE (mode
) - 1 - i
);
4090 /* If all we did was surround TEMP with the two shifts, we
4091 haven't improved anything, so don't use it. Otherwise,
4092 we are better off with TEMP1. */
4093 if (GET_CODE (temp1
) != ASHIFTRT
4094 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4095 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4101 /* We can't handle truncation to a partial integer mode here
4102 because we don't know the real bitsize of the partial
4104 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4107 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4108 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4109 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4111 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4112 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4114 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4115 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4116 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4117 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4118 return XEXP (XEXP (x
, 0), 0);
4120 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4121 (OP:SI foo:SI) if OP is NEG or ABS. */
4122 if ((GET_CODE (XEXP (x
, 0)) == ABS
4123 || GET_CODE (XEXP (x
, 0)) == NEG
)
4124 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4125 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4126 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4127 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4128 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4130 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4132 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4133 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4134 && subreg_lowpart_p (XEXP (x
, 0)))
4135 return SUBREG_REG (XEXP (x
, 0));
4137 /* If we know that the value is already truncated, we can
4138 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4139 is nonzero for the corresponding modes. But don't do this
4140 for an (LSHIFTRT (MULT ...)) since this will cause problems
4141 with the umulXi3_highpart patterns. */
4142 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4143 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4144 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4145 >= GET_MODE_BITSIZE (mode
) + 1
4146 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4147 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4148 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4150 /* A truncate of a comparison can be replaced with a subreg if
4151 STORE_FLAG_VALUE permits. This is like the previous test,
4152 but it works even if the comparison is done in a mode larger
4153 than HOST_BITS_PER_WIDE_INT. */
4154 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4155 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4156 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4157 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4159 /* Similarly, a truncate of a register whose value is a
4160 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4162 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4163 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4164 && (temp
= get_last_value (XEXP (x
, 0)))
4165 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4166 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4170 case FLOAT_TRUNCATE
:
4171 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4172 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4173 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4174 return XEXP (XEXP (x
, 0), 0);
4176 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4177 (OP:SF foo:SF) if OP is NEG or ABS. */
4178 if ((GET_CODE (XEXP (x
, 0)) == ABS
4179 || GET_CODE (XEXP (x
, 0)) == NEG
)
4180 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4181 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4182 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4183 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4185 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4186 is (float_truncate:SF x). */
4187 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4188 && subreg_lowpart_p (XEXP (x
, 0))
4189 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4190 return SUBREG_REG (XEXP (x
, 0));
4195 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4196 using cc0, in which case we want to leave it as a COMPARE
4197 so we can distinguish it from a register-register-copy. */
4198 if (XEXP (x
, 1) == const0_rtx
)
4201 /* In IEEE floating point, x-0 is not the same as x. */
4202 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4203 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4204 || flag_unsafe_math_optimizations
)
4205 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4211 /* (const (const X)) can become (const X). Do it this way rather than
4212 returning the inner CONST since CONST can be shared with a
4214 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4215 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4220 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4221 can add in an offset. find_split_point will split this address up
4222 again if it doesn't match. */
4223 if (GET_CODE (XEXP (x
, 0)) == HIGH
4224 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4230 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4231 outermost. That's because that's the way indexed addresses are
4232 supposed to appear. This code used to check many more cases, but
4233 they are now checked elsewhere. */
4234 if (GET_CODE (XEXP (x
, 0)) == PLUS
4235 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4236 return gen_binary (PLUS
, mode
,
4237 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4239 XEXP (XEXP (x
, 0), 1));
4241 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4242 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4243 bit-field and can be replaced by either a sign_extend or a
4244 sign_extract. The `and' may be a zero_extend and the two
4245 <c>, -<c> constants may be reversed. */
4246 if (GET_CODE (XEXP (x
, 0)) == XOR
4247 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4248 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4249 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4250 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4251 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4252 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4253 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4254 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4255 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4256 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4257 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4258 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4259 == (unsigned int) i
+ 1))))
4260 return simplify_shift_const
4261 (NULL_RTX
, ASHIFTRT
, mode
,
4262 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4263 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4264 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4265 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4267 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4268 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4269 is 1. This produces better code than the alternative immediately
4271 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4272 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4273 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4274 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4275 XEXP (XEXP (x
, 0), 0),
4276 XEXP (XEXP (x
, 0), 1))))
4278 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4280 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4281 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4282 the bitsize of the mode - 1. This allows simplification of
4283 "a = (b & 8) == 0;" */
4284 if (XEXP (x
, 1) == constm1_rtx
4285 && GET_CODE (XEXP (x
, 0)) != REG
4286 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4287 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4288 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4289 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4290 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4291 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4292 GET_MODE_BITSIZE (mode
) - 1),
4293 GET_MODE_BITSIZE (mode
) - 1);
4295 /* If we are adding two things that have no bits in common, convert
4296 the addition into an IOR. This will often be further simplified,
4297 for example in cases like ((a & 1) + (a & 2)), which can
4300 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4301 && (nonzero_bits (XEXP (x
, 0), mode
)
4302 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4304 /* Try to simplify the expression further. */
4305 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4306 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4308 /* If we could, great. If not, do not go ahead with the IOR
4309 replacement, since PLUS appears in many special purpose
4310 address arithmetic instructions. */
4311 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4317 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4318 by reversing the comparison code if valid. */
4319 if (STORE_FLAG_VALUE
== 1
4320 && XEXP (x
, 0) == const1_rtx
4321 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4322 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4323 XEXP (XEXP (x
, 1), 0),
4324 XEXP (XEXP (x
, 1), 1))))
4327 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4328 (and <foo> (const_int pow2-1)) */
4329 if (GET_CODE (XEXP (x
, 1)) == AND
4330 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4331 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4332 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4333 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4334 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4336 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4338 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4339 return gen_binary (MINUS
, mode
,
4340 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4341 XEXP (XEXP (x
, 1), 0)),
4342 XEXP (XEXP (x
, 1), 1));
4346 /* If we have (mult (plus A B) C), apply the distributive law and then
4347 the inverse distributive law to see if things simplify. This
4348 occurs mostly in addresses, often when unrolling loops. */
4350 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4352 x
= apply_distributive_law
4353 (gen_binary (PLUS
, mode
,
4354 gen_binary (MULT
, mode
,
4355 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4356 gen_binary (MULT
, mode
,
4357 XEXP (XEXP (x
, 0), 1),
4358 copy_rtx (XEXP (x
, 1)))));
4360 if (GET_CODE (x
) != MULT
)
4366 /* If this is a divide by a power of two, treat it as a shift if
4367 its first operand is a shift. */
4368 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4369 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4370 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4371 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4372 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4373 || GET_CODE (XEXP (x
, 0)) == ROTATE
4374 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4375 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4379 case GT
: case GTU
: case GE
: case GEU
:
4380 case LT
: case LTU
: case LE
: case LEU
:
4381 case UNEQ
: case LTGT
:
4382 case UNGT
: case UNGE
:
4383 case UNLT
: case UNLE
:
4384 case UNORDERED
: case ORDERED
:
4385 /* If the first operand is a condition code, we can't do anything
4387 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4388 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4390 && XEXP (x
, 0) != cc0_rtx
4394 rtx op0
= XEXP (x
, 0);
4395 rtx op1
= XEXP (x
, 1);
4396 enum rtx_code new_code
;
4398 if (GET_CODE (op0
) == COMPARE
)
4399 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4401 /* Simplify our comparison, if possible. */
4402 new_code
= simplify_comparison (code
, &op0
, &op1
);
4404 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4405 if only the low-order bit is possibly nonzero in X (such as when
4406 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4407 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4408 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4411 Remove any ZERO_EXTRACT we made when thinking this was a
4412 comparison. It may now be simpler to use, e.g., an AND. If a
4413 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4414 the call to make_compound_operation in the SET case. */
4416 if (STORE_FLAG_VALUE
== 1
4417 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4418 && op1
== const0_rtx
4419 && mode
== GET_MODE (op0
)
4420 && nonzero_bits (op0
, mode
) == 1)
4421 return gen_lowpart_for_combine (mode
,
4422 expand_compound_operation (op0
));
4424 else if (STORE_FLAG_VALUE
== 1
4425 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4426 && op1
== const0_rtx
4427 && mode
== GET_MODE (op0
)
4428 && (num_sign_bit_copies (op0
, mode
)
4429 == GET_MODE_BITSIZE (mode
)))
4431 op0
= expand_compound_operation (op0
);
4432 return simplify_gen_unary (NEG
, mode
,
4433 gen_lowpart_for_combine (mode
, op0
),
4437 else if (STORE_FLAG_VALUE
== 1
4438 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4439 && op1
== const0_rtx
4440 && mode
== GET_MODE (op0
)
4441 && nonzero_bits (op0
, mode
) == 1)
4443 op0
= expand_compound_operation (op0
);
4444 return gen_binary (XOR
, mode
,
4445 gen_lowpart_for_combine (mode
, op0
),
4449 else if (STORE_FLAG_VALUE
== 1
4450 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4451 && op1
== const0_rtx
4452 && mode
== GET_MODE (op0
)
4453 && (num_sign_bit_copies (op0
, mode
)
4454 == GET_MODE_BITSIZE (mode
)))
4456 op0
= expand_compound_operation (op0
);
4457 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4460 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4462 if (STORE_FLAG_VALUE
== -1
4463 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4464 && op1
== const0_rtx
4465 && (num_sign_bit_copies (op0
, mode
)
4466 == GET_MODE_BITSIZE (mode
)))
4467 return gen_lowpart_for_combine (mode
,
4468 expand_compound_operation (op0
));
4470 else if (STORE_FLAG_VALUE
== -1
4471 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4472 && op1
== const0_rtx
4473 && mode
== GET_MODE (op0
)
4474 && nonzero_bits (op0
, mode
) == 1)
4476 op0
= expand_compound_operation (op0
);
4477 return simplify_gen_unary (NEG
, mode
,
4478 gen_lowpart_for_combine (mode
, op0
),
4482 else if (STORE_FLAG_VALUE
== -1
4483 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4484 && op1
== const0_rtx
4485 && mode
== GET_MODE (op0
)
4486 && (num_sign_bit_copies (op0
, mode
)
4487 == GET_MODE_BITSIZE (mode
)))
4489 op0
= expand_compound_operation (op0
);
4490 return simplify_gen_unary (NOT
, mode
,
4491 gen_lowpart_for_combine (mode
, op0
),
4495 /* If X is 0/1, (eq X 0) is X-1. */
4496 else if (STORE_FLAG_VALUE
== -1
4497 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4498 && op1
== const0_rtx
4499 && mode
== GET_MODE (op0
)
4500 && nonzero_bits (op0
, mode
) == 1)
4502 op0
= expand_compound_operation (op0
);
4503 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4506 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4507 one bit that might be nonzero, we can convert (ne x 0) to
4508 (ashift x c) where C puts the bit in the sign bit. Remove any
4509 AND with STORE_FLAG_VALUE when we are done, since we are only
4510 going to test the sign bit. */
4511 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4512 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4513 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4514 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4515 && op1
== const0_rtx
4516 && mode
== GET_MODE (op0
)
4517 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4519 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4520 expand_compound_operation (op0
),
4521 GET_MODE_BITSIZE (mode
) - 1 - i
);
4522 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4528 /* If the code changed, return a whole new comparison. */
4529 if (new_code
!= code
)
4530 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4532 /* Otherwise, keep this operation, but maybe change its operands.
4533 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4534 SUBST (XEXP (x
, 0), op0
);
4535 SUBST (XEXP (x
, 1), op1
);
4540 return simplify_if_then_else (x
);
4546 /* If we are processing SET_DEST, we are done. */
4550 return expand_compound_operation (x
);
4553 return simplify_set (x
);
4558 return simplify_logical (x
, last
);
4561 /* (abs (neg <foo>)) -> (abs <foo>) */
4562 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4563 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4565 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4567 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4570 /* If operand is something known to be positive, ignore the ABS. */
4571 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4572 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4573 <= HOST_BITS_PER_WIDE_INT
)
4574 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4575 & ((HOST_WIDE_INT
) 1
4576 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4580 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4581 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4582 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4587 /* (ffs (*_extend <X>)) = (ffs <X>) */
4588 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4589 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4590 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4594 /* (float (sign_extend <X>)) = (float <X>). */
4595 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4596 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4604 /* If this is a shift by a constant amount, simplify it. */
4605 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4606 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4607 INTVAL (XEXP (x
, 1)));
4609 #ifdef SHIFT_COUNT_TRUNCATED
4610 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4612 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4614 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4623 rtx op0
= XEXP (x
, 0);
4624 rtx op1
= XEXP (x
, 1);
4627 if (GET_CODE (op1
) != PARALLEL
)
4629 len
= XVECLEN (op1
, 0);
4631 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4632 && GET_CODE (op0
) == VEC_CONCAT
)
4634 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4636 /* Try to find the element in the VEC_CONCAT. */
4639 if (GET_MODE (op0
) == GET_MODE (x
))
4641 if (GET_CODE (op0
) == VEC_CONCAT
)
4643 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4644 if (op0_size
< offset
)
4645 op0
= XEXP (op0
, 0);
4649 op0
= XEXP (op0
, 1);
4667 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4670 simplify_if_then_else (x
)
4673 enum machine_mode mode
= GET_MODE (x
);
4674 rtx cond
= XEXP (x
, 0);
4675 rtx true_rtx
= XEXP (x
, 1);
4676 rtx false_rtx
= XEXP (x
, 2);
4677 enum rtx_code true_code
= GET_CODE (cond
);
4678 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4681 enum rtx_code false_code
;
4684 /* Simplify storing of the truth value. */
4685 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4686 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4688 /* Also when the truth value has to be reversed. */
4690 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4691 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4695 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4696 in it is being compared against certain values. Get the true and false
4697 comparisons and see if that says anything about the value of each arm. */
4700 && ((false_code
= combine_reversed_comparison_code (cond
))
4702 && GET_CODE (XEXP (cond
, 0)) == REG
)
4705 rtx from
= XEXP (cond
, 0);
4706 rtx true_val
= XEXP (cond
, 1);
4707 rtx false_val
= true_val
;
4710 /* If FALSE_CODE is EQ, swap the codes and arms. */
4712 if (false_code
== EQ
)
4714 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4715 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4718 /* If we are comparing against zero and the expression being tested has
4719 only a single bit that might be nonzero, that is its value when it is
4720 not equal to zero. Similarly if it is known to be -1 or 0. */
4722 if (true_code
== EQ
&& true_val
== const0_rtx
4723 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4724 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4725 else if (true_code
== EQ
&& true_val
== const0_rtx
4726 && (num_sign_bit_copies (from
, GET_MODE (from
))
4727 == GET_MODE_BITSIZE (GET_MODE (from
))))
4728 false_code
= EQ
, false_val
= constm1_rtx
;
4730 /* Now simplify an arm if we know the value of the register in the
4731 branch and it is used in the arm. Be careful due to the potential
4732 of locally-shared RTL. */
4734 if (reg_mentioned_p (from
, true_rtx
))
4735 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4737 pc_rtx
, pc_rtx
, 0, 0);
4738 if (reg_mentioned_p (from
, false_rtx
))
4739 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4741 pc_rtx
, pc_rtx
, 0, 0);
4743 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4744 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4746 true_rtx
= XEXP (x
, 1);
4747 false_rtx
= XEXP (x
, 2);
4748 true_code
= GET_CODE (cond
);
4751 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4752 reversed, do so to avoid needing two sets of patterns for
4753 subtract-and-branch insns. Similarly if we have a constant in the true
4754 arm, the false arm is the same as the first operand of the comparison, or
4755 the false arm is more complicated than the true arm. */
4758 && combine_reversed_comparison_code (cond
) != UNKNOWN
4759 && (true_rtx
== pc_rtx
4760 || (CONSTANT_P (true_rtx
)
4761 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4762 || true_rtx
== const0_rtx
4763 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4764 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4765 || (GET_CODE (true_rtx
) == SUBREG
4766 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4767 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4768 || reg_mentioned_p (true_rtx
, false_rtx
)
4769 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4771 true_code
= reversed_comparison_code (cond
, NULL
);
4773 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4776 SUBST (XEXP (x
, 1), false_rtx
);
4777 SUBST (XEXP (x
, 2), true_rtx
);
4779 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4782 /* It is possible that the conditional has been simplified out. */
4783 true_code
= GET_CODE (cond
);
4784 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4787 /* If the two arms are identical, we don't need the comparison. */
4789 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4792 /* Convert a == b ? b : a to "a". */
4793 if (true_code
== EQ
&& ! side_effects_p (cond
)
4794 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4795 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4796 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4798 else if (true_code
== NE
&& ! side_effects_p (cond
)
4799 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4800 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4801 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4804 /* Look for cases where we have (abs x) or (neg (abs X)). */
4806 if (GET_MODE_CLASS (mode
) == MODE_INT
4807 && GET_CODE (false_rtx
) == NEG
4808 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4810 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4811 && ! side_effects_p (true_rtx
))
4816 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4820 simplify_gen_unary (NEG
, mode
,
4821 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4827 /* Look for MIN or MAX. */
4829 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4831 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4832 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4833 && ! side_effects_p (cond
))
4838 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4841 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4844 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4847 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4852 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4853 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4854 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4855 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4856 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4857 neither 1 or -1, but it isn't worth checking for. */
4859 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4860 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4862 rtx t
= make_compound_operation (true_rtx
, SET
);
4863 rtx f
= make_compound_operation (false_rtx
, SET
);
4864 rtx cond_op0
= XEXP (cond
, 0);
4865 rtx cond_op1
= XEXP (cond
, 1);
4866 enum rtx_code op
= NIL
, extend_op
= NIL
;
4867 enum machine_mode m
= mode
;
4868 rtx z
= 0, c1
= NULL_RTX
;
4870 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4871 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4872 || GET_CODE (t
) == ASHIFT
4873 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4874 && rtx_equal_p (XEXP (t
, 0), f
))
4875 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4877 /* If an identity-zero op is commutative, check whether there
4878 would be a match if we swapped the operands. */
4879 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4880 || GET_CODE (t
) == XOR
)
4881 && rtx_equal_p (XEXP (t
, 1), f
))
4882 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4883 else if (GET_CODE (t
) == SIGN_EXTEND
4884 && (GET_CODE (XEXP (t
, 0)) == PLUS
4885 || GET_CODE (XEXP (t
, 0)) == MINUS
4886 || GET_CODE (XEXP (t
, 0)) == IOR
4887 || GET_CODE (XEXP (t
, 0)) == XOR
4888 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4889 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4890 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4891 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4892 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4893 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4894 && (num_sign_bit_copies (f
, GET_MODE (f
))
4895 > (GET_MODE_BITSIZE (mode
)
4896 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4898 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4899 extend_op
= SIGN_EXTEND
;
4900 m
= GET_MODE (XEXP (t
, 0));
4902 else if (GET_CODE (t
) == SIGN_EXTEND
4903 && (GET_CODE (XEXP (t
, 0)) == PLUS
4904 || GET_CODE (XEXP (t
, 0)) == IOR
4905 || GET_CODE (XEXP (t
, 0)) == XOR
)
4906 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4907 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4908 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4909 && (num_sign_bit_copies (f
, GET_MODE (f
))
4910 > (GET_MODE_BITSIZE (mode
)
4911 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4913 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4914 extend_op
= SIGN_EXTEND
;
4915 m
= GET_MODE (XEXP (t
, 0));
4917 else if (GET_CODE (t
) == ZERO_EXTEND
4918 && (GET_CODE (XEXP (t
, 0)) == PLUS
4919 || GET_CODE (XEXP (t
, 0)) == MINUS
4920 || GET_CODE (XEXP (t
, 0)) == IOR
4921 || GET_CODE (XEXP (t
, 0)) == XOR
4922 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4923 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4924 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4925 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4926 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4927 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4928 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4929 && ((nonzero_bits (f
, GET_MODE (f
))
4930 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4933 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4934 extend_op
= ZERO_EXTEND
;
4935 m
= GET_MODE (XEXP (t
, 0));
4937 else if (GET_CODE (t
) == ZERO_EXTEND
4938 && (GET_CODE (XEXP (t
, 0)) == PLUS
4939 || GET_CODE (XEXP (t
, 0)) == IOR
4940 || GET_CODE (XEXP (t
, 0)) == XOR
)
4941 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4942 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4943 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4944 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4945 && ((nonzero_bits (f
, GET_MODE (f
))
4946 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4949 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4950 extend_op
= ZERO_EXTEND
;
4951 m
= GET_MODE (XEXP (t
, 0));
4956 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4957 pc_rtx
, pc_rtx
, 0, 0);
4958 temp
= gen_binary (MULT
, m
, temp
,
4959 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4960 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4961 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4963 if (extend_op
!= NIL
)
4964 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4970 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4971 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4972 negation of a single bit, we can convert this operation to a shift. We
4973 can actually do this more generally, but it doesn't seem worth it. */
4975 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4976 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4977 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4978 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4979 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4980 == GET_MODE_BITSIZE (mode
))
4981 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4983 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4984 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4989 /* Simplify X, a SET expression. Return the new expression. */
4995 rtx src
= SET_SRC (x
);
4996 rtx dest
= SET_DEST (x
);
4997 enum machine_mode mode
4998 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5002 /* (set (pc) (return)) gets written as (return). */
5003 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5006 /* Now that we know for sure which bits of SRC we are using, see if we can
5007 simplify the expression for the object knowing that we only need the
5010 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5012 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5013 SUBST (SET_SRC (x
), src
);
5016 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5017 the comparison result and try to simplify it unless we already have used
5018 undobuf.other_insn. */
5019 if ((GET_CODE (src
) == COMPARE
5024 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5025 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5026 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5027 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5029 enum rtx_code old_code
= GET_CODE (*cc_use
);
5030 enum rtx_code new_code
;
5032 int other_changed
= 0;
5033 enum machine_mode compare_mode
= GET_MODE (dest
);
5035 if (GET_CODE (src
) == COMPARE
)
5036 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5038 op0
= src
, op1
= const0_rtx
;
5040 /* Simplify our comparison, if possible. */
5041 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5043 #ifdef EXTRA_CC_MODES
5044 /* If this machine has CC modes other than CCmode, check to see if we
5045 need to use a different CC mode here. */
5046 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5047 #endif /* EXTRA_CC_MODES */
5049 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5050 /* If the mode changed, we have to change SET_DEST, the mode in the
5051 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5052 a hard register, just build new versions with the proper mode. If it
5053 is a pseudo, we lose unless it is only time we set the pseudo, in
5054 which case we can safely change its mode. */
5055 if (compare_mode
!= GET_MODE (dest
))
5057 unsigned int regno
= REGNO (dest
);
5058 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5060 if (regno
< FIRST_PSEUDO_REGISTER
5061 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5063 if (regno
>= FIRST_PSEUDO_REGISTER
)
5064 SUBST (regno_reg_rtx
[regno
], new_dest
);
5066 SUBST (SET_DEST (x
), new_dest
);
5067 SUBST (XEXP (*cc_use
, 0), new_dest
);
5075 /* If the code changed, we have to build a new comparison in
5076 undobuf.other_insn. */
5077 if (new_code
!= old_code
)
5079 unsigned HOST_WIDE_INT mask
;
5081 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5084 /* If the only change we made was to change an EQ into an NE or
5085 vice versa, OP0 has only one bit that might be nonzero, and OP1
5086 is zero, check if changing the user of the condition code will
5087 produce a valid insn. If it won't, we can keep the original code
5088 in that insn by surrounding our operation with an XOR. */
5090 if (((old_code
== NE
&& new_code
== EQ
)
5091 || (old_code
== EQ
&& new_code
== NE
))
5092 && ! other_changed
&& op1
== const0_rtx
5093 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5094 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5096 rtx pat
= PATTERN (other_insn
), note
= 0;
5098 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5099 && ! check_asm_operands (pat
)))
5101 PUT_CODE (*cc_use
, old_code
);
5104 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5112 undobuf
.other_insn
= other_insn
;
5115 /* If we are now comparing against zero, change our source if
5116 needed. If we do not use cc0, we always have a COMPARE. */
5117 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5119 SUBST (SET_SRC (x
), op0
);
5125 /* Otherwise, if we didn't previously have a COMPARE in the
5126 correct mode, we need one. */
5127 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5129 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5134 /* Otherwise, update the COMPARE if needed. */
5135 SUBST (XEXP (src
, 0), op0
);
5136 SUBST (XEXP (src
, 1), op1
);
5141 /* Get SET_SRC in a form where we have placed back any
5142 compound expressions. Then do the checks below. */
5143 src
= make_compound_operation (src
, SET
);
5144 SUBST (SET_SRC (x
), src
);
5147 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5148 and X being a REG or (subreg (reg)), we may be able to convert this to
5149 (set (subreg:m2 x) (op)).
5151 We can always do this if M1 is narrower than M2 because that means that
5152 we only care about the low bits of the result.
5154 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5155 perform a narrower operation than requested since the high-order bits will
5156 be undefined. On machine where it is defined, this transformation is safe
5157 as long as M1 and M2 have the same number of words. */
5159 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5160 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5161 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5163 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5164 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5165 #ifndef WORD_REGISTER_OPERATIONS
5166 && (GET_MODE_SIZE (GET_MODE (src
))
5167 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5169 #ifdef CLASS_CANNOT_CHANGE_MODE
5170 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5171 && (TEST_HARD_REG_BIT
5172 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5174 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5175 GET_MODE (SUBREG_REG (src
))))
5177 && (GET_CODE (dest
) == REG
5178 || (GET_CODE (dest
) == SUBREG
5179 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5181 SUBST (SET_DEST (x
),
5182 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5184 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5186 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5189 #ifdef LOAD_EXTEND_OP
5190 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5191 would require a paradoxical subreg. Replace the subreg with a
5192 zero_extend to avoid the reload that would otherwise be required. */
5194 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5195 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5196 && SUBREG_BYTE (src
) == 0
5197 && (GET_MODE_SIZE (GET_MODE (src
))
5198 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5199 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5202 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5203 GET_MODE (src
), SUBREG_REG (src
)));
5209 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5210 are comparing an item known to be 0 or -1 against 0, use a logical
5211 operation instead. Check for one of the arms being an IOR of the other
5212 arm with some value. We compute three terms to be IOR'ed together. In
5213 practice, at most two will be nonzero. Then we do the IOR's. */
5215 if (GET_CODE (dest
) != PC
5216 && GET_CODE (src
) == IF_THEN_ELSE
5217 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5218 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5219 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5220 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5221 #ifdef HAVE_conditional_move
5222 && ! can_conditionally_move_p (GET_MODE (src
))
5224 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5225 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5226 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5227 && ! side_effects_p (src
))
5229 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5230 ? XEXP (src
, 1) : XEXP (src
, 2));
5231 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5232 ? XEXP (src
, 2) : XEXP (src
, 1));
5233 rtx term1
= const0_rtx
, term2
, term3
;
5235 if (GET_CODE (true_rtx
) == IOR
5236 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5237 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5238 else if (GET_CODE (true_rtx
) == IOR
5239 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5240 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5241 else if (GET_CODE (false_rtx
) == IOR
5242 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5243 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5244 else if (GET_CODE (false_rtx
) == IOR
5245 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5246 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5248 term2
= gen_binary (AND
, GET_MODE (src
),
5249 XEXP (XEXP (src
, 0), 0), true_rtx
);
5250 term3
= gen_binary (AND
, GET_MODE (src
),
5251 simplify_gen_unary (NOT
, GET_MODE (src
),
5252 XEXP (XEXP (src
, 0), 0),
5257 gen_binary (IOR
, GET_MODE (src
),
5258 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5264 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5265 whole thing fail. */
5266 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5268 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5271 /* Convert this into a field assignment operation, if possible. */
5272 return make_field_assignment (x
);
5275 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5276 result. LAST is nonzero if this is the last retry. */
5279 simplify_logical (x
, last
)
5283 enum machine_mode mode
= GET_MODE (x
);
5284 rtx op0
= XEXP (x
, 0);
5285 rtx op1
= XEXP (x
, 1);
5288 switch (GET_CODE (x
))
5291 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5292 insn (and may simplify more). */
5293 if (GET_CODE (op0
) == XOR
5294 && rtx_equal_p (XEXP (op0
, 0), op1
)
5295 && ! side_effects_p (op1
))
5296 x
= gen_binary (AND
, mode
,
5297 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5300 if (GET_CODE (op0
) == XOR
5301 && rtx_equal_p (XEXP (op0
, 1), op1
)
5302 && ! side_effects_p (op1
))
5303 x
= gen_binary (AND
, mode
,
5304 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5307 /* Similarly for (~(A ^ B)) & A. */
5308 if (GET_CODE (op0
) == NOT
5309 && GET_CODE (XEXP (op0
, 0)) == XOR
5310 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5311 && ! side_effects_p (op1
))
5312 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5314 if (GET_CODE (op0
) == NOT
5315 && GET_CODE (XEXP (op0
, 0)) == XOR
5316 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5317 && ! side_effects_p (op1
))
5318 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5320 /* We can call simplify_and_const_int only if we don't lose
5321 any (sign) bits when converting INTVAL (op1) to
5322 "unsigned HOST_WIDE_INT". */
5323 if (GET_CODE (op1
) == CONST_INT
5324 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5325 || INTVAL (op1
) > 0))
5327 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5329 /* If we have (ior (and (X C1) C2)) and the next restart would be
5330 the last, simplify this by making C1 as small as possible
5333 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5334 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5335 && GET_CODE (op1
) == CONST_INT
)
5336 return gen_binary (IOR
, mode
,
5337 gen_binary (AND
, mode
, XEXP (op0
, 0),
5338 GEN_INT (INTVAL (XEXP (op0
, 1))
5339 & ~INTVAL (op1
))), op1
);
5341 if (GET_CODE (x
) != AND
)
5344 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5345 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5346 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5349 /* Convert (A | B) & A to A. */
5350 if (GET_CODE (op0
) == IOR
5351 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5352 || rtx_equal_p (XEXP (op0
, 1), op1
))
5353 && ! side_effects_p (XEXP (op0
, 0))
5354 && ! side_effects_p (XEXP (op0
, 1)))
5357 /* In the following group of tests (and those in case IOR below),
5358 we start with some combination of logical operations and apply
5359 the distributive law followed by the inverse distributive law.
5360 Most of the time, this results in no change. However, if some of
5361 the operands are the same or inverses of each other, simplifications
5364 For example, (and (ior A B) (not B)) can occur as the result of
5365 expanding a bit field assignment. When we apply the distributive
5366 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5367 which then simplifies to (and (A (not B))).
5369 If we have (and (ior A B) C), apply the distributive law and then
5370 the inverse distributive law to see if things simplify. */
5372 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5374 x
= apply_distributive_law
5375 (gen_binary (GET_CODE (op0
), mode
,
5376 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5377 gen_binary (AND
, mode
, XEXP (op0
, 1),
5379 if (GET_CODE (x
) != AND
)
5383 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5384 return apply_distributive_law
5385 (gen_binary (GET_CODE (op1
), mode
,
5386 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5387 gen_binary (AND
, mode
, XEXP (op1
, 1),
5390 /* Similarly, taking advantage of the fact that
5391 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5393 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5394 return apply_distributive_law
5395 (gen_binary (XOR
, mode
,
5396 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5397 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5400 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5401 return apply_distributive_law
5402 (gen_binary (XOR
, mode
,
5403 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5404 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5408 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5409 if (GET_CODE (op1
) == CONST_INT
5410 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5411 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5414 /* Convert (A & B) | A to A. */
5415 if (GET_CODE (op0
) == AND
5416 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5417 || rtx_equal_p (XEXP (op0
, 1), op1
))
5418 && ! side_effects_p (XEXP (op0
, 0))
5419 && ! side_effects_p (XEXP (op0
, 1)))
5422 /* If we have (ior (and A B) C), apply the distributive law and then
5423 the inverse distributive law to see if things simplify. */
5425 if (GET_CODE (op0
) == AND
)
5427 x
= apply_distributive_law
5428 (gen_binary (AND
, mode
,
5429 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5430 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5433 if (GET_CODE (x
) != IOR
)
5437 if (GET_CODE (op1
) == AND
)
5439 x
= apply_distributive_law
5440 (gen_binary (AND
, mode
,
5441 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5442 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5445 if (GET_CODE (x
) != IOR
)
5449 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5450 mode size to (rotate A CX). */
5452 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5453 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5454 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5455 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5456 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5457 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5458 == GET_MODE_BITSIZE (mode
)))
5459 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5460 (GET_CODE (op0
) == ASHIFT
5461 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5463 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5464 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5465 does not affect any of the bits in OP1, it can really be done
5466 as a PLUS and we can associate. We do this by seeing if OP1
5467 can be safely shifted left C bits. */
5468 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5469 && GET_CODE (XEXP (op0
, 0)) == PLUS
5470 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5471 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5472 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5474 int count
= INTVAL (XEXP (op0
, 1));
5475 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5477 if (mask
>> count
== INTVAL (op1
)
5478 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5480 SUBST (XEXP (XEXP (op0
, 0), 1),
5481 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5488 /* If we are XORing two things that have no bits in common,
5489 convert them into an IOR. This helps to detect rotation encoded
5490 using those methods and possibly other simplifications. */
5492 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5493 && (nonzero_bits (op0
, mode
)
5494 & nonzero_bits (op1
, mode
)) == 0)
5495 return (gen_binary (IOR
, mode
, op0
, op1
));
5497 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5498 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5501 int num_negated
= 0;
5503 if (GET_CODE (op0
) == NOT
)
5504 num_negated
++, op0
= XEXP (op0
, 0);
5505 if (GET_CODE (op1
) == NOT
)
5506 num_negated
++, op1
= XEXP (op1
, 0);
5508 if (num_negated
== 2)
5510 SUBST (XEXP (x
, 0), op0
);
5511 SUBST (XEXP (x
, 1), op1
);
5513 else if (num_negated
== 1)
5515 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5519 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5520 correspond to a machine insn or result in further simplifications
5521 if B is a constant. */
5523 if (GET_CODE (op0
) == AND
5524 && rtx_equal_p (XEXP (op0
, 1), op1
)
5525 && ! side_effects_p (op1
))
5526 return gen_binary (AND
, mode
,
5527 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5530 else if (GET_CODE (op0
) == AND
5531 && rtx_equal_p (XEXP (op0
, 0), op1
)
5532 && ! side_effects_p (op1
))
5533 return gen_binary (AND
, mode
,
5534 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5537 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5538 comparison if STORE_FLAG_VALUE is 1. */
5539 if (STORE_FLAG_VALUE
== 1
5540 && op1
== const1_rtx
5541 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5542 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5546 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5547 is (lt foo (const_int 0)), so we can perform the above
5548 simplification if STORE_FLAG_VALUE is 1. */
5550 if (STORE_FLAG_VALUE
== 1
5551 && op1
== const1_rtx
5552 && GET_CODE (op0
) == LSHIFTRT
5553 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5554 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5555 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5557 /* (xor (comparison foo bar) (const_int sign-bit))
5558 when STORE_FLAG_VALUE is the sign bit. */
5559 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5560 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5561 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5562 && op1
== const_true_rtx
5563 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5564 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5577 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5578 operations" because they can be replaced with two more basic operations.
5579 ZERO_EXTEND is also considered "compound" because it can be replaced with
5580 an AND operation, which is simpler, though only one operation.
5582 The function expand_compound_operation is called with an rtx expression
5583 and will convert it to the appropriate shifts and AND operations,
5584 simplifying at each stage.
5586 The function make_compound_operation is called to convert an expression
5587 consisting of shifts and ANDs into the equivalent compound expression.
5588 It is the inverse of this function, loosely speaking. */
5591 expand_compound_operation (x
)
5594 unsigned HOST_WIDE_INT pos
= 0, len
;
5596 unsigned int modewidth
;
5599 switch (GET_CODE (x
))
5604 /* We can't necessarily use a const_int for a multiword mode;
5605 it depends on implicitly extending the value.
5606 Since we don't know the right way to extend it,
5607 we can't tell whether the implicit way is right.
5609 Even for a mode that is no wider than a const_int,
5610 we can't win, because we need to sign extend one of its bits through
5611 the rest of it, and we don't know which bit. */
5612 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5615 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5616 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5617 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5618 reloaded. If not for that, MEM's would very rarely be safe.
5620 Reject MODEs bigger than a word, because we might not be able
5621 to reference a two-register group starting with an arbitrary register
5622 (and currently gen_lowpart might crash for a SUBREG). */
5624 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5627 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5628 /* If the inner object has VOIDmode (the only way this can happen
5629 is if it is a ASM_OPERANDS), we can't do anything since we don't
5630 know how much masking to do. */
5639 /* If the operand is a CLOBBER, just return it. */
5640 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5643 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5644 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5645 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5648 len
= INTVAL (XEXP (x
, 1));
5649 pos
= INTVAL (XEXP (x
, 2));
5651 /* If this goes outside the object being extracted, replace the object
5652 with a (use (mem ...)) construct that only combine understands
5653 and is used only for this purpose. */
5654 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5655 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5657 if (BITS_BIG_ENDIAN
)
5658 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5665 /* Convert sign extension to zero extension, if we know that the high
5666 bit is not set, as this is easier to optimize. It will be converted
5667 back to cheaper alternative in make_extraction. */
5668 if (GET_CODE (x
) == SIGN_EXTEND
5669 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5670 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5671 & ~(((unsigned HOST_WIDE_INT
)
5672 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5676 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5677 return expand_compound_operation (temp
);
5680 /* We can optimize some special cases of ZERO_EXTEND. */
5681 if (GET_CODE (x
) == ZERO_EXTEND
)
5683 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5684 know that the last value didn't have any inappropriate bits
5686 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5687 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5688 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5689 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5690 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5691 return XEXP (XEXP (x
, 0), 0);
5693 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5694 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5695 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5696 && subreg_lowpart_p (XEXP (x
, 0))
5697 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5698 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5699 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5700 return SUBREG_REG (XEXP (x
, 0));
5702 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5703 is a comparison and STORE_FLAG_VALUE permits. This is like
5704 the first case, but it works even when GET_MODE (x) is larger
5705 than HOST_WIDE_INT. */
5706 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5707 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5708 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5709 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5710 <= HOST_BITS_PER_WIDE_INT
)
5711 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5712 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5713 return XEXP (XEXP (x
, 0), 0);
5715 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5716 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5717 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5718 && subreg_lowpart_p (XEXP (x
, 0))
5719 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5720 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5721 <= HOST_BITS_PER_WIDE_INT
)
5722 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5723 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5724 return SUBREG_REG (XEXP (x
, 0));
5728 /* If we reach here, we want to return a pair of shifts. The inner
5729 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5730 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5731 logical depending on the value of UNSIGNEDP.
5733 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5734 converted into an AND of a shift.
5736 We must check for the case where the left shift would have a negative
5737 count. This can happen in a case like (x >> 31) & 255 on machines
5738 that can't shift by a constant. On those machines, we would first
5739 combine the shift with the AND to produce a variable-position
5740 extraction. Then the constant of 31 would be substituted in to produce
5741 a such a position. */
5743 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5744 if (modewidth
+ len
>= pos
)
5745 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5747 simplify_shift_const (NULL_RTX
, ASHIFT
,
5750 modewidth
- pos
- len
),
5753 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5754 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5755 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5758 ((HOST_WIDE_INT
) 1 << len
) - 1);
5760 /* Any other cases we can't handle. */
5763 /* If we couldn't do this for some reason, return the original
5765 if (GET_CODE (tem
) == CLOBBER
)
5771 /* X is a SET which contains an assignment of one object into
5772 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5773 or certain SUBREGS). If possible, convert it into a series of
5776 We half-heartedly support variable positions, but do not at all
5777 support variable lengths. */
5780 expand_field_assignment (x
)
5784 rtx pos
; /* Always counts from low bit. */
5787 enum machine_mode compute_mode
;
5789 /* Loop until we find something we can't simplify. */
5792 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5793 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5795 int byte_offset
= SUBREG_BYTE (XEXP (SET_DEST (x
), 0));
5797 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5798 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5799 pos
= GEN_INT (BITS_PER_WORD
* (byte_offset
/ UNITS_PER_WORD
));
5801 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5802 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5804 inner
= XEXP (SET_DEST (x
), 0);
5805 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5806 pos
= XEXP (SET_DEST (x
), 2);
5808 /* If the position is constant and spans the width of INNER,
5809 surround INNER with a USE to indicate this. */
5810 if (GET_CODE (pos
) == CONST_INT
5811 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5812 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5814 if (BITS_BIG_ENDIAN
)
5816 if (GET_CODE (pos
) == CONST_INT
)
5817 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5819 else if (GET_CODE (pos
) == MINUS
5820 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5821 && (INTVAL (XEXP (pos
, 1))
5822 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5823 /* If position is ADJUST - X, new position is X. */
5824 pos
= XEXP (pos
, 0);
5826 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5827 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5833 /* A SUBREG between two modes that occupy the same numbers of words
5834 can be done by moving the SUBREG to the source. */
5835 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5836 /* We need SUBREGs to compute nonzero_bits properly. */
5837 && nonzero_sign_valid
5838 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5839 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5840 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5841 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5843 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5844 gen_lowpart_for_combine
5845 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5852 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5853 inner
= SUBREG_REG (inner
);
5855 compute_mode
= GET_MODE (inner
);
5857 /* Don't attempt bitwise arithmetic on non-integral modes. */
5858 if (! INTEGRAL_MODE_P (compute_mode
))
5860 enum machine_mode imode
;
5862 /* Something is probably seriously wrong if this matches. */
5863 if (! FLOAT_MODE_P (compute_mode
))
5866 /* Try to find an integral mode to pun with. */
5867 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5868 if (imode
== BLKmode
)
5871 compute_mode
= imode
;
5872 inner
= gen_lowpart_for_combine (imode
, inner
);
5875 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5876 if (len
< HOST_BITS_PER_WIDE_INT
)
5877 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5881 /* Now compute the equivalent expression. Make a copy of INNER
5882 for the SET_DEST in case it is a MEM into which we will substitute;
5883 we don't want shared RTL in that case. */
5885 (VOIDmode
, copy_rtx (inner
),
5886 gen_binary (IOR
, compute_mode
,
5887 gen_binary (AND
, compute_mode
,
5888 simplify_gen_unary (NOT
, compute_mode
,
5894 gen_binary (ASHIFT
, compute_mode
,
5895 gen_binary (AND
, compute_mode
,
5896 gen_lowpart_for_combine
5897 (compute_mode
, SET_SRC (x
)),
5905 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5906 it is an RTX that represents a variable starting position; otherwise,
5907 POS is the (constant) starting bit position (counted from the LSB).
5909 INNER may be a USE. This will occur when we started with a bitfield
5910 that went outside the boundary of the object in memory, which is
5911 allowed on most machines. To isolate this case, we produce a USE
5912 whose mode is wide enough and surround the MEM with it. The only
5913 code that understands the USE is this routine. If it is not removed,
5914 it will cause the resulting insn not to match.
5916 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5919 IN_DEST is non-zero if this is a reference in the destination of a
5920 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5921 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5924 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5925 ZERO_EXTRACT should be built even for bits starting at bit 0.
5927 MODE is the desired mode of the result (if IN_DEST == 0).
5929 The result is an RTX for the extraction or NULL_RTX if the target
5933 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5934 unsignedp
, in_dest
, in_compare
)
5935 enum machine_mode mode
;
5939 unsigned HOST_WIDE_INT len
;
5941 int in_dest
, in_compare
;
5943 /* This mode describes the size of the storage area
5944 to fetch the overall value from. Within that, we
5945 ignore the POS lowest bits, etc. */
5946 enum machine_mode is_mode
= GET_MODE (inner
);
5947 enum machine_mode inner_mode
;
5948 enum machine_mode wanted_inner_mode
= byte_mode
;
5949 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5950 enum machine_mode pos_mode
= word_mode
;
5951 enum machine_mode extraction_mode
= word_mode
;
5952 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5955 rtx orig_pos_rtx
= pos_rtx
;
5956 HOST_WIDE_INT orig_pos
;
5958 /* Get some information about INNER and get the innermost object. */
5959 if (GET_CODE (inner
) == USE
)
5960 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5961 /* We don't need to adjust the position because we set up the USE
5962 to pretend that it was a full-word object. */
5963 spans_byte
= 1, inner
= XEXP (inner
, 0);
5964 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5966 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5967 consider just the QI as the memory to extract from.
5968 The subreg adds or removes high bits; its mode is
5969 irrelevant to the meaning of this extraction,
5970 since POS and LEN count from the lsb. */
5971 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5972 is_mode
= GET_MODE (SUBREG_REG (inner
));
5973 inner
= SUBREG_REG (inner
);
5976 inner_mode
= GET_MODE (inner
);
5978 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5979 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5981 /* See if this can be done without an extraction. We never can if the
5982 width of the field is not the same as that of some integer mode. For
5983 registers, we can only avoid the extraction if the position is at the
5984 low-order bit and this is either not in the destination or we have the
5985 appropriate STRICT_LOW_PART operation available.
5987 For MEM, we can avoid an extract if the field starts on an appropriate
5988 boundary and we can change the mode of the memory reference. However,
5989 we cannot directly access the MEM if we have a USE and the underlying
5990 MEM is not TMODE. This combination means that MEM was being used in a
5991 context where bits outside its mode were being referenced; that is only
5992 valid in bit-field insns. */
5994 if (tmode
!= BLKmode
5995 && ! (spans_byte
&& inner_mode
!= tmode
)
5996 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5997 && GET_CODE (inner
) != MEM
5999 || (GET_CODE (inner
) == REG
6000 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
6001 != CODE_FOR_nothing
))))
6002 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6004 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6005 : BITS_PER_UNIT
)) == 0
6006 /* We can't do this if we are widening INNER_MODE (it
6007 may not be aligned, for one thing). */
6008 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6009 && (inner_mode
== tmode
6010 || (! mode_dependent_address_p (XEXP (inner
, 0))
6011 && ! MEM_VOLATILE_P (inner
))))))
6013 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6014 field. If the original and current mode are the same, we need not
6015 adjust the offset. Otherwise, we do if bytes big endian.
6017 If INNER is not a MEM, get a piece consisting of just the field
6018 of interest (in this case POS % BITS_PER_WORD must be 0). */
6020 if (GET_CODE (inner
) == MEM
)
6023 /* POS counts from lsb, but make OFFSET count in memory order. */
6024 if (BYTES_BIG_ENDIAN
)
6025 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6027 offset
= pos
/ BITS_PER_UNIT
;
6029 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
6030 MEM_COPY_ATTRIBUTES (new, inner
);
6032 else if (GET_CODE (inner
) == REG
)
6034 /* We can't call gen_lowpart_for_combine here since we always want
6035 a SUBREG and it would sometimes return a new hard register. */
6036 if (tmode
!= inner_mode
)
6038 int final_word
= pos
/ BITS_PER_WORD
;
6040 if (WORDS_BIG_ENDIAN
6041 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6042 final_word
= ((GET_MODE_SIZE (inner_mode
)
6043 - GET_MODE_SIZE (tmode
))
6044 / UNITS_PER_WORD
) - final_word
;
6046 final_word
*= UNITS_PER_WORD
;
6047 if (BYTES_BIG_ENDIAN
&&
6048 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6049 final_word
+= (GET_MODE_SIZE (inner_mode
)
6050 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6052 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6058 new = force_to_mode (inner
, tmode
,
6059 len
>= HOST_BITS_PER_WIDE_INT
6060 ? ~(unsigned HOST_WIDE_INT
) 0
6061 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6064 /* If this extraction is going into the destination of a SET,
6065 make a STRICT_LOW_PART unless we made a MEM. */
6068 return (GET_CODE (new) == MEM
? new
6069 : (GET_CODE (new) != SUBREG
6070 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6071 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6076 /* If we know that no extraneous bits are set, and that the high
6077 bit is not set, convert the extraction to the cheaper of
6078 sign and zero extension, that are equivalent in these cases. */
6079 if (flag_expensive_optimizations
6080 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6081 && ((nonzero_bits (new, tmode
)
6082 & ~(((unsigned HOST_WIDE_INT
)
6083 GET_MODE_MASK (tmode
))
6087 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6088 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6090 /* Prefer ZERO_EXTENSION, since it gives more information to
6092 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6097 /* Otherwise, sign- or zero-extend unless we already are in the
6100 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6104 /* Unless this is a COMPARE or we have a funny memory reference,
6105 don't do anything with zero-extending field extracts starting at
6106 the low-order bit since they are simple AND operations. */
6107 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6108 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6111 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6112 we would be spanning bytes or if the position is not a constant and the
6113 length is not 1. In all other cases, we would only be going outside
6114 our object in cases when an original shift would have been
6116 if (! spans_byte
&& GET_CODE (inner
) == MEM
6117 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6118 || (pos_rtx
!= 0 && len
!= 1)))
6121 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6122 and the mode for the result. */
6126 wanted_inner_reg_mode
6127 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
6128 if (wanted_inner_reg_mode
== VOIDmode
)
6129 wanted_inner_reg_mode
= word_mode
;
6131 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
6132 if (pos_mode
== VOIDmode
)
6133 pos_mode
= word_mode
;
6135 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6136 if (extraction_mode
== VOIDmode
)
6137 extraction_mode
= word_mode
;
6142 if (! in_dest
&& unsignedp
)
6144 wanted_inner_reg_mode
6145 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6146 if (wanted_inner_reg_mode
== VOIDmode
)
6147 wanted_inner_reg_mode
= word_mode
;
6149 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6150 if (pos_mode
== VOIDmode
)
6151 pos_mode
= word_mode
;
6153 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6154 if (extraction_mode
== VOIDmode
)
6155 extraction_mode
= word_mode
;
6160 if (! in_dest
&& ! unsignedp
)
6162 wanted_inner_reg_mode
6163 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6164 if (wanted_inner_reg_mode
== VOIDmode
)
6165 wanted_inner_reg_mode
= word_mode
;
6167 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6168 if (pos_mode
== VOIDmode
)
6169 pos_mode
= word_mode
;
6171 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6172 if (extraction_mode
== VOIDmode
)
6173 extraction_mode
= word_mode
;
6177 /* Never narrow an object, since that might not be safe. */
6179 if (mode
!= VOIDmode
6180 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6181 extraction_mode
= mode
;
6183 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6184 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6185 pos_mode
= GET_MODE (pos_rtx
);
6187 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6188 if we have to change the mode of memory and cannot, the desired mode is
6190 if (GET_CODE (inner
) != MEM
)
6191 wanted_inner_mode
= wanted_inner_reg_mode
;
6192 else if (inner_mode
!= wanted_inner_mode
6193 && (mode_dependent_address_p (XEXP (inner
, 0))
6194 || MEM_VOLATILE_P (inner
)))
6195 wanted_inner_mode
= extraction_mode
;
6199 if (BITS_BIG_ENDIAN
)
6201 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6202 BITS_BIG_ENDIAN style. If position is constant, compute new
6203 position. Otherwise, build subtraction.
6204 Note that POS is relative to the mode of the original argument.
6205 If it's a MEM we need to recompute POS relative to that.
6206 However, if we're extracting from (or inserting into) a register,
6207 we want to recompute POS relative to wanted_inner_mode. */
6208 int width
= (GET_CODE (inner
) == MEM
6209 ? GET_MODE_BITSIZE (is_mode
)
6210 : GET_MODE_BITSIZE (wanted_inner_mode
));
6213 pos
= width
- len
- pos
;
6216 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6217 /* POS may be less than 0 now, but we check for that below.
6218 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6221 /* If INNER has a wider mode, make it smaller. If this is a constant
6222 extract, try to adjust the byte to point to the byte containing
6224 if (wanted_inner_mode
!= VOIDmode
6225 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6226 && ((GET_CODE (inner
) == MEM
6227 && (inner_mode
== wanted_inner_mode
6228 || (! mode_dependent_address_p (XEXP (inner
, 0))
6229 && ! MEM_VOLATILE_P (inner
))))))
6233 /* The computations below will be correct if the machine is big
6234 endian in both bits and bytes or little endian in bits and bytes.
6235 If it is mixed, we must adjust. */
6237 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6238 adjust OFFSET to compensate. */
6239 if (BYTES_BIG_ENDIAN
6241 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6242 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6244 /* If this is a constant position, we can move to the desired byte. */
6247 offset
+= pos
/ BITS_PER_UNIT
;
6248 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6251 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6253 && is_mode
!= wanted_inner_mode
)
6254 offset
= (GET_MODE_SIZE (is_mode
)
6255 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6257 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6259 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6260 plus_constant (XEXP (inner
, 0), offset
));
6262 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6267 /* If INNER is not memory, we can always get it into the proper mode. If we
6268 are changing its mode, POS must be a constant and smaller than the size
6270 else if (GET_CODE (inner
) != MEM
)
6272 if (GET_MODE (inner
) != wanted_inner_mode
6274 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6277 inner
= force_to_mode (inner
, wanted_inner_mode
,
6279 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6280 ? ~(unsigned HOST_WIDE_INT
) 0
6281 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6286 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6287 have to zero extend. Otherwise, we can just use a SUBREG. */
6289 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6291 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6293 /* If we know that no extraneous bits are set, and that the high
6294 bit is not set, convert extraction to cheaper one - eighter
6295 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6297 if (flag_expensive_optimizations
6298 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6299 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6300 & ~(((unsigned HOST_WIDE_INT
)
6301 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6305 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6307 /* Prefer ZERO_EXTENSION, since it gives more information to
6309 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6314 else if (pos_rtx
!= 0
6315 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6316 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6318 /* Make POS_RTX unless we already have it and it is correct. If we don't
6319 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6321 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6322 pos_rtx
= orig_pos_rtx
;
6324 else if (pos_rtx
== 0)
6325 pos_rtx
= GEN_INT (pos
);
6327 /* Make the required operation. See if we can use existing rtx. */
6328 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6329 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6331 new = gen_lowpart_for_combine (mode
, new);
6336 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6337 with any other operations in X. Return X without that shift if so. */
6340 extract_left_shift (x
, count
)
6344 enum rtx_code code
= GET_CODE (x
);
6345 enum machine_mode mode
= GET_MODE (x
);
6351 /* This is the shift itself. If it is wide enough, we will return
6352 either the value being shifted if the shift count is equal to
6353 COUNT or a shift for the difference. */
6354 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6355 && INTVAL (XEXP (x
, 1)) >= count
)
6356 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6357 INTVAL (XEXP (x
, 1)) - count
);
6361 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6362 return simplify_gen_unary (code
, mode
, tem
, mode
);
6366 case PLUS
: case IOR
: case XOR
: case AND
:
6367 /* If we can safely shift this constant and we find the inner shift,
6368 make a new operation. */
6369 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6370 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6371 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6372 return gen_binary (code
, mode
, tem
,
6373 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6384 /* Look at the expression rooted at X. Look for expressions
6385 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6386 Form these expressions.
6388 Return the new rtx, usually just X.
6390 Also, for machines like the Vax that don't have logical shift insns,
6391 try to convert logical to arithmetic shift operations in cases where
6392 they are equivalent. This undoes the canonicalizations to logical
6393 shifts done elsewhere.
6395 We try, as much as possible, to re-use rtl expressions to save memory.
6397 IN_CODE says what kind of expression we are processing. Normally, it is
6398 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6399 being kludges), it is MEM. When processing the arguments of a comparison
6400 or a COMPARE against zero, it is COMPARE. */
6403 make_compound_operation (x
, in_code
)
6405 enum rtx_code in_code
;
6407 enum rtx_code code
= GET_CODE (x
);
6408 enum machine_mode mode
= GET_MODE (x
);
6409 int mode_width
= GET_MODE_BITSIZE (mode
);
6411 enum rtx_code next_code
;
6417 /* Select the code to be used in recursive calls. Once we are inside an
6418 address, we stay there. If we have a comparison, set to COMPARE,
6419 but once inside, go back to our default of SET. */
6421 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6422 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6423 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6424 : in_code
== COMPARE
? SET
: in_code
);
6426 /* Process depending on the code of this operation. If NEW is set
6427 non-zero, it will be returned. */
6432 /* Convert shifts by constants into multiplications if inside
6434 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6435 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6436 && INTVAL (XEXP (x
, 1)) >= 0)
6438 new = make_compound_operation (XEXP (x
, 0), next_code
);
6439 new = gen_rtx_MULT (mode
, new,
6440 GEN_INT ((HOST_WIDE_INT
) 1
6441 << INTVAL (XEXP (x
, 1))));
6446 /* If the second operand is not a constant, we can't do anything
6448 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6451 /* If the constant is a power of two minus one and the first operand
6452 is a logical right shift, make an extraction. */
6453 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6454 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6456 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6457 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6458 0, in_code
== COMPARE
);
6461 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6462 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6463 && subreg_lowpart_p (XEXP (x
, 0))
6464 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6465 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6467 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6469 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6470 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6471 0, in_code
== COMPARE
);
6473 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6474 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6475 || GET_CODE (XEXP (x
, 0)) == IOR
)
6476 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6477 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6478 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6480 /* Apply the distributive law, and then try to make extractions. */
6481 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6482 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6484 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6486 new = make_compound_operation (new, in_code
);
6489 /* If we are have (and (rotate X C) M) and C is larger than the number
6490 of bits in M, this is an extraction. */
6492 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6493 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6494 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6495 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6497 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6498 new = make_extraction (mode
, new,
6499 (GET_MODE_BITSIZE (mode
)
6500 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6501 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6504 /* On machines without logical shifts, if the operand of the AND is
6505 a logical shift and our mask turns off all the propagated sign
6506 bits, we can replace the logical shift with an arithmetic shift. */
6507 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6508 && (lshr_optab
->handlers
[(int) mode
].insn_code
6509 == CODE_FOR_nothing
)
6510 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6511 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6512 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6513 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6514 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6516 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6518 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6519 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6521 gen_rtx_ASHIFTRT (mode
,
6522 make_compound_operation
6523 (XEXP (XEXP (x
, 0), 0), next_code
),
6524 XEXP (XEXP (x
, 0), 1)));
6527 /* If the constant is one less than a power of two, this might be
6528 representable by an extraction even if no shift is present.
6529 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6530 we are in a COMPARE. */
6531 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6532 new = make_extraction (mode
,
6533 make_compound_operation (XEXP (x
, 0),
6535 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6537 /* If we are in a comparison and this is an AND with a power of two,
6538 convert this into the appropriate bit extract. */
6539 else if (in_code
== COMPARE
6540 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6541 new = make_extraction (mode
,
6542 make_compound_operation (XEXP (x
, 0),
6544 i
, NULL_RTX
, 1, 1, 0, 1);
6549 /* If the sign bit is known to be zero, replace this with an
6550 arithmetic shift. */
6551 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6552 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6553 && mode_width
<= HOST_BITS_PER_WIDE_INT
6554 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6556 new = gen_rtx_ASHIFTRT (mode
,
6557 make_compound_operation (XEXP (x
, 0),
6563 /* ... fall through ... */
6569 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6570 this is a SIGN_EXTRACT. */
6571 if (GET_CODE (rhs
) == CONST_INT
6572 && GET_CODE (lhs
) == ASHIFT
6573 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6574 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6576 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6577 new = make_extraction (mode
, new,
6578 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6579 NULL_RTX
, mode_width
- INTVAL (rhs
),
6580 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6584 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6585 If so, try to merge the shifts into a SIGN_EXTEND. We could
6586 also do this for some cases of SIGN_EXTRACT, but it doesn't
6587 seem worth the effort; the case checked for occurs on Alpha. */
6589 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6590 && ! (GET_CODE (lhs
) == SUBREG
6591 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6592 && GET_CODE (rhs
) == CONST_INT
6593 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6594 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6595 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6596 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6597 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6602 /* Call ourselves recursively on the inner expression. If we are
6603 narrowing the object and it has a different RTL code from
6604 what it originally did, do this SUBREG as a force_to_mode. */
6606 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6607 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6608 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6609 && subreg_lowpart_p (x
))
6611 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6614 /* If we have something other than a SUBREG, we might have
6615 done an expansion, so rerun outselves. */
6616 if (GET_CODE (newer
) != SUBREG
)
6617 newer
= make_compound_operation (newer
, in_code
);
6622 /* If this is a paradoxical subreg, and the new code is a sign or
6623 zero extension, omit the subreg and widen the extension. If it
6624 is a regular subreg, we can still get rid of the subreg by not
6625 widening so much, or in fact removing the extension entirely. */
6626 if ((GET_CODE (tem
) == SIGN_EXTEND
6627 || GET_CODE (tem
) == ZERO_EXTEND
)
6628 && subreg_lowpart_p (x
))
6630 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6631 || (GET_MODE_SIZE (mode
) >
6632 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6633 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6635 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6646 x
= gen_lowpart_for_combine (mode
, new);
6647 code
= GET_CODE (x
);
6650 /* Now recursively process each operand of this operation. */
6651 fmt
= GET_RTX_FORMAT (code
);
6652 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6655 new = make_compound_operation (XEXP (x
, i
), next_code
);
6656 SUBST (XEXP (x
, i
), new);
6662 /* Given M see if it is a value that would select a field of bits
6663 within an item, but not the entire word. Return -1 if not.
6664 Otherwise, return the starting position of the field, where 0 is the
6667 *PLEN is set to the length of the field. */
6670 get_pos_from_mask (m
, plen
)
6671 unsigned HOST_WIDE_INT m
;
6672 unsigned HOST_WIDE_INT
*plen
;
6674 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6675 int pos
= exact_log2 (m
& -m
);
6681 /* Now shift off the low-order zero bits and see if we have a power of
6683 len
= exact_log2 ((m
>> pos
) + 1);
6692 /* See if X can be simplified knowing that we will only refer to it in
6693 MODE and will only refer to those bits that are nonzero in MASK.
6694 If other bits are being computed or if masking operations are done
6695 that select a superset of the bits in MASK, they can sometimes be
6698 Return a possibly simplified expression, but always convert X to
6699 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6701 Also, if REG is non-zero and X is a register equal in value to REG,
6704 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6705 are all off in X. This is used when X will be complemented, by either
6706 NOT, NEG, or XOR. */
6709 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6711 enum machine_mode mode
;
6712 unsigned HOST_WIDE_INT mask
;
6716 enum rtx_code code
= GET_CODE (x
);
6717 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6718 enum machine_mode op_mode
;
6719 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6722 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6723 code below will do the wrong thing since the mode of such an
6724 expression is VOIDmode.
6726 Also do nothing if X is a CLOBBER; this can happen if X was
6727 the return value from a call to gen_lowpart_for_combine. */
6728 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6731 /* We want to perform the operation is its present mode unless we know
6732 that the operation is valid in MODE, in which case we do the operation
6734 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6735 && code_to_optab
[(int) code
] != 0
6736 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6737 != CODE_FOR_nothing
))
6738 ? mode
: GET_MODE (x
));
6740 /* It is not valid to do a right-shift in a narrower mode
6741 than the one it came in with. */
6742 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6743 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6744 op_mode
= GET_MODE (x
);
6746 /* Truncate MASK to fit OP_MODE. */
6748 mask
&= GET_MODE_MASK (op_mode
);
6750 /* When we have an arithmetic operation, or a shift whose count we
6751 do not know, we need to assume that all bit the up to the highest-order
6752 bit in MASK will be needed. This is how we form such a mask. */
6754 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6755 ? GET_MODE_MASK (op_mode
)
6756 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6759 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6761 /* Determine what bits of X are guaranteed to be (non)zero. */
6762 nonzero
= nonzero_bits (x
, mode
);
6764 /* If none of the bits in X are needed, return a zero. */
6765 if (! just_select
&& (nonzero
& mask
) == 0)
6768 /* If X is a CONST_INT, return a new one. Do this here since the
6769 test below will fail. */
6770 if (GET_CODE (x
) == CONST_INT
)
6772 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6773 int width
= GET_MODE_BITSIZE (mode
);
6775 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6776 number, sign extend it. */
6777 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6778 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6779 cval
|= (HOST_WIDE_INT
) -1 << width
;
6781 return GEN_INT (cval
);
6784 /* If X is narrower than MODE and we want all the bits in X's mode, just
6785 get X in the proper mode. */
6786 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6787 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6788 return gen_lowpart_for_combine (mode
, x
);
6790 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6791 MASK are already known to be zero in X, we need not do anything. */
6792 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6798 /* If X is a (clobber (const_int)), return it since we know we are
6799 generating something that won't match. */
6803 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6804 spanned the boundary of the MEM. If we are now masking so it is
6805 within that boundary, we don't need the USE any more. */
6806 if (! BITS_BIG_ENDIAN
6807 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6808 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6815 x
= expand_compound_operation (x
);
6816 if (GET_CODE (x
) != code
)
6817 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6821 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6822 || rtx_equal_p (reg
, get_last_value (x
))))
6827 if (subreg_lowpart_p (x
)
6828 /* We can ignore the effect of this SUBREG if it narrows the mode or
6829 if the constant masks to zero all the bits the mode doesn't
6831 && ((GET_MODE_SIZE (GET_MODE (x
))
6832 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6834 & GET_MODE_MASK (GET_MODE (x
))
6835 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6836 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6840 /* If this is an AND with a constant, convert it into an AND
6841 whose constant is the AND of that constant with MASK. If it
6842 remains an AND of MASK, delete it since it is redundant. */
6844 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6846 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6847 mask
& INTVAL (XEXP (x
, 1)));
6849 /* If X is still an AND, see if it is an AND with a mask that
6850 is just some low-order bits. If so, and it is MASK, we don't
6853 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6854 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6857 /* If it remains an AND, try making another AND with the bits
6858 in the mode mask that aren't in MASK turned on. If the
6859 constant in the AND is wide enough, this might make a
6860 cheaper constant. */
6862 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6863 && GET_MODE_MASK (GET_MODE (x
)) != mask
6864 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6866 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6867 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6868 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6871 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6872 number, sign extend it. */
6873 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6874 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6875 cval
|= (HOST_WIDE_INT
) -1 << width
;
6877 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6878 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6888 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6889 low-order bits (as in an alignment operation) and FOO is already
6890 aligned to that boundary, mask C1 to that boundary as well.
6891 This may eliminate that PLUS and, later, the AND. */
6894 unsigned int width
= GET_MODE_BITSIZE (mode
);
6895 unsigned HOST_WIDE_INT smask
= mask
;
6897 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6898 number, sign extend it. */
6900 if (width
< HOST_BITS_PER_WIDE_INT
6901 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6902 smask
|= (HOST_WIDE_INT
) -1 << width
;
6904 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6905 && exact_log2 (- smask
) >= 0)
6909 && (XEXP (x
, 0) == stack_pointer_rtx
6910 || XEXP (x
, 0) == frame_pointer_rtx
))
6912 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6913 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6915 sp_mask
&= ~(sp_alignment
- 1);
6916 if ((sp_mask
& ~smask
) == 0
6917 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6918 return force_to_mode (plus_constant (XEXP (x
, 0),
6919 ((INTVAL (XEXP (x
, 1)) -
6920 STACK_BIAS
) & smask
)
6922 mode
, smask
, reg
, next_select
);
6925 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6926 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6927 return force_to_mode (plus_constant (XEXP (x
, 0),
6928 (INTVAL (XEXP (x
, 1))
6930 mode
, smask
, reg
, next_select
);
6934 /* ... fall through ... */
6937 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6938 most significant bit in MASK since carries from those bits will
6939 affect the bits we are interested in. */
6944 /* If X is (minus C Y) where C's least set bit is larger than any bit
6945 in the mask, then we may replace with (neg Y). */
6946 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6947 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6948 & -INTVAL (XEXP (x
, 0))))
6951 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6953 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6956 /* Similarly, if C contains every bit in the mask, then we may
6957 replace with (not Y). */
6958 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6959 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6960 == INTVAL (XEXP (x
, 0))))
6962 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6963 XEXP (x
, 1), GET_MODE (x
));
6964 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6972 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6973 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6974 operation which may be a bitfield extraction. Ensure that the
6975 constant we form is not wider than the mode of X. */
6977 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6978 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6979 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6980 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6981 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6982 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6983 + floor_log2 (INTVAL (XEXP (x
, 1))))
6984 < GET_MODE_BITSIZE (GET_MODE (x
)))
6985 && (INTVAL (XEXP (x
, 1))
6986 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6988 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6989 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6990 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6991 XEXP (XEXP (x
, 0), 0), temp
);
6992 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6993 XEXP (XEXP (x
, 0), 1));
6994 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6998 /* For most binary operations, just propagate into the operation and
6999 change the mode if we have an operation of that mode. */
7001 op0
= gen_lowpart_for_combine (op_mode
,
7002 force_to_mode (XEXP (x
, 0), mode
, mask
,
7004 op1
= gen_lowpart_for_combine (op_mode
,
7005 force_to_mode (XEXP (x
, 1), mode
, mask
,
7008 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
7009 MASK since OP1 might have been sign-extended but we never want
7010 to turn on extra bits, since combine might have previously relied
7011 on them being off. */
7012 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
7013 && (INTVAL (op1
) & mask
) != 0)
7014 op1
= GEN_INT (INTVAL (op1
) & mask
);
7016 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7017 x
= gen_binary (code
, op_mode
, op0
, op1
);
7021 /* For left shifts, do the same, but just for the first operand.
7022 However, we cannot do anything with shifts where we cannot
7023 guarantee that the counts are smaller than the size of the mode
7024 because such a count will have a different meaning in a
7027 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7028 && INTVAL (XEXP (x
, 1)) >= 0
7029 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7030 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7031 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7032 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7035 /* If the shift count is a constant and we can do arithmetic in
7036 the mode of the shift, refine which bits we need. Otherwise, use the
7037 conservative form of the mask. */
7038 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7039 && INTVAL (XEXP (x
, 1)) >= 0
7040 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7041 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7042 mask
>>= INTVAL (XEXP (x
, 1));
7046 op0
= gen_lowpart_for_combine (op_mode
,
7047 force_to_mode (XEXP (x
, 0), op_mode
,
7048 mask
, reg
, next_select
));
7050 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7051 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7055 /* Here we can only do something if the shift count is a constant,
7056 this shift constant is valid for the host, and we can do arithmetic
7059 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7060 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7061 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7063 rtx inner
= XEXP (x
, 0);
7064 unsigned HOST_WIDE_INT inner_mask
;
7066 /* Select the mask of the bits we need for the shift operand. */
7067 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7069 /* We can only change the mode of the shift if we can do arithmetic
7070 in the mode of the shift and INNER_MASK is no wider than the
7071 width of OP_MODE. */
7072 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7073 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7074 op_mode
= GET_MODE (x
);
7076 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7078 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7079 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7082 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7083 shift and AND produces only copies of the sign bit (C2 is one less
7084 than a power of two), we can do this with just a shift. */
7086 if (GET_CODE (x
) == LSHIFTRT
7087 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7088 /* The shift puts one of the sign bit copies in the least significant
7090 && ((INTVAL (XEXP (x
, 1))
7091 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7092 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7093 && exact_log2 (mask
+ 1) >= 0
7094 /* Number of bits left after the shift must be more than the mask
7096 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7097 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7098 /* Must be more sign bit copies than the mask needs. */
7099 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7100 >= exact_log2 (mask
+ 1)))
7101 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7102 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7103 - exact_log2 (mask
+ 1)));
7108 /* If we are just looking for the sign bit, we don't need this shift at
7109 all, even if it has a variable count. */
7110 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7111 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7112 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7113 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7115 /* If this is a shift by a constant, get a mask that contains those bits
7116 that are not copies of the sign bit. We then have two cases: If
7117 MASK only includes those bits, this can be a logical shift, which may
7118 allow simplifications. If MASK is a single-bit field not within
7119 those bits, we are requesting a copy of the sign bit and hence can
7120 shift the sign bit to the appropriate location. */
7122 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7123 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7127 /* If the considered data is wider then HOST_WIDE_INT, we can't
7128 represent a mask for all its bits in a single scalar.
7129 But we only care about the lower bits, so calculate these. */
7131 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7133 nonzero
= ~(HOST_WIDE_INT
) 0;
7135 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7136 is the number of bits a full-width mask would have set.
7137 We need only shift if these are fewer than nonzero can
7138 hold. If not, we must keep all bits set in nonzero. */
7140 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7141 < HOST_BITS_PER_WIDE_INT
)
7142 nonzero
>>= INTVAL (XEXP (x
, 1))
7143 + HOST_BITS_PER_WIDE_INT
7144 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7148 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7149 nonzero
>>= INTVAL (XEXP (x
, 1));
7152 if ((mask
& ~nonzero
) == 0
7153 || (i
= exact_log2 (mask
)) >= 0)
7155 x
= simplify_shift_const
7156 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7157 i
< 0 ? INTVAL (XEXP (x
, 1))
7158 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7160 if (GET_CODE (x
) != ASHIFTRT
)
7161 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7165 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7166 even if the shift count isn't a constant. */
7168 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7172 /* If this is a zero- or sign-extension operation that just affects bits
7173 we don't care about, remove it. Be sure the call above returned
7174 something that is still a shift. */
7176 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7177 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7178 && INTVAL (XEXP (x
, 1)) >= 0
7179 && (INTVAL (XEXP (x
, 1))
7180 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7181 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7182 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7183 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7184 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7191 /* If the shift count is constant and we can do computations
7192 in the mode of X, compute where the bits we care about are.
7193 Otherwise, we can't do anything. Don't change the mode of
7194 the shift or propagate MODE into the shift, though. */
7195 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7196 && INTVAL (XEXP (x
, 1)) >= 0)
7198 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7199 GET_MODE (x
), GEN_INT (mask
),
7201 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7203 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7204 INTVAL (temp
), reg
, next_select
));
7209 /* If we just want the low-order bit, the NEG isn't needed since it
7210 won't change the low-order bit. */
7212 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7214 /* We need any bits less significant than the most significant bit in
7215 MASK since carries from those bits will affect the bits we are
7221 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7222 same as the XOR case above. Ensure that the constant we form is not
7223 wider than the mode of X. */
7225 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7226 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7227 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7228 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7229 < GET_MODE_BITSIZE (GET_MODE (x
)))
7230 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7232 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7233 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7234 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7236 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7239 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7240 use the full mask inside the NOT. */
7244 op0
= gen_lowpart_for_combine (op_mode
,
7245 force_to_mode (XEXP (x
, 0), mode
, mask
,
7247 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7248 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7252 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7253 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7254 which is equal to STORE_FLAG_VALUE. */
7255 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7256 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7257 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7258 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7263 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7264 written in a narrower mode. We play it safe and do not do so. */
7267 gen_lowpart_for_combine (GET_MODE (x
),
7268 force_to_mode (XEXP (x
, 1), mode
,
7269 mask
, reg
, next_select
)));
7271 gen_lowpart_for_combine (GET_MODE (x
),
7272 force_to_mode (XEXP (x
, 2), mode
,
7273 mask
, reg
,next_select
)));
7280 /* Ensure we return a value of the proper mode. */
7281 return gen_lowpart_for_combine (mode
, x
);
7284 /* Return nonzero if X is an expression that has one of two values depending on
7285 whether some other value is zero or nonzero. In that case, we return the
7286 value that is being tested, *PTRUE is set to the value if the rtx being
7287 returned has a nonzero value, and *PFALSE is set to the other alternative.
7289 If we return zero, we set *PTRUE and *PFALSE to X. */
7292 if_then_else_cond (x
, ptrue
, pfalse
)
7294 rtx
*ptrue
, *pfalse
;
7296 enum machine_mode mode
= GET_MODE (x
);
7297 enum rtx_code code
= GET_CODE (x
);
7298 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7299 unsigned HOST_WIDE_INT nz
;
7301 /* If we are comparing a value against zero, we are done. */
7302 if ((code
== NE
|| code
== EQ
)
7303 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7305 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7306 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7310 /* If this is a unary operation whose operand has one of two values, apply
7311 our opcode to compute those values. */
7312 else if (GET_RTX_CLASS (code
) == '1'
7313 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7315 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7316 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7317 GET_MODE (XEXP (x
, 0)));
7321 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7322 make can't possibly match and would suppress other optimizations. */
7323 else if (code
== COMPARE
)
7326 /* If this is a binary operation, see if either side has only one of two
7327 values. If either one does or if both do and they are conditional on
7328 the same value, compute the new true and false values. */
7329 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7330 || GET_RTX_CLASS (code
) == '<')
7332 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7333 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7335 if ((cond0
!= 0 || cond1
!= 0)
7336 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7338 /* If if_then_else_cond returned zero, then true/false are the
7339 same rtl. We must copy one of them to prevent invalid rtl
7342 true0
= copy_rtx (true0
);
7343 else if (cond1
== 0)
7344 true1
= copy_rtx (true1
);
7346 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7347 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7348 return cond0
? cond0
: cond1
;
7351 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7352 operands is zero when the other is non-zero, and vice-versa,
7353 and STORE_FLAG_VALUE is 1 or -1. */
7355 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7356 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7358 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7360 rtx op0
= XEXP (XEXP (x
, 0), 1);
7361 rtx op1
= XEXP (XEXP (x
, 1), 1);
7363 cond0
= XEXP (XEXP (x
, 0), 0);
7364 cond1
= XEXP (XEXP (x
, 1), 0);
7366 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7367 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7368 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7369 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7370 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7371 || ((swap_condition (GET_CODE (cond0
))
7372 == combine_reversed_comparison_code (cond1
))
7373 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7374 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7375 && ! side_effects_p (x
))
7377 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7378 *pfalse
= gen_binary (MULT
, mode
,
7380 ? simplify_gen_unary (NEG
, mode
, op1
,
7388 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7390 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7391 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7392 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7394 cond0
= XEXP (XEXP (x
, 0), 0);
7395 cond1
= XEXP (XEXP (x
, 1), 0);
7397 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7398 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7399 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7400 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7401 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7402 || ((swap_condition (GET_CODE (cond0
))
7403 == combine_reversed_comparison_code (cond1
))
7404 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7405 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7406 && ! side_effects_p (x
))
7408 *ptrue
= *pfalse
= const0_rtx
;
7414 else if (code
== IF_THEN_ELSE
)
7416 /* If we have IF_THEN_ELSE already, extract the condition and
7417 canonicalize it if it is NE or EQ. */
7418 cond0
= XEXP (x
, 0);
7419 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7420 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7421 return XEXP (cond0
, 0);
7422 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7424 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7425 return XEXP (cond0
, 0);
7431 /* If X is a normal SUBREG with both inner and outer modes integral,
7432 we can narrow both the true and false values of the inner expression,
7433 if there is a condition. */
7434 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7435 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7436 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7437 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7440 if ((GET_CODE (SUBREG_REG (x
)) == REG
7441 || GET_CODE (SUBREG_REG (x
)) == MEM
7442 || CONSTANT_P (SUBREG_REG (x
)))
7443 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
7444 && (WORDS_BIG_ENDIAN
|| SUBREG_BYTE (x
) >= UNITS_PER_WORD
))
7446 true0
= operand_subword (true0
, SUBREG_BYTE (x
) / UNITS_PER_WORD
, 0,
7447 GET_MODE (SUBREG_REG (x
)));
7448 false0
= operand_subword (false0
, SUBREG_BYTE (x
) / UNITS_PER_WORD
, 0,
7449 GET_MODE (SUBREG_REG (x
)));
7451 *ptrue
= force_to_mode (true0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7453 = force_to_mode (false0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7458 /* If X is a constant, this isn't special and will cause confusions
7459 if we treat it as such. Likewise if it is equivalent to a constant. */
7460 else if (CONSTANT_P (x
)
7461 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7464 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7465 will be least confusing to the rest of the compiler. */
7466 else if (mode
== BImode
)
7468 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7472 /* If X is known to be either 0 or -1, those are the true and
7473 false values when testing X. */
7474 else if (x
== constm1_rtx
|| x
== const0_rtx
7475 || (mode
!= VOIDmode
7476 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7478 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7482 /* Likewise for 0 or a single bit. */
7483 else if (mode
!= VOIDmode
7484 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7485 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7487 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7491 /* Otherwise fail; show no condition with true and false values the same. */
7492 *ptrue
= *pfalse
= x
;
7496 /* Return the value of expression X given the fact that condition COND
7497 is known to be true when applied to REG as its first operand and VAL
7498 as its second. X is known to not be shared and so can be modified in
7501 We only handle the simplest cases, and specifically those cases that
7502 arise with IF_THEN_ELSE expressions. */
7505 known_cond (x
, cond
, reg
, val
)
7510 enum rtx_code code
= GET_CODE (x
);
7515 if (side_effects_p (x
))
7518 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7520 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7523 /* If X is (abs REG) and we know something about REG's relationship
7524 with zero, we may be able to simplify this. */
7526 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7529 case GE
: case GT
: case EQ
:
7532 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7534 GET_MODE (XEXP (x
, 0)));
7539 /* The only other cases we handle are MIN, MAX, and comparisons if the
7540 operands are the same as REG and VAL. */
7542 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7544 if (rtx_equal_p (XEXP (x
, 0), val
))
7545 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7547 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7549 if (GET_RTX_CLASS (code
) == '<')
7551 if (comparison_dominates_p (cond
, code
))
7552 return const_true_rtx
;
7554 code
= combine_reversed_comparison_code (x
);
7556 && comparison_dominates_p (cond
, code
))
7561 else if (code
== SMAX
|| code
== SMIN
7562 || code
== UMIN
|| code
== UMAX
)
7564 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7566 /* Do not reverse the condition when it is NE or EQ.
7567 This is because we cannot conclude anything about
7568 the value of 'SMAX (x, y)' when x is not equal to y,
7569 but we can when x equals y. */
7570 if ((code
== SMAX
|| code
== UMAX
)
7571 && ! (cond
== EQ
|| cond
== NE
))
7572 cond
= reverse_condition (cond
);
7577 return unsignedp
? x
: XEXP (x
, 1);
7579 return unsignedp
? x
: XEXP (x
, 0);
7581 return unsignedp
? XEXP (x
, 1) : x
;
7583 return unsignedp
? XEXP (x
, 0) : x
;
7591 fmt
= GET_RTX_FORMAT (code
);
7592 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7595 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7596 else if (fmt
[i
] == 'E')
7597 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7598 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7605 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7606 assignment as a field assignment. */
7609 rtx_equal_for_field_assignment_p (x
, y
)
7613 if (x
== y
|| rtx_equal_p (x
, y
))
7616 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7619 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7620 Note that all SUBREGs of MEM are paradoxical; otherwise they
7621 would have been rewritten. */
7622 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7623 && GET_CODE (SUBREG_REG (y
)) == MEM
7624 && rtx_equal_p (SUBREG_REG (y
),
7625 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7628 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7629 && GET_CODE (SUBREG_REG (x
)) == MEM
7630 && rtx_equal_p (SUBREG_REG (x
),
7631 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7634 /* We used to see if get_last_value of X and Y were the same but that's
7635 not correct. In one direction, we'll cause the assignment to have
7636 the wrong destination and in the case, we'll import a register into this
7637 insn that might have already have been dead. So fail if none of the
7638 above cases are true. */
7642 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7643 Return that assignment if so.
7645 We only handle the most common cases. */
7648 make_field_assignment (x
)
7651 rtx dest
= SET_DEST (x
);
7652 rtx src
= SET_SRC (x
);
7657 unsigned HOST_WIDE_INT len
;
7659 enum machine_mode mode
;
7661 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7662 a clear of a one-bit field. We will have changed it to
7663 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7666 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7667 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7668 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7669 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7671 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7674 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7678 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7679 && subreg_lowpart_p (XEXP (src
, 0))
7680 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7681 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7682 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7683 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7684 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7686 assign
= make_extraction (VOIDmode
, dest
, 0,
7687 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7690 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7694 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7696 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7697 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7698 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7700 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7703 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7707 /* The other case we handle is assignments into a constant-position
7708 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7709 a mask that has all one bits except for a group of zero bits and
7710 OTHER is known to have zeros where C1 has ones, this is such an
7711 assignment. Compute the position and length from C1. Shift OTHER
7712 to the appropriate position, force it to the required mode, and
7713 make the extraction. Check for the AND in both operands. */
7715 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7718 rhs
= expand_compound_operation (XEXP (src
, 0));
7719 lhs
= expand_compound_operation (XEXP (src
, 1));
7721 if (GET_CODE (rhs
) == AND
7722 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7723 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7724 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7725 else if (GET_CODE (lhs
) == AND
7726 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7727 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7728 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7732 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7733 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7734 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7735 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7738 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7742 /* The mode to use for the source is the mode of the assignment, or of
7743 what is inside a possible STRICT_LOW_PART. */
7744 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7745 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7747 /* Shift OTHER right POS places and make it the source, restricting it
7748 to the proper length and mode. */
7750 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7751 GET_MODE (src
), other
, pos
),
7753 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7754 ? ~(unsigned HOST_WIDE_INT
) 0
7755 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7758 return gen_rtx_SET (VOIDmode
, assign
, src
);
7761 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7765 apply_distributive_law (x
)
7768 enum rtx_code code
= GET_CODE (x
);
7769 rtx lhs
, rhs
, other
;
7771 enum rtx_code inner_code
;
7773 /* Distributivity is not true for floating point.
7774 It can change the value. So don't do it.
7775 -- rms and moshier@world.std.com. */
7776 if (FLOAT_MODE_P (GET_MODE (x
)))
7779 /* The outer operation can only be one of the following: */
7780 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7781 && code
!= PLUS
&& code
!= MINUS
)
7784 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7786 /* If either operand is a primitive we can't do anything, so get out
7788 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7789 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7792 lhs
= expand_compound_operation (lhs
);
7793 rhs
= expand_compound_operation (rhs
);
7794 inner_code
= GET_CODE (lhs
);
7795 if (inner_code
!= GET_CODE (rhs
))
7798 /* See if the inner and outer operations distribute. */
7805 /* These all distribute except over PLUS. */
7806 if (code
== PLUS
|| code
== MINUS
)
7811 if (code
!= PLUS
&& code
!= MINUS
)
7816 /* This is also a multiply, so it distributes over everything. */
7820 /* Non-paradoxical SUBREGs distributes over all operations, provided
7821 the inner modes and byte offsets are the same, this is an extraction
7822 of a low-order part, we don't convert an fp operation to int or
7823 vice versa, and we would not be converting a single-word
7824 operation into a multi-word operation. The latter test is not
7825 required, but it prevents generating unneeded multi-word operations.
7826 Some of the previous tests are redundant given the latter test, but
7827 are retained because they are required for correctness.
7829 We produce the result slightly differently in this case. */
7831 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7832 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7833 || ! subreg_lowpart_p (lhs
)
7834 || (GET_MODE_CLASS (GET_MODE (lhs
))
7835 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7836 || (GET_MODE_SIZE (GET_MODE (lhs
))
7837 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7838 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7841 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7842 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7843 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7849 /* Set LHS and RHS to the inner operands (A and B in the example
7850 above) and set OTHER to the common operand (C in the example).
7851 These is only one way to do this unless the inner operation is
7853 if (GET_RTX_CLASS (inner_code
) == 'c'
7854 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7855 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7856 else if (GET_RTX_CLASS (inner_code
) == 'c'
7857 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7858 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7859 else if (GET_RTX_CLASS (inner_code
) == 'c'
7860 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7861 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7862 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7863 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7867 /* Form the new inner operation, seeing if it simplifies first. */
7868 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7870 /* There is one exception to the general way of distributing:
7871 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7872 if (code
== XOR
&& inner_code
== IOR
)
7875 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7878 /* We may be able to continuing distributing the result, so call
7879 ourselves recursively on the inner operation before forming the
7880 outer operation, which we return. */
7881 return gen_binary (inner_code
, GET_MODE (x
),
7882 apply_distributive_law (tem
), other
);
7885 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7888 Return an equivalent form, if different from X. Otherwise, return X. If
7889 X is zero, we are to always construct the equivalent form. */
7892 simplify_and_const_int (x
, mode
, varop
, constop
)
7894 enum machine_mode mode
;
7896 unsigned HOST_WIDE_INT constop
;
7898 unsigned HOST_WIDE_INT nonzero
;
7901 /* Simplify VAROP knowing that we will be only looking at some of the
7903 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7905 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7906 CONST_INT, we are done. */
7907 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7910 /* See what bits may be nonzero in VAROP. Unlike the general case of
7911 a call to nonzero_bits, here we don't care about bits outside
7914 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7915 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7917 /* Turn off all bits in the constant that are known to already be zero.
7918 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7919 which is tested below. */
7923 /* If we don't have any bits left, return zero. */
7927 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7928 a power of two, we can replace this with a ASHIFT. */
7929 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7930 && (i
= exact_log2 (constop
)) >= 0)
7931 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7933 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7934 or XOR, then try to apply the distributive law. This may eliminate
7935 operations if either branch can be simplified because of the AND.
7936 It may also make some cases more complex, but those cases probably
7937 won't match a pattern either with or without this. */
7939 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7941 gen_lowpart_for_combine
7943 apply_distributive_law
7944 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7945 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7946 XEXP (varop
, 0), constop
),
7947 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7948 XEXP (varop
, 1), constop
))));
7950 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7951 if we already had one (just check for the simplest cases). */
7952 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7953 && GET_MODE (XEXP (x
, 0)) == mode
7954 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7955 varop
= XEXP (x
, 0);
7957 varop
= gen_lowpart_for_combine (mode
, varop
);
7959 /* If we can't make the SUBREG, try to return what we were given. */
7960 if (GET_CODE (varop
) == CLOBBER
)
7961 return x
? x
: varop
;
7963 /* If we are only masking insignificant bits, return VAROP. */
7964 if (constop
== nonzero
)
7967 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7968 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7969 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7973 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7974 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7975 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7977 SUBST (XEXP (x
, 0), varop
);
7983 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7984 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7985 is less useful. We can't allow both, because that results in exponential
7986 run time recursion. There is a nullstone testcase that triggered
7987 this. This macro avoids accidental uses of num_sign_bit_copies. */
7988 #define num_sign_bit_copies()
7990 /* Given an expression, X, compute which bits in X can be non-zero.
7991 We don't care about bits outside of those defined in MODE.
7993 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7994 a shift, AND, or zero_extract, we can do better. */
7996 static unsigned HOST_WIDE_INT
7997 nonzero_bits (x
, mode
)
7999 enum machine_mode mode
;
8001 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8002 unsigned HOST_WIDE_INT inner_nz
;
8004 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8007 /* For floating-point values, assume all bits are needed. */
8008 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8011 /* If X is wider than MODE, use its mode instead. */
8012 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8014 mode
= GET_MODE (x
);
8015 nonzero
= GET_MODE_MASK (mode
);
8016 mode_width
= GET_MODE_BITSIZE (mode
);
8019 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8020 /* Our only callers in this case look for single bit values. So
8021 just return the mode mask. Those tests will then be false. */
8024 #ifndef WORD_REGISTER_OPERATIONS
8025 /* If MODE is wider than X, but both are a single word for both the host
8026 and target machines, we can compute this from which bits of the
8027 object might be nonzero in its own mode, taking into account the fact
8028 that on many CISC machines, accessing an object in a wider mode
8029 causes the high-order bits to become undefined. So they are
8030 not known to be zero. */
8032 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8033 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8034 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8035 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8037 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8038 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8043 code
= GET_CODE (x
);
8047 #ifdef POINTERS_EXTEND_UNSIGNED
8048 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8049 all the bits above ptr_mode are known to be zero. */
8050 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8052 nonzero
&= GET_MODE_MASK (ptr_mode
);
8055 #ifdef STACK_BOUNDARY
8056 /* If this is the stack pointer, we may know something about its
8057 alignment. If PUSH_ROUNDING is defined, it is possible for the
8058 stack to be momentarily aligned only to that amount, so we pick
8059 the least alignment. */
8061 /* We can't check for arg_pointer_rtx here, because it is not
8062 guaranteed to have as much alignment as the stack pointer.
8063 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8064 alignment but the argument pointer has only 64 bit alignment. */
8066 if ((x
== frame_pointer_rtx
8067 || x
== stack_pointer_rtx
8068 || x
== hard_frame_pointer_rtx
8069 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
8070 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
8076 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8078 #ifdef PUSH_ROUNDING
8079 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
8080 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
8083 /* We must return here, otherwise we may get a worse result from
8084 one of the choices below. There is nothing useful below as
8085 far as the stack pointer is concerned. */
8086 return nonzero
&= ~(sp_alignment
- 1);
8090 /* If X is a register whose nonzero bits value is current, use it.
8091 Otherwise, if X is a register whose value we can find, use that
8092 value. Otherwise, use the previously-computed global nonzero bits
8093 for this register. */
8095 if (reg_last_set_value
[REGNO (x
)] != 0
8096 && reg_last_set_mode
[REGNO (x
)] == mode
8097 && (reg_last_set_label
[REGNO (x
)] == label_tick
8098 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8099 && REG_N_SETS (REGNO (x
)) == 1
8100 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8102 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8103 return reg_last_set_nonzero_bits
[REGNO (x
)];
8105 tem
= get_last_value (x
);
8109 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8110 /* If X is narrower than MODE and TEM is a non-negative
8111 constant that would appear negative in the mode of X,
8112 sign-extend it for use in reg_nonzero_bits because some
8113 machines (maybe most) will actually do the sign-extension
8114 and this is the conservative approach.
8116 ??? For 2.5, try to tighten up the MD files in this regard
8117 instead of this kludge. */
8119 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8120 && GET_CODE (tem
) == CONST_INT
8122 && 0 != (INTVAL (tem
)
8123 & ((HOST_WIDE_INT
) 1
8124 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8125 tem
= GEN_INT (INTVAL (tem
)
8126 | ((HOST_WIDE_INT
) (-1)
8127 << GET_MODE_BITSIZE (GET_MODE (x
))));
8129 return nonzero_bits (tem
, mode
);
8131 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8132 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
8137 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8138 /* If X is negative in MODE, sign-extend the value. */
8139 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8140 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8141 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8147 #ifdef LOAD_EXTEND_OP
8148 /* In many, if not most, RISC machines, reading a byte from memory
8149 zeros the rest of the register. Noticing that fact saves a lot
8150 of extra zero-extends. */
8151 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8152 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8157 case UNEQ
: case LTGT
:
8158 case GT
: case GTU
: case UNGT
:
8159 case LT
: case LTU
: case UNLT
:
8160 case GE
: case GEU
: case UNGE
:
8161 case LE
: case LEU
: case UNLE
:
8162 case UNORDERED
: case ORDERED
:
8164 /* If this produces an integer result, we know which bits are set.
8165 Code here used to clear bits outside the mode of X, but that is
8168 if (GET_MODE_CLASS (mode
) == MODE_INT
8169 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8170 nonzero
= STORE_FLAG_VALUE
;
8175 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8176 and num_sign_bit_copies. */
8177 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8178 == GET_MODE_BITSIZE (GET_MODE (x
)))
8182 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8183 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8188 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8189 and num_sign_bit_copies. */
8190 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8191 == GET_MODE_BITSIZE (GET_MODE (x
)))
8197 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8201 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8202 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8203 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8207 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8208 Otherwise, show all the bits in the outer mode but not the inner
8210 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8211 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8213 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8215 & (((HOST_WIDE_INT
) 1
8216 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8217 inner_nz
|= (GET_MODE_MASK (mode
)
8218 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8221 nonzero
&= inner_nz
;
8225 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8226 & nonzero_bits (XEXP (x
, 1), mode
));
8230 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8231 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8232 | nonzero_bits (XEXP (x
, 1), mode
));
8235 case PLUS
: case MINUS
:
8237 case DIV
: case UDIV
:
8238 case MOD
: case UMOD
:
8239 /* We can apply the rules of arithmetic to compute the number of
8240 high- and low-order zero bits of these operations. We start by
8241 computing the width (position of the highest-order non-zero bit)
8242 and the number of low-order zero bits for each value. */
8244 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8245 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8246 int width0
= floor_log2 (nz0
) + 1;
8247 int width1
= floor_log2 (nz1
) + 1;
8248 int low0
= floor_log2 (nz0
& -nz0
);
8249 int low1
= floor_log2 (nz1
& -nz1
);
8250 HOST_WIDE_INT op0_maybe_minusp
8251 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8252 HOST_WIDE_INT op1_maybe_minusp
8253 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8254 unsigned int result_width
= mode_width
;
8262 && (XEXP (x
, 0) == stack_pointer_rtx
8263 || XEXP (x
, 0) == frame_pointer_rtx
)
8264 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8266 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8268 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8269 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8270 width0
= floor_log2 (nz0
) + 1;
8271 width1
= floor_log2 (nz1
) + 1;
8272 low0
= floor_log2 (nz0
& -nz0
);
8273 low1
= floor_log2 (nz1
& -nz1
);
8276 result_width
= MAX (width0
, width1
) + 1;
8277 result_low
= MIN (low0
, low1
);
8280 result_low
= MIN (low0
, low1
);
8283 result_width
= width0
+ width1
;
8284 result_low
= low0
+ low1
;
8287 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8288 result_width
= width0
;
8291 result_width
= width0
;
8294 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8295 result_width
= MIN (width0
, width1
);
8296 result_low
= MIN (low0
, low1
);
8299 result_width
= MIN (width0
, width1
);
8300 result_low
= MIN (low0
, low1
);
8306 if (result_width
< mode_width
)
8307 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8310 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8312 #ifdef POINTERS_EXTEND_UNSIGNED
8313 /* If pointers extend unsigned and this is an addition or subtraction
8314 to a pointer in Pmode, all the bits above ptr_mode are known to be
8316 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8317 && (code
== PLUS
|| code
== MINUS
)
8318 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8319 nonzero
&= GET_MODE_MASK (ptr_mode
);
8325 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8326 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8327 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8331 /* If this is a SUBREG formed for a promoted variable that has
8332 been zero-extended, we know that at least the high-order bits
8333 are zero, though others might be too. */
8335 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8336 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8337 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8339 /* If the inner mode is a single word for both the host and target
8340 machines, we can compute this from which bits of the inner
8341 object might be nonzero. */
8342 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8343 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8344 <= HOST_BITS_PER_WIDE_INT
))
8346 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8348 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8349 /* If this is a typical RISC machine, we only have to worry
8350 about the way loads are extended. */
8351 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8353 & (((unsigned HOST_WIDE_INT
) 1
8354 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8356 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8359 /* On many CISC machines, accessing an object in a wider mode
8360 causes the high-order bits to become undefined. So they are
8361 not known to be zero. */
8362 if (GET_MODE_SIZE (GET_MODE (x
))
8363 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8364 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8365 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8374 /* The nonzero bits are in two classes: any bits within MODE
8375 that aren't in GET_MODE (x) are always significant. The rest of the
8376 nonzero bits are those that are significant in the operand of
8377 the shift when shifted the appropriate number of bits. This
8378 shows that high-order bits are cleared by the right shift and
8379 low-order bits by left shifts. */
8380 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8381 && INTVAL (XEXP (x
, 1)) >= 0
8382 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8384 enum machine_mode inner_mode
= GET_MODE (x
);
8385 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8386 int count
= INTVAL (XEXP (x
, 1));
8387 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8388 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8389 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8390 unsigned HOST_WIDE_INT outer
= 0;
8392 if (mode_width
> width
)
8393 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8395 if (code
== LSHIFTRT
)
8397 else if (code
== ASHIFTRT
)
8401 /* If the sign bit may have been nonzero before the shift, we
8402 need to mark all the places it could have been copied to
8403 by the shift as possibly nonzero. */
8404 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8405 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8407 else if (code
== ASHIFT
)
8410 inner
= ((inner
<< (count
% width
)
8411 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8413 nonzero
&= (outer
| inner
);
8418 /* This is at most the number of bits in the mode. */
8419 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8423 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8424 | nonzero_bits (XEXP (x
, 2), mode
));
8434 /* See the macro definition above. */
8435 #undef num_sign_bit_copies
8437 /* Return the number of bits at the high-order end of X that are known to
8438 be equal to the sign bit. X will be used in mode MODE; if MODE is
8439 VOIDmode, X will be used in its own mode. The returned value will always
8440 be between 1 and the number of bits in MODE. */
8443 num_sign_bit_copies (x
, mode
)
8445 enum machine_mode mode
;
8447 enum rtx_code code
= GET_CODE (x
);
8448 unsigned int bitwidth
;
8449 int num0
, num1
, result
;
8450 unsigned HOST_WIDE_INT nonzero
;
8453 /* If we weren't given a mode, use the mode of X. If the mode is still
8454 VOIDmode, we don't know anything. Likewise if one of the modes is
8457 if (mode
== VOIDmode
)
8458 mode
= GET_MODE (x
);
8460 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8463 bitwidth
= GET_MODE_BITSIZE (mode
);
8465 /* For a smaller object, just ignore the high bits. */
8466 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8468 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8470 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8473 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8475 #ifndef WORD_REGISTER_OPERATIONS
8476 /* If this machine does not do all register operations on the entire
8477 register and MODE is wider than the mode of X, we can say nothing
8478 at all about the high-order bits. */
8481 /* Likewise on machines that do, if the mode of the object is smaller
8482 than a word and loads of that size don't sign extend, we can say
8483 nothing about the high order bits. */
8484 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8485 #ifdef LOAD_EXTEND_OP
8486 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8497 #ifdef POINTERS_EXTEND_UNSIGNED
8498 /* If pointers extend signed and this is a pointer in Pmode, say that
8499 all the bits above ptr_mode are known to be sign bit copies. */
8500 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8502 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8505 if (reg_last_set_value
[REGNO (x
)] != 0
8506 && reg_last_set_mode
[REGNO (x
)] == mode
8507 && (reg_last_set_label
[REGNO (x
)] == label_tick
8508 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8509 && REG_N_SETS (REGNO (x
)) == 1
8510 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8512 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8513 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8515 tem
= get_last_value (x
);
8517 return num_sign_bit_copies (tem
, mode
);
8519 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8520 return reg_sign_bit_copies
[REGNO (x
)];
8524 #ifdef LOAD_EXTEND_OP
8525 /* Some RISC machines sign-extend all loads of smaller than a word. */
8526 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8527 return MAX (1, ((int) bitwidth
8528 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8533 /* If the constant is negative, take its 1's complement and remask.
8534 Then see how many zero bits we have. */
8535 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8536 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8537 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8538 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8540 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8543 /* If this is a SUBREG for a promoted object that is sign-extended
8544 and we are looking at it in a wider mode, we know that at least the
8545 high-order bits are known to be sign bit copies. */
8547 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8549 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8550 return MAX ((int) bitwidth
8551 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8555 /* For a smaller object, just ignore the high bits. */
8556 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8558 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8559 return MAX (1, (num0
8560 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8564 #ifdef WORD_REGISTER_OPERATIONS
8565 #ifdef LOAD_EXTEND_OP
8566 /* For paradoxical SUBREGs on machines where all register operations
8567 affect the entire register, just look inside. Note that we are
8568 passing MODE to the recursive call, so the number of sign bit copies
8569 will remain relative to that mode, not the inner mode. */
8571 /* This works only if loads sign extend. Otherwise, if we get a
8572 reload for the inner part, it may be loaded from the stack, and
8573 then we lose all sign bit copies that existed before the store
8576 if ((GET_MODE_SIZE (GET_MODE (x
))
8577 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8578 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8579 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8585 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8586 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8590 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8591 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8594 /* For a smaller object, just ignore the high bits. */
8595 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8596 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8600 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8602 case ROTATE
: case ROTATERT
:
8603 /* If we are rotating left by a number of bits less than the number
8604 of sign bit copies, we can just subtract that amount from the
8606 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8607 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8609 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8610 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8611 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8616 /* In general, this subtracts one sign bit copy. But if the value
8617 is known to be positive, the number of sign bit copies is the
8618 same as that of the input. Finally, if the input has just one bit
8619 that might be nonzero, all the bits are copies of the sign bit. */
8620 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8621 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8622 return num0
> 1 ? num0
- 1 : 1;
8624 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8629 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8634 case IOR
: case AND
: case XOR
:
8635 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8636 /* Logical operations will preserve the number of sign-bit copies.
8637 MIN and MAX operations always return one of the operands. */
8638 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8639 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8640 return MIN (num0
, num1
);
8642 case PLUS
: case MINUS
:
8643 /* For addition and subtraction, we can have a 1-bit carry. However,
8644 if we are subtracting 1 from a positive number, there will not
8645 be such a carry. Furthermore, if the positive number is known to
8646 be 0 or 1, we know the result is either -1 or 0. */
8648 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8649 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8651 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8652 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8653 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8654 : bitwidth
- floor_log2 (nonzero
) - 1);
8657 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8658 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8659 result
= MAX (1, MIN (num0
, num1
) - 1);
8661 #ifdef POINTERS_EXTEND_UNSIGNED
8662 /* If pointers extend signed and this is an addition or subtraction
8663 to a pointer in Pmode, all the bits above ptr_mode are known to be
8665 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8666 && (code
== PLUS
|| code
== MINUS
)
8667 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8668 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8669 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8675 /* The number of bits of the product is the sum of the number of
8676 bits of both terms. However, unless one of the terms if known
8677 to be positive, we must allow for an additional bit since negating
8678 a negative number can remove one sign bit copy. */
8680 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8681 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8683 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8685 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8686 || (((nonzero_bits (XEXP (x
, 0), mode
)
8687 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8688 && ((nonzero_bits (XEXP (x
, 1), mode
)
8689 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8692 return MAX (1, result
);
8695 /* The result must be <= the first operand. If the first operand
8696 has the high bit set, we know nothing about the number of sign
8698 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8700 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8701 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8704 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8707 /* The result must be <= the scond operand. */
8708 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8711 /* Similar to unsigned division, except that we have to worry about
8712 the case where the divisor is negative, in which case we have
8714 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8716 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8717 || (nonzero_bits (XEXP (x
, 1), mode
)
8718 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8724 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8726 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8727 || (nonzero_bits (XEXP (x
, 1), mode
)
8728 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8734 /* Shifts by a constant add to the number of bits equal to the
8736 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8737 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8738 && INTVAL (XEXP (x
, 1)) > 0)
8739 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8744 /* Left shifts destroy copies. */
8745 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8746 || INTVAL (XEXP (x
, 1)) < 0
8747 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8750 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8751 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8754 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8755 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8756 return MIN (num0
, num1
);
8758 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8759 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8760 case GEU
: case GTU
: case LEU
: case LTU
:
8761 case UNORDERED
: case ORDERED
:
8762 /* If the constant is negative, take its 1's complement and remask.
8763 Then see how many zero bits we have. */
8764 nonzero
= STORE_FLAG_VALUE
;
8765 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8766 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8767 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8769 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8776 /* If we haven't been able to figure it out by one of the above rules,
8777 see if some of the high-order bits are known to be zero. If so,
8778 count those bits and return one less than that amount. If we can't
8779 safely compute the mask for this mode, always return BITWIDTH. */
8781 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8784 nonzero
= nonzero_bits (x
, mode
);
8785 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8786 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8789 /* Return the number of "extended" bits there are in X, when interpreted
8790 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8791 unsigned quantities, this is the number of high-order zero bits.
8792 For signed quantities, this is the number of copies of the sign bit
8793 minus 1. In both case, this function returns the number of "spare"
8794 bits. For example, if two quantities for which this function returns
8795 at least 1 are added, the addition is known not to overflow.
8797 This function will always return 0 unless called during combine, which
8798 implies that it must be called from a define_split. */
8801 extended_count (x
, mode
, unsignedp
)
8803 enum machine_mode mode
;
8806 if (nonzero_sign_valid
== 0)
8810 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8811 ? (GET_MODE_BITSIZE (mode
) - 1
8812 - floor_log2 (nonzero_bits (x
, mode
)))
8814 : num_sign_bit_copies (x
, mode
) - 1);
8817 /* This function is called from `simplify_shift_const' to merge two
8818 outer operations. Specifically, we have already found that we need
8819 to perform operation *POP0 with constant *PCONST0 at the outermost
8820 position. We would now like to also perform OP1 with constant CONST1
8821 (with *POP0 being done last).
8823 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8824 the resulting operation. *PCOMP_P is set to 1 if we would need to
8825 complement the innermost operand, otherwise it is unchanged.
8827 MODE is the mode in which the operation will be done. No bits outside
8828 the width of this mode matter. It is assumed that the width of this mode
8829 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8831 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8832 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8833 result is simply *PCONST0.
8835 If the resulting operation cannot be expressed as one operation, we
8836 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8839 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8840 enum rtx_code
*pop0
;
8841 HOST_WIDE_INT
*pconst0
;
8843 HOST_WIDE_INT const1
;
8844 enum machine_mode mode
;
8847 enum rtx_code op0
= *pop0
;
8848 HOST_WIDE_INT const0
= *pconst0
;
8850 const0
&= GET_MODE_MASK (mode
);
8851 const1
&= GET_MODE_MASK (mode
);
8853 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8857 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8860 if (op1
== NIL
|| op0
== SET
)
8863 else if (op0
== NIL
)
8864 op0
= op1
, const0
= const1
;
8866 else if (op0
== op1
)
8890 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8891 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8894 /* If the two constants aren't the same, we can't do anything. The
8895 remaining six cases can all be done. */
8896 else if (const0
!= const1
)
8904 /* (a & b) | b == b */
8906 else /* op1 == XOR */
8907 /* (a ^ b) | b == a | b */
8913 /* (a & b) ^ b == (~a) & b */
8914 op0
= AND
, *pcomp_p
= 1;
8915 else /* op1 == IOR */
8916 /* (a | b) ^ b == a & ~b */
8917 op0
= AND
, *pconst0
= ~const0
;
8922 /* (a | b) & b == b */
8924 else /* op1 == XOR */
8925 /* (a ^ b) & b) == (~a) & b */
8932 /* Check for NO-OP cases. */
8933 const0
&= GET_MODE_MASK (mode
);
8935 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8937 else if (const0
== 0 && op0
== AND
)
8939 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8943 /* ??? Slightly redundant with the above mask, but not entirely.
8944 Moving this above means we'd have to sign-extend the mode mask
8945 for the final test. */
8946 const0
= trunc_int_for_mode (const0
, mode
);
8954 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8955 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8956 that we started with.
8958 The shift is normally computed in the widest mode we find in VAROP, as
8959 long as it isn't a different number of words than RESULT_MODE. Exceptions
8960 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8963 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8966 enum machine_mode result_mode
;
8970 enum rtx_code orig_code
= code
;
8971 int orig_count
= input_count
;
8974 enum machine_mode mode
= result_mode
;
8975 enum machine_mode shift_mode
, tmode
;
8976 unsigned int mode_words
8977 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8978 /* We form (outer_op (code varop count) (outer_const)). */
8979 enum rtx_code outer_op
= NIL
;
8980 HOST_WIDE_INT outer_const
= 0;
8982 int complement_p
= 0;
8985 /* If we were given an invalid count, don't do anything except exactly
8986 what was requested. */
8988 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8993 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8996 count
= input_count
;
8998 /* Make sure and truncate the "natural" shift on the way in. We don't
8999 want to do this inside the loop as it makes it more difficult to
9001 #ifdef SHIFT_COUNT_TRUNCATED
9002 if (SHIFT_COUNT_TRUNCATED
)
9003 count
%= GET_MODE_BITSIZE (mode
);
9006 /* Unless one of the branches of the `if' in this loop does a `continue',
9007 we will `break' the loop after the `if'. */
9011 /* If we have an operand of (clobber (const_int 0)), just return that
9013 if (GET_CODE (varop
) == CLOBBER
)
9016 /* If we discovered we had to complement VAROP, leave. Making a NOT
9017 here would cause an infinite loop. */
9021 /* Convert ROTATERT to ROTATE. */
9022 if (code
== ROTATERT
)
9023 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
9025 /* We need to determine what mode we will do the shift in. If the
9026 shift is a right shift or a ROTATE, we must always do it in the mode
9027 it was originally done in. Otherwise, we can do it in MODE, the
9028 widest mode encountered. */
9030 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9031 ? result_mode
: mode
);
9033 /* Handle cases where the count is greater than the size of the mode
9034 minus 1. For ASHIFT, use the size minus one as the count (this can
9035 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9036 take the count modulo the size. For other shifts, the result is
9039 Since these shifts are being produced by the compiler by combining
9040 multiple operations, each of which are defined, we know what the
9041 result is supposed to be. */
9043 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
9045 if (code
== ASHIFTRT
)
9046 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9047 else if (code
== ROTATE
|| code
== ROTATERT
)
9048 count
%= GET_MODE_BITSIZE (shift_mode
);
9051 /* We can't simply return zero because there may be an
9059 /* An arithmetic right shift of a quantity known to be -1 or 0
9061 if (code
== ASHIFTRT
9062 && (num_sign_bit_copies (varop
, shift_mode
)
9063 == GET_MODE_BITSIZE (shift_mode
)))
9069 /* If we are doing an arithmetic right shift and discarding all but
9070 the sign bit copies, this is equivalent to doing a shift by the
9071 bitsize minus one. Convert it into that shift because it will often
9072 allow other simplifications. */
9074 if (code
== ASHIFTRT
9075 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9076 >= GET_MODE_BITSIZE (shift_mode
)))
9077 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9079 /* We simplify the tests below and elsewhere by converting
9080 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9081 `make_compound_operation' will convert it to a ASHIFTRT for
9082 those machines (such as Vax) that don't have a LSHIFTRT. */
9083 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9085 && ((nonzero_bits (varop
, shift_mode
)
9086 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9090 switch (GET_CODE (varop
))
9096 new = expand_compound_operation (varop
);
9105 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9106 minus the width of a smaller mode, we can do this with a
9107 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9108 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9109 && ! mode_dependent_address_p (XEXP (varop
, 0))
9110 && ! MEM_VOLATILE_P (varop
)
9111 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9112 MODE_INT
, 1)) != BLKmode
)
9114 if (BYTES_BIG_ENDIAN
)
9115 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
9117 new = gen_rtx_MEM (tmode
,
9118 plus_constant (XEXP (varop
, 0),
9119 count
/ BITS_PER_UNIT
));
9121 MEM_COPY_ATTRIBUTES (new, varop
);
9122 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9123 : ZERO_EXTEND
, mode
, new);
9130 /* Similar to the case above, except that we can only do this if
9131 the resulting mode is the same as that of the underlying
9132 MEM and adjust the address depending on the *bits* endianness
9133 because of the way that bit-field extract insns are defined. */
9134 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9135 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9136 MODE_INT
, 1)) != BLKmode
9137 && tmode
== GET_MODE (XEXP (varop
, 0)))
9139 if (BITS_BIG_ENDIAN
)
9140 new = XEXP (varop
, 0);
9143 new = copy_rtx (XEXP (varop
, 0));
9144 SUBST (XEXP (new, 0),
9145 plus_constant (XEXP (new, 0),
9146 count
/ BITS_PER_UNIT
));
9149 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9150 : ZERO_EXTEND
, mode
, new);
9157 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9158 the same number of words as what we've seen so far. Then store
9159 the widest mode in MODE. */
9160 if (subreg_lowpart_p (varop
)
9161 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9162 > GET_MODE_SIZE (GET_MODE (varop
)))
9163 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9164 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9167 varop
= SUBREG_REG (varop
);
9168 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9169 mode
= GET_MODE (varop
);
9175 /* Some machines use MULT instead of ASHIFT because MULT
9176 is cheaper. But it is still better on those machines to
9177 merge two shifts into one. */
9178 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9179 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9182 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9183 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9189 /* Similar, for when divides are cheaper. */
9190 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9191 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9194 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9195 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9201 /* If we are extracting just the sign bit of an arithmetic
9202 right shift, that shift is not needed. However, the sign
9203 bit of a wider mode may be different from what would be
9204 interpreted as the sign bit in a narrower mode, so, if
9205 the result is narrower, don't discard the shift. */
9206 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9207 && (GET_MODE_BITSIZE (result_mode
)
9208 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9210 varop
= XEXP (varop
, 0);
9214 /* ... fall through ... */
9219 /* Here we have two nested shifts. The result is usually the
9220 AND of a new shift with a mask. We compute the result below. */
9221 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9222 && INTVAL (XEXP (varop
, 1)) >= 0
9223 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9224 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9225 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9227 enum rtx_code first_code
= GET_CODE (varop
);
9228 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9229 unsigned HOST_WIDE_INT mask
;
9232 /* We have one common special case. We can't do any merging if
9233 the inner code is an ASHIFTRT of a smaller mode. However, if
9234 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9235 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9236 we can convert it to
9237 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9238 This simplifies certain SIGN_EXTEND operations. */
9239 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9240 && (GET_MODE_BITSIZE (result_mode
)
9241 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9243 /* C3 has the low-order C1 bits zero. */
9245 mask
= (GET_MODE_MASK (mode
)
9246 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9248 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9249 XEXP (varop
, 0), mask
);
9250 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9252 count
= first_count
;
9257 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9258 than C1 high-order bits equal to the sign bit, we can convert
9259 this to either an ASHIFT or a ASHIFTRT depending on the
9262 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9264 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9265 && GET_MODE (varop
) == shift_mode
9266 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9269 varop
= XEXP (varop
, 0);
9271 signed_count
= count
- first_count
;
9272 if (signed_count
< 0)
9273 count
= -signed_count
, code
= ASHIFT
;
9275 count
= signed_count
;
9280 /* There are some cases we can't do. If CODE is ASHIFTRT,
9281 we can only do this if FIRST_CODE is also ASHIFTRT.
9283 We can't do the case when CODE is ROTATE and FIRST_CODE is
9286 If the mode of this shift is not the mode of the outer shift,
9287 we can't do this if either shift is a right shift or ROTATE.
9289 Finally, we can't do any of these if the mode is too wide
9290 unless the codes are the same.
9292 Handle the case where the shift codes are the same
9295 if (code
== first_code
)
9297 if (GET_MODE (varop
) != result_mode
9298 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9302 count
+= first_count
;
9303 varop
= XEXP (varop
, 0);
9307 if (code
== ASHIFTRT
9308 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9309 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9310 || (GET_MODE (varop
) != result_mode
9311 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9312 || first_code
== ROTATE
9313 || code
== ROTATE
)))
9316 /* To compute the mask to apply after the shift, shift the
9317 nonzero bits of the inner shift the same way the
9318 outer shift will. */
9320 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9323 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9326 /* Give up if we can't compute an outer operation to use. */
9328 || GET_CODE (mask_rtx
) != CONST_INT
9329 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9331 result_mode
, &complement_p
))
9334 /* If the shifts are in the same direction, we add the
9335 counts. Otherwise, we subtract them. */
9336 signed_count
= count
;
9337 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9338 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9339 signed_count
+= first_count
;
9341 signed_count
-= first_count
;
9343 /* If COUNT is positive, the new shift is usually CODE,
9344 except for the two exceptions below, in which case it is
9345 FIRST_CODE. If the count is negative, FIRST_CODE should
9347 if (signed_count
> 0
9348 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9349 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9350 code
= first_code
, count
= signed_count
;
9351 else if (signed_count
< 0)
9352 code
= first_code
, count
= -signed_count
;
9354 count
= signed_count
;
9356 varop
= XEXP (varop
, 0);
9360 /* If we have (A << B << C) for any shift, we can convert this to
9361 (A << C << B). This wins if A is a constant. Only try this if
9362 B is not a constant. */
9364 else if (GET_CODE (varop
) == code
9365 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9367 = simplify_binary_operation (code
, mode
,
9371 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9378 /* Make this fit the case below. */
9379 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9380 GEN_INT (GET_MODE_MASK (mode
)));
9386 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9387 with C the size of VAROP - 1 and the shift is logical if
9388 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9389 we have an (le X 0) operation. If we have an arithmetic shift
9390 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9391 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9393 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9394 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9395 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9396 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9397 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9398 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9401 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9404 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9405 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9410 /* If we have (shift (logical)), move the logical to the outside
9411 to allow it to possibly combine with another logical and the
9412 shift to combine with another shift. This also canonicalizes to
9413 what a ZERO_EXTRACT looks like. Also, some machines have
9414 (and (shift)) insns. */
9416 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9417 && (new = simplify_binary_operation (code
, result_mode
,
9419 GEN_INT (count
))) != 0
9420 && GET_CODE (new) == CONST_INT
9421 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9422 INTVAL (new), result_mode
, &complement_p
))
9424 varop
= XEXP (varop
, 0);
9428 /* If we can't do that, try to simplify the shift in each arm of the
9429 logical expression, make a new logical expression, and apply
9430 the inverse distributive law. */
9432 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9433 XEXP (varop
, 0), count
);
9434 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9435 XEXP (varop
, 1), count
);
9437 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9438 varop
= apply_distributive_law (varop
);
9445 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9446 says that the sign bit can be tested, FOO has mode MODE, C is
9447 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9448 that may be nonzero. */
9449 if (code
== LSHIFTRT
9450 && XEXP (varop
, 1) == const0_rtx
9451 && GET_MODE (XEXP (varop
, 0)) == result_mode
9452 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9453 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9454 && ((STORE_FLAG_VALUE
9455 & ((HOST_WIDE_INT
) 1
9456 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9457 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9458 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9459 (HOST_WIDE_INT
) 1, result_mode
,
9462 varop
= XEXP (varop
, 0);
9469 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9470 than the number of bits in the mode is equivalent to A. */
9471 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9472 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9474 varop
= XEXP (varop
, 0);
9479 /* NEG commutes with ASHIFT since it is multiplication. Move the
9480 NEG outside to allow shifts to combine. */
9482 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9483 (HOST_WIDE_INT
) 0, result_mode
,
9486 varop
= XEXP (varop
, 0);
9492 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9493 is one less than the number of bits in the mode is
9494 equivalent to (xor A 1). */
9495 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9496 && XEXP (varop
, 1) == constm1_rtx
9497 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9498 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9499 (HOST_WIDE_INT
) 1, result_mode
,
9503 varop
= XEXP (varop
, 0);
9507 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9508 that might be nonzero in BAR are those being shifted out and those
9509 bits are known zero in FOO, we can replace the PLUS with FOO.
9510 Similarly in the other operand order. This code occurs when
9511 we are computing the size of a variable-size array. */
9513 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9514 && count
< HOST_BITS_PER_WIDE_INT
9515 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9516 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9517 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9519 varop
= XEXP (varop
, 0);
9522 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9523 && count
< HOST_BITS_PER_WIDE_INT
9524 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9525 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9527 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9528 & nonzero_bits (XEXP (varop
, 1),
9531 varop
= XEXP (varop
, 1);
9535 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9537 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9538 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9540 GEN_INT (count
))) != 0
9541 && GET_CODE (new) == CONST_INT
9542 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9543 INTVAL (new), result_mode
, &complement_p
))
9545 varop
= XEXP (varop
, 0);
9551 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9552 with C the size of VAROP - 1 and the shift is logical if
9553 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9554 we have a (gt X 0) operation. If the shift is arithmetic with
9555 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9556 we have a (neg (gt X 0)) operation. */
9558 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9559 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9560 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9561 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9562 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9563 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9564 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9567 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9570 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9571 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9578 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9579 if the truncate does not affect the value. */
9580 if (code
== LSHIFTRT
9581 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9582 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9583 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9584 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9585 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9587 rtx varop_inner
= XEXP (varop
, 0);
9590 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9591 XEXP (varop_inner
, 0),
9593 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9594 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9607 /* We need to determine what mode to do the shift in. If the shift is
9608 a right shift or ROTATE, we must always do it in the mode it was
9609 originally done in. Otherwise, we can do it in MODE, the widest mode
9610 encountered. The code we care about is that of the shift that will
9611 actually be done, not the shift that was originally requested. */
9613 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9614 ? result_mode
: mode
);
9616 /* We have now finished analyzing the shift. The result should be
9617 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9618 OUTER_OP is non-NIL, it is an operation that needs to be applied
9619 to the result of the shift. OUTER_CONST is the relevant constant,
9620 but we must turn off all bits turned off in the shift.
9622 If we were passed a value for X, see if we can use any pieces of
9623 it. If not, make new rtx. */
9625 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9626 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9627 && INTVAL (XEXP (x
, 1)) == count
)
9628 const_rtx
= XEXP (x
, 1);
9630 const_rtx
= GEN_INT (count
);
9632 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9633 && GET_MODE (XEXP (x
, 0)) == shift_mode
9634 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9635 varop
= XEXP (x
, 0);
9636 else if (GET_MODE (varop
) != shift_mode
)
9637 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9639 /* If we can't make the SUBREG, try to return what we were given. */
9640 if (GET_CODE (varop
) == CLOBBER
)
9641 return x
? x
: varop
;
9643 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9648 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9649 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9651 SUBST (XEXP (x
, 0), varop
);
9652 SUBST (XEXP (x
, 1), const_rtx
);
9655 /* If we have an outer operation and we just made a shift, it is
9656 possible that we could have simplified the shift were it not
9657 for the outer operation. So try to do the simplification
9660 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9661 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9662 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9663 INTVAL (XEXP (x
, 1)));
9665 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9666 turn off all the bits that the shift would have turned off. */
9667 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9668 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9669 GET_MODE_MASK (result_mode
) >> orig_count
);
9671 /* Do the remainder of the processing in RESULT_MODE. */
9672 x
= gen_lowpart_for_combine (result_mode
, x
);
9674 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9677 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9679 if (outer_op
!= NIL
)
9681 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9682 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9684 if (outer_op
== AND
)
9685 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9686 else if (outer_op
== SET
)
9687 /* This means that we have determined that the result is
9688 equivalent to a constant. This should be rare. */
9689 x
= GEN_INT (outer_const
);
9690 else if (GET_RTX_CLASS (outer_op
) == '1')
9691 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9693 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9699 /* Like recog, but we receive the address of a pointer to a new pattern.
9700 We try to match the rtx that the pointer points to.
9701 If that fails, we may try to modify or replace the pattern,
9702 storing the replacement into the same pointer object.
9704 Modifications include deletion or addition of CLOBBERs.
9706 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9707 the CLOBBERs are placed.
9709 The value is the final insn code from the pattern ultimately matched,
9713 recog_for_combine (pnewpat
, insn
, pnotes
)
9718 register rtx pat
= *pnewpat
;
9719 int insn_code_number
;
9720 int num_clobbers_to_add
= 0;
9725 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9726 we use to indicate that something didn't match. If we find such a
9727 thing, force rejection. */
9728 if (GET_CODE (pat
) == PARALLEL
)
9729 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9730 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9731 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9734 /* Remove the old notes prior to trying to recognize the new pattern. */
9735 old_notes
= REG_NOTES (insn
);
9736 REG_NOTES (insn
) = 0;
9738 /* Is the result of combination a valid instruction? */
9739 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9741 /* If it isn't, there is the possibility that we previously had an insn
9742 that clobbered some register as a side effect, but the combined
9743 insn doesn't need to do that. So try once more without the clobbers
9744 unless this represents an ASM insn. */
9746 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9747 && GET_CODE (pat
) == PARALLEL
)
9751 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9752 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9755 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9759 SUBST_INT (XVECLEN (pat
, 0), pos
);
9762 pat
= XVECEXP (pat
, 0, 0);
9764 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9767 REG_NOTES (insn
) = old_notes
;
9769 /* If we had any clobbers to add, make a new pattern than contains
9770 them. Then check to make sure that all of them are dead. */
9771 if (num_clobbers_to_add
)
9773 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9774 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9776 + num_clobbers_to_add
)
9777 : num_clobbers_to_add
+ 1));
9779 if (GET_CODE (pat
) == PARALLEL
)
9780 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9781 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9783 XVECEXP (newpat
, 0, 0) = pat
;
9785 add_clobbers (newpat
, insn_code_number
);
9787 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9788 i
< XVECLEN (newpat
, 0); i
++)
9790 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9791 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9793 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9794 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9802 return insn_code_number
;
9805 /* Like gen_lowpart but for use by combine. In combine it is not possible
9806 to create any new pseudoregs. However, it is safe to create
9807 invalid memory addresses, because combine will try to recognize
9808 them and all they will do is make the combine attempt fail.
9810 If for some reason this cannot do its job, an rtx
9811 (clobber (const_int 0)) is returned.
9812 An insn containing that will not be recognized. */
9817 gen_lowpart_for_combine (mode
, x
)
9818 enum machine_mode mode
;
9823 if (GET_MODE (x
) == mode
)
9826 /* We can only support MODE being wider than a word if X is a
9827 constant integer or has a mode the same size. */
9829 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9830 && ! ((GET_MODE (x
) == VOIDmode
9831 && (GET_CODE (x
) == CONST_INT
9832 || GET_CODE (x
) == CONST_DOUBLE
))
9833 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9834 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9836 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9837 won't know what to do. So we will strip off the SUBREG here and
9838 process normally. */
9839 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9842 if (GET_MODE (x
) == mode
)
9846 result
= gen_lowpart_common (mode
, x
);
9847 #ifdef CLASS_CANNOT_CHANGE_MODE
9849 && GET_CODE (result
) == SUBREG
9850 && GET_CODE (SUBREG_REG (result
)) == REG
9851 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9852 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9853 GET_MODE (SUBREG_REG (result
))))
9854 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9860 if (GET_CODE (x
) == MEM
)
9862 register int offset
= 0;
9865 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9867 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9868 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9870 /* If we want to refer to something bigger than the original memref,
9871 generate a perverse subreg instead. That will force a reload
9872 of the original memref X. */
9873 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9874 return gen_rtx_SUBREG (mode
, x
, 0);
9876 if (WORDS_BIG_ENDIAN
)
9877 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9878 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9880 if (BYTES_BIG_ENDIAN
)
9882 /* Adjust the address so that the address-after-the-data is
9884 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9885 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9887 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9888 MEM_COPY_ATTRIBUTES (new, x
);
9892 /* If X is a comparison operator, rewrite it in a new mode. This
9893 probably won't match, but may allow further simplifications. */
9894 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9895 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9897 /* If we couldn't simplify X any other way, just enclose it in a
9898 SUBREG. Normally, this SUBREG won't match, but some patterns may
9899 include an explicit SUBREG or we may simplify it further in combine. */
9904 if ((WORDS_BIG_ENDIAN
|| BYTES_BIG_ENDIAN
)
9905 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
9907 int difference
= (GET_MODE_SIZE (GET_MODE (x
))
9908 - GET_MODE_SIZE (mode
));
9909 if (WORDS_BIG_ENDIAN
)
9910 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
9911 if (BYTES_BIG_ENDIAN
)
9912 offset
+= difference
% UNITS_PER_WORD
;
9914 return gen_rtx_SUBREG (mode
, x
, offset
);
9918 /* These routines make binary and unary operations by first seeing if they
9919 fold; if not, a new expression is allocated. */
9922 gen_binary (code
, mode
, op0
, op1
)
9924 enum machine_mode mode
;
9930 if (GET_RTX_CLASS (code
) == 'c'
9931 && (GET_CODE (op0
) == CONST_INT
9932 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9933 tem
= op0
, op0
= op1
, op1
= tem
;
9935 if (GET_RTX_CLASS (code
) == '<')
9937 enum machine_mode op_mode
= GET_MODE (op0
);
9939 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9940 just (REL_OP X Y). */
9941 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9943 op1
= XEXP (op0
, 1);
9944 op0
= XEXP (op0
, 0);
9945 op_mode
= GET_MODE (op0
);
9948 if (op_mode
== VOIDmode
)
9949 op_mode
= GET_MODE (op1
);
9950 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9953 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9958 /* Put complex operands first and constants second. */
9959 if (GET_RTX_CLASS (code
) == 'c'
9960 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9961 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
9962 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
9963 || (GET_CODE (op0
) == SUBREG
9964 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
9965 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
9966 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9968 /* If we are turning off bits already known off in OP0, we need not do
9970 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9971 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9972 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9975 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9978 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9979 comparison code that will be tested.
9981 The result is a possibly different comparison code to use. *POP0 and
9982 *POP1 may be updated.
9984 It is possible that we might detect that a comparison is either always
9985 true or always false. However, we do not perform general constant
9986 folding in combine, so this knowledge isn't useful. Such tautologies
9987 should have been detected earlier. Hence we ignore all such cases. */
9989 static enum rtx_code
9990 simplify_comparison (code
, pop0
, pop1
)
9999 enum machine_mode mode
, tmode
;
10001 /* Try a few ways of applying the same transformation to both operands. */
10004 #ifndef WORD_REGISTER_OPERATIONS
10005 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10006 so check specially. */
10007 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10008 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10009 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10010 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10011 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10012 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10013 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10014 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10015 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10016 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10017 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10018 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10019 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10020 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10021 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10022 && (INTVAL (XEXP (op0
, 1))
10023 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10024 - (GET_MODE_BITSIZE
10025 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10027 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10028 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10032 /* If both operands are the same constant shift, see if we can ignore the
10033 shift. We can if the shift is a rotate or if the bits shifted out of
10034 this shift are known to be zero for both inputs and if the type of
10035 comparison is compatible with the shift. */
10036 if (GET_CODE (op0
) == GET_CODE (op1
)
10037 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10038 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10039 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10040 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10041 || (GET_CODE (op0
) == ASHIFTRT
10042 && (code
!= GTU
&& code
!= LTU
10043 && code
!= GEU
&& code
!= LEU
)))
10044 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10045 && INTVAL (XEXP (op0
, 1)) >= 0
10046 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10047 && XEXP (op0
, 1) == XEXP (op1
, 1))
10049 enum machine_mode mode
= GET_MODE (op0
);
10050 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10051 int shift_count
= INTVAL (XEXP (op0
, 1));
10053 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10054 mask
&= (mask
>> shift_count
) << shift_count
;
10055 else if (GET_CODE (op0
) == ASHIFT
)
10056 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10058 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10059 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10060 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10065 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10066 SUBREGs are of the same mode, and, in both cases, the AND would
10067 be redundant if the comparison was done in the narrower mode,
10068 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10069 and the operand's possibly nonzero bits are 0xffffff01; in that case
10070 if we only care about QImode, we don't need the AND). This case
10071 occurs if the output mode of an scc insn is not SImode and
10072 STORE_FLAG_VALUE == 1 (e.g., the 386).
10074 Similarly, check for a case where the AND's are ZERO_EXTEND
10075 operations from some narrower mode even though a SUBREG is not
10078 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10079 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10080 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10082 rtx inner_op0
= XEXP (op0
, 0);
10083 rtx inner_op1
= XEXP (op1
, 0);
10084 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10085 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10088 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10089 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10090 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10091 && (GET_MODE (SUBREG_REG (inner_op0
))
10092 == GET_MODE (SUBREG_REG (inner_op1
)))
10093 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10094 <= HOST_BITS_PER_WIDE_INT
)
10095 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10096 GET_MODE (SUBREG_REG (inner_op0
)))))
10097 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10098 GET_MODE (SUBREG_REG (inner_op1
))))))
10100 op0
= SUBREG_REG (inner_op0
);
10101 op1
= SUBREG_REG (inner_op1
);
10103 /* The resulting comparison is always unsigned since we masked
10104 off the original sign bit. */
10105 code
= unsigned_condition (code
);
10111 for (tmode
= GET_CLASS_NARROWEST_MODE
10112 (GET_MODE_CLASS (GET_MODE (op0
)));
10113 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10114 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10116 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10117 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10118 code
= unsigned_condition (code
);
10127 /* If both operands are NOT, we can strip off the outer operation
10128 and adjust the comparison code for swapped operands; similarly for
10129 NEG, except that this must be an equality comparison. */
10130 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10131 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10132 && (code
== EQ
|| code
== NE
)))
10133 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10139 /* If the first operand is a constant, swap the operands and adjust the
10140 comparison code appropriately, but don't do this if the second operand
10141 is already a constant integer. */
10142 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
10144 tem
= op0
, op0
= op1
, op1
= tem
;
10145 code
= swap_condition (code
);
10148 /* We now enter a loop during which we will try to simplify the comparison.
10149 For the most part, we only are concerned with comparisons with zero,
10150 but some things may really be comparisons with zero but not start
10151 out looking that way. */
10153 while (GET_CODE (op1
) == CONST_INT
)
10155 enum machine_mode mode
= GET_MODE (op0
);
10156 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10157 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10158 int equality_comparison_p
;
10159 int sign_bit_comparison_p
;
10160 int unsigned_comparison_p
;
10161 HOST_WIDE_INT const_op
;
10163 /* We only want to handle integral modes. This catches VOIDmode,
10164 CCmode, and the floating-point modes. An exception is that we
10165 can handle VOIDmode if OP0 is a COMPARE or a comparison
10168 if (GET_MODE_CLASS (mode
) != MODE_INT
10169 && ! (mode
== VOIDmode
10170 && (GET_CODE (op0
) == COMPARE
10171 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10174 /* Get the constant we are comparing against and turn off all bits
10175 not on in our mode. */
10176 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10178 /* If we are comparing against a constant power of two and the value
10179 being compared can only have that single bit nonzero (e.g., it was
10180 `and'ed with that bit), we can replace this with a comparison
10183 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10184 || code
== LT
|| code
== LTU
)
10185 && mode_width
<= HOST_BITS_PER_WIDE_INT
10186 && exact_log2 (const_op
) >= 0
10187 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10189 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10190 op1
= const0_rtx
, const_op
= 0;
10193 /* Similarly, if we are comparing a value known to be either -1 or
10194 0 with -1, change it to the opposite comparison against zero. */
10197 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10198 || code
== GEU
|| code
== LTU
)
10199 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10201 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10202 op1
= const0_rtx
, const_op
= 0;
10205 /* Do some canonicalizations based on the comparison code. We prefer
10206 comparisons against zero and then prefer equality comparisons.
10207 If we can reduce the size of a constant, we will do that too. */
10212 /* < C is equivalent to <= (C - 1) */
10216 op1
= GEN_INT (const_op
);
10218 /* ... fall through to LE case below. */
10224 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10228 op1
= GEN_INT (const_op
);
10232 /* If we are doing a <= 0 comparison on a value known to have
10233 a zero sign bit, we can replace this with == 0. */
10234 else if (const_op
== 0
10235 && mode_width
<= HOST_BITS_PER_WIDE_INT
10236 && (nonzero_bits (op0
, mode
)
10237 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10242 /* >= C is equivalent to > (C - 1). */
10246 op1
= GEN_INT (const_op
);
10248 /* ... fall through to GT below. */
10254 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10258 op1
= GEN_INT (const_op
);
10262 /* If we are doing a > 0 comparison on a value known to have
10263 a zero sign bit, we can replace this with != 0. */
10264 else if (const_op
== 0
10265 && mode_width
<= HOST_BITS_PER_WIDE_INT
10266 && (nonzero_bits (op0
, mode
)
10267 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10272 /* < C is equivalent to <= (C - 1). */
10276 op1
= GEN_INT (const_op
);
10278 /* ... fall through ... */
10281 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10282 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10283 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10285 const_op
= 0, op1
= const0_rtx
;
10293 /* unsigned <= 0 is equivalent to == 0 */
10297 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10298 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10299 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10301 const_op
= 0, op1
= const0_rtx
;
10307 /* >= C is equivalent to < (C - 1). */
10311 op1
= GEN_INT (const_op
);
10313 /* ... fall through ... */
10316 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10317 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10318 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10320 const_op
= 0, op1
= const0_rtx
;
10328 /* unsigned > 0 is equivalent to != 0 */
10332 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10333 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10334 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10336 const_op
= 0, op1
= const0_rtx
;
10345 /* Compute some predicates to simplify code below. */
10347 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10348 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10349 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10352 /* If this is a sign bit comparison and we can do arithmetic in
10353 MODE, say that we will only be needing the sign bit of OP0. */
10354 if (sign_bit_comparison_p
10355 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10356 op0
= force_to_mode (op0
, mode
,
10358 << (GET_MODE_BITSIZE (mode
) - 1)),
10361 /* Now try cases based on the opcode of OP0. If none of the cases
10362 does a "continue", we exit this loop immediately after the
10365 switch (GET_CODE (op0
))
10368 /* If we are extracting a single bit from a variable position in
10369 a constant that has only a single bit set and are comparing it
10370 with zero, we can convert this into an equality comparison
10371 between the position and the location of the single bit. */
10373 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10374 && XEXP (op0
, 1) == const1_rtx
10375 && equality_comparison_p
&& const_op
== 0
10376 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10378 if (BITS_BIG_ENDIAN
)
10381 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10382 if (mode
== VOIDmode
)
10384 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10386 i
= BITS_PER_WORD
- 1 - i
;
10390 op0
= XEXP (op0
, 2);
10394 /* Result is nonzero iff shift count is equal to I. */
10395 code
= reverse_condition (code
);
10399 /* ... fall through ... */
10402 tem
= expand_compound_operation (op0
);
10411 /* If testing for equality, we can take the NOT of the constant. */
10412 if (equality_comparison_p
10413 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10415 op0
= XEXP (op0
, 0);
10420 /* If just looking at the sign bit, reverse the sense of the
10422 if (sign_bit_comparison_p
)
10424 op0
= XEXP (op0
, 0);
10425 code
= (code
== GE
? LT
: GE
);
10431 /* If testing for equality, we can take the NEG of the constant. */
10432 if (equality_comparison_p
10433 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10435 op0
= XEXP (op0
, 0);
10440 /* The remaining cases only apply to comparisons with zero. */
10444 /* When X is ABS or is known positive,
10445 (neg X) is < 0 if and only if X != 0. */
10447 if (sign_bit_comparison_p
10448 && (GET_CODE (XEXP (op0
, 0)) == ABS
10449 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10450 && (nonzero_bits (XEXP (op0
, 0), mode
)
10451 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10453 op0
= XEXP (op0
, 0);
10454 code
= (code
== LT
? NE
: EQ
);
10458 /* If we have NEG of something whose two high-order bits are the
10459 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10460 if (num_sign_bit_copies (op0
, mode
) >= 2)
10462 op0
= XEXP (op0
, 0);
10463 code
= swap_condition (code
);
10469 /* If we are testing equality and our count is a constant, we
10470 can perform the inverse operation on our RHS. */
10471 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10472 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10473 op1
, XEXP (op0
, 1))) != 0)
10475 op0
= XEXP (op0
, 0);
10480 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10481 a particular bit. Convert it to an AND of a constant of that
10482 bit. This will be converted into a ZERO_EXTRACT. */
10483 if (const_op
== 0 && sign_bit_comparison_p
10484 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10485 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10487 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10490 - INTVAL (XEXP (op0
, 1)))));
10491 code
= (code
== LT
? NE
: EQ
);
10495 /* Fall through. */
10498 /* ABS is ignorable inside an equality comparison with zero. */
10499 if (const_op
== 0 && equality_comparison_p
)
10501 op0
= XEXP (op0
, 0);
10507 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10508 to (compare FOO CONST) if CONST fits in FOO's mode and we
10509 are either testing inequality or have an unsigned comparison
10510 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10511 if (! unsigned_comparison_p
10512 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10513 <= HOST_BITS_PER_WIDE_INT
)
10514 && ((unsigned HOST_WIDE_INT
) const_op
10515 < (((unsigned HOST_WIDE_INT
) 1
10516 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10518 op0
= XEXP (op0
, 0);
10524 /* Check for the case where we are comparing A - C1 with C2,
10525 both constants are smaller than 1/2 the maximum positive
10526 value in MODE, and the comparison is equality or unsigned.
10527 In that case, if A is either zero-extended to MODE or has
10528 sufficient sign bits so that the high-order bit in MODE
10529 is a copy of the sign in the inner mode, we can prove that it is
10530 safe to do the operation in the wider mode. This simplifies
10531 many range checks. */
10533 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10534 && subreg_lowpart_p (op0
)
10535 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10536 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10537 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10538 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10539 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10540 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10541 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10542 GET_MODE (SUBREG_REG (op0
)))
10543 & ~GET_MODE_MASK (mode
))
10544 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10545 GET_MODE (SUBREG_REG (op0
)))
10546 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10547 - GET_MODE_BITSIZE (mode
)))))
10549 op0
= SUBREG_REG (op0
);
10553 /* If the inner mode is narrower and we are extracting the low part,
10554 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10555 if (subreg_lowpart_p (op0
)
10556 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10557 /* Fall through */ ;
10561 /* ... fall through ... */
10564 if ((unsigned_comparison_p
|| equality_comparison_p
)
10565 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10566 <= HOST_BITS_PER_WIDE_INT
)
10567 && ((unsigned HOST_WIDE_INT
) const_op
10568 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10570 op0
= XEXP (op0
, 0);
10576 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10577 this for equality comparisons due to pathological cases involving
10579 if (equality_comparison_p
10580 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10581 op1
, XEXP (op0
, 1))))
10583 op0
= XEXP (op0
, 0);
10588 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10589 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10590 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10592 op0
= XEXP (XEXP (op0
, 0), 0);
10593 code
= (code
== LT
? EQ
: NE
);
10599 /* We used to optimize signed comparisons against zero, but that
10600 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10601 arrive here as equality comparisons, or (GEU, LTU) are
10602 optimized away. No need to special-case them. */
10604 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10605 (eq B (minus A C)), whichever simplifies. We can only do
10606 this for equality comparisons due to pathological cases involving
10608 if (equality_comparison_p
10609 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10610 XEXP (op0
, 1), op1
)))
10612 op0
= XEXP (op0
, 0);
10617 if (equality_comparison_p
10618 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10619 XEXP (op0
, 0), op1
)))
10621 op0
= XEXP (op0
, 1);
10626 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10627 of bits in X minus 1, is one iff X > 0. */
10628 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10629 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10630 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10631 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10633 op0
= XEXP (op0
, 1);
10634 code
= (code
== GE
? LE
: GT
);
10640 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10641 if C is zero or B is a constant. */
10642 if (equality_comparison_p
10643 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10644 XEXP (op0
, 1), op1
)))
10646 op0
= XEXP (op0
, 0);
10653 case UNEQ
: case LTGT
:
10654 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10655 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10656 case UNORDERED
: case ORDERED
:
10657 /* We can't do anything if OP0 is a condition code value, rather
10658 than an actual data value. */
10661 || XEXP (op0
, 0) == cc0_rtx
10663 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10666 /* Get the two operands being compared. */
10667 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10668 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10670 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10672 /* Check for the cases where we simply want the result of the
10673 earlier test or the opposite of that result. */
10674 if (code
== NE
|| code
== EQ
10675 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10676 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10677 && (STORE_FLAG_VALUE
10678 & (((HOST_WIDE_INT
) 1
10679 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10680 && (code
== LT
|| code
== GE
)))
10682 enum rtx_code new_code
;
10683 if (code
== LT
|| code
== NE
)
10684 new_code
= GET_CODE (op0
);
10686 new_code
= combine_reversed_comparison_code (op0
);
10688 if (new_code
!= UNKNOWN
)
10699 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10701 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10702 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10703 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10705 op0
= XEXP (op0
, 1);
10706 code
= (code
== GE
? GT
: LE
);
10712 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10713 will be converted to a ZERO_EXTRACT later. */
10714 if (const_op
== 0 && equality_comparison_p
10715 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10716 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10718 op0
= simplify_and_const_int
10719 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10721 XEXP (XEXP (op0
, 0), 1)),
10722 (HOST_WIDE_INT
) 1);
10726 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10727 zero and X is a comparison and C1 and C2 describe only bits set
10728 in STORE_FLAG_VALUE, we can compare with X. */
10729 if (const_op
== 0 && equality_comparison_p
10730 && mode_width
<= HOST_BITS_PER_WIDE_INT
10731 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10732 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10733 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10734 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10735 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10737 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10738 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10739 if ((~STORE_FLAG_VALUE
& mask
) == 0
10740 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10741 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10742 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10744 op0
= XEXP (XEXP (op0
, 0), 0);
10749 /* If we are doing an equality comparison of an AND of a bit equal
10750 to the sign bit, replace this with a LT or GE comparison of
10751 the underlying value. */
10752 if (equality_comparison_p
10754 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10755 && mode_width
<= HOST_BITS_PER_WIDE_INT
10756 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10757 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10759 op0
= XEXP (op0
, 0);
10760 code
= (code
== EQ
? GE
: LT
);
10764 /* If this AND operation is really a ZERO_EXTEND from a narrower
10765 mode, the constant fits within that mode, and this is either an
10766 equality or unsigned comparison, try to do this comparison in
10767 the narrower mode. */
10768 if ((equality_comparison_p
|| unsigned_comparison_p
)
10769 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10770 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10771 & GET_MODE_MASK (mode
))
10773 && const_op
>> i
== 0
10774 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10776 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10780 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10781 in both M1 and M2 and the SUBREG is either paradoxical or
10782 represents the low part, permute the SUBREG and the AND and
10784 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10786 #ifdef WORD_REGISTER_OPERATIONS
10788 > (GET_MODE_BITSIZE
10789 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10790 && mode_width
<= BITS_PER_WORD
)
10793 <= (GET_MODE_BITSIZE
10794 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10795 && subreg_lowpart_p (XEXP (op0
, 0))))
10796 #ifndef WORD_REGISTER_OPERATIONS
10797 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10798 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10799 As originally written the upper bits have a defined value
10800 due to the AND operation. However, if we commute the AND
10801 inside the SUBREG then they no longer have defined values
10802 and the meaning of the code has been changed. */
10803 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10804 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10806 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10807 && mode_width
<= HOST_BITS_PER_WIDE_INT
10808 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10809 <= HOST_BITS_PER_WIDE_INT
)
10810 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10811 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10812 & INTVAL (XEXP (op0
, 1)))
10813 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10814 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10815 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10819 = gen_lowpart_for_combine
10821 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10822 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10826 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10827 (eq (and (lshiftrt X) 1) 0). */
10828 if (const_op
== 0 && equality_comparison_p
10829 && XEXP (op0
, 1) == const1_rtx
10830 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10831 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10833 op0
= simplify_and_const_int
10835 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10836 XEXP (XEXP (op0
, 0), 1)),
10837 (HOST_WIDE_INT
) 1);
10838 code
= (code
== NE
? EQ
: NE
);
10844 /* If we have (compare (ashift FOO N) (const_int C)) and
10845 the high order N bits of FOO (N+1 if an inequality comparison)
10846 are known to be zero, we can do this by comparing FOO with C
10847 shifted right N bits so long as the low-order N bits of C are
10849 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10850 && INTVAL (XEXP (op0
, 1)) >= 0
10851 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10852 < HOST_BITS_PER_WIDE_INT
)
10854 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10855 && mode_width
<= HOST_BITS_PER_WIDE_INT
10856 && (nonzero_bits (XEXP (op0
, 0), mode
)
10857 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10858 + ! equality_comparison_p
))) == 0)
10860 /* We must perform a logical shift, not an arithmetic one,
10861 as we want the top N bits of C to be zero. */
10862 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10864 temp
>>= INTVAL (XEXP (op0
, 1));
10865 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10866 op0
= XEXP (op0
, 0);
10870 /* If we are doing a sign bit comparison, it means we are testing
10871 a particular bit. Convert it to the appropriate AND. */
10872 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10873 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10875 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10878 - INTVAL (XEXP (op0
, 1)))));
10879 code
= (code
== LT
? NE
: EQ
);
10883 /* If this an equality comparison with zero and we are shifting
10884 the low bit to the sign bit, we can convert this to an AND of the
10886 if (const_op
== 0 && equality_comparison_p
10887 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10888 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10890 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10891 (HOST_WIDE_INT
) 1);
10897 /* If this is an equality comparison with zero, we can do this
10898 as a logical shift, which might be much simpler. */
10899 if (equality_comparison_p
&& const_op
== 0
10900 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10902 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10904 INTVAL (XEXP (op0
, 1)));
10908 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10909 do the comparison in a narrower mode. */
10910 if (! unsigned_comparison_p
10911 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10912 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10913 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10914 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10915 MODE_INT
, 1)) != BLKmode
10916 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10917 || ((unsigned HOST_WIDE_INT
) -const_op
10918 <= GET_MODE_MASK (tmode
))))
10920 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10924 /* Likewise if OP0 is a PLUS of a sign extension with a
10925 constant, which is usually represented with the PLUS
10926 between the shifts. */
10927 if (! unsigned_comparison_p
10928 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10929 && GET_CODE (XEXP (op0
, 0)) == PLUS
10930 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10931 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10932 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10933 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10934 MODE_INT
, 1)) != BLKmode
10935 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10936 || ((unsigned HOST_WIDE_INT
) -const_op
10937 <= GET_MODE_MASK (tmode
))))
10939 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10940 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10941 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10944 op0
= gen_binary (PLUS
, tmode
,
10945 gen_lowpart_for_combine (tmode
, inner
),
10950 /* ... fall through ... */
10952 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10953 the low order N bits of FOO are known to be zero, we can do this
10954 by comparing FOO with C shifted left N bits so long as no
10955 overflow occurs. */
10956 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10957 && INTVAL (XEXP (op0
, 1)) >= 0
10958 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10959 && mode_width
<= HOST_BITS_PER_WIDE_INT
10960 && (nonzero_bits (XEXP (op0
, 0), mode
)
10961 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10963 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10966 const_op
<<= INTVAL (XEXP (op0
, 1));
10967 op1
= GEN_INT (const_op
);
10968 op0
= XEXP (op0
, 0);
10972 /* If we are using this shift to extract just the sign bit, we
10973 can replace this with an LT or GE comparison. */
10975 && (equality_comparison_p
|| sign_bit_comparison_p
)
10976 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10977 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10979 op0
= XEXP (op0
, 0);
10980 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10992 /* Now make any compound operations involved in this comparison. Then,
10993 check for an outmost SUBREG on OP0 that is not doing anything or is
10994 paradoxical. The latter case can only occur when it is known that the
10995 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10996 We can never remove a SUBREG for a non-equality comparison because the
10997 sign bit is in a different place in the underlying object. */
10999 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11000 op1
= make_compound_operation (op1
, SET
);
11002 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11003 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11004 && (code
== NE
|| code
== EQ
)
11005 && ((GET_MODE_SIZE (GET_MODE (op0
))
11006 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
11008 op0
= SUBREG_REG (op0
);
11009 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11012 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11013 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11014 && (code
== NE
|| code
== EQ
)
11015 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11016 <= HOST_BITS_PER_WIDE_INT
)
11017 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
11018 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
11019 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
11021 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11022 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
11023 op0
= SUBREG_REG (op0
), op1
= tem
;
11025 /* We now do the opposite procedure: Some machines don't have compare
11026 insns in all modes. If OP0's mode is an integer mode smaller than a
11027 word and we can't do a compare in that mode, see if there is a larger
11028 mode for which we can do the compare. There are a number of cases in
11029 which we can use the wider mode. */
11031 mode
= GET_MODE (op0
);
11032 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11033 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11034 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
11035 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11037 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11038 tmode
= GET_MODE_WIDER_MODE (tmode
))
11039 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
11041 /* If the only nonzero bits in OP0 and OP1 are those in the
11042 narrower mode and this is an equality or unsigned comparison,
11043 we can use the wider mode. Similarly for sign-extended
11044 values, in which case it is true for all comparisons. */
11045 if (((code
== EQ
|| code
== NE
11046 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
11047 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
11048 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
11049 || ((num_sign_bit_copies (op0
, tmode
)
11050 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
11051 && (num_sign_bit_copies (op1
, tmode
)
11052 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
11054 /* If OP0 is an AND and we don't have an AND in MODE either,
11055 make a new AND in the proper mode. */
11056 if (GET_CODE (op0
) == AND
11057 && (add_optab
->handlers
[(int) mode
].insn_code
11058 == CODE_FOR_nothing
))
11059 op0
= gen_binary (AND
, tmode
,
11060 gen_lowpart_for_combine (tmode
,
11062 gen_lowpart_for_combine (tmode
,
11065 op0
= gen_lowpart_for_combine (tmode
, op0
);
11066 op1
= gen_lowpart_for_combine (tmode
, op1
);
11070 /* If this is a test for negative, we can make an explicit
11071 test of the sign bit. */
11073 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11074 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11076 op0
= gen_binary (AND
, tmode
,
11077 gen_lowpart_for_combine (tmode
, op0
),
11078 GEN_INT ((HOST_WIDE_INT
) 1
11079 << (GET_MODE_BITSIZE (mode
) - 1)));
11080 code
= (code
== LT
) ? NE
: EQ
;
11085 #ifdef CANONICALIZE_COMPARISON
11086 /* If this machine only supports a subset of valid comparisons, see if we
11087 can convert an unsupported one into a supported one. */
11088 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11097 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11098 searching backward. */
11099 static enum rtx_code
11100 combine_reversed_comparison_code (exp
)
11103 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11106 if (code1
!= UNKNOWN
11107 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11109 /* Otherwise try and find where the condition codes were last set and
11111 x
= get_last_value (XEXP (exp
, 0));
11112 if (!x
|| GET_CODE (x
) != COMPARE
)
11114 return reversed_comparison_code_parts (GET_CODE (exp
),
11115 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11117 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11118 Return NULL_RTX in case we fail to do the reversal. */
11120 reversed_comparison (exp
, mode
, op0
, op1
)
11122 enum machine_mode mode
;
11124 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11125 if (reversed_code
== UNKNOWN
)
11128 return gen_binary (reversed_code
, mode
, op0
, op1
);
11131 /* Utility function for following routine. Called when X is part of a value
11132 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11133 for each register mentioned. Similar to mention_regs in cse.c */
11136 update_table_tick (x
)
11139 register enum rtx_code code
= GET_CODE (x
);
11140 register const char *fmt
= GET_RTX_FORMAT (code
);
11145 unsigned int regno
= REGNO (x
);
11146 unsigned int endregno
11147 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11148 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11151 for (r
= regno
; r
< endregno
; r
++)
11152 reg_last_set_table_tick
[r
] = label_tick
;
11157 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11158 /* Note that we can't have an "E" in values stored; see
11159 get_last_value_validate. */
11161 update_table_tick (XEXP (x
, i
));
11164 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11165 are saying that the register is clobbered and we no longer know its
11166 value. If INSN is zero, don't update reg_last_set; this is only permitted
11167 with VALUE also zero and is used to invalidate the register. */
11170 record_value_for_reg (reg
, insn
, value
)
11175 unsigned int regno
= REGNO (reg
);
11176 unsigned int endregno
11177 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11178 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11181 /* If VALUE contains REG and we have a previous value for REG, substitute
11182 the previous value. */
11183 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11187 /* Set things up so get_last_value is allowed to see anything set up to
11189 subst_low_cuid
= INSN_CUID (insn
);
11190 tem
= get_last_value (reg
);
11192 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11193 it isn't going to be useful and will take a lot of time to process,
11194 so just use the CLOBBER. */
11198 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11199 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11200 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11201 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11202 tem
= XEXP (tem
, 0);
11204 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11208 /* For each register modified, show we don't know its value, that
11209 we don't know about its bitwise content, that its value has been
11210 updated, and that we don't know the location of the death of the
11212 for (i
= regno
; i
< endregno
; i
++)
11215 reg_last_set
[i
] = insn
;
11217 reg_last_set_value
[i
] = 0;
11218 reg_last_set_mode
[i
] = 0;
11219 reg_last_set_nonzero_bits
[i
] = 0;
11220 reg_last_set_sign_bit_copies
[i
] = 0;
11221 reg_last_death
[i
] = 0;
11224 /* Mark registers that are being referenced in this value. */
11226 update_table_tick (value
);
11228 /* Now update the status of each register being set.
11229 If someone is using this register in this block, set this register
11230 to invalid since we will get confused between the two lives in this
11231 basic block. This makes using this register always invalid. In cse, we
11232 scan the table to invalidate all entries using this register, but this
11233 is too much work for us. */
11235 for (i
= regno
; i
< endregno
; i
++)
11237 reg_last_set_label
[i
] = label_tick
;
11238 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11239 reg_last_set_invalid
[i
] = 1;
11241 reg_last_set_invalid
[i
] = 0;
11244 /* The value being assigned might refer to X (like in "x++;"). In that
11245 case, we must replace it with (clobber (const_int 0)) to prevent
11247 if (value
&& ! get_last_value_validate (&value
, insn
,
11248 reg_last_set_label
[regno
], 0))
11250 value
= copy_rtx (value
);
11251 if (! get_last_value_validate (&value
, insn
,
11252 reg_last_set_label
[regno
], 1))
11256 /* For the main register being modified, update the value, the mode, the
11257 nonzero bits, and the number of sign bit copies. */
11259 reg_last_set_value
[regno
] = value
;
11263 subst_low_cuid
= INSN_CUID (insn
);
11264 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11265 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11266 reg_last_set_sign_bit_copies
[regno
]
11267 = num_sign_bit_copies (value
, GET_MODE (reg
));
11271 /* Called via note_stores from record_dead_and_set_regs to handle one
11272 SET or CLOBBER in an insn. DATA is the instruction in which the
11273 set is occurring. */
11276 record_dead_and_set_regs_1 (dest
, setter
, data
)
11280 rtx record_dead_insn
= (rtx
) data
;
11282 if (GET_CODE (dest
) == SUBREG
)
11283 dest
= SUBREG_REG (dest
);
11285 if (GET_CODE (dest
) == REG
)
11287 /* If we are setting the whole register, we know its value. Otherwise
11288 show that we don't know the value. We can handle SUBREG in
11290 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11291 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11292 else if (GET_CODE (setter
) == SET
11293 && GET_CODE (SET_DEST (setter
)) == SUBREG
11294 && SUBREG_REG (SET_DEST (setter
)) == dest
11295 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11296 && subreg_lowpart_p (SET_DEST (setter
)))
11297 record_value_for_reg (dest
, record_dead_insn
,
11298 gen_lowpart_for_combine (GET_MODE (dest
),
11299 SET_SRC (setter
)));
11301 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11303 else if (GET_CODE (dest
) == MEM
11304 /* Ignore pushes, they clobber nothing. */
11305 && ! push_operand (dest
, GET_MODE (dest
)))
11306 mem_last_set
= INSN_CUID (record_dead_insn
);
11309 /* Update the records of when each REG was most recently set or killed
11310 for the things done by INSN. This is the last thing done in processing
11311 INSN in the combiner loop.
11313 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11314 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11315 and also the similar information mem_last_set (which insn most recently
11316 modified memory) and last_call_cuid (which insn was the most recent
11317 subroutine call). */
11320 record_dead_and_set_regs (insn
)
11326 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11328 if (REG_NOTE_KIND (link
) == REG_DEAD
11329 && GET_CODE (XEXP (link
, 0)) == REG
)
11331 unsigned int regno
= REGNO (XEXP (link
, 0));
11332 unsigned int endregno
11333 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11334 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11337 for (i
= regno
; i
< endregno
; i
++)
11338 reg_last_death
[i
] = insn
;
11340 else if (REG_NOTE_KIND (link
) == REG_INC
)
11341 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11344 if (GET_CODE (insn
) == CALL_INSN
)
11346 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11347 if (call_used_regs
[i
])
11349 reg_last_set_value
[i
] = 0;
11350 reg_last_set_mode
[i
] = 0;
11351 reg_last_set_nonzero_bits
[i
] = 0;
11352 reg_last_set_sign_bit_copies
[i
] = 0;
11353 reg_last_death
[i
] = 0;
11356 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11359 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11362 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11363 register present in the SUBREG, so for each such SUBREG go back and
11364 adjust nonzero and sign bit information of the registers that are
11365 known to have some zero/sign bits set.
11367 This is needed because when combine blows the SUBREGs away, the
11368 information on zero/sign bits is lost and further combines can be
11369 missed because of that. */
11372 record_promoted_value (insn
, subreg
)
11377 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11378 enum machine_mode mode
= GET_MODE (subreg
);
11380 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11383 for (links
= LOG_LINKS (insn
); links
;)
11385 insn
= XEXP (links
, 0);
11386 set
= single_set (insn
);
11388 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11389 || REGNO (SET_DEST (set
)) != regno
11390 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11392 links
= XEXP (links
, 1);
11396 if (reg_last_set
[regno
] == insn
)
11398 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11399 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11402 if (GET_CODE (SET_SRC (set
)) == REG
)
11404 regno
= REGNO (SET_SRC (set
));
11405 links
= LOG_LINKS (insn
);
11412 /* Scan X for promoted SUBREGs. For each one found,
11413 note what it implies to the registers used in it. */
11416 check_promoted_subreg (insn
, x
)
11420 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11421 && GET_CODE (SUBREG_REG (x
)) == REG
)
11422 record_promoted_value (insn
, x
);
11425 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11428 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11432 check_promoted_subreg (insn
, XEXP (x
, i
));
11436 if (XVEC (x
, i
) != 0)
11437 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11438 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11444 /* Utility routine for the following function. Verify that all the registers
11445 mentioned in *LOC are valid when *LOC was part of a value set when
11446 label_tick == TICK. Return 0 if some are not.
11448 If REPLACE is non-zero, replace the invalid reference with
11449 (clobber (const_int 0)) and return 1. This replacement is useful because
11450 we often can get useful information about the form of a value (e.g., if
11451 it was produced by a shift that always produces -1 or 0) even though
11452 we don't know exactly what registers it was produced from. */
11455 get_last_value_validate (loc
, insn
, tick
, replace
)
11462 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11463 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11466 if (GET_CODE (x
) == REG
)
11468 unsigned int regno
= REGNO (x
);
11469 unsigned int endregno
11470 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11471 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11474 for (j
= regno
; j
< endregno
; j
++)
11475 if (reg_last_set_invalid
[j
]
11476 /* If this is a pseudo-register that was only set once and not
11477 live at the beginning of the function, it is always valid. */
11478 || (! (regno
>= FIRST_PSEUDO_REGISTER
11479 && REG_N_SETS (regno
) == 1
11480 && (! REGNO_REG_SET_P
11481 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11482 && reg_last_set_label
[j
] > tick
))
11485 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11491 /* If this is a memory reference, make sure that there were
11492 no stores after it that might have clobbered the value. We don't
11493 have alias info, so we assume any store invalidates it. */
11494 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11495 && INSN_CUID (insn
) <= mem_last_set
)
11498 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11502 for (i
= 0; i
< len
; i
++)
11504 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11505 /* Don't bother with these. They shouldn't occur anyway. */
11509 /* If we haven't found a reason for it to be invalid, it is valid. */
11513 /* Get the last value assigned to X, if known. Some registers
11514 in the value may be replaced with (clobber (const_int 0)) if their value
11515 is known longer known reliably. */
11521 unsigned int regno
;
11524 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11525 then convert it to the desired mode. If this is a paradoxical SUBREG,
11526 we cannot predict what values the "extra" bits might have. */
11527 if (GET_CODE (x
) == SUBREG
11528 && subreg_lowpart_p (x
)
11529 && (GET_MODE_SIZE (GET_MODE (x
))
11530 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11531 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11532 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11534 if (GET_CODE (x
) != REG
)
11538 value
= reg_last_set_value
[regno
];
11540 /* If we don't have a value, or if it isn't for this basic block and
11541 it's either a hard register, set more than once, or it's a live
11542 at the beginning of the function, return 0.
11544 Because if it's not live at the beginnning of the function then the reg
11545 is always set before being used (is never used without being set).
11546 And, if it's set only once, and it's always set before use, then all
11547 uses must have the same last value, even if it's not from this basic
11551 || (reg_last_set_label
[regno
] != label_tick
11552 && (regno
< FIRST_PSEUDO_REGISTER
11553 || REG_N_SETS (regno
) != 1
11554 || (REGNO_REG_SET_P
11555 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11558 /* If the value was set in a later insn than the ones we are processing,
11559 we can't use it even if the register was only set once. */
11560 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11563 /* If the value has all its registers valid, return it. */
11564 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11565 reg_last_set_label
[regno
], 0))
11568 /* Otherwise, make a copy and replace any invalid register with
11569 (clobber (const_int 0)). If that fails for some reason, return 0. */
11571 value
= copy_rtx (value
);
11572 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11573 reg_last_set_label
[regno
], 1))
11579 /* Return nonzero if expression X refers to a REG or to memory
11580 that is set in an instruction more recent than FROM_CUID. */
11583 use_crosses_set_p (x
, from_cuid
)
11587 register const char *fmt
;
11589 register enum rtx_code code
= GET_CODE (x
);
11593 unsigned int regno
= REGNO (x
);
11594 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11595 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11597 #ifdef PUSH_ROUNDING
11598 /* Don't allow uses of the stack pointer to be moved,
11599 because we don't know whether the move crosses a push insn. */
11600 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11603 for (; regno
< endreg
; regno
++)
11604 if (reg_last_set
[regno
]
11605 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11610 if (code
== MEM
&& mem_last_set
> from_cuid
)
11613 fmt
= GET_RTX_FORMAT (code
);
11615 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11620 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11621 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11624 else if (fmt
[i
] == 'e'
11625 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11631 /* Define three variables used for communication between the following
11634 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11635 static int reg_dead_flag
;
11637 /* Function called via note_stores from reg_dead_at_p.
11639 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11640 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11643 reg_dead_at_p_1 (dest
, x
, data
)
11646 void *data ATTRIBUTE_UNUSED
;
11648 unsigned int regno
, endregno
;
11650 if (GET_CODE (dest
) != REG
)
11653 regno
= REGNO (dest
);
11654 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11655 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11657 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11658 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11661 /* Return non-zero if REG is known to be dead at INSN.
11663 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11664 referencing REG, it is dead. If we hit a SET referencing REG, it is
11665 live. Otherwise, see if it is live or dead at the start of the basic
11666 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11667 must be assumed to be always live. */
11670 reg_dead_at_p (reg
, insn
)
11677 /* Set variables for reg_dead_at_p_1. */
11678 reg_dead_regno
= REGNO (reg
);
11679 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11680 ? HARD_REGNO_NREGS (reg_dead_regno
,
11686 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11687 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11689 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11690 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11694 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11695 beginning of function. */
11696 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11697 insn
= prev_nonnote_insn (insn
))
11699 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11701 return reg_dead_flag
== 1 ? 1 : 0;
11703 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11707 /* Get the basic block number that we were in. */
11712 for (block
= 0; block
< n_basic_blocks
; block
++)
11713 if (insn
== BLOCK_HEAD (block
))
11716 if (block
== n_basic_blocks
)
11720 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11721 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11727 /* Note hard registers in X that are used. This code is similar to
11728 that in flow.c, but much simpler since we don't care about pseudos. */
11731 mark_used_regs_combine (x
)
11734 RTX_CODE code
= GET_CODE (x
);
11735 unsigned int regno
;
11747 case ADDR_DIFF_VEC
:
11750 /* CC0 must die in the insn after it is set, so we don't need to take
11751 special note of it here. */
11757 /* If we are clobbering a MEM, mark any hard registers inside the
11758 address as used. */
11759 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11760 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11765 /* A hard reg in a wide mode may really be multiple registers.
11766 If so, mark all of them just like the first. */
11767 if (regno
< FIRST_PSEUDO_REGISTER
)
11769 unsigned int endregno
, r
;
11771 /* None of this applies to the stack, frame or arg pointers */
11772 if (regno
== STACK_POINTER_REGNUM
11773 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11774 || regno
== HARD_FRAME_POINTER_REGNUM
11776 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11777 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11779 || regno
== FRAME_POINTER_REGNUM
)
11782 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11783 for (r
= regno
; r
< endregno
; r
++)
11784 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11790 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11792 register rtx testreg
= SET_DEST (x
);
11794 while (GET_CODE (testreg
) == SUBREG
11795 || GET_CODE (testreg
) == ZERO_EXTRACT
11796 || GET_CODE (testreg
) == SIGN_EXTRACT
11797 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11798 testreg
= XEXP (testreg
, 0);
11800 if (GET_CODE (testreg
) == MEM
)
11801 mark_used_regs_combine (XEXP (testreg
, 0));
11803 mark_used_regs_combine (SET_SRC (x
));
11811 /* Recursively scan the operands of this expression. */
11814 register const char *fmt
= GET_RTX_FORMAT (code
);
11816 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11819 mark_used_regs_combine (XEXP (x
, i
));
11820 else if (fmt
[i
] == 'E')
11824 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11825 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11831 /* Remove register number REGNO from the dead registers list of INSN.
11833 Return the note used to record the death, if there was one. */
11836 remove_death (regno
, insn
)
11837 unsigned int regno
;
11840 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11844 REG_N_DEATHS (regno
)--;
11845 remove_note (insn
, note
);
11851 /* For each register (hardware or pseudo) used within expression X, if its
11852 death is in an instruction with cuid between FROM_CUID (inclusive) and
11853 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11854 list headed by PNOTES.
11856 That said, don't move registers killed by maybe_kill_insn.
11858 This is done when X is being merged by combination into TO_INSN. These
11859 notes will then be distributed as needed. */
11862 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11864 rtx maybe_kill_insn
;
11869 register const char *fmt
;
11870 register int len
, i
;
11871 register enum rtx_code code
= GET_CODE (x
);
11875 unsigned int regno
= REGNO (x
);
11876 register rtx where_dead
= reg_last_death
[regno
];
11877 register rtx before_dead
, after_dead
;
11879 /* Don't move the register if it gets killed in between from and to */
11880 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11881 && ! reg_referenced_p (x
, maybe_kill_insn
))
11884 /* WHERE_DEAD could be a USE insn made by combine, so first we
11885 make sure that we have insns with valid INSN_CUID values. */
11886 before_dead
= where_dead
;
11887 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11888 before_dead
= PREV_INSN (before_dead
);
11890 after_dead
= where_dead
;
11891 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11892 after_dead
= NEXT_INSN (after_dead
);
11894 if (before_dead
&& after_dead
11895 && INSN_CUID (before_dead
) >= from_cuid
11896 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11897 || (where_dead
!= after_dead
11898 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11900 rtx note
= remove_death (regno
, where_dead
);
11902 /* It is possible for the call above to return 0. This can occur
11903 when reg_last_death points to I2 or I1 that we combined with.
11904 In that case make a new note.
11906 We must also check for the case where X is a hard register
11907 and NOTE is a death note for a range of hard registers
11908 including X. In that case, we must put REG_DEAD notes for
11909 the remaining registers in place of NOTE. */
11911 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11912 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11913 > GET_MODE_SIZE (GET_MODE (x
))))
11915 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11916 unsigned int deadend
11917 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11918 GET_MODE (XEXP (note
, 0))));
11919 unsigned int ourend
11920 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11923 for (i
= deadregno
; i
< deadend
; i
++)
11924 if (i
< regno
|| i
>= ourend
)
11925 REG_NOTES (where_dead
)
11926 = gen_rtx_EXPR_LIST (REG_DEAD
,
11927 gen_rtx_REG (reg_raw_mode
[i
], i
),
11928 REG_NOTES (where_dead
));
11931 /* If we didn't find any note, or if we found a REG_DEAD note that
11932 covers only part of the given reg, and we have a multi-reg hard
11933 register, then to be safe we must check for REG_DEAD notes
11934 for each register other than the first. They could have
11935 their own REG_DEAD notes lying around. */
11936 else if ((note
== 0
11938 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11939 < GET_MODE_SIZE (GET_MODE (x
)))))
11940 && regno
< FIRST_PSEUDO_REGISTER
11941 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11943 unsigned int ourend
11944 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11945 unsigned int i
, offset
;
11949 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11953 for (i
= regno
+ offset
; i
< ourend
; i
++)
11954 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11955 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11958 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11960 XEXP (note
, 1) = *pnotes
;
11964 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11966 REG_N_DEATHS (regno
)++;
11972 else if (GET_CODE (x
) == SET
)
11974 rtx dest
= SET_DEST (x
);
11976 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11978 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11979 that accesses one word of a multi-word item, some
11980 piece of everything register in the expression is used by
11981 this insn, so remove any old death. */
11982 /* ??? So why do we test for equality of the sizes? */
11984 if (GET_CODE (dest
) == ZERO_EXTRACT
11985 || GET_CODE (dest
) == STRICT_LOW_PART
11986 || (GET_CODE (dest
) == SUBREG
11987 && (((GET_MODE_SIZE (GET_MODE (dest
))
11988 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11989 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11990 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11992 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11996 /* If this is some other SUBREG, we know it replaces the entire
11997 value, so use that as the destination. */
11998 if (GET_CODE (dest
) == SUBREG
)
11999 dest
= SUBREG_REG (dest
);
12001 /* If this is a MEM, adjust deaths of anything used in the address.
12002 For a REG (the only other possibility), the entire value is
12003 being replaced so the old value is not used in this insn. */
12005 if (GET_CODE (dest
) == MEM
)
12006 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12011 else if (GET_CODE (x
) == CLOBBER
)
12014 len
= GET_RTX_LENGTH (code
);
12015 fmt
= GET_RTX_FORMAT (code
);
12017 for (i
= 0; i
< len
; i
++)
12022 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12023 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12026 else if (fmt
[i
] == 'e')
12027 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12031 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12032 pattern of an insn. X must be a REG. */
12035 reg_bitfield_target_p (x
, body
)
12041 if (GET_CODE (body
) == SET
)
12043 rtx dest
= SET_DEST (body
);
12045 unsigned int regno
, tregno
, endregno
, endtregno
;
12047 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12048 target
= XEXP (dest
, 0);
12049 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12050 target
= SUBREG_REG (XEXP (dest
, 0));
12054 if (GET_CODE (target
) == SUBREG
)
12055 target
= SUBREG_REG (target
);
12057 if (GET_CODE (target
) != REG
)
12060 tregno
= REGNO (target
), regno
= REGNO (x
);
12061 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12062 return target
== x
;
12064 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12065 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12067 return endregno
> tregno
&& regno
< endtregno
;
12070 else if (GET_CODE (body
) == PARALLEL
)
12071 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12072 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12078 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12079 as appropriate. I3 and I2 are the insns resulting from the combination
12080 insns including FROM (I2 may be zero).
12082 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12083 not need REG_DEAD notes because they are being substituted for. This
12084 saves searching in the most common cases.
12086 Each note in the list is either ignored or placed on some insns, depending
12087 on the type of note. */
12090 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12094 rtx elim_i2
, elim_i1
;
12096 rtx note
, next_note
;
12099 for (note
= notes
; note
; note
= next_note
)
12101 rtx place
= 0, place2
= 0;
12103 /* If this NOTE references a pseudo register, ensure it references
12104 the latest copy of that register. */
12105 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12106 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12107 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12109 next_note
= XEXP (note
, 1);
12110 switch (REG_NOTE_KIND (note
))
12113 case REG_EXEC_COUNT
:
12114 /* Doesn't matter much where we put this, as long as it's somewhere.
12115 It is preferable to keep these notes on branches, which is most
12116 likely to be i3. */
12120 case REG_NON_LOCAL_GOTO
:
12121 if (GET_CODE (i3
) == JUMP_INSN
)
12123 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12129 case REG_EH_REGION
:
12130 /* These notes must remain with the call or trapping instruction. */
12131 if (GET_CODE (i3
) == CALL_INSN
)
12133 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12135 else if (flag_non_call_exceptions
)
12137 if (may_trap_p (i3
))
12139 else if (i2
&& may_trap_p (i2
))
12141 /* ??? Otherwise assume we've combined things such that we
12142 can now prove that the instructions can't trap. Drop the
12143 note in this case. */
12149 case REG_EH_RETHROW
:
12151 /* These notes must remain with the call. It should not be
12152 possible for both I2 and I3 to be a call. */
12153 if (GET_CODE (i3
) == CALL_INSN
)
12155 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12162 /* Any clobbers for i3 may still exist, and so we must process
12163 REG_UNUSED notes from that insn.
12165 Any clobbers from i2 or i1 can only exist if they were added by
12166 recog_for_combine. In that case, recog_for_combine created the
12167 necessary REG_UNUSED notes. Trying to keep any original
12168 REG_UNUSED notes from these insns can cause incorrect output
12169 if it is for the same register as the original i3 dest.
12170 In that case, we will notice that the register is set in i3,
12171 and then add a REG_UNUSED note for the destination of i3, which
12172 is wrong. However, it is possible to have REG_UNUSED notes from
12173 i2 or i1 for register which were both used and clobbered, so
12174 we keep notes from i2 or i1 if they will turn into REG_DEAD
12177 /* If this register is set or clobbered in I3, put the note there
12178 unless there is one already. */
12179 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12181 if (from_insn
!= i3
)
12184 if (! (GET_CODE (XEXP (note
, 0)) == REG
12185 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12186 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12189 /* Otherwise, if this register is used by I3, then this register
12190 now dies here, so we must put a REG_DEAD note here unless there
12192 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12193 && ! (GET_CODE (XEXP (note
, 0)) == REG
12194 ? find_regno_note (i3
, REG_DEAD
,
12195 REGNO (XEXP (note
, 0)))
12196 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12198 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12206 /* These notes say something about results of an insn. We can
12207 only support them if they used to be on I3 in which case they
12208 remain on I3. Otherwise they are ignored.
12210 If the note refers to an expression that is not a constant, we
12211 must also ignore the note since we cannot tell whether the
12212 equivalence is still true. It might be possible to do
12213 slightly better than this (we only have a problem if I2DEST
12214 or I1DEST is present in the expression), but it doesn't
12215 seem worth the trouble. */
12217 if (from_insn
== i3
12218 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12223 case REG_NO_CONFLICT
:
12224 /* These notes say something about how a register is used. They must
12225 be present on any use of the register in I2 or I3. */
12226 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12229 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12239 /* This can show up in several ways -- either directly in the
12240 pattern, or hidden off in the constant pool with (or without?)
12241 a REG_EQUAL note. */
12242 /* ??? Ignore the without-reg_equal-note problem for now. */
12243 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12244 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12245 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12246 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12250 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12251 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12252 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12253 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12264 /* These notes say something about the value of a register prior
12265 to the execution of an insn. It is too much trouble to see
12266 if the note is still correct in all situations. It is better
12267 to simply delete it. */
12271 /* If the insn previously containing this note still exists,
12272 put it back where it was. Otherwise move it to the previous
12273 insn. Adjust the corresponding REG_LIBCALL note. */
12274 if (GET_CODE (from_insn
) != NOTE
)
12278 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12279 place
= prev_real_insn (from_insn
);
12281 XEXP (tem
, 0) = place
;
12282 /* If we're deleting the last remaining instruction of a
12283 libcall sequence, don't add the notes. */
12284 else if (XEXP (note
, 0) == from_insn
)
12290 /* This is handled similarly to REG_RETVAL. */
12291 if (GET_CODE (from_insn
) != NOTE
)
12295 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12296 place
= next_real_insn (from_insn
);
12298 XEXP (tem
, 0) = place
;
12299 /* If we're deleting the last remaining instruction of a
12300 libcall sequence, don't add the notes. */
12301 else if (XEXP (note
, 0) == from_insn
)
12307 /* If the register is used as an input in I3, it dies there.
12308 Similarly for I2, if it is non-zero and adjacent to I3.
12310 If the register is not used as an input in either I3 or I2
12311 and it is not one of the registers we were supposed to eliminate,
12312 there are two possibilities. We might have a non-adjacent I2
12313 or we might have somehow eliminated an additional register
12314 from a computation. For example, we might have had A & B where
12315 we discover that B will always be zero. In this case we will
12316 eliminate the reference to A.
12318 In both cases, we must search to see if we can find a previous
12319 use of A and put the death note there. */
12322 && GET_CODE (from_insn
) == CALL_INSN
12323 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12325 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12327 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12328 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12331 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12332 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12337 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12339 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12341 if (! INSN_P (tem
))
12343 if (tem
== bb
->head
)
12348 /* If the register is being set at TEM, see if that is all
12349 TEM is doing. If so, delete TEM. Otherwise, make this
12350 into a REG_UNUSED note instead. */
12351 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12353 rtx set
= single_set (tem
);
12354 rtx inner_dest
= 0;
12356 rtx cc0_setter
= NULL_RTX
;
12360 for (inner_dest
= SET_DEST (set
);
12361 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12362 || GET_CODE (inner_dest
) == SUBREG
12363 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12364 inner_dest
= XEXP (inner_dest
, 0))
12367 /* Verify that it was the set, and not a clobber that
12368 modified the register.
12370 CC0 targets must be careful to maintain setter/user
12371 pairs. If we cannot delete the setter due to side
12372 effects, mark the user with an UNUSED note instead
12375 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12376 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12378 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12379 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12380 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12384 /* Move the notes and links of TEM elsewhere.
12385 This might delete other dead insns recursively.
12386 First set the pattern to something that won't use
12389 PATTERN (tem
) = pc_rtx
;
12391 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12392 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12393 distribute_links (LOG_LINKS (tem
));
12395 PUT_CODE (tem
, NOTE
);
12396 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12397 NOTE_SOURCE_FILE (tem
) = 0;
12400 /* Delete the setter too. */
12403 PATTERN (cc0_setter
) = pc_rtx
;
12405 distribute_notes (REG_NOTES (cc0_setter
),
12406 cc0_setter
, cc0_setter
,
12407 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12408 distribute_links (LOG_LINKS (cc0_setter
));
12410 PUT_CODE (cc0_setter
, NOTE
);
12411 NOTE_LINE_NUMBER (cc0_setter
)
12412 = NOTE_INSN_DELETED
;
12413 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12417 /* If the register is both set and used here, put the
12418 REG_DEAD note here, but place a REG_UNUSED note
12419 here too unless there already is one. */
12420 else if (reg_referenced_p (XEXP (note
, 0),
12425 if (! find_regno_note (tem
, REG_UNUSED
,
12426 REGNO (XEXP (note
, 0))))
12428 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12433 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12435 /* If there isn't already a REG_UNUSED note, put one
12437 if (! find_regno_note (tem
, REG_UNUSED
,
12438 REGNO (XEXP (note
, 0))))
12443 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12444 || (GET_CODE (tem
) == CALL_INSN
12445 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12449 /* If we are doing a 3->2 combination, and we have a
12450 register which formerly died in i3 and was not used
12451 by i2, which now no longer dies in i3 and is used in
12452 i2 but does not die in i2, and place is between i2
12453 and i3, then we may need to move a link from place to
12455 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12456 && INSN_CUID (place
) > INSN_CUID (i2
)
12458 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12459 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12461 rtx links
= LOG_LINKS (place
);
12462 LOG_LINKS (place
) = 0;
12463 distribute_links (links
);
12468 if (tem
== bb
->head
)
12472 /* We haven't found an insn for the death note and it
12473 is still a REG_DEAD note, but we have hit the beginning
12474 of the block. If the existing life info says the reg
12475 was dead, there's nothing left to do. Otherwise, we'll
12476 need to do a global life update after combine. */
12477 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12478 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12479 REGNO (XEXP (note
, 0))))
12481 SET_BIT (refresh_blocks
, this_basic_block
);
12486 /* If the register is set or already dead at PLACE, we needn't do
12487 anything with this note if it is still a REG_DEAD note.
12488 We can here if it is set at all, not if is it totally replace,
12489 which is what `dead_or_set_p' checks, so also check for it being
12492 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12494 unsigned int regno
= REGNO (XEXP (note
, 0));
12496 if (dead_or_set_p (place
, XEXP (note
, 0))
12497 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12499 /* Unless the register previously died in PLACE, clear
12500 reg_last_death. [I no longer understand why this is
12502 if (reg_last_death
[regno
] != place
)
12503 reg_last_death
[regno
] = 0;
12507 reg_last_death
[regno
] = place
;
12509 /* If this is a death note for a hard reg that is occupying
12510 multiple registers, ensure that we are still using all
12511 parts of the object. If we find a piece of the object
12512 that is unused, we must arrange for an appropriate REG_DEAD
12513 note to be added for it. However, we can't just emit a USE
12514 and tag the note to it, since the register might actually
12515 be dead; so we recourse, and the recursive call then finds
12516 the previous insn that used this register. */
12518 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12519 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12521 unsigned int endregno
12522 = regno
+ HARD_REGNO_NREGS (regno
,
12523 GET_MODE (XEXP (note
, 0)));
12527 for (i
= regno
; i
< endregno
; i
++)
12528 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12529 && ! find_regno_fusage (place
, USE
, i
))
12530 || dead_or_set_regno_p (place
, i
))
12535 /* Put only REG_DEAD notes for pieces that are
12536 not already dead or set. */
12538 for (i
= regno
; i
< endregno
;
12539 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12541 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12542 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12544 if (! dead_or_set_p (place
, piece
)
12545 && ! reg_bitfield_target_p (piece
,
12549 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12551 distribute_notes (new_note
, place
, place
,
12552 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12554 else if (! refers_to_regno_p (i
, i
+ 1,
12555 PATTERN (place
), 0)
12556 && ! find_regno_fusage (place
, USE
, i
))
12557 for (tem
= PREV_INSN (place
); ;
12558 tem
= PREV_INSN (tem
))
12560 if (! INSN_P (tem
))
12562 if (tem
== bb
->head
)
12564 SET_BIT (refresh_blocks
,
12571 if (dead_or_set_p (tem
, piece
)
12572 || reg_bitfield_target_p (piece
,
12576 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12591 /* Any other notes should not be present at this point in the
12598 XEXP (note
, 1) = REG_NOTES (place
);
12599 REG_NOTES (place
) = note
;
12601 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12602 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12603 && GET_CODE (XEXP (note
, 0)) == REG
)
12604 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12608 if ((REG_NOTE_KIND (note
) == REG_DEAD
12609 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12610 && GET_CODE (XEXP (note
, 0)) == REG
)
12611 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12613 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12614 REG_NOTE_KIND (note
),
12616 REG_NOTES (place2
));
12621 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12622 I3, I2, and I1 to new locations. This is also called in one case to
12623 add a link pointing at I3 when I3's destination is changed. */
12626 distribute_links (links
)
12629 rtx link
, next_link
;
12631 for (link
= links
; link
; link
= next_link
)
12637 next_link
= XEXP (link
, 1);
12639 /* If the insn that this link points to is a NOTE or isn't a single
12640 set, ignore it. In the latter case, it isn't clear what we
12641 can do other than ignore the link, since we can't tell which
12642 register it was for. Such links wouldn't be used by combine
12645 It is not possible for the destination of the target of the link to
12646 have been changed by combine. The only potential of this is if we
12647 replace I3, I2, and I1 by I3 and I2. But in that case the
12648 destination of I2 also remains unchanged. */
12650 if (GET_CODE (XEXP (link
, 0)) == NOTE
12651 || (set
= single_set (XEXP (link
, 0))) == 0)
12654 reg
= SET_DEST (set
);
12655 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12656 || GET_CODE (reg
) == SIGN_EXTRACT
12657 || GET_CODE (reg
) == STRICT_LOW_PART
)
12658 reg
= XEXP (reg
, 0);
12660 /* A LOG_LINK is defined as being placed on the first insn that uses
12661 a register and points to the insn that sets the register. Start
12662 searching at the next insn after the target of the link and stop
12663 when we reach a set of the register or the end of the basic block.
12665 Note that this correctly handles the link that used to point from
12666 I3 to I2. Also note that not much searching is typically done here
12667 since most links don't point very far away. */
12669 for (insn
= NEXT_INSN (XEXP (link
, 0));
12670 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12671 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12672 insn
= NEXT_INSN (insn
))
12673 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12675 if (reg_referenced_p (reg
, PATTERN (insn
)))
12679 else if (GET_CODE (insn
) == CALL_INSN
12680 && find_reg_fusage (insn
, USE
, reg
))
12686 /* If we found a place to put the link, place it there unless there
12687 is already a link to the same insn as LINK at that point. */
12693 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12694 if (XEXP (link2
, 0) == XEXP (link
, 0))
12699 XEXP (link
, 1) = LOG_LINKS (place
);
12700 LOG_LINKS (place
) = link
;
12702 /* Set added_links_insn to the earliest insn we added a
12704 if (added_links_insn
== 0
12705 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12706 added_links_insn
= place
;
12712 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12718 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12719 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12720 insn
= NEXT_INSN (insn
);
12722 if (INSN_UID (insn
) > max_uid_cuid
)
12725 return INSN_CUID (insn
);
12729 dump_combine_stats (file
)
12734 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12735 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12739 dump_combine_total_stats (file
)
12744 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12745 total_attempts
, total_merges
, total_extras
, total_successes
);