1 ;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors.
2 ;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 2, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to the
18 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19 ;; MA 02110-1301, USA.
21 (define_automaton "ppc7xx,ppc7xxfp")
22 (define_cpu_unit "iu1_7xx,iu2_7xx" "ppc7xx")
23 (define_cpu_unit "fpu_7xx" "ppc7xxfp")
24 (define_cpu_unit "lsu_7xx,bpu_7xx,sru_7xx" "ppc7xx")
25 (define_cpu_unit "du1_7xx,du2_7xx" "ppc7xx")
26 (define_cpu_unit "veccmplx_7xx,vecperm_7xx,vdu_7xx" "ppc7xx")
28 ;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU
29 ;; IU1 can perform all integer operations
30 ;; IU2 can perform all integer operations except imul and idiv
31 ;; LSU 2 stage pipelined
32 ;; FPU 3 stage pipelined
33 ;; Max issue 3 insns/clock cycle (includes 1 branch)
37 ;; The PPC750 user's manual recommends that to reduce branch mispredictions,
38 ;; the insn that sets CR bits should be separated from the branch insn
39 ;; that evaluates them. There is no advantage have more than 10 cycles
41 ;; This could be artificially achieved by exaggerating the latency of
42 ;; compare insns but at the expense of a poorer schedule.
44 ;; Branches go straight to the BPU. All other insns are handled
45 ;; by a dispatch unit which can issue a max of 2 insns per cycle.
46 (define_reservation "ppc750_du" "du1_7xx|du2_7xx")
47 (define_reservation "ppc7400_vec_du" "vdu_7xx")
49 (define_insn_reservation "ppc750-load" 2
50 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
51 load_ux,load_u,fpload,fpload_ux,fpload_u,vecload")
52 (eq_attr "cpu" "ppc750,ppc7400"))
55 (define_insn_reservation "ppc750-store" 1
56 (and (eq_attr "type" "store,store_ux,store_u,\
57 fpstore,fpstore_ux,fpstore_u,vecstore")
58 (eq_attr "cpu" "ppc750,ppc7400"))
61 (define_insn_reservation "ppc750-integer" 1
62 (and (eq_attr "type" "integer,insert_word")
63 (eq_attr "cpu" "ppc750,ppc7400"))
64 "ppc750_du,iu1_7xx|iu2_7xx")
66 (define_insn_reservation "ppc750-two" 1
67 (and (eq_attr "type" "two")
68 (eq_attr "cpu" "ppc750,ppc7400"))
69 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
71 (define_insn_reservation "ppc750-three" 1
72 (and (eq_attr "type" "three")
73 (eq_attr "cpu" "ppc750,ppc7400"))
74 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
76 (define_insn_reservation "ppc750-imul" 4
77 (and (eq_attr "type" "imul,imul_compare")
78 (eq_attr "cpu" "ppc750,ppc7400"))
79 "ppc750_du,iu1_7xx*4")
81 (define_insn_reservation "ppc750-imul2" 3
82 (and (eq_attr "type" "imul2")
83 (eq_attr "cpu" "ppc750,ppc7400"))
84 "ppc750_du,iu1_7xx*2")
86 (define_insn_reservation "ppc750-imul3" 2
87 (and (eq_attr "type" "imul3")
88 (eq_attr "cpu" "ppc750,ppc7400"))
91 (define_insn_reservation "ppc750-idiv" 19
92 (and (eq_attr "type" "idiv")
93 (eq_attr "cpu" "ppc750,ppc7400"))
94 "ppc750_du,iu1_7xx*19")
96 (define_insn_reservation "ppc750-compare" 2
97 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
98 (eq_attr "cpu" "ppc750,ppc7400"))
99 "ppc750_du,(iu1_7xx|iu2_7xx)")
101 (define_insn_reservation "ppc750-fpcompare" 2
102 (and (eq_attr "type" "fpcompare")
103 (eq_attr "cpu" "ppc750,ppc7400"))
106 (define_insn_reservation "ppc750-fp" 3
107 (and (eq_attr "type" "fp")
108 (eq_attr "cpu" "ppc750,ppc7400"))
111 (define_insn_reservation "ppc750-dmul" 4
112 (and (eq_attr "type" "dmul")
113 (eq_attr "cpu" "ppc750"))
114 "ppc750_du,fpu_7xx*2")
116 (define_insn_reservation "ppc7400-dmul" 3
117 (and (eq_attr "type" "dmul")
118 (eq_attr "cpu" "ppc7400"))
121 ; Divides are not pipelined
122 (define_insn_reservation "ppc750-sdiv" 17
123 (and (eq_attr "type" "sdiv")
124 (eq_attr "cpu" "ppc750,ppc7400"))
125 "ppc750_du,fpu_7xx*17")
127 (define_insn_reservation "ppc750-ddiv" 31
128 (and (eq_attr "type" "ddiv")
129 (eq_attr "cpu" "ppc750,ppc7400"))
130 "ppc750_du,fpu_7xx*31")
132 (define_insn_reservation "ppc750-mfcr" 2
133 (and (eq_attr "type" "mfcr,mtcr")
134 (eq_attr "cpu" "ppc750,ppc7400"))
137 (define_insn_reservation "ppc750-crlogical" 3
138 (and (eq_attr "type" "cr_logical,delayed_cr")
139 (eq_attr "cpu" "ppc750,ppc7400"))
140 "ppc750_du,sru_7xx*2")
142 (define_insn_reservation "ppc750-mtjmpr" 2
143 (and (eq_attr "type" "mtjmpr")
144 (eq_attr "cpu" "ppc750,ppc7400"))
147 (define_insn_reservation "ppc750-mfjmpr" 3
148 (and (eq_attr "type" "mfjmpr")
149 (eq_attr "cpu" "ppc750,ppc7400"))
152 (define_insn_reservation "ppc750-jmpreg" 1
153 (and (eq_attr "type" "jmpreg,branch")
154 (eq_attr "cpu" "ppc750,ppc7400"))
158 (define_insn_reservation "ppc7400-vecsimple" 1
159 (and (eq_attr "type" "vecsimple,veccmp")
160 (eq_attr "cpu" "ppc7400"))
161 "ppc750_du,ppc7400_vec_du,veccmplx_7xx")
163 (define_insn_reservation "ppc7400-veccomplex" 4
164 (and (eq_attr "type" "veccomplex")
165 (eq_attr "cpu" "ppc7400"))
166 "ppc750_du,ppc7400_vec_du,veccmplx_7xx")
168 (define_insn_reservation "ppc7400-vecfloat" 4
169 (and (eq_attr "type" "vecfloat")
170 (eq_attr "cpu" "ppc7400"))
171 "ppc750_du,ppc7400_vec_du,veccmplx_7xx")
173 (define_insn_reservation "ppc7400-vecperm" 2
174 (and (eq_attr "type" "vecperm")
175 (eq_attr "cpu" "ppc7400"))
176 "ppc750_du,ppc7400_vec_du,vecperm_7xx")