1 ;; Faraday FA606TE Pipeline Description
2 ;; Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 3, or (at your option) any later
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; These descriptions are based on the information contained in the
22 ;; FA606TE Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
24 ;; Modeled pipeline characteristics:
25 ;; LD -> any use: latency = 2 (1 cycle penalty).
26 ;; ALU -> any use: latency = 1 (0 cycle penalty).
28 ;; This automaton provides a pipeline description for the Faraday
31 ;; The model given here assumes that the condition for all conditional
32 ;; instructions is "true", i.e., that all of the instructions are
35 (define_automaton "fa606te")
37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
39 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
41 ;; There is a single pipeline
43 ;; The ALU pipeline has fetch, decode, execute, memory, and
44 ;; write stages. We only need to model the execute, memory and write
49 (define_cpu_unit "fa606te_core" "fa606te")
51 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
55 ;; ALU instructions require two cycles to execute, and use the ALU
56 ;; pipeline in each of the three stages. The results are available
57 ;; after the execute stage stage has finished.
59 ;; If the destination register is the PC, the pipelines are stalled
60 ;; for several cycles. That case is not modeled here.
63 (define_insn_reservation "606te_alu_op" 1
64 (and (eq_attr "tune" "fa606te")
65 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
66 alu_sreg,alus_sreg,logic_reg,logics_reg,\
67 adc_imm,adcs_imm,adc_reg,adcs_reg,\
69 shift_imm,shift_reg,extend,\
70 alu_shift_imm,alus_shift_imm,\
71 logic_shift_imm,logics_shift_imm,\
72 alu_shift_reg,alus_shift_reg,\
73 logic_shift_reg,logics_shift_reg,\
74 mov_imm,mov_reg,mov_shift,mov_shift_reg,\
75 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
76 mrs,multiple,no_insn"))
79 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
80 ;; Multiplication Instructions
81 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
83 (define_insn_reservation "606te_mult1" 2
84 (and (eq_attr "tune" "fa606te")
85 (eq_attr "type" "smlalxy"))
88 (define_insn_reservation "606te_mult2" 3
89 (and (eq_attr "tune" "fa606te")
90 (eq_attr "type" "smlaxy,smulxy,smulwy,smlawy"))
93 (define_insn_reservation "606te_mult3" 4
94 (and (eq_attr "tune" "fa606te")
95 (eq_attr "type" "mul,mla,muls,mlas"))
98 (define_insn_reservation "606te_mult4" 5
99 (and (eq_attr "tune" "fa606te")
100 (eq_attr "type" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals"))
103 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
104 ;; Load/Store Instructions
105 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
107 ;; The models for load/store instructions do not accurately describe
108 ;; the difference between operations with a base register writeback
109 ;; (such as "ldm!"). These models assume that all memory references
112 (define_insn_reservation "606te_load1_op" 2
113 (and (eq_attr "tune" "fa606te")
114 (eq_attr "type" "load1,load_byte"))
117 (define_insn_reservation "606te_load2_op" 3
118 (and (eq_attr "tune" "fa606te")
119 (eq_attr "type" "load2"))
122 (define_insn_reservation "606te_load3_op" 4
123 (and (eq_attr "tune" "fa606te")
124 (eq_attr "type" "load3"))
127 (define_insn_reservation "606te_load4_op" 5
128 (and (eq_attr "tune" "fa606te")
129 (eq_attr "type" "load4"))
132 (define_insn_reservation "606te_store1_op" 0
133 (and (eq_attr "tune" "fa606te")
134 (eq_attr "type" "store1"))
137 (define_insn_reservation "606te_store2_op" 1
138 (and (eq_attr "tune" "fa606te")
139 (eq_attr "type" "store2"))
142 (define_insn_reservation "606te_store3_op" 2
143 (and (eq_attr "tune" "fa606te")
144 (eq_attr "type" "store3"))
147 (define_insn_reservation "606te_store4_op" 3
148 (and (eq_attr "tune" "fa606te")
149 (eq_attr "type" "store4"))
153 ;;(define_insn_reservation "606te_ldm_op" 9
154 ;; (and (eq_attr "tune" "fa606te")
155 ;; (eq_attr "type" "load2,load3,load4,store2,store3,store4"))
158 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
159 ;; Branch and Call Instructions
160 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
162 ;; Branch instructions are difficult to model accurately. The FA606TE
163 ;; core can predict most branches. If the branch is predicted
164 ;; correctly, and predicted early enough, the branch can be completely
165 ;; eliminated from the instruction stream. Some branches can
166 ;; therefore appear to require zero cycles to execute. We assume that
167 ;; all branches are predicted correctly, and that the latency is
168 ;; therefore the minimum value.
170 (define_insn_reservation "606te_branch_op" 0
171 (and (eq_attr "tune" "fa606te")
172 (eq_attr "type" "branch"))
175 ;; The latency for a call is actually the latency when the result is available.
176 ;; i.e. R0 ready for int return value. For most cases, the return value is set
177 ;; by a mov instruction, which has 1 cycle latency.
178 (define_insn_reservation "606te_call_op" 1
179 (and (eq_attr "tune" "fa606te")
180 (eq_attr "type" "call"))