1 ;; ARM Cortex-A15 NEON pipeline description
2 ;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful, but
12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 ;; General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_attr "cortex_a15_neon_type"
21 "neon_abd, neon_abd_q, neon_arith_acc, neon_arith_acc_q,
22 neon_arith_basic, neon_arith_complex,
23 neon_reduc_add_acc, neon_multiply, neon_multiply_q,
24 neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long,
25 neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic,\
26 neon_shift_imm_complex,
27 neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex,
28 neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith,
29 neon_fp_arith_q, neon_fp_cvt_int,
30 neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul,
31 neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte,
32 neon_fp_recpe_rsqrte_q, neon_bitops, neon_bitops_q, neon_from_gp,
33 neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp,
34 neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e,
35 neon_load_f, neon_store_a, neon_store_b, neon_store_c, neon_store_d,
36 neon_store_e, neon_store_f, neon_store_g, neon_store_h,
39 (eq_attr "type" "neon_abd, neon_abd_long")
40 (const_string "neon_abd")
41 (eq_attr "type" "neon_abd_q")
42 (const_string "neon_abd_q")
43 (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\
44 neon_reduc_add_acc_q")
45 (const_string "neon_arith_acc")
46 (eq_attr "type" "neon_arith_acc_q")
47 (const_string "neon_arith_acc_q")
48 (eq_attr "type" "neon_add, neon_add_q, neon_add_long,\
49 neon_add_widen, neon_neg, neon_neg_q,\
50 neon_reduc_add, neon_reduc_add_q,\
51 neon_reduc_add_long, neon_sub, neon_sub_q,\
52 neon_sub_long, neon_sub_widen, neon_logic,\
53 neon_logic_q, neon_tst, neon_tst_q")
54 (const_string "neon_arith_basic")
55 (eq_attr "type" "neon_abs, neon_abs_q, neon_add_halve_narrow_q,\
56 neon_add_halve, neon_add_halve_q,\
57 neon_sub_halve, neon_sub_halve_q, neon_qabs,\
58 neon_qabs_q, neon_qadd, neon_qadd_q, neon_qneg,\
59 neon_qneg_q, neon_qsub, neon_qsub_q,\
60 neon_sub_halve_narrow_q,\
61 neon_compare, neon_compare_q,\
62 neon_compare_zero, neon_compare_zero_q,\
63 neon_minmax, neon_minmax_q, neon_reduc_minmax,\
65 (const_string "neon_arith_complex")
67 (eq_attr "type" "neon_mul_b, neon_mul_h, neon_mul_s,\
68 neon_mul_h_scalar, neon_mul_s_scalar,\
69 neon_sat_mul_b, neon_sat_mul_h,\
70 neon_sat_mul_s, neon_sat_mul_h_scalar,\
71 neon_sat_mul_s_scalar,\
72 neon_mul_b_long, neon_mul_h_long,\
74 neon_mul_h_scalar_long, neon_mul_s_scalar_long,\
75 neon_sat_mul_b_long, neon_sat_mul_h_long,\
76 neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\
77 neon_sat_mul_s_scalar_long")
78 (const_string "neon_multiply")
79 (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\
80 neon_mul_h_scalar_q, neon_mul_s_scalar_q,\
81 neon_sat_mul_b_q, neon_sat_mul_h_q,\
82 neon_sat_mul_s_q, neon_sat_mul_h_scalar_q,\
83 neon_sat_mul_s_scalar_q")
84 (const_string "neon_multiply_q")
85 (eq_attr "type" "neon_mla_b, neon_mla_h, neon_mla_s,\
86 neon_mla_h_scalar, neon_mla_s_scalar,\
87 neon_mla_b_long, neon_mla_h_long,\
89 neon_mla_h_scalar_long, neon_mla_s_scalar_long")
90 (const_string "neon_mla")
91 (eq_attr "type" "neon_mla_b_q, neon_mla_h_q, neon_mla_s_q,\
92 neon_mla_h_scalar_q, neon_mla_s_scalar_q")
93 (const_string "neon_mla_q")
94 (eq_attr "type" "neon_sat_mla_b_long, neon_sat_mla_h_long,\
95 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\
96 neon_sat_mla_s_scalar_long")
97 (const_string "neon_sat_mla_long")
99 (eq_attr "type" "neon_shift_acc, neon_shift_acc_q")
100 (const_string "neon_shift_acc")
101 (eq_attr "type" "neon_shift_imm, neon_shift_imm_q,\
102 neon_shift_imm_narrow_q, neon_shift_imm_long")
103 (const_string "neon_shift_imm_basic")
104 (eq_attr "type" "neon_sat_shift_imm, neon_sat_shift_imm_q,\
105 neon_sat_shift_imm_narrow_q")
106 (const_string "neon_shift_imm_complex")
107 (eq_attr "type" "neon_shift_reg")
108 (const_string "neon_shift_reg_basic")
109 (eq_attr "type" "neon_shift_reg_q")
110 (const_string "neon_shift_reg_basic_q")
111 (eq_attr "type" "neon_sat_shift_reg")
112 (const_string "neon_shift_reg_complex")
113 (eq_attr "type" "neon_sat_shift_reg_q")
114 (const_string "neon_shift_reg_complex_q")
116 (eq_attr "type" "neon_fp_neg_s, neon_fp_neg_s_q,\
117 neon_fp_abs_s, neon_fp_abs_s_q")
118 (const_string "neon_fp_negabs")
119 (eq_attr "type" "neon_fp_addsub_s, neon_fp_abd_s,\
120 neon_fp_reduc_add_s, neon_fp_compare_s,\
121 neon_fp_minmax_s, neon_fp_minmax_s_q,\
122 neon_fp_reduc_minmax_s, neon_fp_reduc_minmax_s_q")
123 (const_string "neon_fp_arith")
124 (eq_attr "type" "neon_fp_addsub_s_q, neon_fp_abd_s_q,\
125 neon_fp_reduc_add_s_q, neon_fp_compare_s_q")
126 (const_string "neon_fp_arith_q")
127 (eq_attr "type" "neon_fp_to_int_s, neon_int_to_fp_s")
128 (const_string "neon_fp_cvt_int")
129 (eq_attr "type" "neon_fp_to_int_s_q, neon_int_to_fp_s_q")
130 (const_string "neon_fp_cvt_int_q")
131 (eq_attr "type" "neon_fp_cvt_narrow_s_q, neon_fp_cvt_widen_h")
132 (const_string "neon_fp_cvt16")
133 (eq_attr "type" "neon_fp_mul_s, neon_fp_mul_s_scalar")
134 (const_string "neon_fp_mul")
135 (eq_attr "type" "neon_fp_mul_s_q, neon_fp_mul_s_scalar_q")
136 (const_string "neon_fp_mul_q")
137 (eq_attr "type" "neon_fp_mla_s, neon_fp_mla_s_scalar")
138 (const_string "neon_fp_mla")
139 (eq_attr "type" "neon_fp_mla_s_q, neon_fp_mla_s_scalar_q")
140 (const_string "neon_fp_mla_q")
141 (eq_attr "type" "neon_fp_recpe_s, neon_fp_rsqrte_s")
142 (const_string "neon_fp_recpe_rsqrte")
143 (eq_attr "type" "neon_fp_recpe_s_q, neon_fp_rsqrte_s_q")
144 (const_string "neon_fp_recpe_rsqrte_q")
146 (eq_attr "type" "neon_bsl, neon_cls, neon_cnt,\
147 neon_rev, neon_permute,\
148 neon_tbl1, neon_tbl2, neon_zip,\
149 neon_dup, neon_dup_q, neon_ext, neon_ext_q,\
150 neon_move, neon_move_q, neon_move_narrow_q")
151 (const_string "neon_bitops")
152 (eq_attr "type" "neon_bsl_q, neon_cls_q, neon_cnt_q,\
153 neon_rev_q, neon_permute_q")
154 (const_string "neon_bitops_q")
155 (eq_attr "type" "neon_from_gp")
156 (const_string "neon_from_gp")
157 (eq_attr "type" "neon_from_gp_q")
158 (const_string "neon_from_gp_q")
159 (eq_attr "type" "neon_tbl3, neon_tbl4")
160 (const_string "neon_tbl3_tbl4")
161 (eq_attr "type" "neon_zip_q")
162 (const_string "neon_zip_q")
163 (eq_attr "type" "neon_to_gp, neon_to_gp_q")
164 (const_string "neon_to_gp")
166 (eq_attr "type" "f_loads, f_loadd,\
167 neon_load1_1reg, neon_load1_1reg_q,\
168 neon_load1_2reg, neon_load1_2reg_q")
169 (const_string "neon_load_a")
170 (eq_attr "type" "neon_load1_3reg, neon_load1_3reg_q,\
171 neon_load1_4reg, neon_load1_4reg_q")
172 (const_string "neon_load_b")
173 (eq_attr "type" "neon_load1_one_lane, neon_load1_one_lane_q,\
174 neon_load1_all_lanes, neon_load1_all_lanes_q,\
175 neon_load2_2reg, neon_load2_2reg_q,\
176 neon_load2_all_lanes, neon_load2_all_lanes_q")
177 (const_string "neon_load_c")
178 (eq_attr "type" "neon_load2_4reg, neon_load2_4reg_q,\
179 neon_load3_3reg, neon_load3_3reg_q,\
180 neon_load3_one_lane, neon_load3_one_lane_q,\
181 neon_load4_4reg, neon_load4_4reg_q")
182 (const_string "neon_load_d")
183 (eq_attr "type" "neon_load2_one_lane, neon_load2_one_lane_q,\
184 neon_load3_all_lanes, neon_load3_all_lanes_q,\
185 neon_load4_all_lanes, neon_load4_all_lanes_q")
186 (const_string "neon_load_e")
187 (eq_attr "type" "neon_load4_one_lane, neon_load4_one_lane_q")
188 (const_string "neon_load_f")
190 (eq_attr "type" "f_stores, f_stored,\
191 neon_store1_1reg, neon_store1_1reg_q")
192 (const_string "neon_store_a")
193 (eq_attr "type" "neon_store1_2reg, neon_store1_2reg_q")
194 (const_string "neon_store_b")
195 (eq_attr "type" "neon_store1_3reg, neon_store1_3reg_q")
196 (const_string "neon_store_c")
197 (eq_attr "type" "neon_store1_4reg, neon_store1_4reg_q")
198 (const_string "neon_store_d")
199 (eq_attr "type" "neon_store1_one_lane, neon_store1_one_lane_q,\
200 neon_store2_one_lane, neon_store2_one_lane_q")
201 (const_string "neon_store_e")
202 (eq_attr "type" "neon_store2_2reg, neon_store2_2reg_q,\
203 neon_store3_one_lane, neon_store3_one_lane_q,\
204 neon_store4_one_lane, neon_store4_one_lane_q")
205 (const_string "neon_store_f")
206 (eq_attr "type" "neon_store2_4reg, neon_store2_4reg_q,\
207 neon_store4_4reg, neon_store4_4reg_q")
208 (const_string "neon_store_g")
209 (eq_attr "type" "neon_store3_3reg, neon_store3_3reg_q")
210 (const_string "neon_store_h")]
211 (const_string "unknown")))
213 (define_automaton "cortex_a15_neon")
216 (define_cpu_unit "ca15_cx_ij, ca15_cx_ik" "cortex_a15_neon")
219 (define_cpu_unit "ca15_cx_acc" "cortex_a15_neon")
221 ;; The 32x32 integer multiply-accumulate pipeline.
222 (define_cpu_unit "ca15_cx_imac1" "cortex_a15_neon")
223 (define_reservation "ca15_cx_imac" "(ca15_cx_ij+ca15_cx_imac1)")
226 ;; The 64-bit ALU pipeline.
227 (define_cpu_unit "ca15_cx_ialu1, ca15_cx_ialu2" "cortex_a15_neon")
229 ;; IALU with accumulate.
230 (define_reservation "ca15_cx_ialu_with_acc" "ca15_cx_ik+ca15_cx_ialu2+ca15_cx_acc")
232 (define_reservation "ca15_cx_ialu"
233 "((ca15_cx_ij+ca15_cx_ialu1)|(ca15_cx_ik+ca15_cx_ialu2))")
235 ;; Integer shift pipeline.
236 (define_cpu_unit "ca15_cx_ishf" "cortex_a15_neon")
237 (define_reservation "ca15_cx_ishf_with_acc" "ca15_cx_ik+ca15_cx_ishf+ca15_cx_acc")
239 ;; SIMD multiply pipeline.
240 (define_cpu_unit "ca15_cx_fmul1, ca15_cx_fmul2, ca15_cx_fmul3, ca15_cx_fmul4"
243 (define_reservation "ca15_cx_fmul"
244 "(ca15_cx_ij+(ca15_cx_fmul1|ca15_cx_fmul2))|\
245 (ca15_cx_ik+(ca15_cx_fmul3|ca15_cx_fmul4))")
247 (define_reservation "ca15_cx_fmul_2"
248 "(ca15_cx_ij+(ca15_cx_fmul1|ca15_cx_fmul2))+\
249 (ca15_cx_ik+(ca15_cx_fmul3|ca15_cx_fmul4))")
251 ;; SIMD ALU pipeline.
252 (define_cpu_unit "ca15_cx_falu1, ca15_cx_falu2, ca15_cx_falu3, ca15_cx_falu4"
255 (define_reservation "ca15_cx_falu"
256 "(ca15_cx_ij+(ca15_cx_falu1|ca15_cx_falu2))|\
257 (ca15_cx_ik+(ca15_cx_falu3|ca15_cx_falu4))")
259 (define_reservation "ca15_cx_falu_2"
260 "(ca15_cx_ij+(ca15_cx_falu1|ca15_cx_falu2))+\
261 (ca15_cx_ik+(ca15_cx_falu3|ca15_cx_falu4))")
263 ;; SIMD multiply-accumulate pipeline.
264 ;; This can be used if fmul and falu are not reserved.
265 (define_reservation "ca15_cx_fmac"
266 "((ca15_cx_ij+ca15_cx_fmul1),nothing*2,ca15_cx_falu1)|\
267 ((ca15_cx_ij+ca15_cx_fmul2),nothing*2,ca15_cx_falu2)|\
268 ((ca15_cx_ik+ca15_cx_fmul3),nothing*2,ca15_cx_falu3)|\
269 ((ca15_cx_ik+ca15_cx_fmul4),nothing*2,ca15_cx_falu4)")
271 (define_reservation "ca15_cx_fmac_2"
272 "(((ca15_cx_ij+ca15_cx_fmul1),nothing*2,ca15_cx_falu1)|\
273 ((ca15_cx_ij+ca15_cx_fmul2),nothing*2,ca15_cx_falu2))+\
274 (((ca15_cx_ik+ca15_cx_fmul3),nothing*2,ca15_cx_falu3)|\
275 ((ca15_cx_ik+ca15_cx_fmul4),nothing*2,ca15_cx_falu4))")
278 ;; Vector FP multiply pipeline
279 (define_cpu_unit "ca15_cx_vfp_i" "cortex_a15_neon")
281 (define_reservation "ca15_cx_vfp" "ca15_cx_ik+ca15_cx_vfp_i")
283 ;; Load permute pipeline
284 (define_reservation "ca15_cx_perm" "ca15_cx_ij|ca15_cx_ik")
285 (define_reservation "ca15_cx_perm_2" "ca15_cx_ij+ca15_cx_ik")
287 ;; Integer Arithmetic Instructions.
289 (define_insn_reservation "cortex_a15_neon_abd" 5
290 (and (eq_attr "tune" "cortexa15")
291 (eq_attr "cortex_a15_neon_type" "neon_abd"))
292 "ca15_issue1,ca15_cx_ialu")
294 (define_insn_reservation "cortex_a15_neon_abd_q" 5
295 (and (eq_attr "tune" "cortexa15")
296 (eq_attr "cortex_a15_neon_type" "neon_abd_q"))
297 "ca15_issue2,ca15_cx_ialu*2")
299 (define_insn_reservation "cortex_a15_neon_aba" 7
300 (and (eq_attr "tune" "cortexa15")
301 (eq_attr "cortex_a15_neon_type" "neon_arith_acc"))
302 "ca15_issue1,ca15_cx_ialu_with_acc")
304 (define_insn_reservation "cortex_a15_neon_aba_q" 8
305 (and (eq_attr "tune" "cortexa15")
306 (eq_attr "cortex_a15_neon_type" "neon_arith_acc_q"))
307 "ca15_issue2,ca15_cx_ialu_with_acc*2")
309 (define_insn_reservation "cortex_a15_neon_arith_basic" 4
310 (and (eq_attr "tune" "cortexa15")
311 (eq_attr "cortex_a15_neon_type" "neon_arith_basic"))
312 "ca15_issue1,ca15_cx_ialu")
314 (define_insn_reservation "cortex_a15_neon_arith_complex" 5
315 (and (eq_attr "tune" "cortexa15")
316 (eq_attr "cortex_a15_neon_type" "neon_arith_complex"))
317 "ca15_issue1,ca15_cx_ialu")
319 ;; Integer Multiply Instructions.
321 (define_insn_reservation "cortex_a15_neon_multiply" 6
322 (and (eq_attr "tune" "cortexa15")
323 (eq_attr "cortex_a15_neon_type" "neon_multiply"))
324 "ca15_issue1,ca15_cx_imac")
326 (define_insn_reservation "cortex_a15_neon_multiply_q" 7
327 (and (eq_attr "tune" "cortexa15")
328 (eq_attr "cortex_a15_neon_type" "neon_multiply_q"))
329 "ca15_issue2,ca15_cx_imac*2")
331 (define_insn_reservation "cortex_a15_neon_mla" 6
332 (and (eq_attr "tune" "cortexa15")
333 (eq_attr "cortex_a15_neon_type" "neon_mla"))
334 "ca15_issue1,ca15_cx_imac")
336 (define_insn_reservation "cortex_a15_neon_mla_q" 7
337 (and (eq_attr "tune" "cortexa15")
338 (eq_attr "cortex_a15_neon_type" "neon_mla_q"))
339 "ca15_issue1,ca15_cx_imac*2")
341 (define_insn_reservation "cortex_a15_neon_sat_mla_long" 6
342 (and (eq_attr "tune" "cortexa15")
343 (eq_attr "cortex_a15_neon_type" "neon_sat_mla_long"))
344 "ca15_issue1,ca15_cx_imac")
346 ;; Integer Shift Instructions.
348 (define_insn_reservation
349 "cortex_a15_neon_shift_acc" 7
350 (and (eq_attr "tune" "cortexa15")
351 (eq_attr "cortex_a15_neon_type" "neon_shift_acc"))
352 "ca15_issue1,ca15_cx_ishf_with_acc")
354 (define_insn_reservation
355 "cortex_a15_neon_shift_imm_basic" 4
356 (and (eq_attr "tune" "cortexa15")
357 (eq_attr "cortex_a15_neon_type" "neon_shift_imm_basic"))
358 "ca15_issue1,ca15_cx_ik+ca15_cx_ishf")
360 (define_insn_reservation
361 "cortex_a15_neon_shift_imm_complex" 5
362 (and (eq_attr "tune" "cortexa15")
363 (eq_attr "cortex_a15_neon_type" "neon_shift_imm_complex"))
364 "ca15_issue1,ca15_cx_ik+ca15_cx_ishf")
366 (define_insn_reservation
367 "cortex_a15_neon_shift_reg_basic" 4
368 (and (eq_attr "tune" "cortexa15")
369 (eq_attr "cortex_a15_neon_type" "neon_shift_reg_basic"))
370 "ca15_issue1,ca15_cx_ik+ca15_cx_ishf")
372 (define_insn_reservation
373 "cortex_a15_neon_shift_reg_basic_q" 5
374 (and (eq_attr "tune" "cortexa15")
375 (eq_attr "cortex_a15_neon_type" "neon_shift_reg_basic_q"))
376 "ca15_issue2,(ca15_cx_ik+ca15_cx_ishf*2)")
378 (define_insn_reservation
379 "cortex_a15_neon_shift_reg_complex" 5
380 (and (eq_attr "tune" "cortexa15")
381 (eq_attr "cortex_a15_neon_type" "neon_shift_reg_complex"))
382 "ca15_issue2,ca15_cx_ik+ca15_cx_ishf")
384 (define_insn_reservation
385 "cortex_a15_neon_shift_reg_complex_q" 6
386 (and (eq_attr "tune" "cortexa15")
387 (eq_attr "cortex_a15_neon_type" "neon_shift_reg_complex_q"))
388 "ca15_issue2,(ca15_cx_ik+ca15_cx_ishf)*2")
390 ;; Floating Point Instructions.
392 (define_insn_reservation
393 "cortex_a15_neon_fp_negabs" 4
394 (and (eq_attr "tune" "cortexa15")
395 (eq_attr "cortex_a15_neon_type" "neon_fp_negabs"))
396 "ca15_issue1,ca15_cx_falu")
398 (define_insn_reservation
399 "cortex_a15_neon_fp_arith" 6
400 (and (eq_attr "tune" "cortexa15")
401 (eq_attr "cortex_a15_neon_type" "neon_fp_arith"))
402 "ca15_issue1,ca15_cx_falu")
404 (define_insn_reservation
405 "cortex_a15_neon_fp_arith_q" 6
406 (and (eq_attr "tune" "cortexa15")
407 (eq_attr "cortex_a15_neon_type" "neon_fp_arith_q"))
408 "ca15_issue2,ca15_cx_falu_2")
410 (define_insn_reservation
411 "cortex_a15_neon_fp_cvt_int" 6
412 (and (eq_attr "tune" "cortexa15")
413 (eq_attr "cortex_a15_neon_type" "neon_fp_cvt_int"))
414 "ca15_issue1,ca15_cx_falu+ca15_cx_ishf")
416 (define_insn_reservation
417 "cortex_a15_neon_fp_cvt_int_q" 6
418 (and (eq_attr "tune" "cortexa15")
419 (eq_attr "cortex_a15_neon_type" "neon_fp_cvt_int_q"))
420 "ca15_issue2,(ca15_cx_falu+ca15_cx_ishf)*2")
422 (define_insn_reservation
423 "cortex_a15_neon_fp_cvt16" 10
424 (and (eq_attr "tune" "cortexa15")
425 (eq_attr "cortex_a15_neon_type" "neon_fp_cvt16"))
426 "ca15_issue3,(ca15_cx_falu+ca15_cx_ishf)*2+ca15_cx_falu")
428 (define_insn_reservation
429 "cortex_a15_neon_fp_mul" 5
430 (and (eq_attr "tune" "cortexa15")
431 (eq_attr "cortex_a15_neon_type" "neon_fp_mul"))
432 "ca15_issue1,ca15_cx_fmul")
434 (define_insn_reservation
435 "cortex_a15_neon_fp_mul_q" 5
436 (and (eq_attr "tune" "cortexa15")
437 (eq_attr "cortex_a15_neon_type" "neon_fp_mul_q"))
438 "ca15_issue2,ca15_cx_fmul_2")
440 (define_insn_reservation
441 "cortex_a15_neon_fp_mla" 9
442 (and (eq_attr "tune" "cortexa15")
443 (eq_attr "cortex_a15_neon_type" "neon_fp_mla"))
444 "ca15_issue1,ca15_cx_fmul")
446 (define_insn_reservation
447 "cortex_a15_neon_fp_mla_q" 9
448 (and (eq_attr "tune" "cortexa15")
449 (eq_attr "cortex_a15_neon_type" "neon_fp_mla_q"))
450 "ca15_issue2,ca15_cx_fmul_2")
452 (define_insn_reservation
453 "cortex_a15_neon_fp_recps_rsqrte" 9
454 (and (eq_attr "tune" "cortexa15")
455 (eq_attr "cortex_a15_neon_type" "neon_fp_recpe_rsqrte"))
456 "ca15_issue1,ca15_cx_fmac")
458 (define_insn_reservation
459 "cortex_a15_neon_fp_recps_rsqrte_q" 9
460 (and (eq_attr "tune" "cortexa15")
461 (eq_attr "cortex_a15_neon_type" "neon_fp_recpe_rsqrte_q"))
462 "ca15_issue2,ca15_cx_fmac_2")
464 ;; Miscelaaneous Instructions.
466 (define_insn_reservation
467 "cortex_a15_neon_bitops" 4
468 (and (eq_attr "tune" "cortexa15")
469 (eq_attr "cortex_a15_neon_type" "neon_bitops"))
470 "ca15_issue1,ca15_cx_perm")
472 (define_insn_reservation
473 "cortex_a15_neon_bitops_q" 4
474 (and (eq_attr "tune" "cortexa15")
475 (eq_attr "cortex_a15_neon_type" "neon_bitops_q"))
476 "ca15_issue2,ca15_cx_perm_2")
478 (define_insn_reservation
479 "cortex_a15_neon_from_gp" 9
480 (and (eq_attr "tune" "cortexa15")
481 (eq_attr "cortex_a15_neon_type" "neon_from_gp"))
482 "ca15_issue2,ca15_ls1+ca15_ls2+ca15_cx_perm")
484 (define_insn_reservation
485 "cortex_a15_neon_from_gp_q" 9
486 (and (eq_attr "tune" "cortexa15")
487 (eq_attr "cortex_a15_neon_type" "neon_from_gp_q"))
488 "ca15_issue2,ca15_ls1+ca15_ls2+ca15_cx_perm_2")
490 (define_insn_reservation
491 "cortex_a15_neon_tbl3_tbl4" 7
492 (and (eq_attr "tune" "cortexa15")
493 (eq_attr "cortex_a15_neon_type" "neon_tbl3_tbl4"))
494 "ca15_issue2,ca15_cx_perm_2")
496 (define_insn_reservation
497 "cortex_a15_neon_zip_q" 7
498 (and (eq_attr "tune" "cortexa15")
499 (eq_attr "cortex_a15_neon_type" "neon_zip_q"))
500 "ca15_issue3,ca15_cx_perm*3")
502 (define_insn_reservation
503 "cortex_a15_neon_to_gp" 7
504 (and (eq_attr "tune" "cortexa15")
505 (eq_attr "cortex_a15_neon_type" "neon_to_gp"))
506 "ca15_issue2,ca15_ls1+ca15_ls2")
508 ;; Load Instructions.
510 (define_insn_reservation
511 "cortex_a15_neon_load_a" 6
512 (and (eq_attr "tune" "cortexa15")
513 (eq_attr "cortex_a15_neon_type" "neon_load_a"))
514 "ca15_issue1,ca15_ls,ca15_ldr")
516 (define_insn_reservation
517 "cortex_a15_neon_load_b" 7
518 (and (eq_attr "tune" "cortexa15")
519 (eq_attr "cortex_a15_neon_type" "neon_load_b"))
520 "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr")
522 (define_insn_reservation
523 "cortex_a15_neon_load_c" 9
524 (and (eq_attr "tune" "cortexa15")
525 (eq_attr "cortex_a15_neon_type" "neon_load_c"))
526 "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr")
528 (define_insn_reservation
529 "cortex_a15_neon_load_d" 11
530 (and (eq_attr "tune" "cortexa15")
531 (eq_attr "cortex_a15_neon_type" "neon_load_d"))
532 "ca15_issue1,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2")
534 (define_insn_reservation
535 "cortex_a15_neon_load_e" 9
536 (and (eq_attr "tune" "cortexa15")
537 (eq_attr "cortex_a15_neon_type" "neon_load_e"))
538 "ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2")
540 (define_insn_reservation
541 "cortex_a15_neon_load_f" 11
542 (and (eq_attr "tune" "cortexa15")
543 (eq_attr "cortex_a15_neon_type" "neon_load_f"))
544 "ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2")
546 ;; Store Instructions.
548 (define_insn_reservation
549 "cortex_a15_neon_store_a" 0
550 (and (eq_attr "tune" "cortexa15")
551 (eq_attr "cortex_a15_neon_type" "neon_store_a"))
552 "ca15_issue1,ca15_ls1+ca15_ls2,ca15_str")
554 (define_insn_reservation
555 "cortex_a15_neon_store_b" 0
556 (and (eq_attr "tune" "cortexa15")
557 (eq_attr "cortex_a15_neon_type" "neon_store_b"))
558 "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str*2")
560 (define_insn_reservation
561 "cortex_a15_neon_store_c" 0
562 (and (eq_attr "tune" "cortexa15")
563 (eq_attr "cortex_a15_neon_type" "neon_store_c"))
564 "ca15_issue3,ca15_ls1+ca15_ls2,ca15_str*3")
566 (define_insn_reservation
567 "cortex_a15_neon_store_d" 0
568 (and (eq_attr "tune" "cortexa15")
569 (eq_attr "cortex_a15_neon_type" "neon_store_d"))
570 "ca15_issue3,ca15_issue1,ca15_ls1+ca15_ls2,ca15_str*4")
572 (define_insn_reservation
573 "cortex_a15_neon_store_e" 0
574 (and (eq_attr "tune" "cortexa15")
575 (eq_attr "cortex_a15_neon_type" "neon_store_e"))
576 "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str+ca15_cx_perm")
578 (define_insn_reservation
579 "cortex_a15_neon_store_f" 0
580 (and (eq_attr "tune" "cortexa15")
581 (eq_attr "cortex_a15_neon_type" "neon_store_f"))
582 "ca15_issue3,ca15_ls1+ca15_ls2,ca15_str*2+ca15_cx_perm")
584 (define_insn_reservation
585 "cortex_a15_neon_store_g" 0
586 (and (eq_attr "tune" "cortexa15")
587 (eq_attr "cortex_a15_neon_type" "neon_store_g"))
588 "ca15_issue3,ca15_issue3+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2")
590 (define_insn_reservation
591 "cortex_a15_neon_store_h" 0
592 (and (eq_attr "tune" "cortexa15")
593 (eq_attr "cortex_a15_neon_type" "neon_store_h"))
594 "ca15_issue3,ca15_issue2+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2")
598 (define_insn_reservation "cortex_a15_vfp_const" 4
599 (and (eq_attr "tune" "cortexa15")
600 (eq_attr "type" "fconsts,fconstd"))
601 "ca15_issue1,ca15_cx_perm")
603 (define_insn_reservation "cortex_a15_vfp_adds_subs" 6
604 (and (eq_attr "tune" "cortexa15")
605 (eq_attr "type" "fadds"))
606 "ca15_issue1,ca15_cx_vfp")
608 (define_insn_reservation "cortex_a15_vfp_addd_subd" 10
609 (and (eq_attr "tune" "cortexa15")
610 (eq_attr "type" "faddd"))
611 "ca15_issue2,ca15_cx_vfp*2")
613 (define_insn_reservation "cortex_a15_vfp_muls" 7
614 (and (eq_attr "tune" "cortexa15")
615 (eq_attr "type" "fmuls"))
616 "ca15_issue1,ca15_cx_vfp")
618 (define_insn_reservation "cortex_a15_vfp_muld" 12
619 (and (eq_attr "tune" "cortexa15")
620 (eq_attr "type" "fmuld"))
621 "ca15_issue2,ca15_cx_vfp*2")
623 (define_insn_reservation "cortex_a15_vfp_macs" 6
624 (and (eq_attr "tune" "cortexa15")
625 (eq_attr "type" "fmacs,ffmas"))
626 "ca15_issue1,ca15_cx_vfp")
628 (define_insn_reservation "cortex_a15_vfp_macd" 11
629 (and (eq_attr "tune" "cortexa15")
630 (eq_attr "type" "fmacd,ffmad"))
631 "ca15_issue2,ca15_cx_vfp*2")
633 (define_insn_reservation "cortex_a15_vfp_cvt" 6
634 (and (eq_attr "tune" "cortexa15")
635 (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
636 "ca15_issue1,ca15_cx_vfp")
638 (define_insn_reservation "cortex_a15_vfp_cmpd" 8
639 (and (eq_attr "tune" "cortexa15")
640 (eq_attr "type" "fcmpd"))
641 "ca15_issue2,ca15_cx_perm,ca15_cx_vfp")
643 (define_insn_reservation "cortex_a15_vfp_cmps" 8
644 (and (eq_attr "tune" "cortexa15")
645 (eq_attr "type" "fcmps"))
646 "ca15_issue2,ca15_cx_perm,ca15_cx_vfp")
648 (define_insn_reservation "cortex_a15_vfp_arithd" 7
649 (and (eq_attr "tune" "cortexa15")
650 (eq_attr "type" "ffarithd"))
651 "ca15_issue2,ca15_cx_perm*2")
653 (define_insn_reservation "cortex_a15_vfp_cpys" 4
654 (and (eq_attr "tune" "cortexa15")
655 (eq_attr "type" "fmov"))
656 "ca15_issue1,ca15_cx_perm")
658 (define_insn_reservation "cortex_a15_gp_to_vfp" 5
659 (and (eq_attr "tune" "cortexa15")
660 (eq_attr "type" "f_mcr, f_mcrr"))
661 "ca15_issue1,ca15_ls")
663 (define_insn_reservation "cortex_a15_mov_vfp_to_gp" 5
664 (and (eq_attr "tune" "cortexa15")
665 (eq_attr "type" "f_mrc, f_mrrc"))
666 "ca15_issue1,ca15_ls")
668 ;; Moves from floating point registers to general purpose registers
669 ;; induce additional latency.
670 (define_bypass 10 "cortex_a15_vfp*, cortex_a15_neon*, cortex_a15_gp_to_vfp" "cortex_a15_mov_vfp_to_gp")
673 (define_insn_reservation "cortex_a15_vfp_ariths" 7
674 (and (eq_attr "tune" "cortexa15")
675 (eq_attr "type" "ffariths"))
676 "ca15_issue1,ca15_cx_perm")
678 (define_insn_reservation "cortex_a15_vfp_divs" 10
679 (and (eq_attr "tune" "cortexa15")
680 (eq_attr "type" "fdivs, fsqrts"))
681 "ca15_issue1,ca15_cx_ik")
683 (define_insn_reservation "cortex_a15_vfp_divd" 18
684 (and (eq_attr "tune" "cortexa15")
685 (eq_attr "type" "fdivd, fsqrtd"))
686 "ca15_issue1,ca15_cx_ik")