1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 typedef struct reg_stat_struct
{
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
254 DEF_VEC_O(reg_stat_type
);
255 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
257 static VEC(reg_stat_type
,heap
) *reg_stat
;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set
;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid
;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn
;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid
;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs
;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn
;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block
;
299 static bool optimize_this_for_speed_p
;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known
;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost
;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx
*uid_log_links
;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick
;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start
;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode
;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid
;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
350 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
351 union { rtx
*r
; int *i
; } where
;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf
;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences
;
374 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
376 unsigned HOST_WIDE_INT
,
377 unsigned HOST_WIDE_INT
*);
378 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx
*, rtx
);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx
);
385 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
386 static int cant_combine_insn_p (rtx
);
387 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
388 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
389 static int contains_muldiv (rtx
);
390 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx
*find_split_point (rtx
*, rtx
, bool);
394 static rtx
subst (rtx
, rtx
, rtx
, int, int);
395 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
396 static rtx
simplify_if_then_else (rtx
);
397 static rtx
simplify_set (rtx
);
398 static rtx
simplify_logical (rtx
);
399 static rtx
expand_compound_operation (rtx
);
400 static const_rtx
expand_field_assignment (const_rtx
);
401 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
402 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
403 static rtx
extract_left_shift (rtx
, int);
404 static rtx
make_compound_operation (rtx
, enum rtx_code
);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
406 unsigned HOST_WIDE_INT
*);
407 static rtx
canon_reg_for_combine (rtx
, rtx
);
408 static rtx
force_to_mode (rtx
, enum machine_mode
,
409 unsigned HOST_WIDE_INT
, int);
410 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
411 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
412 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
413 static rtx
make_field_assignment (rtx
);
414 static rtx
apply_distributive_law (rtx
);
415 static rtx
distribute_and_simplify_rtx (rtx
, int);
416 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
417 unsigned HOST_WIDE_INT
);
418 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
419 unsigned HOST_WIDE_INT
);
420 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
421 HOST_WIDE_INT
, enum machine_mode
, int *);
422 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
423 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
425 static int recog_for_combine (rtx
*, rtx
, rtx
*);
426 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
427 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
428 static void update_table_tick (rtx
);
429 static void record_value_for_reg (rtx
, rtx
, rtx
);
430 static void check_promoted_subreg (rtx
, rtx
);
431 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
432 static void record_dead_and_set_regs (rtx
);
433 static int get_last_value_validate (rtx
*, rtx
, int, int);
434 static rtx
get_last_value (const_rtx
);
435 static int use_crosses_set_p (const_rtx
, int);
436 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
437 static int reg_dead_at_p (rtx
, rtx
);
438 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
439 static int reg_bitfield_target_p (rtx
, rtx
);
440 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
441 static void distribute_links (rtx
);
442 static void mark_used_regs_combine (rtx
);
443 static void record_promoted_value (rtx
, rtx
);
444 static int unmentioned_reg_p_1 (rtx
*, void *);
445 static bool unmentioned_reg_p (rtx
, rtx
);
446 static int record_truncated_value (rtx
*, void *);
447 static void record_truncated_values (rtx
*, void *);
448 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
449 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern
, rtx insn
)
485 ret
= split_insns (pattern
, insn
);
486 nregs
= max_reg_num ();
487 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
488 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest
, rtx
*loc
)
502 enum rtx_code code
= GET_CODE (x
);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x
)) != CC0
525 && GET_CODE (SET_DEST (x
)) != PC
526 && !REG_P (SET_DEST (x
))
527 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x
)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
530 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
532 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
535 return find_single_use_1 (dest
, &SET_SRC (x
));
539 return find_single_use_1 (dest
, &XEXP (x
, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt
= GET_RTX_FORMAT (code
);
549 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
553 if (dest
== XEXP (x
, i
)
554 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
555 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
558 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
561 result
= this_result
;
562 else if (this_result
)
563 /* Duplicate usage. */
566 else if (fmt
[i
] == 'E')
570 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
572 if (XVECEXP (x
, i
, j
) == dest
574 && REG_P (XVECEXP (x
, i
, j
))
575 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
578 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
581 result
= this_result
;
582 else if (this_result
)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
617 next
= NEXT_INSN (insn
);
619 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
622 result
= find_single_use_1 (dest
, &PATTERN (next
));
632 bb
= BLOCK_FOR_INSN (insn
);
633 for (next
= NEXT_INSN (insn
);
634 next
&& BLOCK_FOR_INSN (next
) == bb
;
635 next
= NEXT_INSN (next
))
636 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
638 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
639 if (XEXP (link
, 0) == insn
)
644 result
= find_single_use_1 (dest
, &PATTERN (next
));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx
*into
, rtx newval
)
666 if (oldval
== newval
)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
674 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
675 && CONST_INT_P (newval
))
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
679 gcc_assert (INTVAL (newval
)
680 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
688 gcc_assert (!(GET_CODE (oldval
) == SUBREG
689 && CONST_INT_P (SUBREG_REG (oldval
))));
690 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
691 && CONST_INT_P (XEXP (oldval
, 0))));
695 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
697 buf
= XNEW (struct undo
);
699 buf
->kind
= UNDO_RTX
;
701 buf
->old_contents
.r
= oldval
;
704 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
714 do_SUBST_INT (int *into
, int newval
)
719 if (oldval
== newval
)
723 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
725 buf
= XNEW (struct undo
);
727 buf
->kind
= UNDO_INT
;
729 buf
->old_contents
.i
= oldval
;
732 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
743 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
746 enum machine_mode oldval
= GET_MODE (*into
);
748 if (oldval
== newval
)
752 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
754 buf
= XNEW (struct undo
);
756 buf
->kind
= UNDO_MODE
;
758 buf
->old_contents
.m
= oldval
;
759 adjust_reg_mode (*into
, newval
);
761 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
776 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
777 rtx newi2pat
, rtx newotherpat
)
779 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
780 int new_i2_cost
, new_i3_cost
;
781 int old_cost
, new_cost
;
783 /* Lookup the original insn_rtx_costs. */
784 i2_cost
= INSN_COST (i2
);
785 i3_cost
= INSN_COST (i3
);
789 i1_cost
= INSN_COST (i1
);
792 i0_cost
= INSN_COST (i0
);
793 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
794 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
798 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
799 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
805 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
806 i1_cost
= i0_cost
= 0;
809 /* Calculate the replacement insn_rtx_costs. */
810 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
813 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
814 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
815 ? new_i2_cost
+ new_i3_cost
: 0;
819 new_cost
= new_i3_cost
;
823 if (undobuf
.other_insn
)
825 int old_other_cost
, new_other_cost
;
827 old_other_cost
= INSN_COST (undobuf
.other_insn
);
828 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
829 if (old_other_cost
> 0 && new_other_cost
> 0)
831 old_cost
+= old_other_cost
;
832 new_cost
+= new_other_cost
;
838 /* Disallow this recombination if both new_cost and old_cost are
839 greater than zero, and new_cost is greater than old cost. */
841 && new_cost
> old_cost
)
848 "rejecting combination of insns %d, %d, %d and %d\n",
849 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
851 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
852 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
857 "rejecting combination of insns %d, %d and %d\n",
858 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
859 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
860 i1_cost
, i2_cost
, i3_cost
, old_cost
);
865 "rejecting combination of insns %d and %d\n",
866 INSN_UID (i2
), INSN_UID (i3
));
867 fprintf (dump_file
, "original costs %d + %d = %d\n",
868 i2_cost
, i3_cost
, old_cost
);
873 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
874 new_i2_cost
, new_i3_cost
, new_cost
);
877 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
883 /* Update the uid_insn_cost array with the replacement costs. */
884 INSN_COST (i2
) = new_i2_cost
;
885 INSN_COST (i3
) = new_i3_cost
;
893 /* Delete any insns that copy a register to itself. */
896 delete_noop_moves (void)
903 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
905 next
= NEXT_INSN (insn
);
906 if (INSN_P (insn
) && noop_move_p (insn
))
909 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
911 delete_insn_and_edges (insn
);
918 /* Fill in log links field for all insns. */
921 create_log_links (void)
925 df_ref
*def_vec
, *use_vec
;
927 next_use
= XCNEWVEC (rtx
, max_reg_num ());
929 /* Pass through each block from the end, recording the uses of each
930 register and establishing log links when def is encountered.
931 Note that we do not clear next_use array in order to save time,
932 so we have to test whether the use is in the same basic block as def.
934 There are a few cases below when we do not consider the definition or
935 usage -- these are taken from original flow.c did. Don't ask me why it is
936 done this way; I don't know and if it works, I don't want to know. */
940 FOR_BB_INSNS_REVERSE (bb
, insn
)
942 if (!NONDEBUG_INSN_P (insn
))
945 /* Log links are created only once. */
946 gcc_assert (!LOG_LINKS (insn
));
948 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
950 df_ref def
= *def_vec
;
951 int regno
= DF_REF_REGNO (def
);
954 if (!next_use
[regno
])
957 /* Do not consider if it is pre/post modification in MEM. */
958 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
961 /* Do not make the log link for frame pointer. */
962 if ((regno
== FRAME_POINTER_REGNUM
963 && (! reload_completed
|| frame_pointer_needed
))
964 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
965 || (regno
== HARD_FRAME_POINTER_REGNUM
966 && (! reload_completed
|| frame_pointer_needed
))
968 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
969 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
974 use_insn
= next_use
[regno
];
975 if (BLOCK_FOR_INSN (use_insn
) == bb
)
979 We don't build a LOG_LINK for hard registers contained
980 in ASM_OPERANDs. If these registers get replaced,
981 we might wind up changing the semantics of the insn,
982 even if reload can make what appear to be valid
983 assignments later. */
984 if (regno
>= FIRST_PSEUDO_REGISTER
985 || asm_noperands (PATTERN (use_insn
)) < 0)
987 /* Don't add duplicate links between instructions. */
989 for (links
= LOG_LINKS (use_insn
); links
;
990 links
= XEXP (links
, 1))
991 if (insn
== XEXP (links
, 0))
995 LOG_LINKS (use_insn
) =
996 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
999 next_use
[regno
] = NULL_RTX
;
1002 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1004 df_ref use
= *use_vec
;
1005 int regno
= DF_REF_REGNO (use
);
1007 /* Do not consider the usage of the stack pointer
1008 by function call. */
1009 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1012 next_use
[regno
] = insn
;
1020 /* Clear LOG_LINKS fields of insns. */
1023 clear_log_links (void)
1027 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1029 free_INSN_LIST_list (&LOG_LINKS (insn
));
1032 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1033 true if we found a LOG_LINK that proves that A feeds B. This only works
1034 if there are no instructions between A and B which could have a link
1035 depending on A, since in that case we would not record a link for B.
1036 We also check the implicit dependency created by a cc0 setter/user
1040 insn_a_feeds_b (rtx a
, rtx b
)
1043 for (links
= LOG_LINKS (b
); links
; links
= XEXP (links
, 1))
1044 if (XEXP (links
, 0) == a
)
1053 /* Main entry point for combiner. F is the first insn of the function.
1054 NREGS is the first unused pseudo-reg number.
1056 Return nonzero if the combiner has turned an indirect jump
1057 instruction into a direct jump. */
1059 combine_instructions (rtx f
, unsigned int nregs
)
1065 rtx links
, nextlinks
;
1067 basic_block last_bb
;
1069 int new_direct_jump_p
= 0;
1071 for (first
= f
; first
&& !INSN_P (first
); )
1072 first
= NEXT_INSN (first
);
1076 combine_attempts
= 0;
1079 combine_successes
= 0;
1081 rtl_hooks
= combine_rtl_hooks
;
1083 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1085 init_recog_no_volatile ();
1087 /* Allocate array for insn info. */
1088 max_uid_known
= get_max_uid ();
1089 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1090 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1092 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1094 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1095 problems when, for example, we have j <<= 1 in a loop. */
1097 nonzero_sign_valid
= 0;
1098 label_tick
= label_tick_ebb_start
= 1;
1100 /* Scan all SETs and see if we can deduce anything about what
1101 bits are known to be zero for some registers and how many copies
1102 of the sign bit are known to exist for those registers.
1104 Also set any known values so that we can use it while searching
1105 for what bits are known to be set. */
1107 setup_incoming_promotions (first
);
1108 /* Allow the entry block and the first block to fall into the same EBB.
1109 Conceptually the incoming promotions are assigned to the entry block. */
1110 last_bb
= ENTRY_BLOCK_PTR
;
1112 create_log_links ();
1113 FOR_EACH_BB (this_basic_block
)
1115 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1120 if (!single_pred_p (this_basic_block
)
1121 || single_pred (this_basic_block
) != last_bb
)
1122 label_tick_ebb_start
= label_tick
;
1123 last_bb
= this_basic_block
;
1125 FOR_BB_INSNS (this_basic_block
, insn
)
1126 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1128 subst_low_luid
= DF_INSN_LUID (insn
);
1131 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1133 record_dead_and_set_regs (insn
);
1136 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1137 if (REG_NOTE_KIND (links
) == REG_INC
)
1138 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1142 /* Record the current insn_rtx_cost of this instruction. */
1143 if (NONJUMP_INSN_P (insn
))
1144 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1145 optimize_this_for_speed_p
);
1147 fprintf(dump_file
, "insn_cost %d: %d\n",
1148 INSN_UID (insn
), INSN_COST (insn
));
1152 nonzero_sign_valid
= 1;
1154 /* Now scan all the insns in forward order. */
1155 label_tick
= label_tick_ebb_start
= 1;
1157 setup_incoming_promotions (first
);
1158 last_bb
= ENTRY_BLOCK_PTR
;
1160 FOR_EACH_BB (this_basic_block
)
1162 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1167 if (!single_pred_p (this_basic_block
)
1168 || single_pred (this_basic_block
) != last_bb
)
1169 label_tick_ebb_start
= label_tick
;
1170 last_bb
= this_basic_block
;
1172 rtl_profile_for_bb (this_basic_block
);
1173 for (insn
= BB_HEAD (this_basic_block
);
1174 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1175 insn
= next
? next
: NEXT_INSN (insn
))
1178 if (NONDEBUG_INSN_P (insn
))
1180 /* See if we know about function return values before this
1181 insn based upon SUBREG flags. */
1182 check_promoted_subreg (insn
, PATTERN (insn
));
1184 /* See if we can find hardregs and subreg of pseudos in
1185 narrower modes. This could help turning TRUNCATEs
1187 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1189 /* Try this insn with each insn it links back to. */
1191 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1192 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
,
1193 NULL_RTX
, &new_direct_jump_p
)) != 0)
1196 /* Try each sequence of three linked insns ending with this one. */
1198 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1200 rtx link
= XEXP (links
, 0);
1202 /* If the linked insn has been replaced by a note, then there
1203 is no point in pursuing this chain any further. */
1207 for (nextlinks
= LOG_LINKS (link
);
1209 nextlinks
= XEXP (nextlinks
, 1))
1210 if ((next
= try_combine (insn
, link
, XEXP (nextlinks
, 0),
1212 &new_direct_jump_p
)) != 0)
1217 /* Try to combine a jump insn that uses CC0
1218 with a preceding insn that sets CC0, and maybe with its
1219 logical predecessor as well.
1220 This is how we make decrement-and-branch insns.
1221 We need this special code because data flow connections
1222 via CC0 do not get entered in LOG_LINKS. */
1225 && (prev
= prev_nonnote_insn (insn
)) != 0
1226 && NONJUMP_INSN_P (prev
)
1227 && sets_cc0_p (PATTERN (prev
)))
1229 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1230 &new_direct_jump_p
)) != 0)
1233 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1234 nextlinks
= XEXP (nextlinks
, 1))
1235 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1237 &new_direct_jump_p
)) != 0)
1241 /* Do the same for an insn that explicitly references CC0. */
1242 if (NONJUMP_INSN_P (insn
)
1243 && (prev
= prev_nonnote_insn (insn
)) != 0
1244 && NONJUMP_INSN_P (prev
)
1245 && sets_cc0_p (PATTERN (prev
))
1246 && GET_CODE (PATTERN (insn
)) == SET
1247 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1249 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1250 &new_direct_jump_p
)) != 0)
1253 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1254 nextlinks
= XEXP (nextlinks
, 1))
1255 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1257 &new_direct_jump_p
)) != 0)
1261 /* Finally, see if any of the insns that this insn links to
1262 explicitly references CC0. If so, try this insn, that insn,
1263 and its predecessor if it sets CC0. */
1264 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1265 if (NONJUMP_INSN_P (XEXP (links
, 0))
1266 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1267 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1268 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1269 && NONJUMP_INSN_P (prev
)
1270 && sets_cc0_p (PATTERN (prev
))
1271 && (next
= try_combine (insn
, XEXP (links
, 0),
1273 &new_direct_jump_p
)) != 0)
1277 /* Try combining an insn with two different insns whose results it
1279 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1280 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1281 nextlinks
= XEXP (nextlinks
, 1))
1282 if ((next
= try_combine (insn
, XEXP (links
, 0),
1283 XEXP (nextlinks
, 0), NULL_RTX
,
1284 &new_direct_jump_p
)) != 0)
1287 /* Try four-instruction combinations. */
1288 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1291 rtx link
= XEXP (links
, 0);
1293 /* If the linked insn has been replaced by a note, then there
1294 is no point in pursuing this chain any further. */
1298 for (next1
= LOG_LINKS (link
); next1
; next1
= XEXP (next1
, 1))
1300 rtx link1
= XEXP (next1
, 0);
1303 /* I0 -> I1 -> I2 -> I3. */
1304 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1305 nextlinks
= XEXP (nextlinks
, 1))
1306 if ((next
= try_combine (insn
, link
, link1
,
1307 XEXP (nextlinks
, 0),
1308 &new_direct_jump_p
)) != 0)
1310 /* I0, I1 -> I2, I2 -> I3. */
1311 for (nextlinks
= XEXP (next1
, 1); nextlinks
;
1312 nextlinks
= XEXP (nextlinks
, 1))
1313 if ((next
= try_combine (insn
, link
, link1
,
1314 XEXP (nextlinks
, 0),
1315 &new_direct_jump_p
)) != 0)
1319 for (next1
= XEXP (links
, 1); next1
; next1
= XEXP (next1
, 1))
1321 rtx link1
= XEXP (next1
, 0);
1324 /* I0 -> I2; I1, I2 -> I3. */
1325 for (nextlinks
= LOG_LINKS (link
); nextlinks
;
1326 nextlinks
= XEXP (nextlinks
, 1))
1327 if ((next
= try_combine (insn
, link
, link1
,
1328 XEXP (nextlinks
, 0),
1329 &new_direct_jump_p
)) != 0)
1331 /* I0 -> I1; I1, I2 -> I3. */
1332 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1333 nextlinks
= XEXP (nextlinks
, 1))
1334 if ((next
= try_combine (insn
, link
, link1
,
1335 XEXP (nextlinks
, 0),
1336 &new_direct_jump_p
)) != 0)
1341 /* Try this insn with each REG_EQUAL note it links back to. */
1342 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1345 rtx temp
= XEXP (links
, 0);
1346 if ((set
= single_set (temp
)) != 0
1347 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1348 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1349 /* Avoid using a register that may already been marked
1350 dead by an earlier instruction. */
1351 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1352 && (GET_MODE (note
) == VOIDmode
1353 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1354 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1356 /* Temporarily replace the set's source with the
1357 contents of the REG_EQUAL note. The insn will
1358 be deleted or recognized by try_combine. */
1359 rtx orig
= SET_SRC (set
);
1360 SET_SRC (set
) = note
;
1362 i2mod_old_rhs
= copy_rtx (orig
);
1363 i2mod_new_rhs
= copy_rtx (note
);
1364 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1365 &new_direct_jump_p
);
1369 SET_SRC (set
) = orig
;
1374 record_dead_and_set_regs (insn
);
1382 default_rtl_profile ();
1385 new_direct_jump_p
|= purge_all_dead_edges ();
1386 delete_noop_moves ();
1389 free (uid_log_links
);
1390 free (uid_insn_cost
);
1391 VEC_free (reg_stat_type
, heap
, reg_stat
);
1394 struct undo
*undo
, *next
;
1395 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1403 total_attempts
+= combine_attempts
;
1404 total_merges
+= combine_merges
;
1405 total_extras
+= combine_extras
;
1406 total_successes
+= combine_successes
;
1408 nonzero_sign_valid
= 0;
1409 rtl_hooks
= general_rtl_hooks
;
1411 /* Make recognizer allow volatile MEMs again. */
1414 return new_direct_jump_p
;
1417 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1420 init_reg_last (void)
1425 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1426 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1429 /* Set up any promoted values for incoming argument registers. */
1432 setup_incoming_promotions (rtx first
)
1435 bool strictly_local
= false;
1437 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1438 arg
= DECL_CHAIN (arg
))
1440 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1442 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1444 /* Only continue if the incoming argument is in a register. */
1448 /* Determine, if possible, whether all call sites of the current
1449 function lie within the current compilation unit. (This does
1450 take into account the exporting of a function via taking its
1451 address, and so forth.) */
1452 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1454 /* The mode and signedness of the argument before any promotions happen
1455 (equal to the mode of the pseudo holding it at that stage). */
1456 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1457 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1459 /* The mode and signedness of the argument after any source language and
1460 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1461 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1462 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1464 /* The mode and signedness of the argument as it is actually passed,
1465 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1466 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1467 TREE_TYPE (cfun
->decl
), 0);
1469 /* The mode of the register in which the argument is being passed. */
1470 mode4
= GET_MODE (reg
);
1472 /* Eliminate sign extensions in the callee when:
1473 (a) A mode promotion has occurred; */
1476 /* (b) The mode of the register is the same as the mode of
1477 the argument as it is passed; */
1480 /* (c) There's no language level extension; */
1483 /* (c.1) All callers are from the current compilation unit. If that's
1484 the case we don't have to rely on an ABI, we only have to know
1485 what we're generating right now, and we know that we will do the
1486 mode1 to mode2 promotion with the given sign. */
1487 else if (!strictly_local
)
1489 /* (c.2) The combination of the two promotions is useful. This is
1490 true when the signs match, or if the first promotion is unsigned.
1491 In the later case, (sign_extend (zero_extend x)) is the same as
1492 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1498 /* Record that the value was promoted from mode1 to mode3,
1499 so that any sign extension at the head of the current
1500 function may be eliminated. */
1501 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1502 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1503 record_value_for_reg (reg
, first
, x
);
1507 /* Called via note_stores. If X is a pseudo that is narrower than
1508 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1510 If we are setting only a portion of X and we can't figure out what
1511 portion, assume all bits will be used since we don't know what will
1514 Similarly, set how many bits of X are known to be copies of the sign bit
1515 at all locations in the function. This is the smallest number implied
1519 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1521 rtx insn
= (rtx
) data
;
1525 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1526 /* If this register is undefined at the start of the file, we can't
1527 say what its contents were. */
1528 && ! REGNO_REG_SET_P
1529 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1530 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1532 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1534 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1536 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1537 rsp
->sign_bit_copies
= 1;
1541 /* If this register is being initialized using itself, and the
1542 register is uninitialized in this basic block, and there are
1543 no LOG_LINKS which set the register, then part of the
1544 register is uninitialized. In that case we can't assume
1545 anything about the number of nonzero bits.
1547 ??? We could do better if we checked this in
1548 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1549 could avoid making assumptions about the insn which initially
1550 sets the register, while still using the information in other
1551 insns. We would have to be careful to check every insn
1552 involved in the combination. */
1555 && reg_referenced_p (x
, PATTERN (insn
))
1556 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1561 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1563 if (dead_or_set_p (XEXP (link
, 0), x
))
1568 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1569 rsp
->sign_bit_copies
= 1;
1574 /* If this is a complex assignment, see if we can convert it into a
1575 simple assignment. */
1576 set
= expand_field_assignment (set
);
1578 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1579 set what we know about X. */
1581 if (SET_DEST (set
) == x
1582 || (GET_CODE (SET_DEST (set
)) == SUBREG
1583 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1584 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1585 && SUBREG_REG (SET_DEST (set
)) == x
))
1587 rtx src
= SET_SRC (set
);
1589 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1590 /* If X is narrower than a word and SRC is a non-negative
1591 constant that would appear negative in the mode of X,
1592 sign-extend it for use in reg_stat[].nonzero_bits because some
1593 machines (maybe most) will actually do the sign-extension
1594 and this is the conservative approach.
1596 ??? For 2.5, try to tighten up the MD files in this regard
1597 instead of this kludge. */
1599 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1600 && CONST_INT_P (src
)
1602 && 0 != (UINTVAL (src
)
1603 & ((unsigned HOST_WIDE_INT
) 1
1604 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1605 src
= GEN_INT (UINTVAL (src
)
1606 | ((unsigned HOST_WIDE_INT
) (-1)
1607 << GET_MODE_BITSIZE (GET_MODE (x
))));
1610 /* Don't call nonzero_bits if it cannot change anything. */
1611 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1612 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1613 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1614 if (rsp
->sign_bit_copies
== 0
1615 || rsp
->sign_bit_copies
> num
)
1616 rsp
->sign_bit_copies
= num
;
1620 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1621 rsp
->sign_bit_copies
= 1;
1626 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1627 optionally insns that were previously combined into I3 or that will be
1628 combined into the merger of INSN and I3. The order is PRED, PRED2,
1629 INSN, SUCC, SUCC2, I3.
1631 Return 0 if the combination is not allowed for any reason.
1633 If the combination is allowed, *PDEST will be set to the single
1634 destination of INSN and *PSRC to the single source, and this function
1638 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1639 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1640 rtx
*pdest
, rtx
*psrc
)
1649 bool all_adjacent
= true;
1655 if (next_active_insn (succ2
) != i3
)
1656 all_adjacent
= false;
1657 if (next_active_insn (succ
) != succ2
)
1658 all_adjacent
= false;
1660 else if (next_active_insn (succ
) != i3
)
1661 all_adjacent
= false;
1662 if (next_active_insn (insn
) != succ
)
1663 all_adjacent
= false;
1665 else if (next_active_insn (insn
) != i3
)
1666 all_adjacent
= false;
1668 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1669 or a PARALLEL consisting of such a SET and CLOBBERs.
1671 If INSN has CLOBBER parallel parts, ignore them for our processing.
1672 By definition, these happen during the execution of the insn. When it
1673 is merged with another insn, all bets are off. If they are, in fact,
1674 needed and aren't also supplied in I3, they may be added by
1675 recog_for_combine. Otherwise, it won't match.
1677 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1680 Get the source and destination of INSN. If more than one, can't
1683 if (GET_CODE (PATTERN (insn
)) == SET
)
1684 set
= PATTERN (insn
);
1685 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1686 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1688 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1690 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1692 switch (GET_CODE (elt
))
1694 /* This is important to combine floating point insns
1695 for the SH4 port. */
1697 /* Combining an isolated USE doesn't make sense.
1698 We depend here on combinable_i3pat to reject them. */
1699 /* The code below this loop only verifies that the inputs of
1700 the SET in INSN do not change. We call reg_set_between_p
1701 to verify that the REG in the USE does not change between
1703 If the USE in INSN was for a pseudo register, the matching
1704 insn pattern will likely match any register; combining this
1705 with any other USE would only be safe if we knew that the
1706 used registers have identical values, or if there was
1707 something to tell them apart, e.g. different modes. For
1708 now, we forgo such complicated tests and simply disallow
1709 combining of USES of pseudo registers with any other USE. */
1710 if (REG_P (XEXP (elt
, 0))
1711 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1713 rtx i3pat
= PATTERN (i3
);
1714 int i
= XVECLEN (i3pat
, 0) - 1;
1715 unsigned int regno
= REGNO (XEXP (elt
, 0));
1719 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1721 if (GET_CODE (i3elt
) == USE
1722 && REG_P (XEXP (i3elt
, 0))
1723 && (REGNO (XEXP (i3elt
, 0)) == regno
1724 ? reg_set_between_p (XEXP (elt
, 0),
1725 PREV_INSN (insn
), i3
)
1726 : regno
>= FIRST_PSEUDO_REGISTER
))
1733 /* We can ignore CLOBBERs. */
1738 /* Ignore SETs whose result isn't used but not those that
1739 have side-effects. */
1740 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1741 && insn_nothrow_p (insn
)
1742 && !side_effects_p (elt
))
1745 /* If we have already found a SET, this is a second one and
1746 so we cannot combine with this insn. */
1754 /* Anything else means we can't combine. */
1760 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1761 so don't do anything with it. */
1762 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1771 set
= expand_field_assignment (set
);
1772 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1774 /* Don't eliminate a store in the stack pointer. */
1775 if (dest
== stack_pointer_rtx
1776 /* Don't combine with an insn that sets a register to itself if it has
1777 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1778 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1779 /* Can't merge an ASM_OPERANDS. */
1780 || GET_CODE (src
) == ASM_OPERANDS
1781 /* Can't merge a function call. */
1782 || GET_CODE (src
) == CALL
1783 /* Don't eliminate a function call argument. */
1785 && (find_reg_fusage (i3
, USE
, dest
)
1787 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1788 && global_regs
[REGNO (dest
)])))
1789 /* Don't substitute into an incremented register. */
1790 || FIND_REG_INC_NOTE (i3
, dest
)
1791 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1792 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1793 /* Don't substitute into a non-local goto, this confuses CFG. */
1794 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1795 /* Make sure that DEST is not used after SUCC but before I3. */
1798 && (reg_used_between_p (dest
, succ2
, i3
)
1799 || reg_used_between_p (dest
, succ
, succ2
)))
1800 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1801 /* Make sure that the value that is to be substituted for the register
1802 does not use any registers whose values alter in between. However,
1803 If the insns are adjacent, a use can't cross a set even though we
1804 think it might (this can happen for a sequence of insns each setting
1805 the same destination; last_set of that register might point to
1806 a NOTE). If INSN has a REG_EQUIV note, the register is always
1807 equivalent to the memory so the substitution is valid even if there
1808 are intervening stores. Also, don't move a volatile asm or
1809 UNSPEC_VOLATILE across any other insns. */
1812 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1813 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1814 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1815 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1816 /* Don't combine across a CALL_INSN, because that would possibly
1817 change whether the life span of some REGs crosses calls or not,
1818 and it is a pain to update that information.
1819 Exception: if source is a constant, moving it later can't hurt.
1820 Accept that as a special case. */
1821 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1824 /* DEST must either be a REG or CC0. */
1827 /* If register alignment is being enforced for multi-word items in all
1828 cases except for parameters, it is possible to have a register copy
1829 insn referencing a hard register that is not allowed to contain the
1830 mode being copied and which would not be valid as an operand of most
1831 insns. Eliminate this problem by not combining with such an insn.
1833 Also, on some machines we don't want to extend the life of a hard
1837 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1838 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1839 /* Don't extend the life of a hard register unless it is
1840 user variable (if we have few registers) or it can't
1841 fit into the desired register (meaning something special
1843 Also avoid substituting a return register into I3, because
1844 reload can't handle a conflict with constraints of other
1846 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1847 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1850 else if (GET_CODE (dest
) != CC0
)
1854 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1855 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1856 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1858 /* Don't substitute for a register intended as a clobberable
1860 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1861 if (rtx_equal_p (reg
, dest
))
1864 /* If the clobber represents an earlyclobber operand, we must not
1865 substitute an expression containing the clobbered register.
1866 As we do not analyze the constraint strings here, we have to
1867 make the conservative assumption. However, if the register is
1868 a fixed hard reg, the clobber cannot represent any operand;
1869 we leave it up to the machine description to either accept or
1870 reject use-and-clobber patterns. */
1872 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1873 || !fixed_regs
[REGNO (reg
)])
1874 if (reg_overlap_mentioned_p (reg
, src
))
1878 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1879 or not), reject, unless nothing volatile comes between it and I3 */
1881 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1883 /* Make sure neither succ nor succ2 contains a volatile reference. */
1884 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1886 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1888 /* We'll check insns between INSN and I3 below. */
1891 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1892 to be an explicit register variable, and was chosen for a reason. */
1894 if (GET_CODE (src
) == ASM_OPERANDS
1895 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1898 /* If there are any volatile insns between INSN and I3, reject, because
1899 they might affect machine state. */
1901 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1902 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& volatile_insn_p (PATTERN (p
)))
1905 /* If INSN contains an autoincrement or autodecrement, make sure that
1906 register is not used between there and I3, and not already used in
1907 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1908 Also insist that I3 not be a jump; if it were one
1909 and the incremented register were spilled, we would lose. */
1912 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1913 if (REG_NOTE_KIND (link
) == REG_INC
1915 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1916 || (pred
!= NULL_RTX
1917 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1918 || (pred2
!= NULL_RTX
1919 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1920 || (succ
!= NULL_RTX
1921 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1922 || (succ2
!= NULL_RTX
1923 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1924 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1929 /* Don't combine an insn that follows a CC0-setting insn.
1930 An insn that uses CC0 must not be separated from the one that sets it.
1931 We do, however, allow I2 to follow a CC0-setting insn if that insn
1932 is passed as I1; in that case it will be deleted also.
1933 We also allow combining in this case if all the insns are adjacent
1934 because that would leave the two CC0 insns adjacent as well.
1935 It would be more logical to test whether CC0 occurs inside I1 or I2,
1936 but that would be much slower, and this ought to be equivalent. */
1938 p
= prev_nonnote_insn (insn
);
1939 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1944 /* If we get here, we have passed all the tests and the combination is
1953 /* LOC is the location within I3 that contains its pattern or the component
1954 of a PARALLEL of the pattern. We validate that it is valid for combining.
1956 One problem is if I3 modifies its output, as opposed to replacing it
1957 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1958 doing so would produce an insn that is not equivalent to the original insns.
1962 (set (reg:DI 101) (reg:DI 100))
1963 (set (subreg:SI (reg:DI 101) 0) <foo>)
1965 This is NOT equivalent to:
1967 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1968 (set (reg:DI 101) (reg:DI 100))])
1970 Not only does this modify 100 (in which case it might still be valid
1971 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1973 We can also run into a problem if I2 sets a register that I1
1974 uses and I1 gets directly substituted into I3 (not via I2). In that
1975 case, we would be getting the wrong value of I2DEST into I3, so we
1976 must reject the combination. This case occurs when I2 and I1 both
1977 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1978 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1979 of a SET must prevent combination from occurring. The same situation
1980 can occur for I0, in which case I0_NOT_IN_SRC is set.
1982 Before doing the above check, we first try to expand a field assignment
1983 into a set of logical operations.
1985 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1986 we place a register that is both set and used within I3. If more than one
1987 such register is detected, we fail.
1989 Return 1 if the combination is valid, zero otherwise. */
1992 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
1993 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
1997 if (GET_CODE (x
) == SET
)
2000 rtx dest
= SET_DEST (set
);
2001 rtx src
= SET_SRC (set
);
2002 rtx inner_dest
= dest
;
2005 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2006 || GET_CODE (inner_dest
) == SUBREG
2007 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2008 inner_dest
= XEXP (inner_dest
, 0);
2010 /* Check for the case where I3 modifies its output, as discussed
2011 above. We don't want to prevent pseudos from being combined
2012 into the address of a MEM, so only prevent the combination if
2013 i1 or i2 set the same MEM. */
2014 if ((inner_dest
!= dest
&&
2015 (!MEM_P (inner_dest
)
2016 || rtx_equal_p (i2dest
, inner_dest
)
2017 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2018 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2019 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2020 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2021 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2023 /* This is the same test done in can_combine_p except we can't test
2024 all_adjacent; we don't have to, since this instruction will stay
2025 in place, thus we are not considering increasing the lifetime of
2028 Also, if this insn sets a function argument, combining it with
2029 something that might need a spill could clobber a previous
2030 function argument; the all_adjacent test in can_combine_p also
2031 checks this; here, we do a more specific test for this case. */
2033 || (REG_P (inner_dest
)
2034 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2035 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2036 GET_MODE (inner_dest
))))
2037 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2038 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2041 /* If DEST is used in I3, it is being killed in this insn, so
2042 record that for later. We have to consider paradoxical
2043 subregs here, since they kill the whole register, but we
2044 ignore partial subregs, STRICT_LOW_PART, etc.
2045 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2046 STACK_POINTER_REGNUM, since these are always considered to be
2047 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2049 if (GET_CODE (subdest
) == SUBREG
2050 && (GET_MODE_SIZE (GET_MODE (subdest
))
2051 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2052 subdest
= SUBREG_REG (subdest
);
2055 && reg_referenced_p (subdest
, PATTERN (i3
))
2056 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2057 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2058 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2060 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2061 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2062 || ! fixed_regs
[REGNO (subdest
)])
2064 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2066 if (*pi3dest_killed
)
2069 *pi3dest_killed
= subdest
;
2073 else if (GET_CODE (x
) == PARALLEL
)
2077 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2078 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2079 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2086 /* Return 1 if X is an arithmetic expression that contains a multiplication
2087 and division. We don't count multiplications by powers of two here. */
2090 contains_muldiv (rtx x
)
2092 switch (GET_CODE (x
))
2094 case MOD
: case DIV
: case UMOD
: case UDIV
:
2098 return ! (CONST_INT_P (XEXP (x
, 1))
2099 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2102 return contains_muldiv (XEXP (x
, 0))
2103 || contains_muldiv (XEXP (x
, 1));
2106 return contains_muldiv (XEXP (x
, 0));
2112 /* Determine whether INSN can be used in a combination. Return nonzero if
2113 not. This is used in try_combine to detect early some cases where we
2114 can't perform combinations. */
2117 cant_combine_insn_p (rtx insn
)
2122 /* If this isn't really an insn, we can't do anything.
2123 This can occur when flow deletes an insn that it has merged into an
2124 auto-increment address. */
2125 if (! INSN_P (insn
))
2128 /* Never combine loads and stores involving hard regs that are likely
2129 to be spilled. The register allocator can usually handle such
2130 reg-reg moves by tying. If we allow the combiner to make
2131 substitutions of likely-spilled regs, reload might die.
2132 As an exception, we allow combinations involving fixed regs; these are
2133 not available to the register allocator so there's no risk involved. */
2135 set
= single_set (insn
);
2138 src
= SET_SRC (set
);
2139 dest
= SET_DEST (set
);
2140 if (GET_CODE (src
) == SUBREG
)
2141 src
= SUBREG_REG (src
);
2142 if (GET_CODE (dest
) == SUBREG
)
2143 dest
= SUBREG_REG (dest
);
2144 if (REG_P (src
) && REG_P (dest
)
2145 && ((HARD_REGISTER_P (src
)
2146 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2147 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2148 || (HARD_REGISTER_P (dest
)
2149 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2150 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2156 struct likely_spilled_retval_info
2158 unsigned regno
, nregs
;
2162 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2163 hard registers that are known to be written to / clobbered in full. */
2165 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2167 struct likely_spilled_retval_info
*const info
=
2168 (struct likely_spilled_retval_info
*) data
;
2169 unsigned regno
, nregs
;
2172 if (!REG_P (XEXP (set
, 0)))
2175 if (regno
>= info
->regno
+ info
->nregs
)
2177 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2178 if (regno
+ nregs
<= info
->regno
)
2180 new_mask
= (2U << (nregs
- 1)) - 1;
2181 if (regno
< info
->regno
)
2182 new_mask
>>= info
->regno
- regno
;
2184 new_mask
<<= regno
- info
->regno
;
2185 info
->mask
&= ~new_mask
;
2188 /* Return nonzero iff part of the return value is live during INSN, and
2189 it is likely spilled. This can happen when more than one insn is needed
2190 to copy the return value, e.g. when we consider to combine into the
2191 second copy insn for a complex value. */
2194 likely_spilled_retval_p (rtx insn
)
2196 rtx use
= BB_END (this_basic_block
);
2198 unsigned regno
, nregs
;
2199 /* We assume here that no machine mode needs more than
2200 32 hard registers when the value overlaps with a register
2201 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2203 struct likely_spilled_retval_info info
;
2205 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2207 reg
= XEXP (PATTERN (use
), 0);
2208 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2210 regno
= REGNO (reg
);
2211 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2214 mask
= (2U << (nregs
- 1)) - 1;
2216 /* Disregard parts of the return value that are set later. */
2220 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2222 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2225 /* Check if any of the (probably) live return value registers is
2230 if ((mask
& 1 << nregs
)
2231 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2237 /* Adjust INSN after we made a change to its destination.
2239 Changing the destination can invalidate notes that say something about
2240 the results of the insn and a LOG_LINK pointing to the insn. */
2243 adjust_for_new_dest (rtx insn
)
2245 /* For notes, be conservative and simply remove them. */
2246 remove_reg_equal_equiv_notes (insn
);
2248 /* The new insn will have a destination that was previously the destination
2249 of an insn just above it. Call distribute_links to make a LOG_LINK from
2250 the next use of that destination. */
2251 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2253 df_insn_rescan (insn
);
2256 /* Return TRUE if combine can reuse reg X in mode MODE.
2257 ADDED_SETS is nonzero if the original set is still required. */
2259 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2267 /* Allow hard registers if the new mode is legal, and occupies no more
2268 registers than the old mode. */
2269 if (regno
< FIRST_PSEUDO_REGISTER
)
2270 return (HARD_REGNO_MODE_OK (regno
, mode
)
2271 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2272 >= hard_regno_nregs
[regno
][mode
]));
2274 /* Or a pseudo that is only used once. */
2275 return (REG_N_SETS (regno
) == 1 && !added_sets
2276 && !REG_USERVAR_P (x
));
2280 /* Check whether X, the destination of a set, refers to part of
2281 the register specified by REG. */
2284 reg_subword_p (rtx x
, rtx reg
)
2286 /* Check that reg is an integer mode register. */
2287 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2290 if (GET_CODE (x
) == STRICT_LOW_PART
2291 || GET_CODE (x
) == ZERO_EXTRACT
)
2294 return GET_CODE (x
) == SUBREG
2295 && SUBREG_REG (x
) == reg
2296 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2300 /* Replace auto-increment addressing modes with explicit operations to access
2301 the same addresses without modifying the corresponding registers. */
2304 cleanup_auto_inc_dec (rtx src
, enum machine_mode mem_mode
)
2307 const RTX_CODE code
= GET_CODE (x
);
2323 /* SCRATCH must be shared because they represent distinct values. */
2326 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2331 if (shared_const_p (x
))
2336 mem_mode
= GET_MODE (x
);
2341 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2342 return gen_rtx_PLUS (GET_MODE (x
),
2343 cleanup_auto_inc_dec (XEXP (x
, 0), mem_mode
),
2344 GEN_INT (code
== PRE_INC
2345 ? GET_MODE_SIZE (mem_mode
)
2346 : -GET_MODE_SIZE (mem_mode
)));
2352 return cleanup_auto_inc_dec (code
== PRE_MODIFY
2353 ? XEXP (x
, 1) : XEXP (x
, 0),
2360 /* Copy the various flags, fields, and other information. We assume
2361 that all fields need copying, and then clear the fields that should
2362 not be copied. That is the sensible default behavior, and forces
2363 us to explicitly document why we are *not* copying a flag. */
2364 x
= shallow_copy_rtx (x
);
2366 /* We do not copy the USED flag, which is used as a mark bit during
2367 walks over the RTL. */
2368 RTX_FLAG (x
, used
) = 0;
2370 /* We do not copy FRAME_RELATED for INSNs. */
2372 RTX_FLAG (x
, frame_related
) = 0;
2374 fmt
= GET_RTX_FORMAT (code
);
2375 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2377 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), mem_mode
);
2378 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2381 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2382 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2384 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), mem_mode
);
2391 /* Auxiliary data structure for propagate_for_debug_stmt. */
2393 struct rtx_subst_pair
2399 /* DATA points to an rtx_subst_pair. Return the value that should be
2403 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2405 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2407 if (!rtx_equal_p (from
, old_rtx
))
2409 if (!pair
->adjusted
)
2411 pair
->adjusted
= true;
2413 pair
->to
= cleanup_auto_inc_dec (pair
->to
, VOIDmode
);
2415 pair
->to
= copy_rtx (pair
->to
);
2417 pair
->to
= make_compound_operation (pair
->to
, SET
);
2420 return copy_rtx (pair
->to
);
2423 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2427 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
)
2431 struct rtx_subst_pair p
;
2435 next
= NEXT_INSN (insn
);
2436 while (next
!= last
)
2439 next
= NEXT_INSN (insn
);
2440 if (DEBUG_INSN_P (insn
))
2442 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2443 dest
, propagate_for_debug_subst
, &p
);
2444 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2446 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2447 df_insn_rescan (insn
);
2452 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2453 Note that the INSN should be deleted *after* removing dead edges, so
2454 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2455 but not for a (set (pc) (label_ref FOO)). */
2458 update_cfg_for_uncondjump (rtx insn
)
2460 basic_block bb
= BLOCK_FOR_INSN (insn
);
2461 bool at_end
= (BB_END (bb
) == insn
);
2464 purge_dead_edges (bb
);
2467 if (at_end
&& EDGE_COUNT (bb
->succs
) == 1)
2471 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2473 /* Remove barriers from the footer if there are any. */
2474 for (insn
= bb
->il
.rtl
->footer
; insn
; insn
= NEXT_INSN (insn
))
2475 if (BARRIER_P (insn
))
2477 if (PREV_INSN (insn
))
2478 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2480 bb
->il
.rtl
->footer
= NEXT_INSN (insn
);
2481 if (NEXT_INSN (insn
))
2482 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2484 else if (LABEL_P (insn
))
2489 /* Try to combine the insns I0, I1 and I2 into I3.
2490 Here I0, I1 and I2 appear earlier than I3.
2491 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2494 If we are combining more than two insns and the resulting insn is not
2495 recognized, try splitting it into two insns. If that happens, I2 and I3
2496 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2497 Otherwise, I0, I1 and I2 are pseudo-deleted.
2499 Return 0 if the combination does not work. Then nothing is changed.
2500 If we did the combination, return the insn at which combine should
2503 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2504 new direct jump instruction. */
2507 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
)
2509 /* New patterns for I3 and I2, respectively. */
2510 rtx newpat
, newi2pat
= 0;
2511 rtvec newpat_vec_with_clobbers
= 0;
2512 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2513 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2515 int added_sets_0
, added_sets_1
, added_sets_2
;
2516 /* Total number of SETs to put into I3. */
2518 /* Nonzero if I2's or I1's body now appears in I3. */
2519 int i2_is_used
= 0, i1_is_used
= 0;
2520 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2521 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2522 /* Contains I3 if the destination of I3 is used in its source, which means
2523 that the old life of I3 is being killed. If that usage is placed into
2524 I2 and not in I3, a REG_DEAD note must be made. */
2525 rtx i3dest_killed
= 0;
2526 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2527 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2528 /* Copy of SET_SRC of I1, if needed. */
2530 /* Set if I2DEST was reused as a scratch register. */
2531 bool i2scratch
= false;
2532 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2533 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2534 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2535 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2536 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2537 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2538 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2539 /* Notes that must be added to REG_NOTES in I3 and I2. */
2540 rtx new_i3_notes
, new_i2_notes
;
2541 /* Notes that we substituted I3 into I2 instead of the normal case. */
2542 int i3_subst_into_i2
= 0;
2543 /* Notes that I1, I2 or I3 is a MULT operation. */
2546 int changed_i3_dest
= 0;
2552 rtx new_other_notes
;
2555 /* Only try four-insn combinations when there's high likelihood of
2556 success. Look for simple insns, such as loads of constants or
2557 binary operations involving a constant. */
2564 if (!flag_expensive_optimizations
)
2567 for (i
= 0; i
< 4; i
++)
2569 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2570 rtx set
= single_set (insn
);
2574 src
= SET_SRC (set
);
2575 if (CONSTANT_P (src
))
2580 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2582 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2583 || GET_CODE (src
) == LSHIFTRT
)
2586 if (ngood
< 2 && nshift
< 2)
2590 /* Exit early if one of the insns involved can't be used for
2592 if (cant_combine_insn_p (i3
)
2593 || cant_combine_insn_p (i2
)
2594 || (i1
&& cant_combine_insn_p (i1
))
2595 || (i0
&& cant_combine_insn_p (i0
))
2596 || likely_spilled_retval_p (i3
))
2600 undobuf
.other_insn
= 0;
2602 /* Reset the hard register usage information. */
2603 CLEAR_HARD_REG_SET (newpat_used_regs
);
2605 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2608 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2609 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2611 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2612 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2614 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2615 INSN_UID (i2
), INSN_UID (i3
));
2618 /* If multiple insns feed into one of I2 or I3, they can be in any
2619 order. To simplify the code below, reorder them in sequence. */
2620 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2621 temp
= i2
, i2
= i0
, i0
= temp
;
2622 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2623 temp
= i1
, i1
= i0
, i0
= temp
;
2624 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2625 temp
= i1
, i1
= i2
, i2
= temp
;
2627 added_links_insn
= 0;
2629 /* First check for one important special case that the code below will
2630 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2631 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2632 we may be able to replace that destination with the destination of I3.
2633 This occurs in the common code where we compute both a quotient and
2634 remainder into a structure, in which case we want to do the computation
2635 directly into the structure to avoid register-register copies.
2637 Note that this case handles both multiple sets in I2 and also cases
2638 where I2 has a number of CLOBBERs inside the PARALLEL.
2640 We make very conservative checks below and only try to handle the
2641 most common cases of this. For example, we only handle the case
2642 where I2 and I3 are adjacent to avoid making difficult register
2645 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2646 && REG_P (SET_SRC (PATTERN (i3
)))
2647 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2648 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2649 && GET_CODE (PATTERN (i2
)) == PARALLEL
2650 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2651 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2652 below would need to check what is inside (and reg_overlap_mentioned_p
2653 doesn't support those codes anyway). Don't allow those destinations;
2654 the resulting insn isn't likely to be recognized anyway. */
2655 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2656 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2657 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2658 SET_DEST (PATTERN (i3
)))
2659 && next_active_insn (i2
) == i3
)
2661 rtx p2
= PATTERN (i2
);
2663 /* Make sure that the destination of I3,
2664 which we are going to substitute into one output of I2,
2665 is not used within another output of I2. We must avoid making this:
2666 (parallel [(set (mem (reg 69)) ...)
2667 (set (reg 69) ...)])
2668 which is not well-defined as to order of actions.
2669 (Besides, reload can't handle output reloads for this.)
2671 The problem can also happen if the dest of I3 is a memory ref,
2672 if another dest in I2 is an indirect memory ref. */
2673 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2674 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2675 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2676 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2677 SET_DEST (XVECEXP (p2
, 0, i
))))
2680 if (i
== XVECLEN (p2
, 0))
2681 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2682 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2683 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2688 subst_low_luid
= DF_INSN_LUID (i2
);
2690 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2691 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2692 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2693 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2695 /* Replace the dest in I2 with our dest and make the resulting
2696 insn the new pattern for I3. Then skip to where we validate
2697 the pattern. Everything was set up above. */
2698 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2700 i3_subst_into_i2
= 1;
2701 goto validate_replacement
;
2705 /* If I2 is setting a pseudo to a constant and I3 is setting some
2706 sub-part of it to another constant, merge them by making a new
2709 && (temp
= single_set (i2
)) != 0
2710 && (CONST_INT_P (SET_SRC (temp
))
2711 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2712 && GET_CODE (PATTERN (i3
)) == SET
2713 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2714 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2715 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2717 rtx dest
= SET_DEST (PATTERN (i3
));
2721 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2723 if (CONST_INT_P (XEXP (dest
, 1))
2724 && CONST_INT_P (XEXP (dest
, 2)))
2726 width
= INTVAL (XEXP (dest
, 1));
2727 offset
= INTVAL (XEXP (dest
, 2));
2728 dest
= XEXP (dest
, 0);
2729 if (BITS_BIG_ENDIAN
)
2730 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2735 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2736 dest
= XEXP (dest
, 0);
2737 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2743 /* If this is the low part, we're done. */
2744 if (subreg_lowpart_p (dest
))
2746 /* Handle the case where inner is twice the size of outer. */
2747 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2748 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2749 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2750 /* Otherwise give up for now. */
2756 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2757 <= HOST_BITS_PER_DOUBLE_INT
))
2760 rtx inner
= SET_SRC (PATTERN (i3
));
2761 rtx outer
= SET_SRC (temp
);
2763 o
= rtx_to_double_int (outer
);
2764 i
= rtx_to_double_int (inner
);
2766 m
= double_int_mask (width
);
2767 i
= double_int_and (i
, m
);
2768 m
= double_int_lshift (m
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2769 i
= double_int_lshift (i
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2770 o
= double_int_ior (double_int_and_not (o
, m
), i
);
2774 subst_low_luid
= DF_INSN_LUID (i2
);
2775 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2776 i2dest
= SET_DEST (temp
);
2777 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2779 /* Replace the source in I2 with the new constant and make the
2780 resulting insn the new pattern for I3. Then skip to where we
2781 validate the pattern. Everything was set up above. */
2782 SUBST (SET_SRC (temp
),
2783 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2785 newpat
= PATTERN (i2
);
2787 /* The dest of I3 has been replaced with the dest of I2. */
2788 changed_i3_dest
= 1;
2789 goto validate_replacement
;
2794 /* If we have no I1 and I2 looks like:
2795 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2797 make up a dummy I1 that is
2800 (set (reg:CC X) (compare:CC Y (const_int 0)))
2802 (We can ignore any trailing CLOBBERs.)
2804 This undoes a previous combination and allows us to match a branch-and-
2807 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2808 && XVECLEN (PATTERN (i2
), 0) >= 2
2809 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2810 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2812 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2813 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2814 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2815 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2816 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2817 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2819 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2820 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2825 /* We make I1 with the same INSN_UID as I2. This gives it
2826 the same DF_INSN_LUID for value tracking. Our fake I1 will
2827 never appear in the insn stream so giving it the same INSN_UID
2828 as I2 will not cause a problem. */
2830 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2831 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2832 INSN_LOCATOR (i2
), -1, NULL_RTX
);
2834 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2835 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2836 SET_DEST (PATTERN (i1
)));
2841 /* Verify that I2 and I1 are valid for combining. */
2842 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2843 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2845 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2852 /* Record whether I2DEST is used in I2SRC and similarly for the other
2853 cases. Knowing this will help in register status updating below. */
2854 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2855 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2856 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2857 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2858 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2859 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2860 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2861 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2862 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2864 /* For the earlier insns, determine which of the subsequent ones they
2866 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2867 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2868 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2869 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2870 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2872 /* Ensure that I3's pattern can be the destination of combines. */
2873 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2874 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2875 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2876 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2883 /* See if any of the insns is a MULT operation. Unless one is, we will
2884 reject a combination that is, since it must be slower. Be conservative
2886 if (GET_CODE (i2src
) == MULT
2887 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2888 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2889 || (GET_CODE (PATTERN (i3
)) == SET
2890 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2893 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2894 We used to do this EXCEPT in one case: I3 has a post-inc in an
2895 output operand. However, that exception can give rise to insns like
2897 which is a famous insn on the PDP-11 where the value of r3 used as the
2898 source was model-dependent. Avoid this sort of thing. */
2901 if (!(GET_CODE (PATTERN (i3
)) == SET
2902 && REG_P (SET_SRC (PATTERN (i3
)))
2903 && MEM_P (SET_DEST (PATTERN (i3
)))
2904 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2905 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2906 /* It's not the exception. */
2909 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2910 if (REG_NOTE_KIND (link
) == REG_INC
2911 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2913 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2920 /* See if the SETs in I1 or I2 need to be kept around in the merged
2921 instruction: whenever the value set there is still needed past I3.
2922 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2924 For the SET in I1, we have two cases: If I1 and I2 independently
2925 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2926 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2927 in I1 needs to be kept around unless I1DEST dies or is set in either
2928 I2 or I3. The same consideration applies to I0. */
2930 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2933 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2934 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2939 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2940 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
2941 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
2945 /* We are about to copy insns for the case where they need to be kept
2946 around. Check that they can be copied in the merged instruction. */
2948 if (targetm
.cannot_copy_insn_p
2949 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2950 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2951 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2957 /* If the set in I2 needs to be kept around, we must make a copy of
2958 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2959 PATTERN (I2), we are only substituting for the original I1DEST, not into
2960 an already-substituted copy. This also prevents making self-referential
2961 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2966 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2967 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2969 i2pat
= copy_rtx (PATTERN (i2
));
2974 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2975 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2977 i1pat
= copy_rtx (PATTERN (i1
));
2982 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2983 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2985 i0pat
= copy_rtx (PATTERN (i0
));
2990 /* Substitute in the latest insn for the regs set by the earlier ones. */
2992 maxreg
= max_reg_num ();
2997 /* Many machines that don't use CC0 have insns that can both perform an
2998 arithmetic operation and set the condition code. These operations will
2999 be represented as a PARALLEL with the first element of the vector
3000 being a COMPARE of an arithmetic operation with the constant zero.
3001 The second element of the vector will set some pseudo to the result
3002 of the same arithmetic operation. If we simplify the COMPARE, we won't
3003 match such a pattern and so will generate an extra insn. Here we test
3004 for this case, where both the comparison and the operation result are
3005 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3006 I2SRC. Later we will make the PARALLEL that contains I2. */
3008 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3009 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3010 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
3011 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3013 #ifdef SELECT_CC_MODE
3015 enum machine_mode compare_mode
;
3018 newpat
= PATTERN (i3
);
3019 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
3023 #ifdef SELECT_CC_MODE
3024 /* See if a COMPARE with the operand we substituted in should be done
3025 with the mode that is currently being used. If not, do the same
3026 processing we do in `subst' for a SET; namely, if the destination
3027 is used only once, try to replace it with a register of the proper
3028 mode and also replace the COMPARE. */
3029 if (undobuf
.other_insn
== 0
3030 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
3031 &undobuf
.other_insn
))
3032 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
3034 != GET_MODE (SET_DEST (newpat
))))
3036 if (can_change_dest_mode (SET_DEST (newpat
), added_sets_2
,
3039 unsigned int regno
= REGNO (SET_DEST (newpat
));
3042 if (regno
< FIRST_PSEUDO_REGISTER
)
3043 new_dest
= gen_rtx_REG (compare_mode
, regno
);
3046 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3047 new_dest
= regno_reg_rtx
[regno
];
3050 SUBST (SET_DEST (newpat
), new_dest
);
3051 SUBST (XEXP (*cc_use
, 0), new_dest
);
3052 SUBST (SET_SRC (newpat
),
3053 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
3056 undobuf
.other_insn
= 0;
3063 /* It is possible that the source of I2 or I1 may be performing
3064 an unneeded operation, such as a ZERO_EXTEND of something
3065 that is known to have the high part zero. Handle that case
3066 by letting subst look at the inner insns.
3068 Another way to do this would be to have a function that tries
3069 to simplify a single insn instead of merging two or more
3070 insns. We don't do this because of the potential of infinite
3071 loops and because of the potential extra memory required.
3072 However, doing it the way we are is a bit of a kludge and
3073 doesn't catch all cases.
3075 But only do this if -fexpensive-optimizations since it slows
3076 things down and doesn't usually win.
3078 This is not done in the COMPARE case above because the
3079 unmodified I2PAT is used in the PARALLEL and so a pattern
3080 with a modified I2SRC would not match. */
3082 if (flag_expensive_optimizations
)
3084 /* Pass pc_rtx so no substitutions are done, just
3088 subst_low_luid
= DF_INSN_LUID (i1
);
3089 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
3092 subst_low_luid
= DF_INSN_LUID (i2
);
3093 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
3096 n_occurrences
= 0; /* `subst' counts here */
3097 subst_low_luid
= DF_INSN_LUID (i2
);
3099 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3100 copy of I2SRC each time we substitute it, in order to avoid creating
3101 self-referential RTL when we will be substituting I1SRC for I1DEST
3102 later. Likewise if I0 feeds into I2, either directly or indirectly
3103 through I1, and I0DEST is in I0SRC. */
3104 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
3105 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3106 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3107 && i0dest_in_i0src
));
3110 /* Record whether I2's body now appears within I3's body. */
3111 i2_is_used
= n_occurrences
;
3114 /* If we already got a failure, don't try to do more. Otherwise, try to
3115 substitute I1 if we have it. */
3117 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3119 /* Check that an autoincrement side-effect on I1 has not been lost.
3120 This happens if I1DEST is mentioned in I2 and dies there, and
3121 has disappeared from the new pattern. */
3122 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3124 && dead_or_set_p (i2
, i1dest
)
3125 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3126 /* Before we can do this substitution, we must redo the test done
3127 above (see detailed comments there) that ensures I1DEST isn't
3128 mentioned in any SETs in NEWPAT that are field assignments. */
3129 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3137 subst_low_luid
= DF_INSN_LUID (i1
);
3139 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3140 copy of I1SRC each time we substitute it, in order to avoid creating
3141 self-referential RTL when we will be substituting I0SRC for I0DEST
3143 newpat
= subst (newpat
, i1dest
, i1src
, 0,
3144 i0_feeds_i1_n
&& i0dest_in_i0src
);
3147 /* Record whether I1's body now appears within I3's body. */
3148 i1_is_used
= n_occurrences
;
3151 /* Likewise for I0 if we have it. */
3153 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3155 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3156 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3157 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3158 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3159 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3166 /* If the following substitution will modify I1SRC, make a copy of it
3167 for the case where it is substituted for I1DEST in I2PAT later. */
3168 if (i0_feeds_i1_n
&& added_sets_2
&& i1_feeds_i2_n
)
3169 i1src_copy
= copy_rtx (i1src
);
3172 subst_low_luid
= DF_INSN_LUID (i0
);
3173 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0);
3177 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3178 to count all the ways that I2SRC and I1SRC can be used. */
3179 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3180 && i2_is_used
+ added_sets_2
> 1)
3181 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3182 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3184 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3185 && (n_occurrences
+ added_sets_0
3186 + (added_sets_1
&& i0_feeds_i1_n
)
3187 + (added_sets_2
&& i0_feeds_i2_n
)
3189 /* Fail if we tried to make a new register. */
3190 || max_reg_num () != maxreg
3191 /* Fail if we couldn't do something and have a CLOBBER. */
3192 || GET_CODE (newpat
) == CLOBBER
3193 /* Fail if this new pattern is a MULT and we didn't have one before
3194 at the outer level. */
3195 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3202 /* If the actions of the earlier insns must be kept
3203 in addition to substituting them into the latest one,
3204 we must make a new PARALLEL for the latest insn
3205 to hold additional the SETs. */
3207 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3209 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3212 if (GET_CODE (newpat
) == PARALLEL
)
3214 rtvec old
= XVEC (newpat
, 0);
3215 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3216 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3217 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3218 sizeof (old
->elem
[0]) * old
->num_elem
);
3223 total_sets
= 1 + extra_sets
;
3224 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3225 XVECEXP (newpat
, 0, 0) = old
;
3229 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3235 t
= subst (t
, i0dest
, i0src
, 0, 0);
3237 XVECEXP (newpat
, 0, --total_sets
) = t
;
3243 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0,
3244 i0_feeds_i1_n
&& i0dest_in_i0src
);
3245 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3246 t
= subst (t
, i0dest
, i0src
, 0, 0);
3248 XVECEXP (newpat
, 0, --total_sets
) = t
;
3252 validate_replacement
:
3254 /* Note which hard regs this insn has as inputs. */
3255 mark_used_regs_combine (newpat
);
3257 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3258 consider splitting this pattern, we might need these clobbers. */
3259 if (i1
&& GET_CODE (newpat
) == PARALLEL
3260 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3262 int len
= XVECLEN (newpat
, 0);
3264 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3265 for (i
= 0; i
< len
; i
++)
3266 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3269 /* Is the result of combination a valid instruction? */
3270 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3272 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3273 the second SET's destination is a register that is unused and isn't
3274 marked as an instruction that might trap in an EH region. In that case,
3275 we just need the first SET. This can occur when simplifying a divmod
3276 insn. We *must* test for this case here because the code below that
3277 splits two independent SETs doesn't handle this case correctly when it
3278 updates the register status.
3280 It's pointless doing this if we originally had two sets, one from
3281 i3, and one from i2. Combining then splitting the parallel results
3282 in the original i2 again plus an invalid insn (which we delete).
3283 The net effect is only to move instructions around, which makes
3284 debug info less accurate.
3286 Also check the case where the first SET's destination is unused.
3287 That would not cause incorrect code, but does cause an unneeded
3290 if (insn_code_number
< 0
3291 && !(added_sets_2
&& i1
== 0)
3292 && GET_CODE (newpat
) == PARALLEL
3293 && XVECLEN (newpat
, 0) == 2
3294 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3295 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3296 && asm_noperands (newpat
) < 0)
3298 rtx set0
= XVECEXP (newpat
, 0, 0);
3299 rtx set1
= XVECEXP (newpat
, 0, 1);
3301 if (((REG_P (SET_DEST (set1
))
3302 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3303 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3304 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3305 && insn_nothrow_p (i3
)
3306 && !side_effects_p (SET_SRC (set1
)))
3309 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3312 else if (((REG_P (SET_DEST (set0
))
3313 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3314 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3315 && find_reg_note (i3
, REG_UNUSED
,
3316 SUBREG_REG (SET_DEST (set0
)))))
3317 && insn_nothrow_p (i3
)
3318 && !side_effects_p (SET_SRC (set0
)))
3321 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3323 if (insn_code_number
>= 0)
3324 changed_i3_dest
= 1;
3328 /* If we were combining three insns and the result is a simple SET
3329 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3330 insns. There are two ways to do this. It can be split using a
3331 machine-specific method (like when you have an addition of a large
3332 constant) or by combine in the function find_split_point. */
3334 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3335 && asm_noperands (newpat
) < 0)
3337 rtx parallel
, m_split
, *split
;
3339 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3340 use I2DEST as a scratch register will help. In the latter case,
3341 convert I2DEST to the mode of the source of NEWPAT if we can. */
3343 m_split
= combine_split_insns (newpat
, i3
);
3345 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3346 inputs of NEWPAT. */
3348 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3349 possible to try that as a scratch reg. This would require adding
3350 more code to make it work though. */
3352 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3354 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3356 /* First try to split using the original register as a
3357 scratch register. */
3358 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3359 gen_rtvec (2, newpat
,
3360 gen_rtx_CLOBBER (VOIDmode
,
3362 m_split
= combine_split_insns (parallel
, i3
);
3364 /* If that didn't work, try changing the mode of I2DEST if
3367 && new_mode
!= GET_MODE (i2dest
)
3368 && new_mode
!= VOIDmode
3369 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3371 enum machine_mode old_mode
= GET_MODE (i2dest
);
3374 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3375 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3378 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3379 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3382 parallel
= (gen_rtx_PARALLEL
3384 gen_rtvec (2, newpat
,
3385 gen_rtx_CLOBBER (VOIDmode
,
3387 m_split
= combine_split_insns (parallel
, i3
);
3390 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3394 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3395 buf
= undobuf
.undos
;
3396 undobuf
.undos
= buf
->next
;
3397 buf
->next
= undobuf
.frees
;
3398 undobuf
.frees
= buf
;
3402 i2scratch
= m_split
!= 0;
3405 /* If recog_for_combine has discarded clobbers, try to use them
3406 again for the split. */
3407 if (m_split
== 0 && newpat_vec_with_clobbers
)
3409 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3410 m_split
= combine_split_insns (parallel
, i3
);
3413 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3415 m_split
= PATTERN (m_split
);
3416 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3417 if (insn_code_number
>= 0)
3420 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3421 && (next_real_insn (i2
) == i3
3422 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3425 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3426 newi2pat
= PATTERN (m_split
);
3428 i3set
= single_set (NEXT_INSN (m_split
));
3429 i2set
= single_set (m_split
);
3431 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3433 /* If I2 or I3 has multiple SETs, we won't know how to track
3434 register status, so don't use these insns. If I2's destination
3435 is used between I2 and I3, we also can't use these insns. */
3437 if (i2_code_number
>= 0 && i2set
&& i3set
3438 && (next_real_insn (i2
) == i3
3439 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3440 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3442 if (insn_code_number
>= 0)
3445 /* It is possible that both insns now set the destination of I3.
3446 If so, we must show an extra use of it. */
3448 if (insn_code_number
>= 0)
3450 rtx new_i3_dest
= SET_DEST (i3set
);
3451 rtx new_i2_dest
= SET_DEST (i2set
);
3453 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3454 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3455 || GET_CODE (new_i3_dest
) == SUBREG
)
3456 new_i3_dest
= XEXP (new_i3_dest
, 0);
3458 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3459 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3460 || GET_CODE (new_i2_dest
) == SUBREG
)
3461 new_i2_dest
= XEXP (new_i2_dest
, 0);
3463 if (REG_P (new_i3_dest
)
3464 && REG_P (new_i2_dest
)
3465 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3466 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3470 /* If we can split it and use I2DEST, go ahead and see if that
3471 helps things be recognized. Verify that none of the registers
3472 are set between I2 and I3. */
3473 if (insn_code_number
< 0
3474 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3478 /* We need I2DEST in the proper mode. If it is a hard register
3479 or the only use of a pseudo, we can change its mode.
3480 Make sure we don't change a hard register to have a mode that
3481 isn't valid for it, or change the number of registers. */
3482 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3483 || GET_MODE (*split
) == VOIDmode
3484 || can_change_dest_mode (i2dest
, added_sets_2
,
3486 && (next_real_insn (i2
) == i3
3487 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3488 /* We can't overwrite I2DEST if its value is still used by
3490 && ! reg_referenced_p (i2dest
, newpat
))
3492 rtx newdest
= i2dest
;
3493 enum rtx_code split_code
= GET_CODE (*split
);
3494 enum machine_mode split_mode
= GET_MODE (*split
);
3495 bool subst_done
= false;
3496 newi2pat
= NULL_RTX
;
3500 /* *SPLIT may be part of I2SRC, so make sure we have the
3501 original expression around for later debug processing.
3502 We should not need I2SRC any more in other cases. */
3503 if (MAY_HAVE_DEBUG_INSNS
)
3504 i2src
= copy_rtx (i2src
);
3508 /* Get NEWDEST as a register in the proper mode. We have already
3509 validated that we can do this. */
3510 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3512 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3513 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3516 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3517 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3521 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3522 an ASHIFT. This can occur if it was inside a PLUS and hence
3523 appeared to be a memory address. This is a kludge. */
3524 if (split_code
== MULT
3525 && CONST_INT_P (XEXP (*split
, 1))
3526 && INTVAL (XEXP (*split
, 1)) > 0
3527 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3529 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3530 XEXP (*split
, 0), GEN_INT (i
)));
3531 /* Update split_code because we may not have a multiply
3533 split_code
= GET_CODE (*split
);
3536 #ifdef INSN_SCHEDULING
3537 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3538 be written as a ZERO_EXTEND. */
3539 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3541 #ifdef LOAD_EXTEND_OP
3542 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3543 what it really is. */
3544 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3546 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3547 SUBREG_REG (*split
)));
3550 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3551 SUBREG_REG (*split
)));
3555 /* Attempt to split binary operators using arithmetic identities. */
3556 if (BINARY_P (SET_SRC (newpat
))
3557 && split_mode
== GET_MODE (SET_SRC (newpat
))
3558 && ! side_effects_p (SET_SRC (newpat
)))
3560 rtx setsrc
= SET_SRC (newpat
);
3561 enum machine_mode mode
= GET_MODE (setsrc
);
3562 enum rtx_code code
= GET_CODE (setsrc
);
3563 rtx src_op0
= XEXP (setsrc
, 0);
3564 rtx src_op1
= XEXP (setsrc
, 1);
3566 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3567 if (rtx_equal_p (src_op0
, src_op1
))
3569 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3570 SUBST (XEXP (setsrc
, 0), newdest
);
3571 SUBST (XEXP (setsrc
, 1), newdest
);
3574 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3575 else if ((code
== PLUS
|| code
== MULT
)
3576 && GET_CODE (src_op0
) == code
3577 && GET_CODE (XEXP (src_op0
, 0)) == code
3578 && (INTEGRAL_MODE_P (mode
)
3579 || (FLOAT_MODE_P (mode
)
3580 && flag_unsafe_math_optimizations
)))
3582 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3583 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3584 rtx r
= XEXP (src_op0
, 1);
3587 /* Split both "((X op Y) op X) op Y" and
3588 "((X op Y) op Y) op X" as "T op T" where T is
3590 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3591 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3593 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3595 SUBST (XEXP (setsrc
, 0), newdest
);
3596 SUBST (XEXP (setsrc
, 1), newdest
);
3599 /* Split "((X op X) op Y) op Y)" as "T op T" where
3601 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3603 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3604 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3605 SUBST (XEXP (setsrc
, 0), newdest
);
3606 SUBST (XEXP (setsrc
, 1), newdest
);
3614 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3615 SUBST (*split
, newdest
);
3618 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3620 /* recog_for_combine might have added CLOBBERs to newi2pat.
3621 Make sure NEWPAT does not depend on the clobbered regs. */
3622 if (GET_CODE (newi2pat
) == PARALLEL
)
3623 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3624 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3626 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3627 if (reg_overlap_mentioned_p (reg
, newpat
))
3634 /* If the split point was a MULT and we didn't have one before,
3635 don't use one now. */
3636 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3637 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3641 /* Check for a case where we loaded from memory in a narrow mode and
3642 then sign extended it, but we need both registers. In that case,
3643 we have a PARALLEL with both loads from the same memory location.
3644 We can split this into a load from memory followed by a register-register
3645 copy. This saves at least one insn, more if register allocation can
3648 We cannot do this if the destination of the first assignment is a
3649 condition code register or cc0. We eliminate this case by making sure
3650 the SET_DEST and SET_SRC have the same mode.
3652 We cannot do this if the destination of the second assignment is
3653 a register that we have already assumed is zero-extended. Similarly
3654 for a SUBREG of such a register. */
3656 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3657 && GET_CODE (newpat
) == PARALLEL
3658 && XVECLEN (newpat
, 0) == 2
3659 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3660 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3661 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3662 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3663 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3664 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3665 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3666 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3668 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3669 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3670 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3672 && VEC_index (reg_stat_type
, reg_stat
,
3673 REGNO (temp
))->nonzero_bits
!= 0
3674 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3675 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3676 && (VEC_index (reg_stat_type
, reg_stat
,
3677 REGNO (temp
))->nonzero_bits
3678 != GET_MODE_MASK (word_mode
))))
3679 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3680 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3682 && VEC_index (reg_stat_type
, reg_stat
,
3683 REGNO (temp
))->nonzero_bits
!= 0
3684 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3685 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3686 && (VEC_index (reg_stat_type
, reg_stat
,
3687 REGNO (temp
))->nonzero_bits
3688 != GET_MODE_MASK (word_mode
)))))
3689 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3690 SET_SRC (XVECEXP (newpat
, 0, 1)))
3691 && ! find_reg_note (i3
, REG_UNUSED
,
3692 SET_DEST (XVECEXP (newpat
, 0, 0))))
3696 newi2pat
= XVECEXP (newpat
, 0, 0);
3697 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3698 newpat
= XVECEXP (newpat
, 0, 1);
3699 SUBST (SET_SRC (newpat
),
3700 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3701 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3703 if (i2_code_number
>= 0)
3704 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3706 if (insn_code_number
>= 0)
3710 /* Similarly, check for a case where we have a PARALLEL of two independent
3711 SETs but we started with three insns. In this case, we can do the sets
3712 as two separate insns. This case occurs when some SET allows two
3713 other insns to combine, but the destination of that SET is still live. */
3715 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3716 && GET_CODE (newpat
) == PARALLEL
3717 && XVECLEN (newpat
, 0) == 2
3718 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3719 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3720 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3721 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3722 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3723 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3724 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3725 XVECEXP (newpat
, 0, 0))
3726 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3727 XVECEXP (newpat
, 0, 1))
3728 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3729 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3731 /* Normally, it doesn't matter which of the two is done first,
3732 but the one that references cc0 can't be the second, and
3733 one which uses any regs/memory set in between i2 and i3 can't
3735 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3738 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3742 newi2pat
= XVECEXP (newpat
, 0, 1);
3743 newpat
= XVECEXP (newpat
, 0, 0);
3745 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3748 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3752 newi2pat
= XVECEXP (newpat
, 0, 0);
3753 newpat
= XVECEXP (newpat
, 0, 1);
3761 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3763 if (i2_code_number
>= 0)
3765 /* recog_for_combine might have added CLOBBERs to newi2pat.
3766 Make sure NEWPAT does not depend on the clobbered regs. */
3767 if (GET_CODE (newi2pat
) == PARALLEL
)
3769 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3770 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3772 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3773 if (reg_overlap_mentioned_p (reg
, newpat
))
3781 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3785 /* If it still isn't recognized, fail and change things back the way they
3787 if ((insn_code_number
< 0
3788 /* Is the result a reasonable ASM_OPERANDS? */
3789 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3795 /* If we had to change another insn, make sure it is valid also. */
3796 if (undobuf
.other_insn
)
3798 CLEAR_HARD_REG_SET (newpat_used_regs
);
3800 other_pat
= PATTERN (undobuf
.other_insn
);
3801 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3804 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3812 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3813 they are adjacent to each other or not. */
3815 rtx p
= prev_nonnote_insn (i3
);
3816 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3817 && sets_cc0_p (newi2pat
))
3825 /* Only allow this combination if insn_rtx_costs reports that the
3826 replacement instructions are cheaper than the originals. */
3827 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3833 if (MAY_HAVE_DEBUG_INSNS
)
3837 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3838 if (undo
->kind
== UNDO_MODE
)
3840 rtx reg
= *undo
->where
.r
;
3841 enum machine_mode new_mode
= GET_MODE (reg
);
3842 enum machine_mode old_mode
= undo
->old_contents
.m
;
3844 /* Temporarily revert mode back. */
3845 adjust_reg_mode (reg
, old_mode
);
3847 if (reg
== i2dest
&& i2scratch
)
3849 /* If we used i2dest as a scratch register with a
3850 different mode, substitute it for the original
3851 i2src while its original mode is temporarily
3852 restored, and then clear i2scratch so that we don't
3853 do it again later. */
3854 propagate_for_debug (i2
, i3
, reg
, i2src
);
3856 /* Put back the new mode. */
3857 adjust_reg_mode (reg
, new_mode
);
3861 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3872 last
= undobuf
.other_insn
;
3876 /* We're dealing with a reg that changed mode but not
3877 meaning, so we want to turn it into a subreg for
3878 the new mode. However, because of REG sharing and
3879 because its mode had already changed, we have to do
3880 it in two steps. First, replace any debug uses of
3881 reg, with its original mode temporarily restored,
3882 with this copy we have created; then, replace the
3883 copy with the SUBREG of the original shared reg,
3884 once again changed to the new mode. */
3885 propagate_for_debug (first
, last
, reg
, tempreg
);
3886 adjust_reg_mode (reg
, new_mode
);
3887 propagate_for_debug (first
, last
, tempreg
,
3888 lowpart_subreg (old_mode
, reg
, new_mode
));
3893 /* If we will be able to accept this, we have made a
3894 change to the destination of I3. This requires us to
3895 do a few adjustments. */
3897 if (changed_i3_dest
)
3899 PATTERN (i3
) = newpat
;
3900 adjust_for_new_dest (i3
);
3903 /* We now know that we can do this combination. Merge the insns and
3904 update the status of registers and LOG_LINKS. */
3906 if (undobuf
.other_insn
)
3910 PATTERN (undobuf
.other_insn
) = other_pat
;
3912 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3913 are still valid. Then add any non-duplicate notes added by
3914 recog_for_combine. */
3915 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3917 next
= XEXP (note
, 1);
3919 if (REG_NOTE_KIND (note
) == REG_UNUSED
3920 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3921 remove_note (undobuf
.other_insn
, note
);
3924 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3925 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3935 /* I3 now uses what used to be its destination and which is now
3936 I2's destination. This requires us to do a few adjustments. */
3937 PATTERN (i3
) = newpat
;
3938 adjust_for_new_dest (i3
);
3940 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3943 However, some later insn might be using I2's dest and have
3944 a LOG_LINK pointing at I3. We must remove this link.
3945 The simplest way to remove the link is to point it at I1,
3946 which we know will be a NOTE. */
3948 /* newi2pat is usually a SET here; however, recog_for_combine might
3949 have added some clobbers. */
3950 if (GET_CODE (newi2pat
) == PARALLEL
)
3951 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3953 ni2dest
= SET_DEST (newi2pat
);
3955 for (insn
= NEXT_INSN (i3
);
3956 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3957 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3958 insn
= NEXT_INSN (insn
))
3960 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3962 for (link
= LOG_LINKS (insn
); link
;
3963 link
= XEXP (link
, 1))
3964 if (XEXP (link
, 0) == i3
)
3965 XEXP (link
, 0) = i1
;
3973 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3974 rtx i3links
, i2links
, i1links
= 0, i0links
= 0;
3978 /* Compute which registers we expect to eliminate. newi2pat may be setting
3979 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3980 same as i3dest, in which case newi2pat may be setting i1dest. */
3981 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3982 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3985 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3986 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3989 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3990 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3994 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3996 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3997 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3999 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4001 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4003 /* Ensure that we do not have something that should not be shared but
4004 occurs multiple times in the new insns. Check this by first
4005 resetting all the `used' flags and then copying anything is shared. */
4007 reset_used_flags (i3notes
);
4008 reset_used_flags (i2notes
);
4009 reset_used_flags (i1notes
);
4010 reset_used_flags (i0notes
);
4011 reset_used_flags (newpat
);
4012 reset_used_flags (newi2pat
);
4013 if (undobuf
.other_insn
)
4014 reset_used_flags (PATTERN (undobuf
.other_insn
));
4016 i3notes
= copy_rtx_if_shared (i3notes
);
4017 i2notes
= copy_rtx_if_shared (i2notes
);
4018 i1notes
= copy_rtx_if_shared (i1notes
);
4019 i0notes
= copy_rtx_if_shared (i0notes
);
4020 newpat
= copy_rtx_if_shared (newpat
);
4021 newi2pat
= copy_rtx_if_shared (newi2pat
);
4022 if (undobuf
.other_insn
)
4023 reset_used_flags (PATTERN (undobuf
.other_insn
));
4025 INSN_CODE (i3
) = insn_code_number
;
4026 PATTERN (i3
) = newpat
;
4028 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4030 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4032 reset_used_flags (call_usage
);
4033 call_usage
= copy_rtx (call_usage
);
4037 /* I2SRC must still be meaningful at this point. Some splitting
4038 operations can invalidate I2SRC, but those operations do not
4041 replace_rtx (call_usage
, i2dest
, i2src
);
4045 replace_rtx (call_usage
, i1dest
, i1src
);
4047 replace_rtx (call_usage
, i0dest
, i0src
);
4049 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4052 if (undobuf
.other_insn
)
4053 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4055 /* We had one special case above where I2 had more than one set and
4056 we replaced a destination of one of those sets with the destination
4057 of I3. In that case, we have to update LOG_LINKS of insns later
4058 in this basic block. Note that this (expensive) case is rare.
4060 Also, in this case, we must pretend that all REG_NOTEs for I2
4061 actually came from I3, so that REG_UNUSED notes from I2 will be
4062 properly handled. */
4064 if (i3_subst_into_i2
)
4066 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4067 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4068 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4069 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4070 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4071 && ! find_reg_note (i2
, REG_UNUSED
,
4072 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4073 for (temp
= NEXT_INSN (i2
);
4074 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4075 || BB_HEAD (this_basic_block
) != temp
);
4076 temp
= NEXT_INSN (temp
))
4077 if (temp
!= i3
&& INSN_P (temp
))
4078 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
4079 if (XEXP (link
, 0) == i2
)
4080 XEXP (link
, 0) = i3
;
4085 while (XEXP (link
, 1))
4086 link
= XEXP (link
, 1);
4087 XEXP (link
, 1) = i2notes
;
4101 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4102 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4103 INSN_CODE (i2
) = i2_code_number
;
4104 PATTERN (i2
) = newi2pat
;
4108 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4109 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4110 SET_INSN_DELETED (i2
);
4117 if (MAY_HAVE_DEBUG_INSNS
)
4118 propagate_for_debug (i1
, i3
, i1dest
, i1src
);
4119 SET_INSN_DELETED (i1
);
4126 if (MAY_HAVE_DEBUG_INSNS
)
4127 propagate_for_debug (i0
, i3
, i0dest
, i0src
);
4128 SET_INSN_DELETED (i0
);
4131 /* Get death notes for everything that is now used in either I3 or
4132 I2 and used to die in a previous insn. If we built two new
4133 patterns, move from I1 to I2 then I2 to I3 so that we get the
4134 proper movement on registers that I2 modifies. */
4137 from_luid
= DF_INSN_LUID (i0
);
4139 from_luid
= DF_INSN_LUID (i1
);
4141 from_luid
= DF_INSN_LUID (i2
);
4143 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4144 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4146 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4148 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4149 elim_i2
, elim_i1
, elim_i0
);
4151 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4152 elim_i2
, elim_i1
, elim_i0
);
4154 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4155 elim_i2
, elim_i1
, elim_i0
);
4157 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4158 elim_i2
, elim_i1
, elim_i0
);
4160 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4161 elim_i2
, elim_i1
, elim_i0
);
4163 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4164 know these are REG_UNUSED and want them to go to the desired insn,
4165 so we always pass it as i3. */
4167 if (newi2pat
&& new_i2_notes
)
4168 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4172 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4175 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4176 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4177 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4178 in that case, it might delete I2. Similarly for I2 and I1.
4179 Show an additional death due to the REG_DEAD note we make here. If
4180 we discard it in distribute_notes, we will decrement it again. */
4184 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4185 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4187 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4189 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4191 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4192 elim_i2
, elim_i1
, elim_i0
);
4195 if (i2dest_in_i2src
)
4197 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4198 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4199 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4200 NULL_RTX
, NULL_RTX
);
4202 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4203 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4206 if (i1dest_in_i1src
)
4208 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4209 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4210 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4211 NULL_RTX
, NULL_RTX
);
4213 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4214 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4217 if (i0dest_in_i0src
)
4219 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4220 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4221 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4222 NULL_RTX
, NULL_RTX
);
4224 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4225 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4228 distribute_links (i3links
);
4229 distribute_links (i2links
);
4230 distribute_links (i1links
);
4231 distribute_links (i0links
);
4236 rtx i2_insn
= 0, i2_val
= 0, set
;
4238 /* The insn that used to set this register doesn't exist, and
4239 this life of the register may not exist either. See if one of
4240 I3's links points to an insn that sets I2DEST. If it does,
4241 that is now the last known value for I2DEST. If we don't update
4242 this and I2 set the register to a value that depended on its old
4243 contents, we will get confused. If this insn is used, thing
4244 will be set correctly in combine_instructions. */
4246 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4247 if ((set
= single_set (XEXP (link
, 0))) != 0
4248 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4249 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
4251 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4253 /* If the reg formerly set in I2 died only once and that was in I3,
4254 zero its use count so it won't make `reload' do any work. */
4256 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4257 && ! i2dest_in_i2src
)
4259 regno
= REGNO (i2dest
);
4260 INC_REG_N_SETS (regno
, -1);
4264 if (i1
&& REG_P (i1dest
))
4267 rtx i1_insn
= 0, i1_val
= 0, set
;
4269 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4270 if ((set
= single_set (XEXP (link
, 0))) != 0
4271 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4272 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
4274 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4276 regno
= REGNO (i1dest
);
4277 if (! added_sets_1
&& ! i1dest_in_i1src
)
4278 INC_REG_N_SETS (regno
, -1);
4281 if (i0
&& REG_P (i0dest
))
4284 rtx i0_insn
= 0, i0_val
= 0, set
;
4286 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4287 if ((set
= single_set (XEXP (link
, 0))) != 0
4288 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4289 i0_insn
= XEXP (link
, 0), i0_val
= SET_SRC (set
);
4291 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4293 regno
= REGNO (i0dest
);
4294 if (! added_sets_0
&& ! i0dest_in_i0src
)
4295 INC_REG_N_SETS (regno
, -1);
4298 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4299 been made to this insn. The order of
4300 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4301 can affect nonzero_bits of newpat */
4303 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4304 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4307 if (undobuf
.other_insn
!= NULL_RTX
)
4311 fprintf (dump_file
, "modifying other_insn ");
4312 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4314 df_insn_rescan (undobuf
.other_insn
);
4317 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4321 fprintf (dump_file
, "modifying insn i1 ");
4322 dump_insn_slim (dump_file
, i0
);
4324 df_insn_rescan (i0
);
4327 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4331 fprintf (dump_file
, "modifying insn i1 ");
4332 dump_insn_slim (dump_file
, i1
);
4334 df_insn_rescan (i1
);
4337 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4341 fprintf (dump_file
, "modifying insn i2 ");
4342 dump_insn_slim (dump_file
, i2
);
4344 df_insn_rescan (i2
);
4347 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4351 fprintf (dump_file
, "modifying insn i3 ");
4352 dump_insn_slim (dump_file
, i3
);
4354 df_insn_rescan (i3
);
4357 /* Set new_direct_jump_p if a new return or simple jump instruction
4358 has been created. Adjust the CFG accordingly. */
4360 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4362 *new_direct_jump_p
= 1;
4363 mark_jump_label (PATTERN (i3
), i3
, 0);
4364 update_cfg_for_uncondjump (i3
);
4367 if (undobuf
.other_insn
!= NULL_RTX
4368 && (returnjump_p (undobuf
.other_insn
)
4369 || any_uncondjump_p (undobuf
.other_insn
)))
4371 *new_direct_jump_p
= 1;
4372 update_cfg_for_uncondjump (undobuf
.other_insn
);
4375 /* A noop might also need cleaning up of CFG, if it comes from the
4376 simplification of a jump. */
4377 if (GET_CODE (newpat
) == SET
4378 && SET_SRC (newpat
) == pc_rtx
4379 && SET_DEST (newpat
) == pc_rtx
)
4381 *new_direct_jump_p
= 1;
4382 update_cfg_for_uncondjump (i3
);
4385 if (undobuf
.other_insn
!= NULL_RTX
4386 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4387 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4388 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4390 *new_direct_jump_p
= 1;
4391 update_cfg_for_uncondjump (undobuf
.other_insn
);
4394 combine_successes
++;
4397 if (added_links_insn
4398 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4399 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4400 return added_links_insn
;
4402 return newi2pat
? i2
: i3
;
4405 /* Undo all the modifications recorded in undobuf. */
4410 struct undo
*undo
, *next
;
4412 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4418 *undo
->where
.r
= undo
->old_contents
.r
;
4421 *undo
->where
.i
= undo
->old_contents
.i
;
4424 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4430 undo
->next
= undobuf
.frees
;
4431 undobuf
.frees
= undo
;
4437 /* We've committed to accepting the changes we made. Move all
4438 of the undos to the free list. */
4443 struct undo
*undo
, *next
;
4445 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4448 undo
->next
= undobuf
.frees
;
4449 undobuf
.frees
= undo
;
4454 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4455 where we have an arithmetic expression and return that point. LOC will
4458 try_combine will call this function to see if an insn can be split into
4462 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4465 enum rtx_code code
= GET_CODE (x
);
4467 unsigned HOST_WIDE_INT len
= 0;
4468 HOST_WIDE_INT pos
= 0;
4470 rtx inner
= NULL_RTX
;
4472 /* First special-case some codes. */
4476 #ifdef INSN_SCHEDULING
4477 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4479 if (MEM_P (SUBREG_REG (x
)))
4482 return find_split_point (&SUBREG_REG (x
), insn
, false);
4486 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4487 using LO_SUM and HIGH. */
4488 if (GET_CODE (XEXP (x
, 0)) == CONST
4489 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4491 enum machine_mode address_mode
4492 = targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (x
));
4495 gen_rtx_LO_SUM (address_mode
,
4496 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4498 return &XEXP (XEXP (x
, 0), 0);
4502 /* If we have a PLUS whose second operand is a constant and the
4503 address is not valid, perhaps will can split it up using
4504 the machine-specific way to split large constants. We use
4505 the first pseudo-reg (one of the virtual regs) as a placeholder;
4506 it will not remain in the result. */
4507 if (GET_CODE (XEXP (x
, 0)) == PLUS
4508 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4509 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4510 MEM_ADDR_SPACE (x
)))
4512 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4513 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4517 /* This should have produced two insns, each of which sets our
4518 placeholder. If the source of the second is a valid address,
4519 we can make put both sources together and make a split point
4523 && NEXT_INSN (seq
) != NULL_RTX
4524 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4525 && NONJUMP_INSN_P (seq
)
4526 && GET_CODE (PATTERN (seq
)) == SET
4527 && SET_DEST (PATTERN (seq
)) == reg
4528 && ! reg_mentioned_p (reg
,
4529 SET_SRC (PATTERN (seq
)))
4530 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4531 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4532 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4533 && memory_address_addr_space_p
4534 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4535 MEM_ADDR_SPACE (x
)))
4537 rtx src1
= SET_SRC (PATTERN (seq
));
4538 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4540 /* Replace the placeholder in SRC2 with SRC1. If we can
4541 find where in SRC2 it was placed, that can become our
4542 split point and we can replace this address with SRC2.
4543 Just try two obvious places. */
4545 src2
= replace_rtx (src2
, reg
, src1
);
4547 if (XEXP (src2
, 0) == src1
)
4548 split
= &XEXP (src2
, 0);
4549 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4550 && XEXP (XEXP (src2
, 0), 0) == src1
)
4551 split
= &XEXP (XEXP (src2
, 0), 0);
4555 SUBST (XEXP (x
, 0), src2
);
4560 /* If that didn't work, perhaps the first operand is complex and
4561 needs to be computed separately, so make a split point there.
4562 This will occur on machines that just support REG + CONST
4563 and have a constant moved through some previous computation. */
4565 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4566 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4567 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4568 return &XEXP (XEXP (x
, 0), 0);
4571 /* If we have a PLUS whose first operand is complex, try computing it
4572 separately by making a split there. */
4573 if (GET_CODE (XEXP (x
, 0)) == PLUS
4574 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4576 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4577 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4578 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4579 return &XEXP (XEXP (x
, 0), 0);
4584 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4585 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4586 we need to put the operand into a register. So split at that
4589 if (SET_DEST (x
) == cc0_rtx
4590 && GET_CODE (SET_SRC (x
)) != COMPARE
4591 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4592 && !OBJECT_P (SET_SRC (x
))
4593 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4594 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4595 return &SET_SRC (x
);
4598 /* See if we can split SET_SRC as it stands. */
4599 split
= find_split_point (&SET_SRC (x
), insn
, true);
4600 if (split
&& split
!= &SET_SRC (x
))
4603 /* See if we can split SET_DEST as it stands. */
4604 split
= find_split_point (&SET_DEST (x
), insn
, false);
4605 if (split
&& split
!= &SET_DEST (x
))
4608 /* See if this is a bitfield assignment with everything constant. If
4609 so, this is an IOR of an AND, so split it into that. */
4610 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4611 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4612 <= HOST_BITS_PER_WIDE_INT
)
4613 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4614 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4615 && CONST_INT_P (SET_SRC (x
))
4616 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4617 + INTVAL (XEXP (SET_DEST (x
), 2)))
4618 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4619 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4621 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4622 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4623 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4624 rtx dest
= XEXP (SET_DEST (x
), 0);
4625 enum machine_mode mode
= GET_MODE (dest
);
4626 unsigned HOST_WIDE_INT mask
4627 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4630 if (BITS_BIG_ENDIAN
)
4631 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4633 or_mask
= gen_int_mode (src
<< pos
, mode
);
4636 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4639 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4641 simplify_gen_binary (IOR
, mode
,
4642 simplify_gen_binary (AND
, mode
,
4647 SUBST (SET_DEST (x
), dest
);
4649 split
= find_split_point (&SET_SRC (x
), insn
, true);
4650 if (split
&& split
!= &SET_SRC (x
))
4654 /* Otherwise, see if this is an operation that we can split into two.
4655 If so, try to split that. */
4656 code
= GET_CODE (SET_SRC (x
));
4661 /* If we are AND'ing with a large constant that is only a single
4662 bit and the result is only being used in a context where we
4663 need to know if it is zero or nonzero, replace it with a bit
4664 extraction. This will avoid the large constant, which might
4665 have taken more than one insn to make. If the constant were
4666 not a valid argument to the AND but took only one insn to make,
4667 this is no worse, but if it took more than one insn, it will
4670 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4671 && REG_P (XEXP (SET_SRC (x
), 0))
4672 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4673 && REG_P (SET_DEST (x
))
4674 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4675 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4676 && XEXP (*split
, 0) == SET_DEST (x
)
4677 && XEXP (*split
, 1) == const0_rtx
)
4679 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4680 XEXP (SET_SRC (x
), 0),
4681 pos
, NULL_RTX
, 1, 1, 0, 0);
4682 if (extraction
!= 0)
4684 SUBST (SET_SRC (x
), extraction
);
4685 return find_split_point (loc
, insn
, false);
4691 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4692 is known to be on, this can be converted into a NEG of a shift. */
4693 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4694 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4695 && 1 <= (pos
= exact_log2
4696 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4697 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4699 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4703 gen_rtx_LSHIFTRT (mode
,
4704 XEXP (SET_SRC (x
), 0),
4707 split
= find_split_point (&SET_SRC (x
), insn
, true);
4708 if (split
&& split
!= &SET_SRC (x
))
4714 inner
= XEXP (SET_SRC (x
), 0);
4716 /* We can't optimize if either mode is a partial integer
4717 mode as we don't know how many bits are significant
4719 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4720 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4724 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4730 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4731 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4733 inner
= XEXP (SET_SRC (x
), 0);
4734 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4735 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4737 if (BITS_BIG_ENDIAN
)
4738 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4739 unsignedp
= (code
== ZERO_EXTRACT
);
4747 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4749 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4751 /* For unsigned, we have a choice of a shift followed by an
4752 AND or two shifts. Use two shifts for field sizes where the
4753 constant might be too large. We assume here that we can
4754 always at least get 8-bit constants in an AND insn, which is
4755 true for every current RISC. */
4757 if (unsignedp
&& len
<= 8)
4762 (mode
, gen_lowpart (mode
, inner
),
4764 GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
)
4767 split
= find_split_point (&SET_SRC (x
), insn
, true);
4768 if (split
&& split
!= &SET_SRC (x
))
4775 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4776 gen_rtx_ASHIFT (mode
,
4777 gen_lowpart (mode
, inner
),
4778 GEN_INT (GET_MODE_BITSIZE (mode
)
4780 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4782 split
= find_split_point (&SET_SRC (x
), insn
, true);
4783 if (split
&& split
!= &SET_SRC (x
))
4788 /* See if this is a simple operation with a constant as the second
4789 operand. It might be that this constant is out of range and hence
4790 could be used as a split point. */
4791 if (BINARY_P (SET_SRC (x
))
4792 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4793 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4794 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4795 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4796 return &XEXP (SET_SRC (x
), 1);
4798 /* Finally, see if this is a simple operation with its first operand
4799 not in a register. The operation might require this operand in a
4800 register, so return it as a split point. We can always do this
4801 because if the first operand were another operation, we would have
4802 already found it as a split point. */
4803 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4804 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4805 return &XEXP (SET_SRC (x
), 0);
4811 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4812 it is better to write this as (not (ior A B)) so we can split it.
4813 Similarly for IOR. */
4814 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4817 gen_rtx_NOT (GET_MODE (x
),
4818 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4820 XEXP (XEXP (x
, 0), 0),
4821 XEXP (XEXP (x
, 1), 0))));
4822 return find_split_point (loc
, insn
, set_src
);
4825 /* Many RISC machines have a large set of logical insns. If the
4826 second operand is a NOT, put it first so we will try to split the
4827 other operand first. */
4828 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4830 rtx tem
= XEXP (x
, 0);
4831 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4832 SUBST (XEXP (x
, 1), tem
);
4838 /* Canonicalization can produce (minus A (mult B C)), where C is a
4839 constant. It may be better to try splitting (plus (mult B -C) A)
4840 instead if this isn't a multiply by a power of two. */
4841 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4842 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4843 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4845 enum machine_mode mode
= GET_MODE (x
);
4846 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4847 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4848 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4849 XEXP (XEXP (x
, 1), 0),
4850 GEN_INT (other_int
)),
4852 return find_split_point (loc
, insn
, set_src
);
4855 /* Split at a multiply-accumulate instruction. However if this is
4856 the SET_SRC, we likely do not have such an instruction and it's
4857 worthless to try this split. */
4858 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4865 /* Otherwise, select our actions depending on our rtx class. */
4866 switch (GET_RTX_CLASS (code
))
4868 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4870 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4873 /* ... fall through ... */
4875 case RTX_COMM_ARITH
:
4877 case RTX_COMM_COMPARE
:
4878 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4881 /* ... fall through ... */
4883 /* Some machines have (and (shift ...) ...) insns. If X is not
4884 an AND, but XEXP (X, 0) is, use it as our split point. */
4885 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4886 return &XEXP (x
, 0);
4888 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4894 /* Otherwise, we don't have a split point. */
4899 /* Throughout X, replace FROM with TO, and return the result.
4900 The result is TO if X is FROM;
4901 otherwise the result is X, but its contents may have been modified.
4902 If they were modified, a record was made in undobuf so that
4903 undo_all will (among other things) return X to its original state.
4905 If the number of changes necessary is too much to record to undo,
4906 the excess changes are not made, so the result is invalid.
4907 The changes already made can still be undone.
4908 undobuf.num_undo is incremented for such changes, so by testing that
4909 the caller can tell whether the result is valid.
4911 `n_occurrences' is incremented each time FROM is replaced.
4913 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4915 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4916 by copying if `n_occurrences' is nonzero. */
4919 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4921 enum rtx_code code
= GET_CODE (x
);
4922 enum machine_mode op0_mode
= VOIDmode
;
4927 /* Two expressions are equal if they are identical copies of a shared
4928 RTX or if they are both registers with the same register number
4931 #define COMBINE_RTX_EQUAL_P(X,Y) \
4933 || (REG_P (X) && REG_P (Y) \
4934 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4936 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4939 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4942 /* If X and FROM are the same register but different modes, they
4943 will not have been seen as equal above. However, the log links code
4944 will make a LOG_LINKS entry for that case. If we do nothing, we
4945 will try to rerecognize our original insn and, when it succeeds,
4946 we will delete the feeding insn, which is incorrect.
4948 So force this insn not to match in this (rare) case. */
4949 if (! in_dest
&& code
== REG
&& REG_P (from
)
4950 && reg_overlap_mentioned_p (x
, from
))
4951 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4953 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4954 of which may contain things that can be combined. */
4955 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4958 /* It is possible to have a subexpression appear twice in the insn.
4959 Suppose that FROM is a register that appears within TO.
4960 Then, after that subexpression has been scanned once by `subst',
4961 the second time it is scanned, TO may be found. If we were
4962 to scan TO here, we would find FROM within it and create a
4963 self-referent rtl structure which is completely wrong. */
4964 if (COMBINE_RTX_EQUAL_P (x
, to
))
4967 /* Parallel asm_operands need special attention because all of the
4968 inputs are shared across the arms. Furthermore, unsharing the
4969 rtl results in recognition failures. Failure to handle this case
4970 specially can result in circular rtl.
4972 Solve this by doing a normal pass across the first entry of the
4973 parallel, and only processing the SET_DESTs of the subsequent
4976 if (code
== PARALLEL
4977 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4978 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4980 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4982 /* If this substitution failed, this whole thing fails. */
4983 if (GET_CODE (new_rtx
) == CLOBBER
4984 && XEXP (new_rtx
, 0) == const0_rtx
)
4987 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4989 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4991 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4994 && GET_CODE (dest
) != CC0
4995 && GET_CODE (dest
) != PC
)
4997 new_rtx
= subst (dest
, from
, to
, 0, unique_copy
);
4999 /* If this substitution failed, this whole thing fails. */
5000 if (GET_CODE (new_rtx
) == CLOBBER
5001 && XEXP (new_rtx
, 0) == const0_rtx
)
5004 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5010 len
= GET_RTX_LENGTH (code
);
5011 fmt
= GET_RTX_FORMAT (code
);
5013 /* We don't need to process a SET_DEST that is a register, CC0,
5014 or PC, so set up to skip this common case. All other cases
5015 where we want to suppress replacing something inside a
5016 SET_SRC are handled via the IN_DEST operand. */
5018 && (REG_P (SET_DEST (x
))
5019 || GET_CODE (SET_DEST (x
)) == CC0
5020 || GET_CODE (SET_DEST (x
)) == PC
))
5023 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5026 op0_mode
= GET_MODE (XEXP (x
, 0));
5028 for (i
= 0; i
< len
; i
++)
5033 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5035 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5037 new_rtx
= (unique_copy
&& n_occurrences
5038 ? copy_rtx (to
) : to
);
5043 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0,
5046 /* If this substitution failed, this whole thing
5048 if (GET_CODE (new_rtx
) == CLOBBER
5049 && XEXP (new_rtx
, 0) == const0_rtx
)
5053 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5056 else if (fmt
[i
] == 'e')
5058 /* If this is a register being set, ignore it. */
5059 new_rtx
= XEXP (x
, i
);
5062 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5064 || code
== STRICT_LOW_PART
))
5067 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5069 /* In general, don't install a subreg involving two
5070 modes not tieable. It can worsen register
5071 allocation, and can even make invalid reload
5072 insns, since the reg inside may need to be copied
5073 from in the outside mode, and that may be invalid
5074 if it is an fp reg copied in integer mode.
5076 We allow two exceptions to this: It is valid if
5077 it is inside another SUBREG and the mode of that
5078 SUBREG and the mode of the inside of TO is
5079 tieable and it is valid if X is a SET that copies
5082 if (GET_CODE (to
) == SUBREG
5083 && ! MODES_TIEABLE_P (GET_MODE (to
),
5084 GET_MODE (SUBREG_REG (to
)))
5085 && ! (code
== SUBREG
5086 && MODES_TIEABLE_P (GET_MODE (x
),
5087 GET_MODE (SUBREG_REG (to
))))
5089 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5092 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5094 #ifdef CANNOT_CHANGE_MODE_CLASS
5097 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5098 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5101 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5104 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5108 /* If we are in a SET_DEST, suppress most cases unless we
5109 have gone inside a MEM, in which case we want to
5110 simplify the address. We assume here that things that
5111 are actually part of the destination have their inner
5112 parts in the first expression. This is true for SUBREG,
5113 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5114 things aside from REG and MEM that should appear in a
5116 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5118 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5119 || code
== ZERO_EXTRACT
))
5121 && i
== 0), unique_copy
);
5123 /* If we found that we will have to reject this combination,
5124 indicate that by returning the CLOBBER ourselves, rather than
5125 an expression containing it. This will speed things up as
5126 well as prevent accidents where two CLOBBERs are considered
5127 to be equal, thus producing an incorrect simplification. */
5129 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5132 if (GET_CODE (x
) == SUBREG
5133 && (CONST_INT_P (new_rtx
)
5134 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
5136 enum machine_mode mode
= GET_MODE (x
);
5138 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5139 GET_MODE (SUBREG_REG (x
)),
5142 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5144 else if (CONST_INT_P (new_rtx
)
5145 && GET_CODE (x
) == ZERO_EXTEND
)
5147 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5148 new_rtx
, GET_MODE (XEXP (x
, 0)));
5152 SUBST (XEXP (x
, i
), new_rtx
);
5157 /* Check if we are loading something from the constant pool via float
5158 extension; in this case we would undo compress_float_constant
5159 optimization and degenerate constant load to an immediate value. */
5160 if (GET_CODE (x
) == FLOAT_EXTEND
5161 && MEM_P (XEXP (x
, 0))
5162 && MEM_READONLY_P (XEXP (x
, 0)))
5164 rtx tmp
= avoid_constant_pool_reference (x
);
5169 /* Try to simplify X. If the simplification changed the code, it is likely
5170 that further simplification will help, so loop, but limit the number
5171 of repetitions that will be performed. */
5173 for (i
= 0; i
< 4; i
++)
5175 /* If X is sufficiently simple, don't bother trying to do anything
5177 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5178 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
5180 if (GET_CODE (x
) == code
)
5183 code
= GET_CODE (x
);
5185 /* We no longer know the original mode of operand 0 since we
5186 have changed the form of X) */
5187 op0_mode
= VOIDmode
;
5193 /* Simplify X, a piece of RTL. We just operate on the expression at the
5194 outer level; call `subst' to simplify recursively. Return the new
5197 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5198 if we are inside a SET_DEST. */
5201 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
5203 enum rtx_code code
= GET_CODE (x
);
5204 enum machine_mode mode
= GET_MODE (x
);
5208 /* If this is a commutative operation, put a constant last and a complex
5209 expression first. We don't need to do this for comparisons here. */
5210 if (COMMUTATIVE_ARITH_P (x
)
5211 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5214 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5215 SUBST (XEXP (x
, 1), temp
);
5218 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5219 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5220 things. Check for cases where both arms are testing the same
5223 Don't do anything if all operands are very simple. */
5226 && ((!OBJECT_P (XEXP (x
, 0))
5227 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5228 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5229 || (!OBJECT_P (XEXP (x
, 1))
5230 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5231 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5233 && (!OBJECT_P (XEXP (x
, 0))
5234 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5235 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5237 rtx cond
, true_rtx
, false_rtx
;
5239 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5241 /* If everything is a comparison, what we have is highly unlikely
5242 to be simpler, so don't use it. */
5243 && ! (COMPARISON_P (x
)
5244 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5246 rtx cop1
= const0_rtx
;
5247 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5249 if (cond_code
== NE
&& COMPARISON_P (cond
))
5252 /* Simplify the alternative arms; this may collapse the true and
5253 false arms to store-flag values. Be careful to use copy_rtx
5254 here since true_rtx or false_rtx might share RTL with x as a
5255 result of the if_then_else_cond call above. */
5256 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5257 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5259 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5260 is unlikely to be simpler. */
5261 if (general_operand (true_rtx
, VOIDmode
)
5262 && general_operand (false_rtx
, VOIDmode
))
5264 enum rtx_code reversed
;
5266 /* Restarting if we generate a store-flag expression will cause
5267 us to loop. Just drop through in this case. */
5269 /* If the result values are STORE_FLAG_VALUE and zero, we can
5270 just make the comparison operation. */
5271 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5272 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5274 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5275 && ((reversed
= reversed_comparison_code_parts
5276 (cond_code
, cond
, cop1
, NULL
))
5278 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5281 /* Likewise, we can make the negate of a comparison operation
5282 if the result values are - STORE_FLAG_VALUE and zero. */
5283 else if (CONST_INT_P (true_rtx
)
5284 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5285 && false_rtx
== const0_rtx
)
5286 x
= simplify_gen_unary (NEG
, mode
,
5287 simplify_gen_relational (cond_code
,
5291 else if (CONST_INT_P (false_rtx
)
5292 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5293 && true_rtx
== const0_rtx
5294 && ((reversed
= reversed_comparison_code_parts
5295 (cond_code
, cond
, cop1
, NULL
))
5297 x
= simplify_gen_unary (NEG
, mode
,
5298 simplify_gen_relational (reversed
,
5303 return gen_rtx_IF_THEN_ELSE (mode
,
5304 simplify_gen_relational (cond_code
,
5309 true_rtx
, false_rtx
);
5311 code
= GET_CODE (x
);
5312 op0_mode
= VOIDmode
;
5317 /* Try to fold this expression in case we have constants that weren't
5320 switch (GET_RTX_CLASS (code
))
5323 if (op0_mode
== VOIDmode
)
5324 op0_mode
= GET_MODE (XEXP (x
, 0));
5325 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5328 case RTX_COMM_COMPARE
:
5330 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5331 if (cmp_mode
== VOIDmode
)
5333 cmp_mode
= GET_MODE (XEXP (x
, 1));
5334 if (cmp_mode
== VOIDmode
)
5335 cmp_mode
= op0_mode
;
5337 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5338 XEXP (x
, 0), XEXP (x
, 1));
5341 case RTX_COMM_ARITH
:
5343 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5345 case RTX_BITFIELD_OPS
:
5347 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5348 XEXP (x
, 1), XEXP (x
, 2));
5357 code
= GET_CODE (temp
);
5358 op0_mode
= VOIDmode
;
5359 mode
= GET_MODE (temp
);
5362 /* First see if we can apply the inverse distributive law. */
5363 if (code
== PLUS
|| code
== MINUS
5364 || code
== AND
|| code
== IOR
|| code
== XOR
)
5366 x
= apply_distributive_law (x
);
5367 code
= GET_CODE (x
);
5368 op0_mode
= VOIDmode
;
5371 /* If CODE is an associative operation not otherwise handled, see if we
5372 can associate some operands. This can win if they are constants or
5373 if they are logically related (i.e. (a & b) & a). */
5374 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5375 || code
== AND
|| code
== IOR
|| code
== XOR
5376 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5377 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5378 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5380 if (GET_CODE (XEXP (x
, 0)) == code
)
5382 rtx other
= XEXP (XEXP (x
, 0), 0);
5383 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5384 rtx inner_op1
= XEXP (x
, 1);
5387 /* Make sure we pass the constant operand if any as the second
5388 one if this is a commutative operation. */
5389 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5391 rtx tem
= inner_op0
;
5392 inner_op0
= inner_op1
;
5395 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5396 : code
== DIV
? MULT
5398 mode
, inner_op0
, inner_op1
);
5400 /* For commutative operations, try the other pair if that one
5402 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5404 other
= XEXP (XEXP (x
, 0), 1);
5405 inner
= simplify_binary_operation (code
, mode
,
5406 XEXP (XEXP (x
, 0), 0),
5411 return simplify_gen_binary (code
, mode
, other
, inner
);
5415 /* A little bit of algebraic simplification here. */
5419 /* Ensure that our address has any ASHIFTs converted to MULT in case
5420 address-recognizing predicates are called later. */
5421 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5422 SUBST (XEXP (x
, 0), temp
);
5426 if (op0_mode
== VOIDmode
)
5427 op0_mode
= GET_MODE (SUBREG_REG (x
));
5429 /* See if this can be moved to simplify_subreg. */
5430 if (CONSTANT_P (SUBREG_REG (x
))
5431 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5432 /* Don't call gen_lowpart if the inner mode
5433 is VOIDmode and we cannot simplify it, as SUBREG without
5434 inner mode is invalid. */
5435 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5436 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5437 return gen_lowpart (mode
, SUBREG_REG (x
));
5439 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5443 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5449 /* Don't change the mode of the MEM if that would change the meaning
5451 if (MEM_P (SUBREG_REG (x
))
5452 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5453 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5454 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5456 /* Note that we cannot do any narrowing for non-constants since
5457 we might have been counting on using the fact that some bits were
5458 zero. We now do this in the SET. */
5463 temp
= expand_compound_operation (XEXP (x
, 0));
5465 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5466 replaced by (lshiftrt X C). This will convert
5467 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5469 if (GET_CODE (temp
) == ASHIFTRT
5470 && CONST_INT_P (XEXP (temp
, 1))
5471 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5472 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5473 INTVAL (XEXP (temp
, 1)));
5475 /* If X has only a single bit that might be nonzero, say, bit I, convert
5476 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5477 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5478 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5479 or a SUBREG of one since we'd be making the expression more
5480 complex if it was just a register. */
5483 && ! (GET_CODE (temp
) == SUBREG
5484 && REG_P (SUBREG_REG (temp
)))
5485 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5487 rtx temp1
= simplify_shift_const
5488 (NULL_RTX
, ASHIFTRT
, mode
,
5489 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5490 GET_MODE_BITSIZE (mode
) - 1 - i
),
5491 GET_MODE_BITSIZE (mode
) - 1 - i
);
5493 /* If all we did was surround TEMP with the two shifts, we
5494 haven't improved anything, so don't use it. Otherwise,
5495 we are better off with TEMP1. */
5496 if (GET_CODE (temp1
) != ASHIFTRT
5497 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5498 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5504 /* We can't handle truncation to a partial integer mode here
5505 because we don't know the real bitsize of the partial
5507 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5510 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5512 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5513 GET_MODE_MASK (mode
), 0));
5515 /* We can truncate a constant value and return it. */
5516 if (CONST_INT_P (XEXP (x
, 0)))
5517 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5519 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5520 whose value is a comparison can be replaced with a subreg if
5521 STORE_FLAG_VALUE permits. */
5522 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5523 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5524 && (temp
= get_last_value (XEXP (x
, 0)))
5525 && COMPARISON_P (temp
))
5526 return gen_lowpart (mode
, XEXP (x
, 0));
5530 /* (const (const X)) can become (const X). Do it this way rather than
5531 returning the inner CONST since CONST can be shared with a
5533 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5534 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5539 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5540 can add in an offset. find_split_point will split this address up
5541 again if it doesn't match. */
5542 if (GET_CODE (XEXP (x
, 0)) == HIGH
5543 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5549 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5550 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5551 bit-field and can be replaced by either a sign_extend or a
5552 sign_extract. The `and' may be a zero_extend and the two
5553 <c>, -<c> constants may be reversed. */
5554 if (GET_CODE (XEXP (x
, 0)) == XOR
5555 && CONST_INT_P (XEXP (x
, 1))
5556 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5557 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5558 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5559 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5560 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5561 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5562 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5563 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5564 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5565 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5566 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5567 == (unsigned int) i
+ 1))))
5568 return simplify_shift_const
5569 (NULL_RTX
, ASHIFTRT
, mode
,
5570 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5571 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5572 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
5573 GET_MODE_BITSIZE (mode
) - (i
+ 1));
5575 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5576 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5577 the bitsize of the mode - 1. This allows simplification of
5578 "a = (b & 8) == 0;" */
5579 if (XEXP (x
, 1) == constm1_rtx
5580 && !REG_P (XEXP (x
, 0))
5581 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5582 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5583 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5584 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5585 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5586 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5587 GET_MODE_BITSIZE (mode
) - 1),
5588 GET_MODE_BITSIZE (mode
) - 1);
5590 /* If we are adding two things that have no bits in common, convert
5591 the addition into an IOR. This will often be further simplified,
5592 for example in cases like ((a & 1) + (a & 2)), which can
5595 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5596 && (nonzero_bits (XEXP (x
, 0), mode
)
5597 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5599 /* Try to simplify the expression further. */
5600 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5601 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
5603 /* If we could, great. If not, do not go ahead with the IOR
5604 replacement, since PLUS appears in many special purpose
5605 address arithmetic instructions. */
5606 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
5612 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5613 (and <foo> (const_int pow2-1)) */
5614 if (GET_CODE (XEXP (x
, 1)) == AND
5615 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5616 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5617 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5618 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5619 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5623 /* If we have (mult (plus A B) C), apply the distributive law and then
5624 the inverse distributive law to see if things simplify. This
5625 occurs mostly in addresses, often when unrolling loops. */
5627 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5629 rtx result
= distribute_and_simplify_rtx (x
, 0);
5634 /* Try simplify a*(b/c) as (a*b)/c. */
5635 if (FLOAT_MODE_P (mode
) && flag_associative_math
5636 && GET_CODE (XEXP (x
, 0)) == DIV
)
5638 rtx tem
= simplify_binary_operation (MULT
, mode
,
5639 XEXP (XEXP (x
, 0), 0),
5642 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5647 /* If this is a divide by a power of two, treat it as a shift if
5648 its first operand is a shift. */
5649 if (CONST_INT_P (XEXP (x
, 1))
5650 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5651 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5652 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5653 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5654 || GET_CODE (XEXP (x
, 0)) == ROTATE
5655 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5656 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5660 case GT
: case GTU
: case GE
: case GEU
:
5661 case LT
: case LTU
: case LE
: case LEU
:
5662 case UNEQ
: case LTGT
:
5663 case UNGT
: case UNGE
:
5664 case UNLT
: case UNLE
:
5665 case UNORDERED
: case ORDERED
:
5666 /* If the first operand is a condition code, we can't do anything
5668 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5669 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5670 && ! CC0_P (XEXP (x
, 0))))
5672 rtx op0
= XEXP (x
, 0);
5673 rtx op1
= XEXP (x
, 1);
5674 enum rtx_code new_code
;
5676 if (GET_CODE (op0
) == COMPARE
)
5677 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5679 /* Simplify our comparison, if possible. */
5680 new_code
= simplify_comparison (code
, &op0
, &op1
);
5682 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5683 if only the low-order bit is possibly nonzero in X (such as when
5684 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5685 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5686 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5689 Remove any ZERO_EXTRACT we made when thinking this was a
5690 comparison. It may now be simpler to use, e.g., an AND. If a
5691 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5692 the call to make_compound_operation in the SET case. */
5694 if (STORE_FLAG_VALUE
== 1
5695 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5696 && op1
== const0_rtx
5697 && mode
== GET_MODE (op0
)
5698 && nonzero_bits (op0
, mode
) == 1)
5699 return gen_lowpart (mode
,
5700 expand_compound_operation (op0
));
5702 else if (STORE_FLAG_VALUE
== 1
5703 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5704 && op1
== const0_rtx
5705 && mode
== GET_MODE (op0
)
5706 && (num_sign_bit_copies (op0
, mode
)
5707 == GET_MODE_BITSIZE (mode
)))
5709 op0
= expand_compound_operation (op0
);
5710 return simplify_gen_unary (NEG
, mode
,
5711 gen_lowpart (mode
, op0
),
5715 else if (STORE_FLAG_VALUE
== 1
5716 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5717 && op1
== const0_rtx
5718 && mode
== GET_MODE (op0
)
5719 && nonzero_bits (op0
, mode
) == 1)
5721 op0
= expand_compound_operation (op0
);
5722 return simplify_gen_binary (XOR
, mode
,
5723 gen_lowpart (mode
, op0
),
5727 else if (STORE_FLAG_VALUE
== 1
5728 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5729 && op1
== const0_rtx
5730 && mode
== GET_MODE (op0
)
5731 && (num_sign_bit_copies (op0
, mode
)
5732 == GET_MODE_BITSIZE (mode
)))
5734 op0
= expand_compound_operation (op0
);
5735 return plus_constant (gen_lowpart (mode
, op0
), 1);
5738 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5740 if (STORE_FLAG_VALUE
== -1
5741 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5742 && op1
== const0_rtx
5743 && (num_sign_bit_copies (op0
, mode
)
5744 == GET_MODE_BITSIZE (mode
)))
5745 return gen_lowpart (mode
,
5746 expand_compound_operation (op0
));
5748 else if (STORE_FLAG_VALUE
== -1
5749 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5750 && op1
== const0_rtx
5751 && mode
== GET_MODE (op0
)
5752 && nonzero_bits (op0
, mode
) == 1)
5754 op0
= expand_compound_operation (op0
);
5755 return simplify_gen_unary (NEG
, mode
,
5756 gen_lowpart (mode
, op0
),
5760 else if (STORE_FLAG_VALUE
== -1
5761 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5762 && op1
== const0_rtx
5763 && mode
== GET_MODE (op0
)
5764 && (num_sign_bit_copies (op0
, mode
)
5765 == GET_MODE_BITSIZE (mode
)))
5767 op0
= expand_compound_operation (op0
);
5768 return simplify_gen_unary (NOT
, mode
,
5769 gen_lowpart (mode
, op0
),
5773 /* If X is 0/1, (eq X 0) is X-1. */
5774 else if (STORE_FLAG_VALUE
== -1
5775 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5776 && op1
== const0_rtx
5777 && mode
== GET_MODE (op0
)
5778 && nonzero_bits (op0
, mode
) == 1)
5780 op0
= expand_compound_operation (op0
);
5781 return plus_constant (gen_lowpart (mode
, op0
), -1);
5784 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5785 one bit that might be nonzero, we can convert (ne x 0) to
5786 (ashift x c) where C puts the bit in the sign bit. Remove any
5787 AND with STORE_FLAG_VALUE when we are done, since we are only
5788 going to test the sign bit. */
5789 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5790 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5791 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5792 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5793 && op1
== const0_rtx
5794 && mode
== GET_MODE (op0
)
5795 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5797 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5798 expand_compound_operation (op0
),
5799 GET_MODE_BITSIZE (mode
) - 1 - i
);
5800 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5806 /* If the code changed, return a whole new comparison. */
5807 if (new_code
!= code
)
5808 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5810 /* Otherwise, keep this operation, but maybe change its operands.
5811 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5812 SUBST (XEXP (x
, 0), op0
);
5813 SUBST (XEXP (x
, 1), op1
);
5818 return simplify_if_then_else (x
);
5824 /* If we are processing SET_DEST, we are done. */
5828 return expand_compound_operation (x
);
5831 return simplify_set (x
);
5835 return simplify_logical (x
);
5842 /* If this is a shift by a constant amount, simplify it. */
5843 if (CONST_INT_P (XEXP (x
, 1)))
5844 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5845 INTVAL (XEXP (x
, 1)));
5847 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5849 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5850 ((unsigned HOST_WIDE_INT
) 1
5851 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5863 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5866 simplify_if_then_else (rtx x
)
5868 enum machine_mode mode
= GET_MODE (x
);
5869 rtx cond
= XEXP (x
, 0);
5870 rtx true_rtx
= XEXP (x
, 1);
5871 rtx false_rtx
= XEXP (x
, 2);
5872 enum rtx_code true_code
= GET_CODE (cond
);
5873 int comparison_p
= COMPARISON_P (cond
);
5876 enum rtx_code false_code
;
5879 /* Simplify storing of the truth value. */
5880 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5881 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5882 XEXP (cond
, 0), XEXP (cond
, 1));
5884 /* Also when the truth value has to be reversed. */
5886 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5887 && (reversed
= reversed_comparison (cond
, mode
)))
5890 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5891 in it is being compared against certain values. Get the true and false
5892 comparisons and see if that says anything about the value of each arm. */
5895 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5897 && REG_P (XEXP (cond
, 0)))
5900 rtx from
= XEXP (cond
, 0);
5901 rtx true_val
= XEXP (cond
, 1);
5902 rtx false_val
= true_val
;
5905 /* If FALSE_CODE is EQ, swap the codes and arms. */
5907 if (false_code
== EQ
)
5909 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5910 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5913 /* If we are comparing against zero and the expression being tested has
5914 only a single bit that might be nonzero, that is its value when it is
5915 not equal to zero. Similarly if it is known to be -1 or 0. */
5917 if (true_code
== EQ
&& true_val
== const0_rtx
5918 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5921 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5923 else if (true_code
== EQ
&& true_val
== const0_rtx
5924 && (num_sign_bit_copies (from
, GET_MODE (from
))
5925 == GET_MODE_BITSIZE (GET_MODE (from
))))
5928 false_val
= constm1_rtx
;
5931 /* Now simplify an arm if we know the value of the register in the
5932 branch and it is used in the arm. Be careful due to the potential
5933 of locally-shared RTL. */
5935 if (reg_mentioned_p (from
, true_rtx
))
5936 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5938 pc_rtx
, pc_rtx
, 0, 0);
5939 if (reg_mentioned_p (from
, false_rtx
))
5940 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5942 pc_rtx
, pc_rtx
, 0, 0);
5944 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5945 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5947 true_rtx
= XEXP (x
, 1);
5948 false_rtx
= XEXP (x
, 2);
5949 true_code
= GET_CODE (cond
);
5952 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5953 reversed, do so to avoid needing two sets of patterns for
5954 subtract-and-branch insns. Similarly if we have a constant in the true
5955 arm, the false arm is the same as the first operand of the comparison, or
5956 the false arm is more complicated than the true arm. */
5959 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5960 && (true_rtx
== pc_rtx
5961 || (CONSTANT_P (true_rtx
)
5962 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5963 || true_rtx
== const0_rtx
5964 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5965 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5966 && !OBJECT_P (false_rtx
))
5967 || reg_mentioned_p (true_rtx
, false_rtx
)
5968 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5970 true_code
= reversed_comparison_code (cond
, NULL
);
5971 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5972 SUBST (XEXP (x
, 1), false_rtx
);
5973 SUBST (XEXP (x
, 2), true_rtx
);
5975 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5978 /* It is possible that the conditional has been simplified out. */
5979 true_code
= GET_CODE (cond
);
5980 comparison_p
= COMPARISON_P (cond
);
5983 /* If the two arms are identical, we don't need the comparison. */
5985 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5988 /* Convert a == b ? b : a to "a". */
5989 if (true_code
== EQ
&& ! side_effects_p (cond
)
5990 && !HONOR_NANS (mode
)
5991 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5992 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5994 else if (true_code
== NE
&& ! side_effects_p (cond
)
5995 && !HONOR_NANS (mode
)
5996 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5997 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6000 /* Look for cases where we have (abs x) or (neg (abs X)). */
6002 if (GET_MODE_CLASS (mode
) == MODE_INT
6004 && XEXP (cond
, 1) == const0_rtx
6005 && GET_CODE (false_rtx
) == NEG
6006 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6007 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6008 && ! side_effects_p (true_rtx
))
6013 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6017 simplify_gen_unary (NEG
, mode
,
6018 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6024 /* Look for MIN or MAX. */
6026 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6028 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6029 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6030 && ! side_effects_p (cond
))
6035 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6038 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6041 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6044 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6049 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6050 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6051 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6052 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6053 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6054 neither 1 or -1, but it isn't worth checking for. */
6056 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6058 && GET_MODE_CLASS (mode
) == MODE_INT
6059 && ! side_effects_p (x
))
6061 rtx t
= make_compound_operation (true_rtx
, SET
);
6062 rtx f
= make_compound_operation (false_rtx
, SET
);
6063 rtx cond_op0
= XEXP (cond
, 0);
6064 rtx cond_op1
= XEXP (cond
, 1);
6065 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6066 enum machine_mode m
= mode
;
6067 rtx z
= 0, c1
= NULL_RTX
;
6069 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6070 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6071 || GET_CODE (t
) == ASHIFT
6072 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6073 && rtx_equal_p (XEXP (t
, 0), f
))
6074 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6076 /* If an identity-zero op is commutative, check whether there
6077 would be a match if we swapped the operands. */
6078 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6079 || GET_CODE (t
) == XOR
)
6080 && rtx_equal_p (XEXP (t
, 1), f
))
6081 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6082 else if (GET_CODE (t
) == SIGN_EXTEND
6083 && (GET_CODE (XEXP (t
, 0)) == PLUS
6084 || GET_CODE (XEXP (t
, 0)) == MINUS
6085 || GET_CODE (XEXP (t
, 0)) == IOR
6086 || GET_CODE (XEXP (t
, 0)) == XOR
6087 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6088 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6089 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6090 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6091 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6092 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6093 && (num_sign_bit_copies (f
, GET_MODE (f
))
6095 (GET_MODE_BITSIZE (mode
)
6096 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6098 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6099 extend_op
= SIGN_EXTEND
;
6100 m
= GET_MODE (XEXP (t
, 0));
6102 else if (GET_CODE (t
) == SIGN_EXTEND
6103 && (GET_CODE (XEXP (t
, 0)) == PLUS
6104 || GET_CODE (XEXP (t
, 0)) == IOR
6105 || GET_CODE (XEXP (t
, 0)) == XOR
)
6106 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6107 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6108 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6109 && (num_sign_bit_copies (f
, GET_MODE (f
))
6111 (GET_MODE_BITSIZE (mode
)
6112 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6114 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6115 extend_op
= SIGN_EXTEND
;
6116 m
= GET_MODE (XEXP (t
, 0));
6118 else if (GET_CODE (t
) == ZERO_EXTEND
6119 && (GET_CODE (XEXP (t
, 0)) == PLUS
6120 || GET_CODE (XEXP (t
, 0)) == MINUS
6121 || GET_CODE (XEXP (t
, 0)) == IOR
6122 || GET_CODE (XEXP (t
, 0)) == XOR
6123 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6124 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6125 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6126 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6127 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6128 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6129 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6130 && ((nonzero_bits (f
, GET_MODE (f
))
6131 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6134 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6135 extend_op
= ZERO_EXTEND
;
6136 m
= GET_MODE (XEXP (t
, 0));
6138 else if (GET_CODE (t
) == ZERO_EXTEND
6139 && (GET_CODE (XEXP (t
, 0)) == PLUS
6140 || GET_CODE (XEXP (t
, 0)) == IOR
6141 || GET_CODE (XEXP (t
, 0)) == XOR
)
6142 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6143 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6144 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6145 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6146 && ((nonzero_bits (f
, GET_MODE (f
))
6147 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6150 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6151 extend_op
= ZERO_EXTEND
;
6152 m
= GET_MODE (XEXP (t
, 0));
6157 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6158 cond_op0
, cond_op1
),
6159 pc_rtx
, pc_rtx
, 0, 0);
6160 temp
= simplify_gen_binary (MULT
, m
, temp
,
6161 simplify_gen_binary (MULT
, m
, c1
,
6163 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
6164 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6166 if (extend_op
!= UNKNOWN
)
6167 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6173 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6174 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6175 negation of a single bit, we can convert this operation to a shift. We
6176 can actually do this more generally, but it doesn't seem worth it. */
6178 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6179 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6180 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6181 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6182 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6183 == GET_MODE_BITSIZE (mode
))
6184 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6186 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6187 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6189 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6190 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6191 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6192 && GET_MODE (XEXP (cond
, 0)) == mode
6193 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6194 == nonzero_bits (XEXP (cond
, 0), mode
)
6195 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6196 return XEXP (cond
, 0);
6201 /* Simplify X, a SET expression. Return the new expression. */
6204 simplify_set (rtx x
)
6206 rtx src
= SET_SRC (x
);
6207 rtx dest
= SET_DEST (x
);
6208 enum machine_mode mode
6209 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6213 /* (set (pc) (return)) gets written as (return). */
6214 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
6217 /* Now that we know for sure which bits of SRC we are using, see if we can
6218 simplify the expression for the object knowing that we only need the
6221 if (GET_MODE_CLASS (mode
) == MODE_INT
6222 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
6224 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6225 SUBST (SET_SRC (x
), src
);
6228 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6229 the comparison result and try to simplify it unless we already have used
6230 undobuf.other_insn. */
6231 if ((GET_MODE_CLASS (mode
) == MODE_CC
6232 || GET_CODE (src
) == COMPARE
6234 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6235 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6236 && COMPARISON_P (*cc_use
)
6237 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6239 enum rtx_code old_code
= GET_CODE (*cc_use
);
6240 enum rtx_code new_code
;
6242 int other_changed
= 0;
6243 rtx inner_compare
= NULL_RTX
;
6244 enum machine_mode compare_mode
= GET_MODE (dest
);
6246 if (GET_CODE (src
) == COMPARE
)
6248 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6249 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6251 inner_compare
= op0
;
6252 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6256 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6258 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6261 new_code
= old_code
;
6262 else if (!CONSTANT_P (tmp
))
6264 new_code
= GET_CODE (tmp
);
6265 op0
= XEXP (tmp
, 0);
6266 op1
= XEXP (tmp
, 1);
6270 rtx pat
= PATTERN (other_insn
);
6271 undobuf
.other_insn
= other_insn
;
6272 SUBST (*cc_use
, tmp
);
6274 /* Attempt to simplify CC user. */
6275 if (GET_CODE (pat
) == SET
)
6277 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6278 if (new_rtx
!= NULL_RTX
)
6279 SUBST (SET_SRC (pat
), new_rtx
);
6282 /* Convert X into a no-op move. */
6283 SUBST (SET_DEST (x
), pc_rtx
);
6284 SUBST (SET_SRC (x
), pc_rtx
);
6288 /* Simplify our comparison, if possible. */
6289 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6291 #ifdef SELECT_CC_MODE
6292 /* If this machine has CC modes other than CCmode, check to see if we
6293 need to use a different CC mode here. */
6294 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6295 compare_mode
= GET_MODE (op0
);
6296 else if (inner_compare
6297 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6298 && new_code
== old_code
6299 && op0
== XEXP (inner_compare
, 0)
6300 && op1
== XEXP (inner_compare
, 1))
6301 compare_mode
= GET_MODE (inner_compare
);
6303 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6306 /* If the mode changed, we have to change SET_DEST, the mode in the
6307 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6308 a hard register, just build new versions with the proper mode. If it
6309 is a pseudo, we lose unless it is only time we set the pseudo, in
6310 which case we can safely change its mode. */
6311 if (compare_mode
!= GET_MODE (dest
))
6313 if (can_change_dest_mode (dest
, 0, compare_mode
))
6315 unsigned int regno
= REGNO (dest
);
6318 if (regno
< FIRST_PSEUDO_REGISTER
)
6319 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6322 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6323 new_dest
= regno_reg_rtx
[regno
];
6326 SUBST (SET_DEST (x
), new_dest
);
6327 SUBST (XEXP (*cc_use
, 0), new_dest
);
6334 #endif /* SELECT_CC_MODE */
6336 /* If the code changed, we have to build a new comparison in
6337 undobuf.other_insn. */
6338 if (new_code
!= old_code
)
6340 int other_changed_previously
= other_changed
;
6341 unsigned HOST_WIDE_INT mask
;
6342 rtx old_cc_use
= *cc_use
;
6344 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6348 /* If the only change we made was to change an EQ into an NE or
6349 vice versa, OP0 has only one bit that might be nonzero, and OP1
6350 is zero, check if changing the user of the condition code will
6351 produce a valid insn. If it won't, we can keep the original code
6352 in that insn by surrounding our operation with an XOR. */
6354 if (((old_code
== NE
&& new_code
== EQ
)
6355 || (old_code
== EQ
&& new_code
== NE
))
6356 && ! other_changed_previously
&& op1
== const0_rtx
6357 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
6358 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6360 rtx pat
= PATTERN (other_insn
), note
= 0;
6362 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6363 && ! check_asm_operands (pat
)))
6365 *cc_use
= old_cc_use
;
6368 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6369 op0
, GEN_INT (mask
));
6375 undobuf
.other_insn
= other_insn
;
6377 /* Otherwise, if we didn't previously have a COMPARE in the
6378 correct mode, we need one. */
6379 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6381 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6384 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6386 SUBST (SET_SRC (x
), op0
);
6389 /* Otherwise, update the COMPARE if needed. */
6390 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6392 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6398 /* Get SET_SRC in a form where we have placed back any
6399 compound expressions. Then do the checks below. */
6400 src
= make_compound_operation (src
, SET
);
6401 SUBST (SET_SRC (x
), src
);
6404 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6405 and X being a REG or (subreg (reg)), we may be able to convert this to
6406 (set (subreg:m2 x) (op)).
6408 We can always do this if M1 is narrower than M2 because that means that
6409 we only care about the low bits of the result.
6411 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6412 perform a narrower operation than requested since the high-order bits will
6413 be undefined. On machine where it is defined, this transformation is safe
6414 as long as M1 and M2 have the same number of words. */
6416 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6417 && !OBJECT_P (SUBREG_REG (src
))
6418 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6420 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6421 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6422 #ifndef WORD_REGISTER_OPERATIONS
6423 && (GET_MODE_SIZE (GET_MODE (src
))
6424 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6426 #ifdef CANNOT_CHANGE_MODE_CLASS
6427 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6428 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6429 GET_MODE (SUBREG_REG (src
)),
6433 || (GET_CODE (dest
) == SUBREG
6434 && REG_P (SUBREG_REG (dest
)))))
6436 SUBST (SET_DEST (x
),
6437 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6439 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6441 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6445 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6448 && GET_CODE (src
) == SUBREG
6449 && subreg_lowpart_p (src
)
6450 && (GET_MODE_BITSIZE (GET_MODE (src
))
6451 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
6453 rtx inner
= SUBREG_REG (src
);
6454 enum machine_mode inner_mode
= GET_MODE (inner
);
6456 /* Here we make sure that we don't have a sign bit on. */
6457 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
6458 && (nonzero_bits (inner
, inner_mode
)
6459 < ((unsigned HOST_WIDE_INT
) 1
6460 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
6462 SUBST (SET_SRC (x
), inner
);
6468 #ifdef LOAD_EXTEND_OP
6469 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6470 would require a paradoxical subreg. Replace the subreg with a
6471 zero_extend to avoid the reload that would otherwise be required. */
6473 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6474 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6475 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6476 && SUBREG_BYTE (src
) == 0
6477 && (GET_MODE_SIZE (GET_MODE (src
))
6478 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6479 && MEM_P (SUBREG_REG (src
)))
6482 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6483 GET_MODE (src
), SUBREG_REG (src
)));
6489 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6490 are comparing an item known to be 0 or -1 against 0, use a logical
6491 operation instead. Check for one of the arms being an IOR of the other
6492 arm with some value. We compute three terms to be IOR'ed together. In
6493 practice, at most two will be nonzero. Then we do the IOR's. */
6495 if (GET_CODE (dest
) != PC
6496 && GET_CODE (src
) == IF_THEN_ELSE
6497 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6498 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6499 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6500 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6501 #ifdef HAVE_conditional_move
6502 && ! can_conditionally_move_p (GET_MODE (src
))
6504 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6505 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6506 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6507 && ! side_effects_p (src
))
6509 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6510 ? XEXP (src
, 1) : XEXP (src
, 2));
6511 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6512 ? XEXP (src
, 2) : XEXP (src
, 1));
6513 rtx term1
= const0_rtx
, term2
, term3
;
6515 if (GET_CODE (true_rtx
) == IOR
6516 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6517 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6518 else if (GET_CODE (true_rtx
) == IOR
6519 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6520 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6521 else if (GET_CODE (false_rtx
) == IOR
6522 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6523 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6524 else if (GET_CODE (false_rtx
) == IOR
6525 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6526 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6528 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6529 XEXP (XEXP (src
, 0), 0), true_rtx
);
6530 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6531 simplify_gen_unary (NOT
, GET_MODE (src
),
6532 XEXP (XEXP (src
, 0), 0),
6537 simplify_gen_binary (IOR
, GET_MODE (src
),
6538 simplify_gen_binary (IOR
, GET_MODE (src
),
6545 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6546 whole thing fail. */
6547 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6549 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6552 /* Convert this into a field assignment operation, if possible. */
6553 return make_field_assignment (x
);
6556 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6560 simplify_logical (rtx x
)
6562 enum machine_mode mode
= GET_MODE (x
);
6563 rtx op0
= XEXP (x
, 0);
6564 rtx op1
= XEXP (x
, 1);
6566 switch (GET_CODE (x
))
6569 /* We can call simplify_and_const_int only if we don't lose
6570 any (sign) bits when converting INTVAL (op1) to
6571 "unsigned HOST_WIDE_INT". */
6572 if (CONST_INT_P (op1
)
6573 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6574 || INTVAL (op1
) > 0))
6576 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6577 if (GET_CODE (x
) != AND
)
6584 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6585 apply the distributive law and then the inverse distributive
6586 law to see if things simplify. */
6587 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6589 rtx result
= distribute_and_simplify_rtx (x
, 0);
6593 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6595 rtx result
= distribute_and_simplify_rtx (x
, 1);
6602 /* If we have (ior (and A B) C), apply the distributive law and then
6603 the inverse distributive law to see if things simplify. */
6605 if (GET_CODE (op0
) == AND
)
6607 rtx result
= distribute_and_simplify_rtx (x
, 0);
6612 if (GET_CODE (op1
) == AND
)
6614 rtx result
= distribute_and_simplify_rtx (x
, 1);
6627 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6628 operations" because they can be replaced with two more basic operations.
6629 ZERO_EXTEND is also considered "compound" because it can be replaced with
6630 an AND operation, which is simpler, though only one operation.
6632 The function expand_compound_operation is called with an rtx expression
6633 and will convert it to the appropriate shifts and AND operations,
6634 simplifying at each stage.
6636 The function make_compound_operation is called to convert an expression
6637 consisting of shifts and ANDs into the equivalent compound expression.
6638 It is the inverse of this function, loosely speaking. */
6641 expand_compound_operation (rtx x
)
6643 unsigned HOST_WIDE_INT pos
= 0, len
;
6645 unsigned int modewidth
;
6648 switch (GET_CODE (x
))
6653 /* We can't necessarily use a const_int for a multiword mode;
6654 it depends on implicitly extending the value.
6655 Since we don't know the right way to extend it,
6656 we can't tell whether the implicit way is right.
6658 Even for a mode that is no wider than a const_int,
6659 we can't win, because we need to sign extend one of its bits through
6660 the rest of it, and we don't know which bit. */
6661 if (CONST_INT_P (XEXP (x
, 0)))
6664 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6665 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6666 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6667 reloaded. If not for that, MEM's would very rarely be safe.
6669 Reject MODEs bigger than a word, because we might not be able
6670 to reference a two-register group starting with an arbitrary register
6671 (and currently gen_lowpart might crash for a SUBREG). */
6673 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6676 /* Reject MODEs that aren't scalar integers because turning vector
6677 or complex modes into shifts causes problems. */
6679 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6682 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6683 /* If the inner object has VOIDmode (the only way this can happen
6684 is if it is an ASM_OPERANDS), we can't do anything since we don't
6685 know how much masking to do. */
6694 /* ... fall through ... */
6697 /* If the operand is a CLOBBER, just return it. */
6698 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6701 if (!CONST_INT_P (XEXP (x
, 1))
6702 || !CONST_INT_P (XEXP (x
, 2))
6703 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6706 /* Reject MODEs that aren't scalar integers because turning vector
6707 or complex modes into shifts causes problems. */
6709 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6712 len
= INTVAL (XEXP (x
, 1));
6713 pos
= INTVAL (XEXP (x
, 2));
6715 /* This should stay within the object being extracted, fail otherwise. */
6716 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6719 if (BITS_BIG_ENDIAN
)
6720 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6727 /* Convert sign extension to zero extension, if we know that the high
6728 bit is not set, as this is easier to optimize. It will be converted
6729 back to cheaper alternative in make_extraction. */
6730 if (GET_CODE (x
) == SIGN_EXTEND
6731 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6732 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6733 & ~(((unsigned HOST_WIDE_INT
)
6734 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6738 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6739 rtx temp2
= expand_compound_operation (temp
);
6741 /* Make sure this is a profitable operation. */
6742 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6743 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6745 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6746 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6752 /* We can optimize some special cases of ZERO_EXTEND. */
6753 if (GET_CODE (x
) == ZERO_EXTEND
)
6755 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6756 know that the last value didn't have any inappropriate bits
6758 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6759 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6760 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6761 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6762 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6763 return XEXP (XEXP (x
, 0), 0);
6765 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6766 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6767 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6768 && subreg_lowpart_p (XEXP (x
, 0))
6769 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6770 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6771 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6772 return SUBREG_REG (XEXP (x
, 0));
6774 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6775 is a comparison and STORE_FLAG_VALUE permits. This is like
6776 the first case, but it works even when GET_MODE (x) is larger
6777 than HOST_WIDE_INT. */
6778 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6779 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6780 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6781 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6782 <= HOST_BITS_PER_WIDE_INT
)
6783 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6784 return XEXP (XEXP (x
, 0), 0);
6786 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6787 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6788 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6789 && subreg_lowpart_p (XEXP (x
, 0))
6790 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6791 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6792 <= HOST_BITS_PER_WIDE_INT
)
6793 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6794 return SUBREG_REG (XEXP (x
, 0));
6798 /* If we reach here, we want to return a pair of shifts. The inner
6799 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6800 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6801 logical depending on the value of UNSIGNEDP.
6803 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6804 converted into an AND of a shift.
6806 We must check for the case where the left shift would have a negative
6807 count. This can happen in a case like (x >> 31) & 255 on machines
6808 that can't shift by a constant. On those machines, we would first
6809 combine the shift with the AND to produce a variable-position
6810 extraction. Then the constant of 31 would be substituted in
6811 to produce such a position. */
6813 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6814 if (modewidth
>= pos
+ len
)
6816 enum machine_mode mode
= GET_MODE (x
);
6817 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6818 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6820 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6821 tem
, modewidth
- pos
- len
);
6822 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6823 mode
, tem
, modewidth
- len
);
6825 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6826 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6827 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6830 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6832 /* Any other cases we can't handle. */
6835 /* If we couldn't do this for some reason, return the original
6837 if (GET_CODE (tem
) == CLOBBER
)
6843 /* X is a SET which contains an assignment of one object into
6844 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6845 or certain SUBREGS). If possible, convert it into a series of
6848 We half-heartedly support variable positions, but do not at all
6849 support variable lengths. */
6852 expand_field_assignment (const_rtx x
)
6855 rtx pos
; /* Always counts from low bit. */
6857 rtx mask
, cleared
, masked
;
6858 enum machine_mode compute_mode
;
6860 /* Loop until we find something we can't simplify. */
6863 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6864 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6866 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6867 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6868 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6870 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6871 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6873 inner
= XEXP (SET_DEST (x
), 0);
6874 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6875 pos
= XEXP (SET_DEST (x
), 2);
6877 /* A constant position should stay within the width of INNER. */
6878 if (CONST_INT_P (pos
)
6879 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6882 if (BITS_BIG_ENDIAN
)
6884 if (CONST_INT_P (pos
))
6885 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6887 else if (GET_CODE (pos
) == MINUS
6888 && CONST_INT_P (XEXP (pos
, 1))
6889 && (INTVAL (XEXP (pos
, 1))
6890 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6891 /* If position is ADJUST - X, new position is X. */
6892 pos
= XEXP (pos
, 0);
6894 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6895 GEN_INT (GET_MODE_BITSIZE (
6902 /* A SUBREG between two modes that occupy the same numbers of words
6903 can be done by moving the SUBREG to the source. */
6904 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6905 /* We need SUBREGs to compute nonzero_bits properly. */
6906 && nonzero_sign_valid
6907 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6908 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6909 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6910 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6912 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6914 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6921 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6922 inner
= SUBREG_REG (inner
);
6924 compute_mode
= GET_MODE (inner
);
6926 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6927 if (! SCALAR_INT_MODE_P (compute_mode
))
6929 enum machine_mode imode
;
6931 /* Don't do anything for vector or complex integral types. */
6932 if (! FLOAT_MODE_P (compute_mode
))
6935 /* Try to find an integral mode to pun with. */
6936 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6937 if (imode
== BLKmode
)
6940 compute_mode
= imode
;
6941 inner
= gen_lowpart (imode
, inner
);
6944 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6945 if (len
>= HOST_BITS_PER_WIDE_INT
)
6948 /* Now compute the equivalent expression. Make a copy of INNER
6949 for the SET_DEST in case it is a MEM into which we will substitute;
6950 we don't want shared RTL in that case. */
6951 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6952 cleared
= simplify_gen_binary (AND
, compute_mode
,
6953 simplify_gen_unary (NOT
, compute_mode
,
6954 simplify_gen_binary (ASHIFT
,
6959 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6960 simplify_gen_binary (
6962 gen_lowpart (compute_mode
, SET_SRC (x
)),
6966 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6967 simplify_gen_binary (IOR
, compute_mode
,
6974 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6975 it is an RTX that represents a variable starting position; otherwise,
6976 POS is the (constant) starting bit position (counted from the LSB).
6978 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6981 IN_DEST is nonzero if this is a reference in the destination of a
6982 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6983 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6986 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6987 ZERO_EXTRACT should be built even for bits starting at bit 0.
6989 MODE is the desired mode of the result (if IN_DEST == 0).
6991 The result is an RTX for the extraction or NULL_RTX if the target
6995 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6996 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6997 int in_dest
, int in_compare
)
6999 /* This mode describes the size of the storage area
7000 to fetch the overall value from. Within that, we
7001 ignore the POS lowest bits, etc. */
7002 enum machine_mode is_mode
= GET_MODE (inner
);
7003 enum machine_mode inner_mode
;
7004 enum machine_mode wanted_inner_mode
;
7005 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7006 enum machine_mode pos_mode
= word_mode
;
7007 enum machine_mode extraction_mode
= word_mode
;
7008 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7010 rtx orig_pos_rtx
= pos_rtx
;
7011 HOST_WIDE_INT orig_pos
;
7013 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7015 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7016 consider just the QI as the memory to extract from.
7017 The subreg adds or removes high bits; its mode is
7018 irrelevant to the meaning of this extraction,
7019 since POS and LEN count from the lsb. */
7020 if (MEM_P (SUBREG_REG (inner
)))
7021 is_mode
= GET_MODE (SUBREG_REG (inner
));
7022 inner
= SUBREG_REG (inner
);
7024 else if (GET_CODE (inner
) == ASHIFT
7025 && CONST_INT_P (XEXP (inner
, 1))
7026 && pos_rtx
== 0 && pos
== 0
7027 && len
> UINTVAL (XEXP (inner
, 1)))
7029 /* We're extracting the least significant bits of an rtx
7030 (ashift X (const_int C)), where LEN > C. Extract the
7031 least significant (LEN - C) bits of X, giving an rtx
7032 whose mode is MODE, then shift it left C times. */
7033 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7034 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7035 unsignedp
, in_dest
, in_compare
);
7037 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7040 inner_mode
= GET_MODE (inner
);
7042 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7043 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7045 /* See if this can be done without an extraction. We never can if the
7046 width of the field is not the same as that of some integer mode. For
7047 registers, we can only avoid the extraction if the position is at the
7048 low-order bit and this is either not in the destination or we have the
7049 appropriate STRICT_LOW_PART operation available.
7051 For MEM, we can avoid an extract if the field starts on an appropriate
7052 boundary and we can change the mode of the memory reference. */
7054 if (tmode
!= BLKmode
7055 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7057 && (inner_mode
== tmode
7059 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
7060 GET_MODE_BITSIZE (inner_mode
))
7061 || reg_truncated_to_mode (tmode
, inner
))
7064 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7065 || (MEM_P (inner
) && pos_rtx
== 0
7067 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7068 : BITS_PER_UNIT
)) == 0
7069 /* We can't do this if we are widening INNER_MODE (it
7070 may not be aligned, for one thing). */
7071 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
7072 && (inner_mode
== tmode
7073 || (! mode_dependent_address_p (XEXP (inner
, 0))
7074 && ! MEM_VOLATILE_P (inner
))))))
7076 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7077 field. If the original and current mode are the same, we need not
7078 adjust the offset. Otherwise, we do if bytes big endian.
7080 If INNER is not a MEM, get a piece consisting of just the field
7081 of interest (in this case POS % BITS_PER_WORD must be 0). */
7085 HOST_WIDE_INT offset
;
7087 /* POS counts from lsb, but make OFFSET count in memory order. */
7088 if (BYTES_BIG_ENDIAN
)
7089 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7091 offset
= pos
/ BITS_PER_UNIT
;
7093 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7095 else if (REG_P (inner
))
7097 if (tmode
!= inner_mode
)
7099 /* We can't call gen_lowpart in a DEST since we
7100 always want a SUBREG (see below) and it would sometimes
7101 return a new hard register. */
7104 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7106 if (WORDS_BIG_ENDIAN
7107 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7108 final_word
= ((GET_MODE_SIZE (inner_mode
)
7109 - GET_MODE_SIZE (tmode
))
7110 / UNITS_PER_WORD
) - final_word
;
7112 final_word
*= UNITS_PER_WORD
;
7113 if (BYTES_BIG_ENDIAN
&&
7114 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7115 final_word
+= (GET_MODE_SIZE (inner_mode
)
7116 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7118 /* Avoid creating invalid subregs, for example when
7119 simplifying (x>>32)&255. */
7120 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7123 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7126 new_rtx
= gen_lowpart (tmode
, inner
);
7132 new_rtx
= force_to_mode (inner
, tmode
,
7133 len
>= HOST_BITS_PER_WIDE_INT
7134 ? ~(unsigned HOST_WIDE_INT
) 0
7135 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7138 /* If this extraction is going into the destination of a SET,
7139 make a STRICT_LOW_PART unless we made a MEM. */
7142 return (MEM_P (new_rtx
) ? new_rtx
7143 : (GET_CODE (new_rtx
) != SUBREG
7144 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7145 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7150 if (CONST_INT_P (new_rtx
)
7151 || GET_CODE (new_rtx
) == CONST_DOUBLE
)
7152 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7153 mode
, new_rtx
, tmode
);
7155 /* If we know that no extraneous bits are set, and that the high
7156 bit is not set, convert the extraction to the cheaper of
7157 sign and zero extension, that are equivalent in these cases. */
7158 if (flag_expensive_optimizations
7159 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
7160 && ((nonzero_bits (new_rtx
, tmode
)
7161 & ~(((unsigned HOST_WIDE_INT
)
7162 GET_MODE_MASK (tmode
))
7166 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7167 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7169 /* Prefer ZERO_EXTENSION, since it gives more information to
7171 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
7172 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
7177 /* Otherwise, sign- or zero-extend unless we already are in the
7180 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7184 /* Unless this is a COMPARE or we have a funny memory reference,
7185 don't do anything with zero-extending field extracts starting at
7186 the low-order bit since they are simple AND operations. */
7187 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7188 && ! in_compare
&& unsignedp
)
7191 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7192 if the position is not a constant and the length is not 1. In all
7193 other cases, we would only be going outside our object in cases when
7194 an original shift would have been undefined. */
7196 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
7197 || (pos_rtx
!= 0 && len
!= 1)))
7200 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7201 and the mode for the result. */
7202 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7204 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7205 pos_mode
= mode_for_extraction (EP_insv
, 2);
7206 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7209 if (! in_dest
&& unsignedp
7210 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7212 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7213 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7214 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7217 if (! in_dest
&& ! unsignedp
7218 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7220 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7221 pos_mode
= mode_for_extraction (EP_extv
, 3);
7222 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7225 /* Never narrow an object, since that might not be safe. */
7227 if (mode
!= VOIDmode
7228 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7229 extraction_mode
= mode
;
7231 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
7232 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7233 pos_mode
= GET_MODE (pos_rtx
);
7235 /* If this is not from memory, the desired mode is the preferred mode
7236 for an extraction pattern's first input operand, or word_mode if there
7239 wanted_inner_mode
= wanted_inner_reg_mode
;
7242 /* Be careful not to go beyond the extracted object and maintain the
7243 natural alignment of the memory. */
7244 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7245 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7246 > GET_MODE_BITSIZE (wanted_inner_mode
))
7248 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7249 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7252 /* If we have to change the mode of memory and cannot, the desired mode
7253 is EXTRACTION_MODE. */
7254 if (inner_mode
!= wanted_inner_mode
7255 && (mode_dependent_address_p (XEXP (inner
, 0))
7256 || MEM_VOLATILE_P (inner
)
7258 wanted_inner_mode
= extraction_mode
;
7263 if (BITS_BIG_ENDIAN
)
7265 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7266 BITS_BIG_ENDIAN style. If position is constant, compute new
7267 position. Otherwise, build subtraction.
7268 Note that POS is relative to the mode of the original argument.
7269 If it's a MEM we need to recompute POS relative to that.
7270 However, if we're extracting from (or inserting into) a register,
7271 we want to recompute POS relative to wanted_inner_mode. */
7272 int width
= (MEM_P (inner
)
7273 ? GET_MODE_BITSIZE (is_mode
)
7274 : GET_MODE_BITSIZE (wanted_inner_mode
));
7277 pos
= width
- len
- pos
;
7280 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7281 /* POS may be less than 0 now, but we check for that below.
7282 Note that it can only be less than 0 if !MEM_P (inner). */
7285 /* If INNER has a wider mode, and this is a constant extraction, try to
7286 make it smaller and adjust the byte to point to the byte containing
7288 if (wanted_inner_mode
!= VOIDmode
7289 && inner_mode
!= wanted_inner_mode
7291 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7293 && ! mode_dependent_address_p (XEXP (inner
, 0))
7294 && ! MEM_VOLATILE_P (inner
))
7298 /* The computations below will be correct if the machine is big
7299 endian in both bits and bytes or little endian in bits and bytes.
7300 If it is mixed, we must adjust. */
7302 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7303 adjust OFFSET to compensate. */
7304 if (BYTES_BIG_ENDIAN
7305 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7306 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7308 /* We can now move to the desired byte. */
7309 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7310 * GET_MODE_SIZE (wanted_inner_mode
);
7311 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7313 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7314 && is_mode
!= wanted_inner_mode
)
7315 offset
= (GET_MODE_SIZE (is_mode
)
7316 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7318 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7321 /* If INNER is not memory, get it into the proper mode. If we are changing
7322 its mode, POS must be a constant and smaller than the size of the new
7324 else if (!MEM_P (inner
))
7326 /* On the LHS, don't create paradoxical subregs implicitely truncating
7327 the register unless TRULY_NOOP_TRUNCATION. */
7329 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner
)),
7330 GET_MODE_BITSIZE (wanted_inner_mode
)))
7333 if (GET_MODE (inner
) != wanted_inner_mode
7335 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7341 inner
= force_to_mode (inner
, wanted_inner_mode
,
7343 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7344 ? ~(unsigned HOST_WIDE_INT
) 0
7345 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7350 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7351 have to zero extend. Otherwise, we can just use a SUBREG. */
7353 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7355 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7357 /* If we know that no extraneous bits are set, and that the high
7358 bit is not set, convert extraction to cheaper one - either
7359 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7361 if (flag_expensive_optimizations
7362 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
7363 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7364 & ~(((unsigned HOST_WIDE_INT
)
7365 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7369 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7371 /* Prefer ZERO_EXTENSION, since it gives more information to
7373 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
7374 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
7379 else if (pos_rtx
!= 0
7380 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7381 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7383 /* Make POS_RTX unless we already have it and it is correct. If we don't
7384 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7386 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7387 pos_rtx
= orig_pos_rtx
;
7389 else if (pos_rtx
== 0)
7390 pos_rtx
= GEN_INT (pos
);
7392 /* Make the required operation. See if we can use existing rtx. */
7393 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7394 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7396 new_rtx
= gen_lowpart (mode
, new_rtx
);
7401 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7402 with any other operations in X. Return X without that shift if so. */
7405 extract_left_shift (rtx x
, int count
)
7407 enum rtx_code code
= GET_CODE (x
);
7408 enum machine_mode mode
= GET_MODE (x
);
7414 /* This is the shift itself. If it is wide enough, we will return
7415 either the value being shifted if the shift count is equal to
7416 COUNT or a shift for the difference. */
7417 if (CONST_INT_P (XEXP (x
, 1))
7418 && INTVAL (XEXP (x
, 1)) >= count
)
7419 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7420 INTVAL (XEXP (x
, 1)) - count
);
7424 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7425 return simplify_gen_unary (code
, mode
, tem
, mode
);
7429 case PLUS
: case IOR
: case XOR
: case AND
:
7430 /* If we can safely shift this constant and we find the inner shift,
7431 make a new operation. */
7432 if (CONST_INT_P (XEXP (x
, 1))
7433 && (UINTVAL (XEXP (x
, 1))
7434 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7435 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7436 return simplify_gen_binary (code
, mode
, tem
,
7437 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7448 /* Look at the expression rooted at X. Look for expressions
7449 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7450 Form these expressions.
7452 Return the new rtx, usually just X.
7454 Also, for machines like the VAX that don't have logical shift insns,
7455 try to convert logical to arithmetic shift operations in cases where
7456 they are equivalent. This undoes the canonicalizations to logical
7457 shifts done elsewhere.
7459 We try, as much as possible, to re-use rtl expressions to save memory.
7461 IN_CODE says what kind of expression we are processing. Normally, it is
7462 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7463 being kludges), it is MEM. When processing the arguments of a comparison
7464 or a COMPARE against zero, it is COMPARE. */
7467 make_compound_operation (rtx x
, enum rtx_code in_code
)
7469 enum rtx_code code
= GET_CODE (x
);
7470 enum machine_mode mode
= GET_MODE (x
);
7471 int mode_width
= GET_MODE_BITSIZE (mode
);
7473 enum rtx_code next_code
;
7479 /* Select the code to be used in recursive calls. Once we are inside an
7480 address, we stay there. If we have a comparison, set to COMPARE,
7481 but once inside, go back to our default of SET. */
7483 next_code
= (code
== MEM
? MEM
7484 : ((code
== PLUS
|| code
== MINUS
)
7485 && SCALAR_INT_MODE_P (mode
)) ? MEM
7486 : ((code
== COMPARE
|| COMPARISON_P (x
))
7487 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7488 : in_code
== COMPARE
? SET
: in_code
);
7490 /* Process depending on the code of this operation. If NEW is set
7491 nonzero, it will be returned. */
7496 /* Convert shifts by constants into multiplications if inside
7498 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7499 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7500 && INTVAL (XEXP (x
, 1)) >= 0
7501 && SCALAR_INT_MODE_P (mode
))
7503 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7504 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7506 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7507 if (GET_CODE (new_rtx
) == NEG
)
7509 new_rtx
= XEXP (new_rtx
, 0);
7512 multval
= trunc_int_for_mode (multval
, mode
);
7513 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7520 lhs
= make_compound_operation (lhs
, next_code
);
7521 rhs
= make_compound_operation (rhs
, next_code
);
7522 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7523 && SCALAR_INT_MODE_P (mode
))
7525 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7527 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7529 else if (GET_CODE (lhs
) == MULT
7530 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7532 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7533 simplify_gen_unary (NEG
, mode
,
7536 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7540 SUBST (XEXP (x
, 0), lhs
);
7541 SUBST (XEXP (x
, 1), rhs
);
7544 x
= gen_lowpart (mode
, new_rtx
);
7550 lhs
= make_compound_operation (lhs
, next_code
);
7551 rhs
= make_compound_operation (rhs
, next_code
);
7552 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7553 && SCALAR_INT_MODE_P (mode
))
7555 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7557 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7559 else if (GET_CODE (rhs
) == MULT
7560 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7562 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7563 simplify_gen_unary (NEG
, mode
,
7566 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7570 SUBST (XEXP (x
, 0), lhs
);
7571 SUBST (XEXP (x
, 1), rhs
);
7574 return gen_lowpart (mode
, new_rtx
);
7577 /* If the second operand is not a constant, we can't do anything
7579 if (!CONST_INT_P (XEXP (x
, 1)))
7582 /* If the constant is a power of two minus one and the first operand
7583 is a logical right shift, make an extraction. */
7584 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7585 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7587 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7588 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7589 0, in_code
== COMPARE
);
7592 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7593 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7594 && subreg_lowpart_p (XEXP (x
, 0))
7595 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7596 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7598 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7600 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7601 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7602 0, in_code
== COMPARE
);
7604 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7605 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7606 || GET_CODE (XEXP (x
, 0)) == IOR
)
7607 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7608 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7609 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7611 /* Apply the distributive law, and then try to make extractions. */
7612 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7613 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7615 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7617 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7620 /* If we are have (and (rotate X C) M) and C is larger than the number
7621 of bits in M, this is an extraction. */
7623 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7624 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7625 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7626 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7628 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7629 new_rtx
= make_extraction (mode
, new_rtx
,
7630 (GET_MODE_BITSIZE (mode
)
7631 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7632 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7635 /* On machines without logical shifts, if the operand of the AND is
7636 a logical shift and our mask turns off all the propagated sign
7637 bits, we can replace the logical shift with an arithmetic shift. */
7638 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7639 && !have_insn_for (LSHIFTRT
, mode
)
7640 && have_insn_for (ASHIFTRT
, mode
)
7641 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7642 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7643 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7644 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7646 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7648 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7649 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7651 gen_rtx_ASHIFTRT (mode
,
7652 make_compound_operation
7653 (XEXP (XEXP (x
, 0), 0), next_code
),
7654 XEXP (XEXP (x
, 0), 1)));
7657 /* If the constant is one less than a power of two, this might be
7658 representable by an extraction even if no shift is present.
7659 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7660 we are in a COMPARE. */
7661 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7662 new_rtx
= make_extraction (mode
,
7663 make_compound_operation (XEXP (x
, 0),
7665 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7667 /* If we are in a comparison and this is an AND with a power of two,
7668 convert this into the appropriate bit extract. */
7669 else if (in_code
== COMPARE
7670 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7671 new_rtx
= make_extraction (mode
,
7672 make_compound_operation (XEXP (x
, 0),
7674 i
, NULL_RTX
, 1, 1, 0, 1);
7679 /* If the sign bit is known to be zero, replace this with an
7680 arithmetic shift. */
7681 if (have_insn_for (ASHIFTRT
, mode
)
7682 && ! have_insn_for (LSHIFTRT
, mode
)
7683 && mode_width
<= HOST_BITS_PER_WIDE_INT
7684 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7686 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7687 make_compound_operation (XEXP (x
, 0),
7693 /* ... fall through ... */
7699 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7700 this is a SIGN_EXTRACT. */
7701 if (CONST_INT_P (rhs
)
7702 && GET_CODE (lhs
) == ASHIFT
7703 && CONST_INT_P (XEXP (lhs
, 1))
7704 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7705 && INTVAL (rhs
) < mode_width
)
7707 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7708 new_rtx
= make_extraction (mode
, new_rtx
,
7709 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7710 NULL_RTX
, mode_width
- INTVAL (rhs
),
7711 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7715 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7716 If so, try to merge the shifts into a SIGN_EXTEND. We could
7717 also do this for some cases of SIGN_EXTRACT, but it doesn't
7718 seem worth the effort; the case checked for occurs on Alpha. */
7721 && ! (GET_CODE (lhs
) == SUBREG
7722 && (OBJECT_P (SUBREG_REG (lhs
))))
7723 && CONST_INT_P (rhs
)
7724 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7725 && INTVAL (rhs
) < mode_width
7726 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7727 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7728 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7729 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7734 /* Call ourselves recursively on the inner expression. If we are
7735 narrowing the object and it has a different RTL code from
7736 what it originally did, do this SUBREG as a force_to_mode. */
7738 rtx inner
= SUBREG_REG (x
), simplified
;
7740 tem
= make_compound_operation (inner
, in_code
);
7743 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7747 if (GET_CODE (tem
) != GET_CODE (inner
)
7748 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7749 && subreg_lowpart_p (x
))
7752 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7754 /* If we have something other than a SUBREG, we might have
7755 done an expansion, so rerun ourselves. */
7756 if (GET_CODE (newer
) != SUBREG
)
7757 newer
= make_compound_operation (newer
, in_code
);
7759 /* force_to_mode can expand compounds. If it just re-expanded the
7760 compound, use gen_lowpart to convert to the desired mode. */
7761 if (rtx_equal_p (newer
, x
)
7762 /* Likewise if it re-expanded the compound only partially.
7763 This happens for SUBREG of ZERO_EXTRACT if they extract
7764 the same number of bits. */
7765 || (GET_CODE (newer
) == SUBREG
7766 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7767 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7768 && GET_CODE (inner
) == AND
7769 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7770 return gen_lowpart (GET_MODE (x
), tem
);
7786 x
= gen_lowpart (mode
, new_rtx
);
7787 code
= GET_CODE (x
);
7790 /* Now recursively process each operand of this operation. */
7791 fmt
= GET_RTX_FORMAT (code
);
7792 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7795 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7796 SUBST (XEXP (x
, i
), new_rtx
);
7798 else if (fmt
[i
] == 'E')
7799 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7801 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7802 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7806 /* If this is a commutative operation, the changes to the operands
7807 may have made it noncanonical. */
7808 if (COMMUTATIVE_ARITH_P (x
)
7809 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7812 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7813 SUBST (XEXP (x
, 1), tem
);
7819 /* Given M see if it is a value that would select a field of bits
7820 within an item, but not the entire word. Return -1 if not.
7821 Otherwise, return the starting position of the field, where 0 is the
7824 *PLEN is set to the length of the field. */
7827 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7829 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7830 int pos
= m
? ctz_hwi (m
) : -1;
7834 /* Now shift off the low-order zero bits and see if we have a
7835 power of two minus 1. */
7836 len
= exact_log2 ((m
>> pos
) + 1);
7845 /* If X refers to a register that equals REG in value, replace these
7846 references with REG. */
7848 canon_reg_for_combine (rtx x
, rtx reg
)
7855 enum rtx_code code
= GET_CODE (x
);
7856 switch (GET_RTX_CLASS (code
))
7859 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7860 if (op0
!= XEXP (x
, 0))
7861 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7866 case RTX_COMM_ARITH
:
7867 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7868 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7869 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7870 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7874 case RTX_COMM_COMPARE
:
7875 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7876 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7877 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7878 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7879 GET_MODE (op0
), op0
, op1
);
7883 case RTX_BITFIELD_OPS
:
7884 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7885 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7886 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7887 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7888 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7889 GET_MODE (op0
), op0
, op1
, op2
);
7894 if (rtx_equal_p (get_last_value (reg
), x
)
7895 || rtx_equal_p (reg
, get_last_value (x
)))
7904 fmt
= GET_RTX_FORMAT (code
);
7906 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7909 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7910 if (op
!= XEXP (x
, i
))
7920 else if (fmt
[i
] == 'E')
7923 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7925 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7926 if (op
!= XVECEXP (x
, i
, j
))
7933 XVECEXP (x
, i
, j
) = op
;
7944 /* Return X converted to MODE. If the value is already truncated to
7945 MODE we can just return a subreg even though in the general case we
7946 would need an explicit truncation. */
7949 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7951 if (!CONST_INT_P (x
)
7952 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7953 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7954 GET_MODE_BITSIZE (GET_MODE (x
)))
7955 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7957 /* Bit-cast X into an integer mode. */
7958 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7959 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7960 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7964 return gen_lowpart (mode
, x
);
7967 /* See if X can be simplified knowing that we will only refer to it in
7968 MODE and will only refer to those bits that are nonzero in MASK.
7969 If other bits are being computed or if masking operations are done
7970 that select a superset of the bits in MASK, they can sometimes be
7973 Return a possibly simplified expression, but always convert X to
7974 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7976 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7977 are all off in X. This is used when X will be complemented, by either
7978 NOT, NEG, or XOR. */
7981 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7984 enum rtx_code code
= GET_CODE (x
);
7985 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7986 enum machine_mode op_mode
;
7987 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7990 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7991 code below will do the wrong thing since the mode of such an
7992 expression is VOIDmode.
7994 Also do nothing if X is a CLOBBER; this can happen if X was
7995 the return value from a call to gen_lowpart. */
7996 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7999 /* We want to perform the operation is its present mode unless we know
8000 that the operation is valid in MODE, in which case we do the operation
8002 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8003 && have_insn_for (code
, mode
))
8004 ? mode
: GET_MODE (x
));
8006 /* It is not valid to do a right-shift in a narrower mode
8007 than the one it came in with. */
8008 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8009 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
8010 op_mode
= GET_MODE (x
);
8012 /* Truncate MASK to fit OP_MODE. */
8014 mask
&= GET_MODE_MASK (op_mode
);
8016 /* When we have an arithmetic operation, or a shift whose count we
8017 do not know, we need to assume that all bits up to the highest-order
8018 bit in MASK will be needed. This is how we form such a mask. */
8019 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8020 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8022 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8025 /* Determine what bits of X are guaranteed to be (non)zero. */
8026 nonzero
= nonzero_bits (x
, mode
);
8028 /* If none of the bits in X are needed, return a zero. */
8029 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8032 /* If X is a CONST_INT, return a new one. Do this here since the
8033 test below will fail. */
8034 if (CONST_INT_P (x
))
8036 if (SCALAR_INT_MODE_P (mode
))
8037 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8040 x
= GEN_INT (INTVAL (x
) & mask
);
8041 return gen_lowpart_common (mode
, x
);
8045 /* If X is narrower than MODE and we want all the bits in X's mode, just
8046 get X in the proper mode. */
8047 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8048 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8049 return gen_lowpart (mode
, x
);
8051 /* We can ignore the effect of a SUBREG if it narrows the mode or
8052 if the constant masks to zero all the bits the mode doesn't have. */
8053 if (GET_CODE (x
) == SUBREG
8054 && subreg_lowpart_p (x
)
8055 && ((GET_MODE_SIZE (GET_MODE (x
))
8056 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8058 & GET_MODE_MASK (GET_MODE (x
))
8059 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8060 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8062 /* The arithmetic simplifications here only work for scalar integer modes. */
8063 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8064 return gen_lowpart_or_truncate (mode
, x
);
8069 /* If X is a (clobber (const_int)), return it since we know we are
8070 generating something that won't match. */
8077 x
= expand_compound_operation (x
);
8078 if (GET_CODE (x
) != code
)
8079 return force_to_mode (x
, mode
, mask
, next_select
);
8083 /* Similarly for a truncate. */
8084 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8087 /* If this is an AND with a constant, convert it into an AND
8088 whose constant is the AND of that constant with MASK. If it
8089 remains an AND of MASK, delete it since it is redundant. */
8091 if (CONST_INT_P (XEXP (x
, 1)))
8093 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8094 mask
& INTVAL (XEXP (x
, 1)));
8096 /* If X is still an AND, see if it is an AND with a mask that
8097 is just some low-order bits. If so, and it is MASK, we don't
8100 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8101 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8105 /* If it remains an AND, try making another AND with the bits
8106 in the mode mask that aren't in MASK turned on. If the
8107 constant in the AND is wide enough, this might make a
8108 cheaper constant. */
8110 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8111 && GET_MODE_MASK (GET_MODE (x
)) != mask
8112 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
8114 unsigned HOST_WIDE_INT cval
8115 = UINTVAL (XEXP (x
, 1))
8116 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8117 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
8120 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8121 number, sign extend it. */
8122 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8123 && (cval
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8124 cval
|= (unsigned HOST_WIDE_INT
) -1 << width
;
8126 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8127 XEXP (x
, 0), GEN_INT (cval
));
8128 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
8129 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8139 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8140 low-order bits (as in an alignment operation) and FOO is already
8141 aligned to that boundary, mask C1 to that boundary as well.
8142 This may eliminate that PLUS and, later, the AND. */
8145 unsigned int width
= GET_MODE_BITSIZE (mode
);
8146 unsigned HOST_WIDE_INT smask
= mask
;
8148 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8149 number, sign extend it. */
8151 if (width
< HOST_BITS_PER_WIDE_INT
8152 && (smask
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8153 smask
|= (unsigned HOST_WIDE_INT
) (-1) << width
;
8155 if (CONST_INT_P (XEXP (x
, 1))
8156 && exact_log2 (- smask
) >= 0
8157 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8158 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8159 return force_to_mode (plus_constant (XEXP (x
, 0),
8160 (INTVAL (XEXP (x
, 1)) & smask
)),
8161 mode
, smask
, next_select
);
8164 /* ... fall through ... */
8167 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8168 most significant bit in MASK since carries from those bits will
8169 affect the bits we are interested in. */
8174 /* If X is (minus C Y) where C's least set bit is larger than any bit
8175 in the mask, then we may replace with (neg Y). */
8176 if (CONST_INT_P (XEXP (x
, 0))
8177 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8178 & -INTVAL (XEXP (x
, 0))))
8181 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8183 return force_to_mode (x
, mode
, mask
, next_select
);
8186 /* Similarly, if C contains every bit in the fuller_mask, then we may
8187 replace with (not Y). */
8188 if (CONST_INT_P (XEXP (x
, 0))
8189 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8191 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8192 XEXP (x
, 1), GET_MODE (x
));
8193 return force_to_mode (x
, mode
, mask
, next_select
);
8201 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8202 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8203 operation which may be a bitfield extraction. Ensure that the
8204 constant we form is not wider than the mode of X. */
8206 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8207 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8208 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8209 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8210 && CONST_INT_P (XEXP (x
, 1))
8211 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8212 + floor_log2 (INTVAL (XEXP (x
, 1))))
8213 < GET_MODE_BITSIZE (GET_MODE (x
)))
8214 && (UINTVAL (XEXP (x
, 1))
8215 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8217 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8218 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8219 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8220 XEXP (XEXP (x
, 0), 0), temp
);
8221 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8222 XEXP (XEXP (x
, 0), 1));
8223 return force_to_mode (x
, mode
, mask
, next_select
);
8227 /* For most binary operations, just propagate into the operation and
8228 change the mode if we have an operation of that mode. */
8230 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8231 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8233 /* If we ended up truncating both operands, truncate the result of the
8234 operation instead. */
8235 if (GET_CODE (op0
) == TRUNCATE
8236 && GET_CODE (op1
) == TRUNCATE
)
8238 op0
= XEXP (op0
, 0);
8239 op1
= XEXP (op1
, 0);
8242 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8243 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8245 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8246 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8250 /* For left shifts, do the same, but just for the first operand.
8251 However, we cannot do anything with shifts where we cannot
8252 guarantee that the counts are smaller than the size of the mode
8253 because such a count will have a different meaning in a
8256 if (! (CONST_INT_P (XEXP (x
, 1))
8257 && INTVAL (XEXP (x
, 1)) >= 0
8258 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
8259 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8260 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8261 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
8264 /* If the shift count is a constant and we can do arithmetic in
8265 the mode of the shift, refine which bits we need. Otherwise, use the
8266 conservative form of the mask. */
8267 if (CONST_INT_P (XEXP (x
, 1))
8268 && INTVAL (XEXP (x
, 1)) >= 0
8269 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
8270 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8271 mask
>>= INTVAL (XEXP (x
, 1));
8275 op0
= gen_lowpart_or_truncate (op_mode
,
8276 force_to_mode (XEXP (x
, 0), op_mode
,
8277 mask
, next_select
));
8279 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8280 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8284 /* Here we can only do something if the shift count is a constant,
8285 this shift constant is valid for the host, and we can do arithmetic
8288 if (CONST_INT_P (XEXP (x
, 1))
8289 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8290 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8292 rtx inner
= XEXP (x
, 0);
8293 unsigned HOST_WIDE_INT inner_mask
;
8295 /* Select the mask of the bits we need for the shift operand. */
8296 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8298 /* We can only change the mode of the shift if we can do arithmetic
8299 in the mode of the shift and INNER_MASK is no wider than the
8300 width of X's mode. */
8301 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8302 op_mode
= GET_MODE (x
);
8304 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8306 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8307 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8310 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8311 shift and AND produces only copies of the sign bit (C2 is one less
8312 than a power of two), we can do this with just a shift. */
8314 if (GET_CODE (x
) == LSHIFTRT
8315 && CONST_INT_P (XEXP (x
, 1))
8316 /* The shift puts one of the sign bit copies in the least significant
8318 && ((INTVAL (XEXP (x
, 1))
8319 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8320 >= GET_MODE_BITSIZE (GET_MODE (x
)))
8321 && exact_log2 (mask
+ 1) >= 0
8322 /* Number of bits left after the shift must be more than the mask
8324 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8325 <= GET_MODE_BITSIZE (GET_MODE (x
)))
8326 /* Must be more sign bit copies than the mask needs. */
8327 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8328 >= exact_log2 (mask
+ 1)))
8329 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8330 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
8331 - exact_log2 (mask
+ 1)));
8336 /* If we are just looking for the sign bit, we don't need this shift at
8337 all, even if it has a variable count. */
8338 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8339 && (mask
== ((unsigned HOST_WIDE_INT
) 1
8340 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8341 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8343 /* If this is a shift by a constant, get a mask that contains those bits
8344 that are not copies of the sign bit. We then have two cases: If
8345 MASK only includes those bits, this can be a logical shift, which may
8346 allow simplifications. If MASK is a single-bit field not within
8347 those bits, we are requesting a copy of the sign bit and hence can
8348 shift the sign bit to the appropriate location. */
8350 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8351 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8355 /* If the considered data is wider than HOST_WIDE_INT, we can't
8356 represent a mask for all its bits in a single scalar.
8357 But we only care about the lower bits, so calculate these. */
8359 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8361 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8363 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8364 is the number of bits a full-width mask would have set.
8365 We need only shift if these are fewer than nonzero can
8366 hold. If not, we must keep all bits set in nonzero. */
8368 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8369 < HOST_BITS_PER_WIDE_INT
)
8370 nonzero
>>= INTVAL (XEXP (x
, 1))
8371 + HOST_BITS_PER_WIDE_INT
8372 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
8376 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8377 nonzero
>>= INTVAL (XEXP (x
, 1));
8380 if ((mask
& ~nonzero
) == 0)
8382 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8383 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8384 if (GET_CODE (x
) != ASHIFTRT
)
8385 return force_to_mode (x
, mode
, mask
, next_select
);
8388 else if ((i
= exact_log2 (mask
)) >= 0)
8390 x
= simplify_shift_const
8391 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8392 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
8394 if (GET_CODE (x
) != ASHIFTRT
)
8395 return force_to_mode (x
, mode
, mask
, next_select
);
8399 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8400 even if the shift count isn't a constant. */
8402 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8403 XEXP (x
, 0), XEXP (x
, 1));
8407 /* If this is a zero- or sign-extension operation that just affects bits
8408 we don't care about, remove it. Be sure the call above returned
8409 something that is still a shift. */
8411 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8412 && CONST_INT_P (XEXP (x
, 1))
8413 && INTVAL (XEXP (x
, 1)) >= 0
8414 && (INTVAL (XEXP (x
, 1))
8415 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8416 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8417 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8418 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8425 /* If the shift count is constant and we can do computations
8426 in the mode of X, compute where the bits we care about are.
8427 Otherwise, we can't do anything. Don't change the mode of
8428 the shift or propagate MODE into the shift, though. */
8429 if (CONST_INT_P (XEXP (x
, 1))
8430 && INTVAL (XEXP (x
, 1)) >= 0)
8432 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8433 GET_MODE (x
), GEN_INT (mask
),
8435 if (temp
&& CONST_INT_P (temp
))
8437 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8438 INTVAL (temp
), next_select
));
8443 /* If we just want the low-order bit, the NEG isn't needed since it
8444 won't change the low-order bit. */
8446 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8448 /* We need any bits less significant than the most significant bit in
8449 MASK since carries from those bits will affect the bits we are
8455 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8456 same as the XOR case above. Ensure that the constant we form is not
8457 wider than the mode of X. */
8459 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8460 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8461 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8462 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8463 < GET_MODE_BITSIZE (GET_MODE (x
)))
8464 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8466 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8468 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8469 XEXP (XEXP (x
, 0), 0), temp
);
8470 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8471 temp
, XEXP (XEXP (x
, 0), 1));
8473 return force_to_mode (x
, mode
, mask
, next_select
);
8476 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8477 use the full mask inside the NOT. */
8481 op0
= gen_lowpart_or_truncate (op_mode
,
8482 force_to_mode (XEXP (x
, 0), mode
, mask
,
8484 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8485 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8489 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8490 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8491 which is equal to STORE_FLAG_VALUE. */
8492 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8493 && XEXP (x
, 1) == const0_rtx
8494 && GET_MODE (XEXP (x
, 0)) == mode
8495 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8496 && (nonzero_bits (XEXP (x
, 0), mode
)
8497 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8498 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8503 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8504 written in a narrower mode. We play it safe and do not do so. */
8507 gen_lowpart_or_truncate (GET_MODE (x
),
8508 force_to_mode (XEXP (x
, 1), mode
,
8509 mask
, next_select
)));
8511 gen_lowpart_or_truncate (GET_MODE (x
),
8512 force_to_mode (XEXP (x
, 2), mode
,
8513 mask
, next_select
)));
8520 /* Ensure we return a value of the proper mode. */
8521 return gen_lowpart_or_truncate (mode
, x
);
8524 /* Return nonzero if X is an expression that has one of two values depending on
8525 whether some other value is zero or nonzero. In that case, we return the
8526 value that is being tested, *PTRUE is set to the value if the rtx being
8527 returned has a nonzero value, and *PFALSE is set to the other alternative.
8529 If we return zero, we set *PTRUE and *PFALSE to X. */
8532 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8534 enum machine_mode mode
= GET_MODE (x
);
8535 enum rtx_code code
= GET_CODE (x
);
8536 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8537 unsigned HOST_WIDE_INT nz
;
8539 /* If we are comparing a value against zero, we are done. */
8540 if ((code
== NE
|| code
== EQ
)
8541 && XEXP (x
, 1) == const0_rtx
)
8543 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8544 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8548 /* If this is a unary operation whose operand has one of two values, apply
8549 our opcode to compute those values. */
8550 else if (UNARY_P (x
)
8551 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8553 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8554 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8555 GET_MODE (XEXP (x
, 0)));
8559 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8560 make can't possibly match and would suppress other optimizations. */
8561 else if (code
== COMPARE
)
8564 /* If this is a binary operation, see if either side has only one of two
8565 values. If either one does or if both do and they are conditional on
8566 the same value, compute the new true and false values. */
8567 else if (BINARY_P (x
))
8569 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8570 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8572 if ((cond0
!= 0 || cond1
!= 0)
8573 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8575 /* If if_then_else_cond returned zero, then true/false are the
8576 same rtl. We must copy one of them to prevent invalid rtl
8579 true0
= copy_rtx (true0
);
8580 else if (cond1
== 0)
8581 true1
= copy_rtx (true1
);
8583 if (COMPARISON_P (x
))
8585 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8587 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8592 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8593 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8596 return cond0
? cond0
: cond1
;
8599 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8600 operands is zero when the other is nonzero, and vice-versa,
8601 and STORE_FLAG_VALUE is 1 or -1. */
8603 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8604 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8606 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8608 rtx op0
= XEXP (XEXP (x
, 0), 1);
8609 rtx op1
= XEXP (XEXP (x
, 1), 1);
8611 cond0
= XEXP (XEXP (x
, 0), 0);
8612 cond1
= XEXP (XEXP (x
, 1), 0);
8614 if (COMPARISON_P (cond0
)
8615 && COMPARISON_P (cond1
)
8616 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8617 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8618 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8619 || ((swap_condition (GET_CODE (cond0
))
8620 == reversed_comparison_code (cond1
, NULL
))
8621 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8622 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8623 && ! side_effects_p (x
))
8625 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8626 *pfalse
= simplify_gen_binary (MULT
, mode
,
8628 ? simplify_gen_unary (NEG
, mode
,
8636 /* Similarly for MULT, AND and UMIN, except that for these the result
8638 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8639 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8640 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8642 cond0
= XEXP (XEXP (x
, 0), 0);
8643 cond1
= XEXP (XEXP (x
, 1), 0);
8645 if (COMPARISON_P (cond0
)
8646 && COMPARISON_P (cond1
)
8647 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8648 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8649 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8650 || ((swap_condition (GET_CODE (cond0
))
8651 == reversed_comparison_code (cond1
, NULL
))
8652 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8653 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8654 && ! side_effects_p (x
))
8656 *ptrue
= *pfalse
= const0_rtx
;
8662 else if (code
== IF_THEN_ELSE
)
8664 /* If we have IF_THEN_ELSE already, extract the condition and
8665 canonicalize it if it is NE or EQ. */
8666 cond0
= XEXP (x
, 0);
8667 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8668 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8669 return XEXP (cond0
, 0);
8670 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8672 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8673 return XEXP (cond0
, 0);
8679 /* If X is a SUBREG, we can narrow both the true and false values
8680 if the inner expression, if there is a condition. */
8681 else if (code
== SUBREG
8682 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8685 true0
= simplify_gen_subreg (mode
, true0
,
8686 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8687 false0
= simplify_gen_subreg (mode
, false0
,
8688 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8689 if (true0
&& false0
)
8697 /* If X is a constant, this isn't special and will cause confusions
8698 if we treat it as such. Likewise if it is equivalent to a constant. */
8699 else if (CONSTANT_P (x
)
8700 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8703 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8704 will be least confusing to the rest of the compiler. */
8705 else if (mode
== BImode
)
8707 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8711 /* If X is known to be either 0 or -1, those are the true and
8712 false values when testing X. */
8713 else if (x
== constm1_rtx
|| x
== const0_rtx
8714 || (mode
!= VOIDmode
8715 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
8717 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8721 /* Likewise for 0 or a single bit. */
8722 else if (SCALAR_INT_MODE_P (mode
)
8723 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8724 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8726 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8730 /* Otherwise fail; show no condition with true and false values the same. */
8731 *ptrue
= *pfalse
= x
;
8735 /* Return the value of expression X given the fact that condition COND
8736 is known to be true when applied to REG as its first operand and VAL
8737 as its second. X is known to not be shared and so can be modified in
8740 We only handle the simplest cases, and specifically those cases that
8741 arise with IF_THEN_ELSE expressions. */
8744 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8746 enum rtx_code code
= GET_CODE (x
);
8751 if (side_effects_p (x
))
8754 /* If either operand of the condition is a floating point value,
8755 then we have to avoid collapsing an EQ comparison. */
8757 && rtx_equal_p (x
, reg
)
8758 && ! FLOAT_MODE_P (GET_MODE (x
))
8759 && ! FLOAT_MODE_P (GET_MODE (val
)))
8762 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8765 /* If X is (abs REG) and we know something about REG's relationship
8766 with zero, we may be able to simplify this. */
8768 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8771 case GE
: case GT
: case EQ
:
8774 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8776 GET_MODE (XEXP (x
, 0)));
8781 /* The only other cases we handle are MIN, MAX, and comparisons if the
8782 operands are the same as REG and VAL. */
8784 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8786 if (rtx_equal_p (XEXP (x
, 0), val
))
8787 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8789 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8791 if (COMPARISON_P (x
))
8793 if (comparison_dominates_p (cond
, code
))
8794 return const_true_rtx
;
8796 code
= reversed_comparison_code (x
, NULL
);
8798 && comparison_dominates_p (cond
, code
))
8803 else if (code
== SMAX
|| code
== SMIN
8804 || code
== UMIN
|| code
== UMAX
)
8806 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8808 /* Do not reverse the condition when it is NE or EQ.
8809 This is because we cannot conclude anything about
8810 the value of 'SMAX (x, y)' when x is not equal to y,
8811 but we can when x equals y. */
8812 if ((code
== SMAX
|| code
== UMAX
)
8813 && ! (cond
== EQ
|| cond
== NE
))
8814 cond
= reverse_condition (cond
);
8819 return unsignedp
? x
: XEXP (x
, 1);
8821 return unsignedp
? x
: XEXP (x
, 0);
8823 return unsignedp
? XEXP (x
, 1) : x
;
8825 return unsignedp
? XEXP (x
, 0) : x
;
8832 else if (code
== SUBREG
)
8834 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8835 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8837 if (SUBREG_REG (x
) != r
)
8839 /* We must simplify subreg here, before we lose track of the
8840 original inner_mode. */
8841 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8842 inner_mode
, SUBREG_BYTE (x
));
8846 SUBST (SUBREG_REG (x
), r
);
8851 /* We don't have to handle SIGN_EXTEND here, because even in the
8852 case of replacing something with a modeless CONST_INT, a
8853 CONST_INT is already (supposed to be) a valid sign extension for
8854 its narrower mode, which implies it's already properly
8855 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8856 story is different. */
8857 else if (code
== ZERO_EXTEND
)
8859 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8860 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8862 if (XEXP (x
, 0) != r
)
8864 /* We must simplify the zero_extend here, before we lose
8865 track of the original inner_mode. */
8866 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8871 SUBST (XEXP (x
, 0), r
);
8877 fmt
= GET_RTX_FORMAT (code
);
8878 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8881 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8882 else if (fmt
[i
] == 'E')
8883 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8884 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8891 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8892 assignment as a field assignment. */
8895 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8897 if (x
== y
|| rtx_equal_p (x
, y
))
8900 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8903 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8904 Note that all SUBREGs of MEM are paradoxical; otherwise they
8905 would have been rewritten. */
8906 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8907 && MEM_P (SUBREG_REG (y
))
8908 && rtx_equal_p (SUBREG_REG (y
),
8909 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8912 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8913 && MEM_P (SUBREG_REG (x
))
8914 && rtx_equal_p (SUBREG_REG (x
),
8915 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8918 /* We used to see if get_last_value of X and Y were the same but that's
8919 not correct. In one direction, we'll cause the assignment to have
8920 the wrong destination and in the case, we'll import a register into this
8921 insn that might have already have been dead. So fail if none of the
8922 above cases are true. */
8926 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8927 Return that assignment if so.
8929 We only handle the most common cases. */
8932 make_field_assignment (rtx x
)
8934 rtx dest
= SET_DEST (x
);
8935 rtx src
= SET_SRC (x
);
8940 unsigned HOST_WIDE_INT len
;
8942 enum machine_mode mode
;
8944 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8945 a clear of a one-bit field. We will have changed it to
8946 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8949 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8950 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8951 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8952 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8954 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8957 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8961 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8962 && subreg_lowpart_p (XEXP (src
, 0))
8963 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8964 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8965 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8966 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8967 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8968 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8970 assign
= make_extraction (VOIDmode
, dest
, 0,
8971 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8974 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8978 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8980 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8981 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8982 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8984 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8987 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8991 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8992 SRC is an AND with all bits of that field set, then we can discard
8994 if (GET_CODE (dest
) == ZERO_EXTRACT
8995 && CONST_INT_P (XEXP (dest
, 1))
8996 && GET_CODE (src
) == AND
8997 && CONST_INT_P (XEXP (src
, 1)))
8999 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9000 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9001 unsigned HOST_WIDE_INT ze_mask
;
9003 if (width
>= HOST_BITS_PER_WIDE_INT
)
9006 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9008 /* Complete overlap. We can remove the source AND. */
9009 if ((and_mask
& ze_mask
) == ze_mask
)
9010 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9012 /* Partial overlap. We can reduce the source AND. */
9013 if ((and_mask
& ze_mask
) != and_mask
)
9015 mode
= GET_MODE (src
);
9016 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9017 gen_int_mode (and_mask
& ze_mask
, mode
));
9018 return gen_rtx_SET (VOIDmode
, dest
, src
);
9022 /* The other case we handle is assignments into a constant-position
9023 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9024 a mask that has all one bits except for a group of zero bits and
9025 OTHER is known to have zeros where C1 has ones, this is such an
9026 assignment. Compute the position and length from C1. Shift OTHER
9027 to the appropriate position, force it to the required mode, and
9028 make the extraction. Check for the AND in both operands. */
9030 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9033 rhs
= expand_compound_operation (XEXP (src
, 0));
9034 lhs
= expand_compound_operation (XEXP (src
, 1));
9036 if (GET_CODE (rhs
) == AND
9037 && CONST_INT_P (XEXP (rhs
, 1))
9038 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9039 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9040 else if (GET_CODE (lhs
) == AND
9041 && CONST_INT_P (XEXP (lhs
, 1))
9042 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9043 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9047 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9048 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
9049 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9050 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9053 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9057 /* The mode to use for the source is the mode of the assignment, or of
9058 what is inside a possible STRICT_LOW_PART. */
9059 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9060 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9062 /* Shift OTHER right POS places and make it the source, restricting it
9063 to the proper length and mode. */
9065 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9069 src
= force_to_mode (src
, mode
,
9070 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
9071 ? ~(unsigned HOST_WIDE_INT
) 0
9072 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9075 /* If SRC is masked by an AND that does not make a difference in
9076 the value being stored, strip it. */
9077 if (GET_CODE (assign
) == ZERO_EXTRACT
9078 && CONST_INT_P (XEXP (assign
, 1))
9079 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9080 && GET_CODE (src
) == AND
9081 && CONST_INT_P (XEXP (src
, 1))
9082 && UINTVAL (XEXP (src
, 1))
9083 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9084 src
= XEXP (src
, 0);
9086 return gen_rtx_SET (VOIDmode
, assign
, src
);
9089 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9093 apply_distributive_law (rtx x
)
9095 enum rtx_code code
= GET_CODE (x
);
9096 enum rtx_code inner_code
;
9097 rtx lhs
, rhs
, other
;
9100 /* Distributivity is not true for floating point as it can change the
9101 value. So we don't do it unless -funsafe-math-optimizations. */
9102 if (FLOAT_MODE_P (GET_MODE (x
))
9103 && ! flag_unsafe_math_optimizations
)
9106 /* The outer operation can only be one of the following: */
9107 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9108 && code
!= PLUS
&& code
!= MINUS
)
9114 /* If either operand is a primitive we can't do anything, so get out
9116 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9119 lhs
= expand_compound_operation (lhs
);
9120 rhs
= expand_compound_operation (rhs
);
9121 inner_code
= GET_CODE (lhs
);
9122 if (inner_code
!= GET_CODE (rhs
))
9125 /* See if the inner and outer operations distribute. */
9132 /* These all distribute except over PLUS. */
9133 if (code
== PLUS
|| code
== MINUS
)
9138 if (code
!= PLUS
&& code
!= MINUS
)
9143 /* This is also a multiply, so it distributes over everything. */
9147 /* Non-paradoxical SUBREGs distributes over all operations,
9148 provided the inner modes and byte offsets are the same, this
9149 is an extraction of a low-order part, we don't convert an fp
9150 operation to int or vice versa, this is not a vector mode,
9151 and we would not be converting a single-word operation into a
9152 multi-word operation. The latter test is not required, but
9153 it prevents generating unneeded multi-word operations. Some
9154 of the previous tests are redundant given the latter test,
9155 but are retained because they are required for correctness.
9157 We produce the result slightly differently in this case. */
9159 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
9160 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
9161 || ! subreg_lowpart_p (lhs
)
9162 || (GET_MODE_CLASS (GET_MODE (lhs
))
9163 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
9164 || (GET_MODE_SIZE (GET_MODE (lhs
))
9165 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
9166 || VECTOR_MODE_P (GET_MODE (lhs
))
9167 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
9168 /* Result might need to be truncated. Don't change mode if
9169 explicit truncation is needed. */
9170 || !TRULY_NOOP_TRUNCATION
9171 (GET_MODE_BITSIZE (GET_MODE (x
)),
9172 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
9175 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
9176 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
9177 return gen_lowpart (GET_MODE (x
), tem
);
9183 /* Set LHS and RHS to the inner operands (A and B in the example
9184 above) and set OTHER to the common operand (C in the example).
9185 There is only one way to do this unless the inner operation is
9187 if (COMMUTATIVE_ARITH_P (lhs
)
9188 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9189 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9190 else if (COMMUTATIVE_ARITH_P (lhs
)
9191 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9192 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9193 else if (COMMUTATIVE_ARITH_P (lhs
)
9194 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9195 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9196 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9197 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9201 /* Form the new inner operation, seeing if it simplifies first. */
9202 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9204 /* There is one exception to the general way of distributing:
9205 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9206 if (code
== XOR
&& inner_code
== IOR
)
9209 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9212 /* We may be able to continuing distributing the result, so call
9213 ourselves recursively on the inner operation before forming the
9214 outer operation, which we return. */
9215 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9216 apply_distributive_law (tem
), other
);
9219 /* See if X is of the form (* (+ A B) C), and if so convert to
9220 (+ (* A C) (* B C)) and try to simplify.
9222 Most of the time, this results in no change. However, if some of
9223 the operands are the same or inverses of each other, simplifications
9226 For example, (and (ior A B) (not B)) can occur as the result of
9227 expanding a bit field assignment. When we apply the distributive
9228 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9229 which then simplifies to (and (A (not B))).
9231 Note that no checks happen on the validity of applying the inverse
9232 distributive law. This is pointless since we can do it in the
9233 few places where this routine is called.
9235 N is the index of the term that is decomposed (the arithmetic operation,
9236 i.e. (+ A B) in the first example above). !N is the index of the term that
9237 is distributed, i.e. of C in the first example above. */
9239 distribute_and_simplify_rtx (rtx x
, int n
)
9241 enum machine_mode mode
;
9242 enum rtx_code outer_code
, inner_code
;
9243 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9245 /* Distributivity is not true for floating point as it can change the
9246 value. So we don't do it unless -funsafe-math-optimizations. */
9247 if (FLOAT_MODE_P (GET_MODE (x
))
9248 && ! flag_unsafe_math_optimizations
)
9251 decomposed
= XEXP (x
, n
);
9252 if (!ARITHMETIC_P (decomposed
))
9255 mode
= GET_MODE (x
);
9256 outer_code
= GET_CODE (x
);
9257 distributed
= XEXP (x
, !n
);
9259 inner_code
= GET_CODE (decomposed
);
9260 inner_op0
= XEXP (decomposed
, 0);
9261 inner_op1
= XEXP (decomposed
, 1);
9263 /* Special case (and (xor B C) (not A)), which is equivalent to
9264 (xor (ior A B) (ior A C)) */
9265 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9267 distributed
= XEXP (distributed
, 0);
9273 /* Distribute the second term. */
9274 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9275 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9279 /* Distribute the first term. */
9280 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9281 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9284 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9286 if (GET_CODE (tmp
) != outer_code
9287 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
9288 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
9294 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9295 in MODE. Return an equivalent form, if different from (and VAROP
9296 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9299 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9300 unsigned HOST_WIDE_INT constop
)
9302 unsigned HOST_WIDE_INT nonzero
;
9303 unsigned HOST_WIDE_INT orig_constop
;
9308 orig_constop
= constop
;
9309 if (GET_CODE (varop
) == CLOBBER
)
9312 /* Simplify VAROP knowing that we will be only looking at some of the
9315 Note by passing in CONSTOP, we guarantee that the bits not set in
9316 CONSTOP are not significant and will never be examined. We must
9317 ensure that is the case by explicitly masking out those bits
9318 before returning. */
9319 varop
= force_to_mode (varop
, mode
, constop
, 0);
9321 /* If VAROP is a CLOBBER, we will fail so return it. */
9322 if (GET_CODE (varop
) == CLOBBER
)
9325 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9326 to VAROP and return the new constant. */
9327 if (CONST_INT_P (varop
))
9328 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9330 /* See what bits may be nonzero in VAROP. Unlike the general case of
9331 a call to nonzero_bits, here we don't care about bits outside
9334 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9336 /* Turn off all bits in the constant that are known to already be zero.
9337 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9338 which is tested below. */
9342 /* If we don't have any bits left, return zero. */
9346 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9347 a power of two, we can replace this with an ASHIFT. */
9348 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9349 && (i
= exact_log2 (constop
)) >= 0)
9350 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9352 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9353 or XOR, then try to apply the distributive law. This may eliminate
9354 operations if either branch can be simplified because of the AND.
9355 It may also make some cases more complex, but those cases probably
9356 won't match a pattern either with or without this. */
9358 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9362 apply_distributive_law
9363 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9364 simplify_and_const_int (NULL_RTX
,
9368 simplify_and_const_int (NULL_RTX
,
9373 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9374 the AND and see if one of the operands simplifies to zero. If so, we
9375 may eliminate it. */
9377 if (GET_CODE (varop
) == PLUS
9378 && exact_log2 (constop
+ 1) >= 0)
9382 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9383 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9384 if (o0
== const0_rtx
)
9386 if (o1
== const0_rtx
)
9390 /* Make a SUBREG if necessary. If we can't make it, fail. */
9391 varop
= gen_lowpart (mode
, varop
);
9392 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9395 /* If we are only masking insignificant bits, return VAROP. */
9396 if (constop
== nonzero
)
9399 if (varop
== orig_varop
&& constop
== orig_constop
)
9402 /* Otherwise, return an AND. */
9403 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9407 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9410 Return an equivalent form, if different from X. Otherwise, return X. If
9411 X is zero, we are to always construct the equivalent form. */
9414 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9415 unsigned HOST_WIDE_INT constop
)
9417 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9422 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9423 gen_int_mode (constop
, mode
));
9424 if (GET_MODE (x
) != mode
)
9425 x
= gen_lowpart (mode
, x
);
9429 /* Given a REG, X, compute which bits in X can be nonzero.
9430 We don't care about bits outside of those defined in MODE.
9432 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9433 a shift, AND, or zero_extract, we can do better. */
9436 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9437 const_rtx known_x ATTRIBUTE_UNUSED
,
9438 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9439 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9440 unsigned HOST_WIDE_INT
*nonzero
)
9445 /* If X is a register whose nonzero bits value is current, use it.
9446 Otherwise, if X is a register whose value we can find, use that
9447 value. Otherwise, use the previously-computed global nonzero bits
9448 for this register. */
9450 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9451 if (rsp
->last_set_value
!= 0
9452 && (rsp
->last_set_mode
== mode
9453 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9454 && GET_MODE_CLASS (mode
) == MODE_INT
))
9455 && ((rsp
->last_set_label
>= label_tick_ebb_start
9456 && rsp
->last_set_label
< label_tick
)
9457 || (rsp
->last_set_label
== label_tick
9458 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9459 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9460 && REG_N_SETS (REGNO (x
)) == 1
9462 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9464 *nonzero
&= rsp
->last_set_nonzero_bits
;
9468 tem
= get_last_value (x
);
9472 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9473 /* If X is narrower than MODE and TEM is a non-negative
9474 constant that would appear negative in the mode of X,
9475 sign-extend it for use in reg_nonzero_bits because some
9476 machines (maybe most) will actually do the sign-extension
9477 and this is the conservative approach.
9479 ??? For 2.5, try to tighten up the MD files in this regard
9480 instead of this kludge. */
9482 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
9483 && CONST_INT_P (tem
)
9485 && 0 != (UINTVAL (tem
)
9486 & ((unsigned HOST_WIDE_INT
) 1
9487 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
9488 tem
= GEN_INT (UINTVAL (tem
)
9489 | ((unsigned HOST_WIDE_INT
) (-1)
9490 << GET_MODE_BITSIZE (GET_MODE (x
))));
9494 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9496 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9498 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
9499 /* We don't know anything about the upper bits. */
9500 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9507 /* Return the number of bits at the high-order end of X that are known to
9508 be equal to the sign bit. X will be used in mode MODE; if MODE is
9509 VOIDmode, X will be used in its own mode. The returned value will always
9510 be between 1 and the number of bits in MODE. */
9513 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9514 const_rtx known_x ATTRIBUTE_UNUSED
,
9515 enum machine_mode known_mode
9517 unsigned int known_ret ATTRIBUTE_UNUSED
,
9518 unsigned int *result
)
9523 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9524 if (rsp
->last_set_value
!= 0
9525 && rsp
->last_set_mode
== mode
9526 && ((rsp
->last_set_label
>= label_tick_ebb_start
9527 && rsp
->last_set_label
< label_tick
)
9528 || (rsp
->last_set_label
== label_tick
9529 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9530 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9531 && REG_N_SETS (REGNO (x
)) == 1
9533 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9535 *result
= rsp
->last_set_sign_bit_copies
;
9539 tem
= get_last_value (x
);
9543 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9544 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
9545 *result
= rsp
->sign_bit_copies
;
9550 /* Return the number of "extended" bits there are in X, when interpreted
9551 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9552 unsigned quantities, this is the number of high-order zero bits.
9553 For signed quantities, this is the number of copies of the sign bit
9554 minus 1. In both case, this function returns the number of "spare"
9555 bits. For example, if two quantities for which this function returns
9556 at least 1 are added, the addition is known not to overflow.
9558 This function will always return 0 unless called during combine, which
9559 implies that it must be called from a define_split. */
9562 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9564 if (nonzero_sign_valid
== 0)
9568 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9569 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9570 - floor_log2 (nonzero_bits (x
, mode
)))
9572 : num_sign_bit_copies (x
, mode
) - 1);
9575 /* This function is called from `simplify_shift_const' to merge two
9576 outer operations. Specifically, we have already found that we need
9577 to perform operation *POP0 with constant *PCONST0 at the outermost
9578 position. We would now like to also perform OP1 with constant CONST1
9579 (with *POP0 being done last).
9581 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9582 the resulting operation. *PCOMP_P is set to 1 if we would need to
9583 complement the innermost operand, otherwise it is unchanged.
9585 MODE is the mode in which the operation will be done. No bits outside
9586 the width of this mode matter. It is assumed that the width of this mode
9587 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9589 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9590 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9591 result is simply *PCONST0.
9593 If the resulting operation cannot be expressed as one operation, we
9594 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9597 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9599 enum rtx_code op0
= *pop0
;
9600 HOST_WIDE_INT const0
= *pconst0
;
9602 const0
&= GET_MODE_MASK (mode
);
9603 const1
&= GET_MODE_MASK (mode
);
9605 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9609 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9612 if (op1
== UNKNOWN
|| op0
== SET
)
9615 else if (op0
== UNKNOWN
)
9616 op0
= op1
, const0
= const1
;
9618 else if (op0
== op1
)
9642 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9643 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9646 /* If the two constants aren't the same, we can't do anything. The
9647 remaining six cases can all be done. */
9648 else if (const0
!= const1
)
9656 /* (a & b) | b == b */
9658 else /* op1 == XOR */
9659 /* (a ^ b) | b == a | b */
9665 /* (a & b) ^ b == (~a) & b */
9666 op0
= AND
, *pcomp_p
= 1;
9667 else /* op1 == IOR */
9668 /* (a | b) ^ b == a & ~b */
9669 op0
= AND
, const0
= ~const0
;
9674 /* (a | b) & b == b */
9676 else /* op1 == XOR */
9677 /* (a ^ b) & b) == (~a) & b */
9684 /* Check for NO-OP cases. */
9685 const0
&= GET_MODE_MASK (mode
);
9687 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9689 else if (const0
== 0 && op0
== AND
)
9691 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9697 /* ??? Slightly redundant with the above mask, but not entirely.
9698 Moving this above means we'd have to sign-extend the mode mask
9699 for the final test. */
9700 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9701 *pconst0
= trunc_int_for_mode (const0
, mode
);
9706 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9707 the shift in. The original shift operation CODE is performed on OP in
9708 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9709 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9710 result of the shift is subject to operation OUTER_CODE with operand
9713 static enum machine_mode
9714 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9715 enum machine_mode orig_mode
, enum machine_mode mode
,
9716 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9718 if (orig_mode
== mode
)
9720 gcc_assert (GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (orig_mode
));
9722 /* In general we can't perform in wider mode for right shift and rotate. */
9726 /* We can still widen if the bits brought in from the left are identical
9727 to the sign bit of ORIG_MODE. */
9728 if (num_sign_bit_copies (op
, mode
)
9729 > (unsigned) (GET_MODE_BITSIZE (mode
)
9730 - GET_MODE_BITSIZE (orig_mode
)))
9735 /* Similarly here but with zero bits. */
9736 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9737 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9740 /* We can also widen if the bits brought in will be masked off. This
9741 operation is performed in ORIG_MODE. */
9742 if (outer_code
== AND
)
9744 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9747 && GET_MODE_BITSIZE (orig_mode
) - care_bits
>= count
)
9763 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9764 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9765 simplify it. Otherwise, return a simplified value.
9767 The shift is normally computed in the widest mode we find in VAROP, as
9768 long as it isn't a different number of words than RESULT_MODE. Exceptions
9769 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9772 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9773 rtx varop
, int orig_count
)
9775 enum rtx_code orig_code
= code
;
9776 rtx orig_varop
= varop
;
9778 enum machine_mode mode
= result_mode
;
9779 enum machine_mode shift_mode
, tmode
;
9780 unsigned int mode_words
9781 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9782 /* We form (outer_op (code varop count) (outer_const)). */
9783 enum rtx_code outer_op
= UNKNOWN
;
9784 HOST_WIDE_INT outer_const
= 0;
9785 int complement_p
= 0;
9788 /* Make sure and truncate the "natural" shift on the way in. We don't
9789 want to do this inside the loop as it makes it more difficult to
9791 if (SHIFT_COUNT_TRUNCATED
)
9792 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9794 /* If we were given an invalid count, don't do anything except exactly
9795 what was requested. */
9797 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9802 /* Unless one of the branches of the `if' in this loop does a `continue',
9803 we will `break' the loop after the `if'. */
9807 /* If we have an operand of (clobber (const_int 0)), fail. */
9808 if (GET_CODE (varop
) == CLOBBER
)
9811 /* Convert ROTATERT to ROTATE. */
9812 if (code
== ROTATERT
)
9814 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9816 if (VECTOR_MODE_P (result_mode
))
9817 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9819 count
= bitsize
- count
;
9822 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9823 mode
, outer_op
, outer_const
);
9825 /* Handle cases where the count is greater than the size of the mode
9826 minus 1. For ASHIFT, use the size minus one as the count (this can
9827 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9828 take the count modulo the size. For other shifts, the result is
9831 Since these shifts are being produced by the compiler by combining
9832 multiple operations, each of which are defined, we know what the
9833 result is supposed to be. */
9835 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9837 if (code
== ASHIFTRT
)
9838 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9839 else if (code
== ROTATE
|| code
== ROTATERT
)
9840 count
%= GET_MODE_BITSIZE (shift_mode
);
9843 /* We can't simply return zero because there may be an
9851 /* If we discovered we had to complement VAROP, leave. Making a NOT
9852 here would cause an infinite loop. */
9856 /* An arithmetic right shift of a quantity known to be -1 or 0
9858 if (code
== ASHIFTRT
9859 && (num_sign_bit_copies (varop
, shift_mode
)
9860 == GET_MODE_BITSIZE (shift_mode
)))
9866 /* If we are doing an arithmetic right shift and discarding all but
9867 the sign bit copies, this is equivalent to doing a shift by the
9868 bitsize minus one. Convert it into that shift because it will often
9869 allow other simplifications. */
9871 if (code
== ASHIFTRT
9872 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9873 >= GET_MODE_BITSIZE (shift_mode
)))
9874 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9876 /* We simplify the tests below and elsewhere by converting
9877 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9878 `make_compound_operation' will convert it to an ASHIFTRT for
9879 those machines (such as VAX) that don't have an LSHIFTRT. */
9880 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9882 && ((nonzero_bits (varop
, shift_mode
)
9883 & ((unsigned HOST_WIDE_INT
) 1
9884 << (GET_MODE_BITSIZE (shift_mode
) - 1))) == 0))
9887 if (((code
== LSHIFTRT
9888 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9889 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9891 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9892 && !((nonzero_bits (varop
, shift_mode
) << count
)
9893 & GET_MODE_MASK (shift_mode
))))
9894 && !side_effects_p (varop
))
9897 switch (GET_CODE (varop
))
9903 new_rtx
= expand_compound_operation (varop
);
9904 if (new_rtx
!= varop
)
9912 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9913 minus the width of a smaller mode, we can do this with a
9914 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9915 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9916 && ! mode_dependent_address_p (XEXP (varop
, 0))
9917 && ! MEM_VOLATILE_P (varop
)
9918 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9919 MODE_INT
, 1)) != BLKmode
)
9921 new_rtx
= adjust_address_nv (varop
, tmode
,
9922 BYTES_BIG_ENDIAN
? 0
9923 : count
/ BITS_PER_UNIT
);
9925 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9926 : ZERO_EXTEND
, mode
, new_rtx
);
9933 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9934 the same number of words as what we've seen so far. Then store
9935 the widest mode in MODE. */
9936 if (subreg_lowpart_p (varop
)
9937 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9938 > GET_MODE_SIZE (GET_MODE (varop
)))
9939 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9940 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9942 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9943 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9945 varop
= SUBREG_REG (varop
);
9946 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9947 mode
= GET_MODE (varop
);
9953 /* Some machines use MULT instead of ASHIFT because MULT
9954 is cheaper. But it is still better on those machines to
9955 merge two shifts into one. */
9956 if (CONST_INT_P (XEXP (varop
, 1))
9957 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9960 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9962 GEN_INT (exact_log2 (
9963 UINTVAL (XEXP (varop
, 1)))));
9969 /* Similar, for when divides are cheaper. */
9970 if (CONST_INT_P (XEXP (varop
, 1))
9971 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9974 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9976 GEN_INT (exact_log2 (
9977 UINTVAL (XEXP (varop
, 1)))));
9983 /* If we are extracting just the sign bit of an arithmetic
9984 right shift, that shift is not needed. However, the sign
9985 bit of a wider mode may be different from what would be
9986 interpreted as the sign bit in a narrower mode, so, if
9987 the result is narrower, don't discard the shift. */
9988 if (code
== LSHIFTRT
9989 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9990 && (GET_MODE_BITSIZE (result_mode
)
9991 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9993 varop
= XEXP (varop
, 0);
9997 /* ... fall through ... */
10002 /* Here we have two nested shifts. The result is usually the
10003 AND of a new shift with a mask. We compute the result below. */
10004 if (CONST_INT_P (XEXP (varop
, 1))
10005 && INTVAL (XEXP (varop
, 1)) >= 0
10006 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
10007 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10008 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10009 && !VECTOR_MODE_P (result_mode
))
10011 enum rtx_code first_code
= GET_CODE (varop
);
10012 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10013 unsigned HOST_WIDE_INT mask
;
10016 /* We have one common special case. We can't do any merging if
10017 the inner code is an ASHIFTRT of a smaller mode. However, if
10018 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10019 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10020 we can convert it to
10021 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10022 This simplifies certain SIGN_EXTEND operations. */
10023 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10024 && count
== (GET_MODE_BITSIZE (result_mode
)
10025 - GET_MODE_BITSIZE (GET_MODE (varop
))))
10027 /* C3 has the low-order C1 bits zero. */
10029 mask
= GET_MODE_MASK (mode
)
10030 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10032 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10033 XEXP (varop
, 0), mask
);
10034 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10036 count
= first_count
;
10041 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10042 than C1 high-order bits equal to the sign bit, we can convert
10043 this to either an ASHIFT or an ASHIFTRT depending on the
10046 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10048 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10049 && GET_MODE (varop
) == shift_mode
10050 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10053 varop
= XEXP (varop
, 0);
10054 count
-= first_count
;
10064 /* There are some cases we can't do. If CODE is ASHIFTRT,
10065 we can only do this if FIRST_CODE is also ASHIFTRT.
10067 We can't do the case when CODE is ROTATE and FIRST_CODE is
10070 If the mode of this shift is not the mode of the outer shift,
10071 we can't do this if either shift is a right shift or ROTATE.
10073 Finally, we can't do any of these if the mode is too wide
10074 unless the codes are the same.
10076 Handle the case where the shift codes are the same
10079 if (code
== first_code
)
10081 if (GET_MODE (varop
) != result_mode
10082 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10083 || code
== ROTATE
))
10086 count
+= first_count
;
10087 varop
= XEXP (varop
, 0);
10091 if (code
== ASHIFTRT
10092 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10093 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
10094 || (GET_MODE (varop
) != result_mode
10095 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10096 || first_code
== ROTATE
10097 || code
== ROTATE
)))
10100 /* To compute the mask to apply after the shift, shift the
10101 nonzero bits of the inner shift the same way the
10102 outer shift will. */
10104 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10107 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10110 /* Give up if we can't compute an outer operation to use. */
10112 || !CONST_INT_P (mask_rtx
)
10113 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10115 result_mode
, &complement_p
))
10118 /* If the shifts are in the same direction, we add the
10119 counts. Otherwise, we subtract them. */
10120 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10121 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10122 count
+= first_count
;
10124 count
-= first_count
;
10126 /* If COUNT is positive, the new shift is usually CODE,
10127 except for the two exceptions below, in which case it is
10128 FIRST_CODE. If the count is negative, FIRST_CODE should
10131 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10132 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10134 else if (count
< 0)
10135 code
= first_code
, count
= -count
;
10137 varop
= XEXP (varop
, 0);
10141 /* If we have (A << B << C) for any shift, we can convert this to
10142 (A << C << B). This wins if A is a constant. Only try this if
10143 B is not a constant. */
10145 else if (GET_CODE (varop
) == code
10146 && CONST_INT_P (XEXP (varop
, 0))
10147 && !CONST_INT_P (XEXP (varop
, 1)))
10149 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10152 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10159 if (VECTOR_MODE_P (mode
))
10162 /* Make this fit the case below. */
10163 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
10164 GEN_INT (GET_MODE_MASK (mode
)));
10170 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10171 with C the size of VAROP - 1 and the shift is logical if
10172 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10173 we have an (le X 0) operation. If we have an arithmetic shift
10174 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10175 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10177 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10178 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10179 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10180 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10181 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10182 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10185 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10188 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10189 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10194 /* If we have (shift (logical)), move the logical to the outside
10195 to allow it to possibly combine with another logical and the
10196 shift to combine with another shift. This also canonicalizes to
10197 what a ZERO_EXTRACT looks like. Also, some machines have
10198 (and (shift)) insns. */
10200 if (CONST_INT_P (XEXP (varop
, 1))
10201 /* We can't do this if we have (ashiftrt (xor)) and the
10202 constant has its sign bit set in shift_mode. */
10203 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10204 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10206 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10208 GEN_INT (count
))) != 0
10209 && CONST_INT_P (new_rtx
)
10210 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10211 INTVAL (new_rtx
), result_mode
, &complement_p
))
10213 varop
= XEXP (varop
, 0);
10217 /* If we can't do that, try to simplify the shift in each arm of the
10218 logical expression, make a new logical expression, and apply
10219 the inverse distributive law. This also can't be done
10220 for some (ashiftrt (xor)). */
10221 if (CONST_INT_P (XEXP (varop
, 1))
10222 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10223 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10226 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10227 XEXP (varop
, 0), count
);
10228 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10229 XEXP (varop
, 1), count
);
10231 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10233 varop
= apply_distributive_law (varop
);
10241 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10242 says that the sign bit can be tested, FOO has mode MODE, C is
10243 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10244 that may be nonzero. */
10245 if (code
== LSHIFTRT
10246 && XEXP (varop
, 1) == const0_rtx
10247 && GET_MODE (XEXP (varop
, 0)) == result_mode
10248 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10249 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10250 && STORE_FLAG_VALUE
== -1
10251 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10252 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10255 varop
= XEXP (varop
, 0);
10262 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10263 than the number of bits in the mode is equivalent to A. */
10264 if (code
== LSHIFTRT
10265 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10266 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10268 varop
= XEXP (varop
, 0);
10273 /* NEG commutes with ASHIFT since it is multiplication. Move the
10274 NEG outside to allow shifts to combine. */
10276 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10279 varop
= XEXP (varop
, 0);
10285 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10286 is one less than the number of bits in the mode is
10287 equivalent to (xor A 1). */
10288 if (code
== LSHIFTRT
10289 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10290 && XEXP (varop
, 1) == constm1_rtx
10291 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10292 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10296 varop
= XEXP (varop
, 0);
10300 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10301 that might be nonzero in BAR are those being shifted out and those
10302 bits are known zero in FOO, we can replace the PLUS with FOO.
10303 Similarly in the other operand order. This code occurs when
10304 we are computing the size of a variable-size array. */
10306 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10307 && count
< HOST_BITS_PER_WIDE_INT
10308 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10309 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10310 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10312 varop
= XEXP (varop
, 0);
10315 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10316 && count
< HOST_BITS_PER_WIDE_INT
10317 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10318 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10320 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10321 & nonzero_bits (XEXP (varop
, 1),
10324 varop
= XEXP (varop
, 1);
10328 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10330 && CONST_INT_P (XEXP (varop
, 1))
10331 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10333 GEN_INT (count
))) != 0
10334 && CONST_INT_P (new_rtx
)
10335 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10336 INTVAL (new_rtx
), result_mode
, &complement_p
))
10338 varop
= XEXP (varop
, 0);
10342 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10343 signbit', and attempt to change the PLUS to an XOR and move it to
10344 the outer operation as is done above in the AND/IOR/XOR case
10345 leg for shift(logical). See details in logical handling above
10346 for reasoning in doing so. */
10347 if (code
== LSHIFTRT
10348 && CONST_INT_P (XEXP (varop
, 1))
10349 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10350 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10352 GEN_INT (count
))) != 0
10353 && CONST_INT_P (new_rtx
)
10354 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10355 INTVAL (new_rtx
), result_mode
, &complement_p
))
10357 varop
= XEXP (varop
, 0);
10364 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10365 with C the size of VAROP - 1 and the shift is logical if
10366 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10367 we have a (gt X 0) operation. If the shift is arithmetic with
10368 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10369 we have a (neg (gt X 0)) operation. */
10371 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10372 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10373 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10374 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10375 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10376 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10377 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10380 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10383 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10384 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10391 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10392 if the truncate does not affect the value. */
10393 if (code
== LSHIFTRT
10394 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10395 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10396 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10397 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
10398 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
10400 rtx varop_inner
= XEXP (varop
, 0);
10403 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10404 XEXP (varop_inner
, 0),
10406 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10407 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10420 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10421 outer_op
, outer_const
);
10423 /* We have now finished analyzing the shift. The result should be
10424 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10425 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10426 to the result of the shift. OUTER_CONST is the relevant constant,
10427 but we must turn off all bits turned off in the shift. */
10429 if (outer_op
== UNKNOWN
10430 && orig_code
== code
&& orig_count
== count
10431 && varop
== orig_varop
10432 && shift_mode
== GET_MODE (varop
))
10435 /* Make a SUBREG if necessary. If we can't make it, fail. */
10436 varop
= gen_lowpart (shift_mode
, varop
);
10437 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10440 /* If we have an outer operation and we just made a shift, it is
10441 possible that we could have simplified the shift were it not
10442 for the outer operation. So try to do the simplification
10445 if (outer_op
!= UNKNOWN
)
10446 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10451 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10453 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10454 turn off all the bits that the shift would have turned off. */
10455 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10456 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10457 GET_MODE_MASK (result_mode
) >> orig_count
);
10459 /* Do the remainder of the processing in RESULT_MODE. */
10460 x
= gen_lowpart_or_truncate (result_mode
, x
);
10462 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10465 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10467 if (outer_op
!= UNKNOWN
)
10469 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10470 && GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10471 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10473 if (outer_op
== AND
)
10474 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10475 else if (outer_op
== SET
)
10477 /* This means that we have determined that the result is
10478 equivalent to a constant. This should be rare. */
10479 if (!side_effects_p (x
))
10480 x
= GEN_INT (outer_const
);
10482 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10483 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10485 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10486 GEN_INT (outer_const
));
10492 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10493 The result of the shift is RESULT_MODE. If we cannot simplify it,
10494 return X or, if it is NULL, synthesize the expression with
10495 simplify_gen_binary. Otherwise, return a simplified value.
10497 The shift is normally computed in the widest mode we find in VAROP, as
10498 long as it isn't a different number of words than RESULT_MODE. Exceptions
10499 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10502 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10503 rtx varop
, int count
)
10505 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10510 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10511 if (GET_MODE (x
) != result_mode
)
10512 x
= gen_lowpart (result_mode
, x
);
10517 /* Like recog, but we receive the address of a pointer to a new pattern.
10518 We try to match the rtx that the pointer points to.
10519 If that fails, we may try to modify or replace the pattern,
10520 storing the replacement into the same pointer object.
10522 Modifications include deletion or addition of CLOBBERs.
10524 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10525 the CLOBBERs are placed.
10527 The value is the final insn code from the pattern ultimately matched,
10531 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10533 rtx pat
= *pnewpat
;
10534 int insn_code_number
;
10535 int num_clobbers_to_add
= 0;
10538 rtx old_notes
, old_pat
;
10540 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10541 we use to indicate that something didn't match. If we find such a
10542 thing, force rejection. */
10543 if (GET_CODE (pat
) == PARALLEL
)
10544 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10545 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10546 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10549 old_pat
= PATTERN (insn
);
10550 old_notes
= REG_NOTES (insn
);
10551 PATTERN (insn
) = pat
;
10552 REG_NOTES (insn
) = 0;
10554 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10555 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10557 if (insn_code_number
< 0)
10558 fputs ("Failed to match this instruction:\n", dump_file
);
10560 fputs ("Successfully matched this instruction:\n", dump_file
);
10561 print_rtl_single (dump_file
, pat
);
10564 /* If it isn't, there is the possibility that we previously had an insn
10565 that clobbered some register as a side effect, but the combined
10566 insn doesn't need to do that. So try once more without the clobbers
10567 unless this represents an ASM insn. */
10569 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10570 && GET_CODE (pat
) == PARALLEL
)
10574 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10575 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10578 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10582 SUBST_INT (XVECLEN (pat
, 0), pos
);
10585 pat
= XVECEXP (pat
, 0, 0);
10587 PATTERN (insn
) = pat
;
10588 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10589 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10591 if (insn_code_number
< 0)
10592 fputs ("Failed to match this instruction:\n", dump_file
);
10594 fputs ("Successfully matched this instruction:\n", dump_file
);
10595 print_rtl_single (dump_file
, pat
);
10598 PATTERN (insn
) = old_pat
;
10599 REG_NOTES (insn
) = old_notes
;
10601 /* Recognize all noop sets, these will be killed by followup pass. */
10602 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10603 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10605 /* If we had any clobbers to add, make a new pattern than contains
10606 them. Then check to make sure that all of them are dead. */
10607 if (num_clobbers_to_add
)
10609 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10610 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10611 ? (XVECLEN (pat
, 0)
10612 + num_clobbers_to_add
)
10613 : num_clobbers_to_add
+ 1));
10615 if (GET_CODE (pat
) == PARALLEL
)
10616 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10617 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10619 XVECEXP (newpat
, 0, 0) = pat
;
10621 add_clobbers (newpat
, insn_code_number
);
10623 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10624 i
< XVECLEN (newpat
, 0); i
++)
10626 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10627 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10629 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10631 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10632 notes
= alloc_reg_note (REG_UNUSED
,
10633 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10642 return insn_code_number
;
10645 /* Like gen_lowpart_general but for use by combine. In combine it
10646 is not possible to create any new pseudoregs. However, it is
10647 safe to create invalid memory addresses, because combine will
10648 try to recognize them and all they will do is make the combine
10651 If for some reason this cannot do its job, an rtx
10652 (clobber (const_int 0)) is returned.
10653 An insn containing that will not be recognized. */
10656 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10658 enum machine_mode imode
= GET_MODE (x
);
10659 unsigned int osize
= GET_MODE_SIZE (omode
);
10660 unsigned int isize
= GET_MODE_SIZE (imode
);
10663 if (omode
== imode
)
10666 /* Return identity if this is a CONST or symbolic reference. */
10668 && (GET_CODE (x
) == CONST
10669 || GET_CODE (x
) == SYMBOL_REF
10670 || GET_CODE (x
) == LABEL_REF
))
10673 /* We can only support MODE being wider than a word if X is a
10674 constant integer or has a mode the same size. */
10675 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10676 && ! ((imode
== VOIDmode
10677 && (CONST_INT_P (x
)
10678 || GET_CODE (x
) == CONST_DOUBLE
))
10679 || isize
== osize
))
10682 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10683 won't know what to do. So we will strip off the SUBREG here and
10684 process normally. */
10685 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10687 x
= SUBREG_REG (x
);
10689 /* For use in case we fall down into the address adjustments
10690 further below, we need to adjust the known mode and size of
10691 x; imode and isize, since we just adjusted x. */
10692 imode
= GET_MODE (x
);
10694 if (imode
== omode
)
10697 isize
= GET_MODE_SIZE (imode
);
10700 result
= gen_lowpart_common (omode
, x
);
10709 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10711 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10714 /* If we want to refer to something bigger than the original memref,
10715 generate a paradoxical subreg instead. That will force a reload
10716 of the original memref X. */
10718 return gen_rtx_SUBREG (omode
, x
, 0);
10720 if (WORDS_BIG_ENDIAN
)
10721 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10723 /* Adjust the address so that the address-after-the-data is
10725 if (BYTES_BIG_ENDIAN
)
10726 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10728 return adjust_address_nv (x
, omode
, offset
);
10731 /* If X is a comparison operator, rewrite it in a new mode. This
10732 probably won't match, but may allow further simplifications. */
10733 else if (COMPARISON_P (x
))
10734 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10736 /* If we couldn't simplify X any other way, just enclose it in a
10737 SUBREG. Normally, this SUBREG won't match, but some patterns may
10738 include an explicit SUBREG or we may simplify it further in combine. */
10744 offset
= subreg_lowpart_offset (omode
, imode
);
10745 if (imode
== VOIDmode
)
10747 imode
= int_mode_for_mode (omode
);
10748 x
= gen_lowpart_common (imode
, x
);
10752 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10758 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10761 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10762 comparison code that will be tested.
10764 The result is a possibly different comparison code to use. *POP0 and
10765 *POP1 may be updated.
10767 It is possible that we might detect that a comparison is either always
10768 true or always false. However, we do not perform general constant
10769 folding in combine, so this knowledge isn't useful. Such tautologies
10770 should have been detected earlier. Hence we ignore all such cases. */
10772 static enum rtx_code
10773 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10779 enum machine_mode mode
, tmode
;
10781 /* Try a few ways of applying the same transformation to both operands. */
10784 #ifndef WORD_REGISTER_OPERATIONS
10785 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10786 so check specially. */
10787 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10788 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10789 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10790 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10791 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10792 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10793 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10794 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10795 && CONST_INT_P (XEXP (op0
, 1))
10796 && XEXP (op0
, 1) == XEXP (op1
, 1)
10797 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10798 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10799 && (INTVAL (XEXP (op0
, 1))
10800 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10801 - (GET_MODE_BITSIZE
10802 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10804 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10805 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10809 /* If both operands are the same constant shift, see if we can ignore the
10810 shift. We can if the shift is a rotate or if the bits shifted out of
10811 this shift are known to be zero for both inputs and if the type of
10812 comparison is compatible with the shift. */
10813 if (GET_CODE (op0
) == GET_CODE (op1
)
10814 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10815 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10816 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10817 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10818 || (GET_CODE (op0
) == ASHIFTRT
10819 && (code
!= GTU
&& code
!= LTU
10820 && code
!= GEU
&& code
!= LEU
)))
10821 && CONST_INT_P (XEXP (op0
, 1))
10822 && INTVAL (XEXP (op0
, 1)) >= 0
10823 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10824 && XEXP (op0
, 1) == XEXP (op1
, 1))
10826 enum machine_mode mode
= GET_MODE (op0
);
10827 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10828 int shift_count
= INTVAL (XEXP (op0
, 1));
10830 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10831 mask
&= (mask
>> shift_count
) << shift_count
;
10832 else if (GET_CODE (op0
) == ASHIFT
)
10833 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10835 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10836 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10837 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10842 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10843 SUBREGs are of the same mode, and, in both cases, the AND would
10844 be redundant if the comparison was done in the narrower mode,
10845 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10846 and the operand's possibly nonzero bits are 0xffffff01; in that case
10847 if we only care about QImode, we don't need the AND). This case
10848 occurs if the output mode of an scc insn is not SImode and
10849 STORE_FLAG_VALUE == 1 (e.g., the 386).
10851 Similarly, check for a case where the AND's are ZERO_EXTEND
10852 operations from some narrower mode even though a SUBREG is not
10855 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10856 && CONST_INT_P (XEXP (op0
, 1))
10857 && CONST_INT_P (XEXP (op1
, 1)))
10859 rtx inner_op0
= XEXP (op0
, 0);
10860 rtx inner_op1
= XEXP (op1
, 0);
10861 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10862 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10865 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10866 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10867 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10868 && (GET_MODE (SUBREG_REG (inner_op0
))
10869 == GET_MODE (SUBREG_REG (inner_op1
)))
10870 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10871 <= HOST_BITS_PER_WIDE_INT
)
10872 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10873 GET_MODE (SUBREG_REG (inner_op0
)))))
10874 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10875 GET_MODE (SUBREG_REG (inner_op1
))))))
10877 op0
= SUBREG_REG (inner_op0
);
10878 op1
= SUBREG_REG (inner_op1
);
10880 /* The resulting comparison is always unsigned since we masked
10881 off the original sign bit. */
10882 code
= unsigned_condition (code
);
10888 for (tmode
= GET_CLASS_NARROWEST_MODE
10889 (GET_MODE_CLASS (GET_MODE (op0
)));
10890 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10891 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10893 op0
= gen_lowpart (tmode
, inner_op0
);
10894 op1
= gen_lowpart (tmode
, inner_op1
);
10895 code
= unsigned_condition (code
);
10904 /* If both operands are NOT, we can strip off the outer operation
10905 and adjust the comparison code for swapped operands; similarly for
10906 NEG, except that this must be an equality comparison. */
10907 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10908 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10909 && (code
== EQ
|| code
== NE
)))
10910 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10916 /* If the first operand is a constant, swap the operands and adjust the
10917 comparison code appropriately, but don't do this if the second operand
10918 is already a constant integer. */
10919 if (swap_commutative_operands_p (op0
, op1
))
10921 tem
= op0
, op0
= op1
, op1
= tem
;
10922 code
= swap_condition (code
);
10925 /* We now enter a loop during which we will try to simplify the comparison.
10926 For the most part, we only are concerned with comparisons with zero,
10927 but some things may really be comparisons with zero but not start
10928 out looking that way. */
10930 while (CONST_INT_P (op1
))
10932 enum machine_mode mode
= GET_MODE (op0
);
10933 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10934 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10935 int equality_comparison_p
;
10936 int sign_bit_comparison_p
;
10937 int unsigned_comparison_p
;
10938 HOST_WIDE_INT const_op
;
10940 /* We only want to handle integral modes. This catches VOIDmode,
10941 CCmode, and the floating-point modes. An exception is that we
10942 can handle VOIDmode if OP0 is a COMPARE or a comparison
10945 if (GET_MODE_CLASS (mode
) != MODE_INT
10946 && ! (mode
== VOIDmode
10947 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10950 /* Get the constant we are comparing against and turn off all bits
10951 not on in our mode. */
10952 const_op
= INTVAL (op1
);
10953 if (mode
!= VOIDmode
)
10954 const_op
= trunc_int_for_mode (const_op
, mode
);
10955 op1
= GEN_INT (const_op
);
10957 /* If we are comparing against a constant power of two and the value
10958 being compared can only have that single bit nonzero (e.g., it was
10959 `and'ed with that bit), we can replace this with a comparison
10962 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10963 || code
== LT
|| code
== LTU
)
10964 && mode_width
<= HOST_BITS_PER_WIDE_INT
10965 && exact_log2 (const_op
) >= 0
10966 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10968 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10969 op1
= const0_rtx
, const_op
= 0;
10972 /* Similarly, if we are comparing a value known to be either -1 or
10973 0 with -1, change it to the opposite comparison against zero. */
10976 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10977 || code
== GEU
|| code
== LTU
)
10978 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10980 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10981 op1
= const0_rtx
, const_op
= 0;
10984 /* Do some canonicalizations based on the comparison code. We prefer
10985 comparisons against zero and then prefer equality comparisons.
10986 If we can reduce the size of a constant, we will do that too. */
10991 /* < C is equivalent to <= (C - 1) */
10995 op1
= GEN_INT (const_op
);
10997 /* ... fall through to LE case below. */
11003 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11007 op1
= GEN_INT (const_op
);
11011 /* If we are doing a <= 0 comparison on a value known to have
11012 a zero sign bit, we can replace this with == 0. */
11013 else if (const_op
== 0
11014 && mode_width
<= HOST_BITS_PER_WIDE_INT
11015 && (nonzero_bits (op0
, mode
)
11016 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11022 /* >= C is equivalent to > (C - 1). */
11026 op1
= GEN_INT (const_op
);
11028 /* ... fall through to GT below. */
11034 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11038 op1
= GEN_INT (const_op
);
11042 /* If we are doing a > 0 comparison on a value known to have
11043 a zero sign bit, we can replace this with != 0. */
11044 else if (const_op
== 0
11045 && mode_width
<= HOST_BITS_PER_WIDE_INT
11046 && (nonzero_bits (op0
, mode
)
11047 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11053 /* < C is equivalent to <= (C - 1). */
11057 op1
= GEN_INT (const_op
);
11059 /* ... fall through ... */
11062 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11063 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11064 && (unsigned HOST_WIDE_INT
) const_op
11065 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11067 const_op
= 0, op1
= const0_rtx
;
11075 /* unsigned <= 0 is equivalent to == 0 */
11079 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11080 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11081 && (unsigned HOST_WIDE_INT
) const_op
11082 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11084 const_op
= 0, op1
= const0_rtx
;
11090 /* >= C is equivalent to > (C - 1). */
11094 op1
= GEN_INT (const_op
);
11096 /* ... fall through ... */
11099 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11100 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11101 && (unsigned HOST_WIDE_INT
) const_op
11102 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11104 const_op
= 0, op1
= const0_rtx
;
11112 /* unsigned > 0 is equivalent to != 0 */
11116 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11117 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11118 && (unsigned HOST_WIDE_INT
) const_op
11119 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11121 const_op
= 0, op1
= const0_rtx
;
11130 /* Compute some predicates to simplify code below. */
11132 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11133 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11134 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11137 /* If this is a sign bit comparison and we can do arithmetic in
11138 MODE, say that we will only be needing the sign bit of OP0. */
11139 if (sign_bit_comparison_p
11140 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11141 op0
= force_to_mode (op0
, mode
,
11142 (unsigned HOST_WIDE_INT
) 1
11143 << (GET_MODE_BITSIZE (mode
) - 1),
11146 /* Now try cases based on the opcode of OP0. If none of the cases
11147 does a "continue", we exit this loop immediately after the
11150 switch (GET_CODE (op0
))
11153 /* If we are extracting a single bit from a variable position in
11154 a constant that has only a single bit set and are comparing it
11155 with zero, we can convert this into an equality comparison
11156 between the position and the location of the single bit. */
11157 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11158 have already reduced the shift count modulo the word size. */
11159 if (!SHIFT_COUNT_TRUNCATED
11160 && CONST_INT_P (XEXP (op0
, 0))
11161 && XEXP (op0
, 1) == const1_rtx
11162 && equality_comparison_p
&& const_op
== 0
11163 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11165 if (BITS_BIG_ENDIAN
)
11167 enum machine_mode new_mode
11168 = mode_for_extraction (EP_extzv
, 1);
11169 if (new_mode
== MAX_MACHINE_MODE
)
11170 i
= BITS_PER_WORD
- 1 - i
;
11174 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
11178 op0
= XEXP (op0
, 2);
11182 /* Result is nonzero iff shift count is equal to I. */
11183 code
= reverse_condition (code
);
11187 /* ... fall through ... */
11190 tem
= expand_compound_operation (op0
);
11199 /* If testing for equality, we can take the NOT of the constant. */
11200 if (equality_comparison_p
11201 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11203 op0
= XEXP (op0
, 0);
11208 /* If just looking at the sign bit, reverse the sense of the
11210 if (sign_bit_comparison_p
)
11212 op0
= XEXP (op0
, 0);
11213 code
= (code
== GE
? LT
: GE
);
11219 /* If testing for equality, we can take the NEG of the constant. */
11220 if (equality_comparison_p
11221 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11223 op0
= XEXP (op0
, 0);
11228 /* The remaining cases only apply to comparisons with zero. */
11232 /* When X is ABS or is known positive,
11233 (neg X) is < 0 if and only if X != 0. */
11235 if (sign_bit_comparison_p
11236 && (GET_CODE (XEXP (op0
, 0)) == ABS
11237 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11238 && (nonzero_bits (XEXP (op0
, 0), mode
)
11239 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11242 op0
= XEXP (op0
, 0);
11243 code
= (code
== LT
? NE
: EQ
);
11247 /* If we have NEG of something whose two high-order bits are the
11248 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11249 if (num_sign_bit_copies (op0
, mode
) >= 2)
11251 op0
= XEXP (op0
, 0);
11252 code
= swap_condition (code
);
11258 /* If we are testing equality and our count is a constant, we
11259 can perform the inverse operation on our RHS. */
11260 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11261 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11262 op1
, XEXP (op0
, 1))) != 0)
11264 op0
= XEXP (op0
, 0);
11269 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11270 a particular bit. Convert it to an AND of a constant of that
11271 bit. This will be converted into a ZERO_EXTRACT. */
11272 if (const_op
== 0 && sign_bit_comparison_p
11273 && CONST_INT_P (XEXP (op0
, 1))
11274 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11276 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11277 ((unsigned HOST_WIDE_INT
) 1
11279 - INTVAL (XEXP (op0
, 1)))));
11280 code
= (code
== LT
? NE
: EQ
);
11284 /* Fall through. */
11287 /* ABS is ignorable inside an equality comparison with zero. */
11288 if (const_op
== 0 && equality_comparison_p
)
11290 op0
= XEXP (op0
, 0);
11296 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11297 (compare FOO CONST) if CONST fits in FOO's mode and we
11298 are either testing inequality or have an unsigned
11299 comparison with ZERO_EXTEND or a signed comparison with
11300 SIGN_EXTEND. But don't do it if we don't have a compare
11301 insn of the given mode, since we'd have to revert it
11302 later on, and then we wouldn't know whether to sign- or
11304 mode
= GET_MODE (XEXP (op0
, 0));
11305 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11306 && ! unsigned_comparison_p
11307 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11308 && ((unsigned HOST_WIDE_INT
) const_op
11309 < (((unsigned HOST_WIDE_INT
) 1
11310 << (GET_MODE_BITSIZE (mode
) - 1))))
11311 && have_insn_for (COMPARE
, mode
))
11313 op0
= XEXP (op0
, 0);
11319 /* Check for the case where we are comparing A - C1 with C2, that is
11321 (subreg:MODE (plus (A) (-C1))) op (C2)
11323 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11324 comparison in the wider mode. One of the following two conditions
11325 must be true in order for this to be valid:
11327 1. The mode extension results in the same bit pattern being added
11328 on both sides and the comparison is equality or unsigned. As
11329 C2 has been truncated to fit in MODE, the pattern can only be
11332 2. The mode extension results in the sign bit being copied on
11335 The difficulty here is that we have predicates for A but not for
11336 (A - C1) so we need to check that C1 is within proper bounds so
11337 as to perturbate A as little as possible. */
11339 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11340 && subreg_lowpart_p (op0
)
11341 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
11342 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11343 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11345 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11346 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11347 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11350 && (unsigned HOST_WIDE_INT
) c1
11351 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11352 && (equality_comparison_p
|| unsigned_comparison_p
)
11353 /* (A - C1) zero-extends if it is positive and sign-extends
11354 if it is negative, C2 both zero- and sign-extends. */
11355 && ((0 == (nonzero_bits (a
, inner_mode
)
11356 & ~GET_MODE_MASK (mode
))
11358 /* (A - C1) sign-extends if it is positive and 1-extends
11359 if it is negative, C2 both sign- and 1-extends. */
11360 || (num_sign_bit_copies (a
, inner_mode
)
11361 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11364 || ((unsigned HOST_WIDE_INT
) c1
11365 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11366 /* (A - C1) always sign-extends, like C2. */
11367 && num_sign_bit_copies (a
, inner_mode
)
11368 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11369 - (mode_width
- 1))))
11371 op0
= SUBREG_REG (op0
);
11376 /* If the inner mode is narrower and we are extracting the low part,
11377 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11378 if (subreg_lowpart_p (op0
)
11379 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11380 /* Fall through */ ;
11384 /* ... fall through ... */
11387 mode
= GET_MODE (XEXP (op0
, 0));
11388 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11389 && (unsigned_comparison_p
|| equality_comparison_p
)
11390 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11391 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
11392 && have_insn_for (COMPARE
, mode
))
11394 op0
= XEXP (op0
, 0);
11400 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11401 this for equality comparisons due to pathological cases involving
11403 if (equality_comparison_p
11404 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11405 op1
, XEXP (op0
, 1))))
11407 op0
= XEXP (op0
, 0);
11412 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11413 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11414 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11416 op0
= XEXP (XEXP (op0
, 0), 0);
11417 code
= (code
== LT
? EQ
: NE
);
11423 /* We used to optimize signed comparisons against zero, but that
11424 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11425 arrive here as equality comparisons, or (GEU, LTU) are
11426 optimized away. No need to special-case them. */
11428 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11429 (eq B (minus A C)), whichever simplifies. We can only do
11430 this for equality comparisons due to pathological cases involving
11432 if (equality_comparison_p
11433 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11434 XEXP (op0
, 1), op1
)))
11436 op0
= XEXP (op0
, 0);
11441 if (equality_comparison_p
11442 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11443 XEXP (op0
, 0), op1
)))
11445 op0
= XEXP (op0
, 1);
11450 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11451 of bits in X minus 1, is one iff X > 0. */
11452 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11453 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11454 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11455 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11457 op0
= XEXP (op0
, 1);
11458 code
= (code
== GE
? LE
: GT
);
11464 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11465 if C is zero or B is a constant. */
11466 if (equality_comparison_p
11467 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11468 XEXP (op0
, 1), op1
)))
11470 op0
= XEXP (op0
, 0);
11477 case UNEQ
: case LTGT
:
11478 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11479 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11480 case UNORDERED
: case ORDERED
:
11481 /* We can't do anything if OP0 is a condition code value, rather
11482 than an actual data value. */
11484 || CC0_P (XEXP (op0
, 0))
11485 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11488 /* Get the two operands being compared. */
11489 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11490 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11492 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11494 /* Check for the cases where we simply want the result of the
11495 earlier test or the opposite of that result. */
11496 if (code
== NE
|| code
== EQ
11497 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
11498 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11499 && (STORE_FLAG_VALUE
11500 & (((unsigned HOST_WIDE_INT
) 1
11501 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
11502 && (code
== LT
|| code
== GE
)))
11504 enum rtx_code new_code
;
11505 if (code
== LT
|| code
== NE
)
11506 new_code
= GET_CODE (op0
);
11508 new_code
= reversed_comparison_code (op0
, NULL
);
11510 if (new_code
!= UNKNOWN
)
11521 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11523 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11524 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11525 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11527 op0
= XEXP (op0
, 1);
11528 code
= (code
== GE
? GT
: LE
);
11534 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11535 will be converted to a ZERO_EXTRACT later. */
11536 if (const_op
== 0 && equality_comparison_p
11537 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11538 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11540 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11541 XEXP (XEXP (op0
, 0), 1));
11542 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11546 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11547 zero and X is a comparison and C1 and C2 describe only bits set
11548 in STORE_FLAG_VALUE, we can compare with X. */
11549 if (const_op
== 0 && equality_comparison_p
11550 && mode_width
<= HOST_BITS_PER_WIDE_INT
11551 && CONST_INT_P (XEXP (op0
, 1))
11552 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11553 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11554 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11555 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11557 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11558 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11559 if ((~STORE_FLAG_VALUE
& mask
) == 0
11560 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11561 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11562 && COMPARISON_P (tem
))))
11564 op0
= XEXP (XEXP (op0
, 0), 0);
11569 /* If we are doing an equality comparison of an AND of a bit equal
11570 to the sign bit, replace this with a LT or GE comparison of
11571 the underlying value. */
11572 if (equality_comparison_p
11574 && CONST_INT_P (XEXP (op0
, 1))
11575 && mode_width
<= HOST_BITS_PER_WIDE_INT
11576 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11577 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11579 op0
= XEXP (op0
, 0);
11580 code
= (code
== EQ
? GE
: LT
);
11584 /* If this AND operation is really a ZERO_EXTEND from a narrower
11585 mode, the constant fits within that mode, and this is either an
11586 equality or unsigned comparison, try to do this comparison in
11591 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11592 -> (ne:DI (reg:SI 4) (const_int 0))
11594 unless TRULY_NOOP_TRUNCATION allows it or the register is
11595 known to hold a value of the required mode the
11596 transformation is invalid. */
11597 if ((equality_comparison_p
|| unsigned_comparison_p
)
11598 && CONST_INT_P (XEXP (op0
, 1))
11599 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11600 & GET_MODE_MASK (mode
))
11602 && const_op
>> i
== 0
11603 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11604 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
11605 GET_MODE_BITSIZE (GET_MODE (op0
)))
11606 || (REG_P (XEXP (op0
, 0))
11607 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11609 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11613 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11614 fits in both M1 and M2 and the SUBREG is either paradoxical
11615 or represents the low part, permute the SUBREG and the AND
11617 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11619 unsigned HOST_WIDE_INT c1
;
11620 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11621 /* Require an integral mode, to avoid creating something like
11623 if (SCALAR_INT_MODE_P (tmode
)
11624 /* It is unsafe to commute the AND into the SUBREG if the
11625 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11626 not defined. As originally written the upper bits
11627 have a defined value due to the AND operation.
11628 However, if we commute the AND inside the SUBREG then
11629 they no longer have defined values and the meaning of
11630 the code has been changed. */
11632 #ifdef WORD_REGISTER_OPERATIONS
11633 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11634 && mode_width
<= BITS_PER_WORD
)
11636 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11637 && subreg_lowpart_p (XEXP (op0
, 0))))
11638 && CONST_INT_P (XEXP (op0
, 1))
11639 && mode_width
<= HOST_BITS_PER_WIDE_INT
11640 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11641 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11642 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11644 && c1
!= GET_MODE_MASK (tmode
))
11646 op0
= simplify_gen_binary (AND
, tmode
,
11647 SUBREG_REG (XEXP (op0
, 0)),
11648 gen_int_mode (c1
, tmode
));
11649 op0
= gen_lowpart (mode
, op0
);
11654 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11655 if (const_op
== 0 && equality_comparison_p
11656 && XEXP (op0
, 1) == const1_rtx
11657 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11659 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11660 XEXP (XEXP (op0
, 0), 0), 1);
11661 code
= (code
== NE
? EQ
: NE
);
11665 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11666 (eq (and (lshiftrt X) 1) 0).
11667 Also handle the case where (not X) is expressed using xor. */
11668 if (const_op
== 0 && equality_comparison_p
11669 && XEXP (op0
, 1) == const1_rtx
11670 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11672 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11673 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11675 if (GET_CODE (shift_op
) == NOT
11676 || (GET_CODE (shift_op
) == XOR
11677 && CONST_INT_P (XEXP (shift_op
, 1))
11678 && CONST_INT_P (shift_count
)
11679 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11680 && (UINTVAL (XEXP (shift_op
, 1))
11681 == (unsigned HOST_WIDE_INT
) 1
11682 << INTVAL (shift_count
))))
11685 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11686 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11687 code
= (code
== NE
? EQ
: NE
);
11694 /* If we have (compare (ashift FOO N) (const_int C)) and
11695 the high order N bits of FOO (N+1 if an inequality comparison)
11696 are known to be zero, we can do this by comparing FOO with C
11697 shifted right N bits so long as the low-order N bits of C are
11699 if (CONST_INT_P (XEXP (op0
, 1))
11700 && INTVAL (XEXP (op0
, 1)) >= 0
11701 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11702 < HOST_BITS_PER_WIDE_INT
)
11703 && (((unsigned HOST_WIDE_INT
) const_op
11704 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11706 && mode_width
<= HOST_BITS_PER_WIDE_INT
11707 && (nonzero_bits (XEXP (op0
, 0), mode
)
11708 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11709 + ! equality_comparison_p
))) == 0)
11711 /* We must perform a logical shift, not an arithmetic one,
11712 as we want the top N bits of C to be zero. */
11713 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11715 temp
>>= INTVAL (XEXP (op0
, 1));
11716 op1
= gen_int_mode (temp
, mode
);
11717 op0
= XEXP (op0
, 0);
11721 /* If we are doing a sign bit comparison, it means we are testing
11722 a particular bit. Convert it to the appropriate AND. */
11723 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11724 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11726 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11727 ((unsigned HOST_WIDE_INT
) 1
11729 - INTVAL (XEXP (op0
, 1)))));
11730 code
= (code
== LT
? NE
: EQ
);
11734 /* If this an equality comparison with zero and we are shifting
11735 the low bit to the sign bit, we can convert this to an AND of the
11737 if (const_op
== 0 && equality_comparison_p
11738 && CONST_INT_P (XEXP (op0
, 1))
11739 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11741 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11747 /* If this is an equality comparison with zero, we can do this
11748 as a logical shift, which might be much simpler. */
11749 if (equality_comparison_p
&& const_op
== 0
11750 && CONST_INT_P (XEXP (op0
, 1)))
11752 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11754 INTVAL (XEXP (op0
, 1)));
11758 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11759 do the comparison in a narrower mode. */
11760 if (! unsigned_comparison_p
11761 && CONST_INT_P (XEXP (op0
, 1))
11762 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11763 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11764 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11765 MODE_INT
, 1)) != BLKmode
11766 && (((unsigned HOST_WIDE_INT
) const_op
11767 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11768 <= GET_MODE_MASK (tmode
)))
11770 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11774 /* Likewise if OP0 is a PLUS of a sign extension with a
11775 constant, which is usually represented with the PLUS
11776 between the shifts. */
11777 if (! unsigned_comparison_p
11778 && CONST_INT_P (XEXP (op0
, 1))
11779 && GET_CODE (XEXP (op0
, 0)) == PLUS
11780 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11781 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11782 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11783 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11784 MODE_INT
, 1)) != BLKmode
11785 && (((unsigned HOST_WIDE_INT
) const_op
11786 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11787 <= GET_MODE_MASK (tmode
)))
11789 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11790 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11791 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11792 add_const
, XEXP (op0
, 1));
11794 op0
= simplify_gen_binary (PLUS
, tmode
,
11795 gen_lowpart (tmode
, inner
),
11800 /* ... fall through ... */
11802 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11803 the low order N bits of FOO are known to be zero, we can do this
11804 by comparing FOO with C shifted left N bits so long as no
11805 overflow occurs. Even if the low order N bits of FOO aren't known
11806 to be zero, if the comparison is >= or < we can use the same
11807 optimization and for > or <= by setting all the low
11808 order N bits in the comparison constant. */
11809 if (CONST_INT_P (XEXP (op0
, 1))
11810 && INTVAL (XEXP (op0
, 1)) > 0
11811 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11812 && mode_width
<= HOST_BITS_PER_WIDE_INT
11813 && (((unsigned HOST_WIDE_INT
) const_op
11814 + (GET_CODE (op0
) != LSHIFTRT
11815 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11818 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11820 unsigned HOST_WIDE_INT low_bits
11821 = (nonzero_bits (XEXP (op0
, 0), mode
)
11822 & (((unsigned HOST_WIDE_INT
) 1
11823 << INTVAL (XEXP (op0
, 1))) - 1));
11824 if (low_bits
== 0 || !equality_comparison_p
)
11826 /* If the shift was logical, then we must make the condition
11828 if (GET_CODE (op0
) == LSHIFTRT
)
11829 code
= unsigned_condition (code
);
11831 const_op
<<= INTVAL (XEXP (op0
, 1));
11833 && (code
== GT
|| code
== GTU
11834 || code
== LE
|| code
== LEU
))
11836 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11837 op1
= GEN_INT (const_op
);
11838 op0
= XEXP (op0
, 0);
11843 /* If we are using this shift to extract just the sign bit, we
11844 can replace this with an LT or GE comparison. */
11846 && (equality_comparison_p
|| sign_bit_comparison_p
)
11847 && CONST_INT_P (XEXP (op0
, 1))
11848 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11850 op0
= XEXP (op0
, 0);
11851 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11863 /* Now make any compound operations involved in this comparison. Then,
11864 check for an outmost SUBREG on OP0 that is not doing anything or is
11865 paradoxical. The latter transformation must only be performed when
11866 it is known that the "extra" bits will be the same in op0 and op1 or
11867 that they don't matter. There are three cases to consider:
11869 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11870 care bits and we can assume they have any convenient value. So
11871 making the transformation is safe.
11873 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11874 In this case the upper bits of op0 are undefined. We should not make
11875 the simplification in that case as we do not know the contents of
11878 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11879 UNKNOWN. In that case we know those bits are zeros or ones. We must
11880 also be sure that they are the same as the upper bits of op1.
11882 We can never remove a SUBREG for a non-equality comparison because
11883 the sign bit is in a different place in the underlying object. */
11885 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11886 op1
= make_compound_operation (op1
, SET
);
11888 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11889 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11890 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11891 && (code
== NE
|| code
== EQ
))
11893 if (GET_MODE_SIZE (GET_MODE (op0
))
11894 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11896 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11898 if (REG_P (SUBREG_REG (op0
)))
11900 op0
= SUBREG_REG (op0
);
11901 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11904 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11905 <= HOST_BITS_PER_WIDE_INT
)
11906 && (nonzero_bits (SUBREG_REG (op0
),
11907 GET_MODE (SUBREG_REG (op0
)))
11908 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11910 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11912 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11913 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11914 op0
= SUBREG_REG (op0
), op1
= tem
;
11918 /* We now do the opposite procedure: Some machines don't have compare
11919 insns in all modes. If OP0's mode is an integer mode smaller than a
11920 word and we can't do a compare in that mode, see if there is a larger
11921 mode for which we can do the compare. There are a number of cases in
11922 which we can use the wider mode. */
11924 mode
= GET_MODE (op0
);
11925 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11926 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11927 && ! have_insn_for (COMPARE
, mode
))
11928 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11930 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11931 tmode
= GET_MODE_WIDER_MODE (tmode
))
11932 if (have_insn_for (COMPARE
, tmode
))
11936 /* If this is a test for negative, we can make an explicit
11937 test of the sign bit. Test this first so we can use
11938 a paradoxical subreg to extend OP0. */
11940 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11941 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11943 op0
= simplify_gen_binary (AND
, tmode
,
11944 gen_lowpart (tmode
, op0
),
11945 GEN_INT ((unsigned HOST_WIDE_INT
) 1
11946 << (GET_MODE_BITSIZE (mode
)
11948 code
= (code
== LT
) ? NE
: EQ
;
11952 /* If the only nonzero bits in OP0 and OP1 are those in the
11953 narrower mode and this is an equality or unsigned comparison,
11954 we can use the wider mode. Similarly for sign-extended
11955 values, in which case it is true for all comparisons. */
11956 zero_extended
= ((code
== EQ
|| code
== NE
11957 || code
== GEU
|| code
== GTU
11958 || code
== LEU
|| code
== LTU
)
11959 && (nonzero_bits (op0
, tmode
)
11960 & ~GET_MODE_MASK (mode
)) == 0
11961 && ((CONST_INT_P (op1
)
11962 || (nonzero_bits (op1
, tmode
)
11963 & ~GET_MODE_MASK (mode
)) == 0)));
11966 || ((num_sign_bit_copies (op0
, tmode
)
11967 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11968 - GET_MODE_BITSIZE (mode
)))
11969 && (num_sign_bit_copies (op1
, tmode
)
11970 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11971 - GET_MODE_BITSIZE (mode
)))))
11973 /* If OP0 is an AND and we don't have an AND in MODE either,
11974 make a new AND in the proper mode. */
11975 if (GET_CODE (op0
) == AND
11976 && !have_insn_for (AND
, mode
))
11977 op0
= simplify_gen_binary (AND
, tmode
,
11978 gen_lowpart (tmode
,
11980 gen_lowpart (tmode
,
11986 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11987 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11991 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11992 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11999 #ifdef CANONICALIZE_COMPARISON
12000 /* If this machine only supports a subset of valid comparisons, see if we
12001 can convert an unsupported one into a supported one. */
12002 CANONICALIZE_COMPARISON (code
, op0
, op1
);
12011 /* Utility function for record_value_for_reg. Count number of
12016 enum rtx_code code
= GET_CODE (x
);
12020 if (GET_RTX_CLASS (code
) == '2'
12021 || GET_RTX_CLASS (code
) == 'c')
12023 rtx x0
= XEXP (x
, 0);
12024 rtx x1
= XEXP (x
, 1);
12027 return 1 + 2 * count_rtxs (x0
);
12029 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
12030 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
12031 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12032 return 2 + 2 * count_rtxs (x0
)
12033 + count_rtxs (x
== XEXP (x1
, 0)
12034 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12036 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
12037 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
12038 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12039 return 2 + 2 * count_rtxs (x1
)
12040 + count_rtxs (x
== XEXP (x0
, 0)
12041 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12044 fmt
= GET_RTX_FORMAT (code
);
12045 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12047 ret
+= count_rtxs (XEXP (x
, i
));
12048 else if (fmt
[i
] == 'E')
12049 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12050 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12055 /* Utility function for following routine. Called when X is part of a value
12056 being stored into last_set_value. Sets last_set_table_tick
12057 for each register mentioned. Similar to mention_regs in cse.c */
12060 update_table_tick (rtx x
)
12062 enum rtx_code code
= GET_CODE (x
);
12063 const char *fmt
= GET_RTX_FORMAT (code
);
12068 unsigned int regno
= REGNO (x
);
12069 unsigned int endregno
= END_REGNO (x
);
12072 for (r
= regno
; r
< endregno
; r
++)
12074 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
12075 rsp
->last_set_table_tick
= label_tick
;
12081 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12084 /* Check for identical subexpressions. If x contains
12085 identical subexpression we only have to traverse one of
12087 if (i
== 0 && ARITHMETIC_P (x
))
12089 /* Note that at this point x1 has already been
12091 rtx x0
= XEXP (x
, 0);
12092 rtx x1
= XEXP (x
, 1);
12094 /* If x0 and x1 are identical then there is no need to
12099 /* If x0 is identical to a subexpression of x1 then while
12100 processing x1, x0 has already been processed. Thus we
12101 are done with x. */
12102 if (ARITHMETIC_P (x1
)
12103 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12106 /* If x1 is identical to a subexpression of x0 then we
12107 still have to process the rest of x0. */
12108 if (ARITHMETIC_P (x0
)
12109 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12111 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12116 update_table_tick (XEXP (x
, i
));
12118 else if (fmt
[i
] == 'E')
12119 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12120 update_table_tick (XVECEXP (x
, i
, j
));
12123 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12124 are saying that the register is clobbered and we no longer know its
12125 value. If INSN is zero, don't update reg_stat[].last_set; this is
12126 only permitted with VALUE also zero and is used to invalidate the
12130 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12132 unsigned int regno
= REGNO (reg
);
12133 unsigned int endregno
= END_REGNO (reg
);
12135 reg_stat_type
*rsp
;
12137 /* If VALUE contains REG and we have a previous value for REG, substitute
12138 the previous value. */
12139 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12143 /* Set things up so get_last_value is allowed to see anything set up to
12145 subst_low_luid
= DF_INSN_LUID (insn
);
12146 tem
= get_last_value (reg
);
12148 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12149 it isn't going to be useful and will take a lot of time to process,
12150 so just use the CLOBBER. */
12154 if (ARITHMETIC_P (tem
)
12155 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12156 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12157 tem
= XEXP (tem
, 0);
12158 else if (count_occurrences (value
, reg
, 1) >= 2)
12160 /* If there are two or more occurrences of REG in VALUE,
12161 prevent the value from growing too much. */
12162 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12163 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12166 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12170 /* For each register modified, show we don't know its value, that
12171 we don't know about its bitwise content, that its value has been
12172 updated, and that we don't know the location of the death of the
12174 for (i
= regno
; i
< endregno
; i
++)
12176 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12179 rsp
->last_set
= insn
;
12181 rsp
->last_set_value
= 0;
12182 rsp
->last_set_mode
= VOIDmode
;
12183 rsp
->last_set_nonzero_bits
= 0;
12184 rsp
->last_set_sign_bit_copies
= 0;
12185 rsp
->last_death
= 0;
12186 rsp
->truncated_to_mode
= VOIDmode
;
12189 /* Mark registers that are being referenced in this value. */
12191 update_table_tick (value
);
12193 /* Now update the status of each register being set.
12194 If someone is using this register in this block, set this register
12195 to invalid since we will get confused between the two lives in this
12196 basic block. This makes using this register always invalid. In cse, we
12197 scan the table to invalidate all entries using this register, but this
12198 is too much work for us. */
12200 for (i
= regno
; i
< endregno
; i
++)
12202 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12203 rsp
->last_set_label
= label_tick
;
12205 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12206 rsp
->last_set_invalid
= 1;
12208 rsp
->last_set_invalid
= 0;
12211 /* The value being assigned might refer to X (like in "x++;"). In that
12212 case, we must replace it with (clobber (const_int 0)) to prevent
12214 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12215 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12217 value
= copy_rtx (value
);
12218 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12222 /* For the main register being modified, update the value, the mode, the
12223 nonzero bits, and the number of sign bit copies. */
12225 rsp
->last_set_value
= value
;
12229 enum machine_mode mode
= GET_MODE (reg
);
12230 subst_low_luid
= DF_INSN_LUID (insn
);
12231 rsp
->last_set_mode
= mode
;
12232 if (GET_MODE_CLASS (mode
) == MODE_INT
12233 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
12234 mode
= nonzero_bits_mode
;
12235 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12236 rsp
->last_set_sign_bit_copies
12237 = num_sign_bit_copies (value
, GET_MODE (reg
));
12241 /* Called via note_stores from record_dead_and_set_regs to handle one
12242 SET or CLOBBER in an insn. DATA is the instruction in which the
12243 set is occurring. */
12246 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12248 rtx record_dead_insn
= (rtx
) data
;
12250 if (GET_CODE (dest
) == SUBREG
)
12251 dest
= SUBREG_REG (dest
);
12253 if (!record_dead_insn
)
12256 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12262 /* If we are setting the whole register, we know its value. Otherwise
12263 show that we don't know the value. We can handle SUBREG in
12265 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12266 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12267 else if (GET_CODE (setter
) == SET
12268 && GET_CODE (SET_DEST (setter
)) == SUBREG
12269 && SUBREG_REG (SET_DEST (setter
)) == dest
12270 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
12271 && subreg_lowpart_p (SET_DEST (setter
)))
12272 record_value_for_reg (dest
, record_dead_insn
,
12273 gen_lowpart (GET_MODE (dest
),
12274 SET_SRC (setter
)));
12276 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12278 else if (MEM_P (dest
)
12279 /* Ignore pushes, they clobber nothing. */
12280 && ! push_operand (dest
, GET_MODE (dest
)))
12281 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12284 /* Update the records of when each REG was most recently set or killed
12285 for the things done by INSN. This is the last thing done in processing
12286 INSN in the combiner loop.
12288 We update reg_stat[], in particular fields last_set, last_set_value,
12289 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12290 last_death, and also the similar information mem_last_set (which insn
12291 most recently modified memory) and last_call_luid (which insn was the
12292 most recent subroutine call). */
12295 record_dead_and_set_regs (rtx insn
)
12300 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12302 if (REG_NOTE_KIND (link
) == REG_DEAD
12303 && REG_P (XEXP (link
, 0)))
12305 unsigned int regno
= REGNO (XEXP (link
, 0));
12306 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12308 for (i
= regno
; i
< endregno
; i
++)
12310 reg_stat_type
*rsp
;
12312 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12313 rsp
->last_death
= insn
;
12316 else if (REG_NOTE_KIND (link
) == REG_INC
)
12317 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12322 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12323 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
12325 reg_stat_type
*rsp
;
12327 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12328 rsp
->last_set_invalid
= 1;
12329 rsp
->last_set
= insn
;
12330 rsp
->last_set_value
= 0;
12331 rsp
->last_set_mode
= VOIDmode
;
12332 rsp
->last_set_nonzero_bits
= 0;
12333 rsp
->last_set_sign_bit_copies
= 0;
12334 rsp
->last_death
= 0;
12335 rsp
->truncated_to_mode
= VOIDmode
;
12338 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12340 /* We can't combine into a call pattern. Remember, though, that
12341 the return value register is set at this LUID. We could
12342 still replace a register with the return value from the
12343 wrong subroutine call! */
12344 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12347 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12350 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12351 register present in the SUBREG, so for each such SUBREG go back and
12352 adjust nonzero and sign bit information of the registers that are
12353 known to have some zero/sign bits set.
12355 This is needed because when combine blows the SUBREGs away, the
12356 information on zero/sign bits is lost and further combines can be
12357 missed because of that. */
12360 record_promoted_value (rtx insn
, rtx subreg
)
12363 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12364 enum machine_mode mode
= GET_MODE (subreg
);
12366 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
12369 for (links
= LOG_LINKS (insn
); links
;)
12371 reg_stat_type
*rsp
;
12373 insn
= XEXP (links
, 0);
12374 set
= single_set (insn
);
12376 if (! set
|| !REG_P (SET_DEST (set
))
12377 || REGNO (SET_DEST (set
)) != regno
12378 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12380 links
= XEXP (links
, 1);
12384 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12385 if (rsp
->last_set
== insn
)
12387 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12388 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12391 if (REG_P (SET_SRC (set
)))
12393 regno
= REGNO (SET_SRC (set
));
12394 links
= LOG_LINKS (insn
);
12401 /* Check if X, a register, is known to contain a value already
12402 truncated to MODE. In this case we can use a subreg to refer to
12403 the truncated value even though in the generic case we would need
12404 an explicit truncation. */
12407 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12409 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12410 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12413 || rsp
->truncation_label
< label_tick_ebb_start
)
12415 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12417 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
12418 GET_MODE_BITSIZE (truncated
)))
12423 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12424 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12425 might be able to turn a truncate into a subreg using this information.
12426 Return -1 if traversing *P is complete or 0 otherwise. */
12429 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12432 enum machine_mode truncated_mode
;
12433 reg_stat_type
*rsp
;
12435 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12437 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12438 truncated_mode
= GET_MODE (x
);
12440 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12443 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
12444 GET_MODE_BITSIZE (original_mode
)))
12447 x
= SUBREG_REG (x
);
12449 /* ??? For hard-regs we now record everything. We might be able to
12450 optimize this using last_set_mode. */
12451 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12452 truncated_mode
= GET_MODE (x
);
12456 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12457 if (rsp
->truncated_to_mode
== 0
12458 || rsp
->truncation_label
< label_tick_ebb_start
12459 || (GET_MODE_SIZE (truncated_mode
)
12460 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12462 rsp
->truncated_to_mode
= truncated_mode
;
12463 rsp
->truncation_label
= label_tick
;
12469 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12470 the modes they are used in. This can help truning TRUNCATEs into
12474 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12476 for_each_rtx (x
, record_truncated_value
, NULL
);
12479 /* Scan X for promoted SUBREGs. For each one found,
12480 note what it implies to the registers used in it. */
12483 check_promoted_subreg (rtx insn
, rtx x
)
12485 if (GET_CODE (x
) == SUBREG
12486 && SUBREG_PROMOTED_VAR_P (x
)
12487 && REG_P (SUBREG_REG (x
)))
12488 record_promoted_value (insn
, x
);
12491 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12494 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12498 check_promoted_subreg (insn
, XEXP (x
, i
));
12502 if (XVEC (x
, i
) != 0)
12503 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12504 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12510 /* Verify that all the registers and memory references mentioned in *LOC are
12511 still valid. *LOC was part of a value set in INSN when label_tick was
12512 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12513 the invalid references with (clobber (const_int 0)) and return 1. This
12514 replacement is useful because we often can get useful information about
12515 the form of a value (e.g., if it was produced by a shift that always
12516 produces -1 or 0) even though we don't know exactly what registers it
12517 was produced from. */
12520 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12523 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12524 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12529 unsigned int regno
= REGNO (x
);
12530 unsigned int endregno
= END_REGNO (x
);
12533 for (j
= regno
; j
< endregno
; j
++)
12535 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12536 if (rsp
->last_set_invalid
12537 /* If this is a pseudo-register that was only set once and not
12538 live at the beginning of the function, it is always valid. */
12539 || (! (regno
>= FIRST_PSEUDO_REGISTER
12540 && REG_N_SETS (regno
) == 1
12541 && (!REGNO_REG_SET_P
12542 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12543 && rsp
->last_set_label
> tick
))
12546 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12553 /* If this is a memory reference, make sure that there were no stores after
12554 it that might have clobbered the value. We don't have alias info, so we
12555 assume any store invalidates it. Moreover, we only have local UIDs, so
12556 we also assume that there were stores in the intervening basic blocks. */
12557 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12558 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12561 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12565 for (i
= 0; i
< len
; i
++)
12569 /* Check for identical subexpressions. If x contains
12570 identical subexpression we only have to traverse one of
12572 if (i
== 1 && ARITHMETIC_P (x
))
12574 /* Note that at this point x0 has already been checked
12575 and found valid. */
12576 rtx x0
= XEXP (x
, 0);
12577 rtx x1
= XEXP (x
, 1);
12579 /* If x0 and x1 are identical then x is also valid. */
12583 /* If x1 is identical to a subexpression of x0 then
12584 while checking x0, x1 has already been checked. Thus
12585 it is valid and so as x. */
12586 if (ARITHMETIC_P (x0
)
12587 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12590 /* If x0 is identical to a subexpression of x1 then x is
12591 valid iff the rest of x1 is valid. */
12592 if (ARITHMETIC_P (x1
)
12593 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12595 get_last_value_validate (&XEXP (x1
,
12596 x0
== XEXP (x1
, 0) ? 1 : 0),
12597 insn
, tick
, replace
);
12600 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12604 else if (fmt
[i
] == 'E')
12605 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12606 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12607 insn
, tick
, replace
) == 0)
12611 /* If we haven't found a reason for it to be invalid, it is valid. */
12615 /* Get the last value assigned to X, if known. Some registers
12616 in the value may be replaced with (clobber (const_int 0)) if their value
12617 is known longer known reliably. */
12620 get_last_value (const_rtx x
)
12622 unsigned int regno
;
12624 reg_stat_type
*rsp
;
12626 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12627 then convert it to the desired mode. If this is a paradoxical SUBREG,
12628 we cannot predict what values the "extra" bits might have. */
12629 if (GET_CODE (x
) == SUBREG
12630 && subreg_lowpart_p (x
)
12631 && (GET_MODE_SIZE (GET_MODE (x
))
12632 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
12633 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12634 return gen_lowpart (GET_MODE (x
), value
);
12640 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12641 value
= rsp
->last_set_value
;
12643 /* If we don't have a value, or if it isn't for this basic block and
12644 it's either a hard register, set more than once, or it's a live
12645 at the beginning of the function, return 0.
12647 Because if it's not live at the beginning of the function then the reg
12648 is always set before being used (is never used without being set).
12649 And, if it's set only once, and it's always set before use, then all
12650 uses must have the same last value, even if it's not from this basic
12654 || (rsp
->last_set_label
< label_tick_ebb_start
12655 && (regno
< FIRST_PSEUDO_REGISTER
12656 || REG_N_SETS (regno
) != 1
12658 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12661 /* If the value was set in a later insn than the ones we are processing,
12662 we can't use it even if the register was only set once. */
12663 if (rsp
->last_set_label
== label_tick
12664 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12667 /* If the value has all its registers valid, return it. */
12668 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12671 /* Otherwise, make a copy and replace any invalid register with
12672 (clobber (const_int 0)). If that fails for some reason, return 0. */
12674 value
= copy_rtx (value
);
12675 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12681 /* Return nonzero if expression X refers to a REG or to memory
12682 that is set in an instruction more recent than FROM_LUID. */
12685 use_crosses_set_p (const_rtx x
, int from_luid
)
12689 enum rtx_code code
= GET_CODE (x
);
12693 unsigned int regno
= REGNO (x
);
12694 unsigned endreg
= END_REGNO (x
);
12696 #ifdef PUSH_ROUNDING
12697 /* Don't allow uses of the stack pointer to be moved,
12698 because we don't know whether the move crosses a push insn. */
12699 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12702 for (; regno
< endreg
; regno
++)
12704 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12706 && rsp
->last_set_label
== label_tick
12707 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12713 if (code
== MEM
&& mem_last_set
> from_luid
)
12716 fmt
= GET_RTX_FORMAT (code
);
12718 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12723 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12724 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12727 else if (fmt
[i
] == 'e'
12728 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12734 /* Define three variables used for communication between the following
12737 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12738 static int reg_dead_flag
;
12740 /* Function called via note_stores from reg_dead_at_p.
12742 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12743 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12746 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12748 unsigned int regno
, endregno
;
12753 regno
= REGNO (dest
);
12754 endregno
= END_REGNO (dest
);
12755 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12756 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12759 /* Return nonzero if REG is known to be dead at INSN.
12761 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12762 referencing REG, it is dead. If we hit a SET referencing REG, it is
12763 live. Otherwise, see if it is live or dead at the start of the basic
12764 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12765 must be assumed to be always live. */
12768 reg_dead_at_p (rtx reg
, rtx insn
)
12773 /* Set variables for reg_dead_at_p_1. */
12774 reg_dead_regno
= REGNO (reg
);
12775 reg_dead_endregno
= END_REGNO (reg
);
12779 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12780 we allow the machine description to decide whether use-and-clobber
12781 patterns are OK. */
12782 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12784 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12785 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12789 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12790 beginning of basic block. */
12791 block
= BLOCK_FOR_INSN (insn
);
12796 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12798 return reg_dead_flag
== 1 ? 1 : 0;
12800 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12804 if (insn
== BB_HEAD (block
))
12807 insn
= PREV_INSN (insn
);
12810 /* Look at live-in sets for the basic block that we were in. */
12811 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12812 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12818 /* Note hard registers in X that are used. */
12821 mark_used_regs_combine (rtx x
)
12823 RTX_CODE code
= GET_CODE (x
);
12824 unsigned int regno
;
12837 case ADDR_DIFF_VEC
:
12840 /* CC0 must die in the insn after it is set, so we don't need to take
12841 special note of it here. */
12847 /* If we are clobbering a MEM, mark any hard registers inside the
12848 address as used. */
12849 if (MEM_P (XEXP (x
, 0)))
12850 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12855 /* A hard reg in a wide mode may really be multiple registers.
12856 If so, mark all of them just like the first. */
12857 if (regno
< FIRST_PSEUDO_REGISTER
)
12859 /* None of this applies to the stack, frame or arg pointers. */
12860 if (regno
== STACK_POINTER_REGNUM
12861 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12862 || regno
== HARD_FRAME_POINTER_REGNUM
12864 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12865 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12867 || regno
== FRAME_POINTER_REGNUM
)
12870 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12876 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12878 rtx testreg
= SET_DEST (x
);
12880 while (GET_CODE (testreg
) == SUBREG
12881 || GET_CODE (testreg
) == ZERO_EXTRACT
12882 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12883 testreg
= XEXP (testreg
, 0);
12885 if (MEM_P (testreg
))
12886 mark_used_regs_combine (XEXP (testreg
, 0));
12888 mark_used_regs_combine (SET_SRC (x
));
12896 /* Recursively scan the operands of this expression. */
12899 const char *fmt
= GET_RTX_FORMAT (code
);
12901 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12904 mark_used_regs_combine (XEXP (x
, i
));
12905 else if (fmt
[i
] == 'E')
12909 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12910 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12916 /* Remove register number REGNO from the dead registers list of INSN.
12918 Return the note used to record the death, if there was one. */
12921 remove_death (unsigned int regno
, rtx insn
)
12923 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12926 remove_note (insn
, note
);
12931 /* For each register (hardware or pseudo) used within expression X, if its
12932 death is in an instruction with luid between FROM_LUID (inclusive) and
12933 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12934 list headed by PNOTES.
12936 That said, don't move registers killed by maybe_kill_insn.
12938 This is done when X is being merged by combination into TO_INSN. These
12939 notes will then be distributed as needed. */
12942 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12947 enum rtx_code code
= GET_CODE (x
);
12951 unsigned int regno
= REGNO (x
);
12952 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12954 /* Don't move the register if it gets killed in between from and to. */
12955 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12956 && ! reg_referenced_p (x
, maybe_kill_insn
))
12960 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12961 && DF_INSN_LUID (where_dead
) >= from_luid
12962 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12964 rtx note
= remove_death (regno
, where_dead
);
12966 /* It is possible for the call above to return 0. This can occur
12967 when last_death points to I2 or I1 that we combined with.
12968 In that case make a new note.
12970 We must also check for the case where X is a hard register
12971 and NOTE is a death note for a range of hard registers
12972 including X. In that case, we must put REG_DEAD notes for
12973 the remaining registers in place of NOTE. */
12975 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12976 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12977 > GET_MODE_SIZE (GET_MODE (x
))))
12979 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12980 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12981 unsigned int ourend
= END_HARD_REGNO (x
);
12984 for (i
= deadregno
; i
< deadend
; i
++)
12985 if (i
< regno
|| i
>= ourend
)
12986 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12989 /* If we didn't find any note, or if we found a REG_DEAD note that
12990 covers only part of the given reg, and we have a multi-reg hard
12991 register, then to be safe we must check for REG_DEAD notes
12992 for each register other than the first. They could have
12993 their own REG_DEAD notes lying around. */
12994 else if ((note
== 0
12996 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12997 < GET_MODE_SIZE (GET_MODE (x
)))))
12998 && regno
< FIRST_PSEUDO_REGISTER
12999 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13001 unsigned int ourend
= END_HARD_REGNO (x
);
13002 unsigned int i
, offset
;
13006 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13010 for (i
= regno
+ offset
; i
< ourend
; i
++)
13011 move_deaths (regno_reg_rtx
[i
],
13012 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13015 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13017 XEXP (note
, 1) = *pnotes
;
13021 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13027 else if (GET_CODE (x
) == SET
)
13029 rtx dest
= SET_DEST (x
);
13031 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13033 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13034 that accesses one word of a multi-word item, some
13035 piece of everything register in the expression is used by
13036 this insn, so remove any old death. */
13037 /* ??? So why do we test for equality of the sizes? */
13039 if (GET_CODE (dest
) == ZERO_EXTRACT
13040 || GET_CODE (dest
) == STRICT_LOW_PART
13041 || (GET_CODE (dest
) == SUBREG
13042 && (((GET_MODE_SIZE (GET_MODE (dest
))
13043 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13044 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13045 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13047 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13051 /* If this is some other SUBREG, we know it replaces the entire
13052 value, so use that as the destination. */
13053 if (GET_CODE (dest
) == SUBREG
)
13054 dest
= SUBREG_REG (dest
);
13056 /* If this is a MEM, adjust deaths of anything used in the address.
13057 For a REG (the only other possibility), the entire value is
13058 being replaced so the old value is not used in this insn. */
13061 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13066 else if (GET_CODE (x
) == CLOBBER
)
13069 len
= GET_RTX_LENGTH (code
);
13070 fmt
= GET_RTX_FORMAT (code
);
13072 for (i
= 0; i
< len
; i
++)
13077 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13078 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13081 else if (fmt
[i
] == 'e')
13082 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13086 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13087 pattern of an insn. X must be a REG. */
13090 reg_bitfield_target_p (rtx x
, rtx body
)
13094 if (GET_CODE (body
) == SET
)
13096 rtx dest
= SET_DEST (body
);
13098 unsigned int regno
, tregno
, endregno
, endtregno
;
13100 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13101 target
= XEXP (dest
, 0);
13102 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13103 target
= SUBREG_REG (XEXP (dest
, 0));
13107 if (GET_CODE (target
) == SUBREG
)
13108 target
= SUBREG_REG (target
);
13110 if (!REG_P (target
))
13113 tregno
= REGNO (target
), regno
= REGNO (x
);
13114 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13115 return target
== x
;
13117 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13118 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13120 return endregno
> tregno
&& regno
< endtregno
;
13123 else if (GET_CODE (body
) == PARALLEL
)
13124 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13125 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13131 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13132 as appropriate. I3 and I2 are the insns resulting from the combination
13133 insns including FROM (I2 may be zero).
13135 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13136 not need REG_DEAD notes because they are being substituted for. This
13137 saves searching in the most common cases.
13139 Each note in the list is either ignored or placed on some insns, depending
13140 on the type of note. */
13143 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13144 rtx elim_i1
, rtx elim_i0
)
13146 rtx note
, next_note
;
13149 for (note
= notes
; note
; note
= next_note
)
13151 rtx place
= 0, place2
= 0;
13153 next_note
= XEXP (note
, 1);
13154 switch (REG_NOTE_KIND (note
))
13158 /* Doesn't matter much where we put this, as long as it's somewhere.
13159 It is preferable to keep these notes on branches, which is most
13160 likely to be i3. */
13164 case REG_NON_LOCAL_GOTO
:
13169 gcc_assert (i2
&& JUMP_P (i2
));
13174 case REG_EH_REGION
:
13175 /* These notes must remain with the call or trapping instruction. */
13178 else if (i2
&& CALL_P (i2
))
13182 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13183 if (may_trap_p (i3
))
13185 else if (i2
&& may_trap_p (i2
))
13187 /* ??? Otherwise assume we've combined things such that we
13188 can now prove that the instructions can't trap. Drop the
13189 note in this case. */
13195 /* These notes must remain with the call. It should not be
13196 possible for both I2 and I3 to be a call. */
13201 gcc_assert (i2
&& CALL_P (i2
));
13207 /* Any clobbers for i3 may still exist, and so we must process
13208 REG_UNUSED notes from that insn.
13210 Any clobbers from i2 or i1 can only exist if they were added by
13211 recog_for_combine. In that case, recog_for_combine created the
13212 necessary REG_UNUSED notes. Trying to keep any original
13213 REG_UNUSED notes from these insns can cause incorrect output
13214 if it is for the same register as the original i3 dest.
13215 In that case, we will notice that the register is set in i3,
13216 and then add a REG_UNUSED note for the destination of i3, which
13217 is wrong. However, it is possible to have REG_UNUSED notes from
13218 i2 or i1 for register which were both used and clobbered, so
13219 we keep notes from i2 or i1 if they will turn into REG_DEAD
13222 /* If this register is set or clobbered in I3, put the note there
13223 unless there is one already. */
13224 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13226 if (from_insn
!= i3
)
13229 if (! (REG_P (XEXP (note
, 0))
13230 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13231 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13234 /* Otherwise, if this register is used by I3, then this register
13235 now dies here, so we must put a REG_DEAD note here unless there
13237 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13238 && ! (REG_P (XEXP (note
, 0))
13239 ? find_regno_note (i3
, REG_DEAD
,
13240 REGNO (XEXP (note
, 0)))
13241 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13243 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13251 /* These notes say something about results of an insn. We can
13252 only support them if they used to be on I3 in which case they
13253 remain on I3. Otherwise they are ignored.
13255 If the note refers to an expression that is not a constant, we
13256 must also ignore the note since we cannot tell whether the
13257 equivalence is still true. It might be possible to do
13258 slightly better than this (we only have a problem if I2DEST
13259 or I1DEST is present in the expression), but it doesn't
13260 seem worth the trouble. */
13262 if (from_insn
== i3
13263 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13268 /* These notes say something about how a register is used. They must
13269 be present on any use of the register in I2 or I3. */
13270 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13273 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13282 case REG_LABEL_TARGET
:
13283 case REG_LABEL_OPERAND
:
13284 /* This can show up in several ways -- either directly in the
13285 pattern, or hidden off in the constant pool with (or without?)
13286 a REG_EQUAL note. */
13287 /* ??? Ignore the without-reg_equal-note problem for now. */
13288 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13289 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13290 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13291 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13295 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13296 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13297 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13298 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13306 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13307 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13309 if (place
&& JUMP_P (place
)
13310 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13311 && (JUMP_LABEL (place
) == NULL
13312 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13314 rtx label
= JUMP_LABEL (place
);
13317 JUMP_LABEL (place
) = XEXP (note
, 0);
13318 else if (LABEL_P (label
))
13319 LABEL_NUSES (label
)--;
13322 if (place2
&& JUMP_P (place2
)
13323 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13324 && (JUMP_LABEL (place2
) == NULL
13325 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13327 rtx label
= JUMP_LABEL (place2
);
13330 JUMP_LABEL (place2
) = XEXP (note
, 0);
13331 else if (LABEL_P (label
))
13332 LABEL_NUSES (label
)--;
13338 /* This note says something about the value of a register prior
13339 to the execution of an insn. It is too much trouble to see
13340 if the note is still correct in all situations. It is better
13341 to simply delete it. */
13345 /* If we replaced the right hand side of FROM_INSN with a
13346 REG_EQUAL note, the original use of the dying register
13347 will not have been combined into I3 and I2. In such cases,
13348 FROM_INSN is guaranteed to be the first of the combined
13349 instructions, so we simply need to search back before
13350 FROM_INSN for the previous use or set of this register,
13351 then alter the notes there appropriately.
13353 If the register is used as an input in I3, it dies there.
13354 Similarly for I2, if it is nonzero and adjacent to I3.
13356 If the register is not used as an input in either I3 or I2
13357 and it is not one of the registers we were supposed to eliminate,
13358 there are two possibilities. We might have a non-adjacent I2
13359 or we might have somehow eliminated an additional register
13360 from a computation. For example, we might have had A & B where
13361 we discover that B will always be zero. In this case we will
13362 eliminate the reference to A.
13364 In both cases, we must search to see if we can find a previous
13365 use of A and put the death note there. */
13368 && from_insn
== i2mod
13369 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13374 && CALL_P (from_insn
)
13375 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13377 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13379 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13380 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13382 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13384 && reg_overlap_mentioned_p (XEXP (note
, 0),
13386 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13387 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13394 basic_block bb
= this_basic_block
;
13396 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13398 if (!NONDEBUG_INSN_P (tem
))
13400 if (tem
== BB_HEAD (bb
))
13405 /* If the register is being set at TEM, see if that is all
13406 TEM is doing. If so, delete TEM. Otherwise, make this
13407 into a REG_UNUSED note instead. Don't delete sets to
13408 global register vars. */
13409 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13410 || !global_regs
[REGNO (XEXP (note
, 0))])
13411 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13413 rtx set
= single_set (tem
);
13414 rtx inner_dest
= 0;
13416 rtx cc0_setter
= NULL_RTX
;
13420 for (inner_dest
= SET_DEST (set
);
13421 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13422 || GET_CODE (inner_dest
) == SUBREG
13423 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13424 inner_dest
= XEXP (inner_dest
, 0))
13427 /* Verify that it was the set, and not a clobber that
13428 modified the register.
13430 CC0 targets must be careful to maintain setter/user
13431 pairs. If we cannot delete the setter due to side
13432 effects, mark the user with an UNUSED note instead
13435 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13436 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13438 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13439 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13440 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13444 /* Move the notes and links of TEM elsewhere.
13445 This might delete other dead insns recursively.
13446 First set the pattern to something that won't use
13448 rtx old_notes
= REG_NOTES (tem
);
13450 PATTERN (tem
) = pc_rtx
;
13451 REG_NOTES (tem
) = NULL
;
13453 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13454 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13455 distribute_links (LOG_LINKS (tem
));
13457 SET_INSN_DELETED (tem
);
13462 /* Delete the setter too. */
13465 PATTERN (cc0_setter
) = pc_rtx
;
13466 old_notes
= REG_NOTES (cc0_setter
);
13467 REG_NOTES (cc0_setter
) = NULL
;
13469 distribute_notes (old_notes
, cc0_setter
,
13470 cc0_setter
, NULL_RTX
,
13471 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13472 distribute_links (LOG_LINKS (cc0_setter
));
13474 SET_INSN_DELETED (cc0_setter
);
13475 if (cc0_setter
== i2
)
13482 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13484 /* If there isn't already a REG_UNUSED note, put one
13485 here. Do not place a REG_DEAD note, even if
13486 the register is also used here; that would not
13487 match the algorithm used in lifetime analysis
13488 and can cause the consistency check in the
13489 scheduler to fail. */
13490 if (! find_regno_note (tem
, REG_UNUSED
,
13491 REGNO (XEXP (note
, 0))))
13496 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13498 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13502 /* If we are doing a 3->2 combination, and we have a
13503 register which formerly died in i3 and was not used
13504 by i2, which now no longer dies in i3 and is used in
13505 i2 but does not die in i2, and place is between i2
13506 and i3, then we may need to move a link from place to
13508 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13510 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13511 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13513 rtx links
= LOG_LINKS (place
);
13514 LOG_LINKS (place
) = 0;
13515 distribute_links (links
);
13520 if (tem
== BB_HEAD (bb
))
13526 /* If the register is set or already dead at PLACE, we needn't do
13527 anything with this note if it is still a REG_DEAD note.
13528 We check here if it is set at all, not if is it totally replaced,
13529 which is what `dead_or_set_p' checks, so also check for it being
13532 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13534 unsigned int regno
= REGNO (XEXP (note
, 0));
13535 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13537 if (dead_or_set_p (place
, XEXP (note
, 0))
13538 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13540 /* Unless the register previously died in PLACE, clear
13541 last_death. [I no longer understand why this is
13543 if (rsp
->last_death
!= place
)
13544 rsp
->last_death
= 0;
13548 rsp
->last_death
= place
;
13550 /* If this is a death note for a hard reg that is occupying
13551 multiple registers, ensure that we are still using all
13552 parts of the object. If we find a piece of the object
13553 that is unused, we must arrange for an appropriate REG_DEAD
13554 note to be added for it. However, we can't just emit a USE
13555 and tag the note to it, since the register might actually
13556 be dead; so we recourse, and the recursive call then finds
13557 the previous insn that used this register. */
13559 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13560 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13562 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13566 for (i
= regno
; i
< endregno
; i
++)
13567 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13568 && ! find_regno_fusage (place
, USE
, i
))
13569 || dead_or_set_regno_p (place
, i
))
13574 /* Put only REG_DEAD notes for pieces that are
13575 not already dead or set. */
13577 for (i
= regno
; i
< endregno
;
13578 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13580 rtx piece
= regno_reg_rtx
[i
];
13581 basic_block bb
= this_basic_block
;
13583 if (! dead_or_set_p (place
, piece
)
13584 && ! reg_bitfield_target_p (piece
,
13587 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13590 distribute_notes (new_note
, place
, place
,
13591 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13594 else if (! refers_to_regno_p (i
, i
+ 1,
13595 PATTERN (place
), 0)
13596 && ! find_regno_fusage (place
, USE
, i
))
13597 for (tem
= PREV_INSN (place
); ;
13598 tem
= PREV_INSN (tem
))
13600 if (!NONDEBUG_INSN_P (tem
))
13602 if (tem
== BB_HEAD (bb
))
13606 if (dead_or_set_p (tem
, piece
)
13607 || reg_bitfield_target_p (piece
,
13610 add_reg_note (tem
, REG_UNUSED
, piece
);
13624 /* Any other notes should not be present at this point in the
13626 gcc_unreachable ();
13631 XEXP (note
, 1) = REG_NOTES (place
);
13632 REG_NOTES (place
) = note
;
13636 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13640 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13641 I3, I2, and I1 to new locations. This is also called to add a link
13642 pointing at I3 when I3's destination is changed. */
13645 distribute_links (rtx links
)
13647 rtx link
, next_link
;
13649 for (link
= links
; link
; link
= next_link
)
13655 next_link
= XEXP (link
, 1);
13657 /* If the insn that this link points to is a NOTE or isn't a single
13658 set, ignore it. In the latter case, it isn't clear what we
13659 can do other than ignore the link, since we can't tell which
13660 register it was for. Such links wouldn't be used by combine
13663 It is not possible for the destination of the target of the link to
13664 have been changed by combine. The only potential of this is if we
13665 replace I3, I2, and I1 by I3 and I2. But in that case the
13666 destination of I2 also remains unchanged. */
13668 if (NOTE_P (XEXP (link
, 0))
13669 || (set
= single_set (XEXP (link
, 0))) == 0)
13672 reg
= SET_DEST (set
);
13673 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13674 || GET_CODE (reg
) == STRICT_LOW_PART
)
13675 reg
= XEXP (reg
, 0);
13677 /* A LOG_LINK is defined as being placed on the first insn that uses
13678 a register and points to the insn that sets the register. Start
13679 searching at the next insn after the target of the link and stop
13680 when we reach a set of the register or the end of the basic block.
13682 Note that this correctly handles the link that used to point from
13683 I3 to I2. Also note that not much searching is typically done here
13684 since most links don't point very far away. */
13686 for (insn
= NEXT_INSN (XEXP (link
, 0));
13687 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13688 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13689 insn
= NEXT_INSN (insn
))
13690 if (DEBUG_INSN_P (insn
))
13692 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13694 if (reg_referenced_p (reg
, PATTERN (insn
)))
13698 else if (CALL_P (insn
)
13699 && find_reg_fusage (insn
, USE
, reg
))
13704 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13707 /* If we found a place to put the link, place it there unless there
13708 is already a link to the same insn as LINK at that point. */
13714 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13715 if (XEXP (link2
, 0) == XEXP (link
, 0))
13720 XEXP (link
, 1) = LOG_LINKS (place
);
13721 LOG_LINKS (place
) = link
;
13723 /* Set added_links_insn to the earliest insn we added a
13725 if (added_links_insn
== 0
13726 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13727 added_links_insn
= place
;
13733 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13734 Check whether the expression pointer to by LOC is a register or
13735 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13736 Otherwise return zero. */
13739 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13744 && (REG_P (x
) || MEM_P (x
))
13745 && ! reg_mentioned_p (x
, (rtx
) expr
))
13750 /* Check for any register or memory mentioned in EQUIV that is not
13751 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13752 of EXPR where some registers may have been replaced by constants. */
13755 unmentioned_reg_p (rtx equiv
, rtx expr
)
13757 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13761 dump_combine_stats (FILE *file
)
13765 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13766 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13770 dump_combine_total_stats (FILE *file
)
13774 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13775 total_attempts
, total_merges
, total_extras
, total_successes
);
13779 gate_handle_combine (void)
13781 return (optimize
> 0);
13784 /* Try combining insns through substitution. */
13785 static unsigned int
13786 rest_of_handle_combine (void)
13788 int rebuild_jump_labels_after_combine
;
13790 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13791 df_note_add_problem ();
13794 regstat_init_n_sets_and_refs ();
13796 rebuild_jump_labels_after_combine
13797 = combine_instructions (get_insns (), max_reg_num ());
13799 /* Combining insns may have turned an indirect jump into a
13800 direct jump. Rebuild the JUMP_LABEL fields of jumping
13802 if (rebuild_jump_labels_after_combine
)
13804 timevar_push (TV_JUMP
);
13805 rebuild_jump_labels (get_insns ());
13807 timevar_pop (TV_JUMP
);
13810 regstat_free_n_sets_and_refs ();
13814 struct rtl_opt_pass pass_combine
=
13818 "combine", /* name */
13819 gate_handle_combine
, /* gate */
13820 rest_of_handle_combine
, /* execute */
13823 0, /* static_pass_number */
13824 TV_COMBINE
, /* tv_id */
13825 PROP_cfglayout
, /* properties_required */
13826 0, /* properties_provided */
13827 0, /* properties_destroyed */
13828 0, /* todo_flags_start */
13830 TODO_df_finish
| TODO_verify_rtl_sharing
|
13831 TODO_ggc_collect
, /* todo_flags_finish */